Hello, we have a design that includes nRF9161 for LTE purpose and a separate MCU.
The power sequencing for nRF9161 is as follows
- VDD1, VDD2 is supplied with 4.2V
- ENABLE pin is pulled up to this 4.2V (so automatically enabled)
- VDD_GPIO is then supplied 5-10 seconds later (it is gated by our PMIC until MCU commands it)
Before VDD_GPIO is supplied from PMIC, we are seeing ~0.4V to 0.5V on this pin. It looks like nRF9161 is back-powering this pin based on VDD1/VDD2. To rule out that PMIC was driving this voltage, we opened a jumper on the trace going to VDD_GPIO and probed the jumper-pad on nRF9161 side and saw above voltage.
We are utilizing only 10 GPIO pins on nRF9161. We probed all of them to make sure they didn't have a pull-up or was being driven by some other IC.
The only 2 IO pins that had a voltage were
- NRESET at 2.15V
- This is expected
- SWDIO at 0.4V
- SWDIO voltage was lesser than VDD_GPIO which leaves me to guess that it is not the source.
Is the back-powered voltage on VDD_GPIO of nRF9161 expected?
