#include <stdio.h>
#include <stdbool.h>
#include "app_error.h"
#include "app_util_platform.h"
#include "nrf_delay.h"
#include "bsp.h"
#include "app_timer.h"
#include "nrf_drv_spi.h"
#include "nordic_common.h"
#include "nrf_drv_gpiote.h"


#define WRITE_BIT             0x40
#define READ_BIT              0x20
#define APP_TIMER_PRESCALER      0                      /**< Value of the RTC1 PRESCALER register. */
#define APP_TIMER_MAX_TIMERS     BSP_APP_TIMERS_NUMBER  /**< Maximum number of simultaneously created timers. */
#define APP_TIMER_OP_QUEUE_SIZE  2                      /**< Size of timer operation queues. */

#define DELAY_MS                 1000                /**< Timer Delay in milli-seconds. */

#define TX_RX_BUF_LENGTH         2                /**< SPI transaction buffer length. */

#if (SPI0_ENABLED == 1)
    static const nrf_drv_spi_t m_spi_master = NRF_DRV_SPI_INSTANCE(0);
#elif (SPI1_ENABLED == 1)
    static const nrf_drv_spi_t m_spi_master = NRF_DRV_SPI_INSTANCE(1);
#elif (SPI2_ENABLED == 1)
    static const nrf_drv_spi_t m_spi_master = NRF_DRV_SPI_INSTANCE(2);
#else
    #error "No SPI enabled."
#endif

// Data buffers.
static uint8_t m_tx_data[TX_RX_BUF_LENGTH] = {0}; /**< A buffer with data to transfer. */
static uint8_t m_rx_data[TX_RX_BUF_LENGTH] = {0}; /**< A buffer for incoming data. */

static volatile bool m_transfer_completed = true; /**< A flag to inform about completed transfer. */



void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name)
{
    UNUSED_VARIABLE(bsp_indication_set(BSP_INDICATE_FATAL_ERROR));

    for (;;)
    {
        // No implementation needed.
    }
}




static void spi_master_event_handler(nrf_drv_spi_event_t event)
{
    uint32_t err_code = NRF_SUCCESS;
   // bool result = false;

    switch (event)
    {
        case NRF_DRV_SPI_EVENT_DONE:
            // Check if data are valid.
          //  result = buf_check(m_rx_data, TX_RX_BUF_LENGTH);
          //  APP_ERROR_CHECK_BOOL(result);

            err_code = bsp_indication_set(BSP_INDICATE_RCV_OK);
            APP_ERROR_CHECK(err_code);

            // Inform application that transfer is completed.
            m_transfer_completed = true;
            break;

        default:
            // No implementation needed.
            break;
    }
}


static void spi_send_recv(uint8_t * const p_tx_data,
                          uint8_t * const p_rx_data,
                          const uint16_t  len)
{
    // Initalize buffers.
   // init_buffers(p_tx_data, p_rx_data, len);

    // Start transfer.
    uint32_t err_code = nrf_drv_spi_transfer(&m_spi_master,
        p_tx_data, len, p_rx_data, len);
    APP_ERROR_CHECK(err_code);
    nrf_delay_ms(10);
}



void bsp_configuration()
{
    uint32_t err_code = NRF_SUCCESS;

    NRF_CLOCK->LFCLKSRC            = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
    NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
    NRF_CLOCK->TASKS_LFCLKSTART    = 1;

    while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0)
    {
        // Do nothing.
    }

    APP_TIMER_INIT(APP_TIMER_PRESCALER, APP_TIMER_MAX_TIMERS, APP_TIMER_OP_QUEUE_SIZE, NULL);
        
    err_code = bsp_init(BSP_INIT_LED, APP_TIMER_TICKS(100, APP_TIMER_PRESCALER), NULL);
    APP_ERROR_CHECK(err_code);
}



//-----------------------------spi functions----------------------------------
void SPIWriteReg(uint8_t addr, uint8_t value)
{
	  uint8_t temp[2];
    uint8_t temp_rec[2]={0};

    temp[0] = addr | WRITE_BIT;
		temp[1] = value;

    //nrf_drv_gpiote_out_clear(22);		
		spi_send_recv(temp, temp_rec, 2);


		if (m_transfer_completed){
			m_transfer_completed=false;
			nrf_delay_ms(1);
		  //nrf_drv_gpiote_out_set(22);
		}
		
		nrf_delay_ms(1);
	
}

uint8_t SPIReadReg(uint8_t addr)
{
	  uint8_t temp[3];
	  uint8_t temp_rec[3]={0};
	
	  temp[0] = addr | READ_BIT ;
	  temp[1] = 0x00;
		temp[2] = 0x00;
		
		//nrf_drv_gpiote_out_clear(22);
		spi_send_recv(temp, temp_rec, 3);
	  
		
	  if (m_transfer_completed){
//			printf("read_finally\n");
			m_transfer_completed=false;
			nrf_delay_ms(1);
		 // nrf_drv_gpiote_out_set(22);
		}
		
		nrf_delay_ms(1);
		
		return temp_rec[2];
}
void  Disablestart()
{
	nrf_drv_gpiote_out_clear(28);
	nrf_delay_ms(1);
}
void  Enablestart()
{
	nrf_drv_gpiote_out_set(28);
	nrf_delay_ms(1);
}
void reset()
{
	nrf_drv_gpiote_out_set(29);
	nrf_delay_ms(10);
	nrf_drv_gpiote_out_clear(29);
	nrf_delay_ms(10);	
	nrf_drv_gpiote_out_set(29);
	nrf_delay_ms(10);
}

int main(void)
{
	
	uint8_t aa=0x01;
	//	nrf_gpio_cfg_output(30);   //DRDY
	 // nrf_gpio_cfg_output(29);  //PWDN
	 // nrf_gpio_cfg_output(28);  //START


	 
  //  nrf_drv_gpiote_out_set(22);   //This should assert the CS for the SPI peripheral
	    
    	  
 		//nrf_delay_ms(1);
    // Setup bsp module.
    bsp_configuration();
	 

    nrf_drv_spi_config_t const config =
    {
        #if (SPI0_ENABLED == 1)
            .sck_pin  = SPIM0_SCK_PIN,
            .mosi_pin = SPIM0_MOSI_PIN,
            .miso_pin = SPIM0_MISO_PIN,
            .ss_pin   = SPIM0_SS_PIN,
        #elif (SPI1_ENABLED == 1)
            .sck_pin  = SPIM1_SCK_PIN,
            .mosi_pin = SPIM1_MOSI_PIN,
            .miso_pin = SPIM1_MISO_PIN,
            .ss_pin   = SPIM1_SS_PIN,
        #elif (SPI2_ENABLED == 1)
            .sck_pin  = SPIM2_SCK_PIN,
            .mosi_pin = SPIM2_MOSI_PIN,
            .miso_pin = SPIM2_MISO_PIN,
            .ss_pin   = SPIM2_SS_PIN,
        #endif
        .irq_priority = APP_IRQ_PRIORITY_LOW,
        .orc          = 0xCC,
        .frequency    = NRF_DRV_SPI_FREQ_1M,
        .mode         = NRF_DRV_SPI_MODE_1,
        .bit_order    = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST,

    };
    ret_code_t err_code = nrf_drv_spi_init(&m_spi_master, &config, spi_master_event_handler);
    APP_ERROR_CHECK(err_code);
		
		//SPIWriteReg(0x02,0x11);
	while(1)
	{		
    
     aa=SPIReadReg(0x02);
	}
}