
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

0000c000 <_vector_start>:
    c000:	20011328 	.word	0x20011328
    c004:	0000d29d 	.word	0x0000d29d
    c008:	0000f841 	.word	0x0000f841
    c00c:	0000d2cd 	.word	0x0000d2cd
    c010:	0000d2cd 	.word	0x0000d2cd
    c014:	0000d2cd 	.word	0x0000d2cd
    c018:	0000d2cd 	.word	0x0000d2cd
    c01c:	0000d2cd 	.word	0x0000d2cd
	...
    c02c:	0000d1f9 	.word	0x0000d1f9
    c030:	0000d2cd 	.word	0x0000d2cd
    c034:	00000000 	.word	0x00000000
    c038:	0000d1a1 	.word	0x0000d1a1
    c03c:	0000f821 	.word	0x0000f821

0000c040 <_irq_vector_table>:
    c040:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c050:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c060:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c070:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c080:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c090:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c0a0:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c0b0:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c0c0:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c0d0:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c0e0:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c0f0:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c100:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c110:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c120:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c130:	0000d25d 0000d25d 0000d25d 0000d25d     ]...]...]...]...
    c140:	0000d25d                                ]...

0000c144 <_vector_end>:
	...

0000c200 <m_firmware_info>:
    c200:	281ee6de 8fcebb4c 00005b02 0000003c     ...(L....[..<...
    c210:	0000444c 00000001 0000c000 0000c000     LD..............
    c220:	9102ffff 00000000 00000000 00000000     ................
	...

Disassembly of section text:

0000c23c <__aeabi_uldivmod>:
    c23c:	b953      	cbnz	r3, c254 <__aeabi_uldivmod+0x18>
    c23e:	b94a      	cbnz	r2, c254 <__aeabi_uldivmod+0x18>
    c240:	2900      	cmp	r1, #0
    c242:	bf08      	it	eq
    c244:	2800      	cmpeq	r0, #0
    c246:	bf1c      	itt	ne
    c248:	f04f 31ff 	movne.w	r1, #4294967295
    c24c:	f04f 30ff 	movne.w	r0, #4294967295
    c250:	f000 b970 	b.w	c534 <__aeabi_idiv0>
    c254:	f1ad 0c08 	sub.w	ip, sp, #8
    c258:	e96d ce04 	strd	ip, lr, [sp, #-16]!
    c25c:	f000 f806 	bl	c26c <__udivmoddi4>
    c260:	f8dd e004 	ldr.w	lr, [sp, #4]
    c264:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    c268:	b004      	add	sp, #16
    c26a:	4770      	bx	lr

0000c26c <__udivmoddi4>:
    c26c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    c270:	9e08      	ldr	r6, [sp, #32]
    c272:	460d      	mov	r5, r1
    c274:	4604      	mov	r4, r0
    c276:	468a      	mov	sl, r1
    c278:	2b00      	cmp	r3, #0
    c27a:	d17f      	bne.n	c37c <__udivmoddi4+0x110>
    c27c:	428a      	cmp	r2, r1
    c27e:	4617      	mov	r7, r2
    c280:	d941      	bls.n	c306 <__udivmoddi4+0x9a>
    c282:	fab2 f282 	clz	r2, r2
    c286:	b14a      	cbz	r2, c29c <__udivmoddi4+0x30>
    c288:	f1c2 0120 	rsb	r1, r2, #32
    c28c:	fa05 f302 	lsl.w	r3, r5, r2
    c290:	4097      	lsls	r7, r2
    c292:	4094      	lsls	r4, r2
    c294:	fa20 f101 	lsr.w	r1, r0, r1
    c298:	ea41 0a03 	orr.w	sl, r1, r3
    c29c:	ea4f 4817 	mov.w	r8, r7, lsr #16
    c2a0:	ea4f 4c14 	mov.w	ip, r4, lsr #16
    c2a4:	fa1f f987 	uxth.w	r9, r7
    c2a8:	fbba fef8 	udiv	lr, sl, r8
    c2ac:	fb08 a31e 	mls	r3, r8, lr, sl
    c2b0:	fb0e f109 	mul.w	r1, lr, r9
    c2b4:	ea4c 4303 	orr.w	r3, ip, r3, lsl #16
    c2b8:	4299      	cmp	r1, r3
    c2ba:	d906      	bls.n	c2ca <__udivmoddi4+0x5e>
    c2bc:	18fb      	adds	r3, r7, r3
    c2be:	d202      	bcs.n	c2c6 <__udivmoddi4+0x5a>
    c2c0:	4299      	cmp	r1, r3
    c2c2:	f200 8124 	bhi.w	c50e <__udivmoddi4+0x2a2>
    c2c6:	f10e 3eff 	add.w	lr, lr, #4294967295
    c2ca:	1a59      	subs	r1, r3, r1
    c2cc:	b2a3      	uxth	r3, r4
    c2ce:	fbb1 f0f8 	udiv	r0, r1, r8
    c2d2:	fb08 1110 	mls	r1, r8, r0, r1
    c2d6:	fb00 f909 	mul.w	r9, r0, r9
    c2da:	ea43 4401 	orr.w	r4, r3, r1, lsl #16
    c2de:	45a1      	cmp	r9, r4
    c2e0:	d905      	bls.n	c2ee <__udivmoddi4+0x82>
    c2e2:	193c      	adds	r4, r7, r4
    c2e4:	d202      	bcs.n	c2ec <__udivmoddi4+0x80>
    c2e6:	45a1      	cmp	r9, r4
    c2e8:	f200 810e 	bhi.w	c508 <__udivmoddi4+0x29c>
    c2ec:	3801      	subs	r0, #1
    c2ee:	eba4 0409 	sub.w	r4, r4, r9
    c2f2:	ea40 400e 	orr.w	r0, r0, lr, lsl #16
    c2f6:	2100      	movs	r1, #0
    c2f8:	b11e      	cbz	r6, c302 <__udivmoddi4+0x96>
    c2fa:	40d4      	lsrs	r4, r2
    c2fc:	2300      	movs	r3, #0
    c2fe:	e9c6 4300 	strd	r4, r3, [r6]
    c302:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    c306:	b902      	cbnz	r2, c30a <__udivmoddi4+0x9e>
    c308:	deff      	udf	#255	; 0xff
    c30a:	fab2 f282 	clz	r2, r2
    c30e:	2a00      	cmp	r2, #0
    c310:	d14f      	bne.n	c3b2 <__udivmoddi4+0x146>
    c312:	1bcb      	subs	r3, r1, r7
    c314:	ea4f 4e17 	mov.w	lr, r7, lsr #16
    c318:	fa1f f887 	uxth.w	r8, r7
    c31c:	2101      	movs	r1, #1
    c31e:	0c25      	lsrs	r5, r4, #16
    c320:	fbb3 fcfe 	udiv	ip, r3, lr
    c324:	fb0e 301c 	mls	r0, lr, ip, r3
    c328:	462b      	mov	r3, r5
    c32a:	fb08 f90c 	mul.w	r9, r8, ip
    c32e:	ea45 4500 	orr.w	r5, r5, r0, lsl #16
    c332:	45a9      	cmp	r9, r5
    c334:	d90a      	bls.n	c34c <__udivmoddi4+0xe0>
    c336:	197d      	adds	r5, r7, r5
    c338:	bf2c      	ite	cs
    c33a:	2301      	movcs	r3, #1
    c33c:	2300      	movcc	r3, #0
    c33e:	45a9      	cmp	r9, r5
    c340:	d902      	bls.n	c348 <__udivmoddi4+0xdc>
    c342:	2b00      	cmp	r3, #0
    c344:	f000 80d9 	beq.w	c4fa <__udivmoddi4+0x28e>
    c348:	f10c 3cff 	add.w	ip, ip, #4294967295
    c34c:	eba5 0509 	sub.w	r5, r5, r9
    c350:	b2a3      	uxth	r3, r4
    c352:	fbb5 f0fe 	udiv	r0, r5, lr
    c356:	fb0e 5510 	mls	r5, lr, r0, r5
    c35a:	fb08 f800 	mul.w	r8, r8, r0
    c35e:	ea43 4405 	orr.w	r4, r3, r5, lsl #16
    c362:	45a0      	cmp	r8, r4
    c364:	d905      	bls.n	c372 <__udivmoddi4+0x106>
    c366:	193c      	adds	r4, r7, r4
    c368:	d202      	bcs.n	c370 <__udivmoddi4+0x104>
    c36a:	45a0      	cmp	r8, r4
    c36c:	f200 80c9 	bhi.w	c502 <__udivmoddi4+0x296>
    c370:	3801      	subs	r0, #1
    c372:	eba4 0408 	sub.w	r4, r4, r8
    c376:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
    c37a:	e7bd      	b.n	c2f8 <__udivmoddi4+0x8c>
    c37c:	428b      	cmp	r3, r1
    c37e:	d908      	bls.n	c392 <__udivmoddi4+0x126>
    c380:	2e00      	cmp	r6, #0
    c382:	f000 80b1 	beq.w	c4e8 <__udivmoddi4+0x27c>
    c386:	2100      	movs	r1, #0
    c388:	e9c6 0500 	strd	r0, r5, [r6]
    c38c:	4608      	mov	r0, r1
    c38e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    c392:	fab3 f183 	clz	r1, r3
    c396:	2900      	cmp	r1, #0
    c398:	d146      	bne.n	c428 <__udivmoddi4+0x1bc>
    c39a:	42ab      	cmp	r3, r5
    c39c:	f0c0 80a7 	bcc.w	c4ee <__udivmoddi4+0x282>
    c3a0:	4282      	cmp	r2, r0
    c3a2:	f240 80a4 	bls.w	c4ee <__udivmoddi4+0x282>
    c3a6:	4608      	mov	r0, r1
    c3a8:	2e00      	cmp	r6, #0
    c3aa:	d0aa      	beq.n	c302 <__udivmoddi4+0x96>
    c3ac:	e9c6 4a00 	strd	r4, sl, [r6]
    c3b0:	e7a7      	b.n	c302 <__udivmoddi4+0x96>
    c3b2:	f1c2 0020 	rsb	r0, r2, #32
    c3b6:	4097      	lsls	r7, r2
    c3b8:	fa01 f302 	lsl.w	r3, r1, r2
    c3bc:	ea4f 4e17 	mov.w	lr, r7, lsr #16
    c3c0:	40c1      	lsrs	r1, r0
    c3c2:	fa24 f500 	lsr.w	r5, r4, r0
    c3c6:	fa1f f887 	uxth.w	r8, r7
    c3ca:	4094      	lsls	r4, r2
    c3cc:	431d      	orrs	r5, r3
    c3ce:	fbb1 f0fe 	udiv	r0, r1, lr
    c3d2:	0c2b      	lsrs	r3, r5, #16
    c3d4:	fb0e 1110 	mls	r1, lr, r0, r1
    c3d8:	fb00 fc08 	mul.w	ip, r0, r8
    c3dc:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
    c3e0:	459c      	cmp	ip, r3
    c3e2:	d909      	bls.n	c3f8 <__udivmoddi4+0x18c>
    c3e4:	18fb      	adds	r3, r7, r3
    c3e6:	bf2c      	ite	cs
    c3e8:	2101      	movcs	r1, #1
    c3ea:	2100      	movcc	r1, #0
    c3ec:	459c      	cmp	ip, r3
    c3ee:	d902      	bls.n	c3f6 <__udivmoddi4+0x18a>
    c3f0:	2900      	cmp	r1, #0
    c3f2:	f000 8095 	beq.w	c520 <__udivmoddi4+0x2b4>
    c3f6:	3801      	subs	r0, #1
    c3f8:	eba3 030c 	sub.w	r3, r3, ip
    c3fc:	b2ad      	uxth	r5, r5
    c3fe:	fbb3 f1fe 	udiv	r1, r3, lr
    c402:	fb0e 3311 	mls	r3, lr, r1, r3
    c406:	fb01 fc08 	mul.w	ip, r1, r8
    c40a:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
    c40e:	45ac      	cmp	ip, r5
    c410:	d905      	bls.n	c41e <__udivmoddi4+0x1b2>
    c412:	197d      	adds	r5, r7, r5
    c414:	d202      	bcs.n	c41c <__udivmoddi4+0x1b0>
    c416:	45ac      	cmp	ip, r5
    c418:	f200 8089 	bhi.w	c52e <__udivmoddi4+0x2c2>
    c41c:	3901      	subs	r1, #1
    c41e:	eba5 030c 	sub.w	r3, r5, ip
    c422:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
    c426:	e77a      	b.n	c31e <__udivmoddi4+0xb2>
    c428:	f1c1 0420 	rsb	r4, r1, #32
    c42c:	408b      	lsls	r3, r1
    c42e:	fa02 f701 	lsl.w	r7, r2, r1
    c432:	fa05 fc01 	lsl.w	ip, r5, r1
    c436:	40e2      	lsrs	r2, r4
    c438:	fa20 f804 	lsr.w	r8, r0, r4
    c43c:	40e5      	lsrs	r5, r4
    c43e:	fa00 fe01 	lsl.w	lr, r0, r1
    c442:	4313      	orrs	r3, r2
    c444:	ea48 020c 	orr.w	r2, r8, ip
    c448:	ea4f 4813 	mov.w	r8, r3, lsr #16
    c44c:	ea4f 4c12 	mov.w	ip, r2, lsr #16
    c450:	fa1f f983 	uxth.w	r9, r3
    c454:	fbb5 faf8 	udiv	sl, r5, r8
    c458:	fb08 551a 	mls	r5, r8, sl, r5
    c45c:	fb0a f009 	mul.w	r0, sl, r9
    c460:	ea4c 4c05 	orr.w	ip, ip, r5, lsl #16
    c464:	4560      	cmp	r0, ip
    c466:	d90a      	bls.n	c47e <__udivmoddi4+0x212>
    c468:	eb13 0c0c 	adds.w	ip, r3, ip
    c46c:	bf2c      	ite	cs
    c46e:	2501      	movcs	r5, #1
    c470:	2500      	movcc	r5, #0
    c472:	4560      	cmp	r0, ip
    c474:	d901      	bls.n	c47a <__udivmoddi4+0x20e>
    c476:	2d00      	cmp	r5, #0
    c478:	d055      	beq.n	c526 <__udivmoddi4+0x2ba>
    c47a:	f10a 3aff 	add.w	sl, sl, #4294967295
    c47e:	ebac 0c00 	sub.w	ip, ip, r0
    c482:	b292      	uxth	r2, r2
    c484:	fbbc f0f8 	udiv	r0, ip, r8
    c488:	fb08 cc10 	mls	ip, r8, r0, ip
    c48c:	fb00 f909 	mul.w	r9, r0, r9
    c490:	ea42 4c0c 	orr.w	ip, r2, ip, lsl #16
    c494:	45e1      	cmp	r9, ip
    c496:	d905      	bls.n	c4a4 <__udivmoddi4+0x238>
    c498:	eb13 0c0c 	adds.w	ip, r3, ip
    c49c:	d201      	bcs.n	c4a2 <__udivmoddi4+0x236>
    c49e:	45e1      	cmp	r9, ip
    c4a0:	d83b      	bhi.n	c51a <__udivmoddi4+0x2ae>
    c4a2:	3801      	subs	r0, #1
    c4a4:	ea40 400a 	orr.w	r0, r0, sl, lsl #16
    c4a8:	ebac 0c09 	sub.w	ip, ip, r9
    c4ac:	fba0 8907 	umull	r8, r9, r0, r7
    c4b0:	45cc      	cmp	ip, r9
    c4b2:	4645      	mov	r5, r8
    c4b4:	464a      	mov	r2, r9
    c4b6:	d302      	bcc.n	c4be <__udivmoddi4+0x252>
    c4b8:	d106      	bne.n	c4c8 <__udivmoddi4+0x25c>
    c4ba:	45c6      	cmp	lr, r8
    c4bc:	d204      	bcs.n	c4c8 <__udivmoddi4+0x25c>
    c4be:	3801      	subs	r0, #1
    c4c0:	ebb8 0507 	subs.w	r5, r8, r7
    c4c4:	eb69 0203 	sbc.w	r2, r9, r3
    c4c8:	b32e      	cbz	r6, c516 <__udivmoddi4+0x2aa>
    c4ca:	ebbe 0305 	subs.w	r3, lr, r5
    c4ce:	eb6c 0c02 	sbc.w	ip, ip, r2
    c4d2:	fa23 f201 	lsr.w	r2, r3, r1
    c4d6:	fa0c f404 	lsl.w	r4, ip, r4
    c4da:	fa2c f301 	lsr.w	r3, ip, r1
    c4de:	2100      	movs	r1, #0
    c4e0:	4314      	orrs	r4, r2
    c4e2:	e9c6 4300 	strd	r4, r3, [r6]
    c4e6:	e70c      	b.n	c302 <__udivmoddi4+0x96>
    c4e8:	4631      	mov	r1, r6
    c4ea:	4630      	mov	r0, r6
    c4ec:	e709      	b.n	c302 <__udivmoddi4+0x96>
    c4ee:	1a84      	subs	r4, r0, r2
    c4f0:	eb65 0303 	sbc.w	r3, r5, r3
    c4f4:	2001      	movs	r0, #1
    c4f6:	469a      	mov	sl, r3
    c4f8:	e756      	b.n	c3a8 <__udivmoddi4+0x13c>
    c4fa:	f1ac 0c02 	sub.w	ip, ip, #2
    c4fe:	443d      	add	r5, r7
    c500:	e724      	b.n	c34c <__udivmoddi4+0xe0>
    c502:	3802      	subs	r0, #2
    c504:	443c      	add	r4, r7
    c506:	e734      	b.n	c372 <__udivmoddi4+0x106>
    c508:	3802      	subs	r0, #2
    c50a:	443c      	add	r4, r7
    c50c:	e6ef      	b.n	c2ee <__udivmoddi4+0x82>
    c50e:	f1ae 0e02 	sub.w	lr, lr, #2
    c512:	443b      	add	r3, r7
    c514:	e6d9      	b.n	c2ca <__udivmoddi4+0x5e>
    c516:	4631      	mov	r1, r6
    c518:	e6f3      	b.n	c302 <__udivmoddi4+0x96>
    c51a:	3802      	subs	r0, #2
    c51c:	449c      	add	ip, r3
    c51e:	e7c1      	b.n	c4a4 <__udivmoddi4+0x238>
    c520:	3802      	subs	r0, #2
    c522:	443b      	add	r3, r7
    c524:	e768      	b.n	c3f8 <__udivmoddi4+0x18c>
    c526:	f1aa 0a02 	sub.w	sl, sl, #2
    c52a:	449c      	add	ip, r3
    c52c:	e7a7      	b.n	c47e <__udivmoddi4+0x212>
    c52e:	3902      	subs	r1, #2
    c530:	443d      	add	r5, r7
    c532:	e774      	b.n	c41e <__udivmoddi4+0x1b2>

0000c534 <__aeabi_idiv0>:
    c534:	4770      	bx	lr
    c536:	bf00      	nop

0000c538 <spi_test_send>:
		return;
	}
}

void spi_test_send(void)
{
    c538:	b510      	push	{r4, lr}
    c53a:	b088      	sub	sp, #32
	int err;
	static u8_t tx_buffer[1];
	static u8_t rx_buffer[1];

	const struct spi_buf tx_buf = {
    c53c:	466a      	mov	r2, sp
		.buf = tx_buffer,
		.len = sizeof(tx_buffer)
	};
	const struct spi_buf_set tx = {
    c53e:	2401      	movs	r4, #1
	const struct spi_buf tx_buf = {
    c540:	4b15      	ldr	r3, [pc, #84]	; (c598 <spi_test_send+0x60>)
	const struct spi_buf_set tx = {
    c542:	9202      	str	r2, [sp, #8]
	const struct spi_buf tx_buf = {
    c544:	e893 0003 	ldmia.w	r3, {r0, r1}
    c548:	e882 0003 	stmia.w	r2, {r0, r1}
		.buffers = &tx_buf,
		.count = 1
	};

	struct spi_buf rx_buf = {
    c54c:	e9d3 0102 	ldrd	r0, r1, [r3, #8]
	const struct spi_buf_set rx = {
		.buffers = &rx_buf,
		.count = 1
	};

	err = spi_transceive(spi_dev, &spi_cfg, &tx, &rx);
    c550:	4b12      	ldr	r3, [pc, #72]	; (c59c <spi_test_send+0x64>)
	struct spi_buf rx_buf = {
    c552:	aa04      	add	r2, sp, #16
    c554:	e882 0003 	stmia.w	r2, {r0, r1}
	const struct spi_buf_set rx = {
    c558:	e9cd 2406 	strd	r2, r4, [sp, #24]
	err = spi_transceive(spi_dev, &spi_cfg, &tx, &rx);
    c55c:	6818      	ldr	r0, [r3, #0]
	const struct spi_buf_set tx = {
    c55e:	9403      	str	r4, [sp, #12]
					const struct spi_buf_set *rx_bufs)
{
	const struct spi_driver_api *api =
		(const struct spi_driver_api *)dev->api;

	return api->transceive(dev, config, tx_bufs, rx_bufs);
    c560:	6883      	ldr	r3, [r0, #8]
    c562:	490f      	ldr	r1, [pc, #60]	; (c5a0 <spi_test_send+0x68>)
    c564:	681c      	ldr	r4, [r3, #0]
    c566:	aa02      	add	r2, sp, #8
    c568:	ab06      	add	r3, sp, #24
    c56a:	47a0      	blx	r4
	if (err) {
    c56c:	4601      	mov	r1, r0
    c56e:	b120      	cbz	r0, c57a <spi_test_send+0x42>
		printk("SPI error: %d\n", err);
    c570:	480c      	ldr	r0, [pc, #48]	; (c5a4 <spi_test_send+0x6c>)
    c572:	f002 ff1d 	bl	f3b0 <printk>
		/* Connect MISO to MOSI for loopback */
		printk("TX sent: %x\n", tx_buffer[0]);
		printk("RX recv: %x\n", rx_buffer[0]);
		tx_buffer[0]++;
	}	
}
    c576:	b008      	add	sp, #32
    c578:	bd10      	pop	{r4, pc}
		printk("TX sent: %x\n", tx_buffer[0]);
    c57a:	4c0b      	ldr	r4, [pc, #44]	; (c5a8 <spi_test_send+0x70>)
    c57c:	480b      	ldr	r0, [pc, #44]	; (c5ac <spi_test_send+0x74>)
    c57e:	7821      	ldrb	r1, [r4, #0]
    c580:	f002 ff16 	bl	f3b0 <printk>
		printk("RX recv: %x\n", rx_buffer[0]);
    c584:	4b0a      	ldr	r3, [pc, #40]	; (c5b0 <spi_test_send+0x78>)
    c586:	480b      	ldr	r0, [pc, #44]	; (c5b4 <spi_test_send+0x7c>)
    c588:	7819      	ldrb	r1, [r3, #0]
    c58a:	f002 ff11 	bl	f3b0 <printk>
		tx_buffer[0]++;
    c58e:	7823      	ldrb	r3, [r4, #0]
    c590:	3301      	adds	r3, #1
    c592:	7023      	strb	r3, [r4, #0]
}
    c594:	e7ef      	b.n	c576 <spi_test_send+0x3e>
    c596:	bf00      	nop
    c598:	000100c0 	.word	0x000100c0
    c59c:	20010208 	.word	0x20010208
    c5a0:	00010118 	.word	0x00010118
    c5a4:	0001020c 	.word	0x0001020c
    c5a8:	2001031d 	.word	0x2001031d
    c5ac:	0001021b 	.word	0x0001021b
    c5b0:	2001031c 	.word	0x2001031c
    c5b4:	00010228 	.word	0x00010228

0000c5b8 <main>:

void main(void)
{
    c5b8:	b510      	push	{r4, lr}
	printk("SPIM Example\n");
    c5ba:	480e      	ldr	r0, [pc, #56]	; (c5f4 <main+0x3c>)
    c5bc:	f002 fef8 	bl	f3b0 <printk>
	if (z_syscall_trap()) {
		return (const struct device *) arch_syscall_invoke1(*(uintptr_t *)&name, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
    c5c0:	480d      	ldr	r0, [pc, #52]	; (c5f8 <main+0x40>)
    c5c2:	f002 f86b 	bl	e69c <z_impl_device_get_binding>
	spi_dev = device_get_binding(spiName);
    c5c6:	4b0d      	ldr	r3, [pc, #52]	; (c5fc <main+0x44>)
    c5c8:	6018      	str	r0, [r3, #0]
	if (spi_dev == NULL) {
    c5ca:	b918      	cbnz	r0, c5d4 <main+0x1c>
		printk("Could not get %s device\n", spiName);
    c5cc:	490a      	ldr	r1, [pc, #40]	; (c5f8 <main+0x40>)
    c5ce:	480c      	ldr	r0, [pc, #48]	; (c600 <main+0x48>)
    c5d0:	f002 feee 	bl	f3b0 <printk>
	spi_init();
	printk("After init\n");
    c5d4:	480b      	ldr	r0, [pc, #44]	; (c604 <main+0x4c>)
    c5d6:	f002 feeb 	bl	f3b0 <printk>
	while (1) {
		spi_test_send();
		k_sleep(K_MSEC(1000));
		printk(".");
    c5da:	4c0b      	ldr	r4, [pc, #44]	; (c608 <main+0x50>)
		spi_test_send();
    c5dc:	f7ff ffac 	bl	c538 <spi_test_send>
		parm0.val = timeout;
		return (int32_t) arch_syscall_invoke2(parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SLEEP);
	}
#endif
	compiler_barrier();
	return z_impl_k_sleep(timeout);
    c5e0:	2100      	movs	r1, #0
    c5e2:	f44f 4000 	mov.w	r0, #32768	; 0x8000
    c5e6:	f002 fc5b 	bl	eea0 <z_impl_k_sleep>
		printk(".");
    c5ea:	4620      	mov	r0, r4
    c5ec:	f002 fee0 	bl	f3b0 <printk>
	while (1) {
    c5f0:	e7f4      	b.n	c5dc <main+0x24>
    c5f2:	bf00      	nop
    c5f4:	00010235 	.word	0x00010235
    c5f8:	00010243 	.word	0x00010243
    c5fc:	20010208 	.word	0x20010208
    c600:	00010249 	.word	0x00010249
    c604:	00010262 	.word	0x00010262
    c608:	0001026e 	.word	0x0001026e

0000c60c <print_digits>:
}
#endif /* CONFIG_PRINTK */

static void print_digits(out_func_t out, void *ctx, printk_val_t num, int base,
			 bool pad_before, char pad_char, int min_width)
{
    c60c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    c610:	b087      	sub	sp, #28
    c612:	460f      	mov	r7, r1
    c614:	4619      	mov	r1, r3
	char buf[DIGITS_BUFLEN];
	int i;

	/* Print it backwards into the end of the buffer, low digits first */
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
		buf[i] = "0123456789abcdef"[num % base];
    c616:	9b10      	ldr	r3, [sp, #64]	; 0x40
{
    c618:	4606      	mov	r6, r0
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
    c61a:	2514      	movs	r5, #20
{
    c61c:	4610      	mov	r0, r2
		buf[i] = "0123456789abcdef"[num % base];
    c61e:	4698      	mov	r8, r3
{
    c620:	f89d b044 	ldrb.w	fp, [sp, #68]	; 0x44
    c624:	f89d a048 	ldrb.w	sl, [sp, #72]	; 0x48
		buf[i] = "0123456789abcdef"[num % base];
    c628:	4c1e      	ldr	r4, [pc, #120]	; (c6a4 <print_digits+0x98>)
    c62a:	ea4f 79e3 	mov.w	r9, r3, asr #31
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
    c62e:	ea50 0301 	orrs.w	r3, r0, r1
    c632:	d11a      	bne.n	c66a <print_digits+0x5e>
		num /= base;
	}

	if (i == DIGITS_BUFLEN - 1) {
    c634:	2d14      	cmp	r5, #20
		buf[i] = '0';
    c636:	bf08      	it	eq
    c638:	2330      	moveq	r3, #48	; 0x30
	} else {
		i++;
	}

	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
    c63a:	9c13      	ldr	r4, [sp, #76]	; 0x4c
		i++;
    c63c:	bf18      	it	ne
    c63e:	3501      	addne	r5, #1
	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
    c640:	442c      	add	r4, r5
		buf[i] = '0';
    c642:	bf08      	it	eq
    c644:	f88d 3014 	strbeq.w	r3, [sp, #20]
	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
    c648:	2c15      	cmp	r4, #21
    c64a:	d01b      	beq.n	c684 <print_digits+0x78>
    c64c:	3c15      	subs	r4, #21

	for (/**/; pad > 0 && pad_before; pad--) {
    c64e:	2c00      	cmp	r4, #0
    c650:	dc1a      	bgt.n	c688 <print_digits+0x7c>
		out(pad_char, ctx);
	}
	for (/**/; i < DIGITS_BUFLEN; i++) {
		out(buf[i], ctx);
    c652:	f81d 0005 	ldrb.w	r0, [sp, r5]
    c656:	4639      	mov	r1, r7
	for (/**/; i < DIGITS_BUFLEN; i++) {
    c658:	3501      	adds	r5, #1
		out(buf[i], ctx);
    c65a:	47b0      	blx	r6
	for (/**/; i < DIGITS_BUFLEN; i++) {
    c65c:	2d15      	cmp	r5, #21
    c65e:	d1f8      	bne.n	c652 <print_digits+0x46>
	}
	for (/**/; pad > 0; pad--) {
    c660:	2c00      	cmp	r4, #0
    c662:	dc19      	bgt.n	c698 <print_digits+0x8c>
		out(pad_char, ctx);
	}
}
    c664:	b007      	add	sp, #28
    c666:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		buf[i] = "0123456789abcdef"[num % base];
    c66a:	4642      	mov	r2, r8
    c66c:	464b      	mov	r3, r9
    c66e:	f7ff fde5 	bl	c23c <__aeabi_uldivmod>
    c672:	4684      	mov	ip, r0
    c674:	460b      	mov	r3, r1
    c676:	5ca2      	ldrb	r2, [r4, r2]
		num /= base;
    c678:	4660      	mov	r0, ip
		buf[i] = "0123456789abcdef"[num % base];
    c67a:	f80d 2005 	strb.w	r2, [sp, r5]
		num /= base;
    c67e:	4619      	mov	r1, r3
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
    c680:	3d01      	subs	r5, #1
    c682:	e7d4      	b.n	c62e <print_digits+0x22>
	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
    c684:	2400      	movs	r4, #0
	for (/**/; i < DIGITS_BUFLEN; i++) {
    c686:	e7e4      	b.n	c652 <print_digits+0x46>
	for (/**/; pad > 0 && pad_before; pad--) {
    c688:	f1bb 0f00 	cmp.w	fp, #0
    c68c:	d0e1      	beq.n	c652 <print_digits+0x46>
		out(pad_char, ctx);
    c68e:	4639      	mov	r1, r7
    c690:	4650      	mov	r0, sl
    c692:	47b0      	blx	r6
	for (/**/; pad > 0 && pad_before; pad--) {
    c694:	3c01      	subs	r4, #1
    c696:	e7da      	b.n	c64e <print_digits+0x42>
		out(pad_char, ctx);
    c698:	4639      	mov	r1, r7
    c69a:	4650      	mov	r0, sl
    c69c:	47b0      	blx	r6
	for (/**/; pad > 0; pad--) {
    c69e:	3c01      	subs	r4, #1
    c6a0:	e7de      	b.n	c660 <print_digits+0x54>
    c6a2:	bf00      	nop
    c6a4:	00010270 	.word	0x00010270

0000c6a8 <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
    c6a8:	680b      	ldr	r3, [r1, #0]
    c6aa:	3301      	adds	r3, #1
    c6ac:	600b      	str	r3, [r1, #0]
	return _char_out(c);
    c6ae:	4b01      	ldr	r3, [pc, #4]	; (c6b4 <char_out+0xc>)
    c6b0:	681b      	ldr	r3, [r3, #0]
    c6b2:	4718      	bx	r3
    c6b4:	20010000 	.word	0x20010000

0000c6b8 <__printk_hook_install>:
	_char_out = fn;
    c6b8:	4b01      	ldr	r3, [pc, #4]	; (c6c0 <__printk_hook_install+0x8>)
    c6ba:	6018      	str	r0, [r3, #0]
}
    c6bc:	4770      	bx	lr
    c6be:	bf00      	nop
    c6c0:	20010000 	.word	0x20010000

0000c6c4 <z_vprintk>:
{
    c6c4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
	char length_mod = 0;
    c6c8:	2600      	movs	r6, #0
{
    c6ca:	4605      	mov	r5, r0
    c6cc:	468b      	mov	fp, r1
    c6ce:	461c      	mov	r4, r3
	int min_width = -1;
    c6d0:	f04f 38ff 	mov.w	r8, #4294967295
	enum pad_type padding = PAD_NONE;
    c6d4:	4637      	mov	r7, r6
{
    c6d6:	b087      	sub	sp, #28
    c6d8:	f102 3aff 	add.w	sl, r2, #4294967295
			might_format = 0;
    c6dc:	f04f 0900 	mov.w	r9, #0
					break;
    c6e0:	e007      	b.n	c6f2 <z_vprintk+0x2e>
		if (!might_format) {
    c6e2:	f1b9 0f00 	cmp.w	r9, #0
    c6e6:	d10b      	bne.n	c700 <z_vprintk+0x3c>
			if (*fmt != '%') {
    c6e8:	2825      	cmp	r0, #37	; 0x25
    c6ea:	f000 810a 	beq.w	c902 <z_vprintk+0x23e>
				out((int)*fmt, ctx);
    c6ee:	4659      	mov	r1, fp
    c6f0:	47a8      	blx	r5
	while (*fmt) {
    c6f2:	f81a 0f01 	ldrb.w	r0, [sl, #1]!
    c6f6:	2800      	cmp	r0, #0
    c6f8:	d1f3      	bne.n	c6e2 <z_vprintk+0x1e>
}
    c6fa:	b007      	add	sp, #28
    c6fc:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			switch (*fmt) {
    c700:	287a      	cmp	r0, #122	; 0x7a
    c702:	d80a      	bhi.n	c71a <z_vprintk+0x56>
    c704:	2862      	cmp	r0, #98	; 0x62
    c706:	d810      	bhi.n	c72a <z_vprintk+0x66>
    c708:	2830      	cmp	r0, #48	; 0x30
    c70a:	d051      	beq.n	c7b0 <z_vprintk+0xec>
    c70c:	d844      	bhi.n	c798 <z_vprintk+0xd4>
    c70e:	2825      	cmp	r0, #37	; 0x25
    c710:	f000 80f5 	beq.w	c8fe <z_vprintk+0x23a>
    c714:	282d      	cmp	r0, #45	; 0x2d
    c716:	f000 80fb 	beq.w	c910 <z_vprintk+0x24c>
					out((int)'%', ctx);
    c71a:	4659      	mov	r1, fp
    c71c:	2025      	movs	r0, #37	; 0x25
    c71e:	47a8      	blx	r5
					out((int)*fmt, ctx);
    c720:	4659      	mov	r1, fp
    c722:	f89a 0000 	ldrb.w	r0, [sl]
    c726:	47a8      	blx	r5
    c728:	e7d8      	b.n	c6dc <z_vprintk+0x18>
    c72a:	f1a0 0363 	sub.w	r3, r0, #99	; 0x63
    c72e:	2b17      	cmp	r3, #23
    c730:	d8f3      	bhi.n	c71a <z_vprintk+0x56>
    c732:	a201      	add	r2, pc, #4	; (adr r2, c738 <z_vprintk+0x74>)
    c734:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
    c738:	0000c8f7 	.word	0x0000c8f7
    c73c:	0000c7f9 	.word	0x0000c7f9
    c740:	0000c71b 	.word	0x0000c71b
    c744:	0000c71b 	.word	0x0000c71b
    c748:	0000c71b 	.word	0x0000c71b
    c74c:	0000c7db 	.word	0x0000c7db
    c750:	0000c7f9 	.word	0x0000c7f9
    c754:	0000c71b 	.word	0x0000c71b
    c758:	0000c71b 	.word	0x0000c71b
    c75c:	0000c7db 	.word	0x0000c7db
    c760:	0000c71b 	.word	0x0000c71b
    c764:	0000c71b 	.word	0x0000c71b
    c768:	0000c71b 	.word	0x0000c71b
    c76c:	0000c873 	.word	0x0000c873
    c770:	0000c71b 	.word	0x0000c71b
    c774:	0000c71b 	.word	0x0000c71b
    c778:	0000c8bf 	.word	0x0000c8bf
    c77c:	0000c71b 	.word	0x0000c71b
    c780:	0000c7f9 	.word	0x0000c7f9
    c784:	0000c71b 	.word	0x0000c71b
    c788:	0000c71b 	.word	0x0000c71b
    c78c:	0000c7a1 	.word	0x0000c7a1
    c790:	0000c71b 	.word	0x0000c71b
    c794:	0000c7db 	.word	0x0000c7db
			switch (*fmt) {
    c798:	2839      	cmp	r0, #57	; 0x39
    c79a:	d915      	bls.n	c7c8 <z_vprintk+0x104>
    c79c:	2858      	cmp	r0, #88	; 0x58
    c79e:	d1bc      	bne.n	c71a <z_vprintk+0x56>
				if (*fmt == 'p') {
    c7a0:	f89a 3000 	ldrb.w	r3, [sl]
    c7a4:	2b70      	cmp	r3, #112	; 0x70
    c7a6:	d16e      	bne.n	c886 <z_vprintk+0x1c2>
					x = va_arg(ap, unsigned int);
    c7a8:	2300      	movs	r3, #0
    c7aa:	f854 2b04 	ldr.w	r2, [r4], #4
    c7ae:	e075      	b.n	c89c <z_vprintk+0x1d8>
				if (min_width < 0 && padding == PAD_NONE) {
    c7b0:	f1b8 0f00 	cmp.w	r8, #0
    c7b4:	da0b      	bge.n	c7ce <z_vprintk+0x10a>
    c7b6:	2f00      	cmp	r7, #0
    c7b8:	f000 80ac 	beq.w	c914 <z_vprintk+0x250>
					min_width = *fmt - '0';
    c7bc:	f1a0 0830 	sub.w	r8, r0, #48	; 0x30
					padding = PAD_SPACE_BEFORE;
    c7c0:	2f00      	cmp	r7, #0
    c7c2:	bf08      	it	eq
    c7c4:	2702      	moveq	r7, #2
    c7c6:	e794      	b.n	c6f2 <z_vprintk+0x2e>
				if (min_width < 0) {
    c7c8:	f1b8 0f00 	cmp.w	r8, #0
    c7cc:	dbf6      	blt.n	c7bc <z_vprintk+0xf8>
					min_width = 10 * min_width + *fmt - '0';
    c7ce:	230a      	movs	r3, #10
    c7d0:	fb03 0808 	mla	r8, r3, r8, r0
    c7d4:	f1a8 0830 	sub.w	r8, r8, #48	; 0x30
    c7d8:	e7f2      	b.n	c7c0 <z_vprintk+0xfc>
				if (*fmt == 'h' && length_mod == 'h') {
    c7da:	2868      	cmp	r0, #104	; 0x68
    c7dc:	d103      	bne.n	c7e6 <z_vprintk+0x122>
    c7de:	2e68      	cmp	r6, #104	; 0x68
    c7e0:	d106      	bne.n	c7f0 <z_vprintk+0x12c>
					length_mod = 'H';
    c7e2:	2648      	movs	r6, #72	; 0x48
    c7e4:	e785      	b.n	c6f2 <z_vprintk+0x2e>
				} else if (*fmt == 'l' && length_mod == 'l') {
    c7e6:	286c      	cmp	r0, #108	; 0x6c
    c7e8:	d102      	bne.n	c7f0 <z_vprintk+0x12c>
    c7ea:	2e6c      	cmp	r6, #108	; 0x6c
    c7ec:	f000 8094 	beq.w	c918 <z_vprintk+0x254>
				} else if (length_mod == 0) {
    c7f0:	2e00      	cmp	r6, #0
    c7f2:	d192      	bne.n	c71a <z_vprintk+0x56>
    c7f4:	4606      	mov	r6, r0
    c7f6:	e77c      	b.n	c6f2 <z_vprintk+0x2e>
				if (length_mod == 'z') {
    c7f8:	2e7a      	cmp	r6, #122	; 0x7a
    c7fa:	d106      	bne.n	c80a <z_vprintk+0x146>
					d = va_arg(ap, long);
    c7fc:	46a1      	mov	r9, r4
    c7fe:	f859 2b04 	ldr.w	r2, [r9], #4
    c802:	17d3      	asrs	r3, r2, #31
				if (*fmt != 'u' && negative(d)) {
    c804:	2875      	cmp	r0, #117	; 0x75
    c806:	d123      	bne.n	c850 <z_vprintk+0x18c>
    c808:	e00f      	b.n	c82a <z_vprintk+0x166>
				} else if (length_mod == 'l') {
    c80a:	2e6c      	cmp	r6, #108	; 0x6c
    c80c:	d0f6      	beq.n	c7fc <z_vprintk+0x138>
				} else if (length_mod == 'L') {
    c80e:	2e4c      	cmp	r6, #76	; 0x4c
    c810:	d105      	bne.n	c81e <z_vprintk+0x15a>
					long long lld = va_arg(ap, long long);
    c812:	3407      	adds	r4, #7
    c814:	f024 0907 	bic.w	r9, r4, #7
					d = (printk_val_t) lld;
    c818:	e8f9 2302 	ldrd	r2, r3, [r9], #8
    c81c:	e7f2      	b.n	c804 <z_vprintk+0x140>
				} else if (*fmt == 'u') {
    c81e:	2875      	cmp	r0, #117	; 0x75
					d = va_arg(ap, unsigned int);
    c820:	6822      	ldr	r2, [r4, #0]
    c822:	f104 0904 	add.w	r9, r4, #4
				} else if (*fmt == 'u') {
    c826:	d112      	bne.n	c84e <z_vprintk+0x18a>
					d = va_arg(ap, unsigned int);
    c828:	2300      	movs	r3, #0
	print_digits(out, ctx, num, 10, padding != PAD_SPACE_AFTER,
    c82a:	1ef8      	subs	r0, r7, #3
    c82c:	bf18      	it	ne
    c82e:	2001      	movne	r0, #1
    c830:	2f01      	cmp	r7, #1
    c832:	bf0c      	ite	eq
    c834:	2430      	moveq	r4, #48	; 0x30
    c836:	2420      	movne	r4, #32
    c838:	9001      	str	r0, [sp, #4]
    c83a:	200a      	movs	r0, #10
    c83c:	e9cd 4802 	strd	r4, r8, [sp, #8]
    c840:	9000      	str	r0, [sp, #0]
    c842:	4659      	mov	r1, fp
    c844:	4628      	mov	r0, r5
    c846:	f7ff fee1 	bl	c60c <print_digits>
}
    c84a:	464c      	mov	r4, r9
    c84c:	e746      	b.n	c6dc <z_vprintk+0x18>
					d = va_arg(ap, int);
    c84e:	17d3      	asrs	r3, r2, #31
				if (*fmt != 'u' && negative(d)) {
    c850:	2a00      	cmp	r2, #0
    c852:	f173 0100 	sbcs.w	r1, r3, #0
    c856:	dae8      	bge.n	c82a <z_vprintk+0x166>
					out((int)'-', ctx);
    c858:	4659      	mov	r1, fp
    c85a:	202d      	movs	r0, #45	; 0x2d
    c85c:	e9cd 2304 	strd	r2, r3, [sp, #16]
    c860:	47a8      	blx	r5
					d = -d;
    c862:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
    c866:	4252      	negs	r2, r2
    c868:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
					min_width--;
    c86c:	f108 38ff 	add.w	r8, r8, #4294967295
    c870:	e7db      	b.n	c82a <z_vprintk+0x166>
				out('0', ctx);
    c872:	4659      	mov	r1, fp
    c874:	2030      	movs	r0, #48	; 0x30
    c876:	47a8      	blx	r5
				out('x', ctx);
    c878:	4659      	mov	r1, fp
    c87a:	2078      	movs	r0, #120	; 0x78
    c87c:	47a8      	blx	r5
				min_width = sizeof(void *) * 2;
    c87e:	f04f 0808 	mov.w	r8, #8
				padding = PAD_ZERO_BEFORE;
    c882:	2701      	movs	r7, #1
    c884:	e78c      	b.n	c7a0 <z_vprintk+0xdc>
				} else if (length_mod == 'l') {
    c886:	2e6c      	cmp	r6, #108	; 0x6c
    c888:	d08e      	beq.n	c7a8 <z_vprintk+0xe4>
				} else if (length_mod == 'L') {
    c88a:	2e4c      	cmp	r6, #76	; 0x4c
    c88c:	d18c      	bne.n	c7a8 <z_vprintk+0xe4>
					x = va_arg(ap, unsigned long long);
    c88e:	1de3      	adds	r3, r4, #7
    c890:	f023 0307 	bic.w	r3, r3, #7
    c894:	461c      	mov	r4, r3
    c896:	685b      	ldr	r3, [r3, #4]
    c898:	f854 2b08 	ldr.w	r2, [r4], #8
	print_digits(out, ctx, num, 16, padding != PAD_SPACE_AFTER,
    c89c:	1ef8      	subs	r0, r7, #3
    c89e:	bf18      	it	ne
    c8a0:	2001      	movne	r0, #1
    c8a2:	2f01      	cmp	r7, #1
    c8a4:	bf0c      	ite	eq
    c8a6:	2130      	moveq	r1, #48	; 0x30
    c8a8:	2120      	movne	r1, #32
    c8aa:	e9cd 1802 	strd	r1, r8, [sp, #8]
    c8ae:	2110      	movs	r1, #16
    c8b0:	9001      	str	r0, [sp, #4]
    c8b2:	9100      	str	r1, [sp, #0]
    c8b4:	4628      	mov	r0, r5
    c8b6:	4659      	mov	r1, fp
    c8b8:	f7ff fea8 	bl	c60c <print_digits>
    c8bc:	e70e      	b.n	c6dc <z_vprintk+0x18>
				char *s = va_arg(ap, char *);
    c8be:	f854 3b04 	ldr.w	r3, [r4], #4
				while (*s) {
    c8c2:	4699      	mov	r9, r3
    c8c4:	464a      	mov	r2, r9
    c8c6:	f819 0b01 	ldrb.w	r0, [r9], #1
    c8ca:	b978      	cbnz	r0, c8ec <z_vprintk+0x228>
				if (padding == PAD_SPACE_AFTER) {
    c8cc:	2f03      	cmp	r7, #3
    c8ce:	d125      	bne.n	c91c <z_vprintk+0x258>
					int remaining = min_width - (s - start);
    c8d0:	eba2 0903 	sub.w	r9, r2, r3
    c8d4:	eba8 0909 	sub.w	r9, r8, r9
					while (remaining-- > 0) {
    c8d8:	f1b9 0f00 	cmp.w	r9, #0
    c8dc:	f77f aefe 	ble.w	c6dc <z_vprintk+0x18>
						out(' ', ctx);
    c8e0:	4659      	mov	r1, fp
    c8e2:	2020      	movs	r0, #32
    c8e4:	47a8      	blx	r5
    c8e6:	f109 39ff 	add.w	r9, r9, #4294967295
    c8ea:	e7f5      	b.n	c8d8 <z_vprintk+0x214>
					out((int)(*s++), ctx);
    c8ec:	4659      	mov	r1, fp
    c8ee:	9304      	str	r3, [sp, #16]
    c8f0:	47a8      	blx	r5
    c8f2:	9b04      	ldr	r3, [sp, #16]
    c8f4:	e7e6      	b.n	c8c4 <z_vprintk+0x200>
				out(c, ctx);
    c8f6:	4659      	mov	r1, fp
    c8f8:	f854 0b04 	ldr.w	r0, [r4], #4
    c8fc:	e713      	b.n	c726 <z_vprintk+0x62>
				out((int)'%', ctx);
    c8fe:	4659      	mov	r1, fp
    c900:	e711      	b.n	c726 <z_vprintk+0x62>
				length_mod = 0;
    c902:	464e      	mov	r6, r9
				padding = PAD_NONE;
    c904:	464f      	mov	r7, r9
				min_width = -1;
    c906:	f04f 38ff 	mov.w	r8, #4294967295
				might_format = 1;
    c90a:	f04f 0901 	mov.w	r9, #1
    c90e:	e6f0      	b.n	c6f2 <z_vprintk+0x2e>
			switch (*fmt) {
    c910:	2703      	movs	r7, #3
    c912:	e6ee      	b.n	c6f2 <z_vprintk+0x2e>
					padding = PAD_ZERO_BEFORE;
    c914:	2701      	movs	r7, #1
    c916:	e6ec      	b.n	c6f2 <z_vprintk+0x2e>
					length_mod = 'L';
    c918:	264c      	movs	r6, #76	; 0x4c
    c91a:	e6ea      	b.n	c6f2 <z_vprintk+0x2e>
			might_format = 0;
    c91c:	4681      	mov	r9, r0
    c91e:	e6e8      	b.n	c6f2 <z_vprintk+0x2e>

0000c920 <vprintk>:
#endif
	}
}
#else
void vprintk(const char *fmt, va_list ap)
{
    c920:	b507      	push	{r0, r1, r2, lr}
    c922:	460b      	mov	r3, r1
	struct out_context ctx = { 0 };
    c924:	2100      	movs	r1, #0
{
    c926:	4602      	mov	r2, r0
	struct out_context ctx = { 0 };
    c928:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
	k_spinlock_key_t key = k_spin_lock(&lock);
#endif

	z_vprintk(char_out, &ctx, fmt, ap);
    c92a:	4803      	ldr	r0, [pc, #12]	; (c938 <vprintk+0x18>)
    c92c:	a901      	add	r1, sp, #4
    c92e:	f7ff fec9 	bl	c6c4 <z_vprintk>

#ifdef CONFIG_PRINTK_SYNC
	k_spin_unlock(&lock, key);
#endif
}
    c932:	b003      	add	sp, #12
    c934:	f85d fb04 	ldr.w	pc, [sp], #4
    c938:	0000c6a9 	.word	0x0000c6a9

0000c93c <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
    c93c:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    c940:	f8b0 9018 	ldrh.w	r9, [r0, #24]
{
    c944:	4604      	mov	r4, r0
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
    c946:	f019 0808 	ands.w	r8, r9, #8
{
    c94a:	4693      	mov	fp, r2
	if (processing) {
    c94c:	d00d      	beq.n	c96a <process_event+0x2e>
		if (evt == EVT_COMPLETE) {
    c94e:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
    c950:	bf0c      	ite	eq
    c952:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
    c956:	f049 0920 	orrne.w	r9, r9, #32
    c95a:	f8a0 9018 	strh.w	r9, [r0, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
    c95e:	f38b 8811 	msr	BASEPRI, fp
    c962:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
    c966:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    c96a:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
    c96e:	2902      	cmp	r1, #2
    c970:	d107      	bne.n	c982 <process_event+0x46>
			evt = process_recheck(mgr);
    c972:	4620      	mov	r0, r4
    c974:	f002 fd29 	bl	f3ca <process_recheck>
		if (evt == EVT_NOP) {
    c978:	2800      	cmp	r0, #0
    c97a:	d0f0      	beq.n	c95e <process_event+0x22>
		if (evt == EVT_COMPLETE) {
    c97c:	2801      	cmp	r0, #1
    c97e:	8b23      	ldrh	r3, [r4, #24]
    c980:	d150      	bne.n	ca24 <process_event+0xe8>
			res = mgr->last_res;
    c982:	6967      	ldr	r7, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    c984:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
    c986:	2f00      	cmp	r7, #0
    c988:	da15      	bge.n	c9b6 <process_event+0x7a>
		*clients = mgr->clients;
    c98a:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c98c:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
    c990:	e9c4 8800 	strd	r8, r8, [r4]
    c994:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
    c998:	8321      	strh	r1, [r4, #24]
		onoff_transition_fn transit = NULL;
    c99a:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    c99c:	8b21      	ldrh	r1, [r4, #24]
    c99e:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
    c9a2:	45ca      	cmp	sl, r9
    c9a4:	d002      	beq.n	c9ac <process_event+0x70>
		if (do_monitors
    c9a6:	68a3      	ldr	r3, [r4, #8]
    c9a8:	2b00      	cmp	r3, #0
    c9aa:	d15c      	bne.n	ca66 <process_event+0x12a>
		    || !sys_slist_is_empty(&clients)
    c9ac:	b90d      	cbnz	r5, c9b2 <process_event+0x76>
		    || (transit != NULL)) {
    c9ae:	2e00      	cmp	r6, #0
    c9b0:	d074      	beq.n	ca9c <process_event+0x160>
    c9b2:	2300      	movs	r3, #0
    c9b4:	e058      	b.n	ca68 <process_event+0x12c>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    c9b6:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
    c9ba:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
    c9bc:	2a01      	cmp	r2, #1
    c9be:	d820      	bhi.n	ca02 <process_event+0xc6>
		*clients = mgr->clients;
    c9c0:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
    c9c4:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
    c9c6:	6825      	ldr	r5, [r4, #0]
	list->head = NULL;
    c9c8:	b289      	uxth	r1, r1
	list->tail = NULL;
    c9ca:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
    c9ce:	d10c      	bne.n	c9ea <process_event+0xae>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
    c9d0:	2d00      	cmp	r5, #0
    c9d2:	462b      	mov	r3, r5
    c9d4:	bf38      	it	cc
    c9d6:	2300      	movcc	r3, #0
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    c9d8:	b12b      	cbz	r3, c9e6 <process_event+0xaa>
				mgr->refs += 1U;
    c9da:	8b62      	ldrh	r2, [r4, #26]
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next_no_check(sys_snode_t *node);

Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    c9dc:	681b      	ldr	r3, [r3, #0]
    c9de:	3201      	adds	r2, #1
    c9e0:	8362      	strh	r2, [r4, #26]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    c9e2:	2b00      	cmp	r3, #0
    c9e4:	d1f8      	bne.n	c9d8 <process_event+0x9c>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c9e6:	f041 0102 	orr.w	r1, r1, #2
		if (process_recheck(mgr) != EVT_NOP) {
    c9ea:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
    c9ec:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    c9ee:	f002 fcec 	bl	f3ca <process_recheck>
    c9f2:	4606      	mov	r6, r0
    c9f4:	2800      	cmp	r0, #0
    c9f6:	d0d1      	beq.n	c99c <process_event+0x60>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    c9f8:	8b23      	ldrh	r3, [r4, #24]
    c9fa:	f043 0320 	orr.w	r3, r3, #32
    c9fe:	8323      	strh	r3, [r4, #24]
    ca00:	e7cb      	b.n	c99a <process_event+0x5e>
	} else if (state == ONOFF_STATE_TO_OFF) {
    ca02:	2b04      	cmp	r3, #4
    ca04:	d10c      	bne.n	ca20 <process_event+0xe4>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    ca06:	f021 0107 	bic.w	r1, r1, #7
    ca0a:	b289      	uxth	r1, r1
		if (process_recheck(mgr) != EVT_NOP) {
    ca0c:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
    ca0e:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    ca10:	f002 fcdb 	bl	f3ca <process_recheck>
    ca14:	4605      	mov	r5, r0
    ca16:	2800      	cmp	r0, #0
    ca18:	d0bf      	beq.n	c99a <process_event+0x5e>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    ca1a:	f041 0120 	orr.w	r1, r1, #32
    ca1e:	8321      	strh	r1, [r4, #24]
    ca20:	2500      	movs	r5, #0
    ca22:	e7ba      	b.n	c99a <process_event+0x5e>
		} else if (evt == EVT_START) {
    ca24:	2803      	cmp	r0, #3
    ca26:	d109      	bne.n	ca3c <process_event+0x100>
			transit = mgr->transitions->start;
    ca28:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    ca2a:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
    ca2e:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    ca30:	f043 0306 	orr.w	r3, r3, #6
}
    ca34:	2500      	movs	r5, #0
	mgr->flags = (state & ONOFF_STATE_MASK)
    ca36:	8323      	strh	r3, [r4, #24]
		res = 0;
    ca38:	462f      	mov	r7, r5
    ca3a:	e7af      	b.n	c99c <process_event+0x60>
		} else if (evt == EVT_STOP) {
    ca3c:	2804      	cmp	r0, #4
    ca3e:	d106      	bne.n	ca4e <process_event+0x112>
			transit = mgr->transitions->stop;
    ca40:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    ca42:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
    ca46:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    ca48:	f043 0304 	orr.w	r3, r3, #4
    ca4c:	e7f2      	b.n	ca34 <process_event+0xf8>
		} else if (evt == EVT_RESET) {
    ca4e:	2805      	cmp	r0, #5
    ca50:	d106      	bne.n	ca60 <process_event+0x124>
			transit = mgr->transitions->reset;
    ca52:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    ca54:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
    ca58:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    ca5a:	f043 0305 	orr.w	r3, r3, #5
    ca5e:	e7e9      	b.n	ca34 <process_event+0xf8>
    ca60:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
    ca62:	462e      	mov	r6, r5
    ca64:	e7e8      	b.n	ca38 <process_event+0xfc>
				   && !sys_slist_is_empty(&mgr->monitors);
    ca66:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
    ca68:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
    ca6c:	8321      	strh	r1, [r4, #24]
    ca6e:	f38b 8811 	msr	BASEPRI, fp
    ca72:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
    ca76:	bb03      	cbnz	r3, caba <process_event+0x17e>
	while (!sys_slist_is_empty(list)) {
    ca78:	2d00      	cmp	r5, #0
    ca7a:	d133      	bne.n	cae4 <process_event+0x1a8>
			if (transit != NULL) {
    ca7c:	b116      	cbz	r6, ca84 <process_event+0x148>
				transit(mgr, transition_complete);
    ca7e:	4620      	mov	r0, r4
    ca80:	4920      	ldr	r1, [pc, #128]	; (cb04 <process_event+0x1c8>)
    ca82:	47b0      	blx	r6
	__asm__ volatile(
    ca84:	f04f 0320 	mov.w	r3, #32
    ca88:	f3ef 8b11 	mrs	fp, BASEPRI
    ca8c:	f383 8811 	msr	BASEPRI, r3
    ca90:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
    ca94:	8b23      	ldrh	r3, [r4, #24]
    ca96:	f023 0308 	bic.w	r3, r3, #8
    ca9a:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
    ca9c:	8b23      	ldrh	r3, [r4, #24]
    ca9e:	06da      	lsls	r2, r3, #27
    caa0:	d528      	bpl.n	caf4 <process_event+0x1b8>
			evt = EVT_COMPLETE;
    caa2:	2101      	movs	r1, #1
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
    caa4:	f023 0310 	bic.w	r3, r3, #16
    caa8:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
    caaa:	f8b4 9018 	ldrh.w	r9, [r4, #24]
    caae:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
    cab2:	2900      	cmp	r1, #0
    cab4:	f47f af5b 	bne.w	c96e <process_event+0x32>
out:
    cab8:	e751      	b.n	c95e <process_event+0x22>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    caba:	68a1      	ldr	r1, [r4, #8]
    cabc:	2900      	cmp	r1, #0
    cabe:	d0db      	beq.n	ca78 <process_event+0x13c>
	return node->next;
    cac0:	680b      	ldr	r3, [r1, #0]
    cac2:	2b00      	cmp	r3, #0
    cac4:	bf38      	it	cc
    cac6:	2300      	movcc	r3, #0
    cac8:	4699      	mov	r9, r3
		mon->callback(mgr, mon, state, res);
    caca:	4652      	mov	r2, sl
    cacc:	463b      	mov	r3, r7
    cace:	4620      	mov	r0, r4
    cad0:	f8d1 b004 	ldr.w	fp, [r1, #4]
    cad4:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    cad6:	f1b9 0f00 	cmp.w	r9, #0
    cada:	d0cd      	beq.n	ca78 <process_event+0x13c>
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    cadc:	4649      	mov	r1, r9
    cade:	f8d9 3000 	ldr.w	r3, [r9]
    cae2:	e7ee      	b.n	cac2 <process_event+0x186>
 *
 * @return A pointer to the first node of the list
 */
static inline sys_snode_t *sys_slist_get_not_empty(sys_slist_t *list);

Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    cae4:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
    cae6:	463b      	mov	r3, r7
    cae8:	4652      	mov	r2, sl
    caea:	4620      	mov	r0, r4
    caec:	682d      	ldr	r5, [r5, #0]
    caee:	f002 fc88 	bl	f402 <notify_one>
    caf2:	e7c1      	b.n	ca78 <process_event+0x13c>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
    caf4:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
    caf8:	bf1e      	ittt	ne
    cafa:	f023 0320 	bicne.w	r3, r3, #32
			evt = EVT_RECHECK;
    cafe:	2102      	movne	r1, #2
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
    cb00:	8323      	strhne	r3, [r4, #24]
			evt = EVT_RECHECK;
    cb02:	e7d2      	b.n	caaa <process_event+0x16e>
    cb04:	0000f42f 	.word	0x0000f42f

0000cb08 <nordicsemi_nrf91_init>:
    cb08:	f04f 0220 	mov.w	r2, #32
    cb0c:	f3ef 8311 	mrs	r3, BASEPRI
    cb10:	f382 8811 	msr	BASEPRI, r2
    cb14:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    cb18:	2101      	movs	r1, #1
    cb1a:	4a04      	ldr	r2, [pc, #16]	; (cb2c <nordicsemi_nrf91_init+0x24>)
    cb1c:	f8c2 1540 	str.w	r1, [r2, #1344]	; 0x540
	__asm__ volatile(
    cb20:	f383 8811 	msr	BASEPRI, r3
    cb24:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    cb28:	2000      	movs	r0, #0
    cb2a:	4770      	bx	lr
    cb2c:	40039000 	.word	0x40039000

0000cb30 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    cb30:	b120      	cbz	r0, cb3c <arch_busy_wait+0xc>
    };

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    cb32:	4b03      	ldr	r3, [pc, #12]	; (cb40 <arch_busy_wait+0x10>)
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    cb34:	0180      	lsls	r0, r0, #6
    cb36:	f043 0301 	orr.w	r3, r3, #1
    cb3a:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    cb3c:	4770      	bx	lr
    cb3e:	bf00      	nop
    cb40:	00010110 	.word	0x00010110

0000cb44 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    cb44:	b510      	push	{r4, lr}
    cb46:	4807      	ldr	r0, [pc, #28]	; (cb64 <uart_console_init+0x20>)
    cb48:	f001 fda8 	bl	e69c <z_impl_device_get_binding>
	__stdout_hook_install(console_out);
    cb4c:	4c06      	ldr	r4, [pc, #24]	; (cb68 <uart_console_init+0x24>)

	ARG_UNUSED(arg);

	/* Claim console device */
	uart_console_dev = device_get_binding(CONFIG_UART_CONSOLE_ON_DEV_NAME);
    cb4e:	4b07      	ldr	r3, [pc, #28]	; (cb6c <uart_console_init+0x28>)
    cb50:	6018      	str	r0, [r3, #0]
	__stdout_hook_install(console_out);
    cb52:	4620      	mov	r0, r4
    cb54:	f000 fe6a 	bl	d82c <__stdout_hook_install>
	__printk_hook_install(console_out);
    cb58:	4620      	mov	r0, r4
    cb5a:	f7ff fdad 	bl	c6b8 <__printk_hook_install>

	uart_console_hook_install();

	return 0;
}
    cb5e:	2000      	movs	r0, #0
    cb60:	bd10      	pop	{r4, pc}
    cb62:	bf00      	nop
    cb64:	00010281 	.word	0x00010281
    cb68:	0000cb71 	.word	0x0000cb71
    cb6c:	2001020c 	.word	0x2001020c

0000cb70 <console_out>:
	if ('\n' == c) {
    cb70:	280a      	cmp	r0, #10
{
    cb72:	b538      	push	{r3, r4, r5, lr}
    cb74:	4604      	mov	r4, r0
    cb76:	4d07      	ldr	r5, [pc, #28]	; (cb94 <console_out+0x24>)
	if ('\n' == c) {
    cb78:	d104      	bne.n	cb84 <console_out+0x14>
    cb7a:	6828      	ldr	r0, [r5, #0]
						unsigned char out_char)
{
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    cb7c:	6883      	ldr	r3, [r0, #8]
    cb7e:	210d      	movs	r1, #13
    cb80:	685b      	ldr	r3, [r3, #4]
    cb82:	4798      	blx	r3
	uart_poll_out(uart_console_dev, c);
    cb84:	6828      	ldr	r0, [r5, #0]
    cb86:	6883      	ldr	r3, [r0, #8]
    cb88:	b2e1      	uxtb	r1, r4
    cb8a:	685b      	ldr	r3, [r3, #4]
    cb8c:	4798      	blx	r3
}
    cb8e:	4620      	mov	r0, r4
    cb90:	bd38      	pop	{r3, r4, r5, pc}
    cb92:	bf00      	nop
    cb94:	2001020c 	.word	0x2001020c

0000cb98 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = DEVICE_GET(clock_nrf)->data;
	size_t offset = (size_t)(mgr - data->mgr);
    cb98:	4a0e      	ldr	r2, [pc, #56]	; (cbd4 <onoff_stop+0x3c>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    cb9a:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    cb9c:	1a84      	subs	r4, r0, r2
{
    cb9e:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
    cba0:	200c      	movs	r0, #12
{
    cba2:	460e      	mov	r6, r1
	err = set_off_state(&subdata->flags, ctx);
    cba4:	2140      	movs	r1, #64	; 0x40
	size_t offset = (size_t)(mgr - data->mgr);
    cba6:	10a3      	asrs	r3, r4, #2
    cba8:	4c0b      	ldr	r4, [pc, #44]	; (cbd8 <onoff_stop+0x40>)
    cbaa:	435c      	muls	r4, r3
    cbac:	b2e4      	uxtb	r4, r4
	err = set_off_state(&subdata->flags, ctx);
    cbae:	fb00 2004 	mla	r0, r0, r4, r2
    cbb2:	4408      	add	r0, r1
    cbb4:	f002 fda6 	bl	f704 <set_off_state>
	if (err < 0) {
    cbb8:	1e01      	subs	r1, r0, #0
    cbba:	db05      	blt.n	cbc8 <onoff_stop+0x30>
	get_sub_config(dev, type)->stop();
    cbbc:	4b07      	ldr	r3, [pc, #28]	; (cbdc <onoff_stop+0x44>)
    cbbe:	eb03 04c4 	add.w	r4, r3, r4, lsl #3
    cbc2:	6863      	ldr	r3, [r4, #4]
    cbc4:	4798      	blx	r3
	return 0;
    cbc6:	2100      	movs	r1, #0
	int res;

	res = stop(DEVICE_GET(clock_nrf), get_subsys(mgr), CTX_ONOFF);
	notify(mgr, res);
    cbc8:	4628      	mov	r0, r5
    cbca:	4633      	mov	r3, r6
}
    cbcc:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    cbd0:	4718      	bx	r3
    cbd2:	bf00      	nop
    cbd4:	20010220 	.word	0x20010220
    cbd8:	b6db6db7 	.word	0xb6db6db7
    cbdc:	00010138 	.word	0x00010138

0000cbe0 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    cbe0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	err = set_starting_state(&subdata->flags, ctx);
    cbe4:	250c      	movs	r5, #12
	size_t offset = (size_t)(mgr - data->mgr);
    cbe6:	4e10      	ldr	r6, [pc, #64]	; (cc28 <onoff_start+0x48>)
{
    cbe8:	4680      	mov	r8, r0
	size_t offset = (size_t)(mgr - data->mgr);
    cbea:	1b84      	subs	r4, r0, r6
    cbec:	10a3      	asrs	r3, r4, #2
    cbee:	4c0f      	ldr	r4, [pc, #60]	; (cc2c <onoff_start+0x4c>)
{
    cbf0:	460f      	mov	r7, r1
	size_t offset = (size_t)(mgr - data->mgr);
    cbf2:	435c      	muls	r4, r3
    cbf4:	b2e4      	uxtb	r4, r4
	err = set_starting_state(&subdata->flags, ctx);
    cbf6:	4365      	muls	r5, r4
    cbf8:	f105 0040 	add.w	r0, r5, #64	; 0x40
    cbfc:	2140      	movs	r1, #64	; 0x40
    cbfe:	4430      	add	r0, r6
    cc00:	f002 fd99 	bl	f736 <set_starting_state>
	if (err < 0) {
    cc04:	1e01      	subs	r1, r0, #0
    cc06:	db09      	blt.n	cc1c <onoff_start+0x3c>
	subdata->cb = data->cb;
    cc08:	4a09      	ldr	r2, [pc, #36]	; (cc30 <onoff_start+0x50>)
    cc0a:	1973      	adds	r3, r6, r5
	subdata->user_data = data->user_data;
    cc0c:	e9c3 270e 	strd	r2, r7, [r3, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    cc10:	4b08      	ldr	r3, [pc, #32]	; (cc34 <onoff_start+0x54>)
    cc12:	f853 3034 	ldr.w	r3, [r3, r4, lsl #3]
	err = async_start(DEVICE_GET(clock_nrf), get_subsys(mgr),
			  &data, CTX_ONOFF);
	if (err < 0) {
		notify(mgr, err);
	}
}
    cc16:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
	 get_sub_config(dev, type)->start();
    cc1a:	4718      	bx	r3
		notify(mgr, err);
    cc1c:	4640      	mov	r0, r8
    cc1e:	463b      	mov	r3, r7
}
    cc20:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		notify(mgr, err);
    cc24:	4718      	bx	r3
    cc26:	bf00      	nop
    cc28:	20010220 	.word	0x20010220
    cc2c:	b6db6db7 	.word	0xb6db6db7
    cc30:	0000f799 	.word	0x0000f799
    cc34:	00010138 	.word	0x00010138

0000cc38 <clk_init>:
		break;
	}
}

static int clk_init(const struct device *dev)
{
    cc38:	b570      	push	{r4, r5, r6, lr}
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    cc3a:	2200      	movs	r2, #0
    cc3c:	2101      	movs	r1, #1
{
    cc3e:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    cc40:	2005      	movs	r0, #5
    cc42:	f000 fa3f 	bl	d0c4 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);
	irq_enable(DT_INST_IRQN(0));
    cc46:	2005      	movs	r0, #5
    cc48:	f000 fa1e 	bl	d088 <arch_irq_enable>
					NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
		nrf_gpio_pin_mcu_select(PIN_XL2,
					NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
	}
#endif
	nrfx_err = nrfx_clock_init(clock_event_handler);
    cc4c:	480f      	ldr	r0, [pc, #60]	; (cc8c <clk_init+0x54>)
    cc4e:	f001 facd 	bl	e1ec <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    cc52:	4b0f      	ldr	r3, [pc, #60]	; (cc90 <clk_init+0x58>)
    cc54:	4298      	cmp	r0, r3
    cc56:	d115      	bne.n	cc84 <clk_init+0x4c>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    cc58:	f002 ffd3 	bl	fc02 <nrfx_clock_enable>

	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);
    cc5c:	68e6      	ldr	r6, [r4, #12]

		err = onoff_manager_init(get_onoff_manager(dev, i),
    cc5e:	490d      	ldr	r1, [pc, #52]	; (cc94 <clk_init+0x5c>)
    cc60:	4630      	mov	r0, r6
    cc62:	f002 fc01 	bl	f468 <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    cc66:	2800      	cmp	r0, #0
    cc68:	db0b      	blt.n	cc82 <clk_init+0x4a>
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    cc6a:	2501      	movs	r5, #1
    cc6c:	6435      	str	r5, [r6, #64]	; 0x40
						get_sub_data(dev, i);
    cc6e:	68e4      	ldr	r4, [r4, #12]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    cc70:	4908      	ldr	r1, [pc, #32]	; (cc94 <clk_init+0x5c>)
    cc72:	f104 001c 	add.w	r0, r4, #28
    cc76:	f002 fbf7 	bl	f468 <onoff_manager_init>
		if (err < 0) {
    cc7a:	2800      	cmp	r0, #0
    cc7c:	db01      	blt.n	cc82 <clk_init+0x4a>
	}

	return 0;
    cc7e:	2000      	movs	r0, #0
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    cc80:	64e5      	str	r5, [r4, #76]	; 0x4c
}
    cc82:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    cc84:	f06f 0004 	mvn.w	r0, #4
    cc88:	e7fb      	b.n	cc82 <clk_init+0x4a>
    cc8a:	bf00      	nop
    cc8c:	0000cccd 	.word	0x0000cccd
    cc90:	0bad0000 	.word	0x0bad0000
    cc94:	00010148 	.word	0x00010148

0000cc98 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    cc98:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    cc9a:	230c      	movs	r3, #12
	sub_data->cb = NULL;
    cc9c:	2200      	movs	r2, #0
	clock_control_cb_t callback = sub_data->cb;
    cc9e:	434b      	muls	r3, r1
    cca0:	4808      	ldr	r0, [pc, #32]	; (ccc4 <clkstarted_handle.constprop.0+0x2c>)
static void clkstarted_handle(const struct device *dev,
    cca2:	b570      	push	{r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    cca4:	18c4      	adds	r4, r0, r3
	set_on_state(&sub_data->flags);
    cca6:	3340      	adds	r3, #64	; 0x40
	void *user_data = sub_data->user_data;
    cca8:	e9d4 560e 	ldrd	r5, r6, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    ccac:	4418      	add	r0, r3
	sub_data->cb = NULL;
    ccae:	63a2      	str	r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    ccb0:	f002 fd5f 	bl	f772 <set_on_state>
	if (callback) {
    ccb4:	b12d      	cbz	r5, ccc2 <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    ccb6:	4632      	mov	r2, r6
    ccb8:	462b      	mov	r3, r5
}
    ccba:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    ccbe:	4802      	ldr	r0, [pc, #8]	; (ccc8 <clkstarted_handle.constprop.0+0x30>)
    ccc0:	4718      	bx	r3
}
    ccc2:	bd70      	pop	{r4, r5, r6, pc}
    ccc4:	20010220 	.word	0x20010220
    ccc8:	20010098 	.word	0x20010098

0000cccc <clock_event_handler>:
	switch (event) {
    cccc:	b110      	cbz	r0, ccd4 <clock_event_handler+0x8>
    ccce:	2801      	cmp	r0, #1
    ccd0:	d004      	beq.n	ccdc <clock_event_handler+0x10>
    ccd2:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    ccd4:	4b03      	ldr	r3, [pc, #12]	; (cce4 <clock_event_handler+0x18>)
    ccd6:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    ccd8:	075b      	lsls	r3, r3, #29
    ccda:	d101      	bne.n	cce0 <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    ccdc:	f7ff bfdc 	b.w	cc98 <clkstarted_handle.constprop.0>
}
    cce0:	4770      	bx	lr
    cce2:	bf00      	nop
    cce4:	20010220 	.word	0x20010220

0000cce8 <generic_hfclk_start>:
{
    cce8:	b508      	push	{r3, lr}
	__asm__ volatile(
    ccea:	f04f 0320 	mov.w	r3, #32
    ccee:	f3ef 8111 	mrs	r1, BASEPRI
    ccf2:	f383 8811 	msr	BASEPRI, r3
    ccf6:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    ccfa:	4a11      	ldr	r2, [pc, #68]	; (cd40 <generic_hfclk_start+0x58>)
    ccfc:	6813      	ldr	r3, [r2, #0]
    ccfe:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
    cd02:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
    cd06:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    cd08:	d00b      	beq.n	cd22 <generic_hfclk_start+0x3a>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    cd0a:	4a0e      	ldr	r2, [pc, #56]	; (cd44 <generic_hfclk_start+0x5c>)
    cd0c:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    cd10:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    cd14:	f013 0301 	ands.w	r3, r3, #1
    cd18:	d003      	beq.n	cd22 <generic_hfclk_start+0x3a>
			set_on_state(get_hf_flags());
    cd1a:	480b      	ldr	r0, [pc, #44]	; (cd48 <generic_hfclk_start+0x60>)
    cd1c:	f002 fd29 	bl	f772 <set_on_state>
			already_started = true;
    cd20:	2301      	movs	r3, #1
	__asm__ volatile(
    cd22:	f381 8811 	msr	BASEPRI, r1
    cd26:	f3bf 8f6f 	isb	sy
	if (already_started) {
    cd2a:	b123      	cbz	r3, cd36 <generic_hfclk_start+0x4e>
}
    cd2c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(DEVICE_GET(clock_nrf),
    cd30:	2000      	movs	r0, #0
    cd32:	f7ff bfb1 	b.w	cc98 <clkstarted_handle.constprop.0>
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    cd36:	2001      	movs	r0, #1
}
    cd38:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    cd3c:	f001 ba66 	b.w	e20c <nrfx_clock_start>
    cd40:	20010270 	.word	0x20010270
    cd44:	40005000 	.word	0x40005000
    cd48:	20010260 	.word	0x20010260

0000cd4c <generic_hfclk_stop>:
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    cd4c:	4b07      	ldr	r3, [pc, #28]	; (cd6c <generic_hfclk_stop+0x20>)
    cd4e:	e8d3 2fef 	ldaex	r2, [r3]
    cd52:	f022 0102 	bic.w	r1, r2, #2
    cd56:	e8c3 1fe0 	stlex	r0, r1, [r3]
    cd5a:	2800      	cmp	r0, #0
    cd5c:	d1f7      	bne.n	cd4e <generic_hfclk_stop+0x2>
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    cd5e:	07d3      	lsls	r3, r2, #31
    cd60:	d402      	bmi.n	cd68 <generic_hfclk_stop+0x1c>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    cd62:	2001      	movs	r0, #1
    cd64:	f001 ba84 	b.w	e270 <nrfx_clock_stop>
}
    cd68:	4770      	bx	lr
    cd6a:	bf00      	nop
    cd6c:	20010270 	.word	0x20010270

0000cd70 <api_blocking_start>:
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    cd70:	2300      	movs	r3, #0
    cd72:	2201      	movs	r2, #1
{
    cd74:	b510      	push	{r4, lr}
    cd76:	b088      	sub	sp, #32
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    cd78:	e9cd 3206 	strd	r3, r2, [sp, #24]
	struct clock_control_async_data data = {
    cd7c:	9301      	str	r3, [sp, #4]
    cd7e:	4b09      	ldr	r3, [pc, #36]	; (cda4 <api_blocking_start+0x34>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    cd80:	ac04      	add	r4, sp, #16
	err = api_start(dev, subsys, &data);
    cd82:	aa01      	add	r2, sp, #4
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    cd84:	e9cd 4404 	strd	r4, r4, [sp, #16]
	struct clock_control_async_data data = {
    cd88:	e9cd 3402 	strd	r3, r4, [sp, #8]
	err = api_start(dev, subsys, &data);
    cd8c:	f002 fd2a 	bl	f7e4 <api_start>
	if (err < 0) {
    cd90:	2800      	cmp	r0, #0
    cd92:	db05      	blt.n	cda0 <api_blocking_start+0x30>
		parm0.val = timeout;
		return (int) arch_syscall_invoke3(*(uintptr_t *)&sem, parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    cd94:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    cd98:	2300      	movs	r3, #0
    cd9a:	4620      	mov	r0, r4
    cd9c:	f002 f8c6 	bl	ef2c <z_impl_k_sem_take>
}
    cda0:	b008      	add	sp, #32
    cda2:	bd10      	pop	{r4, pc}
    cda4:	0000f7ab 	.word	0x0000f7ab

0000cda8 <z_nrf_clock_control_lf_on>:
{
    cda8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    cdac:	2201      	movs	r2, #1
    cdae:	4607      	mov	r7, r0
    cdb0:	4936      	ldr	r1, [pc, #216]	; (ce8c <z_nrf_clock_control_lf_on+0xe4>)
    cdb2:	e8d1 3fef 	ldaex	r3, [r1]
    cdb6:	e8c1 2fe0 	stlex	r0, r2, [r1]
    cdba:	2800      	cmp	r0, #0
    cdbc:	d1f9      	bne.n	cdb2 <z_nrf_clock_control_lf_on+0xa>
	if (atomic_set(&on, 1) == 0) {
    cdbe:	b933      	cbnz	r3, cdce <z_nrf_clock_control_lf_on+0x26>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    cdc0:	4933      	ldr	r1, [pc, #204]	; (ce90 <z_nrf_clock_control_lf_on+0xe8>)
		err = onoff_request(mgr, &cli);
    cdc2:	4834      	ldr	r0, [pc, #208]	; (ce94 <z_nrf_clock_control_lf_on+0xec>)
    cdc4:	604b      	str	r3, [r1, #4]
    cdc6:	60cb      	str	r3, [r1, #12]
    cdc8:	608a      	str	r2, [r1, #8]
    cdca:	f002 fb60 	bl	f48e <onoff_request>
	switch (start_mode) {
    cdce:	1e7b      	subs	r3, r7, #1
    cdd0:	2b01      	cmp	r3, #1
    cdd2:	d82e      	bhi.n	ce32 <z_nrf_clock_control_lf_on+0x8a>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    cdd4:	2f01      	cmp	r7, #1
    cdd6:	d106      	bne.n	cde6 <z_nrf_clock_control_lf_on+0x3e>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    cdd8:	4b2f      	ldr	r3, [pc, #188]	; (ce98 <z_nrf_clock_control_lf_on+0xf0>)
    cdda:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    cdde:	f003 0303 	and.w	r3, r3, #3
    cde2:	2b02      	cmp	r3, #2
    cde4:	d025      	beq.n	ce32 <z_nrf_clock_control_lf_on+0x8a>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    cde6:	f002 ffe0 	bl	fdaa <k_is_in_isr>
    cdea:	4604      	mov	r4, r0
    cdec:	b918      	cbnz	r0, cdf6 <z_nrf_clock_control_lf_on+0x4e>
 */
static inline bool k_is_pre_kernel(void)
{
	extern bool z_sys_post_kernel; /* in init.c */

	return !z_sys_post_kernel;
    cdee:	4b2b      	ldr	r3, [pc, #172]	; (ce9c <z_nrf_clock_control_lf_on+0xf4>)
	int key = isr_mode ? irq_lock() : 0;
    cdf0:	781b      	ldrb	r3, [r3, #0]
    cdf2:	2b00      	cmp	r3, #0
    cdf4:	d144      	bne.n	ce80 <z_nrf_clock_control_lf_on+0xd8>
	__asm__ volatile(
    cdf6:	f04f 0320 	mov.w	r3, #32
    cdfa:	f3ef 8611 	mrs	r6, BASEPRI
    cdfe:	f383 8811 	msr	BASEPRI, r3
    ce02:	f3bf 8f6f 	isb	sy
    ce06:	2401      	movs	r4, #1
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    ce08:	4d23      	ldr	r5, [pc, #140]	; (ce98 <z_nrf_clock_control_lf_on+0xf0>)
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    ce0a:	f8df 809c 	ldr.w	r8, [pc, #156]	; cea8 <z_nrf_clock_control_lf_on+0x100>
    ce0e:	46a9      	mov	r9, r5
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    ce10:	f8d5 3418 	ldr.w	r3, [r5, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    ce14:	f8d5 2418 	ldr.w	r2, [r5, #1048]	; 0x418
    ce18:	03d2      	lsls	r2, r2, #15
    ce1a:	d50c      	bpl.n	ce36 <z_nrf_clock_control_lf_on+0x8e>
	while (!(nrfx_clock_is_running(d, (void *)&type)
    ce1c:	f003 0303 	and.w	r3, r3, #3
    ce20:	2b02      	cmp	r3, #2
    ce22:	d001      	beq.n	ce28 <z_nrf_clock_control_lf_on+0x80>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    ce24:	2f01      	cmp	r7, #1
    ce26:	d106      	bne.n	ce36 <z_nrf_clock_control_lf_on+0x8e>
	if (isr_mode) {
    ce28:	b334      	cbz	r4, ce78 <z_nrf_clock_control_lf_on+0xd0>
	__asm__ volatile(
    ce2a:	f386 8811 	msr	BASEPRI, r6
    ce2e:	f3bf 8f6f 	isb	sy
}
    ce32:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			if (isr_mode) {
    ce36:	b1d4      	cbz	r4, ce6e <z_nrf_clock_control_lf_on+0xc6>
 *
 * @return N/A
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    ce38:	4630      	mov	r0, r6
    ce3a:	f000 fa01 	bl	d240 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    ce3e:	f8d5 3518 	ldr.w	r3, [r5, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    ce42:	b2db      	uxtb	r3, r3
    ce44:	2b01      	cmp	r3, #1
    ce46:	d1e3      	bne.n	ce10 <z_nrf_clock_control_lf_on+0x68>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    ce48:	f8d8 2000 	ldr.w	r2, [r8]
		    && nrf_clock_event_check(NRF_CLOCK,
    ce4c:	2a00      	cmp	r2, #0
    ce4e:	d0df      	beq.n	ce10 <z_nrf_clock_control_lf_on+0x68>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    ce50:	2200      	movs	r2, #0
    ce52:	f8c8 2000 	str.w	r2, [r8]
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    ce56:	f8d8 2000 	ldr.w	r2, [r8]
    p_reg->LFCLKSRC = (uint32_t)(source);
    ce5a:	2202      	movs	r2, #2
 */
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    ce5c:	2120      	movs	r1, #32
    ce5e:	f8c5 2518 	str.w	r2, [r5, #1304]	; 0x518
    ce62:	4a0f      	ldr	r2, [pc, #60]	; (cea0 <z_nrf_clock_control_lf_on+0xf8>)
    ce64:	f8c2 1180 	str.w	r1, [r2, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    ce68:	4a0e      	ldr	r2, [pc, #56]	; (cea4 <z_nrf_clock_control_lf_on+0xfc>)
    ce6a:	6013      	str	r3, [r2, #0]
}
    ce6c:	e7d0      	b.n	ce10 <z_nrf_clock_control_lf_on+0x68>
	return z_impl_k_sleep(timeout);
    ce6e:	2100      	movs	r1, #0
    ce70:	2021      	movs	r0, #33	; 0x21
    ce72:	f002 f815 	bl	eea0 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    ce76:	e7e2      	b.n	ce3e <z_nrf_clock_control_lf_on+0x96>
    p_reg->INTENSET = mask;
    ce78:	2302      	movs	r3, #2
    ce7a:	f8c9 3304 	str.w	r3, [r9, #772]	; 0x304
}
    ce7e:	e7d8      	b.n	ce32 <z_nrf_clock_control_lf_on+0x8a>
    p_reg->INTENCLR = mask;
    ce80:	2202      	movs	r2, #2
    ce82:	4b05      	ldr	r3, [pc, #20]	; (ce98 <z_nrf_clock_control_lf_on+0xf0>)
	int key = isr_mode ? irq_lock() : 0;
    ce84:	4606      	mov	r6, r0
    ce86:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
    ce8a:	e7bd      	b.n	ce08 <z_nrf_clock_control_lf_on+0x60>
    ce8c:	20010274 	.word	0x20010274
    ce90:	20010210 	.word	0x20010210
    ce94:	2001023c 	.word	0x2001023c
    ce98:	40005000 	.word	0x40005000
    ce9c:	20010320 	.word	0x20010320
    cea0:	e000e100 	.word	0xe000e100
    cea4:	40005008 	.word	0x40005008
    cea8:	40005104 	.word	0x40005104

0000ceac <handle_next_cycle_case>:
 * counter progresses during that time it means that 1 cycle elapsed and
 * interrupt is set pending.
 */
static void handle_next_cycle_case(uint32_t t)
{
	set_comparator(t + 2);
    ceac:	1c82      	adds	r2, r0, #2

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE  void nrf_rtc_cc_set(NRF_RTC_Type * p_reg, uint32_t ch, uint32_t cc_val)
{
    p_reg->CC[ch] = cc_val;
    ceae:	4b08      	ldr	r3, [pc, #32]	; (ced0 <handle_next_cycle_case+0x24>)
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
    ceb0:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
    ceb4:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type const * p_reg)
{
     return p_reg->COUNTER;
    ceb8:	f8d3 2504 	ldr.w	r2, [r3, #1284]	; 0x504
	while (t != counter()) {
    cebc:	4290      	cmp	r0, r2
    cebe:	d100      	bne.n	cec2 <handle_next_cycle_case+0x16>
		 * generated. Trigger interrupt.
		 */
		t = counter();
		set_comparator(t + 2);
	}
}
    cec0:	4770      	bx	lr
    cec2:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
		set_comparator(t + 2);
    cec6:	1c82      	adds	r2, r0, #2
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
    cec8:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
    cecc:	e7f2      	b.n	ceb4 <handle_next_cycle_case+0x8>
    cece:	bf00      	nop
    ced0:	40015000 	.word	0x40015000

0000ced4 <rtc_nrf_isr>:
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    ced4:	2200      	movs	r2, #0
    ced6:	4b07      	ldr	r3, [pc, #28]	; (cef4 <rtc_nrf_isr+0x20>)
    ced8:	601a      	str	r2, [r3, #0]
    ceda:	681b      	ldr	r3, [r3, #0]
{
	ARG_UNUSED(arg);
	event_clear();

	uint32_t t = get_comparator();
	uint32_t dticks = counter_sub(t, last_count) / CYC_PER_TICK;
    cedc:	4a06      	ldr	r2, [pc, #24]	; (cef8 <rtc_nrf_isr+0x24>)
    return p_reg->CC[ch];
    cede:	4b07      	ldr	r3, [pc, #28]	; (cefc <rtc_nrf_isr+0x28>)
    cee0:	f8d3 0540 	ldr.w	r0, [r3, #1344]	; 0x540
    cee4:	6813      	ldr	r3, [r2, #0]
	return (a - b) & COUNTER_MAX;
    cee6:	1ac0      	subs	r0, r0, r3
    cee8:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000

	last_count += dticks * CYC_PER_TICK;
    ceec:	4403      	add	r3, r0
    ceee:	6013      	str	r3, [r2, #0]
		 * so it won't get preempted by the interrupt.
		 */
		set_absolute_alarm(last_count + CYC_PER_TICK);
	}

	z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : (dticks > 0));
    cef0:	f002 b9a8 	b.w	f244 <z_clock_announce>
    cef4:	40015140 	.word	0x40015140
    cef8:	20010278 	.word	0x20010278
    cefc:	40015000 	.word	0x40015000

0000cf00 <z_clock_driver_init>:
}

int z_clock_driver_init(const struct device *device)
{
    cf00:	b538      	push	{r3, r4, r5, lr}
}

NRF_STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_reg, uint32_t val)
{
    NRFX_ASSERT(val <= (RTC_PRESCALER_PRESCALER_Msk >> RTC_PRESCALER_PRESCALER_Pos));
    p_reg->PRESCALER = val;
    cf02:	2400      	movs	r4, #0
    cf04:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
    cf08:	4d0e      	ldr	r5, [pc, #56]	; (cf44 <z_clock_driver_init+0x44>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    cf0a:	4b0f      	ldr	r3, [pc, #60]	; (cf48 <z_clock_driver_init+0x48>)
    p_reg->PRESCALER = val;
    cf0c:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    cf10:	601c      	str	r4, [r3, #0]
    cf12:	681b      	ldr	r3, [r3, #0]
    cf14:	4b0d      	ldr	r3, [pc, #52]	; (cf4c <z_clock_driver_init+0x4c>)
	nrf_rtc_prescaler_set(RTC, 0);
	event_clear();
	NVIC_ClearPendingIRQ(RTC_IRQn);
	int_enable();

	IRQ_CONNECT(RTC_IRQn, 1, rtc_nrf_isr, 0, 0);
    cf16:	2101      	movs	r1, #1
    cf18:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    p_reg->INTENSET = mask;
    cf1c:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    cf20:	4622      	mov	r2, r4
    cf22:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    cf26:	2015      	movs	r0, #21
    cf28:	f000 f8cc 	bl	d0c4 <z_arm_irq_priority_set>
	irq_enable(RTC_IRQn);
    cf2c:	2015      	movs	r0, #21
    cf2e:	f000 f8ab 	bl	d088 <arch_irq_enable>
    return (uint32_t)p_reg + task;
}

NRF_STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_reg, nrf_rtc_task_t task)
{
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    cf32:	2301      	movs	r3, #1
    cf34:	4a06      	ldr	r2, [pc, #24]	; (cf50 <z_clock_driver_init+0x50>)

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		set_comparator(counter() + CYC_PER_TICK);
	}

	z_nrf_clock_control_lf_on(mode);
    cf36:	2002      	movs	r0, #2
    cf38:	6013      	str	r3, [r2, #0]
    cf3a:	602b      	str	r3, [r5, #0]
    cf3c:	f7ff ff34 	bl	cda8 <z_nrf_clock_control_lf_on>

	return 0;
}
    cf40:	4620      	mov	r0, r4
    cf42:	bd38      	pop	{r3, r4, r5, pc}
    cf44:	40015000 	.word	0x40015000
    cf48:	40015140 	.word	0x40015140
    cf4c:	e000e100 	.word	0xe000e100
    cf50:	40015008 	.word	0x40015008

0000cf54 <z_clock_set_timeout>:

void z_clock_set_timeout(int32_t ticks, bool idle)
{
    cf54:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
     return p_reg->COUNTER;
    cf56:	4b2d      	ldr	r3, [pc, #180]	; (d00c <z_clock_set_timeout+0xb8>)

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return;
	}

	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    cf58:	4c2d      	ldr	r4, [pc, #180]	; (d010 <z_clock_set_timeout+0xbc>)
    cf5a:	f8d3 2504 	ldr.w	r2, [r3, #1284]	; 0x504
	ticks = MAX(MIN(ticks - 1, (int32_t)MAX_TICKS), 0);

	uint32_t unannounced = counter_sub(counter(), last_count);
    cf5e:	4b2d      	ldr	r3, [pc, #180]	; (d014 <z_clock_set_timeout+0xc0>)
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    cf60:	f1b0 3fff 	cmp.w	r0, #4294967295
    cf64:	bf08      	it	eq
    cf66:	4620      	moveq	r0, r4
	uint32_t unannounced = counter_sub(counter(), last_count);
    cf68:	6819      	ldr	r1, [r3, #0]
	return (a - b) & COUNTER_MAX;
    cf6a:	1a52      	subs	r2, r2, r1
    cf6c:	f022 437f 	bic.w	r3, r2, #4278190080	; 0xff000000
	/* If we haven't announced for more than half the 24-bit wrap
	 * duration, then force an announce to avoid loss of a wrap
	 * event.  This can happen if new timeouts keep being set
	 * before the existing one triggers the interrupt.
	 */
	if (unannounced >= COUNTER_HALF_SPAN) {
    cf70:	0212      	lsls	r2, r2, #8
    cf72:	d438      	bmi.n	cfe6 <z_clock_set_timeout+0x92>
	ticks = MAX(MIN(ticks - 1, (int32_t)MAX_TICKS), 0);
    cf74:	3801      	subs	r0, #1
    cf76:	ea20 70e0 	bic.w	r0, r0, r0, asr #31
    cf7a:	42a0      	cmp	r0, r4
    cf7c:	bfa8      	it	ge
    cf7e:	4620      	movge	r0, r4
	}

	/* Get the cycles from last_count to the tick boundary after
	 * the requested ticks have passed starting now.
	 */
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    cf80:	3301      	adds	r3, #1
    cf82:	4418      	add	r0, r3
	 */
	if (cyc > MAX_CYCLES) {
		cyc = MAX_CYCLES;
	}

	cyc += last_count;
    cf84:	42a0      	cmp	r0, r4
    cf86:	bf94      	ite	ls
    cf88:	180c      	addls	r4, r1, r0
    cf8a:	190c      	addhi	r4, r1, r4
    p_reg->INTENCLR = mask;
    cf8c:	f44f 3080 	mov.w	r0, #65536	; 0x10000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    cf90:	2600      	movs	r6, #0
    p_reg->INTENCLR = mask;
    cf92:	4a1e      	ldr	r2, [pc, #120]	; (d00c <z_clock_set_timeout+0xb8>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    cf94:	4d20      	ldr	r5, [pc, #128]	; (d018 <z_clock_set_timeout+0xc4>)
    p_reg->INTENCLR = mask;
    cf96:	f8c2 0308 	str.w	r0, [r2, #776]	; 0x308
     return p_reg->COUNTER;
    cf9a:	f8d2 1504 	ldr.w	r1, [r2, #1284]	; 0x504
    return p_reg->CC[ch];
    cf9e:	f8d2 3540 	ldr.w	r3, [r2, #1344]	; 0x540
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    cfa2:	602e      	str	r6, [r5, #0]
	return (a - b) & COUNTER_MAX;
    cfa4:	1a5b      	subs	r3, r3, r1
    cfa6:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    cfaa:	682f      	ldr	r7, [r5, #0]
	if (counter_sub(prev_val, now) == 1) {
    cfac:	2b01      	cmp	r3, #1
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
    cfae:	f021 477f 	bic.w	r7, r1, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    cfb2:	f8c2 7540 	str.w	r7, [r2, #1344]	; 0x540
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
    cfb6:	f8c2 0344 	str.w	r0, [r2, #836]	; 0x344
	if (counter_sub(prev_val, now) == 1) {
    cfba:	d104      	bne.n	cfc6 <z_clock_set_timeout+0x72>
	z_impl_k_busy_wait(usec_to_wait);
    cfbc:	200f      	movs	r0, #15
    cfbe:	f002 fefa 	bl	fdb6 <z_impl_k_busy_wait>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    cfc2:	602e      	str	r6, [r5, #0]
    cfc4:	682b      	ldr	r3, [r5, #0]
    cfc6:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
    cfca:	4b14      	ldr	r3, [pc, #80]	; (d01c <z_clock_set_timeout+0xc8>)
    cfcc:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
     return p_reg->COUNTER;
    cfd0:	4b0e      	ldr	r3, [pc, #56]	; (d00c <z_clock_set_timeout+0xb8>)
    cfd2:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    cfd6:	1a22      	subs	r2, r4, r0
    cfd8:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
	if (diff == 1) {
    cfdc:	2a01      	cmp	r2, #1
    cfde:	d104      	bne.n	cfea <z_clock_set_timeout+0x96>
		handle_next_cycle_case(t);
    cfe0:	f7ff ff64 	bl	ceac <handle_next_cycle_case>
    cfe4:	e00b      	b.n	cffe <z_clock_set_timeout+0xaa>
		ticks = 0;
    cfe6:	2000      	movs	r0, #0
    cfe8:	e7ca      	b.n	cf80 <z_clock_set_timeout+0x2c>
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
    cfea:	f024 427f 	bic.w	r2, r4, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    cfee:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
     return p_reg->COUNTER;
    cff2:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    cff6:	1a24      	subs	r4, r4, r0
    cff8:	3c02      	subs	r4, #2
	if (diff > MAX_CYCLES) {
    cffa:	0223      	lsls	r3, r4, #8
    cffc:	d4f0      	bmi.n	cfe0 <z_clock_set_timeout+0x8c>
    p_reg->INTENSET = mask;
    cffe:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    d002:	4b02      	ldr	r3, [pc, #8]	; (d00c <z_clock_set_timeout+0xb8>)
    d004:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
	set_protected_absolute_alarm(cyc);
}
    d008:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    d00a:	bf00      	nop
    d00c:	40015000 	.word	0x40015000
    d010:	007fffff 	.word	0x007fffff
    d014:	20010278 	.word	0x20010278
    d018:	40015140 	.word	0x40015140
    d01c:	e000e100 	.word	0xe000e100

0000d020 <z_clock_elapsed>:
	__asm__ volatile(
    d020:	f04f 0220 	mov.w	r2, #32
    d024:	f3ef 8311 	mrs	r3, BASEPRI
    d028:	f382 8811 	msr	BASEPRI, r2
    d02c:	f3bf 8f6f 	isb	sy
     return p_reg->COUNTER;
    d030:	4a06      	ldr	r2, [pc, #24]	; (d04c <z_clock_elapsed+0x2c>)
    d032:	f8d2 0504 	ldr.w	r0, [r2, #1284]	; 0x504
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return 0;
	}

	k_spinlock_key_t key = k_spin_lock(&lock);
	uint32_t ret = counter_sub(counter(), last_count) / CYC_PER_TICK;
    d036:	4a06      	ldr	r2, [pc, #24]	; (d050 <z_clock_elapsed+0x30>)
	return (a - b) & COUNTER_MAX;
    d038:	6812      	ldr	r2, [r2, #0]
    d03a:	1a80      	subs	r0, r0, r2
    d03c:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	__asm__ volatile(
    d040:	f383 8811 	msr	BASEPRI, r3
    d044:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&lock, key);
	return ret;
}
    d048:	4770      	bx	lr
    d04a:	bf00      	nop
    d04c:	40015000 	.word	0x40015000
    d050:	20010278 	.word	0x20010278

0000d054 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    d054:	4a09      	ldr	r2, [pc, #36]	; (d07c <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    d056:	490a      	ldr	r1, [pc, #40]	; (d080 <arch_swap+0x2c>)
	_current->arch.basepri = key;
    d058:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    d05a:	6809      	ldr	r1, [r1, #0]
	_current->arch.basepri = key;
    d05c:	6798      	str	r0, [r3, #120]	; 0x78
	_current->arch.swap_return_value = _k_neg_eagain;
    d05e:	67d9      	str	r1, [r3, #124]	; 0x7c

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    d060:	4908      	ldr	r1, [pc, #32]	; (d084 <arch_swap+0x30>)
    d062:	684b      	ldr	r3, [r1, #4]
    d064:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    d068:	604b      	str	r3, [r1, #4]
    d06a:	2300      	movs	r3, #0
    d06c:	f383 8811 	msr	BASEPRI, r3
    d070:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    d074:	6893      	ldr	r3, [r2, #8]
}
    d076:	6fd8      	ldr	r0, [r3, #124]	; 0x7c
    d078:	4770      	bx	lr
    d07a:	bf00      	nop
    d07c:	200102dc 	.word	0x200102dc
    d080:	00010208 	.word	0x00010208
    d084:	e000ed00 	.word	0xe000ed00

0000d088 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    d088:	b243      	sxtb	r3, r0
  if ((int32_t)(IRQn) >= 0)
    d08a:	2b00      	cmp	r3, #0
    d08c:	db08      	blt.n	d0a0 <arch_irq_enable+0x18>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    d08e:	2201      	movs	r2, #1
    d090:	f000 001f 	and.w	r0, r0, #31
    d094:	fa02 f000 	lsl.w	r0, r2, r0
    d098:	4a02      	ldr	r2, [pc, #8]	; (d0a4 <arch_irq_enable+0x1c>)
    d09a:	095b      	lsrs	r3, r3, #5
    d09c:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    d0a0:	4770      	bx	lr
    d0a2:	bf00      	nop
    d0a4:	e000e100 	.word	0xe000e100

0000d0a8 <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    d0a8:	4b05      	ldr	r3, [pc, #20]	; (d0c0 <arch_irq_is_enabled+0x18>)
    d0aa:	0942      	lsrs	r2, r0, #5
    d0ac:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    d0b0:	2301      	movs	r3, #1
    d0b2:	f000 001f 	and.w	r0, r0, #31
    d0b6:	fa03 f000 	lsl.w	r0, r3, r0
}
    d0ba:	4010      	ands	r0, r2
    d0bc:	4770      	bx	lr
    d0be:	bf00      	nop
    d0c0:	e000e100 	.word	0xe000e100

0000d0c4 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    d0c4:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    d0c6:	2b00      	cmp	r3, #0
	prio += _IRQ_PRIO_OFFSET;
    d0c8:	f101 0101 	add.w	r1, r1, #1
  {
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d0cc:	bfac      	ite	ge
    d0ce:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
  }
  else
  {
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d0d2:	4b06      	ldrlt	r3, [pc, #24]	; (d0ec <z_arm_irq_priority_set+0x28>)
    d0d4:	ea4f 1141 	mov.w	r1, r1, lsl #5
    d0d8:	b2c9      	uxtb	r1, r1
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d0da:	bfab      	itete	ge
    d0dc:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d0e0:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d0e4:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d0e8:	5419      	strblt	r1, [r3, r0]
}
    d0ea:	4770      	bx	lr
    d0ec:	e000ed14 	.word	0xe000ed14

0000d0f0 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    d0f0:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    d0f4:	9b00      	ldr	r3, [sp, #0]
	iframe->pc &= 0xfffffffe;
    d0f6:	490b      	ldr	r1, [pc, #44]	; (d124 <arch_new_thread+0x34>)
	iframe->a2 = (uint32_t)p1;
    d0f8:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->a3 = (uint32_t)p2;
    d0fc:	9b01      	ldr	r3, [sp, #4]
	iframe->pc &= 0xfffffffe;
    d0fe:	f021 0101 	bic.w	r1, r1, #1
	iframe->a3 = (uint32_t)p2;
    d102:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    d106:	9b02      	ldr	r3, [sp, #8]
	iframe->pc &= 0xfffffffe;
    d108:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->a4 = (uint32_t)p3;
    d10c:	f842 3c14 	str.w	r3, [r2, #-20]

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    d110:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    d114:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    d118:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    d11a:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    d11c:	6582      	str	r2, [r0, #88]	; 0x58
	thread->arch.basepri = 0;
    d11e:	6783      	str	r3, [r0, #120]	; 0x78
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    d120:	4770      	bx	lr
    d122:	bf00      	nop
    d124:	0000f521 	.word	0x0000f521

0000d128 <arch_switch_to_main_thread>:
#endif
}

void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
    d128:	4604      	mov	r4, r0
    d12a:	b508      	push	{r3, lr}
    d12c:	460e      	mov	r6, r1
    d12e:	4615      	mov	r5, r2
	z_arm_configure_static_mpu_regions();
    d130:	f000 fa04 	bl	d53c <z_arm_configure_static_mpu_regions>
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    d134:	4b08      	ldr	r3, [pc, #32]	; (d158 <arch_switch_to_main_thread+0x30>)
    d136:	609c      	str	r4, [r3, #8]
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  // without main extensions, the non-secure PSPLIM is RAZ/WI
  (void)ProcStackPtrLimit;
#else
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    d138:	6ea3      	ldr	r3, [r4, #104]	; 0x68
    d13a:	f383 880b 	msr	PSPLIM, r3

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    d13e:	4628      	mov	r0, r5
    d140:	f386 8809 	msr	PSP, r6
    d144:	2100      	movs	r1, #0
    d146:	b663      	cpsie	if
    d148:	f381 8811 	msr	BASEPRI, r1
    d14c:	f3bf 8f6f 	isb	sy
    d150:	2200      	movs	r2, #0
    d152:	2300      	movs	r3, #0
    d154:	f002 f9e4 	bl	f520 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    d158:	200102dc 	.word	0x200102dc

0000d15c <z_arm_prep_c>:
#else
#define VECTOR_ADDRESS CONFIG_SRAM_BASE_ADDRESS
#endif
static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    d15c:	4a0e      	ldr	r2, [pc, #56]	; (d198 <z_arm_prep_c+0x3c>)
 * This routine prepares for the execution of and runs C code.
 *
 * @return N/A
 */
void z_arm_prep_c(void)
{
    d15e:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    d160:	4b0e      	ldr	r3, [pc, #56]	; (d19c <z_arm_prep_c+0x40>)
    d162:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    d166:	609a      	str	r2, [r3, #8]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    d168:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    d16c:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    d170:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    d174:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    d178:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
  __ASM volatile ("MRS %0, control" : "=r" (result) );
    d17c:	f3ef 8314 	mrs	r3, CONTROL
	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
    d180:	f023 0304 	bic.w	r3, r3, #4
  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
    d184:	f383 8814 	msr	CONTROL, r3
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    d188:	f001 faca 	bl	e720 <z_bss_zero>
	z_data_copy();
    d18c:	f001 fad2 	bl	e734 <z_data_copy>
#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    d190:	f000 f99c 	bl	d4cc <z_arm_interrupt_init>
	z_cstart();
    d194:	f001 fb0c 	bl	e7b0 <z_cstart>
    d198:	0000c000 	.word	0x0000c000
    d19c:	e000ed00 	.word	0xe000ed00

0000d1a0 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_TRACING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    d1a0:	4913      	ldr	r1, [pc, #76]	; (d1f0 <z_arm_pendsv+0x50>)
    ldr r2, [r1, #_kernel_offset_to_current]
    d1a2:	688a      	ldr	r2, [r1, #8]

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    d1a4:	f04f 0038 	mov.w	r0, #56	; 0x38
    add r0, r2
    d1a8:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    d1aa:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    d1ae:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    d1b2:	2020      	movs	r0, #32
    msr BASEPRI, r0
    d1b4:	f380 8811 	msr	BASEPRI, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    d1b8:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    d1bc:	4f0d      	ldr	r7, [pc, #52]	; (d1f4 <z_arm_pendsv+0x54>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    d1be:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    d1c2:	6a4a      	ldr	r2, [r1, #36]	; 0x24

    str r2, [r1, #_kernel_offset_to_current]
    d1c4:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    d1c6:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    d1c8:	6f90      	ldr	r0, [r2, #120]	; 0x78
    movs r3, #0
    d1ca:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    d1cc:	6793      	str	r3, [r2, #120]	; 0x78
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    d1ce:	f380 8811 	msr	BASEPRI, r0
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    d1d2:	f102 0038 	add.w	r0, r2, #56	; 0x38
    ldmia r0, {v1-v8, ip}
    d1d6:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    d1da:	f38c 8809 	msr	PSP, ip
#endif

#ifdef CONFIG_BUILTIN_STACK_GUARD
    /* r2 contains k_thread */
    add r0, r2, #0
    d1de:	f102 0000 	add.w	r0, r2, #0
    push {r2, lr}
    d1e2:	b504      	push	{r2, lr}
    bl configure_builtin_stack_guard
    d1e4:	f002 fb22 	bl	f82c <configure_builtin_stack_guard>
    pop {r2, lr}
    d1e8:	e8bd 4004 	ldmia.w	sp!, {r2, lr}

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (_IntExit or z_arm_svc)
     */
    bx lr
    d1ec:	4770      	bx	lr
    d1ee:	0000      	.short	0x0000
    ldr r1, =_kernel
    d1f0:	200102dc 	.word	0x200102dc
    ldr v4, =_SCS_ICSR
    d1f4:	e000ed04 	.word	0xe000ed04

0000d1f8 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #0x4    /* did we come from thread mode ? */
    d1f8:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    d1fc:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    d1fe:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    d202:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    d206:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    d208:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    d20c:	2902      	cmp	r1, #2
    beq _oops
    d20e:	d0ff      	beq.n	d210 <_oops>

0000d210 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    d210:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    d212:	f002 fb11 	bl	f838 <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    d216:	bd01      	pop	{r0, pc}

0000d218 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    d218:	4901      	ldr	r1, [pc, #4]	; (d220 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    d21a:	2210      	movs	r2, #16
	str	r2, [r1]
    d21c:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    d21e:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    d220:	e000ed10 	.word	0xe000ed10

0000d224 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    d224:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    d226:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    d228:	f380 8811 	msr	BASEPRI, r0
	isb
    d22c:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    d230:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    d234:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    d236:	b662      	cpsie	i
	isb
    d238:	f3bf 8f6f 	isb	sy

	bx	lr
    d23c:	4770      	bx	lr
    d23e:	bf00      	nop

0000d240 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    d240:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    d242:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    d244:	f381 8811 	msr	BASEPRI, r1

	wfe
    d248:	bf20      	wfe

	msr	BASEPRI, r0
    d24a:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    d24e:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    d250:	4770      	bx	lr
    d252:	bf00      	nop

0000d254 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    d254:	bf30      	wfi
    b z_SysNmiOnReset
    d256:	f7ff bffd 	b.w	d254 <z_SysNmiOnReset>
    d25a:	bf00      	nop

0000d25c <_isr_wrapper>:
 * @return N/A
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    d25c:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    d25e:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    d260:	4a0b      	ldr	r2, [pc, #44]	; (d290 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    d262:	6a10      	ldr	r0, [r2, #32]
	cmp r0, #0
    d264:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_sys_power_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    d266:	bf1e      	ittt	ne
	movne	r1, #0
    d268:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    d26a:	6211      	strne	r1, [r2, #32]
		blne	z_sys_power_save_idle_exit
    d26c:	f002 fcef 	blne	fc4e <z_sys_power_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    d270:	b662      	cpsie	i
#endif

#endif /* CONFIG_SYS_POWER_MANAGEMENT */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    d272:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    d276:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    d27a:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	 * interface function.
	 */
	cpsie i
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    d27e:	4905      	ldr	r1, [pc, #20]	; (d294 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    d280:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    d282:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    d284:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    d286:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    d28a:	4903      	ldr	r1, [pc, #12]	; (d298 <_isr_wrapper+0x3c>)
	bx r1
    d28c:	4708      	bx	r1
    d28e:	0000      	.short	0x0000
	ldr r2, =_kernel
    d290:	200102dc 	.word	0x200102dc
	ldr r1, =_sw_isr_table
    d294:	0000feb4 	.word	0x0000feb4
	ldr r1, =z_arm_int_exit
    d298:	0000d2e1 	.word	0x0000d2e1

0000d29c <__start>:
 * search for a __start symbol instead, so create that alias here.
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_platform_init
    d29c:	f002 fa27 	bl	f6ee <z_platform_init>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    d2a0:	2020      	movs	r0, #32
    msr BASEPRI, r0
    d2a2:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    d2a6:	4808      	ldr	r0, [pc, #32]	; (d2c8 <__start+0x2c>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    d2a8:	f44f 6100 	mov.w	r1, #2048	; 0x800
    adds r0, r0, r1
    d2ac:	1840      	adds	r0, r0, r1
    msr PSP, r0
    d2ae:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    d2b2:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    d2b6:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    d2b8:	4308      	orrs	r0, r1
    msr CONTROL, r0
    d2ba:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    d2be:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    d2c2:	f7ff ff4b 	bl	d15c <z_arm_prep_c>
    d2c6:	0000      	.short	0x0000
    ldr r0, =z_interrupt_stacks
    d2c8:	20011468 	.word	0x20011468

0000d2cc <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    d2cc:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    d2d0:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    d2d4:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    d2d6:	4672      	mov	r2, lr
	bl z_arm_fault
    d2d8:	f000 f860 	bl	d39c <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    d2dc:	bd01      	pop	{r0, pc}
    d2de:	bf00      	nop

0000d2e0 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    d2e0:	4b04      	ldr	r3, [pc, #16]	; (d2f4 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    d2e2:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    d2e4:	6a58      	ldr	r0, [r3, #36]	; 0x24
	cmp r0, r1
    d2e6:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    d2e8:	d003      	beq.n	d2f2 <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    d2ea:	4903      	ldr	r1, [pc, #12]	; (d2f8 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    d2ec:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    d2f0:	600a      	str	r2, [r1, #0]

0000d2f2 <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    d2f2:	4770      	bx	lr
	ldr r3, =_kernel
    d2f4:	200102dc 	.word	0x200102dc
	ldr r1, =_SCS_ICSR
    d2f8:	e000ed04 	.word	0xe000ed04

0000d2fc <mem_manage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    d2fc:	4b0c      	ldr	r3, [pc, #48]	; (d330 <mem_manage_fault.isra.0+0x34>)
    d2fe:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error (context area might be"
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    d300:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    d302:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d304:	0792      	lsls	r2, r2, #30
    d306:	d508      	bpl.n	d31a <mem_manage_fault.isra.0+0x1e>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		mmfar = SCB->MMFAR;
    d308:	6b5a      	ldr	r2, [r3, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    d30a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d30c:	0612      	lsls	r2, r2, #24
    d30e:	d504      	bpl.n	d31a <mem_manage_fault.isra.0+0x1e>
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
			if (from_hard_fault) {
    d310:	b118      	cbz	r0, d31a <mem_manage_fault.isra.0+0x1e>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    d312:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d314:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    d318:	629a      	str	r2, [r3, #40]	; 0x28

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf);
    d31a:	2000      	movs	r0, #0
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    d31c:	4b04      	ldr	r3, [pc, #16]	; (d330 <mem_manage_fault.isra.0+0x34>)
    d31e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    d320:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_MSTKERR_Msk) {
    d322:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    d324:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d326:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    d32a:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf);
    d32c:	7008      	strb	r0, [r1, #0]

	return reason;
}
    d32e:	4770      	bx	lr
    d330:	e000ed00 	.word	0xe000ed00

0000d334 <bus_fault.isra.0>:
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    d334:	4b0d      	ldr	r3, [pc, #52]	; (d36c <bus_fault.isra.0+0x38>)
    d336:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error");
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    d338:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    d33a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d33c:	0592      	lsls	r2, r2, #22
    d33e:	d508      	bpl.n	d352 <bus_fault.isra.0+0x1e>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
    d340:	6b9a      	ldr	r2, [r3, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    d342:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d344:	0412      	lsls	r2, r2, #16
    d346:	d504      	bpl.n	d352 <bus_fault.isra.0+0x1e>
			PR_EXC("  BFAR Address: 0x%x", bfar);
			if (from_hard_fault) {
    d348:	b118      	cbz	r0, d352 <bus_fault.isra.0+0x1e>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    d34a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d34c:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    d350:	629a      	str	r2, [r3, #40]	; 0x28
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;

	*recoverable = memory_fault_recoverable(esf);
    d352:	2000      	movs	r0, #0
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    d354:	4b05      	ldr	r3, [pc, #20]	; (d36c <bus_fault.isra.0+0x38>)
    d356:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    d358:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d35a:	05d2      	lsls	r2, r2, #23
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    d35c:	bf58      	it	pl
    d35e:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    d360:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d362:	f442 427f 	orr.w	r2, r2, #65280	; 0xff00
    d366:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf);
    d368:	7008      	strb	r0, [r1, #0]

	return reason;
}
    d36a:	4770      	bx	lr
    d36c:	e000ed00 	.word	0xe000ed00

0000d370 <usage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    d370:	4b09      	ldr	r3, [pc, #36]	; (d398 <usage_fault.isra.0+0x28>)
    d372:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    d374:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unaligned memory access");
	}
#if defined(CONFIG_ARMV8_M_MAINLINE)
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    d376:	6a98      	ldr	r0, [r3, #40]	; 0x28
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    d378:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    d37a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    d37c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    d37e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    d380:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    d382:	f410 1080 	ands.w	r0, r0, #1048576	; 0x100000
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    d386:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    d38a:	ea6f 4212 	mvn.w	r2, r2, lsr #16

	return reason;
}
    d38e:	bf18      	it	ne
    d390:	2002      	movne	r0, #2
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    d392:	629a      	str	r2, [r3, #40]	; 0x28
}
    d394:	4770      	bx	lr
    d396:	bf00      	nop
    d398:	e000ed00 	.word	0xe000ed00

0000d39c <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    d39c:	b570      	push	{r4, r5, r6, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    d39e:	4b39      	ldr	r3, [pc, #228]	; (d484 <z_arm_fault+0xe8>)
{
    d3a0:	4606      	mov	r6, r0
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    d3a2:	685b      	ldr	r3, [r3, #4]
    d3a4:	2500      	movs	r5, #0
{
    d3a6:	b08a      	sub	sp, #40	; 0x28
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    d3a8:	f3c3 0308 	ubfx	r3, r3, #0, #9
    d3ac:	f385 8811 	msr	BASEPRI, r5
    d3b0:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    d3b4:	f002 407f 	and.w	r0, r2, #4278190080	; 0xff000000
    d3b8:	f1b0 4f7f 	cmp.w	r0, #4278190080	; 0xff000000
    d3bc:	d116      	bne.n	d3ec <z_arm_fault+0x50>
	if (exc_return & EXC_RETURN_EXCEPTION_SECURE_Secure) {
    d3be:	07d0      	lsls	r0, r2, #31
    d3c0:	d414      	bmi.n	d3ec <z_arm_fault+0x50>
	if (exc_return & EXC_RETURN_RETURN_STACK_Secure) {
    d3c2:	0654      	lsls	r4, r2, #25
    d3c4:	d403      	bmi.n	d3ce <z_arm_fault+0x32>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    d3c6:	0710      	lsls	r0, r2, #28
    d3c8:	d404      	bmi.n	d3d4 <z_arm_fault+0x38>
			*nested_exc = true;
    d3ca:	2501      	movs	r5, #1
    d3cc:	e004      	b.n	d3d8 <z_arm_fault+0x3c>
		if (exc_return & EXC_RETURN_SPSEL_PROCESS) {
    d3ce:	f012 0504 	ands.w	r5, r2, #4
    d3d2:	d001      	beq.n	d3d8 <z_arm_fault+0x3c>
			ptr_esf = (z_arch_esf_t *)psp;
    d3d4:	460e      	mov	r6, r1
	*nested_exc = false;
    d3d6:	2500      	movs	r5, #0
	*recoverable = false;
    d3d8:	2200      	movs	r2, #0
    d3da:	3b03      	subs	r3, #3
    d3dc:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
    d3e0:	2b03      	cmp	r3, #3
    d3e2:	d847      	bhi.n	d474 <z_arm_fault+0xd8>
    d3e4:	e8df f003 	tbb	[pc, r3]
    d3e8:	3b423e04 	.word	0x3b423e04
		return NULL;
    d3ec:	462e      	mov	r6, r5
    d3ee:	e7f3      	b.n	d3d8 <z_arm_fault+0x3c>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    d3f0:	4b24      	ldr	r3, [pc, #144]	; (d484 <z_arm_fault+0xe8>)
    d3f2:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    d3f4:	0792      	lsls	r2, r2, #30
    d3f6:	d43d      	bmi.n	d474 <z_arm_fault+0xd8>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    d3f8:	6adc      	ldr	r4, [r3, #44]	; 0x2c
    d3fa:	f014 4480 	ands.w	r4, r4, #1073741824	; 0x40000000
    d3fe:	d008      	beq.n	d412 <z_arm_fault+0x76>
		if (SCB_MMFSR != 0) {
    d400:	3328      	adds	r3, #40	; 0x28
    d402:	781b      	ldrb	r3, [r3, #0]
    d404:	b1eb      	cbz	r3, d442 <z_arm_fault+0xa6>
			reason = mem_manage_fault(esf, 1, recoverable);
    d406:	2001      	movs	r0, #1
    d408:	f10d 0107 	add.w	r1, sp, #7
		reason = mem_manage_fault(esf, 0, recoverable);
    d40c:	f7ff ff76 	bl	d2fc <mem_manage_fault.isra.0>
		reason = usage_fault(esf);
    d410:	4604      	mov	r4, r0
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    d412:	f89d 3007 	ldrb.w	r3, [sp, #7]
    d416:	b993      	cbnz	r3, d43e <z_arm_fault+0xa2>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    d418:	2220      	movs	r2, #32
    d41a:	4631      	mov	r1, r6
    d41c:	a802      	add	r0, sp, #8
    d41e:	f002 fa5b 	bl	f8d8 <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    d422:	9b09      	ldr	r3, [sp, #36]	; 0x24
    d424:	b345      	cbz	r5, d478 <z_arm_fault+0xdc>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    d426:	f3c3 0208 	ubfx	r2, r3, #0, #9
    d42a:	b922      	cbnz	r2, d436 <z_arm_fault+0x9a>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    d42c:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    d430:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    d434:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    d436:	4620      	mov	r0, r4
    d438:	a902      	add	r1, sp, #8
    d43a:	f002 f9fb 	bl	f834 <z_arm_fatal_error>
}
    d43e:	b00a      	add	sp, #40	; 0x28
    d440:	bd70      	pop	{r4, r5, r6, pc}
		} else if (SCB_BFSR != 0) {
    d442:	4b11      	ldr	r3, [pc, #68]	; (d488 <z_arm_fault+0xec>)
    d444:	781b      	ldrb	r3, [r3, #0]
    d446:	b12b      	cbz	r3, d454 <z_arm_fault+0xb8>
			reason = bus_fault(esf, 1, recoverable);
    d448:	2001      	movs	r0, #1
    d44a:	f10d 0107 	add.w	r1, sp, #7
		reason = bus_fault(esf, 0, recoverable);
    d44e:	f7ff ff71 	bl	d334 <bus_fault.isra.0>
    d452:	e7dd      	b.n	d410 <z_arm_fault+0x74>
		} else if (SCB_UFSR != 0) {
    d454:	4b0d      	ldr	r3, [pc, #52]	; (d48c <z_arm_fault+0xf0>)
    d456:	8818      	ldrh	r0, [r3, #0]
    d458:	b284      	uxth	r4, r0
    d45a:	2c00      	cmp	r4, #0
    d45c:	d0d9      	beq.n	d412 <z_arm_fault+0x76>
		reason = usage_fault(esf);
    d45e:	f7ff ff87 	bl	d370 <usage_fault.isra.0>
    d462:	e7d5      	b.n	d410 <z_arm_fault+0x74>
		reason = mem_manage_fault(esf, 0, recoverable);
    d464:	2000      	movs	r0, #0
    d466:	f10d 0107 	add.w	r1, sp, #7
    d46a:	e7cf      	b.n	d40c <z_arm_fault+0x70>
		reason = bus_fault(esf, 0, recoverable);
    d46c:	2000      	movs	r0, #0
    d46e:	f10d 0107 	add.w	r1, sp, #7
    d472:	e7ec      	b.n	d44e <z_arm_fault+0xb2>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    d474:	2400      	movs	r4, #0
    d476:	e7cc      	b.n	d412 <z_arm_fault+0x76>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    d478:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    d47c:	f023 0301 	bic.w	r3, r3, #1
    d480:	e7d8      	b.n	d434 <z_arm_fault+0x98>
    d482:	bf00      	nop
    d484:	e000ed00 	.word	0xe000ed00
    d488:	e000ed29 	.word	0xe000ed29
    d48c:	e000ed2a 	.word	0xe000ed2a

0000d490 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    d490:	4b04      	ldr	r3, [pc, #16]	; (d4a4 <z_arm_fault_init+0x14>)
    d492:	695a      	ldr	r2, [r3, #20]
    d494:	f042 0210 	orr.w	r2, r2, #16
    d498:	615a      	str	r2, [r3, #20]
	 *
	 * For Non-Secure Firmware this could allow the Non-Secure Main
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
    d49a:	695a      	ldr	r2, [r3, #20]
    d49c:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
    d4a0:	615a      	str	r2, [r3, #20]
#endif /* CONFIG_BUILTIN_STACK_GUARD */
}
    d4a2:	4770      	bx	lr
    d4a4:	e000ed00 	.word	0xe000ed00

0000d4a8 <sys_arch_reboot>:
  __ASM volatile ("dsb 0xF":::"memory");
    d4a8:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    d4ac:	4905      	ldr	r1, [pc, #20]	; (d4c4 <sys_arch_reboot+0x1c>)
    d4ae:	4b06      	ldr	r3, [pc, #24]	; (d4c8 <sys_arch_reboot+0x20>)
    d4b0:	68ca      	ldr	r2, [r1, #12]
    d4b2:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    d4b6:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    d4b8:	60cb      	str	r3, [r1, #12]
    d4ba:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    d4be:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    d4c0:	e7fd      	b.n	d4be <sys_arch_reboot+0x16>
    d4c2:	bf00      	nop
    d4c4:	e000ed00 	.word	0xe000ed00
    d4c8:	05fa0004 	.word	0x05fa0004

0000d4cc <z_arm_interrupt_init>:
 * @return N/A
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    d4cc:	2300      	movs	r3, #0
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d4ce:	2120      	movs	r1, #32
    d4d0:	4803      	ldr	r0, [pc, #12]	; (d4e0 <z_arm_interrupt_init+0x14>)
    d4d2:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    d4d4:	3301      	adds	r3, #1
    d4d6:	2b41      	cmp	r3, #65	; 0x41
    d4d8:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    d4dc:	d1f9      	bne.n	d4d2 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    d4de:	4770      	bx	lr
    d4e0:	e000e100 	.word	0xe000e100

0000d4e4 <z_impl_k_thread_abort>:
#include <kswap.h>
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
    d4e4:	b510      	push	{r4, lr}
    d4e6:	4604      	mov	r4, r0
	z_thread_single_abort(thread);
    d4e8:	f001 fba2 	bl	ec30 <z_thread_single_abort>

	if (_current == thread) {
    d4ec:	4b11      	ldr	r3, [pc, #68]	; (d534 <z_impl_k_thread_abort+0x50>)
    d4ee:	689b      	ldr	r3, [r3, #8]
    d4f0:	42a3      	cmp	r3, r4
    d4f2:	d107      	bne.n	d504 <z_impl_k_thread_abort+0x20>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    d4f4:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    d4f8:	b183      	cbz	r3, d51c <z_impl_k_thread_abort+0x38>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    d4fa:	4a0f      	ldr	r2, [pc, #60]	; (d538 <z_impl_k_thread_abort+0x54>)
    d4fc:	6853      	ldr	r3, [r2, #4]
    d4fe:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    d502:	6053      	str	r3, [r2, #4]
	__asm__ volatile(
    d504:	f04f 0320 	mov.w	r3, #32
    d508:	f3ef 8011 	mrs	r0, BASEPRI
    d50c:	f383 8811 	msr	BASEPRI, r3
    d510:	f3bf 8f6f 	isb	sy
		}
	}

	/* The abort handler might have altered the ready queue. */
	z_reschedule_unlocked();
}
    d514:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	(void) z_pend_curr_irqlock(arch_irq_lock(), wait_q, timeout);
}

static inline void z_reschedule_unlocked(void)
{
	(void) z_reschedule_irqlock(arch_irq_lock());
    d518:	f002 bb9b 	b.w	fc52 <z_reschedule_irqlock>
    d51c:	f04f 0320 	mov.w	r3, #32
    d520:	f3ef 8011 	mrs	r0, BASEPRI
    d524:	f383 8811 	msr	BASEPRI, r3
    d528:	f3bf 8f6f 	isb	sy

static inline int z_swap_irqlock(unsigned int key)
{
	int ret;
	z_check_stack_sentinel();
	ret = arch_swap(key);
    d52c:	f7ff fd92 	bl	d054 <arch_swap>
	return ret;
    d530:	e7e8      	b.n	d504 <z_impl_k_thread_abort+0x20>
    d532:	bf00      	nop
    d534:	200102dc 	.word	0x200102dc
    d538:	e000ed00 	.word	0xe000ed00

0000d53c <z_arm_configure_static_mpu_regions>:
 *
 * For some MPU architectures, such as the unmodified ARMv8-M MPU,
 * the function must execute with MPU enabled.
 */
void z_arm_configure_static_mpu_regions(void)
{
    d53c:	b510      	push	{r4, lr}
		.size = (uint32_t)&_nocache_ram_size,
		.attr = K_MEM_PARTITION_P_RW_U_NA_NOCACHE,
		};
#endif /* CONFIG_NOCACHE_MEMORY */
#if defined(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT)
		const struct k_mem_partition ramfunc_region =
    d53e:	4b0e      	ldr	r3, [pc, #56]	; (d578 <z_arm_configure_static_mpu_regions+0x3c>)
{
    d540:	b088      	sub	sp, #32
		const struct k_mem_partition ramfunc_region =
    d542:	9302      	str	r3, [sp, #8]
    d544:	4b0d      	ldr	r3, [pc, #52]	; (d57c <z_arm_configure_static_mpu_regions+0x40>)
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    d546:	4c0e      	ldr	r4, [pc, #56]	; (d580 <z_arm_configure_static_mpu_regions+0x44>)
		const struct k_mem_partition ramfunc_region =
    d548:	9303      	str	r3, [sp, #12]
    d54a:	4b0e      	ldr	r3, [pc, #56]	; (d584 <z_arm_configure_static_mpu_regions+0x48>)
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    d54c:	4a0e      	ldr	r2, [pc, #56]	; (d588 <z_arm_configure_static_mpu_regions+0x4c>)
		const struct k_mem_partition ramfunc_region =
    d54e:	9304      	str	r3, [sp, #16]
	const struct k_mem_partition *static_regions[] = {
    d550:	ab02      	add	r3, sp, #8
    d552:	9301      	str	r3, [sp, #4]
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    d554:	a801      	add	r0, sp, #4
    d556:	4623      	mov	r3, r4
    d558:	2101      	movs	r1, #1
    d55a:	f000 f907 	bl	d76c <arm_core_mpu_configure_static_mpu_regions>
	/* Define a constant array of k_mem_partition objects that holds the
	 * boundaries of the areas, inside which dynamic region programming
	 * is allowed. The information is passed to the underlying driver at
	 * initialization.
	 */
	const struct k_mem_partition dyn_region_areas[] = {
    d55e:	2300      	movs	r3, #0
    d560:	9307      	str	r3, [sp, #28]
		{
		.start = _MPU_DYNAMIC_REGIONS_AREA_START,
    d562:	4b0a      	ldr	r3, [pc, #40]	; (d58c <z_arm_configure_static_mpu_regions+0x50>)
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
		}
	};

	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    d564:	2101      	movs	r1, #1
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
    d566:	1ae4      	subs	r4, r4, r3
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    d568:	a805      	add	r0, sp, #20
	const struct k_mem_partition dyn_region_areas[] = {
    d56a:	9305      	str	r3, [sp, #20]
    d56c:	9406      	str	r4, [sp, #24]
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    d56e:	f000 f907 	bl	d780 <arm_core_mpu_mark_areas_for_dynamic_regions>
		ARRAY_SIZE(dyn_region_areas));
#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */
}
    d572:	b008      	add	sp, #32
    d574:	bd10      	pop	{r4, pc}
    d576:	bf00      	nop
    d578:	20010000 	.word	0x20010000
    d57c:	00000000 	.word	0x00000000
    d580:	20040000 	.word	0x20040000
    d584:	00010006 	.word	0x00010006
    d588:	20010000 	.word	0x20010000
    d58c:	20010100 	.word	0x20010100

0000d590 <region_init>:
 * Note:
 *   The caller must provide a valid region index.
 */
static void region_init(const uint32_t index,
	const struct arm_mpu_region *region_conf)
{
    d590:	b510      	push	{r4, lr}
	ARM_MPU_SetRegion(
		/* RNR */
		index,
		/* RBAR */
		(region_conf->base & MPU_RBAR_BASE_Msk)
    d592:	680b      	ldr	r3, [r1, #0]
		| (region_conf->attr.rbar &
    d594:	7a0c      	ldrb	r4, [r1, #8]
		(region_conf->base & MPU_RBAR_BASE_Msk)
    d596:	f023 021f 	bic.w	r2, r3, #31
		| (region_conf->attr.rbar &
    d59a:	f004 031f 	and.w	r3, r4, #31
    d59e:	431a      	orrs	r2, r3
			(MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)),
		/* RLAR */
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    d5a0:	68cb      	ldr	r3, [r1, #12]
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    d5a2:	0964      	lsrs	r4, r4, #5
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    d5a4:	f023 031f 	bic.w	r3, r3, #31
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/   
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
  mpu->RNR = rnr;
    d5a8:	4904      	ldr	r1, [pc, #16]	; (d5bc <region_init+0x2c>)
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    d5aa:	ea43 0344 	orr.w	r3, r3, r4, lsl #1
			& MPU_RLAR_AttrIndx_Msk)
		| MPU_RLAR_EN_Msk
    d5ae:	f043 0301 	orr.w	r3, r3, #1
    d5b2:	6088      	str	r0, [r1, #8]
  mpu->RBAR = rbar;
    d5b4:	60ca      	str	r2, [r1, #12]
  mpu->RLAR = rlar;
    d5b6:	610b      	str	r3, [r1, #16]
	);

	LOG_DBG("[%d] 0x%08x 0x%08x 0x%08x 0x%08x",
			index, region_conf->base, region_conf->attr.rbar,
			region_conf->attr.mair_idx, region_conf->attr.r_limit);
}
    d5b8:	bd10      	pop	{r4, pc}
    d5ba:	bf00      	nop
    d5bc:	e000ed90 	.word	0xe000ed90

0000d5c0 <mpu_configure_regions_and_partition.constprop.0>:
 * sanity check of the memory regions to be programmed.
 *
 * The function performs a full partition of the background memory
 * area, effectively, leaving no space in this area uncovered by MPU.
 */
static int mpu_configure_regions_and_partition(const struct k_mem_partition
    d5c0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    d5c4:	4607      	mov	r7, r0
    d5c6:	4688      	mov	r8, r1
    d5c8:	4614      	mov	r4, r2
	bool do_sanity_check)
{
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    d5ca:	2600      	movs	r6, #0
	MPU->RNR = index;
    d5cc:	4d4a      	ldr	r5, [pc, #296]	; (d6f8 <mpu_configure_regions_and_partition.constprop.0+0x138>)
static int mpu_configure_regions_and_partition(const struct k_mem_partition
    d5ce:	b085      	sub	sp, #20
	for (i = 0; i < regions_num; i++) {
    d5d0:	4546      	cmp	r6, r8
    d5d2:	da0b      	bge.n	d5ec <mpu_configure_regions_and_partition.constprop.0+0x2c>
		if (regions[i]->size == 0U) {
    d5d4:	f857 3026 	ldr.w	r3, [r7, r6, lsl #2]
    d5d8:	f8d3 9004 	ldr.w	r9, [r3, #4]
    d5dc:	f1b9 0f00 	cmp.w	r9, #0
    d5e0:	d03a      	beq.n	d658 <mpu_configure_regions_and_partition.constprop.0+0x98>
		&&
    d5e2:	f1b9 0f1f 	cmp.w	r9, #31
    d5e6:	d805      	bhi.n	d5f4 <mpu_configure_regions_and_partition.constprop.0+0x34>

			reg_index =
				mpu_configure_region(reg_index, regions[i]);

			if (reg_index == -EINVAL) {
				return reg_index;
    d5e8:	f06f 0415 	mvn.w	r4, #21
			reg_index++;
		}
	}

	return reg_index;
}
    d5ec:	4620      	mov	r0, r4
    d5ee:	b005      	add	sp, #20
    d5f0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		&&
    d5f4:	f019 0f1f 	tst.w	r9, #31
    d5f8:	d1f6      	bne.n	d5e8 <mpu_configure_regions_and_partition.constprop.0+0x28>
		((part->start &
    d5fa:	f8d3 a000 	ldr.w	sl, [r3]
		&&
    d5fe:	f01a 0f1f 	tst.w	sl, #31
    d602:	d1f1      	bne.n	d5e8 <mpu_configure_regions_and_partition.constprop.0+0x28>
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    d604:	4650      	mov	r0, sl
    d606:	f002 f942 	bl	f88e <arm_cmse_mpu_region_get>
    d60a:	4683      	mov	fp, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    d60c:	eb09 000a 	add.w	r0, r9, sl
    d610:	3801      	subs	r0, #1
    d612:	f002 f93c 	bl	f88e <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    d616:	4583      	cmp	fp, r0
    d618:	d1e6      	bne.n	d5e8 <mpu_configure_regions_and_partition.constprop.0+0x28>
		if ((u_reg_index == -EINVAL) ||
    d61a:	f11b 0f16 	cmn.w	fp, #22
    d61e:	d0e3      	beq.n	d5e8 <mpu_configure_regions_and_partition.constprop.0+0x28>
			(u_reg_index > (reg_index - 1))) {
    d620:	1e63      	subs	r3, r4, #1
		if ((u_reg_index == -EINVAL) ||
    d622:	455b      	cmp	r3, fp
    d624:	dbe0      	blt.n	d5e8 <mpu_configure_regions_and_partition.constprop.0+0x28>
	MPU->RNR = index;
    d626:	f8c5 b008 	str.w	fp, [r5, #8]
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
    d62a:	68e8      	ldr	r0, [r5, #12]
	MPU->RNR = index;
    d62c:	f8c5 b008 	str.w	fp, [r5, #8]
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    d630:	692b      	ldr	r3, [r5, #16]
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
    d632:	f857 1026 	ldr.w	r1, [r7, r6, lsl #2]
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
    d636:	f020 001f 	bic.w	r0, r0, #31
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    d63a:	f043 0a1f 	orr.w	sl, r3, #31
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
    d63e:	e9d1 3200 	ldrd	r3, r2, [r1]
    d642:	441a      	add	r2, r3
		if ((regions[i]->start == u_reg_base) &&
    d644:	4298      	cmp	r0, r3
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
    d646:	f102 39ff 	add.w	r9, r2, #4294967295
		if ((regions[i]->start == u_reg_base) &&
    d64a:	d118      	bne.n	d67e <mpu_configure_regions_and_partition.constprop.0+0xbe>
    d64c:	45ca      	cmp	sl, r9
    d64e:	d105      	bne.n	d65c <mpu_configure_regions_and_partition.constprop.0+0x9c>
			mpu_configure_region(u_reg_index, regions[i]);
    d650:	fa5f f08b 	uxtb.w	r0, fp
    d654:	f002 f8fb 	bl	f84e <mpu_configure_region>
	for (i = 0; i < regions_num; i++) {
    d658:	3601      	adds	r6, #1
    d65a:	e7b9      	b.n	d5d0 <mpu_configure_regions_and_partition.constprop.0+0x10>
	MPU->RNR = index;
    d65c:	f8c5 b008 	str.w	fp, [r5, #8]
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    d660:	68eb      	ldr	r3, [r5, #12]
		| (base & MPU_RBAR_BASE_Msk);
    d662:	f022 021f 	bic.w	r2, r2, #31
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    d666:	f003 031f 	and.w	r3, r3, #31
		| (base & MPU_RBAR_BASE_Msk);
    d66a:	431a      	orrs	r2, r3
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    d66c:	60ea      	str	r2, [r5, #12]
				mpu_configure_region(reg_index, regions[i]);
    d66e:	b2e0      	uxtb	r0, r4
				mpu_configure_region(reg_index, regions[i]);
    d670:	f002 f8ed 	bl	f84e <mpu_configure_region>
			if (reg_index == -EINVAL) {
    d674:	f110 0f16 	cmn.w	r0, #22
    d678:	d0b6      	beq.n	d5e8 <mpu_configure_regions_and_partition.constprop.0+0x28>
			reg_index++;
    d67a:	1c44      	adds	r4, r0, #1
    d67c:	e7ec      	b.n	d658 <mpu_configure_regions_and_partition.constprop.0+0x98>
	MPU->RNR = index;
    d67e:	f8c5 b008 	str.w	fp, [r5, #8]
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    d682:	692a      	ldr	r2, [r5, #16]
    d684:	3b01      	subs	r3, #1
    d686:	f023 031f 	bic.w	r3, r3, #31
    d68a:	f002 021f 	and.w	r2, r2, #31
		| (limit & MPU_RLAR_LIMIT_Msk);
    d68e:	4313      	orrs	r3, r2
		} else if (reg_last == u_reg_last) {
    d690:	45ca      	cmp	sl, r9
    d692:	b2e0      	uxtb	r0, r4
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    d694:	612b      	str	r3, [r5, #16]
		} else if (reg_last == u_reg_last) {
    d696:	d0eb      	beq.n	d670 <mpu_configure_regions_and_partition.constprop.0+0xb0>
				mpu_configure_region(reg_index, regions[i]);
    d698:	f002 f8d9 	bl	f84e <mpu_configure_region>
			if (reg_index == -EINVAL) {
    d69c:	f110 0f16 	cmn.w	r0, #22
    d6a0:	d0a2      	beq.n	d5e8 <mpu_configure_regions_and_partition.constprop.0+0x28>
	MPU->RNR = index;
    d6a2:	f8c5 b008 	str.w	fp, [r5, #8]
	attr->rbar = MPU->RBAR &
    d6a6:	68ea      	ldr	r2, [r5, #12]
    d6a8:	f89d 3008 	ldrb.w	r3, [sp, #8]
			REGION_LIMIT_ADDR((regions[i]->start +
    d6ac:	f10a 3aff 	add.w	sl, sl, #4294967295
	attr->rbar = MPU->RBAR &
    d6b0:	f362 0304 	bfi	r3, r2, #0, #5
    d6b4:	f88d 3008 	strb.w	r3, [sp, #8]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    d6b8:	692b      	ldr	r3, [r5, #16]
    d6ba:	f89d 2008 	ldrb.w	r2, [sp, #8]
    d6be:	085b      	lsrs	r3, r3, #1
    d6c0:	f363 1247 	bfi	r2, r3, #5, #3
			fill_region.base = regions[i]->start +
    d6c4:	f857 3026 	ldr.w	r3, [r7, r6, lsl #2]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    d6c8:	f88d 2008 	strb.w	r2, [sp, #8]
			fill_region.base = regions[i]->start +
    d6cc:	e9d3 1300 	ldrd	r1, r3, [r3]
    d6d0:	440b      	add	r3, r1
    d6d2:	9300      	str	r3, [sp, #0]
			REGION_LIMIT_ADDR((regions[i]->start +
    d6d4:	f023 031f 	bic.w	r3, r3, #31
			reg_index++;
    d6d8:	3001      	adds	r0, #1
			REGION_LIMIT_ADDR((regions[i]->start +
    d6da:	4453      	add	r3, sl
    d6dc:	eba3 0309 	sub.w	r3, r3, r9
    d6e0:	b2c0      	uxtb	r0, r0
    d6e2:	f023 031f 	bic.w	r3, r3, #31

static int region_allocate_and_init(const uint8_t index,
	const struct arm_mpu_region *region_conf)
{
	/* Attempt to allocate new region index. */
	if (index > (get_num_regions() - 1)) {
    d6e6:	280f      	cmp	r0, #15
			fill_region.attr.r_limit =
    d6e8:	9303      	str	r3, [sp, #12]
    d6ea:	f63f af7d 	bhi.w	d5e8 <mpu_configure_regions_and_partition.constprop.0+0x28>
	}

	LOG_DBG("Program MPU region at index 0x%x", index);

	/* Program region */
	region_init(index, region_conf);
    d6ee:	4669      	mov	r1, sp
    d6f0:	f7ff ff4e 	bl	d590 <region_init>
    d6f4:	e7c1      	b.n	d67a <mpu_configure_regions_and_partition.constprop.0+0xba>
    d6f6:	bf00      	nop
    d6f8:	e000ed90 	.word	0xe000ed90

0000d6fc <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    d6fc:	2205      	movs	r2, #5
    d6fe:	4b03      	ldr	r3, [pc, #12]	; (d70c <arm_core_mpu_enable+0x10>)
    d700:	605a      	str	r2, [r3, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    d702:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    d706:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    d70a:	4770      	bx	lr
    d70c:	e000ed90 	.word	0xe000ed90

0000d710 <arm_core_mpu_disable>:
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
__STATIC_FORCEINLINE void __DMB(void)
{
  __ASM volatile ("dmb 0xF":::"memory");
    d710:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    d714:	2200      	movs	r2, #0
    d716:	4b01      	ldr	r3, [pc, #4]	; (d71c <arm_core_mpu_disable+0xc>)
    d718:	605a      	str	r2, [r3, #4]
}
    d71a:	4770      	bx	lr
    d71c:	e000ed90 	.word	0xe000ed90

0000d720 <arm_mpu_init>:
 *
 * This function provides the default configuration mechanism for the Memory
 * Protection Unit (MPU).
 */
static int arm_mpu_init(const struct device *arg)
{
    d720:	b538      	push	{r3, r4, r5, lr}
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    d722:	4c0e      	ldr	r4, [pc, #56]	; (d75c <arm_mpu_init+0x3c>)
    d724:	6825      	ldr	r5, [r4, #0]
    d726:	2d10      	cmp	r5, #16
    d728:	d814      	bhi.n	d754 <arm_mpu_init+0x34>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    d72a:	f7ff fff1 	bl	d710 <arm_core_mpu_disable>

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    d72e:	2000      	movs	r0, #0
	MPU->MAIR0 =
    d730:	4b0b      	ldr	r3, [pc, #44]	; (d760 <arm_mpu_init+0x40>)
    d732:	4a0c      	ldr	r2, [pc, #48]	; (d764 <arm_mpu_init+0x44>)
    d734:	631a      	str	r2, [r3, #48]	; 0x30
    d736:	4285      	cmp	r5, r0
    d738:	d105      	bne.n	d746 <arm_mpu_init+0x26>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    d73a:	4b0b      	ldr	r3, [pc, #44]	; (d768 <arm_mpu_init+0x48>)
    d73c:	701d      	strb	r5, [r3, #0]


	arm_core_mpu_enable();
    d73e:	f7ff ffdd 	bl	d6fc <arm_core_mpu_enable>
	__ASSERT(
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */
	return 0;
    d742:	2000      	movs	r0, #0
}
    d744:	bd38      	pop	{r3, r4, r5, pc}
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
    d746:	6861      	ldr	r1, [r4, #4]
    d748:	eb01 1100 	add.w	r1, r1, r0, lsl #4
    d74c:	f7ff ff20 	bl	d590 <region_init>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    d750:	3001      	adds	r0, #1
    d752:	e7f0      	b.n	d736 <arm_mpu_init+0x16>
		return -1;
    d754:	f04f 30ff 	mov.w	r0, #4294967295
    d758:	e7f4      	b.n	d744 <arm_mpu_init+0x24>
    d75a:	bf00      	nop
    d75c:	00010154 	.word	0x00010154
    d760:	e000ed90 	.word	0xe000ed90
    d764:	0044ffaa 	.word	0x0044ffaa
    d768:	2001031e 	.word	0x2001031e

0000d76c <arm_core_mpu_configure_static_mpu_regions>:
{
    d76c:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct k_mem_partition
	*static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    d76e:	4c03      	ldr	r4, [pc, #12]	; (d77c <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * given boundaries.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions_and_partition(static_regions,
    d770:	7822      	ldrb	r2, [r4, #0]
    d772:	f7ff ff25 	bl	d5c0 <mpu_configure_regions_and_partition.constprop.0>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    d776:	7020      	strb	r0, [r4, #0]
}
    d778:	bd10      	pop	{r4, pc}
    d77a:	bf00      	nop
    d77c:	2001031e 	.word	0x2001031e

0000d780 <arm_core_mpu_mark_areas_for_dynamic_regions>:
{
    d780:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    d784:	4d26      	ldr	r5, [pc, #152]	; (d820 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa0>)
    d786:	468a      	mov	sl, r1
{
	/* In ARMv8-M architecture we need to store the index values
	 * and the default configuration of the MPU regions, inside
	 * which dynamic memory regions may be programmed at run-time.
	 */
	for (int i = 0; i < dyn_region_areas_num; i++) {
    d788:	4606      	mov	r6, r0
    d78a:	f04f 0800 	mov.w	r8, #0
    d78e:	46ab      	mov	fp, r5
	MPU->RNR = index;
    d790:	4f24      	ldr	r7, [pc, #144]	; (d824 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa4>)
	for (int i = 0; i < dyn_region_areas_num; i++) {
    d792:	45d0      	cmp	r8, sl
    d794:	da1b      	bge.n	d7ce <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
		if (dyn_region_areas[i].size == 0U) {
    d796:	f8d6 9004 	ldr.w	r9, [r6, #4]
    d79a:	f1b9 0f00 	cmp.w	r9, #0
    d79e:	d039      	beq.n	d814 <arm_core_mpu_mark_areas_for_dynamic_regions+0x94>
		}
		/* Non-empty area */

		/* Retrieve HW MPU region index */
		dyn_reg_info[i].index =
			get_region_index(dyn_region_areas[i].start,
    d7a0:	6831      	ldr	r1, [r6, #0]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    d7a2:	4608      	mov	r0, r1
    d7a4:	9101      	str	r1, [sp, #4]
    d7a6:	f002 f872 	bl	f88e <arm_cmse_mpu_region_get>
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    d7aa:	9901      	ldr	r1, [sp, #4]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    d7ac:	4604      	mov	r4, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    d7ae:	eb09 0001 	add.w	r0, r9, r1
    d7b2:	3801      	subs	r0, #1
    d7b4:	f002 f86b 	bl	f88e <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    d7b8:	4284      	cmp	r4, r0
    d7ba:	f04f 0214 	mov.w	r2, #20
    d7be:	4b1a      	ldr	r3, [pc, #104]	; (d828 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa8>)
    d7c0:	d008      	beq.n	d7d4 <arm_core_mpu_mark_areas_for_dynamic_regions+0x54>
		dyn_reg_info[i].index =
    d7c2:	f06f 0315 	mvn.w	r3, #21
    d7c6:	fb02 f808 	mul.w	r8, r2, r8
    d7ca:	f84b 3008 	str.w	r3, [fp, r8]
}
    d7ce:	b003      	add	sp, #12
    d7d0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
					dyn_region_areas[i].size);

		if (dyn_reg_info[i].index == -EINVAL) {
    d7d4:	f114 0f16 	cmn.w	r4, #22
		dyn_reg_info[i].index =
    d7d8:	602c      	str	r4, [r5, #0]
		if (dyn_reg_info[i].index == -EINVAL) {
    d7da:	d0f8      	beq.n	d7ce <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>

			return -EINVAL;
		}

		if (dyn_reg_info[i].index >= static_regions_num) {
    d7dc:	7819      	ldrb	r1, [r3, #0]
    d7de:	42a1      	cmp	r1, r4
    d7e0:	ddf5      	ble.n	d7ce <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
	attr->rbar = MPU->RBAR &
    d7e2:	fb02 b008 	mla	r0, r2, r8, fp
	MPU->RNR = index;
    d7e6:	60bc      	str	r4, [r7, #8]
	MPU->RNR = index;
    d7e8:	60bc      	str	r4, [r7, #8]
	attr->rbar = MPU->RBAR &
    d7ea:	68fc      	ldr	r4, [r7, #12]
    d7ec:	f100 0108 	add.w	r1, r0, #8
    d7f0:	7b00      	ldrb	r0, [r0, #12]
    d7f2:	f364 0004 	bfi	r0, r4, #0, #5
    d7f6:	7108      	strb	r0, [r1, #4]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    d7f8:	6938      	ldr	r0, [r7, #16]
    d7fa:	790c      	ldrb	r4, [r1, #4]
    d7fc:	0840      	lsrs	r0, r0, #1
    d7fe:	f360 1447 	bfi	r4, r0, #5, #3
    d802:	710c      	strb	r4, [r1, #4]
	region_conf->base = (MPU->RBAR & MPU_RBAR_BASE_Msk);
    d804:	68f9      	ldr	r1, [r7, #12]
    d806:	f021 011f 	bic.w	r1, r1, #31
    d80a:	6069      	str	r1, [r5, #4]
	region_conf->attr.r_limit = MPU->RLAR & MPU_RLAR_LIMIT_Msk;
    d80c:	6939      	ldr	r1, [r7, #16]
    d80e:	f021 011f 	bic.w	r1, r1, #31
    d812:	6129      	str	r1, [r5, #16]
	for (int i = 0; i < dyn_region_areas_num; i++) {
    d814:	f108 0801 	add.w	r8, r8, #1
    d818:	3514      	adds	r5, #20
    d81a:	360c      	adds	r6, #12
    d81c:	e7b9      	b.n	d792 <arm_core_mpu_mark_areas_for_dynamic_regions+0x12>
    d81e:	bf00      	nop
    d820:	2001027c 	.word	0x2001027c
    d824:	e000ed90 	.word	0xe000ed90
    d828:	2001031e 	.word	0x2001031e

0000d82c <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
    d82c:	4b01      	ldr	r3, [pc, #4]	; (d834 <__stdout_hook_install+0x8>)
    d82e:	6018      	str	r0, [r3, #0]
}
    d830:	4770      	bx	lr
    d832:	bf00      	nop
    d834:	20010004 	.word	0x20010004

0000d838 <nrf_gpio_cfg_sense_set>:
}

NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;
    d838:	f000 021f 	and.w	r2, r0, #31
    d83c:	4805      	ldr	r0, [pc, #20]	; (d854 <nrf_gpio_cfg_sense_set+0x1c>)
    d83e:	eb00 0082 	add.w	r0, r0, r2, lsl #2
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    d842:	f8d0 3200 	ldr.w	r3, [r0, #512]	; 0x200
    d846:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    d84a:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
    d84e:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
}
    d852:	4770      	bx	lr
    d854:	40842500 	.word	0x40842500

0000d858 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    d858:	b508      	push	{r3, lr}
	static bool gpio_initialized;

	if (!gpio_initialized) {
    d85a:	4b09      	ldr	r3, [pc, #36]	; (d880 <gpio_nrfx_init+0x28>)
    d85c:	781a      	ldrb	r2, [r3, #0]
    d85e:	b96a      	cbnz	r2, d87c <gpio_nrfx_init+0x24>
		gpio_initialized = true;
    d860:	2101      	movs	r1, #1
		IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    d862:	2031      	movs	r0, #49	; 0x31
		gpio_initialized = true;
    d864:	7019      	strb	r1, [r3, #0]
		IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    d866:	2105      	movs	r1, #5
    d868:	f7ff fc2c 	bl	d0c4 <z_arm_irq_priority_set>
			    gpiote_event_handler, NULL, 0);

		irq_enable(DT_IRQN(GPIOTE_NODE));
    d86c:	2031      	movs	r0, #49	; 0x31
    d86e:	f7ff fc0b 	bl	d088 <arch_irq_enable>
    return ((uint32_t)p_reg + event);
}

NRF_STATIC_INLINE void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask)
{
    p_reg->INTENSET = mask;
    d872:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    d876:	4b03      	ldr	r3, [pc, #12]	; (d884 <gpio_nrfx_init+0x2c>)
    d878:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
		nrf_gpiote_int_enable(NRF_GPIOTE, NRF_GPIOTE_INT_PORT_MASK);
	}

	return 0;
}
    d87c:	2000      	movs	r0, #0
    d87e:	bd08      	pop	{r3, pc}
    d880:	2001031f 	.word	0x2001031f
    d884:	40031000 	.word	0x40031000

0000d888 <gpio_nrfx_config>:
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    d888:	4b28      	ldr	r3, [pc, #160]	; (d92c <gpio_nrfx_config+0xa4>)
{
    d88a:	b570      	push	{r4, r5, r6, lr}
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    d88c:	6846      	ldr	r6, [r0, #4]
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    d88e:	4828      	ldr	r0, [pc, #160]	; (d930 <gpio_nrfx_config+0xa8>)
    d890:	4013      	ands	r3, r2
    d892:	4283      	cmp	r3, r0
    d894:	d03b      	beq.n	d90e <gpio_nrfx_config+0x86>
    d896:	d80d      	bhi.n	d8b4 <gpio_nrfx_config+0x2c>
    d898:	2b06      	cmp	r3, #6
    d89a:	d015      	beq.n	d8c8 <gpio_nrfx_config+0x40>
    d89c:	d805      	bhi.n	d8aa <gpio_nrfx_config+0x22>
    d89e:	b19b      	cbz	r3, d8c8 <gpio_nrfx_config+0x40>
    d8a0:	2b02      	cmp	r3, #2
    d8a2:	d036      	beq.n	d912 <gpio_nrfx_config+0x8a>
    d8a4:	f06f 0015 	mvn.w	r0, #21
    d8a8:	e030      	b.n	d90c <gpio_nrfx_config+0x84>
    d8aa:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    d8ae:	d1f9      	bne.n	d8a4 <gpio_nrfx_config+0x1c>
		drive = NRF_GPIO_PIN_H0S1;
    d8b0:	2301      	movs	r3, #1
    d8b2:	e009      	b.n	d8c8 <gpio_nrfx_config+0x40>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    d8b4:	481f      	ldr	r0, [pc, #124]	; (d934 <gpio_nrfx_config+0xac>)
    d8b6:	4283      	cmp	r3, r0
    d8b8:	d02d      	beq.n	d916 <gpio_nrfx_config+0x8e>
    d8ba:	f5b3 0fa0 	cmp.w	r3, #5242880	; 0x500000
    d8be:	d02c      	beq.n	d91a <gpio_nrfx_config+0x92>
    d8c0:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
    d8c4:	d1ee      	bne.n	d8a4 <gpio_nrfx_config+0x1c>
		drive = NRF_GPIO_PIN_S0H1;
    d8c6:	2302      	movs	r3, #2
	if ((flags & GPIO_PULL_UP) != 0) {
    d8c8:	06d0      	lsls	r0, r2, #27
		pull = NRF_GPIO_PIN_PULLUP;
    d8ca:	bf4c      	ite	mi
    d8cc:	2503      	movmi	r5, #3
		pull = NRF_GPIO_PIN_NOPULL;
    d8ce:	f3c2 1540 	ubfxpl	r5, r2, #5, #1
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
    d8d2:	f482 7480 	eor.w	r4, r2, #256	; 0x100
	if ((flags & GPIO_OUTPUT) != 0) {
    d8d6:	f412 7f00 	tst.w	r2, #512	; 0x200
	dir = ((flags & GPIO_OUTPUT) != 0)
    d8da:	f3c2 2040 	ubfx	r0, r2, #9, #1
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
    d8de:	f3c4 2400 	ubfx	r4, r4, #8, #1
	if ((flags & GPIO_OUTPUT) != 0) {
    d8e2:	d006      	beq.n	d8f2 <gpio_nrfx_config+0x6a>
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
    d8e4:	f412 6f00 	tst.w	r2, #2048	; 0x800
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    d8e8:	6876      	ldr	r6, [r6, #4]
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
    d8ea:	d018      	beq.n	d91e <gpio_nrfx_config+0x96>
			nrf_gpio_port_out_set(reg, BIT(pin));
    d8ec:	2201      	movs	r2, #1
    d8ee:	408a      	lsls	r2, r1
    p_reg->OUTSET = set_mask;
    d8f0:	60b2      	str	r2, [r6, #8]
                               | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
    d8f2:	ea40 0244 	orr.w	r2, r0, r4, lsl #1
	return 0;
    d8f6:	2000      	movs	r0, #0
    d8f8:	ea42 2303 	orr.w	r3, r2, r3, lsl #8
    *p_pin = pin_number & 0x1F;
    d8fc:	f001 011f 	and.w	r1, r1, #31
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    d900:	4a0d      	ldr	r2, [pc, #52]	; (d938 <gpio_nrfx_config+0xb0>)
                               | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
    d902:	ea43 0385 	orr.w	r3, r3, r5, lsl #2
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    d906:	3180      	adds	r1, #128	; 0x80
    d908:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
}
    d90c:	bd70      	pop	{r4, r5, r6, pc}
		drive = NRF_GPIO_PIN_H0D1;
    d90e:	2307      	movs	r3, #7
    d910:	e7da      	b.n	d8c8 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_D0S1;
    d912:	2304      	movs	r3, #4
    d914:	e7d8      	b.n	d8c8 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_D0H1;
    d916:	2305      	movs	r3, #5
    d918:	e7d6      	b.n	d8c8 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_H0H1;
    d91a:	2303      	movs	r3, #3
    d91c:	e7d4      	b.n	d8c8 <gpio_nrfx_config+0x40>
		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
    d91e:	0552      	lsls	r2, r2, #21
			nrf_gpio_port_out_clear(reg, BIT(pin));
    d920:	bf42      	ittt	mi
    d922:	2201      	movmi	r2, #1
    d924:	408a      	lslmi	r2, r1
    p_reg->OUTCLR = clr_mask;
    d926:	60f2      	strmi	r2, [r6, #12]
}
    d928:	e7e3      	b.n	d8f2 <gpio_nrfx_config+0x6a>
    d92a:	bf00      	nop
    d92c:	00f00006 	.word	0x00f00006
    d930:	00100006 	.word	0x00100006
    d934:	00400002 	.word	0x00400002
    d938:	40842500 	.word	0x40842500

0000d93c <gpio_nrfx_pin_interrupt_configure>:
{
    d93c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    d940:	460d      	mov	r5, r1
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    d942:	6841      	ldr	r1, [r0, #4]
	struct gpio_nrfx_data *data = get_port_data(port);
    d944:	f8d0 800c 	ldr.w	r8, [r0, #12]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    d948:	7a08      	ldrb	r0, [r1, #8]
    d94a:	f005 071f 	and.w	r7, r5, #31
	if ((mode == GPIO_INT_MODE_EDGE) &&
    d94e:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    d952:	ea47 1740 	orr.w	r7, r7, r0, lsl #5
    d956:	d10a      	bne.n	d96e <gpio_nrfx_pin_interrupt_configure+0x32>
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    d958:	486e      	ldr	r0, [pc, #440]	; (db14 <gpio_nrfx_pin_interrupt_configure+0x1d8>)
    *p_pin = pin_number & 0x1F;
    d95a:	f007 011f 	and.w	r1, r7, #31
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    d95e:	3180      	adds	r1, #128	; 0x80
    d960:	f850 1021 	ldr.w	r1, [r0, r1, lsl #2]
    d964:	07c8      	lsls	r0, r1, #31
    d966:	d508      	bpl.n	d97a <gpio_nrfx_pin_interrupt_configure+0x3e>
		return -ENOTSUP;
    d968:	f06f 0022 	mvn.w	r0, #34	; 0x22
    d96c:	e0c2      	b.n	daf4 <gpio_nrfx_pin_interrupt_configure+0x1b8>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    d96e:	f5b2 5f00 	cmp.w	r2, #8192	; 0x2000
    d972:	f8d8 100c 	ldr.w	r1, [r8, #12]
    d976:	f000 80ae 	beq.w	dad6 <gpio_nrfx_pin_interrupt_configure+0x19a>
    d97a:	2101      	movs	r1, #1
    d97c:	f8d8 000c 	ldr.w	r0, [r8, #12]
    d980:	40a9      	lsls	r1, r5
    d982:	4301      	orrs	r1, r0
    d984:	f8c8 100c 	str.w	r1, [r8, #12]
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    d988:	2101      	movs	r1, #1
    d98a:	f8d8 0014 	ldr.w	r0, [r8, #20]
    d98e:	40a9      	lsls	r1, r5
    d990:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    d994:	f8d8 2018 	ldr.w	r2, [r8, #24]
    d998:	bf0c      	ite	eq
    d99a:	4308      	orreq	r0, r1
    d99c:	4388      	bicne	r0, r1
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
    d99e:	f5b3 2fc0 	cmp.w	r3, #393216	; 0x60000
    d9a2:	bf0c      	ite	eq
    d9a4:	430a      	orreq	r2, r1
    d9a6:	438a      	bicne	r2, r1
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    d9a8:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    d9ac:	f04f 0300 	mov.w	r3, #0
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
    d9b0:	f8c8 2018 	str.w	r2, [r8, #24]
    d9b4:	f8d8 2010 	ldr.w	r2, [r8, #16]
    p_reg->INTENCLR = mask;
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask)
{
    return p_reg->INTENSET & mask;
    d9b8:	4e57      	ldr	r6, [pc, #348]	; (db18 <gpio_nrfx_pin_interrupt_configure+0x1dc>)
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    d9ba:	bf0c      	ite	eq
    d9bc:	4311      	orreq	r1, r2
    d9be:	ea22 0101 	bicne.w	r1, r2, r1
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    d9c2:	f8c8 0014 	str.w	r0, [r8, #20]
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    d9c6:	f8c8 1010 	str.w	r1, [r8, #16]
    d9ca:	f8d6 2304 	ldr.w	r2, [r6, #772]	; 0x304
    d9ce:	b2d2      	uxtb	r2, r2
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
{
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    d9d0:	f503 71a2 	add.w	r1, r3, #324	; 0x144
    d9d4:	f856 1021 	ldr.w	r1, [r6, r1, lsl #2]
    d9d8:	f3c1 2104 	ubfx	r1, r1, #8, #5
		if ((nrf_gpiote_event_pin_get(NRF_GPIOTE, i) == abs_pin)
    d9dc:	428f      	cmp	r7, r1
    d9de:	d17f      	bne.n	dae0 <gpio_nrfx_pin_interrupt_configure+0x1a4>
		    && (intenset & BIT(i))) {
    d9e0:	fa22 f103 	lsr.w	r1, r2, r3
    d9e4:	07c9      	lsls	r1, r1, #31
    d9e6:	d57b      	bpl.n	dae0 <gpio_nrfx_pin_interrupt_configure+0x1a4>
			(void)atomic_and(mask, ~BIT(i));
    d9e8:	2201      	movs	r2, #1
    d9ea:	409a      	lsls	r2, r3
    d9ec:	43d0      	mvns	r0, r2
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    d9ee:	494b      	ldr	r1, [pc, #300]	; (db1c <gpio_nrfx_pin_interrupt_configure+0x1e0>)
    d9f0:	e8d1 4fef 	ldaex	r4, [r1]
    d9f4:	4004      	ands	r4, r0
    d9f6:	e8c1 4fec 	stlex	ip, r4, [r1]
    d9fa:	f1bc 0f00 	cmp.w	ip, #0
    d9fe:	d1f7      	bne.n	d9f0 <gpio_nrfx_pin_interrupt_configure+0xb4>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
    da00:	009b      	lsls	r3, r3, #2
    da02:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    da06:	f503 3344 	add.w	r3, r3, #200704	; 0x31000
    da0a:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
    da0e:	f021 0101 	bic.w	r1, r1, #1
    da12:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    p_reg->INTENCLR = mask;
    da16:	f8c6 2308 	str.w	r2, [r6, #776]	; 0x308
	nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
    da1a:	2100      	movs	r1, #0
    da1c:	4638      	mov	r0, r7
    da1e:	f7ff ff0b 	bl	d838 <nrf_gpio_cfg_sense_set>
	if (data->pin_int_en & BIT(pin)) {
    da22:	f8d8 300c 	ldr.w	r3, [r8, #12]
    da26:	40eb      	lsrs	r3, r5
    da28:	f013 0301 	ands.w	r3, r3, #1
    da2c:	d051      	beq.n	dad2 <gpio_nrfx_pin_interrupt_configure+0x196>
		if (data->trig_edge & BIT(pin)) {
    da2e:	f8d8 3014 	ldr.w	r3, [r8, #20]
    da32:	40eb      	lsrs	r3, r5
    da34:	f013 0401 	ands.w	r4, r3, #1
    da38:	d05e      	beq.n	daf8 <gpio_nrfx_pin_interrupt_configure+0x1bc>
			if (data->double_edge & BIT(pin)) {
    da3a:	f8d8 3018 	ldr.w	r3, [r8, #24]
				pol = NRF_GPIOTE_POLARITY_TOGGLE;
    da3e:	2200      	movs	r2, #0
			if (data->double_edge & BIT(pin)) {
    da40:	40eb      	lsrs	r3, r5
    da42:	07db      	lsls	r3, r3, #31
				pol = NRF_GPIOTE_POLARITY_TOGGLE;
    da44:	bf48      	it	mi
    da46:	2503      	movmi	r5, #3
		atomic_val_t prev = atomic_or(mask, BIT(channel));
    da48:	f04f 0c01 	mov.w	ip, #1
			} else if ((data->int_active_level & BIT(pin)) != 0U) {
    da4c:	bf5f      	itttt	pl
    da4e:	f8d8 1010 	ldrpl.w	r1, [r8, #16]
    da52:	fa21 f505 	lsrpl.w	r5, r1, r5
    da56:	f005 0501 	andpl.w	r5, r5, #1
    da5a:	f1c5 0502 	rsbpl	r5, r5, #2
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    da5e:	492f      	ldr	r1, [pc, #188]	; (db1c <gpio_nrfx_pin_interrupt_configure+0x1e0>)
    da60:	bf58      	it	pl
    da62:	b2ed      	uxtbpl	r5, r5
		atomic_val_t prev = atomic_or(mask, BIT(channel));
    da64:	fa0c f402 	lsl.w	r4, ip, r2
    da68:	e8d1 0fef 	ldaex	r0, [r1]
    da6c:	ea40 0304 	orr.w	r3, r0, r4
    da70:	e8c1 3fee 	stlex	lr, r3, [r1]
    da74:	f1be 0f00 	cmp.w	lr, #0
    da78:	d1f6      	bne.n	da68 <gpio_nrfx_pin_interrupt_configure+0x12c>
		if ((prev & BIT(channel)) == 0) {
    da7a:	40d0      	lsrs	r0, r2
    da7c:	f010 0301 	ands.w	r3, r0, #1
    da80:	d133      	bne.n	daea <gpio_nrfx_pin_interrupt_configure+0x1ae>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    da82:	0091      	lsls	r1, r2, #2
    da84:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    da88:	f501 3144 	add.w	r1, r1, #200704	; 0x31000
    da8c:	f8d1 0510 	ldr.w	r0, [r1, #1296]	; 0x510
			nrf_gpiote_event_t evt =
    da90:	3240      	adds	r2, #64	; 0x40
    da92:	f420 3047 	bic.w	r0, r0, #203776	; 0x31c00
    da96:	f420 7040 	bic.w	r0, r0, #768	; 0x300
    da9a:	f8c1 0510 	str.w	r0, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    da9e:	023f      	lsls	r7, r7, #8
    daa0:	0092      	lsls	r2, r2, #2
    daa2:	f8d1 0510 	ldr.w	r0, [r1, #1296]	; 0x510
    daa6:	f407 57f8 	and.w	r7, r7, #7936	; 0x1f00
    return ((uint32_t)p_reg + event);
    daaa:	b292      	uxth	r2, r2
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    daac:	ea47 4705 	orr.w	r7, r7, r5, lsl #16
    return ((uint32_t)p_reg + event);
    dab0:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    dab4:	f502 3244 	add.w	r2, r2, #200704	; 0x31000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    dab8:	4307      	orrs	r7, r0
    daba:	f8c1 7510 	str.w	r7, [r1, #1296]	; 0x510
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    dabe:	6013      	str	r3, [r2, #0]
    dac0:	6812      	ldr	r2, [r2, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    dac2:	f8d1 2510 	ldr.w	r2, [r1, #1296]	; 0x510
    dac6:	f042 0201 	orr.w	r2, r2, #1
    daca:	f8c1 2510 	str.w	r2, [r1, #1296]	; 0x510
    p_reg->INTENSET = mask;
    dace:	f8c6 4304 	str.w	r4, [r6, #772]	; 0x304
	int res = 0;
    dad2:	4618      	mov	r0, r3
    dad4:	e00e      	b.n	daf4 <gpio_nrfx_pin_interrupt_configure+0x1b8>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    dad6:	2001      	movs	r0, #1
    dad8:	40a8      	lsls	r0, r5
    dada:	ea21 0100 	bic.w	r1, r1, r0
    dade:	e751      	b.n	d984 <gpio_nrfx_pin_interrupt_configure+0x48>
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    dae0:	3301      	adds	r3, #1
    dae2:	2b08      	cmp	r3, #8
    dae4:	f47f af74 	bne.w	d9d0 <gpio_nrfx_pin_interrupt_configure+0x94>
    dae8:	e797      	b.n	da1a <gpio_nrfx_pin_interrupt_configure+0xde>
	for (uint8_t channel = 0; channel < GPIOTE_CH_NUM; ++channel) {
    daea:	3201      	adds	r2, #1
    daec:	2a08      	cmp	r2, #8
    daee:	d1b9      	bne.n	da64 <gpio_nrfx_pin_interrupt_configure+0x128>
	return -ENODEV;
    daf0:	f06f 0012 	mvn.w	r0, #18
}
    daf4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if ((BIT(pin) & data->int_active_level) != 0U) {
    daf8:	f8d8 1010 	ldr.w	r1, [r8, #16]
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    dafc:	4638      	mov	r0, r7
	if ((BIT(pin) & data->int_active_level) != 0U) {
    dafe:	40e9      	lsrs	r1, r5
    db00:	f001 0101 	and.w	r1, r1, #1
    db04:	f1c1 0103 	rsb	r1, r1, #3
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    db08:	b2c9      	uxtb	r1, r1
    db0a:	f7ff fe95 	bl	d838 <nrf_gpio_cfg_sense_set>
	int res = 0;
    db0e:	4620      	mov	r0, r4
    db10:	e7f0      	b.n	daf4 <gpio_nrfx_pin_interrupt_configure+0x1b8>
    db12:	bf00      	nop
    db14:	40842500 	.word	0x40842500
    db18:	40031000 	.word	0x40031000
    db1c:	200102ac 	.word	0x200102ac

0000db20 <gpiote_event_handler>:
{
    db20:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    db24:	4f3f      	ldr	r7, [pc, #252]	; (dc24 <gpiote_event_handler+0x104>)
    db26:	683e      	ldr	r6, [r7, #0]
	if (port_event) {
    db28:	2e00      	cmp	r6, #0
    db2a:	d04f      	beq.n	dbcc <gpiote_event_handler+0xac>
	uint32_t bit = 1U << pin;
    db2c:	f04f 0801 	mov.w	r8, #1
	uint32_t pin = 0U;
    db30:	f04f 0900 	mov.w	r9, #0
	uint32_t out = data->pin_int_en;
    db34:	4b3c      	ldr	r3, [pc, #240]	; (dc28 <gpiote_event_handler+0x108>)
    db36:	68dd      	ldr	r5, [r3, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    db38:	e9d3 2105 	ldrd	r2, r1, [r3, #20]
    db3c:	430a      	orrs	r2, r1
    db3e:	ea25 0502 	bic.w	r5, r5, r2
    return p_reg->IN;
    db42:	4a3a      	ldr	r2, [pc, #232]	; (dc2c <gpiote_event_handler+0x10c>)
	uint32_t pin_states = ~(port_in ^ data->int_active_level);
    db44:	691b      	ldr	r3, [r3, #16]
    db46:	6914      	ldr	r4, [r2, #16]
    db48:	405c      	eors	r4, r3
	uint32_t out = pin_states & level_pins;
    db4a:	ea25 0404 	bic.w	r4, r5, r4
	while (level_pins) {
    db4e:	bb75      	cbnz	r5, dbae <gpiote_event_handler+0x8e>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    db50:	603d      	str	r5, [r7, #0]
    db52:	683b      	ldr	r3, [r7, #0]
	uint32_t fired_triggers[GPIO_COUNT] = {0};
    db54:	2300      	movs	r3, #0
		if (nrf_gpiote_int_enable_check(NRF_GPIOTE, BIT(i)) &&
    db56:	2501      	movs	r5, #1
    db58:	461f      	mov	r7, r3
    return p_reg->INTENSET & mask;
    db5a:	4835      	ldr	r0, [pc, #212]	; (dc30 <gpiote_event_handler+0x110>)
    db5c:	4935      	ldr	r1, [pc, #212]	; (dc34 <gpiote_event_handler+0x114>)
    db5e:	f8d0 2304 	ldr.w	r2, [r0, #772]	; 0x304
    db62:	fa05 fc03 	lsl.w	ip, r5, r3
    db66:	ea1c 0f02 	tst.w	ip, r2
    db6a:	d00f      	beq.n	db8c <gpiote_event_handler+0x6c>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    db6c:	f851 2023 	ldr.w	r2, [r1, r3, lsl #2]
    db70:	b162      	cbz	r2, db8c <gpiote_event_handler+0x6c>
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    db72:	f503 72a2 	add.w	r2, r3, #324	; 0x144
    db76:	f850 2022 	ldr.w	r2, [r0, r2, lsl #2]
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    db7a:	f841 7023 	str.w	r7, [r1, r3, lsl #2]
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    db7e:	f3c2 2204 	ubfx	r2, r2, #8, #5
			fired_triggers[abs_pin / 32U] |= BIT(abs_pin % 32);
    db82:	fa05 f202 	lsl.w	r2, r5, r2
    db86:	4314      	orrs	r4, r2
    db88:	f851 2023 	ldr.w	r2, [r1, r3, lsl #2]
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    db8c:	3301      	adds	r3, #1
    db8e:	2b08      	cmp	r3, #8
    db90:	d1e5      	bne.n	db5e <gpiote_event_handler+0x3e>
	if (fired_triggers[0]) {
    db92:	b9ec      	cbnz	r4, dbd0 <gpiote_event_handler+0xb0>
	if (port_event) {
    db94:	b14e      	cbz	r6, dbaa <gpiote_event_handler+0x8a>
	uint32_t bit = 1U << pin;
    db96:	2601      	movs	r6, #1
	uint32_t pin = 0U;
    db98:	2700      	movs	r7, #0
	uint32_t out = data->pin_int_en;
    db9a:	4d23      	ldr	r5, [pc, #140]	; (dc28 <gpiote_event_handler+0x108>)
    db9c:	68ec      	ldr	r4, [r5, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    db9e:	e9d5 2105 	ldrd	r2, r1, [r5, #20]
    dba2:	430a      	orrs	r2, r1
    dba4:	ea24 0402 	bic.w	r4, r4, r2
	while (level_pins) {
    dba8:	bb54      	cbnz	r4, dc00 <gpiote_event_handler+0xe0>
}
    dbaa:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		if (level_pins & bit) {
    dbae:	ea15 0f08 	tst.w	r5, r8
    dbb2:	d006      	beq.n	dbc2 <gpiote_event_handler+0xa2>
			nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
    dbb4:	2100      	movs	r1, #0
    dbb6:	f009 001f 	and.w	r0, r9, #31
    dbba:	f7ff fe3d 	bl	d838 <nrf_gpio_cfg_sense_set>
			level_pins &= ~bit;
    dbbe:	ea25 0508 	bic.w	r5, r5, r8
		++pin;
    dbc2:	f109 0901 	add.w	r9, r9, #1
		bit <<= 1;
    dbc6:	ea4f 0848 	mov.w	r8, r8, lsl #1
    dbca:	e7c0      	b.n	db4e <gpiote_event_handler+0x2e>
	uint32_t fired_triggers[GPIO_COUNT] = {0};
    dbcc:	4634      	mov	r4, r6
    dbce:	e7c1      	b.n	db54 <gpiote_event_handler+0x34>
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    dbd0:	4b15      	ldr	r3, [pc, #84]	; (dc28 <gpiote_event_handler+0x108>)
    dbd2:	6859      	ldr	r1, [r3, #4]
    dbd4:	2900      	cmp	r1, #0
    dbd6:	d0dd      	beq.n	db94 <gpiote_event_handler+0x74>
	return node->next;
    dbd8:	680d      	ldr	r5, [r1, #0]
		if (cb->pin_mask & pins) {
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    dbda:	4f17      	ldr	r7, [pc, #92]	; (dc38 <gpiote_event_handler+0x118>)
    dbdc:	2d00      	cmp	r5, #0
    dbde:	bf38      	it	cc
    dbe0:	2500      	movcc	r5, #0
		if (cb->pin_mask & pins) {
    dbe2:	688a      	ldr	r2, [r1, #8]
    dbe4:	4022      	ands	r2, r4
    dbe6:	d002      	beq.n	dbee <gpiote_event_handler+0xce>
			cb->handler(port, cb, cb->pin_mask & pins);
    dbe8:	4638      	mov	r0, r7
    dbea:	684b      	ldr	r3, [r1, #4]
    dbec:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    dbee:	2d00      	cmp	r5, #0
    dbf0:	d0d0      	beq.n	db94 <gpiote_event_handler+0x74>
    dbf2:	682b      	ldr	r3, [r5, #0]
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    dbf4:	4629      	mov	r1, r5
    dbf6:	2b00      	cmp	r3, #0
    dbf8:	bf38      	it	cc
    dbfa:	2300      	movcc	r3, #0
    dbfc:	461d      	mov	r5, r3
    dbfe:	e7f0      	b.n	dbe2 <gpiote_event_handler+0xc2>
		if (level_pins & bit) {
    dc00:	4226      	tst	r6, r4
    dc02:	d00c      	beq.n	dc1e <gpiote_event_handler+0xfe>
	if ((BIT(pin) & data->int_active_level) != 0U) {
    dc04:	6929      	ldr	r1, [r5, #16]
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    dc06:	f007 001f 	and.w	r0, r7, #31
	if ((BIT(pin) & data->int_active_level) != 0U) {
    dc0a:	40f9      	lsrs	r1, r7
    dc0c:	f001 0101 	and.w	r1, r1, #1
    dc10:	f1c1 0103 	rsb	r1, r1, #3
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    dc14:	b2c9      	uxtb	r1, r1
    dc16:	f7ff fe0f 	bl	d838 <nrf_gpio_cfg_sense_set>
			level_pins &= ~bit;
    dc1a:	ea24 0406 	bic.w	r4, r4, r6
		++pin;
    dc1e:	3701      	adds	r7, #1
		bit <<= 1;
    dc20:	0076      	lsls	r6, r6, #1
    dc22:	e7c1      	b.n	dba8 <gpiote_event_handler+0x88>
    dc24:	4003117c 	.word	0x4003117c
    dc28:	20010290 	.word	0x20010290
    dc2c:	40842500 	.word	0x40842500
    dc30:	40031000 	.word	0x40031000
    dc34:	40031100 	.word	0x40031100
    dc38:	200100d8 	.word	0x200100d8

0000dc3c <spi_3_init>:
#ifdef CONFIG_SPI_2_NRF_SPIM
SPI_NRFX_SPIM_DEVICE(2);
#endif

#ifdef CONFIG_SPI_3_NRF_SPIM
SPI_NRFX_SPIM_DEVICE(3);
    dc3c:	b538      	push	{r3, r4, r5, lr}
    dc3e:	4604      	mov	r4, r0
    dc40:	2200      	movs	r2, #0
    dc42:	2101      	movs	r1, #1
    dc44:	200b      	movs	r0, #11
    dc46:	f7ff fa3d 	bl	d0c4 <z_arm_irq_priority_set>
	struct spi_nrfx_data *data = get_dev_data(dev);
    dc4a:	68e5      	ldr	r5, [r4, #12]
	result = nrfx_spim_init(&get_dev_config(dev)->spim,
    dc4c:	4a09      	ldr	r2, [pc, #36]	; (dc74 <spi_3_init+0x38>)
	data->dev = dev;
    dc4e:	64ac      	str	r4, [r5, #72]	; 0x48
	result = nrfx_spim_init(&get_dev_config(dev)->spim,
    dc50:	6860      	ldr	r0, [r4, #4]
    dc52:	462b      	mov	r3, r5
    dc54:	f100 010c 	add.w	r1, r0, #12
    dc58:	f000 fb7e 	bl	e358 <nrfx_spim_init>
	if (result != NRFX_SUCCESS) {
    dc5c:	4b06      	ldr	r3, [pc, #24]	; (dc78 <spi_3_init+0x3c>)
    dc5e:	4298      	cmp	r0, r3
    dc60:	d104      	bne.n	dc6c <spi_3_init+0x30>
	spi_context_unlock_unconditionally(&data->ctx);
    dc62:	4628      	mov	r0, r5
    dc64:	f001 ff09 	bl	fa7a <spi_context_unlock_unconditionally>
	return 0;
    dc68:	2000      	movs	r0, #0
SPI_NRFX_SPIM_DEVICE(3);
    dc6a:	bd38      	pop	{r3, r4, r5, pc}
		return -EBUSY;
    dc6c:	f06f 000f 	mvn.w	r0, #15
SPI_NRFX_SPIM_DEVICE(3);
    dc70:	e7fb      	b.n	dc6a <spi_3_init+0x2e>
    dc72:	bf00      	nop
    dc74:	0000fabb 	.word	0x0000fabb
    dc78:	0bad0000 	.word	0x0bad0000

0000dc7c <transfer_next_chunk>:
{
    dc7c:	b5f0      	push	{r4, r5, r6, r7, lr}
	struct spi_nrfx_data *dev_data = get_dev_data(dev);
    dc7e:	68c5      	ldr	r5, [r0, #12]
{
    dc80:	b085      	sub	sp, #20
 * directions have a continuous buffer, i.e. the maximum SPI transfer that
 * can be done with DMA that handles only non-scattered buffers.
 */
static inline size_t spi_context_max_continuous_chunk(struct spi_context *ctx)
{
	if (!ctx->tx_len) {
    dc82:	6beb      	ldr	r3, [r5, #60]	; 0x3c
    dc84:	6c6c      	ldr	r4, [r5, #68]	; 0x44
    dc86:	b97b      	cbnz	r3, dca8 <transfer_next_chunk+0x2c>
	if (chunk_len > 0) {
    dc88:	b99c      	cbnz	r4, dcb2 <transfer_next_chunk+0x36>
	_spi_context_cs_control(ctx, on, false);
    dc8a:	2200      	movs	r2, #0
    dc8c:	4628      	mov	r0, r5
    dc8e:	4611      	mov	r1, r2
    dc90:	f001 fece 	bl	fa30 <_spi_context_cs_control.isra.0>
	ctx->sync_status = status;
    dc94:	626c      	str	r4, [r5, #36]	; 0x24
		arch_syscall_invoke1(*(uintptr_t *)&sem, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    dc96:	f105 0014 	add.w	r0, r5, #20
    dc9a:	f001 f927 	bl	eeec <z_impl_k_sem_give>
	dev_data->busy = false;
    dc9e:	2300      	movs	r3, #0
    dca0:	f885 3050 	strb.w	r3, [r5, #80]	; 0x50
}
    dca4:	b005      	add	sp, #20
    dca6:	bdf0      	pop	{r4, r5, r6, r7, pc}
		return ctx->rx_len;
	} else if (!ctx->rx_len) {
    dca8:	2c00      	cmp	r4, #0
    dcaa:	d035      	beq.n	dd18 <transfer_next_chunk+0x9c>
		return ctx->tx_len;
	}

	return MIN(ctx->tx_len, ctx->rx_len);
    dcac:	429c      	cmp	r4, r3
    dcae:	bf28      	it	cs
    dcb0:	461c      	movcs	r4, r3
		const uint8_t *tx_buf = ctx->tx_buf;
    dcb2:	6ba9      	ldr	r1, [r5, #56]	; 0x38
	const struct spi_nrfx_config *dev_config = get_dev_config(dev);
    dcb4:	6846      	ldr	r6, [r0, #4]
	return !!(ctx->tx_buf && ctx->tx_len);
    dcb6:	b179      	cbz	r1, dcd8 <transfer_next_chunk+0x5c>
    dcb8:	b173      	cbz	r3, dcd8 <transfer_next_chunk+0x5c>

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrfx_is_in_ram(void const * p_object)
{
    return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u);
    dcba:	f001 4360 	and.w	r3, r1, #3758096384	; 0xe0000000
		if (spi_context_tx_buf_on(ctx) && !nrfx_is_in_ram(tx_buf)) {
    dcbe:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
    dcc2:	d009      	beq.n	dcd8 <transfer_next_chunk+0x5c>
			if (chunk_len > sizeof(dev_data->buffer)) {
    dcc4:	2c08      	cmp	r4, #8
    dcc6:	bf28      	it	cs
    dcc8:	2408      	movcs	r4, #8
			memcpy(dev_data->buffer, tx_buf, chunk_len);
    dcca:	f105 0751 	add.w	r7, r5, #81	; 0x51
    dcce:	4622      	mov	r2, r4
    dcd0:	4638      	mov	r0, r7
    dcd2:	f001 fe01 	bl	f8d8 <memcpy>
			tx_buf = dev_data->buffer;
    dcd6:	4639      	mov	r1, r7
		if (chunk_len > dev_config->max_chunk_len) {
    dcd8:	68b2      	ldr	r2, [r6, #8]
    dcda:	6bab      	ldr	r3, [r5, #56]	; 0x38
    dcdc:	4294      	cmp	r4, r2
    dcde:	bf28      	it	cs
    dce0:	4614      	movcs	r4, r2
		xfer.p_tx_buffer = tx_buf;
    dce2:	9100      	str	r1, [sp, #0]
		dev_data->chunk_len = chunk_len;
    dce4:	64ec      	str	r4, [r5, #76]	; 0x4c
    dce6:	b11b      	cbz	r3, dcf0 <transfer_next_chunk+0x74>
    dce8:	6beb      	ldr	r3, [r5, #60]	; 0x3c
		xfer.tx_length   = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
    dcea:	2b00      	cmp	r3, #0
    dcec:	bf18      	it	ne
    dcee:	4623      	movne	r3, r4
    dcf0:	9301      	str	r3, [sp, #4]
		xfer.p_rx_buffer = ctx->rx_buf;
    dcf2:	6c2b      	ldr	r3, [r5, #64]	; 0x40
    dcf4:	9302      	str	r3, [sp, #8]
	return !!(ctx->rx_buf && ctx->rx_len);
    dcf6:	b11b      	cbz	r3, dd00 <transfer_next_chunk+0x84>
    dcf8:	6c6b      	ldr	r3, [r5, #68]	; 0x44
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    dcfa:	2b00      	cmp	r3, #0
    dcfc:	bf18      	it	ne
    dcfe:	4623      	movne	r3, r4
			result = nrfx_spim_xfer(&dev_config->spim, &xfer, 0);
    dd00:	2200      	movs	r2, #0
    dd02:	4669      	mov	r1, sp
    dd04:	4630      	mov	r0, r6
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    dd06:	9303      	str	r3, [sp, #12]
			result = nrfx_spim_xfer(&dev_config->spim, &xfer, 0);
    dd08:	f000 fbcc 	bl	e4a4 <nrfx_spim_xfer>
			if (result == NRFX_SUCCESS) {
    dd0c:	4b03      	ldr	r3, [pc, #12]	; (dd1c <transfer_next_chunk+0xa0>)
    dd0e:	4298      	cmp	r0, r3
    dd10:	d0c8      	beq.n	dca4 <transfer_next_chunk+0x28>
			error = -EIO;
    dd12:	f06f 0404 	mvn.w	r4, #4
    dd16:	e7b8      	b.n	dc8a <transfer_next_chunk+0xe>
    dd18:	461c      	mov	r4, r3
    dd1a:	e7ca      	b.n	dcb2 <transfer_next_chunk+0x36>
    dd1c:	0bad0000 	.word	0x0bad0000

0000dd20 <spi_nrfx_transceive>:
{
    dd20:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	struct spi_nrfx_data *dev_data = get_dev_data(dev);
    dd24:	68c4      	ldr	r4, [r0, #12]
{
    dd26:	4681      	mov	r9, r0
    dd28:	460f      	mov	r7, r1
    dd2a:	4616      	mov	r6, r2
    dd2c:	461d      	mov	r5, r3
	k_sem_take(&ctx->lock, K_FOREVER);
    dd2e:	f104 0b04 	add.w	fp, r4, #4
	return z_impl_k_sem_take(sem, timeout);
    dd32:	f04f 32ff 	mov.w	r2, #4294967295
    dd36:	f04f 33ff 	mov.w	r3, #4294967295
    dd3a:	4658      	mov	r0, fp
    dd3c:	f001 f8f6 	bl	ef2c <z_impl_k_sem_take>
	struct spi_context *ctx = &get_dev_data(dev)->ctx;
    dd40:	f8d9 200c 	ldr.w	r2, [r9, #12]
	if (spi_context_configured(ctx, spi_cfg)) {
    dd44:	6813      	ldr	r3, [r2, #0]
    dd46:	429f      	cmp	r7, r3
    dd48:	d067      	beq.n	de1a <spi_nrfx_transceive+0xfa>
	if ((spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
    dd4a:	f641 0109 	movw	r1, #6153	; 0x1809
	if (SPI_OP_MODE_GET(spi_cfg->operation) != SPI_OP_MODE_MASTER) {
    dd4e:	88bb      	ldrh	r3, [r7, #4]
	if ((spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
    dd50:	420b      	tst	r3, r1
    dd52:	f040 80b5 	bne.w	dec0 <spi_nrfx_transceive+0x1a0>
	if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
    dd56:	f3c3 1345 	ubfx	r3, r3, #5, #6
    dd5a:	2b08      	cmp	r3, #8
    dd5c:	f040 80b0 	bne.w	dec0 <spi_nrfx_transceive+0x1a0>
	if (spi_cfg->frequency < 125000) {
    dd60:	6839      	ldr	r1, [r7, #0]
    dd62:	4b59      	ldr	r3, [pc, #356]	; (dec8 <spi_nrfx_transceive+0x1a8>)
    dd64:	4299      	cmp	r1, r3
    dd66:	f240 80ab 	bls.w	dec0 <spi_nrfx_transceive+0x1a0>
	const nrfx_spim_t *spim = &get_dev_config(dev)->spim;
    dd6a:	f8d9 3004 	ldr.w	r3, [r9, #4]
	ctx->config = spi_cfg;
    dd6e:	6017      	str	r7, [r2, #0]
	const nrfx_spim_t *spim = &get_dev_config(dev)->spim;
    dd70:	9300      	str	r3, [sp, #0]
	if (ctx->config->cs && ctx->config->cs->gpio_dev) {
    dd72:	68bb      	ldr	r3, [r7, #8]
    dd74:	b30b      	cbz	r3, ddba <spi_nrfx_transceive+0x9a>
    dd76:	6818      	ldr	r0, [r3, #0]
    dd78:	b1f8      	cbz	r0, ddba <spi_nrfx_transceive+0x9a>
				   ctx->config->cs->gpio_dt_flags |
    dd7a:	f893 8009 	ldrb.w	r8, [r3, #9]
		gpio_pin_configure(ctx->config->cs->gpio_dev,
    dd7e:	7a19      	ldrb	r1, [r3, #8]
		 != (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH),
		 "Output cannot be initialized low and high");

	if (((flags & GPIO_OUTPUT_INIT_LOGICAL) != 0)
	    && ((flags & (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH)) != 0)
	    && ((flags & GPIO_ACTIVE_LOW) != 0)) {
    dd80:	f018 0f01 	tst.w	r8, #1
    dd84:	bf0c      	ite	eq
    dd86:	f448 58b0 	orreq.w	r8, r8, #5632	; 0x1600
		flags ^= GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH
    dd8a:	f488 6820 	eorne.w	r8, r8, #2560	; 0xa00
	struct gpio_driver_data *data =
    dd8e:	f8d0 a00c 	ldr.w	sl, [r0, #12]
	return api->pin_configure(port, pin, flags);
    dd92:	6883      	ldr	r3, [r0, #8]
    dd94:	4642      	mov	r2, r8
    dd96:	681b      	ldr	r3, [r3, #0]
    dd98:	9101      	str	r1, [sp, #4]
    dd9a:	4798      	blx	r3
	(void)cfg;
	__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
		 "Unsupported pin");

	ret = gpio_config(port, pin, flags);
	if (ret != 0) {
    dd9c:	b968      	cbnz	r0, ddba <spi_nrfx_transceive+0x9a>
		return ret;
	}

	if ((flags & GPIO_ACTIVE_LOW) != 0) {
    dd9e:	2301      	movs	r3, #1
    dda0:	9901      	ldr	r1, [sp, #4]
    dda2:	f8da 2000 	ldr.w	r2, [sl]
    dda6:	fa03 f101 	lsl.w	r1, r3, r1
    ddaa:	f018 0f01 	tst.w	r8, #1
		data->invert |= (gpio_port_pins_t)BIT(pin);
    ddae:	bf14      	ite	ne
    ddb0:	4311      	orrne	r1, r2
	} else {
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
    ddb2:	ea22 0101 	biceq.w	r1, r2, r1
    ddb6:	f8ca 1000 	str.w	r1, [sl]
	nrf_spim_configure(spim->p_reg,
    ddba:	9b00      	ldr	r3, [sp, #0]
    ddbc:	6819      	ldr	r1, [r3, #0]
    ddbe:	88bb      	ldrh	r3, [r7, #4]
	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
    ddc0:	0798      	lsls	r0, r3, #30
    ddc2:	f003 0204 	and.w	r2, r3, #4
    ddc6:	d558      	bpl.n	de7a <spi_nrfx_transceive+0x15a>
			return NRF_SPIM_MODE_2;
    ddc8:	2a00      	cmp	r2, #0
    ddca:	bf14      	ite	ne
    ddcc:	2203      	movne	r2, #3
    ddce:	2202      	moveq	r2, #2
                                          nrf_spim_mode_t      spi_mode,
                                          nrf_spim_bit_order_t spi_bit_order)
{
    uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
        SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
    switch (spi_mode)
    ddd0:	2a02      	cmp	r2, #2
	if (operation & SPI_TRANSFER_LSB) {
    ddd2:	f3c3 1300 	ubfx	r3, r3, #4, #1
    ddd6:	d054      	beq.n	de82 <spi_nrfx_transceive+0x162>
    ddd8:	2a03      	cmp	r2, #3
    ddda:	d055      	beq.n	de88 <spi_nrfx_transceive+0x168>
    dddc:	2a01      	cmp	r2, #1
    ddde:	d101      	bne.n	dde4 <spi_nrfx_transceive+0xc4>
        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
                  (SPIM_CONFIG_CPHA_Leading    << SPIM_CONFIG_CPHA_Pos);
        break;

    case NRF_SPIM_MODE_1:
        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
    dde0:	f043 0302 	orr.w	r3, r3, #2
	if (frequency < 250000) {
    dde4:	4a39      	ldr	r2, [pc, #228]	; (decc <spi_nrfx_transceive+0x1ac>)
    case NRF_SPIM_MODE_3:
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
                  (SPIM_CONFIG_CPHA_Trailing   << SPIM_CONFIG_CPHA_Pos);
        break;
    }
    p_reg->CONFIG = config;
    dde6:	f8c1 3554 	str.w	r3, [r1, #1364]	; 0x554
	nrf_spim_frequency_set(spim->p_reg,
    ddea:	683b      	ldr	r3, [r7, #0]
	if (frequency < 250000) {
    ddec:	4293      	cmp	r3, r2
    ddee:	d94e      	bls.n	de8e <spi_nrfx_transceive+0x16e>
	} else if (frequency < 500000) {
    ddf0:	4a37      	ldr	r2, [pc, #220]	; (ded0 <spi_nrfx_transceive+0x1b0>)
    ddf2:	4293      	cmp	r3, r2
    ddf4:	d94e      	bls.n	de94 <spi_nrfx_transceive+0x174>
	} else if (frequency < 1000000) {
    ddf6:	4a37      	ldr	r2, [pc, #220]	; (ded4 <spi_nrfx_transceive+0x1b4>)
    ddf8:	4293      	cmp	r3, r2
    ddfa:	d94e      	bls.n	de9a <spi_nrfx_transceive+0x17a>
	} else if (frequency < 2000000) {
    ddfc:	4a36      	ldr	r2, [pc, #216]	; (ded8 <spi_nrfx_transceive+0x1b8>)
    ddfe:	4293      	cmp	r3, r2
    de00:	d94e      	bls.n	dea0 <spi_nrfx_transceive+0x180>
	} else if (frequency < 4000000) {
    de02:	4a36      	ldr	r2, [pc, #216]	; (dedc <spi_nrfx_transceive+0x1bc>)
    de04:	4293      	cmp	r3, r2
    de06:	d94e      	bls.n	dea6 <spi_nrfx_transceive+0x186>
		return NRF_SPIM_FREQ_8M;
    de08:	4a35      	ldr	r2, [pc, #212]	; (dee0 <spi_nrfx_transceive+0x1c0>)
    de0a:	4293      	cmp	r3, r2
    de0c:	bf34      	ite	cc
    de0e:	f04f 4380 	movcc.w	r3, #1073741824	; 0x40000000
    de12:	f04f 4300 	movcs.w	r3, #2147483648	; 0x80000000
    p_reg->FREQUENCY = (uint32_t)frequency;
    de16:	f8c1 3524 	str.w	r3, [r1, #1316]	; 0x524
		dev_data->busy = true;
    de1a:	2301      	movs	r3, #1
    de1c:	f884 3050 	strb.w	r3, [r4, #80]	; 0x50
	if (tx_bufs) {
    de20:	2e00      	cmp	r6, #0
    de22:	d043      	beq.n	deac <spi_nrfx_transceive+0x18c>
		ctx->current_tx = tx_bufs->buffers;
    de24:	6833      	ldr	r3, [r6, #0]
		ctx->tx_count = tx_bufs->count;
    de26:	6872      	ldr	r2, [r6, #4]
		ctx->current_tx = tx_bufs->buffers;
    de28:	62a3      	str	r3, [r4, #40]	; 0x28
		ctx->tx_count = tx_bufs->count;
    de2a:	62e2      	str	r2, [r4, #44]	; 0x2c
		ctx->tx_buf = (const uint8_t *)ctx->current_tx->buf;
    de2c:	681a      	ldr	r2, [r3, #0]
		ctx->tx_len = ctx->current_tx->len / dfs;
    de2e:	685b      	ldr	r3, [r3, #4]
		ctx->tx_buf = (const uint8_t *)ctx->current_tx->buf;
    de30:	63a2      	str	r2, [r4, #56]	; 0x38
		ctx->tx_len = ctx->current_tx->len / dfs;
    de32:	63e3      	str	r3, [r4, #60]	; 0x3c
	if (rx_bufs) {
    de34:	2d00      	cmp	r5, #0
    de36:	d03e      	beq.n	deb6 <spi_nrfx_transceive+0x196>
		ctx->current_rx = rx_bufs->buffers;
    de38:	682b      	ldr	r3, [r5, #0]
		ctx->rx_count = rx_bufs->count;
    de3a:	686a      	ldr	r2, [r5, #4]
		ctx->current_rx = rx_bufs->buffers;
    de3c:	6323      	str	r3, [r4, #48]	; 0x30
		ctx->rx_count = rx_bufs->count;
    de3e:	6362      	str	r2, [r4, #52]	; 0x34
		ctx->rx_buf = (uint8_t *)ctx->current_rx->buf;
    de40:	681a      	ldr	r2, [r3, #0]
		ctx->rx_len = ctx->current_rx->len / dfs;
    de42:	685b      	ldr	r3, [r3, #4]
		ctx->rx_buf = (uint8_t *)ctx->current_rx->buf;
    de44:	6422      	str	r2, [r4, #64]	; 0x40
		ctx->rx_len = ctx->current_rx->len / dfs;
    de46:	6463      	str	r3, [r4, #68]	; 0x44
	ctx->sync_status = 0;
    de48:	2200      	movs	r2, #0
	_spi_context_cs_control(ctx, on, false);
    de4a:	2101      	movs	r1, #1
    de4c:	4620      	mov	r0, r4
	ctx->sync_status = 0;
    de4e:	6262      	str	r2, [r4, #36]	; 0x24
	_spi_context_cs_control(ctx, on, false);
    de50:	f001 fdee 	bl	fa30 <_spi_context_cs_control.isra.0>
		transfer_next_chunk(dev);
    de54:	4648      	mov	r0, r9
    de56:	f7ff ff11 	bl	dc7c <transfer_next_chunk>
    de5a:	f04f 32ff 	mov.w	r2, #4294967295
    de5e:	f104 0014 	add.w	r0, r4, #20
    de62:	f04f 33ff 	mov.w	r3, #4294967295
    de66:	f001 f861 	bl	ef2c <z_impl_k_sem_take>
	status = ctx->sync_status;
    de6a:	6a64      	ldr	r4, [r4, #36]	; 0x24
	z_impl_k_sem_give(sem);
    de6c:	4658      	mov	r0, fp
    de6e:	f001 f83d 	bl	eeec <z_impl_k_sem_give>
}
    de72:	4620      	mov	r0, r4
    de74:	b003      	add	sp, #12
    de76:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			return NRF_SPIM_MODE_0;
    de7a:	3a00      	subs	r2, #0
    de7c:	bf18      	it	ne
    de7e:	2201      	movne	r2, #1
    de80:	e7a6      	b.n	ddd0 <spi_nrfx_transceive+0xb0>
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
    de82:	f043 0304 	orr.w	r3, r3, #4
        break;
    de86:	e7ad      	b.n	dde4 <spi_nrfx_transceive+0xc4>
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
    de88:	f043 0306 	orr.w	r3, r3, #6
        break;
    de8c:	e7aa      	b.n	dde4 <spi_nrfx_transceive+0xc4>
		return NRF_SPIM_FREQ_125K;
    de8e:	f04f 7300 	mov.w	r3, #33554432	; 0x2000000
    de92:	e7c0      	b.n	de16 <spi_nrfx_transceive+0xf6>
		return NRF_SPIM_FREQ_250K;
    de94:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    de98:	e7bd      	b.n	de16 <spi_nrfx_transceive+0xf6>
		return NRF_SPIM_FREQ_500K;
    de9a:	f04f 6300 	mov.w	r3, #134217728	; 0x8000000
    de9e:	e7ba      	b.n	de16 <spi_nrfx_transceive+0xf6>
		return NRF_SPIM_FREQ_1M;
    dea0:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    dea4:	e7b7      	b.n	de16 <spi_nrfx_transceive+0xf6>
		return NRF_SPIM_FREQ_2M;
    dea6:	f04f 5300 	mov.w	r3, #536870912	; 0x20000000
    deaa:	e7b4      	b.n	de16 <spi_nrfx_transceive+0xf6>
		ctx->tx_count = 0;
    deac:	e9c4 660a 	strd	r6, r6, [r4, #40]	; 0x28
		ctx->tx_len = 0;
    deb0:	e9c4 660e 	strd	r6, r6, [r4, #56]	; 0x38
    deb4:	e7be      	b.n	de34 <spi_nrfx_transceive+0x114>
		ctx->rx_count = 0;
    deb6:	e9c4 550c 	strd	r5, r5, [r4, #48]	; 0x30
		ctx->rx_len = 0;
    deba:	e9c4 5510 	strd	r5, r5, [r4, #64]	; 0x40
    debe:	e7c3      	b.n	de48 <spi_nrfx_transceive+0x128>
		return -EINVAL;
    dec0:	f06f 0415 	mvn.w	r4, #21
    dec4:	e7d2      	b.n	de6c <spi_nrfx_transceive+0x14c>
    dec6:	bf00      	nop
    dec8:	0001e847 	.word	0x0001e847
    decc:	0003d08f 	.word	0x0003d08f
    ded0:	0007a11f 	.word	0x0007a11f
    ded4:	000f423f 	.word	0x000f423f
    ded8:	001e847f 	.word	0x001e847f
    dedc:	003d08ff 	.word	0x003d08ff
    dee0:	007a1200 	.word	0x007a1200

0000dee4 <uarte_nrfx_configure>:
	return 0;
}

static int uarte_nrfx_configure(const struct device *dev,
				const struct uart_config *cfg)
{
    dee4:	b5f0      	push	{r4, r5, r6, r7, lr}
	nrf_uarte_config_t uarte_cfg;

#if defined(UARTE_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
    dee6:	794b      	ldrb	r3, [r1, #5]
    dee8:	2b01      	cmp	r3, #1
    deea:	d029      	beq.n	df40 <uarte_nrfx_configure+0x5c>
    deec:	2b03      	cmp	r3, #3
    deee:	d124      	bne.n	df3a <uarte_nrfx_configure+0x56>
	case UART_CFG_STOP_BITS_1:
		uarte_cfg.stop = NRF_UARTE_STOP_ONE;
		break;
	case UART_CFG_STOP_BITS_2:
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
    def0:	2610      	movs	r6, #16
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    def2:	798b      	ldrb	r3, [r1, #6]
    def4:	2b03      	cmp	r3, #3
    def6:	d120      	bne.n	df3a <uarte_nrfx_configure+0x56>
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
    def8:	79cc      	ldrb	r4, [r1, #7]
    defa:	b124      	cbz	r4, df06 <uarte_nrfx_configure+0x22>
    defc:	2c01      	cmp	r4, #1
    defe:	d11c      	bne.n	df3a <uarte_nrfx_configure+0x56>
	case UART_CFG_FLOW_CTRL_NONE:
		uarte_cfg.hwfc = NRF_UARTE_HWFC_DISABLED;
		break;
	case UART_CFG_FLOW_CTRL_RTS_CTS:
		if (get_dev_config(dev)->rts_cts_pins_set) {
    df00:	6843      	ldr	r3, [r0, #4]
    df02:	791b      	ldrb	r3, [r3, #4]
    df04:	b1cb      	cbz	r3, df3a <uarte_nrfx_configure+0x56>
	}

#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
    df06:	790a      	ldrb	r2, [r1, #4]
    df08:	b112      	cbz	r2, df10 <uarte_nrfx_configure+0x2c>
    df0a:	2a02      	cmp	r2, #2
    df0c:	d115      	bne.n	df3a <uarte_nrfx_configure+0x56>
	case UART_CFG_PARITY_NONE:
		uarte_cfg.parity = NRF_UARTE_PARITY_EXCLUDED;
		break;
	case UART_CFG_PARITY_EVEN:
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
    df0e:	220e      	movs	r2, #14
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
    df10:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    df12:	6845      	ldr	r5, [r0, #4]
	switch (baudrate) {
    df14:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    df18:	682d      	ldr	r5, [r5, #0]
	switch (baudrate) {
    df1a:	d065      	beq.n	dfe8 <uarte_nrfx_configure+0x104>
    df1c:	d82d      	bhi.n	df7a <uarte_nrfx_configure+0x96>
    df1e:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    df22:	d064      	beq.n	dfee <uarte_nrfx_configure+0x10a>
    df24:	d816      	bhi.n	df54 <uarte_nrfx_configure+0x70>
    df26:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    df2a:	d062      	beq.n	dff2 <uarte_nrfx_configure+0x10e>
    df2c:	d80a      	bhi.n	df44 <uarte_nrfx_configure+0x60>
    df2e:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    df32:	d061      	beq.n	dff8 <uarte_nrfx_configure+0x114>
    df34:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    df38:	d061      	beq.n	dffe <uarte_nrfx_configure+0x11a>
    df3a:	f06f 0022 	mvn.w	r0, #34	; 0x22
    df3e:	e052      	b.n	dfe6 <uarte_nrfx_configure+0x102>
	switch (cfg->stop_bits) {
    df40:	2600      	movs	r6, #0
    df42:	e7d6      	b.n	def2 <uarte_nrfx_configure+0xe>
	switch (baudrate) {
    df44:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    df48:	d05c      	beq.n	e004 <uarte_nrfx_configure+0x120>
    df4a:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    df4e:	d1f4      	bne.n	df3a <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    df50:	4b37      	ldr	r3, [pc, #220]	; (e030 <uarte_nrfx_configure+0x14c>)
    df52:	e03c      	b.n	dfce <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    df54:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    df58:	d057      	beq.n	e00a <uarte_nrfx_configure+0x126>
    df5a:	d807      	bhi.n	df6c <uarte_nrfx_configure+0x88>
    df5c:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    df60:	d055      	beq.n	e00e <uarte_nrfx_configure+0x12a>
    df62:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    df66:	d1e8      	bne.n	df3a <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    df68:	4b32      	ldr	r3, [pc, #200]	; (e034 <uarte_nrfx_configure+0x150>)
    df6a:	e030      	b.n	dfce <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    df6c:	f647 2712 	movw	r7, #31250	; 0x7a12
    df70:	42bb      	cmp	r3, r7
    df72:	d1e2      	bne.n	df3a <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    df74:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    df78:	e029      	b.n	dfce <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    df7a:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    df7e:	d048      	beq.n	e012 <uarte_nrfx_configure+0x12e>
    df80:	d813      	bhi.n	dfaa <uarte_nrfx_configure+0xc6>
    df82:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    df86:	d047      	beq.n	e018 <uarte_nrfx_configure+0x134>
    df88:	d809      	bhi.n	df9e <uarte_nrfx_configure+0xba>
    df8a:	f64d 27c0 	movw	r7, #56000	; 0xdac0
    df8e:	42bb      	cmp	r3, r7
    df90:	d044      	beq.n	e01c <uarte_nrfx_configure+0x138>
    df92:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    df96:	d1d0      	bne.n	df3a <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    df98:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    df9c:	e017      	b.n	dfce <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    df9e:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    dfa2:	d1ca      	bne.n	df3a <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    dfa4:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    dfa8:	e011      	b.n	dfce <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    dfaa:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    dfae:	d038      	beq.n	e022 <uarte_nrfx_configure+0x13e>
    dfb0:	d808      	bhi.n	dfc4 <uarte_nrfx_configure+0xe0>
    dfb2:	4f21      	ldr	r7, [pc, #132]	; (e038 <uarte_nrfx_configure+0x154>)
    dfb4:	42bb      	cmp	r3, r7
    dfb6:	d037      	beq.n	e028 <uarte_nrfx_configure+0x144>
    dfb8:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    dfbc:	d1bd      	bne.n	df3a <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    dfbe:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    dfc2:	e004      	b.n	dfce <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    dfc4:	4f1d      	ldr	r7, [pc, #116]	; (e03c <uarte_nrfx_configure+0x158>)
    dfc6:	42bb      	cmp	r3, r7
    dfc8:	d1b7      	bne.n	df3a <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    dfca:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    dfce:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
		return -ENOTSUP;
	}

	nrf_uarte_configure(get_uarte_instance(dev), &uarte_cfg);

	get_dev_data(dev)->uart_config = *cfg;
    dfd2:	68c3      	ldr	r3, [r0, #12]
                    | (uint32_t)p_cfg->hwfc;
    dfd4:	4334      	orrs	r4, r6
    dfd6:	4322      	orrs	r2, r4
    dfd8:	3304      	adds	r3, #4
    dfda:	c903      	ldmia	r1, {r0, r1}
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    dfdc:	f8c5 256c 	str.w	r2, [r5, #1388]	; 0x56c
    dfe0:	e883 0003 	stmia.w	r3, {r0, r1}

	return 0;
    dfe4:	2000      	movs	r0, #0
}
    dfe6:	bdf0      	pop	{r4, r5, r6, r7, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    dfe8:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    dfec:	e7ef      	b.n	dfce <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    dfee:	4b14      	ldr	r3, [pc, #80]	; (e040 <uarte_nrfx_configure+0x15c>)
    dff0:	e7ed      	b.n	dfce <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    dff2:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    dff6:	e7ea      	b.n	dfce <uarte_nrfx_configure+0xea>
		nrf_baudrate = 0x00014000;
    dff8:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    dffc:	e7e7      	b.n	dfce <uarte_nrfx_configure+0xea>
	switch (baudrate) {
    dffe:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    e002:	e7e4      	b.n	dfce <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    e004:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    e008:	e7e1      	b.n	dfce <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    e00a:	4b0e      	ldr	r3, [pc, #56]	; (e044 <uarte_nrfx_configure+0x160>)
    e00c:	e7df      	b.n	dfce <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    e00e:	4b0e      	ldr	r3, [pc, #56]	; (e048 <uarte_nrfx_configure+0x164>)
    e010:	e7dd      	b.n	dfce <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    e012:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    e016:	e7da      	b.n	dfce <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    e018:	4b0c      	ldr	r3, [pc, #48]	; (e04c <uarte_nrfx_configure+0x168>)
    e01a:	e7d8      	b.n	dfce <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    e01c:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    e020:	e7d5      	b.n	dfce <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    e022:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    e026:	e7d2      	b.n	dfce <uarte_nrfx_configure+0xea>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    e028:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    e02c:	e7cf      	b.n	dfce <uarte_nrfx_configure+0xea>
    e02e:	bf00      	nop
    e030:	0013b000 	.word	0x0013b000
    e034:	004ea000 	.word	0x004ea000
    e038:	0003d090 	.word	0x0003d090
    e03c:	000f4240 	.word	0x000f4240
    e040:	00275000 	.word	0x00275000
    e044:	0075c000 	.word	0x0075c000
    e048:	003af000 	.word	0x003af000
    e04c:	013a9000 	.word	0x013a9000

0000e050 <uarte_instance_init.isra.0>:
	.irq_update		= uarte_nrfx_irq_update,
	.irq_callback_set	= uarte_nrfx_irq_callback_set,
#endif /* UARTE_INTERRUPT_DRIVEN */
};

static int uarte_instance_init(const struct device *dev,
    e050:	b5f8      	push	{r3, r4, r5, r6, r7, lr}

	nrf_uarte_disable(uarte);

	data->dev = dev;

	nrf_gpio_pin_write(config->pseltxd, 1);
    e052:	680f      	ldr	r7, [r1, #0]
static int uarte_instance_init(const struct device *dev,
    e054:	460d      	mov	r5, r1
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    e056:	2101      	movs	r1, #1
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    e058:	f04f 0c00 	mov.w	ip, #0
	return config->uarte_regs;
    e05c:	6843      	ldr	r3, [r0, #4]
	struct uarte_nrfx_data *data = get_dev_data(dev);
    e05e:	68c6      	ldr	r6, [r0, #12]
	return config->uarte_regs;
    e060:	681c      	ldr	r4, [r3, #0]
    *p_pin = pin_number & 0x1F;
    e062:	f007 021f 	and.w	r2, r7, #31
    p_reg->OUTSET = set_mask;
    e066:	4b25      	ldr	r3, [pc, #148]	; (e0fc <uarte_instance_init.isra.0+0xac>)
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    e068:	4091      	lsls	r1, r2
    e06a:	f8c4 c500 	str.w	ip, [r4, #1280]	; 0x500
	data->dev = dev;
    e06e:	6030      	str	r0, [r6, #0]
    p_reg->OUTSET = set_mask;
    e070:	6099      	str	r1, [r3, #8]
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    e072:	2103      	movs	r1, #3
    e074:	3280      	adds	r2, #128	; 0x80
    e076:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
	nrf_gpio_cfg_output(config->pseltxd);

	if (config->pselrxd !=  NRF_UARTE_PSEL_DISCONNECTED) {
    e07a:	686a      	ldr	r2, [r5, #4]
    e07c:	1c51      	adds	r1, r2, #1
    *p_pin = pin_number & 0x1F;
    e07e:	bf1e      	ittt	ne
    e080:	f002 011f 	andne.w	r1, r2, #31
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    e084:	3180      	addne	r1, #128	; 0x80
    e086:	f843 c021 	strne.w	ip, [r3, r1, lsl #2]
		nrf_gpio_cfg_input(config->pselrxd, NRF_GPIO_PIN_NOPULL);
	}

	nrf_uarte_txrx_pins_set(uarte, config->pseltxd, config->pselrxd);

	if (config->pselcts != NRF_UARTE_PSEL_DISCONNECTED) {
    e08a:	68a9      	ldr	r1, [r5, #8]
    p_reg->PSEL.TXD = pseltxd;
    e08c:	f8c4 750c 	str.w	r7, [r4, #1292]	; 0x50c
    e090:	1c4f      	adds	r7, r1, #1
    e092:	bf18      	it	ne
    e094:	2700      	movne	r7, #0
    p_reg->PSEL.RXD = pselrxd;
    e096:	f8c4 2514 	str.w	r2, [r4, #1300]	; 0x514
    *p_pin = pin_number & 0x1F;
    e09a:	bf1e      	ittt	ne
    e09c:	f001 021f 	andne.w	r2, r1, #31
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    e0a0:	3280      	addne	r2, #128	; 0x80
    e0a2:	f843 7022 	strne.w	r7, [r3, r2, lsl #2]
		nrf_gpio_cfg_input(config->pselcts, NRF_GPIO_PIN_NOPULL);
	}

	if (config->pselrts != NRF_UARTE_PSEL_DISCONNECTED) {
    e0a6:	68ef      	ldr	r7, [r5, #12]
    e0a8:	1c7a      	adds	r2, r7, #1
    e0aa:	d00c      	beq.n	e0c6 <uarte_instance_init.isra.0+0x76>
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    e0ac:	f04f 0c01 	mov.w	ip, #1
    *p_pin = pin_number & 0x1F;
    e0b0:	f007 021f 	and.w	r2, r7, #31
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    e0b4:	fa0c fc02 	lsl.w	ip, ip, r2
    p_reg->OUTSET = set_mask;
    e0b8:	f8c3 c008 	str.w	ip, [r3, #8]
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    e0bc:	f04f 0c03 	mov.w	ip, #3
    e0c0:	3280      	adds	r2, #128	; 0x80
    e0c2:	f843 c022 	str.w	ip, [r3, r2, lsl #2]
    p_reg->PSEL.RTS = pselrts;
    e0c6:	f8c4 7508 	str.w	r7, [r4, #1288]	; 0x508
    p_reg->PSEL.CTS = pselcts;
    e0ca:	f8c4 1510 	str.w	r1, [r4, #1296]	; 0x510
		nrf_gpio_cfg_output(config->pselrts);
	}

	nrf_uarte_hwfc_pins_set(uarte, config->pselrts, config->pselcts);

	err = uarte_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
    e0ce:	68c1      	ldr	r1, [r0, #12]
    e0d0:	3104      	adds	r1, #4
    e0d2:	f7ff ff07 	bl	dee4 <uarte_nrfx_configure>
	if (err) {
    e0d6:	b980      	cbnz	r0, e0fa <uarte_instance_init.isra.0+0xaa>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    e0d8:	2308      	movs	r3, #8
    e0da:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
	}
#endif
	/* Enable receiver and transmitter */
	nrf_uarte_enable(uarte);

	if (config->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
    e0de:	686b      	ldr	r3, [r5, #4]
    e0e0:	3301      	adds	r3, #1
    e0e2:	d00a      	beq.n	e0fa <uarte_instance_init.isra.0+0xaa>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e0e4:	f8c4 0110 	str.w	r0, [r4, #272]	; 0x110
    e0e8:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110
NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    p_reg->RXD.MAXCNT = length;
    e0ec:	2301      	movs	r3, #1
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);

		nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
    e0ee:	3610      	adds	r6, #16
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    e0f0:	f8c4 6534 	str.w	r6, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    e0f4:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e0f8:	6023      	str	r3, [r4, #0]
		/* switch off transmitter to save an energy */
		nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPTX);
	}
#endif
	return 0;
}
    e0fa:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    e0fc:	40842500 	.word	0x40842500

0000e100 <uarte_0_init>:
				.tx_buffer = uarte##idx##_tx_buffer,	       \
				.tx_buff_size = sizeof(uarte##idx##_tx_buffer),\
			};))

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
    e100:	b530      	push	{r4, r5, lr}
    e102:	b085      	sub	sp, #20
    e104:	4605      	mov	r5, r0
    e106:	466c      	mov	r4, sp
    e108:	4b04      	ldr	r3, [pc, #16]	; (e11c <uarte_0_init+0x1c>)
    e10a:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    e10c:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
    e110:	4621      	mov	r1, r4
    e112:	4628      	mov	r0, r5
    e114:	f7ff ff9c 	bl	e050 <uarte_instance_init.isra.0>
    e118:	b005      	add	sp, #20
    e11a:	bd30      	pop	{r4, r5, pc}
    e11c:	000100d0 	.word	0x000100d0

0000e120 <uarte_1_init>:
#endif

#ifdef CONFIG_UART_1_NRF_UARTE
UART_NRF_UARTE_DEVICE(1);
    e120:	b530      	push	{r4, r5, lr}
    e122:	b085      	sub	sp, #20
    e124:	4605      	mov	r5, r0
    e126:	466c      	mov	r4, sp
    e128:	4b04      	ldr	r3, [pc, #16]	; (e13c <uarte_1_init+0x1c>)
    e12a:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    e12c:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
    e130:	4621      	mov	r1, r4
    e132:	4628      	mov	r0, r5
    e134:	f7ff ff8c 	bl	e050 <uarte_instance_init.isra.0>
    e138:	b005      	add	sp, #20
    e13a:	bd30      	pop	{r4, r5, pc}
    e13c:	000100e0 	.word	0x000100e0

0000e140 <check_ext_api_requests>:
	}
};
#endif

static int check_ext_api_requests(const struct device *dev)
{
    e140:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
	(void)dev;

	const struct fw_info_ext_api_request *ext_api_req =
			skip_ext_apis(&m_firmware_info);

	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    e144:	2500      	movs	r5, #0
			skip_ext_apis(&m_firmware_info);
    e146:	4c21      	ldr	r4, [pc, #132]	; (e1cc <check_ext_api_requests+0x8c>)
 */
static inline const struct fw_info_ext_api *fw_info_ext_api_check(
							uint32_t ext_api_addr)
{
	const struct fw_info_ext_api *ext_api;
	const uint32_t ext_api_magic[] = {EXT_API_MAGIC};
    e148:	4e21      	ldr	r6, [pc, #132]	; (e1d0 <check_ext_api_requests+0x90>)
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    e14a:	f854 8c04 	ldr.w	r8, [r4, #-4]
			/* EXT_API hard requirement not met. */
			printk("ERROR: Cannot fulfill EXT_API request.\r\n");
			k_panic();
		} else {
			/* EXT_API soft requirement not met. */
			printk("WARNING: Optional EXT_API request not "
    e14e:	f8df 9088 	ldr.w	r9, [pc, #136]	; e1d8 <check_ext_api_requests+0x98>
{
    e152:	b085      	sub	sp, #20
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    e154:	45a8      	cmp	r8, r5
    e156:	d803      	bhi.n	e160 <check_ext_api_requests+0x20>
		}
		ADVANCE_EXT_API_REQ(ext_api_req);
	}

	return 0;
}
    e158:	2000      	movs	r0, #0
    e15a:	b005      	add	sp, #20
    e15c:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
		if (fw_info_ext_api_check((uint32_t)*(ext_api_req->ext_api))
    e160:	6a63      	ldr	r3, [r4, #36]	; 0x24
    e162:	e896 0007 	ldmia.w	r6, {r0, r1, r2}
    e166:	681f      	ldr	r7, [r3, #0]
    e168:	ab01      	add	r3, sp, #4
    e16a:	e883 0007 	stmia.w	r3, {r0, r1, r2}

	ext_api = (const struct fw_info_ext_api *)(ext_api_addr);
	if (memcmp(ext_api->magic, ext_api_magic, CONFIG_FW_INFO_MAGIC_LEN)
    e16e:	220c      	movs	r2, #12
    e170:	4619      	mov	r1, r3
    e172:	4638      	mov	r0, r7
    e174:	f001 fba0 	bl	f8b8 <memcmp>
    e178:	b990      	cbnz	r0, e1a0 <check_ext_api_requests+0x60>
    e17a:	b18f      	cbz	r7, e1a0 <check_ext_api_requests+0x60>
			&& ext_api_satisfies_req(*(ext_api_req->ext_api),
    e17c:	6a63      	ldr	r3, [r4, #36]	; 0x24
	const uint32_t req_id = ext_api_req->request.ext_api_id;
    e17e:	6921      	ldr	r1, [r4, #16]
			&& ext_api_satisfies_req(*(ext_api_req->ext_api),
    e180:	681b      	ldr	r3, [r3, #0]
	return ((ext_api->ext_api_id == req_id)
    e182:	691a      	ldr	r2, [r3, #16]
		&& ((ext_api->ext_api_flags & req_flags) == req_flags));
    e184:	4291      	cmp	r1, r2
    e186:	d10b      	bne.n	e1a0 <check_ext_api_requests+0x60>
		&&  (ext_api->ext_api_version >= req_min_version)
    e188:	699a      	ldr	r2, [r3, #24]
	const uint32_t req_min_version = ext_api_req->request.ext_api_version;
    e18a:	69a1      	ldr	r1, [r4, #24]
		&&  (ext_api->ext_api_version >= req_min_version)
    e18c:	4291      	cmp	r1, r2
    e18e:	d807      	bhi.n	e1a0 <check_ext_api_requests+0x60>
	const uint32_t req_max_version = ext_api_req->ext_api_max_version;
    e190:	69e1      	ldr	r1, [r4, #28]
		&&  (ext_api->ext_api_version <  req_max_version)
    e192:	4291      	cmp	r1, r2
    e194:	d904      	bls.n	e1a0 <check_ext_api_requests+0x60>
	const uint32_t req_flags = ext_api_req->request.ext_api_flags;
    e196:	6962      	ldr	r2, [r4, #20]
		&& ((ext_api->ext_api_flags & req_flags) == req_flags));
    e198:	695b      	ldr	r3, [r3, #20]
    e19a:	ea32 0303 	bics.w	r3, r2, r3
    e19e:	d00a      	beq.n	e1b6 <check_ext_api_requests+0x76>
		} else if (ext_api_req->required) {
    e1a0:	6a27      	ldr	r7, [r4, #32]
    e1a2:	b167      	cbz	r7, e1be <check_ext_api_requests+0x7e>
			printk("ERROR: Cannot fulfill EXT_API request.\r\n");
    e1a4:	480b      	ldr	r0, [pc, #44]	; (e1d4 <check_ext_api_requests+0x94>)
    e1a6:	f001 f903 	bl	f3b0 <printk>
			k_panic();
    e1aa:	4040      	eors	r0, r0
    e1ac:	f380 8811 	msr	BASEPRI, r0
    e1b0:	f04f 0004 	mov.w	r0, #4
    e1b4:	df02      	svc	2
		ADVANCE_EXT_API_REQ(ext_api_req);
    e1b6:	68e3      	ldr	r3, [r4, #12]
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    e1b8:	3501      	adds	r5, #1
		ADVANCE_EXT_API_REQ(ext_api_req);
    e1ba:	441c      	add	r4, r3
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    e1bc:	e7ca      	b.n	e154 <check_ext_api_requests+0x14>
			printk("WARNING: Optional EXT_API request not "
    e1be:	4648      	mov	r0, r9
    e1c0:	f001 f8f6 	bl	f3b0 <printk>
			*ext_api_req->ext_api = NULL;
    e1c4:	6a63      	ldr	r3, [r4, #36]	; 0x24
    e1c6:	601f      	str	r7, [r3, #0]
    e1c8:	e7f5      	b.n	e1b6 <check_ext_api_requests+0x76>
    e1ca:	bf00      	nop
    e1cc:	0000c23c 	.word	0x0000c23c
    e1d0:	000100f0 	.word	0x000100f0
    e1d4:	000102b5 	.word	0x000102b5
    e1d8:	000102de 	.word	0x000102de

0000e1dc <SystemInit>:
    static bool uicr_HFXOCNT_erased(void);
#endif

void SystemCoreClockUpdate(void)
{
    SystemCoreClock = __SYSTEM_CLOCK;
    e1dc:	4b01      	ldr	r3, [pc, #4]	; (e1e4 <SystemInit+0x8>)
    e1de:	4a02      	ldr	r2, [pc, #8]	; (e1e8 <SystemInit+0xc>)
    e1e0:	601a      	str	r2, [r3, #0]
      __DSB();
      __ISB();
    #endif
    
    SystemCoreClockUpdate();
}
    e1e2:	4770      	bx	lr
    e1e4:	2001008c 	.word	0x2001008c
    e1e8:	03d09000 	.word	0x03d09000

0000e1ec <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    e1ec:	4b04      	ldr	r3, [pc, #16]	; (e200 <nrfx_clock_init+0x14>)
    e1ee:	791a      	ldrb	r2, [r3, #4]
    e1f0:	b922      	cbnz	r2, e1fc <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    e1f2:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    e1f4:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    e1f6:	711a      	strb	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    e1f8:	4802      	ldr	r0, [pc, #8]	; (e204 <nrfx_clock_init+0x18>)
    e1fa:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    e1fc:	4802      	ldr	r0, [pc, #8]	; (e208 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    e1fe:	4770      	bx	lr
    e200:	200102b0 	.word	0x200102b0
    e204:	0bad0000 	.word	0x0bad0000
    e208:	0bad000c 	.word	0x0bad000c

0000e20c <nrfx_clock_start>:
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    e20c:	b110      	cbz	r0, e214 <nrfx_clock_start+0x8>
    e20e:	2801      	cmp	r0, #1
    e210:	d01e      	beq.n	e250 <nrfx_clock_start+0x44>
    e212:	4770      	bx	lr
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    e214:	4b13      	ldr	r3, [pc, #76]	; (e264 <nrfx_clock_start+0x58>)
    e216:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    e21a:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
    e21e:	f411 3f80 	tst.w	r1, #65536	; 0x10000
    e222:	4619      	mov	r1, r3
    e224:	d010      	beq.n	e248 <nrfx_clock_start+0x3c>
    {
        case NRF_CLOCK_DOMAIN_LFCLK:
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
            {
                nrf_clock_lfclk_t lfclksrc;
                if (nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc) &&
    e226:	f002 0203 	and.w	r2, r2, #3
    e22a:	2a02      	cmp	r2, #2
    e22c:	d10c      	bne.n	e248 <nrfx_clock_start+0x3c>
    p_reg->LFCLKSRC = (uint32_t)(source);
    e22e:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e232:	2200      	movs	r2, #0
    e234:	4b0c      	ldr	r3, [pc, #48]	; (e268 <nrfx_clock_start+0x5c>)
    e236:	601a      	str	r2, [r3, #0]
    p_reg->INTENSET = mask;
    e238:	2202      	movs	r2, #2
    e23a:	681b      	ldr	r3, [r3, #0]
    e23c:	4b09      	ldr	r3, [pc, #36]	; (e264 <nrfx_clock_start+0x58>)
    e23e:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e242:	2201      	movs	r2, #1
    e244:	609a      	str	r2, [r3, #8]
}
    e246:	4770      	bx	lr
    p_reg->LFCLKSRC = (uint32_t)(source);
    e248:	2301      	movs	r3, #1
    e24a:	f8c1 3518 	str.w	r3, [r1, #1304]	; 0x518
}
    e24e:	e7f0      	b.n	e232 <nrfx_clock_start+0x26>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e250:	2200      	movs	r2, #0
    e252:	4b06      	ldr	r3, [pc, #24]	; (e26c <nrfx_clock_start+0x60>)
    e254:	601a      	str	r2, [r3, #0]
    e256:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    e258:	4b02      	ldr	r3, [pc, #8]	; (e264 <nrfx_clock_start+0x58>)
    e25a:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e25e:	6018      	str	r0, [r3, #0]
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    e260:	4770      	bx	lr
    e262:	bf00      	nop
    e264:	40005000 	.word	0x40005000
    e268:	40005104 	.word	0x40005104
    e26c:	40005100 	.word	0x40005100

0000e270 <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
    e270:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    e272:	b110      	cbz	r0, e27a <nrfx_clock_stop+0xa>
    e274:	2801      	cmp	r0, #1
    e276:	d016      	beq.n	e2a6 <nrfx_clock_stop+0x36>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    e278:	bd38      	pop	{r3, r4, r5, pc}
    p_reg->INTENCLR = mask;
    e27a:	2202      	movs	r2, #2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e27c:	2101      	movs	r1, #1
    e27e:	f242 7510 	movw	r5, #10000	; 0x2710
    p_reg->INTENCLR = mask;
    e282:	4c16      	ldr	r4, [pc, #88]	; (e2dc <nrfx_clock_stop+0x6c>)
    e284:	f8c4 2308 	str.w	r2, [r4, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e288:	4a15      	ldr	r2, [pc, #84]	; (e2e0 <nrfx_clock_stop+0x70>)
    e28a:	6010      	str	r0, [r2, #0]
    e28c:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e28e:	4a15      	ldr	r2, [pc, #84]	; (e2e4 <nrfx_clock_stop+0x74>)
    e290:	6011      	str	r1, [r2, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    e292:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
    e296:	03db      	lsls	r3, r3, #15
    e298:	d5ee      	bpl.n	e278 <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    e29a:	2001      	movs	r0, #1
    e29c:	f001 fcaf 	bl	fbfe <nrfx_busy_wait>
    e2a0:	3d01      	subs	r5, #1
    e2a2:	d1f6      	bne.n	e292 <nrfx_clock_stop+0x22>
    e2a4:	e7e8      	b.n	e278 <nrfx_clock_stop+0x8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e2a6:	2200      	movs	r2, #0
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e2a8:	f242 7510 	movw	r5, #10000	; 0x2710
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e2ac:	4b0e      	ldr	r3, [pc, #56]	; (e2e8 <nrfx_clock_stop+0x78>)
    p_reg->INTENCLR = mask;
    e2ae:	4c0b      	ldr	r4, [pc, #44]	; (e2dc <nrfx_clock_stop+0x6c>)
    e2b0:	f8c4 0308 	str.w	r0, [r4, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e2b4:	601a      	str	r2, [r3, #0]
    e2b6:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e2b8:	4b0c      	ldr	r3, [pc, #48]	; (e2ec <nrfx_clock_stop+0x7c>)
    e2ba:	6018      	str	r0, [r3, #0]
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    e2bc:	f8d4 340c 	ldr.w	r3, [r4, #1036]	; 0x40c
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    e2c0:	f8d4 240c 	ldr.w	r2, [r4, #1036]	; 0x40c
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    e2c4:	f003 0301 	and.w	r3, r3, #1
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    e2c8:	03d2      	lsls	r2, r2, #15
    e2ca:	d5d5      	bpl.n	e278 <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
    e2cc:	2b00      	cmp	r3, #0
    e2ce:	d0d3      	beq.n	e278 <nrfx_clock_stop+0x8>
    e2d0:	2001      	movs	r0, #1
    e2d2:	f001 fc94 	bl	fbfe <nrfx_busy_wait>
    e2d6:	3d01      	subs	r5, #1
    e2d8:	d1f0      	bne.n	e2bc <nrfx_clock_stop+0x4c>
    e2da:	e7cd      	b.n	e278 <nrfx_clock_stop+0x8>
    e2dc:	40005000 	.word	0x40005000
    e2e0:	40005104 	.word	0x40005104
    e2e4:	4000500c 	.word	0x4000500c
    e2e8:	40005100 	.word	0x40005100
    e2ec:	40005004 	.word	0x40005004

0000e2f0 <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    e2f0:	4b15      	ldr	r3, [pc, #84]	; (e348 <nrfx_power_clock_irq_handler+0x58>)
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    e2f2:	b510      	push	{r4, lr}
    e2f4:	681a      	ldr	r2, [r3, #0]
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    e2f6:	b14a      	cbz	r2, e30c <nrfx_power_clock_irq_handler+0x1c>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e2f8:	2000      	movs	r0, #0
    p_reg->INTENCLR = mask;
    e2fa:	2201      	movs	r2, #1
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e2fc:	6018      	str	r0, [r3, #0]
    e2fe:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    e300:	4b12      	ldr	r3, [pc, #72]	; (e34c <nrfx_power_clock_irq_handler+0x5c>)
    e302:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    e306:	4b12      	ldr	r3, [pc, #72]	; (e350 <nrfx_power_clock_irq_handler+0x60>)
    e308:	681b      	ldr	r3, [r3, #0]
    e30a:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    e30c:	4b11      	ldr	r3, [pc, #68]	; (e354 <nrfx_power_clock_irq_handler+0x64>)
    e30e:	681a      	ldr	r2, [r3, #0]
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    e310:	b182      	cbz	r2, e334 <nrfx_power_clock_irq_handler+0x44>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e312:	2200      	movs	r2, #0
    e314:	601a      	str	r2, [r3, #0]
    e316:	681b      	ldr	r3, [r3, #0]
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    e318:	4b0c      	ldr	r3, [pc, #48]	; (e34c <nrfx_power_clock_irq_handler+0x5c>)
    e31a:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    e31e:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    e322:	f002 0203 	and.w	r2, r2, #3
    e326:	2a01      	cmp	r2, #1
    e328:	f04f 0102 	mov.w	r1, #2
    e32c:	d103      	bne.n	e336 <nrfx_power_clock_irq_handler+0x46>
    p_reg->LFCLKSRC = (uint32_t)(source);
    e32e:	f8c3 1518 	str.w	r1, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e332:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    e334:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    e336:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    e33a:	4b05      	ldr	r3, [pc, #20]	; (e350 <nrfx_power_clock_irq_handler+0x60>)
    e33c:	2001      	movs	r0, #1
}
    e33e:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    e342:	681b      	ldr	r3, [r3, #0]
    e344:	4718      	bx	r3
    e346:	bf00      	nop
    e348:	40005100 	.word	0x40005100
    e34c:	40005000 	.word	0x40005000
    e350:	200102b0 	.word	0x200102b0
    e354:	40005104 	.word	0x40005104

0000e358 <nrfx_spim_init>:

nrfx_err_t nrfx_spim_init(nrfx_spim_t const *        p_instance,
                          nrfx_spim_config_t const * p_config,
                          nrfx_spim_evt_handler_t    handler,
                          void *                     p_context)
{
    e358:	4694      	mov	ip, r2
    NRFX_ASSERT(p_config);
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    nrfx_err_t err_code;

    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    e35a:	2224      	movs	r2, #36	; 0x24
{
    e35c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    e360:	7905      	ldrb	r5, [r0, #4]
    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    e362:	4e4c      	ldr	r6, [pc, #304]	; (e494 <nrfx_spim_init+0x13c>)
    e364:	436a      	muls	r2, r5
    e366:	18b4      	adds	r4, r6, r2
    e368:	7f27      	ldrb	r7, [r4, #28]
    e36a:	2f00      	cmp	r7, #0
    e36c:	f040 8090 	bne.w	e490 <nrfx_spim_init+0x138>
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
#endif

    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg;
    e370:	6800      	ldr	r0, [r0, #0]
        return err_code;
    }
#endif // NRFX_CHECK(NRFX_PRS_ENABLED)

    p_cb->handler = handler;
    p_cb->p_context = p_context;
    e372:	6063      	str	r3, [r4, #4]
    e374:	2401      	movs	r4, #1
    e376:	2701      	movs	r7, #1
    p_cb->handler = handler;
    e378:	f846 c002 	str.w	ip, [r6, r2]
    // Configure pins used by the peripheral:
    // - SCK - output with initial value corresponding with the SPI mode used:
    //   0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1);
    //   according to the reference manual guidelines this pin and its input
    //   buffer must always be connected for the SPI to work.
    if (p_config->mode <= NRF_SPIM_MODE_1)
    e37c:	f891 8000 	ldrb.w	r8, [r1]
    e380:	f891 e00c 	ldrb.w	lr, [r1, #12]
    e384:	4b44      	ldr	r3, [pc, #272]	; (e498 <nrfx_spim_init+0x140>)
    p_reg->OUTCLR = clr_mask;
    e386:	f008 021f 	and.w	r2, r8, #31
    e38a:	4094      	lsls	r4, r2
    e38c:	f1be 0f01 	cmp.w	lr, #1
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    e390:	f102 0280 	add.w	r2, r2, #128	; 0x80
    p_reg->OUTCLR = clr_mask;
    e394:	bf94      	ite	ls
    e396:	60dc      	strls	r4, [r3, #12]
    p_reg->OUTSET = set_mask;
    e398:	609c      	strhi	r4, [r3, #8]
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    e39a:	f843 7022 	str.w	r7, [r3, r2, lsl #2]
                 NRF_GPIO_PIN_INPUT_CONNECT,
                 NRF_GPIO_PIN_NOPULL,
                 NRF_GPIO_PIN_S0S1,
                 NRF_GPIO_PIN_NOSENSE);
    // - MOSI (optional) - output with initial value 0,
    if (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED)
    e39e:	784a      	ldrb	r2, [r1, #1]
    e3a0:	2aff      	cmp	r2, #255	; 0xff
    *p_pin = pin_number & 0x1F;
    e3a2:	bf1f      	itttt	ne
    e3a4:	f002 041f 	andne.w	r4, r2, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    e3a8:	40a7      	lslne	r7, r4
    p_reg->OUTCLR = clr_mask;
    e3aa:	60df      	strne	r7, [r3, #12]
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    e3ac:	2703      	movne	r7, #3
    e3ae:	bf1c      	itt	ne
    e3b0:	3480      	addne	r4, #128	; 0x80
    e3b2:	f843 7024 	strne.w	r7, [r3, r4, lsl #2]
    else
    {
        mosi_pin = NRF_SPIM_PIN_NOT_CONNECTED;
    }
    // - MISO (optional) - input,
    if (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED)
    e3b6:	788f      	ldrb	r7, [r1, #2]
        mosi_pin = NRF_SPIM_PIN_NOT_CONNECTED;
    e3b8:	bf08      	it	eq
    e3ba:	f04f 32ff 	moveq.w	r2, #4294967295
    if (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED)
    e3be:	2fff      	cmp	r7, #255	; 0xff
                               | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)
    e3c0:	bf1f      	itttt	ne
    e3c2:	f891 900e 	ldrbne.w	r9, [r1, #14]
    *p_pin = pin_number & 0x1F;
    e3c6:	f007 041f 	andne.w	r4, r7, #31
                               | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)
    e3ca:	ea4f 0989 	movne.w	r9, r9, lsl #2
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    e3ce:	3480      	addne	r4, #128	; 0x80
    e3d0:	bf18      	it	ne
    e3d2:	f843 9024 	strne.w	r9, [r3, r4, lsl #2]
    }
    // - Slave Select (optional) - output with initial value 1 (inactive).

    // 'p_cb->ss_pin' variable is used during transfers to check if SS pin should be toggled,
    // so this field needs to be initialized even if the pin is not used.
    p_cb->ss_pin = p_config->ss_pin;
    e3d6:	f04f 0924 	mov.w	r9, #36	; 0x24
    e3da:	fb09 6905 	mla	r9, r9, r5, r6
    e3de:	78cc      	ldrb	r4, [r1, #3]
        miso_pin = NRF_SPIM_PIN_NOT_CONNECTED;
    e3e0:	bf08      	it	eq
    e3e2:	f04f 37ff 	moveq.w	r7, #4294967295

    if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    e3e6:	2cff      	cmp	r4, #255	; 0xff
    p_cb->ss_pin = p_config->ss_pin;
    e3e8:	f889 401f 	strb.w	r4, [r9, #31]
    if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    e3ec:	d016      	beq.n	e41c <nrfx_spim_init+0xc4>
    {
        if (p_config->ss_active_high)
    e3ee:	f04f 0a01 	mov.w	sl, #1
    e3f2:	f891 9004 	ldrb.w	r9, [r1, #4]
    e3f6:	f004 041f 	and.w	r4, r4, #31
    e3fa:	fa0a fa04 	lsl.w	sl, sl, r4
    e3fe:	f1b9 0f00 	cmp.w	r9, #0
    e402:	d03c      	beq.n	e47e <nrfx_spim_init+0x126>
    p_reg->OUTCLR = clr_mask;
    e404:	f8c3 a00c 	str.w	sl, [r3, #12]
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    e408:	f04f 0a03 	mov.w	sl, #3
    e40c:	3480      	adds	r4, #128	; 0x80
    e40e:	f843 a024 	str.w	sl, [r3, r4, lsl #2]
                                   (p_config->ss_active_high == true ?
                                        NRF_SPIM_CSN_POL_HIGH : NRF_SPIM_CSN_POL_LOW),
                                   p_config->ss_duration);
        }
#endif
        p_cb->ss_active_high = p_config->ss_active_high;
    e412:	2324      	movs	r3, #36	; 0x24
    e414:	fb03 6305 	mla	r3, r3, r5, r6
    e418:	f883 901e 	strb.w	r9, [r3, #30]
    p_reg->FREQUENCY = (uint32_t)frequency;
    e41c:	688b      	ldr	r3, [r1, #8]
    p_reg->PSEL.SCK  = sck_pin;
    e41e:	f8c0 8508 	str.w	r8, [r0, #1288]	; 0x508
    p_reg->PSEL.MOSI = mosi_pin;
    e422:	f8c0 250c 	str.w	r2, [r0, #1292]	; 0x50c
    p_reg->PSEL.MISO = miso_pin;
    e426:	f8c0 7510 	str.w	r7, [r0, #1296]	; 0x510
    p_reg->FREQUENCY = (uint32_t)frequency;
    e42a:	f8c0 3524 	str.w	r3, [r0, #1316]	; 0x524
        SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
    e42e:	7b4b      	ldrb	r3, [r1, #13]
    e430:	3b00      	subs	r3, #0
    e432:	bf18      	it	ne
    e434:	2301      	movne	r3, #1
    switch (spi_mode)
    e436:	f1be 0f02 	cmp.w	lr, #2
    e43a:	d023      	beq.n	e484 <nrfx_spim_init+0x12c>
    e43c:	f1be 0f03 	cmp.w	lr, #3
    e440:	d023      	beq.n	e48a <nrfx_spim_init+0x132>
    e442:	f1be 0f01 	cmp.w	lr, #1
    e446:	d101      	bne.n	e44c <nrfx_spim_init+0xf4>
        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
    e448:	f043 0302 	orr.w	r3, r3, #2
    p_reg->CONFIG = config;
    e44c:	f8c0 3554 	str.w	r3, [r0, #1364]	; 0x554
}

NRF_STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
                                        uint8_t         orc)
{
    p_reg->ORC = orc;
    e450:	798b      	ldrb	r3, [r1, #6]
    e452:	f8c0 35c0 	str.w	r3, [r0, #1472]	; 0x5c0
    p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
    e456:	2307      	movs	r3, #7
    e458:	f8c0 3500 	str.w	r3, [r0, #1280]	; 0x500

    nrf_spim_orc_set(p_spim, p_config->orc);

    nrf_spim_enable(p_spim);

    if (p_cb->handler)
    e45c:	f1bc 0f00 	cmp.w	ip, #0
    e460:	d003      	beq.n	e46a <nrfx_spim_init+0x112>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg),
            p_config->irq_priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg));
    e462:	f340 3007 	sbfx	r0, r0, #12, #8
    e466:	f7fe fe0f 	bl	d088 <arch_irq_enable>
    }

    p_cb->transfer_in_progress = false;
    e46a:	2324      	movs	r3, #36	; 0x24
    e46c:	fb03 6505 	mla	r5, r3, r5, r6
    e470:	2300      	movs	r3, #0
    e472:	776b      	strb	r3, [r5, #29]
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    e474:	2301      	movs	r3, #1

    err_code = NRFX_SUCCESS;
    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
    e476:	4809      	ldr	r0, [pc, #36]	; (e49c <nrfx_spim_init+0x144>)
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    e478:	772b      	strb	r3, [r5, #28]
}
    e47a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    p_reg->OUTSET = set_mask;
    e47e:	f8c3 a008 	str.w	sl, [r3, #8]
}
    e482:	e7c1      	b.n	e408 <nrfx_spim_init+0xb0>
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
    e484:	f043 0304 	orr.w	r3, r3, #4
        break;
    e488:	e7e0      	b.n	e44c <nrfx_spim_init+0xf4>
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
    e48a:	f043 0306 	orr.w	r3, r3, #6
        break;
    e48e:	e7dd      	b.n	e44c <nrfx_spim_init+0xf4>
        return err_code;
    e490:	4803      	ldr	r0, [pc, #12]	; (e4a0 <nrfx_spim_init+0x148>)
    e492:	e7f2      	b.n	e47a <nrfx_spim_init+0x122>
    e494:	200102b8 	.word	0x200102b8
    e498:	40842500 	.word	0x40842500
    e49c:	0bad0000 	.word	0x0bad0000
    e4a0:	0bad0005 	.word	0x0bad0005

0000e4a4 <nrfx_spim_xfer>:
    NRFX_ASSERT(!(flags & NRFX_SPIM_FLAG_HOLD_XFER) ||
                (p_cb->ss_pin == NRFX_SPIM_PIN_NOT_USED));

    nrfx_err_t err_code = NRFX_SUCCESS;

    if (p_cb->transfer_in_progress)
    e4a4:	2324      	movs	r3, #36	; 0x24
{
    e4a6:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    e4aa:	7906      	ldrb	r6, [r0, #4]
    if (p_cb->transfer_in_progress)
    e4ac:	4f43      	ldr	r7, [pc, #268]	; (e5bc <nrfx_spim_xfer+0x118>)
    e4ae:	4373      	muls	r3, r6
{
    e4b0:	4614      	mov	r4, r2
    if (p_cb->transfer_in_progress)
    e4b2:	18fa      	adds	r2, r7, r3
{
    e4b4:	460d      	mov	r5, r1
    if (p_cb->transfer_in_progress)
    e4b6:	7f51      	ldrb	r1, [r2, #29]
{
    e4b8:	4686      	mov	lr, r0
    if (p_cb->transfer_in_progress)
    e4ba:	2900      	cmp	r1, #0
    e4bc:	d17b      	bne.n	e5b6 <nrfx_spim_xfer+0x112>
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
    else
    {
        if (p_cb->handler && !(flags & (NRFX_SPIM_FLAG_REPEATED_XFER |
    e4be:	58fb      	ldr	r3, [r7, r3]
    e4c0:	b123      	cbz	r3, e4cc <nrfx_spim_xfer+0x28>
    e4c2:	f014 0f14 	tst.w	r4, #20
                                        NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER)))
        {
            p_cb->transfer_in_progress = true;
    e4c6:	bf04      	itt	eq
    e4c8:	2301      	moveq	r3, #1
    e4ca:	7753      	strbeq	r3, [r2, #29]
        }
    }

    p_cb->evt.xfer_desc = *p_xfer_desc;
    e4cc:	f04f 0c24 	mov.w	ip, #36	; 0x24
    e4d0:	e895 000f 	ldmia.w	r5, {r0, r1, r2, r3}
    e4d4:	fb0c 7c06 	mla	ip, ip, r6, r7
    e4d8:	f10c 080c 	add.w	r8, ip, #12
    e4dc:	e888 000f 	stmia.w	r8, {r0, r1, r2, r3}

    if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    e4e0:	f89c 301f 	ldrb.w	r3, [ip, #31]
    e4e4:	2bff      	cmp	r3, #255	; 0xff
    e4e6:	d008      	beq.n	e4fa <nrfx_spim_xfer+0x56>
    {
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
        if (!p_cb->use_hw_ss)
#endif
        {
            if (p_cb->ss_active_high)
    e4e8:	f003 021f 	and.w	r2, r3, #31
    e4ec:	2301      	movs	r3, #1
    e4ee:	f89c 101e 	ldrb.w	r1, [ip, #30]
    e4f2:	4093      	lsls	r3, r2
    e4f4:	4a32      	ldr	r2, [pc, #200]	; (e5c0 <nrfx_spim_xfer+0x11c>)
    e4f6:	b1b1      	cbz	r1, e526 <nrfx_spim_xfer+0x82>
    p_reg->OUTSET = set_mask;
    e4f8:	6093      	str	r3, [r2, #8]
    if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) ||
    e4fa:	6829      	ldr	r1, [r5, #0]
    e4fc:	b121      	cbz	r1, e508 <nrfx_spim_xfer+0x64>
    e4fe:	f001 4360 	and.w	r3, r1, #3758096384	; 0xe0000000
    e502:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
    e506:	d106      	bne.n	e516 <nrfx_spim_xfer+0x72>
        (p_xfer_desc->p_rx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_rx_buffer)))
    e508:	68aa      	ldr	r2, [r5, #8]
    if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) ||
    e50a:	b172      	cbz	r2, e52a <nrfx_spim_xfer+0x86>
    e50c:	f002 4360 	and.w	r3, r2, #3758096384	; 0xe0000000
        (p_xfer_desc->p_rx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_rx_buffer)))
    e510:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
    e514:	d009      	beq.n	e52a <nrfx_spim_xfer+0x86>
        p_cb->transfer_in_progress = false;
    e516:	2324      	movs	r3, #36	; 0x24
    e518:	fb03 7606 	mla	r6, r3, r6, r7
    e51c:	2300      	movs	r3, #0
        return err_code;
    e51e:	4829      	ldr	r0, [pc, #164]	; (e5c4 <nrfx_spim_xfer+0x120>)
        p_cb->transfer_in_progress = false;
    e520:	7773      	strb	r3, [r6, #29]
            }
        }
    }

    return spim_xfer(p_instance->p_reg, p_cb,  p_xfer_desc, flags);
}
    e522:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    p_reg->OUTCLR = clr_mask;
    e526:	60d3      	str	r3, [r2, #12]
}
    e528:	e7e7      	b.n	e4fa <nrfx_spim_xfer+0x56>
    return spim_xfer(p_instance->p_reg, p_cb,  p_xfer_desc, flags);
    e52a:	f8de 3000 	ldr.w	r3, [lr]
    nrf_spim_tx_buffer_set(p_spim, p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length);
    e52e:	6868      	ldr	r0, [r5, #4]
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    e530:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
    nrf_spim_rx_buffer_set(p_spim, p_xfer_desc->p_rx_buffer, p_xfer_desc->rx_length);
    e534:	68e9      	ldr	r1, [r5, #12]
    p_reg->TXD.MAXCNT = length;
    e536:	f8c3 0548 	str.w	r0, [r3, #1352]	; 0x548
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    e53a:	f8c3 2534 	str.w	r2, [r3, #1332]	; 0x534
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e53e:	2200      	movs	r2, #0
    p_reg->RXD.MAXCNT = length;
    e540:	f8c3 1538 	str.w	r1, [r3, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e544:	f8c3 2118 	str.w	r2, [r3, #280]	; 0x118
    e548:	f8d3 2118 	ldr.w	r2, [r3, #280]	; 0x118
    if (NRFX_SPIM_FLAG_TX_POSTINC & flags)
    e54c:	f014 0201 	ands.w	r2, r4, #1
}


NRF_STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)
{
    p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_ArrayList << SPIM_TXD_LIST_LIST_Pos;
    e550:	bf18      	it	ne
    e552:	2201      	movne	r2, #1
}

NRF_STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)
{
    p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_Disabled << SPIM_TXD_LIST_LIST_Pos;
    e554:	f8c3 2550 	str.w	r2, [r3, #1360]	; 0x550
    if (NRFX_SPIM_FLAG_RX_POSTINC & flags)
    e558:	f014 0202 	ands.w	r2, r4, #2
}

NRF_STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)
{
    p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_ArrayList << SPIM_RXD_LIST_LIST_Pos;
    e55c:	bf18      	it	ne
    e55e:	2201      	movne	r2, #1
    if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER))
    e560:	f014 0108 	ands.w	r1, r4, #8
}

NRF_STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)
{
    p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_Disabled << SPIM_RXD_LIST_LIST_Pos;
    e564:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e568:	bf04      	itt	eq
    e56a:	2201      	moveq	r2, #1
    e56c:	611a      	streq	r2, [r3, #16]
    if (!p_cb->handler)
    e56e:	2224      	movs	r2, #36	; 0x24
    e570:	4372      	muls	r2, r6
    e572:	58ba      	ldr	r2, [r7, r2]
    e574:	b9b2      	cbnz	r2, e5a4 <nrfx_spim_xfer+0x100>
        if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER))
    e576:	b919      	cbnz	r1, e580 <nrfx_spim_xfer+0xdc>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    e578:	f8d3 2118 	ldr.w	r2, [r3, #280]	; 0x118
            while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END))
    e57c:	2a00      	cmp	r2, #0
    e57e:	d0fb      	beq.n	e578 <nrfx_spim_xfer+0xd4>
        if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    e580:	2324      	movs	r3, #36	; 0x24
    e582:	fb03 7606 	mla	r6, r3, r6, r7
    e586:	7ff3      	ldrb	r3, [r6, #31]
    e588:	2bff      	cmp	r3, #255	; 0xff
    e58a:	d007      	beq.n	e59c <nrfx_spim_xfer+0xf8>
                if (p_cb->ss_active_high)
    e58c:	f003 021f 	and.w	r2, r3, #31
    e590:	2301      	movs	r3, #1
    e592:	7fb1      	ldrb	r1, [r6, #30]
    e594:	4093      	lsls	r3, r2
    e596:	4a0a      	ldr	r2, [pc, #40]	; (e5c0 <nrfx_spim_xfer+0x11c>)
    e598:	b111      	cbz	r1, e5a0 <nrfx_spim_xfer+0xfc>
    p_reg->OUTCLR = clr_mask;
    e59a:	60d3      	str	r3, [r2, #12]
    return err_code;
    e59c:	480a      	ldr	r0, [pc, #40]	; (e5c8 <nrfx_spim_xfer+0x124>)
    e59e:	e7c0      	b.n	e522 <nrfx_spim_xfer+0x7e>
    p_reg->OUTSET = set_mask;
    e5a0:	6093      	str	r3, [r2, #8]
    e5a2:	e7fb      	b.n	e59c <nrfx_spim_xfer+0xf8>
    if (!enable)
    e5a4:	2240      	movs	r2, #64	; 0x40
    e5a6:	f014 0f04 	tst.w	r4, #4
    p_reg->INTENCLR = mask;
    e5aa:	bf14      	ite	ne
    e5ac:	f8c3 2308 	strne.w	r2, [r3, #776]	; 0x308
    p_reg->INTENSET = mask;
    e5b0:	f8c3 2304 	streq.w	r2, [r3, #772]	; 0x304
    e5b4:	e7f2      	b.n	e59c <nrfx_spim_xfer+0xf8>
        return err_code;
    e5b6:	4805      	ldr	r0, [pc, #20]	; (e5cc <nrfx_spim_xfer+0x128>)
    e5b8:	e7b3      	b.n	e522 <nrfx_spim_xfer+0x7e>
    e5ba:	bf00      	nop
    e5bc:	200102b8 	.word	0x200102b8
    e5c0:	40842500 	.word	0x40842500
    e5c4:	0bad000a 	.word	0x0bad000a
    e5c8:	0bad0000 	.word	0x0bad0000
    e5cc:	0bad000b 	.word	0x0bad000b

0000e5d0 <nrfx_spim_3_irq_handler>:
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    e5d0:	4b0f      	ldr	r3, [pc, #60]	; (e610 <nrfx_spim_3_irq_handler+0x40>)
    e5d2:	f8d3 2118 	ldr.w	r2, [r3, #280]	; 0x118
        nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_START);
        return;
    }
#endif

    if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END))
    e5d6:	b1ca      	cbz	r2, e60c <nrfx_spim_3_irq_handler+0x3c>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e5d8:	2200      	movs	r2, #0
    e5da:	f8c3 2118 	str.w	r2, [r3, #280]	; 0x118
    e5de:	f8d3 3118 	ldr.w	r3, [r3, #280]	; 0x118
    if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    e5e2:	4b0c      	ldr	r3, [pc, #48]	; (e614 <nrfx_spim_3_irq_handler+0x44>)
    e5e4:	7fda      	ldrb	r2, [r3, #31]
    e5e6:	2aff      	cmp	r2, #255	; 0xff
    e5e8:	d007      	beq.n	e5fa <nrfx_spim_3_irq_handler+0x2a>
            if (p_cb->ss_active_high)
    e5ea:	f002 011f 	and.w	r1, r2, #31
    e5ee:	2201      	movs	r2, #1
    e5f0:	7f98      	ldrb	r0, [r3, #30]
    e5f2:	408a      	lsls	r2, r1
    e5f4:	4908      	ldr	r1, [pc, #32]	; (e618 <nrfx_spim_3_irq_handler+0x48>)
    e5f6:	b138      	cbz	r0, e608 <nrfx_spim_3_irq_handler+0x38>
    p_reg->OUTCLR = clr_mask;
    e5f8:	60ca      	str	r2, [r1, #12]
    p_cb->transfer_in_progress = false;
    e5fa:	2200      	movs	r2, #0
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    e5fc:	4807      	ldr	r0, [pc, #28]	; (e61c <nrfx_spim_3_irq_handler+0x4c>)
    p_cb->transfer_in_progress = false;
    e5fe:	775a      	strb	r2, [r3, #29]
    p_cb->evt.type = NRFX_SPIM_EVENT_DONE;
    e600:	721a      	strb	r2, [r3, #8]
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    e602:	e9d3 2100 	ldrd	r2, r1, [r3]
    e606:	4710      	bx	r2
    p_reg->OUTSET = set_mask;
    e608:	608a      	str	r2, [r1, #8]
}
    e60a:	e7f6      	b.n	e5fa <nrfx_spim_3_irq_handler+0x2a>

#if NRFX_CHECK(NRFX_SPIM3_ENABLED)
void nrfx_spim_3_irq_handler(void)
{
    irq_handler(NRF_SPIM3, &m_cb[NRFX_SPIM3_INST_IDX]);
}
    e60c:	4770      	bx	lr
    e60e:	bf00      	nop
    e610:	4000b000 	.word	0x4000b000
    e614:	200102b8 	.word	0x200102b8
    e618:	40842500 	.word	0x40842500
    e61c:	200102c0 	.word	0x200102c0

0000e620 <z_sys_init_run_level>:
 * off and the next one begins.
 *
 * @param level init level to run.
 */
void z_sys_init_run_level(int32_t level)
{
    e620:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    e622:	4b10      	ldr	r3, [pc, #64]	; (e664 <z_sys_init_run_level+0x44>)
			/* Initialization failed.
			 * Set the init status bit so device is not declared ready.
			 */
			sys_bitfield_set_bit(
				(mem_addr_t) __device_init_status_start,
				(dev - __device_start));
    e624:	4f10      	ldr	r7, [pc, #64]	; (e668 <z_sys_init_run_level+0x48>)
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    e626:	f853 5020 	ldr.w	r5, [r3, r0, lsl #2]
    e62a:	3001      	adds	r0, #1
    e62c:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    e630:	42ae      	cmp	r6, r5
    e632:	d800      	bhi.n	e636 <z_sys_init_run_level+0x16>
		}
	}
}
    e634:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		if ((entry->init(dev) != 0) && (dev != NULL)) {
    e636:	e9d5 3400 	ldrd	r3, r4, [r5]
    e63a:	4620      	mov	r0, r4
    e63c:	4798      	blx	r3
    e63e:	b170      	cbz	r0, e65e <z_sys_init_run_level+0x3e>
    e640:	b16c      	cbz	r4, e65e <z_sys_init_run_level+0x3e>

static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit)
{
	uint32_t temp = *(volatile uint32_t *)addr;

	*(volatile uint32_t *)addr = temp | (1 << bit);
    e642:	2301      	movs	r3, #1
				(dev - __device_start));
    e644:	1be4      	subs	r4, r4, r7
	void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
{
	/* Doing memory offsets in terms of 32-bit values to prevent
	 * alignment issues
	 */
	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    e646:	4a09      	ldr	r2, [pc, #36]	; (e66c <z_sys_init_run_level+0x4c>)
    e648:	1124      	asrs	r4, r4, #4
    e64a:	0961      	lsrs	r1, r4, #5
	uint32_t temp = *(volatile uint32_t *)addr;
    e64c:	f852 0021 	ldr.w	r0, [r2, r1, lsl #2]
	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    e650:	f004 041f 	and.w	r4, r4, #31
	*(volatile uint32_t *)addr = temp | (1 << bit);
    e654:	fa03 f404 	lsl.w	r4, r3, r4
    e658:	4304      	orrs	r4, r0
    e65a:	f842 4021 	str.w	r4, [r2, r1, lsl #2]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    e65e:	3508      	adds	r5, #8
    e660:	e7e6      	b.n	e630 <z_sys_init_run_level+0x10>
    e662:	bf00      	nop
    e664:	000101f4 	.word	0x000101f4
    e668:	20010098 	.word	0x20010098
    e66c:	200100f8 	.word	0x200100f8

0000e670 <z_device_ready>:

bool z_device_ready(const struct device *dev)
{
	/* Set bit indicates device failed initialization */
	return !(sys_bitfield_test_bit((mem_addr_t)__device_init_status_start,
					(dev - __device_start)));
    e670:	4b08      	ldr	r3, [pc, #32]	; (e694 <z_device_ready+0x24>)
    e672:	1ac0      	subs	r0, r0, r3
    e674:	1100      	asrs	r0, r0, #4
}

static ALWAYS_INLINE
	int sys_bitfield_test_bit(mem_addr_t addr, unsigned int bit)
{
	return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    e676:	4b08      	ldr	r3, [pc, #32]	; (e698 <z_device_ready+0x28>)
    e678:	0942      	lsrs	r2, r0, #5
	uint32_t temp = *(volatile uint32_t *)addr;
    e67a:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
	return temp & (1 << bit);
    e67e:	2301      	movs	r3, #1
	return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    e680:	f000 001f 	and.w	r0, r0, #31
	return temp & (1 << bit);
    e684:	fa03 f000 	lsl.w	r0, r3, r0
	return !(sys_bitfield_test_bit((mem_addr_t)__device_init_status_start,
    e688:	4210      	tst	r0, r2
}
    e68a:	bf0c      	ite	eq
    e68c:	4618      	moveq	r0, r3
    e68e:	2000      	movne	r0, #0
    e690:	4770      	bx	lr
    e692:	bf00      	nop
    e694:	20010098 	.word	0x20010098
    e698:	200100f8 	.word	0x200100f8

0000e69c <z_impl_device_get_binding>:
	for (dev = __device_start; dev != __device_end; dev++) {
    e69c:	4911      	ldr	r1, [pc, #68]	; (e6e4 <z_impl_device_get_binding+0x48>)
{
    e69e:	b570      	push	{r4, r5, r6, lr}
    e6a0:	4605      	mov	r5, r0
    e6a2:	460e      	mov	r6, r1
	for (dev = __device_start; dev != __device_end; dev++) {
    e6a4:	4c10      	ldr	r4, [pc, #64]	; (e6e8 <z_impl_device_get_binding+0x4c>)
    e6a6:	428c      	cmp	r4, r1
    e6a8:	d104      	bne.n	e6b4 <z_impl_device_get_binding+0x18>
	for (dev = __device_start; dev != __device_end; dev++) {
    e6aa:	4c0f      	ldr	r4, [pc, #60]	; (e6e8 <z_impl_device_get_binding+0x4c>)
    e6ac:	42b4      	cmp	r4, r6
    e6ae:	d10a      	bne.n	e6c6 <z_impl_device_get_binding+0x2a>
	return NULL;
    e6b0:	2400      	movs	r4, #0
    e6b2:	e014      	b.n	e6de <z_impl_device_get_binding+0x42>
		if (z_device_ready(dev) && (dev->name == name)) {
    e6b4:	4620      	mov	r0, r4
    e6b6:	f7ff ffdb 	bl	e670 <z_device_ready>
    e6ba:	b110      	cbz	r0, e6c2 <z_impl_device_get_binding+0x26>
    e6bc:	6823      	ldr	r3, [r4, #0]
    e6be:	42ab      	cmp	r3, r5
    e6c0:	d00d      	beq.n	e6de <z_impl_device_get_binding+0x42>
	for (dev = __device_start; dev != __device_end; dev++) {
    e6c2:	3410      	adds	r4, #16
    e6c4:	e7ef      	b.n	e6a6 <z_impl_device_get_binding+0xa>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    e6c6:	4620      	mov	r0, r4
    e6c8:	f7ff ffd2 	bl	e670 <z_device_ready>
    e6cc:	b908      	cbnz	r0, e6d2 <z_impl_device_get_binding+0x36>
	for (dev = __device_start; dev != __device_end; dev++) {
    e6ce:	3410      	adds	r4, #16
    e6d0:	e7ec      	b.n	e6ac <z_impl_device_get_binding+0x10>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    e6d2:	4628      	mov	r0, r5
    e6d4:	6821      	ldr	r1, [r4, #0]
    e6d6:	f001 f8e3 	bl	f8a0 <strcmp>
    e6da:	2800      	cmp	r0, #0
    e6dc:	d1f7      	bne.n	e6ce <z_impl_device_get_binding+0x32>
}
    e6de:	4620      	mov	r0, r4
    e6e0:	bd70      	pop	{r4, r5, r6, pc}
    e6e2:	bf00      	nop
    e6e4:	200100f8 	.word	0x200100f8
    e6e8:	20010098 	.word	0x20010098

0000e6ec <idle>:
#else
#define IDLE_YIELD_IF_COOP() do { } while (false)
#endif

void idle(void *unused1, void *unused2, void *unused3)
{
    e6ec:	b508      	push	{r3, lr}
	_kernel.idle = ticks;
    e6ee:	4d0b      	ldr	r5, [pc, #44]	; (e71c <idle+0x30>)
    e6f0:	f04f 0220 	mov.w	r2, #32
    e6f4:	f3ef 8311 	mrs	r3, BASEPRI
    e6f8:	f382 8811 	msr	BASEPRI, r2
    e6fc:	f3bf 8f6f 	isb	sy
	int32_t ticks = z_get_next_timeout_expiry();
    e700:	f001 fb71 	bl	fde6 <z_get_next_timeout_expiry>
	z_set_timeout_expiry((ticks < IDLE_THRESH) ? 1 : ticks, true);
    e704:	2101      	movs	r1, #1
	int32_t ticks = z_get_next_timeout_expiry();
    e706:	4604      	mov	r4, r0
	z_set_timeout_expiry((ticks < IDLE_THRESH) ? 1 : ticks, true);
    e708:	2802      	cmp	r0, #2
    e70a:	bfd8      	it	le
    e70c:	4608      	movle	r0, r1
    e70e:	f001 fb7a 	bl	fe06 <z_set_timeout_expiry>
	_kernel.idle = ticks;
    e712:	622c      	str	r4, [r5, #32]
	arch_cpu_idle();
    e714:	f7fe fd86 	bl	d224 <arch_cpu_idle>
}
    e718:	e7ea      	b.n	e6f0 <idle+0x4>
    e71a:	bf00      	nop
    e71c:	200102dc 	.word	0x200102dc

0000e720 <z_bss_zero>:
 *
 * @return N/A
 */
void z_bss_zero(void)
{
	(void)memset(__bss_start, 0, __bss_end - __bss_start);
    e720:	4802      	ldr	r0, [pc, #8]	; (e72c <z_bss_zero+0xc>)
    e722:	4a03      	ldr	r2, [pc, #12]	; (e730 <z_bss_zero+0x10>)
    e724:	2100      	movs	r1, #0
    e726:	1a12      	subs	r2, r2, r0
    e728:	f001 b901 	b.w	f92e <memset>
    e72c:	20010100 	.word	0x20010100
    e730:	20010324 	.word	0x20010324

0000e734 <z_data_copy>:
 * This routine copies the data section from ROM to RAM.
 *
 * @return N/A
 */
void z_data_copy(void)
{
    e734:	b508      	push	{r3, lr}
	(void)memcpy(&__data_ram_start, &__data_rom_start,
		 __data_ram_end - __data_ram_start);
    e736:	4806      	ldr	r0, [pc, #24]	; (e750 <z_data_copy+0x1c>)
	(void)memcpy(&__data_ram_start, &__data_rom_start,
    e738:	4a06      	ldr	r2, [pc, #24]	; (e754 <z_data_copy+0x20>)
    e73a:	4907      	ldr	r1, [pc, #28]	; (e758 <z_data_copy+0x24>)
    e73c:	1a12      	subs	r2, r2, r0
    e73e:	f001 f8cb 	bl	f8d8 <memcpy>
#else
	(void)memcpy(&_app_smem_start, &_app_smem_rom_start,
		 _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    e742:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	(void)memcpy(&_ramfunc_ram_start, &_ramfunc_rom_start,
    e746:	4a05      	ldr	r2, [pc, #20]	; (e75c <z_data_copy+0x28>)
    e748:	4905      	ldr	r1, [pc, #20]	; (e760 <z_data_copy+0x2c>)
    e74a:	4806      	ldr	r0, [pc, #24]	; (e764 <z_data_copy+0x30>)
    e74c:	f001 b8c4 	b.w	f8d8 <memcpy>
    e750:	20010000 	.word	0x20010000
    e754:	200100fc 	.word	0x200100fc
    e758:	00010350 	.word	0x00010350
    e75c:	00000000 	.word	0x00000000
    e760:	00010350 	.word	0x00010350
    e764:	20010000 	.word	0x20010000

0000e768 <bg_thread_main>:
	static const unsigned int boot_delay = CONFIG_BOOT_DELAY;
#else
	static const unsigned int boot_delay;
#endif

	z_sys_post_kernel = true;
    e768:	2201      	movs	r2, #1
{
    e76a:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    e76c:	4b0b      	ldr	r3, [pc, #44]	; (e79c <bg_thread_main+0x34>)

	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    e76e:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
    e770:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    e772:	f7ff ff55 	bl	e620 <z_sys_init_run_level>
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
    e776:	4a0a      	ldr	r2, [pc, #40]	; (e7a0 <bg_thread_main+0x38>)
    e778:	490a      	ldr	r1, [pc, #40]	; (e7a4 <bg_thread_main+0x3c>)
    e77a:	480b      	ldr	r0, [pc, #44]	; (e7a8 <bg_thread_main+0x40>)
    e77c:	f000 fe18 	bl	f3b0 <printk>
	__do_global_ctors_aux();
	__do_init_array_aux();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    e780:	2003      	movs	r0, #3
    e782:	f7ff ff4d 	bl	e620 <z_sys_init_run_level>

	z_init_static_threads();
    e786:	f000 fc2b 	bl	efe0 <z_init_static_threads>
	z_timestamp_main = k_cycle_get_32();
#endif

	extern void main(void);

	main();
    e78a:	f7fd ff15 	bl	c5b8 <main>

	/* Mark nonessenrial since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    e78e:	4a07      	ldr	r2, [pc, #28]	; (e7ac <bg_thread_main+0x44>)
    e790:	7b13      	ldrb	r3, [r2, #12]
    e792:	f023 0301 	bic.w	r3, r3, #1
    e796:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    e798:	bd08      	pop	{r3, pc}
    e79a:	bf00      	nop
    e79c:	20010320 	.word	0x20010320
    e7a0:	00010310 	.word	0x00010310
    e7a4:	00010311 	.word	0x00010311
    e7a8:	0001031d 	.word	0x0001031d
    e7ac:	20010180 	.word	0x20010180

0000e7b0 <z_cstart>:
 * cleared/zeroed.
 *
 * @return Does not return
 */
FUNC_NORETURN void z_cstart(void)
{
    e7b0:	e92d 4880 	stmdb	sp!, {r7, fp, lr}
 * @return N/A
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
		(uint32_t)(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) +
    e7b4:	4b34      	ldr	r3, [pc, #208]	; (e888 <z_cstart+0xd8>)
    e7b6:	b0a7      	sub	sp, #156	; 0x9c
	uint32_t msp =
    e7b8:	f503 6900 	add.w	r9, r3, #2048	; 0x800
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    e7bc:	f389 8808 	msr	MSP, r9
  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
    e7c0:	f383 880a 	msr	MSPLIM, r3
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    e7c4:	2400      	movs	r4, #0
    e7c6:	23e0      	movs	r3, #224	; 0xe0
    e7c8:	4d30      	ldr	r5, [pc, #192]	; (e88c <z_cstart+0xdc>)
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    e7ca:	f04f 0b01 	mov.w	fp, #1
    e7ce:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    e7d2:	77ec      	strb	r4, [r5, #31]
    e7d4:	762c      	strb	r4, [r5, #24]
    e7d6:	766c      	strb	r4, [r5, #25]
    e7d8:	76ac      	strb	r4, [r5, #26]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    e7da:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	_kernel.ready_q.cache = &z_main_thread;
    e7dc:	4e2c      	ldr	r6, [pc, #176]	; (e890 <z_cstart+0xe0>)
    e7de:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    e7e2:	626b      	str	r3, [r5, #36]	; 0x24

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    e7e4:	f7fe fe54 	bl	d490 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    e7e8:	f7fe fd16 	bl	d218 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    e7ec:	f04f 33ff 	mov.w	r3, #4294967295
    e7f0:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    e7f2:	62eb      	str	r3, [r5, #44]	; 0x2c
{
	dummy_thread->base.thread_state = _THREAD_DUMMY;
#ifdef CONFIG_SCHED_CPU_MASK
	dummy_thread->base.cpu_mask = -1;
#endif
	dummy_thread->base.user_options = K_ESSENTIAL;
    e7f4:	f240 1301 	movw	r3, #257	; 0x101
#endif
#ifdef CONFIG_USERSPACE
	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
#endif

	_current_cpu->current = dummy_thread;
    e7f8:	4d26      	ldr	r5, [pc, #152]	; (e894 <z_cstart+0xe4>)
	dummy_thread->base.user_options = K_ESSENTIAL;
    e7fa:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    e7fe:	ab06      	add	r3, sp, #24
    e800:	60ab      	str	r3, [r5, #8]

	z_dummy_thread_init(&dummy_thread);
#endif

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    e802:	4620      	mov	r0, r4
	dummy_thread->stack_info.size = 0U;
    e804:	e9cd 4420 	strd	r4, r4, [sp, #128]	; 0x80
    e808:	f7ff ff0a 	bl	e620 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    e80c:	2001      	movs	r0, #1
    e80e:	f7ff ff07 	bl	e620 <z_sys_init_run_level>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    e812:	f8df a098 	ldr.w	sl, [pc, #152]	; e8ac <z_cstart+0xfc>
	z_sched_init();
    e816:	f000 fae9 	bl	edec <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    e81a:	4b1f      	ldr	r3, [pc, #124]	; (e898 <z_cstart+0xe8>)
	_kernel.ready_q.cache = &z_main_thread;
    e81c:	626e      	str	r6, [r5, #36]	; 0x24
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    e81e:	f44f 5280 	mov.w	r2, #4096	; 0x1000
    e822:	491e      	ldr	r1, [pc, #120]	; (e89c <z_cstart+0xec>)
    e824:	9305      	str	r3, [sp, #20]
    e826:	4630      	mov	r0, r6
    e828:	4653      	mov	r3, sl
    e82a:	e9cd 4b03 	strd	r4, fp, [sp, #12]
    e82e:	e9cd 4401 	strd	r4, r4, [sp, #4]
    e832:	9400      	str	r4, [sp, #0]
    e834:	f000 fba4 	bl	ef80 <z_setup_new_thread>
	sys_trace_thread_resume(thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    e838:	7b73      	ldrb	r3, [r6, #13]
    e83a:	4680      	mov	r8, r0
    e83c:	f023 0304 	bic.w	r3, r3, #4
	z_ready_thread(&z_main_thread);
    e840:	4630      	mov	r0, r6
    e842:	7373      	strb	r3, [r6, #13]
    e844:	f001 fa31 	bl	fcaa <z_ready_thread>
	z_setup_new_thread(thread, stack,
    e848:	230f      	movs	r3, #15
    e84a:	4f15      	ldr	r7, [pc, #84]	; (e8a0 <z_cstart+0xf0>)
    e84c:	f44f 72a0 	mov.w	r2, #320	; 0x140
    e850:	e9cd 4302 	strd	r4, r3, [sp, #8]
    e854:	4913      	ldr	r1, [pc, #76]	; (e8a4 <z_cstart+0xf4>)
    e856:	4b14      	ldr	r3, [pc, #80]	; (e8a8 <z_cstart+0xf8>)
    e858:	4638      	mov	r0, r7
    e85a:	e9cd b404 	strd	fp, r4, [sp, #16]
    e85e:	e9cd 4400 	strd	r4, r4, [sp]
    e862:	f000 fb8d 	bl	ef80 <z_setup_new_thread>
    e866:	7b7b      	ldrb	r3, [r7, #13]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    e868:	4652      	mov	r2, sl
    e86a:	f023 0304 	bic.w	r3, r3, #4
    e86e:	737b      	strb	r3, [r7, #13]
 * @return N/A
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
    e870:	f105 0318 	add.w	r3, r5, #24
    e874:	4641      	mov	r1, r8
    e876:	4630      	mov	r0, r6
	list->tail = (sys_dnode_t *)list;
    e878:	e9c5 3306 	strd	r3, r3, [r5, #24]
		_kernel.cpus[i].idle_thread = &z_idle_threads[i];
    e87c:	60ef      	str	r7, [r5, #12]
		_kernel.cpus[i].id = i;
    e87e:	752c      	strb	r4, [r5, #20]
		_kernel.cpus[i].irq_stack =
    e880:	f8c5 9004 	str.w	r9, [r5, #4]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    e884:	f7fe fc50 	bl	d128 <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    e888:	20011468 	.word	0x20011468
    e88c:	e000ed00 	.word	0xe000ed00
    e890:	20010180 	.word	0x20010180
    e894:	200102dc 	.word	0x200102dc
    e898:	00010344 	.word	0x00010344
    e89c:	20010328 	.word	0x20010328
    e8a0:	20010100 	.word	0x20010100
    e8a4:	20011328 	.word	0x20011328
    e8a8:	0000e6ed 	.word	0x0000e6ed
    e8ac:	0000e769 	.word	0x0000e769

0000e8b0 <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(void)
{
    e8b0:	b510      	push	{r4, lr}
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time != 0) {
    e8b2:	4c08      	ldr	r4, [pc, #32]	; (e8d4 <z_reset_time_slice+0x24>)
    e8b4:	6823      	ldr	r3, [r4, #0]
    e8b6:	b15b      	cbz	r3, e8d0 <z_reset_time_slice+0x20>
		_current_cpu->slice_ticks = slice_time + z_clock_elapsed();
    e8b8:	f7fe fbb2 	bl	d020 <z_clock_elapsed>
    e8bc:	4603      	mov	r3, r0
    e8be:	6820      	ldr	r0, [r4, #0]
    e8c0:	4a05      	ldr	r2, [pc, #20]	; (e8d8 <z_reset_time_slice+0x28>)
    e8c2:	4403      	add	r3, r0
		z_set_timeout_expiry(slice_time, false);
    e8c4:	2100      	movs	r1, #0
	}
}
    e8c6:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		_current_cpu->slice_ticks = slice_time + z_clock_elapsed();
    e8ca:	6113      	str	r3, [r2, #16]
		z_set_timeout_expiry(slice_time, false);
    e8cc:	f001 ba9b 	b.w	fe06 <z_set_timeout_expiry>
}
    e8d0:	bd10      	pop	{r4, pc}
    e8d2:	bf00      	nop
    e8d4:	20010314 	.word	0x20010314
    e8d8:	200102dc 	.word	0x200102dc

0000e8dc <k_sched_time_slice_set>:

void k_sched_time_slice_set(int32_t slice, int prio)
{
    e8dc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    e8de:	4605      	mov	r5, r0
    e8e0:	460c      	mov	r4, r1
    e8e2:	f04f 0320 	mov.w	r3, #32
    e8e6:	f3ef 8611 	mrs	r6, BASEPRI
    e8ea:	f383 8811 	msr	BASEPRI, r3
    e8ee:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		_current_cpu->slice_ticks = 0;
    e8f2:	2200      	movs	r2, #0
		} else {
			return t * (to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    e8f4:	f44f 4700 	mov.w	r7, #32768	; 0x8000
    e8f8:	f240 30e7 	movw	r0, #999	; 0x3e7
    e8fc:	2100      	movs	r1, #0
    e8fe:	4b0a      	ldr	r3, [pc, #40]	; (e928 <k_sched_time_slice_set+0x4c>)
    e900:	fbe7 0105 	umlal	r0, r1, r7, r5
    e904:	611a      	str	r2, [r3, #16]
    e906:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    e90a:	2300      	movs	r3, #0
    e90c:	f7fd fc96 	bl	c23c <__aeabi_uldivmod>
		slice_time = k_ms_to_ticks_ceil32(slice);
    e910:	4b06      	ldr	r3, [pc, #24]	; (e92c <k_sched_time_slice_set+0x50>)
    e912:	6018      	str	r0, [r3, #0]
		slice_max_prio = prio;
    e914:	4b06      	ldr	r3, [pc, #24]	; (e930 <k_sched_time_slice_set+0x54>)
    e916:	601c      	str	r4, [r3, #0]
		z_reset_time_slice();
    e918:	f7ff ffca 	bl	e8b0 <z_reset_time_slice>
	__asm__ volatile(
    e91c:	f386 8811 	msr	BASEPRI, r6
    e920:	f3bf 8f6f 	isb	sy
	}
}
    e924:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    e926:	bf00      	nop
    e928:	200102dc 	.word	0x200102dc
    e92c:	20010314 	.word	0x20010314
    e930:	20010310 	.word	0x20010310

0000e934 <z_reschedule>:
{
#ifdef CONFIG_SMP
	_current_cpu->swap_ok = 0;
#endif

	return arch_irq_unlocked(key) && !arch_is_in_isr();
    e934:	b949      	cbnz	r1, e94a <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    e936:	f3ef 8005 	mrs	r0, IPSR
    e93a:	b930      	cbnz	r0, e94a <z_reschedule+0x16>
	return _kernel.ready_q.cache;
    e93c:	4b05      	ldr	r3, [pc, #20]	; (e954 <z_reschedule+0x20>)
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
	if (resched(key.key) && need_swap()) {
    e93e:	6a5a      	ldr	r2, [r3, #36]	; 0x24
    e940:	689b      	ldr	r3, [r3, #8]
    e942:	429a      	cmp	r2, r3
    e944:	d001      	beq.n	e94a <z_reschedule+0x16>
	ret = arch_swap(key);
    e946:	f7fe bb85 	b.w	d054 <arch_swap>
    e94a:	f381 8811 	msr	BASEPRI, r1
    e94e:	f3bf 8f6f 	isb	sy
		z_swap(lock, key);
	} else {
		k_spin_unlock(lock, key);
	}
}
    e952:	4770      	bx	lr
    e954:	200102dc 	.word	0x200102dc

0000e958 <k_sched_lock>:
	__asm__ volatile(
    e958:	f04f 0320 	mov.w	r3, #32
    e95c:	f3ef 8111 	mrs	r1, BASEPRI
    e960:	f383 8811 	msr	BASEPRI, r3
    e964:	f3bf 8f6f 	isb	sy
{
#ifdef CONFIG_PREEMPT_ENABLED
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1, "");

	--_current->base.sched_locked;
    e968:	4b04      	ldr	r3, [pc, #16]	; (e97c <k_sched_lock+0x24>)
    e96a:	689a      	ldr	r2, [r3, #8]
    e96c:	7bd3      	ldrb	r3, [r2, #15]
    e96e:	3b01      	subs	r3, #1
    e970:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    e972:	f381 8811 	msr	BASEPRI, r1
    e976:	f3bf 8f6f 	isb	sy
void k_sched_lock(void)
{
	LOCKED(&sched_spinlock) {
		z_sched_lock();
	}
}
    e97a:	4770      	bx	lr
    e97c:	200102dc 	.word	0x200102dc

0000e980 <z_priq_dumb_remove>:
}

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
#if defined(CONFIG_SWAP_NONATOMIC) && defined(CONFIG_SCHED_DUMB)
	if (pq == &_kernel.ready_q.runq && thread == _current &&
    e980:	4b09      	ldr	r3, [pc, #36]	; (e9a8 <z_priq_dumb_remove+0x28>)
    e982:	f103 0228 	add.w	r2, r3, #40	; 0x28
    e986:	4282      	cmp	r2, r0
    e988:	d105      	bne.n	e996 <z_priq_dumb_remove+0x16>
    e98a:	689b      	ldr	r3, [r3, #8]
    e98c:	428b      	cmp	r3, r1
    e98e:	d102      	bne.n	e996 <z_priq_dumb_remove+0x16>
    e990:	7b4b      	ldrb	r3, [r1, #13]
    e992:	06db      	lsls	r3, r3, #27
    e994:	d106      	bne.n	e9a4 <z_priq_dumb_remove+0x24>
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	node->prev->next = node->next;
    e996:	e9d1 3200 	ldrd	r3, r2, [r1]
    e99a:	6013      	str	r3, [r2, #0]
	node->next->prev = node->prev;
    e99c:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    e99e:	2300      	movs	r3, #0
	node->prev = NULL;
    e9a0:	e9c1 3300 	strd	r3, r3, [r1]
#endif

	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
}
    e9a4:	4770      	bx	lr
    e9a6:	bf00      	nop
    e9a8:	200102dc 	.word	0x200102dc

0000e9ac <update_cache>:
{
    e9ac:	b570      	push	{r4, r5, r6, lr}
	struct k_thread *thread = _priq_run_best(&_kernel.ready_q.runq);
    e9ae:	4c10      	ldr	r4, [pc, #64]	; (e9f0 <update_cache+0x44>)
{
    e9b0:	4606      	mov	r6, r0
	struct k_thread *thread = _priq_run_best(&_kernel.ready_q.runq);
    e9b2:	f104 0028 	add.w	r0, r4, #40	; 0x28
    e9b6:	f001 f96e 	bl	fc96 <z_priq_dumb_best>
    e9ba:	4605      	mov	r5, r0
	if (_current->base.thread_state & _THREAD_ABORTING) {
    e9bc:	68a3      	ldr	r3, [r4, #8]
    e9be:	7b59      	ldrb	r1, [r3, #13]
    e9c0:	0688      	lsls	r0, r1, #26
		_current->base.thread_state |= _THREAD_DEAD;
    e9c2:	bf44      	itt	mi
    e9c4:	f041 0108 	orrmi.w	r1, r1, #8
    e9c8:	7359      	strbmi	r1, [r3, #13]
	return thread ? thread : _current_cpu->idle_thread;
    e9ca:	b905      	cbnz	r5, e9ce <update_cache+0x22>
    e9cc:	68e5      	ldr	r5, [r4, #12]
	if (preempt_ok != 0) {
    e9ce:	b94e      	cbnz	r6, e9e4 <update_cache+0x38>
	if (z_is_thread_prevented_from_running(_current)) {
    e9d0:	7b5a      	ldrb	r2, [r3, #13]
    e9d2:	06d2      	lsls	r2, r2, #27
    e9d4:	d106      	bne.n	e9e4 <update_cache+0x38>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    e9d6:	69aa      	ldr	r2, [r5, #24]
    e9d8:	b922      	cbnz	r2, e9e4 <update_cache+0x38>
	if (is_preempt(_current) || is_metairq(thread)) {
    e9da:	89da      	ldrh	r2, [r3, #14]
    e9dc:	2a7f      	cmp	r2, #127	; 0x7f
    e9de:	d901      	bls.n	e9e4 <update_cache+0x38>
		_kernel.ready_q.cache = _current;
    e9e0:	6263      	str	r3, [r4, #36]	; 0x24
}
    e9e2:	bd70      	pop	{r4, r5, r6, pc}
		if (thread != _current) {
    e9e4:	42ab      	cmp	r3, r5
    e9e6:	d001      	beq.n	e9ec <update_cache+0x40>
			z_reset_time_slice();
    e9e8:	f7ff ff62 	bl	e8b0 <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    e9ec:	6265      	str	r5, [r4, #36]	; 0x24
}
    e9ee:	e7f8      	b.n	e9e2 <update_cache+0x36>
    e9f0:	200102dc 	.word	0x200102dc

0000e9f4 <k_sched_unlock>:
{
    e9f4:	b510      	push	{r4, lr}
	__asm__ volatile(
    e9f6:	f04f 0320 	mov.w	r3, #32
    e9fa:	f3ef 8411 	mrs	r4, BASEPRI
    e9fe:	f383 8811 	msr	BASEPRI, r3
    ea02:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    ea06:	4b08      	ldr	r3, [pc, #32]	; (ea28 <k_sched_unlock+0x34>)
		update_cache(0);
    ea08:	2000      	movs	r0, #0
		++_current->base.sched_locked;
    ea0a:	689a      	ldr	r2, [r3, #8]
    ea0c:	7bd3      	ldrb	r3, [r2, #15]
    ea0e:	3301      	adds	r3, #1
    ea10:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    ea12:	f7ff ffcb 	bl	e9ac <update_cache>
	__asm__ volatile(
    ea16:	f384 8811 	msr	BASEPRI, r4
    ea1a:	f3bf 8f6f 	isb	sy
}
    ea1e:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    ea22:	f001 b922 	b.w	fc6a <z_reschedule_unlocked>
    ea26:	bf00      	nop
    ea28:	200102dc 	.word	0x200102dc

0000ea2c <ready_thread>:
{
    ea2c:	b470      	push	{r4, r5, r6}
	return !((z_is_thread_prevented_from_running(thread)) != 0 ||
    ea2e:	7b43      	ldrb	r3, [r0, #13]
    ea30:	06db      	lsls	r3, r3, #27
    ea32:	d12a      	bne.n	ea8a <CONFIG_SYS_PM_MIN_RESIDENCY_DEEP_SLEEP_1+0x2a>

int z_abort_timeout(struct _timeout *to);

static inline bool z_is_inactive_timeout(struct _timeout *t)
{
	return !sys_dnode_is_linked(&t->node);
    ea34:	6983      	ldr	r3, [r0, #24]
	if (z_is_thread_ready(thread)) {
    ea36:	bb43      	cbnz	r3, ea8a <CONFIG_SYS_PM_MIN_RESIDENCY_DEEP_SLEEP_1+0x2a>
	return list->head == list;
    ea38:	4a15      	ldr	r2, [pc, #84]	; (ea90 <CONFIG_SYS_PM_MIN_RESIDENCY_DEEP_SLEEP_1+0x30>)
    ea3a:	4611      	mov	r1, r2
    ea3c:	f851 4f28 	ldr.w	r4, [r1, #40]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    ea40:	428c      	cmp	r4, r1
    ea42:	bf18      	it	ne
    ea44:	4623      	movne	r3, r4
    ea46:	2b00      	cmp	r3, #0
    ea48:	bf38      	it	cc
    ea4a:	2300      	movcc	r3, #0
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    ea4c:	6ad4      	ldr	r4, [r2, #44]	; 0x2c
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    ea4e:	b1b3      	cbz	r3, ea7e <CONFIG_SYS_PM_MIN_RESIDENCY_DEEP_SLEEP_1+0x1e>
	if (thread_1->base.prio < thread_2->base.prio) {
    ea50:	f990 600e 	ldrsb.w	r6, [r0, #14]
    ea54:	f993 500e 	ldrsb.w	r5, [r3, #14]
    ea58:	42ae      	cmp	r6, r5
    ea5a:	db03      	blt.n	ea64 <CONFIG_SYS_PM_MIN_RESIDENCY_DEEP_SLEEP_1+0x4>
	return (node == list->tail) ? NULL : node->next;
    ea5c:	42a3      	cmp	r3, r4
    ea5e:	d00e      	beq.n	ea7e <CONFIG_SYS_PM_MIN_RESIDENCY_DEEP_SLEEP_1+0x1e>
    ea60:	681b      	ldr	r3, [r3, #0]
    ea62:	e7f4      	b.n	ea4e <ready_thread+0x22>
	node->prev = successor->prev;
    ea64:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    ea66:	e9c0 3200 	strd	r3, r2, [r0]
	successor->prev->next = node;
    ea6a:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    ea6c:	6058      	str	r0, [r3, #4]
	thread->base.thread_state |= states;
    ea6e:	7b43      	ldrb	r3, [r0, #13]
    ea70:	f063 037f 	orn	r3, r3, #127	; 0x7f
    ea74:	7343      	strb	r3, [r0, #13]
}
    ea76:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    ea78:	2000      	movs	r0, #0
    ea7a:	f7ff bf97 	b.w	e9ac <update_cache>
	node->prev = list->tail;
    ea7e:	e9c0 1400 	strd	r1, r4, [r0]
	list->tail->next = node;
    ea82:	6ad3      	ldr	r3, [r2, #44]	; 0x2c
    ea84:	6018      	str	r0, [r3, #0]
	list->tail = node;
    ea86:	62d0      	str	r0, [r2, #44]	; 0x2c
}
    ea88:	e7f1      	b.n	ea6e <CONFIG_SYS_PM_MIN_RESIDENCY_DEEP_SLEEP_1+0xe>
}
    ea8a:	bc70      	pop	{r4, r5, r6}
    ea8c:	4770      	bx	lr
    ea8e:	bf00      	nop
    ea90:	200102dc 	.word	0x200102dc

0000ea94 <z_sched_start>:
{
    ea94:	b510      	push	{r4, lr}
	__asm__ volatile(
    ea96:	f04f 0220 	mov.w	r2, #32
    ea9a:	f3ef 8411 	mrs	r4, BASEPRI
    ea9e:	f382 8811 	msr	BASEPRI, r2
    eaa2:	f3bf 8f6f 	isb	sy
	if (z_has_thread_started(thread)) {
    eaa6:	7b42      	ldrb	r2, [r0, #13]
    eaa8:	0751      	lsls	r1, r2, #29
    eaaa:	d404      	bmi.n	eab6 <z_sched_start+0x22>
	__asm__ volatile(
    eaac:	f384 8811 	msr	BASEPRI, r4
    eab0:	f3bf 8f6f 	isb	sy
}
    eab4:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    eab6:	f022 0204 	bic.w	r2, r2, #4
    eaba:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    eabc:	f7ff ffb6 	bl	ea2c <ready_thread>
	z_reschedule(&sched_spinlock, key);
    eac0:	4621      	mov	r1, r4
}
    eac2:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    eac6:	4801      	ldr	r0, [pc, #4]	; (eacc <z_sched_start+0x38>)
    eac8:	f7ff bf34 	b.w	e934 <z_reschedule>
    eacc:	20010321 	.word	0x20010321

0000ead0 <move_thread_to_end_of_prio_q>:
{
    ead0:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    ead2:	f990 300d 	ldrsb.w	r3, [r0, #13]
{
    ead6:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    ead8:	2b00      	cmp	r3, #0
    eada:	da02      	bge.n	eae2 <move_thread_to_end_of_prio_q+0x12>
		_priq_run_remove(&_kernel.ready_q.runq, thread);
    eadc:	4817      	ldr	r0, [pc, #92]	; (eb3c <move_thread_to_end_of_prio_q+0x6c>)
    eade:	f7ff ff4f 	bl	e980 <z_priq_dumb_remove>
	return list->head == list;
    eae2:	4a17      	ldr	r2, [pc, #92]	; (eb40 <move_thread_to_end_of_prio_q+0x70>)
    eae4:	4610      	mov	r0, r2
    eae6:	f850 3f28 	ldr.w	r3, [r0, #40]!
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    eaea:	6ad4      	ldr	r4, [r2, #44]	; 0x2c
	return sys_dlist_is_empty(list) ? NULL : list->head;
    eaec:	4283      	cmp	r3, r0
    eaee:	bf08      	it	eq
    eaf0:	2300      	moveq	r3, #0
    eaf2:	2b00      	cmp	r3, #0
    eaf4:	bf38      	it	cc
    eaf6:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    eaf8:	b1d3      	cbz	r3, eb30 <move_thread_to_end_of_prio_q+0x60>
	if (thread_1->base.prio < thread_2->base.prio) {
    eafa:	f991 600e 	ldrsb.w	r6, [r1, #14]
    eafe:	f993 500e 	ldrsb.w	r5, [r3, #14]
    eb02:	42ae      	cmp	r6, r5
    eb04:	db03      	blt.n	eb0e <move_thread_to_end_of_prio_q+0x3e>
	return (node == list->tail) ? NULL : node->next;
    eb06:	42a3      	cmp	r3, r4
    eb08:	d012      	beq.n	eb30 <move_thread_to_end_of_prio_q+0x60>
    eb0a:	681b      	ldr	r3, [r3, #0]
    eb0c:	e7f4      	b.n	eaf8 <move_thread_to_end_of_prio_q+0x28>
	node->prev = successor->prev;
    eb0e:	6858      	ldr	r0, [r3, #4]
	node->next = successor;
    eb10:	e9c1 3000 	strd	r3, r0, [r1]
	successor->prev->next = node;
    eb14:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    eb16:	6059      	str	r1, [r3, #4]
	thread->base.thread_state |= states;
    eb18:	7b4b      	ldrb	r3, [r1, #13]
	update_cache(thread == _current);
    eb1a:	6890      	ldr	r0, [r2, #8]
    eb1c:	f063 037f 	orn	r3, r3, #127	; 0x7f
    eb20:	734b      	strb	r3, [r1, #13]
    eb22:	1a43      	subs	r3, r0, r1
    eb24:	4258      	negs	r0, r3
    eb26:	4158      	adcs	r0, r3
}
    eb28:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    eb2c:	f7ff bf3e 	b.w	e9ac <update_cache>
	node->prev = list->tail;
    eb30:	e9c1 0400 	strd	r0, r4, [r1]
	list->tail->next = node;
    eb34:	6ad3      	ldr	r3, [r2, #44]	; 0x2c
    eb36:	6019      	str	r1, [r3, #0]
	list->tail = node;
    eb38:	62d1      	str	r1, [r2, #44]	; 0x2c
}
    eb3a:	e7ed      	b.n	eb18 <move_thread_to_end_of_prio_q+0x48>
    eb3c:	20010304 	.word	0x20010304
    eb40:	200102dc 	.word	0x200102dc

0000eb44 <z_time_slice>:
{
    eb44:	4601      	mov	r1, r0
    eb46:	b570      	push	{r4, r5, r6, lr}
	__asm__ volatile(
    eb48:	f04f 0320 	mov.w	r3, #32
    eb4c:	f3ef 8411 	mrs	r4, BASEPRI
    eb50:	f383 8811 	msr	BASEPRI, r3
    eb54:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    eb58:	4b16      	ldr	r3, [pc, #88]	; (ebb4 <z_time_slice+0x70>)
    eb5a:	4a17      	ldr	r2, [pc, #92]	; (ebb8 <z_time_slice+0x74>)
    eb5c:	6898      	ldr	r0, [r3, #8]
    eb5e:	6815      	ldr	r5, [r2, #0]
    eb60:	42a8      	cmp	r0, r5
    eb62:	461d      	mov	r5, r3
    eb64:	d106      	bne.n	eb74 <z_time_slice+0x30>
			z_reset_time_slice();
    eb66:	f7ff fea3 	bl	e8b0 <z_reset_time_slice>
	__asm__ volatile(
    eb6a:	f384 8811 	msr	BASEPRI, r4
    eb6e:	f3bf 8f6f 	isb	sy
}
    eb72:	bd70      	pop	{r4, r5, r6, pc}
	pending_current = NULL;
    eb74:	2600      	movs	r6, #0
    eb76:	6016      	str	r6, [r2, #0]
	if (slice_time && sliceable(_current)) {
    eb78:	4a10      	ldr	r2, [pc, #64]	; (ebbc <z_time_slice+0x78>)
    eb7a:	6812      	ldr	r2, [r2, #0]
    eb7c:	b1ba      	cbz	r2, ebae <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    eb7e:	89c2      	ldrh	r2, [r0, #14]
    eb80:	2a7f      	cmp	r2, #127	; 0x7f
    eb82:	d814      	bhi.n	ebae <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
    eb84:	7b42      	ldrb	r2, [r0, #13]
    eb86:	06d2      	lsls	r2, r2, #27
    eb88:	d111      	bne.n	ebae <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    eb8a:	4a0d      	ldr	r2, [pc, #52]	; (ebc0 <z_time_slice+0x7c>)
    eb8c:	f990 600e 	ldrsb.w	r6, [r0, #14]
    eb90:	6812      	ldr	r2, [r2, #0]
    eb92:	4296      	cmp	r6, r2
    eb94:	db0b      	blt.n	ebae <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    eb96:	4a0b      	ldr	r2, [pc, #44]	; (ebc4 <z_time_slice+0x80>)
    eb98:	4290      	cmp	r0, r2
    eb9a:	d008      	beq.n	ebae <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
    eb9c:	691a      	ldr	r2, [r3, #16]
    eb9e:	428a      	cmp	r2, r1
    eba0:	dc02      	bgt.n	eba8 <z_time_slice+0x64>
			move_thread_to_end_of_prio_q(_current);
    eba2:	f7ff ff95 	bl	ead0 <move_thread_to_end_of_prio_q>
    eba6:	e7de      	b.n	eb66 <z_time_slice+0x22>
			_current_cpu->slice_ticks -= ticks;
    eba8:	1a52      	subs	r2, r2, r1
    ebaa:	611a      	str	r2, [r3, #16]
    ebac:	e7dd      	b.n	eb6a <z_time_slice+0x26>
		_current_cpu->slice_ticks = 0;
    ebae:	2300      	movs	r3, #0
    ebb0:	612b      	str	r3, [r5, #16]
    ebb2:	e7da      	b.n	eb6a <z_time_slice+0x26>
    ebb4:	200102dc 	.word	0x200102dc
    ebb8:	2001030c 	.word	0x2001030c
    ebbc:	20010314 	.word	0x20010314
    ebc0:	20010310 	.word	0x20010310
    ebc4:	20010100 	.word	0x20010100

0000ebc8 <z_impl_k_thread_suspend>:
{
    ebc8:	b570      	push	{r4, r5, r6, lr}
    ebca:	4604      	mov	r4, r0
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    ebcc:	3018      	adds	r0, #24
    ebce:	f001 f8f4 	bl	fdba <z_abort_timeout>
	__asm__ volatile(
    ebd2:	f04f 0320 	mov.w	r3, #32
    ebd6:	f3ef 8611 	mrs	r6, BASEPRI
    ebda:	f383 8811 	msr	BASEPRI, r3
    ebde:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    ebe2:	f994 300d 	ldrsb.w	r3, [r4, #13]
    ebe6:	2b00      	cmp	r3, #0
    ebe8:	da07      	bge.n	ebfa <z_impl_k_thread_suspend+0x32>
			_priq_run_remove(&_kernel.ready_q.runq, thread);
    ebea:	4621      	mov	r1, r4
    ebec:	480e      	ldr	r0, [pc, #56]	; (ec28 <z_impl_k_thread_suspend+0x60>)
    ebee:	f7ff fec7 	bl	e980 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    ebf2:	7b63      	ldrb	r3, [r4, #13]
    ebf4:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    ebf8:	7363      	strb	r3, [r4, #13]
		update_cache(thread == _current);
    ebfa:	4d0c      	ldr	r5, [pc, #48]	; (ec2c <z_impl_k_thread_suspend+0x64>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    ebfc:	7b63      	ldrb	r3, [r4, #13]
    ebfe:	68a8      	ldr	r0, [r5, #8]
    ec00:	f043 0310 	orr.w	r3, r3, #16
    ec04:	7363      	strb	r3, [r4, #13]
    ec06:	1b03      	subs	r3, r0, r4
    ec08:	4258      	negs	r0, r3
    ec0a:	4158      	adcs	r0, r3
    ec0c:	f7ff fece 	bl	e9ac <update_cache>
	__asm__ volatile(
    ec10:	f386 8811 	msr	BASEPRI, r6
    ec14:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    ec18:	68ab      	ldr	r3, [r5, #8]
    ec1a:	42a3      	cmp	r3, r4
    ec1c:	d103      	bne.n	ec26 <z_impl_k_thread_suspend+0x5e>
}
    ec1e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    ec22:	f001 b822 	b.w	fc6a <z_reschedule_unlocked>
}
    ec26:	bd70      	pop	{r4, r5, r6, pc}
    ec28:	20010304 	.word	0x20010304
    ec2c:	200102dc 	.word	0x200102dc

0000ec30 <z_thread_single_abort>:
	if (thread->fn_abort != NULL) {
    ec30:	6e03      	ldr	r3, [r0, #96]	; 0x60
{
    ec32:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    ec36:	4604      	mov	r4, r0
	if (thread->fn_abort != NULL) {
    ec38:	b103      	cbz	r3, ec3c <z_thread_single_abort+0xc>
		thread->fn_abort();
    ec3a:	4798      	blx	r3
    ec3c:	f104 0018 	add.w	r0, r4, #24
    ec40:	f001 f8bb 	bl	fdba <z_abort_timeout>
	__asm__ volatile(
    ec44:	f04f 0320 	mov.w	r3, #32
    ec48:	f3ef 8611 	mrs	r6, BASEPRI
    ec4c:	f383 8811 	msr	BASEPRI, r3
    ec50:	f3bf 8f6f 	isb	sy
	return !((z_is_thread_prevented_from_running(thread)) != 0 ||
    ec54:	7b63      	ldrb	r3, [r4, #13]
    ec56:	06d8      	lsls	r0, r3, #27
    ec58:	d123      	bne.n	eca2 <z_thread_single_abort+0x72>
		if (z_is_thread_ready(thread)) {
    ec5a:	69a2      	ldr	r2, [r4, #24]
    ec5c:	bb0a      	cbnz	r2, eca2 <z_thread_single_abort+0x72>
			if (z_is_thread_queued(thread)) {
    ec5e:	0619      	lsls	r1, r3, #24
    ec60:	d507      	bpl.n	ec72 <z_thread_single_abort+0x42>
				_priq_run_remove(&_kernel.ready_q.runq,
    ec62:	4621      	mov	r1, r4
    ec64:	481e      	ldr	r0, [pc, #120]	; (ece0 <z_thread_single_abort+0xb0>)
    ec66:	f7ff fe8b 	bl	e980 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    ec6a:	7b63      	ldrb	r3, [r4, #13]
    ec6c:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    ec70:	7363      	strb	r3, [r4, #13]
			update_cache(thread == _current);
    ec72:	4b1c      	ldr	r3, [pc, #112]	; (ece4 <z_thread_single_abort+0xb4>)
    ec74:	6898      	ldr	r0, [r3, #8]
    ec76:	1b02      	subs	r2, r0, r4
    ec78:	4250      	negs	r0, r2
    ec7a:	4150      	adcs	r0, r2
    ec7c:	f7ff fe96 	bl	e9ac <update_cache>
			waiter->base.pended_on = NULL;
    ec80:	2700      	movs	r7, #0
		thread->base.thread_state |= mask;
    ec82:	7b63      	ldrb	r3, [r4, #13]
	sys_dlist_init(&w->waitq);
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    ec84:	f104 0830 	add.w	r8, r4, #48	; 0x30
    ec88:	f043 0308 	orr.w	r3, r3, #8
    ec8c:	7363      	strb	r3, [r4, #13]
	return list->head == list;
    ec8e:	6b25      	ldr	r5, [r4, #48]	; 0x30
	return sys_dlist_is_empty(list) ? NULL : list->head;
    ec90:	4545      	cmp	r5, r8
    ec92:	d000      	beq.n	ec96 <z_thread_single_abort+0x66>
		while ((waiter = z_waitq_head(&thread->base.join_waiters)) !=
    ec94:	b995      	cbnz	r5, ecbc <z_thread_single_abort+0x8c>
	__asm__ volatile(
    ec96:	f386 8811 	msr	BASEPRI, r6
    ec9a:	f3bf 8f6f 	isb	sy
}
    ec9e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
			if (z_is_thread_pending(thread)) {
    eca2:	079b      	lsls	r3, r3, #30
    eca4:	d5ec      	bpl.n	ec80 <z_thread_single_abort+0x50>
				_priq_wait_remove(&pended_on(thread)->waitq,
    eca6:	4621      	mov	r1, r4
    eca8:	68a0      	ldr	r0, [r4, #8]
    ecaa:	f7ff fe69 	bl	e980 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    ecae:	7b63      	ldrb	r3, [r4, #13]
    ecb0:	f023 0302 	bic.w	r3, r3, #2
    ecb4:	7363      	strb	r3, [r4, #13]
				thread->base.pended_on = NULL;
    ecb6:	2300      	movs	r3, #0
    ecb8:	60a3      	str	r3, [r4, #8]
    ecba:	e7e1      	b.n	ec80 <z_thread_single_abort+0x50>
    ecbc:	f105 0018 	add.w	r0, r5, #24
    ecc0:	f001 f87b 	bl	fdba <z_abort_timeout>
			_priq_wait_remove(&pended_on(waiter)->waitq, waiter);
    ecc4:	68a8      	ldr	r0, [r5, #8]
    ecc6:	4629      	mov	r1, r5
    ecc8:	f7ff fe5a 	bl	e980 <z_priq_dumb_remove>
    eccc:	7b6b      	ldrb	r3, [r5, #13]
			ready_thread(waiter);
    ecce:	4628      	mov	r0, r5
    ecd0:	f023 0302 	bic.w	r3, r3, #2
    ecd4:	736b      	strb	r3, [r5, #13]
			waiter->base.pended_on = NULL;
    ecd6:	60af      	str	r7, [r5, #8]
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    ecd8:	67ef      	str	r7, [r5, #124]	; 0x7c
			ready_thread(waiter);
    ecda:	f7ff fea7 	bl	ea2c <ready_thread>
    ecde:	e7d6      	b.n	ec8e <z_thread_single_abort+0x5e>
    ece0:	20010304 	.word	0x20010304
    ece4:	200102dc 	.word	0x200102dc

0000ece8 <unready_thread>:
{
    ece8:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    ecea:	f990 300d 	ldrsb.w	r3, [r0, #13]
{
    ecee:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    ecf0:	2b00      	cmp	r3, #0
    ecf2:	da06      	bge.n	ed02 <unready_thread+0x1a>
		_priq_run_remove(&_kernel.ready_q.runq, thread);
    ecf4:	4807      	ldr	r0, [pc, #28]	; (ed14 <unready_thread+0x2c>)
    ecf6:	f7ff fe43 	bl	e980 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    ecfa:	7b4b      	ldrb	r3, [r1, #13]
    ecfc:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    ed00:	734b      	strb	r3, [r1, #13]
	update_cache(thread == _current);
    ed02:	4b05      	ldr	r3, [pc, #20]	; (ed18 <unready_thread+0x30>)
    ed04:	6898      	ldr	r0, [r3, #8]
    ed06:	1a43      	subs	r3, r0, r1
    ed08:	4258      	negs	r0, r3
    ed0a:	4158      	adcs	r0, r3
}
    ed0c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    ed10:	f7ff be4c 	b.w	e9ac <update_cache>
    ed14:	20010304 	.word	0x20010304
    ed18:	200102dc 	.word	0x200102dc

0000ed1c <pend>:
{
    ed1c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    ed20:	4606      	mov	r6, r0
    ed22:	4614      	mov	r4, r2
    ed24:	461d      	mov	r5, r3
	__asm__ volatile(
    ed26:	f04f 0320 	mov.w	r3, #32
    ed2a:	f3ef 8711 	mrs	r7, BASEPRI
    ed2e:	f383 8811 	msr	BASEPRI, r3
    ed32:	f3bf 8f6f 	isb	sy
		add_to_waitq_locked(thread, wait_q);
    ed36:	f000 ffe8 	bl	fd0a <add_to_waitq_locked>
	__asm__ volatile(
    ed3a:	f387 8811 	msr	BASEPRI, r7
    ed3e:	f3bf 8f6f 	isb	sy
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    ed42:	1c6b      	adds	r3, r5, #1
    ed44:	bf08      	it	eq
    ed46:	f1b4 3fff 	cmpeq.w	r4, #4294967295
    ed4a:	d008      	beq.n	ed5e <pend+0x42>
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
    ed4c:	4622      	mov	r2, r4
    ed4e:	462b      	mov	r3, r5
    ed50:	f106 0018 	add.w	r0, r6, #24
    ed54:	4903      	ldr	r1, [pc, #12]	; (ed64 <pend+0x48>)
}
    ed56:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    ed5a:	f000 b9eb 	b.w	f134 <z_add_timeout>
    ed5e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    ed62:	bf00      	nop
    ed64:	0000fccb 	.word	0x0000fccb

0000ed68 <z_pend_curr>:
{
    ed68:	b510      	push	{r4, lr}
    ed6a:	460c      	mov	r4, r1
	pending_current = _current;
    ed6c:	4b06      	ldr	r3, [pc, #24]	; (ed88 <z_pend_curr+0x20>)
{
    ed6e:	4611      	mov	r1, r2
	pending_current = _current;
    ed70:	6898      	ldr	r0, [r3, #8]
    ed72:	4b06      	ldr	r3, [pc, #24]	; (ed8c <z_pend_curr+0x24>)
    ed74:	6018      	str	r0, [r3, #0]
	pend(_current, wait_q, timeout);
    ed76:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    ed7a:	f7ff ffcf 	bl	ed1c <pend>
    ed7e:	4620      	mov	r0, r4
}
    ed80:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    ed84:	f7fe b966 	b.w	d054 <arch_swap>
    ed88:	200102dc 	.word	0x200102dc
    ed8c:	2001030c 	.word	0x2001030c

0000ed90 <z_tick_sleep.part.0>:
	z_impl_k_yield();
}
#include <syscalls/k_yield_mrsh.c>
#endif

static int32_t z_tick_sleep(int32_t ticks)
    ed90:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    ed92:	4605      	mov	r5, r0
#else
	ticks += _TICK_ALIGN;
	timeout = (k_ticks_t) ticks;
#endif

	expected_wakeup_time = ticks + z_tick_get_32();
    ed94:	f001 f851 	bl	fe3a <z_tick_get_32>
    ed98:	182c      	adds	r4, r5, r0
	__asm__ volatile(
    ed9a:	f04f 0320 	mov.w	r3, #32
    ed9e:	f3ef 8711 	mrs	r7, BASEPRI
    eda2:	f383 8811 	msr	BASEPRI, r3
    eda6:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

#if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC)
	pending_current = _current;
    edaa:	4e0d      	ldr	r6, [pc, #52]	; (ede0 <z_tick_sleep.part.0+0x50>)
    edac:	4b0d      	ldr	r3, [pc, #52]	; (ede4 <z_tick_sleep.part.0+0x54>)
    edae:	68b0      	ldr	r0, [r6, #8]
    edb0:	6018      	str	r0, [r3, #0]
#endif
	unready_thread(_current);
    edb2:	f7ff ff99 	bl	ece8 <unready_thread>
	z_add_thread_timeout(_current, timeout);
    edb6:	68b0      	ldr	r0, [r6, #8]
    edb8:	490b      	ldr	r1, [pc, #44]	; (ede8 <z_tick_sleep.part.0+0x58>)
    edba:	462a      	mov	r2, r5
    edbc:	17eb      	asrs	r3, r5, #31
    edbe:	3018      	adds	r0, #24
    edc0:	f000 f9b8 	bl	f134 <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    edc4:	68b2      	ldr	r2, [r6, #8]
    edc6:	4638      	mov	r0, r7
	thread->base.thread_state |= _THREAD_SUSPENDED;
    edc8:	7b53      	ldrb	r3, [r2, #13]
    edca:	f043 0310 	orr.w	r3, r3, #16
    edce:	7353      	strb	r3, [r2, #13]
    edd0:	f7fe f940 	bl	d054 <arch_swap>

	(void)z_swap(&sched_spinlock, key);

	__ASSERT(!z_is_thread_state_set(_current, _THREAD_SUSPENDED), "");

	ticks = expected_wakeup_time - z_tick_get_32();
    edd4:	f001 f831 	bl	fe3a <z_tick_get_32>
    edd8:	1a20      	subs	r0, r4, r0
		return ticks;
	}
#endif

	return 0;
}
    edda:	ea20 70e0 	bic.w	r0, r0, r0, asr #31
    edde:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    ede0:	200102dc 	.word	0x200102dc
    ede4:	2001030c 	.word	0x2001030c
    ede8:	0000fccb 	.word	0x0000fccb

0000edec <z_sched_init>:
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    edec:	2100      	movs	r1, #0
	list->head = (sys_dnode_t *)list;
    edee:	4b04      	ldr	r3, [pc, #16]	; (ee00 <z_sched_init+0x14>)
    edf0:	4608      	mov	r0, r1
    edf2:	f103 0228 	add.w	r2, r3, #40	; 0x28
	list->tail = (sys_dnode_t *)list;
    edf6:	e9c3 220a 	strd	r2, r2, [r3, #40]	; 0x28
    edfa:	f7ff bd6f 	b.w	e8dc <k_sched_time_slice_set>
    edfe:	bf00      	nop
    ee00:	200102dc 	.word	0x200102dc

0000ee04 <z_impl_k_yield>:
{
    ee04:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	if (!z_is_idle_thread_object(_current)) {
    ee06:	4c24      	ldr	r4, [pc, #144]	; (ee98 <z_impl_k_yield+0x94>)
    ee08:	4b24      	ldr	r3, [pc, #144]	; (ee9c <z_impl_k_yield+0x98>)
    ee0a:	68a2      	ldr	r2, [r4, #8]
    ee0c:	429a      	cmp	r2, r3
    ee0e:	d030      	beq.n	ee72 <z_impl_k_yield+0x6e>
    ee10:	f04f 0320 	mov.w	r3, #32
    ee14:	f3ef 8511 	mrs	r5, BASEPRI
    ee18:	f383 8811 	msr	BASEPRI, r3
    ee1c:	f3bf 8f6f 	isb	sy
				_priq_run_remove(&_kernel.ready_q.runq,
    ee20:	68a1      	ldr	r1, [r4, #8]
    ee22:	f104 0028 	add.w	r0, r4, #40	; 0x28
    ee26:	f7ff fdab 	bl	e980 <z_priq_dumb_remove>
	return list->head == list;
    ee2a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
			_priq_run_add(&_kernel.ready_q.runq, _current);
    ee2c:	68a2      	ldr	r2, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    ee2e:	4283      	cmp	r3, r0
    ee30:	bf08      	it	eq
    ee32:	2300      	moveq	r3, #0
    ee34:	2b00      	cmp	r3, #0
    ee36:	bf38      	it	cc
    ee38:	2300      	movcc	r3, #0
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    ee3a:	6ae1      	ldr	r1, [r4, #44]	; 0x2c
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    ee3c:	b32b      	cbz	r3, ee8a <z_impl_k_yield+0x86>
	if (thread_1->base.prio < thread_2->base.prio) {
    ee3e:	f992 700e 	ldrsb.w	r7, [r2, #14]
    ee42:	f993 600e 	ldrsb.w	r6, [r3, #14]
    ee46:	42b7      	cmp	r7, r6
    ee48:	db03      	blt.n	ee52 <z_impl_k_yield+0x4e>
	return (node == list->tail) ? NULL : node->next;
    ee4a:	428b      	cmp	r3, r1
    ee4c:	d01d      	beq.n	ee8a <z_impl_k_yield+0x86>
    ee4e:	681b      	ldr	r3, [r3, #0]
    ee50:	e7f4      	b.n	ee3c <z_impl_k_yield+0x38>
	node->prev = successor->prev;
    ee52:	6859      	ldr	r1, [r3, #4]
	node->next = successor;
    ee54:	e9c2 3100 	strd	r3, r1, [r2]
	successor->prev->next = node;
    ee58:	600a      	str	r2, [r1, #0]
	successor->prev = node;
    ee5a:	605a      	str	r2, [r3, #4]
	thread->base.thread_state |= states;
    ee5c:	7b53      	ldrb	r3, [r2, #13]
			update_cache(1);
    ee5e:	2001      	movs	r0, #1
    ee60:	f063 037f 	orn	r3, r3, #127	; 0x7f
    ee64:	7353      	strb	r3, [r2, #13]
    ee66:	f7ff fda1 	bl	e9ac <update_cache>
	__asm__ volatile(
    ee6a:	f385 8811 	msr	BASEPRI, r5
    ee6e:	f3bf 8f6f 	isb	sy
	__asm__ volatile(
    ee72:	f04f 0320 	mov.w	r3, #32
    ee76:	f3ef 8011 	mrs	r0, BASEPRI
    ee7a:	f383 8811 	msr	BASEPRI, r3
    ee7e:	f3bf 8f6f 	isb	sy
}
    ee82:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    ee86:	f7fe b8e5 	b.w	d054 <arch_swap>
	node->prev = list->tail;
    ee8a:	e9c2 0100 	strd	r0, r1, [r2]
	list->tail->next = node;
    ee8e:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    ee90:	601a      	str	r2, [r3, #0]
	list->tail = node;
    ee92:	62e2      	str	r2, [r4, #44]	; 0x2c
}
    ee94:	e7e2      	b.n	ee5c <z_impl_k_yield+0x58>
    ee96:	bf00      	nop
    ee98:	200102dc 	.word	0x200102dc
    ee9c:	20010100 	.word	0x20010100

0000eea0 <z_impl_k_sleep>:

int32_t z_impl_k_sleep(k_timeout_t timeout)
{
    eea0:	460b      	mov	r3, r1
	k_ticks_t ticks;

	__ASSERT(!arch_is_in_isr(), "");
	sys_trace_void(SYS_TRACE_ID_SLEEP);

	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    eea2:	3301      	adds	r3, #1
    eea4:	bf08      	it	eq
    eea6:	f1b0 3fff 	cmpeq.w	r0, #4294967295
{
    eeaa:	b510      	push	{r4, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    eeac:	d106      	bne.n	eebc <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
    eeae:	4b0b      	ldr	r3, [pc, #44]	; (eedc <z_impl_k_sleep+0x3c>)
    eeb0:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    eeb2:	f7ff fe89 	bl	ebc8 <z_impl_k_thread_suspend>
		return (int32_t) K_TICKS_FOREVER;
    eeb6:	f04f 30ff 	mov.w	r0, #4294967295
#endif

	ticks = z_tick_sleep(ticks);
	sys_trace_end_call(SYS_TRACE_ID_SLEEP);
	return k_ticks_to_ms_floor64(ticks);
}
    eeba:	bd10      	pop	{r4, pc}
	ticks = z_tick_sleep(ticks);
    eebc:	4604      	mov	r4, r0
	if (ticks == 0) {
    eebe:	b948      	cbnz	r0, eed4 <z_impl_k_sleep+0x34>
	z_impl_k_yield();
    eec0:	f7ff ffa0 	bl	ee04 <z_impl_k_yield>
		} else {
			return (t * to_hz + off) / from_hz;
    eec4:	f44f 707a 	mov.w	r0, #1000	; 0x3e8
    eec8:	fb84 3400 	smull	r3, r4, r4, r0
    eecc:	0bd8      	lsrs	r0, r3, #15
    eece:	ea40 4044 	orr.w	r0, r0, r4, lsl #17
	return k_ticks_to_ms_floor64(ticks);
    eed2:	e7f2      	b.n	eeba <z_impl_k_sleep+0x1a>
    eed4:	f7ff ff5c 	bl	ed90 <z_tick_sleep.part.0>
    eed8:	4604      	mov	r4, r0
    eeda:	e7f3      	b.n	eec4 <z_impl_k_sleep+0x24>
    eedc:	200102dc 	.word	0x200102dc

0000eee0 <z_impl_k_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    eee0:	4b01      	ldr	r3, [pc, #4]	; (eee8 <z_impl_k_current_get+0x8>)
    eee2:	6898      	ldr	r0, [r3, #8]
    eee4:	4770      	bx	lr
    eee6:	bf00      	nop
    eee8:	200102dc 	.word	0x200102dc

0000eeec <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    eeec:	b538      	push	{r3, r4, r5, lr}
    eeee:	4604      	mov	r4, r0
    eef0:	f04f 0320 	mov.w	r3, #32
    eef4:	f3ef 8511 	mrs	r5, BASEPRI
    eef8:	f383 8811 	msr	BASEPRI, r3
    eefc:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	sys_trace_semaphore_give(sem);
	thread = z_unpend_first_thread(&sem->wait_q);
    ef00:	f000 ff2e 	bl	fd60 <z_unpend_first_thread>

	if (thread != NULL) {
    ef04:	b148      	cbz	r0, ef1a <z_impl_k_sem_give+0x2e>
    ef06:	2200      	movs	r2, #0
    ef08:	67c2      	str	r2, [r0, #124]	; 0x7c
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    ef0a:	f000 fece 	bl	fcaa <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    ef0e:	4629      	mov	r1, r5
	sys_trace_end_call(SYS_TRACE_ID_SEMA_GIVE);
}
    ef10:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    ef14:	4804      	ldr	r0, [pc, #16]	; (ef28 <z_impl_k_sem_give+0x3c>)
    ef16:	f7ff bd0d 	b.w	e934 <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    ef1a:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    ef1e:	429a      	cmp	r2, r3
    ef20:	bf18      	it	ne
    ef22:	3301      	addne	r3, #1
    ef24:	60a3      	str	r3, [r4, #8]
		handle_poll_events(sem);
    ef26:	e7f2      	b.n	ef0e <z_impl_k_sem_give+0x22>
    ef28:	20010321 	.word	0x20010321

0000ef2c <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    ef2c:	b537      	push	{r0, r1, r2, r4, r5, lr}
    ef2e:	4614      	mov	r4, r2
    ef30:	461d      	mov	r5, r3
    ef32:	f04f 0320 	mov.w	r3, #32
    ef36:	f3ef 8111 	mrs	r1, BASEPRI
    ef3a:	f383 8811 	msr	BASEPRI, r3
    ef3e:	f3bf 8f6f 	isb	sy
		  K_TIMEOUT_EQ(timeout, K_NO_WAIT)), "");

	k_spinlock_key_t key = k_spin_lock(&lock);
	sys_trace_semaphore_take(sem);

	if (likely(sem->count > 0U)) {
    ef42:	6883      	ldr	r3, [r0, #8]
    ef44:	b143      	cbz	r3, ef58 <z_impl_k_sem_take+0x2c>
		sem->count--;
    ef46:	3b01      	subs	r3, #1
    ef48:	6083      	str	r3, [r0, #8]
	__asm__ volatile(
    ef4a:	f381 8811 	msr	BASEPRI, r1
    ef4e:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    ef52:	2000      	movs	r0, #0
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);

out:
	sys_trace_end_call(SYS_TRACE_ID_SEMA_TAKE);
	return ret;
}
    ef54:	b003      	add	sp, #12
    ef56:	bd30      	pop	{r4, r5, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    ef58:	ea54 0305 	orrs.w	r3, r4, r5
    ef5c:	d106      	bne.n	ef6c <z_impl_k_sem_take+0x40>
    ef5e:	f381 8811 	msr	BASEPRI, r1
    ef62:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    ef66:	f06f 000f 	mvn.w	r0, #15
    ef6a:	e7f3      	b.n	ef54 <z_impl_k_sem_take+0x28>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    ef6c:	4602      	mov	r2, r0
    ef6e:	e9cd 4500 	strd	r4, r5, [sp]
    ef72:	4802      	ldr	r0, [pc, #8]	; (ef7c <z_impl_k_sem_take+0x50>)
    ef74:	f7ff fef8 	bl	ed68 <z_pend_curr>
	return ret;
    ef78:	e7ec      	b.n	ef54 <z_impl_k_sem_take+0x28>
    ef7a:	bf00      	nop
    ef7c:	20010321 	.word	0x20010321

0000ef80 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    ef80:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
	sys_dlist_init(&w->waitq);
    ef84:	f100 0530 	add.w	r5, r0, #48	; 0x30
	list->tail = (sys_dnode_t *)list;
    ef88:	e9c0 550c 	strd	r5, r5, [r0, #48]	; 0x30
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */

	thread_base->user_options = (uint8_t)options;
    ef8c:	9d0e      	ldr	r5, [sp, #56]	; 0x38
{
    ef8e:	4604      	mov	r4, r0
	thread_base->user_options = (uint8_t)options;
    ef90:	7305      	strb	r5, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    ef92:	2504      	movs	r5, #4
    ef94:	7345      	strb	r5, [r0, #13]

	thread_base->prio = priority;
    ef96:	9d0d      	ldr	r5, [sp, #52]	; 0x34
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    ef98:	1dd6      	adds	r6, r2, #7
	thread_base->prio = priority;
    ef9a:	7385      	strb	r5, [r0, #14]

	thread_base->sched_locked = 0U;
    ef9c:	2500      	movs	r5, #0
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    ef9e:	9a0c      	ldr	r2, [sp, #48]	; 0x30
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    efa0:	f026 0607 	bic.w	r6, r6, #7
	node->prev = NULL;
    efa4:	e9c0 5506 	strd	r5, r5, [r0, #24]
	new_thread->stack_info.size = stack_buf_size;
    efa8:	e9c0 161a 	strd	r1, r6, [r0, #104]	; 0x68
	thread_base->sched_locked = 0U;
    efac:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    efae:	6705      	str	r5, [r0, #112]	; 0x70
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    efb0:	9202      	str	r2, [sp, #8]
    efb2:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
	stack_ptr = (char *)stack + stack_obj_size;
    efb4:	eb01 0806 	add.w	r8, r1, r6
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    efb8:	9201      	str	r2, [sp, #4]
    efba:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    efbc:	9200      	str	r2, [sp, #0]
    efbe:	4642      	mov	r2, r8
    efc0:	f7fe f896 	bl	d0f0 <arch_new_thread>
	if (!_current) {
    efc4:	4b05      	ldr	r3, [pc, #20]	; (efdc <z_setup_new_thread+0x5c>)
	new_thread->fn_abort = NULL;
    efc6:	e9c4 5517 	strd	r5, r5, [r4, #92]	; 0x5c
	if (!_current) {
    efca:	689b      	ldr	r3, [r3, #8]
    efcc:	b103      	cbz	r3, efd0 <z_setup_new_thread+0x50>
	new_thread->resource_pool = _current->resource_pool;
    efce:	6f5b      	ldr	r3, [r3, #116]	; 0x74
}
    efd0:	4640      	mov	r0, r8
    efd2:	6763      	str	r3, [r4, #116]	; 0x74
    efd4:	b004      	add	sp, #16
    efd6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    efda:	bf00      	nop
    efdc:	200102dc 	.word	0x200102dc

0000efe0 <z_init_static_threads>:
{
    efe0:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	_FOREACH_STATIC_THREAD(thread_data) {
    efe4:	4e2a      	ldr	r6, [pc, #168]	; (f090 <z_init_static_threads+0xb0>)
    efe6:	4d2b      	ldr	r5, [pc, #172]	; (f094 <z_init_static_threads+0xb4>)
    efe8:	46b0      	mov	r8, r6
{
    efea:	b086      	sub	sp, #24
	_FOREACH_STATIC_THREAD(thread_data) {
    efec:	42b5      	cmp	r5, r6
    efee:	f105 0430 	add.w	r4, r5, #48	; 0x30
    eff2:	d310      	bcc.n	f016 <z_init_static_threads+0x36>
	k_sched_lock();
    eff4:	f7ff fcb0 	bl	e958 <k_sched_lock>
    eff8:	f44f 4900 	mov.w	r9, #32768	; 0x8000
    effc:	f240 36e7 	movw	r6, #999	; 0x3e7
    f000:	2700      	movs	r7, #0
	_FOREACH_STATIC_THREAD(thread_data) {
    f002:	4c24      	ldr	r4, [pc, #144]	; (f094 <z_init_static_threads+0xb4>)
    f004:	f8df a090 	ldr.w	sl, [pc, #144]	; f098 <z_init_static_threads+0xb8>
    f008:	4544      	cmp	r4, r8
    f00a:	d321      	bcc.n	f050 <z_init_static_threads+0x70>
}
    f00c:	b006      	add	sp, #24
    f00e:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	k_sched_unlock();
    f012:	f7ff bcef 	b.w	e9f4 <k_sched_unlock>
		z_setup_new_thread(
    f016:	f854 3c04 	ldr.w	r3, [r4, #-4]
    f01a:	9305      	str	r3, [sp, #20]
    f01c:	f854 3c10 	ldr.w	r3, [r4, #-16]
    f020:	9304      	str	r3, [sp, #16]
    f022:	f854 3c14 	ldr.w	r3, [r4, #-20]
    f026:	9303      	str	r3, [sp, #12]
    f028:	f854 3c18 	ldr.w	r3, [r4, #-24]
    f02c:	9302      	str	r3, [sp, #8]
    f02e:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    f032:	9301      	str	r3, [sp, #4]
    f034:	f854 3c20 	ldr.w	r3, [r4, #-32]
    f038:	9300      	str	r3, [sp, #0]
    f03a:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    f03e:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    f042:	f7ff ff9d 	bl	ef80 <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    f046:	f854 3c30 	ldr.w	r3, [r4, #-48]
    f04a:	65dd      	str	r5, [r3, #92]	; 0x5c
    f04c:	4625      	mov	r5, r4
    f04e:	e7cd      	b.n	efec <z_init_static_threads+0xc>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    f050:	6a63      	ldr	r3, [r4, #36]	; 0x24
    f052:	1c5a      	adds	r2, r3, #1
    f054:	d00d      	beq.n	f072 <z_init_static_threads+0x92>
    f056:	4630      	mov	r0, r6
    f058:	4639      	mov	r1, r7
					    K_MSEC(thread_data->init_delay));
    f05a:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    f05e:	fbc9 0103 	smlal	r0, r1, r9, r3
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    f062:	42b9      	cmp	r1, r7
    f064:	bf08      	it	eq
    f066:	42b0      	cmpeq	r0, r6
			schedule_new_thread(thread_data->init_thread,
    f068:	6825      	ldr	r5, [r4, #0]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    f06a:	d104      	bne.n	f076 <z_init_static_threads+0x96>
	z_sched_start(thread);
    f06c:	4628      	mov	r0, r5
    f06e:	f7ff fd11 	bl	ea94 <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    f072:	3430      	adds	r4, #48	; 0x30
    f074:	e7c8      	b.n	f008 <z_init_static_threads+0x28>
    f076:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    f07a:	2300      	movs	r3, #0
    f07c:	f7fd f8de 	bl	c23c <__aeabi_uldivmod>
    f080:	4602      	mov	r2, r0
    f082:	460b      	mov	r3, r1
    f084:	f105 0018 	add.w	r0, r5, #24
    f088:	4651      	mov	r1, sl
    f08a:	f000 f853 	bl	f134 <z_add_timeout>
    f08e:	e7f0      	b.n	f072 <z_init_static_threads+0x92>
    f090:	200100fc 	.word	0x200100fc
    f094:	200100fc 	.word	0x200100fc
    f098:	0000fccb 	.word	0x0000fccb

0000f09c <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? z_clock_elapsed() : 0;
    f09c:	4b03      	ldr	r3, [pc, #12]	; (f0ac <elapsed+0x10>)
    f09e:	681b      	ldr	r3, [r3, #0]
    f0a0:	b90b      	cbnz	r3, f0a6 <elapsed+0xa>
    f0a2:	f7fd bfbd 	b.w	d020 <z_clock_elapsed>
}
    f0a6:	2000      	movs	r0, #0
    f0a8:	4770      	bx	lr
    f0aa:	bf00      	nop
    f0ac:	20010318 	.word	0x20010318

0000f0b0 <remove_timeout>:
{
    f0b0:	b530      	push	{r4, r5, lr}
    f0b2:	6803      	ldr	r3, [r0, #0]
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    f0b4:	b168      	cbz	r0, f0d2 <remove_timeout+0x22>
    f0b6:	4a0a      	ldr	r2, [pc, #40]	; (f0e0 <remove_timeout+0x30>)
	return (node == list->tail) ? NULL : node->next;
    f0b8:	6852      	ldr	r2, [r2, #4]
    f0ba:	4290      	cmp	r0, r2
    f0bc:	d009      	beq.n	f0d2 <remove_timeout+0x22>
	if (next(t) != NULL) {
    f0be:	b143      	cbz	r3, f0d2 <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    f0c0:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    f0c4:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    f0c8:	1912      	adds	r2, r2, r4
    f0ca:	eb45 0101 	adc.w	r1, r5, r1
    f0ce:	e9c3 2104 	strd	r2, r1, [r3, #16]
	node->prev->next = node->next;
    f0d2:	6842      	ldr	r2, [r0, #4]
    f0d4:	6013      	str	r3, [r2, #0]
	node->next->prev = node->prev;
    f0d6:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    f0d8:	2300      	movs	r3, #0
	node->prev = NULL;
    f0da:	e9c0 3300 	strd	r3, r3, [r0]
}
    f0de:	bd30      	pop	{r4, r5, pc}
    f0e0:	20010090 	.word	0x20010090

0000f0e4 <next_timeout>:

static int32_t next_timeout(void)
{
    f0e4:	b538      	push	{r3, r4, r5, lr}
	return list->head == list;
    f0e6:	4b11      	ldr	r3, [pc, #68]	; (f12c <next_timeout+0x48>)
    f0e8:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    f0ea:	429c      	cmp	r4, r3
    f0ec:	bf08      	it	eq
    f0ee:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    f0f0:	f7ff ffd4 	bl	f09c <elapsed>
    f0f4:	4605      	mov	r5, r0
	int32_t ret = to == NULL ? MAX_WAIT
    f0f6:	b1ac      	cbz	r4, f124 <next_timeout+0x40>
		: MIN(MAX_WAIT, MAX(0, to->dticks - ticks_elapsed));
    f0f8:	e9d4 0104 	ldrd	r0, r1, [r4, #16]
    f0fc:	1b40      	subs	r0, r0, r5
    f0fe:	eb61 71e5 	sbc.w	r1, r1, r5, asr #31
	int32_t ret = to == NULL ? MAX_WAIT
    f102:	f1b0 4f00 	cmp.w	r0, #2147483648	; 0x80000000
    f106:	f171 0300 	sbcs.w	r3, r1, #0
    f10a:	da0b      	bge.n	f124 <next_timeout+0x40>
		: MIN(MAX_WAIT, MAX(0, to->dticks - ticks_elapsed));
    f10c:	2800      	cmp	r0, #0
    f10e:	f171 0300 	sbcs.w	r3, r1, #0
    f112:	da00      	bge.n	f116 <next_timeout+0x32>
    f114:	2000      	movs	r0, #0

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    f116:	4b06      	ldr	r3, [pc, #24]	; (f130 <next_timeout+0x4c>)
    f118:	691b      	ldr	r3, [r3, #16]
    f11a:	b113      	cbz	r3, f122 <next_timeout+0x3e>
    f11c:	4298      	cmp	r0, r3
    f11e:	bfa8      	it	ge
    f120:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    f122:	bd38      	pop	{r3, r4, r5, pc}
	int32_t ret = to == NULL ? MAX_WAIT
    f124:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    f128:	e7f5      	b.n	f116 <next_timeout+0x32>
    f12a:	bf00      	nop
    f12c:	20010090 	.word	0x20010090
    f130:	200102dc 	.word	0x200102dc

0000f134 <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
    f134:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    f138:	9101      	str	r1, [sp, #4]
    f13a:	4619      	mov	r1, r3
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    f13c:	1c4b      	adds	r3, r1, #1
    f13e:	bf08      	it	eq
    f140:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    f144:	4682      	mov	sl, r0
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    f146:	d06b      	beq.n	f220 <z_add_timeout+0xec>
#ifdef CONFIG_LEGACY_TIMEOUT_API
	k_ticks_t ticks = timeout;
#else
	k_ticks_t ticks = timeout.ticks + 1;

	if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) && Z_TICK_ABS(ticks) >= 0) {
    f148:	f06f 0301 	mvn.w	r3, #1
    f14c:	f04f 3bff 	mov.w	fp, #4294967295
	k_ticks_t ticks = timeout.ticks + 1;
    f150:	1c54      	adds	r4, r2, #1
    f152:	f141 0500 	adc.w	r5, r1, #0
	if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) && Z_TICK_ABS(ticks) >= 0) {
    f156:	ebb3 0804 	subs.w	r8, r3, r4
    f15a:	eb6b 0905 	sbc.w	r9, fp, r5
    f15e:	f1b8 0f00 	cmp.w	r8, #0
    f162:	f179 0300 	sbcs.w	r3, r9, #0
    f166:	db0f      	blt.n	f188 <z_add_timeout+0x54>
		ticks = Z_TICK_ABS(ticks) - (curr_tick + elapsed());
    f168:	f7ff ff98 	bl	f09c <elapsed>
    f16c:	f06f 0301 	mvn.w	r3, #1
    f170:	4a32      	ldr	r2, [pc, #200]	; (f23c <z_add_timeout+0x108>)
    f172:	e9d2 1c00 	ldrd	r1, ip, [r2]
    f176:	1a5b      	subs	r3, r3, r1
    f178:	eb6b 020c 	sbc.w	r2, fp, ip
    f17c:	1b1e      	subs	r6, r3, r4
    f17e:	eb62 0705 	sbc.w	r7, r2, r5
    f182:	1a34      	subs	r4, r6, r0
    f184:	eb67 75e0 	sbc.w	r5, r7, r0, asr #31
	}
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    f188:	9b01      	ldr	r3, [sp, #4]
    f18a:	f8ca 3008 	str.w	r3, [sl, #8]
	__asm__ volatile(
    f18e:	f04f 0320 	mov.w	r3, #32
    f192:	f3ef 8611 	mrs	r6, BASEPRI
    f196:	f383 8811 	msr	BASEPRI, r3
    f19a:	f3bf 8f6f 	isb	sy
	ticks = MAX(1, ticks);

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		to->dticks = ticks + elapsed();
    f19e:	f7ff ff7d 	bl	f09c <elapsed>
	ticks = MAX(1, ticks);
    f1a2:	2c01      	cmp	r4, #1
    f1a4:	f175 0300 	sbcs.w	r3, r5, #0
    f1a8:	bfbc      	itt	lt
    f1aa:	2401      	movlt	r4, #1
    f1ac:	2500      	movlt	r5, #0
	return list->head == list;
    f1ae:	4b24      	ldr	r3, [pc, #144]	; (f240 <z_add_timeout+0x10c>)
		to->dticks = ticks + elapsed();
    f1b0:	1824      	adds	r4, r4, r0
    f1b2:	681a      	ldr	r2, [r3, #0]
    f1b4:	eb45 75e0 	adc.w	r5, r5, r0, asr #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
    f1b8:	429a      	cmp	r2, r3
    f1ba:	e9ca 4504 	strd	r4, r5, [sl, #16]
    f1be:	d001      	beq.n	f1c4 <z_add_timeout+0x90>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    f1c0:	685f      	ldr	r7, [r3, #4]
		for (t = first(); t != NULL; t = next(t)) {
    f1c2:	b952      	cbnz	r2, f1da <z_add_timeout+0xa6>
	node->prev = list->tail;
    f1c4:	685a      	ldr	r2, [r3, #4]
	node->next = list;
    f1c6:	f8ca 3000 	str.w	r3, [sl]
	node->prev = list->tail;
    f1ca:	f8ca 2004 	str.w	r2, [sl, #4]
	list->tail->next = node;
    f1ce:	685a      	ldr	r2, [r3, #4]
    f1d0:	f8c2 a000 	str.w	sl, [r2]
	list->tail = node;
    f1d4:	f8c3 a004 	str.w	sl, [r3, #4]
}
    f1d8:	e014      	b.n	f204 <z_add_timeout+0xd0>
			if (t->dticks > to->dticks) {
    f1da:	e9d2 8904 	ldrd	r8, r9, [r2, #16]
    f1de:	e9da 4504 	ldrd	r4, r5, [sl, #16]
    f1e2:	4544      	cmp	r4, r8
    f1e4:	eb75 0109 	sbcs.w	r1, r5, r9
    f1e8:	da1d      	bge.n	f226 <z_add_timeout+0xf2>
				t->dticks -= to->dticks;
    f1ea:	ebb8 0004 	subs.w	r0, r8, r4
    f1ee:	eb69 0105 	sbc.w	r1, r9, r5
    f1f2:	e9c2 0104 	strd	r0, r1, [r2, #16]
	node->prev = successor->prev;
    f1f6:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
    f1f8:	e9ca 2100 	strd	r2, r1, [sl]
	successor->prev->next = node;
    f1fc:	f8c1 a000 	str.w	sl, [r1]
	successor->prev = node;
    f200:	f8c2 a004 	str.w	sl, [r2, #4]
	return list->head == list;
    f204:	681a      	ldr	r2, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    f206:	429a      	cmp	r2, r3
    f208:	d006      	beq.n	f218 <z_add_timeout+0xe4>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    f20a:	4592      	cmp	sl, r2
    f20c:	d104      	bne.n	f218 <z_add_timeout+0xe4>
			z_clock_set_timeout(next_timeout(), false);
    f20e:	f7ff ff69 	bl	f0e4 <next_timeout>
    f212:	2100      	movs	r1, #0
    f214:	f7fd fe9e 	bl	cf54 <z_clock_set_timeout>
	__asm__ volatile(
    f218:	f386 8811 	msr	BASEPRI, r6
    f21c:	f3bf 8f6f 	isb	sy
		}
	}
}
    f220:	b003      	add	sp, #12
    f222:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			to->dticks -= t->dticks;
    f226:	ebb4 0008 	subs.w	r0, r4, r8
    f22a:	eb65 0109 	sbc.w	r1, r5, r9
	return (node == list->tail) ? NULL : node->next;
    f22e:	42ba      	cmp	r2, r7
    f230:	e9ca 0104 	strd	r0, r1, [sl, #16]
    f234:	d0c6      	beq.n	f1c4 <z_add_timeout+0x90>
    f236:	6812      	ldr	r2, [r2, #0]
    f238:	e7c3      	b.n	f1c2 <z_add_timeout+0x8e>
    f23a:	bf00      	nop
    f23c:	20010200 	.word	0x20010200
    f240:	20010090 	.word	0x20010090

0000f244 <z_clock_announce>:
		}
	}
}

void z_clock_announce(int32_t ticks)
{
    f244:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    f248:	4606      	mov	r6, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    f24a:	f7ff fc7b 	bl	eb44 <z_time_slice>
	__asm__ volatile(
    f24e:	f04f 0320 	mov.w	r3, #32
    f252:	f3ef 8411 	mrs	r4, BASEPRI
    f256:	f383 8811 	msr	BASEPRI, r3
    f25a:	f3bf 8f6f 	isb	sy
#endif

	k_spinlock_key_t key = k_spin_lock(&timeout_lock);

	announce_remaining = ticks;
    f25e:	f8df a0b0 	ldr.w	sl, [pc, #176]	; f310 <z_clock_announce+0xcc>
    f262:	4d2a      	ldr	r5, [pc, #168]	; (f30c <z_clock_announce+0xc8>)
    f264:	4651      	mov	r1, sl
	return list->head == list;
    f266:	f8df b0ac 	ldr.w	fp, [pc, #172]	; f314 <z_clock_announce+0xd0>
    f26a:	602e      	str	r6, [r5, #0]
    f26c:	f8d5 c000 	ldr.w	ip, [r5]
    f270:	f8db 0000 	ldr.w	r0, [fp]
    f274:	4662      	mov	r2, ip
    f276:	e9da 8900 	ldrd	r8, r9, [sl]
    f27a:	17d3      	asrs	r3, r2, #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
    f27c:	4558      	cmp	r0, fp
    f27e:	e9cd 2300 	strd	r2, r3, [sp]
    f282:	d00d      	beq.n	f2a0 <z_clock_announce+0x5c>

	while (first() != NULL && first()->dticks <= announce_remaining) {
    f284:	b160      	cbz	r0, f2a0 <z_clock_announce+0x5c>
    f286:	e9d0 6704 	ldrd	r6, r7, [r0, #16]
    f28a:	45b4      	cmp	ip, r6
    f28c:	41bb      	sbcs	r3, r7
    f28e:	da1d      	bge.n	f2cc <z_clock_announce+0x88>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    f290:	9b00      	ldr	r3, [sp, #0]
    f292:	ebb6 0c03 	subs.w	ip, r6, r3
    f296:	9b01      	ldr	r3, [sp, #4]
    f298:	eb67 0603 	sbc.w	r6, r7, r3
    f29c:	e9c0 c604 	strd	ip, r6, [r0, #16]
	}

	curr_tick += announce_remaining;
	announce_remaining = 0;
    f2a0:	2600      	movs	r6, #0
	curr_tick += announce_remaining;
    f2a2:	9b00      	ldr	r3, [sp, #0]
	announce_remaining = 0;
    f2a4:	602e      	str	r6, [r5, #0]
	curr_tick += announce_remaining;
    f2a6:	eb13 0208 	adds.w	r2, r3, r8
    f2aa:	9b01      	ldr	r3, [sp, #4]
    f2ac:	eb43 0309 	adc.w	r3, r3, r9
    f2b0:	e9c1 2300 	strd	r2, r3, [r1]

	z_clock_set_timeout(next_timeout(), false);
    f2b4:	f7ff ff16 	bl	f0e4 <next_timeout>
    f2b8:	4631      	mov	r1, r6
    f2ba:	f7fd fe4b 	bl	cf54 <z_clock_set_timeout>
	__asm__ volatile(
    f2be:	f384 8811 	msr	BASEPRI, r4
    f2c2:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    f2c6:	b003      	add	sp, #12
    f2c8:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		t->dticks = 0;
    f2cc:	2200      	movs	r2, #0
    f2ce:	2300      	movs	r3, #0
		curr_tick += dt;
    f2d0:	eb18 0806 	adds.w	r8, r8, r6
    f2d4:	eb49 79e6 	adc.w	r9, r9, r6, asr #31
		t->dticks = 0;
    f2d8:	e9c0 2304 	strd	r2, r3, [r0, #16]
		announce_remaining -= dt;
    f2dc:	ebac 0606 	sub.w	r6, ip, r6
		curr_tick += dt;
    f2e0:	e9ca 8900 	strd	r8, r9, [sl]
		announce_remaining -= dt;
    f2e4:	602e      	str	r6, [r5, #0]
		remove_timeout(t);
    f2e6:	f7ff fee3 	bl	f0b0 <remove_timeout>
    f2ea:	f384 8811 	msr	BASEPRI, r4
    f2ee:	f3bf 8f6f 	isb	sy
		t->fn(t);
    f2f2:	6883      	ldr	r3, [r0, #8]
    f2f4:	4798      	blx	r3
	__asm__ volatile(
    f2f6:	f04f 0320 	mov.w	r3, #32
    f2fa:	f3ef 8411 	mrs	r4, BASEPRI
    f2fe:	f383 8811 	msr	BASEPRI, r3
    f302:	f3bf 8f6f 	isb	sy

	/* Note that we need to use the underlying arch-specific lock
	 * implementation.  The "irq_lock()" API in SMP context is
	 * actually a wrapper for a global spinlock!
	 */
	k.key = arch_irq_lock();
    f306:	4902      	ldr	r1, [pc, #8]	; (f310 <z_clock_announce+0xcc>)
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    f308:	e7b0      	b.n	f26c <z_clock_announce+0x28>
    f30a:	bf00      	nop
    f30c:	20010318 	.word	0x20010318
    f310:	20010200 	.word	0x20010200
    f314:	20010090 	.word	0x20010090

0000f318 <z_tick_get>:

int64_t z_tick_get(void)
{
    f318:	b510      	push	{r4, lr}
    f31a:	f04f 0320 	mov.w	r3, #32
    f31e:	f3ef 8411 	mrs	r4, BASEPRI
    f322:	f383 8811 	msr	BASEPRI, r3
    f326:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + z_clock_elapsed();
    f32a:	f7fd fe79 	bl	d020 <z_clock_elapsed>
    f32e:	4b06      	ldr	r3, [pc, #24]	; (f348 <z_tick_get+0x30>)
    f330:	e9d3 2300 	ldrd	r2, r3, [r3]
    f334:	1812      	adds	r2, r2, r0
    f336:	f143 0300 	adc.w	r3, r3, #0
	__asm__ volatile(
    f33a:	f384 8811 	msr	BASEPRI, r4
    f33e:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    f342:	4610      	mov	r0, r2
    f344:	4619      	mov	r1, r3
    f346:	bd10      	pop	{r4, pc}
    f348:	20010200 	.word	0x20010200

0000f34c <statics_init>:
	z_waitq_init(&h->wait_q);
	sys_heap_init(&h->heap, mem, bytes);
}

static int statics_init(const struct device *unused)
{
    f34c:	b538      	push	{r3, r4, r5, lr}
	ARG_UNUSED(unused);
	Z_STRUCT_SECTION_FOREACH(k_heap, h) {
    f34e:	4c06      	ldr	r4, [pc, #24]	; (f368 <statics_init+0x1c>)
    f350:	4d06      	ldr	r5, [pc, #24]	; (f36c <statics_init+0x20>)
    f352:	42ac      	cmp	r4, r5
    f354:	d301      	bcc.n	f35a <statics_init+0xe>
		k_heap_init(h, h->heap.init_mem, h->heap.init_bytes);
	}
	return 0;
}
    f356:	2000      	movs	r0, #0
    f358:	bd38      	pop	{r3, r4, r5, pc}
		k_heap_init(h, h->heap.init_mem, h->heap.init_bytes);
    f35a:	4620      	mov	r0, r4
    f35c:	e9d4 1201 	ldrd	r1, r2, [r4, #4]
    f360:	f000 fd6f 	bl	fe42 <k_heap_init>
	Z_STRUCT_SECTION_FOREACH(k_heap, h) {
    f364:	3414      	adds	r4, #20
    f366:	e7f4      	b.n	f352 <statics_init+0x6>
    f368:	200100fc 	.word	0x200100fc
    f36c:	200100fc 	.word	0x200100fc

0000f370 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    f370:	4603      	mov	r3, r0
    f372:	b158      	cbz	r0, f38c <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    f374:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    f376:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    f37a:	2a01      	cmp	r2, #1
    f37c:	d003      	beq.n	f386 <sys_notify_validate+0x16>
    f37e:	2a03      	cmp	r2, #3
    f380:	d104      	bne.n	f38c <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    f382:	6802      	ldr	r2, [r0, #0]
    f384:	b112      	cbz	r2, f38c <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    f386:	2000      	movs	r0, #0
    f388:	6098      	str	r0, [r3, #8]
    f38a:	4770      	bx	lr
		return -EINVAL;
    f38c:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    f390:	4770      	bx	lr

0000f392 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    f392:	6842      	ldr	r2, [r0, #4]

sys_notify_generic_callback sys_notify_finalize(struct sys_notify *notify,
						    int res)
{
    f394:	4603      	mov	r3, r0
	return method & SYS_NOTIFY_METHOD_MASK;
    f396:	f002 0203 	and.w	r2, r2, #3

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
	switch (method) {
    f39a:	2a03      	cmp	r2, #3
    f39c:	f04f 0200 	mov.w	r2, #0
	notify->result = res;
    f3a0:	6081      	str	r1, [r0, #8]
	sys_notify_generic_callback rv = 0;
    f3a2:	bf14      	ite	ne
    f3a4:	4610      	movne	r0, r2
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    f3a6:	6800      	ldreq	r0, [r0, #0]
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    f3a8:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    f3aa:	4770      	bx	lr

0000f3ac <arch_printk_char_out>:
}
    f3ac:	2000      	movs	r0, #0
    f3ae:	4770      	bx	lr

0000f3b0 <printk>:
 * @param fmt formatted string to output
 *
 * @return N/A
 */
void printk(const char *fmt, ...)
{
    f3b0:	b40f      	push	{r0, r1, r2, r3}
    f3b2:	b507      	push	{r0, r1, r2, lr}
    f3b4:	a904      	add	r1, sp, #16
    f3b6:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    f3ba:	9101      	str	r1, [sp, #4]

	if (IS_ENABLED(CONFIG_LOG_PRINTK)) {
		log_printk(fmt, ap);
	} else {
		vprintk(fmt, ap);
    f3bc:	f7fd fab0 	bl	c920 <vprintk>
	}
	va_end(ap);
}
    f3c0:	b003      	add	sp, #12
    f3c2:	f85d eb04 	ldr.w	lr, [sp], #4
    f3c6:	b004      	add	sp, #16
    f3c8:	4770      	bx	lr

0000f3ca <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    f3ca:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    f3cc:	f013 0307 	ands.w	r3, r3, #7
    f3d0:	d105      	bne.n	f3de <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    f3d2:	6803      	ldr	r3, [r0, #0]
    f3d4:	2b00      	cmp	r3, #0
		evt = EVT_START;
    f3d6:	bf0c      	ite	eq
    f3d8:	2000      	moveq	r0, #0
    f3da:	2003      	movne	r0, #3
    f3dc:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    f3de:	2b02      	cmp	r3, #2
    f3e0:	d105      	bne.n	f3ee <process_recheck+0x24>
		   && (mgr->refs == 0)) {
    f3e2:	8b43      	ldrh	r3, [r0, #26]
    f3e4:	2b00      	cmp	r3, #0
		evt = EVT_STOP;
    f3e6:	bf14      	ite	ne
    f3e8:	2000      	movne	r0, #0
    f3ea:	2004      	moveq	r0, #4
    f3ec:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    f3ee:	2b01      	cmp	r3, #1
    f3f0:	d105      	bne.n	f3fe <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    f3f2:	6803      	ldr	r3, [r0, #0]
    f3f4:	2b00      	cmp	r3, #0
		evt = EVT_RESET;
    f3f6:	bf0c      	ite	eq
    f3f8:	2000      	moveq	r0, #0
    f3fa:	2005      	movne	r0, #5
    f3fc:	4770      	bx	lr
	int evt = EVT_NOP;
    f3fe:	2000      	movs	r0, #0
}
    f400:	4770      	bx	lr

0000f402 <notify_one>:
{
    f402:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    f406:	460d      	mov	r5, r1
    f408:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    f40a:	4619      	mov	r1, r3
    f40c:	1d28      	adds	r0, r5, #4
{
    f40e:	4690      	mov	r8, r2
    f410:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    f412:	f7ff ffbe 	bl	f392 <sys_notify_finalize>
	if (cb) {
    f416:	4604      	mov	r4, r0
    f418:	b138      	cbz	r0, f42a <notify_one+0x28>
		cb(mgr, cli, state, res);
    f41a:	4633      	mov	r3, r6
    f41c:	4642      	mov	r2, r8
    f41e:	4629      	mov	r1, r5
    f420:	4638      	mov	r0, r7
    f422:	46a4      	mov	ip, r4
}
    f424:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    f428:	4760      	bx	ip
}
    f42a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

0000f42e <transition_complete>:
{
    f42e:	b410      	push	{r4}
	__asm__ volatile(
    f430:	f04f 0420 	mov.w	r4, #32
    f434:	f3ef 8211 	mrs	r2, BASEPRI
    f438:	f384 8811 	msr	BASEPRI, r4
    f43c:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    f440:	6141      	str	r1, [r0, #20]
}
    f442:	bc10      	pop	{r4}
	process_event(mgr, EVT_COMPLETE, key);
    f444:	2101      	movs	r1, #1
    f446:	f7fd ba79 	b.w	c93c <process_event>

0000f44a <validate_args>:
{
    f44a:	b510      	push	{r4, lr}
    f44c:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    f44e:	b140      	cbz	r0, f462 <validate_args+0x18>
    f450:	b139      	cbz	r1, f462 <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
    f452:	1d08      	adds	r0, r1, #4
    f454:	f7ff ff8c 	bl	f370 <sys_notify_validate>
	if ((rv == 0)
    f458:	b928      	cbnz	r0, f466 <validate_args+0x1c>
	    && ((cli->notify.flags
    f45a:	68a3      	ldr	r3, [r4, #8]
    f45c:	f033 0303 	bics.w	r3, r3, #3
    f460:	d001      	beq.n	f466 <validate_args+0x1c>
		rv = -EINVAL;
    f462:	f06f 0015 	mvn.w	r0, #21
}
    f466:	bd10      	pop	{r4, pc}

0000f468 <onoff_manager_init>:
{
    f468:	b538      	push	{r3, r4, r5, lr}
    f46a:	460c      	mov	r4, r1
	if ((mgr == NULL)
    f46c:	4605      	mov	r5, r0
    f46e:	b158      	cbz	r0, f488 <onoff_manager_init+0x20>
	    || (transitions == NULL)
    f470:	b151      	cbz	r1, f488 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    f472:	680b      	ldr	r3, [r1, #0]
    f474:	b143      	cbz	r3, f488 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    f476:	684b      	ldr	r3, [r1, #4]
    f478:	b133      	cbz	r3, f488 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    f47a:	221c      	movs	r2, #28
    f47c:	2100      	movs	r1, #0
    f47e:	f000 fa56 	bl	f92e <memset>
	return 0;
    f482:	2000      	movs	r0, #0
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    f484:	612c      	str	r4, [r5, #16]
}
    f486:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    f488:	f06f 0015 	mvn.w	r0, #21
    f48c:	e7fb      	b.n	f486 <onoff_manager_init+0x1e>

0000f48e <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    f48e:	b570      	push	{r4, r5, r6, lr}
    f490:	4604      	mov	r4, r0
    f492:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    f494:	f7ff ffd9 	bl	f44a <validate_args>

	if (rv < 0) {
    f498:	1e05      	subs	r5, r0, #0
    f49a:	db31      	blt.n	f500 <onoff_request+0x72>
    f49c:	f04f 0320 	mov.w	r3, #32
    f4a0:	f3ef 8111 	mrs	r1, BASEPRI
    f4a4:	f383 8811 	msr	BASEPRI, r3
    f4a8:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    f4ac:	f64f 75ff 	movw	r5, #65535	; 0xffff
    f4b0:	8b63      	ldrh	r3, [r4, #26]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    f4b2:	8b20      	ldrh	r0, [r4, #24]
	if (mgr->refs == SERVICE_REFS_MAX) {
    f4b4:	42ab      	cmp	r3, r5
    f4b6:	f000 0207 	and.w	r2, r0, #7
    f4ba:	d02e      	beq.n	f51a <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
    f4bc:	2a02      	cmp	r2, #2
    f4be:	d10e      	bne.n	f4de <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
    f4c0:	3301      	adds	r3, #1
    f4c2:	8363      	strh	r3, [r4, #26]
	rv = state;
    f4c4:	4615      	mov	r5, r2
		notify = true;
    f4c6:	2301      	movs	r3, #1
	__asm__ volatile(
    f4c8:	f381 8811 	msr	BASEPRI, r1
    f4cc:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    f4d0:	b1b3      	cbz	r3, f500 <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
    f4d2:	2300      	movs	r3, #0
    f4d4:	4631      	mov	r1, r6
    f4d6:	4620      	mov	r0, r4
    f4d8:	f7ff ff93 	bl	f402 <notify_one>
    f4dc:	e010      	b.n	f500 <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
    f4de:	0783      	lsls	r3, r0, #30
    f4e0:	d001      	beq.n	f4e6 <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
    f4e2:	2a06      	cmp	r2, #6
    f4e4:	d10e      	bne.n	f504 <onoff_request+0x76>
	parent->next = child;
    f4e6:	2300      	movs	r3, #0
    f4e8:	6033      	str	r3, [r6, #0]
Z_GENLIST_APPEND(slist, snode)
    f4ea:	6863      	ldr	r3, [r4, #4]
    f4ec:	b993      	cbnz	r3, f514 <onoff_request+0x86>
	list->head = node;
    f4ee:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
    f4f2:	4615      	mov	r5, r2
    f4f4:	b962      	cbnz	r2, f510 <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
    f4f6:	460a      	mov	r2, r1
    f4f8:	4620      	mov	r0, r4
    f4fa:	2102      	movs	r1, #2
    f4fc:	f7fd fa1e 	bl	c93c <process_event>
		}
	}

	return rv;
}
    f500:	4628      	mov	r0, r5
    f502:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
    f504:	2a05      	cmp	r2, #5
    f506:	bf0c      	ite	eq
    f508:	f06f 0522 	mvneq.w	r5, #34	; 0x22
    f50c:	f06f 0504 	mvnne.w	r5, #4
    f510:	2300      	movs	r3, #0
    f512:	e7d9      	b.n	f4c8 <onoff_request+0x3a>
	parent->next = child;
    f514:	601e      	str	r6, [r3, #0]
	list->tail = node;
    f516:	6066      	str	r6, [r4, #4]
}
    f518:	e7eb      	b.n	f4f2 <onoff_request+0x64>
		rv = -EAGAIN;
    f51a:	f06f 050a 	mvn.w	r5, #10
    f51e:	e7f7      	b.n	f510 <onoff_request+0x82>

0000f520 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    f520:	4604      	mov	r4, r0
    f522:	b508      	push	{r3, lr}
    f524:	4608      	mov	r0, r1
    f526:	4611      	mov	r1, r2
	entry(p1, p2, p3);
    f528:	461a      	mov	r2, r3
    f52a:	47a0      	blx	r4
	return z_impl_k_current_get();
    f52c:	f7ff fcd8 	bl	eee0 <z_impl_k_current_get>
	z_impl_k_thread_abort(thread);
    f530:	f7fd ffd8 	bl	d4e4 <z_impl_k_thread_abort>

0000f534 <chunk_field>:
				 enum chunk_fields f)
{
	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];

	if (big_heap(h)) {
    f534:	6883      	ldr	r3, [r0, #8]
	void *cmem = &buf[c];
    f536:	eb00 01c1 	add.w	r1, r0, r1, lsl #3
	if (big_heap(h)) {
    f53a:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
		return ((uint32_t *)cmem)[f];
    f53e:	bf2c      	ite	cs
    f540:	f851 0022 	ldrcs.w	r0, [r1, r2, lsl #2]
	} else {
		return ((uint16_t *)cmem)[f];
    f544:	f831 0012 	ldrhcc.w	r0, [r1, r2, lsl #1]
	}
}
    f548:	4770      	bx	lr

0000f54a <chunk_set>:
			     enum chunk_fields f, chunkid_t val)
{
	CHECK(c <= h->len);

	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];
    f54a:	eb00 01c1 	add.w	r1, r0, r1, lsl #3

	if (big_heap(h)) {
    f54e:	6880      	ldr	r0, [r0, #8]
    f550:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
		CHECK(val == (uint32_t)val);
		((uint32_t *)cmem)[f] = val;
    f554:	bf2c      	ite	cs
    f556:	f841 3022 	strcs.w	r3, [r1, r2, lsl #2]
	} else {
		CHECK(val == (uint16_t)val);
		((uint16_t *)cmem)[f] = val;
    f55a:	f821 3012 	strhcc.w	r3, [r1, r2, lsl #1]
	}
}
    f55e:	4770      	bx	lr

0000f560 <chunk_size>:
	return chunk_field(h, c, SIZE_AND_USED) & 1;
}

static inline size_t chunk_size(struct z_heap *h, chunkid_t c)
{
	return chunk_field(h, c, SIZE_AND_USED) >> 1;
    f560:	2201      	movs	r2, #1
{
    f562:	b508      	push	{r3, lr}
	return chunk_field(h, c, SIZE_AND_USED) >> 1;
    f564:	f7ff ffe6 	bl	f534 <chunk_field>
}
    f568:	0840      	lsrs	r0, r0, #1
    f56a:	bd08      	pop	{r3, pc}

0000f56c <set_chunk_used>:
static inline void set_chunk_used(struct z_heap *h, chunkid_t c, bool used)
{
	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];

	if (big_heap(h)) {
    f56c:	6883      	ldr	r3, [r0, #8]
	void *cmem = &buf[c];
    f56e:	eb00 01c1 	add.w	r1, r0, r1, lsl #3
	if (big_heap(h)) {
    f572:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
    f576:	d308      	bcc.n	f58a <set_chunk_used+0x1e>
		if (used) {
    f578:	684b      	ldr	r3, [r1, #4]
    f57a:	b11a      	cbz	r2, f584 <set_chunk_used+0x18>
			((uint32_t *)cmem)[SIZE_AND_USED] |= 1;
    f57c:	f043 0301 	orr.w	r3, r3, #1
		} else {
			((uint32_t *)cmem)[SIZE_AND_USED] &= ~1;
    f580:	604b      	str	r3, [r1, #4]
    f582:	4770      	bx	lr
    f584:	f023 0301 	bic.w	r3, r3, #1
    f588:	e7fa      	b.n	f580 <set_chunk_used+0x14>
		}
	} else {
		if (used) {
    f58a:	884b      	ldrh	r3, [r1, #2]
    f58c:	b11a      	cbz	r2, f596 <set_chunk_used+0x2a>
			((uint16_t *)cmem)[SIZE_AND_USED] |= 1;
    f58e:	f043 0301 	orr.w	r3, r3, #1
		} else {
			((uint16_t *)cmem)[SIZE_AND_USED] &= ~1;
    f592:	804b      	strh	r3, [r1, #2]
		}
	}
}
    f594:	4770      	bx	lr
			((uint16_t *)cmem)[SIZE_AND_USED] &= ~1;
    f596:	f023 0301 	bic.w	r3, r3, #1
    f59a:	e7fa      	b.n	f592 <set_chunk_used+0x26>

0000f59c <set_chunk_size>:
 * when its size is modified, and potential set_chunk_used() is always
 * invoked after set_chunk_size().
 */
static inline void set_chunk_size(struct z_heap *h, chunkid_t c, size_t size)
{
	chunk_set(h, c, SIZE_AND_USED, size << 1);
    f59c:	0053      	lsls	r3, r2, #1
    f59e:	2201      	movs	r2, #1
    f5a0:	f7ff bfd3 	b.w	f54a <chunk_set>

0000f5a4 <bucket_idx>:
	return big_heap(h) && chunk_size(h, c) == 1;
}

static inline size_t chunk_header_bytes(struct z_heap *h)
{
	return big_heap(h) ? 8 : 4;
    f5a4:	6880      	ldr	r0, [r0, #8]
	return bytes_to_chunksz(h, 1);
}

static inline int bucket_idx(struct z_heap *h, size_t sz)
{
	size_t usable_sz = sz - min_chunk_size(h) + 1;
    f5a6:	3101      	adds	r1, #1
	return (bytes + CHUNK_UNIT - 1) / CHUNK_UNIT;
    f5a8:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
    f5ac:	bf2c      	ite	cs
    f5ae:	2002      	movcs	r0, #2
    f5b0:	2001      	movcc	r0, #1
	size_t usable_sz = sz - min_chunk_size(h) + 1;
    f5b2:	1a08      	subs	r0, r1, r0
	return 31 - __builtin_clz(usable_sz);
    f5b4:	fab0 f080 	clz	r0, r0
}
    f5b8:	f1c0 001f 	rsb	r0, r0, #31
    f5bc:	4770      	bx	lr

0000f5be <free_list_add>:
		set_prev_free_chunk(h, second, c);
	}
}

static void free_list_add(struct z_heap *h, chunkid_t c)
{
    f5be:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    f5c2:	4604      	mov	r4, r0
    f5c4:	460d      	mov	r5, r1
	return sizeof(void *) > 4 || chunks > 0x7fff;
    f5c6:	f7ff ffcb 	bl	f560 <chunk_size>
	return big_heap(h) && chunk_size(h, c) == 1;
    f5ca:	68a3      	ldr	r3, [r4, #8]
    f5cc:	4601      	mov	r1, r0
    f5ce:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
    f5d2:	d301      	bcc.n	f5d8 <free_list_add+0x1a>
	if (!solo_free_header(h, c)) {
    f5d4:	2801      	cmp	r0, #1
    f5d6:	d035      	beq.n	f644 <free_list_add+0x86>
		int bidx = bucket_idx(h, chunk_size(h, c));
    f5d8:	4620      	mov	r0, r4
    f5da:	f7ff ffe3 	bl	f5a4 <bucket_idx>
	if (b->next == 0) {
    f5de:	eb04 0280 	add.w	r2, r4, r0, lsl #2
    f5e2:	6916      	ldr	r6, [r2, #16]
    f5e4:	b99e      	cbnz	r6, f60e <free_list_add+0x50>
		h->avail_buckets |= (1 << bidx);
    f5e6:	2301      	movs	r3, #1
    f5e8:	fa03 f000 	lsl.w	r0, r3, r0
    f5ec:	68e3      	ldr	r3, [r4, #12]
	chunk_set(h, c, FREE_PREV, prev);
    f5ee:	4629      	mov	r1, r5
    f5f0:	4303      	orrs	r3, r0
    f5f2:	60e3      	str	r3, [r4, #12]
    f5f4:	4620      	mov	r0, r4
		b->next = c;
    f5f6:	6115      	str	r5, [r2, #16]
    f5f8:	462b      	mov	r3, r5
    f5fa:	2202      	movs	r2, #2
    f5fc:	f7ff ffa5 	bl	f54a <chunk_set>
	chunk_set(h, c, FREE_NEXT, next);
    f600:	2203      	movs	r2, #3
    f602:	4629      	mov	r1, r5
	chunk_set(h, c, FREE_PREV, prev);
    f604:	4620      	mov	r0, r4
		free_list_add_bidx(h, c, bidx);
	}
}
    f606:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    f60a:	f7ff bf9e 	b.w	f54a <chunk_set>
	return chunk_field(h, c, FREE_PREV);
    f60e:	2202      	movs	r2, #2
    f610:	4631      	mov	r1, r6
    f612:	4620      	mov	r0, r4
    f614:	f7ff ff8e 	bl	f534 <chunk_field>
    f618:	4607      	mov	r7, r0
	chunk_set(h, c, FREE_PREV, prev);
    f61a:	4603      	mov	r3, r0
    f61c:	2202      	movs	r2, #2
    f61e:	4629      	mov	r1, r5
    f620:	4620      	mov	r0, r4
    f622:	f7ff ff92 	bl	f54a <chunk_set>
	chunk_set(h, c, FREE_NEXT, next);
    f626:	4633      	mov	r3, r6
    f628:	2203      	movs	r2, #3
    f62a:	4629      	mov	r1, r5
    f62c:	4620      	mov	r0, r4
    f62e:	f7ff ff8c 	bl	f54a <chunk_set>
    f632:	2203      	movs	r2, #3
    f634:	4639      	mov	r1, r7
    f636:	462b      	mov	r3, r5
    f638:	4620      	mov	r0, r4
    f63a:	f7ff ff86 	bl	f54a <chunk_set>
	chunk_set(h, c, FREE_PREV, prev);
    f63e:	2202      	movs	r2, #2
    f640:	4631      	mov	r1, r6
    f642:	e7df      	b.n	f604 <free_list_add+0x46>
    f644:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

0000f648 <sys_heap_init>:
	return big_heap_bytes(size) ? 8 : 4;
    f648:	f5b2 2f80 	cmp.w	r2, #262144	; 0x40000
	set_chunk_used(h, c, true);
	return mem;
}

void sys_heap_init(struct sys_heap *heap, void *mem, size_t bytes)
{
    f64c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    f64e:	bf2c      	ite	cs
    f650:	2508      	movcs	r5, #8
    f652:	2504      	movcc	r5, #4
	CHECK(end > addr);
	__ASSERT(buf_sz > chunksz(sizeof(struct z_heap)), "heap size is too small");

	struct z_heap *h = (struct z_heap *)addr;
	heap->heap = h;
	h->chunk0_hdr_area = 0;
    f654:	2300      	movs	r3, #0
	bytes -= heap_footer_bytes(bytes);
    f656:	1b55      	subs	r5, r2, r5
	h->chunk0_hdr_area = 0;
    f658:	2200      	movs	r2, #0
	uintptr_t addr = ROUND_UP(mem, CHUNK_UNIT);
    f65a:	1dcc      	adds	r4, r1, #7
    f65c:	f024 0407 	bic.w	r4, r4, #7
	heap->heap = h;
    f660:	6004      	str	r4, [r0, #0]
	h->chunk0_hdr_area = 0;
    f662:	e9c4 2300 	strd	r2, r3, [r4]
	h->len = buf_sz;
	h->avail_buckets = 0;
    f666:	2300      	movs	r3, #0
	uintptr_t end = ROUND_DOWN((uint8_t *)mem + bytes, CHUNK_UNIT);
    f668:	440d      	add	r5, r1
    f66a:	f025 0507 	bic.w	r5, r5, #7
	size_t buf_sz = (end - addr) / CHUNK_UNIT;
    f66e:	1b2d      	subs	r5, r5, r4
    f670:	08ed      	lsrs	r5, r5, #3

	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    f672:	4629      	mov	r1, r5
    f674:	4620      	mov	r0, r4
	h->len = buf_sz;
    f676:	60a5      	str	r5, [r4, #8]
	h->avail_buckets = 0;
    f678:	60e3      	str	r3, [r4, #12]
	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    f67a:	f7ff ff93 	bl	f5a4 <bucket_idx>
	size_t chunk0_size = chunksz(sizeof(struct z_heap) +
    f67e:	0086      	lsls	r6, r0, #2
	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    f680:	1c41      	adds	r1, r0, #1
				     nb_buckets * sizeof(struct z_heap_bucket));

	__ASSERT(chunk0_size + min_chunk_size(h) < buf_sz, "heap size is too small");

	for (int i = 0; i < nb_buckets; i++) {
		h->buckets[i].next = 0;
    f682:	4618      	mov	r0, r3
	return (bytes + CHUNK_UNIT - 1) / CHUNK_UNIT;
    f684:	361b      	adds	r6, #27
    f686:	08f6      	lsrs	r6, r6, #3
	for (int i = 0; i < nb_buckets; i++) {
    f688:	f104 0210 	add.w	r2, r4, #16
    f68c:	428b      	cmp	r3, r1
    f68e:	db29      	blt.n	f6e4 <sys_heap_init+0x9c>
	}

	/* chunk containing our struct z_heap */
	set_chunk_size(h, 0, chunk0_size);
    f690:	4632      	mov	r2, r6
    f692:	4620      	mov	r0, r4
    f694:	2100      	movs	r1, #0
    f696:	f7ff ff81 	bl	f59c <set_chunk_size>
	set_chunk_used(h, 0, true);

	/* chunk containing the free heap */
	set_chunk_size(h, chunk0_size, buf_sz - chunk0_size);
    f69a:	1baf      	subs	r7, r5, r6
	set_chunk_used(h, 0, true);
    f69c:	4620      	mov	r0, r4
    f69e:	2201      	movs	r2, #1
    f6a0:	2100      	movs	r1, #0
    f6a2:	f7ff ff63 	bl	f56c <set_chunk_used>
	set_chunk_size(h, chunk0_size, buf_sz - chunk0_size);
    f6a6:	463a      	mov	r2, r7
    f6a8:	4631      	mov	r1, r6
    f6aa:	f7ff ff77 	bl	f59c <set_chunk_size>
	chunk_set(h, c, LEFT_SIZE, size);
    f6ae:	4633      	mov	r3, r6
    f6b0:	4631      	mov	r1, r6
    f6b2:	4620      	mov	r0, r4
    f6b4:	2200      	movs	r2, #0
    f6b6:	f7ff ff48 	bl	f54a <chunk_set>
	set_left_chunk_size(h, chunk0_size, chunk0_size);

	/* the end marker chunk */
	set_chunk_size(h, buf_sz, 0);
    f6ba:	4629      	mov	r1, r5
    f6bc:	4620      	mov	r0, r4
    f6be:	2200      	movs	r2, #0
    f6c0:	f7ff ff6c 	bl	f59c <set_chunk_size>
    f6c4:	463b      	mov	r3, r7
    f6c6:	4629      	mov	r1, r5
    f6c8:	4620      	mov	r0, r4
    f6ca:	2200      	movs	r2, #0
    f6cc:	f7ff ff3d 	bl	f54a <chunk_set>
	set_left_chunk_size(h, buf_sz, buf_sz - chunk0_size);
	set_chunk_used(h, buf_sz, true);
    f6d0:	4629      	mov	r1, r5
    f6d2:	4620      	mov	r0, r4
    f6d4:	2201      	movs	r2, #1
    f6d6:	f7ff ff49 	bl	f56c <set_chunk_used>

	free_list_add(h, chunk0_size);
    f6da:	4631      	mov	r1, r6
}
    f6dc:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
	free_list_add(h, chunk0_size);
    f6e0:	f7ff bf6d 	b.w	f5be <free_list_add>
		h->buckets[i].next = 0;
    f6e4:	f842 0b04 	str.w	r0, [r2], #4
	for (int i = 0; i < nb_buckets; i++) {
    f6e8:	3301      	adds	r3, #1
    f6ea:	e7cf      	b.n	f68c <sys_heap_init+0x44>

0000f6ec <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM(CONFIG_DEPRECATED_ZEPHYR_INT_TYPES, 1);
GEN_ABSOLUTE_SYM(CONFIG_REBOOT, 1);
GEN_ABSOLUTE_SYM(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    f6ec:	4770      	bx	lr

0000f6ee <z_platform_init>:

void z_platform_init(void)
{
	SystemInit();
    f6ee:	f7fe bd75 	b.w	e1dc <SystemInit>

0000f6f2 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    f6f2:	b2cb      	uxtb	r3, r1
    f6f4:	210c      	movs	r1, #12
    f6f6:	68c2      	ldr	r2, [r0, #12]
    f6f8:	fb03 2101 	mla	r1, r3, r1, r2
    f6fc:	6c08      	ldr	r0, [r1, #64]	; 0x40
}
    f6fe:	f000 0007 	and.w	r0, r0, #7
    f702:	4770      	bx	lr

0000f704 <set_off_state>:
	__asm__ volatile(
    f704:	f04f 0320 	mov.w	r3, #32
    f708:	f3ef 8211 	mrs	r2, BASEPRI
    f70c:	f383 8811 	msr	BASEPRI, r3
    f710:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    f714:	6803      	ldr	r3, [r0, #0]
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    f716:	f013 03c0 	ands.w	r3, r3, #192	; 0xc0
    f71a:	d001      	beq.n	f720 <set_off_state+0x1c>
    f71c:	428b      	cmp	r3, r1
    f71e:	d107      	bne.n	f730 <set_off_state+0x2c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    f720:	2301      	movs	r3, #1
    f722:	6003      	str	r3, [r0, #0]
	int err = 0;
    f724:	2000      	movs	r0, #0
	__asm__ volatile(
    f726:	f382 8811 	msr	BASEPRI, r2
    f72a:	f3bf 8f6f 	isb	sy
}
    f72e:	4770      	bx	lr
		err = -EPERM;
    f730:	f04f 30ff 	mov.w	r0, #4294967295
    f734:	e7f7      	b.n	f726 <set_off_state+0x22>

0000f736 <set_starting_state>:
{
    f736:	b510      	push	{r4, lr}
	__asm__ volatile(
    f738:	f04f 0320 	mov.w	r3, #32
    f73c:	f3ef 8211 	mrs	r2, BASEPRI
    f740:	f383 8811 	msr	BASEPRI, r3
    f744:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    f748:	6803      	ldr	r3, [r0, #0]
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    f74a:	f003 0407 	and.w	r4, r3, #7
    f74e:	2c01      	cmp	r4, #1
    f750:	d106      	bne.n	f760 <set_starting_state+0x2a>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    f752:	6001      	str	r1, [r0, #0]
	int err = 0;
    f754:	2000      	movs	r0, #0
	__asm__ volatile(
    f756:	f382 8811 	msr	BASEPRI, r2
    f75a:	f3bf 8f6f 	isb	sy
}
    f75e:	bd10      	pop	{r4, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    f760:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
	} else if (current_ctx != ctx) {
    f764:	428b      	cmp	r3, r1
		err = -EBUSY;
    f766:	bf14      	ite	ne
    f768:	f04f 30ff 	movne.w	r0, #4294967295
    f76c:	f06f 000f 	mvneq.w	r0, #15
    f770:	e7f1      	b.n	f756 <set_starting_state+0x20>

0000f772 <set_on_state>:
	__asm__ volatile(
    f772:	f04f 0320 	mov.w	r3, #32
    f776:	f3ef 8211 	mrs	r2, BASEPRI
    f77a:	f383 8811 	msr	BASEPRI, r3
    f77e:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    f782:	6803      	ldr	r3, [r0, #0]
    f784:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    f788:	f043 0302 	orr.w	r3, r3, #2
    f78c:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    f78e:	f382 8811 	msr	BASEPRI, r2
    f792:	f3bf 8f6f 	isb	sy
}
    f796:	4770      	bx	lr

0000f798 <onoff_started_callback>:
{
    f798:	b410      	push	{r4}
	notify(mgr, 0);
    f79a:	241c      	movs	r4, #28
	return &data->mgr[type];
    f79c:	68c0      	ldr	r0, [r0, #12]
    f79e:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    f7a0:	fb03 0004 	mla	r0, r3, r4, r0
    f7a4:	2100      	movs	r1, #0
}
    f7a6:	bc10      	pop	{r4}
	notify(mgr, 0);
    f7a8:	4710      	bx	r2

0000f7aa <blocking_start_callback>:
{
    f7aa:	4610      	mov	r0, r2
	z_impl_k_sem_give(sem);
    f7ac:	f7ff bb9e 	b.w	eeec <z_impl_k_sem_give>

0000f7b0 <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    f7b0:	2000      	movs	r0, #0
    f7b2:	f7fe bd5d 	b.w	e270 <nrfx_clock_stop>

0000f7b6 <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    f7b6:	2000      	movs	r0, #0
    f7b8:	f7fe bd28 	b.w	e20c <nrfx_clock_start>

0000f7bc <api_stop>:
{
    f7bc:	b538      	push	{r3, r4, r5, lr}
	err = set_off_state(&subdata->flags, ctx);
    f7be:	230c      	movs	r3, #12
    f7c0:	b2cc      	uxtb	r4, r1
    f7c2:	4363      	muls	r3, r4
{
    f7c4:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
    f7c6:	68c0      	ldr	r0, [r0, #12]
    f7c8:	3340      	adds	r3, #64	; 0x40
    f7ca:	2180      	movs	r1, #128	; 0x80
    f7cc:	4418      	add	r0, r3
    f7ce:	f7ff ff99 	bl	f704 <set_off_state>
	if (err < 0) {
    f7d2:	2800      	cmp	r0, #0
    f7d4:	db05      	blt.n	f7e2 <api_stop+0x26>
	get_sub_config(dev, type)->stop();
    f7d6:	6869      	ldr	r1, [r5, #4]
    f7d8:	eb01 04c4 	add.w	r4, r1, r4, lsl #3
    f7dc:	6863      	ldr	r3, [r4, #4]
    f7de:	4798      	blx	r3
	return 0;
    f7e0:	2000      	movs	r0, #0
}
    f7e2:	bd38      	pop	{r3, r4, r5, pc}

0000f7e4 <api_start>:
{
    f7e4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	err = set_starting_state(&subdata->flags, ctx);
    f7e8:	f04f 080c 	mov.w	r8, #12
    f7ec:	b2cd      	uxtb	r5, r1
    f7ee:	fb08 f805 	mul.w	r8, r8, r5
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    f7f2:	68c4      	ldr	r4, [r0, #12]
{
    f7f4:	4606      	mov	r6, r0
	err = set_starting_state(&subdata->flags, ctx);
    f7f6:	f108 0040 	add.w	r0, r8, #64	; 0x40
    f7fa:	2180      	movs	r1, #128	; 0x80
    f7fc:	4420      	add	r0, r4
{
    f7fe:	4617      	mov	r7, r2
	err = set_starting_state(&subdata->flags, ctx);
    f800:	f7ff ff99 	bl	f736 <set_starting_state>
	if (err < 0) {
    f804:	2800      	cmp	r0, #0
    f806:	db09      	blt.n	f81c <api_start+0x38>
	subdata->cb = data->cb;
    f808:	687b      	ldr	r3, [r7, #4]
    f80a:	4444      	add	r4, r8
    f80c:	63a3      	str	r3, [r4, #56]	; 0x38
	subdata->user_data = data->user_data;
    f80e:	68bb      	ldr	r3, [r7, #8]
    f810:	63e3      	str	r3, [r4, #60]	; 0x3c
	 get_sub_config(dev, type)->start();
    f812:	6873      	ldr	r3, [r6, #4]
    f814:	f853 3035 	ldr.w	r3, [r3, r5, lsl #3]
    f818:	4798      	blx	r3
	return 0;
    f81a:	2000      	movs	r0, #0
}
    f81c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

0000f820 <z_clock_isr>:
/* Weak-linked noop defaults for optional driver interfaces: */

void __weak z_clock_isr(void *arg)
{
	__ASSERT_NO_MSG(false);
}
    f820:	4770      	bx	lr

0000f822 <z_clock_idle_exit>:
{
}

void __weak z_clock_idle_exit(void)
{
}
    f822:	4770      	bx	lr

0000f824 <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    f824:	2100      	movs	r1, #0
    f826:	2001      	movs	r0, #1
    f828:	f000 b804 	b.w	f834 <z_arm_fatal_error>

0000f82c <configure_builtin_stack_guard>:
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    f82c:	6e83      	ldr	r3, [r0, #104]	; 0x68
    f82e:	f383 880b 	msr	PSPLIM, r3
}
    f832:	4770      	bx	lr

0000f834 <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    f834:	f000 b9f0 	b.w	fc18 <z_fatal_error>

0000f838 <z_do_kernel_oops>:
 *   fault handler will executed insted of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    f838:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
    f83a:	6800      	ldr	r0, [r0, #0]
    f83c:	f000 b9ec 	b.w	fc18 <z_fatal_error>

0000f840 <z_arm_nmi>:
 *
 * @return N/A
 */

void z_arm_nmi(void)
{
    f840:	b508      	push	{r3, lr}
	handler();
    f842:	f7fd fd07 	bl	d254 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    f846:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    f84a:	f7fd bd49 	b.w	d2e0 <z_arm_exc_exit>

0000f84e <mpu_configure_region>:
{
    f84e:	b530      	push	{r4, r5, lr}
	get_region_attr_from_k_mem_partition_info(&region_conf.attr,
    f850:	684b      	ldr	r3, [r1, #4]
	region_conf.base = new_region->start;
    f852:	680c      	ldr	r4, [r1, #0]
{
    f854:	b085      	sub	sp, #20
	p_attr->rbar = attr->rbar &
    f856:	890a      	ldrh	r2, [r1, #8]
    f858:	7a8d      	ldrb	r5, [r1, #10]
	region_conf.base = new_region->start;
    f85a:	9400      	str	r4, [sp, #0]
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
    f85c:	3b01      	subs	r3, #1
    f85e:	f024 041f 	bic.w	r4, r4, #31
    f862:	4423      	add	r3, r4
	p_attr->rbar = attr->rbar &
    f864:	f002 021f 	and.w	r2, r2, #31
    f868:	ea42 1245 	orr.w	r2, r2, r5, lsl #5
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
    f86c:	f023 031f 	bic.w	r3, r3, #31
	if (index > (get_num_regions() - 1)) {
    f870:	280f      	cmp	r0, #15
    f872:	4604      	mov	r4, r0
	p_attr->rbar = attr->rbar &
    f874:	f88d 2008 	strb.w	r2, [sp, #8]
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
    f878:	9303      	str	r3, [sp, #12]
    f87a:	d805      	bhi.n	f888 <mpu_configure_region+0x3a>
	region_init(index, region_conf);
    f87c:	4669      	mov	r1, sp
    f87e:	f7fd fe87 	bl	d590 <region_init>
}
    f882:	4620      	mov	r0, r4
    f884:	b005      	add	sp, #20
    f886:	bd30      	pop	{r4, r5, pc}
		return -EINVAL;
    f888:	f06f 0415 	mvn.w	r4, #21
	return region_allocate_and_init(index,
    f88c:	e7f9      	b.n	f882 <mpu_configure_region+0x34>

0000f88e <arm_cmse_mpu_region_get>:
__CMSE_TT_ASM ()

__extension__ static __inline __attribute__ ((__always_inline__))
cmse_address_info_t
cmse_TT (void *__p)
__CMSE_TT_ASM ()
    f88e:	e840 f300 	tt	r3, r0

int arm_cmse_mpu_region_get(uint32_t addr)
{
	cmse_address_info_t addr_info =	cmse_TT((void *)addr);

	if (addr_info.flags.mpu_region_valid) {
    f892:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    f896:	b2d8      	uxtb	r0, r3
		return addr_info.flags.mpu_region;
	}

	return -EINVAL;
}
    f898:	bf08      	it	eq
    f89a:	f06f 0015 	mvneq.w	r0, #21
    f89e:	4770      	bx	lr

0000f8a0 <strcmp>:
 * @return negative # if <s1> < <s2>, 0 if <s1> == <s2>, else positive #
 */

int strcmp(const char *s1, const char *s2)
{
	while ((*s1 == *s2) && (*s1 != '\0')) {
    f8a0:	1e43      	subs	r3, r0, #1
    f8a2:	3901      	subs	r1, #1
    f8a4:	f813 2f01 	ldrb.w	r2, [r3, #1]!
    f8a8:	f811 0f01 	ldrb.w	r0, [r1, #1]!
    f8ac:	4282      	cmp	r2, r0
    f8ae:	d101      	bne.n	f8b4 <strcmp+0x14>
    f8b0:	2a00      	cmp	r2, #0
    f8b2:	d1f7      	bne.n	f8a4 <strcmp+0x4>
		s1++;
		s2++;
	}

	return *s1 - *s2;
}
    f8b4:	1a10      	subs	r0, r2, r0
    f8b6:	4770      	bx	lr

0000f8b8 <memcmp>:
 * @brief Compare two memory areas
 *
 * @return negative # if <m1> < <m2>, 0 if <m1> == <m2>, else positive #
 */
int memcmp(const void *m1, const void *m2, size_t n)
{
    f8b8:	b510      	push	{r4, lr}
	const char *c1 = m1;
	const char *c2 = m2;

	if (!n) {
    f8ba:	b15a      	cbz	r2, f8d4 <memcmp+0x1c>
    f8bc:	3901      	subs	r1, #1
    f8be:	1884      	adds	r4, r0, r2
		return 0;
	}

	while ((--n > 0) && (*c1 == *c2)) {
    f8c0:	f810 2b01 	ldrb.w	r2, [r0], #1
    f8c4:	f811 3f01 	ldrb.w	r3, [r1, #1]!
    f8c8:	42a0      	cmp	r0, r4
    f8ca:	d001      	beq.n	f8d0 <memcmp+0x18>
    f8cc:	429a      	cmp	r2, r3
    f8ce:	d0f7      	beq.n	f8c0 <memcmp+0x8>
		c1++;
		c2++;
	}

	return *c1 - *c2;
    f8d0:	1ad0      	subs	r0, r2, r3
}
    f8d2:	bd10      	pop	{r4, pc}
		return 0;
    f8d4:	4610      	mov	r0, r2
    f8d6:	e7fc      	b.n	f8d2 <memcmp+0x1a>

0000f8d8 <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *_MLIBC_RESTRICT d, const void *_MLIBC_RESTRICT s, size_t n)
{
    f8d8:	b5f0      	push	{r4, r5, r6, r7, lr}

	unsigned char *d_byte = (unsigned char *)d;
	const unsigned char *s_byte = (const unsigned char *)s;
	const uintptr_t mask = sizeof(mem_word_t) - 1;

	if ((((uintptr_t)d ^ (uintptr_t)s_byte) & mask) == 0) {
    f8da:	ea81 0400 	eor.w	r4, r1, r0
    f8de:	07a5      	lsls	r5, r4, #30
    f8e0:	4603      	mov	r3, r0
    f8e2:	d00b      	beq.n	f8fc <memcpy+0x24>
    f8e4:	3b01      	subs	r3, #1
    f8e6:	440a      	add	r2, r1
		s_byte = (unsigned char *)s_word;
	}

	/* do byte-sized copying until finished */

	while (n > 0) {
    f8e8:	4291      	cmp	r1, r2
    f8ea:	d11b      	bne.n	f924 <memcpy+0x4c>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    f8ec:	bdf0      	pop	{r4, r5, r6, r7, pc}
			if (n == 0) {
    f8ee:	2a00      	cmp	r2, #0
    f8f0:	d0fc      	beq.n	f8ec <memcpy+0x14>
			*(d_byte++) = *(s_byte++);
    f8f2:	f811 4b01 	ldrb.w	r4, [r1], #1
			n--;
    f8f6:	3a01      	subs	r2, #1
			*(d_byte++) = *(s_byte++);
    f8f8:	f803 4b01 	strb.w	r4, [r3], #1
		while (((uintptr_t)d_byte) & mask) {
    f8fc:	079c      	lsls	r4, r3, #30
    f8fe:	d1f6      	bne.n	f8ee <memcpy+0x16>
    f900:	f022 0403 	bic.w	r4, r2, #3
    f904:	1f1d      	subs	r5, r3, #4
    f906:	0896      	lsrs	r6, r2, #2
    f908:	190f      	adds	r7, r1, r4
		while (n >= sizeof(mem_word_t)) {
    f90a:	42b9      	cmp	r1, r7
    f90c:	d105      	bne.n	f91a <memcpy+0x42>
    f90e:	f06f 0503 	mvn.w	r5, #3
    f912:	4423      	add	r3, r4
    f914:	fb05 2206 	mla	r2, r5, r6, r2
    f918:	e7e4      	b.n	f8e4 <memcpy+0xc>
			*(d_word++) = *(s_word++);
    f91a:	f851 cb04 	ldr.w	ip, [r1], #4
    f91e:	f845 cf04 	str.w	ip, [r5, #4]!
			n -= sizeof(mem_word_t);
    f922:	e7f2      	b.n	f90a <memcpy+0x32>
		*(d_byte++) = *(s_byte++);
    f924:	f811 4b01 	ldrb.w	r4, [r1], #1
    f928:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    f92c:	e7dc      	b.n	f8e8 <memcpy+0x10>

0000f92e <memset>:

void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
    f92e:	4603      	mov	r3, r0
{
    f930:	b570      	push	{r4, r5, r6, lr}
	unsigned char c_byte = (unsigned char)c;
    f932:	b2c9      	uxtb	r1, r1

	while (((uintptr_t)d_byte) & (sizeof(mem_word_t) - 1)) {
    f934:	079c      	lsls	r4, r3, #30
    f936:	d111      	bne.n	f95c <memset+0x2e>
	/* do word-sized initialization as long as possible */

	mem_word_t *d_word = (mem_word_t *)d_byte;
	mem_word_t c_word = (mem_word_t)c_byte;

	c_word |= c_word << 8;
    f938:	ea41 2401 	orr.w	r4, r1, r1, lsl #8
	c_word |= c_word << 16;
    f93c:	f022 0603 	bic.w	r6, r2, #3
    f940:	ea44 4504 	orr.w	r5, r4, r4, lsl #16
#if Z_MEM_WORD_T_WIDTH > 32
	c_word |= c_word << 32;
#endif

	while (n >= sizeof(mem_word_t)) {
    f944:	441e      	add	r6, r3
    f946:	0894      	lsrs	r4, r2, #2
    f948:	42b3      	cmp	r3, r6
    f94a:	d10d      	bne.n	f968 <memset+0x3a>
    f94c:	f06f 0503 	mvn.w	r5, #3
    f950:	fb05 2204 	mla	r2, r5, r4, r2
    f954:	441a      	add	r2, r3

	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;

	while (n > 0) {
    f956:	4293      	cmp	r3, r2
    f958:	d109      	bne.n	f96e <memset+0x40>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    f95a:	bd70      	pop	{r4, r5, r6, pc}
		if (n == 0) {
    f95c:	2a00      	cmp	r2, #0
    f95e:	d0fc      	beq.n	f95a <memset+0x2c>
		*(d_byte++) = c_byte;
    f960:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    f964:	3a01      	subs	r2, #1
    f966:	e7e5      	b.n	f934 <memset+0x6>
		*(d_word++) = c_word;
    f968:	f843 5b04 	str.w	r5, [r3], #4
		n -= sizeof(mem_word_t);
    f96c:	e7ec      	b.n	f948 <memset+0x1a>
		*(d_byte++) = c_byte;
    f96e:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    f972:	e7f0      	b.n	f956 <memset+0x28>

0000f974 <_stdout_hook_default>:
}
    f974:	f04f 30ff 	mov.w	r0, #4294967295
    f978:	4770      	bx	lr

0000f97a <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    f97a:	6843      	ldr	r3, [r0, #4]
}
    f97c:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    f97e:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    f980:	691b      	ldr	r3, [r3, #16]
	*value = nrf_gpio_port_in_read(reg);
    f982:	600b      	str	r3, [r1, #0]
}
    f984:	4770      	bx	lr

0000f986 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    f986:	6843      	ldr	r3, [r0, #4]
    f988:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
    f98a:	6858      	ldr	r0, [r3, #4]
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
    f98c:	4042      	eors	r2, r0
    f98e:	400a      	ands	r2, r1
    f990:	4042      	eors	r2, r0
    p_reg->OUT = value;
    f992:	605a      	str	r2, [r3, #4]
}
    f994:	2000      	movs	r0, #0
    f996:	4770      	bx	lr

0000f998 <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    f998:	6843      	ldr	r3, [r0, #4]
}
    f99a:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    f99c:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTSET = set_mask;
    f99e:	6099      	str	r1, [r3, #8]
}
    f9a0:	4770      	bx	lr

0000f9a2 <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    f9a2:	6843      	ldr	r3, [r0, #4]
}
    f9a4:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    f9a6:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTCLR = clr_mask;
    f9a8:	60d9      	str	r1, [r3, #12]
}
    f9aa:	4770      	bx	lr

0000f9ac <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    f9ac:	6843      	ldr	r3, [r0, #4]
}
    f9ae:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    f9b0:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    f9b2:	6853      	ldr	r3, [r2, #4]
	nrf_gpio_port_out_write(reg, value ^ mask);
    f9b4:	404b      	eors	r3, r1
    p_reg->OUT = value;
    f9b6:	6053      	str	r3, [r2, #4]
}
    f9b8:	4770      	bx	lr

0000f9ba <gpio_nrfx_manage_callback>:
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    f9ba:	68c3      	ldr	r3, [r0, #12]
{
    f9bc:	b530      	push	{r4, r5, lr}
Z_GENLIST_IS_EMPTY(slist)
    f9be:	6858      	ldr	r0, [r3, #4]
	if (!sys_slist_is_empty(callbacks)) {
    f9c0:	b158      	cbz	r0, f9da <gpio_nrfx_manage_callback+0x20>
 * @return true if node was removed
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    f9c2:	2400      	movs	r4, #0
    f9c4:	4281      	cmp	r1, r0
    f9c6:	d113      	bne.n	f9f0 <gpio_nrfx_manage_callback+0x36>
Z_GENLIST_REMOVE(slist, snode)
    f9c8:	6808      	ldr	r0, [r1, #0]
    f9ca:	b95c      	cbnz	r4, f9e4 <gpio_nrfx_manage_callback+0x2a>
    f9cc:	689c      	ldr	r4, [r3, #8]
	list->head = node;
    f9ce:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    f9d0:	42a1      	cmp	r1, r4
    f9d2:	d100      	bne.n	f9d6 <gpio_nrfx_manage_callback+0x1c>
	list->tail = node;
    f9d4:	6098      	str	r0, [r3, #8]
	parent->next = child;
    f9d6:	2000      	movs	r0, #0
    f9d8:	6008      	str	r0, [r1, #0]
	if (set) {
    f9da:	b972      	cbnz	r2, f9fa <gpio_nrfx_manage_callback+0x40>
	return 0;
    f9dc:	2000      	movs	r0, #0
}
    f9de:	bd30      	pop	{r4, r5, pc}
    f9e0:	4628      	mov	r0, r5
    f9e2:	e7ef      	b.n	f9c4 <gpio_nrfx_manage_callback+0xa>
    f9e4:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
    f9e6:	6898      	ldr	r0, [r3, #8]
    f9e8:	4281      	cmp	r1, r0
	list->tail = node;
    f9ea:	bf08      	it	eq
    f9ec:	609c      	streq	r4, [r3, #8]
}
    f9ee:	e7f2      	b.n	f9d6 <gpio_nrfx_manage_callback+0x1c>
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    f9f0:	6805      	ldr	r5, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    f9f2:	4604      	mov	r4, r0
    f9f4:	2d00      	cmp	r5, #0
    f9f6:	d1f3      	bne.n	f9e0 <gpio_nrfx_manage_callback+0x26>
			if (!set) {
    f9f8:	b13a      	cbz	r2, fa0a <gpio_nrfx_manage_callback+0x50>
Z_GENLIST_PREPEND(slist, snode)
    f9fa:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
    f9fc:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
    f9fe:	6898      	ldr	r0, [r3, #8]
	list->head = node;
    fa00:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    fa02:	2800      	cmp	r0, #0
    fa04:	d1ea      	bne.n	f9dc <gpio_nrfx_manage_callback+0x22>
	list->tail = node;
    fa06:	6099      	str	r1, [r3, #8]
}
    fa08:	e7e9      	b.n	f9de <gpio_nrfx_manage_callback+0x24>
				return -EINVAL;
    fa0a:	f06f 0015 	mvn.w	r0, #21
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    fa0e:	e7e6      	b.n	f9de <gpio_nrfx_manage_callback+0x24>

0000fa10 <gpio_pin_set>:

	(void)cfg;
	__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
		 "Unsupported pin");

	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    fa10:	2301      	movs	r3, #1
    fa12:	fa03 f101 	lsl.w	r1, r3, r1
    fa16:	68c3      	ldr	r3, [r0, #12]
    fa18:	681b      	ldr	r3, [r3, #0]
    fa1a:	4219      	tst	r1, r3
		value = (value != 0) ? 0 : 1;
    fa1c:	bf18      	it	ne
    fa1e:	f082 0201 	eorne.w	r2, r2, #1
	if (value != 0)	{
    fa22:	b112      	cbz	r2, fa2a <gpio_pin_set+0x1a>
	return api->port_set_bits_raw(port, pins);
    fa24:	6883      	ldr	r3, [r0, #8]
    fa26:	68db      	ldr	r3, [r3, #12]
	return api->port_clear_bits_raw(port, pins);
    fa28:	4718      	bx	r3
    fa2a:	6883      	ldr	r3, [r0, #8]
    fa2c:	691b      	ldr	r3, [r3, #16]
    fa2e:	e7fb      	b.n	fa28 <gpio_pin_set+0x18>

0000fa30 <_spi_context_cs_control.isra.0>:
static inline void _spi_context_cs_control(struct spi_context *ctx,
    fa30:	b538      	push	{r3, r4, r5, lr}
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio_dev) {
    fa32:	6805      	ldr	r5, [r0, #0]
static inline void _spi_context_cs_control(struct spi_context *ctx,
    fa34:	4604      	mov	r4, r0
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio_dev) {
    fa36:	b1fd      	cbz	r5, fa78 <_spi_context_cs_control.isra.0+0x48>
    fa38:	68ab      	ldr	r3, [r5, #8]
    fa3a:	b1eb      	cbz	r3, fa78 <_spi_context_cs_control.isra.0+0x48>
    fa3c:	6818      	ldr	r0, [r3, #0]
    fa3e:	b1d8      	cbz	r0, fa78 <_spi_context_cs_control.isra.0+0x48>
		if (on) {
    fa40:	b151      	cbz	r1, fa58 <_spi_context_cs_control.isra.0+0x28>
			gpio_pin_set(ctx->config->cs->gpio_dev,
    fa42:	7a19      	ldrb	r1, [r3, #8]
    fa44:	2201      	movs	r2, #1
    fa46:	f7ff ffe3 	bl	fa10 <gpio_pin_set>
			k_busy_wait(ctx->config->cs->delay);
    fa4a:	6823      	ldr	r3, [r4, #0]
    fa4c:	689b      	ldr	r3, [r3, #8]
    fa4e:	6858      	ldr	r0, [r3, #4]
}
    fa50:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_impl_k_busy_wait(usec_to_wait);
    fa54:	f000 b9af 	b.w	fdb6 <z_impl_k_busy_wait>
			if (!force_off &&
    fa58:	b912      	cbnz	r2, fa60 <_spi_context_cs_control.isra.0+0x30>
    fa5a:	88aa      	ldrh	r2, [r5, #4]
    fa5c:	0492      	lsls	r2, r2, #18
    fa5e:	d40b      	bmi.n	fa78 <_spi_context_cs_control.isra.0+0x48>
			k_busy_wait(ctx->config->cs->delay);
    fa60:	6858      	ldr	r0, [r3, #4]
    fa62:	f000 f9a8 	bl	fdb6 <z_impl_k_busy_wait>
			gpio_pin_set(ctx->config->cs->gpio_dev,
    fa66:	6823      	ldr	r3, [r4, #0]
    fa68:	2200      	movs	r2, #0
    fa6a:	689b      	ldr	r3, [r3, #8]
    fa6c:	7a19      	ldrb	r1, [r3, #8]
    fa6e:	6818      	ldr	r0, [r3, #0]
}
    fa70:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
			gpio_pin_set(ctx->config->cs->gpio_dev,
    fa74:	f7ff bfcc 	b.w	fa10 <gpio_pin_set>
}
    fa78:	bd38      	pop	{r3, r4, r5, pc}

0000fa7a <spi_context_unlock_unconditionally>:
{
    fa7a:	b510      	push	{r4, lr}
	_spi_context_cs_control(ctx, false, true);
    fa7c:	2201      	movs	r2, #1
    fa7e:	2100      	movs	r1, #0
{
    fa80:	4604      	mov	r4, r0
	_spi_context_cs_control(ctx, false, true);
    fa82:	f7ff ffd5 	bl	fa30 <_spi_context_cs_control.isra.0>
	if (!k_sem_count_get(&ctx->lock)) {
    fa86:	68e3      	ldr	r3, [r4, #12]
    fa88:	b923      	cbnz	r3, fa94 <spi_context_unlock_unconditionally+0x1a>
	z_impl_k_sem_give(sem);
    fa8a:	1d20      	adds	r0, r4, #4
}
    fa8c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    fa90:	f7ff ba2c 	b.w	eeec <z_impl_k_sem_give>
    fa94:	bd10      	pop	{r4, pc}

0000fa96 <spi_nrfx_release>:
	struct spi_nrfx_data *dev_data = get_dev_data(dev);
    fa96:	68c0      	ldr	r0, [r0, #12]
{
    fa98:	b510      	push	{r4, lr}
	if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
    fa9a:	6803      	ldr	r3, [r0, #0]
    fa9c:	428b      	cmp	r3, r1
    fa9e:	d106      	bne.n	faae <spi_nrfx_release+0x18>
	if (dev_data->busy) {
    faa0:	f890 4050 	ldrb.w	r4, [r0, #80]	; 0x50
    faa4:	b934      	cbnz	r4, fab4 <spi_nrfx_release+0x1e>
	spi_context_unlock_unconditionally(&dev_data->ctx);
    faa6:	f7ff ffe8 	bl	fa7a <spi_context_unlock_unconditionally>
	return 0;
    faaa:	4620      	mov	r0, r4
}
    faac:	bd10      	pop	{r4, pc}
		return -EINVAL;
    faae:	f06f 0015 	mvn.w	r0, #21
    fab2:	e7fb      	b.n	faac <spi_nrfx_release+0x16>
		return -EBUSY;
    fab4:	f06f 000f 	mvn.w	r0, #15
    fab8:	e7f8      	b.n	faac <spi_nrfx_release+0x16>

0000faba <event_handler>:
	if (p_event->type == NRFX_SPIM_EVENT_DONE) {
    faba:	7803      	ldrb	r3, [r0, #0]
    fabc:	2b00      	cmp	r3, #0
    fabe:	d135      	bne.n	fb2c <event_handler+0x72>
	if (!ctx->tx_len) {
    fac0:	6bca      	ldr	r2, [r1, #60]	; 0x3c
		spi_context_update_tx(&dev_data->ctx, 1, dev_data->chunk_len);
    fac2:	6ccb      	ldr	r3, [r1, #76]	; 0x4c
    fac4:	b182      	cbz	r2, fae8 <event_handler+0x2e>
	if (len > ctx->tx_len) {
    fac6:	4293      	cmp	r3, r2
    fac8:	d80e      	bhi.n	fae8 <event_handler+0x2e>
	ctx->tx_len -= len;
    faca:	1ad2      	subs	r2, r2, r3
    facc:	63ca      	str	r2, [r1, #60]	; 0x3c
	if (!ctx->tx_len) {
    face:	bb0a      	cbnz	r2, fb14 <event_handler+0x5a>
		ctx->tx_count--;
    fad0:	6aca      	ldr	r2, [r1, #44]	; 0x2c
    fad2:	3a01      	subs	r2, #1
    fad4:	62ca      	str	r2, [r1, #44]	; 0x2c
		if (ctx->tx_count) {
    fad6:	b30a      	cbz	r2, fb1c <event_handler+0x62>
			ctx->current_tx++;
    fad8:	6a8a      	ldr	r2, [r1, #40]	; 0x28
    fada:	f102 0008 	add.w	r0, r2, #8
    fade:	6288      	str	r0, [r1, #40]	; 0x28
			ctx->tx_buf = (const uint8_t *)ctx->current_tx->buf;
    fae0:	6890      	ldr	r0, [r2, #8]
			ctx->tx_len = ctx->current_tx->len / dfs;
    fae2:	68d2      	ldr	r2, [r2, #12]
			ctx->tx_buf = (const uint8_t *)ctx->current_tx->buf;
    fae4:	6388      	str	r0, [r1, #56]	; 0x38
			ctx->tx_len = ctx->current_tx->len / dfs;
    fae6:	63ca      	str	r2, [r1, #60]	; 0x3c
	if (!ctx->rx_len) {
    fae8:	6c4a      	ldr	r2, [r1, #68]	; 0x44
    faea:	b182      	cbz	r2, fb0e <event_handler+0x54>
	if (len > ctx->rx_len) {
    faec:	4293      	cmp	r3, r2
    faee:	d80e      	bhi.n	fb0e <event_handler+0x54>
	ctx->rx_len -= len;
    faf0:	1ad2      	subs	r2, r2, r3
    faf2:	644a      	str	r2, [r1, #68]	; 0x44
	if (!ctx->rx_len) {
    faf4:	b9a2      	cbnz	r2, fb20 <event_handler+0x66>
		ctx->rx_count--;
    faf6:	6b4b      	ldr	r3, [r1, #52]	; 0x34
    faf8:	3b01      	subs	r3, #1
    fafa:	634b      	str	r3, [r1, #52]	; 0x34
		if (ctx->rx_count) {
    fafc:	b1a3      	cbz	r3, fb28 <event_handler+0x6e>
			ctx->current_rx++;
    fafe:	6b0b      	ldr	r3, [r1, #48]	; 0x30
    fb00:	f103 0208 	add.w	r2, r3, #8
    fb04:	630a      	str	r2, [r1, #48]	; 0x30
			ctx->rx_buf = (uint8_t *)ctx->current_rx->buf;
    fb06:	689a      	ldr	r2, [r3, #8]
			ctx->rx_len = ctx->current_rx->len / dfs;
    fb08:	68db      	ldr	r3, [r3, #12]
			ctx->rx_buf = (uint8_t *)ctx->current_rx->buf;
    fb0a:	640a      	str	r2, [r1, #64]	; 0x40
			ctx->rx_len = ctx->current_rx->len / dfs;
    fb0c:	644b      	str	r3, [r1, #68]	; 0x44
		transfer_next_chunk(dev_data->dev);
    fb0e:	6c88      	ldr	r0, [r1, #72]	; 0x48
    fb10:	f7fe b8b4 	b.w	dc7c <transfer_next_chunk>
	} else if (ctx->tx_buf) {
    fb14:	6b8a      	ldr	r2, [r1, #56]	; 0x38
    fb16:	2a00      	cmp	r2, #0
    fb18:	d0e6      	beq.n	fae8 <event_handler+0x2e>
		ctx->tx_buf += dfs * len;
    fb1a:	441a      	add	r2, r3
    fb1c:	638a      	str	r2, [r1, #56]	; 0x38
    fb1e:	e7e3      	b.n	fae8 <event_handler+0x2e>
	} else if (ctx->rx_buf) {
    fb20:	6c0a      	ldr	r2, [r1, #64]	; 0x40
    fb22:	2a00      	cmp	r2, #0
    fb24:	d0f3      	beq.n	fb0e <event_handler+0x54>
		ctx->rx_buf += dfs * len;
    fb26:	4413      	add	r3, r2
    fb28:	640b      	str	r3, [r1, #64]	; 0x40
    fb2a:	e7f0      	b.n	fb0e <event_handler+0x54>
}
    fb2c:	4770      	bx	lr

0000fb2e <uarte_nrfx_config_get>:
{
    fb2e:	460b      	mov	r3, r1
	*cfg = get_dev_data(dev)->uart_config;
    fb30:	68c2      	ldr	r2, [r0, #12]
    fb32:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    fb36:	e883 0003 	stmia.w	r3, {r0, r1}
}
    fb3a:	2000      	movs	r0, #0
    fb3c:	4770      	bx	lr

0000fb3e <uarte_nrfx_err_check>:
	return config->uarte_regs;
    fb3e:	6843      	ldr	r3, [r0, #4]
    fb40:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    fb42:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    fb46:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    fb4a:	4770      	bx	lr

0000fb4c <uarte_nrfx_poll_in>:
	return config->uarte_regs;
    fb4c:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = get_dev_data(dev);
    fb4e:	68c2      	ldr	r2, [r0, #12]
	return config->uarte_regs;
    fb50:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    fb52:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    fb56:	b148      	cbz	r0, fb6c <uarte_nrfx_poll_in+0x20>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    fb58:	2000      	movs	r0, #0
	*c = data->rx_data;
    fb5a:	7c12      	ldrb	r2, [r2, #16]
    fb5c:	700a      	strb	r2, [r1, #0]
    fb5e:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    fb62:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    fb66:	2201      	movs	r2, #1
    fb68:	601a      	str	r2, [r3, #0]
	return 0;
    fb6a:	4770      	bx	lr
		return -1;
    fb6c:	f04f 30ff 	mov.w	r0, #4294967295
}
    fb70:	4770      	bx	lr

0000fb72 <uarte_nrfx_poll_out>:
{
    fb72:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
	return config->uarte_regs;
    fb76:	6843      	ldr	r3, [r0, #4]
{
    fb78:	f88d 1007 	strb.w	r1, [sp, #7]
	return config->uarte_regs;
    fb7c:	681c      	ldr	r4, [r3, #0]
	struct uarte_nrfx_data *data = get_dev_data(dev);
    fb7e:	68c6      	ldr	r6, [r0, #12]
	if (!k_is_in_isr()) {
    fb80:	f000 f913 	bl	fdaa <k_is_in_isr>
    fb84:	bb98      	cbnz	r0, fbee <uarte_nrfx_poll_out+0x7c>
		lock = &data->poll_out_lock;
    fb86:	2564      	movs	r5, #100	; 0x64
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    fb88:	f04f 0801 	mov.w	r8, #1
    fb8c:	f106 070c 	add.w	r7, r6, #12
    fb90:	e8d7 3fef 	ldaex	r3, [r7]
    fb94:	2b00      	cmp	r3, #0
    fb96:	d103      	bne.n	fba0 <uarte_nrfx_poll_out+0x2e>
    fb98:	e8c7 8fe2 	stlex	r2, r8, [r7]
    fb9c:	2a00      	cmp	r2, #0
    fb9e:	d1f7      	bne.n	fb90 <uarte_nrfx_poll_out+0x1e>
		while (atomic_cas((atomic_t *) lock,
    fba0:	d007      	beq.n	fbb2 <uarte_nrfx_poll_out+0x40>
	return z_impl_k_sleep(timeout);
    fba2:	2021      	movs	r0, #33	; 0x21
    fba4:	2100      	movs	r1, #0
    fba6:	3d01      	subs	r5, #1
    fba8:	f7ff f97a 	bl	eea0 <z_impl_k_sleep>
			if (--safety_cnt == 0) {
    fbac:	f015 05ff 	ands.w	r5, r5, #255	; 0xff
    fbb0:	d1ee      	bne.n	fb90 <uarte_nrfx_poll_out+0x1e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    fbb2:	2300      	movs	r3, #0
    fbb4:	f8c4 3120 	str.w	r3, [r4, #288]	; 0x120
    fbb8:	f8d4 3120 	ldr.w	r3, [r4, #288]	; 0x120
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    fbbc:	f10d 0307 	add.w	r3, sp, #7
    fbc0:	f8c4 3544 	str.w	r3, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    fbc4:	2301      	movs	r3, #1
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    fbc6:	f44f 757a 	mov.w	r5, #1000	; 0x3e8
    p_reg->TXD.MAXCNT = length;
    fbca:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    fbce:	60a3      	str	r3, [r4, #8]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    fbd0:	f8d4 3120 	ldr.w	r3, [r4, #288]	; 0x120
	NRFX_WAIT_FOR(nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX),
    fbd4:	b923      	cbnz	r3, fbe0 <uarte_nrfx_poll_out+0x6e>
    fbd6:	2001      	movs	r0, #1
    fbd8:	f000 f811 	bl	fbfe <nrfx_busy_wait>
    fbdc:	3d01      	subs	r5, #1
    fbde:	d1f7      	bne.n	fbd0 <uarte_nrfx_poll_out+0x5e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    fbe0:	2301      	movs	r3, #1
    fbe2:	60e3      	str	r3, [r4, #12]
	*lock = 0;
    fbe4:	2300      	movs	r3, #0
    fbe6:	60f3      	str	r3, [r6, #12]
}
    fbe8:	b002      	add	sp, #8
    fbea:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		*lock = 1;
    fbee:	2301      	movs	r3, #1
    fbf0:	60f3      	str	r3, [r6, #12]
    fbf2:	e7de      	b.n	fbb2 <uarte_nrfx_poll_out+0x40>

0000fbf4 <k_sys_fatal_error_handler>:
	ARG_UNUSED(reason);

	LOG_PANIC();

	LOG_ERR("Resetting system");
	sys_arch_reboot(0);
    fbf4:	2000      	movs	r0, #0
{
    fbf6:	b508      	push	{r3, lr}
	sys_arch_reboot(0);
    fbf8:	f7fd fc56 	bl	d4a8 <sys_arch_reboot>

0000fbfc <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    fbfc:	4700      	bx	r0

0000fbfe <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    fbfe:	f000 b8da 	b.w	fdb6 <z_impl_k_busy_wait>

0000fc02 <nrfx_clock_enable>:
{
    fc02:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    fc04:	2005      	movs	r0, #5
    fc06:	f7fd fa4f 	bl	d0a8 <arch_irq_is_enabled>
    fc0a:	b920      	cbnz	r0, fc16 <nrfx_clock_enable+0x14>
}
    fc0c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    fc10:	2005      	movs	r0, #5
    fc12:	f7fd ba39 	b.w	d088 <arch_irq_enable>
    fc16:	bd08      	pop	{r3, pc}

0000fc18 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    fc18:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    fc1a:	4605      	mov	r5, r0
    fc1c:	460e      	mov	r6, r1
	__asm__ volatile(
    fc1e:	f04f 0320 	mov.w	r3, #32
    fc22:	f3ef 8711 	mrs	r7, BASEPRI
    fc26:	f383 8811 	msr	BASEPRI, r3
    fc2a:	f3bf 8f6f 	isb	sy
	return z_impl_k_current_get();
    fc2e:	f7ff f957 	bl	eee0 <z_impl_k_current_get>
	LOG_ERR("Current thread: %p (%s)", thread,
		log_strdup(thread_name_get(thread)));

	z_coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    fc32:	4631      	mov	r1, r6
    fc34:	4604      	mov	r4, r0
    fc36:	4628      	mov	r0, r5
    fc38:	f7ff ffdc 	bl	fbf4 <k_sys_fatal_error_handler>
	__asm__ volatile(
    fc3c:	f387 8811 	msr	BASEPRI, r7
    fc40:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    fc44:	4620      	mov	r0, r4
#endif /*CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION */
	}

	arch_irq_unlock(key);
	k_thread_abort(thread);
}
    fc46:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    fc4a:	f7fd bc4b 	b.w	d4e4 <z_impl_k_thread_abort>

0000fc4e <z_sys_power_save_idle_exit>:
	z_clock_idle_exit();
    fc4e:	f7ff bde8 	b.w	f822 <z_clock_idle_exit>

0000fc52 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    fc52:	4603      	mov	r3, r0
    fc54:	b920      	cbnz	r0, fc60 <z_reschedule_irqlock+0xe>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    fc56:	f3ef 8205 	mrs	r2, IPSR
    fc5a:	b90a      	cbnz	r2, fc60 <z_reschedule_irqlock+0xe>
    fc5c:	f7fd b9fa 	b.w	d054 <arch_swap>
    fc60:	f383 8811 	msr	BASEPRI, r3
    fc64:	f3bf 8f6f 	isb	sy
}
    fc68:	4770      	bx	lr

0000fc6a <z_reschedule_unlocked>:
	__asm__ volatile(
    fc6a:	f04f 0320 	mov.w	r3, #32
    fc6e:	f3ef 8011 	mrs	r0, BASEPRI
    fc72:	f383 8811 	msr	BASEPRI, r3
    fc76:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    fc7a:	f7ff bfea 	b.w	fc52 <z_reschedule_irqlock>

0000fc7e <unpend_thread_no_timeout>:
{
    fc7e:	4601      	mov	r1, r0
    fc80:	b508      	push	{r3, lr}
	_priq_wait_remove(&pended_on(thread)->waitq, thread);
    fc82:	6880      	ldr	r0, [r0, #8]
    fc84:	f7fe fe7c 	bl	e980 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    fc88:	7b4b      	ldrb	r3, [r1, #13]
    fc8a:	f023 0302 	bic.w	r3, r3, #2
    fc8e:	734b      	strb	r3, [r1, #13]
	thread->base.pended_on = NULL;
    fc90:	2300      	movs	r3, #0
    fc92:	608b      	str	r3, [r1, #8]
}
    fc94:	bd08      	pop	{r3, pc}

0000fc96 <z_priq_dumb_best>:
{
    fc96:	4603      	mov	r3, r0
	return list->head == list;
    fc98:	6800      	ldr	r0, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    fc9a:	4283      	cmp	r3, r0
    fc9c:	d003      	beq.n	fca6 <z_priq_dumb_best+0x10>
	if (n != NULL) {
    fc9e:	2800      	cmp	r0, #0
    fca0:	bf38      	it	cc
    fca2:	2000      	movcc	r0, #0
    fca4:	4770      	bx	lr
	struct k_thread *thread = NULL;
    fca6:	2000      	movs	r0, #0
}
    fca8:	4770      	bx	lr

0000fcaa <z_ready_thread>:
{
    fcaa:	b510      	push	{r4, lr}
    fcac:	f04f 0320 	mov.w	r3, #32
    fcb0:	f3ef 8411 	mrs	r4, BASEPRI
    fcb4:	f383 8811 	msr	BASEPRI, r3
    fcb8:	f3bf 8f6f 	isb	sy
		ready_thread(thread);
    fcbc:	f7fe feb6 	bl	ea2c <ready_thread>
	__asm__ volatile(
    fcc0:	f384 8811 	msr	BASEPRI, r4
    fcc4:	f3bf 8f6f 	isb	sy
}
    fcc8:	bd10      	pop	{r4, pc}

0000fcca <z_thread_timeout>:
{
    fcca:	b570      	push	{r4, r5, r6, lr}
    fccc:	4604      	mov	r4, r0
	__asm__ volatile(
    fcce:	f04f 0320 	mov.w	r3, #32
    fcd2:	f3ef 8611 	mrs	r6, BASEPRI
    fcd6:	f383 8811 	msr	BASEPRI, r3
    fcda:	f3bf 8f6f 	isb	sy
		if (thread->base.pended_on != NULL) {
    fcde:	f850 3c10 	ldr.w	r3, [r0, #-16]
		struct k_thread *thread = CONTAINER_OF(timeout,
    fce2:	f1a0 0518 	sub.w	r5, r0, #24
		if (thread->base.pended_on != NULL) {
    fce6:	b113      	cbz	r3, fcee <z_thread_timeout+0x24>
			unpend_thread_no_timeout(thread);
    fce8:	4628      	mov	r0, r5
    fcea:	f7ff ffc8 	bl	fc7e <unpend_thread_no_timeout>
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    fcee:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
		ready_thread(thread);
    fcf2:	4628      	mov	r0, r5
    fcf4:	f023 0314 	bic.w	r3, r3, #20
    fcf8:	f804 3c0b 	strb.w	r3, [r4, #-11]
    fcfc:	f7fe fe96 	bl	ea2c <ready_thread>
	__asm__ volatile(
    fd00:	f386 8811 	msr	BASEPRI, r6
    fd04:	f3bf 8f6f 	isb	sy
}
    fd08:	bd70      	pop	{r4, r5, r6, pc}

0000fd0a <add_to_waitq_locked>:
{
    fd0a:	b538      	push	{r3, r4, r5, lr}
    fd0c:	4604      	mov	r4, r0
    fd0e:	460d      	mov	r5, r1
	unready_thread(thread);
    fd10:	f7fe ffea 	bl	ece8 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    fd14:	7b63      	ldrb	r3, [r4, #13]
    fd16:	f043 0302 	orr.w	r3, r3, #2
    fd1a:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    fd1c:	b1c5      	cbz	r5, fd50 <add_to_waitq_locked+0x46>
	return list->head == list;
    fd1e:	682b      	ldr	r3, [r5, #0]
		thread->base.pended_on = wait_q;
    fd20:	60a5      	str	r5, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    fd22:	429d      	cmp	r5, r3
    fd24:	bf08      	it	eq
    fd26:	2300      	moveq	r3, #0
    fd28:	2b00      	cmp	r3, #0
    fd2a:	bf38      	it	cc
    fd2c:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    fd2e:	b183      	cbz	r3, fd52 <add_to_waitq_locked+0x48>
	if (thread_1->base.prio < thread_2->base.prio) {
    fd30:	f994 100e 	ldrsb.w	r1, [r4, #14]
    fd34:	f993 200e 	ldrsb.w	r2, [r3, #14]
    fd38:	4291      	cmp	r1, r2
    fd3a:	db04      	blt.n	fd46 <add_to_waitq_locked+0x3c>
	return (node == list->tail) ? NULL : node->next;
    fd3c:	686a      	ldr	r2, [r5, #4]
    fd3e:	429a      	cmp	r2, r3
    fd40:	d007      	beq.n	fd52 <add_to_waitq_locked+0x48>
    fd42:	681b      	ldr	r3, [r3, #0]
    fd44:	e7f3      	b.n	fd2e <add_to_waitq_locked+0x24>
	node->prev = successor->prev;
    fd46:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    fd48:	e9c4 3200 	strd	r3, r2, [r4]
	successor->prev->next = node;
    fd4c:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    fd4e:	605c      	str	r4, [r3, #4]
}
    fd50:	bd38      	pop	{r3, r4, r5, pc}
	node->prev = list->tail;
    fd52:	686b      	ldr	r3, [r5, #4]
	node->next = list;
    fd54:	6025      	str	r5, [r4, #0]
	node->prev = list->tail;
    fd56:	6063      	str	r3, [r4, #4]
	list->tail->next = node;
    fd58:	686b      	ldr	r3, [r5, #4]
    fd5a:	601c      	str	r4, [r3, #0]
	list->tail = node;
    fd5c:	606c      	str	r4, [r5, #4]
    fd5e:	e7f7      	b.n	fd50 <add_to_waitq_locked+0x46>

0000fd60 <z_unpend_first_thread>:
{
    fd60:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    fd62:	f04f 0320 	mov.w	r3, #32
    fd66:	f3ef 8211 	mrs	r2, BASEPRI
    fd6a:	f383 8811 	msr	BASEPRI, r3
    fd6e:	f3bf 8f6f 	isb	sy
		ret = _priq_wait_best(&wait_q->waitq);
    fd72:	f7ff ff90 	bl	fc96 <z_priq_dumb_best>
    fd76:	4604      	mov	r4, r0
	__asm__ volatile(
    fd78:	f382 8811 	msr	BASEPRI, r2
    fd7c:	f3bf 8f6f 	isb	sy

static inline struct k_thread *z_unpend1_no_timeout(_wait_q_t *wait_q)
{
	struct k_thread *thread = z_find_first_thread_to_unpend(wait_q, NULL);

	if (thread != NULL) {
    fd80:	b188      	cbz	r0, fda6 <z_unpend_first_thread+0x46>
	__asm__ volatile(
    fd82:	f04f 0320 	mov.w	r3, #32
    fd86:	f3ef 8511 	mrs	r5, BASEPRI
    fd8a:	f383 8811 	msr	BASEPRI, r3
    fd8e:	f3bf 8f6f 	isb	sy
		unpend_thread_no_timeout(thread);
    fd92:	f7ff ff74 	bl	fc7e <unpend_thread_no_timeout>
	__asm__ volatile(
    fd96:	f385 8811 	msr	BASEPRI, r5
    fd9a:	f3bf 8f6f 	isb	sy
	return z_abort_timeout(&thread->base.timeout);
    fd9e:	f104 0018 	add.w	r0, r4, #24
    fda2:	f000 f80a 	bl	fdba <z_abort_timeout>
}
    fda6:	4620      	mov	r0, r4
    fda8:	bd38      	pop	{r3, r4, r5, pc}

0000fdaa <k_is_in_isr>:
    fdaa:	f3ef 8005 	mrs	r0, IPSR
}
    fdae:	3800      	subs	r0, #0
    fdb0:	bf18      	it	ne
    fdb2:	2001      	movne	r0, #1
    fdb4:	4770      	bx	lr

0000fdb6 <z_impl_k_busy_wait>:
	arch_busy_wait(usec_to_wait);
    fdb6:	f7fc bebb 	b.w	cb30 <arch_busy_wait>

0000fdba <z_abort_timeout>:
{
    fdba:	b510      	push	{r4, lr}
	__asm__ volatile(
    fdbc:	f04f 0220 	mov.w	r2, #32
    fdc0:	f3ef 8411 	mrs	r4, BASEPRI
    fdc4:	f382 8811 	msr	BASEPRI, r2
    fdc8:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
    fdcc:	6803      	ldr	r3, [r0, #0]
    fdce:	b13b      	cbz	r3, fde0 <z_abort_timeout+0x26>
			remove_timeout(to);
    fdd0:	f7ff f96e 	bl	f0b0 <remove_timeout>
			ret = 0;
    fdd4:	2000      	movs	r0, #0
	__asm__ volatile(
    fdd6:	f384 8811 	msr	BASEPRI, r4
    fdda:	f3bf 8f6f 	isb	sy
}
    fdde:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
    fde0:	f06f 0015 	mvn.w	r0, #21
    fde4:	e7f7      	b.n	fdd6 <z_abort_timeout+0x1c>

0000fde6 <z_get_next_timeout_expiry>:
{
    fde6:	b510      	push	{r4, lr}
	__asm__ volatile(
    fde8:	f04f 0320 	mov.w	r3, #32
    fdec:	f3ef 8411 	mrs	r4, BASEPRI
    fdf0:	f383 8811 	msr	BASEPRI, r3
    fdf4:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
    fdf8:	f7ff f974 	bl	f0e4 <next_timeout>
	__asm__ volatile(
    fdfc:	f384 8811 	msr	BASEPRI, r4
    fe00:	f3bf 8f6f 	isb	sy
}
    fe04:	bd10      	pop	{r4, pc}

0000fe06 <z_set_timeout_expiry>:
{
    fe06:	b570      	push	{r4, r5, r6, lr}
    fe08:	4604      	mov	r4, r0
    fe0a:	460d      	mov	r5, r1
	__asm__ volatile(
    fe0c:	f04f 0320 	mov.w	r3, #32
    fe10:	f3ef 8611 	mrs	r6, BASEPRI
    fe14:	f383 8811 	msr	BASEPRI, r3
    fe18:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
    fe1c:	f7ff f962 	bl	f0e4 <next_timeout>
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
    fe20:	2801      	cmp	r0, #1
    fe22:	dd05      	ble.n	fe30 <z_set_timeout_expiry+0x2a>
    fe24:	42a0      	cmp	r0, r4
    fe26:	dd03      	ble.n	fe30 <z_set_timeout_expiry+0x2a>
			z_clock_set_timeout(ticks, is_idle);
    fe28:	4629      	mov	r1, r5
    fe2a:	4620      	mov	r0, r4
    fe2c:	f7fd f892 	bl	cf54 <z_clock_set_timeout>
	__asm__ volatile(
    fe30:	f386 8811 	msr	BASEPRI, r6
    fe34:	f3bf 8f6f 	isb	sy
}
    fe38:	bd70      	pop	{r4, r5, r6, pc}

0000fe3a <z_tick_get_32>:

uint32_t z_tick_get_32(void)
{
    fe3a:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)z_tick_get();
    fe3c:	f7ff fa6c 	bl	f318 <z_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    fe40:	bd08      	pop	{r3, pc}

0000fe42 <k_heap_init>:
{
    fe42:	b410      	push	{r4}
    fe44:	f100 040c 	add.w	r4, r0, #12
	list->tail = (sys_dnode_t *)list;
    fe48:	e9c0 4403 	strd	r4, r4, [r0, #12]
}
    fe4c:	bc10      	pop	{r4}
	sys_heap_init(&h->heap, mem, bytes);
    fe4e:	f7ff bbfb 	b.w	f648 <sys_heap_init>

0000fe52 <_OffsetAbsSyms>:
#include "offsets_aarch64.c"
#else
#include "offsets_aarch32.c"
#endif

GEN_ABS_SYM_END
    fe52:	4770      	bx	lr
