
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_start>:
#include <syscalls/z_errno_mrsh.c>

#else
int *z_impl_z_errno(void)
{
	return &_current->errno_var;
   0:	20000c70 	.word	0x20000c70
}
   4:	00001855 	.word	0x00001855
   8:	0000499b 	.word	0x0000499b
   c:	00001885 	.word	0x00001885
  10:	00001885 	.word	0x00001885
  14:	00001885 	.word	0x00001885
  18:	00001885 	.word	0x00001885
  1c:	00001885 	.word	0x00001885
	...
  2c:	00001669 	.word	0x00001669
  30:	00001885 	.word	0x00001885
  34:	00000000 	.word	0x00000000
  38:	00001611 	.word	0x00001611
  3c:	00004881 	.word	0x00004881

00000040 <_irq_vector_table>:
  40:	00001815 00001815 00001815 00001815     ................
  50:	00001815 00001815 00001815 00001815     ................
  60:	00001815 00001815 00001815 00001815     ................
  70:	00001815 00001815 00001815 00001815     ................
  80:	00001815 00001815 00001815 00001815     ................
  90:	00001815 00001815 00001815 00001815     ................
  a0:	00001815 00001815 00001815 00001815     ................
  b0:	00001815 00001815 00001815 00001815     ................
  c0:	00001815 00001815 00001815 00001815     ................
  d0:	00001815 00001815 00001815 00001815     ................
  e0:	00001815 00001815 00001815 00001815     ................
  f0:	00001815 00001815 00001815 00001815     ................
 100:	00001815 00001815 00001815 00001815     ................
 110:	00001815 00001815 00001815 00001815     ................
 120:	00001815 00001815 00001815 00001815     ................
 130:	00001815 00001815 00001815 00001815     ................
 140:	00001815                                ....

00000144 <_vector_end>:
	...

00000200 <m_firmware_info>:
 200:	281ee6de 8fcebb4c 00005b02 0000003c     ...(L....[..<...
 210:	00008000 00000001 00000000 00000000     ................
 220:	9102ffff 00000000 00000000 00000000     ................
	...

Disassembly of section text:

0000023c <__aeabi_uldivmod>:
     23c:	b953      	cbnz	r3, 254 <__aeabi_uldivmod+0x18>
     23e:	b94a      	cbnz	r2, 254 <__aeabi_uldivmod+0x18>
     240:	2900      	cmp	r1, #0
     242:	bf08      	it	eq
     244:	2800      	cmpeq	r0, #0
     246:	bf1c      	itt	ne
     248:	f04f 31ff 	movne.w	r1, #4294967295
     24c:	f04f 30ff 	movne.w	r0, #4294967295
     250:	f000 b96c 	b.w	52c <__aeabi_idiv0>
     254:	f1ad 0c08 	sub.w	ip, sp, #8
     258:	e96d ce04 	strd	ip, lr, [sp, #-16]!
     25c:	f000 f806 	bl	26c <__udivmoddi4>
     260:	f8dd e004 	ldr.w	lr, [sp, #4]
     264:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     268:	b004      	add	sp, #16
     26a:	4770      	bx	lr

0000026c <__udivmoddi4>:
     26c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     270:	9d08      	ldr	r5, [sp, #32]
     272:	4604      	mov	r4, r0
     274:	4688      	mov	r8, r1
     276:	2b00      	cmp	r3, #0
     278:	d17d      	bne.n	376 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xf6>
     27a:	428a      	cmp	r2, r1
     27c:	4617      	mov	r7, r2
     27e:	d93f      	bls.n	300 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x80>
     280:	fab2 f282 	clz	r2, r2
     284:	b142      	cbz	r2, 298 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x18>
     286:	f1c2 0020 	rsb	r0, r2, #32
     28a:	4091      	lsls	r1, r2
     28c:	4097      	lsls	r7, r2
     28e:	fa24 f000 	lsr.w	r0, r4, r0
     292:	4094      	lsls	r4, r2
     294:	ea40 0801 	orr.w	r8, r0, r1
     298:	ea4f 4c17 	mov.w	ip, r7, lsr #16
     29c:	0c23      	lsrs	r3, r4, #16
     29e:	fa1f fe87 	uxth.w	lr, r7
     2a2:	fbb8 f6fc 	udiv	r6, r8, ip
     2a6:	fb0c 8116 	mls	r1, ip, r6, r8
     2aa:	fb06 f00e 	mul.w	r0, r6, lr
     2ae:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
     2b2:	4298      	cmp	r0, r3
     2b4:	d905      	bls.n	2c2 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x42>
     2b6:	18fb      	adds	r3, r7, r3
     2b8:	d202      	bcs.n	2c0 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x40>
     2ba:	4298      	cmp	r0, r3
     2bc:	f200 8124 	bhi.w	508 <CONFIG_FLASH_SIZE+0x108>
     2c0:	3e01      	subs	r6, #1
     2c2:	1a19      	subs	r1, r3, r0
     2c4:	b2a3      	uxth	r3, r4
     2c6:	fbb1 f0fc 	udiv	r0, r1, ip
     2ca:	fb0c 1110 	mls	r1, ip, r0, r1
     2ce:	fb00 fe0e 	mul.w	lr, r0, lr
     2d2:	ea43 4401 	orr.w	r4, r3, r1, lsl #16
     2d6:	45a6      	cmp	lr, r4
     2d8:	d905      	bls.n	2e6 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x66>
     2da:	193c      	adds	r4, r7, r4
     2dc:	d202      	bcs.n	2e4 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x64>
     2de:	45a6      	cmp	lr, r4
     2e0:	f200 810f 	bhi.w	502 <CONFIG_FLASH_SIZE+0x102>
     2e4:	3801      	subs	r0, #1
     2e6:	ea40 4006 	orr.w	r0, r0, r6, lsl #16
     2ea:	eba4 040e 	sub.w	r4, r4, lr
     2ee:	2600      	movs	r6, #0
     2f0:	b11d      	cbz	r5, 2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     2f2:	40d4      	lsrs	r4, r2
     2f4:	2300      	movs	r3, #0
     2f6:	e9c5 4300 	strd	r4, r3, [r5]
     2fa:	4631      	mov	r1, r6
     2fc:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     300:	b902      	cbnz	r2, 304 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x84>
     302:	deff      	udf	#255	; 0xff
     304:	fab2 f282 	clz	r2, r2
     308:	2a00      	cmp	r2, #0
     30a:	d150      	bne.n	3ae <CONFIG_PM_PARTITION_SIZE_PROVISION+0x12e>
     30c:	1bcb      	subs	r3, r1, r7
     30e:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     312:	fa1f f887 	uxth.w	r8, r7
     316:	2601      	movs	r6, #1
     318:	0c21      	lsrs	r1, r4, #16
     31a:	fbb3 fcfe 	udiv	ip, r3, lr
     31e:	fb0e 301c 	mls	r0, lr, ip, r3
     322:	460b      	mov	r3, r1
     324:	fb08 f90c 	mul.w	r9, r8, ip
     328:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
     32c:	4589      	cmp	r9, r1
     32e:	d90a      	bls.n	346 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xc6>
     330:	1879      	adds	r1, r7, r1
     332:	bf2c      	ite	cs
     334:	2301      	movcs	r3, #1
     336:	2300      	movcc	r3, #0
     338:	4589      	cmp	r9, r1
     33a:	d902      	bls.n	342 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xc2>
     33c:	2b00      	cmp	r3, #0
     33e:	f000 80d9 	beq.w	4f4 <CONFIG_FLASH_SIZE+0xf4>
     342:	f10c 3cff 	add.w	ip, ip, #4294967295
     346:	eba1 0109 	sub.w	r1, r1, r9
     34a:	b2a3      	uxth	r3, r4
     34c:	fbb1 f0fe 	udiv	r0, r1, lr
     350:	fb0e 1110 	mls	r1, lr, r0, r1
     354:	fb08 f800 	mul.w	r8, r8, r0
     358:	ea43 4401 	orr.w	r4, r3, r1, lsl #16
     35c:	45a0      	cmp	r8, r4
     35e:	d905      	bls.n	36c <CONFIG_PM_PARTITION_SIZE_PROVISION+0xec>
     360:	193c      	adds	r4, r7, r4
     362:	d202      	bcs.n	36a <CONFIG_PM_PARTITION_SIZE_PROVISION+0xea>
     364:	45a0      	cmp	r8, r4
     366:	f200 80c9 	bhi.w	4fc <CONFIG_FLASH_SIZE+0xfc>
     36a:	3801      	subs	r0, #1
     36c:	eba4 0408 	sub.w	r4, r4, r8
     370:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     374:	e7bc      	b.n	2f0 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x70>
     376:	428b      	cmp	r3, r1
     378:	d909      	bls.n	38e <CONFIG_PM_PARTITION_SIZE_PROVISION+0x10e>
     37a:	2d00      	cmp	r5, #0
     37c:	f000 80b1 	beq.w	4e2 <CONFIG_FLASH_SIZE+0xe2>
     380:	2600      	movs	r6, #0
     382:	e9c5 0100 	strd	r0, r1, [r5]
     386:	4630      	mov	r0, r6
     388:	4631      	mov	r1, r6
     38a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     38e:	fab3 f683 	clz	r6, r3
     392:	2e00      	cmp	r6, #0
     394:	d146      	bne.n	424 <CONFIG_FLASH_SIZE+0x24>
     396:	428b      	cmp	r3, r1
     398:	f0c0 80a6 	bcc.w	4e8 <CONFIG_FLASH_SIZE+0xe8>
     39c:	4282      	cmp	r2, r0
     39e:	f240 80a3 	bls.w	4e8 <CONFIG_FLASH_SIZE+0xe8>
     3a2:	4630      	mov	r0, r6
     3a4:	2d00      	cmp	r5, #0
     3a6:	d0a8      	beq.n	2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     3a8:	e9c5 4800 	strd	r4, r8, [r5]
     3ac:	e7a5      	b.n	2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     3ae:	4097      	lsls	r7, r2
     3b0:	f1c2 0320 	rsb	r3, r2, #32
     3b4:	fa01 f002 	lsl.w	r0, r1, r2
     3b8:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     3bc:	40d9      	lsrs	r1, r3
     3be:	fa24 f303 	lsr.w	r3, r4, r3
     3c2:	fa1f f887 	uxth.w	r8, r7
     3c6:	4094      	lsls	r4, r2
     3c8:	4303      	orrs	r3, r0
     3ca:	fbb1 f0fe 	udiv	r0, r1, lr
     3ce:	0c1e      	lsrs	r6, r3, #16
     3d0:	fb0e 1110 	mls	r1, lr, r0, r1
     3d4:	fb00 fc08 	mul.w	ip, r0, r8
     3d8:	ea46 4101 	orr.w	r1, r6, r1, lsl #16
     3dc:	458c      	cmp	ip, r1
     3de:	d909      	bls.n	3f4 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x174>
     3e0:	1879      	adds	r1, r7, r1
     3e2:	bf2c      	ite	cs
     3e4:	2601      	movcs	r6, #1
     3e6:	2600      	movcc	r6, #0
     3e8:	458c      	cmp	ip, r1
     3ea:	d902      	bls.n	3f2 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x172>
     3ec:	2e00      	cmp	r6, #0
     3ee:	f000 8093 	beq.w	518 <CONFIG_FLASH_SIZE+0x118>
     3f2:	3801      	subs	r0, #1
     3f4:	eba1 010c 	sub.w	r1, r1, ip
     3f8:	b29b      	uxth	r3, r3
     3fa:	fbb1 f6fe 	udiv	r6, r1, lr
     3fe:	fb0e 1116 	mls	r1, lr, r6, r1
     402:	fb06 fc08 	mul.w	ip, r6, r8
     406:	ea43 4101 	orr.w	r1, r3, r1, lsl #16
     40a:	458c      	cmp	ip, r1
     40c:	d905      	bls.n	41a <CONFIG_FLASH_SIZE+0x1a>
     40e:	1879      	adds	r1, r7, r1
     410:	d202      	bcs.n	418 <CONFIG_FLASH_SIZE+0x18>
     412:	458c      	cmp	ip, r1
     414:	f200 8087 	bhi.w	526 <CONFIG_FLASH_SIZE+0x126>
     418:	3e01      	subs	r6, #1
     41a:	eba1 030c 	sub.w	r3, r1, ip
     41e:	ea46 4600 	orr.w	r6, r6, r0, lsl #16
     422:	e779      	b.n	318 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x98>
     424:	f1c6 0720 	rsb	r7, r6, #32
     428:	fa03 f406 	lsl.w	r4, r3, r6
     42c:	fa02 fc06 	lsl.w	ip, r2, r6
     430:	fa01 fe06 	lsl.w	lr, r1, r6
     434:	40fa      	lsrs	r2, r7
     436:	fa20 f807 	lsr.w	r8, r0, r7
     43a:	40f9      	lsrs	r1, r7
     43c:	fa00 f306 	lsl.w	r3, r0, r6
     440:	4322      	orrs	r2, r4
     442:	ea48 040e 	orr.w	r4, r8, lr
     446:	ea4f 4812 	mov.w	r8, r2, lsr #16
     44a:	ea4f 4e14 	mov.w	lr, r4, lsr #16
     44e:	fa1f f982 	uxth.w	r9, r2
     452:	fbb1 faf8 	udiv	sl, r1, r8
     456:	fb08 111a 	mls	r1, r8, sl, r1
     45a:	fb0a f009 	mul.w	r0, sl, r9
     45e:	ea4e 4e01 	orr.w	lr, lr, r1, lsl #16
     462:	4570      	cmp	r0, lr
     464:	d90a      	bls.n	47c <CONFIG_FLASH_SIZE+0x7c>
     466:	eb12 0e0e 	adds.w	lr, r2, lr
     46a:	bf2c      	ite	cs
     46c:	2101      	movcs	r1, #1
     46e:	2100      	movcc	r1, #0
     470:	4570      	cmp	r0, lr
     472:	d901      	bls.n	478 <CONFIG_FLASH_SIZE+0x78>
     474:	2900      	cmp	r1, #0
     476:	d052      	beq.n	51e <CONFIG_FLASH_SIZE+0x11e>
     478:	f10a 3aff 	add.w	sl, sl, #4294967295
     47c:	ebae 0e00 	sub.w	lr, lr, r0
     480:	b2a4      	uxth	r4, r4
     482:	fbbe f0f8 	udiv	r0, lr, r8
     486:	fb08 ee10 	mls	lr, r8, r0, lr
     48a:	fb00 f909 	mul.w	r9, r0, r9
     48e:	ea44 4e0e 	orr.w	lr, r4, lr, lsl #16
     492:	45f1      	cmp	r9, lr
     494:	d905      	bls.n	4a2 <CONFIG_FLASH_SIZE+0xa2>
     496:	eb12 0e0e 	adds.w	lr, r2, lr
     49a:	d201      	bcs.n	4a0 <CONFIG_FLASH_SIZE+0xa0>
     49c:	45f1      	cmp	r9, lr
     49e:	d838      	bhi.n	512 <CONFIG_FLASH_SIZE+0x112>
     4a0:	3801      	subs	r0, #1
     4a2:	ea40 400a 	orr.w	r0, r0, sl, lsl #16
     4a6:	ebae 0e09 	sub.w	lr, lr, r9
     4aa:	fba0 890c 	umull	r8, r9, r0, ip
     4ae:	45ce      	cmp	lr, r9
     4b0:	4641      	mov	r1, r8
     4b2:	464c      	mov	r4, r9
     4b4:	d302      	bcc.n	4bc <CONFIG_FLASH_SIZE+0xbc>
     4b6:	d106      	bne.n	4c6 <CONFIG_FLASH_SIZE+0xc6>
     4b8:	4543      	cmp	r3, r8
     4ba:	d204      	bcs.n	4c6 <CONFIG_FLASH_SIZE+0xc6>
     4bc:	3801      	subs	r0, #1
     4be:	ebb8 010c 	subs.w	r1, r8, ip
     4c2:	eb69 0402 	sbc.w	r4, r9, r2
     4c6:	b315      	cbz	r5, 50e <CONFIG_FLASH_SIZE+0x10e>
     4c8:	1a5a      	subs	r2, r3, r1
     4ca:	eb6e 0e04 	sbc.w	lr, lr, r4
     4ce:	40f2      	lsrs	r2, r6
     4d0:	fa0e f707 	lsl.w	r7, lr, r7
     4d4:	fa2e f306 	lsr.w	r3, lr, r6
     4d8:	2600      	movs	r6, #0
     4da:	4317      	orrs	r7, r2
     4dc:	e9c5 7300 	strd	r7, r3, [r5]
     4e0:	e70b      	b.n	2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     4e2:	462e      	mov	r6, r5
     4e4:	4628      	mov	r0, r5
     4e6:	e708      	b.n	2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     4e8:	1a84      	subs	r4, r0, r2
     4ea:	eb61 0103 	sbc.w	r1, r1, r3
     4ee:	2001      	movs	r0, #1
     4f0:	4688      	mov	r8, r1
     4f2:	e757      	b.n	3a4 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x124>
     4f4:	f1ac 0c02 	sub.w	ip, ip, #2
     4f8:	4439      	add	r1, r7
     4fa:	e724      	b.n	346 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xc6>
     4fc:	3802      	subs	r0, #2
     4fe:	443c      	add	r4, r7
     500:	e734      	b.n	36c <CONFIG_PM_PARTITION_SIZE_PROVISION+0xec>
     502:	3802      	subs	r0, #2
     504:	443c      	add	r4, r7
     506:	e6ee      	b.n	2e6 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x66>
     508:	3e02      	subs	r6, #2
     50a:	443b      	add	r3, r7
     50c:	e6d9      	b.n	2c2 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x42>
     50e:	462e      	mov	r6, r5
     510:	e6f3      	b.n	2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     512:	3802      	subs	r0, #2
     514:	4496      	add	lr, r2
     516:	e7c4      	b.n	4a2 <CONFIG_FLASH_SIZE+0xa2>
     518:	3802      	subs	r0, #2
     51a:	4439      	add	r1, r7
     51c:	e76a      	b.n	3f4 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x174>
     51e:	f1aa 0a02 	sub.w	sl, sl, #2
     522:	4496      	add	lr, r2
     524:	e7aa      	b.n	47c <CONFIG_FLASH_SIZE+0x7c>
     526:	3e02      	subs	r6, #2
     528:	4439      	add	r1, r7
     52a:	e776      	b.n	41a <CONFIG_FLASH_SIZE+0x1a>

0000052c <__aeabi_idiv0>:
     52c:	4770      	bx	lr
     52e:	bf00      	nop

00000530 <__gnu_cmse_nonsecure_call>:
     530:	e92d 4fe0 	stmdb	sp!, {r5, r6, r7, r8, r9, sl, fp, lr}
     534:	4627      	mov	r7, r4
     536:	46a0      	mov	r8, r4
     538:	46a1      	mov	r9, r4
     53a:	46a2      	mov	sl, r4
     53c:	46a3      	mov	fp, r4
     53e:	46a4      	mov	ip, r4
     540:	ed2d 8b10 	vpush	{d8-d15}
     544:	f04f 0500 	mov.w	r5, #0
     548:	ec45 5b18 	vmov	d8, r5, r5
     54c:	ec45 5a19 	vmov	s18, s19, r5, r5
     550:	ec45 5a1a 	vmov	s20, s21, r5, r5
     554:	ec45 5a1b 	vmov	s22, s23, r5, r5
     558:	ec45 5a1c 	vmov	s24, s25, r5, r5
     55c:	ec45 5a1d 	vmov	s26, s27, r5, r5
     560:	ec45 5a1e 	vmov	s28, s29, r5, r5
     564:	ec45 5a1f 	vmov	s30, s31, r5, r5
     568:	eef1 5a10 	vmrs	r5, fpscr
     56c:	f64f 7660 	movw	r6, #65376	; 0xff60
     570:	f6c0 76ff 	movt	r6, #4095	; 0xfff
     574:	4035      	ands	r5, r6
     576:	eee1 5a10 	vmsr	fpscr, r5
     57a:	f384 8800 	msr	CPSR_f, r4
     57e:	4625      	mov	r5, r4
     580:	4626      	mov	r6, r4
     582:	47a4      	blxns	r4
     584:	ecbd 8b10 	vpop	{d8-d15}
     588:	e8bd 8fe0 	ldmia.w	sp!, {r5, r6, r7, r8, r9, sl, fp, pc}

0000058c <print_digits>:
}
#endif /* CONFIG_PRINTK */

static void print_digits(out_func_t out, void *ctx, printk_val_t num, int base,
			 bool pad_before, char pad_char, int min_width)
{
     58c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     590:	b087      	sub	sp, #28
     592:	460f      	mov	r7, r1
     594:	4619      	mov	r1, r3
	char buf[DIGITS_BUFLEN];
	int i;

	/* Print it backwards into the end of the buffer, low digits first */
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
		buf[i] = "0123456789abcdef"[num % base];
     596:	9b10      	ldr	r3, [sp, #64]	; 0x40
{
     598:	4606      	mov	r6, r0
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
     59a:	2514      	movs	r5, #20
{
     59c:	4610      	mov	r0, r2
		buf[i] = "0123456789abcdef"[num % base];
     59e:	4698      	mov	r8, r3
{
     5a0:	f89d b044 	ldrb.w	fp, [sp, #68]	; 0x44
     5a4:	f89d a048 	ldrb.w	sl, [sp, #72]	; 0x48
		buf[i] = "0123456789abcdef"[num % base];
     5a8:	4c1e      	ldr	r4, [pc, #120]	; (624 <print_digits+0x98>)
     5aa:	ea4f 79e3 	mov.w	r9, r3, asr #31
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
     5ae:	ea50 0301 	orrs.w	r3, r0, r1
     5b2:	d11a      	bne.n	5ea <print_digits+0x5e>
		num /= base;
	}

	if (i == DIGITS_BUFLEN - 1) {
     5b4:	2d14      	cmp	r5, #20
		buf[i] = '0';
     5b6:	bf08      	it	eq
     5b8:	2330      	moveq	r3, #48	; 0x30
	} else {
		i++;
	}

	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
     5ba:	9c13      	ldr	r4, [sp, #76]	; 0x4c
		i++;
     5bc:	bf18      	it	ne
     5be:	3501      	addne	r5, #1
	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
     5c0:	442c      	add	r4, r5
		buf[i] = '0';
     5c2:	bf08      	it	eq
     5c4:	f88d 3014 	strbeq.w	r3, [sp, #20]
	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
     5c8:	2c15      	cmp	r4, #21
     5ca:	d01b      	beq.n	604 <print_digits+0x78>
     5cc:	3c15      	subs	r4, #21

	for (/**/; pad > 0 && pad_before; pad--) {
     5ce:	2c00      	cmp	r4, #0
     5d0:	dc1a      	bgt.n	608 <print_digits+0x7c>
		out(pad_char, ctx);
	}
	for (/**/; i < DIGITS_BUFLEN; i++) {
		out(buf[i], ctx);
     5d2:	f81d 0005 	ldrb.w	r0, [sp, r5]
     5d6:	4639      	mov	r1, r7
	for (/**/; i < DIGITS_BUFLEN; i++) {
     5d8:	3501      	adds	r5, #1
		out(buf[i], ctx);
     5da:	47b0      	blx	r6
	for (/**/; i < DIGITS_BUFLEN; i++) {
     5dc:	2d15      	cmp	r5, #21
     5de:	d1f8      	bne.n	5d2 <print_digits+0x46>
	}
	for (/**/; pad > 0; pad--) {
     5e0:	2c00      	cmp	r4, #0
     5e2:	dc19      	bgt.n	618 <print_digits+0x8c>
		out(pad_char, ctx);
	}
}
     5e4:	b007      	add	sp, #28
     5e6:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		buf[i] = "0123456789abcdef"[num % base];
     5ea:	4642      	mov	r2, r8
     5ec:	464b      	mov	r3, r9
     5ee:	f7ff fe25 	bl	23c <__aeabi_uldivmod>
     5f2:	4684      	mov	ip, r0
     5f4:	460b      	mov	r3, r1
     5f6:	5ca2      	ldrb	r2, [r4, r2]
		num /= base;
     5f8:	4660      	mov	r0, ip
		buf[i] = "0123456789abcdef"[num % base];
     5fa:	f80d 2005 	strb.w	r2, [sp, r5]
		num /= base;
     5fe:	4619      	mov	r1, r3
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
     600:	3d01      	subs	r5, #1
     602:	e7d4      	b.n	5ae <print_digits+0x22>
	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
     604:	2400      	movs	r4, #0
	for (/**/; i < DIGITS_BUFLEN; i++) {
     606:	e7e4      	b.n	5d2 <print_digits+0x46>
	for (/**/; pad > 0 && pad_before; pad--) {
     608:	f1bb 0f00 	cmp.w	fp, #0
     60c:	d0e1      	beq.n	5d2 <print_digits+0x46>
		out(pad_char, ctx);
     60e:	4639      	mov	r1, r7
     610:	4650      	mov	r0, sl
     612:	47b0      	blx	r6
	for (/**/; pad > 0 && pad_before; pad--) {
     614:	3c01      	subs	r4, #1
     616:	e7da      	b.n	5ce <print_digits+0x42>
		out(pad_char, ctx);
     618:	4639      	mov	r1, r7
     61a:	4650      	mov	r0, sl
     61c:	47b0      	blx	r6
	for (/**/; pad > 0; pad--) {
     61e:	3c01      	subs	r4, #1
     620:	e7de      	b.n	5e0 <print_digits+0x54>
     622:	bf00      	nop
     624:	000053e1 	.word	0x000053e1

00000628 <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
     628:	680b      	ldr	r3, [r1, #0]
     62a:	3301      	adds	r3, #1
     62c:	600b      	str	r3, [r1, #0]
	return _char_out(c);
     62e:	4b01      	ldr	r3, [pc, #4]	; (634 <char_out+0xc>)
     630:	681b      	ldr	r3, [r3, #0]
     632:	4718      	bx	r3
     634:	20000000 	.word	0x20000000

00000638 <__printk_hook_install>:
	_char_out = fn;
     638:	4b01      	ldr	r3, [pc, #4]	; (640 <__printk_hook_install+0x8>)
     63a:	6018      	str	r0, [r3, #0]
}
     63c:	4770      	bx	lr
     63e:	bf00      	nop
     640:	20000000 	.word	0x20000000

00000644 <z_vprintk>:
{
     644:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
	char length_mod = 0;
     648:	2600      	movs	r6, #0
{
     64a:	4605      	mov	r5, r0
     64c:	468b      	mov	fp, r1
     64e:	461c      	mov	r4, r3
	int min_width = -1;
     650:	f04f 38ff 	mov.w	r8, #4294967295
	enum pad_type padding = PAD_NONE;
     654:	4637      	mov	r7, r6
{
     656:	b087      	sub	sp, #28
     658:	f102 3aff 	add.w	sl, r2, #4294967295
			might_format = 0;
     65c:	f04f 0900 	mov.w	r9, #0
					break;
     660:	e007      	b.n	672 <z_vprintk+0x2e>
		if (!might_format) {
     662:	f1b9 0f00 	cmp.w	r9, #0
     666:	d10b      	bne.n	680 <z_vprintk+0x3c>
			if (*fmt != '%') {
     668:	2825      	cmp	r0, #37	; 0x25
     66a:	f000 810a 	beq.w	882 <CONFIG_ISR_STACK_SIZE+0x82>
				out((int)*fmt, ctx);
     66e:	4659      	mov	r1, fp
     670:	47a8      	blx	r5
	while (*fmt) {
     672:	f81a 0f01 	ldrb.w	r0, [sl, #1]!
     676:	2800      	cmp	r0, #0
     678:	d1f3      	bne.n	662 <z_vprintk+0x1e>
}
     67a:	b007      	add	sp, #28
     67c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			switch (*fmt) {
     680:	287a      	cmp	r0, #122	; 0x7a
     682:	d80a      	bhi.n	69a <z_vprintk+0x56>
     684:	2862      	cmp	r0, #98	; 0x62
     686:	d810      	bhi.n	6aa <z_vprintk+0x66>
     688:	2830      	cmp	r0, #48	; 0x30
     68a:	d051      	beq.n	730 <z_vprintk+0xec>
     68c:	d844      	bhi.n	718 <z_vprintk+0xd4>
     68e:	2825      	cmp	r0, #37	; 0x25
     690:	f000 80f5 	beq.w	87e <CONFIG_ISR_STACK_SIZE+0x7e>
     694:	282d      	cmp	r0, #45	; 0x2d
     696:	f000 80fb 	beq.w	890 <CONFIG_ISR_STACK_SIZE+0x90>
					out((int)'%', ctx);
     69a:	4659      	mov	r1, fp
     69c:	2025      	movs	r0, #37	; 0x25
     69e:	47a8      	blx	r5
					out((int)*fmt, ctx);
     6a0:	4659      	mov	r1, fp
     6a2:	f89a 0000 	ldrb.w	r0, [sl]
     6a6:	47a8      	blx	r5
     6a8:	e7d8      	b.n	65c <z_vprintk+0x18>
     6aa:	f1a0 0363 	sub.w	r3, r0, #99	; 0x63
     6ae:	2b17      	cmp	r3, #23
     6b0:	d8f3      	bhi.n	69a <z_vprintk+0x56>
     6b2:	a201      	add	r2, pc, #4	; (adr r2, 6b8 <z_vprintk+0x74>)
     6b4:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
     6b8:	00000877 	.word	0x00000877
     6bc:	00000779 	.word	0x00000779
     6c0:	0000069b 	.word	0x0000069b
     6c4:	0000069b 	.word	0x0000069b
     6c8:	0000069b 	.word	0x0000069b
     6cc:	0000075b 	.word	0x0000075b
     6d0:	00000779 	.word	0x00000779
     6d4:	0000069b 	.word	0x0000069b
     6d8:	0000069b 	.word	0x0000069b
     6dc:	0000075b 	.word	0x0000075b
     6e0:	0000069b 	.word	0x0000069b
     6e4:	0000069b 	.word	0x0000069b
     6e8:	0000069b 	.word	0x0000069b
     6ec:	000007f3 	.word	0x000007f3
     6f0:	0000069b 	.word	0x0000069b
     6f4:	0000069b 	.word	0x0000069b
     6f8:	0000083f 	.word	0x0000083f
     6fc:	0000069b 	.word	0x0000069b
     700:	00000779 	.word	0x00000779
     704:	0000069b 	.word	0x0000069b
     708:	0000069b 	.word	0x0000069b
     70c:	00000721 	.word	0x00000721
     710:	0000069b 	.word	0x0000069b
     714:	0000075b 	.word	0x0000075b
			switch (*fmt) {
     718:	2839      	cmp	r0, #57	; 0x39
     71a:	d915      	bls.n	748 <z_vprintk+0x104>
     71c:	2858      	cmp	r0, #88	; 0x58
     71e:	d1bc      	bne.n	69a <z_vprintk+0x56>
				if (*fmt == 'p') {
     720:	f89a 3000 	ldrb.w	r3, [sl]
     724:	2b70      	cmp	r3, #112	; 0x70
     726:	d16e      	bne.n	806 <CONFIG_ISR_STACK_SIZE+0x6>
					x = va_arg(ap, unsigned int);
     728:	2300      	movs	r3, #0
     72a:	f854 2b04 	ldr.w	r2, [r4], #4
     72e:	e075      	b.n	81c <CONFIG_ISR_STACK_SIZE+0x1c>
				if (min_width < 0 && padding == PAD_NONE) {
     730:	f1b8 0f00 	cmp.w	r8, #0
     734:	da0b      	bge.n	74e <z_vprintk+0x10a>
     736:	2f00      	cmp	r7, #0
     738:	f000 80ac 	beq.w	894 <CONFIG_ISR_STACK_SIZE+0x94>
					min_width = *fmt - '0';
     73c:	f1a0 0830 	sub.w	r8, r0, #48	; 0x30
					padding = PAD_SPACE_BEFORE;
     740:	2f00      	cmp	r7, #0
     742:	bf08      	it	eq
     744:	2702      	moveq	r7, #2
     746:	e794      	b.n	672 <z_vprintk+0x2e>
				if (min_width < 0) {
     748:	f1b8 0f00 	cmp.w	r8, #0
     74c:	dbf6      	blt.n	73c <z_vprintk+0xf8>
					min_width = 10 * min_width + *fmt - '0';
     74e:	230a      	movs	r3, #10
     750:	fb03 0808 	mla	r8, r3, r8, r0
     754:	f1a8 0830 	sub.w	r8, r8, #48	; 0x30
     758:	e7f2      	b.n	740 <z_vprintk+0xfc>
				if (*fmt == 'h' && length_mod == 'h') {
     75a:	2868      	cmp	r0, #104	; 0x68
     75c:	d103      	bne.n	766 <z_vprintk+0x122>
     75e:	2e68      	cmp	r6, #104	; 0x68
     760:	d106      	bne.n	770 <z_vprintk+0x12c>
					length_mod = 'H';
     762:	2648      	movs	r6, #72	; 0x48
     764:	e785      	b.n	672 <z_vprintk+0x2e>
				} else if (*fmt == 'l' && length_mod == 'l') {
     766:	286c      	cmp	r0, #108	; 0x6c
     768:	d102      	bne.n	770 <z_vprintk+0x12c>
     76a:	2e6c      	cmp	r6, #108	; 0x6c
     76c:	f000 8094 	beq.w	898 <CONFIG_ISR_STACK_SIZE+0x98>
				} else if (length_mod == 0) {
     770:	2e00      	cmp	r6, #0
     772:	d192      	bne.n	69a <z_vprintk+0x56>
     774:	4606      	mov	r6, r0
     776:	e77c      	b.n	672 <z_vprintk+0x2e>
				if (length_mod == 'z') {
     778:	2e7a      	cmp	r6, #122	; 0x7a
     77a:	d106      	bne.n	78a <z_vprintk+0x146>
					d = va_arg(ap, long);
     77c:	46a1      	mov	r9, r4
     77e:	f859 2b04 	ldr.w	r2, [r9], #4
     782:	17d3      	asrs	r3, r2, #31
				if (*fmt != 'u' && negative(d)) {
     784:	2875      	cmp	r0, #117	; 0x75
     786:	d123      	bne.n	7d0 <z_vprintk+0x18c>
     788:	e00f      	b.n	7aa <z_vprintk+0x166>
				} else if (length_mod == 'l') {
     78a:	2e6c      	cmp	r6, #108	; 0x6c
     78c:	d0f6      	beq.n	77c <z_vprintk+0x138>
				} else if (length_mod == 'L') {
     78e:	2e4c      	cmp	r6, #76	; 0x4c
     790:	d105      	bne.n	79e <z_vprintk+0x15a>
					long long lld = va_arg(ap, long long);
     792:	3407      	adds	r4, #7
     794:	f024 0907 	bic.w	r9, r4, #7
					d = (printk_val_t) lld;
     798:	e8f9 2302 	ldrd	r2, r3, [r9], #8
     79c:	e7f2      	b.n	784 <z_vprintk+0x140>
				} else if (*fmt == 'u') {
     79e:	2875      	cmp	r0, #117	; 0x75
					d = va_arg(ap, unsigned int);
     7a0:	6822      	ldr	r2, [r4, #0]
     7a2:	f104 0904 	add.w	r9, r4, #4
				} else if (*fmt == 'u') {
     7a6:	d112      	bne.n	7ce <z_vprintk+0x18a>
					d = va_arg(ap, unsigned int);
     7a8:	2300      	movs	r3, #0
	print_digits(out, ctx, num, 10, padding != PAD_SPACE_AFTER,
     7aa:	1ef8      	subs	r0, r7, #3
     7ac:	bf18      	it	ne
     7ae:	2001      	movne	r0, #1
     7b0:	2f01      	cmp	r7, #1
     7b2:	bf0c      	ite	eq
     7b4:	2430      	moveq	r4, #48	; 0x30
     7b6:	2420      	movne	r4, #32
     7b8:	9001      	str	r0, [sp, #4]
     7ba:	200a      	movs	r0, #10
     7bc:	e9cd 4802 	strd	r4, r8, [sp, #8]
     7c0:	9000      	str	r0, [sp, #0]
     7c2:	4659      	mov	r1, fp
     7c4:	4628      	mov	r0, r5
     7c6:	f7ff fee1 	bl	58c <print_digits>
}
     7ca:	464c      	mov	r4, r9
     7cc:	e746      	b.n	65c <z_vprintk+0x18>
					d = va_arg(ap, int);
     7ce:	17d3      	asrs	r3, r2, #31
				if (*fmt != 'u' && negative(d)) {
     7d0:	2a00      	cmp	r2, #0
     7d2:	f173 0100 	sbcs.w	r1, r3, #0
     7d6:	dae8      	bge.n	7aa <z_vprintk+0x166>
					out((int)'-', ctx);
     7d8:	4659      	mov	r1, fp
     7da:	202d      	movs	r0, #45	; 0x2d
     7dc:	e9cd 2304 	strd	r2, r3, [sp, #16]
     7e0:	47a8      	blx	r5
					d = -d;
     7e2:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
     7e6:	4252      	negs	r2, r2
     7e8:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
					min_width--;
     7ec:	f108 38ff 	add.w	r8, r8, #4294967295
     7f0:	e7db      	b.n	7aa <z_vprintk+0x166>
				out('0', ctx);
     7f2:	4659      	mov	r1, fp
     7f4:	2030      	movs	r0, #48	; 0x30
     7f6:	47a8      	blx	r5
				out('x', ctx);
     7f8:	4659      	mov	r1, fp
     7fa:	2078      	movs	r0, #120	; 0x78
     7fc:	47a8      	blx	r5
				min_width = sizeof(void *) * 2;
     7fe:	f04f 0808 	mov.w	r8, #8
				padding = PAD_ZERO_BEFORE;
     802:	2701      	movs	r7, #1
     804:	e78c      	b.n	720 <z_vprintk+0xdc>
				} else if (length_mod == 'l') {
     806:	2e6c      	cmp	r6, #108	; 0x6c
     808:	d08e      	beq.n	728 <z_vprintk+0xe4>
				} else if (length_mod == 'L') {
     80a:	2e4c      	cmp	r6, #76	; 0x4c
     80c:	d18c      	bne.n	728 <z_vprintk+0xe4>
					x = va_arg(ap, unsigned long long);
     80e:	1de3      	adds	r3, r4, #7
     810:	f023 0307 	bic.w	r3, r3, #7
     814:	461c      	mov	r4, r3
     816:	685b      	ldr	r3, [r3, #4]
     818:	f854 2b08 	ldr.w	r2, [r4], #8
	print_digits(out, ctx, num, 16, padding != PAD_SPACE_AFTER,
     81c:	1ef8      	subs	r0, r7, #3
     81e:	bf18      	it	ne
     820:	2001      	movne	r0, #1
     822:	2f01      	cmp	r7, #1
     824:	bf0c      	ite	eq
     826:	2130      	moveq	r1, #48	; 0x30
     828:	2120      	movne	r1, #32
     82a:	e9cd 1802 	strd	r1, r8, [sp, #8]
     82e:	2110      	movs	r1, #16
     830:	9001      	str	r0, [sp, #4]
     832:	9100      	str	r1, [sp, #0]
     834:	4628      	mov	r0, r5
     836:	4659      	mov	r1, fp
     838:	f7ff fea8 	bl	58c <print_digits>
     83c:	e70e      	b.n	65c <z_vprintk+0x18>
				char *s = va_arg(ap, char *);
     83e:	f854 3b04 	ldr.w	r3, [r4], #4
				while (*s) {
     842:	4699      	mov	r9, r3
     844:	464a      	mov	r2, r9
     846:	f819 0b01 	ldrb.w	r0, [r9], #1
     84a:	b978      	cbnz	r0, 86c <CONFIG_ISR_STACK_SIZE+0x6c>
				if (padding == PAD_SPACE_AFTER) {
     84c:	2f03      	cmp	r7, #3
     84e:	d125      	bne.n	89c <CONFIG_ISR_STACK_SIZE+0x9c>
					int remaining = min_width - (s - start);
     850:	eba2 0903 	sub.w	r9, r2, r3
     854:	eba8 0909 	sub.w	r9, r8, r9
					while (remaining-- > 0) {
     858:	f1b9 0f00 	cmp.w	r9, #0
     85c:	f77f aefe 	ble.w	65c <z_vprintk+0x18>
						out(' ', ctx);
     860:	4659      	mov	r1, fp
     862:	2020      	movs	r0, #32
     864:	47a8      	blx	r5
     866:	f109 39ff 	add.w	r9, r9, #4294967295
     86a:	e7f5      	b.n	858 <CONFIG_ISR_STACK_SIZE+0x58>
					out((int)(*s++), ctx);
     86c:	4659      	mov	r1, fp
     86e:	9304      	str	r3, [sp, #16]
     870:	47a8      	blx	r5
     872:	9b04      	ldr	r3, [sp, #16]
     874:	e7e6      	b.n	844 <CONFIG_ISR_STACK_SIZE+0x44>
				out(c, ctx);
     876:	4659      	mov	r1, fp
     878:	f854 0b04 	ldr.w	r0, [r4], #4
     87c:	e713      	b.n	6a6 <z_vprintk+0x62>
				out((int)'%', ctx);
     87e:	4659      	mov	r1, fp
     880:	e711      	b.n	6a6 <z_vprintk+0x62>
				length_mod = 0;
     882:	464e      	mov	r6, r9
				padding = PAD_NONE;
     884:	464f      	mov	r7, r9
				min_width = -1;
     886:	f04f 38ff 	mov.w	r8, #4294967295
				might_format = 1;
     88a:	f04f 0901 	mov.w	r9, #1
     88e:	e6f0      	b.n	672 <z_vprintk+0x2e>
			switch (*fmt) {
     890:	2703      	movs	r7, #3
     892:	e6ee      	b.n	672 <z_vprintk+0x2e>
					padding = PAD_ZERO_BEFORE;
     894:	2701      	movs	r7, #1
     896:	e6ec      	b.n	672 <z_vprintk+0x2e>
					length_mod = 'L';
     898:	264c      	movs	r6, #76	; 0x4c
     89a:	e6ea      	b.n	672 <z_vprintk+0x2e>
			might_format = 0;
     89c:	4681      	mov	r9, r0
     89e:	e6e8      	b.n	672 <z_vprintk+0x2e>

000008a0 <vprintk>:
#endif
	}
}
#else
void vprintk(const char *fmt, va_list ap)
{
     8a0:	b507      	push	{r0, r1, r2, lr}
     8a2:	460b      	mov	r3, r1
	struct out_context ctx = { 0 };
     8a4:	2100      	movs	r1, #0
{
     8a6:	4602      	mov	r2, r0
	struct out_context ctx = { 0 };
     8a8:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
	k_spinlock_key_t key = k_spin_lock(&lock);
#endif

	z_vprintk(char_out, &ctx, fmt, ap);
     8aa:	4803      	ldr	r0, [pc, #12]	; (8b8 <vprintk+0x18>)
     8ac:	a901      	add	r1, sp, #4
     8ae:	f7ff fec9 	bl	644 <z_vprintk>

#ifdef CONFIG_PRINTK_SYNC
	k_spin_unlock(&lock, key);
#endif
}
     8b2:	b003      	add	sp, #12
     8b4:	f85d fb04 	ldr.w	pc, [sp], #4
     8b8:	00000629 	.word	0x00000629

000008bc <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     8bc:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     8c0:	f8b0 9018 	ldrh.w	r9, [r0, #24]
{
     8c4:	4604      	mov	r4, r0
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     8c6:	f019 0808 	ands.w	r8, r9, #8
{
     8ca:	4693      	mov	fp, r2
	if (processing) {
     8cc:	d00e      	beq.n	8ec <process_event+0x30>
		if (evt == EVT_COMPLETE) {
     8ce:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     8d0:	bf0c      	ite	eq
     8d2:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
     8d6:	f049 0920 	orrne.w	r9, r9, #32
     8da:	f8a0 9018 	strh.w	r9, [r0, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     8de:	f38b 8811 	msr	BASEPRI, fp
     8e2:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     8e6:	b003      	add	sp, #12
     8e8:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				transit(mgr, transition_complete);
     8ec:	f8df a198 	ldr.w	sl, [pc, #408]	; a88 <process_event+0x1cc>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     8f0:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
     8f4:	2902      	cmp	r1, #2
     8f6:	d107      	bne.n	908 <process_event+0x4c>
			evt = process_recheck(mgr);
     8f8:	4620      	mov	r0, r4
     8fa:	f003 fd94 	bl	4426 <process_recheck>
		if (evt == EVT_NOP) {
     8fe:	2800      	cmp	r0, #0
     900:	d0ed      	beq.n	8de <process_event+0x22>
		if (evt == EVT_COMPLETE) {
     902:	2801      	cmp	r0, #1
     904:	8b23      	ldrh	r3, [r4, #24]
     906:	d14d      	bne.n	9a4 <process_event+0xe8>
			res = mgr->last_res;
     908:	6967      	ldr	r7, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     90a:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
     90c:	2f00      	cmp	r7, #0
     90e:	da15      	bge.n	93c <process_event+0x80>
		*clients = mgr->clients;
     910:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     912:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
     916:	e9c4 8800 	strd	r8, r8, [r4]
     91a:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
     91e:	8321      	strh	r1, [r4, #24]
		onoff_transition_fn transit = NULL;
     920:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     922:	8b21      	ldrh	r1, [r4, #24]
     924:	f001 0207 	and.w	r2, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     928:	454a      	cmp	r2, r9
     92a:	d002      	beq.n	932 <process_event+0x76>
		if (do_monitors
     92c:	68a3      	ldr	r3, [r4, #8]
     92e:	2b00      	cmp	r3, #0
     930:	d159      	bne.n	9e6 <process_event+0x12a>
		    || !sys_slist_is_empty(&clients)
     932:	b90d      	cbnz	r5, 938 <process_event+0x7c>
		    || (transit != NULL)) {
     934:	2e00      	cmp	r6, #0
     936:	d071      	beq.n	a1c <process_event+0x160>
     938:	2300      	movs	r3, #0
     93a:	e055      	b.n	9e8 <process_event+0x12c>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     93c:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
     940:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
     942:	2a01      	cmp	r2, #1
     944:	d81f      	bhi.n	986 <process_event+0xca>
		*clients = mgr->clients;
     946:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
     94a:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
     94c:	6825      	ldr	r5, [r4, #0]
	list->head = NULL;
     94e:	b289      	uxth	r1, r1
	list->tail = NULL;
     950:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
     954:	d10c      	bne.n	970 <process_event+0xb4>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     956:	2d00      	cmp	r5, #0
     958:	462b      	mov	r3, r5
     95a:	bf38      	it	cc
     95c:	2300      	movcc	r3, #0
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     95e:	b12b      	cbz	r3, 96c <process_event+0xb0>
				mgr->refs += 1U;
     960:	8b62      	ldrh	r2, [r4, #26]
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next_no_check(sys_snode_t *node);

Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     962:	681b      	ldr	r3, [r3, #0]
     964:	3201      	adds	r2, #1
     966:	8362      	strh	r2, [r4, #26]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     968:	2b00      	cmp	r3, #0
     96a:	d1f8      	bne.n	95e <process_event+0xa2>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     96c:	f041 0102 	orr.w	r1, r1, #2
		if (process_recheck(mgr) != EVT_NOP) {
     970:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     972:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     974:	f003 fd57 	bl	4426 <process_recheck>
     978:	2800      	cmp	r0, #0
     97a:	d0d1      	beq.n	920 <process_event+0x64>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     97c:	8b23      	ldrh	r3, [r4, #24]
     97e:	f043 0320 	orr.w	r3, r3, #32
     982:	8323      	strh	r3, [r4, #24]
     984:	e7cc      	b.n	920 <process_event+0x64>
	} else if (state == ONOFF_STATE_TO_OFF) {
     986:	2b04      	cmp	r3, #4
     988:	d10a      	bne.n	9a0 <process_event+0xe4>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     98a:	f021 0107 	bic.w	r1, r1, #7
     98e:	b289      	uxth	r1, r1
		if (process_recheck(mgr) != EVT_NOP) {
     990:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     992:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     994:	f003 fd47 	bl	4426 <process_recheck>
     998:	b110      	cbz	r0, 9a0 <process_event+0xe4>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     99a:	f041 0120 	orr.w	r1, r1, #32
     99e:	8321      	strh	r1, [r4, #24]
     9a0:	2500      	movs	r5, #0
     9a2:	e7bd      	b.n	920 <process_event+0x64>
		} else if (evt == EVT_START) {
     9a4:	2803      	cmp	r0, #3
     9a6:	d109      	bne.n	9bc <process_event+0x100>
			transit = mgr->transitions->start;
     9a8:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     9aa:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
     9ae:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     9b0:	f043 0306 	orr.w	r3, r3, #6
}
     9b4:	2500      	movs	r5, #0
	mgr->flags = (state & ONOFF_STATE_MASK)
     9b6:	8323      	strh	r3, [r4, #24]
		res = 0;
     9b8:	462f      	mov	r7, r5
     9ba:	e7b2      	b.n	922 <process_event+0x66>
		} else if (evt == EVT_STOP) {
     9bc:	2804      	cmp	r0, #4
     9be:	d106      	bne.n	9ce <process_event+0x112>
			transit = mgr->transitions->stop;
     9c0:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     9c2:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
     9c6:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     9c8:	f043 0304 	orr.w	r3, r3, #4
     9cc:	e7f2      	b.n	9b4 <process_event+0xf8>
		} else if (evt == EVT_RESET) {
     9ce:	2805      	cmp	r0, #5
     9d0:	d106      	bne.n	9e0 <process_event+0x124>
			transit = mgr->transitions->reset;
     9d2:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     9d4:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
     9d8:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     9da:	f043 0305 	orr.w	r3, r3, #5
     9de:	e7e9      	b.n	9b4 <process_event+0xf8>
     9e0:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
     9e2:	462e      	mov	r6, r5
     9e4:	e7e8      	b.n	9b8 <process_event+0xfc>
				   && !sys_slist_is_empty(&mgr->monitors);
     9e6:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     9e8:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     9ec:	8321      	strh	r1, [r4, #24]
     9ee:	f38b 8811 	msr	BASEPRI, fp
     9f2:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
     9f6:	bb03      	cbnz	r3, a3a <process_event+0x17e>
	while (!sys_slist_is_empty(list)) {
     9f8:	2d00      	cmp	r5, #0
     9fa:	d134      	bne.n	a66 <process_event+0x1aa>
			if (transit != NULL) {
     9fc:	b116      	cbz	r6, a04 <process_event+0x148>
				transit(mgr, transition_complete);
     9fe:	4651      	mov	r1, sl
     a00:	4620      	mov	r0, r4
     a02:	47b0      	blx	r6
	__asm__ volatile(
     a04:	f04f 0320 	mov.w	r3, #32
     a08:	f3ef 8b11 	mrs	fp, BASEPRI
     a0c:	f383 8811 	msr	BASEPRI, r3
     a10:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     a14:	8b23      	ldrh	r3, [r4, #24]
     a16:	f023 0308 	bic.w	r3, r3, #8
     a1a:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     a1c:	8b23      	ldrh	r3, [r4, #24]
     a1e:	06da      	lsls	r2, r3, #27
     a20:	d52a      	bpl.n	a78 <process_event+0x1bc>
			evt = EVT_COMPLETE;
     a22:	2101      	movs	r1, #1
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     a24:	f023 0310 	bic.w	r3, r3, #16
     a28:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
     a2a:	f8b4 9018 	ldrh.w	r9, [r4, #24]
     a2e:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
     a32:	2900      	cmp	r1, #0
     a34:	f47f af5e 	bne.w	8f4 <process_event+0x38>
out:
     a38:	e751      	b.n	8de <process_event+0x22>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     a3a:	68a1      	ldr	r1, [r4, #8]
     a3c:	2900      	cmp	r1, #0
     a3e:	d0db      	beq.n	9f8 <process_event+0x13c>
	return node->next;
     a40:	680b      	ldr	r3, [r1, #0]
     a42:	2b00      	cmp	r3, #0
     a44:	bf38      	it	cc
     a46:	2300      	movcc	r3, #0
     a48:	4699      	mov	r9, r3
		mon->callback(mgr, mon, state, res);
     a4a:	4620      	mov	r0, r4
     a4c:	463b      	mov	r3, r7
     a4e:	f8d1 b004 	ldr.w	fp, [r1, #4]
     a52:	9201      	str	r2, [sp, #4]
     a54:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     a56:	9a01      	ldr	r2, [sp, #4]
     a58:	f1b9 0f00 	cmp.w	r9, #0
     a5c:	d0cc      	beq.n	9f8 <process_event+0x13c>
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     a5e:	4649      	mov	r1, r9
     a60:	f8d9 3000 	ldr.w	r3, [r9]
     a64:	e7ed      	b.n	a42 <process_event+0x186>
 *
 * @return A pointer to the first node of the list
 */
static inline sys_snode_t *sys_slist_get_not_empty(sys_slist_t *list);

Z_GENLIST_GET_NOT_EMPTY(slist, snode)
     a66:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
     a68:	463b      	mov	r3, r7
     a6a:	4620      	mov	r0, r4
     a6c:	9201      	str	r2, [sp, #4]
     a6e:	682d      	ldr	r5, [r5, #0]
     a70:	f003 fcf5 	bl	445e <notify_one>
	while (!sys_slist_is_empty(list)) {
     a74:	9a01      	ldr	r2, [sp, #4]
     a76:	e7bf      	b.n	9f8 <process_event+0x13c>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     a78:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     a7c:	bf1e      	ittt	ne
     a7e:	f023 0320 	bicne.w	r3, r3, #32
			evt = EVT_RECHECK;
     a82:	2102      	movne	r1, #2
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     a84:	8323      	strhne	r3, [r4, #24]
			evt = EVT_RECHECK;
     a86:	e7d0      	b.n	a2a <process_event+0x16e>
     a88:	0000448b 	.word	0x0000448b

00000a8c <nordicsemi_nrf91_init>:
     a8c:	f04f 0220 	mov.w	r2, #32
     a90:	f3ef 8311 	mrs	r3, BASEPRI
     a94:	f382 8811 	msr	BASEPRI, r2
     a98:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
     a9c:	2101      	movs	r1, #1
     a9e:	4a04      	ldr	r2, [pc, #16]	; (ab0 <nordicsemi_nrf91_init+0x24>)
     aa0:	f8c2 1540 	str.w	r1, [r2, #1344]	; 0x540
	__asm__ volatile(
     aa4:	f383 8811 	msr	BASEPRI, r3
     aa8:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
     aac:	2000      	movs	r0, #0
     aae:	4770      	bx	lr
     ab0:	50039000 	.word	0x50039000

00000ab4 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
     ab4:	b120      	cbz	r0, ac0 <arch_busy_wait+0xc>
    };

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
     ab6:	4b03      	ldr	r3, [pc, #12]	; (ac4 <arch_busy_wait+0x10>)
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
     ab8:	0180      	lsls	r0, r0, #6
     aba:	f043 0301 	orr.w	r3, r3, #1
     abe:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
     ac0:	4770      	bx	lr
     ac2:	bf00      	nop
     ac4:	00005140 	.word	0x00005140

00000ac8 <sys_reboot>:

extern void sys_arch_reboot(int type);
extern void sys_clock_disable(void);

void sys_reboot(int type)
{
     ac8:	b507      	push	{r0, r1, r2, lr}
     aca:	9001      	str	r0, [sp, #4]
	__asm__ volatile(
     acc:	f04f 0220 	mov.w	r2, #32
     ad0:	f3ef 8311 	mrs	r3, BASEPRI
     ad4:	f382 8811 	msr	BASEPRI, r2
     ad8:	f3bf 8f6f 	isb	sy
	(void)irq_lock();
#ifdef CONFIG_SYS_CLOCK_EXISTS
	sys_clock_disable();
     adc:	f003 fed2 	bl	4884 <sys_clock_disable>
#endif

	sys_arch_reboot(type);
     ae0:	9801      	ldr	r0, [sp, #4]
     ae2:	f000 ffed 	bl	1ac0 <sys_arch_reboot>

	/* should never get here */
	printk("Failed to reboot: spinning endlessly...\n");
     ae6:	4803      	ldr	r0, [pc, #12]	; (af4 <sys_reboot+0x2c>)
     ae8:	f003 fc90 	bl	440c <printk>
 *
 * @return N/A
 */
static inline void k_cpu_idle(void)
{
	arch_cpu_idle();
     aec:	f000 fe40 	bl	1770 <arch_cpu_idle>
     af0:	e7fc      	b.n	aec <sys_reboot+0x24>
     af2:	bf00      	nop
     af4:	000053f2 	.word	0x000053f2

00000af8 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
     af8:	b508      	push	{r3, lr}
	if (z_syscall_trap()) {
		return (const struct device *) arch_syscall_invoke1(*(uintptr_t *)&name, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
     afa:	4806      	ldr	r0, [pc, #24]	; (b14 <uart_console_init+0x1c>)
     afc:	f001 fd58 	bl	25b0 <z_impl_device_get_binding>

	ARG_UNUSED(arg);

	/* Claim console device */
	uart_console_dev = device_get_binding(CONFIG_UART_CONSOLE_ON_DEV_NAME);
     b00:	4b05      	ldr	r3, [pc, #20]	; (b18 <uart_console_init+0x20>)
     b02:	6018      	str	r0, [r3, #0]
	__stdout_hook_install(console_out);
     b04:	4805      	ldr	r0, [pc, #20]	; (b1c <uart_console_init+0x24>)
     b06:	f001 fa13 	bl	1f30 <__stdout_hook_install>
	__printk_hook_install(console_out);
     b0a:	4804      	ldr	r0, [pc, #16]	; (b1c <uart_console_init+0x24>)
     b0c:	f7ff fd94 	bl	638 <__printk_hook_install>

	uart_console_hook_install();

	return 0;
}
     b10:	2000      	movs	r0, #0
     b12:	bd08      	pop	{r3, pc}
     b14:	0000541b 	.word	0x0000541b
     b18:	20000268 	.word	0x20000268
     b1c:	00000b21 	.word	0x00000b21

00000b20 <console_out>:
	if ('\n' == c) {
     b20:	280a      	cmp	r0, #10
{
     b22:	b538      	push	{r3, r4, r5, lr}
     b24:	4604      	mov	r4, r0
     b26:	4d07      	ldr	r5, [pc, #28]	; (b44 <console_out+0x24>)
	if ('\n' == c) {
     b28:	d104      	bne.n	b34 <console_out+0x14>
     b2a:	6828      	ldr	r0, [r5, #0]
						unsigned char out_char)
{
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
     b2c:	6883      	ldr	r3, [r0, #8]
     b2e:	210d      	movs	r1, #13
     b30:	685b      	ldr	r3, [r3, #4]
     b32:	4798      	blx	r3
	uart_poll_out(uart_console_dev, c);
     b34:	6828      	ldr	r0, [r5, #0]
     b36:	6883      	ldr	r3, [r0, #8]
     b38:	b2e1      	uxtb	r1, r4
     b3a:	685b      	ldr	r3, [r3, #4]
     b3c:	4798      	blx	r3
}
     b3e:	4620      	mov	r0, r4
     b40:	bd38      	pop	{r3, r4, r5, pc}
     b42:	bf00      	nop
     b44:	20000268 	.word	0x20000268

00000b48 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = DEVICE_GET(clock_nrf)->data;
	size_t offset = (size_t)(mgr - data->mgr);
     b48:	4a0e      	ldr	r2, [pc, #56]	; (b84 <onoff_stop+0x3c>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
     b4a:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
     b4c:	1a84      	subs	r4, r0, r2
{
     b4e:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
     b50:	200c      	movs	r0, #12
{
     b52:	460e      	mov	r6, r1
	err = set_off_state(&subdata->flags, ctx);
     b54:	2140      	movs	r1, #64	; 0x40
	size_t offset = (size_t)(mgr - data->mgr);
     b56:	10a3      	asrs	r3, r4, #2
     b58:	4c0b      	ldr	r4, [pc, #44]	; (b88 <onoff_stop+0x40>)
     b5a:	435c      	muls	r4, r3
     b5c:	b2e4      	uxtb	r4, r4
	err = set_off_state(&subdata->flags, ctx);
     b5e:	fb00 2004 	mla	r0, r0, r4, r2
     b62:	4408      	add	r0, r1
     b64:	f003 fdfd 	bl	4762 <set_off_state>
	if (err < 0) {
     b68:	1e01      	subs	r1, r0, #0
     b6a:	db05      	blt.n	b78 <onoff_stop+0x30>
	get_sub_config(dev, type)->stop();
     b6c:	4b07      	ldr	r3, [pc, #28]	; (b8c <onoff_stop+0x44>)
     b6e:	eb03 04c4 	add.w	r4, r3, r4, lsl #3
     b72:	6863      	ldr	r3, [r4, #4]
     b74:	4798      	blx	r3
	return 0;
     b76:	2100      	movs	r1, #0
	int res;

	res = stop(DEVICE_GET(clock_nrf), get_subsys(mgr), CTX_ONOFF);
	notify(mgr, res);
     b78:	4628      	mov	r0, r5
     b7a:	4633      	mov	r3, r6
}
     b7c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
     b80:	4718      	bx	r3
     b82:	bf00      	nop
     b84:	2000027c 	.word	0x2000027c
     b88:	b6db6db7 	.word	0xb6db6db7
     b8c:	0000515c 	.word	0x0000515c

00000b90 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
     b90:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	err = set_starting_state(&subdata->flags, ctx);
     b94:	250c      	movs	r5, #12
	size_t offset = (size_t)(mgr - data->mgr);
     b96:	4e10      	ldr	r6, [pc, #64]	; (bd8 <onoff_start+0x48>)
{
     b98:	4680      	mov	r8, r0
	size_t offset = (size_t)(mgr - data->mgr);
     b9a:	1b84      	subs	r4, r0, r6
     b9c:	10a3      	asrs	r3, r4, #2
     b9e:	4c0f      	ldr	r4, [pc, #60]	; (bdc <onoff_start+0x4c>)
{
     ba0:	460f      	mov	r7, r1
	size_t offset = (size_t)(mgr - data->mgr);
     ba2:	435c      	muls	r4, r3
     ba4:	b2e4      	uxtb	r4, r4
	err = set_starting_state(&subdata->flags, ctx);
     ba6:	4365      	muls	r5, r4
     ba8:	f105 0040 	add.w	r0, r5, #64	; 0x40
     bac:	2140      	movs	r1, #64	; 0x40
     bae:	4430      	add	r0, r6
     bb0:	f003 fdf0 	bl	4794 <set_starting_state>
	if (err < 0) {
     bb4:	1e01      	subs	r1, r0, #0
     bb6:	db09      	blt.n	bcc <onoff_start+0x3c>
	subdata->cb = data->cb;
     bb8:	4a09      	ldr	r2, [pc, #36]	; (be0 <onoff_start+0x50>)
     bba:	1973      	adds	r3, r6, r5
	subdata->user_data = data->user_data;
     bbc:	e9c3 270e 	strd	r2, r7, [r3, #56]	; 0x38
	 get_sub_config(dev, type)->start();
     bc0:	4b08      	ldr	r3, [pc, #32]	; (be4 <onoff_start+0x54>)
     bc2:	f853 3034 	ldr.w	r3, [r3, r4, lsl #3]
	err = async_start(DEVICE_GET(clock_nrf), get_subsys(mgr),
			  &data, CTX_ONOFF);
	if (err < 0) {
		notify(mgr, err);
	}
}
     bc6:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
	 get_sub_config(dev, type)->start();
     bca:	4718      	bx	r3
		notify(mgr, err);
     bcc:	4640      	mov	r0, r8
     bce:	463b      	mov	r3, r7
}
     bd0:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		notify(mgr, err);
     bd4:	4718      	bx	r3
     bd6:	bf00      	nop
     bd8:	2000027c 	.word	0x2000027c
     bdc:	b6db6db7 	.word	0xb6db6db7
     be0:	000047f7 	.word	0x000047f7
     be4:	0000515c 	.word	0x0000515c

00000be8 <clk_init>:
		break;
	}
}

static int clk_init(const struct device *dev)
{
     be8:	b570      	push	{r4, r5, r6, lr}
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
     bea:	2200      	movs	r2, #0
     bec:	2101      	movs	r1, #1
{
     bee:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
     bf0:	2005      	movs	r0, #5
     bf2:	f000 fd67 	bl	16c4 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);
	irq_enable(DT_INST_IRQN(0));
     bf6:	2005      	movs	r0, #5
     bf8:	f000 fd46 	bl	1688 <arch_irq_enable>
					NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
		nrf_gpio_pin_mcu_select(PIN_XL2,
					NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
	}
#endif
	nrfx_err = nrfx_clock_init(clock_event_handler);
     bfc:	480f      	ldr	r0, [pc, #60]	; (c3c <clk_init+0x54>)
     bfe:	f001 fbe1 	bl	23c4 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
     c02:	4b0f      	ldr	r3, [pc, #60]	; (c40 <clk_init+0x58>)
     c04:	4298      	cmp	r0, r3
     c06:	d115      	bne.n	c34 <clk_init+0x4c>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
     c08:	f003 ffef 	bl	4bea <nrfx_clock_enable>

	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);
     c0c:	68e6      	ldr	r6, [r4, #12]

		err = onoff_manager_init(get_onoff_manager(dev, i),
     c0e:	490d      	ldr	r1, [pc, #52]	; (c44 <clk_init+0x5c>)
     c10:	4630      	mov	r0, r6
     c12:	f003 fc58 	bl	44c6 <onoff_manager_init>
					 &transitions);
		if (err < 0) {
     c16:	2800      	cmp	r0, #0
     c18:	db0b      	blt.n	c32 <clk_init+0x4a>
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
     c1a:	2501      	movs	r5, #1
     c1c:	6435      	str	r5, [r6, #64]	; 0x40
						get_sub_data(dev, i);
     c1e:	68e4      	ldr	r4, [r4, #12]
		err = onoff_manager_init(get_onoff_manager(dev, i),
     c20:	4908      	ldr	r1, [pc, #32]	; (c44 <clk_init+0x5c>)
     c22:	f104 001c 	add.w	r0, r4, #28
     c26:	f003 fc4e 	bl	44c6 <onoff_manager_init>
		if (err < 0) {
     c2a:	2800      	cmp	r0, #0
     c2c:	db01      	blt.n	c32 <clk_init+0x4a>
	}

	return 0;
     c2e:	2000      	movs	r0, #0
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
     c30:	64e5      	str	r5, [r4, #76]	; 0x4c
}
     c32:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
     c34:	f06f 0004 	mvn.w	r0, #4
     c38:	e7fb      	b.n	c32 <clk_init+0x4a>
     c3a:	bf00      	nop
     c3c:	00000c85 	.word	0x00000c85
     c40:	0bad0000 	.word	0x0bad0000
     c44:	0000516c 	.word	0x0000516c

00000c48 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
     c48:	b573      	push	{r0, r1, r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
     c4a:	230c      	movs	r3, #12
static void clkstarted_handle(const struct device *dev,
     c4c:	4601      	mov	r1, r0
	sub_data->cb = NULL;
     c4e:	2600      	movs	r6, #0
	clock_control_cb_t callback = sub_data->cb;
     c50:	434b      	muls	r3, r1
     c52:	480a      	ldr	r0, [pc, #40]	; (c7c <clkstarted_handle.constprop.0+0x34>)
     c54:	18c4      	adds	r4, r0, r3
	set_on_state(&sub_data->flags);
     c56:	3340      	adds	r3, #64	; 0x40
	void *user_data = sub_data->user_data;
     c58:	e9d4 520e 	ldrd	r5, r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
     c5c:	4418      	add	r0, r3
	sub_data->cb = NULL;
     c5e:	63a6      	str	r6, [r4, #56]	; 0x38
	void *user_data = sub_data->user_data;
     c60:	9201      	str	r2, [sp, #4]
	set_on_state(&sub_data->flags);
     c62:	f003 fdb5 	bl	47d0 <set_on_state>
	if (callback) {
     c66:	b135      	cbz	r5, c76 <clkstarted_handle.constprop.0+0x2e>
		callback(dev, (clock_control_subsys_t)type, user_data);
     c68:	462b      	mov	r3, r5
     c6a:	9a01      	ldr	r2, [sp, #4]
     c6c:	4804      	ldr	r0, [pc, #16]	; (c80 <clkstarted_handle.constprop.0+0x38>)
}
     c6e:	b002      	add	sp, #8
     c70:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
     c74:	4718      	bx	r3
}
     c76:	b002      	add	sp, #8
     c78:	bd70      	pop	{r4, r5, r6, pc}
     c7a:	bf00      	nop
     c7c:	2000027c 	.word	0x2000027c
     c80:	200000bc 	.word	0x200000bc

00000c84 <clock_event_handler>:
	switch (event) {
     c84:	b110      	cbz	r0, c8c <clock_event_handler+0x8>
     c86:	2801      	cmp	r0, #1
     c88:	d004      	beq.n	c94 <clock_event_handler+0x10>
     c8a:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
     c8c:	4b03      	ldr	r3, [pc, #12]	; (c9c <clock_event_handler+0x18>)
     c8e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
     c90:	075b      	lsls	r3, r3, #29
     c92:	d101      	bne.n	c98 <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
     c94:	f7ff bfd8 	b.w	c48 <clkstarted_handle.constprop.0>
}
     c98:	4770      	bx	lr
     c9a:	bf00      	nop
     c9c:	2000027c 	.word	0x2000027c

00000ca0 <generic_hfclk_start>:
{
     ca0:	b508      	push	{r3, lr}
     ca2:	f04f 0320 	mov.w	r3, #32
     ca6:	f3ef 8111 	mrs	r1, BASEPRI
     caa:	f383 8811 	msr	BASEPRI, r3
     cae:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
     cb2:	4a12      	ldr	r2, [pc, #72]	; (cfc <generic_hfclk_start+0x5c>)
     cb4:	6813      	ldr	r3, [r2, #0]
     cb6:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
     cba:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
     cbe:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
     cc0:	d00c      	beq.n	cdc <generic_hfclk_start+0x3c>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
     cc2:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
     cc6:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
     cca:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
     cce:	f013 0301 	ands.w	r3, r3, #1
     cd2:	d003      	beq.n	cdc <generic_hfclk_start+0x3c>
			set_on_state(get_hf_flags());
     cd4:	480a      	ldr	r0, [pc, #40]	; (d00 <generic_hfclk_start+0x60>)
     cd6:	f003 fd7b 	bl	47d0 <set_on_state>
			already_started = true;
     cda:	2301      	movs	r3, #1
	__asm__ volatile(
     cdc:	f381 8811 	msr	BASEPRI, r1
     ce0:	f3bf 8f6f 	isb	sy
	if (already_started) {
     ce4:	b123      	cbz	r3, cf0 <generic_hfclk_start+0x50>
}
     ce6:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(DEVICE_GET(clock_nrf),
     cea:	2000      	movs	r0, #0
     cec:	f7ff bfac 	b.w	c48 <clkstarted_handle.constprop.0>
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
     cf0:	2001      	movs	r0, #1
}
     cf2:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
     cf6:	f001 bb75 	b.w	23e4 <nrfx_clock_start>
     cfa:	bf00      	nop
     cfc:	200002cc 	.word	0x200002cc
     d00:	200002bc 	.word	0x200002bc

00000d04 <generic_hfclk_stop>:
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
     d04:	4b07      	ldr	r3, [pc, #28]	; (d24 <generic_hfclk_stop+0x20>)
     d06:	e8d3 2fef 	ldaex	r2, [r3]
     d0a:	f022 0102 	bic.w	r1, r2, #2
     d0e:	e8c3 1fe0 	stlex	r0, r1, [r3]
     d12:	2800      	cmp	r0, #0
     d14:	d1f7      	bne.n	d06 <generic_hfclk_stop+0x2>
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
     d16:	07d3      	lsls	r3, r2, #31
     d18:	d402      	bmi.n	d20 <generic_hfclk_stop+0x1c>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
     d1a:	2001      	movs	r0, #1
     d1c:	f001 bb94 	b.w	2448 <nrfx_clock_stop>
}
     d20:	4770      	bx	lr
     d22:	bf00      	nop
     d24:	200002cc 	.word	0x200002cc

00000d28 <api_blocking_start>:
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
     d28:	2300      	movs	r3, #0
     d2a:	2201      	movs	r2, #1
{
     d2c:	b510      	push	{r4, lr}
     d2e:	b088      	sub	sp, #32
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
     d30:	e9cd 3206 	strd	r3, r2, [sp, #24]
	struct clock_control_async_data data = {
     d34:	9301      	str	r3, [sp, #4]
     d36:	4b09      	ldr	r3, [pc, #36]	; (d5c <api_blocking_start+0x34>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
     d38:	ac04      	add	r4, sp, #16
	err = api_start(dev, subsys, &data);
     d3a:	aa01      	add	r2, sp, #4
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
     d3c:	e9cd 4404 	strd	r4, r4, [sp, #16]
	struct clock_control_async_data data = {
     d40:	e9cd 3402 	strd	r3, r4, [sp, #8]
	err = api_start(dev, subsys, &data);
     d44:	f003 fd7e 	bl	4844 <api_start>
	if (err < 0) {
     d48:	2800      	cmp	r0, #0
     d4a:	db05      	blt.n	d58 <api_blocking_start+0x30>
		parm0.val = timeout;
		return (int) arch_syscall_invoke3(*(uintptr_t *)&sem, parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
     d4c:	f44f 4280 	mov.w	r2, #16384	; 0x4000
     d50:	2300      	movs	r3, #0
     d52:	4620      	mov	r0, r4
     d54:	f002 f9fa 	bl	314c <z_impl_k_sem_take>
}
     d58:	b008      	add	sp, #32
     d5a:	bd10      	pop	{r4, pc}
     d5c:	0000480b 	.word	0x0000480b

00000d60 <z_nrf_clock_control_lf_on>:
{
     d60:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
     d64:	2201      	movs	r2, #1
     d66:	4606      	mov	r6, r0
     d68:	4939      	ldr	r1, [pc, #228]	; (e50 <z_nrf_clock_control_lf_on+0xf0>)
     d6a:	e8d1 3fef 	ldaex	r3, [r1]
     d6e:	e8c1 2fe0 	stlex	r0, r2, [r1]
     d72:	2800      	cmp	r0, #0
     d74:	d1f9      	bne.n	d6a <z_nrf_clock_control_lf_on+0xa>
	if (atomic_set(&on, 1) == 0) {
     d76:	b933      	cbnz	r3, d86 <z_nrf_clock_control_lf_on+0x26>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
     d78:	4936      	ldr	r1, [pc, #216]	; (e54 <z_nrf_clock_control_lf_on+0xf4>)
		err = onoff_request(mgr, &cli);
     d7a:	4837      	ldr	r0, [pc, #220]	; (e58 <z_nrf_clock_control_lf_on+0xf8>)
     d7c:	604b      	str	r3, [r1, #4]
     d7e:	60cb      	str	r3, [r1, #12]
     d80:	608a      	str	r2, [r1, #8]
     d82:	f003 fbb3 	bl	44ec <onoff_request>
	switch (start_mode) {
     d86:	1e73      	subs	r3, r6, #1
     d88:	2b01      	cmp	r3, #1
     d8a:	d832      	bhi.n	df2 <z_nrf_clock_control_lf_on+0x92>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
     d8c:	2e01      	cmp	r6, #1
     d8e:	d107      	bne.n	da0 <z_nrf_clock_control_lf_on+0x40>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
     d90:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
     d94:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
     d98:	f003 0303 	and.w	r3, r3, #3
     d9c:	2b02      	cmp	r3, #2
     d9e:	d028      	beq.n	df2 <z_nrf_clock_control_lf_on+0x92>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
     da0:	f004 f81a 	bl	4dd8 <k_is_in_isr>
     da4:	4604      	mov	r4, r0
     da6:	b918      	cbnz	r0, db0 <z_nrf_clock_control_lf_on+0x50>
	return !z_sys_post_kernel;
     da8:	4b2c      	ldr	r3, [pc, #176]	; (e5c <z_nrf_clock_control_lf_on+0xfc>)
	int key = isr_mode ? irq_lock() : 0;
     daa:	781b      	ldrb	r3, [r3, #0]
     dac:	2b00      	cmp	r3, #0
     dae:	d147      	bne.n	e40 <z_nrf_clock_control_lf_on+0xe0>
	__asm__ volatile(
     db0:	f04f 0320 	mov.w	r3, #32
     db4:	f3ef 8511 	mrs	r5, BASEPRI
     db8:	f383 8811 	msr	BASEPRI, r3
     dbc:	f3bf 8f6f 	isb	sy
     dc0:	2401      	movs	r4, #1
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
     dc2:	4f27      	ldr	r7, [pc, #156]	; (e60 <z_nrf_clock_control_lf_on+0x100>)
 */
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
     dc4:	f8df 809c 	ldr.w	r8, [pc, #156]	; e64 <z_nrf_clock_control_lf_on+0x104>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
     dc8:	f8df 909c 	ldr.w	r9, [pc, #156]	; e68 <z_nrf_clock_control_lf_on+0x108>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
     dcc:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
     dd0:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
     dd4:	f8d2 2418 	ldr.w	r2, [r2, #1048]	; 0x418
     dd8:	03d2      	lsls	r2, r2, #15
     dda:	d50c      	bpl.n	df6 <z_nrf_clock_control_lf_on+0x96>
	while (!(nrfx_clock_is_running(d, (void *)&type)
     ddc:	f003 0303 	and.w	r3, r3, #3
     de0:	2b02      	cmp	r3, #2
     de2:	d001      	beq.n	de8 <z_nrf_clock_control_lf_on+0x88>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
     de4:	2e01      	cmp	r6, #1
     de6:	d106      	bne.n	df6 <z_nrf_clock_control_lf_on+0x96>
	if (isr_mode) {
     de8:	b324      	cbz	r4, e34 <z_nrf_clock_control_lf_on+0xd4>
	__asm__ volatile(
     dea:	f385 8811 	msr	BASEPRI, r5
     dee:	f3bf 8f6f 	isb	sy
}
     df2:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			if (isr_mode) {
     df6:	b1c4      	cbz	r4, e2a <z_nrf_clock_control_lf_on+0xca>
 *
 * @return N/A
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
     df8:	4628      	mov	r0, r5
     dfa:	f000 fcc7 	bl	178c <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
     dfe:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
     e02:	f8d2 3518 	ldr.w	r3, [r2, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
     e06:	b2db      	uxtb	r3, r3
     e08:	2b01      	cmp	r3, #1
     e0a:	d1df      	bne.n	dcc <z_nrf_clock_control_lf_on+0x6c>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
     e0c:	6839      	ldr	r1, [r7, #0]
		    && nrf_clock_event_check(NRF_CLOCK,
     e0e:	2900      	cmp	r1, #0
     e10:	d0dc      	beq.n	dcc <z_nrf_clock_control_lf_on+0x6c>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
     e12:	2100      	movs	r1, #0
     e14:	6039      	str	r1, [r7, #0]
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
     e16:	6839      	ldr	r1, [r7, #0]
    p_reg->LFCLKSRC = (uint32_t)(source);
     e18:	2102      	movs	r1, #2
     e1a:	f8c2 1518 	str.w	r1, [r2, #1304]	; 0x518
     e1e:	2220      	movs	r2, #32
     e20:	f8c8 2180 	str.w	r2, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
     e24:	f8c9 3000 	str.w	r3, [r9]
}
     e28:	e7d0      	b.n	dcc <z_nrf_clock_control_lf_on+0x6c>
	return z_impl_k_sleep(timeout);
     e2a:	2100      	movs	r1, #0
     e2c:	2021      	movs	r0, #33	; 0x21
     e2e:	f002 f947 	bl	30c0 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
     e32:	e7e4      	b.n	dfe <z_nrf_clock_control_lf_on+0x9e>
    p_reg->INTENSET = mask;
     e34:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
     e38:	2202      	movs	r2, #2
     e3a:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
     e3e:	e7d8      	b.n	df2 <z_nrf_clock_control_lf_on+0x92>
    p_reg->INTENCLR = mask;
     e40:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
     e44:	2202      	movs	r2, #2
	int key = isr_mode ? irq_lock() : 0;
     e46:	4605      	mov	r5, r0
     e48:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
     e4c:	e7b9      	b.n	dc2 <z_nrf_clock_control_lf_on+0x62>
     e4e:	bf00      	nop
     e50:	200002d0 	.word	0x200002d0
     e54:	2000026c 	.word	0x2000026c
     e58:	20000298 	.word	0x20000298
     e5c:	2000086d 	.word	0x2000086d
     e60:	50005104 	.word	0x50005104
     e64:	e000e100 	.word	0xe000e100
     e68:	50005008 	.word	0x50005008

00000e6c <handle_next_cycle_case>:
 * counter progresses during that time it means that 1 cycle elapsed and
 * interrupt is set pending.
 */
static void handle_next_cycle_case(uint32_t t)
{
	set_comparator(t + 2);
     e6c:	1c82      	adds	r2, r0, #2

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE  void nrf_rtc_cc_set(NRF_RTC_Type * p_reg, uint32_t ch, uint32_t cc_val)
{
    p_reg->CC[ch] = cc_val;
     e6e:	4b08      	ldr	r3, [pc, #32]	; (e90 <handle_next_cycle_case+0x24>)
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
     e70:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
     e74:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type const * p_reg)
{
     return p_reg->COUNTER;
     e78:	f8d3 2504 	ldr.w	r2, [r3, #1284]	; 0x504
	while (t != counter()) {
     e7c:	4290      	cmp	r0, r2
     e7e:	d100      	bne.n	e82 <handle_next_cycle_case+0x16>
		 * generated. Trigger interrupt.
		 */
		t = counter();
		set_comparator(t + 2);
	}
}
     e80:	4770      	bx	lr
     e82:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
		set_comparator(t + 2);
     e86:	1c82      	adds	r2, r0, #2
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
     e88:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
     e8c:	e7f2      	b.n	e74 <handle_next_cycle_case+0x8>
     e8e:	bf00      	nop
     e90:	50015000 	.word	0x50015000

00000e94 <rtc_nrf_isr>:
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
     e94:	2200      	movs	r2, #0
     e96:	4b07      	ldr	r3, [pc, #28]	; (eb4 <rtc_nrf_isr+0x20>)
     e98:	601a      	str	r2, [r3, #0]
     e9a:	681b      	ldr	r3, [r3, #0]
{
	ARG_UNUSED(arg);
	event_clear();

	uint32_t t = get_comparator();
	uint32_t dticks = counter_sub(t, last_count) / CYC_PER_TICK;
     e9c:	4a06      	ldr	r2, [pc, #24]	; (eb8 <rtc_nrf_isr+0x24>)
    return p_reg->CC[ch];
     e9e:	4b07      	ldr	r3, [pc, #28]	; (ebc <rtc_nrf_isr+0x28>)
     ea0:	f8d3 0540 	ldr.w	r0, [r3, #1344]	; 0x540
     ea4:	6813      	ldr	r3, [r2, #0]
	return (a - b) & COUNTER_MAX;
     ea6:	1ac0      	subs	r0, r0, r3
     ea8:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000

	last_count += dticks * CYC_PER_TICK;
     eac:	4403      	add	r3, r0
     eae:	6013      	str	r3, [r2, #0]
		 * so it won't get preempted by the interrupt.
		 */
		set_absolute_alarm(last_count + CYC_PER_TICK);
	}

	z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : (dticks > 0));
     eb0:	f002 bad8 	b.w	3464 <z_clock_announce>
     eb4:	50015140 	.word	0x50015140
     eb8:	200002d4 	.word	0x200002d4
     ebc:	50015000 	.word	0x50015000

00000ec0 <z_clock_driver_init>:
}

int z_clock_driver_init(const struct device *device)
{
     ec0:	b538      	push	{r3, r4, r5, lr}
}

NRF_STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_reg, uint32_t val)
{
    NRFX_ASSERT(val <= (RTC_PRESCALER_PRESCALER_Msk >> RTC_PRESCALER_PRESCALER_Pos));
    p_reg->PRESCALER = val;
     ec2:	2400      	movs	r4, #0
     ec4:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
     ec8:	4d0e      	ldr	r5, [pc, #56]	; (f04 <z_clock_driver_init+0x44>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
     eca:	4b0f      	ldr	r3, [pc, #60]	; (f08 <z_clock_driver_init+0x48>)
    p_reg->PRESCALER = val;
     ecc:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
     ed0:	601c      	str	r4, [r3, #0]
     ed2:	681b      	ldr	r3, [r3, #0]
     ed4:	4b0d      	ldr	r3, [pc, #52]	; (f0c <z_clock_driver_init+0x4c>)
	nrf_rtc_prescaler_set(RTC, 0);
	event_clear();
	NVIC_ClearPendingIRQ(RTC_IRQn);
	int_enable();

	IRQ_CONNECT(RTC_IRQn, 1, rtc_nrf_isr, 0, 0);
     ed6:	2101      	movs	r1, #1
     ed8:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    p_reg->INTENSET = mask;
     edc:	f44f 3380 	mov.w	r3, #65536	; 0x10000
     ee0:	4622      	mov	r2, r4
     ee2:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
     ee6:	2015      	movs	r0, #21
     ee8:	f000 fbec 	bl	16c4 <z_arm_irq_priority_set>
	irq_enable(RTC_IRQn);
     eec:	2015      	movs	r0, #21
     eee:	f000 fbcb 	bl	1688 <arch_irq_enable>
    return (uint32_t)p_reg + task;
}

NRF_STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_reg, nrf_rtc_task_t task)
{
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
     ef2:	2301      	movs	r3, #1
     ef4:	4a06      	ldr	r2, [pc, #24]	; (f10 <z_clock_driver_init+0x50>)

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		set_comparator(counter() + CYC_PER_TICK);
	}

	z_nrf_clock_control_lf_on(mode);
     ef6:	2002      	movs	r0, #2
     ef8:	6013      	str	r3, [r2, #0]
     efa:	602b      	str	r3, [r5, #0]
     efc:	f7ff ff30 	bl	d60 <z_nrf_clock_control_lf_on>

	return 0;
}
     f00:	4620      	mov	r0, r4
     f02:	bd38      	pop	{r3, r4, r5, pc}
     f04:	50015000 	.word	0x50015000
     f08:	50015140 	.word	0x50015140
     f0c:	e000e100 	.word	0xe000e100
     f10:	50015008 	.word	0x50015008

00000f14 <z_clock_set_timeout>:

void z_clock_set_timeout(int32_t ticks, bool idle)
{
     f14:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
     return p_reg->COUNTER;
     f16:	4b2d      	ldr	r3, [pc, #180]	; (fcc <z_clock_set_timeout+0xb8>)

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return;
	}

	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
     f18:	4c2d      	ldr	r4, [pc, #180]	; (fd0 <z_clock_set_timeout+0xbc>)
     f1a:	f8d3 2504 	ldr.w	r2, [r3, #1284]	; 0x504
	ticks = MAX(MIN(ticks - 1, (int32_t)MAX_TICKS), 0);

	uint32_t unannounced = counter_sub(counter(), last_count);
     f1e:	4b2d      	ldr	r3, [pc, #180]	; (fd4 <z_clock_set_timeout+0xc0>)
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
     f20:	f1b0 3fff 	cmp.w	r0, #4294967295
     f24:	bf08      	it	eq
     f26:	4620      	moveq	r0, r4
	uint32_t unannounced = counter_sub(counter(), last_count);
     f28:	6819      	ldr	r1, [r3, #0]
	return (a - b) & COUNTER_MAX;
     f2a:	1a52      	subs	r2, r2, r1
     f2c:	f022 437f 	bic.w	r3, r2, #4278190080	; 0xff000000
	/* If we haven't announced for more than half the 24-bit wrap
	 * duration, then force an announce to avoid loss of a wrap
	 * event.  This can happen if new timeouts keep being set
	 * before the existing one triggers the interrupt.
	 */
	if (unannounced >= COUNTER_HALF_SPAN) {
     f30:	0212      	lsls	r2, r2, #8
     f32:	d438      	bmi.n	fa6 <z_clock_set_timeout+0x92>
	ticks = MAX(MIN(ticks - 1, (int32_t)MAX_TICKS), 0);
     f34:	3801      	subs	r0, #1
     f36:	ea20 70e0 	bic.w	r0, r0, r0, asr #31
     f3a:	42a0      	cmp	r0, r4
     f3c:	bfa8      	it	ge
     f3e:	4620      	movge	r0, r4
	}

	/* Get the cycles from last_count to the tick boundary after
	 * the requested ticks have passed starting now.
	 */
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
     f40:	3301      	adds	r3, #1
     f42:	4418      	add	r0, r3
	 */
	if (cyc > MAX_CYCLES) {
		cyc = MAX_CYCLES;
	}

	cyc += last_count;
     f44:	42a0      	cmp	r0, r4
     f46:	bf94      	ite	ls
     f48:	180c      	addls	r4, r1, r0
     f4a:	190c      	addhi	r4, r1, r4
    p_reg->INTENCLR = mask;
     f4c:	f44f 3080 	mov.w	r0, #65536	; 0x10000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
     f50:	2600      	movs	r6, #0
    p_reg->INTENCLR = mask;
     f52:	4a1e      	ldr	r2, [pc, #120]	; (fcc <z_clock_set_timeout+0xb8>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
     f54:	4d20      	ldr	r5, [pc, #128]	; (fd8 <z_clock_set_timeout+0xc4>)
    p_reg->INTENCLR = mask;
     f56:	f8c2 0308 	str.w	r0, [r2, #776]	; 0x308
     return p_reg->COUNTER;
     f5a:	f8d2 1504 	ldr.w	r1, [r2, #1284]	; 0x504
    return p_reg->CC[ch];
     f5e:	f8d2 3540 	ldr.w	r3, [r2, #1344]	; 0x540
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
     f62:	602e      	str	r6, [r5, #0]
	return (a - b) & COUNTER_MAX;
     f64:	1a5b      	subs	r3, r3, r1
     f66:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
     f6a:	682f      	ldr	r7, [r5, #0]
	if (counter_sub(prev_val, now) == 1) {
     f6c:	2b01      	cmp	r3, #1
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
     f6e:	f021 477f 	bic.w	r7, r1, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
     f72:	f8c2 7540 	str.w	r7, [r2, #1344]	; 0x540
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
     f76:	f8c2 0344 	str.w	r0, [r2, #836]	; 0x344
	if (counter_sub(prev_val, now) == 1) {
     f7a:	d104      	bne.n	f86 <z_clock_set_timeout+0x72>
	z_impl_k_busy_wait(usec_to_wait);
     f7c:	200f      	movs	r0, #15
     f7e:	f003 ff31 	bl	4de4 <z_impl_k_busy_wait>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
     f82:	602e      	str	r6, [r5, #0]
     f84:	682b      	ldr	r3, [r5, #0]
     f86:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
     f8a:	4b14      	ldr	r3, [pc, #80]	; (fdc <z_clock_set_timeout+0xc8>)
     f8c:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
     return p_reg->COUNTER;
     f90:	4b0e      	ldr	r3, [pc, #56]	; (fcc <z_clock_set_timeout+0xb8>)
     f92:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
     f96:	1a22      	subs	r2, r4, r0
     f98:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
	if (diff == 1) {
     f9c:	2a01      	cmp	r2, #1
     f9e:	d104      	bne.n	faa <z_clock_set_timeout+0x96>
		handle_next_cycle_case(t);
     fa0:	f7ff ff64 	bl	e6c <handle_next_cycle_case>
     fa4:	e00b      	b.n	fbe <z_clock_set_timeout+0xaa>
		ticks = 0;
     fa6:	2000      	movs	r0, #0
     fa8:	e7ca      	b.n	f40 <z_clock_set_timeout+0x2c>
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
     faa:	f024 427f 	bic.w	r2, r4, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
     fae:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
     return p_reg->COUNTER;
     fb2:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
     fb6:	1a24      	subs	r4, r4, r0
     fb8:	3c02      	subs	r4, #2
	if (diff > MAX_CYCLES) {
     fba:	0223      	lsls	r3, r4, #8
     fbc:	d4f0      	bmi.n	fa0 <z_clock_set_timeout+0x8c>
    p_reg->INTENSET = mask;
     fbe:	f44f 3280 	mov.w	r2, #65536	; 0x10000
     fc2:	4b02      	ldr	r3, [pc, #8]	; (fcc <z_clock_set_timeout+0xb8>)
     fc4:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
	set_protected_absolute_alarm(cyc);
}
     fc8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
     fca:	bf00      	nop
     fcc:	50015000 	.word	0x50015000
     fd0:	007fffff 	.word	0x007fffff
     fd4:	200002d4 	.word	0x200002d4
     fd8:	50015140 	.word	0x50015140
     fdc:	e000e100 	.word	0xe000e100

00000fe0 <z_clock_elapsed>:
	__asm__ volatile(
     fe0:	f04f 0220 	mov.w	r2, #32
     fe4:	f3ef 8311 	mrs	r3, BASEPRI
     fe8:	f382 8811 	msr	BASEPRI, r2
     fec:	f3bf 8f6f 	isb	sy
     return p_reg->COUNTER;
     ff0:	4a06      	ldr	r2, [pc, #24]	; (100c <z_clock_elapsed+0x2c>)
     ff2:	f8d2 0504 	ldr.w	r0, [r2, #1284]	; 0x504
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return 0;
	}

	k_spinlock_key_t key = k_spin_lock(&lock);
	uint32_t ret = counter_sub(counter(), last_count) / CYC_PER_TICK;
     ff6:	4a06      	ldr	r2, [pc, #24]	; (1010 <z_clock_elapsed+0x30>)
	return (a - b) & COUNTER_MAX;
     ff8:	6812      	ldr	r2, [r2, #0]
     ffa:	1a80      	subs	r0, r0, r2
     ffc:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	__asm__ volatile(
    1000:	f383 8811 	msr	BASEPRI, r3
    1004:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&lock, key);
	return ret;
}
    1008:	4770      	bx	lr
    100a:	bf00      	nop
    100c:	50015000 	.word	0x50015000
    1010:	200002d4 	.word	0x200002d4

00001014 <config_regions>:
}
#endif /* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS */


static void config_regions(bool ram, size_t start, size_t end, uint32_t perm)
{
    1014:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
	const size_t region_size = ram ? RAM_SECURE_ATTRIBUTION_REGION_SIZE
					: FLASH_SECURE_ATTRIBUTION_REGION_SIZE;
    1016:	2800      	cmp	r0, #0
{
    1018:	461c      	mov	r4, r3

	for (size_t i = start; i < end; i++) {
    101a:	460d      	mov	r5, r1
					: FLASH_SECURE_ATTRIBUTION_REGION_SIZE;
    101c:	bf14      	ite	ne
    101e:	f44f 5300 	movne.w	r3, #8192	; 0x2000
    1022:	f44f 4300 	moveq.w	r3, #32768	; 0x8000
	for (size_t i = start; i < end; i++) {
    1026:	4e20      	ldr	r6, [pc, #128]	; (10a8 <config_regions+0x94>)
    1028:	4295      	cmp	r5, r2
    102a:	d332      	bcc.n	1092 <config_regions+0x7e>
		} else {
			NRF_SPU->FLASHREGION[i].PERM = perm;
		}
	}

	PRINT("%02u %02u 0x%05x 0x%05x \t", start, end - 1,
    102c:	fb02 f003 	mul.w	r0, r2, r3
    1030:	3a01      	subs	r2, #1
    1032:	434b      	muls	r3, r1
    1034:	9000      	str	r0, [sp, #0]
    1036:	481d      	ldr	r0, [pc, #116]	; (10ac <config_regions+0x98>)
    1038:	f003 f9e8 	bl	440c <printk>
				region_size * start, region_size * end);
	PRINT("%s", perm & (ram ? SRAM_SECURE : FLASH_SECURE) ? "Secure\t\t" :
    103c:	4b1c      	ldr	r3, [pc, #112]	; (10b0 <config_regions+0x9c>)
    103e:	f014 0f10 	tst.w	r4, #16
    1042:	491c      	ldr	r1, [pc, #112]	; (10b4 <config_regions+0xa0>)
    1044:	481c      	ldr	r0, [pc, #112]	; (10b8 <config_regions+0xa4>)
    1046:	bf08      	it	eq
    1048:	4619      	moveq	r1, r3
    104a:	f003 f9df 	bl	440c <printk>
								"Non-Secure\t");
	PRINT("%c", perm & (ram ? SRAM_READ : FLASH_READ)  ? 'r' : '-');
    104e:	f014 0f04 	tst.w	r4, #4
    1052:	bf14      	ite	ne
    1054:	2172      	movne	r1, #114	; 0x72
    1056:	212d      	moveq	r1, #45	; 0x2d
    1058:	4818      	ldr	r0, [pc, #96]	; (10bc <config_regions+0xa8>)
    105a:	f003 f9d7 	bl	440c <printk>
	PRINT("%c", perm & (ram ? SRAM_WRITE : FLASH_WRITE) ? 'w' : '-');
    105e:	f014 0f02 	tst.w	r4, #2
    1062:	bf14      	ite	ne
    1064:	2177      	movne	r1, #119	; 0x77
    1066:	212d      	moveq	r1, #45	; 0x2d
    1068:	4814      	ldr	r0, [pc, #80]	; (10bc <config_regions+0xa8>)
    106a:	f003 f9cf 	bl	440c <printk>
	PRINT("%c", perm & (ram ? SRAM_EXEC : FLASH_EXEC)  ? 'x' : '-');
    106e:	f014 0f01 	tst.w	r4, #1
    1072:	bf0c      	ite	eq
    1074:	212d      	moveq	r1, #45	; 0x2d
    1076:	2178      	movne	r1, #120	; 0x78
    1078:	4810      	ldr	r0, [pc, #64]	; (10bc <config_regions+0xa8>)
    107a:	f003 f9c7 	bl	440c <printk>
	PRINT("%c", perm & (ram ? SRAM_LOCK : FLASH_LOCK)  ? 'l' : '-');
    107e:	216c      	movs	r1, #108	; 0x6c
    1080:	480e      	ldr	r0, [pc, #56]	; (10bc <config_regions+0xa8>)
    1082:	f003 f9c3 	bl	440c <printk>
	PRINT("\n");
    1086:	480e      	ldr	r0, [pc, #56]	; (10c0 <config_regions+0xac>)
}
    1088:	b003      	add	sp, #12
    108a:	e8bd 40f0 	ldmia.w	sp!, {r4, r5, r6, r7, lr}
	PRINT("\n");
    108e:	f003 b9bd 	b.w	440c <printk>
		if (ram) {
    1092:	b128      	cbz	r0, 10a0 <config_regions+0x8c>
			NRF_SPU->RAMREGION[i].PERM = perm;
    1094:	f505 77e0 	add.w	r7, r5, #448	; 0x1c0
			NRF_SPU->FLASHREGION[i].PERM = perm;
    1098:	f846 4027 	str.w	r4, [r6, r7, lsl #2]
	for (size_t i = start; i < end; i++) {
    109c:	3501      	adds	r5, #1
    109e:	e7c3      	b.n	1028 <config_regions+0x14>
			NRF_SPU->FLASHREGION[i].PERM = perm;
    10a0:	f505 77c0 	add.w	r7, r5, #384	; 0x180
    10a4:	e7f8      	b.n	1098 <config_regions+0x84>
    10a6:	bf00      	nop
    10a8:	50003000 	.word	0x50003000
    10ac:	00005441 	.word	0x00005441
    10b0:	00005435 	.word	0x00005435
    10b4:	0000542c 	.word	0x0000542c
    10b8:	000055c0 	.word	0x000055c0
    10bc:	0000545b 	.word	0x0000545b
    10c0:	00005796 	.word	0x00005796

000010c4 <spm_config_peripheral.constprop.0>:
		     SPU_PERIPHID_PERM_SECUREMAPPING_Split;

	return present && (usel || split);
}

static int spm_config_peripheral(uint8_t id, bool dma_present)
    10c4:	b508      	push	{r3, lr}
	 * Assign DMA capabilities and lock down the attribution.
	 *
	 * Note: the function assumes that the peripheral ID matches
	 * the IRQ line.
	 */
	NVIC_DisableIRQ(id);
    10c6:	b243      	sxtb	r3, r0
  if ((int32_t)(IRQn) >= 0)
    10c8:	2b00      	cmp	r3, #0
    10ca:	db0c      	blt.n	10e6 <spm_config_peripheral.constprop.0+0x22>
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    10cc:	2201      	movs	r2, #1
    10ce:	f000 011f 	and.w	r1, r0, #31
    10d2:	408a      	lsls	r2, r1
    10d4:	095b      	lsrs	r3, r3, #5
    10d6:	4910      	ldr	r1, [pc, #64]	; (1118 <spm_config_peripheral.constprop.0+0x54>)
    10d8:	3320      	adds	r3, #32
    10da:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    10de:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    10e2:	f3bf 8f6f 	isb	sy
	const uint32_t perm = NRF_SPU->PERIPHID[id].PERM;
    10e6:	0083      	lsls	r3, r0, #2
    10e8:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    10ec:	f503 5340 	add.w	r3, r3, #12288	; 0x3000
	if (id == NRFX_PERIPHERAL_ID_GET(NRF_GPIOTE1_NS)) {
    10f0:	2831      	cmp	r0, #49	; 0x31
	const uint32_t perm = NRF_SPU->PERIPHID[id].PERM;
    10f2:	f8d3 2800 	ldr.w	r2, [r3, #2048]	; 0x800
	if (id == NRFX_PERIPHERAL_ID_GET(NRF_GPIOTE1_NS)) {
    10f6:	d006      	beq.n	1106 <spm_config_peripheral.constprop.0+0x42>
	return present && (usel || split);
    10f8:	2a00      	cmp	r2, #0
    10fa:	da07      	bge.n	110c <spm_config_peripheral.constprop.0+0x48>
	bool usel = (perm & SPU_PERIPHID_PERM_SECUREMAPPING_Msk) ==
    10fc:	f002 0203 	and.w	r2, r2, #3
	return present && (usel || split);
    1100:	3a02      	subs	r2, #2
    1102:	2a01      	cmp	r2, #1
    1104:	d802      	bhi.n	110c <spm_config_peripheral.constprop.0+0x48>

	if (usel_or_split(id)) {
		NRF_SPU->PERIPHID[id].PERM = PERIPH_PRESENT | PERIPH_NONSEC |
    1106:	4a05      	ldr	r2, [pc, #20]	; (111c <spm_config_peripheral.constprop.0+0x58>)
    1108:	f8c3 2800 	str.w	r2, [r3, #2048]	; 0x800
	}

	/* Even for non-present peripherals we force IRQs to be routed
	 * to Non-Secure state.
	 */
	irq_target_state_set(id, IRQ_TARGET_STATE_NON_SECURE);
    110c:	2101      	movs	r1, #1
    110e:	f003 fc0c 	bl	492a <irq_target_state_set>
	return 0;
}
    1112:	2000      	movs	r0, #0
    1114:	bd08      	pop	{r3, pc}
    1116:	bf00      	nop
    1118:	e000e100 	.word	0xe000e100
    111c:	80000100 	.word	0x80000100

00001120 <spm_jump>:
	tz_nonsecure_fpu_access_enable();
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */
}

void spm_jump(void)
{
    1120:	b530      	push	{r4, r5, lr}
	 * The assumption is that the MSP is located at VTOR_NS[0].
	 */
	uint32_t *vtor_ns = (uint32_t *)NON_SECURE_APP_ADDRESS;

	PRINT("SPM: NS image at 0x%x\n", (uint32_t)vtor_ns);
	PRINT("SPM: NS MSP at 0x%x\n", vtor_ns[0]);
    1122:	f44f 4440 	mov.w	r4, #49152	; 0xc000
	PRINT("SPM: NS reset vector at 0x%x\n", vtor_ns[1]);
    1126:	f24c 0504 	movw	r5, #49156	; 0xc004
{
    112a:	b085      	sub	sp, #20
	PRINT("SPM: NS image at 0x%x\n", (uint32_t)vtor_ns);
    112c:	f44f 4140 	mov.w	r1, #49152	; 0xc000
    1130:	482c      	ldr	r0, [pc, #176]	; (11e4 <spm_jump+0xc4>)
    1132:	f003 f96b 	bl	440c <printk>
	PRINT("SPM: NS MSP at 0x%x\n", vtor_ns[0]);
    1136:	6821      	ldr	r1, [r4, #0]
    1138:	482b      	ldr	r0, [pc, #172]	; (11e8 <spm_jump+0xc8>)
    113a:	f003 f967 	bl	440c <printk>
	PRINT("SPM: NS reset vector at 0x%x\n", vtor_ns[1]);
    113e:	6829      	ldr	r1, [r5, #0]
    1140:	482a      	ldr	r0, [pc, #168]	; (11ec <spm_jump+0xcc>)
    1142:	f003 f963 	bl	440c <printk>

	/* Configure Non-Secure stack */
	tz_nonsecure_setup_conf_t spm_ns_conf = {
    1146:	2210      	movs	r2, #16
    1148:	2100      	movs	r1, #0
    114a:	4668      	mov	r0, sp
    114c:	f003 fcb4 	bl	4ab8 <memset>
		.vtor_ns = (uint32_t)vtor_ns,
		.msp_ns = vtor_ns[0],
    1150:	6823      	ldr	r3, [r4, #0]
	tz_nonsecure_state_setup(spm_ns_conf);
    1152:	4668      	mov	r0, sp
	tz_nonsecure_setup_conf_t spm_ns_conf = {
    1154:	9300      	str	r3, [sp, #0]
    1156:	9402      	str	r4, [sp, #8]
	tz_nonsecure_state_setup(spm_ns_conf);
    1158:	f000 fe74 	bl	1e44 <tz_nonsecure_state_setup>
	tz_nonsecure_exception_prio_config(1);
    115c:	2001      	movs	r0, #1
    115e:	f000 fea1 	bl	1ea4 <tz_nonsecure_exception_prio_config>
	tz_nbanked_exception_target_state_set(0);
    1162:	2000      	movs	r0, #0
    1164:	f000 fe8a 	bl	1e7c <tz_nbanked_exception_target_state_set>
	tz_nonsecure_system_reset_req_block(
    1168:	2000      	movs	r0, #0
    116a:	f000 feaf 	bl	1ecc <tz_nonsecure_system_reset_req_block>
	tz_sau_configure(0, 1);
    116e:	2101      	movs	r1, #1
    1170:	2000      	movs	r0, #0
    1172:	f000 fec9 	bl	1f08 <tz_sau_configure>
	tz_nonsecure_fpu_access_enable();
    1176:	f000 febd 	bl	1ef4 <tz_nonsecure_fpu_access_enable>

	spm_configure_ns(&spm_ns_conf);

	/* Generate function pointer for Non-Secure function call. */
	TZ_NONSECURE_FUNC_PTR_DECLARE(reset_ns);
	reset_ns = TZ_NONSECURE_FUNC_PTR_CREATE(vtor_ns[1]);
    117a:	682c      	ldr	r4, [r5, #0]

	if (TZ_NONSECURE_FUNC_PTR_IS_NS(reset_ns)) {
		PRINT("SPM: prepare to jump to Non-Secure image.\n");
    117c:	481c      	ldr	r0, [pc, #112]	; (11f0 <spm_jump+0xd0>)
    117e:	f003 f945 	bl	440c <printk>
		/* Note: Move UARTE0 before jumping, if it is
		 * to be used on the Non-Secure domain.
		 */

		/* Configure UARTE0 as non-secure */
		spm_config_peripheral(
    1182:	2008      	movs	r0, #8
    1184:	f7ff ff9e 	bl	10c4 <spm_config_peripheral.constprop.0>
	reset_ns = TZ_NONSECURE_FUNC_PTR_CREATE(vtor_ns[1]);
    1188:	f024 0401 	bic.w	r4, r4, #1
  __ASM volatile ("dsb 0xF":::"memory");
    118c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1190:	f3bf 8f6f 	isb	sy

		__DSB();
		__ISB();

		/* Jump to Non-Secure firmware */
		reset_ns();
    1194:	0864      	lsrs	r4, r4, #1
    1196:	0064      	lsls	r4, r4, #1
    1198:	4620      	mov	r0, r4
    119a:	4621      	mov	r1, r4
    119c:	4622      	mov	r2, r4
    119e:	4623      	mov	r3, r4
    11a0:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    11a4:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    11a8:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    11ac:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    11b0:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    11b4:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    11b8:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    11bc:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    11c0:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    11c4:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    11c8:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    11cc:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    11d0:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    11d4:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    11d8:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    11dc:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    11e0:	f7ff f9a6 	bl	530 <__gnu_cmse_nonsecure_call>

		CODE_UNREACHABLE;
    11e4:	0000545e 	.word	0x0000545e
    11e8:	00005475 	.word	0x00005475
    11ec:	0000548a 	.word	0x0000548a
    11f0:	000054a8 	.word	0x000054a8

000011f4 <spm_config>:
		      (uint32_t)reset_ns);
	}
}

void spm_config(void)
{
    11f4:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	PRINT("Flash regions\t\tDomain\t\tPermissions\n");
    11f8:	483b      	ldr	r0, [pc, #236]	; (12e8 <spm_config+0xf4>)
    11fa:	f003 f907 	bl	440c <printk>
	config_regions(false, 0, NON_SECURE_FLASH_REGION_INDEX,
    11fe:	2100      	movs	r1, #0
    1200:	f240 1317 	movw	r3, #279	; 0x117
    1204:	4608      	mov	r0, r1
    1206:	2201      	movs	r2, #1
    1208:	f7ff ff04 	bl	1014 <config_regions>
	config_regions(false, NON_SECURE_FLASH_REGION_INDEX,
    120c:	f240 1307 	movw	r3, #263	; 0x107
    1210:	2220      	movs	r2, #32
    1212:	2101      	movs	r1, #1
    1214:	2000      	movs	r0, #0
    1216:	f7ff fefd 	bl	1014 <config_regions>
	PRINT("\n");
    121a:	4834      	ldr	r0, [pc, #208]	; (12ec <spm_config+0xf8>)
    121c:	f003 f8f6 	bl	440c <printk>
	uint32_t nsc_size = FLASH_NSC_SIZE_FROM_ADDR(__sg_start);
    1220:	4b33      	ldr	r3, [pc, #204]	; (12f0 <spm_config+0xfc>)
                                            bool               lock_conf)
{
    NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].REGION & SPU_FLASHNSC_REGION_LOCK_Msk));
    NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].SIZE & SPU_FLASHNSC_SIZE_LOCK_Msk));

    p_reg->FLASHNSC[flash_nsc_id].REGION = (uint32_t)region_number |
    1222:	4a34      	ldr	r2, [pc, #208]	; (12f4 <spm_config+0x100>)
    1224:	f3c3 31c4 	ubfx	r1, r3, #15, #5
    1228:	f3c3 030e 	ubfx	r3, r3, #0, #15
    122c:	f5c3 4300 	rsb	r3, r3, #32768	; 0x8000
        (lock_conf ? SPU_FLASHNSC_REGION_LOCK_Msk : 0);
    p_reg->FLASHNSC[flash_nsc_id].SIZE = (uint32_t)flash_nsc_size |
    1230:	f3c3 1343 	ubfx	r3, r3, #5, #4
    p_reg->FLASHNSC[flash_nsc_id].REGION = (uint32_t)region_number |
    1234:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->FLASHNSC[flash_nsc_id].SIZE = (uint32_t)flash_nsc_size |
    1238:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
	PRINT("Non-secure callable region 0 placed in flash region %d with size %d.\n",
    123c:	f8d2 1500 	ldr.w	r1, [r2, #1280]	; 0x500
    1240:	f8d2 2504 	ldr.w	r2, [r2, #1284]	; 0x504
    1244:	482c      	ldr	r0, [pc, #176]	; (12f8 <spm_config+0x104>)
    1246:	0152      	lsls	r2, r2, #5
    1248:	f003 f8e0 	bl	440c <printk>
	PRINT("\n");
    124c:	4827      	ldr	r0, [pc, #156]	; (12ec <spm_config+0xf8>)
    124e:	f003 f8dd 	bl	440c <printk>
	int err = spm_secure_services_init();
    1252:	f003 fb18 	bl	4886 <spm_secure_services_init>
	if (err != 0) {
    1256:	4601      	mov	r1, r0
    1258:	b110      	cbz	r0, 1260 <spm_config+0x6c>
		PRINT("Could not initialize secure services (err %d).\n", err);
    125a:	4828      	ldr	r0, [pc, #160]	; (12fc <spm_config+0x108>)
    125c:	f003 f8d6 	bl	440c <printk>
	NRF_SPU->DPPI[0].PERM = mask;
    1260:	2400      	movs	r4, #0
	PRINT("SRAM region\t\tDomain\t\tPermissions\n");
    1262:	4827      	ldr	r0, [pc, #156]	; (1300 <spm_config+0x10c>)
    1264:	f003 f8d2 	bl	440c <printk>
	config_regions(true, 0, NON_SECURE_RAM_REGION_INDEX,
    1268:	f240 1317 	movw	r3, #279	; 0x117
    126c:	2208      	movs	r2, #8
    126e:	2100      	movs	r1, #0
    1270:	2001      	movs	r0, #1
    1272:	f7ff fecf 	bl	1014 <config_regions>
	NRF_SPU->DPPI[0].PERM = mask;
    1276:	4d1f      	ldr	r5, [pc, #124]	; (12f4 <spm_config+0x100>)
	config_regions(true, NON_SECURE_RAM_REGION_INDEX,
    1278:	f240 1307 	movw	r3, #263	; 0x107
    127c:	2220      	movs	r2, #32
    127e:	2108      	movs	r1, #8
    1280:	2001      	movs	r0, #1
    1282:	f7ff fec7 	bl	1014 <config_regions>
	PRINT("\n");
    1286:	4819      	ldr	r0, [pc, #100]	; (12ec <spm_config+0xf8>)
    1288:	f003 f8c0 	bl	440c <printk>
	NRF_SPU->DPPI[0].PERM = mask;
    128c:	f8c5 4480 	str.w	r4, [r5, #1152]	; 0x480
	PRINT("Peripheral\t\tDomain\t\tStatus\n");
    1290:	481c      	ldr	r0, [pc, #112]	; (1304 <spm_config+0x110>)
    1292:	f003 f8bb 	bl	440c <printk>
		PRINT("%02u %-21s%s", i, periph[i].name,
    1296:	4f1c      	ldr	r7, [pc, #112]	; (1308 <spm_config+0x114>)
		NRF_SPU->GPIOPORT[0].PERM = 0;
    1298:	f8c5 44c0 	str.w	r4, [r5, #1216]	; 0x4c0
		PRINT("%02u %-21s%s", i, periph[i].name,
    129c:	f8df 807c 	ldr.w	r8, [pc, #124]	; 131c <spm_config+0x128>
    12a0:	4d1a      	ldr	r5, [pc, #104]	; (130c <spm_config+0x118>)
    12a2:	f8df 907c 	ldr.w	r9, [pc, #124]	; 1320 <spm_config+0x12c>
    12a6:	796e      	ldrb	r6, [r5, #5]
    12a8:	4621      	mov	r1, r4
    12aa:	2e00      	cmp	r6, #0
    12ac:	bf14      	ite	ne
    12ae:	463b      	movne	r3, r7
    12b0:	4643      	moveq	r3, r8
    12b2:	4648      	mov	r0, r9
    12b4:	682a      	ldr	r2, [r5, #0]
    12b6:	f003 f8a9 	bl	440c <printk>
		if (!periph[i].nonsecure) {
    12ba:	b966      	cbnz	r6, 12d6 <spm_config+0xe2>
			PRINT("\tSKIP\n");
    12bc:	4814      	ldr	r0, [pc, #80]	; (1310 <spm_config+0x11c>)
	for (size_t i = 0; i < ARRAY_SIZE(periph); i++) {
    12be:	3401      	adds	r4, #1
			PRINT("\tOK\n");
    12c0:	f003 f8a4 	bl	440c <printk>
	for (size_t i = 0; i < ARRAY_SIZE(periph); i++) {
    12c4:	2c1a      	cmp	r4, #26
    12c6:	f105 0508 	add.w	r5, r5, #8
    12ca:	d1ec      	bne.n	12a6 <spm_config+0xb2>
	PRINT("\n");
    12cc:	4807      	ldr	r0, [pc, #28]	; (12ec <spm_config+0xf8>)
	spm_config_flash();
	spm_config_sram();
	spm_config_peripherals();
}
    12ce:	e8bd 43f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	PRINT("\n");
    12d2:	f003 b89b 	b.w	440c <printk>
		err = spm_config_peripheral(periph[i].id, false);
    12d6:	7928      	ldrb	r0, [r5, #4]
    12d8:	f7ff fef4 	bl	10c4 <spm_config_peripheral.constprop.0>
		if (err) {
    12dc:	b108      	cbz	r0, 12e2 <spm_config+0xee>
			PRINT("\tERROR\n");
    12de:	480d      	ldr	r0, [pc, #52]	; (1314 <spm_config+0x120>)
    12e0:	e7ed      	b.n	12be <spm_config+0xca>
			PRINT("\tOK\n");
    12e2:	480d      	ldr	r0, [pc, #52]	; (1318 <spm_config+0x124>)
    12e4:	e7eb      	b.n	12be <spm_config+0xca>
    12e6:	bf00      	nop
    12e8:	000054de 	.word	0x000054de
    12ec:	00005796 	.word	0x00005796
    12f0:	00007fe0 	.word	0x00007fe0
    12f4:	50003000 	.word	0x50003000
    12f8:	00005502 	.word	0x00005502
    12fc:	00005548 	.word	0x00005548
    1300:	00005578 	.word	0x00005578
    1304:	0000559a 	.word	0x0000559a
    1308:	000054d3 	.word	0x000054d3
    130c:	00005178 	.word	0x00005178
    1310:	000055c3 	.word	0x000055c3
    1314:	000055ca 	.word	0x000055ca
    1318:	000055d2 	.word	0x000055d2
    131c:	00005439 	.word	0x00005439
    1320:	000055b6 	.word	0x000055b6

00001324 <__acle_se_spm_request_read_nse>:
};


__TZ_NONSECURE_ENTRY_FUNC
int spm_request_read_nse(void *destination, uint32_t addr, size_t len)
{
    1324:	b510      	push	{r4, lr}
		 .size = FICR_PUBLIC_SIZE},
		{.start = FICR_RESTRICTED_ADDR,
		 .size = FICR_RESTRICTED_SIZE},
	};

	if (destination == NULL || len <= 0) {
    1326:	2800      	cmp	r0, #0
    1328:	d04b      	beq.n	13c2 <__acle_se_spm_request_read_nse+0x9e>
    132a:	2a00      	cmp	r2, #0
    132c:	d049      	beq.n	13c2 <__acle_se_spm_request_read_nse+0x9e>

	for (size_t i = 0; i < ARRAY_SIZE(ranges); i++) {
		uint32_t start = ranges[i].start;
		uint32_t size = ranges[i].size;

		if (addr >= start && addr + len <= start + size) {
    132e:	4b26      	ldr	r3, [pc, #152]	; (13c8 <__acle_se_spm_request_read_nse+0xa4>)
    1330:	4299      	cmp	r1, r3
    1332:	d93c      	bls.n	13ae <__acle_se_spm_request_read_nse+0x8a>
    1334:	1854      	adds	r4, r2, r1
    1336:	f603 231d 	addw	r3, r3, #2589	; 0xa1d
    133a:	429c      	cmp	r4, r3
    133c:	d83a      	bhi.n	13b4 <__acle_se_spm_request_read_nse+0x90>
			memcpy(destination, (const void *)addr, len);
    133e:	f003 fb90 	bl	4a62 <memcpy>
			return 0;
    1342:	2000      	movs	r0, #0
		}
	}

	return -EPERM;
}
    1344:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    1348:	4671      	mov	r1, lr
    134a:	4672      	mov	r2, lr
    134c:	4673      	mov	r3, lr
    134e:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    1352:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    1356:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    135a:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    135e:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    1362:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    1366:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    136a:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    136e:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    1372:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    1376:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    137a:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    137e:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    1382:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    1386:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    138a:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    138e:	f38e 8c00 	msr	CPSR_fs, lr
    1392:	b410      	push	{r4}
    1394:	eef1 ca10 	vmrs	ip, fpscr
    1398:	f64f 7460 	movw	r4, #65376	; 0xff60
    139c:	f6c0 74ff 	movt	r4, #4095	; 0xfff
    13a0:	ea0c 0c04 	and.w	ip, ip, r4
    13a4:	eee1 ca10 	vmsr	fpscr, ip
    13a8:	bc10      	pop	{r4}
    13aa:	46f4      	mov	ip, lr
    13ac:	4774      	bxns	lr
		if (addr >= start && addr + len <= start + size) {
    13ae:	4b07      	ldr	r3, [pc, #28]	; (13cc <__acle_se_spm_request_read_nse+0xa8>)
    13b0:	4299      	cmp	r1, r3
    13b2:	d903      	bls.n	13bc <__acle_se_spm_request_read_nse+0x98>
    13b4:	4b06      	ldr	r3, [pc, #24]	; (13d0 <__acle_se_spm_request_read_nse+0xac>)
    13b6:	1854      	adds	r4, r2, r1
    13b8:	429c      	cmp	r4, r3
    13ba:	d9c0      	bls.n	133e <__acle_se_spm_request_read_nse+0x1a>
	return -EPERM;
    13bc:	f04f 30ff 	mov.w	r0, #4294967295
    13c0:	e7c0      	b.n	1344 <__acle_se_spm_request_read_nse+0x20>
		return -EINVAL;
    13c2:	f06f 0015 	mvn.w	r0, #21
    13c6:	e7bd      	b.n	1344 <__acle_se_spm_request_read_nse+0x20>
    13c8:	00ff0203 	.word	0x00ff0203
    13cc:	00ff012f 	.word	0x00ff012f
    13d0:	00ff0138 	.word	0x00ff0138

000013d4 <__acle_se_spm_firmware_info_nse>:


#ifdef CONFIG_SPM_SERVICE_FIND_FIRMWARE_INFO
__TZ_NONSECURE_ENTRY_FUNC
int spm_firmware_info_nse(uint32_t fw_address, struct fw_info *info)
{
    13d4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    13d8:	4681      	mov	r9, r0
	const struct fw_info *tmp_info;

	if (info == NULL) {
    13da:	460e      	mov	r6, r1
{
    13dc:	b085      	sub	sp, #20
	if (info == NULL) {
    13de:	2900      	cmp	r1, #0
    13e0:	d054      	beq.n	148c <__acle_se_spm_firmware_info_nse+0xb8>
 */
static inline const struct fw_info *fw_info_find(uint32_t firmware_address)
{
	const struct fw_info *finfo;

	for (uint32_t i = 0; i < FW_INFO_OFFSET_COUNT; i++) {
    13e2:	f04f 0800 	mov.w	r8, #0
    13e6:	f8df b0b8 	ldr.w	fp, [pc, #184]	; 14a0 <__acle_se_spm_firmware_info_nse+0xcc>
	const uint32_t fw_info_magic[] = {FIRMWARE_INFO_MAGIC};
    13ea:	f8df a0b8 	ldr.w	sl, [pc, #184]	; 14a4 <__acle_se_spm_firmware_info_nse+0xd0>
    13ee:	af01      	add	r7, sp, #4
		finfo = fw_info_check(firmware_address +
						fw_info_allowed_offsets[i]);
    13f0:	f85b 5b04 	ldr.w	r5, [fp], #4
	const uint32_t fw_info_magic[] = {FIRMWARE_INFO_MAGIC};
    13f4:	e89a 0007 	ldmia.w	sl, {r0, r1, r2}
		finfo = fw_info_check(firmware_address +
    13f8:	444d      	add	r5, r9
	const uint32_t fw_info_magic[] = {FIRMWARE_INFO_MAGIC};
    13fa:	e887 0007 	stmia.w	r7, {r0, r1, r2}
	if (memcmp(finfo->magic, fw_info_magic, CONFIG_FW_INFO_MAGIC_LEN)
    13fe:	220c      	movs	r2, #12
    1400:	4639      	mov	r1, r7
    1402:	4628      	mov	r0, r5
    1404:	f003 fb06 	bl	4a14 <memcmp>
    1408:	4604      	mov	r4, r0
    140a:	b908      	cbnz	r0, 1410 <__acle_se_spm_firmware_info_nse+0x3c>
		if (finfo) {
    140c:	2d00      	cmp	r5, #0
    140e:	d140      	bne.n	1492 <__acle_se_spm_firmware_info_nse+0xbe>
	for (uint32_t i = 0; i < FW_INFO_OFFSET_COUNT; i++) {
    1410:	f108 0801 	add.w	r8, r8, #1
    1414:	f1b8 0f05 	cmp.w	r8, #5
    1418:	d1ea      	bne.n	13f0 <__acle_se_spm_firmware_info_nse+0x1c>
	if (tmp_info != NULL) {
		memcpy(info, tmp_info, sizeof(*tmp_info));
		return 0;
	}

	return -EFAULT;
    141a:	f06f 040d 	mvn.w	r4, #13
}
    141e:	4620      	mov	r0, r4
    1420:	b005      	add	sp, #20
    1422:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    1426:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    142a:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    142e:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    1432:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    1436:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    143a:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    143e:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    1442:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    1446:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    144a:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    144e:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    1452:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    1456:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    145a:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    145e:	e8bd 4ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1462:	4671      	mov	r1, lr
    1464:	4672      	mov	r2, lr
    1466:	4673      	mov	r3, lr
    1468:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    146c:	f38e 8c00 	msr	CPSR_fs, lr
    1470:	b410      	push	{r4}
    1472:	eef1 ca10 	vmrs	ip, fpscr
    1476:	f64f 7460 	movw	r4, #65376	; 0xff60
    147a:	f6c0 74ff 	movt	r4, #4095	; 0xfff
    147e:	ea0c 0c04 	and.w	ip, ip, r4
    1482:	eee1 ca10 	vmsr	fpscr, ip
    1486:	bc10      	pop	{r4}
    1488:	46f4      	mov	ip, lr
    148a:	4774      	bxns	lr
		return -EINVAL;
    148c:	f06f 0415 	mvn.w	r4, #21
    1490:	e7c5      	b.n	141e <__acle_se_spm_firmware_info_nse+0x4a>
		memcpy(info, tmp_info, sizeof(*tmp_info));
    1492:	223c      	movs	r2, #60	; 0x3c
    1494:	4629      	mov	r1, r5
    1496:	4630      	mov	r0, r6
    1498:	f003 fae3 	bl	4a62 <memcpy>
		return 0;
    149c:	e7bf      	b.n	141e <__acle_se_spm_firmware_info_nse+0x4a>
    149e:	bf00      	nop
    14a0:	00005248 	.word	0x00005248
    14a4:	000050f0 	.word	0x000050f0

000014a8 <nrf_cc3xx_platform_abort_init>:

/** @brief Function to initialize the nrf_cc3xx_platform abort APIs.
 */
void nrf_cc3xx_platform_abort_init(void)
{
	nrf_cc3xx_platform_set_abort(&apis);
    14a8:	4801      	ldr	r0, [pc, #4]	; (14b0 <nrf_cc3xx_platform_abort_init+0x8>)
    14aa:	f002 ba75 	b.w	3998 <nrf_cc3xx_platform_set_abort>
    14ae:	bf00      	nop
    14b0:	0000525c 	.word	0x0000525c

000014b4 <mutex_unlock_platform>:
}


/** @brief Static function to unlock a mutex
 */
static int32_t mutex_unlock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    14b4:	b508      	push	{r3, lr}
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
    14b6:	b130      	cbz	r0, 14c6 <mutex_unlock_platform+0x12>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    /* Ensure that the mutex has been initialized */
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    14b8:	6843      	ldr	r3, [r0, #4]
    14ba:	b13b      	cbz	r3, 14cc <mutex_unlock_platform+0x18>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    }

    p_mutex = (struct k_mutex *)mutex->mutex;
    14bc:	6800      	ldr	r0, [r0, #0]
	return z_impl_k_mutex_unlock(mutex);
    14be:	f001 fa7d 	bl	29bc <z_impl_k_mutex_unlock>

    k_mutex_unlock(p_mutex);
    return NRF_CC3XX_PLATFORM_SUCCESS;
    14c2:	2000      	movs	r0, #0
}
    14c4:	bd08      	pop	{r3, pc}
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    14c6:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    14ca:	e7fb      	b.n	14c4 <mutex_unlock_platform+0x10>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    14cc:	4800      	ldr	r0, [pc, #0]	; (14d0 <mutex_unlock_platform+0x1c>)
    14ce:	e7f9      	b.n	14c4 <mutex_unlock_platform+0x10>
    14d0:	ffff8fea 	.word	0xffff8fea

000014d4 <mutex_free_platform>:
static void mutex_free_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    14d4:	b510      	push	{r4, lr}
    if (mutex == NULL) {
    14d6:	4604      	mov	r4, r0
    14d8:	b918      	cbnz	r0, 14e2 <mutex_free_platform+0xe>
        platform_abort_apis.abort_fn(
    14da:	4b0b      	ldr	r3, [pc, #44]	; (1508 <mutex_free_platform+0x34>)
    14dc:	480b      	ldr	r0, [pc, #44]	; (150c <mutex_free_platform+0x38>)
    14de:	685b      	ldr	r3, [r3, #4]
    14e0:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    14e2:	6861      	ldr	r1, [r4, #4]
    14e4:	b159      	cbz	r1, 14fe <mutex_free_platform+0x2a>
    if ((mutex->flags & NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED) != 0) {
    14e6:	f011 0102 	ands.w	r1, r1, #2
    14ea:	6820      	ldr	r0, [r4, #0]
    14ec:	d008      	beq.n	1500 <mutex_free_platform+0x2c>
        k_mem_slab_free(&mutex_slab, mutex->mutex);
    14ee:	4601      	mov	r1, r0
    14f0:	4807      	ldr	r0, [pc, #28]	; (1510 <mutex_free_platform+0x3c>)
    14f2:	f001 f9c1 	bl	2878 <k_mem_slab_free>
        mutex->mutex = NULL;
    14f6:	2300      	movs	r3, #0
    14f8:	6023      	str	r3, [r4, #0]
    mutex->flags = NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID;
    14fa:	2300      	movs	r3, #0
    14fc:	6063      	str	r3, [r4, #4]
}
    14fe:	bd10      	pop	{r4, pc}
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    1500:	2214      	movs	r2, #20
    1502:	f003 fad9 	bl	4ab8 <memset>
    1506:	e7f8      	b.n	14fa <mutex_free_platform+0x26>
    1508:	20000070 	.word	0x20000070
    150c:	000056d3 	.word	0x000056d3
    1510:	200002d8 	.word	0x200002d8

00001514 <mutex_init_platform>:
static void mutex_init_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1514:	b510      	push	{r4, lr}
    if (mutex == NULL) {
    1516:	4604      	mov	r4, r0
    1518:	b918      	cbnz	r0, 1522 <mutex_init_platform+0xe>
        platform_abort_apis.abort_fn(
    151a:	4b14      	ldr	r3, [pc, #80]	; (156c <mutex_init_platform+0x58>)
    151c:	4814      	ldr	r0, [pc, #80]	; (1570 <mutex_init_platform+0x5c>)
    151e:	685b      	ldr	r3, [r3, #4]
    1520:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID &&
    1522:	6863      	ldr	r3, [r4, #4]
    1524:	b9cb      	cbnz	r3, 155a <mutex_init_platform+0x46>
    1526:	6823      	ldr	r3, [r4, #0]
    1528:	b9bb      	cbnz	r3, 155a <mutex_init_platform+0x46>
        ret = k_mem_slab_alloc(&mutex_slab, &mutex->mutex, K_FOREVER);
    152a:	f04f 32ff 	mov.w	r2, #4294967295
    152e:	f04f 33ff 	mov.w	r3, #4294967295
    1532:	4621      	mov	r1, r4
    1534:	480f      	ldr	r0, [pc, #60]	; (1574 <mutex_init_platform+0x60>)
    1536:	f001 f96d 	bl	2814 <k_mem_slab_alloc>
        if(ret != 0 || mutex->mutex == NULL)
    153a:	b908      	cbnz	r0, 1540 <mutex_init_platform+0x2c>
    153c:	6823      	ldr	r3, [r4, #0]
    153e:	b91b      	cbnz	r3, 1548 <mutex_init_platform+0x34>
            platform_abort_apis.abort_fn(
    1540:	4b0a      	ldr	r3, [pc, #40]	; (156c <mutex_init_platform+0x58>)
    1542:	480d      	ldr	r0, [pc, #52]	; (1578 <mutex_init_platform+0x64>)
    1544:	685b      	ldr	r3, [r3, #4]
    1546:	4798      	blx	r3
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    1548:	2214      	movs	r2, #20
    154a:	2100      	movs	r1, #0
    154c:	6820      	ldr	r0, [r4, #0]
    154e:	f003 fab3 	bl	4ab8 <memset>
        mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED;
    1552:	6863      	ldr	r3, [r4, #4]
    1554:	f043 0302 	orr.w	r3, r3, #2
    1558:	6063      	str	r3, [r4, #4]
    p_mutex = (struct k_mutex *)mutex->mutex;
    155a:	6820      	ldr	r0, [r4, #0]
	return z_impl_k_mutex_init(mutex);
    155c:	f003 fb89 	bl	4c72 <z_impl_k_mutex_init>
    mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_VALID;
    1560:	6863      	ldr	r3, [r4, #4]
    1562:	f043 0301 	orr.w	r3, r3, #1
    1566:	6063      	str	r3, [r4, #4]
}
    1568:	bd10      	pop	{r4, pc}
    156a:	bf00      	nop
    156c:	20000070 	.word	0x20000070
    1570:	000056d3 	.word	0x000056d3
    1574:	200002d8 	.word	0x200002d8
    1578:	000056f9 	.word	0x000056f9

0000157c <mutex_lock_platform>:
static int32_t mutex_lock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    157c:	b508      	push	{r3, lr}
    if(mutex == NULL) {
    157e:	b168      	cbz	r0, 159c <mutex_lock_platform+0x20>
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1580:	6843      	ldr	r3, [r0, #4]
    1582:	b173      	cbz	r3, 15a2 <mutex_lock_platform+0x26>
    p_mutex = (struct k_mutex *)mutex->mutex;
    1584:	6800      	ldr	r0, [r0, #0]
	return z_impl_k_mutex_lock(mutex, timeout);
    1586:	f04f 33ff 	mov.w	r3, #4294967295
    158a:	f04f 32ff 	mov.w	r2, #4294967295
    158e:	f001 f99d 	bl	28cc <z_impl_k_mutex_lock>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_FAILED;
    1592:	4b05      	ldr	r3, [pc, #20]	; (15a8 <mutex_lock_platform+0x2c>)
    if (ret == 0) {
    1594:	2800      	cmp	r0, #0
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_FAILED;
    1596:	bf18      	it	ne
    1598:	4618      	movne	r0, r3
}
    159a:	bd08      	pop	{r3, pc}
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    159c:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    15a0:	e7fb      	b.n	159a <mutex_lock_platform+0x1e>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    15a2:	4802      	ldr	r0, [pc, #8]	; (15ac <mutex_lock_platform+0x30>)
    15a4:	e7f9      	b.n	159a <mutex_lock_platform+0x1e>
    15a6:	bf00      	nop
    15a8:	ffff8fe9 	.word	0xffff8fe9
    15ac:	ffff8fea 	.word	0xffff8fea

000015b0 <nrf_cc3xx_platform_mutex_init>:
};

/** @brief Function to initialize the nrf_cc3xx_platform mutex APIs
 */
void nrf_cc3xx_platform_mutex_init(void)
{
    15b0:	b508      	push	{r3, lr}
    k_mem_slab_init(&mutex_slab,
    15b2:	4906      	ldr	r1, [pc, #24]	; (15cc <nrf_cc3xx_platform_mutex_init+0x1c>)
    15b4:	2340      	movs	r3, #64	; 0x40
    15b6:	2214      	movs	r2, #20
    15b8:	4805      	ldr	r0, [pc, #20]	; (15d0 <nrf_cc3xx_platform_mutex_init+0x20>)
    15ba:	f003 fb3f 	bl	4c3c <k_mem_slab_init>
            mutex_slab_buffer,
            sizeof(struct k_mutex),
            NUM_MUTEXES);

    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
}
    15be:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
    15c2:	4904      	ldr	r1, [pc, #16]	; (15d4 <nrf_cc3xx_platform_mutex_init+0x24>)
    15c4:	4804      	ldr	r0, [pc, #16]	; (15d8 <nrf_cc3xx_platform_mutex_init+0x28>)
    15c6:	f002 ba39 	b.w	3a3c <nrf_cc3xx_platform_set_mutexes>
    15ca:	bf00      	nop
    15cc:	200002f4 	.word	0x200002f4
    15d0:	200002d8 	.word	0x200002d8
    15d4:	00005274 	.word	0x00005274
    15d8:	00005264 	.word	0x00005264

000015dc <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    15dc:	4a09      	ldr	r2, [pc, #36]	; (1604 <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    15de:	490a      	ldr	r1, [pc, #40]	; (1608 <arch_swap+0x2c>)
	_current->arch.basepri = key;
    15e0:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    15e2:	6809      	ldr	r1, [r1, #0]
	_current->arch.basepri = key;
    15e4:	6798      	str	r0, [r3, #120]	; 0x78
	_current->arch.swap_return_value = _k_neg_eagain;
    15e6:	67d9      	str	r1, [r3, #124]	; 0x7c

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    15e8:	4908      	ldr	r1, [pc, #32]	; (160c <arch_swap+0x30>)
    15ea:	684b      	ldr	r3, [r1, #4]
    15ec:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    15f0:	604b      	str	r3, [r1, #4]
    15f2:	2300      	movs	r3, #0
    15f4:	f383 8811 	msr	BASEPRI, r3
    15f8:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    15fc:	6893      	ldr	r3, [r2, #8]
}
    15fe:	6fd8      	ldr	r0, [r3, #124]	; 0x7c
    1600:	4770      	bx	lr
    1602:	bf00      	nop
    1604:	20000810 	.word	0x20000810
    1608:	000052e8 	.word	0x000052e8
    160c:	e000ed00 	.word	0xe000ed00

00001610 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_TRACING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    1610:	4913      	ldr	r1, [pc, #76]	; (1660 <z_arm_pendsv+0x50>)
    ldr r2, [r1, #_kernel_offset_to_current]
    1612:	688a      	ldr	r2, [r1, #8]

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    1614:	f04f 0038 	mov.w	r0, #56	; 0x38
    add r0, r2
    1618:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    161a:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    161e:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    1622:	2020      	movs	r0, #32
    msr BASEPRI, r0
    1624:	f380 8811 	msr	BASEPRI, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    1628:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    162c:	4f0d      	ldr	r7, [pc, #52]	; (1664 <z_arm_pendsv+0x54>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    162e:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    1632:	6a4a      	ldr	r2, [r1, #36]	; 0x24

    str r2, [r1, #_kernel_offset_to_current]
    1634:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    1636:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    1638:	6f90      	ldr	r0, [r2, #120]	; 0x78
    movs r3, #0
    163a:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    163c:	6793      	str	r3, [r2, #120]	; 0x78
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    163e:	f380 8811 	msr	BASEPRI, r0
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    1642:	f102 0038 	add.w	r0, r2, #56	; 0x38
    ldmia r0, {v1-v8, ip}
    1646:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    164a:	f38c 8809 	msr	PSP, ip
#endif

#ifdef CONFIG_BUILTIN_STACK_GUARD
    /* r2 contains k_thread */
    add r0, r2, #0
    164e:	f102 0000 	add.w	r0, r2, #0
    push {r2, lr}
    1652:	b504      	push	{r2, lr}
    bl configure_builtin_stack_guard
    1654:	f003 f997 	bl	4986 <configure_builtin_stack_guard>
    pop {r2, lr}
    1658:	e8bd 4004 	ldmia.w	sp!, {r2, lr}

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (_IntExit or z_arm_svc)
     */
    bx lr
    165c:	4770      	bx	lr
    165e:	0000      	.short	0x0000
    ldr r1, =_kernel
    1660:	20000810 	.word	0x20000810
    ldr v4, =_SCS_ICSR
    1664:	e000ed04 	.word	0xe000ed04

00001668 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #0x4    /* did we come from thread mode ? */
    1668:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    166c:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    166e:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    1672:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    1676:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    1678:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    167c:	2902      	cmp	r1, #2
    beq _oops
    167e:	d0ff      	beq.n	1680 <_oops>

00001680 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    1680:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    1682:	f003 f986 	bl	4992 <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    1686:	bd01      	pop	{r0, pc}

00001688 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    1688:	b243      	sxtb	r3, r0
  if ((int32_t)(IRQn) >= 0)
    168a:	2b00      	cmp	r3, #0
    168c:	db08      	blt.n	16a0 <arch_irq_enable+0x18>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    168e:	2201      	movs	r2, #1
    1690:	f000 001f 	and.w	r0, r0, #31
    1694:	fa02 f000 	lsl.w	r0, r2, r0
    1698:	4a02      	ldr	r2, [pc, #8]	; (16a4 <arch_irq_enable+0x1c>)
    169a:	095b      	lsrs	r3, r3, #5
    169c:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    16a0:	4770      	bx	lr
    16a2:	bf00      	nop
    16a4:	e000e100 	.word	0xe000e100

000016a8 <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    16a8:	4b05      	ldr	r3, [pc, #20]	; (16c0 <arch_irq_is_enabled+0x18>)
    16aa:	0942      	lsrs	r2, r0, #5
    16ac:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    16b0:	2301      	movs	r3, #1
    16b2:	f000 001f 	and.w	r0, r0, #31
    16b6:	fa03 f000 	lsl.w	r0, r3, r0
}
    16ba:	4010      	ands	r0, r2
    16bc:	4770      	bx	lr
    16be:	bf00      	nop
    16c0:	e000e100 	.word	0xe000e100

000016c4 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    16c4:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    16c6:	2b00      	cmp	r3, #0
	prio += _IRQ_PRIO_OFFSET;
    16c8:	f101 0101 	add.w	r1, r1, #1
  {
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    16cc:	bfac      	ite	ge
    16ce:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
  }
  else
  {
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    16d2:	4b06      	ldrlt	r3, [pc, #24]	; (16ec <z_arm_irq_priority_set+0x28>)
    16d4:	ea4f 1141 	mov.w	r1, r1, lsl #5
    16d8:	b2c9      	uxtb	r1, r1
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    16da:	bfab      	itete	ge
    16dc:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    16e0:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    16e4:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    16e8:	5419      	strblt	r1, [r3, r0]
}
    16ea:	4770      	bx	lr
    16ec:	e000ed14 	.word	0xe000ed14

000016f0 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    16f0:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    16f4:	9b00      	ldr	r3, [sp, #0]
	iframe->pc &= 0xfffffffe;
    16f6:	490b      	ldr	r1, [pc, #44]	; (1724 <arch_new_thread+0x34>)
	iframe->a2 = (uint32_t)p1;
    16f8:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->a3 = (uint32_t)p2;
    16fc:	9b01      	ldr	r3, [sp, #4]
	iframe->pc &= 0xfffffffe;
    16fe:	f021 0101 	bic.w	r1, r1, #1
	iframe->a3 = (uint32_t)p2;
    1702:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    1706:	9b02      	ldr	r3, [sp, #8]
	iframe->pc &= 0xfffffffe;
    1708:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->a4 = (uint32_t)p3;
    170c:	f842 3c14 	str.w	r3, [r2, #-20]

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    1710:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    1714:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    1718:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    171a:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    171c:	6582      	str	r2, [r0, #88]	; 0x58
	thread->arch.basepri = 0;
    171e:	6783      	str	r3, [r0, #120]	; 0x78
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    1720:	4770      	bx	lr
    1722:	bf00      	nop
    1724:	0000457f 	.word	0x0000457f

00001728 <arch_switch_to_main_thread>:
#endif
}

void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
    1728:	b508      	push	{r3, lr}
    172a:	4604      	mov	r4, r0
    172c:	460e      	mov	r6, r1
    172e:	4615      	mov	r5, r2
  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
    1730:	2300      	movs	r3, #0
    1732:	eee1 3a10 	vmsr	fpscr, r3
	z_arm_configure_static_mpu_regions();
    1736:	f000 fa0d 	bl	1b54 <z_arm_configure_static_mpu_regions>
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    173a:	4b09      	ldr	r3, [pc, #36]	; (1760 <arch_switch_to_main_thread+0x38>)
    173c:	609c      	str	r4, [r3, #8]
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    173e:	6ea3      	ldr	r3, [r4, #104]	; 0x68
    1740:	f383 880b 	msr	PSPLIM, r3

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    1744:	4628      	mov	r0, r5
    1746:	f386 8809 	msr	PSP, r6
    174a:	2100      	movs	r1, #0
    174c:	b663      	cpsie	if
    174e:	f381 8811 	msr	BASEPRI, r1
    1752:	f3bf 8f6f 	isb	sy
    1756:	2200      	movs	r2, #0
    1758:	2300      	movs	r3, #0
    175a:	f002 ff10 	bl	457e <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    175e:	bf00      	nop
    1760:	20000810 	.word	0x20000810

00001764 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    1764:	4901      	ldr	r1, [pc, #4]	; (176c <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    1766:	2210      	movs	r2, #16
	str	r2, [r1]
    1768:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    176a:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    176c:	e000ed10 	.word	0xe000ed10

00001770 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    1770:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    1772:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    1774:	f380 8811 	msr	BASEPRI, r0
	isb
    1778:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    177c:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    1780:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    1782:	b662      	cpsie	i
	isb
    1784:	f3bf 8f6f 	isb	sy

	bx	lr
    1788:	4770      	bx	lr
    178a:	bf00      	nop

0000178c <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    178c:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    178e:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    1790:	f381 8811 	msr	BASEPRI, r1

	wfe
    1794:	bf20      	wfe

	msr	BASEPRI, r0
    1796:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    179a:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    179c:	4770      	bx	lr
    179e:	bf00      	nop

000017a0 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    17a0:	bf30      	wfi
    b z_SysNmiOnReset
    17a2:	f7ff bffd 	b.w	17a0 <z_SysNmiOnReset>
    17a6:	bf00      	nop

000017a8 <z_arm_prep_c>:
#else
#define VECTOR_ADDRESS CONFIG_SRAM_BASE_ADDRESS
#endif
static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    17a8:	4a17      	ldr	r2, [pc, #92]	; (1808 <z_arm_prep_c+0x60>)
 * This routine prepares for the execution of and runs C code.
 *
 * @return N/A
 */
void z_arm_prep_c(void)
{
    17aa:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    17ac:	4b17      	ldr	r3, [pc, #92]	; (180c <z_arm_prep_c+0x64>)
    17ae:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    17b2:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    17b4:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    17b8:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    17bc:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    17c0:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    17c4:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	SCB->CPACR |= CPACR_CP10_PRIV_ACCESS | CPACR_CP11_PRIV_ACCESS;
    17c8:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    17cc:	f442 02a0 	orr.w	r2, r2, #5242880	; 0x500000
    17d0:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	FPU->FPCCR &= (~(FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk));
    17d4:	4a0e      	ldr	r2, [pc, #56]	; (1810 <z_arm_prep_c+0x68>)
    17d6:	6853      	ldr	r3, [r2, #4]
    17d8:	f023 4340 	bic.w	r3, r3, #3221225472	; 0xc0000000
    17dc:	6053      	str	r3, [r2, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    17de:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    17e2:	f3bf 8f6f 	isb	sy
  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
    17e6:	2300      	movs	r3, #0
    17e8:	eee1 3a10 	vmsr	fpscr, r3
  __ASM volatile ("MRS %0, control" : "=r" (result) );
    17ec:	f3ef 8314 	mrs	r3, CONTROL
	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
    17f0:	f023 0304 	bic.w	r3, r3, #4
  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
    17f4:	f383 8814 	msr	CONTROL, r3
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    17f8:	f000 ff1c 	bl	2634 <z_bss_zero>
	z_data_copy();
    17fc:	f000 ff24 	bl	2648 <z_data_copy>
#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    1800:	f000 f970 	bl	1ae4 <z_arm_interrupt_init>
	z_cstart();
    1804:	f000 ff5e 	bl	26c4 <z_cstart>
    1808:	00000000 	.word	0x00000000
    180c:	e000ed00 	.word	0xe000ed00
    1810:	e000ef30 	.word	0xe000ef30

00001814 <_isr_wrapper>:
 * @return N/A
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    1814:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    1816:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    1818:	4a0b      	ldr	r2, [pc, #44]	; (1848 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    181a:	6a10      	ldr	r0, [r2, #32]
	cmp r0, #0
    181c:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_sys_power_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    181e:	bf1e      	ittt	ne
	movne	r1, #0
    1820:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    1822:	6211      	strne	r1, [r2, #32]
		blne	z_sys_power_save_idle_exit
    1824:	f003 fa08 	blne	4c38 <z_sys_power_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    1828:	b662      	cpsie	i
#endif

#endif /* CONFIG_SYS_POWER_MANAGEMENT */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    182a:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    182e:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    1832:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	 * interface function.
	 */
	cpsie i
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    1836:	4905      	ldr	r1, [pc, #20]	; (184c <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    1838:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    183a:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    183c:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    183e:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    1842:	4903      	ldr	r1, [pc, #12]	; (1850 <_isr_wrapper+0x3c>)
	bx r1
    1844:	4708      	bx	r1
    1846:	0000      	.short	0x0000
	ldr r2, =_kernel
    1848:	20000810 	.word	0x20000810
	ldr r1, =_sw_isr_table
    184c:	00004ee8 	.word	0x00004ee8
	ldr r1, =z_arm_int_exit
    1850:	00001aa5 	.word	0x00001aa5

00001854 <__start>:
 * search for a __start symbol instead, so create that alias here.
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_platform_init
    1854:	f002 ff7a 	bl	474c <z_platform_init>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    1858:	2020      	movs	r0, #32
    msr BASEPRI, r0
    185a:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    185e:	4808      	ldr	r0, [pc, #32]	; (1880 <__start+0x2c>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    1860:	f44f 6100 	mov.w	r1, #2048	; 0x800
    adds r0, r0, r1
    1864:	1840      	adds	r0, r0, r1
    msr PSP, r0
    1866:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    186a:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    186e:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    1870:	4308      	orrs	r0, r1
    msr CONTROL, r0
    1872:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    1876:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    187a:	f7ff ff95 	bl	17a8 <z_arm_prep_c>
    187e:	0000      	.short	0x0000
    ldr r0, =z_interrupt_stacks
    1880:	20000db0 	.word	0x20000db0

00001884 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    1884:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    1888:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    188c:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    188e:	4672      	mov	r2, lr
	bl z_arm_fault
    1890:	f000 f870 	bl	1974 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    1894:	bd01      	pop	{r0, pc}
    1896:	bf00      	nop

00001898 <mem_manage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    1898:	4b0c      	ldr	r3, [pc, #48]	; (18cc <mem_manage_fault.isra.0+0x34>)
    189a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error (context area might be"
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    189c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    189e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    18a0:	0792      	lsls	r2, r2, #30
    18a2:	d508      	bpl.n	18b6 <mem_manage_fault.isra.0+0x1e>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		mmfar = SCB->MMFAR;
    18a4:	6b5a      	ldr	r2, [r3, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    18a6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    18a8:	0612      	lsls	r2, r2, #24
    18aa:	d504      	bpl.n	18b6 <mem_manage_fault.isra.0+0x1e>
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
			if (from_hard_fault) {
    18ac:	b118      	cbz	r0, 18b6 <mem_manage_fault.isra.0+0x1e>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    18ae:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    18b0:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    18b4:	629a      	str	r2, [r3, #40]	; 0x28

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf);
    18b6:	2000      	movs	r0, #0
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    18b8:	4b04      	ldr	r3, [pc, #16]	; (18cc <mem_manage_fault.isra.0+0x34>)
    18ba:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    18bc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_MSTKERR_Msk) {
    18be:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    18c0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    18c2:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    18c6:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf);
    18c8:	7008      	strb	r0, [r1, #0]

	return reason;
}
    18ca:	4770      	bx	lr
    18cc:	e000ed00 	.word	0xe000ed00

000018d0 <bus_fault.isra.0>:
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    18d0:	4b0d      	ldr	r3, [pc, #52]	; (1908 <bus_fault.isra.0+0x38>)
    18d2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error");
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    18d4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    18d6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    18d8:	0592      	lsls	r2, r2, #22
    18da:	d508      	bpl.n	18ee <bus_fault.isra.0+0x1e>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
    18dc:	6b9a      	ldr	r2, [r3, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    18de:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    18e0:	0412      	lsls	r2, r2, #16
    18e2:	d504      	bpl.n	18ee <bus_fault.isra.0+0x1e>
			PR_EXC("  BFAR Address: 0x%x", bfar);
			if (from_hard_fault) {
    18e4:	b118      	cbz	r0, 18ee <bus_fault.isra.0+0x1e>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    18e6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    18e8:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    18ec:	629a      	str	r2, [r3, #40]	; 0x28
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;

	*recoverable = memory_fault_recoverable(esf);
    18ee:	2000      	movs	r0, #0
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    18f0:	4b05      	ldr	r3, [pc, #20]	; (1908 <bus_fault.isra.0+0x38>)
    18f2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    18f4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    18f6:	05d2      	lsls	r2, r2, #23
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    18f8:	bf58      	it	pl
    18fa:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    18fc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    18fe:	f442 427f 	orr.w	r2, r2, #65280	; 0xff00
    1902:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf);
    1904:	7008      	strb	r0, [r1, #0]

	return reason;
}
    1906:	4770      	bx	lr
    1908:	e000ed00 	.word	0xe000ed00

0000190c <usage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    190c:	4b09      	ldr	r3, [pc, #36]	; (1934 <usage_fault.isra.0+0x28>)
    190e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    1910:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unaligned memory access");
	}
#if defined(CONFIG_ARMV8_M_MAINLINE)
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    1912:	6a98      	ldr	r0, [r3, #40]	; 0x28
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    1914:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    1916:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    1918:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    191a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    191c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    191e:	f410 1080 	ands.w	r0, r0, #1048576	; 0x100000
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    1922:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    1926:	ea6f 4212 	mvn.w	r2, r2, lsr #16

	return reason;
}
    192a:	bf18      	it	ne
    192c:	2002      	movne	r0, #2
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    192e:	629a      	str	r2, [r3, #40]	; 0x28
}
    1930:	4770      	bx	lr
    1932:	bf00      	nop
    1934:	e000ed00 	.word	0xe000ed00

00001938 <secure_fault.isra.0>:
 */
static void secure_fault(const z_arch_esf_t *esf)
{
	PR_FAULT_INFO("***** SECURE FAULT *****");

	STORE_xFAR(sfar, SAU->SFAR);
    1938:	4b0d      	ldr	r3, [pc, #52]	; (1970 <secure_fault.isra.0+0x38>)
    193a:	699a      	ldr	r2, [r3, #24]
	if ((SAU->SFSR & SAU_SFSR_SFARVALID_Msk) != 0) {
    193c:	695a      	ldr	r2, [r3, #20]
		PR_EXC("  Address: 0x%x", sfar);
	}

	/* bits are sticky: they stack and must be reset */
	if ((SAU->SFSR & SAU_SFSR_INVEP_Msk) != 0) {
    193e:	695a      	ldr	r2, [r3, #20]
    1940:	07d0      	lsls	r0, r2, #31
    1942:	d40f      	bmi.n	1964 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid entry point");
	} else if ((SAU->SFSR & SAU_SFSR_INVIS_Msk) != 0) {
    1944:	695a      	ldr	r2, [r3, #20]
    1946:	0791      	lsls	r1, r2, #30
    1948:	d40c      	bmi.n	1964 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid integrity signature");
	} else if ((SAU->SFSR & SAU_SFSR_INVER_Msk) != 0) {
    194a:	695a      	ldr	r2, [r3, #20]
    194c:	0752      	lsls	r2, r2, #29
    194e:	d409      	bmi.n	1964 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid exception return");
	} else if ((SAU->SFSR & SAU_SFSR_AUVIOL_Msk) != 0) {
    1950:	695a      	ldr	r2, [r3, #20]
    1952:	0710      	lsls	r0, r2, #28
    1954:	d406      	bmi.n	1964 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Attribution unit violation");
	} else if ((SAU->SFSR & SAU_SFSR_INVTRAN_Msk) != 0) {
    1956:	695a      	ldr	r2, [r3, #20]
    1958:	06d1      	lsls	r1, r2, #27
    195a:	d403      	bmi.n	1964 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid transition");
	} else if ((SAU->SFSR & SAU_SFSR_LSPERR_Msk) != 0) {
    195c:	695a      	ldr	r2, [r3, #20]
    195e:	0692      	lsls	r2, r2, #26
		PR_FAULT_INFO("  Lazy state preservation");
	} else if ((SAU->SFSR & SAU_SFSR_LSERR_Msk) != 0) {
    1960:	bf58      	it	pl
    1962:	695a      	ldrpl	r2, [r3, #20]
		PR_FAULT_INFO("  Lazy state error");
	}

	/* clear SFSR sticky bits */
	SAU->SFSR |= 0xFF;
    1964:	695a      	ldr	r2, [r3, #20]
    1966:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    196a:	615a      	str	r2, [r3, #20]
}
    196c:	4770      	bx	lr
    196e:	bf00      	nop
    1970:	e000edd0 	.word	0xe000edd0

00001974 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    1974:	b5f0      	push	{r4, r5, r6, r7, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    1976:	4b41      	ldr	r3, [pc, #260]	; (1a7c <z_arm_fault+0x108>)
    1978:	2500      	movs	r5, #0
    197a:	685b      	ldr	r3, [r3, #4]
{
    197c:	b08b      	sub	sp, #44	; 0x2c
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    197e:	f3c3 0308 	ubfx	r3, r3, #0, #9
    1982:	f385 8811 	msr	BASEPRI, r5
    1986:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    198a:	f002 447f 	and.w	r4, r2, #4278190080	; 0xff000000
    198e:	f1b4 4f7f 	cmp.w	r4, #4278190080	; 0xff000000
    1992:	d11e      	bne.n	19d2 <z_arm_fault+0x5e>
	if ((exc_return & EXC_RETURN_EXCEPTION_SECURE_Secure) == 0U) {
    1994:	f012 0401 	ands.w	r4, r2, #1
    1998:	d01a      	beq.n	19d0 <z_arm_fault+0x5c>
	if (exc_return & EXC_RETURN_RETURN_STACK_Secure) {
    199a:	0656      	lsls	r6, r2, #25
    199c:	f002 0408 	and.w	r4, r2, #8
    19a0:	d467      	bmi.n	1a72 <z_arm_fault+0xfe>
		if (exc_return & EXC_RETURN_SPSEL_PROCESS) {
    19a2:	f082 0204 	eor.w	r2, r2, #4
    19a6:	f3c2 0580 	ubfx	r5, r2, #2, #1
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    19aa:	b164      	cbz	r4, 19c6 <z_arm_fault+0x52>
  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
    19ac:	f3ef 8689 	mrs	r6, PSP_NS
	*recoverable = false;
    19b0:	2200      	movs	r2, #0
    19b2:	3b03      	subs	r3, #3
    19b4:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
    19b8:	2b04      	cmp	r3, #4
    19ba:	d84b      	bhi.n	1a54 <z_arm_fault+0xe0>
    19bc:	e8df f003 	tbb	[pc, r3]
    19c0:	41504c0b 	.word	0x41504c0b
    19c4:	48          	.byte	0x48
    19c5:	00          	.byte	0x00
  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
    19c6:	f3ef 8688 	mrs	r6, MSP_NS
  return(result);
    19ca:	e7f1      	b.n	19b0 <z_arm_fault+0x3c>
			ptr_esf =  (z_arch_esf_t *)psp;
    19cc:	460e      	mov	r6, r1
    19ce:	e7ef      	b.n	19b0 <z_arm_fault+0x3c>
	*nested_exc = false;
    19d0:	4625      	mov	r5, r4
		return NULL;
    19d2:	462e      	mov	r6, r5
    19d4:	e7ec      	b.n	19b0 <z_arm_fault+0x3c>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    19d6:	4b29      	ldr	r3, [pc, #164]	; (1a7c <z_arm_fault+0x108>)
    19d8:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    19da:	0792      	lsls	r2, r2, #30
    19dc:	d43a      	bmi.n	1a54 <z_arm_fault+0xe0>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    19de:	6adc      	ldr	r4, [r3, #44]	; 0x2c
    19e0:	f014 4480 	ands.w	r4, r4, #1073741824	; 0x40000000
    19e4:	d008      	beq.n	19f8 <z_arm_fault+0x84>
		if (SCB_MMFSR != 0) {
    19e6:	3328      	adds	r3, #40	; 0x28
    19e8:	781b      	ldrb	r3, [r3, #0]
    19ea:	b1eb      	cbz	r3, 1a28 <z_arm_fault+0xb4>
			reason = mem_manage_fault(esf, 1, recoverable);
    19ec:	2001      	movs	r0, #1
    19ee:	f10d 0107 	add.w	r1, sp, #7
		reason = mem_manage_fault(esf, 0, recoverable);
    19f2:	f7ff ff51 	bl	1898 <mem_manage_fault.isra.0>
    19f6:	4604      	mov	r4, r0
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    19f8:	f89d 3007 	ldrb.w	r3, [sp, #7]
    19fc:	b993      	cbnz	r3, 1a24 <z_arm_fault+0xb0>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    19fe:	2220      	movs	r2, #32
    1a00:	4631      	mov	r1, r6
    1a02:	a802      	add	r0, sp, #8
    1a04:	f003 f82d 	bl	4a62 <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    1a08:	9b09      	ldr	r3, [sp, #36]	; 0x24
    1a0a:	b36d      	cbz	r5, 1a68 <z_arm_fault+0xf4>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    1a0c:	f3c3 0208 	ubfx	r2, r3, #0, #9
    1a10:	b922      	cbnz	r2, 1a1c <z_arm_fault+0xa8>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    1a12:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    1a16:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    1a1a:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    1a1c:	4620      	mov	r0, r4
    1a1e:	a902      	add	r1, sp, #8
    1a20:	f002 ffb5 	bl	498e <z_arm_fatal_error>
}
    1a24:	b00b      	add	sp, #44	; 0x2c
    1a26:	bdf0      	pop	{r4, r5, r6, r7, pc}
		} else if (SCB_BFSR != 0) {
    1a28:	4b15      	ldr	r3, [pc, #84]	; (1a80 <z_arm_fault+0x10c>)
    1a2a:	781b      	ldrb	r3, [r3, #0]
    1a2c:	b12b      	cbz	r3, 1a3a <z_arm_fault+0xc6>
			reason = bus_fault(esf, 1, recoverable);
    1a2e:	2001      	movs	r0, #1
    1a30:	f10d 0107 	add.w	r1, sp, #7
		reason = bus_fault(esf, 0, recoverable);
    1a34:	f7ff ff4c 	bl	18d0 <bus_fault.isra.0>
    1a38:	e7dd      	b.n	19f6 <z_arm_fault+0x82>
		} else if (SCB_UFSR != 0) {
    1a3a:	4b12      	ldr	r3, [pc, #72]	; (1a84 <z_arm_fault+0x110>)
    1a3c:	881f      	ldrh	r7, [r3, #0]
    1a3e:	b2bf      	uxth	r7, r7
    1a40:	b117      	cbz	r7, 1a48 <z_arm_fault+0xd4>
		reason = usage_fault(esf);
    1a42:	f7ff ff63 	bl	190c <usage_fault.isra.0>
    1a46:	e7d6      	b.n	19f6 <z_arm_fault+0x82>
		} else if (SAU->SFSR != 0) {
    1a48:	4b0f      	ldr	r3, [pc, #60]	; (1a88 <z_arm_fault+0x114>)
    1a4a:	695c      	ldr	r4, [r3, #20]
    1a4c:	2c00      	cmp	r4, #0
    1a4e:	d0d3      	beq.n	19f8 <z_arm_fault+0x84>
		secure_fault(esf);
    1a50:	f7ff ff72 	bl	1938 <secure_fault.isra.0>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    1a54:	2400      	movs	r4, #0
    1a56:	e7cf      	b.n	19f8 <z_arm_fault+0x84>
		reason = mem_manage_fault(esf, 0, recoverable);
    1a58:	2000      	movs	r0, #0
    1a5a:	f10d 0107 	add.w	r1, sp, #7
    1a5e:	e7c8      	b.n	19f2 <z_arm_fault+0x7e>
		reason = bus_fault(esf, 0, recoverable);
    1a60:	2000      	movs	r0, #0
    1a62:	f10d 0107 	add.w	r1, sp, #7
    1a66:	e7e5      	b.n	1a34 <z_arm_fault+0xc0>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    1a68:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    1a6c:	f023 0301 	bic.w	r3, r3, #1
    1a70:	e7d3      	b.n	1a1a <z_arm_fault+0xa6>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    1a72:	2c00      	cmp	r4, #0
    1a74:	d1aa      	bne.n	19cc <z_arm_fault+0x58>
			ptr_esf = (z_arch_esf_t *)msp;
    1a76:	4606      	mov	r6, r0
			*nested_exc = true;
    1a78:	2501      	movs	r5, #1
    1a7a:	e799      	b.n	19b0 <z_arm_fault+0x3c>
    1a7c:	e000ed00 	.word	0xe000ed00
    1a80:	e000ed29 	.word	0xe000ed29
    1a84:	e000ed2a 	.word	0xe000ed2a
    1a88:	e000edd0 	.word	0xe000edd0

00001a8c <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    1a8c:	4b04      	ldr	r3, [pc, #16]	; (1aa0 <z_arm_fault_init+0x14>)
    1a8e:	695a      	ldr	r2, [r3, #20]
    1a90:	f042 0210 	orr.w	r2, r2, #16
    1a94:	615a      	str	r2, [r3, #20]
	 *
	 * For Non-Secure Firmware this could allow the Non-Secure Main
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
    1a96:	695a      	ldr	r2, [r3, #20]
    1a98:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
    1a9c:	615a      	str	r2, [r3, #20]
#endif /* CONFIG_BUILTIN_STACK_GUARD */
}
    1a9e:	4770      	bx	lr
    1aa0:	e000ed00 	.word	0xe000ed00

00001aa4 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    1aa4:	4b04      	ldr	r3, [pc, #16]	; (1ab8 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    1aa6:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    1aa8:	6a58      	ldr	r0, [r3, #36]	; 0x24
	cmp r0, r1
    1aaa:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    1aac:	d003      	beq.n	1ab6 <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    1aae:	4903      	ldr	r1, [pc, #12]	; (1abc <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    1ab0:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    1ab4:	600a      	str	r2, [r1, #0]

00001ab6 <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    1ab6:	4770      	bx	lr
	ldr r3, =_kernel
    1ab8:	20000810 	.word	0x20000810
	ldr r1, =_SCS_ICSR
    1abc:	e000ed04 	.word	0xe000ed04

00001ac0 <sys_arch_reboot>:
  __ASM volatile ("dsb 0xF":::"memory");
    1ac0:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    1ac4:	4905      	ldr	r1, [pc, #20]	; (1adc <sys_arch_reboot+0x1c>)
    1ac6:	4b06      	ldr	r3, [pc, #24]	; (1ae0 <sys_arch_reboot+0x20>)
    1ac8:	68ca      	ldr	r2, [r1, #12]
    1aca:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    1ace:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    1ad0:	60cb      	str	r3, [r1, #12]
    1ad2:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    1ad6:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    1ad8:	e7fd      	b.n	1ad6 <sys_arch_reboot+0x16>
    1ada:	bf00      	nop
    1adc:	e000ed00 	.word	0xe000ed00
    1ae0:	05fa0004 	.word	0x05fa0004

00001ae4 <z_arm_interrupt_init>:
 * @return N/A
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    1ae4:	2300      	movs	r3, #0
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1ae6:	2120      	movs	r1, #32
    1ae8:	4803      	ldr	r0, [pc, #12]	; (1af8 <z_arm_interrupt_init+0x14>)
    1aea:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    1aec:	3301      	adds	r3, #1
    1aee:	2b41      	cmp	r3, #65	; 0x41
    1af0:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    1af4:	d1f9      	bne.n	1aea <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    1af6:	4770      	bx	lr
    1af8:	e000e100 	.word	0xe000e100

00001afc <z_impl_k_thread_abort>:
#include <kswap.h>
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
    1afc:	b510      	push	{r4, lr}
    1afe:	4604      	mov	r4, r0
	z_thread_single_abort(thread);
    1b00:	f001 f962 	bl	2dc8 <z_thread_single_abort>

	if (_current == thread) {
    1b04:	4b11      	ldr	r3, [pc, #68]	; (1b4c <z_impl_k_thread_abort+0x50>)
    1b06:	689b      	ldr	r3, [r3, #8]
    1b08:	42a3      	cmp	r3, r4
    1b0a:	d107      	bne.n	1b1c <z_impl_k_thread_abort+0x20>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    1b0c:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    1b10:	b183      	cbz	r3, 1b34 <z_impl_k_thread_abort+0x38>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    1b12:	4a0f      	ldr	r2, [pc, #60]	; (1b50 <z_impl_k_thread_abort+0x54>)
    1b14:	6853      	ldr	r3, [r2, #4]
    1b16:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    1b1a:	6053      	str	r3, [r2, #4]
	__asm__ volatile(
    1b1c:	f04f 0320 	mov.w	r3, #32
    1b20:	f3ef 8011 	mrs	r0, BASEPRI
    1b24:	f383 8811 	msr	BASEPRI, r3
    1b28:	f3bf 8f6f 	isb	sy
		}
	}

	/* The abort handler might have altered the ready queue. */
	z_reschedule_unlocked();
}
    1b2c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	(void) z_pend_curr_irqlock(arch_irq_lock(), wait_q, timeout);
}

static inline void z_reschedule_unlocked(void)
{
	(void) z_reschedule_irqlock(arch_irq_lock());
    1b30:	f003 b8a6 	b.w	4c80 <z_reschedule_irqlock>
    1b34:	f04f 0320 	mov.w	r3, #32
    1b38:	f3ef 8011 	mrs	r0, BASEPRI
    1b3c:	f383 8811 	msr	BASEPRI, r3
    1b40:	f3bf 8f6f 	isb	sy

static inline int z_swap_irqlock(unsigned int key)
{
	int ret;
	z_check_stack_sentinel();
	ret = arch_swap(key);
    1b44:	f7ff fd4a 	bl	15dc <arch_swap>
	return ret;
    1b48:	e7e8      	b.n	1b1c <z_impl_k_thread_abort+0x20>
    1b4a:	bf00      	nop
    1b4c:	20000810 	.word	0x20000810
    1b50:	e000ed00 	.word	0xe000ed00

00001b54 <z_arm_configure_static_mpu_regions>:
 *
 * For some MPU architectures, such as the unmodified ARMv8-M MPU,
 * the function must execute with MPU enabled.
 */
void z_arm_configure_static_mpu_regions(void)
{
    1b54:	b510      	push	{r4, lr}
		.size = (uint32_t)&_nocache_ram_size,
		.attr = K_MEM_PARTITION_P_RW_U_NA_NOCACHE,
		};
#endif /* CONFIG_NOCACHE_MEMORY */
#if defined(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT)
		const struct k_mem_partition ramfunc_region =
    1b56:	4b0e      	ldr	r3, [pc, #56]	; (1b90 <z_arm_configure_static_mpu_regions+0x3c>)
{
    1b58:	b088      	sub	sp, #32
		const struct k_mem_partition ramfunc_region =
    1b5a:	9302      	str	r3, [sp, #8]
    1b5c:	4b0d      	ldr	r3, [pc, #52]	; (1b94 <z_arm_configure_static_mpu_regions+0x40>)
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    1b5e:	4c0e      	ldr	r4, [pc, #56]	; (1b98 <z_arm_configure_static_mpu_regions+0x44>)
		const struct k_mem_partition ramfunc_region =
    1b60:	9303      	str	r3, [sp, #12]
    1b62:	4b0e      	ldr	r3, [pc, #56]	; (1b9c <z_arm_configure_static_mpu_regions+0x48>)
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    1b64:	4a0e      	ldr	r2, [pc, #56]	; (1ba0 <z_arm_configure_static_mpu_regions+0x4c>)
		const struct k_mem_partition ramfunc_region =
    1b66:	9304      	str	r3, [sp, #16]
	const struct k_mem_partition *static_regions[] = {
    1b68:	ab02      	add	r3, sp, #8
    1b6a:	9301      	str	r3, [sp, #4]
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    1b6c:	a801      	add	r0, sp, #4
    1b6e:	4623      	mov	r3, r4
    1b70:	2101      	movs	r1, #1
    1b72:	f000 f907 	bl	1d84 <arm_core_mpu_configure_static_mpu_regions>
	/* Define a constant array of k_mem_partition objects that holds the
	 * boundaries of the areas, inside which dynamic region programming
	 * is allowed. The information is passed to the underlying driver at
	 * initialization.
	 */
	const struct k_mem_partition dyn_region_areas[] = {
    1b76:	2300      	movs	r3, #0
    1b78:	9307      	str	r3, [sp, #28]
		{
		.start = _MPU_DYNAMIC_REGIONS_AREA_START,
    1b7a:	4b0a      	ldr	r3, [pc, #40]	; (1ba4 <z_arm_configure_static_mpu_regions+0x50>)
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
		}
	};

	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    1b7c:	2101      	movs	r1, #1
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
    1b7e:	1ae4      	subs	r4, r4, r3
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    1b80:	a805      	add	r0, sp, #20
	const struct k_mem_partition dyn_region_areas[] = {
    1b82:	9305      	str	r3, [sp, #20]
    1b84:	9406      	str	r4, [sp, #24]
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    1b86:	f000 f907 	bl	1d98 <arm_core_mpu_mark_areas_for_dynamic_regions>
		ARRAY_SIZE(dyn_region_areas));
#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */
}
    1b8a:	b008      	add	sp, #32
    1b8c:	bd10      	pop	{r4, pc}
    1b8e:	bf00      	nop
    1b90:	20000000 	.word	0x20000000
    1b94:	00000000 	.word	0x00000000
    1b98:	20010000 	.word	0x20010000
    1b9c:	00010006 	.word	0x00010006
    1ba0:	20000000 	.word	0x20000000
    1ba4:	20000160 	.word	0x20000160

00001ba8 <region_init>:
 * Note:
 *   The caller must provide a valid region index.
 */
static void region_init(const uint32_t index,
	const struct arm_mpu_region *region_conf)
{
    1ba8:	b510      	push	{r4, lr}
	ARM_MPU_SetRegion(
		/* RNR */
		index,
		/* RBAR */
		(region_conf->base & MPU_RBAR_BASE_Msk)
    1baa:	680b      	ldr	r3, [r1, #0]
		| (region_conf->attr.rbar &
    1bac:	7a0c      	ldrb	r4, [r1, #8]
		(region_conf->base & MPU_RBAR_BASE_Msk)
    1bae:	f023 021f 	bic.w	r2, r3, #31
		| (region_conf->attr.rbar &
    1bb2:	f004 031f 	and.w	r3, r4, #31
    1bb6:	431a      	orrs	r2, r3
			(MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)),
		/* RLAR */
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    1bb8:	68cb      	ldr	r3, [r1, #12]
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    1bba:	0964      	lsrs	r4, r4, #5
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    1bbc:	f023 031f 	bic.w	r3, r3, #31
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/   
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
  mpu->RNR = rnr;
    1bc0:	4904      	ldr	r1, [pc, #16]	; (1bd4 <region_init+0x2c>)
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    1bc2:	ea43 0344 	orr.w	r3, r3, r4, lsl #1
			& MPU_RLAR_AttrIndx_Msk)
		| MPU_RLAR_EN_Msk
    1bc6:	f043 0301 	orr.w	r3, r3, #1
    1bca:	6088      	str	r0, [r1, #8]
  mpu->RBAR = rbar;
    1bcc:	60ca      	str	r2, [r1, #12]
  mpu->RLAR = rlar;
    1bce:	610b      	str	r3, [r1, #16]
	);

	LOG_DBG("[%d] 0x%08x 0x%08x 0x%08x 0x%08x",
			index, region_conf->base, region_conf->attr.rbar,
			region_conf->attr.mair_idx, region_conf->attr.r_limit);
}
    1bd0:	bd10      	pop	{r4, pc}
    1bd2:	bf00      	nop
    1bd4:	e000ed90 	.word	0xe000ed90

00001bd8 <mpu_configure_regions_and_partition.constprop.0>:
 * sanity check of the memory regions to be programmed.
 *
 * The function performs a full partition of the background memory
 * area, effectively, leaving no space in this area uncovered by MPU.
 */
static int mpu_configure_regions_and_partition(const struct k_mem_partition
    1bd8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1bdc:	4607      	mov	r7, r0
    1bde:	4688      	mov	r8, r1
    1be0:	4614      	mov	r4, r2
	bool do_sanity_check)
{
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    1be2:	2600      	movs	r6, #0
	MPU->RNR = index;
    1be4:	4d4a      	ldr	r5, [pc, #296]	; (1d10 <mpu_configure_regions_and_partition.constprop.0+0x138>)
static int mpu_configure_regions_and_partition(const struct k_mem_partition
    1be6:	b085      	sub	sp, #20
	for (i = 0; i < regions_num; i++) {
    1be8:	4546      	cmp	r6, r8
    1bea:	da0b      	bge.n	1c04 <mpu_configure_regions_and_partition.constprop.0+0x2c>
		if (regions[i]->size == 0U) {
    1bec:	f857 3026 	ldr.w	r3, [r7, r6, lsl #2]
    1bf0:	f8d3 9004 	ldr.w	r9, [r3, #4]
    1bf4:	f1b9 0f00 	cmp.w	r9, #0
    1bf8:	d03a      	beq.n	1c70 <mpu_configure_regions_and_partition.constprop.0+0x98>
		&&
    1bfa:	f1b9 0f1f 	cmp.w	r9, #31
    1bfe:	d805      	bhi.n	1c0c <mpu_configure_regions_and_partition.constprop.0+0x34>

			reg_index =
				mpu_configure_region(reg_index, regions[i]);

			if (reg_index == -EINVAL) {
				return reg_index;
    1c00:	f06f 0415 	mvn.w	r4, #21
			reg_index++;
		}
	}

	return reg_index;
}
    1c04:	4620      	mov	r0, r4
    1c06:	b005      	add	sp, #20
    1c08:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		&&
    1c0c:	f019 0f1f 	tst.w	r9, #31
    1c10:	d1f6      	bne.n	1c00 <mpu_configure_regions_and_partition.constprop.0+0x28>
		((part->start &
    1c12:	f8d3 a000 	ldr.w	sl, [r3]
		&&
    1c16:	f01a 0f1f 	tst.w	sl, #31
    1c1a:	d1f1      	bne.n	1c00 <mpu_configure_regions_and_partition.constprop.0+0x28>
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    1c1c:	4650      	mov	r0, sl
    1c1e:	f002 fee3 	bl	49e8 <arm_cmse_mpu_region_get>
    1c22:	4683      	mov	fp, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    1c24:	eb09 000a 	add.w	r0, r9, sl
    1c28:	3801      	subs	r0, #1
    1c2a:	f002 fedd 	bl	49e8 <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    1c2e:	4583      	cmp	fp, r0
    1c30:	d1e6      	bne.n	1c00 <mpu_configure_regions_and_partition.constprop.0+0x28>
		if ((u_reg_index == -EINVAL) ||
    1c32:	f11b 0f16 	cmn.w	fp, #22
    1c36:	d0e3      	beq.n	1c00 <mpu_configure_regions_and_partition.constprop.0+0x28>
			(u_reg_index > (reg_index - 1))) {
    1c38:	1e63      	subs	r3, r4, #1
		if ((u_reg_index == -EINVAL) ||
    1c3a:	455b      	cmp	r3, fp
    1c3c:	dbe0      	blt.n	1c00 <mpu_configure_regions_and_partition.constprop.0+0x28>
	MPU->RNR = index;
    1c3e:	f8c5 b008 	str.w	fp, [r5, #8]
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
    1c42:	68e8      	ldr	r0, [r5, #12]
	MPU->RNR = index;
    1c44:	f8c5 b008 	str.w	fp, [r5, #8]
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    1c48:	692b      	ldr	r3, [r5, #16]
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
    1c4a:	f857 1026 	ldr.w	r1, [r7, r6, lsl #2]
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
    1c4e:	f020 001f 	bic.w	r0, r0, #31
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    1c52:	f043 0a1f 	orr.w	sl, r3, #31
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
    1c56:	e9d1 3200 	ldrd	r3, r2, [r1]
    1c5a:	441a      	add	r2, r3
		if ((regions[i]->start == u_reg_base) &&
    1c5c:	4298      	cmp	r0, r3
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
    1c5e:	f102 39ff 	add.w	r9, r2, #4294967295
		if ((regions[i]->start == u_reg_base) &&
    1c62:	d118      	bne.n	1c96 <mpu_configure_regions_and_partition.constprop.0+0xbe>
    1c64:	45ca      	cmp	sl, r9
    1c66:	d105      	bne.n	1c74 <mpu_configure_regions_and_partition.constprop.0+0x9c>
			mpu_configure_region(u_reg_index, regions[i]);
    1c68:	fa5f f08b 	uxtb.w	r0, fp
    1c6c:	f002 fe9c 	bl	49a8 <mpu_configure_region>
	for (i = 0; i < regions_num; i++) {
    1c70:	3601      	adds	r6, #1
    1c72:	e7b9      	b.n	1be8 <mpu_configure_regions_and_partition.constprop.0+0x10>
	MPU->RNR = index;
    1c74:	f8c5 b008 	str.w	fp, [r5, #8]
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    1c78:	68eb      	ldr	r3, [r5, #12]
		| (base & MPU_RBAR_BASE_Msk);
    1c7a:	f022 021f 	bic.w	r2, r2, #31
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    1c7e:	f003 031f 	and.w	r3, r3, #31
		| (base & MPU_RBAR_BASE_Msk);
    1c82:	431a      	orrs	r2, r3
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    1c84:	60ea      	str	r2, [r5, #12]
				mpu_configure_region(reg_index, regions[i]);
    1c86:	b2e0      	uxtb	r0, r4
				mpu_configure_region(reg_index, regions[i]);
    1c88:	f002 fe8e 	bl	49a8 <mpu_configure_region>
			if (reg_index == -EINVAL) {
    1c8c:	f110 0f16 	cmn.w	r0, #22
    1c90:	d0b6      	beq.n	1c00 <mpu_configure_regions_and_partition.constprop.0+0x28>
			reg_index++;
    1c92:	1c44      	adds	r4, r0, #1
    1c94:	e7ec      	b.n	1c70 <mpu_configure_regions_and_partition.constprop.0+0x98>
	MPU->RNR = index;
    1c96:	f8c5 b008 	str.w	fp, [r5, #8]
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    1c9a:	692a      	ldr	r2, [r5, #16]
    1c9c:	3b01      	subs	r3, #1
    1c9e:	f023 031f 	bic.w	r3, r3, #31
    1ca2:	f002 021f 	and.w	r2, r2, #31
		| (limit & MPU_RLAR_LIMIT_Msk);
    1ca6:	4313      	orrs	r3, r2
		} else if (reg_last == u_reg_last) {
    1ca8:	45ca      	cmp	sl, r9
    1caa:	b2e0      	uxtb	r0, r4
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    1cac:	612b      	str	r3, [r5, #16]
		} else if (reg_last == u_reg_last) {
    1cae:	d0eb      	beq.n	1c88 <mpu_configure_regions_and_partition.constprop.0+0xb0>
				mpu_configure_region(reg_index, regions[i]);
    1cb0:	f002 fe7a 	bl	49a8 <mpu_configure_region>
			if (reg_index == -EINVAL) {
    1cb4:	f110 0f16 	cmn.w	r0, #22
    1cb8:	d0a2      	beq.n	1c00 <mpu_configure_regions_and_partition.constprop.0+0x28>
	MPU->RNR = index;
    1cba:	f8c5 b008 	str.w	fp, [r5, #8]
	attr->rbar = MPU->RBAR &
    1cbe:	68ea      	ldr	r2, [r5, #12]
    1cc0:	f89d 3008 	ldrb.w	r3, [sp, #8]
			REGION_LIMIT_ADDR((regions[i]->start +
    1cc4:	f10a 3aff 	add.w	sl, sl, #4294967295
	attr->rbar = MPU->RBAR &
    1cc8:	f362 0304 	bfi	r3, r2, #0, #5
    1ccc:	f88d 3008 	strb.w	r3, [sp, #8]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    1cd0:	692b      	ldr	r3, [r5, #16]
    1cd2:	f89d 2008 	ldrb.w	r2, [sp, #8]
    1cd6:	085b      	lsrs	r3, r3, #1
    1cd8:	f363 1247 	bfi	r2, r3, #5, #3
			fill_region.base = regions[i]->start +
    1cdc:	f857 3026 	ldr.w	r3, [r7, r6, lsl #2]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    1ce0:	f88d 2008 	strb.w	r2, [sp, #8]
			fill_region.base = regions[i]->start +
    1ce4:	e9d3 1300 	ldrd	r1, r3, [r3]
    1ce8:	440b      	add	r3, r1
    1cea:	9300      	str	r3, [sp, #0]
			REGION_LIMIT_ADDR((regions[i]->start +
    1cec:	f023 031f 	bic.w	r3, r3, #31
			reg_index++;
    1cf0:	3001      	adds	r0, #1
			REGION_LIMIT_ADDR((regions[i]->start +
    1cf2:	4453      	add	r3, sl
    1cf4:	eba3 0309 	sub.w	r3, r3, r9
    1cf8:	b2c0      	uxtb	r0, r0
    1cfa:	f023 031f 	bic.w	r3, r3, #31

static int region_allocate_and_init(const uint8_t index,
	const struct arm_mpu_region *region_conf)
{
	/* Attempt to allocate new region index. */
	if (index > (get_num_regions() - 1)) {
    1cfe:	280f      	cmp	r0, #15
			fill_region.attr.r_limit =
    1d00:	9303      	str	r3, [sp, #12]
    1d02:	f63f af7d 	bhi.w	1c00 <mpu_configure_regions_and_partition.constprop.0+0x28>
	}

	LOG_DBG("Program MPU region at index 0x%x", index);

	/* Program region */
	region_init(index, region_conf);
    1d06:	4669      	mov	r1, sp
    1d08:	f7ff ff4e 	bl	1ba8 <region_init>
    1d0c:	e7c1      	b.n	1c92 <mpu_configure_regions_and_partition.constprop.0+0xba>
    1d0e:	bf00      	nop
    1d10:	e000ed90 	.word	0xe000ed90

00001d14 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    1d14:	2205      	movs	r2, #5
    1d16:	4b03      	ldr	r3, [pc, #12]	; (1d24 <arm_core_mpu_enable+0x10>)
    1d18:	605a      	str	r2, [r3, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    1d1a:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1d1e:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    1d22:	4770      	bx	lr
    1d24:	e000ed90 	.word	0xe000ed90

00001d28 <arm_core_mpu_disable>:
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
__STATIC_FORCEINLINE void __DMB(void)
{
  __ASM volatile ("dmb 0xF":::"memory");
    1d28:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    1d2c:	2200      	movs	r2, #0
    1d2e:	4b01      	ldr	r3, [pc, #4]	; (1d34 <arm_core_mpu_disable+0xc>)
    1d30:	605a      	str	r2, [r3, #4]
}
    1d32:	4770      	bx	lr
    1d34:	e000ed90 	.word	0xe000ed90

00001d38 <arm_mpu_init>:
 *
 * This function provides the default configuration mechanism for the Memory
 * Protection Unit (MPU).
 */
static int arm_mpu_init(const struct device *arg)
{
    1d38:	b538      	push	{r3, r4, r5, lr}
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    1d3a:	4c0e      	ldr	r4, [pc, #56]	; (1d74 <arm_mpu_init+0x3c>)
    1d3c:	6825      	ldr	r5, [r4, #0]
    1d3e:	2d10      	cmp	r5, #16
    1d40:	d814      	bhi.n	1d6c <arm_mpu_init+0x34>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    1d42:	f7ff fff1 	bl	1d28 <arm_core_mpu_disable>

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1d46:	2000      	movs	r0, #0
	MPU->MAIR0 =
    1d48:	4b0b      	ldr	r3, [pc, #44]	; (1d78 <arm_mpu_init+0x40>)
    1d4a:	4a0c      	ldr	r2, [pc, #48]	; (1d7c <arm_mpu_init+0x44>)
    1d4c:	631a      	str	r2, [r3, #48]	; 0x30
    1d4e:	4285      	cmp	r5, r0
    1d50:	d105      	bne.n	1d5e <arm_mpu_init+0x26>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    1d52:	4b0b      	ldr	r3, [pc, #44]	; (1d80 <arm_mpu_init+0x48>)
    1d54:	701d      	strb	r5, [r3, #0]


	arm_core_mpu_enable();
    1d56:	f7ff ffdd 	bl	1d14 <arm_core_mpu_enable>
	__ASSERT(
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */
	return 0;
    1d5a:	2000      	movs	r0, #0
}
    1d5c:	bd38      	pop	{r3, r4, r5, pc}
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
    1d5e:	6861      	ldr	r1, [r4, #4]
    1d60:	eb01 1100 	add.w	r1, r1, r0, lsl #4
    1d64:	f7ff ff20 	bl	1ba8 <region_init>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1d68:	3001      	adds	r0, #1
    1d6a:	e7f0      	b.n	1d4e <arm_mpu_init+0x16>
		return -1;
    1d6c:	f04f 30ff 	mov.w	r0, #4294967295
    1d70:	e7f4      	b.n	1d5c <arm_mpu_init+0x24>
    1d72:	bf00      	nop
    1d74:	00005288 	.word	0x00005288
    1d78:	e000ed90 	.word	0xe000ed90
    1d7c:	0044ffaa 	.word	0x0044ffaa
    1d80:	2000086c 	.word	0x2000086c

00001d84 <arm_core_mpu_configure_static_mpu_regions>:
{
    1d84:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct k_mem_partition
	*static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    1d86:	4c03      	ldr	r4, [pc, #12]	; (1d94 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * given boundaries.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions_and_partition(static_regions,
    1d88:	7822      	ldrb	r2, [r4, #0]
    1d8a:	f7ff ff25 	bl	1bd8 <mpu_configure_regions_and_partition.constprop.0>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    1d8e:	7020      	strb	r0, [r4, #0]
}
    1d90:	bd10      	pop	{r4, pc}
    1d92:	bf00      	nop
    1d94:	2000086c 	.word	0x2000086c

00001d98 <arm_core_mpu_mark_areas_for_dynamic_regions>:
{
    1d98:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1d9c:	4d26      	ldr	r5, [pc, #152]	; (1e38 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa0>)
    1d9e:	468a      	mov	sl, r1
{
	/* In ARMv8-M architecture we need to store the index values
	 * and the default configuration of the MPU regions, inside
	 * which dynamic memory regions may be programmed at run-time.
	 */
	for (int i = 0; i < dyn_region_areas_num; i++) {
    1da0:	4606      	mov	r6, r0
    1da2:	f04f 0800 	mov.w	r8, #0
    1da6:	46ab      	mov	fp, r5
	MPU->RNR = index;
    1da8:	4f24      	ldr	r7, [pc, #144]	; (1e3c <arm_core_mpu_mark_areas_for_dynamic_regions+0xa4>)
	for (int i = 0; i < dyn_region_areas_num; i++) {
    1daa:	45d0      	cmp	r8, sl
    1dac:	da1b      	bge.n	1de6 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
		if (dyn_region_areas[i].size == 0U) {
    1dae:	f8d6 9004 	ldr.w	r9, [r6, #4]
    1db2:	f1b9 0f00 	cmp.w	r9, #0
    1db6:	d039      	beq.n	1e2c <arm_core_mpu_mark_areas_for_dynamic_regions+0x94>
		}
		/* Non-empty area */

		/* Retrieve HW MPU region index */
		dyn_reg_info[i].index =
			get_region_index(dyn_region_areas[i].start,
    1db8:	6831      	ldr	r1, [r6, #0]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    1dba:	4608      	mov	r0, r1
    1dbc:	9101      	str	r1, [sp, #4]
    1dbe:	f002 fe13 	bl	49e8 <arm_cmse_mpu_region_get>
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    1dc2:	9901      	ldr	r1, [sp, #4]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    1dc4:	4604      	mov	r4, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    1dc6:	eb09 0001 	add.w	r0, r9, r1
    1dca:	3801      	subs	r0, #1
    1dcc:	f002 fe0c 	bl	49e8 <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    1dd0:	4284      	cmp	r4, r0
    1dd2:	f04f 0214 	mov.w	r2, #20
    1dd6:	4b1a      	ldr	r3, [pc, #104]	; (1e40 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa8>)
    1dd8:	d008      	beq.n	1dec <arm_core_mpu_mark_areas_for_dynamic_regions+0x54>
		dyn_reg_info[i].index =
    1dda:	f06f 0315 	mvn.w	r3, #21
    1dde:	fb02 f808 	mul.w	r8, r2, r8
    1de2:	f84b 3008 	str.w	r3, [fp, r8]
}
    1de6:	b003      	add	sp, #12
    1de8:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
					dyn_region_areas[i].size);

		if (dyn_reg_info[i].index == -EINVAL) {
    1dec:	f114 0f16 	cmn.w	r4, #22
		dyn_reg_info[i].index =
    1df0:	602c      	str	r4, [r5, #0]
		if (dyn_reg_info[i].index == -EINVAL) {
    1df2:	d0f8      	beq.n	1de6 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>

			return -EINVAL;
		}

		if (dyn_reg_info[i].index >= static_regions_num) {
    1df4:	7819      	ldrb	r1, [r3, #0]
    1df6:	42a1      	cmp	r1, r4
    1df8:	ddf5      	ble.n	1de6 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
	attr->rbar = MPU->RBAR &
    1dfa:	fb02 b008 	mla	r0, r2, r8, fp
	MPU->RNR = index;
    1dfe:	60bc      	str	r4, [r7, #8]
	MPU->RNR = index;
    1e00:	60bc      	str	r4, [r7, #8]
	attr->rbar = MPU->RBAR &
    1e02:	68fc      	ldr	r4, [r7, #12]
    1e04:	f100 0108 	add.w	r1, r0, #8
    1e08:	7b00      	ldrb	r0, [r0, #12]
    1e0a:	f364 0004 	bfi	r0, r4, #0, #5
    1e0e:	7108      	strb	r0, [r1, #4]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    1e10:	6938      	ldr	r0, [r7, #16]
    1e12:	790c      	ldrb	r4, [r1, #4]
    1e14:	0840      	lsrs	r0, r0, #1
    1e16:	f360 1447 	bfi	r4, r0, #5, #3
    1e1a:	710c      	strb	r4, [r1, #4]
	region_conf->base = (MPU->RBAR & MPU_RBAR_BASE_Msk);
    1e1c:	68f9      	ldr	r1, [r7, #12]
    1e1e:	f021 011f 	bic.w	r1, r1, #31
    1e22:	6069      	str	r1, [r5, #4]
	region_conf->attr.r_limit = MPU->RLAR & MPU_RLAR_LIMIT_Msk;
    1e24:	6939      	ldr	r1, [r7, #16]
    1e26:	f021 011f 	bic.w	r1, r1, #31
    1e2a:	6129      	str	r1, [r5, #16]
	for (int i = 0; i < dyn_region_areas_num; i++) {
    1e2c:	f108 0801 	add.w	r8, r8, #1
    1e30:	3514      	adds	r5, #20
    1e32:	360c      	adds	r6, #12
    1e34:	e7b9      	b.n	1daa <arm_core_mpu_mark_areas_for_dynamic_regions+0x12>
    1e36:	bf00      	nop
    1e38:	200007f4 	.word	0x200007f4
    1e3c:	e000ed90 	.word	0xe000ed90
    1e40:	2000086c 	.word	0x2000086c

00001e44 <tz_nonsecure_state_setup>:
}
#endif /* CONFIG_ARMV8_M_MAINLINE */

void tz_nonsecure_state_setup(const tz_nonsecure_setup_conf_t *p_ns_conf)
{
	configure_nonsecure_vtor_offset(p_ns_conf->vtor_ns);
    1e44:	6882      	ldr	r2, [r0, #8]
	SCB_NS->VTOR = vtor_ns;
    1e46:	4b0c      	ldr	r3, [pc, #48]	; (1e78 <tz_nonsecure_state_setup+0x34>)
    1e48:	609a      	str	r2, [r3, #8]
  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
    1e4a:	6803      	ldr	r3, [r0, #0]
    1e4c:	f383 8888 	msr	MSP_NS, r3
  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
    1e50:	6843      	ldr	r3, [r0, #4]
    1e52:	f383 8889 	msr	PSP_NS, r3
	configure_nonsecure_psp(p_ns_conf->psp_ns);
	/* Select which stack-pointer to use (MSP or PSP) and
	 * the privilege level for thread mode.
	 */
	configure_nonsecure_control(p_ns_conf->control_ns.spsel,
		p_ns_conf->control_ns.npriv);
    1e56:	7b02      	ldrb	r2, [r0, #12]
    1e58:	f002 0101 	and.w	r1, r2, #1
  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
    1e5c:	f3ef 8394 	mrs	r3, CONTROL_NS
	control_ns &= ~(CONTROL_SPSEL_Msk | CONTROL_nPRIV_Msk);
    1e60:	f023 0303 	bic.w	r3, r3, #3
	if (spsel_ns) {
    1e64:	0792      	lsls	r2, r2, #30
		control_ns |= CONTROL_SPSEL_Msk;
    1e66:	bf48      	it	mi
    1e68:	f043 0302 	orrmi.w	r3, r3, #2
	if (npriv_ns) {
    1e6c:	b109      	cbz	r1, 1e72 <tz_nonsecure_state_setup+0x2e>
		control_ns |= CONTROL_nPRIV_Msk;
    1e6e:	f043 0301 	orr.w	r3, r3, #1
  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
    1e72:	f383 8894 	msr	CONTROL_NS, r3
}
    1e76:	4770      	bx	lr
    1e78:	e002ed00 	.word	0xe002ed00

00001e7c <tz_nbanked_exception_target_state_set>:

void tz_nbanked_exception_target_state_set(int secure_state)
{
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    1e7c:	4a08      	ldr	r2, [pc, #32]	; (1ea0 <tz_nbanked_exception_target_state_set+0x24>)
    1e7e:	68d3      	ldr	r3, [r2, #12]
	if (secure_state) {
    1e80:	b148      	cbz	r0, 1e96 <tz_nbanked_exception_target_state_set+0x1a>
		aircr_payload &= ~(SCB_AIRCR_BFHFNMINS_Msk);
    1e82:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
    1e86:	041b      	lsls	r3, r3, #16
    1e88:	0c1b      	lsrs	r3, r3, #16
	} else {
		aircr_payload |= SCB_AIRCR_BFHFNMINS_Msk;
	}
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
			& SCB_AIRCR_VECTKEY_Msk)
		| aircr_payload;
    1e8a:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
    1e8e:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
    1e92:	60d3      	str	r3, [r2, #12]
}
    1e94:	4770      	bx	lr
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    1e96:	b29b      	uxth	r3, r3
		aircr_payload |= SCB_AIRCR_BFHFNMINS_Msk;
    1e98:	f443 5300 	orr.w	r3, r3, #8192	; 0x2000
    1e9c:	e7f5      	b.n	1e8a <tz_nbanked_exception_target_state_set+0xe>
    1e9e:	bf00      	nop
    1ea0:	e000ed00 	.word	0xe000ed00

00001ea4 <tz_nonsecure_exception_prio_config>:

void tz_nonsecure_exception_prio_config(int secure_boost)
{
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    1ea4:	4a08      	ldr	r2, [pc, #32]	; (1ec8 <tz_nonsecure_exception_prio_config+0x24>)
    1ea6:	68d3      	ldr	r3, [r2, #12]
	if (secure_boost) {
    1ea8:	b140      	cbz	r0, 1ebc <tz_nonsecure_exception_prio_config+0x18>
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    1eaa:	b29b      	uxth	r3, r3
		aircr_payload |= SCB_AIRCR_PRIS_Msk;
    1eac:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
	} else {
		aircr_payload &= ~(SCB_AIRCR_PRIS_Msk);
	}
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
			& SCB_AIRCR_VECTKEY_Msk)
		| aircr_payload;
    1eb0:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
    1eb4:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
    1eb8:	60d3      	str	r3, [r2, #12]
}
    1eba:	4770      	bx	lr
		aircr_payload &= ~(SCB_AIRCR_PRIS_Msk);
    1ebc:	f423 4380 	bic.w	r3, r3, #16384	; 0x4000
    1ec0:	041b      	lsls	r3, r3, #16
    1ec2:	0c1b      	lsrs	r3, r3, #16
    1ec4:	e7f4      	b.n	1eb0 <tz_nonsecure_exception_prio_config+0xc>
    1ec6:	bf00      	nop
    1ec8:	e000ed00 	.word	0xe000ed00

00001ecc <tz_nonsecure_system_reset_req_block>:

void tz_nonsecure_system_reset_req_block(int block)
{
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    1ecc:	4a08      	ldr	r2, [pc, #32]	; (1ef0 <tz_nonsecure_system_reset_req_block+0x24>)
    1ece:	68d3      	ldr	r3, [r2, #12]
	if (block) {
    1ed0:	b140      	cbz	r0, 1ee4 <tz_nonsecure_system_reset_req_block+0x18>
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    1ed2:	b29b      	uxth	r3, r3
		aircr_payload |= SCB_AIRCR_SYSRESETREQS_Msk;
    1ed4:	f043 0308 	orr.w	r3, r3, #8
	} else {
		aircr_payload &= ~(SCB_AIRCR_SYSRESETREQS_Msk);
	}
	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)
			& SCB_AIRCR_VECTKEY_Msk)
		| aircr_payload;
    1ed8:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
    1edc:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)
    1ee0:	60d3      	str	r3, [r2, #12]
}
    1ee2:	4770      	bx	lr
		aircr_payload &= ~(SCB_AIRCR_SYSRESETREQS_Msk);
    1ee4:	f023 0308 	bic.w	r3, r3, #8
    1ee8:	041b      	lsls	r3, r3, #16
    1eea:	0c1b      	lsrs	r3, r3, #16
    1eec:	e7f4      	b.n	1ed8 <tz_nonsecure_system_reset_req_block+0xc>
    1eee:	bf00      	nop
    1ef0:	e000ed00 	.word	0xe000ed00

00001ef4 <tz_nonsecure_fpu_access_enable>:

#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
void tz_nonsecure_fpu_access_enable(void)
{
	SCB->NSACR |=
    1ef4:	4a03      	ldr	r2, [pc, #12]	; (1f04 <tz_nonsecure_fpu_access_enable+0x10>)
    1ef6:	f8d2 308c 	ldr.w	r3, [r2, #140]	; 0x8c
    1efa:	f443 6340 	orr.w	r3, r3, #3072	; 0xc00
    1efe:	f8c2 308c 	str.w	r3, [r2, #140]	; 0x8c
		(1UL << SCB_NSACR_CP10_Pos) | (1UL << SCB_NSACR_CP11_Pos);
}
    1f02:	4770      	bx	lr
    1f04:	e000ed00 	.word	0xe000ed00

00001f08 <tz_sau_configure>:
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */

void tz_sau_configure(int enable, int allns)
{
	if (enable) {
    1f08:	4b08      	ldr	r3, [pc, #32]	; (1f2c <tz_sau_configure+0x24>)
  \brief   Enable SAU
  \details Enables the Security Attribution Unit (SAU).
 */
__STATIC_INLINE void TZ_SAU_Enable(void)
{
    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
    1f0a:	681a      	ldr	r2, [r3, #0]
    1f0c:	b118      	cbz	r0, 1f16 <tz_sau_configure+0xe>
    1f0e:	f042 0201 	orr.w	r2, r2, #1
	} else {
		TZ_SAU_Disable();
		if (allns) {
			SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
		} else {
			SAU->CTRL &= ~(SAU_CTRL_ALLNS_Msk);
    1f12:	601a      	str	r2, [r3, #0]
		}
	}
}
    1f14:	4770      	bx	lr
  \brief   Disable SAU
  \details Disables the Security Attribution Unit (SAU).
 */
__STATIC_INLINE void TZ_SAU_Disable(void)
{
    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
    1f16:	f022 0201 	bic.w	r2, r2, #1
    1f1a:	601a      	str	r2, [r3, #0]
			SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
    1f1c:	681a      	ldr	r2, [r3, #0]
		if (allns) {
    1f1e:	b111      	cbz	r1, 1f26 <tz_sau_configure+0x1e>
			SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
    1f20:	f042 0202 	orr.w	r2, r2, #2
    1f24:	e7f5      	b.n	1f12 <tz_sau_configure+0xa>
			SAU->CTRL &= ~(SAU_CTRL_ALLNS_Msk);
    1f26:	f022 0202 	bic.w	r2, r2, #2
    1f2a:	e7f2      	b.n	1f12 <tz_sau_configure+0xa>
    1f2c:	e000edd0 	.word	0xe000edd0

00001f30 <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
    1f30:	4b01      	ldr	r3, [pc, #4]	; (1f38 <__stdout_hook_install+0x8>)
    1f32:	6018      	str	r0, [r3, #0]
}
    1f34:	4770      	bx	lr
    1f36:	bf00      	nop
    1f38:	20000024 	.word	0x20000024

00001f3c <uarte_nrfx_configure>:
	return 0;
}

static int uarte_nrfx_configure(const struct device *dev,
				const struct uart_config *cfg)
{
    1f3c:	b5f0      	push	{r4, r5, r6, r7, lr}
	nrf_uarte_config_t uarte_cfg;

#if defined(UARTE_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
    1f3e:	794b      	ldrb	r3, [r1, #5]
    1f40:	2b01      	cmp	r3, #1
    1f42:	d029      	beq.n	1f98 <uarte_nrfx_configure+0x5c>
    1f44:	2b03      	cmp	r3, #3
    1f46:	d124      	bne.n	1f92 <uarte_nrfx_configure+0x56>
	case UART_CFG_STOP_BITS_1:
		uarte_cfg.stop = NRF_UARTE_STOP_ONE;
		break;
	case UART_CFG_STOP_BITS_2:
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
    1f48:	2610      	movs	r6, #16
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    1f4a:	798b      	ldrb	r3, [r1, #6]
    1f4c:	2b03      	cmp	r3, #3
    1f4e:	d120      	bne.n	1f92 <uarte_nrfx_configure+0x56>
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
    1f50:	79cc      	ldrb	r4, [r1, #7]
    1f52:	b124      	cbz	r4, 1f5e <uarte_nrfx_configure+0x22>
    1f54:	2c01      	cmp	r4, #1
    1f56:	d11c      	bne.n	1f92 <uarte_nrfx_configure+0x56>
	case UART_CFG_FLOW_CTRL_NONE:
		uarte_cfg.hwfc = NRF_UARTE_HWFC_DISABLED;
		break;
	case UART_CFG_FLOW_CTRL_RTS_CTS:
		if (get_dev_config(dev)->rts_cts_pins_set) {
    1f58:	6843      	ldr	r3, [r0, #4]
    1f5a:	791b      	ldrb	r3, [r3, #4]
    1f5c:	b1cb      	cbz	r3, 1f92 <uarte_nrfx_configure+0x56>
	}

#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
    1f5e:	790a      	ldrb	r2, [r1, #4]
    1f60:	b112      	cbz	r2, 1f68 <uarte_nrfx_configure+0x2c>
    1f62:	2a02      	cmp	r2, #2
    1f64:	d115      	bne.n	1f92 <uarte_nrfx_configure+0x56>
	case UART_CFG_PARITY_NONE:
		uarte_cfg.parity = NRF_UARTE_PARITY_EXCLUDED;
		break;
	case UART_CFG_PARITY_EVEN:
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
    1f66:	220e      	movs	r2, #14
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
    1f68:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    1f6a:	6845      	ldr	r5, [r0, #4]
	switch (baudrate) {
    1f6c:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    1f70:	682d      	ldr	r5, [r5, #0]
	switch (baudrate) {
    1f72:	d065      	beq.n	2040 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x40>
    1f74:	d82d      	bhi.n	1fd2 <uarte_nrfx_configure+0x96>
    1f76:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    1f7a:	d064      	beq.n	2046 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x46>
    1f7c:	d816      	bhi.n	1fac <uarte_nrfx_configure+0x70>
    1f7e:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    1f82:	d062      	beq.n	204a <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x4a>
    1f84:	d80a      	bhi.n	1f9c <uarte_nrfx_configure+0x60>
    1f86:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    1f8a:	d061      	beq.n	2050 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x50>
    1f8c:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    1f90:	d061      	beq.n	2056 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x56>
    1f92:	f06f 0022 	mvn.w	r0, #34	; 0x22
    1f96:	e052      	b.n	203e <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x3e>
	switch (cfg->stop_bits) {
    1f98:	2600      	movs	r6, #0
    1f9a:	e7d6      	b.n	1f4a <uarte_nrfx_configure+0xe>
	switch (baudrate) {
    1f9c:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    1fa0:	d05c      	beq.n	205c <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x5c>
    1fa2:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    1fa6:	d1f4      	bne.n	1f92 <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    1fa8:	4b37      	ldr	r3, [pc, #220]	; (2088 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x88>)
    1faa:	e03c      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
	switch (baudrate) {
    1fac:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    1fb0:	d057      	beq.n	2062 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x62>
    1fb2:	d807      	bhi.n	1fc4 <uarte_nrfx_configure+0x88>
    1fb4:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    1fb8:	d055      	beq.n	2066 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x66>
    1fba:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    1fbe:	d1e8      	bne.n	1f92 <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    1fc0:	4b32      	ldr	r3, [pc, #200]	; (208c <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x8c>)
    1fc2:	e030      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
	switch (baudrate) {
    1fc4:	f647 2712 	movw	r7, #31250	; 0x7a12
    1fc8:	42bb      	cmp	r3, r7
    1fca:	d1e2      	bne.n	1f92 <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    1fcc:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    1fd0:	e029      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
	switch (baudrate) {
    1fd2:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    1fd6:	d048      	beq.n	206a <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x6a>
    1fd8:	d813      	bhi.n	2002 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x2>
    1fda:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    1fde:	d047      	beq.n	2070 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x70>
    1fe0:	d809      	bhi.n	1ff6 <uarte_nrfx_configure+0xba>
    1fe2:	f64d 27c0 	movw	r7, #56000	; 0xdac0
    1fe6:	42bb      	cmp	r3, r7
    1fe8:	d044      	beq.n	2074 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x74>
    1fea:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    1fee:	d1d0      	bne.n	1f92 <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    1ff0:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    1ff4:	e017      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
	switch (baudrate) {
    1ff6:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    1ffa:	d1ca      	bne.n	1f92 <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    1ffc:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    2000:	e011      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
	switch (baudrate) {
    2002:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    2006:	d038      	beq.n	207a <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x7a>
    2008:	d808      	bhi.n	201c <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x1c>
    200a:	4f21      	ldr	r7, [pc, #132]	; (2090 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x90>)
    200c:	42bb      	cmp	r3, r7
    200e:	d037      	beq.n	2080 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x80>
    2010:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    2014:	d1bd      	bne.n	1f92 <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    2016:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    201a:	e004      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
	switch (baudrate) {
    201c:	4f1d      	ldr	r7, [pc, #116]	; (2094 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x94>)
    201e:	42bb      	cmp	r3, r7
    2020:	d1b7      	bne.n	1f92 <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    2022:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    2026:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
		return -ENOTSUP;
	}

	nrf_uarte_configure(get_uarte_instance(dev), &uarte_cfg);

	get_dev_data(dev)->uart_config = *cfg;
    202a:	68c3      	ldr	r3, [r0, #12]
                    | (uint32_t)p_cfg->hwfc;
    202c:	4334      	orrs	r4, r6
    202e:	4322      	orrs	r2, r4
    2030:	3304      	adds	r3, #4
    2032:	c903      	ldmia	r1, {r0, r1}
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    2034:	f8c5 256c 	str.w	r2, [r5, #1388]	; 0x56c
    2038:	e883 0003 	stmia.w	r3, {r0, r1}

	return 0;
    203c:	2000      	movs	r0, #0
}
    203e:	bdf0      	pop	{r4, r5, r6, r7, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    2040:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    2044:	e7ef      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    2046:	4b14      	ldr	r3, [pc, #80]	; (2098 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x98>)
    2048:	e7ed      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    204a:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    204e:	e7ea      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
		nrf_baudrate = 0x00014000;
    2050:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    2054:	e7e7      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
	switch (baudrate) {
    2056:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    205a:	e7e4      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    205c:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    2060:	e7e1      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    2062:	4b0e      	ldr	r3, [pc, #56]	; (209c <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x9c>)
    2064:	e7df      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    2066:	4b0e      	ldr	r3, [pc, #56]	; (20a0 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0xa0>)
    2068:	e7dd      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    206a:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    206e:	e7da      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    2070:	4b0c      	ldr	r3, [pc, #48]	; (20a4 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0xa4>)
    2072:	e7d8      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    2074:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    2078:	e7d5      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    207a:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    207e:	e7d2      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    2080:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    2084:	e7cf      	b.n	2026 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x26>
    2086:	bf00      	nop
    2088:	0013b000 	.word	0x0013b000
    208c:	004ea000 	.word	0x004ea000
    2090:	0003d090 	.word	0x0003d090
    2094:	000f4240 	.word	0x000f4240
    2098:	00275000 	.word	0x00275000
    209c:	0075c000 	.word	0x0075c000
    20a0:	003af000 	.word	0x003af000
    20a4:	013a9000 	.word	0x013a9000

000020a8 <uarte_instance_init.isra.0>:
	.irq_update		= uarte_nrfx_irq_update,
	.irq_callback_set	= uarte_nrfx_irq_callback_set,
#endif /* UARTE_INTERRUPT_DRIVEN */
};

static int uarte_instance_init(const struct device *dev,
    20a8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}

	nrf_uarte_disable(uarte);

	data->dev = dev;

	nrf_gpio_pin_write(config->pseltxd, 1);
    20aa:	680f      	ldr	r7, [r1, #0]
static int uarte_instance_init(const struct device *dev,
    20ac:	460d      	mov	r5, r1

NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
{
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);

    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    20ae:	2101      	movs	r1, #1
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    20b0:	f04f 0c00 	mov.w	ip, #0
	return config->uarte_regs;
    20b4:	6843      	ldr	r3, [r0, #4]
	struct uarte_nrfx_data *data = get_dev_data(dev);
    20b6:	68c6      	ldr	r6, [r0, #12]
	return config->uarte_regs;
    20b8:	681c      	ldr	r4, [r3, #0]
}

NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;
    20ba:	f007 021f 	and.w	r2, r7, #31
    p_reg->OUTSET = set_mask;
    20be:	4b25      	ldr	r3, [pc, #148]	; (2154 <uarte_instance_init.isra.0+0xac>)
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    20c0:	4091      	lsls	r1, r2
    20c2:	f8c4 c500 	str.w	ip, [r4, #1280]	; 0x500
	data->dev = dev;
    20c6:	6030      	str	r0, [r6, #0]
    p_reg->OUTSET = set_mask;
    20c8:	6099      	str	r1, [r3, #8]
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    20ca:	2103      	movs	r1, #3
    20cc:	3280      	adds	r2, #128	; 0x80
    20ce:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
	nrf_gpio_cfg_output(config->pseltxd);

	if (config->pselrxd !=  NRF_UARTE_PSEL_DISCONNECTED) {
    20d2:	686a      	ldr	r2, [r5, #4]
    20d4:	1c51      	adds	r1, r2, #1
    *p_pin = pin_number & 0x1F;
    20d6:	bf1e      	ittt	ne
    20d8:	f002 011f 	andne.w	r1, r2, #31
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    20dc:	3180      	addne	r1, #128	; 0x80
    20de:	f843 c021 	strne.w	ip, [r3, r1, lsl #2]
		nrf_gpio_cfg_input(config->pselrxd, NRF_GPIO_PIN_NOPULL);
	}

	nrf_uarte_txrx_pins_set(uarte, config->pseltxd, config->pselrxd);

	if (config->pselcts != NRF_UARTE_PSEL_DISCONNECTED) {
    20e2:	68a9      	ldr	r1, [r5, #8]
    p_reg->PSEL.TXD = pseltxd;
    20e4:	f8c4 750c 	str.w	r7, [r4, #1292]	; 0x50c
    20e8:	1c4f      	adds	r7, r1, #1
    20ea:	bf18      	it	ne
    20ec:	2700      	movne	r7, #0
    p_reg->PSEL.RXD = pselrxd;
    20ee:	f8c4 2514 	str.w	r2, [r4, #1300]	; 0x514
    *p_pin = pin_number & 0x1F;
    20f2:	bf1e      	ittt	ne
    20f4:	f001 021f 	andne.w	r2, r1, #31
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    20f8:	3280      	addne	r2, #128	; 0x80
    20fa:	f843 7022 	strne.w	r7, [r3, r2, lsl #2]
		nrf_gpio_cfg_input(config->pselcts, NRF_GPIO_PIN_NOPULL);
	}

	if (config->pselrts != NRF_UARTE_PSEL_DISCONNECTED) {
    20fe:	68ef      	ldr	r7, [r5, #12]
    2100:	1c7a      	adds	r2, r7, #1
    2102:	d00c      	beq.n	211e <uarte_instance_init.isra.0+0x76>
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2104:	f04f 0c01 	mov.w	ip, #1
    *p_pin = pin_number & 0x1F;
    2108:	f007 021f 	and.w	r2, r7, #31
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    210c:	fa0c fc02 	lsl.w	ip, ip, r2
    p_reg->OUTSET = set_mask;
    2110:	f8c3 c008 	str.w	ip, [r3, #8]
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    2114:	f04f 0c03 	mov.w	ip, #3
    2118:	3280      	adds	r2, #128	; 0x80
    211a:	f843 c022 	str.w	ip, [r3, r2, lsl #2]
    p_reg->PSEL.RTS = pselrts;
    211e:	f8c4 7508 	str.w	r7, [r4, #1288]	; 0x508
    p_reg->PSEL.CTS = pselcts;
    2122:	f8c4 1510 	str.w	r1, [r4, #1296]	; 0x510
		nrf_gpio_cfg_output(config->pselrts);
	}

	nrf_uarte_hwfc_pins_set(uarte, config->pselrts, config->pselcts);

	err = uarte_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
    2126:	68c1      	ldr	r1, [r0, #12]
    2128:	3104      	adds	r1, #4
    212a:	f7ff ff07 	bl	1f3c <uarte_nrfx_configure>
	if (err) {
    212e:	b980      	cbnz	r0, 2152 <uarte_instance_init.isra.0+0xaa>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    2130:	2308      	movs	r3, #8
    2132:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
	}
#endif
	/* Enable receiver and transmitter */
	nrf_uarte_enable(uarte);

	if (config->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
    2136:	686b      	ldr	r3, [r5, #4]
    2138:	3301      	adds	r3, #1
    213a:	d00a      	beq.n	2152 <uarte_instance_init.isra.0+0xaa>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    213c:	f8c4 0110 	str.w	r0, [r4, #272]	; 0x110
    2140:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110
NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    p_reg->RXD.MAXCNT = length;
    2144:	2301      	movs	r3, #1
		nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);

		nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
    2146:	3610      	adds	r6, #16
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    2148:	f8c4 6534 	str.w	r6, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    214c:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2150:	6023      	str	r3, [r4, #0]
		/* switch off transmitter to save an energy */
		nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPTX);
	}
#endif
	return 0;
}
    2152:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    2154:	50842500 	.word	0x50842500

00002158 <uarte_0_init>:
				.tx_buffer = uarte##idx##_tx_buffer,	       \
				.tx_buff_size = sizeof(uarte##idx##_tx_buffer),\
			};))

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
    2158:	b530      	push	{r4, r5, lr}
    215a:	b085      	sub	sp, #20
    215c:	4605      	mov	r5, r0
    215e:	466c      	mov	r4, sp
    2160:	4b04      	ldr	r3, [pc, #16]	; (2174 <uarte_0_init+0x1c>)
    2162:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    2164:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
    2168:	4621      	mov	r1, r4
    216a:	4628      	mov	r0, r5
    216c:	f7ff ff9c 	bl	20a8 <uarte_instance_init.isra.0>
    2170:	b005      	add	sp, #20
    2172:	bd30      	pop	{r4, r5, pc}
    2174:	000050fc 	.word	0x000050fc

00002178 <uarte_1_init>:
#endif

#ifdef CONFIG_UART_1_NRF_UARTE
UART_NRF_UARTE_DEVICE(1);
    2178:	b530      	push	{r4, r5, lr}
    217a:	b085      	sub	sp, #20
    217c:	4605      	mov	r5, r0
    217e:	466c      	mov	r4, sp
    2180:	4b04      	ldr	r3, [pc, #16]	; (2194 <uarte_1_init+0x1c>)
    2182:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    2184:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
    2188:	4621      	mov	r1, r4
    218a:	4628      	mov	r0, r5
    218c:	f7ff ff8c 	bl	20a8 <uarte_instance_init.isra.0>
    2190:	b005      	add	sp, #20
    2192:	bd30      	pop	{r4, r5, pc}
    2194:	0000510c 	.word	0x0000510c

00002198 <check_ext_api_requests>:
	}
};
#endif

static int check_ext_api_requests(const struct device *dev)
{
    2198:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
	(void)dev;

	const struct fw_info_ext_api_request *ext_api_req =
			skip_ext_apis(&m_firmware_info);

	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    219c:	2500      	movs	r5, #0
			skip_ext_apis(&m_firmware_info);
    219e:	4c21      	ldr	r4, [pc, #132]	; (2224 <check_ext_api_requests+0x8c>)
	const uint32_t ext_api_magic[] = {EXT_API_MAGIC};
    21a0:	4e21      	ldr	r6, [pc, #132]	; (2228 <check_ext_api_requests+0x90>)
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    21a2:	f854 8c04 	ldr.w	r8, [r4, #-4]
			/* EXT_API hard requirement not met. */
			printk("ERROR: Cannot fulfill EXT_API request.\r\n");
			k_panic();
		} else {
			/* EXT_API soft requirement not met. */
			printk("WARNING: Optional EXT_API request not "
    21a6:	f8df 9088 	ldr.w	r9, [pc, #136]	; 2230 <check_ext_api_requests+0x98>
{
    21aa:	b085      	sub	sp, #20
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    21ac:	45a8      	cmp	r8, r5
    21ae:	d803      	bhi.n	21b8 <check_ext_api_requests+0x20>
		}
		ADVANCE_EXT_API_REQ(ext_api_req);
	}

	return 0;
}
    21b0:	2000      	movs	r0, #0
    21b2:	b005      	add	sp, #20
    21b4:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
		if (fw_info_ext_api_check((uint32_t)*(ext_api_req->ext_api))
    21b8:	6a63      	ldr	r3, [r4, #36]	; 0x24
    21ba:	e896 0007 	ldmia.w	r6, {r0, r1, r2}
    21be:	681f      	ldr	r7, [r3, #0]
    21c0:	ab01      	add	r3, sp, #4
    21c2:	e883 0007 	stmia.w	r3, {r0, r1, r2}
	if (memcmp(ext_api->magic, ext_api_magic, CONFIG_FW_INFO_MAGIC_LEN)
    21c6:	220c      	movs	r2, #12
    21c8:	4619      	mov	r1, r3
    21ca:	4638      	mov	r0, r7
    21cc:	f002 fc22 	bl	4a14 <memcmp>
    21d0:	b990      	cbnz	r0, 21f8 <check_ext_api_requests+0x60>
    21d2:	b18f      	cbz	r7, 21f8 <check_ext_api_requests+0x60>
			&& ext_api_satisfies_req(*(ext_api_req->ext_api),
    21d4:	6a63      	ldr	r3, [r4, #36]	; 0x24
	const uint32_t req_id = ext_api_req->request.ext_api_id;
    21d6:	6921      	ldr	r1, [r4, #16]
			&& ext_api_satisfies_req(*(ext_api_req->ext_api),
    21d8:	681b      	ldr	r3, [r3, #0]
	return ((ext_api->ext_api_id == req_id)
    21da:	691a      	ldr	r2, [r3, #16]
		&& ((ext_api->ext_api_flags & req_flags) == req_flags));
    21dc:	4291      	cmp	r1, r2
    21de:	d10b      	bne.n	21f8 <check_ext_api_requests+0x60>
		&&  (ext_api->ext_api_version >= req_min_version)
    21e0:	699a      	ldr	r2, [r3, #24]
	const uint32_t req_min_version = ext_api_req->request.ext_api_version;
    21e2:	69a1      	ldr	r1, [r4, #24]
		&&  (ext_api->ext_api_version >= req_min_version)
    21e4:	4291      	cmp	r1, r2
    21e6:	d807      	bhi.n	21f8 <check_ext_api_requests+0x60>
	const uint32_t req_max_version = ext_api_req->ext_api_max_version;
    21e8:	69e1      	ldr	r1, [r4, #28]
		&&  (ext_api->ext_api_version <  req_max_version)
    21ea:	4291      	cmp	r1, r2
    21ec:	d904      	bls.n	21f8 <check_ext_api_requests+0x60>
	const uint32_t req_flags = ext_api_req->request.ext_api_flags;
    21ee:	6962      	ldr	r2, [r4, #20]
		&& ((ext_api->ext_api_flags & req_flags) == req_flags));
    21f0:	695b      	ldr	r3, [r3, #20]
    21f2:	ea32 0303 	bics.w	r3, r2, r3
    21f6:	d00a      	beq.n	220e <check_ext_api_requests+0x76>
		} else if (ext_api_req->required) {
    21f8:	6a27      	ldr	r7, [r4, #32]
    21fa:	b167      	cbz	r7, 2216 <check_ext_api_requests+0x7e>
			printk("ERROR: Cannot fulfill EXT_API request.\r\n");
    21fc:	480b      	ldr	r0, [pc, #44]	; (222c <check_ext_api_requests+0x94>)
    21fe:	f002 f905 	bl	440c <printk>
			k_panic();
    2202:	4040      	eors	r0, r0
    2204:	f380 8811 	msr	BASEPRI, r0
    2208:	f04f 0004 	mov.w	r0, #4
    220c:	df02      	svc	2
		ADVANCE_EXT_API_REQ(ext_api_req);
    220e:	68e3      	ldr	r3, [r4, #12]
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2210:	3501      	adds	r5, #1
		ADVANCE_EXT_API_REQ(ext_api_req);
    2212:	441c      	add	r4, r3
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2214:	e7ca      	b.n	21ac <check_ext_api_requests+0x14>
			printk("WARNING: Optional EXT_API request not "
    2216:	4648      	mov	r0, r9
    2218:	f002 f8f8 	bl	440c <printk>
			*ext_api_req->ext_api = NULL;
    221c:	6a63      	ldr	r3, [r4, #36]	; 0x24
    221e:	601f      	str	r7, [r3, #0]
    2220:	e7f5      	b.n	220e <check_ext_api_requests+0x76>
    2222:	bf00      	nop
    2224:	0000023c 	.word	0x0000023c
    2228:	0000511c 	.word	0x0000511c
    222c:	0000573c 	.word	0x0000573c
    2230:	00005765 	.word	0x00005765

00002234 <nrf91_errata_14>:
    #ifndef NRF91_SERIES
        return false;
    #else
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
            uint32_t var2 = *(uint32_t *)0x00FF0134ul;
    2234:	4b05      	ldr	r3, [pc, #20]	; (224c <nrf91_errata_14+0x18>)
    2236:	6818      	ldr	r0, [r3, #0]
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    2238:	3b04      	subs	r3, #4
        #endif
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            if (var1 == 0x09)
    223a:	681b      	ldr	r3, [r3, #0]
    223c:	2b09      	cmp	r3, #9
    223e:	d103      	bne.n	2248 <nrf91_errata_14+0x14>
            {
                switch(var2)
    2240:	1e43      	subs	r3, r0, #1
    2242:	4258      	negs	r0, r3
    2244:	4158      	adcs	r0, r3
    2246:	4770      	bx	lr
                    default:
                        return false;
                }
            }
        #endif
        return false;
    2248:	2000      	movs	r0, #0
    #endif
}
    224a:	4770      	bx	lr
    224c:	00ff0134 	.word	0x00ff0134

00002250 <SystemInit>:
        /* Perform Secure-mode initialization routines. */

        /* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled.
        * Nordic SPU should handle Secure Attribution tasks */
        #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
          SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
    2250:	4a4f      	ldr	r2, [pc, #316]	; (2390 <SystemInit+0x140>)
{
    2252:	b508      	push	{r3, lr}
          SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
    2254:	6813      	ldr	r3, [r2, #0]
    2256:	f043 0302 	orr.w	r3, r3, #2
    225a:	6013      	str	r3, [r2, #0]
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    225c:	4b4d      	ldr	r3, [pc, #308]	; (2394 <SystemInit+0x144>)
            if (var1 == 0x09)
    225e:	681b      	ldr	r3, [r3, #0]
    2260:	2b09      	cmp	r3, #9
        #endif
        
        /* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_6()){
            NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos);
    2262:	bf01      	itttt	eq
    2264:	f04f 2350 	moveq.w	r3, #1342197760	; 0x50005000
    2268:	2200      	moveq	r2, #0
    226a:	f8c3 2114 	streq.w	r2, [r3, #276]	; 0x114
            NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos);
    226e:	f8c3 2118 	streq.w	r2, [r3, #280]	; 0x118
        }

        /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_14()){
    2272:	f7ff ffdf 	bl	2234 <nrf91_errata_14>
    2276:	b130      	cbz	r0, 2286 <SystemInit+0x36>
            *((volatile uint32_t *)0x50004A38) = 0x01ul;
    2278:	2301      	movs	r3, #1
    227a:	4a47      	ldr	r2, [pc, #284]	; (2398 <SystemInit+0x148>)
    227c:	6013      	str	r3, [r2, #0]
            NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
    227e:	f6a2 2238 	subw	r2, r2, #2616	; 0xa38
    2282:	f8c2 3578 	str.w	r3, [r2, #1400]	; 0x578
{
    #ifndef NRF91_SERIES
        return false;
    #else
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    2286:	4b43      	ldr	r3, [pc, #268]	; (2394 <SystemInit+0x144>)
            uint32_t var2 = *(uint32_t *)0x00FF0134ul;
        #endif
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            if (var1 == 0x09)
    2288:	681b      	ldr	r3, [r3, #0]
    228a:	2b09      	cmp	r3, #9
    228c:	d107      	bne.n	229e <SystemInit+0x4e>
            uint32_t var2 = *(uint32_t *)0x00FF0134ul;
    228e:	4b43      	ldr	r3, [pc, #268]	; (239c <SystemInit+0x14c>)
            {
                switch(var2)
    2290:	681b      	ldr	r3, [r3, #0]
    2292:	2b01      	cmp	r3, #1
        }

        /* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_15()){
            NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
    2294:	bf1e      	ittt	ne
    2296:	2201      	movne	r2, #1
    2298:	4b41      	ldrne	r3, [pc, #260]	; (23a0 <SystemInit+0x150>)
    229a:	f8c3 2578 	strne.w	r2, [r3, #1400]	; 0x578
        }

        /* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_20()){
    229e:	f7ff ffc9 	bl	2234 <nrf91_errata_14>
    22a2:	b110      	cbz	r0, 22aa <SystemInit+0x5a>
            *((volatile uint32_t *)0x5003AEE4) = 0xE;
    22a4:	220e      	movs	r2, #14
    22a6:	4b3f      	ldr	r3, [pc, #252]	; (23a4 <SystemInit+0x154>)
    22a8:	601a      	str	r2, [r3, #0]
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    22aa:	4b3a      	ldr	r3, [pc, #232]	; (2394 <SystemInit+0x144>)
            if (var1 == 0x09)
    22ac:	681b      	ldr	r3, [r3, #0]
    22ae:	2b09      	cmp	r3, #9
    22b0:	d104      	bne.n	22bc <SystemInit+0x6c>
        }

        /* Workaround for Errata 31 "XOSC32k Startup Failure" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_31()){
            *((volatile uint32_t *)0x5000470Cul) = 0x0;
    22b2:	2200      	movs	r2, #0
    22b4:	4b3c      	ldr	r3, [pc, #240]	; (23a8 <SystemInit+0x158>)
    22b6:	601a      	str	r2, [r3, #0]
            *((volatile uint32_t *)0x50004710ul) = 0x1;
    22b8:	2201      	movs	r2, #1
    22ba:	605a      	str	r2, [r3, #4]
{
    22bc:	2200      	movs	r2, #0
    22be:	00d3      	lsls	r3, r2, #3
    22c0:	f503 037f 	add.w	r3, r3, #16711680	; 0xff0000
        }

        /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
         until one ADDR is not initialized. */
        uint32_t index = 0;
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    22c4:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
    22c8:	3101      	adds	r1, #1
    22ca:	d008      	beq.n	22de <SystemInit+0x8e>
          #if defined ( __ICCARM__ )
              #pragma diag_suppress=Pa082
          #endif
          *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
    22cc:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    22d0:	3201      	adds	r2, #1
          *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
    22d2:	f8d3 3304 	ldr.w	r3, [r3, #772]	; 0x304
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    22d6:	f5b2 7f80 	cmp.w	r2, #256	; 0x100
          *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
    22da:	600b      	str	r3, [r1, #0]
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    22dc:	d1ef      	bne.n	22be <SystemInit+0x6e>
    }
    
    
    bool uicr_HFXOSRC_erased()
    {
        if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) {
    22de:	4b33      	ldr	r3, [pc, #204]	; (23ac <SystemInit+0x15c>)
    22e0:	69da      	ldr	r2, [r3, #28]
        if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) {
    22e2:	07d1      	lsls	r1, r2, #31
    22e4:	d53b      	bpl.n	235e <SystemInit+0x10e>
          while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    22e6:	4b32      	ldr	r3, [pc, #200]	; (23b0 <SystemInit+0x160>)
    22e8:	4619      	mov	r1, r3
    22ea:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    22ee:	2a01      	cmp	r2, #1
    22f0:	d1fb      	bne.n	22ea <SystemInit+0x9a>
          NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen;
    22f2:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
          while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    22f6:	f8d1 3400 	ldr.w	r3, [r1, #1024]	; 0x400
    22fa:	2b01      	cmp	r3, #1
    22fc:	d1fb      	bne.n	22f6 <SystemInit+0xa6>
        if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) {
    22fe:	4b2b      	ldr	r3, [pc, #172]	; (23ac <SystemInit+0x15c>)
    2300:	69da      	ldr	r2, [r3, #28]
          if (uicr_HFXOSRC_erased()){
    2302:	07d2      	lsls	r2, r2, #31
    2304:	d508      	bpl.n	2318 <SystemInit+0xc8>
            uicr_erased_value = NRF_UICR_S->HFXOSRC;
    2306:	69da      	ldr	r2, [r3, #28]
            while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2308:	4929      	ldr	r1, [pc, #164]	; (23b0 <SystemInit+0x160>)
            uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO;
    230a:	f022 0201 	bic.w	r2, r2, #1
            NRF_UICR_S->HFXOSRC = uicr_new_value;
    230e:	61da      	str	r2, [r3, #28]
            while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2310:	f8d1 2400 	ldr.w	r2, [r1, #1024]	; 0x400
    2314:	2a01      	cmp	r2, #1
    2316:	d1fb      	bne.n	2310 <SystemInit+0xc0>
        if (NRF_UICR_S->HFXOCNT == 0xFFFFFFFFul) {
    2318:	6a1a      	ldr	r2, [r3, #32]
    231a:	3201      	adds	r2, #1
    231c:	d10a      	bne.n	2334 <SystemInit+0xe4>
            uicr_erased_value = NRF_UICR_S->HFXOCNT;
    231e:	6a1a      	ldr	r2, [r3, #32]
            uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20;
    2320:	f022 02ff 	bic.w	r2, r2, #255	; 0xff
    2324:	f042 0220 	orr.w	r2, r2, #32
            NRF_UICR_S->HFXOCNT = uicr_new_value;
    2328:	621a      	str	r2, [r3, #32]
            while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    232a:	4a21      	ldr	r2, [pc, #132]	; (23b0 <SystemInit+0x160>)
    232c:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    2330:	2b01      	cmp	r3, #1
    2332:	d1fb      	bne.n	232c <SystemInit+0xdc>
          NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren;
    2334:	2200      	movs	r2, #0
    2336:	4b1e      	ldr	r3, [pc, #120]	; (23b0 <SystemInit+0x160>)
    2338:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
          while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    233c:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    2340:	2a01      	cmp	r2, #1
    2342:	d1fb      	bne.n	233c <SystemInit+0xec>
  __ASM volatile ("dsb 0xF":::"memory");
    2344:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2348:	491a      	ldr	r1, [pc, #104]	; (23b4 <SystemInit+0x164>)
    234a:	4b1b      	ldr	r3, [pc, #108]	; (23b8 <SystemInit+0x168>)
    234c:	68ca      	ldr	r2, [r1, #12]
    234e:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2352:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    2354:	60cb      	str	r3, [r1, #12]
    2356:	f3bf 8f4f 	dsb	sy
    __NOP();
    235a:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    235c:	e7fd      	b.n	235a <SystemInit+0x10a>
        if (NRF_UICR_S->HFXOCNT == 0xFFFFFFFFul) {
    235e:	6a1b      	ldr	r3, [r3, #32]
    2360:	3301      	adds	r3, #1
    2362:	d0c0      	beq.n	22e6 <SystemInit+0x96>
        SCB->NSACR |= (3UL << 10);
    2364:	4b13      	ldr	r3, [pc, #76]	; (23b4 <SystemInit+0x164>)
    2366:	f8d3 208c 	ldr.w	r2, [r3, #140]	; 0x8c
    236a:	f442 6240 	orr.w	r2, r2, #3072	; 0xc00
    236e:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
      SCB->CPACR |= (3UL << 20) | (3UL << 22);
    2372:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    2376:	f442 0270 	orr.w	r2, r2, #15728640	; 0xf00000
    237a:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    237e:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2382:	f3bf 8f6f 	isb	sy
    SystemCoreClock = __SYSTEM_CLOCK;
    2386:	4b0d      	ldr	r3, [pc, #52]	; (23bc <SystemInit+0x16c>)
    2388:	4a0d      	ldr	r2, [pc, #52]	; (23c0 <SystemInit+0x170>)
    238a:	601a      	str	r2, [r3, #0]
}
    238c:	bd08      	pop	{r3, pc}
    238e:	bf00      	nop
    2390:	e000edd0 	.word	0xe000edd0
    2394:	00ff0130 	.word	0x00ff0130
    2398:	50004a38 	.word	0x50004a38
    239c:	00ff0134 	.word	0x00ff0134
    23a0:	50004000 	.word	0x50004000
    23a4:	5003aee4 	.word	0x5003aee4
    23a8:	5000470c 	.word	0x5000470c
    23ac:	00ff8000 	.word	0x00ff8000
    23b0:	50039000 	.word	0x50039000
    23b4:	e000ed00 	.word	0xe000ed00
    23b8:	05fa0004 	.word	0x05fa0004
    23bc:	20000050 	.word	0x20000050
    23c0:	03d09000 	.word	0x03d09000

000023c4 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    23c4:	4b04      	ldr	r3, [pc, #16]	; (23d8 <nrfx_clock_init+0x14>)
    23c6:	791a      	ldrb	r2, [r3, #4]
    23c8:	b922      	cbnz	r2, 23d4 <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    23ca:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    23cc:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    23ce:	711a      	strb	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    23d0:	4802      	ldr	r0, [pc, #8]	; (23dc <nrfx_clock_init+0x18>)
    23d2:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    23d4:	4802      	ldr	r0, [pc, #8]	; (23e0 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    23d6:	4770      	bx	lr
    23d8:	20000808 	.word	0x20000808
    23dc:	0bad0000 	.word	0x0bad0000
    23e0:	0bad000c 	.word	0x0bad000c

000023e4 <nrfx_clock_start>:
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    23e4:	b110      	cbz	r0, 23ec <nrfx_clock_start+0x8>
    23e6:	2801      	cmp	r0, #1
    23e8:	d020      	beq.n	242c <nrfx_clock_start+0x48>
    23ea:	4770      	bx	lr
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    23ec:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    23f0:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    23f4:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    23f8:	03c9      	lsls	r1, r1, #15
    23fa:	d511      	bpl.n	2420 <nrfx_clock_start+0x3c>
    {
        case NRF_CLOCK_DOMAIN_LFCLK:
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
            {
                nrf_clock_lfclk_t lfclksrc;
                if (nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc) &&
    23fc:	f003 0303 	and.w	r3, r3, #3
    2400:	2b02      	cmp	r3, #2
    2402:	d10d      	bne.n	2420 <nrfx_clock_start+0x3c>
    p_reg->LFCLKSRC = (uint32_t)(source);
    2404:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2408:	2200      	movs	r2, #0
    240a:	4b0d      	ldr	r3, [pc, #52]	; (2440 <nrfx_clock_start+0x5c>)
    240c:	601a      	str	r2, [r3, #0]
    240e:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    2410:	2202      	movs	r2, #2
    2412:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    2416:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    241a:	2201      	movs	r2, #1
    241c:	609a      	str	r2, [r3, #8]
}
    241e:	4770      	bx	lr
    p_reg->LFCLKSRC = (uint32_t)(source);
    2420:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    2424:	2201      	movs	r2, #1
    2426:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    242a:	e7ed      	b.n	2408 <nrfx_clock_start+0x24>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    242c:	2200      	movs	r2, #0
    242e:	4b05      	ldr	r3, [pc, #20]	; (2444 <nrfx_clock_start+0x60>)
    2430:	601a      	str	r2, [r3, #0]
    2432:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    2434:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    2438:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    243c:	6018      	str	r0, [r3, #0]
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    243e:	4770      	bx	lr
    2440:	50005104 	.word	0x50005104
    2444:	50005100 	.word	0x50005100

00002448 <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
    2448:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    244a:	b110      	cbz	r0, 2452 <nrfx_clock_stop+0xa>
    244c:	2801      	cmp	r0, #1
    244e:	d018      	beq.n	2482 <nrfx_clock_stop+0x3a>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    2450:	bd38      	pop	{r3, r4, r5, pc}
    p_reg->INTENCLR = mask;
    2452:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    2456:	2202      	movs	r2, #2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2458:	2101      	movs	r1, #1
    245a:	f242 7510 	movw	r5, #10000	; 0x2710
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    245e:	461c      	mov	r4, r3
    p_reg->INTENCLR = mask;
    2460:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2464:	4a15      	ldr	r2, [pc, #84]	; (24bc <nrfx_clock_stop+0x74>)
    2466:	6010      	str	r0, [r2, #0]
    2468:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    246a:	4a15      	ldr	r2, [pc, #84]	; (24c0 <nrfx_clock_stop+0x78>)
    246c:	6011      	str	r1, [r2, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    246e:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
    2472:	03db      	lsls	r3, r3, #15
    2474:	d5ec      	bpl.n	2450 <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    2476:	2001      	movs	r0, #1
    2478:	f002 fbb5 	bl	4be6 <nrfx_busy_wait>
    247c:	3d01      	subs	r5, #1
    247e:	d1f6      	bne.n	246e <nrfx_clock_stop+0x26>
    2480:	e7e6      	b.n	2450 <nrfx_clock_stop+0x8>
    p_reg->INTENCLR = mask;
    2482:	f04f 2450 	mov.w	r4, #1342197760	; 0x50005000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2486:	2200      	movs	r2, #0
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2488:	f242 7510 	movw	r5, #10000	; 0x2710
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    248c:	4b0d      	ldr	r3, [pc, #52]	; (24c4 <nrfx_clock_stop+0x7c>)
    p_reg->INTENCLR = mask;
    248e:	f8c4 0308 	str.w	r0, [r4, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2492:	601a      	str	r2, [r3, #0]
    2494:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2496:	4b0c      	ldr	r3, [pc, #48]	; (24c8 <nrfx_clock_stop+0x80>)
    2498:	6018      	str	r0, [r3, #0]
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    249a:	f8d4 340c 	ldr.w	r3, [r4, #1036]	; 0x40c
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    249e:	f8d4 240c 	ldr.w	r2, [r4, #1036]	; 0x40c
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    24a2:	f003 0301 	and.w	r3, r3, #1
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    24a6:	03d2      	lsls	r2, r2, #15
    24a8:	d5d2      	bpl.n	2450 <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
    24aa:	2b00      	cmp	r3, #0
    24ac:	d0d0      	beq.n	2450 <nrfx_clock_stop+0x8>
    24ae:	2001      	movs	r0, #1
    24b0:	f002 fb99 	bl	4be6 <nrfx_busy_wait>
    24b4:	3d01      	subs	r5, #1
    24b6:	d1f0      	bne.n	249a <nrfx_clock_stop+0x52>
    24b8:	e7ca      	b.n	2450 <nrfx_clock_stop+0x8>
    24ba:	bf00      	nop
    24bc:	50005104 	.word	0x50005104
    24c0:	5000500c 	.word	0x5000500c
    24c4:	50005100 	.word	0x50005100
    24c8:	50005004 	.word	0x50005004

000024cc <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    24cc:	4b16      	ldr	r3, [pc, #88]	; (2528 <nrfx_power_clock_irq_handler+0x5c>)
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    24ce:	b510      	push	{r4, lr}
    24d0:	681a      	ldr	r2, [r3, #0]
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    24d2:	b152      	cbz	r2, 24ea <nrfx_power_clock_irq_handler+0x1e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    24d4:	2000      	movs	r0, #0
    24d6:	6018      	str	r0, [r3, #0]
    24d8:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    24da:	2201      	movs	r2, #1
    24dc:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    24e0:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    24e4:	4b11      	ldr	r3, [pc, #68]	; (252c <nrfx_power_clock_irq_handler+0x60>)
    24e6:	681b      	ldr	r3, [r3, #0]
    24e8:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    24ea:	4b11      	ldr	r3, [pc, #68]	; (2530 <nrfx_power_clock_irq_handler+0x64>)
    24ec:	681a      	ldr	r2, [r3, #0]
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    24ee:	b18a      	cbz	r2, 2514 <nrfx_power_clock_irq_handler+0x48>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    24f0:	2200      	movs	r2, #0
    24f2:	601a      	str	r2, [r3, #0]
    24f4:	681b      	ldr	r3, [r3, #0]
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    24f6:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    24fa:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    24fe:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    2502:	f002 0203 	and.w	r2, r2, #3
    2506:	2a01      	cmp	r2, #1
    2508:	f04f 0102 	mov.w	r1, #2
    250c:	d103      	bne.n	2516 <nrfx_power_clock_irq_handler+0x4a>
    p_reg->LFCLKSRC = (uint32_t)(source);
    250e:	f8c3 1518 	str.w	r1, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2512:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    2514:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    2516:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    251a:	4b04      	ldr	r3, [pc, #16]	; (252c <nrfx_power_clock_irq_handler+0x60>)
    251c:	2001      	movs	r0, #1
}
    251e:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    2522:	681b      	ldr	r3, [r3, #0]
    2524:	4718      	bx	r3
    2526:	bf00      	nop
    2528:	50005100 	.word	0x50005100
    252c:	20000808 	.word	0x20000808
    2530:	50005104 	.word	0x50005104

00002534 <z_sys_init_run_level>:
 * off and the next one begins.
 *
 * @param level init level to run.
 */
void z_sys_init_run_level(int32_t level)
{
    2534:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    2536:	4b10      	ldr	r3, [pc, #64]	; (2578 <z_sys_init_run_level+0x44>)
			/* Initialization failed.
			 * Set the init status bit so device is not declared ready.
			 */
			sys_bitfield_set_bit(
				(mem_addr_t) __device_init_status_start,
				(dev - __device_start));
    2538:	4f10      	ldr	r7, [pc, #64]	; (257c <z_sys_init_run_level+0x48>)
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    253a:	f853 5020 	ldr.w	r5, [r3, r0, lsl #2]
    253e:	3001      	adds	r0, #1
    2540:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    2544:	42ae      	cmp	r6, r5
    2546:	d800      	bhi.n	254a <z_sys_init_run_level+0x16>
		}
	}
}
    2548:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		if ((entry->init(dev) != 0) && (dev != NULL)) {
    254a:	e9d5 3400 	ldrd	r3, r4, [r5]
    254e:	4620      	mov	r0, r4
    2550:	4798      	blx	r3
    2552:	b170      	cbz	r0, 2572 <z_sys_init_run_level+0x3e>
    2554:	b16c      	cbz	r4, 2572 <z_sys_init_run_level+0x3e>

static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit)
{
	uint32_t temp = *(volatile uint32_t *)addr;

	*(volatile uint32_t *)addr = temp | (1 << bit);
    2556:	2301      	movs	r3, #1
				(dev - __device_start));
    2558:	1be4      	subs	r4, r4, r7
	void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
{
	/* Doing memory offsets in terms of 32-bit values to prevent
	 * alignment issues
	 */
	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    255a:	4a09      	ldr	r2, [pc, #36]	; (2580 <z_sys_init_run_level+0x4c>)
    255c:	1124      	asrs	r4, r4, #4
    255e:	0961      	lsrs	r1, r4, #5
	uint32_t temp = *(volatile uint32_t *)addr;
    2560:	f852 0021 	ldr.w	r0, [r2, r1, lsl #2]
	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    2564:	f004 041f 	and.w	r4, r4, #31
	*(volatile uint32_t *)addr = temp | (1 << bit);
    2568:	fa03 f404 	lsl.w	r4, r3, r4
    256c:	4304      	orrs	r4, r0
    256e:	f842 4021 	str.w	r4, [r2, r1, lsl #2]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    2572:	3508      	adds	r5, #8
    2574:	e7e6      	b.n	2544 <z_sys_init_run_level+0x10>
    2576:	bf00      	nop
    2578:	000052d4 	.word	0x000052d4
    257c:	200000bc 	.word	0x200000bc
    2580:	2000010c 	.word	0x2000010c

00002584 <z_device_ready>:

bool z_device_ready(const struct device *dev)
{
	/* Set bit indicates device failed initialization */
	return !(sys_bitfield_test_bit((mem_addr_t)__device_init_status_start,
					(dev - __device_start)));
    2584:	4b08      	ldr	r3, [pc, #32]	; (25a8 <z_device_ready+0x24>)
    2586:	1ac0      	subs	r0, r0, r3
    2588:	1100      	asrs	r0, r0, #4
}

static ALWAYS_INLINE
	int sys_bitfield_test_bit(mem_addr_t addr, unsigned int bit)
{
	return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    258a:	4b08      	ldr	r3, [pc, #32]	; (25ac <z_device_ready+0x28>)
    258c:	0942      	lsrs	r2, r0, #5
	uint32_t temp = *(volatile uint32_t *)addr;
    258e:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
	return temp & (1 << bit);
    2592:	2301      	movs	r3, #1
	return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    2594:	f000 001f 	and.w	r0, r0, #31
	return temp & (1 << bit);
    2598:	fa03 f000 	lsl.w	r0, r3, r0
	return !(sys_bitfield_test_bit((mem_addr_t)__device_init_status_start,
    259c:	4210      	tst	r0, r2
}
    259e:	bf0c      	ite	eq
    25a0:	4618      	moveq	r0, r3
    25a2:	2000      	movne	r0, #0
    25a4:	4770      	bx	lr
    25a6:	bf00      	nop
    25a8:	200000bc 	.word	0x200000bc
    25ac:	2000010c 	.word	0x2000010c

000025b0 <z_impl_device_get_binding>:
	for (dev = __device_start; dev != __device_end; dev++) {
    25b0:	4911      	ldr	r1, [pc, #68]	; (25f8 <z_impl_device_get_binding+0x48>)
{
    25b2:	b570      	push	{r4, r5, r6, lr}
    25b4:	4605      	mov	r5, r0
    25b6:	460e      	mov	r6, r1
	for (dev = __device_start; dev != __device_end; dev++) {
    25b8:	4c10      	ldr	r4, [pc, #64]	; (25fc <z_impl_device_get_binding+0x4c>)
    25ba:	428c      	cmp	r4, r1
    25bc:	d104      	bne.n	25c8 <z_impl_device_get_binding+0x18>
	for (dev = __device_start; dev != __device_end; dev++) {
    25be:	4c0f      	ldr	r4, [pc, #60]	; (25fc <z_impl_device_get_binding+0x4c>)
    25c0:	42b4      	cmp	r4, r6
    25c2:	d10a      	bne.n	25da <z_impl_device_get_binding+0x2a>
	return NULL;
    25c4:	2400      	movs	r4, #0
    25c6:	e014      	b.n	25f2 <z_impl_device_get_binding+0x42>
		if (z_device_ready(dev) && (dev->name == name)) {
    25c8:	4620      	mov	r0, r4
    25ca:	f7ff ffdb 	bl	2584 <z_device_ready>
    25ce:	b110      	cbz	r0, 25d6 <z_impl_device_get_binding+0x26>
    25d0:	6823      	ldr	r3, [r4, #0]
    25d2:	42ab      	cmp	r3, r5
    25d4:	d00d      	beq.n	25f2 <z_impl_device_get_binding+0x42>
	for (dev = __device_start; dev != __device_end; dev++) {
    25d6:	3410      	adds	r4, #16
    25d8:	e7ef      	b.n	25ba <z_impl_device_get_binding+0xa>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    25da:	4620      	mov	r0, r4
    25dc:	f7ff ffd2 	bl	2584 <z_device_ready>
    25e0:	b908      	cbnz	r0, 25e6 <z_impl_device_get_binding+0x36>
	for (dev = __device_start; dev != __device_end; dev++) {
    25e2:	3410      	adds	r4, #16
    25e4:	e7ec      	b.n	25c0 <z_impl_device_get_binding+0x10>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    25e6:	4628      	mov	r0, r5
    25e8:	6821      	ldr	r1, [r4, #0]
    25ea:	f002 fa07 	bl	49fc <strcmp>
    25ee:	2800      	cmp	r0, #0
    25f0:	d1f7      	bne.n	25e2 <z_impl_device_get_binding+0x32>
}
    25f2:	4620      	mov	r0, r4
    25f4:	bd70      	pop	{r4, r5, r6, pc}
    25f6:	bf00      	nop
    25f8:	2000010c 	.word	0x2000010c
    25fc:	200000bc 	.word	0x200000bc

00002600 <idle>:
#else
#define IDLE_YIELD_IF_COOP() do { } while (false)
#endif

void idle(void *unused1, void *unused2, void *unused3)
{
    2600:	b508      	push	{r3, lr}
	_kernel.idle = ticks;
    2602:	4d0b      	ldr	r5, [pc, #44]	; (2630 <idle+0x30>)
    2604:	f04f 0220 	mov.w	r2, #32
    2608:	f3ef 8311 	mrs	r3, BASEPRI
    260c:	f382 8811 	msr	BASEPRI, r2
    2610:	f3bf 8f6f 	isb	sy
	int32_t ticks = z_get_next_timeout_expiry();
    2614:	f002 fbfe 	bl	4e14 <z_get_next_timeout_expiry>
	z_set_timeout_expiry((ticks < IDLE_THRESH) ? 1 : ticks, true);
    2618:	2101      	movs	r1, #1
	int32_t ticks = z_get_next_timeout_expiry();
    261a:	4604      	mov	r4, r0
	z_set_timeout_expiry((ticks < IDLE_THRESH) ? 1 : ticks, true);
    261c:	2802      	cmp	r0, #2
    261e:	bfd8      	it	le
    2620:	4608      	movle	r0, r1
    2622:	f002 fc07 	bl	4e34 <z_set_timeout_expiry>
	_kernel.idle = ticks;
    2626:	622c      	str	r4, [r5, #32]
	arch_cpu_idle();
    2628:	f7ff f8a2 	bl	1770 <arch_cpu_idle>
}
    262c:	e7ea      	b.n	2604 <idle+0x4>
    262e:	bf00      	nop
    2630:	20000810 	.word	0x20000810

00002634 <z_bss_zero>:
 *
 * @return N/A
 */
void z_bss_zero(void)
{
	(void)memset(__bss_start, 0, __bss_end - __bss_start);
    2634:	4802      	ldr	r0, [pc, #8]	; (2640 <z_bss_zero+0xc>)
    2636:	4a03      	ldr	r2, [pc, #12]	; (2644 <z_bss_zero+0x10>)
    2638:	2100      	movs	r1, #0
    263a:	1a12      	subs	r2, r2, r0
    263c:	f002 ba3c 	b.w	4ab8 <memset>
    2640:	20000160 	.word	0x20000160
    2644:	20000870 	.word	0x20000870

00002648 <z_data_copy>:
 * This routine copies the data section from ROM to RAM.
 *
 * @return N/A
 */
void z_data_copy(void)
{
    2648:	b508      	push	{r3, lr}
	(void)memcpy(&__data_ram_start, &__data_rom_start,
		 __data_ram_end - __data_ram_start);
    264a:	4806      	ldr	r0, [pc, #24]	; (2664 <z_data_copy+0x1c>)
	(void)memcpy(&__data_ram_start, &__data_rom_start,
    264c:	4a06      	ldr	r2, [pc, #24]	; (2668 <z_data_copy+0x20>)
    264e:	4907      	ldr	r1, [pc, #28]	; (266c <z_data_copy+0x24>)
    2650:	1a12      	subs	r2, r2, r0
    2652:	f002 fa06 	bl	4a62 <memcpy>
#else
	(void)memcpy(&_app_smem_start, &_app_smem_rom_start,
		 _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    2656:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	(void)memcpy(&_ramfunc_ram_start, &_ramfunc_rom_start,
    265a:	4a05      	ldr	r2, [pc, #20]	; (2670 <z_data_copy+0x28>)
    265c:	4905      	ldr	r1, [pc, #20]	; (2674 <z_data_copy+0x2c>)
    265e:	4806      	ldr	r0, [pc, #24]	; (2678 <z_data_copy+0x30>)
    2660:	f002 b9ff 	b.w	4a62 <memcpy>
    2664:	20000000 	.word	0x20000000
    2668:	20000160 	.word	0x20000160
    266c:	000057e0 	.word	0x000057e0
    2670:	00000000 	.word	0x00000000
    2674:	000057e0 	.word	0x000057e0
    2678:	20000000 	.word	0x20000000

0000267c <bg_thread_main>:
	static const unsigned int boot_delay = CONFIG_BOOT_DELAY;
#else
	static const unsigned int boot_delay;
#endif

	z_sys_post_kernel = true;
    267c:	2201      	movs	r2, #1
{
    267e:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    2680:	4b0b      	ldr	r3, [pc, #44]	; (26b0 <bg_thread_main+0x34>)

	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    2682:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
    2684:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    2686:	f7ff ff55 	bl	2534 <z_sys_init_run_level>
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
    268a:	4a0a      	ldr	r2, [pc, #40]	; (26b4 <bg_thread_main+0x38>)
    268c:	490a      	ldr	r1, [pc, #40]	; (26b8 <bg_thread_main+0x3c>)
    268e:	480b      	ldr	r0, [pc, #44]	; (26bc <bg_thread_main+0x40>)
    2690:	f001 febc 	bl	440c <printk>
	__do_global_ctors_aux();
	__do_init_array_aux();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    2694:	2003      	movs	r0, #3
    2696:	f7ff ff4d 	bl	2534 <z_sys_init_run_level>

	z_init_static_threads();
    269a:	f000 fdb1 	bl	3200 <z_init_static_threads>
	z_timestamp_main = k_cycle_get_32();
#endif

	extern void main(void);

	main();
    269e:	f001 fe8f 	bl	43c0 <main>

	/* Mark nonessenrial since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    26a2:	4a07      	ldr	r2, [pc, #28]	; (26c0 <bg_thread_main+0x44>)
    26a4:	7b13      	ldrb	r3, [r2, #12]
    26a6:	f023 0301 	bic.w	r3, r3, #1
    26aa:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    26ac:	bd08      	pop	{r3, pc}
    26ae:	bf00      	nop
    26b0:	2000086d 	.word	0x2000086d
    26b4:	00005434 	.word	0x00005434
    26b8:	000057a3 	.word	0x000057a3
    26bc:	000057af 	.word	0x000057af
    26c0:	200001e0 	.word	0x200001e0

000026c4 <z_cstart>:
 * cleared/zeroed.
 *
 * @return Does not return
 */
FUNC_NORETURN void z_cstart(void)
{
    26c4:	e92d 4880 	stmdb	sp!, {r7, fp, lr}
 * @return N/A
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
		(uint32_t)(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) +
    26c8:	4b37      	ldr	r3, [pc, #220]	; (27a8 <z_cstart+0xe4>)
    26ca:	b0a7      	sub	sp, #156	; 0x9c
	uint32_t msp =
    26cc:	f503 6900 	add.w	r9, r3, #2048	; 0x800
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    26d0:	f389 8808 	msr	MSP, r9
  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
    26d4:	f383 880a 	msr	MSPLIM, r3
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    26d8:	2400      	movs	r4, #0
    26da:	23e0      	movs	r3, #224	; 0xe0
    26dc:	4d33      	ldr	r5, [pc, #204]	; (27ac <z_cstart+0xe8>)
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    26de:	f04f 0b01 	mov.w	fp, #1
    26e2:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    26e6:	77ec      	strb	r4, [r5, #31]
    26e8:	762c      	strb	r4, [r5, #24]
    26ea:	766c      	strb	r4, [r5, #25]
    26ec:	76ac      	strb	r4, [r5, #26]
    26ee:	76ec      	strb	r4, [r5, #27]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    26f0:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	_kernel.ready_q.cache = &z_main_thread;
    26f2:	4e2f      	ldr	r6, [pc, #188]	; (27b0 <z_cstart+0xec>)
    26f4:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    26f8:	626b      	str	r3, [r5, #36]	; 0x24
		      SCB_SHCSR_BUSFAULTENA_Msk;
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	/* Enable Secure Fault */
	SCB->SHCSR |= SCB_SHCSR_SECUREFAULTENA_Msk;
    26fa:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    26fc:	f8df a0cc 	ldr.w	sl, [pc, #204]	; 27cc <z_cstart+0x108>
    2700:	f443 2300 	orr.w	r3, r3, #524288	; 0x80000
    2704:	626b      	str	r3, [r5, #36]	; 0x24
	/* Clear BFAR before setting BusFaults to target Non-Secure state. */
	SCB->BFAR = 0;
    2706:	63ac      	str	r4, [r5, #56]	; 0x38

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    2708:	f7ff f9c0 	bl	1a8c <z_arm_fault_init>
	z_arm_cpu_idle_init();
    270c:	f7ff f82a 	bl	1764 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    2710:	f04f 33ff 	mov.w	r3, #4294967295
    2714:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    2716:	62eb      	str	r3, [r5, #44]	; 0x2c
{
	dummy_thread->base.thread_state = _THREAD_DUMMY;
#ifdef CONFIG_SCHED_CPU_MASK
	dummy_thread->base.cpu_mask = -1;
#endif
	dummy_thread->base.user_options = K_ESSENTIAL;
    2718:	f240 1301 	movw	r3, #257	; 0x101
#endif
#ifdef CONFIG_USERSPACE
	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
#endif

	_current_cpu->current = dummy_thread;
    271c:	4d25      	ldr	r5, [pc, #148]	; (27b4 <z_cstart+0xf0>)
	dummy_thread->base.user_options = K_ESSENTIAL;
    271e:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    2722:	ab06      	add	r3, sp, #24
    2724:	60ab      	str	r3, [r5, #8]

	z_dummy_thread_init(&dummy_thread);
#endif

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    2726:	4620      	mov	r0, r4
	dummy_thread->stack_info.size = 0U;
    2728:	e9cd 4420 	strd	r4, r4, [sp, #128]	; 0x80
    272c:	f7ff ff02 	bl	2534 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    2730:	2001      	movs	r0, #1
    2732:	f7ff feff 	bl	2534 <z_sys_init_run_level>
	z_sched_init();
    2736:	f000 fc69 	bl	300c <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    273a:	4b1f      	ldr	r3, [pc, #124]	; (27b8 <z_cstart+0xf4>)
	_kernel.ready_q.cache = &z_main_thread;
    273c:	626e      	str	r6, [r5, #36]	; 0x24
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    273e:	f44f 6280 	mov.w	r2, #1024	; 0x400
    2742:	491e      	ldr	r1, [pc, #120]	; (27bc <z_cstart+0xf8>)
    2744:	9305      	str	r3, [sp, #20]
    2746:	4630      	mov	r0, r6
    2748:	4653      	mov	r3, sl
    274a:	e9cd 4b03 	strd	r4, fp, [sp, #12]
    274e:	e9cd 4401 	strd	r4, r4, [sp, #4]
    2752:	9400      	str	r4, [sp, #0]
    2754:	f000 fd24 	bl	31a0 <z_setup_new_thread>
	sys_trace_thread_resume(thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    2758:	7b73      	ldrb	r3, [r6, #13]
    275a:	4680      	mov	r8, r0
    275c:	f023 0304 	bic.w	r3, r3, #4
	z_ready_thread(&z_main_thread);
    2760:	4630      	mov	r0, r6
    2762:	7373      	strb	r3, [r6, #13]
    2764:	f002 fab8 	bl	4cd8 <z_ready_thread>
	z_setup_new_thread(thread, stack,
    2768:	230f      	movs	r3, #15
    276a:	4f15      	ldr	r7, [pc, #84]	; (27c0 <z_cstart+0xfc>)
    276c:	f44f 72a0 	mov.w	r2, #320	; 0x140
    2770:	e9cd 4302 	strd	r4, r3, [sp, #8]
    2774:	4913      	ldr	r1, [pc, #76]	; (27c4 <z_cstart+0x100>)
    2776:	4b14      	ldr	r3, [pc, #80]	; (27c8 <z_cstart+0x104>)
    2778:	4638      	mov	r0, r7
    277a:	e9cd b404 	strd	fp, r4, [sp, #16]
    277e:	e9cd 4400 	strd	r4, r4, [sp]
    2782:	f000 fd0d 	bl	31a0 <z_setup_new_thread>
    2786:	7b7b      	ldrb	r3, [r7, #13]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    2788:	4652      	mov	r2, sl
    278a:	f023 0304 	bic.w	r3, r3, #4
    278e:	737b      	strb	r3, [r7, #13]
 * @return N/A
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
    2790:	f105 0318 	add.w	r3, r5, #24
    2794:	4641      	mov	r1, r8
    2796:	4630      	mov	r0, r6
	list->tail = (sys_dnode_t *)list;
    2798:	e9c5 3306 	strd	r3, r3, [r5, #24]
		_kernel.cpus[i].idle_thread = &z_idle_threads[i];
    279c:	60ef      	str	r7, [r5, #12]
		_kernel.cpus[i].id = i;
    279e:	752c      	strb	r4, [r5, #20]
		_kernel.cpus[i].irq_stack =
    27a0:	f8c5 9004 	str.w	r9, [r5, #4]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    27a4:	f7fe ffc0 	bl	1728 <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    27a8:	20000db0 	.word	0x20000db0
    27ac:	e000ed00 	.word	0xe000ed00
    27b0:	200001e0 	.word	0x200001e0
    27b4:	20000810 	.word	0x20000810
    27b8:	000057d6 	.word	0x000057d6
    27bc:	20000870 	.word	0x20000870
    27c0:	20000160 	.word	0x20000160
    27c4:	20000c70 	.word	0x20000c70
    27c8:	00002601 	.word	0x00002601
    27cc:	0000267d 	.word	0x0000267d

000027d0 <init_mem_slab_module>:
 * Perform any initialization that wasn't done at build time.
 *
 * @return N/A
 */
static int init_mem_slab_module(const struct device *dev)
{
    27d0:	b570      	push	{r4, r5, r6, lr}
	int rc = 0;
	ARG_UNUSED(dev);

	Z_STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    27d2:	4b0e      	ldr	r3, [pc, #56]	; (280c <init_mem_slab_module+0x3c>)
    27d4:	4c0e      	ldr	r4, [pc, #56]	; (2810 <init_mem_slab_module+0x40>)
    27d6:	42a3      	cmp	r3, r4
    27d8:	d301      	bcc.n	27de <init_mem_slab_module+0xe>
		}
		SYS_TRACING_OBJ_INIT(k_mem_slab, slab);
		z_object_init(slab);
	}

out:
    27da:	2000      	movs	r0, #0
	return rc;
}
    27dc:	bd70      	pop	{r4, r5, r6, pc}
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    27de:	e9d3 0103 	ldrd	r0, r1, [r3, #12]
    27e2:	ea41 0200 	orr.w	r2, r1, r0
    27e6:	f012 0203 	ands.w	r2, r2, #3
    27ea:	d10b      	bne.n	2804 <init_mem_slab_module+0x34>
	for (j = 0U; j < slab->num_blocks; j++) {
    27ec:	689d      	ldr	r5, [r3, #8]
	slab->free_list = NULL;
    27ee:	615a      	str	r2, [r3, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    27f0:	42aa      	cmp	r2, r5
    27f2:	d101      	bne.n	27f8 <init_mem_slab_module+0x28>
	Z_STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    27f4:	331c      	adds	r3, #28
    27f6:	e7ee      	b.n	27d6 <init_mem_slab_module+0x6>
		*(char **)p = slab->free_list;
    27f8:	695e      	ldr	r6, [r3, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    27fa:	3201      	adds	r2, #1
		*(char **)p = slab->free_list;
    27fc:	600e      	str	r6, [r1, #0]
		slab->free_list = p;
    27fe:	6159      	str	r1, [r3, #20]
		p += slab->block_size;
    2800:	4401      	add	r1, r0
	for (j = 0U; j < slab->num_blocks; j++) {
    2802:	e7f5      	b.n	27f0 <init_mem_slab_module+0x20>
		return -EINVAL;
    2804:	f06f 0015 	mvn.w	r0, #21
	return rc;
    2808:	e7e8      	b.n	27dc <init_mem_slab_module+0xc>
    280a:	bf00      	nop
    280c:	20000110 	.word	0x20000110
    2810:	20000110 	.word	0x20000110

00002814 <k_mem_slab_alloc>:
out:
	return rc;
}

int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
{
    2814:	b5d3      	push	{r0, r1, r4, r6, r7, lr}
    2816:	460c      	mov	r4, r1
    2818:	4616      	mov	r6, r2
    281a:	461f      	mov	r7, r3
    281c:	f04f 0320 	mov.w	r3, #32
    2820:	f3ef 8111 	mrs	r1, BASEPRI
    2824:	f383 8811 	msr	BASEPRI, r3
    2828:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	int result;

	if (slab->free_list != NULL) {
    282c:	6943      	ldr	r3, [r0, #20]
    282e:	b15b      	cbz	r3, 2848 <k_mem_slab_alloc+0x34>
		/* take a free block */
		*mem = slab->free_list;
    2830:	6023      	str	r3, [r4, #0]
		slab->free_list = *(char **)(slab->free_list);
    2832:	681b      	ldr	r3, [r3, #0]
    2834:	6143      	str	r3, [r0, #20]
		slab->num_used++;
    2836:	6983      	ldr	r3, [r0, #24]
    2838:	3301      	adds	r3, #1
    283a:	6183      	str	r3, [r0, #24]
		result = 0;
    283c:	2000      	movs	r0, #0
	__asm__ volatile(
    283e:	f381 8811 	msr	BASEPRI, r1
    2842:	f3bf 8f6f 	isb	sy
		return result;
	}

	k_spin_unlock(&lock, key);

	return result;
    2846:	e011      	b.n	286c <k_mem_slab_alloc+0x58>
	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    2848:	ea56 0207 	orrs.w	r2, r6, r7
    284c:	d103      	bne.n	2856 <k_mem_slab_alloc+0x42>
		result = -ENOMEM;
    284e:	f06f 000b 	mvn.w	r0, #11
		*mem = NULL;
    2852:	6023      	str	r3, [r4, #0]
		result = -ENOMEM;
    2854:	e7f3      	b.n	283e <k_mem_slab_alloc+0x2a>
		result = z_pend_curr(&lock, key, &slab->wait_q, timeout);
    2856:	4602      	mov	r2, r0
    2858:	e9cd 6700 	strd	r6, r7, [sp]
    285c:	4804      	ldr	r0, [pc, #16]	; (2870 <k_mem_slab_alloc+0x5c>)
    285e:	f000 fb4f 	bl	2f00 <z_pend_curr>
		if (result == 0) {
    2862:	b918      	cbnz	r0, 286c <k_mem_slab_alloc+0x58>
			*mem = _current->base.swap_data;
    2864:	4b03      	ldr	r3, [pc, #12]	; (2874 <k_mem_slab_alloc+0x60>)
    2866:	689b      	ldr	r3, [r3, #8]
    2868:	695b      	ldr	r3, [r3, #20]
    286a:	6023      	str	r3, [r4, #0]
}
    286c:	b002      	add	sp, #8
    286e:	bdd0      	pop	{r4, r6, r7, pc}
    2870:	2000086e 	.word	0x2000086e
    2874:	20000810 	.word	0x20000810

00002878 <k_mem_slab_free>:

void k_mem_slab_free(struct k_mem_slab *slab, void **mem)
{
    2878:	b570      	push	{r4, r5, r6, lr}
    287a:	4604      	mov	r4, r0
    287c:	460d      	mov	r5, r1
	__asm__ volatile(
    287e:	f04f 0320 	mov.w	r3, #32
    2882:	f3ef 8611 	mrs	r6, BASEPRI
    2886:	f383 8811 	msr	BASEPRI, r3
    288a:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *pending_thread = z_unpend_first_thread(&slab->wait_q);
    288e:	f002 fa7e 	bl	4d8e <z_unpend_first_thread>

	if (pending_thread != NULL) {
    2892:	b158      	cbz	r0, 28ac <k_mem_slab_free+0x34>
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    2894:	2100      	movs	r1, #0
		z_thread_return_value_set_with_data(pending_thread, 0, *mem);
    2896:	682a      	ldr	r2, [r5, #0]
    2898:	67c1      	str	r1, [r0, #124]	; 0x7c
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    289a:	6142      	str	r2, [r0, #20]
		z_ready_thread(pending_thread);
    289c:	f002 fa1c 	bl	4cd8 <z_ready_thread>
		z_reschedule(&lock, key);
    28a0:	4631      	mov	r1, r6
		**(char ***)mem = slab->free_list;
		slab->free_list = *(char **)mem;
		slab->num_used--;
		k_spin_unlock(&lock, key);
	}
}
    28a2:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule(&lock, key);
    28a6:	4808      	ldr	r0, [pc, #32]	; (28c8 <k_mem_slab_free+0x50>)
    28a8:	f000 b910 	b.w	2acc <z_reschedule>
		**(char ***)mem = slab->free_list;
    28ac:	682b      	ldr	r3, [r5, #0]
    28ae:	6962      	ldr	r2, [r4, #20]
    28b0:	601a      	str	r2, [r3, #0]
		slab->free_list = *(char **)mem;
    28b2:	682b      	ldr	r3, [r5, #0]
    28b4:	6163      	str	r3, [r4, #20]
		slab->num_used--;
    28b6:	69a3      	ldr	r3, [r4, #24]
    28b8:	3b01      	subs	r3, #1
    28ba:	61a3      	str	r3, [r4, #24]
	__asm__ volatile(
    28bc:	f386 8811 	msr	BASEPRI, r6
    28c0:	f3bf 8f6f 	isb	sy
}
    28c4:	bd70      	pop	{r4, r5, r6, pc}
    28c6:	bf00      	nop
    28c8:	2000086e 	.word	0x2000086e

000028cc <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
    28cc:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    28d0:	4604      	mov	r4, r0
    28d2:	4616      	mov	r6, r2
    28d4:	461f      	mov	r7, r3
	__asm__ volatile(
    28d6:	f04f 0320 	mov.w	r3, #32
    28da:	f3ef 8811 	mrs	r8, BASEPRI
    28de:	f383 8811 	msr	BASEPRI, r3
    28e2:	f3bf 8f6f 	isb	sy
	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	sys_trace_mutex_lock(mutex);
	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    28e6:	68c3      	ldr	r3, [r0, #12]
    28e8:	4a32      	ldr	r2, [pc, #200]	; (29b4 <z_impl_k_mutex_lock+0xe8>)
    28ea:	b16b      	cbz	r3, 2908 <z_impl_k_mutex_lock+0x3c>
    28ec:	6880      	ldr	r0, [r0, #8]
    28ee:	6891      	ldr	r1, [r2, #8]
    28f0:	4288      	cmp	r0, r1
    28f2:	d019      	beq.n	2928 <z_impl_k_mutex_lock+0x5c>
		sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);

		return 0;
	}

	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
    28f4:	ea56 0307 	orrs.w	r3, r6, r7
    28f8:	d118      	bne.n	292c <z_impl_k_mutex_lock+0x60>
	__asm__ volatile(
    28fa:	f388 8811 	msr	BASEPRI, r8
    28fe:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);
		return -EBUSY;
    2902:	f06f 000f 	mvn.w	r0, #15
    2906:	e00c      	b.n	2922 <z_impl_k_mutex_lock+0x56>
					_current->base.prio :
    2908:	6891      	ldr	r1, [r2, #8]
    290a:	f991 100e 	ldrsb.w	r1, [r1, #14]
		mutex->lock_count++;
    290e:	3301      	adds	r3, #1
    2910:	60e3      	str	r3, [r4, #12]
		mutex->owner = _current;
    2912:	6893      	ldr	r3, [r2, #8]
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
    2914:	6121      	str	r1, [r4, #16]
		mutex->owner = _current;
    2916:	60a3      	str	r3, [r4, #8]
    2918:	f388 8811 	msr	BASEPRI, r8
    291c:	f3bf 8f6f 	isb	sy
		return 0;
    2920:	2000      	movs	r0, #0
		k_spin_unlock(&lock, key);
	}

	sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);
	return -EAGAIN;
}
    2922:	b002      	add	sp, #8
    2924:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
					_current->base.prio :
    2928:	6921      	ldr	r1, [r4, #16]
    292a:	e7f0      	b.n	290e <z_impl_k_mutex_lock+0x42>
	new_prio = new_prio_for_inheritance(_current->base.prio,
    292c:	f990 300e 	ldrsb.w	r3, [r0, #14]
    2930:	f991 100e 	ldrsb.w	r1, [r1, #14]
    2934:	4299      	cmp	r1, r3
    2936:	bfa8      	it	ge
    2938:	4619      	movge	r1, r3
    293a:	ea21 71e1 	bic.w	r1, r1, r1, asr #31
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
    293e:	4299      	cmp	r1, r3
    2940:	da2c      	bge.n	299c <z_impl_k_mutex_lock+0xd0>
		return z_set_prio(mutex->owner, new_prio);
    2942:	f000 fb1f 	bl	2f84 <z_set_prio>
    2946:	4605      	mov	r5, r0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
    2948:	4622      	mov	r2, r4
    294a:	4641      	mov	r1, r8
    294c:	e9cd 6700 	strd	r6, r7, [sp]
    2950:	4819      	ldr	r0, [pc, #100]	; (29b8 <z_impl_k_mutex_lock+0xec>)
    2952:	f000 fad5 	bl	2f00 <z_pend_curr>
	if (got_mutex == 0) {
    2956:	2800      	cmp	r0, #0
    2958:	d0e3      	beq.n	2922 <z_impl_k_mutex_lock+0x56>
	__asm__ volatile(
    295a:	f04f 0320 	mov.w	r3, #32
    295e:	f3ef 8611 	mrs	r6, BASEPRI
    2962:	f383 8811 	msr	BASEPRI, r3
    2966:	f3bf 8f6f 	isb	sy
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    296a:	6823      	ldr	r3, [r4, #0]
    296c:	6921      	ldr	r1, [r4, #16]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    296e:	42a3      	cmp	r3, r4
    2970:	d007      	beq.n	2982 <z_impl_k_mutex_lock+0xb6>
		new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    2972:	b133      	cbz	r3, 2982 <z_impl_k_mutex_lock+0xb6>
    2974:	f993 300e 	ldrsb.w	r3, [r3, #14]
    2978:	4299      	cmp	r1, r3
    297a:	bfa8      	it	ge
    297c:	4619      	movge	r1, r3
    297e:	ea21 71e1 	bic.w	r1, r1, r1, asr #31
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    2982:	68a0      	ldr	r0, [r4, #8]
	if (mutex->owner->base.prio != new_prio) {
    2984:	f990 300e 	ldrsb.w	r3, [r0, #14]
    2988:	4299      	cmp	r1, r3
    298a:	d109      	bne.n	29a0 <z_impl_k_mutex_lock+0xd4>
	if (resched) {
    298c:	b16d      	cbz	r5, 29aa <z_impl_k_mutex_lock+0xde>
		z_reschedule(&lock, key);
    298e:	4631      	mov	r1, r6
    2990:	4809      	ldr	r0, [pc, #36]	; (29b8 <z_impl_k_mutex_lock+0xec>)
    2992:	f000 f89b 	bl	2acc <z_reschedule>
	return -EAGAIN;
    2996:	f06f 000a 	mvn.w	r0, #10
    299a:	e7c2      	b.n	2922 <z_impl_k_mutex_lock+0x56>
	bool resched = false;
    299c:	2500      	movs	r5, #0
    299e:	e7d3      	b.n	2948 <z_impl_k_mutex_lock+0x7c>
		return z_set_prio(mutex->owner, new_prio);
    29a0:	f000 faf0 	bl	2f84 <z_set_prio>
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    29a4:	2800      	cmp	r0, #0
    29a6:	d1f2      	bne.n	298e <z_impl_k_mutex_lock+0xc2>
    29a8:	e7f0      	b.n	298c <z_impl_k_mutex_lock+0xc0>
	__asm__ volatile(
    29aa:	f386 8811 	msr	BASEPRI, r6
    29ae:	f3bf 8f6f 	isb	sy
    29b2:	e7f0      	b.n	2996 <z_impl_k_mutex_lock+0xca>
    29b4:	20000810 	.word	0x20000810
    29b8:	2000086e 	.word	0x2000086e

000029bc <z_impl_k_mutex_unlock>:
}
#include <syscalls/k_mutex_lock_mrsh.c>
#endif

int z_impl_k_mutex_unlock(struct k_mutex *mutex)
{
    29bc:	b538      	push	{r3, r4, r5, lr}
	struct k_thread *new_owner;

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	CHECKIF(mutex->owner == NULL) {
    29be:	6883      	ldr	r3, [r0, #8]
{
    29c0:	4604      	mov	r4, r0
	CHECKIF(mutex->owner == NULL) {
    29c2:	2b00      	cmp	r3, #0
    29c4:	d036      	beq.n	2a34 <z_impl_k_mutex_unlock+0x78>
		return -EINVAL;
	}
	/*
	 * The current thread does not own the mutex.
	 */
	CHECKIF(mutex->owner != _current) {
    29c6:	4a1e      	ldr	r2, [pc, #120]	; (2a40 <z_impl_k_mutex_unlock+0x84>)
    29c8:	6892      	ldr	r2, [r2, #8]
    29ca:	4293      	cmp	r3, r2
    29cc:	d135      	bne.n	2a3a <z_impl_k_mutex_unlock+0x7e>
{
#ifdef CONFIG_PREEMPT_ENABLED
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1, "");

	--_current->base.sched_locked;
    29ce:	7bda      	ldrb	r2, [r3, #15]
    29d0:	3a01      	subs	r2, #1
    29d2:	73da      	strb	r2, [r3, #15]

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count - 1U != 0U) {
    29d4:	68c3      	ldr	r3, [r0, #12]
    29d6:	2b01      	cmp	r3, #1
    29d8:	d005      	beq.n	29e6 <z_impl_k_mutex_unlock+0x2a>
		mutex->lock_count--;
    29da:	3b01      	subs	r3, #1
    29dc:	60c3      	str	r3, [r0, #12]
		k_spin_unlock(&lock, key);
	}


k_mutex_unlock_return:
	k_sched_unlock();
    29de:	f000 f8d5 	bl	2b8c <k_sched_unlock>
	sys_trace_end_call(SYS_TRACE_ID_MUTEX_UNLOCK);

	return 0;
    29e2:	2000      	movs	r0, #0
}
    29e4:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    29e6:	f04f 0320 	mov.w	r3, #32
    29ea:	f3ef 8511 	mrs	r5, BASEPRI
    29ee:	f383 8811 	msr	BASEPRI, r3
    29f2:	f3bf 8f6f 	isb	sy
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
    29f6:	6901      	ldr	r1, [r0, #16]
    29f8:	6880      	ldr	r0, [r0, #8]
	if (mutex->owner->base.prio != new_prio) {
    29fa:	f990 300e 	ldrsb.w	r3, [r0, #14]
    29fe:	4299      	cmp	r1, r3
    2a00:	d001      	beq.n	2a06 <z_impl_k_mutex_unlock+0x4a>
		return z_set_prio(mutex->owner, new_prio);
    2a02:	f000 fabf 	bl	2f84 <z_set_prio>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
    2a06:	4620      	mov	r0, r4
    2a08:	f002 f9c1 	bl	4d8e <z_unpend_first_thread>
	mutex->owner = new_owner;
    2a0c:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
    2a0e:	b158      	cbz	r0, 2a28 <z_impl_k_mutex_unlock+0x6c>
		mutex->owner_orig_prio = new_owner->base.prio;
    2a10:	f990 200e 	ldrsb.w	r2, [r0, #14]
    2a14:	6122      	str	r2, [r4, #16]
    2a16:	2200      	movs	r2, #0
    2a18:	67c2      	str	r2, [r0, #124]	; 0x7c
		z_ready_thread(new_owner);
    2a1a:	f002 f95d 	bl	4cd8 <z_ready_thread>
		z_reschedule(&lock, key);
    2a1e:	4629      	mov	r1, r5
    2a20:	4808      	ldr	r0, [pc, #32]	; (2a44 <z_impl_k_mutex_unlock+0x88>)
    2a22:	f000 f853 	bl	2acc <z_reschedule>
    2a26:	e7da      	b.n	29de <z_impl_k_mutex_unlock+0x22>
		mutex->lock_count = 0U;
    2a28:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    2a2a:	f385 8811 	msr	BASEPRI, r5
    2a2e:	f3bf 8f6f 	isb	sy
    2a32:	e7d4      	b.n	29de <z_impl_k_mutex_unlock+0x22>
		return -EINVAL;
    2a34:	f06f 0015 	mvn.w	r0, #21
    2a38:	e7d4      	b.n	29e4 <z_impl_k_mutex_unlock+0x28>
		return -EPERM;
    2a3a:	f04f 30ff 	mov.w	r0, #4294967295
    2a3e:	e7d1      	b.n	29e4 <z_impl_k_mutex_unlock+0x28>
    2a40:	20000810 	.word	0x20000810
    2a44:	2000086e 	.word	0x2000086e

00002a48 <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(void)
{
    2a48:	b510      	push	{r4, lr}
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time != 0) {
    2a4a:	4c08      	ldr	r4, [pc, #32]	; (2a6c <z_reset_time_slice+0x24>)
    2a4c:	6823      	ldr	r3, [r4, #0]
    2a4e:	b15b      	cbz	r3, 2a68 <z_reset_time_slice+0x20>
		_current_cpu->slice_ticks = slice_time + z_clock_elapsed();
    2a50:	f7fe fac6 	bl	fe0 <z_clock_elapsed>
    2a54:	6822      	ldr	r2, [r4, #0]
    2a56:	4906      	ldr	r1, [pc, #24]	; (2a70 <z_reset_time_slice+0x28>)
    2a58:	4410      	add	r0, r2
    2a5a:	6108      	str	r0, [r1, #16]
		z_set_timeout_expiry(slice_time, false);
	}
}
    2a5c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		z_set_timeout_expiry(slice_time, false);
    2a60:	2100      	movs	r1, #0
    2a62:	4610      	mov	r0, r2
    2a64:	f002 b9e6 	b.w	4e34 <z_set_timeout_expiry>
}
    2a68:	bd10      	pop	{r4, pc}
    2a6a:	bf00      	nop
    2a6c:	20000848 	.word	0x20000848
    2a70:	20000810 	.word	0x20000810

00002a74 <k_sched_time_slice_set>:

void k_sched_time_slice_set(int32_t slice, int prio)
{
    2a74:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2a76:	460c      	mov	r4, r1
	__asm__ volatile(
    2a78:	f04f 0320 	mov.w	r3, #32
    2a7c:	f3ef 8511 	mrs	r5, BASEPRI
    2a80:	f383 8811 	msr	BASEPRI, r3
    2a84:	f3bf 8f6f 	isb	sy
		} else {
			return t * (to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    2a88:	f44f 4100 	mov.w	r1, #32768	; 0x8000
    2a8c:	f240 36e7 	movw	r6, #999	; 0x3e7
    2a90:	2700      	movs	r7, #0
	LOCKED(&sched_spinlock) {
		_current_cpu->slice_ticks = 0;
    2a92:	2200      	movs	r2, #0
    2a94:	fbe1 6700 	umlal	r6, r7, r1, r0
    2a98:	4b09      	ldr	r3, [pc, #36]	; (2ac0 <k_sched_time_slice_set+0x4c>)
    2a9a:	4630      	mov	r0, r6
    2a9c:	611a      	str	r2, [r3, #16]
    2a9e:	4639      	mov	r1, r7
    2aa0:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    2aa4:	2300      	movs	r3, #0
    2aa6:	f7fd fbc9 	bl	23c <__aeabi_uldivmod>
		slice_time = k_ms_to_ticks_ceil32(slice);
    2aaa:	4b06      	ldr	r3, [pc, #24]	; (2ac4 <k_sched_time_slice_set+0x50>)
    2aac:	6018      	str	r0, [r3, #0]
		slice_max_prio = prio;
    2aae:	4b06      	ldr	r3, [pc, #24]	; (2ac8 <k_sched_time_slice_set+0x54>)
    2ab0:	601c      	str	r4, [r3, #0]
		z_reset_time_slice();
    2ab2:	f7ff ffc9 	bl	2a48 <z_reset_time_slice>
	__asm__ volatile(
    2ab6:	f385 8811 	msr	BASEPRI, r5
    2aba:	f3bf 8f6f 	isb	sy
	}
}
    2abe:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    2ac0:	20000810 	.word	0x20000810
    2ac4:	20000848 	.word	0x20000848
    2ac8:	20000844 	.word	0x20000844

00002acc <z_reschedule>:
{
#ifdef CONFIG_SMP
	_current_cpu->swap_ok = 0;
#endif

	return arch_irq_unlocked(key) && !arch_is_in_isr();
    2acc:	b949      	cbnz	r1, 2ae2 <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    2ace:	f3ef 8005 	mrs	r0, IPSR
    2ad2:	b930      	cbnz	r0, 2ae2 <z_reschedule+0x16>
	return _kernel.ready_q.cache;
    2ad4:	4b05      	ldr	r3, [pc, #20]	; (2aec <z_reschedule+0x20>)
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
	if (resched(key.key) && need_swap()) {
    2ad6:	6a5a      	ldr	r2, [r3, #36]	; 0x24
    2ad8:	689b      	ldr	r3, [r3, #8]
    2ada:	429a      	cmp	r2, r3
    2adc:	d001      	beq.n	2ae2 <z_reschedule+0x16>
	ret = arch_swap(key);
    2ade:	f7fe bd7d 	b.w	15dc <arch_swap>
    2ae2:	f381 8811 	msr	BASEPRI, r1
    2ae6:	f3bf 8f6f 	isb	sy
		z_swap(lock, key);
	} else {
		k_spin_unlock(lock, key);
	}
}
    2aea:	4770      	bx	lr
    2aec:	20000810 	.word	0x20000810

00002af0 <k_sched_lock>:
	__asm__ volatile(
    2af0:	f04f 0320 	mov.w	r3, #32
    2af4:	f3ef 8111 	mrs	r1, BASEPRI
    2af8:	f383 8811 	msr	BASEPRI, r3
    2afc:	f3bf 8f6f 	isb	sy
	--_current->base.sched_locked;
    2b00:	4b04      	ldr	r3, [pc, #16]	; (2b14 <k_sched_lock+0x24>)
    2b02:	689a      	ldr	r2, [r3, #8]
    2b04:	7bd3      	ldrb	r3, [r2, #15]
    2b06:	3b01      	subs	r3, #1
    2b08:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    2b0a:	f381 8811 	msr	BASEPRI, r1
    2b0e:	f3bf 8f6f 	isb	sy
void k_sched_lock(void)
{
	LOCKED(&sched_spinlock) {
		z_sched_lock();
	}
}
    2b12:	4770      	bx	lr
    2b14:	20000810 	.word	0x20000810

00002b18 <z_priq_dumb_remove>:
}

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
#if defined(CONFIG_SWAP_NONATOMIC) && defined(CONFIG_SCHED_DUMB)
	if (pq == &_kernel.ready_q.runq && thread == _current &&
    2b18:	4b09      	ldr	r3, [pc, #36]	; (2b40 <z_priq_dumb_remove+0x28>)
    2b1a:	f103 0228 	add.w	r2, r3, #40	; 0x28
    2b1e:	4282      	cmp	r2, r0
    2b20:	d105      	bne.n	2b2e <z_priq_dumb_remove+0x16>
    2b22:	689b      	ldr	r3, [r3, #8]
    2b24:	428b      	cmp	r3, r1
    2b26:	d102      	bne.n	2b2e <z_priq_dumb_remove+0x16>
    2b28:	7b4b      	ldrb	r3, [r1, #13]
    2b2a:	06db      	lsls	r3, r3, #27
    2b2c:	d106      	bne.n	2b3c <z_priq_dumb_remove+0x24>
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	node->prev->next = node->next;
    2b2e:	e9d1 3200 	ldrd	r3, r2, [r1]
    2b32:	6013      	str	r3, [r2, #0]
	node->next->prev = node->prev;
    2b34:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    2b36:	2300      	movs	r3, #0
	node->prev = NULL;
    2b38:	e9c1 3300 	strd	r3, r3, [r1]
#endif

	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
}
    2b3c:	4770      	bx	lr
    2b3e:	bf00      	nop
    2b40:	20000810 	.word	0x20000810

00002b44 <update_cache>:
{
    2b44:	b570      	push	{r4, r5, r6, lr}
	struct k_thread *thread = _priq_run_best(&_kernel.ready_q.runq);
    2b46:	4c10      	ldr	r4, [pc, #64]	; (2b88 <update_cache+0x44>)
{
    2b48:	4606      	mov	r6, r0
	struct k_thread *thread = _priq_run_best(&_kernel.ready_q.runq);
    2b4a:	f104 0028 	add.w	r0, r4, #40	; 0x28
    2b4e:	f002 f8b9 	bl	4cc4 <z_priq_dumb_best>
    2b52:	4605      	mov	r5, r0
	if (_current->base.thread_state & _THREAD_ABORTING) {
    2b54:	68a3      	ldr	r3, [r4, #8]
    2b56:	7b59      	ldrb	r1, [r3, #13]
    2b58:	0688      	lsls	r0, r1, #26
		_current->base.thread_state |= _THREAD_DEAD;
    2b5a:	bf44      	itt	mi
    2b5c:	f041 0108 	orrmi.w	r1, r1, #8
    2b60:	7359      	strbmi	r1, [r3, #13]
	return thread ? thread : _current_cpu->idle_thread;
    2b62:	b905      	cbnz	r5, 2b66 <update_cache+0x22>
    2b64:	68e5      	ldr	r5, [r4, #12]
	if (preempt_ok != 0) {
    2b66:	b94e      	cbnz	r6, 2b7c <update_cache+0x38>
	if (z_is_thread_prevented_from_running(_current)) {
    2b68:	7b5a      	ldrb	r2, [r3, #13]
    2b6a:	06d2      	lsls	r2, r2, #27
    2b6c:	d106      	bne.n	2b7c <update_cache+0x38>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    2b6e:	69aa      	ldr	r2, [r5, #24]
    2b70:	b922      	cbnz	r2, 2b7c <update_cache+0x38>
	if (is_preempt(_current) || is_metairq(thread)) {
    2b72:	89da      	ldrh	r2, [r3, #14]
    2b74:	2a7f      	cmp	r2, #127	; 0x7f
    2b76:	d901      	bls.n	2b7c <update_cache+0x38>
		_kernel.ready_q.cache = _current;
    2b78:	6263      	str	r3, [r4, #36]	; 0x24
}
    2b7a:	bd70      	pop	{r4, r5, r6, pc}
		if (thread != _current) {
    2b7c:	42ab      	cmp	r3, r5
    2b7e:	d001      	beq.n	2b84 <update_cache+0x40>
			z_reset_time_slice();
    2b80:	f7ff ff62 	bl	2a48 <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    2b84:	6265      	str	r5, [r4, #36]	; 0x24
}
    2b86:	e7f8      	b.n	2b7a <update_cache+0x36>
    2b88:	20000810 	.word	0x20000810

00002b8c <k_sched_unlock>:
{
    2b8c:	b510      	push	{r4, lr}
	__asm__ volatile(
    2b8e:	f04f 0320 	mov.w	r3, #32
    2b92:	f3ef 8411 	mrs	r4, BASEPRI
    2b96:	f383 8811 	msr	BASEPRI, r3
    2b9a:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    2b9e:	4b08      	ldr	r3, [pc, #32]	; (2bc0 <k_sched_unlock+0x34>)
		update_cache(0);
    2ba0:	2000      	movs	r0, #0
		++_current->base.sched_locked;
    2ba2:	689a      	ldr	r2, [r3, #8]
    2ba4:	7bd3      	ldrb	r3, [r2, #15]
    2ba6:	3301      	adds	r3, #1
    2ba8:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    2baa:	f7ff ffcb 	bl	2b44 <update_cache>
	__asm__ volatile(
    2bae:	f384 8811 	msr	BASEPRI, r4
    2bb2:	f3bf 8f6f 	isb	sy
}
    2bb6:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    2bba:	f002 b86d 	b.w	4c98 <z_reschedule_unlocked>
    2bbe:	bf00      	nop
    2bc0:	20000810 	.word	0x20000810

00002bc4 <ready_thread>:
{
    2bc4:	b470      	push	{r4, r5, r6}
	return !((z_is_thread_prevented_from_running(thread)) != 0 ||
    2bc6:	7b43      	ldrb	r3, [r0, #13]
    2bc8:	06db      	lsls	r3, r3, #27
    2bca:	d12a      	bne.n	2c22 <ready_thread+0x5e>

int z_abort_timeout(struct _timeout *to);

static inline bool z_is_inactive_timeout(struct _timeout *t)
{
	return !sys_dnode_is_linked(&t->node);
    2bcc:	6983      	ldr	r3, [r0, #24]
	if (z_is_thread_ready(thread)) {
    2bce:	bb43      	cbnz	r3, 2c22 <ready_thread+0x5e>
	return list->head == list;
    2bd0:	4a15      	ldr	r2, [pc, #84]	; (2c28 <ready_thread+0x64>)
    2bd2:	4611      	mov	r1, r2
    2bd4:	f851 4f28 	ldr.w	r4, [r1, #40]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    2bd8:	428c      	cmp	r4, r1
    2bda:	bf18      	it	ne
    2bdc:	4623      	movne	r3, r4
    2bde:	2b00      	cmp	r3, #0
    2be0:	bf38      	it	cc
    2be2:	2300      	movcc	r3, #0
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    2be4:	6ad4      	ldr	r4, [r2, #44]	; 0x2c
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    2be6:	b1b3      	cbz	r3, 2c16 <ready_thread+0x52>
	if (thread_1->base.prio < thread_2->base.prio) {
    2be8:	f990 600e 	ldrsb.w	r6, [r0, #14]
    2bec:	f993 500e 	ldrsb.w	r5, [r3, #14]
    2bf0:	42ae      	cmp	r6, r5
    2bf2:	db03      	blt.n	2bfc <ready_thread+0x38>
	return (node == list->tail) ? NULL : node->next;
    2bf4:	42a3      	cmp	r3, r4
    2bf6:	d00e      	beq.n	2c16 <ready_thread+0x52>
    2bf8:	681b      	ldr	r3, [r3, #0]
    2bfa:	e7f4      	b.n	2be6 <ready_thread+0x22>
	node->prev = successor->prev;
    2bfc:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    2bfe:	e9c0 3200 	strd	r3, r2, [r0]
	successor->prev->next = node;
    2c02:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    2c04:	6058      	str	r0, [r3, #4]
	thread->base.thread_state |= states;
    2c06:	7b43      	ldrb	r3, [r0, #13]
    2c08:	f063 037f 	orn	r3, r3, #127	; 0x7f
    2c0c:	7343      	strb	r3, [r0, #13]
}
    2c0e:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    2c10:	2000      	movs	r0, #0
    2c12:	f7ff bf97 	b.w	2b44 <update_cache>
	node->prev = list->tail;
    2c16:	e9c0 1400 	strd	r1, r4, [r0]
	list->tail->next = node;
    2c1a:	6ad3      	ldr	r3, [r2, #44]	; 0x2c
    2c1c:	6018      	str	r0, [r3, #0]
	list->tail = node;
    2c1e:	62d0      	str	r0, [r2, #44]	; 0x2c
}
    2c20:	e7f1      	b.n	2c06 <ready_thread+0x42>
}
    2c22:	bc70      	pop	{r4, r5, r6}
    2c24:	4770      	bx	lr
    2c26:	bf00      	nop
    2c28:	20000810 	.word	0x20000810

00002c2c <z_sched_start>:
{
    2c2c:	b510      	push	{r4, lr}
	__asm__ volatile(
    2c2e:	f04f 0220 	mov.w	r2, #32
    2c32:	f3ef 8411 	mrs	r4, BASEPRI
    2c36:	f382 8811 	msr	BASEPRI, r2
    2c3a:	f3bf 8f6f 	isb	sy
	if (z_has_thread_started(thread)) {
    2c3e:	7b42      	ldrb	r2, [r0, #13]
    2c40:	0751      	lsls	r1, r2, #29
    2c42:	d404      	bmi.n	2c4e <z_sched_start+0x22>
	__asm__ volatile(
    2c44:	f384 8811 	msr	BASEPRI, r4
    2c48:	f3bf 8f6f 	isb	sy
}
    2c4c:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    2c4e:	f022 0204 	bic.w	r2, r2, #4
    2c52:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    2c54:	f7ff ffb6 	bl	2bc4 <ready_thread>
	z_reschedule(&sched_spinlock, key);
    2c58:	4621      	mov	r1, r4
}
    2c5a:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    2c5e:	4801      	ldr	r0, [pc, #4]	; (2c64 <z_sched_start+0x38>)
    2c60:	f7ff bf34 	b.w	2acc <z_reschedule>
    2c64:	2000086e 	.word	0x2000086e

00002c68 <move_thread_to_end_of_prio_q>:
{
    2c68:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    2c6a:	f990 300d 	ldrsb.w	r3, [r0, #13]
{
    2c6e:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    2c70:	2b00      	cmp	r3, #0
    2c72:	da02      	bge.n	2c7a <move_thread_to_end_of_prio_q+0x12>
		_priq_run_remove(&_kernel.ready_q.runq, thread);
    2c74:	4817      	ldr	r0, [pc, #92]	; (2cd4 <move_thread_to_end_of_prio_q+0x6c>)
    2c76:	f7ff ff4f 	bl	2b18 <z_priq_dumb_remove>
	return list->head == list;
    2c7a:	4a17      	ldr	r2, [pc, #92]	; (2cd8 <move_thread_to_end_of_prio_q+0x70>)
    2c7c:	4610      	mov	r0, r2
    2c7e:	f850 3f28 	ldr.w	r3, [r0, #40]!
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    2c82:	6ad4      	ldr	r4, [r2, #44]	; 0x2c
	return sys_dlist_is_empty(list) ? NULL : list->head;
    2c84:	4283      	cmp	r3, r0
    2c86:	bf08      	it	eq
    2c88:	2300      	moveq	r3, #0
    2c8a:	2b00      	cmp	r3, #0
    2c8c:	bf38      	it	cc
    2c8e:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    2c90:	b1d3      	cbz	r3, 2cc8 <move_thread_to_end_of_prio_q+0x60>
	if (thread_1->base.prio < thread_2->base.prio) {
    2c92:	f991 600e 	ldrsb.w	r6, [r1, #14]
    2c96:	f993 500e 	ldrsb.w	r5, [r3, #14]
    2c9a:	42ae      	cmp	r6, r5
    2c9c:	db03      	blt.n	2ca6 <move_thread_to_end_of_prio_q+0x3e>
	return (node == list->tail) ? NULL : node->next;
    2c9e:	42a3      	cmp	r3, r4
    2ca0:	d012      	beq.n	2cc8 <move_thread_to_end_of_prio_q+0x60>
    2ca2:	681b      	ldr	r3, [r3, #0]
    2ca4:	e7f4      	b.n	2c90 <move_thread_to_end_of_prio_q+0x28>
	node->prev = successor->prev;
    2ca6:	6858      	ldr	r0, [r3, #4]
	node->next = successor;
    2ca8:	e9c1 3000 	strd	r3, r0, [r1]
	successor->prev->next = node;
    2cac:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    2cae:	6059      	str	r1, [r3, #4]
	thread->base.thread_state |= states;
    2cb0:	7b4b      	ldrb	r3, [r1, #13]
	update_cache(thread == _current);
    2cb2:	6890      	ldr	r0, [r2, #8]
    2cb4:	f063 037f 	orn	r3, r3, #127	; 0x7f
    2cb8:	734b      	strb	r3, [r1, #13]
    2cba:	1a43      	subs	r3, r0, r1
    2cbc:	4258      	negs	r0, r3
    2cbe:	4158      	adcs	r0, r3
}
    2cc0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    2cc4:	f7ff bf3e 	b.w	2b44 <update_cache>
	node->prev = list->tail;
    2cc8:	e9c1 0400 	strd	r0, r4, [r1]
	list->tail->next = node;
    2ccc:	6ad3      	ldr	r3, [r2, #44]	; 0x2c
    2cce:	6019      	str	r1, [r3, #0]
	list->tail = node;
    2cd0:	62d1      	str	r1, [r2, #44]	; 0x2c
}
    2cd2:	e7ed      	b.n	2cb0 <move_thread_to_end_of_prio_q+0x48>
    2cd4:	20000838 	.word	0x20000838
    2cd8:	20000810 	.word	0x20000810

00002cdc <z_time_slice>:
{
    2cdc:	4601      	mov	r1, r0
    2cde:	b570      	push	{r4, r5, r6, lr}
	__asm__ volatile(
    2ce0:	f04f 0320 	mov.w	r3, #32
    2ce4:	f3ef 8411 	mrs	r4, BASEPRI
    2ce8:	f383 8811 	msr	BASEPRI, r3
    2cec:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    2cf0:	4b16      	ldr	r3, [pc, #88]	; (2d4c <z_time_slice+0x70>)
    2cf2:	4a17      	ldr	r2, [pc, #92]	; (2d50 <z_time_slice+0x74>)
    2cf4:	6898      	ldr	r0, [r3, #8]
    2cf6:	6815      	ldr	r5, [r2, #0]
    2cf8:	42a8      	cmp	r0, r5
    2cfa:	461d      	mov	r5, r3
    2cfc:	d106      	bne.n	2d0c <z_time_slice+0x30>
			z_reset_time_slice();
    2cfe:	f7ff fea3 	bl	2a48 <z_reset_time_slice>
	__asm__ volatile(
    2d02:	f384 8811 	msr	BASEPRI, r4
    2d06:	f3bf 8f6f 	isb	sy
}
    2d0a:	bd70      	pop	{r4, r5, r6, pc}
	pending_current = NULL;
    2d0c:	2600      	movs	r6, #0
    2d0e:	6016      	str	r6, [r2, #0]
	if (slice_time && sliceable(_current)) {
    2d10:	4a10      	ldr	r2, [pc, #64]	; (2d54 <z_time_slice+0x78>)
    2d12:	6812      	ldr	r2, [r2, #0]
    2d14:	b1ba      	cbz	r2, 2d46 <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    2d16:	89c2      	ldrh	r2, [r0, #14]
    2d18:	2a7f      	cmp	r2, #127	; 0x7f
    2d1a:	d814      	bhi.n	2d46 <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
    2d1c:	7b42      	ldrb	r2, [r0, #13]
    2d1e:	06d2      	lsls	r2, r2, #27
    2d20:	d111      	bne.n	2d46 <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    2d22:	4a0d      	ldr	r2, [pc, #52]	; (2d58 <z_time_slice+0x7c>)
    2d24:	f990 600e 	ldrsb.w	r6, [r0, #14]
    2d28:	6812      	ldr	r2, [r2, #0]
    2d2a:	4296      	cmp	r6, r2
    2d2c:	db0b      	blt.n	2d46 <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    2d2e:	4a0b      	ldr	r2, [pc, #44]	; (2d5c <z_time_slice+0x80>)
    2d30:	4290      	cmp	r0, r2
    2d32:	d008      	beq.n	2d46 <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
    2d34:	691a      	ldr	r2, [r3, #16]
    2d36:	428a      	cmp	r2, r1
    2d38:	dc02      	bgt.n	2d40 <z_time_slice+0x64>
			move_thread_to_end_of_prio_q(_current);
    2d3a:	f7ff ff95 	bl	2c68 <move_thread_to_end_of_prio_q>
    2d3e:	e7de      	b.n	2cfe <z_time_slice+0x22>
			_current_cpu->slice_ticks -= ticks;
    2d40:	1a52      	subs	r2, r2, r1
    2d42:	611a      	str	r2, [r3, #16]
    2d44:	e7dd      	b.n	2d02 <z_time_slice+0x26>
		_current_cpu->slice_ticks = 0;
    2d46:	2300      	movs	r3, #0
    2d48:	612b      	str	r3, [r5, #16]
    2d4a:	e7da      	b.n	2d02 <z_time_slice+0x26>
    2d4c:	20000810 	.word	0x20000810
    2d50:	20000840 	.word	0x20000840
    2d54:	20000848 	.word	0x20000848
    2d58:	20000844 	.word	0x20000844
    2d5c:	20000160 	.word	0x20000160

00002d60 <z_impl_k_thread_suspend>:
{
    2d60:	b570      	push	{r4, r5, r6, lr}
    2d62:	4604      	mov	r4, r0
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    2d64:	3018      	adds	r0, #24
    2d66:	f002 f83f 	bl	4de8 <z_abort_timeout>
	__asm__ volatile(
    2d6a:	f04f 0320 	mov.w	r3, #32
    2d6e:	f3ef 8611 	mrs	r6, BASEPRI
    2d72:	f383 8811 	msr	BASEPRI, r3
    2d76:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    2d7a:	f994 300d 	ldrsb.w	r3, [r4, #13]
    2d7e:	2b00      	cmp	r3, #0
    2d80:	da07      	bge.n	2d92 <z_impl_k_thread_suspend+0x32>
			_priq_run_remove(&_kernel.ready_q.runq, thread);
    2d82:	4621      	mov	r1, r4
    2d84:	480e      	ldr	r0, [pc, #56]	; (2dc0 <z_impl_k_thread_suspend+0x60>)
    2d86:	f7ff fec7 	bl	2b18 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    2d8a:	7b63      	ldrb	r3, [r4, #13]
    2d8c:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    2d90:	7363      	strb	r3, [r4, #13]
		update_cache(thread == _current);
    2d92:	4d0c      	ldr	r5, [pc, #48]	; (2dc4 <z_impl_k_thread_suspend+0x64>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    2d94:	7b63      	ldrb	r3, [r4, #13]
    2d96:	68a8      	ldr	r0, [r5, #8]
    2d98:	f043 0310 	orr.w	r3, r3, #16
    2d9c:	7363      	strb	r3, [r4, #13]
    2d9e:	1b03      	subs	r3, r0, r4
    2da0:	4258      	negs	r0, r3
    2da2:	4158      	adcs	r0, r3
    2da4:	f7ff fece 	bl	2b44 <update_cache>
	__asm__ volatile(
    2da8:	f386 8811 	msr	BASEPRI, r6
    2dac:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    2db0:	68ab      	ldr	r3, [r5, #8]
    2db2:	42a3      	cmp	r3, r4
    2db4:	d103      	bne.n	2dbe <z_impl_k_thread_suspend+0x5e>
}
    2db6:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    2dba:	f001 bf6d 	b.w	4c98 <z_reschedule_unlocked>
}
    2dbe:	bd70      	pop	{r4, r5, r6, pc}
    2dc0:	20000838 	.word	0x20000838
    2dc4:	20000810 	.word	0x20000810

00002dc8 <z_thread_single_abort>:
	if (thread->fn_abort != NULL) {
    2dc8:	6e03      	ldr	r3, [r0, #96]	; 0x60
{
    2dca:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    2dce:	4604      	mov	r4, r0
	if (thread->fn_abort != NULL) {
    2dd0:	b103      	cbz	r3, 2dd4 <z_thread_single_abort+0xc>
		thread->fn_abort();
    2dd2:	4798      	blx	r3
    2dd4:	f104 0018 	add.w	r0, r4, #24
    2dd8:	f002 f806 	bl	4de8 <z_abort_timeout>
	__asm__ volatile(
    2ddc:	f04f 0320 	mov.w	r3, #32
    2de0:	f3ef 8611 	mrs	r6, BASEPRI
    2de4:	f383 8811 	msr	BASEPRI, r3
    2de8:	f3bf 8f6f 	isb	sy
	return !((z_is_thread_prevented_from_running(thread)) != 0 ||
    2dec:	7b63      	ldrb	r3, [r4, #13]
    2dee:	06d8      	lsls	r0, r3, #27
    2df0:	d123      	bne.n	2e3a <z_thread_single_abort+0x72>
		if (z_is_thread_ready(thread)) {
    2df2:	69a2      	ldr	r2, [r4, #24]
    2df4:	bb0a      	cbnz	r2, 2e3a <z_thread_single_abort+0x72>
			if (z_is_thread_queued(thread)) {
    2df6:	0619      	lsls	r1, r3, #24
    2df8:	d507      	bpl.n	2e0a <z_thread_single_abort+0x42>
				_priq_run_remove(&_kernel.ready_q.runq,
    2dfa:	4621      	mov	r1, r4
    2dfc:	481e      	ldr	r0, [pc, #120]	; (2e78 <z_thread_single_abort+0xb0>)
    2dfe:	f7ff fe8b 	bl	2b18 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    2e02:	7b63      	ldrb	r3, [r4, #13]
    2e04:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    2e08:	7363      	strb	r3, [r4, #13]
			update_cache(thread == _current);
    2e0a:	4b1c      	ldr	r3, [pc, #112]	; (2e7c <z_thread_single_abort+0xb4>)
    2e0c:	6898      	ldr	r0, [r3, #8]
    2e0e:	1b02      	subs	r2, r0, r4
    2e10:	4250      	negs	r0, r2
    2e12:	4150      	adcs	r0, r2
    2e14:	f7ff fe96 	bl	2b44 <update_cache>
			waiter->base.pended_on = NULL;
    2e18:	2700      	movs	r7, #0
		thread->base.thread_state |= mask;
    2e1a:	7b63      	ldrb	r3, [r4, #13]
	sys_dlist_init(&w->waitq);
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    2e1c:	f104 0830 	add.w	r8, r4, #48	; 0x30
    2e20:	f043 0308 	orr.w	r3, r3, #8
    2e24:	7363      	strb	r3, [r4, #13]
	return list->head == list;
    2e26:	6b25      	ldr	r5, [r4, #48]	; 0x30
	return sys_dlist_is_empty(list) ? NULL : list->head;
    2e28:	4545      	cmp	r5, r8
    2e2a:	d000      	beq.n	2e2e <z_thread_single_abort+0x66>
		while ((waiter = z_waitq_head(&thread->base.join_waiters)) !=
    2e2c:	b995      	cbnz	r5, 2e54 <z_thread_single_abort+0x8c>
	__asm__ volatile(
    2e2e:	f386 8811 	msr	BASEPRI, r6
    2e32:	f3bf 8f6f 	isb	sy
}
    2e36:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
			if (z_is_thread_pending(thread)) {
    2e3a:	079b      	lsls	r3, r3, #30
    2e3c:	d5ec      	bpl.n	2e18 <z_thread_single_abort+0x50>
				_priq_wait_remove(&pended_on(thread)->waitq,
    2e3e:	4621      	mov	r1, r4
    2e40:	68a0      	ldr	r0, [r4, #8]
    2e42:	f7ff fe69 	bl	2b18 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    2e46:	7b63      	ldrb	r3, [r4, #13]
    2e48:	f023 0302 	bic.w	r3, r3, #2
    2e4c:	7363      	strb	r3, [r4, #13]
				thread->base.pended_on = NULL;
    2e4e:	2300      	movs	r3, #0
    2e50:	60a3      	str	r3, [r4, #8]
    2e52:	e7e1      	b.n	2e18 <z_thread_single_abort+0x50>
    2e54:	f105 0018 	add.w	r0, r5, #24
    2e58:	f001 ffc6 	bl	4de8 <z_abort_timeout>
			_priq_wait_remove(&pended_on(waiter)->waitq, waiter);
    2e5c:	68a8      	ldr	r0, [r5, #8]
    2e5e:	4629      	mov	r1, r5
    2e60:	f7ff fe5a 	bl	2b18 <z_priq_dumb_remove>
    2e64:	7b6b      	ldrb	r3, [r5, #13]
			ready_thread(waiter);
    2e66:	4628      	mov	r0, r5
    2e68:	f023 0302 	bic.w	r3, r3, #2
    2e6c:	736b      	strb	r3, [r5, #13]
			waiter->base.pended_on = NULL;
    2e6e:	60af      	str	r7, [r5, #8]
    2e70:	67ef      	str	r7, [r5, #124]	; 0x7c
			ready_thread(waiter);
    2e72:	f7ff fea7 	bl	2bc4 <ready_thread>
    2e76:	e7d6      	b.n	2e26 <z_thread_single_abort+0x5e>
    2e78:	20000838 	.word	0x20000838
    2e7c:	20000810 	.word	0x20000810

00002e80 <unready_thread>:
{
    2e80:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    2e82:	f990 300d 	ldrsb.w	r3, [r0, #13]
{
    2e86:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    2e88:	2b00      	cmp	r3, #0
    2e8a:	da06      	bge.n	2e9a <unready_thread+0x1a>
		_priq_run_remove(&_kernel.ready_q.runq, thread);
    2e8c:	4807      	ldr	r0, [pc, #28]	; (2eac <unready_thread+0x2c>)
    2e8e:	f7ff fe43 	bl	2b18 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    2e92:	7b4b      	ldrb	r3, [r1, #13]
    2e94:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    2e98:	734b      	strb	r3, [r1, #13]
	update_cache(thread == _current);
    2e9a:	4b05      	ldr	r3, [pc, #20]	; (2eb0 <unready_thread+0x30>)
    2e9c:	6898      	ldr	r0, [r3, #8]
    2e9e:	1a43      	subs	r3, r0, r1
    2ea0:	4258      	negs	r0, r3
    2ea2:	4158      	adcs	r0, r3
}
    2ea4:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    2ea8:	f7ff be4c 	b.w	2b44 <update_cache>
    2eac:	20000838 	.word	0x20000838
    2eb0:	20000810 	.word	0x20000810

00002eb4 <pend>:
{
    2eb4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    2eb8:	4606      	mov	r6, r0
    2eba:	4614      	mov	r4, r2
    2ebc:	461d      	mov	r5, r3
	__asm__ volatile(
    2ebe:	f04f 0320 	mov.w	r3, #32
    2ec2:	f3ef 8711 	mrs	r7, BASEPRI
    2ec6:	f383 8811 	msr	BASEPRI, r3
    2eca:	f3bf 8f6f 	isb	sy
		add_to_waitq_locked(thread, wait_q);
    2ece:	f001 ff33 	bl	4d38 <add_to_waitq_locked>
	__asm__ volatile(
    2ed2:	f387 8811 	msr	BASEPRI, r7
    2ed6:	f3bf 8f6f 	isb	sy
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    2eda:	1c6b      	adds	r3, r5, #1
    2edc:	bf08      	it	eq
    2ede:	f1b4 3fff 	cmpeq.w	r4, #4294967295
    2ee2:	d008      	beq.n	2ef6 <pend+0x42>
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
    2ee4:	4622      	mov	r2, r4
    2ee6:	462b      	mov	r3, r5
    2ee8:	f106 0018 	add.w	r0, r6, #24
    2eec:	4903      	ldr	r1, [pc, #12]	; (2efc <pend+0x48>)
}
    2eee:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    2ef2:	f000 ba2f 	b.w	3354 <z_add_timeout>
    2ef6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    2efa:	bf00      	nop
    2efc:	00004cf9 	.word	0x00004cf9

00002f00 <z_pend_curr>:
{
    2f00:	b510      	push	{r4, lr}
    2f02:	460c      	mov	r4, r1
	pending_current = _current;
    2f04:	4b06      	ldr	r3, [pc, #24]	; (2f20 <z_pend_curr+0x20>)
{
    2f06:	4611      	mov	r1, r2
	pending_current = _current;
    2f08:	6898      	ldr	r0, [r3, #8]
    2f0a:	4b06      	ldr	r3, [pc, #24]	; (2f24 <z_pend_curr+0x24>)
    2f0c:	6018      	str	r0, [r3, #0]
	pend(_current, wait_q, timeout);
    2f0e:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    2f12:	f7ff ffcf 	bl	2eb4 <pend>
    2f16:	4620      	mov	r0, r4
}
    2f18:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    2f1c:	f7fe bb5e 	b.w	15dc <arch_swap>
    2f20:	20000810 	.word	0x20000810
    2f24:	20000840 	.word	0x20000840

00002f28 <z_tick_sleep.part.0>:
	z_impl_k_yield();
}
#include <syscalls/k_yield_mrsh.c>
#endif

static int32_t z_tick_sleep(int32_t ticks)
    2f28:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2f2a:	4605      	mov	r5, r0
#else
	ticks += _TICK_ALIGN;
	timeout = (k_ticks_t) ticks;
#endif

	expected_wakeup_time = ticks + z_tick_get_32();
    2f2c:	f001 ff9d 	bl	4e6a <z_tick_get_32>
    2f30:	182c      	adds	r4, r5, r0
	__asm__ volatile(
    2f32:	f04f 0320 	mov.w	r3, #32
    2f36:	f3ef 8711 	mrs	r7, BASEPRI
    2f3a:	f383 8811 	msr	BASEPRI, r3
    2f3e:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

#if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC)
	pending_current = _current;
    2f42:	4e0d      	ldr	r6, [pc, #52]	; (2f78 <z_tick_sleep.part.0+0x50>)
    2f44:	4b0d      	ldr	r3, [pc, #52]	; (2f7c <z_tick_sleep.part.0+0x54>)
    2f46:	68b0      	ldr	r0, [r6, #8]
    2f48:	6018      	str	r0, [r3, #0]
#endif
	unready_thread(_current);
    2f4a:	f7ff ff99 	bl	2e80 <unready_thread>
	z_add_thread_timeout(_current, timeout);
    2f4e:	68b0      	ldr	r0, [r6, #8]
    2f50:	490b      	ldr	r1, [pc, #44]	; (2f80 <z_tick_sleep.part.0+0x58>)
    2f52:	462a      	mov	r2, r5
    2f54:	17eb      	asrs	r3, r5, #31
    2f56:	3018      	adds	r0, #24
    2f58:	f000 f9fc 	bl	3354 <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    2f5c:	68b2      	ldr	r2, [r6, #8]
    2f5e:	4638      	mov	r0, r7
	thread->base.thread_state |= _THREAD_SUSPENDED;
    2f60:	7b53      	ldrb	r3, [r2, #13]
    2f62:	f043 0310 	orr.w	r3, r3, #16
    2f66:	7353      	strb	r3, [r2, #13]
    2f68:	f7fe fb38 	bl	15dc <arch_swap>

	(void)z_swap(&sched_spinlock, key);

	__ASSERT(!z_is_thread_state_set(_current, _THREAD_SUSPENDED), "");

	ticks = expected_wakeup_time - z_tick_get_32();
    2f6c:	f001 ff7d 	bl	4e6a <z_tick_get_32>
    2f70:	1a20      	subs	r0, r4, r0
		return ticks;
	}
#endif

	return 0;
}
    2f72:	ea20 70e0 	bic.w	r0, r0, r0, asr #31
    2f76:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    2f78:	20000810 	.word	0x20000810
    2f7c:	20000840 	.word	0x20000840
    2f80:	00004cf9 	.word	0x00004cf9

00002f84 <z_set_prio>:
{
    2f84:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    2f88:	4604      	mov	r4, r0
    2f8a:	f04f 0320 	mov.w	r3, #32
    2f8e:	f3ef 8811 	mrs	r8, BASEPRI
    2f92:	f383 8811 	msr	BASEPRI, r3
    2f96:	f3bf 8f6f 	isb	sy
	return !((z_is_thread_prevented_from_running(thread)) != 0 ||
    2f9a:	7b43      	ldrb	r3, [r0, #13]
    2f9c:	b24e      	sxtb	r6, r1
    2f9e:	06db      	lsls	r3, r3, #27
    2fa0:	d12e      	bne.n	3000 <z_set_prio+0x7c>
	return !sys_dnode_is_linked(&t->node);
    2fa2:	6985      	ldr	r5, [r0, #24]
		if (need_sched) {
    2fa4:	bb65      	cbnz	r5, 3000 <z_set_prio+0x7c>
				_priq_run_remove(&_kernel.ready_q.runq, thread);
    2fa6:	4f18      	ldr	r7, [pc, #96]	; (3008 <z_set_prio+0x84>)
    2fa8:	4621      	mov	r1, r4
    2faa:	f107 0028 	add.w	r0, r7, #40	; 0x28
    2fae:	f7ff fdb3 	bl	2b18 <z_priq_dumb_remove>
	return list->head == list;
    2fb2:	6abb      	ldr	r3, [r7, #40]	; 0x28
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    2fb4:	6afa      	ldr	r2, [r7, #44]	; 0x2c
	return sys_dlist_is_empty(list) ? NULL : list->head;
    2fb6:	4283      	cmp	r3, r0
    2fb8:	bf18      	it	ne
    2fba:	461d      	movne	r5, r3
    2fbc:	2d00      	cmp	r5, #0
    2fbe:	bf38      	it	cc
    2fc0:	2500      	movcc	r5, #0
				thread->base.prio = prio;
    2fc2:	73a6      	strb	r6, [r4, #14]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    2fc4:	b1b5      	cbz	r5, 2ff4 <z_set_prio+0x70>
	if (thread_1->base.prio < thread_2->base.prio) {
    2fc6:	f995 100e 	ldrsb.w	r1, [r5, #14]
    2fca:	42b1      	cmp	r1, r6
    2fcc:	dc03      	bgt.n	2fd6 <z_set_prio+0x52>
	return (node == list->tail) ? NULL : node->next;
    2fce:	42aa      	cmp	r2, r5
    2fd0:	d010      	beq.n	2ff4 <z_set_prio+0x70>
    2fd2:	682d      	ldr	r5, [r5, #0]
    2fd4:	e7f6      	b.n	2fc4 <z_set_prio+0x40>
	node->prev = successor->prev;
    2fd6:	686a      	ldr	r2, [r5, #4]
	node->next = successor;
    2fd8:	e9c4 5200 	strd	r5, r2, [r4]
	successor->prev->next = node;
    2fdc:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    2fde:	606c      	str	r4, [r5, #4]
			update_cache(1);
    2fe0:	2001      	movs	r0, #1
    2fe2:	f7ff fdaf 	bl	2b44 <update_cache>
    2fe6:	2001      	movs	r0, #1
	__asm__ volatile(
    2fe8:	f388 8811 	msr	BASEPRI, r8
    2fec:	f3bf 8f6f 	isb	sy
}
    2ff0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	node->prev = list->tail;
    2ff4:	e9c4 0200 	strd	r0, r2, [r4]
	list->tail->next = node;
    2ff8:	6afb      	ldr	r3, [r7, #44]	; 0x2c
    2ffa:	601c      	str	r4, [r3, #0]
	list->tail = node;
    2ffc:	62fc      	str	r4, [r7, #44]	; 0x2c
}
    2ffe:	e7ef      	b.n	2fe0 <z_set_prio+0x5c>
			thread->base.prio = prio;
    3000:	2000      	movs	r0, #0
    3002:	73a6      	strb	r6, [r4, #14]
    3004:	e7f0      	b.n	2fe8 <z_set_prio+0x64>
    3006:	bf00      	nop
    3008:	20000810 	.word	0x20000810

0000300c <z_sched_init>:
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    300c:	2100      	movs	r1, #0
	list->head = (sys_dnode_t *)list;
    300e:	4b04      	ldr	r3, [pc, #16]	; (3020 <z_sched_init+0x14>)
    3010:	4608      	mov	r0, r1
    3012:	f103 0228 	add.w	r2, r3, #40	; 0x28
	list->tail = (sys_dnode_t *)list;
    3016:	e9c3 220a 	strd	r2, r2, [r3, #40]	; 0x28
    301a:	f7ff bd2b 	b.w	2a74 <k_sched_time_slice_set>
    301e:	bf00      	nop
    3020:	20000810 	.word	0x20000810

00003024 <z_impl_k_yield>:
{
    3024:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	if (!z_is_idle_thread_object(_current)) {
    3026:	4c24      	ldr	r4, [pc, #144]	; (30b8 <z_impl_k_yield+0x94>)
    3028:	4b24      	ldr	r3, [pc, #144]	; (30bc <z_impl_k_yield+0x98>)
    302a:	68a2      	ldr	r2, [r4, #8]
    302c:	429a      	cmp	r2, r3
    302e:	d030      	beq.n	3092 <z_impl_k_yield+0x6e>
	__asm__ volatile(
    3030:	f04f 0320 	mov.w	r3, #32
    3034:	f3ef 8511 	mrs	r5, BASEPRI
    3038:	f383 8811 	msr	BASEPRI, r3
    303c:	f3bf 8f6f 	isb	sy
				_priq_run_remove(&_kernel.ready_q.runq,
    3040:	68a1      	ldr	r1, [r4, #8]
    3042:	f104 0028 	add.w	r0, r4, #40	; 0x28
    3046:	f7ff fd67 	bl	2b18 <z_priq_dumb_remove>
	return list->head == list;
    304a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
			_priq_run_add(&_kernel.ready_q.runq, _current);
    304c:	68a2      	ldr	r2, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    304e:	4283      	cmp	r3, r0
    3050:	bf08      	it	eq
    3052:	2300      	moveq	r3, #0
    3054:	2b00      	cmp	r3, #0
    3056:	bf38      	it	cc
    3058:	2300      	movcc	r3, #0
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    305a:	6ae1      	ldr	r1, [r4, #44]	; 0x2c
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    305c:	b32b      	cbz	r3, 30aa <z_impl_k_yield+0x86>
	if (thread_1->base.prio < thread_2->base.prio) {
    305e:	f992 700e 	ldrsb.w	r7, [r2, #14]
    3062:	f993 600e 	ldrsb.w	r6, [r3, #14]
    3066:	42b7      	cmp	r7, r6
    3068:	db03      	blt.n	3072 <z_impl_k_yield+0x4e>
	return (node == list->tail) ? NULL : node->next;
    306a:	428b      	cmp	r3, r1
    306c:	d01d      	beq.n	30aa <z_impl_k_yield+0x86>
    306e:	681b      	ldr	r3, [r3, #0]
    3070:	e7f4      	b.n	305c <z_impl_k_yield+0x38>
	node->prev = successor->prev;
    3072:	6859      	ldr	r1, [r3, #4]
	node->next = successor;
    3074:	e9c2 3100 	strd	r3, r1, [r2]
	successor->prev->next = node;
    3078:	600a      	str	r2, [r1, #0]
	successor->prev = node;
    307a:	605a      	str	r2, [r3, #4]
	thread->base.thread_state |= states;
    307c:	7b53      	ldrb	r3, [r2, #13]
			update_cache(1);
    307e:	2001      	movs	r0, #1
    3080:	f063 037f 	orn	r3, r3, #127	; 0x7f
    3084:	7353      	strb	r3, [r2, #13]
    3086:	f7ff fd5d 	bl	2b44 <update_cache>
	__asm__ volatile(
    308a:	f385 8811 	msr	BASEPRI, r5
    308e:	f3bf 8f6f 	isb	sy
	__asm__ volatile(
    3092:	f04f 0320 	mov.w	r3, #32
    3096:	f3ef 8011 	mrs	r0, BASEPRI
    309a:	f383 8811 	msr	BASEPRI, r3
    309e:	f3bf 8f6f 	isb	sy
}
    30a2:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    30a6:	f7fe ba99 	b.w	15dc <arch_swap>
	node->prev = list->tail;
    30aa:	e9c2 0100 	strd	r0, r1, [r2]
	list->tail->next = node;
    30ae:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    30b0:	601a      	str	r2, [r3, #0]
	list->tail = node;
    30b2:	62e2      	str	r2, [r4, #44]	; 0x2c
}
    30b4:	e7e2      	b.n	307c <z_impl_k_yield+0x58>
    30b6:	bf00      	nop
    30b8:	20000810 	.word	0x20000810
    30bc:	20000160 	.word	0x20000160

000030c0 <z_impl_k_sleep>:

int32_t z_impl_k_sleep(k_timeout_t timeout)
{
    30c0:	460b      	mov	r3, r1
	k_ticks_t ticks;

	__ASSERT(!arch_is_in_isr(), "");
	sys_trace_void(SYS_TRACE_ID_SLEEP);

	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    30c2:	3301      	adds	r3, #1
    30c4:	bf08      	it	eq
    30c6:	f1b0 3fff 	cmpeq.w	r0, #4294967295
{
    30ca:	b510      	push	{r4, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    30cc:	d106      	bne.n	30dc <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
    30ce:	4b0b      	ldr	r3, [pc, #44]	; (30fc <z_impl_k_sleep+0x3c>)
    30d0:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    30d2:	f7ff fe45 	bl	2d60 <z_impl_k_thread_suspend>
		return (int32_t) K_TICKS_FOREVER;
    30d6:	f04f 30ff 	mov.w	r0, #4294967295
#endif

	ticks = z_tick_sleep(ticks);
	sys_trace_end_call(SYS_TRACE_ID_SLEEP);
	return k_ticks_to_ms_floor64(ticks);
}
    30da:	bd10      	pop	{r4, pc}
	ticks = z_tick_sleep(ticks);
    30dc:	4604      	mov	r4, r0
	if (ticks == 0) {
    30de:	b948      	cbnz	r0, 30f4 <z_impl_k_sleep+0x34>
	z_impl_k_yield();
    30e0:	f7ff ffa0 	bl	3024 <z_impl_k_yield>
		} else {
			return (t * to_hz + off) / from_hz;
    30e4:	f44f 707a 	mov.w	r0, #1000	; 0x3e8
    30e8:	fb84 3400 	smull	r3, r4, r4, r0
    30ec:	0bd8      	lsrs	r0, r3, #15
    30ee:	ea40 4044 	orr.w	r0, r0, r4, lsl #17
	return k_ticks_to_ms_floor64(ticks);
    30f2:	e7f2      	b.n	30da <z_impl_k_sleep+0x1a>
    30f4:	f7ff ff18 	bl	2f28 <z_tick_sleep.part.0>
    30f8:	4604      	mov	r4, r0
    30fa:	e7f3      	b.n	30e4 <z_impl_k_sleep+0x24>
    30fc:	20000810 	.word	0x20000810

00003100 <z_impl_k_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    3100:	4b01      	ldr	r3, [pc, #4]	; (3108 <z_impl_k_current_get+0x8>)
    3102:	6898      	ldr	r0, [r3, #8]
    3104:	4770      	bx	lr
    3106:	bf00      	nop
    3108:	20000810 	.word	0x20000810

0000310c <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    310c:	b538      	push	{r3, r4, r5, lr}
    310e:	4604      	mov	r4, r0
    3110:	f04f 0320 	mov.w	r3, #32
    3114:	f3ef 8511 	mrs	r5, BASEPRI
    3118:	f383 8811 	msr	BASEPRI, r3
    311c:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	sys_trace_semaphore_give(sem);
	thread = z_unpend_first_thread(&sem->wait_q);
    3120:	f001 fe35 	bl	4d8e <z_unpend_first_thread>

	if (thread != NULL) {
    3124:	b148      	cbz	r0, 313a <z_impl_k_sem_give+0x2e>
    3126:	2200      	movs	r2, #0
    3128:	67c2      	str	r2, [r0, #124]	; 0x7c
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    312a:	f001 fdd5 	bl	4cd8 <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    312e:	4629      	mov	r1, r5
	sys_trace_end_call(SYS_TRACE_ID_SEMA_GIVE);
}
    3130:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    3134:	4804      	ldr	r0, [pc, #16]	; (3148 <z_impl_k_sem_give+0x3c>)
    3136:	f7ff bcc9 	b.w	2acc <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    313a:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    313e:	429a      	cmp	r2, r3
    3140:	bf18      	it	ne
    3142:	3301      	addne	r3, #1
    3144:	60a3      	str	r3, [r4, #8]
		handle_poll_events(sem);
    3146:	e7f2      	b.n	312e <z_impl_k_sem_give+0x22>
    3148:	2000086e 	.word	0x2000086e

0000314c <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    314c:	b537      	push	{r0, r1, r2, r4, r5, lr}
    314e:	4614      	mov	r4, r2
    3150:	461d      	mov	r5, r3
    3152:	f04f 0320 	mov.w	r3, #32
    3156:	f3ef 8111 	mrs	r1, BASEPRI
    315a:	f383 8811 	msr	BASEPRI, r3
    315e:	f3bf 8f6f 	isb	sy
		  K_TIMEOUT_EQ(timeout, K_NO_WAIT)), "");

	k_spinlock_key_t key = k_spin_lock(&lock);
	sys_trace_semaphore_take(sem);

	if (likely(sem->count > 0U)) {
    3162:	6883      	ldr	r3, [r0, #8]
    3164:	b143      	cbz	r3, 3178 <z_impl_k_sem_take+0x2c>
		sem->count--;
    3166:	3b01      	subs	r3, #1
    3168:	6083      	str	r3, [r0, #8]
	__asm__ volatile(
    316a:	f381 8811 	msr	BASEPRI, r1
    316e:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    3172:	2000      	movs	r0, #0
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);

out:
	sys_trace_end_call(SYS_TRACE_ID_SEMA_TAKE);
	return ret;
}
    3174:	b003      	add	sp, #12
    3176:	bd30      	pop	{r4, r5, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    3178:	ea54 0305 	orrs.w	r3, r4, r5
    317c:	d106      	bne.n	318c <z_impl_k_sem_take+0x40>
    317e:	f381 8811 	msr	BASEPRI, r1
    3182:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    3186:	f06f 000f 	mvn.w	r0, #15
    318a:	e7f3      	b.n	3174 <z_impl_k_sem_take+0x28>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    318c:	4602      	mov	r2, r0
    318e:	e9cd 4500 	strd	r4, r5, [sp]
    3192:	4802      	ldr	r0, [pc, #8]	; (319c <z_impl_k_sem_take+0x50>)
    3194:	f7ff feb4 	bl	2f00 <z_pend_curr>
	return ret;
    3198:	e7ec      	b.n	3174 <z_impl_k_sem_take+0x28>
    319a:	bf00      	nop
    319c:	2000086e 	.word	0x2000086e

000031a0 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    31a0:	e92d 41b0 	stmdb	sp!, {r4, r5, r7, r8, lr}
	sys_dlist_init(&w->waitq);
    31a4:	f100 0530 	add.w	r5, r0, #48	; 0x30
    31a8:	b085      	sub	sp, #20
	list->tail = (sys_dnode_t *)list;
    31aa:	e9c0 550c 	strd	r5, r5, [r0, #48]	; 0x30
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */

	thread_base->user_options = (uint8_t)options;
    31ae:	9d0e      	ldr	r5, [sp, #56]	; 0x38
{
    31b0:	4604      	mov	r4, r0
	thread_base->user_options = (uint8_t)options;
    31b2:	7305      	strb	r5, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    31b4:	2504      	movs	r5, #4
    31b6:	7345      	strb	r5, [r0, #13]

	thread_base->prio = priority;
    31b8:	9d0d      	ldr	r5, [sp, #52]	; 0x34
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    31ba:	3207      	adds	r2, #7
	thread_base->prio = priority;
    31bc:	7385      	strb	r5, [r0, #14]

	thread_base->sched_locked = 0U;
    31be:	2500      	movs	r5, #0
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    31c0:	f022 0207 	bic.w	r2, r2, #7
	new_thread->stack_info.size = stack_buf_size;
    31c4:	e9c0 121a 	strd	r1, r2, [r0, #104]	; 0x68
	stack_ptr = (char *)stack + stack_obj_size;
    31c8:	eb01 0802 	add.w	r8, r1, r2
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    31cc:	9a0c      	ldr	r2, [sp, #48]	; 0x30
	node->prev = NULL;
    31ce:	e9c0 5506 	strd	r5, r5, [r0, #24]
	thread_base->sched_locked = 0U;
    31d2:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    31d4:	6705      	str	r5, [r0, #112]	; 0x70
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    31d6:	9202      	str	r2, [sp, #8]
    31d8:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    31da:	9201      	str	r2, [sp, #4]
    31dc:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    31de:	9200      	str	r2, [sp, #0]
    31e0:	4642      	mov	r2, r8
    31e2:	f7fe fa85 	bl	16f0 <arch_new_thread>
	if (!_current) {
    31e6:	4b05      	ldr	r3, [pc, #20]	; (31fc <z_setup_new_thread+0x5c>)
	new_thread->fn_abort = NULL;
    31e8:	e9c4 5517 	strd	r5, r5, [r4, #92]	; 0x5c
	if (!_current) {
    31ec:	689b      	ldr	r3, [r3, #8]
    31ee:	b103      	cbz	r3, 31f2 <z_setup_new_thread+0x52>
	new_thread->resource_pool = _current->resource_pool;
    31f0:	6f5b      	ldr	r3, [r3, #116]	; 0x74
}
    31f2:	4640      	mov	r0, r8
    31f4:	6763      	str	r3, [r4, #116]	; 0x74
    31f6:	b005      	add	sp, #20
    31f8:	e8bd 81b0 	ldmia.w	sp!, {r4, r5, r7, r8, pc}
    31fc:	20000810 	.word	0x20000810

00003200 <z_init_static_threads>:
{
    3200:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	_FOREACH_STATIC_THREAD(thread_data) {
    3204:	4e2a      	ldr	r6, [pc, #168]	; (32b0 <z_init_static_threads+0xb0>)
    3206:	4d2b      	ldr	r5, [pc, #172]	; (32b4 <z_init_static_threads+0xb4>)
    3208:	46b0      	mov	r8, r6
{
    320a:	b086      	sub	sp, #24
	_FOREACH_STATIC_THREAD(thread_data) {
    320c:	42b5      	cmp	r5, r6
    320e:	f105 0430 	add.w	r4, r5, #48	; 0x30
    3212:	d310      	bcc.n	3236 <z_init_static_threads+0x36>
	k_sched_lock();
    3214:	f7ff fc6c 	bl	2af0 <k_sched_lock>
    3218:	f44f 4900 	mov.w	r9, #32768	; 0x8000
    321c:	f240 36e7 	movw	r6, #999	; 0x3e7
    3220:	2700      	movs	r7, #0
	_FOREACH_STATIC_THREAD(thread_data) {
    3222:	4c24      	ldr	r4, [pc, #144]	; (32b4 <z_init_static_threads+0xb4>)
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
    3224:	f8df a090 	ldr.w	sl, [pc, #144]	; 32b8 <z_init_static_threads+0xb8>
    3228:	4544      	cmp	r4, r8
    322a:	d321      	bcc.n	3270 <z_init_static_threads+0x70>
}
    322c:	b006      	add	sp, #24
    322e:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	k_sched_unlock();
    3232:	f7ff bcab 	b.w	2b8c <k_sched_unlock>
		z_setup_new_thread(
    3236:	f854 3c04 	ldr.w	r3, [r4, #-4]
    323a:	9305      	str	r3, [sp, #20]
    323c:	f854 3c10 	ldr.w	r3, [r4, #-16]
    3240:	9304      	str	r3, [sp, #16]
    3242:	f854 3c14 	ldr.w	r3, [r4, #-20]
    3246:	9303      	str	r3, [sp, #12]
    3248:	f854 3c18 	ldr.w	r3, [r4, #-24]
    324c:	9302      	str	r3, [sp, #8]
    324e:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    3252:	9301      	str	r3, [sp, #4]
    3254:	f854 3c20 	ldr.w	r3, [r4, #-32]
    3258:	9300      	str	r3, [sp, #0]
    325a:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    325e:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    3262:	f7ff ff9d 	bl	31a0 <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    3266:	f854 3c30 	ldr.w	r3, [r4, #-48]
    326a:	65dd      	str	r5, [r3, #92]	; 0x5c
    326c:	4625      	mov	r5, r4
    326e:	e7cd      	b.n	320c <z_init_static_threads+0xc>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    3270:	6a63      	ldr	r3, [r4, #36]	; 0x24
    3272:	1c5a      	adds	r2, r3, #1
    3274:	d00d      	beq.n	3292 <z_init_static_threads+0x92>
    3276:	4630      	mov	r0, r6
    3278:	4639      	mov	r1, r7
					    K_MSEC(thread_data->init_delay));
    327a:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    327e:	fbc9 0103 	smlal	r0, r1, r9, r3
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3282:	42b9      	cmp	r1, r7
    3284:	bf08      	it	eq
    3286:	42b0      	cmpeq	r0, r6
			schedule_new_thread(thread_data->init_thread,
    3288:	6825      	ldr	r5, [r4, #0]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    328a:	d104      	bne.n	3296 <z_init_static_threads+0x96>
	z_sched_start(thread);
    328c:	4628      	mov	r0, r5
    328e:	f7ff fccd 	bl	2c2c <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    3292:	3430      	adds	r4, #48	; 0x30
    3294:	e7c8      	b.n	3228 <z_init_static_threads+0x28>
    3296:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    329a:	2300      	movs	r3, #0
    329c:	f7fc ffce 	bl	23c <__aeabi_uldivmod>
    32a0:	4602      	mov	r2, r0
    32a2:	460b      	mov	r3, r1
    32a4:	f105 0018 	add.w	r0, r5, #24
    32a8:	4651      	mov	r1, sl
    32aa:	f000 f853 	bl	3354 <z_add_timeout>
    32ae:	e7f0      	b.n	3292 <z_init_static_threads+0x92>
    32b0:	20000110 	.word	0x20000110
    32b4:	20000110 	.word	0x20000110
    32b8:	00004cf9 	.word	0x00004cf9

000032bc <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? z_clock_elapsed() : 0;
    32bc:	4b03      	ldr	r3, [pc, #12]	; (32cc <elapsed+0x10>)
    32be:	681b      	ldr	r3, [r3, #0]
    32c0:	b90b      	cbnz	r3, 32c6 <elapsed+0xa>
    32c2:	f7fd be8d 	b.w	fe0 <z_clock_elapsed>
}
    32c6:	2000      	movs	r0, #0
    32c8:	4770      	bx	lr
    32ca:	bf00      	nop
    32cc:	2000084c 	.word	0x2000084c

000032d0 <remove_timeout>:
{
    32d0:	b530      	push	{r4, r5, lr}
    32d2:	6803      	ldr	r3, [r0, #0]
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    32d4:	b168      	cbz	r0, 32f2 <remove_timeout+0x22>
    32d6:	4a0a      	ldr	r2, [pc, #40]	; (3300 <remove_timeout+0x30>)
	return (node == list->tail) ? NULL : node->next;
    32d8:	6852      	ldr	r2, [r2, #4]
    32da:	4290      	cmp	r0, r2
    32dc:	d009      	beq.n	32f2 <remove_timeout+0x22>
	if (next(t) != NULL) {
    32de:	b143      	cbz	r3, 32f2 <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    32e0:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    32e4:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    32e8:	1912      	adds	r2, r2, r4
    32ea:	eb45 0101 	adc.w	r1, r5, r1
    32ee:	e9c3 2104 	strd	r2, r1, [r3, #16]
	node->prev->next = node->next;
    32f2:	6842      	ldr	r2, [r0, #4]
    32f4:	6013      	str	r3, [r2, #0]
	node->next->prev = node->prev;
    32f6:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    32f8:	2300      	movs	r3, #0
	node->prev = NULL;
    32fa:	e9c0 3300 	strd	r3, r3, [r0]
}
    32fe:	bd30      	pop	{r4, r5, pc}
    3300:	20000054 	.word	0x20000054

00003304 <next_timeout>:
	return list->head == list;
    3304:	4b11      	ldr	r3, [pc, #68]	; (334c <next_timeout+0x48>)

static int32_t next_timeout(void)
{
    3306:	b510      	push	{r4, lr}
    3308:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    330a:	429c      	cmp	r4, r3
    330c:	bf08      	it	eq
    330e:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    3310:	f7ff ffd4 	bl	32bc <elapsed>
	int32_t ret = to == NULL ? MAX_WAIT
    3314:	b1bc      	cbz	r4, 3346 <next_timeout+0x42>
		: MIN(MAX_WAIT, MAX(0, to->dticks - ticks_elapsed));
    3316:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    331a:	1a12      	subs	r2, r2, r0
    331c:	eb63 73e0 	sbc.w	r3, r3, r0, asr #31
	int32_t ret = to == NULL ? MAX_WAIT
    3320:	f1b2 4f00 	cmp.w	r2, #2147483648	; 0x80000000
    3324:	f173 0100 	sbcs.w	r1, r3, #0
    3328:	da0d      	bge.n	3346 <next_timeout+0x42>
		: MIN(MAX_WAIT, MAX(0, to->dticks - ticks_elapsed));
    332a:	4619      	mov	r1, r3
    332c:	2a00      	cmp	r2, #0
    332e:	f171 0300 	sbcs.w	r3, r1, #0
    3332:	4610      	mov	r0, r2
    3334:	da00      	bge.n	3338 <next_timeout+0x34>
    3336:	2000      	movs	r0, #0

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    3338:	4b05      	ldr	r3, [pc, #20]	; (3350 <next_timeout+0x4c>)
    333a:	691b      	ldr	r3, [r3, #16]
    333c:	b113      	cbz	r3, 3344 <next_timeout+0x40>
    333e:	4298      	cmp	r0, r3
    3340:	bfa8      	it	ge
    3342:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    3344:	bd10      	pop	{r4, pc}
	int32_t ret = to == NULL ? MAX_WAIT
    3346:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    334a:	e7f5      	b.n	3338 <next_timeout+0x34>
    334c:	20000054 	.word	0x20000054
    3350:	20000810 	.word	0x20000810

00003354 <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
    3354:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3358:	9101      	str	r1, [sp, #4]
    335a:	4619      	mov	r1, r3
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    335c:	1c4b      	adds	r3, r1, #1
    335e:	bf08      	it	eq
    3360:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    3364:	4682      	mov	sl, r0
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3366:	d06b      	beq.n	3440 <z_add_timeout+0xec>
#ifdef CONFIG_LEGACY_TIMEOUT_API
	k_ticks_t ticks = timeout;
#else
	k_ticks_t ticks = timeout.ticks + 1;

	if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) && Z_TICK_ABS(ticks) >= 0) {
    3368:	f06f 0301 	mvn.w	r3, #1
    336c:	f04f 3bff 	mov.w	fp, #4294967295
	k_ticks_t ticks = timeout.ticks + 1;
    3370:	1c54      	adds	r4, r2, #1
    3372:	f141 0500 	adc.w	r5, r1, #0
	if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) && Z_TICK_ABS(ticks) >= 0) {
    3376:	ebb3 0804 	subs.w	r8, r3, r4
    337a:	eb6b 0905 	sbc.w	r9, fp, r5
    337e:	f1b8 0f00 	cmp.w	r8, #0
    3382:	f179 0300 	sbcs.w	r3, r9, #0
    3386:	db0f      	blt.n	33a8 <z_add_timeout+0x54>
		ticks = Z_TICK_ABS(ticks) - (curr_tick + elapsed());
    3388:	f7ff ff98 	bl	32bc <elapsed>
    338c:	f06f 0301 	mvn.w	r3, #1
    3390:	4a32      	ldr	r2, [pc, #200]	; (345c <z_add_timeout+0x108>)
    3392:	e9d2 1c00 	ldrd	r1, ip, [r2]
    3396:	1a5b      	subs	r3, r3, r1
    3398:	eb6b 020c 	sbc.w	r2, fp, ip
    339c:	1b1e      	subs	r6, r3, r4
    339e:	eb62 0705 	sbc.w	r7, r2, r5
    33a2:	1a34      	subs	r4, r6, r0
    33a4:	eb67 75e0 	sbc.w	r5, r7, r0, asr #31
	}
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    33a8:	9b01      	ldr	r3, [sp, #4]
    33aa:	f8ca 3008 	str.w	r3, [sl, #8]
	__asm__ volatile(
    33ae:	f04f 0320 	mov.w	r3, #32
    33b2:	f3ef 8611 	mrs	r6, BASEPRI
    33b6:	f383 8811 	msr	BASEPRI, r3
    33ba:	f3bf 8f6f 	isb	sy
	ticks = MAX(1, ticks);

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		to->dticks = ticks + elapsed();
    33be:	f7ff ff7d 	bl	32bc <elapsed>
	ticks = MAX(1, ticks);
    33c2:	2c01      	cmp	r4, #1
    33c4:	f175 0300 	sbcs.w	r3, r5, #0
    33c8:	bfbc      	itt	lt
    33ca:	2401      	movlt	r4, #1
    33cc:	2500      	movlt	r5, #0
	return list->head == list;
    33ce:	4b24      	ldr	r3, [pc, #144]	; (3460 <z_add_timeout+0x10c>)
		to->dticks = ticks + elapsed();
    33d0:	1824      	adds	r4, r4, r0
    33d2:	681a      	ldr	r2, [r3, #0]
    33d4:	eb45 75e0 	adc.w	r5, r5, r0, asr #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
    33d8:	429a      	cmp	r2, r3
    33da:	e9ca 4504 	strd	r4, r5, [sl, #16]
    33de:	d001      	beq.n	33e4 <z_add_timeout+0x90>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    33e0:	685f      	ldr	r7, [r3, #4]
		for (t = first(); t != NULL; t = next(t)) {
    33e2:	b952      	cbnz	r2, 33fa <z_add_timeout+0xa6>
	node->prev = list->tail;
    33e4:	685a      	ldr	r2, [r3, #4]
	node->next = list;
    33e6:	f8ca 3000 	str.w	r3, [sl]
	node->prev = list->tail;
    33ea:	f8ca 2004 	str.w	r2, [sl, #4]
	list->tail->next = node;
    33ee:	685a      	ldr	r2, [r3, #4]
    33f0:	f8c2 a000 	str.w	sl, [r2]
	list->tail = node;
    33f4:	f8c3 a004 	str.w	sl, [r3, #4]
}
    33f8:	e014      	b.n	3424 <z_add_timeout+0xd0>
			if (t->dticks > to->dticks) {
    33fa:	e9d2 8904 	ldrd	r8, r9, [r2, #16]
    33fe:	e9da 4504 	ldrd	r4, r5, [sl, #16]
    3402:	4544      	cmp	r4, r8
    3404:	eb75 0109 	sbcs.w	r1, r5, r9
    3408:	da1d      	bge.n	3446 <z_add_timeout+0xf2>
				t->dticks -= to->dticks;
    340a:	ebb8 0004 	subs.w	r0, r8, r4
    340e:	eb69 0105 	sbc.w	r1, r9, r5
    3412:	e9c2 0104 	strd	r0, r1, [r2, #16]
	node->prev = successor->prev;
    3416:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
    3418:	e9ca 2100 	strd	r2, r1, [sl]
	successor->prev->next = node;
    341c:	f8c1 a000 	str.w	sl, [r1]
	successor->prev = node;
    3420:	f8c2 a004 	str.w	sl, [r2, #4]
	return list->head == list;
    3424:	681a      	ldr	r2, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3426:	429a      	cmp	r2, r3
    3428:	d006      	beq.n	3438 <z_add_timeout+0xe4>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    342a:	4592      	cmp	sl, r2
    342c:	d104      	bne.n	3438 <z_add_timeout+0xe4>
			z_clock_set_timeout(next_timeout(), false);
    342e:	f7ff ff69 	bl	3304 <next_timeout>
    3432:	2100      	movs	r1, #0
    3434:	f7fd fd6e 	bl	f14 <z_clock_set_timeout>
	__asm__ volatile(
    3438:	f386 8811 	msr	BASEPRI, r6
    343c:	f3bf 8f6f 	isb	sy
		}
	}
}
    3440:	b003      	add	sp, #12
    3442:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			to->dticks -= t->dticks;
    3446:	ebb4 0008 	subs.w	r0, r4, r8
    344a:	eb65 0109 	sbc.w	r1, r5, r9
	return (node == list->tail) ? NULL : node->next;
    344e:	42ba      	cmp	r2, r7
    3450:	e9ca 0104 	strd	r0, r1, [sl, #16]
    3454:	d0c6      	beq.n	33e4 <z_add_timeout+0x90>
    3456:	6812      	ldr	r2, [r2, #0]
    3458:	e7c3      	b.n	33e2 <z_add_timeout+0x8e>
    345a:	bf00      	nop
    345c:	20000260 	.word	0x20000260
    3460:	20000054 	.word	0x20000054

00003464 <z_clock_announce>:
		}
	}
}

void z_clock_announce(int32_t ticks)
{
    3464:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3468:	4606      	mov	r6, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    346a:	f7ff fc37 	bl	2cdc <z_time_slice>
	__asm__ volatile(
    346e:	f04f 0320 	mov.w	r3, #32
    3472:	f3ef 8411 	mrs	r4, BASEPRI
    3476:	f383 8811 	msr	BASEPRI, r3
    347a:	f3bf 8f6f 	isb	sy
#endif

	k_spinlock_key_t key = k_spin_lock(&timeout_lock);

	announce_remaining = ticks;
    347e:	f8df a0b0 	ldr.w	sl, [pc, #176]	; 3530 <z_clock_announce+0xcc>
    3482:	4d2a      	ldr	r5, [pc, #168]	; (352c <z_clock_announce+0xc8>)
    3484:	4651      	mov	r1, sl
	return list->head == list;
    3486:	f8df b0ac 	ldr.w	fp, [pc, #172]	; 3534 <z_clock_announce+0xd0>
    348a:	602e      	str	r6, [r5, #0]
    348c:	f8d5 c000 	ldr.w	ip, [r5]
    3490:	f8db 0000 	ldr.w	r0, [fp]
    3494:	4662      	mov	r2, ip
    3496:	e9da 8900 	ldrd	r8, r9, [sl]
    349a:	17d3      	asrs	r3, r2, #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
    349c:	4558      	cmp	r0, fp
    349e:	e9cd 2300 	strd	r2, r3, [sp]
    34a2:	d00d      	beq.n	34c0 <z_clock_announce+0x5c>

	while (first() != NULL && first()->dticks <= announce_remaining) {
    34a4:	b160      	cbz	r0, 34c0 <z_clock_announce+0x5c>
    34a6:	e9d0 6704 	ldrd	r6, r7, [r0, #16]
    34aa:	45b4      	cmp	ip, r6
    34ac:	41bb      	sbcs	r3, r7
    34ae:	da1d      	bge.n	34ec <z_clock_announce+0x88>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    34b0:	9b00      	ldr	r3, [sp, #0]
    34b2:	ebb6 0c03 	subs.w	ip, r6, r3
    34b6:	9b01      	ldr	r3, [sp, #4]
    34b8:	eb67 0603 	sbc.w	r6, r7, r3
    34bc:	e9c0 c604 	strd	ip, r6, [r0, #16]
	}

	curr_tick += announce_remaining;
	announce_remaining = 0;
    34c0:	2600      	movs	r6, #0
	curr_tick += announce_remaining;
    34c2:	9b00      	ldr	r3, [sp, #0]
	announce_remaining = 0;
    34c4:	602e      	str	r6, [r5, #0]
	curr_tick += announce_remaining;
    34c6:	eb13 0208 	adds.w	r2, r3, r8
    34ca:	9b01      	ldr	r3, [sp, #4]
    34cc:	eb43 0309 	adc.w	r3, r3, r9
    34d0:	e9c1 2300 	strd	r2, r3, [r1]

	z_clock_set_timeout(next_timeout(), false);
    34d4:	f7ff ff16 	bl	3304 <next_timeout>
    34d8:	4631      	mov	r1, r6
    34da:	f7fd fd1b 	bl	f14 <z_clock_set_timeout>
	__asm__ volatile(
    34de:	f384 8811 	msr	BASEPRI, r4
    34e2:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    34e6:	b003      	add	sp, #12
    34e8:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		t->dticks = 0;
    34ec:	2200      	movs	r2, #0
    34ee:	2300      	movs	r3, #0
		curr_tick += dt;
    34f0:	eb18 0806 	adds.w	r8, r8, r6
    34f4:	eb49 79e6 	adc.w	r9, r9, r6, asr #31
		t->dticks = 0;
    34f8:	e9c0 2304 	strd	r2, r3, [r0, #16]
		announce_remaining -= dt;
    34fc:	ebac 0606 	sub.w	r6, ip, r6
		curr_tick += dt;
    3500:	e9ca 8900 	strd	r8, r9, [sl]
		announce_remaining -= dt;
    3504:	602e      	str	r6, [r5, #0]
		remove_timeout(t);
    3506:	f7ff fee3 	bl	32d0 <remove_timeout>
    350a:	f384 8811 	msr	BASEPRI, r4
    350e:	f3bf 8f6f 	isb	sy
		t->fn(t);
    3512:	6883      	ldr	r3, [r0, #8]
    3514:	4798      	blx	r3
	__asm__ volatile(
    3516:	f04f 0320 	mov.w	r3, #32
    351a:	f3ef 8411 	mrs	r4, BASEPRI
    351e:	f383 8811 	msr	BASEPRI, r3
    3522:	f3bf 8f6f 	isb	sy

	/* Note that we need to use the underlying arch-specific lock
	 * implementation.  The "irq_lock()" API in SMP context is
	 * actually a wrapper for a global spinlock!
	 */
	k.key = arch_irq_lock();
    3526:	4902      	ldr	r1, [pc, #8]	; (3530 <z_clock_announce+0xcc>)
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    3528:	e7b0      	b.n	348c <z_clock_announce+0x28>
    352a:	bf00      	nop
    352c:	2000084c 	.word	0x2000084c
    3530:	20000260 	.word	0x20000260
    3534:	20000054 	.word	0x20000054

00003538 <z_tick_get>:

int64_t z_tick_get(void)
{
    3538:	b510      	push	{r4, lr}
    353a:	f04f 0320 	mov.w	r3, #32
    353e:	f3ef 8411 	mrs	r4, BASEPRI
    3542:	f383 8811 	msr	BASEPRI, r3
    3546:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + z_clock_elapsed();
    354a:	f7fd fd49 	bl	fe0 <z_clock_elapsed>
    354e:	4b06      	ldr	r3, [pc, #24]	; (3568 <z_tick_get+0x30>)
    3550:	e9d3 2300 	ldrd	r2, r3, [r3]
    3554:	1812      	adds	r2, r2, r0
    3556:	f143 0300 	adc.w	r3, r3, #0
	__asm__ volatile(
    355a:	f384 8811 	msr	BASEPRI, r4
    355e:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    3562:	4610      	mov	r0, r2
    3564:	4619      	mov	r1, r3
    3566:	bd10      	pop	{r4, pc}
    3568:	20000260 	.word	0x20000260

0000356c <statics_init>:
	z_waitq_init(&h->wait_q);
	sys_heap_init(&h->heap, mem, bytes);
}

static int statics_init(const struct device *unused)
{
    356c:	b538      	push	{r3, r4, r5, lr}
	ARG_UNUSED(unused);
	Z_STRUCT_SECTION_FOREACH(k_heap, h) {
    356e:	4c06      	ldr	r4, [pc, #24]	; (3588 <statics_init+0x1c>)
    3570:	4d06      	ldr	r5, [pc, #24]	; (358c <statics_init+0x20>)
    3572:	42ac      	cmp	r4, r5
    3574:	d301      	bcc.n	357a <statics_init+0xe>
		k_heap_init(h, h->heap.init_mem, h->heap.init_bytes);
	}
	return 0;
}
    3576:	2000      	movs	r0, #0
    3578:	bd38      	pop	{r3, r4, r5, pc}
		k_heap_init(h, h->heap.init_mem, h->heap.init_bytes);
    357a:	4620      	mov	r0, r4
    357c:	e9d4 1201 	ldrd	r1, r2, [r4, #4]
    3580:	f001 fc77 	bl	4e72 <k_heap_init>
	Z_STRUCT_SECTION_FOREACH(k_heap, h) {
    3584:	3414      	adds	r4, #20
    3586:	e7f4      	b.n	3572 <statics_init+0x6>
    3588:	20000110 	.word	0x20000110
    358c:	20000110 	.word	0x20000110

00003590 <CC_PalMemCopyPlat>:
    3590:	f001 ba50 	b.w	4a34 <memmove>

00003594 <CC_PalMemSetZeroPlat>:
    3594:	460a      	mov	r2, r1
    3596:	2100      	movs	r1, #0
    3598:	f001 ba8e 	b.w	4ab8 <memset>

0000359c <CC_PalInit>:
    359c:	b510      	push	{r4, lr}
    359e:	4811      	ldr	r0, [pc, #68]	; (35e4 <CC_PalInit+0x48>)
    35a0:	f000 f848 	bl	3634 <CC_PalMutexCreate>
    35a4:	b100      	cbz	r0, 35a8 <CC_PalInit+0xc>
    35a6:	bd10      	pop	{r4, pc}
    35a8:	480f      	ldr	r0, [pc, #60]	; (35e8 <CC_PalInit+0x4c>)
    35aa:	f000 f843 	bl	3634 <CC_PalMutexCreate>
    35ae:	2800      	cmp	r0, #0
    35b0:	d1f9      	bne.n	35a6 <CC_PalInit+0xa>
    35b2:	4c0e      	ldr	r4, [pc, #56]	; (35ec <CC_PalInit+0x50>)
    35b4:	4620      	mov	r0, r4
    35b6:	f000 f83d 	bl	3634 <CC_PalMutexCreate>
    35ba:	2800      	cmp	r0, #0
    35bc:	d1f3      	bne.n	35a6 <CC_PalInit+0xa>
    35be:	4b0c      	ldr	r3, [pc, #48]	; (35f0 <CC_PalInit+0x54>)
    35c0:	480c      	ldr	r0, [pc, #48]	; (35f4 <CC_PalInit+0x58>)
    35c2:	601c      	str	r4, [r3, #0]
    35c4:	f000 f836 	bl	3634 <CC_PalMutexCreate>
    35c8:	4601      	mov	r1, r0
    35ca:	2800      	cmp	r0, #0
    35cc:	d1eb      	bne.n	35a6 <CC_PalInit+0xa>
    35ce:	f000 f82d 	bl	362c <CC_PalDmaInit>
    35d2:	4604      	mov	r4, r0
    35d4:	b108      	cbz	r0, 35da <CC_PalInit+0x3e>
    35d6:	4620      	mov	r0, r4
    35d8:	bd10      	pop	{r4, pc}
    35da:	f000 f851 	bl	3680 <CC_PalPowerSaveModeInit>
    35de:	4620      	mov	r0, r4
    35e0:	e7fa      	b.n	35d8 <CC_PalInit+0x3c>
    35e2:	bf00      	nop
    35e4:	20000068 	.word	0x20000068
    35e8:	2000005c 	.word	0x2000005c
    35ec:	20000064 	.word	0x20000064
    35f0:	2000006c 	.word	0x2000006c
    35f4:	20000060 	.word	0x20000060

000035f8 <CC_PalTerminate>:
    35f8:	b508      	push	{r3, lr}
    35fa:	4808      	ldr	r0, [pc, #32]	; (361c <CC_PalTerminate+0x24>)
    35fc:	f000 f824 	bl	3648 <CC_PalMutexDestroy>
    3600:	4807      	ldr	r0, [pc, #28]	; (3620 <CC_PalTerminate+0x28>)
    3602:	f000 f821 	bl	3648 <CC_PalMutexDestroy>
    3606:	4807      	ldr	r0, [pc, #28]	; (3624 <CC_PalTerminate+0x2c>)
    3608:	f000 f81e 	bl	3648 <CC_PalMutexDestroy>
    360c:	4806      	ldr	r0, [pc, #24]	; (3628 <CC_PalTerminate+0x30>)
    360e:	f000 f81b 	bl	3648 <CC_PalMutexDestroy>
    3612:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    3616:	f000 b80b 	b.w	3630 <CC_PalDmaTerminate>
    361a:	bf00      	nop
    361c:	20000068 	.word	0x20000068
    3620:	2000005c 	.word	0x2000005c
    3624:	20000064 	.word	0x20000064
    3628:	20000060 	.word	0x20000060

0000362c <CC_PalDmaInit>:
    362c:	2000      	movs	r0, #0
    362e:	4770      	bx	lr

00003630 <CC_PalDmaTerminate>:
    3630:	4770      	bx	lr
    3632:	bf00      	nop

00003634 <CC_PalMutexCreate>:
    3634:	b508      	push	{r3, lr}
    3636:	4b03      	ldr	r3, [pc, #12]	; (3644 <CC_PalMutexCreate+0x10>)
    3638:	6802      	ldr	r2, [r0, #0]
    363a:	681b      	ldr	r3, [r3, #0]
    363c:	6810      	ldr	r0, [r2, #0]
    363e:	4798      	blx	r3
    3640:	2000      	movs	r0, #0
    3642:	bd08      	pop	{r3, pc}
    3644:	20000080 	.word	0x20000080

00003648 <CC_PalMutexDestroy>:
    3648:	b508      	push	{r3, lr}
    364a:	4b03      	ldr	r3, [pc, #12]	; (3658 <CC_PalMutexDestroy+0x10>)
    364c:	6802      	ldr	r2, [r0, #0]
    364e:	685b      	ldr	r3, [r3, #4]
    3650:	6810      	ldr	r0, [r2, #0]
    3652:	4798      	blx	r3
    3654:	2000      	movs	r0, #0
    3656:	bd08      	pop	{r3, pc}
    3658:	20000080 	.word	0x20000080

0000365c <CC_PalMutexLock>:
    365c:	4b02      	ldr	r3, [pc, #8]	; (3668 <CC_PalMutexLock+0xc>)
    365e:	6802      	ldr	r2, [r0, #0]
    3660:	689b      	ldr	r3, [r3, #8]
    3662:	6810      	ldr	r0, [r2, #0]
    3664:	4718      	bx	r3
    3666:	bf00      	nop
    3668:	20000080 	.word	0x20000080

0000366c <CC_PalMutexUnlock>:
    366c:	b508      	push	{r3, lr}
    366e:	4b03      	ldr	r3, [pc, #12]	; (367c <CC_PalMutexUnlock+0x10>)
    3670:	6802      	ldr	r2, [r0, #0]
    3672:	68db      	ldr	r3, [r3, #12]
    3674:	6810      	ldr	r0, [r2, #0]
    3676:	4798      	blx	r3
    3678:	2000      	movs	r0, #0
    367a:	bd08      	pop	{r3, pc}
    367c:	20000080 	.word	0x20000080

00003680 <CC_PalPowerSaveModeInit>:
    3680:	b570      	push	{r4, r5, r6, lr}
    3682:	4c09      	ldr	r4, [pc, #36]	; (36a8 <CC_PalPowerSaveModeInit+0x28>)
    3684:	4d09      	ldr	r5, [pc, #36]	; (36ac <CC_PalPowerSaveModeInit+0x2c>)
    3686:	6920      	ldr	r0, [r4, #16]
    3688:	68ab      	ldr	r3, [r5, #8]
    368a:	4798      	blx	r3
    368c:	b118      	cbz	r0, 3696 <CC_PalPowerSaveModeInit+0x16>
    368e:	4b08      	ldr	r3, [pc, #32]	; (36b0 <CC_PalPowerSaveModeInit+0x30>)
    3690:	4808      	ldr	r0, [pc, #32]	; (36b4 <CC_PalPowerSaveModeInit+0x34>)
    3692:	685b      	ldr	r3, [r3, #4]
    3694:	4798      	blx	r3
    3696:	2100      	movs	r1, #0
    3698:	4a07      	ldr	r2, [pc, #28]	; (36b8 <CC_PalPowerSaveModeInit+0x38>)
    369a:	68eb      	ldr	r3, [r5, #12]
    369c:	6011      	str	r1, [r2, #0]
    369e:	6920      	ldr	r0, [r4, #16]
    36a0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    36a4:	4718      	bx	r3
    36a6:	bf00      	nop
    36a8:	20000090 	.word	0x20000090
    36ac:	20000080 	.word	0x20000080
    36b0:	20000070 	.word	0x20000070
    36b4:	000052ec 	.word	0x000052ec
    36b8:	20000850 	.word	0x20000850

000036bc <CC_PalPowerSaveModeSelect>:
    36bc:	b570      	push	{r4, r5, r6, lr}
    36be:	4d1a      	ldr	r5, [pc, #104]	; (3728 <CC_PalPowerSaveModeSelect+0x6c>)
    36c0:	4e1a      	ldr	r6, [pc, #104]	; (372c <CC_PalPowerSaveModeSelect+0x70>)
    36c2:	4604      	mov	r4, r0
    36c4:	68b2      	ldr	r2, [r6, #8]
    36c6:	6928      	ldr	r0, [r5, #16]
    36c8:	4790      	blx	r2
    36ca:	b9f0      	cbnz	r0, 370a <CC_PalPowerSaveModeSelect+0x4e>
    36cc:	b15c      	cbz	r4, 36e6 <CC_PalPowerSaveModeSelect+0x2a>
    36ce:	4c18      	ldr	r4, [pc, #96]	; (3730 <CC_PalPowerSaveModeSelect+0x74>)
    36d0:	6823      	ldr	r3, [r4, #0]
    36d2:	b1ab      	cbz	r3, 3700 <CC_PalPowerSaveModeSelect+0x44>
    36d4:	2b01      	cmp	r3, #1
    36d6:	d01a      	beq.n	370e <CC_PalPowerSaveModeSelect+0x52>
    36d8:	3b01      	subs	r3, #1
    36da:	6023      	str	r3, [r4, #0]
    36dc:	6928      	ldr	r0, [r5, #16]
    36de:	68f3      	ldr	r3, [r6, #12]
    36e0:	4798      	blx	r3
    36e2:	2000      	movs	r0, #0
    36e4:	bd70      	pop	{r4, r5, r6, pc}
    36e6:	4c12      	ldr	r4, [pc, #72]	; (3730 <CC_PalPowerSaveModeSelect+0x74>)
    36e8:	6821      	ldr	r1, [r4, #0]
    36ea:	b939      	cbnz	r1, 36fc <CC_PalPowerSaveModeSelect+0x40>
    36ec:	2001      	movs	r0, #1
    36ee:	4b11      	ldr	r3, [pc, #68]	; (3734 <CC_PalPowerSaveModeSelect+0x78>)
    36f0:	4a11      	ldr	r2, [pc, #68]	; (3738 <CC_PalPowerSaveModeSelect+0x7c>)
    36f2:	f8c3 0500 	str.w	r0, [r3, #1280]	; 0x500
    36f6:	6813      	ldr	r3, [r2, #0]
    36f8:	2b00      	cmp	r3, #0
    36fa:	d1fc      	bne.n	36f6 <CC_PalPowerSaveModeSelect+0x3a>
    36fc:	3101      	adds	r1, #1
    36fe:	6021      	str	r1, [r4, #0]
    3700:	68f3      	ldr	r3, [r6, #12]
    3702:	6928      	ldr	r0, [r5, #16]
    3704:	4798      	blx	r3
    3706:	2000      	movs	r0, #0
    3708:	bd70      	pop	{r4, r5, r6, pc}
    370a:	480c      	ldr	r0, [pc, #48]	; (373c <CC_PalPowerSaveModeSelect+0x80>)
    370c:	bd70      	pop	{r4, r5, r6, pc}
    370e:	4a0a      	ldr	r2, [pc, #40]	; (3738 <CC_PalPowerSaveModeSelect+0x7c>)
    3710:	6813      	ldr	r3, [r2, #0]
    3712:	2b00      	cmp	r3, #0
    3714:	d1fc      	bne.n	3710 <CC_PalPowerSaveModeSelect+0x54>
    3716:	4a07      	ldr	r2, [pc, #28]	; (3734 <CC_PalPowerSaveModeSelect+0x78>)
    3718:	f06f 407e 	mvn.w	r0, #4261412864	; 0xfe000000
    371c:	f8c2 3500 	str.w	r3, [r2, #1280]	; 0x500
    3720:	f000 f820 	bl	3764 <CC_HalMaskInterrupt>
    3724:	6823      	ldr	r3, [r4, #0]
    3726:	e7d7      	b.n	36d8 <CC_PalPowerSaveModeSelect+0x1c>
    3728:	20000090 	.word	0x20000090
    372c:	20000080 	.word	0x20000080
    3730:	20000850 	.word	0x20000850
    3734:	50840000 	.word	0x50840000
    3738:	50841910 	.word	0x50841910
    373c:	ffff8fe9 	.word	0xffff8fe9

00003740 <CC_HalInit>:
    3740:	2000      	movs	r0, #0
    3742:	4770      	bx	lr

00003744 <CC_HalTerminate>:
    3744:	2000      	movs	r0, #0
    3746:	4770      	bx	lr

00003748 <CC_HalClearInterruptBit>:
    3748:	0543      	lsls	r3, r0, #21
    374a:	d503      	bpl.n	3754 <CC_HalClearInterruptBit+0xc>
    374c:	f04f 32ff 	mov.w	r2, #4294967295
    3750:	4b02      	ldr	r3, [pc, #8]	; (375c <CC_HalClearInterruptBit+0x14>)
    3752:	601a      	str	r2, [r3, #0]
    3754:	4b02      	ldr	r3, [pc, #8]	; (3760 <CC_HalClearInterruptBit+0x18>)
    3756:	6018      	str	r0, [r3, #0]
    3758:	4770      	bx	lr
    375a:	bf00      	nop
    375c:	50841108 	.word	0x50841108
    3760:	50841a08 	.word	0x50841a08

00003764 <CC_HalMaskInterrupt>:
    3764:	4b01      	ldr	r3, [pc, #4]	; (376c <CC_HalMaskInterrupt+0x8>)
    3766:	6018      	str	r0, [r3, #0]
    3768:	4770      	bx	lr
    376a:	bf00      	nop
    376c:	50841a04 	.word	0x50841a04

00003770 <CC_HalWaitInterruptRND>:
    3770:	b108      	cbz	r0, 3776 <CC_HalWaitInterruptRND+0x6>
    3772:	f000 b803 	b.w	377c <CC_PalWaitInterruptRND>
    3776:	f44f 0075 	mov.w	r0, #16056320	; 0xf50000
    377a:	4770      	bx	lr

0000377c <CC_PalWaitInterruptRND>:
    377c:	4602      	mov	r2, r0
    377e:	4807      	ldr	r0, [pc, #28]	; (379c <CC_PalWaitInterruptRND+0x20>)
    3780:	6803      	ldr	r3, [r0, #0]
    3782:	4213      	tst	r3, r2
    3784:	d0fc      	beq.n	3780 <CC_PalWaitInterruptRND+0x4>
    3786:	b121      	cbz	r1, 3792 <CC_PalWaitInterruptRND+0x16>
    3788:	4b05      	ldr	r3, [pc, #20]	; (37a0 <CC_PalWaitInterruptRND+0x24>)
    378a:	4806      	ldr	r0, [pc, #24]	; (37a4 <CC_PalWaitInterruptRND+0x28>)
    378c:	681b      	ldr	r3, [r3, #0]
    378e:	600b      	str	r3, [r1, #0]
    3790:	6003      	str	r3, [r0, #0]
    3792:	4b05      	ldr	r3, [pc, #20]	; (37a8 <CC_PalWaitInterruptRND+0x2c>)
    3794:	2000      	movs	r0, #0
    3796:	601a      	str	r2, [r3, #0]
    3798:	4770      	bx	lr
    379a:	bf00      	nop
    379c:	50841a00 	.word	0x50841a00
    37a0:	50841104 	.word	0x50841104
    37a4:	50841108 	.word	0x50841108
    37a8:	50841a08 	.word	0x50841a08

000037ac <mbedtls_platform_setup>:
    37ac:	f000 b89e 	b.w	38ec <nrf_cc3xx_platform_init>

000037b0 <mbedtls_platform_zeroize>:
    37b0:	b138      	cbz	r0, 37c2 <mbedtls_platform_zeroize+0x12>
    37b2:	b131      	cbz	r1, 37c2 <mbedtls_platform_zeroize+0x12>
    37b4:	2200      	movs	r2, #0
    37b6:	4401      	add	r1, r0
    37b8:	4603      	mov	r3, r0
    37ba:	3001      	adds	r0, #1
    37bc:	4281      	cmp	r1, r0
    37be:	701a      	strb	r2, [r3, #0]
    37c0:	d1fa      	bne.n	37b8 <mbedtls_platform_zeroize+0x8>
    37c2:	4770      	bx	lr

000037c4 <mbedtls_hardware_poll>:
    37c4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    37c8:	f5ad 7d1a 	sub.w	sp, sp, #616	; 0x268
    37cc:	460e      	mov	r6, r1
    37ce:	9205      	str	r2, [sp, #20]
    37d0:	2100      	movs	r1, #0
    37d2:	4614      	mov	r4, r2
    37d4:	a812      	add	r0, sp, #72	; 0x48
    37d6:	f44f 7208 	mov.w	r2, #544	; 0x220
    37da:	461d      	mov	r5, r3
    37dc:	f001 f96c 	bl	4ab8 <memset>
    37e0:	2100      	movs	r1, #0
    37e2:	2228      	movs	r2, #40	; 0x28
    37e4:	a808      	add	r0, sp, #32
    37e6:	9106      	str	r1, [sp, #24]
    37e8:	f001 f966 	bl	4ab8 <memset>
    37ec:	2e00      	cmp	r6, #0
    37ee:	d03c      	beq.n	386a <mbedtls_hardware_poll+0xa6>
    37f0:	2d00      	cmp	r5, #0
    37f2:	d03a      	beq.n	386a <mbedtls_hardware_poll+0xa6>
    37f4:	2c00      	cmp	r4, #0
    37f6:	d038      	beq.n	386a <mbedtls_hardware_poll+0xa6>
    37f8:	2104      	movs	r1, #4
    37fa:	a806      	add	r0, sp, #24
    37fc:	f7ff feca 	bl	3594 <CC_PalMemSetZeroPlat>
    3800:	a808      	add	r0, sp, #32
    3802:	2128      	movs	r1, #40	; 0x28
    3804:	f7ff fec6 	bl	3594 <CC_PalMemSetZeroPlat>
    3808:	a808      	add	r0, sp, #32
    380a:	f000 f831 	bl	3870 <RNG_PLAT_SetUserRngParameters>
    380e:	b178      	cbz	r0, 3830 <mbedtls_hardware_poll+0x6c>
    3810:	f04f 37ff 	mov.w	r7, #4294967295
    3814:	f44f 7108 	mov.w	r1, #544	; 0x220
    3818:	a812      	add	r0, sp, #72	; 0x48
    381a:	f7ff ffc9 	bl	37b0 <mbedtls_platform_zeroize>
    381e:	2104      	movs	r1, #4
    3820:	a806      	add	r0, sp, #24
    3822:	f7ff ffc5 	bl	37b0 <mbedtls_platform_zeroize>
    3826:	4638      	mov	r0, r7
    3828:	f50d 7d1a 	add.w	sp, sp, #616	; 0x268
    382c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    3830:	ab12      	add	r3, sp, #72	; 0x48
    3832:	f10d 081c 	add.w	r8, sp, #28
    3836:	4602      	mov	r2, r0
    3838:	e9cd 5301 	strd	r5, r3, [sp, #4]
    383c:	9003      	str	r0, [sp, #12]
    383e:	ab05      	add	r3, sp, #20
    3840:	a908      	add	r1, sp, #32
    3842:	f8cd 8000 	str.w	r8, [sp]
    3846:	a806      	add	r0, sp, #24
    3848:	f000 fd14 	bl	4274 <LLF_RND_GetTrngSource>
    384c:	2800      	cmp	r0, #0
    384e:	d1df      	bne.n	3810 <mbedtls_hardware_poll+0x4c>
    3850:	682b      	ldr	r3, [r5, #0]
    3852:	42a3      	cmp	r3, r4
    3854:	d3dc      	bcc.n	3810 <mbedtls_hardware_poll+0x4c>
    3856:	f8d8 1000 	ldr.w	r1, [r8]
    385a:	4607      	mov	r7, r0
    385c:	4622      	mov	r2, r4
    385e:	4630      	mov	r0, r6
    3860:	3108      	adds	r1, #8
    3862:	f7ff fe95 	bl	3590 <CC_PalMemCopyPlat>
    3866:	602c      	str	r4, [r5, #0]
    3868:	e7d4      	b.n	3814 <mbedtls_hardware_poll+0x50>
    386a:	f04f 37ff 	mov.w	r7, #4294967295
    386e:	e7da      	b.n	3826 <mbedtls_hardware_poll+0x62>

00003870 <RNG_PLAT_SetUserRngParameters>:
    3870:	231c      	movs	r3, #28
    3872:	b530      	push	{r4, r5, lr}
    3874:	b083      	sub	sp, #12
    3876:	a901      	add	r1, sp, #4
    3878:	4604      	mov	r4, r0
    387a:	9301      	str	r3, [sp, #4]
    387c:	f000 f9ce 	bl	3c1c <CC_PalTrngParamGet>
    3880:	4605      	mov	r5, r0
    3882:	b938      	cbnz	r0, 3894 <RNG_PLAT_SetUserRngParameters+0x24>
    3884:	9b01      	ldr	r3, [sp, #4]
    3886:	2b1c      	cmp	r3, #28
    3888:	d007      	beq.n	389a <RNG_PLAT_SetUserRngParameters+0x2a>
    388a:	4d16      	ldr	r5, [pc, #88]	; (38e4 <RNG_PLAT_SetUserRngParameters+0x74>)
    388c:	4620      	mov	r0, r4
    388e:	211c      	movs	r1, #28
    3890:	f7ff fe80 	bl	3594 <CC_PalMemSetZeroPlat>
    3894:	4628      	mov	r0, r5
    3896:	b003      	add	sp, #12
    3898:	bd30      	pop	{r4, r5, pc}
    389a:	2101      	movs	r1, #1
    389c:	e9d4 3200 	ldrd	r3, r2, [r4]
    38a0:	3b00      	subs	r3, #0
    38a2:	bf18      	it	ne
    38a4:	2301      	movne	r3, #1
    38a6:	61e1      	str	r1, [r4, #28]
    38a8:	b10a      	cbz	r2, 38ae <RNG_PLAT_SetUserRngParameters+0x3e>
    38aa:	f043 0302 	orr.w	r3, r3, #2
    38ae:	68a2      	ldr	r2, [r4, #8]
    38b0:	b932      	cbnz	r2, 38c0 <RNG_PLAT_SetUserRngParameters+0x50>
    38b2:	68e2      	ldr	r2, [r4, #12]
    38b4:	b942      	cbnz	r2, 38c8 <RNG_PLAT_SetUserRngParameters+0x58>
    38b6:	e9c4 3208 	strd	r3, r2, [r4, #32]
    38ba:	b98b      	cbnz	r3, 38e0 <RNG_PLAT_SetUserRngParameters+0x70>
    38bc:	4d0a      	ldr	r5, [pc, #40]	; (38e8 <RNG_PLAT_SetUserRngParameters+0x78>)
    38be:	e7e5      	b.n	388c <RNG_PLAT_SetUserRngParameters+0x1c>
    38c0:	68e2      	ldr	r2, [r4, #12]
    38c2:	f043 0304 	orr.w	r3, r3, #4
    38c6:	b13a      	cbz	r2, 38d8 <RNG_PLAT_SetUserRngParameters+0x68>
    38c8:	2200      	movs	r2, #0
    38ca:	4628      	mov	r0, r5
    38cc:	f043 0308 	orr.w	r3, r3, #8
    38d0:	e9c4 3208 	strd	r3, r2, [r4, #32]
    38d4:	b003      	add	sp, #12
    38d6:	bd30      	pop	{r4, r5, pc}
    38d8:	4615      	mov	r5, r2
    38da:	e9c4 3208 	strd	r3, r2, [r4, #32]
    38de:	e7d9      	b.n	3894 <RNG_PLAT_SetUserRngParameters+0x24>
    38e0:	4615      	mov	r5, r2
    38e2:	e7d7      	b.n	3894 <RNG_PLAT_SetUserRngParameters+0x24>
    38e4:	00f00c37 	.word	0x00f00c37
    38e8:	00f00c0e 	.word	0x00f00c0e

000038ec <nrf_cc3xx_platform_init>:
    38ec:	b510      	push	{r4, lr}
    38ee:	4c0c      	ldr	r4, [pc, #48]	; (3920 <nrf_cc3xx_platform_init+0x34>)
    38f0:	6823      	ldr	r3, [r4, #0]
    38f2:	b113      	cbz	r3, 38fa <nrf_cc3xx_platform_init+0xe>
    38f4:	4b0b      	ldr	r3, [pc, #44]	; (3924 <nrf_cc3xx_platform_init+0x38>)
    38f6:	681b      	ldr	r3, [r3, #0]
    38f8:	b92b      	cbnz	r3, 3906 <nrf_cc3xx_platform_init+0x1a>
    38fa:	f000 f94f 	bl	3b9c <CC_LibInit>
    38fe:	b930      	cbnz	r0, 390e <nrf_cc3xx_platform_init+0x22>
    3900:	2201      	movs	r2, #1
    3902:	4b08      	ldr	r3, [pc, #32]	; (3924 <nrf_cc3xx_platform_init+0x38>)
    3904:	601a      	str	r2, [r3, #0]
    3906:	2301      	movs	r3, #1
    3908:	2000      	movs	r0, #0
    390a:	6023      	str	r3, [r4, #0]
    390c:	bd10      	pop	{r4, pc}
    390e:	3801      	subs	r0, #1
    3910:	2806      	cmp	r0, #6
    3912:	d901      	bls.n	3918 <nrf_cc3xx_platform_init+0x2c>
    3914:	4804      	ldr	r0, [pc, #16]	; (3928 <nrf_cc3xx_platform_init+0x3c>)
    3916:	bd10      	pop	{r4, pc}
    3918:	4b04      	ldr	r3, [pc, #16]	; (392c <nrf_cc3xx_platform_init+0x40>)
    391a:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    391e:	bd10      	pop	{r4, pc}
    3920:	20000854 	.word	0x20000854
    3924:	20000858 	.word	0x20000858
    3928:	ffff8ffe 	.word	0xffff8ffe
    392c:	0000530c 	.word	0x0000530c

00003930 <nrf_cc3xx_platform_init_no_rng>:
    3930:	b510      	push	{r4, lr}
    3932:	4c0a      	ldr	r4, [pc, #40]	; (395c <nrf_cc3xx_platform_init_no_rng+0x2c>)
    3934:	6823      	ldr	r3, [r4, #0]
    3936:	b11b      	cbz	r3, 3940 <nrf_cc3xx_platform_init_no_rng+0x10>
    3938:	2301      	movs	r3, #1
    393a:	2000      	movs	r0, #0
    393c:	6023      	str	r3, [r4, #0]
    393e:	bd10      	pop	{r4, pc}
    3940:	f000 f898 	bl	3a74 <CC_LibInitNoRng>
    3944:	2800      	cmp	r0, #0
    3946:	d0f7      	beq.n	3938 <nrf_cc3xx_platform_init_no_rng+0x8>
    3948:	3801      	subs	r0, #1
    394a:	2806      	cmp	r0, #6
    394c:	d803      	bhi.n	3956 <nrf_cc3xx_platform_init_no_rng+0x26>
    394e:	4b04      	ldr	r3, [pc, #16]	; (3960 <nrf_cc3xx_platform_init_no_rng+0x30>)
    3950:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    3954:	bd10      	pop	{r4, pc}
    3956:	4803      	ldr	r0, [pc, #12]	; (3964 <nrf_cc3xx_platform_init_no_rng+0x34>)
    3958:	bd10      	pop	{r4, pc}
    395a:	bf00      	nop
    395c:	20000854 	.word	0x20000854
    3960:	0000530c 	.word	0x0000530c
    3964:	ffff8ffe 	.word	0xffff8ffe

00003968 <nrf_cc3xx_platform_abort>:
    3968:	f3bf 8f4f 	dsb	sy
    396c:	4905      	ldr	r1, [pc, #20]	; (3984 <nrf_cc3xx_platform_abort+0x1c>)
    396e:	4b06      	ldr	r3, [pc, #24]	; (3988 <nrf_cc3xx_platform_abort+0x20>)
    3970:	68ca      	ldr	r2, [r1, #12]
    3972:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    3976:	4313      	orrs	r3, r2
    3978:	60cb      	str	r3, [r1, #12]
    397a:	f3bf 8f4f 	dsb	sy
    397e:	bf00      	nop
    3980:	e7fd      	b.n	397e <nrf_cc3xx_platform_abort+0x16>
    3982:	bf00      	nop
    3984:	e000ed00 	.word	0xe000ed00
    3988:	05fa0004 	.word	0x05fa0004

0000398c <CC_PalAbort>:
    398c:	4b01      	ldr	r3, [pc, #4]	; (3994 <CC_PalAbort+0x8>)
    398e:	685b      	ldr	r3, [r3, #4]
    3990:	4718      	bx	r3
    3992:	bf00      	nop
    3994:	20000070 	.word	0x20000070

00003998 <nrf_cc3xx_platform_set_abort>:
    3998:	4b02      	ldr	r3, [pc, #8]	; (39a4 <nrf_cc3xx_platform_set_abort+0xc>)
    399a:	e9d0 1200 	ldrd	r1, r2, [r0]
    399e:	e9c3 1200 	strd	r1, r2, [r3]
    39a2:	4770      	bx	lr
    39a4:	20000070 	.word	0x20000070

000039a8 <mutex_unlock>:
    39a8:	b148      	cbz	r0, 39be <mutex_unlock+0x16>
    39aa:	6843      	ldr	r3, [r0, #4]
    39ac:	b12b      	cbz	r3, 39ba <mutex_unlock+0x12>
    39ae:	f3bf 8f5f 	dmb	sy
    39b2:	2300      	movs	r3, #0
    39b4:	6003      	str	r3, [r0, #0]
    39b6:	4618      	mov	r0, r3
    39b8:	4770      	bx	lr
    39ba:	4802      	ldr	r0, [pc, #8]	; (39c4 <mutex_unlock+0x1c>)
    39bc:	4770      	bx	lr
    39be:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    39c2:	4770      	bx	lr
    39c4:	ffff8fea 	.word	0xffff8fea

000039c8 <mutex_free>:
    39c8:	b510      	push	{r4, lr}
    39ca:	4604      	mov	r4, r0
    39cc:	b128      	cbz	r0, 39da <mutex_free+0x12>
    39ce:	6863      	ldr	r3, [r4, #4]
    39d0:	b113      	cbz	r3, 39d8 <mutex_free+0x10>
    39d2:	2300      	movs	r3, #0
    39d4:	6023      	str	r3, [r4, #0]
    39d6:	6063      	str	r3, [r4, #4]
    39d8:	bd10      	pop	{r4, pc}
    39da:	4b02      	ldr	r3, [pc, #8]	; (39e4 <mutex_free+0x1c>)
    39dc:	4802      	ldr	r0, [pc, #8]	; (39e8 <mutex_free+0x20>)
    39de:	685b      	ldr	r3, [r3, #4]
    39e0:	4798      	blx	r3
    39e2:	e7f4      	b.n	39ce <mutex_free+0x6>
    39e4:	20000070 	.word	0x20000070
    39e8:	00005328 	.word	0x00005328

000039ec <mutex_init>:
    39ec:	b510      	push	{r4, lr}
    39ee:	4604      	mov	r4, r0
    39f0:	b130      	cbz	r0, 3a00 <mutex_init+0x14>
    39f2:	2200      	movs	r2, #0
    39f4:	6863      	ldr	r3, [r4, #4]
    39f6:	6022      	str	r2, [r4, #0]
    39f8:	f043 0301 	orr.w	r3, r3, #1
    39fc:	6063      	str	r3, [r4, #4]
    39fe:	bd10      	pop	{r4, pc}
    3a00:	4801      	ldr	r0, [pc, #4]	; (3a08 <mutex_init+0x1c>)
    3a02:	f7ff ffc3 	bl	398c <CC_PalAbort>
    3a06:	e7f4      	b.n	39f2 <mutex_init+0x6>
    3a08:	00005350 	.word	0x00005350

00003a0c <mutex_lock>:
    3a0c:	b180      	cbz	r0, 3a30 <mutex_lock+0x24>
    3a0e:	6843      	ldr	r3, [r0, #4]
    3a10:	b163      	cbz	r3, 3a2c <mutex_lock+0x20>
    3a12:	2201      	movs	r2, #1
    3a14:	e8d0 3fef 	ldaex	r3, [r0]
    3a18:	e8c0 2fe1 	stlex	r1, r2, [r0]
    3a1c:	2900      	cmp	r1, #0
    3a1e:	d1f9      	bne.n	3a14 <mutex_lock+0x8>
    3a20:	2b01      	cmp	r3, #1
    3a22:	d0f7      	beq.n	3a14 <mutex_lock+0x8>
    3a24:	f3bf 8f5f 	dmb	sy
    3a28:	2000      	movs	r0, #0
    3a2a:	4770      	bx	lr
    3a2c:	4802      	ldr	r0, [pc, #8]	; (3a38 <mutex_lock+0x2c>)
    3a2e:	4770      	bx	lr
    3a30:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    3a34:	4770      	bx	lr
    3a36:	bf00      	nop
    3a38:	ffff8fea 	.word	0xffff8fea

00003a3c <nrf_cc3xx_platform_set_mutexes>:
    3a3c:	b470      	push	{r4, r5, r6}
    3a3e:	4b0b      	ldr	r3, [pc, #44]	; (3a6c <nrf_cc3xx_platform_set_mutexes+0x30>)
    3a40:	6806      	ldr	r6, [r0, #0]
    3a42:	68c2      	ldr	r2, [r0, #12]
    3a44:	e9d0 5401 	ldrd	r5, r4, [r0, #4]
    3a48:	e9c3 4202 	strd	r4, r2, [r3, #8]
    3a4c:	e9c3 6500 	strd	r6, r5, [r3]
    3a50:	e9d1 0203 	ldrd	r0, r2, [r1, #12]
    3a54:	680e      	ldr	r6, [r1, #0]
    3a56:	4b06      	ldr	r3, [pc, #24]	; (3a70 <nrf_cc3xx_platform_set_mutexes+0x34>)
    3a58:	e9d1 5401 	ldrd	r5, r4, [r1, #4]
    3a5c:	e9c3 6500 	strd	r6, r5, [r3]
    3a60:	e9c3 4002 	strd	r4, r0, [r3, #8]
    3a64:	611a      	str	r2, [r3, #16]
    3a66:	bc70      	pop	{r4, r5, r6}
    3a68:	4770      	bx	lr
    3a6a:	bf00      	nop
    3a6c:	20000080 	.word	0x20000080
    3a70:	20000090 	.word	0x20000090

00003a74 <CC_LibInitNoRng>:
    3a74:	b510      	push	{r4, lr}
    3a76:	f7ff fe63 	bl	3740 <CC_HalInit>
    3a7a:	b120      	cbz	r0, 3a86 <CC_LibInitNoRng+0x12>
    3a7c:	2403      	movs	r4, #3
    3a7e:	f7ff fdbb 	bl	35f8 <CC_PalTerminate>
    3a82:	4620      	mov	r0, r4
    3a84:	bd10      	pop	{r4, pc}
    3a86:	f7ff fd89 	bl	359c <CC_PalInit>
    3a8a:	b990      	cbnz	r0, 3ab2 <CC_LibInitNoRng+0x3e>
    3a8c:	f7ff fe16 	bl	36bc <CC_PalPowerSaveModeSelect>
    3a90:	b990      	cbnz	r0, 3ab8 <CC_LibInitNoRng+0x44>
    3a92:	4b0f      	ldr	r3, [pc, #60]	; (3ad0 <CC_LibInitNoRng+0x5c>)
    3a94:	681b      	ldr	r3, [r3, #0]
    3a96:	0e1b      	lsrs	r3, r3, #24
    3a98:	2bf0      	cmp	r3, #240	; 0xf0
    3a9a:	d108      	bne.n	3aae <CC_LibInitNoRng+0x3a>
    3a9c:	4a0d      	ldr	r2, [pc, #52]	; (3ad4 <CC_LibInitNoRng+0x60>)
    3a9e:	4b0e      	ldr	r3, [pc, #56]	; (3ad8 <CC_LibInitNoRng+0x64>)
    3aa0:	6812      	ldr	r2, [r2, #0]
    3aa2:	429a      	cmp	r2, r3
    3aa4:	d00a      	beq.n	3abc <CC_LibInitNoRng+0x48>
    3aa6:	2407      	movs	r4, #7
    3aa8:	f7ff fe4c 	bl	3744 <CC_HalTerminate>
    3aac:	e7e7      	b.n	3a7e <CC_LibInitNoRng+0xa>
    3aae:	2406      	movs	r4, #6
    3ab0:	e7fa      	b.n	3aa8 <CC_LibInitNoRng+0x34>
    3ab2:	2404      	movs	r4, #4
    3ab4:	4620      	mov	r0, r4
    3ab6:	bd10      	pop	{r4, pc}
    3ab8:	2400      	movs	r4, #0
    3aba:	e7f5      	b.n	3aa8 <CC_LibInitNoRng+0x34>
    3abc:	2001      	movs	r0, #1
    3abe:	f7ff fdfd 	bl	36bc <CC_PalPowerSaveModeSelect>
    3ac2:	4604      	mov	r4, r0
    3ac4:	2800      	cmp	r0, #0
    3ac6:	d1f7      	bne.n	3ab8 <CC_LibInitNoRng+0x44>
    3ac8:	4b04      	ldr	r3, [pc, #16]	; (3adc <CC_LibInitNoRng+0x68>)
    3aca:	6018      	str	r0, [r3, #0]
    3acc:	e7d9      	b.n	3a82 <CC_LibInitNoRng+0xe>
    3ace:	bf00      	nop
    3ad0:	50841928 	.word	0x50841928
    3ad4:	50841a24 	.word	0x50841a24
    3ad8:	20e00000 	.word	0x20e00000
    3adc:	50841a0c 	.word	0x50841a0c

00003ae0 <CC_LibInitRngModule>:
    3ae0:	b530      	push	{r4, r5, lr}
    3ae2:	f5ad 7d15 	sub.w	sp, sp, #596	; 0x254
    3ae6:	f44f 7208 	mov.w	r2, #544	; 0x220
    3aea:	2100      	movs	r1, #0
    3aec:	a80c      	add	r0, sp, #48	; 0x30
    3aee:	f000 ffe3 	bl	4ab8 <memset>
    3af2:	2100      	movs	r1, #0
    3af4:	2228      	movs	r2, #40	; 0x28
    3af6:	a802      	add	r0, sp, #8
    3af8:	9101      	str	r1, [sp, #4]
    3afa:	f000 ffdd 	bl	4ab8 <memset>
    3afe:	a802      	add	r0, sp, #8
    3b00:	f7ff feb6 	bl	3870 <RNG_PLAT_SetUserRngParameters>
    3b04:	b120      	cbz	r0, 3b10 <CC_LibInitRngModule+0x30>
    3b06:	2405      	movs	r4, #5
    3b08:	4620      	mov	r0, r4
    3b0a:	f50d 7d15 	add.w	sp, sp, #596	; 0x254
    3b0e:	bd30      	pop	{r4, r5, pc}
    3b10:	4d1d      	ldr	r5, [pc, #116]	; (3b88 <CC_LibInitRngModule+0xa8>)
    3b12:	f04f 31ff 	mov.w	r1, #4294967295
    3b16:	6828      	ldr	r0, [r5, #0]
    3b18:	f7ff fda0 	bl	365c <CC_PalMutexLock>
    3b1c:	4604      	mov	r4, r0
    3b1e:	b9e8      	cbnz	r0, 3b5c <CC_LibInitRngModule+0x7c>
    3b20:	2000      	movs	r0, #0
    3b22:	f7ff fdcb 	bl	36bc <CC_PalPowerSaveModeSelect>
    3b26:	bb58      	cbnz	r0, 3b80 <CC_LibInitRngModule+0xa0>
    3b28:	aa0c      	add	r2, sp, #48	; 0x30
    3b2a:	a902      	add	r1, sp, #8
    3b2c:	a801      	add	r0, sp, #4
    3b2e:	f000 fbed 	bl	430c <LLF_RND_RunTrngStartupTest>
    3b32:	4604      	mov	r4, r0
    3b34:	2001      	movs	r0, #1
    3b36:	f7ff fdc1 	bl	36bc <CC_PalPowerSaveModeSelect>
    3b3a:	b9e8      	cbnz	r0, 3b78 <CC_LibInitRngModule+0x98>
    3b3c:	6828      	ldr	r0, [r5, #0]
    3b3e:	f7ff fd95 	bl	366c <CC_PalMutexUnlock>
    3b42:	b928      	cbnz	r0, 3b50 <CC_LibInitRngModule+0x70>
    3b44:	2c00      	cmp	r4, #0
    3b46:	d1de      	bne.n	3b06 <CC_LibInitRngModule+0x26>
    3b48:	4620      	mov	r0, r4
    3b4a:	f50d 7d15 	add.w	sp, sp, #596	; 0x254
    3b4e:	bd30      	pop	{r4, r5, pc}
    3b50:	480e      	ldr	r0, [pc, #56]	; (3b8c <CC_LibInitRngModule+0xac>)
    3b52:	f7ff ff1b 	bl	398c <CC_PalAbort>
    3b56:	2c00      	cmp	r4, #0
    3b58:	d0f6      	beq.n	3b48 <CC_LibInitRngModule+0x68>
    3b5a:	e7d4      	b.n	3b06 <CC_LibInitRngModule+0x26>
    3b5c:	480c      	ldr	r0, [pc, #48]	; (3b90 <CC_LibInitRngModule+0xb0>)
    3b5e:	f7ff ff15 	bl	398c <CC_PalAbort>
    3b62:	2c01      	cmp	r4, #1
    3b64:	d1dc      	bne.n	3b20 <CC_LibInitRngModule+0x40>
    3b66:	6828      	ldr	r0, [r5, #0]
    3b68:	f7ff fd80 	bl	366c <CC_PalMutexUnlock>
    3b6c:	2800      	cmp	r0, #0
    3b6e:	d0ca      	beq.n	3b06 <CC_LibInitRngModule+0x26>
    3b70:	4806      	ldr	r0, [pc, #24]	; (3b8c <CC_LibInitRngModule+0xac>)
    3b72:	f7ff ff0b 	bl	398c <CC_PalAbort>
    3b76:	e7c6      	b.n	3b06 <CC_LibInitRngModule+0x26>
    3b78:	4806      	ldr	r0, [pc, #24]	; (3b94 <CC_LibInitRngModule+0xb4>)
    3b7a:	f7ff ff07 	bl	398c <CC_PalAbort>
    3b7e:	e7dd      	b.n	3b3c <CC_LibInitRngModule+0x5c>
    3b80:	4805      	ldr	r0, [pc, #20]	; (3b98 <CC_LibInitRngModule+0xb8>)
    3b82:	f7ff ff03 	bl	398c <CC_PalAbort>
    3b86:	e7cf      	b.n	3b28 <CC_LibInitRngModule+0x48>
    3b88:	2000006c 	.word	0x2000006c
    3b8c:	0000538c 	.word	0x0000538c
    3b90:	00005374 	.word	0x00005374
    3b94:	000053c4 	.word	0x000053c4
    3b98:	000053a4 	.word	0x000053a4

00003b9c <CC_LibInit>:
    3b9c:	b508      	push	{r3, lr}
    3b9e:	f7ff fdcf 	bl	3740 <CC_HalInit>
    3ba2:	b118      	cbz	r0, 3bac <CC_LibInit+0x10>
    3ba4:	f7ff fd28 	bl	35f8 <CC_PalTerminate>
    3ba8:	2003      	movs	r0, #3
    3baa:	bd08      	pop	{r3, pc}
    3bac:	f7ff fcf6 	bl	359c <CC_PalInit>
    3bb0:	b9c0      	cbnz	r0, 3be4 <CC_LibInit+0x48>
    3bb2:	f7ff fd83 	bl	36bc <CC_PalPowerSaveModeSelect>
    3bb6:	b9b8      	cbnz	r0, 3be8 <CC_LibInit+0x4c>
    3bb8:	4b14      	ldr	r3, [pc, #80]	; (3c0c <CC_LibInit+0x70>)
    3bba:	681b      	ldr	r3, [r3, #0]
    3bbc:	0e1b      	lsrs	r3, r3, #24
    3bbe:	2bf0      	cmp	r3, #240	; 0xf0
    3bc0:	d10a      	bne.n	3bd8 <CC_LibInit+0x3c>
    3bc2:	4a13      	ldr	r2, [pc, #76]	; (3c10 <CC_LibInit+0x74>)
    3bc4:	4b13      	ldr	r3, [pc, #76]	; (3c14 <CC_LibInit+0x78>)
    3bc6:	6812      	ldr	r2, [r2, #0]
    3bc8:	429a      	cmp	r2, r3
    3bca:	d017      	beq.n	3bfc <CC_LibInit+0x60>
    3bcc:	f7ff fdba 	bl	3744 <CC_HalTerminate>
    3bd0:	f7ff fd12 	bl	35f8 <CC_PalTerminate>
    3bd4:	2007      	movs	r0, #7
    3bd6:	bd08      	pop	{r3, pc}
    3bd8:	f7ff fdb4 	bl	3744 <CC_HalTerminate>
    3bdc:	f7ff fd0c 	bl	35f8 <CC_PalTerminate>
    3be0:	2006      	movs	r0, #6
    3be2:	bd08      	pop	{r3, pc}
    3be4:	2004      	movs	r0, #4
    3be6:	bd08      	pop	{r3, pc}
    3be8:	f7ff fdac 	bl	3744 <CC_HalTerminate>
    3bec:	f7ff fd04 	bl	35f8 <CC_PalTerminate>
    3bf0:	f7ff ff76 	bl	3ae0 <CC_LibInitRngModule>
    3bf4:	2800      	cmp	r0, #0
    3bf6:	bf18      	it	ne
    3bf8:	2005      	movne	r0, #5
    3bfa:	bd08      	pop	{r3, pc}
    3bfc:	2001      	movs	r0, #1
    3bfe:	f7ff fd5d 	bl	36bc <CC_PalPowerSaveModeSelect>
    3c02:	2800      	cmp	r0, #0
    3c04:	d1f0      	bne.n	3be8 <CC_LibInit+0x4c>
    3c06:	4b04      	ldr	r3, [pc, #16]	; (3c18 <CC_LibInit+0x7c>)
    3c08:	6018      	str	r0, [r3, #0]
    3c0a:	e7f1      	b.n	3bf0 <CC_LibInit+0x54>
    3c0c:	50841928 	.word	0x50841928
    3c10:	50841a24 	.word	0x50841a24
    3c14:	20e00000 	.word	0x20e00000
    3c18:	50841a0c 	.word	0x50841a0c

00003c1c <CC_PalTrngParamGet>:
    3c1c:	2800      	cmp	r0, #0
    3c1e:	d066      	beq.n	3cee <CC_PalTrngParamGet+0xd2>
    3c20:	2900      	cmp	r1, #0
    3c22:	d064      	beq.n	3cee <CC_PalTrngParamGet+0xd2>
    3c24:	680b      	ldr	r3, [r1, #0]
    3c26:	2b1c      	cmp	r3, #28
    3c28:	d161      	bne.n	3cee <CC_PalTrngParamGet+0xd2>
    3c2a:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3c2e:	4a3b      	ldr	r2, [pc, #236]	; (3d1c <CC_PalTrngParamGet+0x100>)
    3c30:	f8d3 1c10 	ldr.w	r1, [r3, #3088]	; 0xc10
    3c34:	4291      	cmp	r1, r2
    3c36:	d05c      	beq.n	3cf2 <CC_PalTrngParamGet+0xd6>
    3c38:	f8d3 2c10 	ldr.w	r2, [r3, #3088]	; 0xc10
    3c3c:	3201      	adds	r2, #1
    3c3e:	d058      	beq.n	3cf2 <CC_PalTrngParamGet+0xd6>
    3c40:	f8d3 2c10 	ldr.w	r2, [r3, #3088]	; 0xc10
    3c44:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3c48:	6002      	str	r2, [r0, #0]
    3c4a:	f8d3 1c14 	ldr.w	r1, [r3, #3092]	; 0xc14
    3c4e:	4a34      	ldr	r2, [pc, #208]	; (3d20 <CC_PalTrngParamGet+0x104>)
    3c50:	4291      	cmp	r1, r2
    3c52:	d060      	beq.n	3d16 <CC_PalTrngParamGet+0xfa>
    3c54:	f8d3 2c14 	ldr.w	r2, [r3, #3092]	; 0xc14
    3c58:	3201      	adds	r2, #1
    3c5a:	d05c      	beq.n	3d16 <CC_PalTrngParamGet+0xfa>
    3c5c:	f8d3 2c14 	ldr.w	r2, [r3, #3092]	; 0xc14
    3c60:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3c64:	6042      	str	r2, [r0, #4]
    3c66:	f8d3 2c18 	ldr.w	r2, [r3, #3096]	; 0xc18
    3c6a:	f512 7f94 	cmn.w	r2, #296	; 0x128
    3c6e:	d04f      	beq.n	3d10 <CC_PalTrngParamGet+0xf4>
    3c70:	f8d3 2c18 	ldr.w	r2, [r3, #3096]	; 0xc18
    3c74:	3201      	adds	r2, #1
    3c76:	d04b      	beq.n	3d10 <CC_PalTrngParamGet+0xf4>
    3c78:	f8d3 2c18 	ldr.w	r2, [r3, #3096]	; 0xc18
    3c7c:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3c80:	6082      	str	r2, [r0, #8]
    3c82:	f8d3 1c1c 	ldr.w	r1, [r3, #3100]	; 0xc1c
    3c86:	4a27      	ldr	r2, [pc, #156]	; (3d24 <CC_PalTrngParamGet+0x108>)
    3c88:	4291      	cmp	r1, r2
    3c8a:	d03e      	beq.n	3d0a <CC_PalTrngParamGet+0xee>
    3c8c:	f8d3 2c1c 	ldr.w	r2, [r3, #3100]	; 0xc1c
    3c90:	3201      	adds	r2, #1
    3c92:	d03a      	beq.n	3d0a <CC_PalTrngParamGet+0xee>
    3c94:	f8d3 2c1c 	ldr.w	r2, [r3, #3100]	; 0xc1c
    3c98:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3c9c:	60c2      	str	r2, [r0, #12]
    3c9e:	f8d3 2c00 	ldr.w	r2, [r3, #3072]	; 0xc00
    3ca2:	3270      	adds	r2, #112	; 0x70
    3ca4:	d02f      	beq.n	3d06 <CC_PalTrngParamGet+0xea>
    3ca6:	f8d3 2c00 	ldr.w	r2, [r3, #3072]	; 0xc00
    3caa:	3201      	adds	r2, #1
    3cac:	d02b      	beq.n	3d06 <CC_PalTrngParamGet+0xea>
    3cae:	f8d3 2c00 	ldr.w	r2, [r3, #3072]	; 0xc00
    3cb2:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3cb6:	6102      	str	r2, [r0, #16]
    3cb8:	f8d3 2c04 	ldr.w	r2, [r3, #3076]	; 0xc04
    3cbc:	32af      	adds	r2, #175	; 0xaf
    3cbe:	d020      	beq.n	3d02 <CC_PalTrngParamGet+0xe6>
    3cc0:	f8d3 2c04 	ldr.w	r2, [r3, #3076]	; 0xc04
    3cc4:	3201      	adds	r2, #1
    3cc6:	d01c      	beq.n	3d02 <CC_PalTrngParamGet+0xe6>
    3cc8:	f8d3 2c04 	ldr.w	r2, [r3, #3076]	; 0xc04
    3ccc:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3cd0:	6142      	str	r2, [r0, #20]
    3cd2:	f8d3 1c08 	ldr.w	r1, [r3, #3080]	; 0xc08
    3cd6:	4a14      	ldr	r2, [pc, #80]	; (3d28 <CC_PalTrngParamGet+0x10c>)
    3cd8:	4291      	cmp	r1, r2
    3cda:	d00d      	beq.n	3cf8 <CC_PalTrngParamGet+0xdc>
    3cdc:	f8d3 2c08 	ldr.w	r2, [r3, #3080]	; 0xc08
    3ce0:	3201      	adds	r2, #1
    3ce2:	d009      	beq.n	3cf8 <CC_PalTrngParamGet+0xdc>
    3ce4:	f8d3 3c08 	ldr.w	r3, [r3, #3080]	; 0xc08
    3ce8:	6183      	str	r3, [r0, #24]
    3cea:	2000      	movs	r0, #0
    3cec:	4770      	bx	lr
    3cee:	2001      	movs	r0, #1
    3cf0:	4770      	bx	lr
    3cf2:	f640 02fc 	movw	r2, #2300	; 0x8fc
    3cf6:	e7a5      	b.n	3c44 <CC_PalTrngParamGet+0x28>
    3cf8:	f240 3337 	movw	r3, #823	; 0x337
    3cfc:	6183      	str	r3, [r0, #24]
    3cfe:	2000      	movs	r0, #0
    3d00:	4770      	bx	lr
    3d02:	2251      	movs	r2, #81	; 0x51
    3d04:	e7e2      	b.n	3ccc <CC_PalTrngParamGet+0xb0>
    3d06:	2290      	movs	r2, #144	; 0x90
    3d08:	e7d3      	b.n	3cb2 <CC_PalTrngParamGet+0x96>
    3d0a:	f642 1204 	movw	r2, #10500	; 0x2904
    3d0e:	e7c3      	b.n	3c98 <CC_PalTrngParamGet+0x7c>
    3d10:	f640 62d8 	movw	r2, #3800	; 0xed8
    3d14:	e7b2      	b.n	3c7c <CC_PalTrngParamGet+0x60>
    3d16:	f242 02d0 	movw	r2, #8400	; 0x20d0
    3d1a:	e7a1      	b.n	3c60 <CC_PalTrngParamGet+0x44>
    3d1c:	fffff8fc 	.word	0xfffff8fc
    3d20:	ffff20d0 	.word	0xffff20d0
    3d24:	ffff2904 	.word	0xffff2904
    3d28:	fffff337 	.word	0xfffff337

00003d2c <startTrngHW>:
    3d2c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    3d30:	2800      	cmp	r0, #0
    3d32:	d077      	beq.n	3e24 <startTrngHW+0xf8>
    3d34:	460c      	mov	r4, r1
    3d36:	2900      	cmp	r1, #0
    3d38:	d074      	beq.n	3e24 <startTrngHW+0xf8>
    3d3a:	461d      	mov	r5, r3
    3d3c:	2b00      	cmp	r3, #0
    3d3e:	d071      	beq.n	3e24 <startTrngHW+0xf8>
    3d40:	4606      	mov	r6, r0
    3d42:	b11a      	cbz	r2, 3d4c <startTrngHW+0x20>
    3d44:	2201      	movs	r2, #1
    3d46:	2300      	movs	r3, #0
    3d48:	602a      	str	r2, [r5, #0]
    3d4a:	6003      	str	r3, [r0, #0]
    3d4c:	682b      	ldr	r3, [r5, #0]
    3d4e:	2b00      	cmp	r3, #0
    3d50:	d064      	beq.n	3e1c <startTrngHW+0xf0>
    3d52:	4629      	mov	r1, r5
    3d54:	4620      	mov	r0, r4
    3d56:	f000 fb15 	bl	4384 <LLF_RND_GetFastestRosc>
    3d5a:	4607      	mov	r7, r0
    3d5c:	2800      	cmp	r0, #0
    3d5e:	d15e      	bne.n	3e1e <startTrngHW+0xf2>
    3d60:	4621      	mov	r1, r4
    3d62:	6828      	ldr	r0, [r5, #0]
    3d64:	f000 faf0 	bl	4348 <LLF_RND_GetRoscSampleCnt>
    3d68:	4607      	mov	r7, r0
    3d6a:	2800      	cmp	r0, #0
    3d6c:	d157      	bne.n	3e1e <startTrngHW+0xf2>
    3d6e:	682b      	ldr	r3, [r5, #0]
    3d70:	2b08      	cmp	r3, #8
    3d72:	d066      	beq.n	3e42 <startTrngHW+0x116>
    3d74:	2b04      	cmp	r3, #4
    3d76:	d067      	beq.n	3e48 <startTrngHW+0x11c>
    3d78:	f1a3 0802 	sub.w	r8, r3, #2
    3d7c:	fab8 f888 	clz	r8, r8
    3d80:	ea4f 1858 	mov.w	r8, r8, lsr #5
    3d84:	2301      	movs	r3, #1
    3d86:	469c      	mov	ip, r3
    3d88:	4a31      	ldr	r2, [pc, #196]	; (3e50 <startTrngHW+0x124>)
    3d8a:	4932      	ldr	r1, [pc, #200]	; (3e54 <startTrngHW+0x128>)
    3d8c:	6013      	str	r3, [r2, #0]
    3d8e:	4610      	mov	r0, r2
    3d90:	600b      	str	r3, [r1, #0]
    3d92:	3a94      	subs	r2, #148	; 0x94
    3d94:	f8c0 c000 	str.w	ip, [r0]
    3d98:	6a63      	ldr	r3, [r4, #36]	; 0x24
    3d9a:	6013      	str	r3, [r2, #0]
    3d9c:	6811      	ldr	r1, [r2, #0]
    3d9e:	428b      	cmp	r3, r1
    3da0:	d1f8      	bne.n	3d94 <startTrngHW+0x68>
    3da2:	f04f 0900 	mov.w	r9, #0
    3da6:	4b2c      	ldr	r3, [pc, #176]	; (3e58 <startTrngHW+0x12c>)
    3da8:	f04f 30ff 	mov.w	r0, #4294967295
    3dac:	f8c3 9000 	str.w	r9, [r3]
    3db0:	f7ff fcca 	bl	3748 <CC_HalClearInterruptBit>
    3db4:	4b29      	ldr	r3, [pc, #164]	; (3e5c <startTrngHW+0x130>)
    3db6:	4a2a      	ldr	r2, [pc, #168]	; (3e60 <startTrngHW+0x134>)
    3db8:	4648      	mov	r0, r9
    3dba:	601a      	str	r2, [r3, #0]
    3dbc:	f7ff fcd2 	bl	3764 <CC_HalMaskInterrupt>
    3dc0:	4a28      	ldr	r2, [pc, #160]	; (3e64 <startTrngHW+0x138>)
    3dc2:	4b29      	ldr	r3, [pc, #164]	; (3e68 <startTrngHW+0x13c>)
    3dc4:	f8c2 8000 	str.w	r8, [r2]
    3dc8:	6818      	ldr	r0, [r3, #0]
    3dca:	f440 6080 	orr.w	r0, r0, #1024	; 0x400
    3dce:	f7ff fcc9 	bl	3764 <CC_HalMaskInterrupt>
    3dd2:	220a      	movs	r2, #10
    3dd4:	4b25      	ldr	r3, [pc, #148]	; (3e6c <startTrngHW+0x140>)
    3dd6:	601a      	str	r2, [r3, #0]
    3dd8:	9a08      	ldr	r2, [sp, #32]
    3dda:	6923      	ldr	r3, [r4, #16]
    3ddc:	2a01      	cmp	r2, #1
    3dde:	6a61      	ldr	r1, [r4, #36]	; 0x24
    3de0:	d024      	beq.n	3e2c <startTrngHW+0x100>
    3de2:	4a23      	ldr	r2, [pc, #140]	; (3e70 <startTrngHW+0x144>)
    3de4:	fba2 2303 	umull	r2, r3, r2, r3
    3de8:	091b      	lsrs	r3, r3, #4
    3dea:	2201      	movs	r2, #1
    3dec:	fb03 f301 	mul.w	r3, r3, r1
    3df0:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    3df4:	491f      	ldr	r1, [pc, #124]	; (3e74 <startTrngHW+0x148>)
    3df6:	03db      	lsls	r3, r3, #15
    3df8:	099b      	lsrs	r3, r3, #6
    3dfa:	600b      	str	r3, [r1, #0]
    3dfc:	4b16      	ldr	r3, [pc, #88]	; (3e58 <startTrngHW+0x12c>)
    3dfe:	4638      	mov	r0, r7
    3e00:	601a      	str	r2, [r3, #0]
    3e02:	6833      	ldr	r3, [r6, #0]
    3e04:	682a      	ldr	r2, [r5, #0]
    3e06:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    3e0a:	ea43 6302 	orr.w	r3, r3, r2, lsl #24
    3e0e:	6033      	str	r3, [r6, #0]
    3e10:	682a      	ldr	r2, [r5, #0]
    3e12:	ea43 2302 	orr.w	r3, r3, r2, lsl #8
    3e16:	6033      	str	r3, [r6, #0]
    3e18:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    3e1c:	4f16      	ldr	r7, [pc, #88]	; (3e78 <startTrngHW+0x14c>)
    3e1e:	4638      	mov	r0, r7
    3e20:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    3e24:	4f15      	ldr	r7, [pc, #84]	; (3e7c <startTrngHW+0x150>)
    3e26:	4638      	mov	r0, r7
    3e28:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    3e2c:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3e30:	f8d3 2c0c 	ldr.w	r2, [r3, #3084]	; 0xc0c
    3e34:	3201      	adds	r2, #1
    3e36:	d002      	beq.n	3e3e <startTrngHW+0x112>
    3e38:	f8d3 3c0c 	ldr.w	r3, [r3, #3084]	; 0xc0c
    3e3c:	e7d1      	b.n	3de2 <startTrngHW+0xb6>
    3e3e:	2316      	movs	r3, #22
    3e40:	e7d3      	b.n	3dea <startTrngHW+0xbe>
    3e42:	f04f 0803 	mov.w	r8, #3
    3e46:	e79d      	b.n	3d84 <startTrngHW+0x58>
    3e48:	f04f 0802 	mov.w	r8, #2
    3e4c:	e79a      	b.n	3d84 <startTrngHW+0x58>
    3e4e:	bf00      	nop
    3e50:	508411c4 	.word	0x508411c4
    3e54:	50841140 	.word	0x50841140
    3e58:	5084112c 	.word	0x5084112c
    3e5c:	50841100 	.word	0x50841100
    3e60:	0ffffffe 	.word	0x0ffffffe
    3e64:	5084110c 	.word	0x5084110c
    3e68:	50841a04 	.word	0x50841a04
    3e6c:	50841138 	.word	0x50841138
    3e70:	aaaaaaab 	.word	0xaaaaaaab
    3e74:	508411d8 	.word	0x508411d8
    3e78:	00f10c31 	.word	0x00f10c31
    3e7c:	00f10c35 	.word	0x00f10c35

00003e80 <LLF_RND_RepetitionCounterTest.part.0>:
    3e80:	b4f0      	push	{r4, r5, r6, r7}
    3e82:	2400      	movs	r4, #0
    3e84:	00c9      	lsls	r1, r1, #3
    3e86:	4626      	mov	r6, r4
    3e88:	4627      	mov	r7, r4
    3e8a:	f101 3cff 	add.w	ip, r1, #4294967295
    3e8e:	e006      	b.n	3e9e <LLF_RND_RepetitionCounterTest.part.0+0x1e>
    3e90:	429f      	cmp	r7, r3
    3e92:	d015      	beq.n	3ec0 <LLF_RND_RepetitionCounterTest.part.0+0x40>
    3e94:	2601      	movs	r6, #1
    3e96:	4565      	cmp	r5, ip
    3e98:	d818      	bhi.n	3ecc <LLF_RND_RepetitionCounterTest.part.0+0x4c>
    3e9a:	462c      	mov	r4, r5
    3e9c:	461f      	mov	r7, r3
    3e9e:	0963      	lsrs	r3, r4, #5
    3ea0:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
    3ea4:	f004 011f 	and.w	r1, r4, #31
    3ea8:	40cb      	lsrs	r3, r1
    3eaa:	291f      	cmp	r1, #31
    3eac:	f104 0501 	add.w	r5, r4, #1
    3eb0:	bf18      	it	ne
    3eb2:	f003 0301 	andne.w	r3, r3, #1
    3eb6:	2c00      	cmp	r4, #0
    3eb8:	d1ea      	bne.n	3e90 <LLF_RND_RepetitionCounterTest.part.0+0x10>
    3eba:	2601      	movs	r6, #1
    3ebc:	4635      	mov	r5, r6
    3ebe:	e7ec      	b.n	3e9a <LLF_RND_RepetitionCounterTest.part.0+0x1a>
    3ec0:	3601      	adds	r6, #1
    3ec2:	4296      	cmp	r6, r2
    3ec4:	d1e7      	bne.n	3e96 <LLF_RND_RepetitionCounterTest.part.0+0x16>
    3ec6:	4803      	ldr	r0, [pc, #12]	; (3ed4 <LLF_RND_RepetitionCounterTest.part.0+0x54>)
    3ec8:	bcf0      	pop	{r4, r5, r6, r7}
    3eca:	4770      	bx	lr
    3ecc:	2000      	movs	r0, #0
    3ece:	bcf0      	pop	{r4, r5, r6, r7}
    3ed0:	4770      	bx	lr
    3ed2:	bf00      	nop
    3ed4:	00f10c36 	.word	0x00f10c36

00003ed8 <LLF_RND_AdaptiveProportionTest>:
    3ed8:	2800      	cmp	r0, #0
    3eda:	d05f      	beq.n	3f9c <LLF_RND_AdaptiveProportionTest+0xc4>
    3edc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3ee0:	1e4c      	subs	r4, r1, #1
    3ee2:	f5b4 7f04 	cmp.w	r4, #528	; 0x210
    3ee6:	d226      	bcs.n	3f36 <LLF_RND_AdaptiveProportionTest+0x5e>
    3ee8:	b32b      	cbz	r3, 3f36 <LLF_RND_AdaptiveProportionTest+0x5e>
    3eea:	b322      	cbz	r2, 3f36 <LLF_RND_AdaptiveProportionTest+0x5e>
    3eec:	00cc      	lsls	r4, r1, #3
    3eee:	2b01      	cmp	r3, #1
    3ef0:	f104 3eff 	add.w	lr, r4, #4294967295
    3ef4:	d02f      	beq.n	3f56 <LLF_RND_AdaptiveProportionTest+0x7e>
    3ef6:	2100      	movs	r1, #0
    3ef8:	468c      	mov	ip, r1
    3efa:	460f      	mov	r7, r1
    3efc:	460d      	mov	r5, r1
    3efe:	f103 38ff 	add.w	r8, r3, #4294967295
    3f02:	094c      	lsrs	r4, r1, #5
    3f04:	f850 4024 	ldr.w	r4, [r0, r4, lsl #2]
    3f08:	f001 061f 	and.w	r6, r1, #31
    3f0c:	40f4      	lsrs	r4, r6
    3f0e:	2e1f      	cmp	r6, #31
    3f10:	bf18      	it	ne
    3f12:	f004 0401 	andne.w	r4, r4, #1
    3f16:	b921      	cbnz	r1, 3f22 <LLF_RND_AdaptiveProportionTest+0x4a>
    3f18:	2501      	movs	r5, #1
    3f1a:	46ac      	mov	ip, r5
    3f1c:	4629      	mov	r1, r5
    3f1e:	4627      	mov	r7, r4
    3f20:	e7ef      	b.n	3f02 <LLF_RND_AdaptiveProportionTest+0x2a>
    3f22:	42ab      	cmp	r3, r5
    3f24:	d013      	beq.n	3f4e <LLF_RND_AdaptiveProportionTest+0x76>
    3f26:	42a7      	cmp	r7, r4
    3f28:	d101      	bne.n	3f2e <LLF_RND_AdaptiveProportionTest+0x56>
    3f2a:	f10c 0c01 	add.w	ip, ip, #1
    3f2e:	4545      	cmp	r5, r8
    3f30:	d104      	bne.n	3f3c <LLF_RND_AdaptiveProportionTest+0x64>
    3f32:	4562      	cmp	r2, ip
    3f34:	d202      	bcs.n	3f3c <LLF_RND_AdaptiveProportionTest+0x64>
    3f36:	481a      	ldr	r0, [pc, #104]	; (3fa0 <LLF_RND_AdaptiveProportionTest+0xc8>)
    3f38:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    3f3c:	463c      	mov	r4, r7
    3f3e:	3101      	adds	r1, #1
    3f40:	458e      	cmp	lr, r1
    3f42:	f105 0501 	add.w	r5, r5, #1
    3f46:	d2ea      	bcs.n	3f1e <LLF_RND_AdaptiveProportionTest+0x46>
    3f48:	2000      	movs	r0, #0
    3f4a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    3f4e:	2500      	movs	r5, #0
    3f50:	f04f 0c01 	mov.w	ip, #1
    3f54:	e7f3      	b.n	3f3e <LLF_RND_AdaptiveProportionTest+0x66>
    3f56:	2600      	movs	r6, #0
    3f58:	46b4      	mov	ip, r6
    3f5a:	4637      	mov	r7, r6
    3f5c:	4631      	mov	r1, r6
    3f5e:	094b      	lsrs	r3, r1, #5
    3f60:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
    3f64:	f001 051f 	and.w	r5, r1, #31
    3f68:	40eb      	lsrs	r3, r5
    3f6a:	2d1f      	cmp	r5, #31
    3f6c:	bf18      	it	ne
    3f6e:	f003 0301 	andne.w	r3, r3, #1
    3f72:	b139      	cbz	r1, 3f84 <LLF_RND_AdaptiveProportionTest+0xac>
    3f74:	b95f      	cbnz	r7, 3f8e <LLF_RND_AdaptiveProportionTest+0xb6>
    3f76:	459c      	cmp	ip, r3
    3f78:	d001      	beq.n	3f7e <LLF_RND_AdaptiveProportionTest+0xa6>
    3f7a:	4663      	mov	r3, ip
    3f7c:	e008      	b.n	3f90 <LLF_RND_AdaptiveProportionTest+0xb8>
    3f7e:	4663      	mov	r3, ip
    3f80:	3601      	adds	r6, #1
    3f82:	e005      	b.n	3f90 <LLF_RND_AdaptiveProportionTest+0xb8>
    3f84:	2601      	movs	r6, #1
    3f86:	4631      	mov	r1, r6
    3f88:	469c      	mov	ip, r3
    3f8a:	2701      	movs	r7, #1
    3f8c:	e7e7      	b.n	3f5e <LLF_RND_AdaptiveProportionTest+0x86>
    3f8e:	463e      	mov	r6, r7
    3f90:	42b2      	cmp	r2, r6
    3f92:	d3d0      	bcc.n	3f36 <LLF_RND_AdaptiveProportionTest+0x5e>
    3f94:	3101      	adds	r1, #1
    3f96:	42a1      	cmp	r1, r4
    3f98:	d1f6      	bne.n	3f88 <LLF_RND_AdaptiveProportionTest+0xb0>
    3f9a:	e7d5      	b.n	3f48 <LLF_RND_AdaptiveProportionTest+0x70>
    3f9c:	4800      	ldr	r0, [pc, #0]	; (3fa0 <LLF_RND_AdaptiveProportionTest+0xc8>)
    3f9e:	4770      	bx	lr
    3fa0:	00f10c37 	.word	0x00f10c37

00003fa4 <getTrngSource>:
    3fa4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3fa8:	b08d      	sub	sp, #52	; 0x34
    3faa:	9e18      	ldr	r6, [sp, #96]	; 0x60
    3fac:	4607      	mov	r7, r0
    3fae:	460c      	mov	r4, r1
    3fb0:	9d17      	ldr	r5, [sp, #92]	; 0x5c
    3fb2:	2e00      	cmp	r6, #0
    3fb4:	d14c      	bne.n	4050 <getTrngSource+0xac>
    3fb6:	f8d1 b010 	ldr.w	fp, [r1, #16]
    3fba:	2100      	movs	r1, #0
    3fbc:	601d      	str	r5, [r3, #0]
    3fbe:	9b16      	ldr	r3, [sp, #88]	; 0x58
    3fc0:	6019      	str	r1, [r3, #0]
    3fc2:	2a00      	cmp	r2, #0
    3fc4:	f000 811e 	beq.w	4204 <getTrngSource+0x260>
    3fc8:	4a9a      	ldr	r2, [pc, #616]	; (4234 <getTrngSource+0x290>)
    3fca:	4b9b      	ldr	r3, [pc, #620]	; (4238 <getTrngSource+0x294>)
    3fcc:	6811      	ldr	r1, [r2, #0]
    3fce:	6a62      	ldr	r2, [r4, #36]	; 0x24
    3fd0:	681b      	ldr	r3, [r3, #0]
    3fd2:	429a      	cmp	r2, r3
    3fd4:	d147      	bne.n	4066 <getTrngSource+0xc2>
    3fd6:	290a      	cmp	r1, #10
    3fd8:	d145      	bne.n	4066 <getTrngSource+0xc2>
    3fda:	78fb      	ldrb	r3, [r7, #3]
    3fdc:	9304      	str	r3, [sp, #16]
    3fde:	2304      	movs	r3, #4
    3fe0:	46b8      	mov	r8, r7
    3fe2:	9302      	str	r3, [sp, #8]
    3fe4:	4b95      	ldr	r3, [pc, #596]	; (423c <getTrngSource+0x298>)
    3fe6:	fba3 230b 	umull	r2, r3, r3, fp
    3fea:	ea4f 0a93 	mov.w	sl, r3, lsr #2
    3fee:	eb0a 034a 	add.w	r3, sl, sl, lsl #1
    3ff2:	f105 0208 	add.w	r2, r5, #8
    3ff6:	9203      	str	r2, [sp, #12]
    3ff8:	ebab 0a43 	sub.w	sl, fp, r3, lsl #1
    3ffc:	9b16      	ldr	r3, [sp, #88]	; 0x58
    3ffe:	f8c3 b000 	str.w	fp, [r3]
    4002:	f1bb 0f00 	cmp.w	fp, #0
    4006:	f000 80c3 	beq.w	4190 <getTrngSource+0x1ec>
    400a:	465d      	mov	r5, fp
    400c:	f04f 0900 	mov.w	r9, #0
    4010:	9e03      	ldr	r6, [sp, #12]
    4012:	f000 f9c7 	bl	43a4 <LLF_RND_TurnOffTrng>
    4016:	2300      	movs	r3, #0
    4018:	9305      	str	r3, [sp, #20]
    401a:	f1b8 0f00 	cmp.w	r8, #0
    401e:	f000 80e5 	beq.w	41ec <getTrngSource+0x248>
    4022:	2c00      	cmp	r4, #0
    4024:	f000 80e2 	beq.w	41ec <getTrngSource+0x248>
    4028:	9b04      	ldr	r3, [sp, #16]
    402a:	2b00      	cmp	r3, #0
    402c:	f000 80dc 	beq.w	41e8 <getTrngSource+0x244>
    4030:	4620      	mov	r0, r4
    4032:	a904      	add	r1, sp, #16
    4034:	f000 f9a6 	bl	4384 <LLF_RND_GetFastestRosc>
    4038:	b1b8      	cbz	r0, 406a <getTrngSource+0xc6>
    403a:	4b81      	ldr	r3, [pc, #516]	; (4240 <getTrngSource+0x29c>)
    403c:	4298      	cmp	r0, r3
    403e:	f040 80a7 	bne.w	4190 <getTrngSource+0x1ec>
    4042:	9002      	str	r0, [sp, #8]
    4044:	f000 f9ae 	bl	43a4 <LLF_RND_TurnOffTrng>
    4048:	9802      	ldr	r0, [sp, #8]
    404a:	b00d      	add	sp, #52	; 0x34
    404c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    4050:	f44f 017f 	mov.w	r1, #16711680	; 0xff0000
    4054:	f8d1 0c0c 	ldr.w	r0, [r1, #3084]	; 0xc0c
    4058:	3001      	adds	r0, #1
    405a:	bf0c      	ite	eq
    405c:	f44f 7b04 	moveq.w	fp, #528	; 0x210
    4060:	f8d1 bc0c 	ldrne.w	fp, [r1, #3084]	; 0xc0c
    4064:	e7a9      	b.n	3fba <getTrngSource+0x16>
    4066:	4877      	ldr	r0, [pc, #476]	; (4244 <getTrngSource+0x2a0>)
    4068:	e7eb      	b.n	4042 <getTrngSource+0x9e>
    406a:	4621      	mov	r1, r4
    406c:	9804      	ldr	r0, [sp, #16]
    406e:	f000 f96b 	bl	4348 <LLF_RND_GetRoscSampleCnt>
    4072:	2800      	cmp	r0, #0
    4074:	d1e1      	bne.n	403a <getTrngSource+0x96>
    4076:	9f04      	ldr	r7, [sp, #16]
    4078:	2f08      	cmp	r7, #8
    407a:	f000 80b9 	beq.w	41f0 <getTrngSource+0x24c>
    407e:	2f04      	cmp	r7, #4
    4080:	f000 80b8 	beq.w	41f4 <getTrngSource+0x250>
    4084:	f1a7 0702 	sub.w	r7, r7, #2
    4088:	fab7 f787 	clz	r7, r7
    408c:	097f      	lsrs	r7, r7, #5
    408e:	2301      	movs	r3, #1
    4090:	4619      	mov	r1, r3
    4092:	486d      	ldr	r0, [pc, #436]	; (4248 <getTrngSource+0x2a4>)
    4094:	6003      	str	r3, [r0, #0]
    4096:	f840 3c84 	str.w	r3, [r0, #-132]
    409a:	4b6b      	ldr	r3, [pc, #428]	; (4248 <getTrngSource+0x2a4>)
    409c:	4866      	ldr	r0, [pc, #408]	; (4238 <getTrngSource+0x294>)
    409e:	6019      	str	r1, [r3, #0]
    40a0:	6a63      	ldr	r3, [r4, #36]	; 0x24
    40a2:	6003      	str	r3, [r0, #0]
    40a4:	6800      	ldr	r0, [r0, #0]
    40a6:	4283      	cmp	r3, r0
    40a8:	d1f7      	bne.n	409a <getTrngSource+0xf6>
    40aa:	2300      	movs	r3, #0
    40ac:	4a67      	ldr	r2, [pc, #412]	; (424c <getTrngSource+0x2a8>)
    40ae:	f04f 30ff 	mov.w	r0, #4294967295
    40b2:	6013      	str	r3, [r2, #0]
    40b4:	f7ff fb48 	bl	3748 <CC_HalClearInterruptBit>
    40b8:	2300      	movs	r3, #0
    40ba:	4965      	ldr	r1, [pc, #404]	; (4250 <getTrngSource+0x2ac>)
    40bc:	4618      	mov	r0, r3
    40be:	4b65      	ldr	r3, [pc, #404]	; (4254 <getTrngSource+0x2b0>)
    40c0:	6019      	str	r1, [r3, #0]
    40c2:	f7ff fb4f 	bl	3764 <CC_HalMaskInterrupt>
    40c6:	4964      	ldr	r1, [pc, #400]	; (4258 <getTrngSource+0x2b4>)
    40c8:	4b64      	ldr	r3, [pc, #400]	; (425c <getTrngSource+0x2b8>)
    40ca:	600f      	str	r7, [r1, #0]
    40cc:	6818      	ldr	r0, [r3, #0]
    40ce:	4f5b      	ldr	r7, [pc, #364]	; (423c <getTrngSource+0x298>)
    40d0:	f440 6080 	orr.w	r0, r0, #1024	; 0x400
    40d4:	f7ff fb46 	bl	3764 <CC_HalMaskInterrupt>
    40d8:	210a      	movs	r1, #10
    40da:	2201      	movs	r2, #1
    40dc:	4b55      	ldr	r3, [pc, #340]	; (4234 <getTrngSource+0x290>)
    40de:	4860      	ldr	r0, [pc, #384]	; (4260 <getTrngSource+0x2bc>)
    40e0:	6019      	str	r1, [r3, #0]
    40e2:	6921      	ldr	r1, [r4, #16]
    40e4:	6a63      	ldr	r3, [r4, #36]	; 0x24
    40e6:	fba7 c101 	umull	ip, r1, r7, r1
    40ea:	0909      	lsrs	r1, r1, #4
    40ec:	fb03 f301 	mul.w	r3, r3, r1
    40f0:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    40f4:	03db      	lsls	r3, r3, #15
    40f6:	099b      	lsrs	r3, r3, #6
    40f8:	6003      	str	r3, [r0, #0]
    40fa:	4b54      	ldr	r3, [pc, #336]	; (424c <getTrngSource+0x2a8>)
    40fc:	a805      	add	r0, sp, #20
    40fe:	601a      	str	r2, [r3, #0]
    4100:	9904      	ldr	r1, [sp, #16]
    4102:	f8d8 2000 	ldr.w	r2, [r8]
    4106:	020b      	lsls	r3, r1, #8
    4108:	ea43 6301 	orr.w	r3, r3, r1, lsl #24
    410c:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
    4110:	4313      	orrs	r3, r2
    4112:	f8c8 3000 	str.w	r3, [r8]
    4116:	f000 f907 	bl	4328 <LLF_RND_WaitRngInterrupt>
    411a:	2800      	cmp	r0, #0
    411c:	d18d      	bne.n	403a <getTrngSource+0x96>
    411e:	4b51      	ldr	r3, [pc, #324]	; (4264 <getTrngSource+0x2c0>)
    4120:	fba7 2705 	umull	r2, r7, r7, r5
    4124:	681a      	ldr	r2, [r3, #0]
    4126:	3314      	adds	r3, #20
    4128:	9206      	str	r2, [sp, #24]
    412a:	f853 2c10 	ldr.w	r2, [r3, #-16]
    412e:	ebb9 0f97 	cmp.w	r9, r7, lsr #2
    4132:	9207      	str	r2, [sp, #28]
    4134:	f853 2c0c 	ldr.w	r2, [r3, #-12]
    4138:	9208      	str	r2, [sp, #32]
    413a:	f853 2c08 	ldr.w	r2, [r3, #-8]
    413e:	9209      	str	r2, [sp, #36]	; 0x24
    4140:	f853 2c04 	ldr.w	r2, [r3, #-4]
    4144:	920a      	str	r2, [sp, #40]	; 0x28
    4146:	681b      	ldr	r3, [r3, #0]
    4148:	930b      	str	r3, [sp, #44]	; 0x2c
    414a:	d102      	bne.n	4152 <getTrngSource+0x1ae>
    414c:	f1ba 0f00 	cmp.w	sl, #0
    4150:	d141      	bne.n	41d6 <getTrngSource+0x232>
    4152:	2218      	movs	r2, #24
    4154:	4630      	mov	r0, r6
    4156:	eb0d 0102 	add.w	r1, sp, r2
    415a:	f7ff fa19 	bl	3590 <CC_PalMemCopyPlat>
    415e:	3d18      	subs	r5, #24
    4160:	3618      	adds	r6, #24
    4162:	f109 0901 	add.w	r9, r9, #1
    4166:	2d00      	cmp	r5, #0
    4168:	f47f af53 	bne.w	4012 <getTrngSource+0x6e>
    416c:	f5bb 7f04 	cmp.w	fp, #528	; 0x210
    4170:	d85d      	bhi.n	422e <getTrngSource+0x28a>
    4172:	9d03      	ldr	r5, [sp, #12]
    4174:	4659      	mov	r1, fp
    4176:	4628      	mov	r0, r5
    4178:	6962      	ldr	r2, [r4, #20]
    417a:	f7ff fe81 	bl	3e80 <LLF_RND_RepetitionCounterTest.part.0>
    417e:	2800      	cmp	r0, #0
    4180:	d04b      	beq.n	421a <getTrngSource+0x276>
    4182:	2300      	movs	r3, #0
    4184:	9a16      	ldr	r2, [sp, #88]	; 0x58
    4186:	6013      	str	r3, [r2, #0]
    4188:	4b2d      	ldr	r3, [pc, #180]	; (4240 <getTrngSource+0x29c>)
    418a:	4298      	cmp	r0, r3
    418c:	f43f af59 	beq.w	4042 <getTrngSource+0x9e>
    4190:	9d04      	ldr	r5, [sp, #16]
    4192:	2d08      	cmp	r5, #8
    4194:	d034      	beq.n	4200 <getTrngSource+0x25c>
    4196:	2200      	movs	r2, #0
    4198:	ab04      	add	r3, sp, #16
    419a:	4621      	mov	r1, r4
    419c:	4640      	mov	r0, r8
    419e:	006d      	lsls	r5, r5, #1
    41a0:	9200      	str	r2, [sp, #0]
    41a2:	9504      	str	r5, [sp, #16]
    41a4:	f7ff fdc2 	bl	3d2c <startTrngHW>
    41a8:	4b2f      	ldr	r3, [pc, #188]	; (4268 <getTrngSource+0x2c4>)
    41aa:	4298      	cmp	r0, r3
    41ac:	d024      	beq.n	41f8 <getTrngSource+0x254>
    41ae:	2800      	cmp	r0, #0
    41b0:	f47f af47 	bne.w	4042 <getTrngSource+0x9e>
    41b4:	f8d8 2000 	ldr.w	r2, [r8]
    41b8:	0a13      	lsrs	r3, r2, #8
    41ba:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
    41be:	4313      	orrs	r3, r2
    41c0:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    41c4:	f8c8 3000 	str.w	r3, [r8]
    41c8:	9b02      	ldr	r3, [sp, #8]
    41ca:	3b01      	subs	r3, #1
    41cc:	9302      	str	r3, [sp, #8]
    41ce:	f47f af15 	bne.w	3ffc <getTrngSource+0x58>
    41d2:	2000      	movs	r0, #0
    41d4:	e735      	b.n	4042 <getTrngSource+0x9e>
    41d6:	4630      	mov	r0, r6
    41d8:	4652      	mov	r2, sl
    41da:	a906      	add	r1, sp, #24
    41dc:	f7ff f9d8 	bl	3590 <CC_PalMemCopyPlat>
    41e0:	eba5 050a 	sub.w	r5, r5, sl
    41e4:	4456      	add	r6, sl
    41e6:	e7bc      	b.n	4162 <getTrngSource+0x1be>
    41e8:	481f      	ldr	r0, [pc, #124]	; (4268 <getTrngSource+0x2c4>)
    41ea:	e726      	b.n	403a <getTrngSource+0x96>
    41ec:	481f      	ldr	r0, [pc, #124]	; (426c <getTrngSource+0x2c8>)
    41ee:	e724      	b.n	403a <getTrngSource+0x96>
    41f0:	2703      	movs	r7, #3
    41f2:	e74c      	b.n	408e <getTrngSource+0xea>
    41f4:	2702      	movs	r7, #2
    41f6:	e74a      	b.n	408e <getTrngSource+0xea>
    41f8:	6a23      	ldr	r3, [r4, #32]
    41fa:	2b00      	cmp	r3, #0
    41fc:	f43f af21 	beq.w	4042 <getTrngSource+0x9e>
    4200:	481b      	ldr	r0, [pc, #108]	; (4270 <getTrngSource+0x2cc>)
    4202:	e71e      	b.n	4042 <getTrngSource+0x9e>
    4204:	2201      	movs	r2, #1
    4206:	4621      	mov	r1, r4
    4208:	4638      	mov	r0, r7
    420a:	9600      	str	r6, [sp, #0]
    420c:	ab04      	add	r3, sp, #16
    420e:	f7ff fd8d 	bl	3d2c <startTrngHW>
    4212:	2800      	cmp	r0, #0
    4214:	f43f aee3 	beq.w	3fde <getTrngSource+0x3a>
    4218:	e713      	b.n	4042 <getTrngSource+0x9e>
    421a:	f44f 6380 	mov.w	r3, #1024	; 0x400
    421e:	4659      	mov	r1, fp
    4220:	4628      	mov	r0, r5
    4222:	69a2      	ldr	r2, [r4, #24]
    4224:	f7ff fe58 	bl	3ed8 <LLF_RND_AdaptiveProportionTest>
    4228:	2800      	cmp	r0, #0
    422a:	d1aa      	bne.n	4182 <getTrngSource+0x1de>
    422c:	e7d1      	b.n	41d2 <getTrngSource+0x22e>
    422e:	9b16      	ldr	r3, [sp, #88]	; 0x58
    4230:	601d      	str	r5, [r3, #0]
    4232:	e7ad      	b.n	4190 <getTrngSource+0x1ec>
    4234:	50841138 	.word	0x50841138
    4238:	50841130 	.word	0x50841130
    423c:	aaaaaaab 	.word	0xaaaaaaab
    4240:	00f10c02 	.word	0x00f10c02
    4244:	00f10c30 	.word	0x00f10c30
    4248:	508411c4 	.word	0x508411c4
    424c:	5084112c 	.word	0x5084112c
    4250:	0ffffffe 	.word	0x0ffffffe
    4254:	50841100 	.word	0x50841100
    4258:	5084110c 	.word	0x5084110c
    425c:	50841a04 	.word	0x50841a04
    4260:	508411d8 	.word	0x508411d8
    4264:	50841114 	.word	0x50841114
    4268:	00f10c31 	.word	0x00f10c31
    426c:	00f10c35 	.word	0x00f10c35
    4270:	00f10c32 	.word	0x00f10c32

00004274 <LLF_RND_GetTrngSource>:
    4274:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4278:	4e1f      	ldr	r6, [pc, #124]	; (42f8 <LLF_RND_GetTrngSource+0x84>)
    427a:	b084      	sub	sp, #16
    427c:	4604      	mov	r4, r0
    427e:	460d      	mov	r5, r1
    4280:	6830      	ldr	r0, [r6, #0]
    4282:	f04f 31ff 	mov.w	r1, #4294967295
    4286:	4690      	mov	r8, r2
    4288:	9f0c      	ldr	r7, [sp, #48]	; 0x30
    428a:	f7ff f9e7 	bl	365c <CC_PalMutexLock>
    428e:	b9d8      	cbnz	r0, 42c8 <LLF_RND_GetTrngSource+0x54>
    4290:	2000      	movs	r0, #0
    4292:	f7ff fa13 	bl	36bc <CC_PalPowerSaveModeSelect>
    4296:	b9f8      	cbnz	r0, 42d8 <LLF_RND_GetTrngSource+0x64>
    4298:	2300      	movs	r3, #0
    429a:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    429c:	4620      	mov	r0, r4
    429e:	9200      	str	r2, [sp, #0]
    42a0:	9302      	str	r3, [sp, #8]
    42a2:	4642      	mov	r2, r8
    42a4:	4629      	mov	r1, r5
    42a6:	9b0a      	ldr	r3, [sp, #40]	; 0x28
    42a8:	9701      	str	r7, [sp, #4]
    42aa:	f7ff fe7b 	bl	3fa4 <getTrngSource>
    42ae:	4604      	mov	r4, r0
    42b0:	2001      	movs	r0, #1
    42b2:	f7ff fa03 	bl	36bc <CC_PalPowerSaveModeSelect>
    42b6:	b9d0      	cbnz	r0, 42ee <LLF_RND_GetTrngSource+0x7a>
    42b8:	6830      	ldr	r0, [r6, #0]
    42ba:	f7ff f9d7 	bl	366c <CC_PalMutexUnlock>
    42be:	b978      	cbnz	r0, 42e0 <LLF_RND_GetTrngSource+0x6c>
    42c0:	4620      	mov	r0, r4
    42c2:	b004      	add	sp, #16
    42c4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    42c8:	480c      	ldr	r0, [pc, #48]	; (42fc <LLF_RND_GetTrngSource+0x88>)
    42ca:	f7ff fb5f 	bl	398c <CC_PalAbort>
    42ce:	2000      	movs	r0, #0
    42d0:	f7ff f9f4 	bl	36bc <CC_PalPowerSaveModeSelect>
    42d4:	2800      	cmp	r0, #0
    42d6:	d0df      	beq.n	4298 <LLF_RND_GetTrngSource+0x24>
    42d8:	4809      	ldr	r0, [pc, #36]	; (4300 <LLF_RND_GetTrngSource+0x8c>)
    42da:	f7ff fb57 	bl	398c <CC_PalAbort>
    42de:	e7db      	b.n	4298 <LLF_RND_GetTrngSource+0x24>
    42e0:	4808      	ldr	r0, [pc, #32]	; (4304 <LLF_RND_GetTrngSource+0x90>)
    42e2:	f7ff fb53 	bl	398c <CC_PalAbort>
    42e6:	4620      	mov	r0, r4
    42e8:	b004      	add	sp, #16
    42ea:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    42ee:	4806      	ldr	r0, [pc, #24]	; (4308 <LLF_RND_GetTrngSource+0x94>)
    42f0:	f7ff fb4c 	bl	398c <CC_PalAbort>
    42f4:	e7e0      	b.n	42b8 <LLF_RND_GetTrngSource+0x44>
    42f6:	bf00      	nop
    42f8:	2000006c 	.word	0x2000006c
    42fc:	00005374 	.word	0x00005374
    4300:	000053a4 	.word	0x000053a4
    4304:	0000538c 	.word	0x0000538c
    4308:	000053c4 	.word	0x000053c4

0000430c <LLF_RND_RunTrngStartupTest>:
    430c:	b510      	push	{r4, lr}
    430e:	2401      	movs	r4, #1
    4310:	b086      	sub	sp, #24
    4312:	ab05      	add	r3, sp, #20
    4314:	e9cd 2401 	strd	r2, r4, [sp, #4]
    4318:	9300      	str	r3, [sp, #0]
    431a:	2200      	movs	r2, #0
    431c:	ab04      	add	r3, sp, #16
    431e:	f7ff fe41 	bl	3fa4 <getTrngSource>
    4322:	b006      	add	sp, #24
    4324:	bd10      	pop	{r4, pc}
    4326:	bf00      	nop

00004328 <LLF_RND_WaitRngInterrupt>:
    4328:	4601      	mov	r1, r0
    432a:	b508      	push	{r3, lr}
    432c:	f44f 6080 	mov.w	r0, #1024	; 0x400
    4330:	f7ff fa1e 	bl	3770 <CC_HalWaitInterruptRND>
    4334:	2300      	movs	r3, #0
    4336:	4902      	ldr	r1, [pc, #8]	; (4340 <LLF_RND_WaitRngInterrupt+0x18>)
    4338:	4a02      	ldr	r2, [pc, #8]	; (4344 <LLF_RND_WaitRngInterrupt+0x1c>)
    433a:	600b      	str	r3, [r1, #0]
    433c:	6013      	str	r3, [r2, #0]
    433e:	bd08      	pop	{r3, pc}
    4340:	508411c8 	.word	0x508411c8
    4344:	5084112c 	.word	0x5084112c

00004348 <LLF_RND_GetRoscSampleCnt>:
    4348:	3801      	subs	r0, #1
    434a:	2807      	cmp	r0, #7
    434c:	d805      	bhi.n	435a <LLF_RND_GetRoscSampleCnt+0x12>
    434e:	e8df f000 	tbb	[pc, r0]
    4352:	0e0a      	.short	0x0e0a
    4354:	04041204 	.word	0x04041204
    4358:	0604      	.short	0x0604
    435a:	4809      	ldr	r0, [pc, #36]	; (4380 <LLF_RND_GetRoscSampleCnt+0x38>)
    435c:	4770      	bx	lr
    435e:	68cb      	ldr	r3, [r1, #12]
    4360:	2000      	movs	r0, #0
    4362:	624b      	str	r3, [r1, #36]	; 0x24
    4364:	4770      	bx	lr
    4366:	680b      	ldr	r3, [r1, #0]
    4368:	2000      	movs	r0, #0
    436a:	624b      	str	r3, [r1, #36]	; 0x24
    436c:	4770      	bx	lr
    436e:	684b      	ldr	r3, [r1, #4]
    4370:	2000      	movs	r0, #0
    4372:	624b      	str	r3, [r1, #36]	; 0x24
    4374:	4770      	bx	lr
    4376:	688b      	ldr	r3, [r1, #8]
    4378:	2000      	movs	r0, #0
    437a:	624b      	str	r3, [r1, #36]	; 0x24
    437c:	4770      	bx	lr
    437e:	bf00      	nop
    4380:	00f10c31 	.word	0x00f10c31

00004384 <LLF_RND_GetFastestRosc>:
    4384:	680b      	ldr	r3, [r1, #0]
    4386:	e002      	b.n	438e <LLF_RND_GetFastestRosc+0xa>
    4388:	2b08      	cmp	r3, #8
    438a:	600b      	str	r3, [r1, #0]
    438c:	d806      	bhi.n	439c <LLF_RND_GetFastestRosc+0x18>
    438e:	6a02      	ldr	r2, [r0, #32]
    4390:	4213      	tst	r3, r2
    4392:	ea4f 0343 	mov.w	r3, r3, lsl #1
    4396:	d0f7      	beq.n	4388 <LLF_RND_GetFastestRosc+0x4>
    4398:	2000      	movs	r0, #0
    439a:	4770      	bx	lr
    439c:	4800      	ldr	r0, [pc, #0]	; (43a0 <LLF_RND_GetFastestRosc+0x1c>)
    439e:	4770      	bx	lr
    43a0:	00f10c31 	.word	0x00f10c31

000043a4 <LLF_RND_TurnOffTrng>:
    43a4:	2300      	movs	r3, #0
    43a6:	4904      	ldr	r1, [pc, #16]	; (43b8 <LLF_RND_TurnOffTrng+0x14>)
    43a8:	4a04      	ldr	r2, [pc, #16]	; (43bc <LLF_RND_TurnOffTrng+0x18>)
    43aa:	600b      	str	r3, [r1, #0]
    43ac:	f44f 6080 	mov.w	r0, #1024	; 0x400
    43b0:	6013      	str	r3, [r2, #0]
    43b2:	f7ff b9c9 	b.w	3748 <CC_HalClearInterruptBit>
    43b6:	bf00      	nop
    43b8:	5084112c 	.word	0x5084112c
    43bc:	508411c4 	.word	0x508411c4

000043c0 <main>:
 *  0 kB  |---------------------|
 */


void main(void)
{
    43c0:	b508      	push	{r3, lr}
	spm_config();
    43c2:	f7fc ff17 	bl	11f4 <spm_config>
	spm_jump();
}
    43c6:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	spm_jump();
    43ca:	f7fc bea9 	b.w	1120 <spm_jump>

000043ce <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    43ce:	b160      	cbz	r0, 43ea <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    43d0:	6843      	ldr	r3, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    43d2:	f003 0303 	and.w	r3, r3, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    43d6:	2b01      	cmp	r3, #1
    43d8:	d003      	beq.n	43e2 <sys_notify_validate+0x14>
    43da:	2b03      	cmp	r3, #3
    43dc:	d105      	bne.n	43ea <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    43de:	6803      	ldr	r3, [r0, #0]
    43e0:	b11b      	cbz	r3, 43ea <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    43e2:	2300      	movs	r3, #0
    43e4:	6083      	str	r3, [r0, #8]
    43e6:	4618      	mov	r0, r3
    43e8:	4770      	bx	lr
		return -EINVAL;
    43ea:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    43ee:	4770      	bx	lr

000043f0 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    43f0:	2200      	movs	r2, #0
    43f2:	6843      	ldr	r3, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    43f4:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    43f6:	f003 0303 	and.w	r3, r3, #3
	switch (method) {
    43fa:	2b03      	cmp	r3, #3
	sys_notify_generic_callback rv = 0;
    43fc:	bf14      	ite	ne
    43fe:	4613      	movne	r3, r2
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    4400:	6803      	ldreq	r3, [r0, #0]
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    4402:	6042      	str	r2, [r0, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    4404:	4618      	mov	r0, r3
    4406:	4770      	bx	lr

00004408 <arch_printk_char_out>:
}
    4408:	2000      	movs	r0, #0
    440a:	4770      	bx	lr

0000440c <printk>:
 * @param fmt formatted string to output
 *
 * @return N/A
 */
void printk(const char *fmt, ...)
{
    440c:	b40f      	push	{r0, r1, r2, r3}
    440e:	b507      	push	{r0, r1, r2, lr}
    4410:	a904      	add	r1, sp, #16
    4412:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    4416:	9101      	str	r1, [sp, #4]

	if (IS_ENABLED(CONFIG_LOG_PRINTK)) {
		log_printk(fmt, ap);
	} else {
		vprintk(fmt, ap);
    4418:	f7fc fa42 	bl	8a0 <vprintk>
	}
	va_end(ap);
}
    441c:	b003      	add	sp, #12
    441e:	f85d eb04 	ldr.w	lr, [sp], #4
    4422:	b004      	add	sp, #16
    4424:	4770      	bx	lr

00004426 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    4426:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    4428:	f013 0307 	ands.w	r3, r3, #7
    442c:	d105      	bne.n	443a <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    442e:	6803      	ldr	r3, [r0, #0]
    4430:	2b00      	cmp	r3, #0
		evt = EVT_START;
    4432:	bf0c      	ite	eq
    4434:	2000      	moveq	r0, #0
    4436:	2003      	movne	r0, #3
    4438:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    443a:	2b02      	cmp	r3, #2
    443c:	d105      	bne.n	444a <process_recheck+0x24>
		   && (mgr->refs == 0)) {
    443e:	8b43      	ldrh	r3, [r0, #26]
    4440:	2b00      	cmp	r3, #0
		evt = EVT_STOP;
    4442:	bf14      	ite	ne
    4444:	2000      	movne	r0, #0
    4446:	2004      	moveq	r0, #4
    4448:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    444a:	2b01      	cmp	r3, #1
    444c:	d105      	bne.n	445a <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    444e:	6803      	ldr	r3, [r0, #0]
    4450:	2b00      	cmp	r3, #0
		evt = EVT_RESET;
    4452:	bf0c      	ite	eq
    4454:	2000      	moveq	r0, #0
    4456:	2005      	movne	r0, #5
    4458:	4770      	bx	lr
	int evt = EVT_NOP;
    445a:	2000      	movs	r0, #0
}
    445c:	4770      	bx	lr

0000445e <notify_one>:
{
    445e:	b573      	push	{r0, r1, r4, r5, r6, lr}
    4460:	460d      	mov	r5, r1
    4462:	4606      	mov	r6, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    4464:	4619      	mov	r1, r3
    4466:	1d28      	adds	r0, r5, #4
{
    4468:	9201      	str	r2, [sp, #4]
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    446a:	9300      	str	r3, [sp, #0]
    446c:	f7ff ffc0 	bl	43f0 <sys_notify_finalize>
	if (cb) {
    4470:	4604      	mov	r4, r0
    4472:	b140      	cbz	r0, 4486 <notify_one+0x28>
		cb(mgr, cli, state, res);
    4474:	e9dd 3200 	ldrd	r3, r2, [sp]
    4478:	4629      	mov	r1, r5
    447a:	4630      	mov	r0, r6
    447c:	46a4      	mov	ip, r4
}
    447e:	b002      	add	sp, #8
    4480:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		cb(mgr, cli, state, res);
    4484:	4760      	bx	ip
}
    4486:	b002      	add	sp, #8
    4488:	bd70      	pop	{r4, r5, r6, pc}

0000448a <transition_complete>:
{
    448a:	b410      	push	{r4}
	__asm__ volatile(
    448c:	f04f 0420 	mov.w	r4, #32
    4490:	f3ef 8211 	mrs	r2, BASEPRI
    4494:	f384 8811 	msr	BASEPRI, r4
    4498:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    449c:	6141      	str	r1, [r0, #20]
}
    449e:	f85d 4b04 	ldr.w	r4, [sp], #4
	process_event(mgr, EVT_COMPLETE, key);
    44a2:	2101      	movs	r1, #1
    44a4:	f7fc ba0a 	b.w	8bc <process_event>

000044a8 <validate_args>:
{
    44a8:	b510      	push	{r4, lr}
    44aa:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    44ac:	b140      	cbz	r0, 44c0 <validate_args+0x18>
    44ae:	b139      	cbz	r1, 44c0 <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
    44b0:	1d08      	adds	r0, r1, #4
    44b2:	f7ff ff8c 	bl	43ce <sys_notify_validate>
	if ((rv == 0)
    44b6:	b928      	cbnz	r0, 44c4 <validate_args+0x1c>
	    && ((cli->notify.flags
    44b8:	68a3      	ldr	r3, [r4, #8]
    44ba:	f033 0303 	bics.w	r3, r3, #3
    44be:	d001      	beq.n	44c4 <validate_args+0x1c>
		rv = -EINVAL;
    44c0:	f06f 0015 	mvn.w	r0, #21
}
    44c4:	bd10      	pop	{r4, pc}

000044c6 <onoff_manager_init>:
{
    44c6:	b538      	push	{r3, r4, r5, lr}
    44c8:	460c      	mov	r4, r1
	if ((mgr == NULL)
    44ca:	4605      	mov	r5, r0
    44cc:	b158      	cbz	r0, 44e6 <onoff_manager_init+0x20>
	    || (transitions == NULL)
    44ce:	b151      	cbz	r1, 44e6 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    44d0:	680b      	ldr	r3, [r1, #0]
    44d2:	b143      	cbz	r3, 44e6 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    44d4:	684b      	ldr	r3, [r1, #4]
    44d6:	b133      	cbz	r3, 44e6 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    44d8:	221c      	movs	r2, #28
    44da:	2100      	movs	r1, #0
    44dc:	f000 faec 	bl	4ab8 <memset>
	return 0;
    44e0:	2000      	movs	r0, #0
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    44e2:	612c      	str	r4, [r5, #16]
}
    44e4:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    44e6:	f06f 0015 	mvn.w	r0, #21
    44ea:	e7fb      	b.n	44e4 <onoff_manager_init+0x1e>

000044ec <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    44ec:	b570      	push	{r4, r5, r6, lr}
    44ee:	4604      	mov	r4, r0
    44f0:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    44f2:	f7ff ffd9 	bl	44a8 <validate_args>

	if (rv < 0) {
    44f6:	1e05      	subs	r5, r0, #0
    44f8:	db31      	blt.n	455e <onoff_request+0x72>
    44fa:	f04f 0320 	mov.w	r3, #32
    44fe:	f3ef 8111 	mrs	r1, BASEPRI
    4502:	f383 8811 	msr	BASEPRI, r3
    4506:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    450a:	f64f 75ff 	movw	r5, #65535	; 0xffff
    450e:	8b63      	ldrh	r3, [r4, #26]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    4510:	8b20      	ldrh	r0, [r4, #24]
	if (mgr->refs == SERVICE_REFS_MAX) {
    4512:	42ab      	cmp	r3, r5
    4514:	f000 0207 	and.w	r2, r0, #7
    4518:	d02e      	beq.n	4578 <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
    451a:	2a02      	cmp	r2, #2
    451c:	d10e      	bne.n	453c <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
    451e:	3301      	adds	r3, #1
    4520:	8363      	strh	r3, [r4, #26]
	rv = state;
    4522:	4615      	mov	r5, r2
		notify = true;
    4524:	2301      	movs	r3, #1
	__asm__ volatile(
    4526:	f381 8811 	msr	BASEPRI, r1
    452a:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    452e:	b1b3      	cbz	r3, 455e <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
    4530:	2300      	movs	r3, #0
    4532:	4631      	mov	r1, r6
    4534:	4620      	mov	r0, r4
    4536:	f7ff ff92 	bl	445e <notify_one>
    453a:	e010      	b.n	455e <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
    453c:	0783      	lsls	r3, r0, #30
    453e:	d001      	beq.n	4544 <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
    4540:	2a06      	cmp	r2, #6
    4542:	d10e      	bne.n	4562 <onoff_request+0x76>
	parent->next = child;
    4544:	2300      	movs	r3, #0
    4546:	6033      	str	r3, [r6, #0]
Z_GENLIST_APPEND(slist, snode)
    4548:	6863      	ldr	r3, [r4, #4]
    454a:	b993      	cbnz	r3, 4572 <onoff_request+0x86>
	list->head = node;
    454c:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
    4550:	4615      	mov	r5, r2
    4552:	b962      	cbnz	r2, 456e <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
    4554:	460a      	mov	r2, r1
    4556:	4620      	mov	r0, r4
    4558:	2102      	movs	r1, #2
    455a:	f7fc f9af 	bl	8bc <process_event>
		}
	}

	return rv;
}
    455e:	4628      	mov	r0, r5
    4560:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
    4562:	2a05      	cmp	r2, #5
    4564:	bf0c      	ite	eq
    4566:	f06f 0522 	mvneq.w	r5, #34	; 0x22
    456a:	f06f 0504 	mvnne.w	r5, #4
    456e:	2300      	movs	r3, #0
    4570:	e7d9      	b.n	4526 <onoff_request+0x3a>
	parent->next = child;
    4572:	601e      	str	r6, [r3, #0]
	list->tail = node;
    4574:	6066      	str	r6, [r4, #4]
}
    4576:	e7eb      	b.n	4550 <onoff_request+0x64>
		rv = -EAGAIN;
    4578:	f06f 050a 	mvn.w	r5, #10
    457c:	e7f7      	b.n	456e <onoff_request+0x82>

0000457e <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    457e:	4604      	mov	r4, r0
    4580:	b508      	push	{r3, lr}
    4582:	4608      	mov	r0, r1
    4584:	4611      	mov	r1, r2
	entry(p1, p2, p3);
    4586:	461a      	mov	r2, r3
    4588:	47a0      	blx	r4
	return z_impl_k_current_get();
    458a:	f7fe fdb9 	bl	3100 <z_impl_k_current_get>
	z_impl_k_thread_abort(thread);
    458e:	f7fd fab5 	bl	1afc <z_impl_k_thread_abort>

00004592 <chunk_field>:
				 enum chunk_fields f)
{
	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];

	if (big_heap(h)) {
    4592:	6883      	ldr	r3, [r0, #8]
	void *cmem = &buf[c];
    4594:	eb00 01c1 	add.w	r1, r0, r1, lsl #3
	if (big_heap(h)) {
    4598:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
		return ((uint32_t *)cmem)[f];
    459c:	bf2c      	ite	cs
    459e:	f851 0022 	ldrcs.w	r0, [r1, r2, lsl #2]
	} else {
		return ((uint16_t *)cmem)[f];
    45a2:	f831 0012 	ldrhcc.w	r0, [r1, r2, lsl #1]
	}
}
    45a6:	4770      	bx	lr

000045a8 <chunk_set>:
			     enum chunk_fields f, chunkid_t val)
{
	CHECK(c <= h->len);

	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];
    45a8:	eb00 01c1 	add.w	r1, r0, r1, lsl #3

	if (big_heap(h)) {
    45ac:	6880      	ldr	r0, [r0, #8]
    45ae:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
		CHECK(val == (uint32_t)val);
		((uint32_t *)cmem)[f] = val;
    45b2:	bf2c      	ite	cs
    45b4:	f841 3022 	strcs.w	r3, [r1, r2, lsl #2]
	} else {
		CHECK(val == (uint16_t)val);
		((uint16_t *)cmem)[f] = val;
    45b8:	f821 3012 	strhcc.w	r3, [r1, r2, lsl #1]
	}
}
    45bc:	4770      	bx	lr

000045be <chunk_size>:
	return chunk_field(h, c, SIZE_AND_USED) & 1;
}

static inline size_t chunk_size(struct z_heap *h, chunkid_t c)
{
	return chunk_field(h, c, SIZE_AND_USED) >> 1;
    45be:	2201      	movs	r2, #1
{
    45c0:	b508      	push	{r3, lr}
	return chunk_field(h, c, SIZE_AND_USED) >> 1;
    45c2:	f7ff ffe6 	bl	4592 <chunk_field>
}
    45c6:	0840      	lsrs	r0, r0, #1
    45c8:	bd08      	pop	{r3, pc}

000045ca <set_chunk_used>:
static inline void set_chunk_used(struct z_heap *h, chunkid_t c, bool used)
{
	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];

	if (big_heap(h)) {
    45ca:	6883      	ldr	r3, [r0, #8]
	void *cmem = &buf[c];
    45cc:	eb00 01c1 	add.w	r1, r0, r1, lsl #3
	if (big_heap(h)) {
    45d0:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
    45d4:	d308      	bcc.n	45e8 <set_chunk_used+0x1e>
		if (used) {
    45d6:	684b      	ldr	r3, [r1, #4]
    45d8:	b11a      	cbz	r2, 45e2 <set_chunk_used+0x18>
			((uint32_t *)cmem)[SIZE_AND_USED] |= 1;
    45da:	f043 0301 	orr.w	r3, r3, #1
		} else {
			((uint32_t *)cmem)[SIZE_AND_USED] &= ~1;
    45de:	604b      	str	r3, [r1, #4]
    45e0:	4770      	bx	lr
    45e2:	f023 0301 	bic.w	r3, r3, #1
    45e6:	e7fa      	b.n	45de <set_chunk_used+0x14>
		}
	} else {
		if (used) {
    45e8:	884b      	ldrh	r3, [r1, #2]
    45ea:	b11a      	cbz	r2, 45f4 <set_chunk_used+0x2a>
			((uint16_t *)cmem)[SIZE_AND_USED] |= 1;
    45ec:	f043 0301 	orr.w	r3, r3, #1
		} else {
			((uint16_t *)cmem)[SIZE_AND_USED] &= ~1;
    45f0:	804b      	strh	r3, [r1, #2]
		}
	}
}
    45f2:	4770      	bx	lr
			((uint16_t *)cmem)[SIZE_AND_USED] &= ~1;
    45f4:	f023 0301 	bic.w	r3, r3, #1
    45f8:	e7fa      	b.n	45f0 <set_chunk_used+0x26>

000045fa <set_chunk_size>:
 * when its size is modified, and potential set_chunk_used() is always
 * invoked after set_chunk_size().
 */
static inline void set_chunk_size(struct z_heap *h, chunkid_t c, size_t size)
{
	chunk_set(h, c, SIZE_AND_USED, size << 1);
    45fa:	0053      	lsls	r3, r2, #1
    45fc:	2201      	movs	r2, #1
    45fe:	f7ff bfd3 	b.w	45a8 <chunk_set>

00004602 <bucket_idx>:
	return big_heap(h) && chunk_size(h, c) == 1;
}

static inline size_t chunk_header_bytes(struct z_heap *h)
{
	return big_heap(h) ? 8 : 4;
    4602:	6880      	ldr	r0, [r0, #8]
	return bytes_to_chunksz(h, 1);
}

static inline int bucket_idx(struct z_heap *h, size_t sz)
{
	size_t usable_sz = sz - min_chunk_size(h) + 1;
    4604:	3101      	adds	r1, #1
	return (bytes + CHUNK_UNIT - 1) / CHUNK_UNIT;
    4606:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
    460a:	bf2c      	ite	cs
    460c:	2002      	movcs	r0, #2
    460e:	2001      	movcc	r0, #1
	size_t usable_sz = sz - min_chunk_size(h) + 1;
    4610:	1a08      	subs	r0, r1, r0
	return 31 - __builtin_clz(usable_sz);
    4612:	fab0 f080 	clz	r0, r0
}
    4616:	f1c0 001f 	rsb	r0, r0, #31
    461a:	4770      	bx	lr

0000461c <free_list_add>:
		set_prev_free_chunk(h, second, c);
	}
}

static void free_list_add(struct z_heap *h, chunkid_t c)
{
    461c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4620:	4604      	mov	r4, r0
    4622:	460d      	mov	r5, r1
	return sizeof(void *) > 4 || chunks > 0x7fff;
    4624:	f7ff ffcb 	bl	45be <chunk_size>
	return big_heap(h) && chunk_size(h, c) == 1;
    4628:	68a3      	ldr	r3, [r4, #8]
    462a:	4601      	mov	r1, r0
    462c:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
    4630:	d301      	bcc.n	4636 <free_list_add+0x1a>
	if (!solo_free_header(h, c)) {
    4632:	2801      	cmp	r0, #1
    4634:	d035      	beq.n	46a2 <free_list_add+0x86>
		int bidx = bucket_idx(h, chunk_size(h, c));
    4636:	4620      	mov	r0, r4
    4638:	f7ff ffe3 	bl	4602 <bucket_idx>
	if (b->next == 0) {
    463c:	eb04 0280 	add.w	r2, r4, r0, lsl #2
    4640:	6916      	ldr	r6, [r2, #16]
    4642:	b99e      	cbnz	r6, 466c <free_list_add+0x50>
		h->avail_buckets |= (1 << bidx);
    4644:	2301      	movs	r3, #1
    4646:	fa03 f000 	lsl.w	r0, r3, r0
    464a:	68e3      	ldr	r3, [r4, #12]
	chunk_set(h, c, FREE_PREV, prev);
    464c:	4629      	mov	r1, r5
    464e:	4303      	orrs	r3, r0
    4650:	60e3      	str	r3, [r4, #12]
    4652:	4620      	mov	r0, r4
		b->next = c;
    4654:	6115      	str	r5, [r2, #16]
    4656:	462b      	mov	r3, r5
    4658:	2202      	movs	r2, #2
    465a:	f7ff ffa5 	bl	45a8 <chunk_set>
	chunk_set(h, c, FREE_NEXT, next);
    465e:	2203      	movs	r2, #3
    4660:	4629      	mov	r1, r5
	chunk_set(h, c, FREE_PREV, prev);
    4662:	4620      	mov	r0, r4
		free_list_add_bidx(h, c, bidx);
	}
}
    4664:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    4668:	f7ff bf9e 	b.w	45a8 <chunk_set>
	return chunk_field(h, c, FREE_PREV);
    466c:	2202      	movs	r2, #2
    466e:	4631      	mov	r1, r6
    4670:	4620      	mov	r0, r4
    4672:	f7ff ff8e 	bl	4592 <chunk_field>
    4676:	4607      	mov	r7, r0
	chunk_set(h, c, FREE_PREV, prev);
    4678:	4603      	mov	r3, r0
    467a:	2202      	movs	r2, #2
    467c:	4629      	mov	r1, r5
    467e:	4620      	mov	r0, r4
    4680:	f7ff ff92 	bl	45a8 <chunk_set>
	chunk_set(h, c, FREE_NEXT, next);
    4684:	4633      	mov	r3, r6
    4686:	2203      	movs	r2, #3
    4688:	4629      	mov	r1, r5
    468a:	4620      	mov	r0, r4
    468c:	f7ff ff8c 	bl	45a8 <chunk_set>
    4690:	2203      	movs	r2, #3
    4692:	4639      	mov	r1, r7
    4694:	462b      	mov	r3, r5
    4696:	4620      	mov	r0, r4
    4698:	f7ff ff86 	bl	45a8 <chunk_set>
	chunk_set(h, c, FREE_PREV, prev);
    469c:	2202      	movs	r2, #2
    469e:	4631      	mov	r1, r6
    46a0:	e7df      	b.n	4662 <free_list_add+0x46>
    46a2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

000046a6 <sys_heap_init>:
	return big_heap_bytes(size) ? 8 : 4;
    46a6:	f5b2 2f80 	cmp.w	r2, #262144	; 0x40000
	set_chunk_used(h, c, true);
	return mem;
}

void sys_heap_init(struct sys_heap *heap, void *mem, size_t bytes)
{
    46aa:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    46ac:	bf2c      	ite	cs
    46ae:	2508      	movcs	r5, #8
    46b0:	2504      	movcc	r5, #4
	CHECK(end > addr);
	__ASSERT(buf_sz > chunksz(sizeof(struct z_heap)), "heap size is too small");

	struct z_heap *h = (struct z_heap *)addr;
	heap->heap = h;
	h->chunk0_hdr_area = 0;
    46b2:	2300      	movs	r3, #0
	bytes -= heap_footer_bytes(bytes);
    46b4:	1b55      	subs	r5, r2, r5
	h->chunk0_hdr_area = 0;
    46b6:	2200      	movs	r2, #0
	uintptr_t addr = ROUND_UP(mem, CHUNK_UNIT);
    46b8:	1dcc      	adds	r4, r1, #7
    46ba:	f024 0407 	bic.w	r4, r4, #7
	heap->heap = h;
    46be:	6004      	str	r4, [r0, #0]
	h->chunk0_hdr_area = 0;
    46c0:	e9c4 2300 	strd	r2, r3, [r4]
	h->len = buf_sz;
	h->avail_buckets = 0;
    46c4:	2300      	movs	r3, #0
	uintptr_t end = ROUND_DOWN((uint8_t *)mem + bytes, CHUNK_UNIT);
    46c6:	440d      	add	r5, r1
    46c8:	f025 0507 	bic.w	r5, r5, #7
	size_t buf_sz = (end - addr) / CHUNK_UNIT;
    46cc:	1b2d      	subs	r5, r5, r4
    46ce:	08ed      	lsrs	r5, r5, #3

	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    46d0:	4629      	mov	r1, r5
    46d2:	4620      	mov	r0, r4
	h->len = buf_sz;
    46d4:	60a5      	str	r5, [r4, #8]
	h->avail_buckets = 0;
    46d6:	60e3      	str	r3, [r4, #12]
	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    46d8:	f7ff ff93 	bl	4602 <bucket_idx>
	size_t chunk0_size = chunksz(sizeof(struct z_heap) +
    46dc:	0086      	lsls	r6, r0, #2
	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    46de:	1c41      	adds	r1, r0, #1
				     nb_buckets * sizeof(struct z_heap_bucket));

	__ASSERT(chunk0_size + min_chunk_size(h) < buf_sz, "heap size is too small");

	for (int i = 0; i < nb_buckets; i++) {
		h->buckets[i].next = 0;
    46e0:	4618      	mov	r0, r3
	return (bytes + CHUNK_UNIT - 1) / CHUNK_UNIT;
    46e2:	361b      	adds	r6, #27
    46e4:	08f6      	lsrs	r6, r6, #3
	for (int i = 0; i < nb_buckets; i++) {
    46e6:	f104 0210 	add.w	r2, r4, #16
    46ea:	428b      	cmp	r3, r1
    46ec:	db29      	blt.n	4742 <sys_heap_init+0x9c>
	}

	/* chunk containing our struct z_heap */
	set_chunk_size(h, 0, chunk0_size);
    46ee:	4632      	mov	r2, r6
    46f0:	4620      	mov	r0, r4
    46f2:	2100      	movs	r1, #0
    46f4:	f7ff ff81 	bl	45fa <set_chunk_size>
	set_chunk_used(h, 0, true);

	/* chunk containing the free heap */
	set_chunk_size(h, chunk0_size, buf_sz - chunk0_size);
    46f8:	1baf      	subs	r7, r5, r6
	set_chunk_used(h, 0, true);
    46fa:	4620      	mov	r0, r4
    46fc:	2201      	movs	r2, #1
    46fe:	2100      	movs	r1, #0
    4700:	f7ff ff63 	bl	45ca <set_chunk_used>
	set_chunk_size(h, chunk0_size, buf_sz - chunk0_size);
    4704:	463a      	mov	r2, r7
    4706:	4631      	mov	r1, r6
    4708:	f7ff ff77 	bl	45fa <set_chunk_size>
	chunk_set(h, c, LEFT_SIZE, size);
    470c:	4633      	mov	r3, r6
    470e:	4631      	mov	r1, r6
    4710:	4620      	mov	r0, r4
    4712:	2200      	movs	r2, #0
    4714:	f7ff ff48 	bl	45a8 <chunk_set>
	set_left_chunk_size(h, chunk0_size, chunk0_size);

	/* the end marker chunk */
	set_chunk_size(h, buf_sz, 0);
    4718:	4629      	mov	r1, r5
    471a:	4620      	mov	r0, r4
    471c:	2200      	movs	r2, #0
    471e:	f7ff ff6c 	bl	45fa <set_chunk_size>
    4722:	463b      	mov	r3, r7
    4724:	4629      	mov	r1, r5
    4726:	4620      	mov	r0, r4
    4728:	2200      	movs	r2, #0
    472a:	f7ff ff3d 	bl	45a8 <chunk_set>
	set_left_chunk_size(h, buf_sz, buf_sz - chunk0_size);
	set_chunk_used(h, buf_sz, true);
    472e:	4629      	mov	r1, r5
    4730:	4620      	mov	r0, r4
    4732:	2201      	movs	r2, #1
    4734:	f7ff ff49 	bl	45ca <set_chunk_used>

	free_list_add(h, chunk0_size);
    4738:	4631      	mov	r1, r6
}
    473a:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
	free_list_add(h, chunk0_size);
    473e:	f7ff bf6d 	b.w	461c <free_list_add>
		h->buckets[i].next = 0;
    4742:	f842 0b04 	str.w	r0, [r2], #4
	for (int i = 0; i < nb_buckets; i++) {
    4746:	3301      	adds	r3, #1
    4748:	e7cf      	b.n	46ea <sys_heap_init+0x44>

0000474a <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM(CONFIG_OUTPUT_PRINT_MEMORY_USAGE, 1);
GEN_ABSOLUTE_SYM(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM(CONFIG_REBOOT, 1);
GEN_ABSOLUTE_SYM(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    474a:	4770      	bx	lr

0000474c <z_platform_init>:

void z_platform_init(void)
{
	SystemInit();
    474c:	f7fd bd80 	b.w	2250 <SystemInit>

00004750 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    4750:	b2cb      	uxtb	r3, r1
    4752:	210c      	movs	r1, #12
    4754:	68c2      	ldr	r2, [r0, #12]
    4756:	fb03 2101 	mla	r1, r3, r1, r2
    475a:	6c08      	ldr	r0, [r1, #64]	; 0x40
}
    475c:	f000 0007 	and.w	r0, r0, #7
    4760:	4770      	bx	lr

00004762 <set_off_state>:
	__asm__ volatile(
    4762:	f04f 0320 	mov.w	r3, #32
    4766:	f3ef 8211 	mrs	r2, BASEPRI
    476a:	f383 8811 	msr	BASEPRI, r3
    476e:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    4772:	6803      	ldr	r3, [r0, #0]
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    4774:	f013 03c0 	ands.w	r3, r3, #192	; 0xc0
    4778:	d001      	beq.n	477e <set_off_state+0x1c>
    477a:	428b      	cmp	r3, r1
    477c:	d107      	bne.n	478e <set_off_state+0x2c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    477e:	2301      	movs	r3, #1
    4780:	6003      	str	r3, [r0, #0]
	int err = 0;
    4782:	2000      	movs	r0, #0
	__asm__ volatile(
    4784:	f382 8811 	msr	BASEPRI, r2
    4788:	f3bf 8f6f 	isb	sy
}
    478c:	4770      	bx	lr
		err = -EPERM;
    478e:	f04f 30ff 	mov.w	r0, #4294967295
    4792:	e7f7      	b.n	4784 <set_off_state+0x22>

00004794 <set_starting_state>:
{
    4794:	b510      	push	{r4, lr}
	__asm__ volatile(
    4796:	f04f 0320 	mov.w	r3, #32
    479a:	f3ef 8211 	mrs	r2, BASEPRI
    479e:	f383 8811 	msr	BASEPRI, r3
    47a2:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    47a6:	6803      	ldr	r3, [r0, #0]
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    47a8:	f003 0407 	and.w	r4, r3, #7
    47ac:	2c01      	cmp	r4, #1
    47ae:	d106      	bne.n	47be <set_starting_state+0x2a>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    47b0:	6001      	str	r1, [r0, #0]
	int err = 0;
    47b2:	2000      	movs	r0, #0
	__asm__ volatile(
    47b4:	f382 8811 	msr	BASEPRI, r2
    47b8:	f3bf 8f6f 	isb	sy
}
    47bc:	bd10      	pop	{r4, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    47be:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
	} else if (current_ctx != ctx) {
    47c2:	428b      	cmp	r3, r1
		err = -EBUSY;
    47c4:	bf14      	ite	ne
    47c6:	f04f 30ff 	movne.w	r0, #4294967295
    47ca:	f06f 000f 	mvneq.w	r0, #15
    47ce:	e7f1      	b.n	47b4 <set_starting_state+0x20>

000047d0 <set_on_state>:
	__asm__ volatile(
    47d0:	f04f 0320 	mov.w	r3, #32
    47d4:	f3ef 8211 	mrs	r2, BASEPRI
    47d8:	f383 8811 	msr	BASEPRI, r3
    47dc:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    47e0:	6803      	ldr	r3, [r0, #0]
    47e2:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    47e6:	f043 0302 	orr.w	r3, r3, #2
    47ea:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    47ec:	f382 8811 	msr	BASEPRI, r2
    47f0:	f3bf 8f6f 	isb	sy
}
    47f4:	4770      	bx	lr

000047f6 <onoff_started_callback>:
{
    47f6:	b410      	push	{r4}
	notify(mgr, 0);
    47f8:	241c      	movs	r4, #28
	return &data->mgr[type];
    47fa:	68c0      	ldr	r0, [r0, #12]
    47fc:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    47fe:	fb03 0004 	mla	r0, r3, r4, r0
    4802:	2100      	movs	r1, #0
}
    4804:	f85d 4b04 	ldr.w	r4, [sp], #4
	notify(mgr, 0);
    4808:	4710      	bx	r2

0000480a <blocking_start_callback>:
{
    480a:	4610      	mov	r0, r2
		arch_syscall_invoke1(*(uintptr_t *)&sem, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    480c:	f7fe bc7e 	b.w	310c <z_impl_k_sem_give>

00004810 <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    4810:	2000      	movs	r0, #0
    4812:	f7fd be19 	b.w	2448 <nrfx_clock_stop>

00004816 <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    4816:	2000      	movs	r0, #0
    4818:	f7fd bde4 	b.w	23e4 <nrfx_clock_start>

0000481c <api_stop>:
{
    481c:	b538      	push	{r3, r4, r5, lr}
	err = set_off_state(&subdata->flags, ctx);
    481e:	230c      	movs	r3, #12
    4820:	b2cc      	uxtb	r4, r1
    4822:	4363      	muls	r3, r4
{
    4824:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
    4826:	68c0      	ldr	r0, [r0, #12]
    4828:	3340      	adds	r3, #64	; 0x40
    482a:	2180      	movs	r1, #128	; 0x80
    482c:	4418      	add	r0, r3
    482e:	f7ff ff98 	bl	4762 <set_off_state>
	if (err < 0) {
    4832:	2800      	cmp	r0, #0
    4834:	db05      	blt.n	4842 <api_stop+0x26>
	get_sub_config(dev, type)->stop();
    4836:	6869      	ldr	r1, [r5, #4]
    4838:	eb01 04c4 	add.w	r4, r1, r4, lsl #3
    483c:	6863      	ldr	r3, [r4, #4]
    483e:	4798      	blx	r3
	return 0;
    4840:	2000      	movs	r0, #0
}
    4842:	bd38      	pop	{r3, r4, r5, pc}

00004844 <api_start>:
{
    4844:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	err = set_starting_state(&subdata->flags, ctx);
    4848:	f04f 080c 	mov.w	r8, #12
    484c:	b2cd      	uxtb	r5, r1
    484e:	fb08 f805 	mul.w	r8, r8, r5
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    4852:	68c4      	ldr	r4, [r0, #12]
{
    4854:	4606      	mov	r6, r0
	err = set_starting_state(&subdata->flags, ctx);
    4856:	f108 0040 	add.w	r0, r8, #64	; 0x40
    485a:	2180      	movs	r1, #128	; 0x80
    485c:	4420      	add	r0, r4
{
    485e:	4617      	mov	r7, r2
	err = set_starting_state(&subdata->flags, ctx);
    4860:	f7ff ff98 	bl	4794 <set_starting_state>
	if (err < 0) {
    4864:	2800      	cmp	r0, #0
    4866:	db09      	blt.n	487c <api_start+0x38>
	subdata->cb = data->cb;
    4868:	687b      	ldr	r3, [r7, #4]
    486a:	4444      	add	r4, r8
    486c:	63a3      	str	r3, [r4, #56]	; 0x38
	subdata->user_data = data->user_data;
    486e:	68bb      	ldr	r3, [r7, #8]
    4870:	63e3      	str	r3, [r4, #60]	; 0x3c
	 get_sub_config(dev, type)->start();
    4872:	6873      	ldr	r3, [r6, #4]
    4874:	f853 3035 	ldr.w	r3, [r3, r5, lsl #3]
    4878:	4798      	blx	r3
	return 0;
    487a:	2000      	movs	r0, #0
}
    487c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00004880 <z_clock_isr>:
/* Weak-linked noop defaults for optional driver interfaces: */

void __weak z_clock_isr(void *arg)
{
	__ASSERT_NO_MSG(false);
}
    4880:	4770      	bx	lr

00004882 <z_clock_idle_exit>:
{
}

void __weak z_clock_idle_exit(void)
{
}
    4882:	4770      	bx	lr

00004884 <sys_clock_disable>:
    4884:	4770      	bx	lr

00004886 <spm_secure_services_init>:
	mbedtls_platform_context platform_ctx = {0};
    4886:	2300      	movs	r3, #0
{
    4888:	b507      	push	{r0, r1, r2, lr}
	err = mbedtls_platform_setup(&platform_ctx);
    488a:	a801      	add	r0, sp, #4
	mbedtls_platform_context platform_ctx = {0};
    488c:	f88d 3004 	strb.w	r3, [sp, #4]
	err = mbedtls_platform_setup(&platform_ctx);
    4890:	f7fe ff8c 	bl	37ac <mbedtls_platform_setup>
}
    4894:	b003      	add	sp, #12
    4896:	f85d fb04 	ldr.w	pc, [sp], #4

0000489a <__acle_se_spm_request_random_number_nse>:
	if (len != MBEDTLS_ENTROPY_MAX_GATHER) {
    489a:	2990      	cmp	r1, #144	; 0x90
{
    489c:	b508      	push	{r3, lr}
    489e:	4613      	mov	r3, r2
	if (len != MBEDTLS_ENTROPY_MAX_GATHER) {
    48a0:	d139      	bne.n	4916 <__acle_se_spm_request_random_number_nse+0x7c>
	err = mbedtls_hardware_poll(NULL, output, len, olen);
    48a2:	460a      	mov	r2, r1
    48a4:	4601      	mov	r1, r0
    48a6:	2000      	movs	r0, #0
    48a8:	f7fe ff8c 	bl	37c4 <mbedtls_hardware_poll>
}
    48ac:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    48b0:	4671      	mov	r1, lr
    48b2:	4672      	mov	r2, lr
    48b4:	4673      	mov	r3, lr
    48b6:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    48ba:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    48be:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    48c2:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    48c6:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    48ca:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    48ce:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    48d2:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    48d6:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    48da:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    48de:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    48e2:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    48e6:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    48ea:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    48ee:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    48f2:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    48f6:	f38e 8c00 	msr	CPSR_fs, lr
    48fa:	b410      	push	{r4}
    48fc:	eef1 ca10 	vmrs	ip, fpscr
    4900:	f64f 7460 	movw	r4, #65376	; 0xff60
    4904:	f6c0 74ff 	movt	r4, #4095	; 0xfff
    4908:	ea0c 0c04 	and.w	ip, ip, r4
    490c:	eee1 ca10 	vmsr	fpscr, ip
    4910:	bc10      	pop	{r4}
    4912:	46f4      	mov	ip, lr
    4914:	4774      	bxns	lr
		return -EINVAL;
    4916:	f06f 0015 	mvn.w	r0, #21
    491a:	e7c7      	b.n	48ac <__acle_se_spm_request_random_number_nse+0x12>

0000491c <abort_function>:
	sys_reboot(SYS_REBOOT_WARM);
    491c:	2000      	movs	r0, #0
    491e:	f7fc b8d3 	b.w	ac8 <sys_reboot>

00004922 <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    4922:	2100      	movs	r1, #0
    4924:	2001      	movs	r0, #1
    4926:	f000 b832 	b.w	498e <z_arm_fatal_error>

0000492a <irq_target_state_set>:
irq_target_state_t irq_target_state_set(unsigned int irq,
	irq_target_state_t irq_target_state)
{
	uint32_t result;

	if (irq_target_state == IRQ_TARGET_STATE_SECURE) {
    492a:	b243      	sxtb	r3, r0
    492c:	b9c9      	cbnz	r1, 4962 <irq_target_state_set+0x38>
  if ((int32_t)(IRQn) >= 0)
    492e:	2b00      	cmp	r3, #0
    4930:	db15      	blt.n	495e <irq_target_state_set+0x34>
    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
    4932:	2101      	movs	r1, #1
    4934:	095b      	lsrs	r3, r3, #5
    4936:	009b      	lsls	r3, r3, #2
    4938:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    493c:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    4940:	f8d3 2280 	ldr.w	r2, [r3, #640]	; 0x280
    4944:	f000 001f 	and.w	r0, r0, #31
    4948:	4081      	lsls	r1, r0
    494a:	ea22 0201 	bic.w	r2, r2, r1
    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
    494e:	f8c3 2280 	str.w	r2, [r3, #640]	; 0x280
    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
    4952:	f8d3 1280 	ldr.w	r1, [r3, #640]	; 0x280
    4956:	40c1      	lsrs	r1, r0
    4958:	f001 0101 	and.w	r1, r1, #1
	} else {
		/* Set target to Non-Secure */
		result = NVIC_SetTargetState(irq);
	}

	if (result) {
    495c:	b2c9      	uxtb	r1, r1
		return IRQ_TARGET_STATE_NON_SECURE;
	} else {
		return IRQ_TARGET_STATE_SECURE;
	}
}
    495e:	4608      	mov	r0, r1
    4960:	4770      	bx	lr
  if ((int32_t)(IRQn) >= 0)
    4962:	2b00      	cmp	r3, #0
    4964:	db0d      	blt.n	4982 <irq_target_state_set+0x58>
    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
    4966:	2201      	movs	r2, #1
    4968:	095b      	lsrs	r3, r3, #5
    496a:	009b      	lsls	r3, r3, #2
    496c:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    4970:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    4974:	f8d3 1280 	ldr.w	r1, [r3, #640]	; 0x280
    4978:	f000 001f 	and.w	r0, r0, #31
    497c:	4082      	lsls	r2, r0
    497e:	430a      	orrs	r2, r1
    4980:	e7e5      	b.n	494e <irq_target_state_set+0x24>
		return IRQ_TARGET_STATE_SECURE;
    4982:	2100      	movs	r1, #0
    4984:	e7eb      	b.n	495e <irq_target_state_set+0x34>

00004986 <configure_builtin_stack_guard>:
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    4986:	6e83      	ldr	r3, [r0, #104]	; 0x68
    4988:	f383 880b 	msr	PSPLIM, r3
}
    498c:	4770      	bx	lr

0000498e <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    498e:	f000 b937 	b.w	4c00 <z_fatal_error>

00004992 <z_do_kernel_oops>:
 *   fault handler will executed insted of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    4992:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
    4994:	6800      	ldr	r0, [r0, #0]
    4996:	f000 b933 	b.w	4c00 <z_fatal_error>

0000499a <z_arm_nmi>:
 *
 * @return N/A
 */

void z_arm_nmi(void)
{
    499a:	b508      	push	{r3, lr}
	handler();
    499c:	f7fc ff00 	bl	17a0 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    49a0:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    49a4:	f7fd b87e 	b.w	1aa4 <z_arm_exc_exit>

000049a8 <mpu_configure_region>:
{
    49a8:	b530      	push	{r4, r5, lr}
	get_region_attr_from_k_mem_partition_info(&region_conf.attr,
    49aa:	684b      	ldr	r3, [r1, #4]
	region_conf.base = new_region->start;
    49ac:	680c      	ldr	r4, [r1, #0]
{
    49ae:	b085      	sub	sp, #20
	p_attr->rbar = attr->rbar &
    49b0:	890a      	ldrh	r2, [r1, #8]
    49b2:	7a8d      	ldrb	r5, [r1, #10]
	region_conf.base = new_region->start;
    49b4:	9400      	str	r4, [sp, #0]
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
    49b6:	3b01      	subs	r3, #1
    49b8:	f024 041f 	bic.w	r4, r4, #31
    49bc:	4423      	add	r3, r4
	p_attr->rbar = attr->rbar &
    49be:	f002 021f 	and.w	r2, r2, #31
    49c2:	ea42 1245 	orr.w	r2, r2, r5, lsl #5
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
    49c6:	f023 031f 	bic.w	r3, r3, #31
	if (index > (get_num_regions() - 1)) {
    49ca:	280f      	cmp	r0, #15
    49cc:	4604      	mov	r4, r0
	p_attr->rbar = attr->rbar &
    49ce:	f88d 2008 	strb.w	r2, [sp, #8]
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
    49d2:	9303      	str	r3, [sp, #12]
    49d4:	d805      	bhi.n	49e2 <mpu_configure_region+0x3a>
	region_init(index, region_conf);
    49d6:	4669      	mov	r1, sp
    49d8:	f7fd f8e6 	bl	1ba8 <region_init>
}
    49dc:	4620      	mov	r0, r4
    49de:	b005      	add	sp, #20
    49e0:	bd30      	pop	{r4, r5, pc}
		return -EINVAL;
    49e2:	f06f 0415 	mvn.w	r4, #21
	return region_allocate_and_init(index,
    49e6:	e7f9      	b.n	49dc <mpu_configure_region+0x34>

000049e8 <arm_cmse_mpu_region_get>:
__CMSE_TT_ASM ()

__extension__ static __inline __attribute__ ((__always_inline__))
cmse_address_info_t
cmse_TT (void *__p)
__CMSE_TT_ASM ()
    49e8:	e840 f000 	tt	r0, r0
    49ec:	b2c3      	uxtb	r3, r0

int arm_cmse_mpu_region_get(uint32_t addr)
{
	cmse_address_info_t addr_info =	cmse_TT((void *)addr);

	if (addr_info.flags.mpu_region_valid) {
    49ee:	f410 3f80 	tst.w	r0, #65536	; 0x10000
		return addr_info.flags.mpu_region;
	}

	return -EINVAL;
}
    49f2:	bf14      	ite	ne
    49f4:	4618      	movne	r0, r3
    49f6:	f06f 0015 	mvneq.w	r0, #21
    49fa:	4770      	bx	lr

000049fc <strcmp>:
 * @return negative # if <s1> < <s2>, 0 if <s1> == <s2>, else positive #
 */

int strcmp(const char *s1, const char *s2)
{
	while ((*s1 == *s2) && (*s1 != '\0')) {
    49fc:	3801      	subs	r0, #1
    49fe:	3901      	subs	r1, #1
    4a00:	f810 3f01 	ldrb.w	r3, [r0, #1]!
    4a04:	f811 2f01 	ldrb.w	r2, [r1, #1]!
    4a08:	4293      	cmp	r3, r2
    4a0a:	d101      	bne.n	4a10 <strcmp+0x14>
    4a0c:	2b00      	cmp	r3, #0
    4a0e:	d1f7      	bne.n	4a00 <strcmp+0x4>
		s1++;
		s2++;
	}

	return *s1 - *s2;
}
    4a10:	1a98      	subs	r0, r3, r2
    4a12:	4770      	bx	lr

00004a14 <memcmp>:
 * @brief Compare two memory areas
 *
 * @return negative # if <m1> < <m2>, 0 if <m1> == <m2>, else positive #
 */
int memcmp(const void *m1, const void *m2, size_t n)
{
    4a14:	b510      	push	{r4, lr}
	const char *c1 = m1;
	const char *c2 = m2;

	if (!n) {
    4a16:	b15a      	cbz	r2, 4a30 <memcmp+0x1c>
    4a18:	3901      	subs	r1, #1
    4a1a:	1884      	adds	r4, r0, r2
		return 0;
	}

	while ((--n > 0) && (*c1 == *c2)) {
    4a1c:	f810 2b01 	ldrb.w	r2, [r0], #1
    4a20:	f811 3f01 	ldrb.w	r3, [r1, #1]!
    4a24:	42a0      	cmp	r0, r4
    4a26:	d001      	beq.n	4a2c <memcmp+0x18>
    4a28:	429a      	cmp	r2, r3
    4a2a:	d0f7      	beq.n	4a1c <memcmp+0x8>
		c1++;
		c2++;
	}

	return *c1 - *c2;
    4a2c:	1ad0      	subs	r0, r2, r3
}
    4a2e:	bd10      	pop	{r4, pc}
		return 0;
    4a30:	4610      	mov	r0, r2
    4a32:	e7fc      	b.n	4a2e <memcmp+0x1a>

00004a34 <memmove>:
void *memmove(void *d, const void *s, size_t n)
{
	char *dest = d;
	const char *src  = s;

	if ((size_t) (dest - src) < n) {
    4a34:	1a43      	subs	r3, r0, r1
    4a36:	4293      	cmp	r3, r2
{
    4a38:	b510      	push	{r4, lr}
    4a3a:	eb00 0302 	add.w	r3, r0, r2
	if ((size_t) (dest - src) < n) {
    4a3e:	d308      	bcc.n	4a52 <memmove+0x1e>
	char *dest = d;
    4a40:	4602      	mov	r2, r0
    4a42:	3901      	subs	r1, #1
			n--;
			dest[n] = src[n];
		}
	} else {
		/* It is safe to perform a forward-copy */
		while (n > 0) {
    4a44:	429a      	cmp	r2, r3
    4a46:	d00b      	beq.n	4a60 <memmove+0x2c>
			*dest = *src;
    4a48:	f811 4f01 	ldrb.w	r4, [r1, #1]!
    4a4c:	f802 4b01 	strb.w	r4, [r2], #1
			dest++;
			src++;
			n--;
    4a50:	e7f8      	b.n	4a44 <memmove+0x10>
    4a52:	440a      	add	r2, r1
			dest[n] = src[n];
    4a54:	f812 4d01 	ldrb.w	r4, [r2, #-1]!
		while (n > 0) {
    4a58:	428a      	cmp	r2, r1
			dest[n] = src[n];
    4a5a:	f803 4d01 	strb.w	r4, [r3, #-1]!
		while (n > 0) {
    4a5e:	d1f9      	bne.n	4a54 <memmove+0x20>
		}
	}

	return d;
}
    4a60:	bd10      	pop	{r4, pc}

00004a62 <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *_MLIBC_RESTRICT d, const void *_MLIBC_RESTRICT s, size_t n)
{
    4a62:	b5f0      	push	{r4, r5, r6, r7, lr}

	unsigned char *d_byte = (unsigned char *)d;
	const unsigned char *s_byte = (const unsigned char *)s;
	const uintptr_t mask = sizeof(mem_word_t) - 1;

	if ((((uintptr_t)d ^ (uintptr_t)s_byte) & mask) == 0) {
    4a64:	ea81 0400 	eor.w	r4, r1, r0
    4a68:	07a5      	lsls	r5, r4, #30
    4a6a:	4603      	mov	r3, r0
    4a6c:	d00b      	beq.n	4a86 <memcpy+0x24>
    4a6e:	3b01      	subs	r3, #1
    4a70:	440a      	add	r2, r1
		s_byte = (unsigned char *)s_word;
	}

	/* do byte-sized copying until finished */

	while (n > 0) {
    4a72:	4291      	cmp	r1, r2
    4a74:	d11b      	bne.n	4aae <memcpy+0x4c>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    4a76:	bdf0      	pop	{r4, r5, r6, r7, pc}
			if (n == 0) {
    4a78:	2a00      	cmp	r2, #0
    4a7a:	d0fc      	beq.n	4a76 <memcpy+0x14>
			*(d_byte++) = *(s_byte++);
    4a7c:	f811 4b01 	ldrb.w	r4, [r1], #1
			n--;
    4a80:	3a01      	subs	r2, #1
			*(d_byte++) = *(s_byte++);
    4a82:	f803 4b01 	strb.w	r4, [r3], #1
		while (((uintptr_t)d_byte) & mask) {
    4a86:	079c      	lsls	r4, r3, #30
    4a88:	d1f6      	bne.n	4a78 <memcpy+0x16>
    4a8a:	f022 0403 	bic.w	r4, r2, #3
    4a8e:	1f1d      	subs	r5, r3, #4
    4a90:	0896      	lsrs	r6, r2, #2
    4a92:	190f      	adds	r7, r1, r4
		while (n >= sizeof(mem_word_t)) {
    4a94:	42b9      	cmp	r1, r7
    4a96:	d105      	bne.n	4aa4 <memcpy+0x42>
    4a98:	f06f 0503 	mvn.w	r5, #3
    4a9c:	4423      	add	r3, r4
    4a9e:	fb05 2206 	mla	r2, r5, r6, r2
    4aa2:	e7e4      	b.n	4a6e <memcpy+0xc>
			*(d_word++) = *(s_word++);
    4aa4:	f851 cb04 	ldr.w	ip, [r1], #4
    4aa8:	f845 cf04 	str.w	ip, [r5, #4]!
			n -= sizeof(mem_word_t);
    4aac:	e7f2      	b.n	4a94 <memcpy+0x32>
		*(d_byte++) = *(s_byte++);
    4aae:	f811 4b01 	ldrb.w	r4, [r1], #1
    4ab2:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    4ab6:	e7dc      	b.n	4a72 <memcpy+0x10>

00004ab8 <memset>:

void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
    4ab8:	4603      	mov	r3, r0
{
    4aba:	b570      	push	{r4, r5, r6, lr}
	unsigned char c_byte = (unsigned char)c;
    4abc:	b2c9      	uxtb	r1, r1

	while (((uintptr_t)d_byte) & (sizeof(mem_word_t) - 1)) {
    4abe:	079c      	lsls	r4, r3, #30
    4ac0:	d111      	bne.n	4ae6 <memset+0x2e>
	/* do word-sized initialization as long as possible */

	mem_word_t *d_word = (mem_word_t *)d_byte;
	mem_word_t c_word = (mem_word_t)c_byte;

	c_word |= c_word << 8;
    4ac2:	ea41 2401 	orr.w	r4, r1, r1, lsl #8
	c_word |= c_word << 16;
    4ac6:	f022 0603 	bic.w	r6, r2, #3
    4aca:	ea44 4504 	orr.w	r5, r4, r4, lsl #16
#if Z_MEM_WORD_T_WIDTH > 32
	c_word |= c_word << 32;
#endif

	while (n >= sizeof(mem_word_t)) {
    4ace:	441e      	add	r6, r3
    4ad0:	0894      	lsrs	r4, r2, #2
    4ad2:	42b3      	cmp	r3, r6
    4ad4:	d10d      	bne.n	4af2 <memset+0x3a>
    4ad6:	f06f 0503 	mvn.w	r5, #3
    4ada:	fb05 2204 	mla	r2, r5, r4, r2
    4ade:	441a      	add	r2, r3

	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;

	while (n > 0) {
    4ae0:	4293      	cmp	r3, r2
    4ae2:	d109      	bne.n	4af8 <memset+0x40>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    4ae4:	bd70      	pop	{r4, r5, r6, pc}
		if (n == 0) {
    4ae6:	2a00      	cmp	r2, #0
    4ae8:	d0fc      	beq.n	4ae4 <memset+0x2c>
		*(d_byte++) = c_byte;
    4aea:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    4aee:	3a01      	subs	r2, #1
    4af0:	e7e5      	b.n	4abe <memset+0x6>
		*(d_word++) = c_word;
    4af2:	f843 5b04 	str.w	r5, [r3], #4
		n -= sizeof(mem_word_t);
    4af6:	e7ec      	b.n	4ad2 <memset+0x1a>
		*(d_byte++) = c_byte;
    4af8:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    4afc:	e7f0      	b.n	4ae0 <memset+0x28>

00004afe <_stdout_hook_default>:
}
    4afe:	f04f 30ff 	mov.w	r0, #4294967295
    4b02:	4770      	bx	lr

00004b04 <uarte_nrfx_config_get>:
{
    4b04:	460b      	mov	r3, r1
	*cfg = get_dev_data(dev)->uart_config;
    4b06:	68c2      	ldr	r2, [r0, #12]
    4b08:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    4b0c:	e883 0003 	stmia.w	r3, {r0, r1}
}
    4b10:	2000      	movs	r0, #0
    4b12:	4770      	bx	lr

00004b14 <uarte_nrfx_err_check>:
	return config->uarte_regs;
    4b14:	6843      	ldr	r3, [r0, #4]
    4b16:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    4b18:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    4b1c:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    4b20:	4770      	bx	lr

00004b22 <uarte_nrfx_poll_in>:
	return config->uarte_regs;
    4b22:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = get_dev_data(dev);
    4b24:	68c2      	ldr	r2, [r0, #12]
	return config->uarte_regs;
    4b26:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4b28:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    4b2c:	b148      	cbz	r0, 4b42 <uarte_nrfx_poll_in+0x20>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4b2e:	2000      	movs	r0, #0
	*c = data->rx_data;
    4b30:	7c12      	ldrb	r2, [r2, #16]
    4b32:	700a      	strb	r2, [r1, #0]
    4b34:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    4b38:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4b3c:	2201      	movs	r2, #1
    4b3e:	601a      	str	r2, [r3, #0]
	return 0;
    4b40:	4770      	bx	lr
		return -1;
    4b42:	f04f 30ff 	mov.w	r0, #4294967295
}
    4b46:	4770      	bx	lr

00004b48 <uarte_nrfx_poll_out>:
{
    4b48:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
	return config->uarte_regs;
    4b4c:	6843      	ldr	r3, [r0, #4]
{
    4b4e:	f88d 1007 	strb.w	r1, [sp, #7]
	return config->uarte_regs;
    4b52:	681c      	ldr	r4, [r3, #0]
	struct uarte_nrfx_data *data = get_dev_data(dev);
    4b54:	68c6      	ldr	r6, [r0, #12]
	if (!k_is_in_isr()) {
    4b56:	f000 f93f 	bl	4dd8 <k_is_in_isr>
    4b5a:	bb98      	cbnz	r0, 4bc4 <uarte_nrfx_poll_out+0x7c>
		lock = &data->poll_out_lock;
    4b5c:	2564      	movs	r5, #100	; 0x64
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    4b5e:	f04f 0801 	mov.w	r8, #1
    4b62:	f106 070c 	add.w	r7, r6, #12
    4b66:	e8d7 3fef 	ldaex	r3, [r7]
    4b6a:	2b00      	cmp	r3, #0
    4b6c:	d103      	bne.n	4b76 <uarte_nrfx_poll_out+0x2e>
    4b6e:	e8c7 8fe2 	stlex	r2, r8, [r7]
    4b72:	2a00      	cmp	r2, #0
    4b74:	d1f7      	bne.n	4b66 <uarte_nrfx_poll_out+0x1e>
		while (atomic_cas((atomic_t *) lock,
    4b76:	d007      	beq.n	4b88 <uarte_nrfx_poll_out+0x40>
	return z_impl_k_sleep(timeout);
    4b78:	2021      	movs	r0, #33	; 0x21
    4b7a:	2100      	movs	r1, #0
    4b7c:	3d01      	subs	r5, #1
    4b7e:	f7fe fa9f 	bl	30c0 <z_impl_k_sleep>
			if (--safety_cnt == 0) {
    4b82:	f015 05ff 	ands.w	r5, r5, #255	; 0xff
    4b86:	d1ee      	bne.n	4b66 <uarte_nrfx_poll_out+0x1e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4b88:	2300      	movs	r3, #0
    4b8a:	f8c4 3120 	str.w	r3, [r4, #288]	; 0x120
    4b8e:	f8d4 3120 	ldr.w	r3, [r4, #288]	; 0x120
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    4b92:	f10d 0307 	add.w	r3, sp, #7
    4b96:	f8c4 3544 	str.w	r3, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    4b9a:	2301      	movs	r3, #1
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4b9c:	f44f 757a 	mov.w	r5, #1000	; 0x3e8
    p_reg->TXD.MAXCNT = length;
    4ba0:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4ba4:	60a3      	str	r3, [r4, #8]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4ba6:	f8d4 3120 	ldr.w	r3, [r4, #288]	; 0x120
	NRFX_WAIT_FOR(nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX),
    4baa:	b923      	cbnz	r3, 4bb6 <uarte_nrfx_poll_out+0x6e>
    4bac:	2001      	movs	r0, #1
    4bae:	f000 f81a 	bl	4be6 <nrfx_busy_wait>
    4bb2:	3d01      	subs	r5, #1
    4bb4:	d1f7      	bne.n	4ba6 <uarte_nrfx_poll_out+0x5e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4bb6:	2301      	movs	r3, #1
    4bb8:	60e3      	str	r3, [r4, #12]
	*lock = 0;
    4bba:	2300      	movs	r3, #0
    4bbc:	60f3      	str	r3, [r6, #12]
}
    4bbe:	b002      	add	sp, #8
    4bc0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		*lock = 1;
    4bc4:	2301      	movs	r3, #1
    4bc6:	60f3      	str	r3, [r6, #12]
    4bc8:	e7de      	b.n	4b88 <uarte_nrfx_poll_out+0x40>

00004bca <k_sys_fatal_error_handler>:
	ARG_UNUSED(reason);

	LOG_PANIC();

	LOG_ERR("Resetting system");
	sys_arch_reboot(0);
    4bca:	2000      	movs	r0, #0
{
    4bcc:	b508      	push	{r3, lr}
	sys_arch_reboot(0);
    4bce:	f7fc ff77 	bl	1ac0 <sys_arch_reboot>

00004bd2 <hw_cc3xx_init>:
#include <nrf_cc3xx_platform.h>

#if CONFIG_HW_CC3XX

static int hw_cc3xx_init(const struct device *dev)
{
    4bd2:	b508      	push	{r3, lr}
	int res;

	__ASSERT_NO_MSG(dev != NULL);

	/* Set the RTOS abort APIs */
	nrf_cc3xx_platform_abort_init();
    4bd4:	f7fc fc68 	bl	14a8 <nrf_cc3xx_platform_abort_init>

	/* Set the RTOS mutex APIs */
	nrf_cc3xx_platform_mutex_init();
    4bd8:	f7fc fcea 	bl	15b0 <nrf_cc3xx_platform_mutex_init>
	res = nrf_cc3xx_platform_init();
#else
	res = nrf_cc3xx_platform_init_no_rng();
#endif
	return res;
}
    4bdc:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	res = nrf_cc3xx_platform_init_no_rng();
    4be0:	f7fe bea6 	b.w	3930 <nrf_cc3xx_platform_init_no_rng>

00004be4 <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    4be4:	4700      	bx	r0

00004be6 <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    4be6:	f000 b8fd 	b.w	4de4 <z_impl_k_busy_wait>

00004bea <nrfx_clock_enable>:
{
    4bea:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    4bec:	2005      	movs	r0, #5
    4bee:	f7fc fd5b 	bl	16a8 <arch_irq_is_enabled>
    4bf2:	b920      	cbnz	r0, 4bfe <nrfx_clock_enable+0x14>
}
    4bf4:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    4bf8:	2005      	movs	r0, #5
    4bfa:	f7fc bd45 	b.w	1688 <arch_irq_enable>
    4bfe:	bd08      	pop	{r3, pc}

00004c00 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    4c00:	b573      	push	{r0, r1, r4, r5, r6, lr}
    4c02:	4605      	mov	r5, r0
    4c04:	9101      	str	r1, [sp, #4]
	__asm__ volatile(
    4c06:	f04f 0320 	mov.w	r3, #32
    4c0a:	f3ef 8611 	mrs	r6, BASEPRI
    4c0e:	f383 8811 	msr	BASEPRI, r3
    4c12:	f3bf 8f6f 	isb	sy
	return z_impl_k_current_get();
    4c16:	f7fe fa73 	bl	3100 <z_impl_k_current_get>
	LOG_ERR("Current thread: %p (%s)", thread,
		log_strdup(thread_name_get(thread)));

	z_coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    4c1a:	9901      	ldr	r1, [sp, #4]
    4c1c:	4604      	mov	r4, r0
    4c1e:	4628      	mov	r0, r5
    4c20:	f7ff ffd3 	bl	4bca <k_sys_fatal_error_handler>
	__asm__ volatile(
    4c24:	f386 8811 	msr	BASEPRI, r6
    4c28:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    4c2c:	4620      	mov	r0, r4
#endif /*CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION */
	}

	arch_irq_unlock(key);
	k_thread_abort(thread);
}
    4c2e:	b002      	add	sp, #8
    4c30:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    4c34:	f7fc bf62 	b.w	1afc <z_impl_k_thread_abort>

00004c38 <z_sys_power_save_idle_exit>:
	z_clock_idle_exit();
    4c38:	f7ff be23 	b.w	4882 <z_clock_idle_exit>

00004c3c <k_mem_slab_init>:
{
    4c3c:	b530      	push	{r4, r5, lr}
	slab->num_used = 0U;
    4c3e:	2400      	movs	r4, #0
    4c40:	6184      	str	r4, [r0, #24]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    4c42:	ea41 0402 	orr.w	r4, r1, r2
    4c46:	f014 0403 	ands.w	r4, r4, #3
	slab->block_size = block_size;
    4c4a:	e9c0 3202 	strd	r3, r2, [r0, #8]
	slab->buffer = buffer;
    4c4e:	6101      	str	r1, [r0, #16]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    4c50:	d10c      	bne.n	4c6c <k_mem_slab_init+0x30>
	slab->free_list = NULL;
    4c52:	6144      	str	r4, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    4c54:	42a3      	cmp	r3, r4
    4c56:	d103      	bne.n	4c60 <k_mem_slab_init+0x24>
	list->tail = (sys_dnode_t *)list;
    4c58:	e9c0 0000 	strd	r0, r0, [r0]
}
    4c5c:	2000      	movs	r0, #0
}
    4c5e:	bd30      	pop	{r4, r5, pc}
		*(char **)p = slab->free_list;
    4c60:	6945      	ldr	r5, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    4c62:	3401      	adds	r4, #1
		*(char **)p = slab->free_list;
    4c64:	600d      	str	r5, [r1, #0]
		slab->free_list = p;
    4c66:	6141      	str	r1, [r0, #20]
		p += slab->block_size;
    4c68:	4411      	add	r1, r2
	for (j = 0U; j < slab->num_blocks; j++) {
    4c6a:	e7f3      	b.n	4c54 <k_mem_slab_init+0x18>
		return -EINVAL;
    4c6c:	f06f 0015 	mvn.w	r0, #21
	return rc;
    4c70:	e7f5      	b.n	4c5e <k_mem_slab_init+0x22>

00004c72 <z_impl_k_mutex_init>:
	mutex->owner = NULL;
    4c72:	2300      	movs	r3, #0
    4c74:	e9c0 0000 	strd	r0, r0, [r0]
	mutex->lock_count = 0U;
    4c78:	e9c0 3302 	strd	r3, r3, [r0, #8]
}
    4c7c:	4618      	mov	r0, r3
    4c7e:	4770      	bx	lr

00004c80 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    4c80:	4603      	mov	r3, r0
    4c82:	b920      	cbnz	r0, 4c8e <z_reschedule_irqlock+0xe>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    4c84:	f3ef 8205 	mrs	r2, IPSR
    4c88:	b90a      	cbnz	r2, 4c8e <z_reschedule_irqlock+0xe>
    4c8a:	f7fc bca7 	b.w	15dc <arch_swap>
    4c8e:	f383 8811 	msr	BASEPRI, r3
    4c92:	f3bf 8f6f 	isb	sy
}
    4c96:	4770      	bx	lr

00004c98 <z_reschedule_unlocked>:
	__asm__ volatile(
    4c98:	f04f 0320 	mov.w	r3, #32
    4c9c:	f3ef 8011 	mrs	r0, BASEPRI
    4ca0:	f383 8811 	msr	BASEPRI, r3
    4ca4:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    4ca8:	f7ff bfea 	b.w	4c80 <z_reschedule_irqlock>

00004cac <unpend_thread_no_timeout>:
{
    4cac:	4601      	mov	r1, r0
    4cae:	b508      	push	{r3, lr}
	_priq_wait_remove(&pended_on(thread)->waitq, thread);
    4cb0:	6880      	ldr	r0, [r0, #8]
    4cb2:	f7fd ff31 	bl	2b18 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    4cb6:	7b4b      	ldrb	r3, [r1, #13]
    4cb8:	f023 0302 	bic.w	r3, r3, #2
    4cbc:	734b      	strb	r3, [r1, #13]
	thread->base.pended_on = NULL;
    4cbe:	2300      	movs	r3, #0
    4cc0:	608b      	str	r3, [r1, #8]
}
    4cc2:	bd08      	pop	{r3, pc}

00004cc4 <z_priq_dumb_best>:
	return list->head == list;
    4cc4:	6803      	ldr	r3, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4cc6:	4298      	cmp	r0, r3
    4cc8:	d004      	beq.n	4cd4 <z_priq_dumb_best+0x10>
	if (n != NULL) {
    4cca:	2b00      	cmp	r3, #0
    4ccc:	bf38      	it	cc
    4cce:	2300      	movcc	r3, #0
    4cd0:	4618      	mov	r0, r3
    4cd2:	4770      	bx	lr
	struct k_thread *thread = NULL;
    4cd4:	2000      	movs	r0, #0
}
    4cd6:	4770      	bx	lr

00004cd8 <z_ready_thread>:
{
    4cd8:	b510      	push	{r4, lr}
    4cda:	f04f 0320 	mov.w	r3, #32
    4cde:	f3ef 8411 	mrs	r4, BASEPRI
    4ce2:	f383 8811 	msr	BASEPRI, r3
    4ce6:	f3bf 8f6f 	isb	sy
		ready_thread(thread);
    4cea:	f7fd ff6b 	bl	2bc4 <ready_thread>
	__asm__ volatile(
    4cee:	f384 8811 	msr	BASEPRI, r4
    4cf2:	f3bf 8f6f 	isb	sy
}
    4cf6:	bd10      	pop	{r4, pc}

00004cf8 <z_thread_timeout>:
{
    4cf8:	b537      	push	{r0, r1, r2, r4, r5, lr}
    4cfa:	4604      	mov	r4, r0
	__asm__ volatile(
    4cfc:	f04f 0320 	mov.w	r3, #32
    4d00:	f3ef 8511 	mrs	r5, BASEPRI
    4d04:	f383 8811 	msr	BASEPRI, r3
    4d08:	f3bf 8f6f 	isb	sy
		if (thread->base.pended_on != NULL) {
    4d0c:	f854 3c10 	ldr.w	r3, [r4, #-16]
		struct k_thread *thread = CONTAINER_OF(timeout,
    4d10:	3818      	subs	r0, #24
		if (thread->base.pended_on != NULL) {
    4d12:	b11b      	cbz	r3, 4d1c <z_thread_timeout+0x24>
			unpend_thread_no_timeout(thread);
    4d14:	9001      	str	r0, [sp, #4]
    4d16:	f7ff ffc9 	bl	4cac <unpend_thread_no_timeout>
    4d1a:	9801      	ldr	r0, [sp, #4]
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    4d1c:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
    4d20:	f023 0314 	bic.w	r3, r3, #20
    4d24:	f804 3c0b 	strb.w	r3, [r4, #-11]
		ready_thread(thread);
    4d28:	f7fd ff4c 	bl	2bc4 <ready_thread>
	__asm__ volatile(
    4d2c:	f385 8811 	msr	BASEPRI, r5
    4d30:	f3bf 8f6f 	isb	sy
}
    4d34:	b003      	add	sp, #12
    4d36:	bd30      	pop	{r4, r5, pc}

00004d38 <add_to_waitq_locked>:
{
    4d38:	b538      	push	{r3, r4, r5, lr}
    4d3a:	4604      	mov	r4, r0
    4d3c:	460d      	mov	r5, r1
	unready_thread(thread);
    4d3e:	f7fe f89f 	bl	2e80 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    4d42:	7b63      	ldrb	r3, [r4, #13]
    4d44:	f043 0302 	orr.w	r3, r3, #2
    4d48:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    4d4a:	b1c5      	cbz	r5, 4d7e <add_to_waitq_locked+0x46>
	return list->head == list;
    4d4c:	682b      	ldr	r3, [r5, #0]
		thread->base.pended_on = wait_q;
    4d4e:	60a5      	str	r5, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4d50:	429d      	cmp	r5, r3
    4d52:	bf08      	it	eq
    4d54:	2300      	moveq	r3, #0
    4d56:	2b00      	cmp	r3, #0
    4d58:	bf38      	it	cc
    4d5a:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4d5c:	b183      	cbz	r3, 4d80 <add_to_waitq_locked+0x48>
	if (thread_1->base.prio < thread_2->base.prio) {
    4d5e:	f994 100e 	ldrsb.w	r1, [r4, #14]
    4d62:	f993 200e 	ldrsb.w	r2, [r3, #14]
    4d66:	4291      	cmp	r1, r2
    4d68:	db04      	blt.n	4d74 <add_to_waitq_locked+0x3c>
	return (node == list->tail) ? NULL : node->next;
    4d6a:	686a      	ldr	r2, [r5, #4]
    4d6c:	429a      	cmp	r2, r3
    4d6e:	d007      	beq.n	4d80 <add_to_waitq_locked+0x48>
    4d70:	681b      	ldr	r3, [r3, #0]
    4d72:	e7f3      	b.n	4d5c <add_to_waitq_locked+0x24>
	node->prev = successor->prev;
    4d74:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    4d76:	e9c4 3200 	strd	r3, r2, [r4]
	successor->prev->next = node;
    4d7a:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    4d7c:	605c      	str	r4, [r3, #4]
}
    4d7e:	bd38      	pop	{r3, r4, r5, pc}
	node->prev = list->tail;
    4d80:	686b      	ldr	r3, [r5, #4]
	node->next = list;
    4d82:	6025      	str	r5, [r4, #0]
	node->prev = list->tail;
    4d84:	6063      	str	r3, [r4, #4]
	list->tail->next = node;
    4d86:	686b      	ldr	r3, [r5, #4]
    4d88:	601c      	str	r4, [r3, #0]
	list->tail = node;
    4d8a:	606c      	str	r4, [r5, #4]
    4d8c:	e7f7      	b.n	4d7e <add_to_waitq_locked+0x46>

00004d8e <z_unpend_first_thread>:
{
    4d8e:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    4d90:	f04f 0320 	mov.w	r3, #32
    4d94:	f3ef 8211 	mrs	r2, BASEPRI
    4d98:	f383 8811 	msr	BASEPRI, r3
    4d9c:	f3bf 8f6f 	isb	sy
		ret = _priq_wait_best(&wait_q->waitq);
    4da0:	f7ff ff90 	bl	4cc4 <z_priq_dumb_best>
    4da4:	4604      	mov	r4, r0
	__asm__ volatile(
    4da6:	f382 8811 	msr	BASEPRI, r2
    4daa:	f3bf 8f6f 	isb	sy

static inline struct k_thread *z_unpend1_no_timeout(_wait_q_t *wait_q)
{
	struct k_thread *thread = z_find_first_thread_to_unpend(wait_q, NULL);

	if (thread != NULL) {
    4dae:	b188      	cbz	r0, 4dd4 <z_unpend_first_thread+0x46>
	__asm__ volatile(
    4db0:	f04f 0320 	mov.w	r3, #32
    4db4:	f3ef 8511 	mrs	r5, BASEPRI
    4db8:	f383 8811 	msr	BASEPRI, r3
    4dbc:	f3bf 8f6f 	isb	sy
		unpend_thread_no_timeout(thread);
    4dc0:	f7ff ff74 	bl	4cac <unpend_thread_no_timeout>
	__asm__ volatile(
    4dc4:	f385 8811 	msr	BASEPRI, r5
    4dc8:	f3bf 8f6f 	isb	sy
	return z_abort_timeout(&thread->base.timeout);
    4dcc:	f104 0018 	add.w	r0, r4, #24
    4dd0:	f000 f80a 	bl	4de8 <z_abort_timeout>
}
    4dd4:	4620      	mov	r0, r4
    4dd6:	bd38      	pop	{r3, r4, r5, pc}

00004dd8 <k_is_in_isr>:
    4dd8:	f3ef 8005 	mrs	r0, IPSR
}
    4ddc:	3800      	subs	r0, #0
    4dde:	bf18      	it	ne
    4de0:	2001      	movne	r0, #1
    4de2:	4770      	bx	lr

00004de4 <z_impl_k_busy_wait>:
	arch_busy_wait(usec_to_wait);
    4de4:	f7fb be66 	b.w	ab4 <arch_busy_wait>

00004de8 <z_abort_timeout>:
{
    4de8:	b510      	push	{r4, lr}
	__asm__ volatile(
    4dea:	f04f 0220 	mov.w	r2, #32
    4dee:	f3ef 8411 	mrs	r4, BASEPRI
    4df2:	f382 8811 	msr	BASEPRI, r2
    4df6:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
    4dfa:	6803      	ldr	r3, [r0, #0]
    4dfc:	b13b      	cbz	r3, 4e0e <z_abort_timeout+0x26>
			remove_timeout(to);
    4dfe:	f7fe fa67 	bl	32d0 <remove_timeout>
			ret = 0;
    4e02:	2000      	movs	r0, #0
	__asm__ volatile(
    4e04:	f384 8811 	msr	BASEPRI, r4
    4e08:	f3bf 8f6f 	isb	sy
}
    4e0c:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
    4e0e:	f06f 0015 	mvn.w	r0, #21
    4e12:	e7f7      	b.n	4e04 <z_abort_timeout+0x1c>

00004e14 <z_get_next_timeout_expiry>:
{
    4e14:	b510      	push	{r4, lr}
	__asm__ volatile(
    4e16:	f04f 0320 	mov.w	r3, #32
    4e1a:	f3ef 8411 	mrs	r4, BASEPRI
    4e1e:	f383 8811 	msr	BASEPRI, r3
    4e22:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
    4e26:	f7fe fa6d 	bl	3304 <next_timeout>
	__asm__ volatile(
    4e2a:	f384 8811 	msr	BASEPRI, r4
    4e2e:	f3bf 8f6f 	isb	sy
}
    4e32:	bd10      	pop	{r4, pc}

00004e34 <z_set_timeout_expiry>:
{
    4e34:	b537      	push	{r0, r1, r2, r4, r5, lr}
    4e36:	4604      	mov	r4, r0
    4e38:	9101      	str	r1, [sp, #4]
	__asm__ volatile(
    4e3a:	f04f 0320 	mov.w	r3, #32
    4e3e:	f3ef 8511 	mrs	r5, BASEPRI
    4e42:	f383 8811 	msr	BASEPRI, r3
    4e46:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
    4e4a:	f7fe fa5b 	bl	3304 <next_timeout>
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
    4e4e:	2801      	cmp	r0, #1
    4e50:	dd05      	ble.n	4e5e <z_set_timeout_expiry+0x2a>
    4e52:	42a0      	cmp	r0, r4
    4e54:	9901      	ldr	r1, [sp, #4]
    4e56:	dd02      	ble.n	4e5e <z_set_timeout_expiry+0x2a>
			z_clock_set_timeout(ticks, is_idle);
    4e58:	4620      	mov	r0, r4
    4e5a:	f7fc f85b 	bl	f14 <z_clock_set_timeout>
	__asm__ volatile(
    4e5e:	f385 8811 	msr	BASEPRI, r5
    4e62:	f3bf 8f6f 	isb	sy
}
    4e66:	b003      	add	sp, #12
    4e68:	bd30      	pop	{r4, r5, pc}

00004e6a <z_tick_get_32>:

uint32_t z_tick_get_32(void)
{
    4e6a:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)z_tick_get();
    4e6c:	f7fe fb64 	bl	3538 <z_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    4e70:	bd08      	pop	{r3, pc}

00004e72 <k_heap_init>:
{
    4e72:	b410      	push	{r4}
	sys_dlist_init(&w->waitq);
    4e74:	f100 040c 	add.w	r4, r0, #12
	list->tail = (sys_dnode_t *)list;
    4e78:	e9c0 4403 	strd	r4, r4, [r0, #12]
}
    4e7c:	f85d 4b04 	ldr.w	r4, [sp], #4
	sys_heap_init(&h->heap, mem, bytes);
    4e80:	f7ff bc11 	b.w	46a6 <sys_heap_init>

00004e84 <_OffsetAbsSyms>:
#include "offsets_aarch64.c"
#else
#include "offsets_aarch32.c"
#endif

GEN_ABS_SYM_END
    4e84:	4770      	bx	lr

Disassembly of section .gnu.sgstubs:

00005940 <spm_firmware_info_nse-0x26a0>:
	...

00007fe0 <spm_firmware_info_nse>:
    7fe0:	e97f e97f 	sg
    7fe4:	f7f9 b9f6 	b.w	13d4 <__acle_se_spm_firmware_info_nse>

00007fe8 <spm_request_random_number_nse>:
    7fe8:	e97f e97f 	sg
    7fec:	f7fc bc55 	b.w	489a <__acle_se_spm_request_random_number_nse>

00007ff0 <spm_request_read_nse>:
    7ff0:	e97f e97f 	sg
    7ff4:	f7f9 b996 	b.w	1324 <__acle_se_spm_request_read_nse>
	...
