/*
 * Generated by gen_defines.py
 *
 * DTS input file:
 *   D:/prj/Perforce/Nordic/BMS-O/DEV_JSC/apps_file_system/sys_heap/build/mcuboot/zephyr/zephyr.dts.pre
 *
 * Directories with bindings:
 *   D:/prj/Perforce/Nordic/BMS-O/MAIN/sdks/v2.2.0/nrf/dts/bindings, $ZEPHYR_BASE\dts\bindings
 *
 * Node dependency ordering (ordinal and path):
 *   0   /
 *   1   /aliases
 *   2   /chosen
 *   3   /entropy_bt_hci
 *   4   /cpus
 *   5   /cpus/cpu@0
 *   6   /cpus/cpu@0/mpu@e000ed90
 *   7   /leds
 *   8   /soc
 *   9   /soc/peripheral@50000000
 *   10  /soc/peripheral@50000000/gpio@842500
 *   11  /leds/led_0
 *   12  /pin-controller
 *   13  /pin-controller/uart0_default
 *   14  /pin-controller/uart0_default/group1
 *   15  /pin-controller/uart0_sleep
 *   16  /pin-controller/uart0_sleep/group1
 *   17  /reserved-memory
 *   18  /reserved-memory/image_modem@20016000
 *   19  /reserved-memory/image_ns@20020000
 *   20  /reserved-memory/image_s@20000000
 *   21  /soc/ctrlap@50006000
 *   22  /soc/ficr@ff0000
 *   23  /soc/interrupt-controller@e000e100
 *   24  /soc/gpiote@5000d000
 *   25  /soc/memory@20000000
 *   26  /soc/spu@50003000
 *   27  /soc/timer@e000e010
 *   28  /soc/uicr@ff8000
 *   29  /soc/crypto@50840000
 *   30  /soc/crypto@50840000/crypto@50841000
 *   31  /soc/peripheral@50000000/adc@e000
 *   32  /soc/peripheral@50000000/clock@5000
 *   33  /soc/peripheral@50000000/dppic@17000
 *   34  /soc/peripheral@50000000/egu@1b000
 *   35  /soc/peripheral@50000000/egu@1c000
 *   36  /soc/peripheral@50000000/egu@1d000
 *   37  /soc/peripheral@50000000/egu@1e000
 *   38  /soc/peripheral@50000000/egu@1f000
 *   39  /soc/peripheral@50000000/egu@20000
 *   40  /soc/peripheral@50000000/i2c@8000
 *   41  /soc/peripheral@50000000/i2c@9000
 *   42  /soc/peripheral@50000000/i2c@a000
 *   43  /soc/peripheral@50000000/i2c@b000
 *   44  /soc/peripheral@50000000/i2s@28000
 *   45  /soc/peripheral@50000000/ipc@2a000
 *   46  /soc/peripheral@50000000/kmu@39000
 *   47  /soc/peripheral@50000000/pdm@26000
 *   48  /soc/peripheral@50000000/power@5000
 *   49  /soc/peripheral@50000000/pwm@21000
 *   50  /soc/peripheral@50000000/pwm@22000
 *   51  /soc/peripheral@50000000/pwm@23000
 *   52  /soc/peripheral@50000000/pwm@24000
 *   53  /soc/peripheral@50000000/regulator@4000
 *   54  /soc/peripheral@50000000/rtc@14000
 *   55  /soc/peripheral@50000000/rtc@15000
 *   56  /soc/peripheral@50000000/spi@8000
 *   57  /soc/peripheral@50000000/spi@9000
 *   58  /soc/peripheral@50000000/spi@a000
 *   59  /soc/peripheral@50000000/spi@b000
 *   60  /soc/peripheral@50000000/timer@f000
 *   61  /soc/peripheral@50000000/timer@10000
 *   62  /soc/peripheral@50000000/timer@11000
 *   63  /soc/peripheral@50000000/uart@8000
 *   64  /soc/peripheral@50000000/uart@9000
 *   65  /soc/peripheral@50000000/uart@a000
 *   66  /soc/peripheral@50000000/uart@b000
 *   67  /soc/peripheral@50000000/vmc@3a000
 *   68  /soc/peripheral@50000000/watchdog@18000
 *   69  /soc/peripheral@50000000/flash-controller@39000
 *   70  /soc/peripheral@50000000/flash-controller@39000/flash@0
 *   71  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *   72  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0
 *   73  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000
 *   74  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000
 *   75  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000
 *   76  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000
 *   77  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f0000
 *   78  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@fa000
 *
 * Definitions derived from these nodes in dependency order are next,
 * followed by /chosen nodes.
 */

/* Used to remove brackets from around a single argument */
#define DT_DEBRACKET_INTERNAL(...) __VA_ARGS__

/*
 * Devicetree node: /
 *
 * Node identifier: DT_N
 */

/* Node's full path: */
#define DT_N_PATH "/"

/* Node's name with unit-address: */
#define DT_N_FULL_NAME "/"

/* Helper macros for child nodes of this node. */
#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_leds) fn(DT_N_S_reserved_memory)
#define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory)
#define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_leds) fn(DT_N_S_reserved_memory)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_ORD 0

/* Ordinals for what this node depends on directly: */
#define DT_N_REQUIRES_ORDS /* nothing */

/* Ordinals for what depends directly on this node: */
#define DT_N_SUPPORTS_ORDS \
	1, /* /aliases */ \
	2, /* /chosen */ \
	3, /* /entropy_bt_hci */ \
	4, /* /cpus */ \
	7, /* /leds */ \
	8, /* /soc */ \
	12, /* /pin-controller */ \
	17, /* /reserved-memory */

/* Existence and alternate IDs: */
#define DT_N_EXISTS 1
#define DT_N_INST_0_nordic_nrf9160_dk_nrf9160 DT_N

/* Macros for properties that are special in the specification: */
#define DT_N_REG_NUM 0
#define DT_N_RANGES_NUM 0
#define DT_N_FOREACH_RANGE(fn) 
#define DT_N_IRQ_NUM 0
#define DT_N_COMPAT_MATCHES_nordic_nrf9160_dk_nrf9160 1
#define DT_N_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_COMPAT_MODEL_IDX_0 "nrf9160-dk-nrf9160"
#define DT_N_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_P_compatible {"nordic,nrf9160-dk-nrf9160"}
#define DT_N_P_compatible_IDX_0 "nordic,nrf9160-dk-nrf9160"
#define DT_N_P_compatible_IDX_0_STRING_TOKEN nordic_nrf9160_dk_nrf9160
#define DT_N_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF9160_DK_NRF9160
#define DT_N_P_compatible_IDX_0_EXISTS 1
#define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_LEN 1
#define DT_N_P_compatible_EXISTS 1

/*
 * Devicetree node: /aliases
 *
 * Node identifier: DT_N_S_aliases
 */

/* Node's full path: */
#define DT_N_S_aliases_PATH "/aliases"

/* Node's name with unit-address: */
#define DT_N_S_aliases_FULL_NAME "aliases"

/* Node parent (/) identifier: */
#define DT_N_S_aliases_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_aliases_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_aliases_FOREACH_CHILD(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_aliases_ORD 1

/* Ordinals for what this node depends on directly: */
#define DT_N_S_aliases_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_aliases_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_aliases_REG_NUM 0
#define DT_N_S_aliases_RANGES_NUM 0
#define DT_N_S_aliases_FOREACH_RANGE(fn) 
#define DT_N_S_aliases_IRQ_NUM 0
#define DT_N_S_aliases_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_aliases_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /chosen
 *
 * Node identifier: DT_N_S_chosen
 */

/* Node's full path: */
#define DT_N_S_chosen_PATH "/chosen"

/* Node's name with unit-address: */
#define DT_N_S_chosen_FULL_NAME "chosen"

/* Node parent (/) identifier: */
#define DT_N_S_chosen_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_chosen_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_chosen_FOREACH_CHILD(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_chosen_ORD 2

/* Ordinals for what this node depends on directly: */
#define DT_N_S_chosen_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_chosen_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_chosen_REG_NUM 0
#define DT_N_S_chosen_RANGES_NUM 0
#define DT_N_S_chosen_FOREACH_RANGE(fn) 
#define DT_N_S_chosen_IRQ_NUM 0
#define DT_N_S_chosen_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_chosen_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /entropy_bt_hci
 *
 * Node identifier: DT_N_S_entropy_bt_hci
 *
 * Binding (compatible = zephyr,bt-hci-entropy):
 *   $ZEPHYR_BASE\dts\bindings\bluetooth\zephyr,bt-hci-entropy.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_entropy_bt_hci_PATH "/entropy_bt_hci"

/* Node's name with unit-address: */
#define DT_N_S_entropy_bt_hci_FULL_NAME "entropy_bt_hci"

/* Node parent (/) identifier: */
#define DT_N_S_entropy_bt_hci_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_entropy_bt_hci_CHILD_IDX 4

/* Helper macros for child nodes of this node. */
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD(fn) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_entropy_bt_hci_ORD 3

/* Ordinals for what this node depends on directly: */
#define DT_N_S_entropy_bt_hci_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_entropy_bt_hci_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_entropy_bt_hci_EXISTS 1
#define DT_N_INST_0_zephyr_bt_hci_entropy DT_N_S_entropy_bt_hci
#define DT_N_NODELABEL_rng_hci            DT_N_S_entropy_bt_hci

/* Macros for properties that are special in the specification: */
#define DT_N_S_entropy_bt_hci_REG_NUM 0
#define DT_N_S_entropy_bt_hci_RANGES_NUM 0
#define DT_N_S_entropy_bt_hci_FOREACH_RANGE(fn) 
#define DT_N_S_entropy_bt_hci_IRQ_NUM 0
#define DT_N_S_entropy_bt_hci_COMPAT_MATCHES_zephyr_bt_hci_entropy 1
#define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding"
#define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0 "bt-hci-entropy"
#define DT_N_S_entropy_bt_hci_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_entropy_bt_hci_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_entropy_bt_hci_P_status "okay"
#define DT_N_S_entropy_bt_hci_P_status_STRING_TOKEN okay
#define DT_N_S_entropy_bt_hci_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_entropy_bt_hci_P_status_ENUM_IDX 1
#define DT_N_S_entropy_bt_hci_P_status_ENUM_TOKEN okay
#define DT_N_S_entropy_bt_hci_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, status, 0) \
	fn(DT_N_S_entropy_bt_hci, status, 1) \
	fn(DT_N_S_entropy_bt_hci, status, 2) \
	fn(DT_N_S_entropy_bt_hci, status, 3)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_entropy_bt_hci, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_entropy_bt_hci, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_entropy_bt_hci, status, 3)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__) \
	fn(DT_N_S_entropy_bt_hci, status, 1, __VA_ARGS__) \
	fn(DT_N_S_entropy_bt_hci, status, 2, __VA_ARGS__) \
	fn(DT_N_S_entropy_bt_hci, status, 3, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_entropy_bt_hci, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_entropy_bt_hci, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_entropy_bt_hci, status, 3, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_status_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_compatible {"zephyr,bt-hci-entropy"}
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0 "zephyr,bt-hci-entropy"
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_entropy
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_ENTROPY
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, compatible, 0)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, compatible, 0)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_compatible_LEN 1
#define DT_N_S_entropy_bt_hci_P_compatible_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_wakeup_source 0
#define DT_N_S_entropy_bt_hci_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /cpus
 *
 * Node identifier: DT_N_S_cpus
 */

/* Node's full path: */
#define DT_N_S_cpus_PATH "/cpus"

/* Node's name with unit-address: */
#define DT_N_S_cpus_FULL_NAME "cpus"

/* Node parent (/) identifier: */
#define DT_N_S_cpus_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_CHILD_IDX 5

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_ORD 4

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_SUPPORTS_ORDS \
	5, /* /cpus/cpu@0 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_REG_NUM 0
#define DT_N_S_cpus_RANGES_NUM 0
#define DT_N_S_cpus_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_IRQ_NUM 0
#define DT_N_S_cpus_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/cpu@0
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0
 *
 * Binding (compatible = arm,cortex-m33f):
 *   $ZEPHYR_BASE\dts\bindings\cpu\arm,cortex-m33f.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0"

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_ORD 5

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \
	4, /* /cpus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS \
	6, /* /cpus/cpu@0/mpu@e000ed90 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_EXISTS 1
#define DT_N_INST_0_arm_cortex_m33f DT_N_S_cpus_S_cpu_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m33f 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0 "cortex-m33f"
#define DT_N_S_cpus_S_cpu_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m33f"}
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m33f"
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_TOKEN arm_cortex_m33f
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CORTEX_M33F
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */}
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, reg, 0)
#define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, reg, 0)
#define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, reg, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, reg, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@0/mpu@e000ed90
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
 *
 * Binding (compatible = arm,armv8m-mpu):
 *   $ZEPHYR_BASE\dts\bindings\mmu_mpu\arm,armv8m-mpu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PATH "/cpus/cpu@0/mpu@e000ed90"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME "mpu@e000ed90"

/* Node parent (/cpus/cpu@0) identifier: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PARENT DT_N_S_cpus_S_cpu_0

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD 6

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REQUIRES_ORDS \
	5, /* /cpus/cpu@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_EXISTS 1
#define DT_N_INST_0_arm_armv8m_mpu DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
#define DT_N_NODELABEL_mpu         DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS 3758157200 /* 0xe000ed90 */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE 64 /* 0x40 */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MATCHES_arm_armv8m_mpu 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MODEL_IDX_0 "armv8m-mpu"
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg {3758157200 /* 0xe000ed90 */, 64 /* 0x40 */}
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0 3758157200
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1 64
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 0) \
	fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 1)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 1)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 1, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 1, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions 16
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible {"arm,armv8m-mpu"}
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0 "arm,armv8m-mpu"
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_mpu
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_MPU
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /leds
 *
 * Node identifier: DT_N_S_leds
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\led\gpio-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_PATH "/leds"

/* Node's name with unit-address: */
#define DT_N_S_leds_FULL_NAME "leds"

/* Node parent (/) identifier: */
#define DT_N_S_leds_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_CHILD_IDX 6

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_leds_ORD 7

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_SUPPORTS_ORDS \
	11, /* /leds/led_0 */

/* Existence and alternate IDs: */
#define DT_N_S_leds_EXISTS 1
#define DT_N_INST_0_gpio_leds DT_N_S_leds

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_REG_NUM 0
#define DT_N_S_leds_RANGES_NUM 0
#define DT_N_S_leds_FOREACH_RANGE(fn) 
#define DT_N_S_leds_IRQ_NUM 0
#define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1
#define DT_N_S_leds_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_P_compatible {"gpio-leds"}
#define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds"
#define DT_N_S_leds_P_compatible_IDX_0_STRING_TOKEN gpio_leds
#define DT_N_S_leds_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_LEDS
#define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_LEN 1
#define DT_N_S_leds_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc
 *
 * Node identifier: DT_N_S_soc
 */

/* Node's full path: */
#define DT_N_S_soc_PATH "/soc"

/* Node's name with unit-address: */
#define DT_N_S_soc_FULL_NAME "soc"

/* Node parent (/) identifier: */
#define DT_N_S_soc_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_CHILD_IDX 2

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_crypto_50840000) fn(DT_N_S_soc_S_ctrlap_50006000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000)
#define DT_N_S_soc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50840000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ctrlap_50006000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000)
#define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_crypto_50840000) fn(DT_N_S_soc_S_ctrlap_50006000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50840000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ctrlap_50006000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_ORD 8

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_SUPPORTS_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	21, /* /soc/ctrlap@50006000 */ \
	22, /* /soc/ficr@ff0000 */ \
	23, /* /soc/interrupt-controller@e000e100 */ \
	24, /* /soc/gpiote@5000d000 */ \
	25, /* /soc/memory@20000000 */ \
	26, /* /soc/spu@50003000 */ \
	27, /* /soc/timer@e000e010 */ \
	28, /* /soc/uicr@ff8000 */ \
	29, /* /soc/crypto@50840000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_EXISTS 1
#define DT_N_INST_0_nordic_nrf9160_sica DT_N_S_soc
#define DT_N_INST_0_nordic_nrf9160      DT_N_S_soc
#define DT_N_INST_0_nordic_nrf91        DT_N_S_soc
#define DT_N_INST_0_simple_bus          DT_N_S_soc

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_REG_NUM 0
#define DT_N_S_soc_RANGES_NUM 0
#define DT_N_S_soc_FOREACH_RANGE(fn) 
#define DT_N_S_soc_IRQ_NUM 0
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9160_sica 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_0 "nRF9160-SICA"
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9160 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
#define DT_N_S_soc_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_1 "nRF9160"
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf91 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_2_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_2 "Nordic Semiconductor"
#define DT_N_S_soc_COMPAT_MODEL_IDX_2_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_2 "nRF91"
#define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_P_compatible {"nordic,nRF9160-SICA", "nordic,nRF9160", "nordic,nRF91", "simple-bus"}
#define DT_N_S_soc_P_compatible_IDX_0 "nordic,nRF9160-SICA"
#define DT_N_S_soc_P_compatible_IDX_0_STRING_TOKEN nordic_nRF9160_SICA
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF9160_SICA
#define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_1 "nordic,nRF9160"
#define DT_N_S_soc_P_compatible_IDX_1_STRING_TOKEN nordic_nRF9160
#define DT_N_S_soc_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF9160
#define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_2 "nordic,nRF91"
#define DT_N_S_soc_P_compatible_IDX_2_STRING_TOKEN nordic_nRF91
#define DT_N_S_soc_P_compatible_IDX_2_STRING_UPPER_TOKEN NORDIC_NRF91
#define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_3 "simple-bus"
#define DT_N_S_soc_P_compatible_IDX_3_STRING_TOKEN simple_bus
#define DT_N_S_soc_P_compatible_IDX_3_STRING_UPPER_TOKEN SIMPLE_BUS
#define DT_N_S_soc_P_compatible_IDX_3_EXISTS 1
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0) \
	fn(DT_N_S_soc, compatible, 1) \
	fn(DT_N_S_soc, compatible, 2) \
	fn(DT_N_S_soc, compatible, 3)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 3)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 3, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 3, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_LEN 4
#define DT_N_S_soc_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_PATH "/soc/peripheral@50000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_FULL_NAME "peripheral@50000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_CHILD_IDX 3

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_ORD 9

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_REQUIRES_ORDS \
	8, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_SUPPORTS_ORDS \
	10, /* /soc/peripheral@50000000/gpio@842500 */ \
	31, /* /soc/peripheral@50000000/adc@e000 */ \
	32, /* /soc/peripheral@50000000/clock@5000 */ \
	33, /* /soc/peripheral@50000000/dppic@17000 */ \
	34, /* /soc/peripheral@50000000/egu@1b000 */ \
	35, /* /soc/peripheral@50000000/egu@1c000 */ \
	36, /* /soc/peripheral@50000000/egu@1d000 */ \
	37, /* /soc/peripheral@50000000/egu@1e000 */ \
	38, /* /soc/peripheral@50000000/egu@1f000 */ \
	39, /* /soc/peripheral@50000000/egu@20000 */ \
	40, /* /soc/peripheral@50000000/i2c@8000 */ \
	41, /* /soc/peripheral@50000000/i2c@9000 */ \
	42, /* /soc/peripheral@50000000/i2c@a000 */ \
	43, /* /soc/peripheral@50000000/i2c@b000 */ \
	44, /* /soc/peripheral@50000000/i2s@28000 */ \
	45, /* /soc/peripheral@50000000/ipc@2a000 */ \
	46, /* /soc/peripheral@50000000/kmu@39000 */ \
	47, /* /soc/peripheral@50000000/pdm@26000 */ \
	48, /* /soc/peripheral@50000000/power@5000 */ \
	49, /* /soc/peripheral@50000000/pwm@21000 */ \
	50, /* /soc/peripheral@50000000/pwm@22000 */ \
	51, /* /soc/peripheral@50000000/pwm@23000 */ \
	52, /* /soc/peripheral@50000000/pwm@24000 */ \
	53, /* /soc/peripheral@50000000/regulator@4000 */ \
	54, /* /soc/peripheral@50000000/rtc@14000 */ \
	55, /* /soc/peripheral@50000000/rtc@15000 */ \
	56, /* /soc/peripheral@50000000/spi@8000 */ \
	57, /* /soc/peripheral@50000000/spi@9000 */ \
	58, /* /soc/peripheral@50000000/spi@a000 */ \
	59, /* /soc/peripheral@50000000/spi@b000 */ \
	60, /* /soc/peripheral@50000000/timer@f000 */ \
	61, /* /soc/peripheral@50000000/timer@10000 */ \
	62, /* /soc/peripheral@50000000/timer@11000 */ \
	63, /* /soc/peripheral@50000000/uart@8000 */ \
	64, /* /soc/peripheral@50000000/uart@9000 */ \
	65, /* /soc/peripheral@50000000/uart@a000 */ \
	66, /* /soc/peripheral@50000000/uart@b000 */ \
	67, /* /soc/peripheral@50000000/vmc@3a000 */ \
	68, /* /soc/peripheral@50000000/watchdog@18000 */ \
	69, /* /soc/peripheral@50000000/flash-controller@39000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_REG_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_RANGES_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 1342177280 /* 0x50000000 */
#define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_LENGTH 268435456 /* 0x10000000 */
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_peripheral_50000000, 0)
#define DT_N_S_soc_S_peripheral_50000000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /soc/peripheral@50000000/gpio@842500
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PATH "/soc/peripheral@50000000/gpio@842500"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FULL_NAME "gpio@842500"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_CHILD_IDX 31

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_ORD 10

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_SUPPORTS_ORDS \
	11, /* /leds/led_0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpio DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_NODELABEL_gpio0        DT_N_S_soc_S_peripheral_50000000_S_gpio_842500

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_ADDRESS 1350837504 /* 0x50842500 */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MODEL_IDX_0 "nrf-gpio"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg {8660224 /* 0x842500 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_0 8660224
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_1 768
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_port 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_port_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios 32
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /leds/led_0
 *
 * Node identifier: DT_N_S_leds_S_led_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_0_PATH "/leds/led_0"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_0_FULL_NAME "led_0"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_0_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_0_ORD 11

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_0_REQUIRES_ORDS \
	7, /* /leds */ \
	10, /* /soc/peripheral@50000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_0_EXISTS 1
#define DT_N_ALIAS_led0            DT_N_S_leds_S_led_0
#define DT_N_ALIAS_bootloader_led0 DT_N_S_leds_S_led_0
#define DT_N_ALIAS_mcuboot_led0    DT_N_S_leds_S_led_0
#define DT_N_NODELABEL_led0        DT_N_S_leds_S_led_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_0_REG_NUM 0
#define DT_N_S_leds_S_led_0_RANGES_NUM 0
#define DT_N_S_leds_S_led_0_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_0_IRQ_NUM 0
#define DT_N_S_leds_S_led_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin 31
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, gpios, 0)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, gpios, 0)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_gpios_LEN 1
#define DT_N_S_leds_S_led_0_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_0_P_label "Green LED 1"
#define DT_N_S_leds_S_led_0_P_label_STRING_TOKEN Green_LED_1
#define DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN GREEN_LED_1
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, label, 0) \
	fn(DT_N_S_leds_S_led_0, label, 1) \
	fn(DT_N_S_leds_S_led_0, label, 2) \
	fn(DT_N_S_leds_S_led_0, label, 3) \
	fn(DT_N_S_leds_S_led_0, label, 4) \
	fn(DT_N_S_leds_S_led_0, label, 5) \
	fn(DT_N_S_leds_S_led_0, label, 6) \
	fn(DT_N_S_leds_S_led_0, label, 7) \
	fn(DT_N_S_leds_S_led_0, label, 8) \
	fn(DT_N_S_leds_S_led_0, label, 9) \
	fn(DT_N_S_leds_S_led_0, label, 10)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, label, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 10)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__) \
	fn(DT_N_S_leds_S_led_0, label, 1, __VA_ARGS__) \
	fn(DT_N_S_leds_S_led_0, label, 2, __VA_ARGS__) \
	fn(DT_N_S_leds_S_led_0, label, 3, __VA_ARGS__) \
	fn(DT_N_S_leds_S_led_0, label, 4, __VA_ARGS__) \
	fn(DT_N_S_leds_S_led_0, label, 5, __VA_ARGS__) \
	fn(DT_N_S_leds_S_led_0, label, 6, __VA_ARGS__) \
	fn(DT_N_S_leds_S_led_0, label, 7, __VA_ARGS__) \
	fn(DT_N_S_leds_S_led_0, label, 8, __VA_ARGS__) \
	fn(DT_N_S_leds_S_led_0, label, 9, __VA_ARGS__) \
	fn(DT_N_S_leds_S_led_0, label, 10, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, label, 10, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_label_EXISTS 1

/*
 * Devicetree node: /pin-controller
 *
 * Node identifier: DT_N_S_pin_controller
 *
 * Binding (compatible = nordic,nrf-pinctrl):
 *   $ZEPHYR_BASE\dts\bindings\pinctrl\nordic,nrf-pinctrl.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_PATH "/pin-controller"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_FULL_NAME "pin-controller"

/* Node parent (/) identifier: */
#define DT_N_S_pin_controller_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_CHILD_IDX 3

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_ORD 12

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_SUPPORTS_ORDS \
	13, /* /pin-controller/uart0_default */ \
	15, /* /pin-controller/uart0_sleep */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pinctrl DT_N_S_pin_controller
#define DT_N_NODELABEL_pinctrl         DT_N_S_pin_controller

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_REG_NUM 0
#define DT_N_S_pin_controller_RANGES_NUM 0
#define DT_N_S_pin_controller_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_IRQ_NUM 0
#define DT_N_S_pin_controller_COMPAT_MATCHES_nordic_nrf_pinctrl 1
#define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0 "nrf-pinctrl"
#define DT_N_S_pin_controller_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_P_compatible {"nordic,nrf-pinctrl"}
#define DT_N_S_pin_controller_P_compatible_IDX_0 "nordic,nrf-pinctrl"
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pinctrl
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PINCTRL
#define DT_N_S_pin_controller_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller, compatible, 0)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller, compatible, 0)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_compatible_LEN 1
#define DT_N_S_pin_controller_P_compatible_EXISTS 1
#define DT_N_S_pin_controller_P_wakeup_source 0
#define DT_N_S_pin_controller_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart0_default
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_default_PATH "/pin-controller/uart0_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_default_FULL_NAME "uart0_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_uart0_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_default_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_default_ORD 13

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_default_REQUIRES_ORDS \
	12, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_default_SUPPORTS_ORDS \
	14, /* /pin-controller/uart0_default/group1 */ \
	63, /* /soc/peripheral@50000000/uart@8000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_default_EXISTS 1
#define DT_N_NODELABEL_uart0_default DT_N_S_pin_controller_S_uart0_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_default_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/uart0_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PATH "/pin-controller/uart0_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/uart0_default) identifier: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PARENT DT_N_S_pin_controller_S_uart0_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD 14

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_REQUIRES_ORDS \
	13, /* /pin-controller/uart0_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels {27 /* 0x1b */, 65562 /* 0x1001a */}
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0 27
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_1 65562
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart0_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_sleep_PATH "/pin-controller/uart0_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_sleep_FULL_NAME "uart0_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_uart0_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_sleep_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_sleep_ORD 15

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_sleep_REQUIRES_ORDS \
	12, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_sleep_SUPPORTS_ORDS \
	16, /* /pin-controller/uart0_sleep/group1 */ \
	63, /* /soc/peripheral@50000000/uart@8000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_sleep_EXISTS 1
#define DT_N_NODELABEL_uart0_sleep DT_N_S_pin_controller_S_uart0_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/uart0_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PATH "/pin-controller/uart0_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/uart0_sleep) identifier: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart0_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_ORD 16

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REQUIRES_ORDS \
	15, /* /pin-controller/uart0_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels {27 /* 0x1b */, 65562 /* 0x1001a */}
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0 27
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1 65562
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable_EXISTS 1

/*
 * Devicetree node: /reserved-memory
 *
 * Node identifier: DT_N_S_reserved_memory
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_PATH "/reserved-memory"

/* Node's name with unit-address: */
#define DT_N_S_reserved_memory_FULL_NAME "reserved-memory"

/* Node parent (/) identifier: */
#define DT_N_S_reserved_memory_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_reserved_memory_CHILD_IDX 7

/* Helper macros for child nodes of this node. */
#define DT_N_S_reserved_memory_FOREACH_CHILD(fn) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000)
#define DT_N_S_reserved_memory_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_s_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_modem_20016000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20020000)
#define DT_N_S_reserved_memory_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__)
#define DT_N_S_reserved_memory_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__)
#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000)
#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_s_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_modem_20016000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20020000)
#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__)
#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_ORD 17

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_SUPPORTS_ORDS \
	18, /* /reserved-memory/image_modem@20016000 */ \
	19, /* /reserved-memory/image_ns@20020000 */ \
	20, /* /reserved-memory/image_s@20000000 */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_reserved_memory_REG_NUM 0
#define DT_N_S_reserved_memory_RANGES_NUM 0
#define DT_N_S_reserved_memory_FOREACH_RANGE(fn) 
#define DT_N_S_reserved_memory_IRQ_NUM 0
#define DT_N_S_reserved_memory_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_reserved_memory_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /reserved-memory/image_modem@20016000
 *
 * Node identifier: DT_N_S_reserved_memory_S_image_modem_20016000
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_S_image_modem_20016000_PATH "/reserved-memory/image_modem@20016000"

/* Node's name with unit-address: */
#define DT_N_S_reserved_memory_S_image_modem_20016000_FULL_NAME "image_modem@20016000"

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_modem_20016000_PARENT DT_N_S_reserved_memory

/* Node's index in its parent's list of children: */
#define DT_N_S_reserved_memory_S_image_modem_20016000_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD(fn) 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_S_image_modem_20016000_ORD 18

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_S_image_modem_20016000_REQUIRES_ORDS \
	17, /* /reserved-memory */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_S_image_modem_20016000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_modem_20016000_EXISTS 1
#define DT_N_NODELABEL_sram0_modem DT_N_S_reserved_memory_S_image_modem_20016000

/* Macros for properties that are special in the specification: */
#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_VAL_ADDRESS 536961024 /* 0x20016000 */
#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_VAL_SIZE 40960 /* 0xa000 */
#define DT_N_S_reserved_memory_S_image_modem_20016000_RANGES_NUM 0
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_RANGE(fn) 
#define DT_N_S_reserved_memory_S_image_modem_20016000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_modem_20016000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_reserved_memory_S_image_modem_20016000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg {536961024 /* 0x20016000 */, 40960 /* 0xa000 */}
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_0 536961024
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_1 40960
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 0) \
	fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 1)
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 1)
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 1, __VA_ARGS__)
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 1, __VA_ARGS__)
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_EXISTS 1

/*
 * Devicetree node: /reserved-memory/image_ns@20020000
 *
 * Node identifier: DT_N_S_reserved_memory_S_image_ns_20020000
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_PATH "/reserved-memory/image_ns@20020000"

/* Node's name with unit-address: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_FULL_NAME "image_ns@20020000"

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_PARENT DT_N_S_reserved_memory

/* Node's index in its parent's list of children: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_CHILD_IDX 2

/* Helper macros for child nodes of this node. */
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD(fn) 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_ORD 19

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_REQUIRES_ORDS \
	17, /* /reserved-memory */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_EXISTS 1
#define DT_N_NODELABEL_sram0_ns DT_N_S_reserved_memory_S_image_ns_20020000

/* Macros for properties that are special in the specification: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_ADDRESS 537001984 /* 0x20020000 */
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_SIZE 131072 /* 0x20000 */
#define DT_N_S_reserved_memory_S_image_ns_20020000_RANGES_NUM 0
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_RANGE(fn) 
#define DT_N_S_reserved_memory_S_image_ns_20020000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_ns_20020000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg {537001984 /* 0x20020000 */, 131072 /* 0x20000 */}
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0 537001984
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1 131072
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 0) \
	fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 1)
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 1)
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 1, __VA_ARGS__)
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 1, __VA_ARGS__)
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_EXISTS 1

/*
 * Devicetree node: /reserved-memory/image_s@20000000
 *
 * Node identifier: DT_N_S_reserved_memory_S_image_s_20000000
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_S_image_s_20000000_PATH "/reserved-memory/image_s@20000000"

/* Node's name with unit-address: */
#define DT_N_S_reserved_memory_S_image_s_20000000_FULL_NAME "image_s@20000000"

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_s_20000000_PARENT DT_N_S_reserved_memory

/* Node's index in its parent's list of children: */
#define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD(fn) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_S_image_s_20000000_ORD 20

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_S_image_s_20000000_REQUIRES_ORDS \
	17, /* /reserved-memory */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_S_image_s_20000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_s_20000000_EXISTS 1
#define DT_N_NODELABEL_sram0_s DT_N_S_reserved_memory_S_image_s_20000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_SIZE 90112 /* 0x16000 */
#define DT_N_S_reserved_memory_S_image_s_20000000_RANGES_NUM 0
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_RANGE(fn) 
#define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_s_20000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_reserved_memory_S_image_s_20000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg {536870912 /* 0x20000000 */, 90112 /* 0x16000 */}
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0 536870912
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1 90112
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 0) \
	fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 1)
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 1)
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 1, __VA_ARGS__)
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 1, __VA_ARGS__)
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/ctrlap@50006000
 *
 * Node identifier: DT_N_S_soc_S_ctrlap_50006000
 *
 * Binding (compatible = nordic,nrf-ctrlapperi):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-ctrlapperi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ctrlap_50006000_PATH "/soc/ctrlap@50006000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ctrlap_50006000_FULL_NAME "ctrlap@50006000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ctrlap_50006000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ctrlap_50006000_CHILD_IDX 5

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ctrlap_50006000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ctrlap_50006000_ORD 21

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ctrlap_50006000_REQUIRES_ORDS \
	8, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ctrlap_50006000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ctrlap_50006000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ctrlapperi DT_N_S_soc_S_ctrlap_50006000
#define DT_N_NODELABEL_ctrlap             DT_N_S_soc_S_ctrlap_50006000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ctrlap_50006000_REG_NUM 1
#define DT_N_S_soc_S_ctrlap_50006000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ctrlap_50006000_REG_IDX_0_VAL_ADDRESS 1342201856 /* 0x50006000 */
#define DT_N_S_soc_S_ctrlap_50006000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ctrlap_50006000_RANGES_NUM 0
#define DT_N_S_soc_S_ctrlap_50006000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ctrlap_50006000_IRQ_NUM 0
#define DT_N_S_soc_S_ctrlap_50006000_COMPAT_MATCHES_nordic_nrf_ctrlapperi 1
#define DT_N_S_soc_S_ctrlap_50006000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ctrlap_50006000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_ctrlap_50006000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ctrlap_50006000_COMPAT_MODEL_IDX_0 "nrf-ctrlapperi"
#define DT_N_S_soc_S_ctrlap_50006000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ctrlap_50006000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ctrlap_50006000_P_reg {1342201856 /* 0x50006000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ctrlap_50006000_P_reg_IDX_0 1342201856
#define DT_N_S_soc_S_ctrlap_50006000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ctrlap_50006000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ctrlap_50006000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ctrlap_50006000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ctrlap_50006000, reg, 0) \
	fn(DT_N_S_soc_S_ctrlap_50006000, reg, 1)
#define DT_N_S_soc_S_ctrlap_50006000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ctrlap_50006000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ctrlap_50006000, reg, 1)
#define DT_N_S_soc_S_ctrlap_50006000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ctrlap_50006000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ctrlap_50006000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_ctrlap_50006000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ctrlap_50006000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ctrlap_50006000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_ctrlap_50006000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ctrlap_50006000_P_status "okay"
#define DT_N_S_soc_S_ctrlap_50006000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_ctrlap_50006000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ctrlap_50006000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_ctrlap_50006000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_ctrlap_50006000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ctrlap_50006000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ctrlap_50006000, status, 0) \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 1) \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 2) \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 3)
#define DT_N_S_soc_S_ctrlap_50006000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ctrlap_50006000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 3)
#define DT_N_S_soc_S_ctrlap_50006000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ctrlap_50006000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_ctrlap_50006000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ctrlap_50006000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ctrlap_50006000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_ctrlap_50006000_P_status_EXISTS 1
#define DT_N_S_soc_S_ctrlap_50006000_P_compatible {"nordic,nrf-ctrlapperi"}
#define DT_N_S_soc_S_ctrlap_50006000_P_compatible_IDX_0 "nordic,nrf-ctrlapperi"
#define DT_N_S_soc_S_ctrlap_50006000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ctrlapperi
#define DT_N_S_soc_S_ctrlap_50006000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CTRLAPPERI
#define DT_N_S_soc_S_ctrlap_50006000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ctrlap_50006000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ctrlap_50006000, compatible, 0)
#define DT_N_S_soc_S_ctrlap_50006000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ctrlap_50006000, compatible, 0)
#define DT_N_S_soc_S_ctrlap_50006000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ctrlap_50006000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ctrlap_50006000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ctrlap_50006000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ctrlap_50006000_P_compatible_LEN 1
#define DT_N_S_soc_S_ctrlap_50006000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ctrlap_50006000_P_wakeup_source 0
#define DT_N_S_soc_S_ctrlap_50006000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/ficr@ff0000
 *
 * Node identifier: DT_N_S_soc_S_ficr_ff0000
 *
 * Binding (compatible = nordic,nrf-ficr):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-ficr.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ficr_ff0000_PATH "/soc/ficr@ff0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ficr_ff0000_FULL_NAME "ficr@ff0000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ficr_ff0000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ficr_ff0000_CHILD_IDX 8

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ficr_ff0000_ORD 22

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ficr_ff0000_REQUIRES_ORDS \
	8, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ficr_ff0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ficr_ff0000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ficr DT_N_S_soc_S_ficr_ff0000
#define DT_N_NODELABEL_ficr         DT_N_S_soc_S_ficr_ff0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ficr_ff0000_REG_NUM 1
#define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_ADDRESS 16711680 /* 0xff0000 */
#define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ficr_ff0000_RANGES_NUM 0
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ficr_ff0000_IRQ_NUM 0
#define DT_N_S_soc_S_ficr_ff0000_COMPAT_MATCHES_nordic_nrf_ficr 1
#define DT_N_S_soc_S_ficr_ff0000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_ficr_ff0000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_COMPAT_MODEL_IDX_0 "nrf-ficr"
#define DT_N_S_soc_S_ficr_ff0000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ficr_ff0000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ficr_ff0000_P_reg {16711680 /* 0xff0000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_0 16711680
#define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, reg, 0) \
	fn(DT_N_S_soc_S_ficr_ff0000, reg, 1)
#define DT_N_S_soc_S_ficr_ff0000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ficr_ff0000, reg, 1)
#define DT_N_S_soc_S_ficr_ff0000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ficr_ff0000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ff0000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ficr_ff0000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ff0000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_status "okay"
#define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, status, 0) \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 1) \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 2) \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 3)
#define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 3)
#define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ficr_ff0000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ff0000_P_status_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_compatible {"nordic,nrf-ficr"}
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0 "nordic,nrf-ficr"
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ficr
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_FICR
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0)
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0)
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_LEN 1
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_wakeup_source 0
#define DT_N_S_soc_S_ficr_ff0000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/interrupt-controller@e000e100
 *
 * Node identifier: DT_N_S_soc_S_interrupt_controller_e000e100
 *
 * Binding (compatible = arm,v8m-nvic):
 *   $ZEPHYR_BASE\dts\bindings\interrupt-controller\arm,v8m-nvic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PATH "/soc/interrupt-controller@e000e100"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME "interrupt-controller@e000e100"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD 23

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS \
	8, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \
	24, /* /soc/gpiote@5000d000 */ \
	26, /* /soc/spu@50003000 */ \
	30, /* /soc/crypto@50840000/crypto@50841000 */ \
	31, /* /soc/peripheral@50000000/adc@e000 */ \
	32, /* /soc/peripheral@50000000/clock@5000 */ \
	34, /* /soc/peripheral@50000000/egu@1b000 */ \
	35, /* /soc/peripheral@50000000/egu@1c000 */ \
	36, /* /soc/peripheral@50000000/egu@1d000 */ \
	37, /* /soc/peripheral@50000000/egu@1e000 */ \
	38, /* /soc/peripheral@50000000/egu@1f000 */ \
	39, /* /soc/peripheral@50000000/egu@20000 */ \
	40, /* /soc/peripheral@50000000/i2c@8000 */ \
	41, /* /soc/peripheral@50000000/i2c@9000 */ \
	42, /* /soc/peripheral@50000000/i2c@a000 */ \
	43, /* /soc/peripheral@50000000/i2c@b000 */ \
	44, /* /soc/peripheral@50000000/i2s@28000 */ \
	45, /* /soc/peripheral@50000000/ipc@2a000 */ \
	46, /* /soc/peripheral@50000000/kmu@39000 */ \
	47, /* /soc/peripheral@50000000/pdm@26000 */ \
	48, /* /soc/peripheral@50000000/power@5000 */ \
	49, /* /soc/peripheral@50000000/pwm@21000 */ \
	50, /* /soc/peripheral@50000000/pwm@22000 */ \
	51, /* /soc/peripheral@50000000/pwm@23000 */ \
	52, /* /soc/peripheral@50000000/pwm@24000 */ \
	54, /* /soc/peripheral@50000000/rtc@14000 */ \
	55, /* /soc/peripheral@50000000/rtc@15000 */ \
	56, /* /soc/peripheral@50000000/spi@8000 */ \
	57, /* /soc/peripheral@50000000/spi@9000 */ \
	58, /* /soc/peripheral@50000000/spi@a000 */ \
	59, /* /soc/peripheral@50000000/spi@b000 */ \
	60, /* /soc/peripheral@50000000/timer@f000 */ \
	61, /* /soc/peripheral@50000000/timer@10000 */ \
	62, /* /soc/peripheral@50000000/timer@11000 */ \
	63, /* /soc/peripheral@50000000/uart@8000 */ \
	64, /* /soc/peripheral@50000000/uart@9000 */ \
	65, /* /soc/peripheral@50000000/uart@a000 */ \
	66, /* /soc/peripheral@50000000/uart@b000 */ \
	68, /* /soc/peripheral@50000000/watchdog@18000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1
#define DT_N_INST_0_arm_v8m_nvic DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_NODELABEL_nvic      DT_N_S_soc_S_interrupt_controller_e000e100

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0 "v8m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 0) \
	fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 1)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 1)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 3
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v8m-nvic"}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v8m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_TOKEN arm_v8m_nvic
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_V8M_NVIC
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/gpiote@5000d000
 *
 * Node identifier: DT_N_S_soc_S_gpiote_5000d000
 *
 * Binding (compatible = nordic,nrf-gpiote):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpiote.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_gpiote_5000d000_PATH "/soc/gpiote@5000d000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_gpiote_5000d000_FULL_NAME "gpiote@5000d000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpiote_5000d000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_gpiote_5000d000_CHILD_IDX 6

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpiote_5000d000_ORD 24

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpiote_5000d000_REQUIRES_ORDS \
	8, /* /soc */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpiote_5000d000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpiote_5000d000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_5000d000
#define DT_N_NODELABEL_gpiote         DT_N_S_soc_S_gpiote_5000d000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_gpiote_5000d000_REG_NUM 1
#define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_ADDRESS 1342230528 /* 0x5000d000 */
#define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_gpiote_5000d000_RANGES_NUM 0
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_NUM 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq 13
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority 5
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MATCHES_nordic_nrf_gpiote 1
#define DT_N_S_soc_S_gpiote_5000d000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MODEL_IDX_0 "nrf-gpiote"
#define DT_N_S_soc_S_gpiote_5000d000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_gpiote_5000d000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_gpiote_5000d000_P_reg {1342230528 /* 0x5000d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_0 1342230528
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, reg, 0) \
	fn(DT_N_S_soc_S_gpiote_5000d000, reg, 1)
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpiote_5000d000, reg, 1)
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpiote_5000d000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpiote_5000d000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts {13 /* 0xd */, 5 /* 0x5 */}
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_0 13
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_1 5
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 0) \
	fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 1)
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 1)
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpiote_5000d000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_status "okay"
#define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0) \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 1) \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 2) \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 3)
#define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 3)
#define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpiote_5000d000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_status_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible {"nordic,nrf-gpiote"}
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0 "nordic,nrf-gpiote"
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0)
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0)
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_LEN 1
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_wakeup_source 0
#define DT_N_S_soc_S_gpiote_5000d000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/memory@20000000
 *
 * Node identifier: DT_N_S_soc_S_memory_20000000
 *
 * Binding (compatible = mmio-sram):
 *   $ZEPHYR_BASE\dts\bindings\sram\mmio-sram.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_20000000_PATH "/soc/memory@20000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_20000000_FULL_NAME "memory@20000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_20000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_20000000_CHILD_IDX 2

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_20000000_ORD 25

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS \
	8, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_20000000_EXISTS 1
#define DT_N_INST_0_mmio_sram DT_N_S_soc_S_memory_20000000
#define DT_N_NODELABEL_sram0  DT_N_S_soc_S_memory_20000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_20000000_REG_NUM 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_memory_20000000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_20000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_20000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_20000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_20000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0 536870912
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_20000000, reg, 0) \
	fn(DT_N_S_soc_S_memory_20000000, reg, 1)
#define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_20000000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_20000000, reg, 1)
#define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_20000000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_memory_20000000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_20000000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_20000000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible {"mmio-sram"}
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0 "mmio-sram"
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_TOKEN mmio_sram
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_20000000, compatible, 0)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_20000000, compatible, 0)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_20000000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/spu@50003000
 *
 * Node identifier: DT_N_S_soc_S_spu_50003000
 *
 * Binding (compatible = nordic,nrf-spu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-spu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spu_50003000_PATH "/soc/spu@50003000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spu_50003000_FULL_NAME "spu@50003000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spu_50003000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spu_50003000_CHILD_IDX 7

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spu_50003000_ORD 26

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spu_50003000_REQUIRES_ORDS \
	8, /* /soc */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spu_50003000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spu_50003000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_spu DT_N_S_soc_S_spu_50003000
#define DT_N_NODELABEL_spu         DT_N_S_soc_S_spu_50003000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spu_50003000_REG_NUM 1
#define DT_N_S_soc_S_spu_50003000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_ADDRESS 1342189568 /* 0x50003000 */
#define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_spu_50003000_RANGES_NUM 0
#define DT_N_S_soc_S_spu_50003000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spu_50003000_IRQ_NUM 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq 3
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_COMPAT_MATCHES_nordic_nrf_spu 1
#define DT_N_S_soc_S_spu_50003000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_spu_50003000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_COMPAT_MODEL_IDX_0 "nrf-spu"
#define DT_N_S_soc_S_spu_50003000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spu_50003000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_spu_50003000_P_reg {1342189568 /* 0x50003000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_spu_50003000_P_reg_IDX_0 1342189568
#define DT_N_S_soc_S_spu_50003000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_spu_50003000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, reg, 0) \
	fn(DT_N_S_soc_S_spu_50003000, reg, 1)
#define DT_N_S_soc_S_spu_50003000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spu_50003000, reg, 1)
#define DT_N_S_soc_S_spu_50003000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spu_50003000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spu_50003000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_interrupts {3 /* 0x3 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_0 3
#define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, interrupts, 0) \
	fn(DT_N_S_soc_S_spu_50003000, interrupts, 1)
#define DT_N_S_soc_S_spu_50003000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spu_50003000, interrupts, 1)
#define DT_N_S_soc_S_spu_50003000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spu_50003000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spu_50003000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_status "okay"
#define DT_N_S_soc_S_spu_50003000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_spu_50003000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spu_50003000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_spu_50003000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_spu_50003000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, status, 0) \
	fn(DT_N_S_soc_S_spu_50003000, status, 1) \
	fn(DT_N_S_soc_S_spu_50003000, status, 2) \
	fn(DT_N_S_soc_S_spu_50003000, status, 3)
#define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spu_50003000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spu_50003000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spu_50003000, status, 3)
#define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spu_50003000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spu_50003000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spu_50003000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spu_50003000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spu_50003000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spu_50003000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_status_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_compatible {"nordic,nrf-spu"}
#define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0 "nordic,nrf-spu"
#define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spu
#define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPU
#define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, compatible, 0)
#define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, compatible, 0)
#define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_compatible_LEN 1
#define DT_N_S_soc_S_spu_50003000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_wakeup_source 0
#define DT_N_S_soc_S_spu_50003000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/timer@e000e010
 *
 * Node identifier: DT_N_S_soc_S_timer_e000e010
 *
 * Binding (compatible = arm,armv8m-systick):
 *   $ZEPHYR_BASE\dts\bindings\timer\arm,armv8m-systick.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timer_e000e010_PATH "/soc/timer@e000e010"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME "timer@e000e010"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timer_e000e010_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_e000e010_ORD 27

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \
	8, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_e000e010_EXISTS 1
#define DT_N_INST_0_arm_armv8m_systick DT_N_S_soc_S_timer_e000e010
#define DT_N_NODELABEL_systick         DT_N_S_soc_S_timer_e000e010

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timer_e000e010_REG_NUM 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */
#define DT_N_S_soc_S_timer_e000e010_RANGES_NUM 0
#define DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0 "armv8m-systick"
#define DT_N_S_soc_S_timer_e000e010_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, reg, 0) \
	fn(DT_N_S_soc_S_timer_e000e010, reg, 1)
#define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, reg, 1)
#define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timer_e000e010, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_status "disabled"
#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, status, 0) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 1) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 2) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 3) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 4) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 5) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 6) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 7)
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 7)
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timer_e000e010, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timer_e000e010, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_status_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv8m-systick"}
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv8m-systick"
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_systick
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_SYSTICK
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source 0
#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/uicr@ff8000
 *
 * Node identifier: DT_N_S_soc_S_uicr_ff8000
 *
 * Binding (compatible = nordic,nrf-uicr):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-uicr.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_uicr_ff8000_PATH "/soc/uicr@ff8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_uicr_ff8000_FULL_NAME "uicr@ff8000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uicr_ff8000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_uicr_ff8000_CHILD_IDX 9

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_uicr_ff8000_ORD 28

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_uicr_ff8000_REQUIRES_ORDS \
	8, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_uicr_ff8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uicr_ff8000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_uicr DT_N_S_soc_S_uicr_ff8000
#define DT_N_NODELABEL_uicr         DT_N_S_soc_S_uicr_ff8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_uicr_ff8000_REG_NUM 1
#define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_ADDRESS 16744448 /* 0xff8000 */
#define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uicr_ff8000_RANGES_NUM 0
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_uicr_ff8000_IRQ_NUM 0
#define DT_N_S_soc_S_uicr_ff8000_COMPAT_MATCHES_nordic_nrf_uicr 1
#define DT_N_S_soc_S_uicr_ff8000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_uicr_ff8000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_COMPAT_MODEL_IDX_0 "nrf-uicr"
#define DT_N_S_soc_S_uicr_ff8000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_uicr_ff8000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_uicr_ff8000_P_reg {16744448 /* 0xff8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_0 16744448
#define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, reg, 0) \
	fn(DT_N_S_soc_S_uicr_ff8000, reg, 1)
#define DT_N_S_soc_S_uicr_ff8000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uicr_ff8000, reg, 1)
#define DT_N_S_soc_S_uicr_ff8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_uicr_ff8000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_ff8000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uicr_ff8000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_ff8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_status "okay"
#define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, status, 0) \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 1) \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 2) \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 3)
#define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 3)
#define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uicr_ff8000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_ff8000_P_status_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_compatible {"nordic,nrf-uicr"}
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0 "nordic,nrf-uicr"
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uicr
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UICR
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0)
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0)
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_LEN 1
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_wakeup_source 0
#define DT_N_S_soc_S_uicr_ff8000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/crypto@50840000
 *
 * Node identifier: DT_N_S_soc_S_crypto_50840000
 *
 * Binding (compatible = nordic,nrf-cc310):
 *   $ZEPHYR_BASE\dts\bindings\crypto\nordic,nrf-cc310.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_crypto_50840000_PATH "/soc/crypto@50840000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_crypto_50840000_FULL_NAME "crypto@50840000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_crypto_50840000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_crypto_50840000_CHILD_IDX 4

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000)
#define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000)
#define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000)
#define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000)
#define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_crypto_50840000_ORD 29

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_crypto_50840000_REQUIRES_ORDS \
	8, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_crypto_50840000_SUPPORTS_ORDS \
	30, /* /soc/crypto@50840000/crypto@50841000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_crypto_50840000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_cc310 DT_N_S_soc_S_crypto_50840000
#define DT_N_NODELABEL_cryptocell    DT_N_S_soc_S_crypto_50840000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_crypto_50840000_REG_NUM 1
#define DT_N_S_soc_S_crypto_50840000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_REG_IDX_0_VAL_ADDRESS 1350828032 /* 0x50840000 */
#define DT_N_S_soc_S_crypto_50840000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_crypto_50840000_RANGES_NUM 0
#define DT_N_S_soc_S_crypto_50840000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_crypto_50840000_IRQ_NUM 0
#define DT_N_S_soc_S_crypto_50840000_COMPAT_MATCHES_nordic_nrf_cc310 1
#define DT_N_S_soc_S_crypto_50840000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_crypto_50840000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_COMPAT_MODEL_IDX_0 "nrf-cc310"
#define DT_N_S_soc_S_crypto_50840000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_crypto_50840000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_crypto_50840000_P_reg {1350828032 /* 0x50840000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_0 1350828032
#define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_crypto_50840000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50840000, reg, 0) \
	fn(DT_N_S_soc_S_crypto_50840000, reg, 1)
#define DT_N_S_soc_S_crypto_50840000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50840000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000, reg, 1)
#define DT_N_S_soc_S_crypto_50840000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50840000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_crypto_50840000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50840000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_P_reg_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_P_status "okay"
#define DT_N_S_soc_S_crypto_50840000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_crypto_50840000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_crypto_50840000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_crypto_50840000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_crypto_50840000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_crypto_50840000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50840000, status, 0) \
	fn(DT_N_S_soc_S_crypto_50840000, status, 1) \
	fn(DT_N_S_soc_S_crypto_50840000, status, 2) \
	fn(DT_N_S_soc_S_crypto_50840000, status, 3)
#define DT_N_S_soc_S_crypto_50840000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50840000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000, status, 3)
#define DT_N_S_soc_S_crypto_50840000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50840000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_crypto_50840000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_crypto_50840000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_crypto_50840000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50840000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_P_status_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_P_compatible {"nordic,nrf-cc310"}
#define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_0 "nordic,nrf-cc310"
#define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_cc310
#define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CC310
#define DT_N_S_soc_S_crypto_50840000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50840000, compatible, 0)
#define DT_N_S_soc_S_crypto_50840000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50840000, compatible, 0)
#define DT_N_S_soc_S_crypto_50840000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50840000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50840000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_P_compatible_LEN 1
#define DT_N_S_soc_S_crypto_50840000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_P_wakeup_source 0
#define DT_N_S_soc_S_crypto_50840000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/crypto@50840000/crypto@50841000
 *
 * Node identifier: DT_N_S_soc_S_crypto_50840000_S_crypto_50841000
 *
 * Binding (compatible = arm,cryptocell-310):
 *   $ZEPHYR_BASE\dts\bindings\crypto\arm,cryptocell-310.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_PATH "/soc/crypto@50840000/crypto@50841000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_FULL_NAME "crypto@50841000"

/* Node parent (/soc/crypto@50840000) identifier: */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_PARENT DT_N_S_soc_S_crypto_50840000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_ORD 30

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_REQUIRES_ORDS \
	23, /* /soc/interrupt-controller@e000e100 */ \
	29, /* /soc/crypto@50840000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_EXISTS 1
#define DT_N_INST_0_arm_cryptocell_310 DT_N_S_soc_S_crypto_50840000_S_crypto_50841000
#define DT_N_NODELABEL_cryptocell310   DT_N_S_soc_S_crypto_50840000_S_crypto_50841000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_REG_NUM 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_REG_IDX_0_VAL_ADDRESS 1350832128 /* 0x50841000 */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_RANGES_NUM 0
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_IRQ_NUM 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_IRQ_IDX_0_VAL_irq 64
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_COMPAT_MATCHES_arm_cryptocell_310 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_COMPAT_MODEL_IDX_0 "cryptocell-310"
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_reg {1350832128 /* 0x50841000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_reg_IDX_0 1350832128
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, reg, 0) \
	fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, reg, 1)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, reg, 1)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_reg_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_interrupts {64 /* 0x40 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_interrupts_IDX_0 64
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, interrupts, 0) \
	fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, interrupts, 1)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, interrupts, 1)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_compatible {"arm,cryptocell-310"}
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_compatible_IDX_0 "arm,cryptocell-310"
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_compatible_IDX_0_STRING_TOKEN arm_cryptocell_310
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CRYPTOCELL_310
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, compatible, 0)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, compatible, 0)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_compatible_LEN 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_wakeup_source 0
#define DT_N_S_soc_S_crypto_50840000_S_crypto_50841000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/adc@e000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_adc_e000
 *
 * Binding (compatible = nordic,nrf-saadc):
 *   $ZEPHYR_BASE\dts\bindings\adc\nordic,nrf-saadc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PATH "/soc/peripheral@50000000/adc@e000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FULL_NAME "adc@e000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_ORD 31

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_saadc DT_N_S_soc_S_peripheral_50000000_S_adc_e000
#define DT_N_NODELABEL_adc           DT_N_S_soc_S_peripheral_50000000_S_adc_e000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_ADDRESS 1342234624 /* 0x5000e000 */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq 14
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MATCHES_nordic_nrf_saadc 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MODEL_IDX_0 "nrf-saadc"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg {57344 /* 0xe000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_0 57344
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts {14 /* 0xe */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_0 14
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible {"nordic,nrf-saadc"}
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0 "nordic,nrf-saadc"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_saadc
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SAADC
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/clock@5000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_clock_5000
 *
 * Binding (compatible = nordic,nrf-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\nordic,nrf-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PATH "/soc/peripheral@50000000/clock@5000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FULL_NAME "clock@5000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_CHILD_IDX 34

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_ORD 32

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_clock DT_N_S_soc_S_peripheral_50000000_S_clock_5000
#define DT_N_NODELABEL_clock         DT_N_S_soc_S_peripheral_50000000_S_clock_5000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq 5
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MATCHES_nordic_nrf_clock 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MODEL_IDX_0 "nrf-clock"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_0 20480
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_0 5
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible {"nordic,nrf-clock"}
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0 "nordic,nrf-clock"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_clock
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CLOCK
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/dppic@17000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_dppic_17000
 *
 * Binding (compatible = nordic,nrf-dppic):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-dppic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PATH "/soc/peripheral@50000000/dppic@17000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FULL_NAME "dppic@17000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_CHILD_IDX 2

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_ORD 33

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_dppic DT_N_S_soc_S_peripheral_50000000_S_dppic_17000
#define DT_N_NODELABEL_dppic         DT_N_S_soc_S_peripheral_50000000_S_dppic_17000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_ADDRESS 1342271488 /* 0x50017000 */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MATCHES_nordic_nrf_dppic 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MODEL_IDX_0 "nrf-dppic"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg {94208 /* 0x17000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_0 94208
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible {"nordic,nrf-dppic"}
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0 "nordic,nrf-dppic"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dppic
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DPPIC
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1b000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PATH "/soc/peripheral@50000000/egu@1b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FULL_NAME "egu@1b000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_CHILD_IDX 3

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_ORD 34

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1b000
#define DT_N_NODELABEL_egu0        DT_N_S_soc_S_peripheral_50000000_S_egu_1b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_ADDRESS 1342287872 /* 0x5001b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq 27
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg {110592 /* 0x1b000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_0 110592
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts {27 /* 0x1b */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_0 27
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1c000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1c000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PATH "/soc/peripheral@50000000/egu@1c000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FULL_NAME "egu@1c000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_CHILD_IDX 4

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_ORD 35

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1c000
#define DT_N_NODELABEL_egu1        DT_N_S_soc_S_peripheral_50000000_S_egu_1c000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_ADDRESS 1342291968 /* 0x5001c000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq 28
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg {114688 /* 0x1c000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_0 114688
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts {28 /* 0x1c */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_0 28
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1d000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1d000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PATH "/soc/peripheral@50000000/egu@1d000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FULL_NAME "egu@1d000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_CHILD_IDX 5

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_ORD 36

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1d000
#define DT_N_NODELABEL_egu2        DT_N_S_soc_S_peripheral_50000000_S_egu_1d000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_ADDRESS 1342296064 /* 0x5001d000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq 29
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg {118784 /* 0x1d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_0 118784
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts {29 /* 0x1d */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_0 29
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1e000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1e000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PATH "/soc/peripheral@50000000/egu@1e000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FULL_NAME "egu@1e000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_CHILD_IDX 6

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_ORD 37

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1e000
#define DT_N_NODELABEL_egu3        DT_N_S_soc_S_peripheral_50000000_S_egu_1e000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_ADDRESS 1342300160 /* 0x5001e000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq 30
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg {122880 /* 0x1e000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_0 122880
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts {30 /* 0x1e */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_0 30
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1f000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1f000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PATH "/soc/peripheral@50000000/egu@1f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FULL_NAME "egu@1f000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_CHILD_IDX 7

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_ORD 38

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_EXISTS 1
#define DT_N_INST_4_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1f000
#define DT_N_NODELABEL_egu4        DT_N_S_soc_S_peripheral_50000000_S_egu_1f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_ADDRESS 1342304256 /* 0x5001f000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq 31
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg {126976 /* 0x1f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_0 126976
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts {31 /* 0x1f */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_0 31
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@20000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_20000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PATH "/soc/peripheral@50000000/egu@20000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FULL_NAME "egu@20000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_CHILD_IDX 8

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_ORD 39

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_EXISTS 1
#define DT_N_INST_5_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_20000
#define DT_N_NODELABEL_egu5        DT_N_S_soc_S_peripheral_50000000_S_egu_20000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_ADDRESS 1342308352 /* 0x50020000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq 32
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg {131072 /* 0x20000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_0 131072
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts {32 /* 0x20 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_0 32
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_8000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PATH "/soc/peripheral@50000000/i2c@8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FULL_NAME "i2c@8000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_CHILD_IDX 19

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_ORD 40

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_8000
#define DT_N_NODELABEL_i2c0         DT_N_S_soc_S_peripheral_50000000_S_i2c_8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_flash_buf_max_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_clock_frequency 100000
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@9000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PATH "/soc/peripheral@50000000/i2c@9000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FULL_NAME "i2c@9000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_CHILD_IDX 20

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_ORD 41

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
#define DT_N_NODELABEL_i2c1         DT_N_S_soc_S_peripheral_50000000_S_i2c_9000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_flash_buf_max_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_clock_frequency 100000
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_a000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PATH "/soc/peripheral@50000000/i2c@a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FULL_NAME "i2c@a000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_CHILD_IDX 21

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_ORD 42

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_a000
#define DT_N_NODELABEL_i2c2         DT_N_S_soc_S_peripheral_50000000_S_i2c_a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_REG_IDX_0_VAL_ADDRESS 1342218240 /* 0x5000a000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_VAL_irq 10
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_zephyr_flash_buf_max_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_IDX_0 40960
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_IDX_0 10
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_clock_frequency 100000
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_a000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_b000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PATH "/soc/peripheral@50000000/i2c@b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FULL_NAME "i2c@b000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_CHILD_IDX 22

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_ORD 43

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_b000
#define DT_N_NODELABEL_i2c3         DT_N_S_soc_S_peripheral_50000000_S_i2c_b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_flash_buf_max_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_clock_frequency 100000
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2s@28000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2s_28000
 *
 * Binding (compatible = nordic,nrf-i2s):
 *   $ZEPHYR_BASE\dts\bindings\i2s\nordic,nrf-i2s.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PATH "/soc/peripheral@50000000/i2s@28000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FULL_NAME "i2s@28000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_CHILD_IDX 10

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_ORD 44

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_i2s DT_N_S_soc_S_peripheral_50000000_S_i2s_28000
#define DT_N_NODELABEL_i2s0        DT_N_S_soc_S_peripheral_50000000_S_i2s_28000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_ADDRESS 1342341120 /* 0x50028000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq 40
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MATCHES_nordic_nrf_i2s 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MODEL_IDX_0 "nrf-i2s"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg {163840 /* 0x28000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_0 163840
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts {40 /* 0x28 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_0 40
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 7) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 8) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 9) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 10) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 11)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 11)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 11, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 11, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible {"nordic,nrf-i2s"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0 "nordic,nrf-i2s"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_i2s
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_I2S
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/ipc@2a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000
 *
 * Binding (compatible = nordic,nrf-ipc):
 *   $ZEPHYR_BASE\dts\bindings\ipm\nordic,nrf-ipc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_PATH "/soc/peripheral@50000000/ipc@2a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FULL_NAME "ipc@2a000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_CHILD_IDX 9

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_ORD 45

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ipc DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000
#define DT_N_NODELABEL_ipc         DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_IDX_0_VAL_ADDRESS 1342349312 /* 0x5002a000 */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq 42
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_COMPAT_MATCHES_nordic_nrf_ipc 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_COMPAT_MODEL_IDX_0 "nrf-ipc"
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg {172032 /* 0x2a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_IDX_0 172032
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts {42 /* 0x2a */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_IDX_0 42
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible {"nordic,nrf-ipc"}
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_IDX_0 "nordic,nrf-ipc"
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ipc
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_IPC
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/kmu@39000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_kmu_39000
 *
 * Binding (compatible = nordic,nrf-kmu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-kmu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PATH "/soc/peripheral@50000000/kmu@39000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FULL_NAME "kmu@39000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_CHILD_IDX 11

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_ORD 46

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_kmu DT_N_S_soc_S_peripheral_50000000_S_kmu_39000
#define DT_N_NODELABEL_kmu         DT_N_S_soc_S_peripheral_50000000_S_kmu_39000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq 57
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MATCHES_nordic_nrf_kmu 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MODEL_IDX_0 "nrf-kmu"
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_0 233472
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts {57 /* 0x39 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_0 57
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible {"nordic,nrf-kmu"}
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0 "nordic,nrf-kmu"
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_kmu
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_KMU
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pdm@26000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pdm_26000
 *
 * Binding (compatible = nordic,nrf-pdm):
 *   $ZEPHYR_BASE\dts\bindings\audio\nordic,nrf-pdm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PATH "/soc/peripheral@50000000/pdm@26000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FULL_NAME "pdm@26000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_CHILD_IDX 12

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_ORD 47

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pdm DT_N_S_soc_S_peripheral_50000000_S_pdm_26000
#define DT_N_NODELABEL_pdm0        DT_N_S_soc_S_peripheral_50000000_S_pdm_26000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_ADDRESS 1342332928 /* 0x50026000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq 38
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MATCHES_nordic_nrf_pdm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MODEL_IDX_0 "nrf-pdm"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg {155648 /* 0x26000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_0 155648
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts {38 /* 0x26 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_0 38
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 7) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 8) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 9) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 10) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 11)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 11)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 11, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 11, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_queue_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_queue_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible {"nordic,nrf-pdm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0 "nordic,nrf-pdm"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pdm
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PDM
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/power@5000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000
 *
 * Binding (compatible = nordic,nrf-power):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-power.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PATH "/soc/peripheral@50000000/power@5000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FULL_NAME "power@5000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_CHILD_IDX 35

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_ORD 48

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_power DT_N_S_soc_S_peripheral_50000000_S_power_5000
#define DT_N_NODELABEL_power         DT_N_S_soc_S_peripheral_50000000_S_power_5000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq 5
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MATCHES_nordic_nrf_power 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MODEL_IDX_0 "nrf-power"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_0 20480
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_0 5
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible {"nordic,nrf-power"}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0 "nordic,nrf-power"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_power
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_POWER
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@21000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_21000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PATH "/soc/peripheral@50000000/pwm@21000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FULL_NAME "pwm@21000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_CHILD_IDX 27

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_ORD 49

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_21000
#define DT_N_NODELABEL_pwm0        DT_N_S_soc_S_peripheral_50000000_S_pwm_21000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_ADDRESS 1342312448 /* 0x50021000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq 33
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg {135168 /* 0x21000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_0 135168
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts {33 /* 0x21 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_0 33
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@22000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_22000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PATH "/soc/peripheral@50000000/pwm@22000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FULL_NAME "pwm@22000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_CHILD_IDX 28

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_ORD 50

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_22000
#define DT_N_NODELABEL_pwm1        DT_N_S_soc_S_peripheral_50000000_S_pwm_22000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_ADDRESS 1342316544 /* 0x50022000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq 34
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg {139264 /* 0x22000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_0 139264
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts {34 /* 0x22 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_0 34
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@23000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_23000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PATH "/soc/peripheral@50000000/pwm@23000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FULL_NAME "pwm@23000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_CHILD_IDX 29

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_ORD 51

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_23000
#define DT_N_NODELABEL_pwm2        DT_N_S_soc_S_peripheral_50000000_S_pwm_23000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_ADDRESS 1342320640 /* 0x50023000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq 35
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg {143360 /* 0x23000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_0 143360
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts {35 /* 0x23 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_0 35
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@24000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_24000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PATH "/soc/peripheral@50000000/pwm@24000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FULL_NAME "pwm@24000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_CHILD_IDX 30

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_ORD 52

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_24000
#define DT_N_NODELABEL_pwm3        DT_N_S_soc_S_peripheral_50000000_S_pwm_24000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_ADDRESS 1342324736 /* 0x50024000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq 36
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg {147456 /* 0x24000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_0 147456
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts {36 /* 0x24 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_0 36
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/regulator@4000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000
 *
 * Binding (compatible = nordic,nrf-regulators):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-regulators.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PATH "/soc/peripheral@50000000/regulator@4000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FULL_NAME "regulator@4000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_CHILD_IDX 13

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_ORD 53

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_regulators DT_N_S_soc_S_peripheral_50000000_S_regulator_4000
#define DT_N_NODELABEL_regulators         DT_N_S_soc_S_peripheral_50000000_S_regulator_4000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_ADDRESS 1342193664 /* 0x50004000 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MATCHES_nordic_nrf_regulators 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MODEL_IDX_0 "nrf-regulators"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg {16384 /* 0x4000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_0 16384
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible {"nordic,nrf-regulators"}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0 "nordic,nrf-regulators"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_regulators
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_REGULATORS
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/rtc@14000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_14000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PATH "/soc/peripheral@50000000/rtc@14000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FULL_NAME "rtc@14000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_CHILD_IDX 32

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_ORD 54

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_14000
#define DT_N_NODELABEL_rtc0        DT_N_S_soc_S_peripheral_50000000_S_rtc_14000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_ADDRESS 1342259200 /* 0x50014000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq 20
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MODEL_IDX_0 "nrf-rtc"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg {81920 /* 0x14000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_0 81920
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_cc_num 4
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency 32768
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts {20 /* 0x14 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_0 20
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/rtc@15000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_15000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PATH "/soc/peripheral@50000000/rtc@15000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FULL_NAME "rtc@15000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_CHILD_IDX 33

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_ORD 55

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_15000
#define DT_N_NODELABEL_rtc1        DT_N_S_soc_S_peripheral_50000000_S_rtc_15000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_ADDRESS 1342263296 /* 0x50015000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq 21
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MODEL_IDX_0 "nrf-rtc"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg {86016 /* 0x15000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_0 86016
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_cc_num 4
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency 32768
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts {21 /* 0x15 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_0 21
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_8000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PATH "/soc/peripheral@50000000/spi@8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FULL_NAME "spi@8000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_CHILD_IDX 23

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_ORD 56

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_8000
#define DT_N_NODELABEL_spi0         DT_N_S_soc_S_peripheral_50000000_S_spi_8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_miso_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_miso_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_miso_pull_down 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_miso_pull_down_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_rx_delay_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_rx_delay_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@9000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_9000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PATH "/soc/peripheral@50000000/spi@9000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FULL_NAME "spi@9000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_CHILD_IDX 24

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_ORD 57

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_9000
#define DT_N_NODELABEL_spi1         DT_N_S_soc_S_peripheral_50000000_S_spi_9000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_miso_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_miso_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_miso_pull_down 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_miso_pull_down_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_rx_delay_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_rx_delay_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_a000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PATH "/soc/peripheral@50000000/spi@a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FULL_NAME "spi@a000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_CHILD_IDX 25

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_ORD 58

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_a000
#define DT_N_NODELABEL_spi2         DT_N_S_soc_S_peripheral_50000000_S_spi_a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_ADDRESS 1342218240 /* 0x5000a000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq 10
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_miso_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_miso_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_miso_pull_down 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_miso_pull_down_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_0 40960
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_0 10
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_b000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PATH "/soc/peripheral@50000000/spi@b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FULL_NAME "spi@b000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_CHILD_IDX 26

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_ORD 59

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_b000
#define DT_N_NODELABEL_spi3         DT_N_S_soc_S_peripheral_50000000_S_spi_b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_miso_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_miso_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_miso_pull_down 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_miso_pull_down_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_rx_delay_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_rx_delay_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/timer@f000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_f000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PATH "/soc/peripheral@50000000/timer@f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FULL_NAME "timer@f000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_CHILD_IDX 37

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_ORD 60

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_f000
#define DT_N_NODELABEL_timer0        DT_N_S_soc_S_peripheral_50000000_S_timer_f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_ADDRESS 1342238720 /* 0x5000f000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq 15
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg {61440 /* 0xf000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_0 61440
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts {15 /* 0xf */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_0 15
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/timer@10000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_10000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PATH "/soc/peripheral@50000000/timer@10000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FULL_NAME "timer@10000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_CHILD_IDX 38

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_ORD 61

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_10000
#define DT_N_NODELABEL_timer1        DT_N_S_soc_S_peripheral_50000000_S_timer_10000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_ADDRESS 1342242816 /* 0x50010000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq 16
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg {65536 /* 0x10000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_0 65536
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts {16 /* 0x10 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_0 16
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/timer@11000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_11000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PATH "/soc/peripheral@50000000/timer@11000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FULL_NAME "timer@11000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_CHILD_IDX 39

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_ORD 62

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_11000
#define DT_N_NODELABEL_timer2        DT_N_S_soc_S_peripheral_50000000_S_timer_11000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_ADDRESS 1342246912 /* 0x50011000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq 17
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg {69632 /* 0x11000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_0 69632
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts {17 /* 0x11 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_0 17
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_8000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PATH "/soc/peripheral@50000000/uart@8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FULL_NAME "uart@8000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_CHILD_IDX 15

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_ORD 63

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	13, /* /pin-controller/uart0_default */ \
	15, /* /pin-controller/uart0_sleep */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_N_NODELABEL_uart0         DT_N_S_soc_S_peripheral_50000000_S_uart_8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NUM 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart0_default
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart0_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed 115200
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_ENUM_IDX 12
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_rx_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_rx_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_cts_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_cts_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart0_default
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart0_default
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart0_sleep
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart0_sleep
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@9000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_9000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PATH "/soc/peripheral@50000000/uart@9000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FULL_NAME "uart@9000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_CHILD_IDX 16

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_ORD 64

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_9000
#define DT_N_NODELABEL_uart1         DT_N_S_soc_S_peripheral_50000000_S_uart_9000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_rx_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_rx_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_cts_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_cts_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_a000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_PATH "/soc/peripheral@50000000/uart@a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FULL_NAME "uart@a000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_CHILD_IDX 17

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_ORD 65

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_a000
#define DT_N_NODELABEL_uart2         DT_N_S_soc_S_peripheral_50000000_S_uart_a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_REG_IDX_0_VAL_ADDRESS 1342218240 /* 0x5000a000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_VAL_irq 10
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_IDX_0 40960
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_IDX_0 10
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_rx_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_rx_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_cts_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_cts_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_a000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_b000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PATH "/soc/peripheral@50000000/uart@b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FULL_NAME "uart@b000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_CHILD_IDX 18

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_ORD 66

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_b000
#define DT_N_NODELABEL_uart3         DT_N_S_soc_S_peripheral_50000000_S_uart_b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_rx_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_rx_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_cts_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_cts_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 7)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 7, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/vmc@3a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000
 *
 * Binding (compatible = nordic,nrf-vmc):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-vmc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_PATH "/soc/peripheral@50000000/vmc@3a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FULL_NAME "vmc@3a000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_CHILD_IDX 14

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_ORD 67

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_vmc DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000
#define DT_N_NODELABEL_vmc         DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_REG_IDX_0_VAL_ADDRESS 1342414848 /* 0x5003a000 */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_COMPAT_MATCHES_nordic_nrf_vmc 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_COMPAT_MODEL_IDX_0 "nrf-vmc"
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg {237568 /* 0x3a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_IDX_0 237568
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible {"nordic,nrf-vmc"}
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_IDX_0 "nordic,nrf-vmc"
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_vmc
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_VMC
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/watchdog@18000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
 *
 * Binding (compatible = nordic,nrf-wdt):
 *   $ZEPHYR_BASE\dts\bindings\watchdog\nordic,nrf-wdt.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PATH "/soc/peripheral@50000000/watchdog@18000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FULL_NAME "watchdog@18000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_CHILD_IDX 36

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_ORD 68

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */ \
	23, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_wdt DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
#define DT_N_NODELABEL_wdt         DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
#define DT_N_NODELABEL_wdt0        DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_ADDRESS 1342275584 /* 0x50018000 */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq 24
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MATCHES_nordic_nrf_wdt 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MODEL_IDX_0 "nrf-wdt"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg {98304 /* 0x18000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_0 98304
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts {24 /* 0x18 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_0 24
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, interrupts, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 3)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 3, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible {"nordic,nrf-wdt"}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0 "nordic,nrf-wdt"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_wdt
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_WDT
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
 *
 * Binding (compatible = nordic,nrf91-flash-controller):
 *   $ZEPHYR_BASE\dts\bindings\flash_controller\nordic,nrf91-flash-controller.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PATH "/soc/peripheral@50000000/flash-controller@39000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FULL_NAME "flash-controller@39000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_ORD 69

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REQUIRES_ORDS \
	9, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_SUPPORTS_ORDS \
	70, /* /soc/peripheral@50000000/flash-controller@39000/flash@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_EXISTS 1
#define DT_N_INST_0_nordic_nrf91_flash_controller DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
#define DT_N_NODELABEL_flash_controller           DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MATCHES_nordic_nrf91_flash_controller 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MODEL_IDX_0 "nrf91-flash-controller"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_partial_erase 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_partial_erase_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_0 233472
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible {"nordic,nrf91-flash-controller"}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0 "nordic,nrf91-flash-controller"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf91_flash_controller
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF91_FLASH_CONTROLLER
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
 *
 * Binding (compatible = soc-nv-flash):
 *   $ZEPHYR_BASE\dts\bindings\mtd\soc-nv-flash.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FULL_NAME "flash@0"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_ORD 70

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REQUIRES_ORDS \
	69, /* /soc/peripheral@50000000/flash-controller@39000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_SUPPORTS_ORDS \
	71, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_EXISTS 1
#define DT_N_INST_0_soc_nv_flash DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
#define DT_N_NODELABEL_flash0    DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_SIZE 1048576 /* 0x100000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_COMPAT_MATCHES_soc_nv_flash 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size 4096
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible {"soc-nv-flash"}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0 "soc-nv-flash"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_TOKEN soc_nv_flash
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SOC_NV_FLASH
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg {0 /* 0x0 */, 1048576 /* 0x100000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1 1048576
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_wakeup_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\fixed-partitions.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FULL_NAME "partitions"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD 71

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_REQUIRES_ORDS \
	70, /* /soc/peripheral@50000000/flash-controller@39000/flash@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_SUPPORTS_ORDS \
	72, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0 */ \
	73, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000 */ \
	74, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000 */ \
	75, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000 */ \
	76, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000 */ \
	77, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f0000 */ \
	78, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@fa000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_EXISTS 1
#define DT_N_INST_0_fixed_partitions DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_REG_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FULL_NAME "partition@0"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD 72

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REQUIRES_ORDS \
	71, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_EXISTS 1
#define DT_N_NODELABEL_boot_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label "mcuboot"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_TOKEN mcuboot
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN MCUBOOT
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 6)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 6)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 6, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 6, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 65536 /* 0x10000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1 65536
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME "partition@10000"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD 73

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REQUIRES_ORDS \
	71, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_EXISTS 1
#define DT_N_NODELABEL_slot0_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_ADDRESS 65536 /* 0x10000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARTITION_ID 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label "image-0"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_TOKEN image_0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UPPER_TOKEN IMAGE_0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 6)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 6)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 6, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 6, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg {65536 /* 0x10000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0 65536
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FULL_NAME "partition@50000"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_CHILD_IDX 2

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_ORD 74

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REQUIRES_ORDS \
	71, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_EXISTS 1
#define DT_N_NODELABEL_slot0_ns_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_ADDRESS 327680 /* 0x50000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARTITION_ID 2

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label "image-0-nonsecure"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_TOKEN image_0_nonsecure
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_UPPER_TOKEN IMAGE_0_NONSECURE
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 7) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 8) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 9) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 10) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 11) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 12) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 13) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 14) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 15) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 16)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 13) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 14) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 15) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 16)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 11, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 12, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 13, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 14, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 15, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 16, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 16, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg {327680 /* 0x50000 */, 196608 /* 0x30000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0 327680
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1 196608
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FULL_NAME "partition@80000"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_CHILD_IDX 3

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_ORD 75

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REQUIRES_ORDS \
	71, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_EXISTS 1
#define DT_N_NODELABEL_slot1_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_ADDRESS 524288 /* 0x80000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARTITION_ID 3

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label "image-1"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_TOKEN image_1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_UPPER_TOKEN IMAGE_1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 6)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 6)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 6, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 6, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg {524288 /* 0x80000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0 524288
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FULL_NAME "partition@c0000"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_CHILD_IDX 4

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_ORD 76

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REQUIRES_ORDS \
	71, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_EXISTS 1
#define DT_N_NODELABEL_slot1_ns_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_ADDRESS 786432 /* 0xc0000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARTITION_ID 4

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label "image-1-nonsecure"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_TOKEN image_1_nonsecure
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_UPPER_TOKEN IMAGE_1_NONSECURE
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 7) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 8) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 9) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 10) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 11) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 12) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 13) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 14) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 15) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 16)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 13) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 14) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 15) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 16)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 11, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 12, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 13, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 14, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 15, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 16, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 16, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg {786432 /* 0xc0000 */, 196608 /* 0x30000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0 786432
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1 196608
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f0000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FULL_NAME "partition@f0000"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_CHILD_IDX 5

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_ORD 77

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REQUIRES_ORDS \
	71, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_EXISTS 1
#define DT_N_NODELABEL_scratch_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_ADDRESS 983040 /* 0xf0000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_SIZE 40960 /* 0xa000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARTITION_ID 5

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label "image-scratch"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_STRING_TOKEN image_scratch
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_STRING_UPPER_TOKEN IMAGE_SCRATCH
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 7) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 8) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 9) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 10) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 11) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 12)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 12)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 11, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 12, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 12, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg {983040 /* 0xf0000 */, 40960 /* 0xa000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0 983040
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1 40960
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@fa000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@fa000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FULL_NAME "partition@fa000"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_CHILD_IDX 6

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_ORD 78

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REQUIRES_ORDS \
	71, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_EXISTS 1
#define DT_N_NODELABEL_storage_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_ADDRESS 1024000 /* 0xfa000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_SIZE 24576 /* 0x6000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARTITION_ID 6

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label "storage"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_STRING_TOKEN storage
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_STRING_UPPER_TOKEN STORAGE
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 6)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 6)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 6, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 6, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg {1024000 /* 0xfa000 */, 24576 /* 0x6000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0 1024000
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1 24576
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_EXISTS 1

/*
 * Chosen nodes
 */
#define DT_CHOSEN_zephyr_entropy                          DT_N_S_soc_S_crypto_50840000
#define DT_CHOSEN_zephyr_entropy_EXISTS                   1
#define DT_CHOSEN_zephyr_flash_controller                 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
#define DT_CHOSEN_zephyr_flash_controller_EXISTS          1
#define DT_CHOSEN_zephyr_console                          DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_CHOSEN_zephyr_console_EXISTS                   1
#define DT_CHOSEN_zephyr_shell_uart                       DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_CHOSEN_zephyr_shell_uart_EXISTS                1
#define DT_CHOSEN_zephyr_uart_mcumgr                      DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_CHOSEN_zephyr_uart_mcumgr_EXISTS               1
#define DT_CHOSEN_zephyr_sram                             DT_N_S_reserved_memory_S_image_s_20000000
#define DT_CHOSEN_zephyr_sram_EXISTS                      1
#define DT_CHOSEN_zephyr_flash                            DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
#define DT_CHOSEN_zephyr_flash_EXISTS                     1
#define DT_CHOSEN_zephyr_code_partition                   DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
#define DT_CHOSEN_zephyr_code_partition_EXISTS            1
#define DT_CHOSEN_zephyr_sram_secure_partition            DT_N_S_reserved_memory_S_image_s_20000000
#define DT_CHOSEN_zephyr_sram_secure_partition_EXISTS     1
#define DT_CHOSEN_zephyr_sram_non_secure_partition        DT_N_S_reserved_memory_S_image_ns_20020000
#define DT_CHOSEN_zephyr_sram_non_secure_partition_EXISTS 1

/* Macros for iterating over all nodes and enabled nodes */
#define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) fn(DT_N_S_soc_S_crypto_50840000) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000) fn(DT_N_S_soc_S_ctrlap_50006000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_reserved_memory) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000)
#define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) fn(DT_N_S_soc_S_crypto_50840000) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000) fn(DT_N_S_soc_S_ctrlap_50006000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_reserved_memory) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000)
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_0 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
#define DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000
#define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_1 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000
#define DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000
#define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_storage DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000
#define DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS 1

/*
 * Macros for compatibles with status "okay" nodes
 */
#define DT_COMPAT_HAS_OKAY_nordic_nrf9160_dk_nrf9160 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf9160_sica 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf9160 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf91 1
#define DT_COMPAT_HAS_OKAY_simple_bus 1
#define DT_COMPAT_HAS_OKAY_arm_v8m_nvic 1
#define DT_COMPAT_HAS_OKAY_mmio_sram 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf91_flash_controller 1
#define DT_COMPAT_HAS_OKAY_soc_nv_flash 1
#define DT_COMPAT_HAS_OKAY_fixed_partitions 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_saadc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_dppic 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_egu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ipc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_kmu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_regulators 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_vmc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uarte 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_rtc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_clock 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_power 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_wdt 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_timer 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_cc310 1
#define DT_COMPAT_HAS_OKAY_arm_cryptocell_310 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ctrlapperi 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_spu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ficr 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uicr 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_pinctrl 1
#define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_entropy 1
#define DT_COMPAT_HAS_OKAY_arm_cortex_m33f 1
#define DT_COMPAT_HAS_OKAY_arm_armv8m_mpu 1
#define DT_COMPAT_HAS_OKAY_gpio_leds 1

/*
 * Macros for status "okay" instances of each compatible
 */
#define DT_N_INST_nordic_nrf9160_dk_nrf9160_NUM_OKAY 1
#define DT_N_INST_nordic_nrf9160_sica_NUM_OKAY 1
#define DT_N_INST_nordic_nrf9160_NUM_OKAY 1
#define DT_N_INST_nordic_nrf91_NUM_OKAY 1
#define DT_N_INST_simple_bus_NUM_OKAY 1
#define DT_N_INST_arm_v8m_nvic_NUM_OKAY 1
#define DT_N_INST_mmio_sram_NUM_OKAY 1
#define DT_N_INST_nordic_nrf91_flash_controller_NUM_OKAY 1
#define DT_N_INST_soc_nv_flash_NUM_OKAY 1
#define DT_N_INST_fixed_partitions_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_saadc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_dppic_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_egu_NUM_OKAY 6
#define DT_N_INST_nordic_nrf_ipc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_kmu_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_regulators_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_vmc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_uarte_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpio_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_rtc_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_clock_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_power_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_wdt_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_timer_NUM_OKAY 3
#define DT_N_INST_nordic_nrf_cc310_NUM_OKAY 1
#define DT_N_INST_arm_cryptocell_310_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ctrlapperi_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_spu_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ficr_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_uicr_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_pinctrl_NUM_OKAY 1
#define DT_N_INST_zephyr_bt_hci_entropy_NUM_OKAY 1
#define DT_N_INST_arm_cortex_m33f_NUM_OKAY 1
#define DT_N_INST_arm_armv8m_mpu_NUM_OKAY 1
#define DT_N_INST_gpio_leds_NUM_OKAY 1
#define DT_FOREACH_OKAY_nordic_nrf9160_dk_nrf9160(fn) fn(DT_N)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf9160_dk_nrf9160(fn, ...) fn(DT_N, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf9160_dk_nrf9160(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9160_dk_nrf9160(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf9160_sica(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf9160_sica(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf9160_sica(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9160_sica(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf9160(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf9160(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf9160(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9160(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf91(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf91(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf91(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf91(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_simple_bus(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_v8m_nvic(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100)
#define DT_FOREACH_OKAY_VARGS_arm_v8m_nvic(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_v8m_nvic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_v8m_nvic(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_mmio_sram(fn) fn(DT_N_S_soc_S_memory_20000000)
#define DT_FOREACH_OKAY_VARGS_mmio_sram(fn, ...) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_mmio_sram(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf91_flash_controller(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf91_flash_controller(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf91_flash_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf91_flash_controller(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_soc_nv_flash(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
#define DT_FOREACH_OKAY_VARGS_soc_nv_flash(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_fixed_partitions(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
#define DT_FOREACH_OKAY_VARGS_fixed_partitions(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_fixed_partitions(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_fixed_partitions(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_saadc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_saadc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_saadc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_saadc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_dppic(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_dppic(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_dppic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_dppic(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_egu(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_egu(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_egu(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_egu(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ipc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ipc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ipc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ipc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_kmu(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_kmu(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_kmu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_kmu(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_regulators(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_regulators(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_regulators(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_regulators(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_vmc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_vmc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_3a000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_vmc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_vmc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_uarte(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_uarte(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_uarte(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uarte(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_gpio(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpio(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpio(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpio(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_rtc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_rtc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_rtc(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_rtc(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_clock(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_clock(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_clock(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_power(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_power(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_power(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_power(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_wdt(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_wdt(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_wdt(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_wdt(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_timer(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_timer(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_timer(fn) fn(0) fn(1) fn(2)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_timer(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_cc310(fn) fn(DT_N_S_soc_S_crypto_50840000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_cc310(fn, ...) fn(DT_N_S_soc_S_crypto_50840000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_cc310(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_cc310(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_cryptocell_310(fn) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000)
#define DT_FOREACH_OKAY_VARGS_arm_cryptocell_310(fn, ...) fn(DT_N_S_soc_S_crypto_50840000_S_crypto_50841000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_cryptocell_310(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_cryptocell_310(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ctrlapperi(fn) fn(DT_N_S_soc_S_ctrlap_50006000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ctrlapperi(fn, ...) fn(DT_N_S_soc_S_ctrlap_50006000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ctrlapperi(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ctrlapperi(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_gpiote(fn) fn(DT_N_S_soc_S_gpiote_5000d000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpiote(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpiote(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_spu(fn) fn(DT_N_S_soc_S_spu_50003000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_spu(fn, ...) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_spu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spu(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ficr(fn) fn(DT_N_S_soc_S_ficr_ff0000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ficr(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ficr(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ficr(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_uicr(fn) fn(DT_N_S_soc_S_uicr_ff8000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_uicr(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_uicr(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uicr(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_pinctrl(fn) fn(DT_N_S_pin_controller)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_pinctrl(fn, ...) fn(DT_N_S_pin_controller, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_pinctrl(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pinctrl(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_bt_hci_entropy(fn) fn(DT_N_S_entropy_bt_hci)
#define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_bt_hci_entropy(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_cortex_m33f(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_FOREACH_OKAY_VARGS_arm_cortex_m33f(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_cortex_m33f(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m33f(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_armv8m_mpu(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
#define DT_FOREACH_OKAY_VARGS_arm_armv8m_mpu(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_armv8m_mpu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_mpu(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_gpio_leds(fn) fn(DT_N_S_leds)
#define DT_FOREACH_OKAY_VARGS_gpio_leds(fn, ...) fn(DT_N_S_leds, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_gpio_leds(fn, ...) fn(0, __VA_ARGS__)

/*
 * Bus information for status "okay" nodes of each compatible
 */
