
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_start>:
#include <syscalls/z_errno_mrsh.c>

#else
int *z_impl_z_errno(void)
{
	return &_current->errno_var;
   0:	20001360 	.word	0x20001360
}
   4:	00001545 	.word	0x00001545
   8:	00004307 	.word	0x00004307
   c:	00001519 	.word	0x00001519
  10:	00001519 	.word	0x00001519
  14:	00001519 	.word	0x00001519
  18:	00001519 	.word	0x00001519
	...
  2c:	00001221 	.word	0x00001221
  30:	00001519 	.word	0x00001519
  34:	00000000 	.word	0x00000000
  38:	000011cd 	.word	0x000011cd
  3c:	000046e5 	.word	0x000046e5

00000040 <_irq_vector_table>:
  40:	000012d9 000012d9 000012d9 000012d9     ................
  50:	000012d9 000012d9 000012d9 000012d9     ................
  60:	000012d9 000012d9 000012d9 000012d9     ................
  70:	000012d9 000012d9 000012d9 000012d9     ................
  80:	000012d9 000012d9 000012d9 000012d9     ................
  90:	000012d9 000012d9 000012d9 000012d9     ................
  a0:	000012d9 000012d9 000012d9 000012d9     ................
  b0:	000012d9 000012d9 000012d9 000012d9     ................
  c0:	000012d9 000012d9 000012d9 000012d9     ................
  d0:	000012d9 000012d9 000012d9 000012d9     ................
  e0:	000012d9 000012d9 000012d9 000012d9     ................
  f0:	000012d9 000012d9 000012d9 000012d9     ................

Disassembly of section text:

00000100 <__aeabi_uldivmod>:
     100:	b953      	cbnz	r3, 118 <__aeabi_uldivmod+0x18>
     102:	b94a      	cbnz	r2, 118 <__aeabi_uldivmod+0x18>
     104:	2900      	cmp	r1, #0
     106:	bf08      	it	eq
     108:	2800      	cmpeq	r0, #0
     10a:	bf1c      	itt	ne
     10c:	f04f 31ff 	movne.w	r1, #4294967295
     110:	f04f 30ff 	movne.w	r0, #4294967295
     114:	f000 b96c 	b.w	3f0 <__aeabi_idiv0>
     118:	f1ad 0c08 	sub.w	ip, sp, #8
     11c:	e96d ce04 	strd	ip, lr, [sp, #-16]!
     120:	f000 f806 	bl	130 <__udivmoddi4>
     124:	f8dd e004 	ldr.w	lr, [sp, #4]
     128:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     12c:	b004      	add	sp, #16
     12e:	4770      	bx	lr

00000130 <__udivmoddi4>:
     130:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     134:	9e08      	ldr	r6, [sp, #32]
     136:	460d      	mov	r5, r1
     138:	4604      	mov	r4, r0
     13a:	468e      	mov	lr, r1
     13c:	2b00      	cmp	r3, #0
     13e:	f040 8082 	bne.w	246 <CONFIG_IDLE_STACK_SIZE+0x106>
     142:	428a      	cmp	r2, r1
     144:	4617      	mov	r7, r2
     146:	d946      	bls.n	1d6 <CONFIG_IDLE_STACK_SIZE+0x96>
     148:	fab2 f282 	clz	r2, r2
     14c:	b14a      	cbz	r2, 162 <CONFIG_IDLE_STACK_SIZE+0x22>
     14e:	f1c2 0120 	rsb	r1, r2, #32
     152:	fa05 f302 	lsl.w	r3, r5, r2
     156:	fa20 f101 	lsr.w	r1, r0, r1
     15a:	4097      	lsls	r7, r2
     15c:	ea41 0e03 	orr.w	lr, r1, r3
     160:	4094      	lsls	r4, r2
     162:	ea4f 4817 	mov.w	r8, r7, lsr #16
     166:	0c23      	lsrs	r3, r4, #16
     168:	fbbe fcf8 	udiv	ip, lr, r8
     16c:	b2b9      	uxth	r1, r7
     16e:	fb08 ee1c 	mls	lr, r8, ip, lr
     172:	ea43 430e 	orr.w	r3, r3, lr, lsl #16
     176:	fb0c f001 	mul.w	r0, ip, r1
     17a:	4298      	cmp	r0, r3
     17c:	d90a      	bls.n	194 <CONFIG_IDLE_STACK_SIZE+0x54>
     17e:	18fb      	adds	r3, r7, r3
     180:	f10c 35ff 	add.w	r5, ip, #4294967295
     184:	f080 8116 	bcs.w	3b4 <CONFIG_IDLE_STACK_SIZE+0x274>
     188:	4298      	cmp	r0, r3
     18a:	f240 8113 	bls.w	3b4 <CONFIG_IDLE_STACK_SIZE+0x274>
     18e:	f1ac 0c02 	sub.w	ip, ip, #2
     192:	443b      	add	r3, r7
     194:	1a1b      	subs	r3, r3, r0
     196:	b2a4      	uxth	r4, r4
     198:	fbb3 f0f8 	udiv	r0, r3, r8
     19c:	fb08 3310 	mls	r3, r8, r0, r3
     1a0:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     1a4:	fb00 f101 	mul.w	r1, r0, r1
     1a8:	42a1      	cmp	r1, r4
     1aa:	d909      	bls.n	1c0 <CONFIG_IDLE_STACK_SIZE+0x80>
     1ac:	193c      	adds	r4, r7, r4
     1ae:	f100 33ff 	add.w	r3, r0, #4294967295
     1b2:	f080 8101 	bcs.w	3b8 <CONFIG_IDLE_STACK_SIZE+0x278>
     1b6:	42a1      	cmp	r1, r4
     1b8:	f240 80fe 	bls.w	3b8 <CONFIG_IDLE_STACK_SIZE+0x278>
     1bc:	3802      	subs	r0, #2
     1be:	443c      	add	r4, r7
     1c0:	1a64      	subs	r4, r4, r1
     1c2:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     1c6:	2100      	movs	r1, #0
     1c8:	b11e      	cbz	r6, 1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     1ca:	40d4      	lsrs	r4, r2
     1cc:	2300      	movs	r3, #0
     1ce:	e9c6 4300 	strd	r4, r3, [r6]
     1d2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     1d6:	b902      	cbnz	r2, 1da <CONFIG_IDLE_STACK_SIZE+0x9a>
     1d8:	deff      	udf	#255	; 0xff
     1da:	fab2 f282 	clz	r2, r2
     1de:	2a00      	cmp	r2, #0
     1e0:	d14f      	bne.n	282 <CONFIG_IDLE_STACK_SIZE+0x142>
     1e2:	1bcb      	subs	r3, r1, r7
     1e4:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     1e8:	fa1f f887 	uxth.w	r8, r7
     1ec:	2101      	movs	r1, #1
     1ee:	fbb3 fcfe 	udiv	ip, r3, lr
     1f2:	0c25      	lsrs	r5, r4, #16
     1f4:	fb0e 331c 	mls	r3, lr, ip, r3
     1f8:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     1fc:	fb08 f30c 	mul.w	r3, r8, ip
     200:	42ab      	cmp	r3, r5
     202:	d907      	bls.n	214 <CONFIG_IDLE_STACK_SIZE+0xd4>
     204:	197d      	adds	r5, r7, r5
     206:	f10c 30ff 	add.w	r0, ip, #4294967295
     20a:	d202      	bcs.n	212 <CONFIG_IDLE_STACK_SIZE+0xd2>
     20c:	42ab      	cmp	r3, r5
     20e:	f200 80e7 	bhi.w	3e0 <CONFIG_IDLE_STACK_SIZE+0x2a0>
     212:	4684      	mov	ip, r0
     214:	1aed      	subs	r5, r5, r3
     216:	b2a3      	uxth	r3, r4
     218:	fbb5 f0fe 	udiv	r0, r5, lr
     21c:	fb0e 5510 	mls	r5, lr, r0, r5
     220:	ea43 4405 	orr.w	r4, r3, r5, lsl #16
     224:	fb08 f800 	mul.w	r8, r8, r0
     228:	45a0      	cmp	r8, r4
     22a:	d907      	bls.n	23c <CONFIG_IDLE_STACK_SIZE+0xfc>
     22c:	193c      	adds	r4, r7, r4
     22e:	f100 33ff 	add.w	r3, r0, #4294967295
     232:	d202      	bcs.n	23a <CONFIG_IDLE_STACK_SIZE+0xfa>
     234:	45a0      	cmp	r8, r4
     236:	f200 80d7 	bhi.w	3e8 <CONFIG_IDLE_STACK_SIZE+0x2a8>
     23a:	4618      	mov	r0, r3
     23c:	eba4 0408 	sub.w	r4, r4, r8
     240:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     244:	e7c0      	b.n	1c8 <CONFIG_IDLE_STACK_SIZE+0x88>
     246:	428b      	cmp	r3, r1
     248:	d908      	bls.n	25c <CONFIG_IDLE_STACK_SIZE+0x11c>
     24a:	2e00      	cmp	r6, #0
     24c:	f000 80af 	beq.w	3ae <CONFIG_IDLE_STACK_SIZE+0x26e>
     250:	2100      	movs	r1, #0
     252:	e9c6 0500 	strd	r0, r5, [r6]
     256:	4608      	mov	r0, r1
     258:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     25c:	fab3 f183 	clz	r1, r3
     260:	2900      	cmp	r1, #0
     262:	d14b      	bne.n	2fc <CONFIG_IDLE_STACK_SIZE+0x1bc>
     264:	42ab      	cmp	r3, r5
     266:	d302      	bcc.n	26e <CONFIG_IDLE_STACK_SIZE+0x12e>
     268:	4282      	cmp	r2, r0
     26a:	f200 80b7 	bhi.w	3dc <CONFIG_IDLE_STACK_SIZE+0x29c>
     26e:	1a84      	subs	r4, r0, r2
     270:	eb65 0303 	sbc.w	r3, r5, r3
     274:	2001      	movs	r0, #1
     276:	469e      	mov	lr, r3
     278:	2e00      	cmp	r6, #0
     27a:	d0aa      	beq.n	1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     27c:	e9c6 4e00 	strd	r4, lr, [r6]
     280:	e7a7      	b.n	1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     282:	f1c2 0c20 	rsb	ip, r2, #32
     286:	fa01 f302 	lsl.w	r3, r1, r2
     28a:	4097      	lsls	r7, r2
     28c:	fa20 f00c 	lsr.w	r0, r0, ip
     290:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     294:	fa21 fc0c 	lsr.w	ip, r1, ip
     298:	4318      	orrs	r0, r3
     29a:	fbbc f1fe 	udiv	r1, ip, lr
     29e:	0c05      	lsrs	r5, r0, #16
     2a0:	fb0e cc11 	mls	ip, lr, r1, ip
     2a4:	fa1f f887 	uxth.w	r8, r7
     2a8:	ea45 450c 	orr.w	r5, r5, ip, lsl #16
     2ac:	fb01 f308 	mul.w	r3, r1, r8
     2b0:	42ab      	cmp	r3, r5
     2b2:	fa04 f402 	lsl.w	r4, r4, r2
     2b6:	d909      	bls.n	2cc <CONFIG_IDLE_STACK_SIZE+0x18c>
     2b8:	197d      	adds	r5, r7, r5
     2ba:	f101 3cff 	add.w	ip, r1, #4294967295
     2be:	f080 808b 	bcs.w	3d8 <CONFIG_IDLE_STACK_SIZE+0x298>
     2c2:	42ab      	cmp	r3, r5
     2c4:	f240 8088 	bls.w	3d8 <CONFIG_IDLE_STACK_SIZE+0x298>
     2c8:	3902      	subs	r1, #2
     2ca:	443d      	add	r5, r7
     2cc:	1aeb      	subs	r3, r5, r3
     2ce:	b285      	uxth	r5, r0
     2d0:	fbb3 f0fe 	udiv	r0, r3, lr
     2d4:	fb0e 3310 	mls	r3, lr, r0, r3
     2d8:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     2dc:	fb00 f308 	mul.w	r3, r0, r8
     2e0:	42ab      	cmp	r3, r5
     2e2:	d907      	bls.n	2f4 <CONFIG_IDLE_STACK_SIZE+0x1b4>
     2e4:	197d      	adds	r5, r7, r5
     2e6:	f100 3cff 	add.w	ip, r0, #4294967295
     2ea:	d271      	bcs.n	3d0 <CONFIG_IDLE_STACK_SIZE+0x290>
     2ec:	42ab      	cmp	r3, r5
     2ee:	d96f      	bls.n	3d0 <CONFIG_IDLE_STACK_SIZE+0x290>
     2f0:	3802      	subs	r0, #2
     2f2:	443d      	add	r5, r7
     2f4:	1aeb      	subs	r3, r5, r3
     2f6:	ea40 4101 	orr.w	r1, r0, r1, lsl #16
     2fa:	e778      	b.n	1ee <CONFIG_IDLE_STACK_SIZE+0xae>
     2fc:	f1c1 0c20 	rsb	ip, r1, #32
     300:	408b      	lsls	r3, r1
     302:	fa22 f70c 	lsr.w	r7, r2, ip
     306:	431f      	orrs	r7, r3
     308:	fa20 f40c 	lsr.w	r4, r0, ip
     30c:	fa05 f301 	lsl.w	r3, r5, r1
     310:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     314:	fa25 f50c 	lsr.w	r5, r5, ip
     318:	431c      	orrs	r4, r3
     31a:	0c23      	lsrs	r3, r4, #16
     31c:	fbb5 f9fe 	udiv	r9, r5, lr
     320:	fa1f f887 	uxth.w	r8, r7
     324:	fb0e 5519 	mls	r5, lr, r9, r5
     328:	ea43 4505 	orr.w	r5, r3, r5, lsl #16
     32c:	fb09 fa08 	mul.w	sl, r9, r8
     330:	45aa      	cmp	sl, r5
     332:	fa02 f201 	lsl.w	r2, r2, r1
     336:	fa00 f301 	lsl.w	r3, r0, r1
     33a:	d908      	bls.n	34e <CONFIG_IDLE_STACK_SIZE+0x20e>
     33c:	197d      	adds	r5, r7, r5
     33e:	f109 30ff 	add.w	r0, r9, #4294967295
     342:	d247      	bcs.n	3d4 <CONFIG_IDLE_STACK_SIZE+0x294>
     344:	45aa      	cmp	sl, r5
     346:	d945      	bls.n	3d4 <CONFIG_IDLE_STACK_SIZE+0x294>
     348:	f1a9 0902 	sub.w	r9, r9, #2
     34c:	443d      	add	r5, r7
     34e:	eba5 050a 	sub.w	r5, r5, sl
     352:	b2a4      	uxth	r4, r4
     354:	fbb5 f0fe 	udiv	r0, r5, lr
     358:	fb0e 5510 	mls	r5, lr, r0, r5
     35c:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
     360:	fb00 f808 	mul.w	r8, r0, r8
     364:	45a0      	cmp	r8, r4
     366:	d907      	bls.n	378 <CONFIG_IDLE_STACK_SIZE+0x238>
     368:	193c      	adds	r4, r7, r4
     36a:	f100 35ff 	add.w	r5, r0, #4294967295
     36e:	d22d      	bcs.n	3cc <CONFIG_IDLE_STACK_SIZE+0x28c>
     370:	45a0      	cmp	r8, r4
     372:	d92b      	bls.n	3cc <CONFIG_IDLE_STACK_SIZE+0x28c>
     374:	3802      	subs	r0, #2
     376:	443c      	add	r4, r7
     378:	ea40 4009 	orr.w	r0, r0, r9, lsl #16
     37c:	eba4 0408 	sub.w	r4, r4, r8
     380:	fba0 8902 	umull	r8, r9, r0, r2
     384:	454c      	cmp	r4, r9
     386:	46c6      	mov	lr, r8
     388:	464d      	mov	r5, r9
     38a:	d319      	bcc.n	3c0 <CONFIG_IDLE_STACK_SIZE+0x280>
     38c:	d016      	beq.n	3bc <CONFIG_IDLE_STACK_SIZE+0x27c>
     38e:	b15e      	cbz	r6, 3a8 <CONFIG_IDLE_STACK_SIZE+0x268>
     390:	ebb3 020e 	subs.w	r2, r3, lr
     394:	eb64 0405 	sbc.w	r4, r4, r5
     398:	fa04 fc0c 	lsl.w	ip, r4, ip
     39c:	40ca      	lsrs	r2, r1
     39e:	ea4c 0202 	orr.w	r2, ip, r2
     3a2:	40cc      	lsrs	r4, r1
     3a4:	e9c6 2400 	strd	r2, r4, [r6]
     3a8:	2100      	movs	r1, #0
     3aa:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     3ae:	4631      	mov	r1, r6
     3b0:	4630      	mov	r0, r6
     3b2:	e70e      	b.n	1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     3b4:	46ac      	mov	ip, r5
     3b6:	e6ed      	b.n	194 <CONFIG_IDLE_STACK_SIZE+0x54>
     3b8:	4618      	mov	r0, r3
     3ba:	e701      	b.n	1c0 <CONFIG_IDLE_STACK_SIZE+0x80>
     3bc:	4543      	cmp	r3, r8
     3be:	d2e6      	bcs.n	38e <CONFIG_IDLE_STACK_SIZE+0x24e>
     3c0:	ebb8 0e02 	subs.w	lr, r8, r2
     3c4:	eb69 0507 	sbc.w	r5, r9, r7
     3c8:	3801      	subs	r0, #1
     3ca:	e7e0      	b.n	38e <CONFIG_IDLE_STACK_SIZE+0x24e>
     3cc:	4628      	mov	r0, r5
     3ce:	e7d3      	b.n	378 <CONFIG_IDLE_STACK_SIZE+0x238>
     3d0:	4660      	mov	r0, ip
     3d2:	e78f      	b.n	2f4 <CONFIG_IDLE_STACK_SIZE+0x1b4>
     3d4:	4681      	mov	r9, r0
     3d6:	e7ba      	b.n	34e <CONFIG_IDLE_STACK_SIZE+0x20e>
     3d8:	4661      	mov	r1, ip
     3da:	e777      	b.n	2cc <CONFIG_IDLE_STACK_SIZE+0x18c>
     3dc:	4608      	mov	r0, r1
     3de:	e74b      	b.n	278 <CONFIG_IDLE_STACK_SIZE+0x138>
     3e0:	f1ac 0c02 	sub.w	ip, ip, #2
     3e4:	443d      	add	r5, r7
     3e6:	e715      	b.n	214 <CONFIG_IDLE_STACK_SIZE+0xd4>
     3e8:	3802      	subs	r0, #2
     3ea:	443c      	add	r4, r7
     3ec:	e726      	b.n	23c <CONFIG_IDLE_STACK_SIZE+0xfc>
     3ee:	bf00      	nop

000003f0 <__aeabi_idiv0>:
     3f0:	4770      	bx	lr
     3f2:	bf00      	nop

000003f4 <main>:
#define PIN	0
#define FLAGS	0
#endif

void main(void)
{
     3f4:	b570      	push	{r4, r5, r6, lr}
		/* coverity[OVERRUN] */
		return (const struct device *) arch_syscall_invoke1(*(uintptr_t *)&name, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
     3f6:	4816      	ldr	r0, [pc, #88]	; (450 <CONFIG_FLASH_SIZE+0x50>)
     3f8:	f002 fc86 	bl	2d08 <z_impl_device_get_binding>
	const struct device *dev;
	bool led_is_on = true;
	int ret;

	dev = device_get_binding(LED0);
	if (dev == NULL) {
     3fc:	4604      	mov	r4, r0
     3fe:	b328      	cbz	r0, 44c <CONFIG_FLASH_SIZE+0x4c>
{
	const struct gpio_driver_api *api =
		(const struct gpio_driver_api *)port->api;
	const struct gpio_driver_config *const cfg =
		(const struct gpio_driver_config *)port->config;
	struct gpio_driver_data *data =
     400:	6902      	ldr	r2, [r0, #16]
	const struct gpio_driver_api *api =
     402:	6881      	ldr	r1, [r0, #8]
	(void)cfg;
	__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
		 "Unsupported pin");

	if ((flags & GPIO_ACTIVE_LOW) != 0) {
		data->invert |= (gpio_port_pins_t)BIT(pin);
     404:	6813      	ldr	r3, [r2, #0]
     406:	f043 0340 	orr.w	r3, r3, #64	; 0x40
     40a:	6013      	str	r3, [r2, #0]
	} else {
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
	}

	return api->pin_configure(port, pin, flags);
     40c:	680b      	ldr	r3, [r1, #0]
     40e:	f240 6201 	movw	r2, #1537	; 0x601
     412:	2106      	movs	r1, #6
     414:	4798      	blx	r3
		return;
	}

	ret = gpio_pin_configure(dev, PIN, GPIO_OUTPUT_ACTIVE | FLAGS);
	if (ret < 0) {
     416:	2800      	cmp	r0, #0
     418:	db18      	blt.n	44c <CONFIG_FLASH_SIZE+0x4c>
	bool led_is_on = true;
     41a:	2501      	movs	r5, #1

	(void)cfg;
	__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
		 "Unsupported pin");

	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
     41c:	6923      	ldr	r3, [r4, #16]
     41e:	681b      	ldr	r3, [r3, #0]
     420:	f085 0601 	eor.w	r6, r5, #1
     424:	f013 0f40 	tst.w	r3, #64	; 0x40
		value = (value != 0) ? 0 : 1;
     428:	bf18      	it	ne
     42a:	b2f5      	uxtbne	r5, r6
	if (value != 0)	{
     42c:	b15d      	cbz	r5, 446 <CONFIG_FLASH_SIZE+0x46>
	return api->port_set_bits_raw(port, pins);
     42e:	68a3      	ldr	r3, [r4, #8]
     430:	68db      	ldr	r3, [r3, #12]
	return api->port_clear_bits_raw(port, pins);
     432:	2140      	movs	r1, #64	; 0x40
     434:	4620      	mov	r0, r4
     436:	4798      	blx	r3
		return;
	}

	while (1) {
		gpio_pin_set(dev, PIN, (int)led_is_on);
		led_is_on = !led_is_on;
     438:	b2f5      	uxtb	r5, r6
		/* coverity[OVERRUN] */
		return (int32_t) arch_syscall_invoke2(parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SLEEP);
	}
#endif
	compiler_barrier();
	return z_impl_k_sleep(timeout);
     43a:	2100      	movs	r1, #0
     43c:	f640 40cd 	movw	r0, #3277	; 0xccd
     440:	f003 fa40 	bl	38c4 <z_impl_k_sleep>
 * @return Zero if the requested time has elapsed or the number of milliseconds
 * left to sleep, if thread was woken up by \ref k_wakeup call.
 */
static inline int32_t k_msleep(int32_t ms)
{
	return k_sleep(Z_TIMEOUT_MS(ms));
     444:	e7ea      	b.n	41c <CONFIG_FLASH_SIZE+0x1c>
     446:	68a3      	ldr	r3, [r4, #8]
     448:	691b      	ldr	r3, [r3, #16]
     44a:	e7f2      	b.n	432 <CONFIG_FLASH_SIZE+0x32>
		k_msleep(SLEEP_TIME_MS);
	}
}
     44c:	bd70      	pop	{r4, r5, r6, pc}
     44e:	bf00      	nop
     450:	00004e2c 	.word	0x00004e2c

00000454 <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
     454:	680b      	ldr	r3, [r1, #0]
     456:	3301      	adds	r3, #1
     458:	600b      	str	r3, [r1, #0]
	return _char_out(c);
     45a:	4b01      	ldr	r3, [pc, #4]	; (460 <char_out+0xc>)
     45c:	681b      	ldr	r3, [r3, #0]
     45e:	4718      	bx	r3
     460:	20000000 	.word	0x20000000

00000464 <vprintk>:
#endif
	}
}
#else
void vprintk(const char *fmt, va_list ap)
{
     464:	b507      	push	{r0, r1, r2, lr}
     466:	460b      	mov	r3, r1
	struct out_context ctx = { 0 };
     468:	2100      	movs	r1, #0
{
     46a:	4602      	mov	r2, r0
	struct out_context ctx = { 0 };
     46c:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
	k_spinlock_key_t key = k_spin_lock(&lock);
#endif

	cbvprintf(char_out, &ctx, fmt, ap);
     46e:	4803      	ldr	r0, [pc, #12]	; (47c <vprintk+0x18>)
     470:	a901      	add	r1, sp, #4
     472:	f000 f8eb 	bl	64c <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
	k_spin_unlock(&lock, key);
#endif
}
     476:	b003      	add	sp, #12
     478:	f85d fb04 	ldr.w	pc, [sp], #4
     47c:	00000455 	.word	0x00000455

00000480 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     480:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     484:	f8b0 9018 	ldrh.w	r9, [r0, #24]
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     488:	f019 0808 	ands.w	r8, r9, #8
{
     48c:	4604      	mov	r4, r0
     48e:	4693      	mov	fp, r2
	if (processing) {
     490:	d00d      	beq.n	4ae <process_event+0x2e>
		if (evt == EVT_COMPLETE) {
     492:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     494:	bf0c      	ite	eq
     496:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
     49a:	f049 0920 	orrne.w	r9, r9, #32
     49e:	f8a0 9018 	strh.w	r9, [r0, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     4a2:	f38b 8811 	msr	BASEPRI, fp
     4a6:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     4aa:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     4ae:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
     4b2:	2902      	cmp	r1, #2
     4b4:	d107      	bne.n	4c6 <process_event+0x46>
			evt = process_recheck(mgr);
     4b6:	4620      	mov	r0, r4
     4b8:	f003 fdfb 	bl	40b2 <process_recheck>
		if (evt == EVT_NOP) {
     4bc:	2800      	cmp	r0, #0
     4be:	d0f0      	beq.n	4a2 <process_event+0x22>
		if (evt == EVT_COMPLETE) {
     4c0:	2801      	cmp	r0, #1
     4c2:	8b23      	ldrh	r3, [r4, #24]
     4c4:	d150      	bne.n	568 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x80>
			res = mgr->last_res;
     4c6:	6967      	ldr	r7, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     4c8:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
     4ca:	2f00      	cmp	r7, #0
     4cc:	da15      	bge.n	4fa <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x12>
		*clients = mgr->clients;
     4ce:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     4d0:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
     4d4:	e9c4 8800 	strd	r8, r8, [r4]
     4d8:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
     4dc:	8321      	strh	r1, [r4, #24]
		onoff_transition_fn transit = NULL;
     4de:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     4e0:	8b21      	ldrh	r1, [r4, #24]
     4e2:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     4e6:	45ca      	cmp	sl, r9
     4e8:	d002      	beq.n	4f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x8>
		if (do_monitors
     4ea:	68a3      	ldr	r3, [r4, #8]
     4ec:	2b00      	cmp	r3, #0
     4ee:	d15c      	bne.n	5aa <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc2>
		    || !sys_slist_is_empty(&clients)
     4f0:	b90d      	cbnz	r5, 4f6 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xe>
		    || (transit != NULL)) {
     4f2:	2e00      	cmp	r6, #0
     4f4:	d074      	beq.n	5e0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xf8>
     4f6:	2300      	movs	r3, #0
     4f8:	e058      	b.n	5ac <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc4>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     4fa:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
     4fe:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
     500:	2a01      	cmp	r2, #1
     502:	d820      	bhi.n	546 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x5e>
		*clients = mgr->clients;
     504:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
     508:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
     50a:	6825      	ldr	r5, [r4, #0]
	list->head = NULL;
     50c:	b289      	uxth	r1, r1
	list->tail = NULL;
     50e:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
     512:	d10c      	bne.n	52e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x46>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     514:	2d00      	cmp	r5, #0
     516:	462b      	mov	r3, r5
     518:	bf38      	it	cc
     51a:	2300      	movcc	r3, #0
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     51c:	b12b      	cbz	r3, 52a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x42>
				mgr->refs += 1U;
     51e:	8b62      	ldrh	r2, [r4, #26]
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next_no_check(sys_snode_t *node);

Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     520:	681b      	ldr	r3, [r3, #0]
     522:	3201      	adds	r2, #1
     524:	8362      	strh	r2, [r4, #26]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     526:	2b00      	cmp	r3, #0
     528:	d1f8      	bne.n	51c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x34>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     52a:	f041 0102 	orr.w	r1, r1, #2
	mgr->flags = (state & ONOFF_STATE_MASK)
     52e:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     530:	4620      	mov	r0, r4
     532:	f003 fdbe 	bl	40b2 <process_recheck>
     536:	4606      	mov	r6, r0
     538:	2800      	cmp	r0, #0
     53a:	d0d1      	beq.n	4e0 <process_event+0x60>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     53c:	8b23      	ldrh	r3, [r4, #24]
     53e:	f043 0320 	orr.w	r3, r3, #32
     542:	8323      	strh	r3, [r4, #24]
     544:	e7cb      	b.n	4de <process_event+0x5e>
	} else if (state == ONOFF_STATE_TO_OFF) {
     546:	2b04      	cmp	r3, #4
     548:	d10c      	bne.n	564 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x7c>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     54a:	f021 0107 	bic.w	r1, r1, #7
     54e:	b289      	uxth	r1, r1
	mgr->flags = (state & ONOFF_STATE_MASK)
     550:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     552:	4620      	mov	r0, r4
     554:	f003 fdad 	bl	40b2 <process_recheck>
     558:	4605      	mov	r5, r0
     55a:	2800      	cmp	r0, #0
     55c:	d0bf      	beq.n	4de <process_event+0x5e>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     55e:	f041 0120 	orr.w	r1, r1, #32
     562:	8321      	strh	r1, [r4, #24]
     564:	2500      	movs	r5, #0
     566:	e7ba      	b.n	4de <process_event+0x5e>
		} else if (evt == EVT_START) {
     568:	2803      	cmp	r0, #3
     56a:	d109      	bne.n	580 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x98>
			transit = mgr->transitions->start;
     56c:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     56e:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
     572:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     574:	f043 0306 	orr.w	r3, r3, #6
	mgr->flags = (state & ONOFF_STATE_MASK)
     578:	8323      	strh	r3, [r4, #24]
}
     57a:	2500      	movs	r5, #0
		res = 0;
     57c:	462f      	mov	r7, r5
     57e:	e7af      	b.n	4e0 <process_event+0x60>
		} else if (evt == EVT_STOP) {
     580:	2804      	cmp	r0, #4
     582:	d106      	bne.n	592 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xaa>
			transit = mgr->transitions->stop;
     584:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     586:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
     58a:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     58c:	f043 0304 	orr.w	r3, r3, #4
     590:	e7f2      	b.n	578 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x90>
		} else if (evt == EVT_RESET) {
     592:	2805      	cmp	r0, #5
     594:	d106      	bne.n	5a4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xbc>
			transit = mgr->transitions->reset;
     596:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     598:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
     59c:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     59e:	f043 0305 	orr.w	r3, r3, #5
     5a2:	e7e9      	b.n	578 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x90>
     5a4:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
     5a6:	462e      	mov	r6, r5
     5a8:	e7e8      	b.n	57c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x94>
				   && !sys_slist_is_empty(&mgr->monitors);
     5aa:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     5ac:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     5b0:	8321      	strh	r1, [r4, #24]
     5b2:	f38b 8811 	msr	BASEPRI, fp
     5b6:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
     5ba:	bb03      	cbnz	r3, 5fe <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x116>
	while (!sys_slist_is_empty(list)) {
     5bc:	2d00      	cmp	r5, #0
     5be:	d133      	bne.n	628 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x140>
			if (transit != NULL) {
     5c0:	b116      	cbz	r6, 5c8 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xe0>
				transit(mgr, transition_complete);
     5c2:	4921      	ldr	r1, [pc, #132]	; (648 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x160>)
     5c4:	4620      	mov	r0, r4
     5c6:	47b0      	blx	r6
	__asm__ volatile(
     5c8:	f04f 0320 	mov.w	r3, #32
     5cc:	f3ef 8b11 	mrs	fp, BASEPRI
     5d0:	f383 8812 	msr	BASEPRI_MAX, r3
     5d4:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     5d8:	8b23      	ldrh	r3, [r4, #24]
     5da:	f023 0308 	bic.w	r3, r3, #8
     5de:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     5e0:	8b23      	ldrh	r3, [r4, #24]
     5e2:	06da      	lsls	r2, r3, #27
     5e4:	d528      	bpl.n	638 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x150>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     5e6:	f023 0310 	bic.w	r3, r3, #16
     5ea:	8323      	strh	r3, [r4, #24]
			evt = EVT_COMPLETE;
     5ec:	2101      	movs	r1, #1
		state = mgr->flags & ONOFF_STATE_MASK;
     5ee:	f8b4 9018 	ldrh.w	r9, [r4, #24]
     5f2:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
     5f6:	2900      	cmp	r1, #0
     5f8:	f47f af5b 	bne.w	4b2 <process_event+0x32>
out:
     5fc:	e751      	b.n	4a2 <process_event+0x22>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     5fe:	68a1      	ldr	r1, [r4, #8]
     600:	2900      	cmp	r1, #0
     602:	d0db      	beq.n	5bc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xd4>
	return node->next;
     604:	680b      	ldr	r3, [r1, #0]
		mon->callback(mgr, mon, state, res);
     606:	f8d1 b004 	ldr.w	fp, [r1, #4]
     60a:	2b00      	cmp	r3, #0
     60c:	bf38      	it	cc
     60e:	2300      	movcc	r3, #0
     610:	4699      	mov	r9, r3
     612:	4652      	mov	r2, sl
     614:	463b      	mov	r3, r7
     616:	4620      	mov	r0, r4
     618:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     61a:	f1b9 0f00 	cmp.w	r9, #0
     61e:	d0cd      	beq.n	5bc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xd4>
     620:	f8d9 3000 	ldr.w	r3, [r9]
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     624:	4649      	mov	r1, r9
     626:	e7ee      	b.n	606 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x11e>
 *
 * @return A pointer to the first node of the list
 */
static inline sys_snode_t *sys_slist_get_not_empty(sys_slist_t *list);

Z_GENLIST_GET_NOT_EMPTY(slist, snode)
     628:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
     62a:	463b      	mov	r3, r7
     62c:	4652      	mov	r2, sl
     62e:	4620      	mov	r0, r4
     630:	682d      	ldr	r5, [r5, #0]
     632:	f003 fd5a 	bl	40ea <notify_one>
     636:	e7c1      	b.n	5bc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xd4>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     638:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     63c:	bf1e      	ittt	ne
     63e:	f023 0320 	bicne.w	r3, r3, #32
     642:	8323      	strhne	r3, [r4, #24]
			evt = EVT_RECHECK;
     644:	2102      	movne	r1, #2
     646:	e7d2      	b.n	5ee <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x106>
     648:	00004117 	.word	0x00004117

0000064c <cbvprintf>:

	return (int)count;
}

int cbvprintf(cbprintf_cb out, void *ctx, const char *fp, va_list ap)
{
     64c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     650:	b091      	sub	sp, #68	; 0x44
     652:	468b      	mov	fp, r1
     654:	9002      	str	r0, [sp, #8]
     656:	4692      	mov	sl, r2
     658:	461c      	mov	r4, r3
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
     65a:	2500      	movs	r5, #0
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
     65c:	f89a 0000 	ldrb.w	r0, [sl]
     660:	b908      	cbnz	r0, 666 <cbvprintf+0x1a>
			OUTC(' ');
			--width;
		}
	}

	return count;
     662:	4628      	mov	r0, r5
     664:	e35e      	b.n	d24 <CONFIG_ISR_STACK_SIZE+0x524>
		if (*fp != '%') {
     666:	2825      	cmp	r0, #37	; 0x25
     668:	f10a 0701 	add.w	r7, sl, #1
     66c:	d007      	beq.n	67e <cbvprintf+0x32>
			OUTC('%');
     66e:	9b02      	ldr	r3, [sp, #8]
     670:	4659      	mov	r1, fp
     672:	4798      	blx	r3
     674:	2800      	cmp	r0, #0
     676:	f2c0 8355 	blt.w	d24 <CONFIG_ISR_STACK_SIZE+0x524>
     67a:	3501      	adds	r5, #1
			break;
     67c:	e210      	b.n	aa0 <CONFIG_ISR_STACK_SIZE+0x2a0>
		} state = {
     67e:	2218      	movs	r2, #24
     680:	2100      	movs	r1, #0
     682:	a80a      	add	r0, sp, #40	; 0x28
     684:	f003 fe77 	bl	4376 <memset>
	if (*sp == '%') {
     688:	f89a 3001 	ldrb.w	r3, [sl, #1]
     68c:	2b25      	cmp	r3, #37	; 0x25
     68e:	d078      	beq.n	782 <cbvprintf+0x136>
     690:	2200      	movs	r2, #0
     692:	4694      	mov	ip, r2
     694:	4616      	mov	r6, r2
     696:	4696      	mov	lr, r2
     698:	4610      	mov	r0, r2
     69a:	4639      	mov	r1, r7
		switch (*sp) {
     69c:	f817 3b01 	ldrb.w	r3, [r7], #1
     6a0:	2b2b      	cmp	r3, #43	; 0x2b
     6a2:	f000 809d 	beq.w	7e0 <cbvprintf+0x194>
     6a6:	f200 8094 	bhi.w	7d2 <cbvprintf+0x186>
     6aa:	2b20      	cmp	r3, #32
     6ac:	f000 809b 	beq.w	7e6 <cbvprintf+0x19a>
     6b0:	2b23      	cmp	r3, #35	; 0x23
     6b2:	f000 809a 	beq.w	7ea <cbvprintf+0x19e>
     6b6:	b128      	cbz	r0, 6c4 <cbvprintf+0x78>
     6b8:	f89d 0030 	ldrb.w	r0, [sp, #48]	; 0x30
     6bc:	f040 0004 	orr.w	r0, r0, #4
     6c0:	f88d 0030 	strb.w	r0, [sp, #48]	; 0x30
     6c4:	f1be 0f00 	cmp.w	lr, #0
     6c8:	d005      	beq.n	6d6 <cbvprintf+0x8a>
     6ca:	f89d 0030 	ldrb.w	r0, [sp, #48]	; 0x30
     6ce:	f040 0008 	orr.w	r0, r0, #8
     6d2:	f88d 0030 	strb.w	r0, [sp, #48]	; 0x30
     6d6:	b12e      	cbz	r6, 6e4 <cbvprintf+0x98>
     6d8:	f89d 0030 	ldrb.w	r0, [sp, #48]	; 0x30
     6dc:	f040 0010 	orr.w	r0, r0, #16
     6e0:	f88d 0030 	strb.w	r0, [sp, #48]	; 0x30
     6e4:	f1bc 0f00 	cmp.w	ip, #0
     6e8:	d005      	beq.n	6f6 <cbvprintf+0xaa>
     6ea:	f89d 0030 	ldrb.w	r0, [sp, #48]	; 0x30
     6ee:	f040 0020 	orr.w	r0, r0, #32
     6f2:	f88d 0030 	strb.w	r0, [sp, #48]	; 0x30
     6f6:	b12a      	cbz	r2, 704 <cbvprintf+0xb8>
     6f8:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
     6fc:	f042 0240 	orr.w	r2, r2, #64	; 0x40
     700:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	if (conv->flag_zero && conv->flag_dash) {
     704:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
     708:	f002 0044 	and.w	r0, r2, #68	; 0x44
     70c:	2844      	cmp	r0, #68	; 0x44
     70e:	d103      	bne.n	718 <cbvprintf+0xcc>
		conv->flag_zero = false;
     710:	f36f 1286 	bfc	r2, #6, #1
     714:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	conv->width_present = true;
     718:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
	if (*sp == '*') {
     71c:	2b2a      	cmp	r3, #42	; 0x2a
	conv->width_present = true;
     71e:	f042 0280 	orr.w	r2, r2, #128	; 0x80
     722:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	if (*sp == '*') {
     726:	d17b      	bne.n	820 <CONFIG_ISR_STACK_SIZE+0x20>
		conv->width_star = true;
     728:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     72c:	f042 0201 	orr.w	r2, r2, #1
     730:	1c4b      	adds	r3, r1, #1
     732:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
	conv->prec_present = (*sp == '.');
     736:	781a      	ldrb	r2, [r3, #0]
     738:	2a2e      	cmp	r2, #46	; 0x2e
     73a:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     73e:	bf0c      	ite	eq
     740:	2101      	moveq	r1, #1
     742:	2100      	movne	r1, #0
     744:	f361 0241 	bfi	r2, r1, #1, #1
     748:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
	if (!conv->prec_present) {
     74c:	d174      	bne.n	838 <CONFIG_ISR_STACK_SIZE+0x38>
	if (*sp == '*') {
     74e:	785a      	ldrb	r2, [r3, #1]
     750:	2a2a      	cmp	r2, #42	; 0x2a
     752:	d06a      	beq.n	82a <CONFIG_ISR_STACK_SIZE+0x2a>
     754:	3301      	adds	r3, #1
	size_t val = 0;
     756:	2100      	movs	r1, #0
		val = 10U * val + *sp++ - '0';
     758:	260a      	movs	r6, #10
			(((unsigned)c) <= (unsigned)'~'));
}

static inline int isdigit(int a)
{
	return (int)(((unsigned)(a)-(unsigned)'0') < 10U);
     75a:	4618      	mov	r0, r3
     75c:	f810 2b01 	ldrb.w	r2, [r0], #1
     760:	f1a2 0730 	sub.w	r7, r2, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     764:	2f09      	cmp	r7, #9
     766:	f240 808e 	bls.w	886 <CONFIG_ISR_STACK_SIZE+0x86>
	conv->unsupported |= ((conv->prec_value < 0)
     76a:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
	conv->prec_value = prec;
     76e:	910e      	str	r1, [sp, #56]	; 0x38
	conv->unsupported |= ((conv->prec_value < 0)
     770:	f3c2 0040 	ubfx	r0, r2, #1, #1
     774:	ea40 71d1 	orr.w	r1, r0, r1, lsr #31
     778:	f361 0241 	bfi	r2, r1, #1, #1
     77c:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	return sp;
     780:	e05a      	b.n	838 <CONFIG_ISR_STACK_SIZE+0x38>
		conv->specifier = *sp++;
     782:	f10a 0702 	add.w	r7, sl, #2
     786:	f88d 3033 	strb.w	r3, [sp, #51]	; 0x33
		if (conv->width_star) {
     78a:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     78e:	07d9      	lsls	r1, r3, #31
     790:	f140 8149 	bpl.w	a26 <CONFIG_ISR_STACK_SIZE+0x226>
			width = va_arg(ap, int);
     794:	f854 9b04 	ldr.w	r9, [r4], #4
			if (width < 0) {
     798:	f1b9 0f00 	cmp.w	r9, #0
     79c:	da07      	bge.n	7ae <cbvprintf+0x162>
				conv->flag_dash = true;
     79e:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
     7a2:	f042 0204 	orr.w	r2, r2, #4
     7a6:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
				width = -width;
     7aa:	f1c9 0900 	rsb	r9, r9, #0
		if (conv->prec_star) {
     7ae:	075a      	lsls	r2, r3, #29
     7b0:	f140 8142 	bpl.w	a38 <CONFIG_ISR_STACK_SIZE+0x238>
			int arg = va_arg(ap, int);
     7b4:	f854 8b04 	ldr.w	r8, [r4], #4
			if (arg < 0) {
     7b8:	f1b8 0f00 	cmp.w	r8, #0
     7bc:	f280 8141 	bge.w	a42 <CONFIG_ISR_STACK_SIZE+0x242>
				conv->prec_present = false;
     7c0:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     7c4:	f36f 0341 	bfc	r3, #1, #1
     7c8:	f88d 3031 	strb.w	r3, [sp, #49]	; 0x31
		int precision = -1;
     7cc:	f04f 38ff 	mov.w	r8, #4294967295
     7d0:	e137      	b.n	a42 <CONFIG_ISR_STACK_SIZE+0x242>
		switch (*sp) {
     7d2:	2b2d      	cmp	r3, #45	; 0x2d
     7d4:	d00c      	beq.n	7f0 <cbvprintf+0x1a4>
     7d6:	2b30      	cmp	r3, #48	; 0x30
     7d8:	f47f af6d 	bne.w	6b6 <cbvprintf+0x6a>
			conv->flag_zero = true;
     7dc:	2201      	movs	r2, #1
	} while (loop);
     7de:	e75c      	b.n	69a <cbvprintf+0x4e>
			conv->flag_plus = true;
     7e0:	f04f 0e01 	mov.w	lr, #1
     7e4:	e759      	b.n	69a <cbvprintf+0x4e>
			conv->flag_space = true;
     7e6:	2601      	movs	r6, #1
     7e8:	e757      	b.n	69a <cbvprintf+0x4e>
			conv->flag_hash = true;
     7ea:	f04f 0c01 	mov.w	ip, #1
     7ee:	e754      	b.n	69a <cbvprintf+0x4e>
		switch (*sp) {
     7f0:	2001      	movs	r0, #1
     7f2:	e752      	b.n	69a <cbvprintf+0x4e>
		val = 10U * val + *sp++ - '0';
     7f4:	fb0c 0202 	mla	r2, ip, r2, r0
     7f8:	3a30      	subs	r2, #48	; 0x30
     7fa:	4633      	mov	r3, r6
     7fc:	461e      	mov	r6, r3
     7fe:	f816 0b01 	ldrb.w	r0, [r6], #1
     802:	f1a0 0730 	sub.w	r7, r0, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     806:	2f09      	cmp	r7, #9
     808:	d9f4      	bls.n	7f4 <cbvprintf+0x1a8>
	if (sp != wp) {
     80a:	4299      	cmp	r1, r3
     80c:	d093      	beq.n	736 <cbvprintf+0xea>
		conv->unsupported |= ((conv->width_value < 0)
     80e:	f89d 1030 	ldrb.w	r1, [sp, #48]	; 0x30
		conv->width_value = width;
     812:	920d      	str	r2, [sp, #52]	; 0x34
				      || (width != (size_t)conv->width_value));
     814:	0fd2      	lsrs	r2, r2, #31
		conv->unsupported |= ((conv->width_value < 0)
     816:	f362 0141 	bfi	r1, r2, #1, #1
     81a:	f88d 1030 	strb.w	r1, [sp, #48]	; 0x30
     81e:	e78a      	b.n	736 <cbvprintf+0xea>
     820:	460b      	mov	r3, r1
	size_t val = 0;
     822:	2200      	movs	r2, #0
		val = 10U * val + *sp++ - '0';
     824:	f04f 0c0a 	mov.w	ip, #10
     828:	e7e8      	b.n	7fc <cbvprintf+0x1b0>
		conv->prec_star = true;
     82a:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     82e:	f042 0204 	orr.w	r2, r2, #4
     832:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
		return ++sp;
     836:	3302      	adds	r3, #2
	switch (*sp) {
     838:	461f      	mov	r7, r3
     83a:	f817 2b01 	ldrb.w	r2, [r7], #1
     83e:	2a6c      	cmp	r2, #108	; 0x6c
     840:	d041      	beq.n	8c6 <CONFIG_ISR_STACK_SIZE+0xc6>
     842:	d825      	bhi.n	890 <CONFIG_ISR_STACK_SIZE+0x90>
     844:	2a68      	cmp	r2, #104	; 0x68
     846:	d02b      	beq.n	8a0 <CONFIG_ISR_STACK_SIZE+0xa0>
     848:	2a6a      	cmp	r2, #106	; 0x6a
     84a:	d046      	beq.n	8da <CONFIG_ISR_STACK_SIZE+0xda>
     84c:	2a4c      	cmp	r2, #76	; 0x4c
     84e:	d04c      	beq.n	8ea <CONFIG_ISR_STACK_SIZE+0xea>
     850:	461f      	mov	r7, r3
	conv->specifier = *sp++;
     852:	f817 2b01 	ldrb.w	r2, [r7], #1
     856:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     85a:	f88d 2033 	strb.w	r2, [sp, #51]	; 0x33
	switch (conv->specifier) {
     85e:	2a78      	cmp	r2, #120	; 0x78
     860:	f200 80d9 	bhi.w	a16 <CONFIG_ISR_STACK_SIZE+0x216>
     864:	2a57      	cmp	r2, #87	; 0x57
     866:	d84d      	bhi.n	904 <CONFIG_ISR_STACK_SIZE+0x104>
     868:	2a41      	cmp	r2, #65	; 0x41
     86a:	d003      	beq.n	874 <CONFIG_ISR_STACK_SIZE+0x74>
     86c:	3a45      	subs	r2, #69	; 0x45
     86e:	2a02      	cmp	r2, #2
     870:	f200 80d1 	bhi.w	a16 <CONFIG_ISR_STACK_SIZE+0x216>
		conv->specifier_cat = SPECIFIER_FP;
     874:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
     878:	2204      	movs	r2, #4
     87a:	f362 0302 	bfi	r3, r2, #0, #3
     87e:	f88d 3032 	strb.w	r3, [sp, #50]	; 0x32
			unsupported = true;
     882:	2301      	movs	r3, #1
			break;
     884:	e09e      	b.n	9c4 <CONFIG_ISR_STACK_SIZE+0x1c4>
		val = 10U * val + *sp++ - '0';
     886:	fb06 2101 	mla	r1, r6, r1, r2
     88a:	3930      	subs	r1, #48	; 0x30
     88c:	4603      	mov	r3, r0
     88e:	e764      	b.n	75a <cbvprintf+0x10e>
	switch (*sp) {
     890:	2a74      	cmp	r2, #116	; 0x74
     892:	d026      	beq.n	8e2 <CONFIG_ISR_STACK_SIZE+0xe2>
     894:	2a7a      	cmp	r2, #122	; 0x7a
     896:	d1db      	bne.n	850 <CONFIG_ISR_STACK_SIZE+0x50>
		conv->length_mod = LENGTH_Z;
     898:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     89c:	2206      	movs	r2, #6
     89e:	e00d      	b.n	8bc <CONFIG_ISR_STACK_SIZE+0xbc>
		if (*++sp == 'h') {
     8a0:	785a      	ldrb	r2, [r3, #1]
     8a2:	2a68      	cmp	r2, #104	; 0x68
     8a4:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     8a8:	d106      	bne.n	8b8 <CONFIG_ISR_STACK_SIZE+0xb8>
			conv->length_mod = LENGTH_HH;
     8aa:	2101      	movs	r1, #1
			conv->length_mod = LENGTH_LL;
     8ac:	f361 02c6 	bfi	r2, r1, #3, #4
     8b0:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
			++sp;
     8b4:	1c9f      	adds	r7, r3, #2
     8b6:	e7cc      	b.n	852 <CONFIG_ISR_STACK_SIZE+0x52>
			conv->length_mod = LENGTH_H;
     8b8:	4613      	mov	r3, r2
     8ba:	2202      	movs	r2, #2
		conv->length_mod = LENGTH_T;
     8bc:	f362 03c6 	bfi	r3, r2, #3, #4
     8c0:	f88d 3031 	strb.w	r3, [sp, #49]	; 0x31
		break;
     8c4:	e7c5      	b.n	852 <CONFIG_ISR_STACK_SIZE+0x52>
		if (*++sp == 'l') {
     8c6:	785a      	ldrb	r2, [r3, #1]
     8c8:	2a6c      	cmp	r2, #108	; 0x6c
     8ca:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     8ce:	d101      	bne.n	8d4 <CONFIG_ISR_STACK_SIZE+0xd4>
			conv->length_mod = LENGTH_LL;
     8d0:	2104      	movs	r1, #4
     8d2:	e7eb      	b.n	8ac <CONFIG_ISR_STACK_SIZE+0xac>
			conv->length_mod = LENGTH_L;
     8d4:	4613      	mov	r3, r2
     8d6:	2203      	movs	r2, #3
     8d8:	e7f0      	b.n	8bc <CONFIG_ISR_STACK_SIZE+0xbc>
		conv->length_mod = LENGTH_J;
     8da:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     8de:	2205      	movs	r2, #5
     8e0:	e7ec      	b.n	8bc <CONFIG_ISR_STACK_SIZE+0xbc>
		conv->length_mod = LENGTH_T;
     8e2:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     8e6:	2207      	movs	r2, #7
     8e8:	e7e8      	b.n	8bc <CONFIG_ISR_STACK_SIZE+0xbc>
		conv->unsupported = true;
     8ea:	f8bd 3030 	ldrh.w	r3, [sp, #48]	; 0x30
     8ee:	f423 43f0 	bic.w	r3, r3, #30720	; 0x7800
     8f2:	f023 0302 	bic.w	r3, r3, #2
     8f6:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
     8fa:	f043 0302 	orr.w	r3, r3, #2
     8fe:	f8ad 3030 	strh.w	r3, [sp, #48]	; 0x30
		break;
     902:	e7a6      	b.n	852 <CONFIG_ISR_STACK_SIZE+0x52>
     904:	f1a2 0158 	sub.w	r1, r2, #88	; 0x58
     908:	2920      	cmp	r1, #32
     90a:	f200 8084 	bhi.w	a16 <CONFIG_ISR_STACK_SIZE+0x216>
     90e:	a001      	add	r0, pc, #4	; (adr r0, 914 <CONFIG_ISR_STACK_SIZE+0x114>)
     910:	f850 f021 	ldr.w	pc, [r0, r1, lsl #2]
     914:	000009d9 	.word	0x000009d9
     918:	00000a17 	.word	0x00000a17
     91c:	00000a17 	.word	0x00000a17
     920:	00000a17 	.word	0x00000a17
     924:	00000a17 	.word	0x00000a17
     928:	00000a17 	.word	0x00000a17
     92c:	00000a17 	.word	0x00000a17
     930:	00000a17 	.word	0x00000a17
     934:	00000a17 	.word	0x00000a17
     938:	00000875 	.word	0x00000875
     93c:	00000a17 	.word	0x00000a17
     940:	000009d9 	.word	0x000009d9
     944:	00000999 	.word	0x00000999
     948:	00000875 	.word	0x00000875
     94c:	00000875 	.word	0x00000875
     950:	00000875 	.word	0x00000875
     954:	00000a17 	.word	0x00000a17
     958:	00000999 	.word	0x00000999
     95c:	00000a17 	.word	0x00000a17
     960:	00000a17 	.word	0x00000a17
     964:	00000a17 	.word	0x00000a17
     968:	00000a17 	.word	0x00000a17
     96c:	000009e1 	.word	0x000009e1
     970:	000009d9 	.word	0x000009d9
     974:	000009fd 	.word	0x000009fd
     978:	00000a17 	.word	0x00000a17
     97c:	00000a17 	.word	0x00000a17
     980:	000009fd 	.word	0x000009fd
     984:	00000a17 	.word	0x00000a17
     988:	000009d9 	.word	0x000009d9
     98c:	00000a17 	.word	0x00000a17
     990:	00000a17 	.word	0x00000a17
     994:	000009d9 	.word	0x000009d9
		conv->specifier_cat = SPECIFIER_SINT;
     998:	f89d 1032 	ldrb.w	r1, [sp, #50]	; 0x32
     99c:	2001      	movs	r0, #1
		if (conv->length_mod == LENGTH_UPPER_L) {
     99e:	f003 0378 	and.w	r3, r3, #120	; 0x78
		conv->specifier_cat = SPECIFIER_UINT;
     9a2:	f360 0102 	bfi	r1, r0, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     9a6:	2b40      	cmp	r3, #64	; 0x40
		conv->specifier_cat = SPECIFIER_UINT;
     9a8:	f88d 1032 	strb.w	r1, [sp, #50]	; 0x32
			conv->invalid = true;
     9ac:	bf02      	ittt	eq
     9ae:	f89d 1030 	ldrbeq.w	r1, [sp, #48]	; 0x30
     9b2:	f041 0101 	orreq.w	r1, r1, #1
     9b6:	f88d 1030 	strbeq.w	r1, [sp, #48]	; 0x30
		if (conv->specifier == 'c') {
     9ba:	2a63      	cmp	r2, #99	; 0x63
     9bc:	d131      	bne.n	a22 <CONFIG_ISR_STACK_SIZE+0x222>
			unsupported = (conv->length_mod != LENGTH_NONE);
     9be:	3b00      	subs	r3, #0
     9c0:	bf18      	it	ne
     9c2:	2301      	movne	r3, #1
	conv->unsupported |= unsupported;
     9c4:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
     9c8:	f3c2 0140 	ubfx	r1, r2, #1, #1
     9cc:	430b      	orrs	r3, r1
     9ce:	f363 0241 	bfi	r2, r3, #1, #1
     9d2:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	return sp;
     9d6:	e6d8      	b.n	78a <cbvprintf+0x13e>
		conv->specifier_cat = SPECIFIER_UINT;
     9d8:	f89d 1032 	ldrb.w	r1, [sp, #50]	; 0x32
     9dc:	2002      	movs	r0, #2
     9de:	e7de      	b.n	99e <CONFIG_ISR_STACK_SIZE+0x19e>
		conv->specifier_cat = SPECIFIER_PTR;
     9e0:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod == LENGTH_UPPER_L) {
     9e4:	f003 0378 	and.w	r3, r3, #120	; 0x78
     9e8:	f1a3 0040 	sub.w	r0, r3, #64	; 0x40
		conv->specifier_cat = SPECIFIER_PTR;
     9ec:	2103      	movs	r1, #3
     9ee:	f361 0202 	bfi	r2, r1, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     9f2:	4243      	negs	r3, r0
		conv->specifier_cat = SPECIFIER_PTR;
     9f4:	f88d 2032 	strb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod == LENGTH_UPPER_L) {
     9f8:	4143      	adcs	r3, r0
     9fa:	e7e3      	b.n	9c4 <CONFIG_ISR_STACK_SIZE+0x1c4>
		conv->specifier_cat = SPECIFIER_PTR;
     9fc:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
     a00:	2103      	movs	r1, #3
		if (conv->length_mod != LENGTH_NONE) {
     a02:	f013 0f78 	tst.w	r3, #120	; 0x78
		conv->specifier_cat = SPECIFIER_PTR;
     a06:	f361 0202 	bfi	r2, r1, #0, #3
     a0a:	f88d 2032 	strb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod != LENGTH_NONE) {
     a0e:	bf14      	ite	ne
     a10:	2301      	movne	r3, #1
     a12:	2300      	moveq	r3, #0
     a14:	e7d6      	b.n	9c4 <CONFIG_ISR_STACK_SIZE+0x1c4>
		conv->invalid = true;
     a16:	f89d 3030 	ldrb.w	r3, [sp, #48]	; 0x30
     a1a:	f043 0301 	orr.w	r3, r3, #1
     a1e:	f88d 3030 	strb.w	r3, [sp, #48]	; 0x30
	bool unsupported = false;
     a22:	2300      	movs	r3, #0
     a24:	e7ce      	b.n	9c4 <CONFIG_ISR_STACK_SIZE+0x1c4>
		} else if (conv->width_present) {
     a26:	f99d 2030 	ldrsb.w	r2, [sp, #48]	; 0x30
     a2a:	2a00      	cmp	r2, #0
			width = conv->width_value;
     a2c:	bfb4      	ite	lt
     a2e:	f8dd 9034 	ldrlt.w	r9, [sp, #52]	; 0x34
		int width = -1;
     a32:	f04f 39ff 	movge.w	r9, #4294967295
     a36:	e6ba      	b.n	7ae <cbvprintf+0x162>
		} else if (conv->prec_present) {
     a38:	079b      	lsls	r3, r3, #30
     a3a:	f57f aec7 	bpl.w	7cc <cbvprintf+0x180>
			precision = conv->prec_value;
     a3e:	f8dd 8038 	ldr.w	r8, [sp, #56]	; 0x38
			= (enum length_mod_enum)conv->length_mod;
     a42:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
		conv->pad0_value = 0;
     a46:	2300      	movs	r3, #0
		conv->pad0_pre_exp = 0;
     a48:	e9cd 330d 	strd	r3, r3, [sp, #52]	; 0x34
			= (enum specifier_cat_enum)conv->specifier_cat;
     a4c:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
		enum specifier_cat_enum specifier_cat
     a50:	f003 0307 	and.w	r3, r3, #7
		if (specifier_cat == SPECIFIER_SINT) {
     a54:	2b01      	cmp	r3, #1
			= (enum length_mod_enum)conv->length_mod;
     a56:	f3c2 02c3 	ubfx	r2, r2, #3, #4
		if (specifier_cat == SPECIFIER_SINT) {
     a5a:	d136      	bne.n	aca <CONFIG_ISR_STACK_SIZE+0x2ca>
			switch (length_mod) {
     a5c:	1ed3      	subs	r3, r2, #3
     a5e:	2b04      	cmp	r3, #4
     a60:	d820      	bhi.n	aa4 <CONFIG_ISR_STACK_SIZE+0x2a4>
     a62:	e8df f003 	tbb	[pc, r3]
     a66:	0703      	.short	0x0703
     a68:	1f07      	.short	0x1f07
     a6a:	1f          	.byte	0x1f
     a6b:	00          	.byte	0x00
					value->sint = va_arg(ap, long);
     a6c:	f854 0b04 	ldr.w	r0, [r4], #4
				value->sint = (short)value->sint;
     a70:	17c1      	asrs	r1, r0, #31
     a72:	e004      	b.n	a7e <CONFIG_ISR_STACK_SIZE+0x27e>
					(sint_value_type)va_arg(ap, intmax_t);
     a74:	3407      	adds	r4, #7
     a76:	f024 0407 	bic.w	r4, r4, #7
				value->sint =
     a7a:	e8f4 0102 	ldrd	r0, r1, [r4], #8
				value->sint = (short)value->sint;
     a7e:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
		if (conv->invalid || conv->unsupported) {
     a82:	f89d 3030 	ldrb.w	r3, [sp, #48]	; 0x30
     a86:	f013 0603 	ands.w	r6, r3, #3
     a8a:	d054      	beq.n	b36 <CONFIG_ISR_STACK_SIZE+0x336>
			OUTS(sp, fp);
     a8c:	9802      	ldr	r0, [sp, #8]
     a8e:	463b      	mov	r3, r7
     a90:	4652      	mov	r2, sl
     a92:	4659      	mov	r1, fp
     a94:	f003 fc0d 	bl	42b2 <outs>
     a98:	2800      	cmp	r0, #0
     a9a:	f2c0 8143 	blt.w	d24 <CONFIG_ISR_STACK_SIZE+0x524>
     a9e:	4405      	add	r5, r0
			continue;
     aa0:	46ba      	mov	sl, r7
     aa2:	e5db      	b.n	65c <cbvprintf+0x10>
					(sint_value_type)va_arg(ap, ptrdiff_t);
     aa4:	f854 0b04 	ldr.w	r0, [r4], #4
			if (length_mod == LENGTH_HH) {
     aa8:	2a01      	cmp	r2, #1
					(sint_value_type)va_arg(ap, ptrdiff_t);
     aaa:	ea4f 71e0 	mov.w	r1, r0, asr #31
     aae:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
			if (length_mod == LENGTH_HH) {
     ab2:	d105      	bne.n	ac0 <CONFIG_ISR_STACK_SIZE+0x2c0>
				value->uint = (unsigned char)value->uint;
     ab4:	f89d 3028 	ldrb.w	r3, [sp, #40]	; 0x28
				value->uint = (unsigned short)value->uint;
     ab8:	930a      	str	r3, [sp, #40]	; 0x28
     aba:	2300      	movs	r3, #0
     abc:	930b      	str	r3, [sp, #44]	; 0x2c
     abe:	e7e0      	b.n	a82 <CONFIG_ISR_STACK_SIZE+0x282>
			} else if (length_mod == LENGTH_H) {
     ac0:	2a02      	cmp	r2, #2
     ac2:	d1de      	bne.n	a82 <CONFIG_ISR_STACK_SIZE+0x282>
				value->sint = (short)value->sint;
     ac4:	f9bd 0028 	ldrsh.w	r0, [sp, #40]	; 0x28
     ac8:	e7d2      	b.n	a70 <CONFIG_ISR_STACK_SIZE+0x270>
		} else if (specifier_cat == SPECIFIER_UINT) {
     aca:	2b02      	cmp	r3, #2
     acc:	d123      	bne.n	b16 <CONFIG_ISR_STACK_SIZE+0x316>
			switch (length_mod) {
     ace:	1ed3      	subs	r3, r2, #3
     ad0:	2b04      	cmp	r3, #4
     ad2:	d813      	bhi.n	afc <CONFIG_ISR_STACK_SIZE+0x2fc>
     ad4:	e8df f003 	tbb	[pc, r3]
     ad8:	120a0a03 	.word	0x120a0a03
     adc:	12          	.byte	0x12
     add:	00          	.byte	0x00
					value->uint = (wchar_t)va_arg(ap,
     ade:	6820      	ldr	r0, [r4, #0]
     ae0:	900a      	str	r0, [sp, #40]	; 0x28
     ae2:	2100      	movs	r1, #0
     ae4:	1d23      	adds	r3, r4, #4
     ae6:	910b      	str	r1, [sp, #44]	; 0x2c
					(uint_value_type)va_arg(ap, size_t);
     ae8:	461c      	mov	r4, r3
     aea:	e7ca      	b.n	a82 <CONFIG_ISR_STACK_SIZE+0x282>
					(uint_value_type)va_arg(ap,
     aec:	3407      	adds	r4, #7
     aee:	f024 0307 	bic.w	r3, r4, #7
				value->uint =
     af2:	e8f3 0102 	ldrd	r0, r1, [r3], #8
     af6:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
				break;
     afa:	e7f5      	b.n	ae8 <CONFIG_ISR_STACK_SIZE+0x2e8>
					(uint_value_type)va_arg(ap, size_t);
     afc:	f854 3b04 	ldr.w	r3, [r4], #4
     b00:	930a      	str	r3, [sp, #40]	; 0x28
			if (length_mod == LENGTH_HH) {
     b02:	2a01      	cmp	r2, #1
					(uint_value_type)va_arg(ap, size_t);
     b04:	f04f 0300 	mov.w	r3, #0
     b08:	930b      	str	r3, [sp, #44]	; 0x2c
			if (length_mod == LENGTH_HH) {
     b0a:	d0d3      	beq.n	ab4 <CONFIG_ISR_STACK_SIZE+0x2b4>
			} else if (length_mod == LENGTH_H) {
     b0c:	2a02      	cmp	r2, #2
     b0e:	d1b8      	bne.n	a82 <CONFIG_ISR_STACK_SIZE+0x282>
				value->uint = (unsigned short)value->uint;
     b10:	f8bd 3028 	ldrh.w	r3, [sp, #40]	; 0x28
     b14:	e7d0      	b.n	ab8 <CONFIG_ISR_STACK_SIZE+0x2b8>
		} else if (specifier_cat == SPECIFIER_FP) {
     b16:	2b04      	cmp	r3, #4
     b18:	d107      	bne.n	b2a <CONFIG_ISR_STACK_SIZE+0x32a>
			if (length_mod == LENGTH_UPPER_L) {
     b1a:	3407      	adds	r4, #7
     b1c:	f024 0407 	bic.w	r4, r4, #7
     b20:	e8f4 0102 	ldrd	r0, r1, [r4], #8
				value->ldbl = va_arg(ap, long double);
     b24:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
     b28:	e7ab      	b.n	a82 <CONFIG_ISR_STACK_SIZE+0x282>
		} else if (specifier_cat == SPECIFIER_PTR) {
     b2a:	2b03      	cmp	r3, #3
			value->ptr = va_arg(ap, void *);
     b2c:	bf04      	itt	eq
     b2e:	f854 3b04 	ldreq.w	r3, [r4], #4
     b32:	930a      	streq	r3, [sp, #40]	; 0x28
     b34:	e7a5      	b.n	a82 <CONFIG_ISR_STACK_SIZE+0x282>
		switch (conv->specifier) {
     b36:	f89d 0033 	ldrb.w	r0, [sp, #51]	; 0x33
     b3a:	2878      	cmp	r0, #120	; 0x78
     b3c:	d8b0      	bhi.n	aa0 <CONFIG_ISR_STACK_SIZE+0x2a0>
     b3e:	2862      	cmp	r0, #98	; 0x62
     b40:	d822      	bhi.n	b88 <CONFIG_ISR_STACK_SIZE+0x388>
     b42:	2825      	cmp	r0, #37	; 0x25
     b44:	f43f ad93 	beq.w	66e <cbvprintf+0x22>
     b48:	2858      	cmp	r0, #88	; 0x58
     b4a:	d1a9      	bne.n	aa0 <CONFIG_ISR_STACK_SIZE+0x2a0>
			bps = encode_uint(value->uint, conv, buf, bpe);
     b4c:	f10d 0326 	add.w	r3, sp, #38	; 0x26
     b50:	9300      	str	r3, [sp, #0]
     b52:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	; 0x28
     b56:	ab04      	add	r3, sp, #16
     b58:	aa0c      	add	r2, sp, #48	; 0x30
     b5a:	f003 fb5f 	bl	421c <encode_uint>
     b5e:	4682      	mov	sl, r0
			if (precision >= 0) {
     b60:	f1b8 0f00 	cmp.w	r8, #0
     b64:	f10d 0026 	add.w	r0, sp, #38	; 0x26
     b68:	db0c      	blt.n	b84 <CONFIG_ISR_STACK_SIZE+0x384>
				conv->flag_zero = false;
     b6a:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
				size_t len = bpe - bps;
     b6e:	eba0 030a 	sub.w	r3, r0, sl
				conv->flag_zero = false;
     b72:	f36f 1286 	bfc	r2, #6, #1
				if (len < (size_t)precision) {
     b76:	4598      	cmp	r8, r3
				conv->flag_zero = false;
     b78:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
				if (len < (size_t)precision) {
     b7c:	d902      	bls.n	b84 <CONFIG_ISR_STACK_SIZE+0x384>
					conv->pad0_value = precision - (int)len;
     b7e:	eba8 0303 	sub.w	r3, r8, r3
     b82:	930d      	str	r3, [sp, #52]	; 0x34
		const char *bpe = buf + sizeof(buf);
     b84:	4680      	mov	r8, r0
     b86:	e03d      	b.n	c04 <CONFIG_ISR_STACK_SIZE+0x404>
     b88:	3863      	subs	r0, #99	; 0x63
     b8a:	2815      	cmp	r0, #21
     b8c:	d888      	bhi.n	aa0 <CONFIG_ISR_STACK_SIZE+0x2a0>
     b8e:	a101      	add	r1, pc, #4	; (adr r1, b94 <CONFIG_ISR_STACK_SIZE+0x394>)
     b90:	f851 f020 	ldr.w	pc, [r1, r0, lsl #2]
     b94:	00000c15 	.word	0x00000c15
     b98:	00000c79 	.word	0x00000c79
     b9c:	00000aa1 	.word	0x00000aa1
     ba0:	00000aa1 	.word	0x00000aa1
     ba4:	00000aa1 	.word	0x00000aa1
     ba8:	00000aa1 	.word	0x00000aa1
     bac:	00000c79 	.word	0x00000c79
     bb0:	00000aa1 	.word	0x00000aa1
     bb4:	00000aa1 	.word	0x00000aa1
     bb8:	00000aa1 	.word	0x00000aa1
     bbc:	00000aa1 	.word	0x00000aa1
     bc0:	00000cd7 	.word	0x00000cd7
     bc4:	00000ca5 	.word	0x00000ca5
     bc8:	00000ca9 	.word	0x00000ca9
     bcc:	00000aa1 	.word	0x00000aa1
     bd0:	00000aa1 	.word	0x00000aa1
     bd4:	00000bed 	.word	0x00000bed
     bd8:	00000aa1 	.word	0x00000aa1
     bdc:	00000ca5 	.word	0x00000ca5
     be0:	00000aa1 	.word	0x00000aa1
     be4:	00000aa1 	.word	0x00000aa1
     be8:	00000ca5 	.word	0x00000ca5
			if (precision >= 0) {
     bec:	f1b8 0f00 	cmp.w	r8, #0
			bps = (const char *)value->ptr;
     bf0:	f8dd a028 	ldr.w	sl, [sp, #40]	; 0x28
			if (precision >= 0) {
     bf4:	db0a      	blt.n	c0c <CONFIG_ISR_STACK_SIZE+0x40c>
				len = strnlen(bps, precision);
     bf6:	4641      	mov	r1, r8
     bf8:	4650      	mov	r0, sl
     bfa:	f003 fb9c 	bl	4336 <strnlen>
			bpe = bps + len;
     bfe:	eb0a 0800 	add.w	r8, sl, r0
		char sign = 0;
     c02:	2600      	movs	r6, #0
		if (bps == NULL) {
     c04:	f1ba 0f00 	cmp.w	sl, #0
     c08:	d10c      	bne.n	c24 <CONFIG_ISR_STACK_SIZE+0x424>
     c0a:	e749      	b.n	aa0 <CONFIG_ISR_STACK_SIZE+0x2a0>
				len = strlen(bps);
     c0c:	4650      	mov	r0, sl
     c0e:	f003 fb8b 	bl	4328 <strlen>
     c12:	e7f4      	b.n	bfe <CONFIG_ISR_STACK_SIZE+0x3fe>
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     c14:	9b0a      	ldr	r3, [sp, #40]	; 0x28
     c16:	f88d 3010 	strb.w	r3, [sp, #16]
			break;
     c1a:	2600      	movs	r6, #0
			bpe = buf + 1;
     c1c:	f10d 0811 	add.w	r8, sp, #17
			bps = buf;
     c20:	f10d 0a10 	add.w	sl, sp, #16
		size_t nj_len = (bpe - bps);
     c24:	eba8 030a 	sub.w	r3, r8, sl
		if (sign != 0) {
     c28:	b106      	cbz	r6, c2c <CONFIG_ISR_STACK_SIZE+0x42c>
			nj_len += 1U;
     c2a:	3301      	adds	r3, #1
		if (conv->altform_0c) {
     c2c:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
     c30:	06d0      	lsls	r0, r2, #27
     c32:	d56b      	bpl.n	d0c <CONFIG_ISR_STACK_SIZE+0x50c>
			nj_len += 2U;
     c34:	3302      	adds	r3, #2
		if (conv->pad_fp) {
     c36:	0652      	lsls	r2, r2, #25
		nj_len += conv->pad0_value;
     c38:	990d      	ldr	r1, [sp, #52]	; 0x34
			nj_len += conv->pad0_pre_exp;
     c3a:	bf48      	it	mi
     c3c:	9a0e      	ldrmi	r2, [sp, #56]	; 0x38
		nj_len += conv->pad0_value;
     c3e:	440b      	add	r3, r1
			nj_len += conv->pad0_pre_exp;
     c40:	bf48      	it	mi
     c42:	189b      	addmi	r3, r3, r2
		if (width > 0) {
     c44:	f1b9 0f00 	cmp.w	r9, #0
     c48:	dd79      	ble.n	d3e <CONFIG_ISR_STACK_SIZE+0x53e>
			if (!conv->flag_dash) {
     c4a:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
			width -= (int)nj_len;
     c4e:	eba9 0903 	sub.w	r9, r9, r3
			if (!conv->flag_dash) {
     c52:	f3c2 0380 	ubfx	r3, r2, #2, #1
     c56:	9303      	str	r3, [sp, #12]
     c58:	0753      	lsls	r3, r2, #29
     c5a:	d470      	bmi.n	d3e <CONFIG_ISR_STACK_SIZE+0x53e>
				if (conv->flag_zero) {
     c5c:	0650      	lsls	r0, r2, #25
     c5e:	d564      	bpl.n	d2a <CONFIG_ISR_STACK_SIZE+0x52a>
					if (sign != 0) {
     c60:	b146      	cbz	r6, c74 <CONFIG_ISR_STACK_SIZE+0x474>
						OUTC(sign);
     c62:	9b02      	ldr	r3, [sp, #8]
     c64:	4659      	mov	r1, fp
     c66:	4630      	mov	r0, r6
     c68:	4798      	blx	r3
     c6a:	2800      	cmp	r0, #0
     c6c:	db5a      	blt.n	d24 <CONFIG_ISR_STACK_SIZE+0x524>
						sign = 0;
     c6e:	9b03      	ldr	r3, [sp, #12]
						OUTC(sign);
     c70:	3501      	adds	r5, #1
						sign = 0;
     c72:	461e      	mov	r6, r3
					pad = '0';
     c74:	2330      	movs	r3, #48	; 0x30
     c76:	e059      	b.n	d2c <CONFIG_ISR_STACK_SIZE+0x52c>
			if (conv->flag_plus) {
     c78:	071e      	lsls	r6, r3, #28
     c7a:	d411      	bmi.n	ca0 <CONFIG_ISR_STACK_SIZE+0x4a0>
				sign = ' ';
     c7c:	f013 0610 	ands.w	r6, r3, #16
     c80:	bf18      	it	ne
     c82:	2620      	movne	r6, #32
			sint = value->sint;
     c84:	e9dd 230a 	ldrd	r2, r3, [sp, #40]	; 0x28
			if (sint < 0) {
     c88:	2a00      	cmp	r2, #0
     c8a:	f173 0100 	sbcs.w	r1, r3, #0
     c8e:	f6bf af5d 	bge.w	b4c <CONFIG_ISR_STACK_SIZE+0x34c>
				value->uint = (uint_value_type)-sint;
     c92:	4252      	negs	r2, r2
     c94:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
     c98:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
				sign = '-';
     c9c:	262d      	movs	r6, #45	; 0x2d
     c9e:	e755      	b.n	b4c <CONFIG_ISR_STACK_SIZE+0x34c>
				sign = '+';
     ca0:	262b      	movs	r6, #43	; 0x2b
     ca2:	e7ef      	b.n	c84 <CONFIG_ISR_STACK_SIZE+0x484>
		switch (conv->specifier) {
     ca4:	2600      	movs	r6, #0
     ca6:	e751      	b.n	b4c <CONFIG_ISR_STACK_SIZE+0x34c>
			if (value->ptr != NULL) {
     ca8:	980a      	ldr	r0, [sp, #40]	; 0x28
     caa:	b348      	cbz	r0, d00 <CONFIG_ISR_STACK_SIZE+0x500>
				bps = encode_uint((uintptr_t)value->ptr, conv,
     cac:	f10d 0326 	add.w	r3, sp, #38	; 0x26
     cb0:	9300      	str	r3, [sp, #0]
     cb2:	aa0c      	add	r2, sp, #48	; 0x30
     cb4:	ab04      	add	r3, sp, #16
     cb6:	2100      	movs	r1, #0
     cb8:	f003 fab0 	bl	421c <encode_uint>
				conv->altform_0c = true;
     cbc:	f8bd 3032 	ldrh.w	r3, [sp, #50]	; 0x32
     cc0:	f003 03ef 	and.w	r3, r3, #239	; 0xef
     cc4:	f443 43f0 	orr.w	r3, r3, #30720	; 0x7800
     cc8:	f043 0310 	orr.w	r3, r3, #16
				bps = encode_uint((uintptr_t)value->ptr, conv,
     ccc:	4682      	mov	sl, r0
				conv->altform_0c = true;
     cce:	f8ad 3032 	strh.w	r3, [sp, #50]	; 0x32
		char sign = 0;
     cd2:	2600      	movs	r6, #0
				goto prec_int_pad0;
     cd4:	e744      	b.n	b60 <CONFIG_ISR_STACK_SIZE+0x360>
				store_count(conv, value->ptr, count);
     cd6:	9b0a      	ldr	r3, [sp, #40]	; 0x28
	switch ((enum length_mod_enum)conv->length_mod) {
     cd8:	2a07      	cmp	r2, #7
     cda:	f63f aee1 	bhi.w	aa0 <CONFIG_ISR_STACK_SIZE+0x2a0>
     cde:	e8df f002 	tbb	[pc, r2]
     ce2:	040d      	.short	0x040d
     ce4:	08080d06 	.word	0x08080d06
     ce8:	0d0d      	.short	0x0d0d
		*(signed char *)dp = (signed char)count;
     cea:	701d      	strb	r5, [r3, #0]
		break;
     cec:	e6d8      	b.n	aa0 <CONFIG_ISR_STACK_SIZE+0x2a0>
		*(short *)dp = (short)count;
     cee:	801d      	strh	r5, [r3, #0]
		break;
     cf0:	e6d6      	b.n	aa0 <CONFIG_ISR_STACK_SIZE+0x2a0>
		*(intmax_t *)dp = (intmax_t)count;
     cf2:	4628      	mov	r0, r5
     cf4:	17e9      	asrs	r1, r5, #31
     cf6:	e9c3 0100 	strd	r0, r1, [r3]
		break;
     cfa:	e6d1      	b.n	aa0 <CONFIG_ISR_STACK_SIZE+0x2a0>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
     cfc:	601d      	str	r5, [r3, #0]
		break;
     cfe:	e6cf      	b.n	aa0 <CONFIG_ISR_STACK_SIZE+0x2a0>
			bpe = bps + 5;
     d00:	f8df 80c4 	ldr.w	r8, [pc, #196]	; dc8 <CONFIG_ISR_STACK_SIZE+0x5c8>
     d04:	4606      	mov	r6, r0
			bps = "(nil)";
     d06:	f1a8 0a05 	sub.w	sl, r8, #5
     d0a:	e78b      	b.n	c24 <CONFIG_ISR_STACK_SIZE+0x424>
		} else if (conv->altform_0) {
     d0c:	0711      	lsls	r1, r2, #28
			nj_len += 1U;
     d0e:	bf48      	it	mi
     d10:	3301      	addmi	r3, #1
     d12:	e790      	b.n	c36 <CONFIG_ISR_STACK_SIZE+0x436>
					OUTC(pad);
     d14:	4618      	mov	r0, r3
     d16:	9303      	str	r3, [sp, #12]
     d18:	4659      	mov	r1, fp
     d1a:	9b02      	ldr	r3, [sp, #8]
     d1c:	4798      	blx	r3
     d1e:	2800      	cmp	r0, #0
     d20:	9b03      	ldr	r3, [sp, #12]
     d22:	da04      	bge.n	d2e <CONFIG_ISR_STACK_SIZE+0x52e>
#undef OUTS
#undef OUTC
}
     d24:	b011      	add	sp, #68	; 0x44
     d26:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				char pad = ' ';
     d2a:	2320      	movs	r3, #32
     d2c:	444d      	add	r5, r9
     d2e:	464a      	mov	r2, r9
				while (width-- > 0) {
     d30:	2a00      	cmp	r2, #0
     d32:	eba5 0109 	sub.w	r1, r5, r9
     d36:	f109 39ff 	add.w	r9, r9, #4294967295
     d3a:	dceb      	bgt.n	d14 <CONFIG_ISR_STACK_SIZE+0x514>
     d3c:	460d      	mov	r5, r1
		if (sign != 0) {
     d3e:	b136      	cbz	r6, d4e <CONFIG_ISR_STACK_SIZE+0x54e>
			OUTC(sign);
     d40:	9b02      	ldr	r3, [sp, #8]
     d42:	4659      	mov	r1, fp
     d44:	4630      	mov	r0, r6
     d46:	4798      	blx	r3
     d48:	2800      	cmp	r0, #0
     d4a:	dbeb      	blt.n	d24 <CONFIG_ISR_STACK_SIZE+0x524>
     d4c:	3501      	adds	r5, #1
			if (conv->altform_0c | conv->altform_0) {
     d4e:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
     d52:	06d9      	lsls	r1, r3, #27
     d54:	d401      	bmi.n	d5a <CONFIG_ISR_STACK_SIZE+0x55a>
     d56:	071a      	lsls	r2, r3, #28
     d58:	d506      	bpl.n	d68 <CONFIG_ISR_STACK_SIZE+0x568>
				OUTC('0');
     d5a:	9b02      	ldr	r3, [sp, #8]
     d5c:	4659      	mov	r1, fp
     d5e:	2030      	movs	r0, #48	; 0x30
     d60:	4798      	blx	r3
     d62:	2800      	cmp	r0, #0
     d64:	dbde      	blt.n	d24 <CONFIG_ISR_STACK_SIZE+0x524>
     d66:	3501      	adds	r5, #1
			if (conv->altform_0c) {
     d68:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
     d6c:	06db      	lsls	r3, r3, #27
     d6e:	d507      	bpl.n	d80 <CONFIG_ISR_STACK_SIZE+0x580>
				OUTC(conv->specifier);
     d70:	f89d 0033 	ldrb.w	r0, [sp, #51]	; 0x33
     d74:	9b02      	ldr	r3, [sp, #8]
     d76:	4659      	mov	r1, fp
     d78:	4798      	blx	r3
     d7a:	2800      	cmp	r0, #0
     d7c:	dbd2      	blt.n	d24 <CONFIG_ISR_STACK_SIZE+0x524>
     d7e:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
     d80:	9e0d      	ldr	r6, [sp, #52]	; 0x34
     d82:	442e      	add	r6, r5
     d84:	1b73      	subs	r3, r6, r5
     d86:	2b00      	cmp	r3, #0
     d88:	dc16      	bgt.n	db8 <CONFIG_ISR_STACK_SIZE+0x5b8>
			OUTS(bps, bpe);
     d8a:	9802      	ldr	r0, [sp, #8]
     d8c:	4643      	mov	r3, r8
     d8e:	4652      	mov	r2, sl
     d90:	4659      	mov	r1, fp
     d92:	f003 fa8e 	bl	42b2 <outs>
     d96:	2800      	cmp	r0, #0
     d98:	dbc4      	blt.n	d24 <CONFIG_ISR_STACK_SIZE+0x524>
     d9a:	4405      	add	r5, r0
		while (width > 0) {
     d9c:	44a9      	add	r9, r5
     d9e:	eba9 0305 	sub.w	r3, r9, r5
     da2:	2b00      	cmp	r3, #0
     da4:	f77f ae7c 	ble.w	aa0 <CONFIG_ISR_STACK_SIZE+0x2a0>
			OUTC(' ');
     da8:	9b02      	ldr	r3, [sp, #8]
     daa:	4659      	mov	r1, fp
     dac:	2020      	movs	r0, #32
     dae:	4798      	blx	r3
     db0:	2800      	cmp	r0, #0
     db2:	dbb7      	blt.n	d24 <CONFIG_ISR_STACK_SIZE+0x524>
     db4:	3501      	adds	r5, #1
			--width;
     db6:	e7f2      	b.n	d9e <CONFIG_ISR_STACK_SIZE+0x59e>
				OUTC('0');
     db8:	9b02      	ldr	r3, [sp, #8]
     dba:	4659      	mov	r1, fp
     dbc:	2030      	movs	r0, #48	; 0x30
     dbe:	4798      	blx	r3
     dc0:	2800      	cmp	r0, #0
     dc2:	dbaf      	blt.n	d24 <CONFIG_ISR_STACK_SIZE+0x524>
     dc4:	3501      	adds	r5, #1
     dc6:	e7dd      	b.n	d84 <CONFIG_ISR_STACK_SIZE+0x584>
     dc8:	00004e38 	.word	0x00004e38

00000dcc <sys_reboot>:

extern void sys_arch_reboot(int type);
extern void sys_clock_disable(void);

FUNC_NORETURN void sys_reboot(int type)
{
     dcc:	b508      	push	{r3, lr}
     dce:	4604      	mov	r4, r0
     dd0:	f04f 0220 	mov.w	r2, #32
     dd4:	f3ef 8311 	mrs	r3, BASEPRI
     dd8:	f382 8812 	msr	BASEPRI_MAX, r2
     ddc:	f3bf 8f6f 	isb	sy
	(void)irq_lock();
#ifdef CONFIG_SYS_CLOCK_EXISTS
	sys_clock_disable();
     de0:	f003 fc82 	bl	46e8 <sys_clock_disable>
#endif

	sys_arch_reboot(type);
     de4:	4620      	mov	r0, r4
     de6:	f000 fcff 	bl	17e8 <sys_arch_reboot>

	/* should never get here */
	printk("Failed to reboot: spinning endlessly...\n");
     dea:	4803      	ldr	r0, [pc, #12]	; (df8 <sys_reboot+0x2c>)
     dec:	f003 f954 	bl	4098 <printk>
 *
 * @return N/A
 */
static inline void k_cpu_idle(void)
{
	arch_cpu_idle();
     df0:	f000 f964 	bl	10bc <arch_cpu_idle>
     df4:	e7fc      	b.n	df0 <sys_reboot+0x24>
     df6:	bf00      	nop
     df8:	00004e39 	.word	0x00004e39

00000dfc <pm_state_notify>:
/*
 * Function called to notify when the system is entering / exiting a
 * power state
 */
static inline void pm_state_notify(bool entering_state)
{
     dfc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
     dfe:	4605      	mov	r5, r0
     e00:	f04f 0320 	mov.w	r3, #32
     e04:	f3ef 8611 	mrs	r6, BASEPRI
     e08:	f383 8812 	msr	BASEPRI_MAX, r3
     e0c:	f3bf 8f6f 	isb	sy
	struct pm_notifier *notifier;
	k_spinlock_key_t pm_notifier_key;
	void (*callback)(enum pm_state state);

	pm_notifier_key = k_spin_lock(&pm_notifier_lock);
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
     e10:	4b0b      	ldr	r3, [pc, #44]	; (e40 <pm_state_notify+0x44>)
     e12:	681c      	ldr	r4, [r3, #0]
     e14:	2c00      	cmp	r4, #0
     e16:	bf38      	it	cc
     e18:	2400      	movcc	r4, #0
     e1a:	b15c      	cbz	r4, e34 <pm_state_notify+0x38>
		} else {
			callback = notifier->state_exit;
		}

		if (callback) {
			callback(z_power_state.state);
     e1c:	4f09      	ldr	r7, [pc, #36]	; (e44 <pm_state_notify+0x48>)
			callback = notifier->state_exit;
     e1e:	e9d4 3201 	ldrd	r3, r2, [r4, #4]
     e22:	2d00      	cmp	r5, #0
     e24:	bf08      	it	eq
     e26:	4613      	moveq	r3, r2
		if (callback) {
     e28:	b10b      	cbz	r3, e2e <pm_state_notify+0x32>
			callback(z_power_state.state);
     e2a:	7838      	ldrb	r0, [r7, #0]
     e2c:	4798      	blx	r3
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     e2e:	6824      	ldr	r4, [r4, #0]
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
     e30:	2c00      	cmp	r4, #0
     e32:	d1f4      	bne.n	e1e <pm_state_notify+0x22>
	__asm__ volatile(
     e34:	f386 8811 	msr	BASEPRI, r6
     e38:	f3bf 8f6f 	isb	sy
		}
	}
	k_spin_unlock(&pm_notifier_lock, pm_notifier_key);
}
     e3c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
     e3e:	bf00      	nop
     e40:	20000238 	.word	0x20000238
     e44:	20000240 	.word	0x20000240

00000e48 <pm_system_resume>:

void pm_system_resume(void)
{
     e48:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	 * and it may schedule another thread.
	 *
	 * Call pm_idle_exit_notification_disable() if this
	 * notification is not required.
	 */
	if (!post_ops_done) {
     e4a:	4b0f      	ldr	r3, [pc, #60]	; (e88 <pm_system_resume+0x40>)
     e4c:	681a      	ldr	r2, [r3, #0]
     e4e:	b9ba      	cbnz	r2, e80 <pm_system_resume+0x38>
		post_ops_done = 1;
     e50:	2201      	movs	r2, #1
     e52:	601a      	str	r2, [r3, #0]
		exit_pos_ops(z_power_state);
     e54:	4a0d      	ldr	r2, [pc, #52]	; (e8c <pm_system_resume+0x44>)
     e56:	ca07      	ldmia	r2, {r0, r1, r2}
     e58:	ab01      	add	r3, sp, #4
     e5a:	e883 0007 	stmia.w	r3, {r0, r1, r2}
	if (pm_power_state_exit_post_ops != NULL) {
     e5e:	4a0c      	ldr	r2, [pc, #48]	; (e90 <pm_system_resume+0x48>)
     e60:	b14a      	cbz	r2, e76 <pm_system_resume+0x2e>
		pm_power_state_exit_post_ops(info);
     e62:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
     e66:	f003 faa2 	bl	43ae <pm_power_state_exit_post_ops>
		pm_state_notify(false);
     e6a:	2000      	movs	r0, #0
	}
}
     e6c:	b005      	add	sp, #20
     e6e:	f85d eb04 	ldr.w	lr, [sp], #4
		pm_state_notify(false);
     e72:	f7ff bfc3 	b.w	dfc <pm_state_notify>
     e76:	f382 8811 	msr	BASEPRI, r2
     e7a:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
     e7e:	e7f4      	b.n	e6a <pm_system_resume+0x22>
}
     e80:	b005      	add	sp, #20
     e82:	f85d fb04 	ldr.w	pc, [sp], #4
     e86:	bf00      	nop
     e88:	20000004 	.word	0x20000004
     e8c:	20000240 	.word	0x20000240
     e90:	000043af 	.word	0x000043af

00000e94 <pm_system_suspend>:
	return PM_STATE_ACTIVE;
}
#endif

enum pm_state pm_system_suspend(int32_t ticks)
{
     e94:	b5f0      	push	{r4, r5, r6, r7, lr}
     e96:	b089      	sub	sp, #36	; 0x24
	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);
	z_power_state = pm_policy_next_state(ticks);
     e98:	466e      	mov	r6, sp
     e9a:	4601      	mov	r1, r0
{
     e9c:	4605      	mov	r5, r0
	z_power_state = pm_policy_next_state(ticks);
     e9e:	4630      	mov	r0, r6
     ea0:	f003 fa1e 	bl	42e0 <pm_policy_next_state>
     ea4:	e896 0007 	ldmia.w	r6, {r0, r1, r2}
     ea8:	4c17      	ldr	r4, [pc, #92]	; (f08 <pm_system_suspend+0x74>)
     eaa:	e884 0007 	stmia.w	r4, {r0, r1, r2}
	if (z_power_state.state == PM_STATE_ACTIVE) {
     eae:	7820      	ldrb	r0, [r4, #0]
     eb0:	b340      	cbz	r0, f04 <pm_system_suspend+0x70>
		LOG_DBG("No PM operations done.");
		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks, z_power_state.state);
		return z_power_state.state;
	}
	post_ops_done = 0;
     eb2:	4b16      	ldr	r3, [pc, #88]	; (f0c <pm_system_suspend+0x78>)
     eb4:	2100      	movs	r1, #0
     eb6:	6019      	str	r1, [r3, #0]

	if (ticks != K_TICKS_FOREVER) {
     eb8:	1c6b      	adds	r3, r5, #1
     eba:	d00e      	beq.n	eda <pm_system_suspend+0x46>
		} else {
			return t * ((uint64_t)to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
     ebc:	4814      	ldr	r0, [pc, #80]	; (f10 <pm_system_suspend+0x7c>)
     ebe:	4617      	mov	r7, r2
     ec0:	f44f 4600 	mov.w	r6, #32768	; 0x8000
     ec4:	2100      	movs	r1, #0
     ec6:	4a13      	ldr	r2, [pc, #76]	; (f14 <pm_system_suspend+0x80>)
     ec8:	2300      	movs	r3, #0
     eca:	fbe6 0107 	umlal	r0, r1, r6, r7
     ece:	f7ff f917 	bl	100 <__aeabi_uldivmod>

		/*
		 * We need to set the timer to interrupt a little bit early to
		 * accommodate the time required by the CPU to fully wake up.
		 */
		z_set_timeout_expiry(ticks -
     ed2:	2101      	movs	r1, #1
     ed4:	1a28      	subs	r0, r5, r0
     ed6:	f003 fd78 	bl	49ca <z_set_timeout_expiry>
	 * state. We don't want to be scheduled out yet, first we need
	 * to send a notification about leaving the idle state. So,
	 * we lock the scheduler here and unlock just after we have
	 * sent the notification in pm_system_resume().
	 */
	k_sched_lock();
     eda:	f002 fa63 	bl	33a4 <k_sched_lock>
	pm_debug_start_timer();
	/* Enter power state */
	pm_state_notify(true);
     ede:	2001      	movs	r0, #1
     ee0:	f7ff ff8c 	bl	dfc <pm_state_notify>
	pm_state_set(z_power_state);
     ee4:	e894 0007 	ldmia.w	r4, {r0, r1, r2}
     ee8:	ab05      	add	r3, sp, #20
     eea:	e883 0007 	stmia.w	r3, {r0, r1, r2}
	if (pm_power_state_set != NULL) {
     eee:	4a0a      	ldr	r2, [pc, #40]	; (f18 <pm_system_suspend+0x84>)
     ef0:	b11a      	cbz	r2, efa <pm_system_suspend+0x66>
		pm_power_state_set(info);
     ef2:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
     ef6:	f003 fa47 	bl	4388 <pm_power_state_set>
		/* Turn on peripherals and restore device states as necessary */
		pm_resume_devices();
	}
#endif
	pm_log_debug_info(z_power_state.state);
	pm_system_resume();
     efa:	f7ff ffa5 	bl	e48 <pm_system_resume>
	k_sched_unlock();
     efe:	f002 fc2b 	bl	3758 <k_sched_unlock>
	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks, z_power_state.state);
	return z_power_state.state;
     f02:	7820      	ldrb	r0, [r4, #0]
}
     f04:	b009      	add	sp, #36	; 0x24
     f06:	bdf0      	pop	{r4, r5, r6, r7, pc}
     f08:	20000240 	.word	0x20000240
     f0c:	20000004 	.word	0x20000004
     f10:	000f423f 	.word	0x000f423f
     f14:	000f4240 	.word	0x000f4240
     f18:	00004389 	.word	0x00004389

00000f1c <nrf_cc3xx_platform_abort_init>:

/** @brief Function to initialize the nrf_cc3xx_platform abort APIs.
 */
void nrf_cc3xx_platform_abort_init(void)
{
	nrf_cc3xx_platform_set_abort(&apis);
     f1c:	4801      	ldr	r0, [pc, #4]	; (f24 <nrf_cc3xx_platform_abort_init+0x8>)
     f1e:	f002 bf09 	b.w	3d34 <nrf_cc3xx_platform_set_abort>
     f22:	bf00      	nop
     f24:	00004c98 	.word	0x00004c98

00000f28 <mutex_unlock_platform>:
    }
}

/** @brief Static function to unlock a mutex
 */
static int32_t mutex_unlock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
     f28:	b508      	push	{r3, lr}
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
     f2a:	b1d0      	cbz	r0, f62 <mutex_unlock_platform+0x3a>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    switch (mutex->flags)
     f2c:	6843      	ldr	r3, [r0, #4]
     f2e:	2b04      	cmp	r3, #4
     f30:	d111      	bne.n	f56 <mutex_unlock_platform+0x2e>
 * @return true if @a new_value is written, false otherwise.
 */
static inline bool atomic_cas(atomic_t *target, atomic_val_t old_value,
			  atomic_val_t new_value)
{
	return __atomic_compare_exchange_n(target, &old_value, new_value,
     f32:	2200      	movs	r2, #0
     f34:	6803      	ldr	r3, [r0, #0]
     f36:	f3bf 8f5b 	dmb	ish
     f3a:	e853 1f00 	ldrex	r1, [r3]
     f3e:	2901      	cmp	r1, #1
     f40:	d103      	bne.n	f4a <mutex_unlock_platform+0x22>
     f42:	e843 2000 	strex	r0, r2, [r3]
     f46:	2800      	cmp	r0, #0
     f48:	d1f7      	bne.n	f3a <mutex_unlock_platform+0x12>
     f4a:	f3bf 8f5b 	dmb	ish
    {
    case NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC:
        return atomic_cas((atomic_t *)mutex->mutex, 1, 0) ?
                       NRF_CC3XX_PLATFORM_SUCCESS :
     f4e:	4807      	ldr	r0, [pc, #28]	; (f6c <mutex_unlock_platform+0x44>)
     f50:	bf08      	it	eq
     f52:	4610      	moveq	r0, r2
        p_mutex = (struct k_mutex *)mutex->mutex;

        k_mutex_unlock(p_mutex);
        return NRF_CC3XX_PLATFORM_SUCCESS;
    }
}
     f54:	bd08      	pop	{r3, pc}
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
     f56:	b13b      	cbz	r3, f68 <mutex_unlock_platform+0x40>
        p_mutex = (struct k_mutex *)mutex->mutex;
     f58:	6800      	ldr	r0, [r0, #0]
		/* coverity[OVERRUN] */
		return (int) arch_syscall_invoke1(*(uintptr_t *)&mutex, K_SYSCALL_K_MUTEX_UNLOCK);
	}
#endif
	compiler_barrier();
	return z_impl_k_mutex_unlock(mutex);
     f5a:	f002 f939 	bl	31d0 <z_impl_k_mutex_unlock>
        return NRF_CC3XX_PLATFORM_SUCCESS;
     f5e:	2000      	movs	r0, #0
     f60:	e7f8      	b.n	f54 <mutex_unlock_platform+0x2c>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
     f62:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
     f66:	e7f5      	b.n	f54 <mutex_unlock_platform+0x2c>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
     f68:	4801      	ldr	r0, [pc, #4]	; (f70 <mutex_unlock_platform+0x48>)
     f6a:	e7f3      	b.n	f54 <mutex_unlock_platform+0x2c>
     f6c:	ffff8fe9 	.word	0xffff8fe9
     f70:	ffff8fea 	.word	0xffff8fea

00000f74 <mutex_free_platform>:
static void mutex_free_platform(nrf_cc3xx_platform_mutex_t *mutex) {
     f74:	b510      	push	{r4, lr}
    if (mutex == NULL) {
     f76:	4604      	mov	r4, r0
     f78:	b918      	cbnz	r0, f82 <mutex_free_platform+0xe>
        platform_abort_apis.abort_fn(
     f7a:	4b0d      	ldr	r3, [pc, #52]	; (fb0 <mutex_free_platform+0x3c>)
     f7c:	480d      	ldr	r0, [pc, #52]	; (fb4 <mutex_free_platform+0x40>)
     f7e:	685b      	ldr	r3, [r3, #4]
     f80:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
     f82:	6861      	ldr	r1, [r4, #4]
     f84:	2908      	cmp	r1, #8
     f86:	d00d      	beq.n	fa4 <mutex_free_platform+0x30>
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
     f88:	f031 0304 	bics.w	r3, r1, #4
     f8c:	d00a      	beq.n	fa4 <mutex_free_platform+0x30>
    if ((mutex->flags & NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED) != 0) {
     f8e:	f011 0102 	ands.w	r1, r1, #2
     f92:	d008      	beq.n	fa6 <mutex_free_platform+0x32>
        k_mem_slab_free(&mutex_slab, &mutex->mutex);
     f94:	4808      	ldr	r0, [pc, #32]	; (fb8 <mutex_free_platform+0x44>)
     f96:	4621      	mov	r1, r4
     f98:	f003 fc0b 	bl	47b2 <k_mem_slab_free>
        mutex->mutex = NULL;
     f9c:	2300      	movs	r3, #0
     f9e:	6023      	str	r3, [r4, #0]
    mutex->flags = NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID;
     fa0:	2300      	movs	r3, #0
     fa2:	6063      	str	r3, [r4, #4]
}
     fa4:	bd10      	pop	{r4, pc}
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
     fa6:	6820      	ldr	r0, [r4, #0]
     fa8:	2214      	movs	r2, #20
     faa:	f003 f9e4 	bl	4376 <memset>
     fae:	e7f7      	b.n	fa0 <mutex_free_platform+0x2c>
     fb0:	20000048 	.word	0x20000048
     fb4:	00004e62 	.word	0x00004e62
     fb8:	2000024c 	.word	0x2000024c

00000fbc <mutex_init_platform>:
static void mutex_init_platform(nrf_cc3xx_platform_mutex_t *mutex) {
     fbc:	b510      	push	{r4, lr}
    if (mutex == NULL) {
     fbe:	4604      	mov	r4, r0
     fc0:	b918      	cbnz	r0, fca <mutex_init_platform+0xe>
        platform_abort_apis.abort_fn(
     fc2:	4b16      	ldr	r3, [pc, #88]	; (101c <CONFIG_FPROTECT_BLOCK_SIZE+0x1c>)
     fc4:	4816      	ldr	r0, [pc, #88]	; (1020 <CONFIG_FPROTECT_BLOCK_SIZE+0x20>)
     fc6:	685b      	ldr	r3, [r3, #4]
     fc8:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
     fca:	6863      	ldr	r3, [r4, #4]
     fcc:	2b04      	cmp	r3, #4
     fce:	d023      	beq.n	1018 <CONFIG_FPROTECT_BLOCK_SIZE+0x18>
     fd0:	2b08      	cmp	r3, #8
     fd2:	d021      	beq.n	1018 <CONFIG_FPROTECT_BLOCK_SIZE+0x18>
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID &&
     fd4:	b9cb      	cbnz	r3, 100a <CONFIG_FPROTECT_BLOCK_SIZE+0xa>
     fd6:	6823      	ldr	r3, [r4, #0]
     fd8:	b9bb      	cbnz	r3, 100a <CONFIG_FPROTECT_BLOCK_SIZE+0xa>
        ret = k_mem_slab_alloc(&mutex_slab, &mutex->mutex, K_FOREVER);
     fda:	4812      	ldr	r0, [pc, #72]	; (1024 <CONFIG_FPROTECT_BLOCK_SIZE+0x24>)
     fdc:	f04f 32ff 	mov.w	r2, #4294967295
     fe0:	f04f 33ff 	mov.w	r3, #4294967295
     fe4:	4621      	mov	r1, r4
     fe6:	f001 ff9f 	bl	2f28 <k_mem_slab_alloc>
        if(ret != 0 || mutex->mutex == NULL)
     fea:	b908      	cbnz	r0, ff0 <mutex_init_platform+0x34>
     fec:	6823      	ldr	r3, [r4, #0]
     fee:	b91b      	cbnz	r3, ff8 <mutex_init_platform+0x3c>
            platform_abort_apis.abort_fn(
     ff0:	4b0a      	ldr	r3, [pc, #40]	; (101c <CONFIG_FPROTECT_BLOCK_SIZE+0x1c>)
     ff2:	480d      	ldr	r0, [pc, #52]	; (1028 <CONFIG_FPROTECT_BLOCK_SIZE+0x28>)
     ff4:	685b      	ldr	r3, [r3, #4]
     ff6:	4798      	blx	r3
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
     ff8:	6820      	ldr	r0, [r4, #0]
     ffa:	2214      	movs	r2, #20
     ffc:	2100      	movs	r1, #0
     ffe:	f003 f9ba 	bl	4376 <memset>
        mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED;
    1002:	6863      	ldr	r3, [r4, #4]
    1004:	f043 0302 	orr.w	r3, r3, #2
    1008:	6063      	str	r3, [r4, #4]
    p_mutex = (struct k_mutex *)mutex->mutex;
    100a:	6820      	ldr	r0, [r4, #0]
	return z_impl_k_mutex_init(mutex);
    100c:	f003 fc07 	bl	481e <z_impl_k_mutex_init>
    mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_VALID;
    1010:	6863      	ldr	r3, [r4, #4]
    1012:	f043 0301 	orr.w	r3, r3, #1
    1016:	6063      	str	r3, [r4, #4]
}
    1018:	bd10      	pop	{r4, pc}
    101a:	bf00      	nop
    101c:	20000048 	.word	0x20000048
    1020:	00004e62 	.word	0x00004e62
    1024:	2000024c 	.word	0x2000024c
    1028:	00004e88 	.word	0x00004e88

0000102c <mutex_lock_platform>:
static int32_t mutex_lock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    102c:	b508      	push	{r3, lr}
    if(mutex == NULL) {
    102e:	b308      	cbz	r0, 1074 <mutex_lock_platform+0x48>
    switch (mutex->flags) {
    1030:	6843      	ldr	r3, [r0, #4]
    1032:	2b04      	cmp	r3, #4
    1034:	d110      	bne.n	1058 <mutex_lock_platform+0x2c>
    1036:	2201      	movs	r2, #1
    1038:	6803      	ldr	r3, [r0, #0]
    103a:	f3bf 8f5b 	dmb	ish
    103e:	e853 1f00 	ldrex	r1, [r3]
    1042:	2900      	cmp	r1, #0
    1044:	d103      	bne.n	104e <mutex_lock_platform+0x22>
    1046:	e843 2000 	strex	r0, r2, [r3]
    104a:	2800      	cmp	r0, #0
    104c:	d1f7      	bne.n	103e <mutex_lock_platform+0x12>
    104e:	f3bf 8f5b 	dmb	ish
                       NRF_CC3XX_PLATFORM_SUCCESS :
    1052:	d10b      	bne.n	106c <mutex_lock_platform+0x40>
    1054:	2000      	movs	r0, #0
}
    1056:	bd08      	pop	{r3, pc}
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1058:	b153      	cbz	r3, 1070 <mutex_lock_platform+0x44>
        p_mutex = (struct k_mutex *)mutex->mutex;
    105a:	6800      	ldr	r0, [r0, #0]
	return z_impl_k_mutex_lock(mutex, timeout);
    105c:	f04f 32ff 	mov.w	r2, #4294967295
    1060:	f04f 33ff 	mov.w	r3, #4294967295
    1064:	f002 f836 	bl	30d4 <z_impl_k_mutex_lock>
        if (ret == 0) {
    1068:	2800      	cmp	r0, #0
    106a:	d0f3      	beq.n	1054 <mutex_lock_platform+0x28>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    106c:	4803      	ldr	r0, [pc, #12]	; (107c <mutex_lock_platform+0x50>)
    106e:	e7f2      	b.n	1056 <mutex_lock_platform+0x2a>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    1070:	4803      	ldr	r0, [pc, #12]	; (1080 <mutex_lock_platform+0x54>)
    1072:	e7f0      	b.n	1056 <mutex_lock_platform+0x2a>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    1074:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    1078:	e7ed      	b.n	1056 <mutex_lock_platform+0x2a>
    107a:	bf00      	nop
    107c:	ffff8fe9 	.word	0xffff8fe9
    1080:	ffff8fea 	.word	0xffff8fea

00001084 <nrf_cc3xx_platform_mutex_init>:
};

/** @brief Function to initialize the nrf_cc3xx_platform mutex APIs
 */
void nrf_cc3xx_platform_mutex_init(void)
{
    1084:	b508      	push	{r3, lr}
    k_mem_slab_init(&mutex_slab,
    1086:	4906      	ldr	r1, [pc, #24]	; (10a0 <nrf_cc3xx_platform_mutex_init+0x1c>)
    1088:	4806      	ldr	r0, [pc, #24]	; (10a4 <nrf_cc3xx_platform_mutex_init+0x20>)
    108a:	2340      	movs	r3, #64	; 0x40
    108c:	2214      	movs	r2, #20
    108e:	f003 fb75 	bl	477c <k_mem_slab_init>
                mutex_slab_buffer,
                sizeof(struct k_mutex),
                NUM_MUTEXES);

    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
}
    1092:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
    1096:	4904      	ldr	r1, [pc, #16]	; (10a8 <nrf_cc3xx_platform_mutex_init+0x24>)
    1098:	4804      	ldr	r0, [pc, #16]	; (10ac <nrf_cc3xx_platform_mutex_init+0x28>)
    109a:	f002 bead 	b.w	3df8 <nrf_cc3xx_platform_set_mutexes>
    109e:	bf00      	nop
    10a0:	20000268 	.word	0x20000268
    10a4:	2000024c 	.word	0x2000024c
    10a8:	00004cb0 	.word	0x00004cb0
    10ac:	00004ca0 	.word	0x00004ca0

000010b0 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    10b0:	4901      	ldr	r1, [pc, #4]	; (10b8 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    10b2:	2210      	movs	r2, #16
	str	r2, [r1]
    10b4:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    10b6:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    10b8:	e000ed10 	.word	0xe000ed10

000010bc <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    10bc:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    10be:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    10c0:	f380 8811 	msr	BASEPRI, r0
	isb
    10c4:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    10c8:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    10cc:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    10ce:	b662      	cpsie	i
	isb
    10d0:	f3bf 8f6f 	isb	sy

	bx	lr
    10d4:	4770      	bx	lr
    10d6:	bf00      	nop

000010d8 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    10d8:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    10da:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    10dc:	f381 8811 	msr	BASEPRI, r1

	wfe
    10e0:	bf20      	wfe

	msr	BASEPRI, r0
    10e2:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    10e6:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    10e8:	4770      	bx	lr
    10ea:	bf00      	nop

000010ec <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    10ec:	b243      	sxtb	r3, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    10ee:	2b00      	cmp	r3, #0
    10f0:	db08      	blt.n	1104 <arch_irq_enable+0x18>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    10f2:	2201      	movs	r2, #1
    10f4:	f000 001f 	and.w	r0, r0, #31
    10f8:	fa02 f000 	lsl.w	r0, r2, r0
    10fc:	095b      	lsrs	r3, r3, #5
    10fe:	4a02      	ldr	r2, [pc, #8]	; (1108 <arch_irq_enable+0x1c>)
    1100:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    1104:	4770      	bx	lr
    1106:	bf00      	nop
    1108:	e000e100 	.word	0xe000e100

0000110c <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    110c:	4b05      	ldr	r3, [pc, #20]	; (1124 <arch_irq_is_enabled+0x18>)
    110e:	0942      	lsrs	r2, r0, #5
    1110:	f000 001f 	and.w	r0, r0, #31
    1114:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    1118:	2301      	movs	r3, #1
    111a:	fa03 f000 	lsl.w	r0, r3, r0
}
    111e:	4010      	ands	r0, r2
    1120:	4770      	bx	lr
    1122:	bf00      	nop
    1124:	e000e100 	.word	0xe000e100

00001128 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    1128:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    112a:	2b00      	cmp	r3, #0
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    112c:	bfa8      	it	ge
    112e:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
		prio += _IRQ_PRIO_OFFSET;
    1132:	f101 0101 	add.w	r1, r1, #1
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1136:	bfb8      	it	lt
    1138:	4b06      	ldrlt	r3, [pc, #24]	; (1154 <z_arm_irq_priority_set+0x2c>)
    113a:	ea4f 1141 	mov.w	r1, r1, lsl #5
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    113e:	bfac      	ite	ge
    1140:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1144:	f000 000f 	andlt.w	r0, r0, #15
    1148:	b2c9      	uxtb	r1, r1
    114a:	bfb4      	ite	lt
    114c:	5419      	strblt	r1, [r3, r0]
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    114e:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
}
    1152:	4770      	bx	lr
    1154:	e000ed14 	.word	0xe000ed14

00001158 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    1158:	bf30      	wfi
    b z_SysNmiOnReset
    115a:	f7ff bffd 	b.w	1158 <z_SysNmiOnReset>
    115e:	bf00      	nop

00001160 <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1160:	4a0b      	ldr	r2, [pc, #44]	; (1190 <z_arm_prep_c+0x30>)
 * This routine prepares for the execution of and runs C code.
 *
 * @return N/A
 */
void z_arm_prep_c(void)
{
    1162:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1164:	4b0b      	ldr	r3, [pc, #44]	; (1194 <z_arm_prep_c+0x34>)
    1166:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    116a:	609a      	str	r2, [r3, #8]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    116c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1170:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    1174:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    1178:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    117c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    1180:	f001 fe34 	bl	2dec <z_bss_zero>
	z_data_copy();
    1184:	f002 fc10 	bl	39a8 <z_data_copy>
#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    1188:	f000 f9d0 	bl	152c <z_arm_interrupt_init>
	z_cstart();
    118c:	f001 fe38 	bl	2e00 <z_cstart>
    1190:	00000000 	.word	0x00000000
    1194:	e000ed00 	.word	0xe000ed00

00001198 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    1198:	4a09      	ldr	r2, [pc, #36]	; (11c0 <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    119a:	490a      	ldr	r1, [pc, #40]	; (11c4 <arch_swap+0x2c>)
	_current->arch.basepri = key;
    119c:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    119e:	6809      	ldr	r1, [r1, #0]
    11a0:	6799      	str	r1, [r3, #120]	; 0x78

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    11a2:	4909      	ldr	r1, [pc, #36]	; (11c8 <arch_swap+0x30>)
	_current->arch.basepri = key;
    11a4:	6758      	str	r0, [r3, #116]	; 0x74
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    11a6:	684b      	ldr	r3, [r1, #4]
    11a8:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    11ac:	604b      	str	r3, [r1, #4]
	__asm__ volatile(
    11ae:	2300      	movs	r3, #0
    11b0:	f383 8811 	msr	BASEPRI, r3
    11b4:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    11b8:	6893      	ldr	r3, [r2, #8]
}
    11ba:	6f98      	ldr	r0, [r3, #120]	; 0x78
    11bc:	4770      	bx	lr
    11be:	bf00      	nop
    11c0:	20000934 	.word	0x20000934
    11c4:	00004da0 	.word	0x00004da0
    11c8:	e000ed00 	.word	0xe000ed00

000011cc <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    11cc:	4912      	ldr	r1, [pc, #72]	; (1218 <z_arm_pendsv+0x4c>)
    ldr r2, [r1, #_kernel_offset_to_current]
    11ce:	688a      	ldr	r2, [r1, #8]
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    11d0:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    11d4:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    11d6:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    11da:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    11de:	2020      	movs	r0, #32
    msr BASEPRI_MAX, r0
    11e0:	f380 8812 	msr	BASEPRI_MAX, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    11e4:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    11e8:	4f0c      	ldr	r7, [pc, #48]	; (121c <z_arm_pendsv+0x50>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    11ea:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    11ee:	69ca      	ldr	r2, [r1, #28]

    str r2, [r1, #_kernel_offset_to_current]
    11f0:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    11f2:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    11f4:	6f50      	ldr	r0, [r2, #116]	; 0x74
    movs r3, #0
    11f6:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    11f8:	6753      	str	r3, [r2, #116]	; 0x74
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    11fa:	f380 8811 	msr	BASEPRI, r0
    isb
#endif

#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
    /* Re-program dynamic memory map */
    push {r2,lr}
    11fe:	b504      	push	{r2, lr}
    mov r0, r2 /* _current thread */
    1200:	4610      	mov	r0, r2
    bl z_arm_configure_dynamic_mpu_regions
    1202:	f000 fa29 	bl	1658 <z_arm_configure_dynamic_mpu_regions>
    pop {r2,lr}
    1206:	e8bd 4004 	ldmia.w	sp!, {r2, lr}
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    120a:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    120e:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    1212:	f38c 8809 	msr	PSP, ip

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    1216:	4770      	bx	lr
    ldr r1, =_kernel
    1218:	20000934 	.word	0x20000934
    ldr v4, =_SCS_ICSR
    121c:	e000ed04 	.word	0xe000ed04

00001220 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    1220:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    1224:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    1226:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    122a:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    122e:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    1230:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    1234:	2902      	cmp	r1, #2
    beq _oops
    1236:	d0ff      	beq.n	1238 <_oops>

00001238 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    1238:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    123a:	f003 f85c 	bl	42f6 <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    123e:	bd01      	pop	{r0, pc}

00001240 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    1240:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    1244:	9b00      	ldr	r3, [sp, #0]
    1246:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->pc &= 0xfffffffe;
    124a:	490a      	ldr	r1, [pc, #40]	; (1274 <arch_new_thread+0x34>)
	iframe->a3 = (uint32_t)p2;
    124c:	9b01      	ldr	r3, [sp, #4]
    124e:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    1252:	9b02      	ldr	r3, [sp, #8]
    1254:	f842 3c14 	str.w	r3, [r2, #-20]
	iframe->pc &= 0xfffffffe;
    1258:	f021 0101 	bic.w	r1, r1, #1

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    125c:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    1260:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->pc &= 0xfffffffe;
    1264:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    1268:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    126a:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    126c:	6502      	str	r2, [r0, #80]	; 0x50
	thread->arch.basepri = 0;
    126e:	6743      	str	r3, [r0, #116]	; 0x74
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    1270:	4770      	bx	lr
    1272:	bf00      	nop
    1274:	00004209 	.word	0x00004209

00001278 <z_check_thread_stack_fail>:
 *         thread stack corruption, otherwise return 0.
 */
uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp)
{
#if defined(CONFIG_MULTITHREADING)
	const struct k_thread *thread = _current;
    1278:	4a0b      	ldr	r2, [pc, #44]	; (12a8 <z_check_thread_stack_fail+0x30>)
{
    127a:	4603      	mov	r3, r0
	const struct k_thread *thread = _current;
    127c:	6890      	ldr	r0, [r2, #8]

	if (thread == NULL) {
    127e:	b190      	cbz	r0, 12a6 <z_check_thread_stack_fail+0x2e>
			return thread->stack_info.start;
		}
	}
#else /* CONFIG_USERSPACE */
#if defined(CONFIG_MULTITHREADING)
	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
    1280:	f113 0f16 	cmn.w	r3, #22
    1284:	6e40      	ldr	r0, [r0, #100]	; 0x64
    1286:	d005      	beq.n	1294 <z_check_thread_stack_fail+0x1c>
    1288:	f1a0 0220 	sub.w	r2, r0, #32
    128c:	429a      	cmp	r2, r3
    128e:	d806      	bhi.n	129e <z_check_thread_stack_fail+0x26>
    1290:	4283      	cmp	r3, r0
    1292:	d204      	bcs.n	129e <z_check_thread_stack_fail+0x26>
    1294:	4281      	cmp	r1, r0
    1296:	bf2c      	ite	cs
    1298:	2100      	movcs	r1, #0
    129a:	2101      	movcc	r1, #1
    129c:	e000      	b.n	12a0 <z_check_thread_stack_fail+0x28>
    129e:	2100      	movs	r1, #0
    12a0:	2900      	cmp	r1, #0
		return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack);
	}
#endif
#endif /* CONFIG_USERSPACE */

	return 0;
    12a2:	bf08      	it	eq
    12a4:	2000      	moveq	r0, #0
}
    12a6:	4770      	bx	lr
    12a8:	20000934 	.word	0x20000934

000012ac <arch_switch_to_main_thread>:
#endif /* CONFIG_FPU */
}

void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
    12ac:	b508      	push	{r3, lr}
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    12ae:	4b09      	ldr	r3, [pc, #36]	; (12d4 <arch_switch_to_main_thread+0x28>)
    12b0:	6098      	str	r0, [r3, #8]
{
    12b2:	460d      	mov	r5, r1
    12b4:	4614      	mov	r4, r2
#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
	/*
	 * If stack protection is enabled, make sure to set it
	 * before jumping to thread entry function
	 */
	z_arm_configure_dynamic_mpu_regions(main_thread);
    12b6:	f000 f9cf 	bl	1658 <z_arm_configure_dynamic_mpu_regions>

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    12ba:	4620      	mov	r0, r4
    12bc:	f385 8809 	msr	PSP, r5
    12c0:	2100      	movs	r1, #0
    12c2:	b663      	cpsie	if
    12c4:	f381 8811 	msr	BASEPRI, r1
    12c8:	f3bf 8f6f 	isb	sy
    12cc:	2200      	movs	r2, #0
    12ce:	2300      	movs	r3, #0
    12d0:	f002 ff9a 	bl	4208 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    12d4:	20000934 	.word	0x20000934

000012d8 <_isr_wrapper>:
 * @return N/A
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    12d8:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    12da:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    12dc:	4a0b      	ldr	r2, [pc, #44]	; (130c <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    12de:	6990      	ldr	r0, [r2, #24]
	cmp r0, #0
    12e0:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    12e2:	bf1e      	ittt	ne
	movne	r1, #0
    12e4:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    12e6:	6191      	strne	r1, [r2, #24]
		blne	z_pm_save_idle_exit
    12e8:	f003 fa92 	blne	4810 <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    12ec:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    12ee:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    12f2:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    12f6:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    12fa:	4905      	ldr	r1, [pc, #20]	; (1310 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    12fc:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    12fe:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    1300:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    1302:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    1306:	4903      	ldr	r1, [pc, #12]	; (1314 <_isr_wrapper+0x3c>)
	bx r1
    1308:	4708      	bx	r1
    130a:	0000      	.short	0x0000
	ldr r2, =_kernel
    130c:	20000934 	.word	0x20000934
	ldr r1, =_sw_isr_table
    1310:	00004ae8 	.word	0x00004ae8
	ldr r1, =z_arm_int_exit
    1314:	00001319 	.word	0x00001319

00001318 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    1318:	4b04      	ldr	r3, [pc, #16]	; (132c <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    131a:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    131c:	69d8      	ldr	r0, [r3, #28]
	cmp r0, r1
    131e:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    1320:	d003      	beq.n	132a <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    1322:	4903      	ldr	r1, [pc, #12]	; (1330 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    1324:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    1328:	600a      	str	r2, [r1, #0]

0000132a <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    132a:	4770      	bx	lr
	ldr r3, =_kernel
    132c:	20000934 	.word	0x20000934
	ldr r1, =_SCS_ICSR
    1330:	e000ed04 	.word	0xe000ed04

00001334 <mem_manage_fault>:
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
			      bool *recoverable)
{
    1334:	b538      	push	{r3, r4, r5, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    1336:	4b19      	ldr	r3, [pc, #100]	; (139c <mem_manage_fault+0x68>)
{
    1338:	4614      	mov	r4, r2
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    133a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error (context area might be"
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    133c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    133e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
{
    1340:	4605      	mov	r5, r0
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    1342:	0790      	lsls	r0, r2, #30
    1344:	d519      	bpl.n	137a <mem_manage_fault+0x46>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		uint32_t temp = SCB->MMFAR;
    1346:	6b58      	ldr	r0, [r3, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    1348:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    134a:	0612      	lsls	r2, r2, #24
    134c:	d515      	bpl.n	137a <mem_manage_fault+0x46>
			mmfar = temp;
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
			if (from_hard_fault != 0) {
    134e:	b119      	cbz	r1, 1358 <mem_manage_fault+0x24>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    1350:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1352:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    1356:	629a      	str	r2, [r3, #40]	; 0x28
			}
		}
	}
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    1358:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Instruction Access Violation");
	}
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    135a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	 * crossed into an area beyond the thread stack.]
	 *
	 * Data Access Violation errors may or may not be caused by
	 * thread stack overflows.
	 */
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    135c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    135e:	06d1      	lsls	r1, r2, #27
    1360:	d40e      	bmi.n	1380 <mem_manage_fault+0x4c>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    1362:	6a9b      	ldr	r3, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1364:	079a      	lsls	r2, r3, #30
    1366:	d40b      	bmi.n	1380 <mem_manage_fault+0x4c>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    1368:	2000      	movs	r0, #0
		"without stack guard, user-mode or null-pointer detection\n");
#endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */
	}

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    136a:	4a0c      	ldr	r2, [pc, #48]	; (139c <mem_manage_fault+0x68>)
    136c:	6a93      	ldr	r3, [r2, #40]	; 0x28
    136e:	f043 03ff 	orr.w	r3, r3, #255	; 0xff
    1372:	6293      	str	r3, [r2, #40]	; 0x28

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf, true);
    1374:	2300      	movs	r3, #0
    1376:	7023      	strb	r3, [r4, #0]

	return reason;
}
    1378:	bd38      	pop	{r3, r4, r5, pc}
	uint32_t mmfar = -EINVAL;
    137a:	f06f 0015 	mvn.w	r0, #21
    137e:	e7eb      	b.n	1358 <mem_manage_fault+0x24>
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
    1380:	4b06      	ldr	r3, [pc, #24]	; (139c <mem_manage_fault+0x68>)
    1382:	685b      	ldr	r3, [r3, #4]
    1384:	051b      	lsls	r3, r3, #20
    1386:	d5ef      	bpl.n	1368 <mem_manage_fault+0x34>
			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
    1388:	4629      	mov	r1, r5
    138a:	f7ff ff75 	bl	1278 <z_check_thread_stack_fail>
			if (min_stack_ptr) {
    138e:	2800      	cmp	r0, #0
    1390:	d0ea      	beq.n	1368 <mem_manage_fault+0x34>
  \details Assigns the given value to the Process Stack Pointer (PSP).
  \param [in]    topOfProcStack  Process Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
{
  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
    1392:	f380 8809 	msr	PSP, r0
				reason = K_ERR_STACK_CHK_FAIL;
    1396:	2002      	movs	r0, #2
    1398:	e7e7      	b.n	136a <mem_manage_fault+0x36>
    139a:	bf00      	nop
    139c:	e000ed00 	.word	0xe000ed00

000013a0 <bus_fault.isra.0>:
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    13a0:	4b0d      	ldr	r3, [pc, #52]	; (13d8 <bus_fault.isra.0+0x38>)
    13a2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error");
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    13a4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    13a6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    13a8:	0592      	lsls	r2, r2, #22
    13aa:	d508      	bpl.n	13be <bus_fault.isra.0+0x1e>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
    13ac:	6b9a      	ldr	r2, [r3, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    13ae:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    13b0:	0412      	lsls	r2, r2, #16
    13b2:	d504      	bpl.n	13be <bus_fault.isra.0+0x1e>
			PR_EXC("  BFAR Address: 0x%x", bfar);
			if (from_hard_fault != 0) {
    13b4:	b118      	cbz	r0, 13be <bus_fault.isra.0+0x1e>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    13b6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    13b8:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    13bc:	629a      	str	r2, [r3, #40]	; 0x28
			}
		}
	}
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    13be:	4b06      	ldr	r3, [pc, #24]	; (13d8 <bus_fault.isra.0+0x38>)
    13c0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Imprecise data bus error");
	}
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    13c2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    13c4:	05d2      	lsls	r2, r2, #23
		PR_FAULT_INFO("  Instruction bus error");
#if !defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	}
#else
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    13c6:	bf58      	it	pl
    13c8:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
		SYSMPU->CESR &= ~sperr;
	}
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    13ca:	6a9a      	ldr	r2, [r3, #40]	; 0x28

	*recoverable = memory_fault_recoverable(esf, true);
    13cc:	2000      	movs	r0, #0
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    13ce:	f442 427f 	orr.w	r2, r2, #65280	; 0xff00
    13d2:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    13d4:	7008      	strb	r0, [r1, #0]

	return reason;
}
    13d6:	4770      	bx	lr
    13d8:	e000ed00 	.word	0xe000ed00

000013dc <usage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    13dc:	4b07      	ldr	r3, [pc, #28]	; (13fc <usage_fault.isra.0+0x20>)
    13de:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    13e0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    13e2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    13e4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    13e6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    13e8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    13ea:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    13ec:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    13f0:	ea6f 4212 	mvn.w	r2, r2, lsr #16
    13f4:	629a      	str	r2, [r3, #40]	; 0x28

	return reason;
}
    13f6:	2000      	movs	r0, #0
    13f8:	4770      	bx	lr
    13fa:	bf00      	nop
    13fc:	e000ed00 	.word	0xe000ed00

00001400 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    1400:	b570      	push	{r4, r5, r6, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    1402:	4b3e      	ldr	r3, [pc, #248]	; (14fc <z_arm_fault+0xfc>)
    1404:	685b      	ldr	r3, [r3, #4]
{
    1406:	b08a      	sub	sp, #40	; 0x28
    1408:	460d      	mov	r5, r1
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    140a:	f3c3 0308 	ubfx	r3, r3, #0, #9
    140e:	2600      	movs	r6, #0
    1410:	f386 8811 	msr	BASEPRI, r6
    1414:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    1418:	f002 417f 	and.w	r1, r2, #4278190080	; 0xff000000
    141c:	f1b1 4f7f 	cmp.w	r1, #4278190080	; 0xff000000
    1420:	d111      	bne.n	1446 <z_arm_fault+0x46>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    1422:	f002 010c 	and.w	r1, r2, #12
    1426:	2908      	cmp	r1, #8
    1428:	d00d      	beq.n	1446 <z_arm_fault+0x46>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    142a:	0712      	lsls	r2, r2, #28
    142c:	d401      	bmi.n	1432 <z_arm_fault+0x32>
			ptr_esf = (z_arch_esf_t *)msp;
    142e:	4605      	mov	r5, r0
			*nested_exc = true;
    1430:	2601      	movs	r6, #1
	*recoverable = false;
    1432:	2200      	movs	r2, #0
    1434:	3b03      	subs	r3, #3
    1436:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
    143a:	2b03      	cmp	r3, #3
    143c:	d857      	bhi.n	14ee <z_arm_fault+0xee>
    143e:	e8df f003 	tbb	[pc, r3]
    1442:	4e04      	.short	0x4e04
    1444:	4b52      	.short	0x4b52
		return NULL;
    1446:	4635      	mov	r5, r6
    1448:	e7f3      	b.n	1432 <z_arm_fault+0x32>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    144a:	4b2c      	ldr	r3, [pc, #176]	; (14fc <z_arm_fault+0xfc>)
    144c:	6adc      	ldr	r4, [r3, #44]	; 0x2c
    144e:	f014 0402 	ands.w	r4, r4, #2
    1452:	d14c      	bne.n	14ee <z_arm_fault+0xee>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    1454:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    1456:	2a00      	cmp	r2, #0
    1458:	db18      	blt.n	148c <z_arm_fault+0x8c>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    145a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    145c:	005b      	lsls	r3, r3, #1
    145e:	d515      	bpl.n	148c <z_arm_fault+0x8c>
	uint16_t fault_insn = *(ret_addr - 1);
    1460:	69ab      	ldr	r3, [r5, #24]
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    1462:	f833 2c02 	ldrh.w	r2, [r3, #-2]
    1466:	f64d 7302 	movw	r3, #57090	; 0xdf02
    146a:	429a      	cmp	r2, r3
    146c:	d00d      	beq.n	148a <z_arm_fault+0x8a>
		} else if (SCB_MMFSR != 0) {
    146e:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    1472:	f603 6326 	addw	r3, r3, #3622	; 0xe26
    1476:	781b      	ldrb	r3, [r3, #0]
    1478:	b303      	cbz	r3, 14bc <z_arm_fault+0xbc>
			reason = mem_manage_fault(esf, 1, recoverable);
    147a:	f10d 0207 	add.w	r2, sp, #7
    147e:	2101      	movs	r1, #1
		reason = mem_manage_fault(esf, 0, recoverable);
    1480:	4628      	mov	r0, r5
    1482:	f7ff ff57 	bl	1334 <mem_manage_fault>
    1486:	4604      	mov	r4, r0
		break;
    1488:	e000      	b.n	148c <z_arm_fault+0x8c>
			reason = esf->basic.r0;
    148a:	682c      	ldr	r4, [r5, #0]
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    148c:	f89d 3007 	ldrb.w	r3, [sp, #7]
    1490:	b993      	cbnz	r3, 14b8 <z_arm_fault+0xb8>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    1492:	2220      	movs	r2, #32
    1494:	4629      	mov	r1, r5
    1496:	a802      	add	r0, sp, #8
    1498:	f002 ff62 	bl	4360 <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    149c:	9b09      	ldr	r3, [sp, #36]	; 0x24
    149e:	b346      	cbz	r6, 14f2 <z_arm_fault+0xf2>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    14a0:	f3c3 0208 	ubfx	r2, r3, #0, #9
    14a4:	b922      	cbnz	r2, 14b0 <z_arm_fault+0xb0>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    14a6:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    14aa:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    14ae:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    14b0:	a902      	add	r1, sp, #8
    14b2:	4620      	mov	r0, r4
    14b4:	f002 ff1d 	bl	42f2 <z_arm_fatal_error>
}
    14b8:	b00a      	add	sp, #40	; 0x28
    14ba:	bd70      	pop	{r4, r5, r6, pc}
		} else if (SCB_BFSR != 0) {
    14bc:	4b10      	ldr	r3, [pc, #64]	; (1500 <z_arm_fault+0x100>)
    14be:	781b      	ldrb	r3, [r3, #0]
    14c0:	b12b      	cbz	r3, 14ce <z_arm_fault+0xce>
			reason = bus_fault(esf, 1, recoverable);
    14c2:	f10d 0107 	add.w	r1, sp, #7
    14c6:	2001      	movs	r0, #1
		reason = bus_fault(esf, 0, recoverable);
    14c8:	f7ff ff6a 	bl	13a0 <bus_fault.isra.0>
    14cc:	e7db      	b.n	1486 <z_arm_fault+0x86>
		} else if (SCB_UFSR != 0) {
    14ce:	4b0d      	ldr	r3, [pc, #52]	; (1504 <z_arm_fault+0x104>)
    14d0:	881b      	ldrh	r3, [r3, #0]
    14d2:	b29b      	uxth	r3, r3
    14d4:	2b00      	cmp	r3, #0
    14d6:	d0d9      	beq.n	148c <z_arm_fault+0x8c>
		reason = usage_fault(esf);
    14d8:	f7ff ff80 	bl	13dc <usage_fault.isra.0>
    14dc:	e7d3      	b.n	1486 <z_arm_fault+0x86>
		reason = mem_manage_fault(esf, 0, recoverable);
    14de:	f10d 0207 	add.w	r2, sp, #7
    14e2:	2100      	movs	r1, #0
    14e4:	e7cc      	b.n	1480 <z_arm_fault+0x80>
		reason = bus_fault(esf, 0, recoverable);
    14e6:	f10d 0107 	add.w	r1, sp, #7
    14ea:	2000      	movs	r0, #0
    14ec:	e7ec      	b.n	14c8 <z_arm_fault+0xc8>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    14ee:	2400      	movs	r4, #0
    14f0:	e7cc      	b.n	148c <z_arm_fault+0x8c>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    14f2:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    14f6:	f023 0301 	bic.w	r3, r3, #1
    14fa:	e7d8      	b.n	14ae <z_arm_fault+0xae>
    14fc:	e000ed00 	.word	0xe000ed00
    1500:	e000ed29 	.word	0xe000ed29
    1504:	e000ed2a 	.word	0xe000ed2a

00001508 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    1508:	4a02      	ldr	r2, [pc, #8]	; (1514 <z_arm_fault_init+0xc>)
    150a:	6953      	ldr	r3, [r2, #20]
    150c:	f043 0310 	orr.w	r3, r3, #16
    1510:	6153      	str	r3, [r2, #20]
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
}
    1512:	4770      	bx	lr
    1514:	e000ed00 	.word	0xe000ed00

00001518 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    1518:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    151c:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    1520:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    1522:	4672      	mov	r2, lr
	bl z_arm_fault
    1524:	f7ff ff6c 	bl	1400 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    1528:	bd01      	pop	{r0, pc}
    152a:	bf00      	nop

0000152c <z_arm_interrupt_init>:
    152c:	4804      	ldr	r0, [pc, #16]	; (1540 <z_arm_interrupt_init+0x14>)
 * @return N/A
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    152e:	2300      	movs	r3, #0
    1530:	2120      	movs	r1, #32
    1532:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    1534:	3301      	adds	r3, #1
    1536:	2b30      	cmp	r3, #48	; 0x30
    1538:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    153c:	d1f9      	bne.n	1532 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    153e:	4770      	bx	lr
    1540:	e000e100 	.word	0xe000e100

00001544 <__start>:
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    1544:	2000      	movs	r0, #0
    msr CONTROL, r0
    1546:	f380 8814 	msr	CONTROL, r0
    isb
    154a:	f3bf 8f6f 	isb	sy
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    154e:	f003 fa61 	bl	4a14 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    1552:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    1554:	490d      	ldr	r1, [pc, #52]	; (158c <__start+0x48>)
    str r0, [r1]
    1556:	6008      	str	r0, [r1, #0]
    dsb
    1558:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    155c:	480c      	ldr	r0, [pc, #48]	; (1590 <__start+0x4c>)
    msr msp, r0
    155e:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    1562:	f000 f829 	bl	15b8 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    1566:	2020      	movs	r0, #32
    msr BASEPRI, r0
    1568:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    156c:	4809      	ldr	r0, [pc, #36]	; (1594 <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    156e:	f44f 6102 	mov.w	r1, #2080	; 0x820
    adds r0, r0, r1
    1572:	1840      	adds	r0, r0, r1
    msr PSP, r0
    1574:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    1578:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    157c:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    157e:	4308      	orrs	r0, r1
    msr CONTROL, r0
    1580:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    1584:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    1588:	f7ff fdea 	bl	1160 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    158c:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    1590:	20001360 	.word	0x20001360
    ldr r0, =z_interrupt_stacks
    1594:	200014e0 	.word	0x200014e0

00001598 <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    1598:	4a06      	ldr	r2, [pc, #24]	; (15b4 <z_arm_clear_arm_mpu_config+0x1c>)
    159a:	6811      	ldr	r1, [r2, #0]

	for (i = 0; i < num_regions; i++) {
    159c:	2300      	movs	r3, #0
	int num_regions =
    159e:	f3c1 2107 	ubfx	r1, r1, #8, #8
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
  MPU->RASR = 0U;
    15a2:	4618      	mov	r0, r3
	for (i = 0; i < num_regions; i++) {
    15a4:	428b      	cmp	r3, r1
    15a6:	d100      	bne.n	15aa <z_arm_clear_arm_mpu_config+0x12>
		ARM_MPU_ClrRegion(i);
	}
}
    15a8:	4770      	bx	lr
  MPU->RNR = rnr;
    15aa:	6093      	str	r3, [r2, #8]
  MPU->RASR = 0U;
    15ac:	6110      	str	r0, [r2, #16]
	for (i = 0; i < num_regions; i++) {
    15ae:	3301      	adds	r3, #1
    15b0:	e7f8      	b.n	15a4 <z_arm_clear_arm_mpu_config+0xc>
    15b2:	bf00      	nop
    15b4:	e000ed90 	.word	0xe000ed90

000015b8 <z_arm_init_arch_hw_at_boot>:
 * components and core registers.
 *
 * @return N/A
 */
void z_arm_init_arch_hw_at_boot(void)
{
    15b8:	b508      	push	{r3, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    15ba:	b672      	cpsid	i
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    15bc:	2300      	movs	r3, #0
    15be:	f383 8813 	msr	FAULTMASK, r3

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    15c2:	f7ff ffe9 	bl	1598 <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    15c6:	4b14      	ldr	r3, [pc, #80]	; (1618 <z_arm_init_arch_hw_at_boot+0x60>)
    15c8:	f04f 32ff 	mov.w	r2, #4294967295
    15cc:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
    15d0:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
    15d4:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    15d8:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
    15dc:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
    15e0:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
    15e4:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    15e8:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    15ec:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    15f0:	f8c3 2184 	str.w	r2, [r3, #388]	; 0x184
    15f4:	f8c3 2188 	str.w	r2, [r3, #392]	; 0x188
    15f8:	f8c3 218c 	str.w	r2, [r3, #396]	; 0x18c
    15fc:	f8c3 2190 	str.w	r2, [r3, #400]	; 0x190
    1600:	f8c3 2194 	str.w	r2, [r3, #404]	; 0x194
    1604:	f8c3 2198 	str.w	r2, [r3, #408]	; 0x198
    1608:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c
  __ASM volatile ("cpsie i" : : : "memory");
    160c:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    160e:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1612:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    1616:	bd08      	pop	{r3, pc}
    1618:	e000e100 	.word	0xe000e100

0000161c <z_impl_k_thread_abort>:
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
	if (_current == thread) {
    161c:	4b06      	ldr	r3, [pc, #24]	; (1638 <z_impl_k_thread_abort+0x1c>)
    161e:	689b      	ldr	r3, [r3, #8]
    1620:	4283      	cmp	r3, r0
    1622:	d107      	bne.n	1634 <z_impl_k_thread_abort+0x18>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    1624:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    1628:	b123      	cbz	r3, 1634 <z_impl_k_thread_abort+0x18>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    162a:	4a04      	ldr	r2, [pc, #16]	; (163c <z_impl_k_thread_abort+0x20>)
    162c:	6853      	ldr	r3, [r2, #4]
    162e:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    1632:	6053      	str	r3, [r2, #4]
		}
	}

	z_thread_abort(thread);
    1634:	f002 b966 	b.w	3904 <z_thread_abort>
    1638:	20000934 	.word	0x20000934
    163c:	e000ed00 	.word	0xe000ed00

00001640 <z_arm_configure_static_mpu_regions>:
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    1640:	4b02      	ldr	r3, [pc, #8]	; (164c <z_arm_configure_static_mpu_regions+0xc>)
    1642:	4a03      	ldr	r2, [pc, #12]	; (1650 <z_arm_configure_static_mpu_regions+0x10>)
    1644:	4803      	ldr	r0, [pc, #12]	; (1654 <z_arm_configure_static_mpu_regions+0x14>)
    1646:	2101      	movs	r1, #1
    1648:	f000 b868 	b.w	171c <arm_core_mpu_configure_static_mpu_regions>
    164c:	20040000 	.word	0x20040000
    1650:	20000000 	.word	0x20000000
    1654:	00004cc4 	.word	0x00004cc4

00001658 <z_arm_configure_dynamic_mpu_regions>:
#endif /* CONFIG_USERSPACE */
	{
		/* A supervisor thread only has the normal thread stack to
		 * protect with a stack guard.
		 */
		guard_start = thread->stack_info.start - guard_size;
    1658:	6e42      	ldr	r2, [r0, #100]	; 0x64
	}

	__ASSERT(region_num < _MAX_DYNAMIC_MPU_REGIONS_NUM,
		"Out-of-bounds error for dynamic region map.");

	dynamic_regions[region_num].start = guard_start;
    165a:	4b05      	ldr	r3, [pc, #20]	; (1670 <z_arm_configure_dynamic_mpu_regions+0x18>)
		guard_start = thread->stack_info.start - guard_size;
    165c:	3a20      	subs	r2, #32
	dynamic_regions[region_num].start = guard_start;
    165e:	601a      	str	r2, [r3, #0]
	dynamic_regions[region_num].size = guard_size;
	dynamic_regions[region_num].attr = K_MEM_PARTITION_P_RO_U_NA;
    1660:	4a04      	ldr	r2, [pc, #16]	; (1674 <z_arm_configure_dynamic_mpu_regions+0x1c>)
    1662:	2120      	movs	r1, #32
    1664:	e9c3 1201 	strd	r1, r2, [r3, #4]

	region_num++;
#endif /* CONFIG_MPU_STACK_GUARD */

	/* Configure the dynamic MPU regions */
	arm_core_mpu_configure_dynamic_mpu_regions(dynamic_regions,
    1668:	4618      	mov	r0, r3
    166a:	2101      	movs	r1, #1
    166c:	f000 b860 	b.w	1730 <arm_core_mpu_configure_dynamic_mpu_regions>
    1670:	20000768 	.word	0x20000768
    1674:	150b0000 	.word	0x150b0000

00001678 <mpu_configure_regions>:
 * sanity check of the memory regions to be programmed.
 */
static int mpu_configure_regions(const struct z_arm_mpu_partition
	regions[], uint8_t regions_num, uint8_t start_reg_index,
	bool do_sanity_check)
{
    1678:	b5f0      	push	{r4, r5, r6, r7, lr}
#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */
}

static inline void set_region_number(uint32_t index)
{
	MPU->RNR = index;
    167a:	4f1e      	ldr	r7, [pc, #120]	; (16f4 <mpu_configure_regions+0x7c>)
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    167c:	2600      	movs	r6, #0
    167e:	428e      	cmp	r6, r1
    1680:	db01      	blt.n	1686 <mpu_configure_regions+0xe>
		/* Increment number of programmed MPU indices. */
		reg_index++;
	}

	return reg_index;
}
    1682:	4610      	mov	r0, r2
    1684:	bdf0      	pop	{r4, r5, r6, r7, pc}
		if (regions[i].size == 0U) {
    1686:	6844      	ldr	r4, [r0, #4]
    1688:	b384      	cbz	r4, 16ec <mpu_configure_regions+0x74>
		if (do_sanity_check &&
    168a:	b153      	cbz	r3, 16a2 <mpu_configure_regions+0x2a>
	 * and greater or equal to the minimum
	 * MPU region size. Start address of the
	 * partition must align with size.
	 */
	int partition_is_valid =
		((part->size & (part->size - 1U)) == 0U)
    168c:	f104 3cff 	add.w	ip, r4, #4294967295
		&&
		(part->size >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
		&&
    1690:	ea14 0f0c 	tst.w	r4, ip
    1694:	d118      	bne.n	16c8 <mpu_configure_regions+0x50>
		&&
    1696:	2c1f      	cmp	r4, #31
    1698:	d916      	bls.n	16c8 <mpu_configure_regions+0x50>
		((part->start & (part->size - 1U)) == 0U);
    169a:	6805      	ldr	r5, [r0, #0]
		&&
    169c:	ea1c 0f05 	tst.w	ip, r5
    16a0:	d112      	bne.n	16c8 <mpu_configure_regions+0x50>
 * to that power-of-two value.
 */
static inline uint32_t size_to_mpu_rasr_size(uint32_t size)
{
	/* The minimal supported region size is 32 bytes */
	if (size <= 32U) {
    16a2:	2c20      	cmp	r4, #32
	region_conf.base = new_region->start;
    16a4:	6805      	ldr	r5, [r0, #0]
	get_region_attr_from_mpu_partition_info(&region_conf.attr,
    16a6:	f8d0 c008 	ldr.w	ip, [r0, #8]
		reg_index = mpu_configure_region(reg_index, &regions[i]);
    16aa:	b2d2      	uxtb	r2, r2
    16ac:	d90f      	bls.n	16ce <mpu_configure_regions+0x56>
	/*
	 * A size value greater than 2^31 could not be handled by
	 * round_up_to_next_power_of_two() properly. We handle
	 * it separately here.
	 */
	if (size > (1UL << 31)) {
    16ae:	f1b4 4f00 	cmp.w	r4, #2147483648	; 0x80000000
    16b2:	d80e      	bhi.n	16d2 <mpu_configure_regions+0x5a>
		return REGION_4G;
	}

	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    16b4:	3c01      	subs	r4, #1
    16b6:	fab4 f484 	clz	r4, r4
    16ba:	f1c4 041f 	rsb	r4, r4, #31
    16be:	0064      	lsls	r4, r4, #1
	if (index > (get_num_regions() - 1U)) {
    16c0:	2a07      	cmp	r2, #7
#if defined(CONFIG_CPU_CORTEX_R)
	(void) size;

	p_attr->rasr = attr->rasr_attr;
#else
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    16c2:	ea4c 0404 	orr.w	r4, ip, r4
    16c6:	d906      	bls.n	16d6 <mpu_configure_regions+0x5e>
			return -EINVAL;
    16c8:	f06f 0215 	mvn.w	r2, #21
    16cc:	e7d9      	b.n	1682 <mpu_configure_regions+0xa>
		return REGION_32B;
    16ce:	2408      	movs	r4, #8
    16d0:	e7f6      	b.n	16c0 <mpu_configure_regions+0x48>
		return REGION_4G;
    16d2:	243e      	movs	r4, #62	; 0x3e
    16d4:	e7f4      	b.n	16c0 <mpu_configure_regions+0x48>
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    16d6:	f025 051f 	bic.w	r5, r5, #31
				| MPU_RBAR_VALID_Msk | index;
    16da:	4315      	orrs	r5, r2
    16dc:	f045 0510 	orr.w	r5, r5, #16
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    16e0:	f044 0401 	orr.w	r4, r4, #1
    16e4:	60ba      	str	r2, [r7, #8]
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    16e6:	60fd      	str	r5, [r7, #12]
		reg_index++;
    16e8:	3201      	adds	r2, #1
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    16ea:	613c      	str	r4, [r7, #16]
	for (i = 0; i < regions_num; i++) {
    16ec:	3601      	adds	r6, #1
    16ee:	300c      	adds	r0, #12
    16f0:	e7c5      	b.n	167e <mpu_configure_regions+0x6>
    16f2:	bf00      	nop
    16f4:	e000ed90 	.word	0xe000ed90

000016f8 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    16f8:	4b03      	ldr	r3, [pc, #12]	; (1708 <arm_core_mpu_enable+0x10>)
    16fa:	2205      	movs	r2, #5
    16fc:	605a      	str	r2, [r3, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    16fe:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1702:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    1706:	4770      	bx	lr
    1708:	e000ed90 	.word	0xe000ed90

0000170c <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    170c:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    1710:	4b01      	ldr	r3, [pc, #4]	; (1718 <arm_core_mpu_disable+0xc>)
    1712:	2200      	movs	r2, #0
    1714:	605a      	str	r2, [r3, #4]
}
    1716:	4770      	bx	lr
    1718:	e000ed90 	.word	0xe000ed90

0000171c <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    171c:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    171e:	4c03      	ldr	r4, [pc, #12]	; (172c <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    1720:	2301      	movs	r3, #1
    1722:	7822      	ldrb	r2, [r4, #0]
    1724:	f7ff ffa8 	bl	1678 <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    1728:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    172a:	bd10      	pop	{r4, pc}
    172c:	20000984 	.word	0x20000984

00001730 <arm_core_mpu_configure_dynamic_mpu_regions>:
/**
 * @brief configure dynamic MPU regions.
 */
void arm_core_mpu_configure_dynamic_mpu_regions(const struct z_arm_mpu_partition
	dynamic_regions[], uint8_t regions_num)
{
    1730:	b508      	push	{r3, lr}

	/* In ARMv7-M architecture the dynamic regions are
	 * programmed on top of existing SRAM region configuration.
	 */

	mpu_reg_index = mpu_configure_regions(dynamic_regions,
    1732:	4a08      	ldr	r2, [pc, #32]	; (1754 <arm_core_mpu_configure_dynamic_mpu_regions+0x24>)
    1734:	2300      	movs	r3, #0
    1736:	7812      	ldrb	r2, [r2, #0]
    1738:	f7ff ff9e 	bl	1678 <mpu_configure_regions>
		regions_num, mpu_reg_index, false);

	if (mpu_reg_index != -EINVAL) {
    173c:	f110 0f16 	cmn.w	r0, #22
    1740:	d003      	beq.n	174a <arm_core_mpu_configure_dynamic_mpu_regions+0x1a>
  MPU->RNR = rnr;
    1742:	4b05      	ldr	r3, [pc, #20]	; (1758 <arm_core_mpu_configure_dynamic_mpu_regions+0x28>)
  MPU->RASR = 0U;
    1744:	2200      	movs	r2, #0

		/* Disable the non-programmed MPU regions. */
		for (int i = mpu_reg_index; i < get_num_regions(); i++) {
    1746:	2807      	cmp	r0, #7
    1748:	dd00      	ble.n	174c <arm_core_mpu_configure_dynamic_mpu_regions+0x1c>
		== -EINVAL) {

		__ASSERT(0, "Configuring %u dynamic MPU regions failed\n",
			regions_num);
	}
}
    174a:	bd08      	pop	{r3, pc}
  MPU->RNR = rnr;
    174c:	6098      	str	r0, [r3, #8]
  MPU->RASR = 0U;
    174e:	611a      	str	r2, [r3, #16]
    1750:	3001      	adds	r0, #1
    1752:	e7f8      	b.n	1746 <arm_core_mpu_configure_dynamic_mpu_regions+0x16>
    1754:	20000984 	.word	0x20000984
    1758:	e000ed90 	.word	0xe000ed90

0000175c <z_arm_mpu_init>:
 */
int z_arm_mpu_init(void)
{
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    175c:	4913      	ldr	r1, [pc, #76]	; (17ac <z_arm_mpu_init+0x50>)
    175e:	6808      	ldr	r0, [r1, #0]
    1760:	2808      	cmp	r0, #8
{
    1762:	b510      	push	{r4, lr}
	if (mpu_config.num_regions > get_num_regions()) {
    1764:	d81e      	bhi.n	17a4 <z_arm_mpu_init+0x48>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    1766:	f7ff ffd1 	bl	170c <arm_core_mpu_disable>
    176a:	4c11      	ldr	r4, [pc, #68]	; (17b0 <z_arm_mpu_init+0x54>)
    176c:	6849      	ldr	r1, [r1, #4]

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    176e:	2200      	movs	r2, #0
    1770:	4290      	cmp	r0, r2
    1772:	f101 010c 	add.w	r1, r1, #12
    1776:	d105      	bne.n	1784 <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    1778:	4b0e      	ldr	r3, [pc, #56]	; (17b4 <z_arm_mpu_init+0x58>)
    177a:	7018      	strb	r0, [r3, #0]


	arm_core_mpu_enable();
    177c:	f7ff ffbc 	bl	16f8 <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    1780:	2000      	movs	r0, #0
}
    1782:	bd10      	pop	{r4, pc}
    1784:	60a2      	str	r2, [r4, #8]
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    1786:	f851 3c0c 	ldr.w	r3, [r1, #-12]
    178a:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    178e:	4313      	orrs	r3, r2
    1790:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    1794:	60e3      	str	r3, [r4, #12]
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    1796:	f851 3c04 	ldr.w	r3, [r1, #-4]
    179a:	f043 0301 	orr.w	r3, r3, #1
    179e:	6123      	str	r3, [r4, #16]
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    17a0:	3201      	adds	r2, #1
    17a2:	e7e5      	b.n	1770 <z_arm_mpu_init+0x14>
		return -1;
    17a4:	f04f 30ff 	mov.w	r0, #4294967295
    17a8:	e7eb      	b.n	1782 <z_arm_mpu_init+0x26>
    17aa:	bf00      	nop
    17ac:	00004cd0 	.word	0x00004cd0
    17b0:	e000ed90 	.word	0xe000ed90
    17b4:	20000984 	.word	0x20000984

000017b8 <nordicsemi_nrf52_init>:
	__asm__ volatile(
    17b8:	f04f 0320 	mov.w	r3, #32
    17bc:	f3ef 8211 	mrs	r2, BASEPRI
    17c0:	f383 8812 	msr	BASEPRI_MAX, r3
    17c4:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    17c8:	4906      	ldr	r1, [pc, #24]	; (17e4 <nordicsemi_nrf52_init+0x2c>)
    17ca:	2301      	movs	r3, #1
    17cc:	f8c1 3540 	str.w	r3, [r1, #1344]	; 0x540
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    17d0:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    17d4:	f8c1 3578 	str.w	r3, [r1, #1400]	; 0x578
	__asm__ volatile(
    17d8:	f382 8811 	msr	BASEPRI, r2
    17dc:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    17e0:	2000      	movs	r0, #0
    17e2:	4770      	bx	lr
    17e4:	4001e000 	.word	0x4001e000

000017e8 <sys_arch_reboot>:
    *p_gpregret = val;
    17e8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    17ec:	b2c0      	uxtb	r0, r0
    17ee:	f8c3 051c 	str.w	r0, [r3, #1308]	; 0x51c
  __ASM volatile ("dsb 0xF":::"memory");
    17f2:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    17f6:	4905      	ldr	r1, [pc, #20]	; (180c <sys_arch_reboot+0x24>)
    17f8:	4b05      	ldr	r3, [pc, #20]	; (1810 <sys_arch_reboot+0x28>)
    17fa:	68ca      	ldr	r2, [r1, #12]
    17fc:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    1800:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    1802:	60cb      	str	r3, [r1, #12]
    1804:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    1808:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    180a:	e7fd      	b.n	1808 <sys_arch_reboot+0x20>
    180c:	e000ed00 	.word	0xe000ed00
    1810:	05fa0004 	.word	0x05fa0004

00001814 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    1814:	b120      	cbz	r0, 1820 <arch_busy_wait+0xc>
    };

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    1816:	4b03      	ldr	r3, [pc, #12]	; (1824 <arch_busy_wait+0x10>)
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    1818:	0180      	lsls	r0, r0, #6
    181a:	f043 0301 	orr.w	r3, r3, #1
    181e:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    1820:	4770      	bx	lr
    1822:	bf00      	nop
    1824:	00004c90 	.word	0x00004c90

00001828 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    1828:	4a0e      	ldr	r2, [pc, #56]	; (1864 <onoff_stop+0x3c>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    182a:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    182c:	1a84      	subs	r4, r0, r2
    182e:	10a3      	asrs	r3, r4, #2
    1830:	4c0d      	ldr	r4, [pc, #52]	; (1868 <onoff_stop+0x40>)
    1832:	435c      	muls	r4, r3
{
    1834:	4605      	mov	r5, r0
    1836:	b2e4      	uxtb	r4, r4
	err = set_off_state(&subdata->flags, ctx);
    1838:	200c      	movs	r0, #12
    183a:	fb00 2004 	mla	r0, r0, r4, r2
{
    183e:	460e      	mov	r6, r1
	err = set_off_state(&subdata->flags, ctx);
    1840:	2140      	movs	r1, #64	; 0x40
    1842:	4408      	add	r0, r1
    1844:	f002 fdc7 	bl	43d6 <set_off_state>
	if (err < 0) {
    1848:	1e01      	subs	r1, r0, #0
    184a:	db05      	blt.n	1858 <onoff_stop+0x30>
	get_sub_config(dev, type)->stop();
    184c:	4b07      	ldr	r3, [pc, #28]	; (186c <onoff_stop+0x44>)
    184e:	eb03 04c4 	add.w	r4, r3, r4, lsl #3
    1852:	6863      	ldr	r3, [r4, #4]
    1854:	4798      	blx	r3
	return 0;
    1856:	2100      	movs	r1, #0
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
	notify(mgr, res);
    1858:	4628      	mov	r0, r5
    185a:	4633      	mov	r3, r6
}
    185c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    1860:	4718      	bx	r3
    1862:	bf00      	nop
    1864:	20000784 	.word	0x20000784
    1868:	b6db6db7 	.word	0xb6db6db7
    186c:	00004d04 	.word	0x00004d04

00001870 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    1870:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1874:	4e10      	ldr	r6, [pc, #64]	; (18b8 <onoff_start+0x48>)
    1876:	1b84      	subs	r4, r0, r6
    1878:	10a3      	asrs	r3, r4, #2
    187a:	4c10      	ldr	r4, [pc, #64]	; (18bc <onoff_start+0x4c>)
    187c:	435c      	muls	r4, r3
    187e:	b2e4      	uxtb	r4, r4
	err = set_starting_state(&subdata->flags, ctx);
    1880:	250c      	movs	r5, #12
    1882:	4365      	muls	r5, r4
{
    1884:	4680      	mov	r8, r0
	err = set_starting_state(&subdata->flags, ctx);
    1886:	f105 0040 	add.w	r0, r5, #64	; 0x40
{
    188a:	460f      	mov	r7, r1
	err = set_starting_state(&subdata->flags, ctx);
    188c:	4430      	add	r0, r6
    188e:	2140      	movs	r1, #64	; 0x40
    1890:	f002 fdba 	bl	4408 <set_starting_state>
	if (err < 0) {
    1894:	1e01      	subs	r1, r0, #0
    1896:	db09      	blt.n	18ac <onoff_start+0x3c>
	subdata->cb = cb;
    1898:	4a09      	ldr	r2, [pc, #36]	; (18c0 <onoff_start+0x50>)
    189a:	1973      	adds	r3, r6, r5
	subdata->user_data = user_data;
    189c:	e9c3 270e 	strd	r2, r7, [r3, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    18a0:	4b08      	ldr	r3, [pc, #32]	; (18c4 <onoff_start+0x54>)
    18a2:	f853 3034 	ldr.w	r3, [r3, r4, lsl #3]
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
		notify(mgr, err);
	}
}
    18a6:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
	 get_sub_config(dev, type)->start();
    18aa:	4718      	bx	r3
		notify(mgr, err);
    18ac:	4640      	mov	r0, r8
    18ae:	463b      	mov	r3, r7
}
    18b0:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		notify(mgr, err);
    18b4:	4718      	bx	r3
    18b6:	bf00      	nop
    18b8:	20000784 	.word	0x20000784
    18bc:	b6db6db7 	.word	0xb6db6db7
    18c0:	0000446b 	.word	0x0000446b
    18c4:	00004d04 	.word	0x00004d04

000018c8 <clk_init>:
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    18c8:	2200      	movs	r2, #0
{
    18ca:	b570      	push	{r4, r5, r6, lr}
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    18cc:	2101      	movs	r1, #1
{
    18ce:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    18d0:	4610      	mov	r0, r2
    18d2:	f7ff fc29 	bl	1128 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);
	irq_enable(DT_INST_IRQN(0));
    18d6:	2000      	movs	r0, #0
    18d8:	f7ff fc08 	bl	10ec <arch_irq_enable>

	nrfx_err = nrfx_clock_init(clock_event_handler);
    18dc:	480f      	ldr	r0, [pc, #60]	; (191c <clk_init+0x54>)
    18de:	f001 f873 	bl	29c8 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    18e2:	4b0f      	ldr	r3, [pc, #60]	; (1920 <clk_init+0x58>)
    18e4:	4298      	cmp	r0, r3
    18e6:	d115      	bne.n	1914 <clk_init+0x4c>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    18e8:	f002 ff11 	bl	470e <nrfx_clock_enable>

	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);
    18ec:	6926      	ldr	r6, [r4, #16]

		err = onoff_manager_init(get_onoff_manager(dev, i),
    18ee:	490d      	ldr	r1, [pc, #52]	; (1924 <clk_init+0x5c>)
    18f0:	4630      	mov	r0, r6
    18f2:	f002 fc2d 	bl	4150 <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    18f6:	2800      	cmp	r0, #0
    18f8:	db0b      	blt.n	1912 <clk_init+0x4a>
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    18fa:	2501      	movs	r5, #1
    18fc:	6435      	str	r5, [r6, #64]	; 0x40
						get_sub_data(dev, i);
    18fe:	6924      	ldr	r4, [r4, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    1900:	4908      	ldr	r1, [pc, #32]	; (1924 <clk_init+0x5c>)
    1902:	f104 001c 	add.w	r0, r4, #28
    1906:	f002 fc23 	bl	4150 <onoff_manager_init>
		if (err < 0) {
    190a:	2800      	cmp	r0, #0
    190c:	db01      	blt.n	1912 <clk_init+0x4a>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    190e:	64e5      	str	r5, [r4, #76]	; 0x4c
	}

	return 0;
    1910:	2000      	movs	r0, #0
}
    1912:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    1914:	f06f 0004 	mvn.w	r0, #4
    1918:	e7fb      	b.n	1912 <clk_init+0x4a>
    191a:	bf00      	nop
    191c:	0000195d 	.word	0x0000195d
    1920:	0bad0000 	.word	0x0bad0000
    1924:	00004d14 	.word	0x00004d14

00001928 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    1928:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    192a:	230c      	movs	r3, #12
    192c:	4809      	ldr	r0, [pc, #36]	; (1954 <clkstarted_handle.constprop.0+0x2c>)
    192e:	434b      	muls	r3, r1
static void clkstarted_handle(const struct device *dev,
    1930:	b570      	push	{r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    1932:	18c4      	adds	r4, r0, r3
	void *user_data = sub_data->user_data;
    1934:	e9d4 560e 	ldrd	r5, r6, [r4, #56]	; 0x38
	sub_data->cb = NULL;
    1938:	2200      	movs	r2, #0
	set_on_state(&sub_data->flags);
    193a:	3340      	adds	r3, #64	; 0x40
	sub_data->cb = NULL;
    193c:	63a2      	str	r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    193e:	4418      	add	r0, r3
    1940:	f002 fd80 	bl	4444 <set_on_state>
	if (callback) {
    1944:	b12d      	cbz	r5, 1952 <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    1946:	4632      	mov	r2, r6
    1948:	462b      	mov	r3, r5
    194a:	4803      	ldr	r0, [pc, #12]	; (1958 <clkstarted_handle.constprop.0+0x30>)
}
    194c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    1950:	4718      	bx	r3
}
    1952:	bd70      	pop	{r4, r5, r6, pc}
    1954:	20000784 	.word	0x20000784
    1958:	00004a70 	.word	0x00004a70

0000195c <clock_event_handler>:
	switch (event) {
    195c:	b110      	cbz	r0, 1964 <clock_event_handler+0x8>
    195e:	2801      	cmp	r0, #1
    1960:	d004      	beq.n	196c <clock_event_handler+0x10>
    1962:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    1964:	4b03      	ldr	r3, [pc, #12]	; (1974 <clock_event_handler+0x18>)
    1966:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    1968:	075b      	lsls	r3, r3, #29
    196a:	d101      	bne.n	1970 <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    196c:	f7ff bfdc 	b.w	1928 <clkstarted_handle.constprop.0>
}
    1970:	4770      	bx	lr
    1972:	bf00      	nop
    1974:	20000784 	.word	0x20000784

00001978 <generic_hfclk_start>:
{
    1978:	b508      	push	{r3, lr}
	__asm__ volatile(
    197a:	f04f 0320 	mov.w	r3, #32
    197e:	f3ef 8111 	mrs	r1, BASEPRI
    1982:	f383 8812 	msr	BASEPRI_MAX, r3
    1986:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    198a:	4a12      	ldr	r2, [pc, #72]	; (19d4 <generic_hfclk_start+0x5c>)
    198c:	6813      	ldr	r3, [r2, #0]
    198e:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
    1992:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
    1996:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    1998:	d00c      	beq.n	19b4 <generic_hfclk_start+0x3c>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    199a:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    199e:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    19a2:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    19a6:	f013 0301 	ands.w	r3, r3, #1
    19aa:	d003      	beq.n	19b4 <generic_hfclk_start+0x3c>
			set_on_state(get_hf_flags());
    19ac:	480a      	ldr	r0, [pc, #40]	; (19d8 <generic_hfclk_start+0x60>)
    19ae:	f002 fd49 	bl	4444 <set_on_state>
			already_started = true;
    19b2:	2301      	movs	r3, #1
	__asm__ volatile(
    19b4:	f381 8811 	msr	BASEPRI, r1
    19b8:	f3bf 8f6f 	isb	sy
	if (already_started) {
    19bc:	b123      	cbz	r3, 19c8 <generic_hfclk_start+0x50>
}
    19be:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    19c2:	2000      	movs	r0, #0
    19c4:	f7ff bfb0 	b.w	1928 <clkstarted_handle.constprop.0>
}
    19c8:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    19cc:	2001      	movs	r0, #1
    19ce:	f001 b80b 	b.w	29e8 <nrfx_clock_start>
    19d2:	bf00      	nop
    19d4:	200007d4 	.word	0x200007d4
    19d8:	200007c4 	.word	0x200007c4

000019dc <generic_hfclk_stop>:
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    19dc:	4b09      	ldr	r3, [pc, #36]	; (1a04 <generic_hfclk_stop+0x28>)
    19de:	f3bf 8f5b 	dmb	ish
    19e2:	e853 2f00 	ldrex	r2, [r3]
    19e6:	f022 0102 	bic.w	r1, r2, #2
    19ea:	e843 1000 	strex	r0, r1, [r3]
    19ee:	2800      	cmp	r0, #0
    19f0:	d1f7      	bne.n	19e2 <generic_hfclk_stop+0x6>
    19f2:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    19f6:	07d3      	lsls	r3, r2, #31
    19f8:	d402      	bmi.n	1a00 <generic_hfclk_stop+0x24>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    19fa:	2001      	movs	r0, #1
    19fc:	f001 b826 	b.w	2a4c <nrfx_clock_stop>
}
    1a00:	4770      	bx	lr
    1a02:	bf00      	nop
    1a04:	200007d4 	.word	0x200007d4

00001a08 <api_blocking_start>:
{
    1a08:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1a0a:	2200      	movs	r2, #0
    1a0c:	2301      	movs	r3, #1
    1a0e:	e9cd 2302 	strd	r2, r3, [sp, #8]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1a12:	4a09      	ldr	r2, [pc, #36]	; (1a38 <api_blocking_start+0x30>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1a14:	f8cd d000 	str.w	sp, [sp]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1a18:	466b      	mov	r3, sp
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1a1a:	f8cd d004 	str.w	sp, [sp, #4]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1a1e:	f002 fd4a 	bl	44b6 <api_start>
	if (err < 0) {
    1a22:	2800      	cmp	r0, #0
    1a24:	db05      	blt.n	1a32 <api_blocking_start+0x2a>
		/* coverity[OVERRUN] */
		return (int) arch_syscall_invoke3(*(uintptr_t *)&sem, parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    1a26:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    1a2a:	2300      	movs	r3, #0
    1a2c:	4668      	mov	r0, sp
    1a2e:	f001 fc35 	bl	329c <z_impl_k_sem_take>
}
    1a32:	b005      	add	sp, #20
    1a34:	f85d fb04 	ldr.w	pc, [sp], #4
    1a38:	00004489 	.word	0x00004489

00001a3c <z_nrf_clock_control_lf_on>:
{
    1a3c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    1a40:	493a      	ldr	r1, [pc, #232]	; (1b2c <z_nrf_clock_control_lf_on+0xf0>)
    1a42:	f3bf 8f5b 	dmb	ish
    1a46:	4606      	mov	r6, r0
    1a48:	2201      	movs	r2, #1
    1a4a:	e851 3f00 	ldrex	r3, [r1]
    1a4e:	e841 2000 	strex	r0, r2, [r1]
    1a52:	2800      	cmp	r0, #0
    1a54:	d1f9      	bne.n	1a4a <z_nrf_clock_control_lf_on+0xe>
    1a56:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    1a5a:	b933      	cbnz	r3, 1a6a <z_nrf_clock_control_lf_on+0x2e>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    1a5c:	4934      	ldr	r1, [pc, #208]	; (1b30 <z_nrf_clock_control_lf_on+0xf4>)
		err = onoff_request(mgr, &cli);
    1a5e:	4835      	ldr	r0, [pc, #212]	; (1b34 <z_nrf_clock_control_lf_on+0xf8>)
    1a60:	604b      	str	r3, [r1, #4]
    1a62:	60cb      	str	r3, [r1, #12]
    1a64:	608a      	str	r2, [r1, #8]
    1a66:	f002 fb86 	bl	4176 <onoff_request>
	switch (start_mode) {
    1a6a:	1e73      	subs	r3, r6, #1
    1a6c:	2b01      	cmp	r3, #1
    1a6e:	d832      	bhi.n	1ad6 <z_nrf_clock_control_lf_on+0x9a>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    1a70:	2e01      	cmp	r6, #1
    1a72:	d107      	bne.n	1a84 <z_nrf_clock_control_lf_on+0x48>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    1a74:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1a78:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
    1a7c:	f003 0303 	and.w	r3, r3, #3
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    1a80:	2b01      	cmp	r3, #1
    1a82:	d028      	beq.n	1ad6 <z_nrf_clock_control_lf_on+0x9a>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    1a84:	f002 febe 	bl	4804 <k_is_in_isr>
    1a88:	4604      	mov	r4, r0
    1a8a:	b918      	cbnz	r0, 1a94 <z_nrf_clock_control_lf_on+0x58>
	return !z_sys_post_kernel;
    1a8c:	4b2a      	ldr	r3, [pc, #168]	; (1b38 <z_nrf_clock_control_lf_on+0xfc>)
	int key = isr_mode ? irq_lock() : 0;
    1a8e:	781b      	ldrb	r3, [r3, #0]
    1a90:	2b00      	cmp	r3, #0
    1a92:	d144      	bne.n	1b1e <z_nrf_clock_control_lf_on+0xe2>
	__asm__ volatile(
    1a94:	f04f 0320 	mov.w	r3, #32
    1a98:	f3ef 8511 	mrs	r5, BASEPRI
    1a9c:	f383 8812 	msr	BASEPRI_MAX, r3
    1aa0:	f3bf 8f6f 	isb	sy
    1aa4:	2401      	movs	r4, #1
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    1aa6:	4f25      	ldr	r7, [pc, #148]	; (1b3c <z_nrf_clock_control_lf_on+0x100>)
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1aa8:	f8df 8094 	ldr.w	r8, [pc, #148]	; 1b40 <z_nrf_clock_control_lf_on+0x104>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    1aac:	f8df 9094 	ldr.w	r9, [pc, #148]	; 1b44 <z_nrf_clock_control_lf_on+0x108>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    1ab0:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    1ab4:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    1ab8:	f8d2 2418 	ldr.w	r2, [r2, #1048]	; 0x418
    1abc:	03d2      	lsls	r2, r2, #15
    1abe:	d50c      	bpl.n	1ada <z_nrf_clock_control_lf_on+0x9e>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    1ac0:	f003 0303 	and.w	r3, r3, #3
	while (!(nrfx_clock_is_running(d, (void *)&type)
    1ac4:	2b01      	cmp	r3, #1
    1ac6:	d001      	beq.n	1acc <z_nrf_clock_control_lf_on+0x90>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    1ac8:	2e01      	cmp	r6, #1
    1aca:	d106      	bne.n	1ada <z_nrf_clock_control_lf_on+0x9e>
	if (isr_mode) {
    1acc:	b30c      	cbz	r4, 1b12 <z_nrf_clock_control_lf_on+0xd6>
	__asm__ volatile(
    1ace:	f385 8811 	msr	BASEPRI, r5
    1ad2:	f3bf 8f6f 	isb	sy
}
    1ad6:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    1ada:	b1ac      	cbz	r4, 1b08 <z_nrf_clock_control_lf_on+0xcc>
 *
 * @return N/A
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    1adc:	4628      	mov	r0, r5
    1ade:	f7ff fafb 	bl	10d8 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    1ae2:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    1ae6:	f8d2 3518 	ldr.w	r3, [r2, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    1aea:	2b00      	cmp	r3, #0
    1aec:	d1e0      	bne.n	1ab0 <z_nrf_clock_control_lf_on+0x74>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    1aee:	6839      	ldr	r1, [r7, #0]
		    && nrf_clock_event_check(NRF_CLOCK,
    1af0:	2900      	cmp	r1, #0
    1af2:	d0dd      	beq.n	1ab0 <z_nrf_clock_control_lf_on+0x74>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    1af4:	603b      	str	r3, [r7, #0]
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    1af6:	683b      	ldr	r3, [r7, #0]
    p_reg->LFCLKSRC = (uint32_t)(source);
    1af8:	2301      	movs	r3, #1
    1afa:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    1afe:	f8c8 3180 	str.w	r3, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    1b02:	f8c9 3000 	str.w	r3, [r9]
}
    1b06:	e7d3      	b.n	1ab0 <z_nrf_clock_control_lf_on+0x74>
	return z_impl_k_sleep(timeout);
    1b08:	2100      	movs	r1, #0
    1b0a:	2021      	movs	r0, #33	; 0x21
    1b0c:	f001 feda 	bl	38c4 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    1b10:	e7e7      	b.n	1ae2 <z_nrf_clock_control_lf_on+0xa6>
    p_reg->INTENSET = mask;
    1b12:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1b16:	2202      	movs	r2, #2
    1b18:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    1b1c:	e7db      	b.n	1ad6 <z_nrf_clock_control_lf_on+0x9a>
    p_reg->INTENCLR = mask;
    1b1e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1b22:	2202      	movs	r2, #2
    1b24:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
	int key = isr_mode ? irq_lock() : 0;
    1b28:	4605      	mov	r5, r0
}
    1b2a:	e7bc      	b.n	1aa6 <z_nrf_clock_control_lf_on+0x6a>
    1b2c:	200007d8 	.word	0x200007d8
    1b30:	20000774 	.word	0x20000774
    1b34:	200007a0 	.word	0x200007a0
    1b38:	20000d96 	.word	0x20000d96
    1b3c:	40000104 	.word	0x40000104
    1b40:	e000e100 	.word	0xe000e100
    1b44:	40000008 	.word	0x40000008

00001b48 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    1b48:	b508      	push	{r3, lr}
	static bool gpio_initialized;

	if (!gpio_initialized) {
    1b4a:	4b09      	ldr	r3, [pc, #36]	; (1b70 <gpio_nrfx_init+0x28>)
    1b4c:	781a      	ldrb	r2, [r3, #0]
    1b4e:	b96a      	cbnz	r2, 1b6c <gpio_nrfx_init+0x24>
		gpio_initialized = true;
    1b50:	2101      	movs	r1, #1
    1b52:	7019      	strb	r1, [r3, #0]
		IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    1b54:	2006      	movs	r0, #6
    1b56:	2105      	movs	r1, #5
    1b58:	f7ff fae6 	bl	1128 <z_arm_irq_priority_set>
			    gpiote_event_handler, NULL, 0);

		irq_enable(DT_IRQN(GPIOTE_NODE));
    1b5c:	2006      	movs	r0, #6
    1b5e:	f7ff fac5 	bl	10ec <arch_irq_enable>
    return ((uint32_t)p_reg + event);
}

NRF_STATIC_INLINE void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask)
{
    p_reg->INTENSET = mask;
    1b62:	4b04      	ldr	r3, [pc, #16]	; (1b74 <gpio_nrfx_init+0x2c>)
    1b64:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    1b68:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
		nrf_gpiote_int_enable(NRF_GPIOTE, NRF_GPIOTE_INT_PORT_MASK);
	}

	return 0;
}
    1b6c:	2000      	movs	r0, #0
    1b6e:	bd08      	pop	{r3, pc}
    1b70:	20000985 	.word	0x20000985
    1b74:	40006000 	.word	0x40006000

00001b78 <gpio_nrfx_config>:
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1b78:	4b2b      	ldr	r3, [pc, #172]	; (1c28 <gpio_nrfx_config+0xb0>)
{
    1b7a:	b5f0      	push	{r4, r5, r6, r7, lr}
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    1b7c:	6844      	ldr	r4, [r0, #4]
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1b7e:	482b      	ldr	r0, [pc, #172]	; (1c2c <gpio_nrfx_config+0xb4>)
    1b80:	4013      	ands	r3, r2
    1b82:	4283      	cmp	r3, r0
    1b84:	d041      	beq.n	1c0a <gpio_nrfx_config+0x92>
    1b86:	d80d      	bhi.n	1ba4 <gpio_nrfx_config+0x2c>
    1b88:	2b06      	cmp	r3, #6
    1b8a:	d015      	beq.n	1bb8 <gpio_nrfx_config+0x40>
    1b8c:	d805      	bhi.n	1b9a <gpio_nrfx_config+0x22>
    1b8e:	b19b      	cbz	r3, 1bb8 <gpio_nrfx_config+0x40>
    1b90:	2b02      	cmp	r3, #2
    1b92:	d03c      	beq.n	1c0e <gpio_nrfx_config+0x96>
    1b94:	f06f 0015 	mvn.w	r0, #21
    1b98:	e036      	b.n	1c08 <gpio_nrfx_config+0x90>
    1b9a:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    1b9e:	d1f9      	bne.n	1b94 <gpio_nrfx_config+0x1c>
		drive = NRF_GPIO_PIN_H0S1;
    1ba0:	2301      	movs	r3, #1
    1ba2:	e009      	b.n	1bb8 <gpio_nrfx_config+0x40>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1ba4:	4822      	ldr	r0, [pc, #136]	; (1c30 <gpio_nrfx_config+0xb8>)
    1ba6:	4283      	cmp	r3, r0
    1ba8:	d033      	beq.n	1c12 <gpio_nrfx_config+0x9a>
    1baa:	f5b3 0fa0 	cmp.w	r3, #5242880	; 0x500000
    1bae:	d032      	beq.n	1c16 <gpio_nrfx_config+0x9e>
    1bb0:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
    1bb4:	d1ee      	bne.n	1b94 <gpio_nrfx_config+0x1c>
		drive = NRF_GPIO_PIN_S0H1;
    1bb6:	2302      	movs	r3, #2
	if ((flags & GPIO_PULL_UP) != 0) {
    1bb8:	06d0      	lsls	r0, r2, #27
		pull = NRF_GPIO_PIN_NOPULL;
    1bba:	bf54      	ite	pl
    1bbc:	f3c2 1640 	ubfxpl	r6, r2, #5, #1
		pull = NRF_GPIO_PIN_PULLUP;
    1bc0:	2603      	movmi	r6, #3
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
    1bc2:	f482 7580 	eor.w	r5, r2, #256	; 0x100
	if ((flags & GPIO_OUTPUT) != 0) {
    1bc6:	0597      	lsls	r7, r2, #22
	dir = ((flags & GPIO_OUTPUT) != 0)
    1bc8:	f3c2 2040 	ubfx	r0, r2, #9, #1
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
    1bcc:	f3c5 2500 	ubfx	r5, r5, #8, #1
	if ((flags & GPIO_OUTPUT) != 0) {
    1bd0:	d507      	bpl.n	1be2 <gpio_nrfx_config+0x6a>
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
    1bd2:	f412 6f00 	tst.w	r2, #2048	; 0x800
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    1bd6:	6867      	ldr	r7, [r4, #4]
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
    1bd8:	d01f      	beq.n	1c1a <gpio_nrfx_config+0xa2>
			nrf_gpio_port_out_set(reg, BIT(pin));
    1bda:	2201      	movs	r2, #1
    1bdc:	408a      	lsls	r2, r1
}


NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
{
    p_reg->OUTSET = set_mask;
    1bde:	f8c7 2508 	str.w	r2, [r7, #1288]	; 0x508
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;

    return pin_number >> 5;
    1be2:	7a22      	ldrb	r2, [r4, #8]
        case 1: return NRF_P1;
    1be4:	4c13      	ldr	r4, [pc, #76]	; (1c34 <gpio_nrfx_config+0xbc>)
    1be6:	2a01      	cmp	r2, #1
    *p_pin = pin_number & 0x1F;
    1be8:	f001 011f 	and.w	r1, r1, #31
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    1bec:	ea40 0245 	orr.w	r2, r0, r5, lsl #1
        case 1: return NRF_P1;
    1bf0:	bf18      	it	ne
    1bf2:	f04f 44a0 	movne.w	r4, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    1bf6:	ea42 2303 	orr.w	r3, r2, r3, lsl #8
    reg->PIN_CNF[pin_number] = cnf;
    1bfa:	f501 71e0 	add.w	r1, r1, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    1bfe:	ea43 0386 	orr.w	r3, r3, r6, lsl #2
    reg->PIN_CNF[pin_number] = cnf;
    1c02:	f844 3021 	str.w	r3, [r4, r1, lsl #2]
	return 0;
    1c06:	2000      	movs	r0, #0
}
    1c08:	bdf0      	pop	{r4, r5, r6, r7, pc}
		drive = NRF_GPIO_PIN_H0D1;
    1c0a:	2307      	movs	r3, #7
    1c0c:	e7d4      	b.n	1bb8 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_D0S1;
    1c0e:	2304      	movs	r3, #4
    1c10:	e7d2      	b.n	1bb8 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_D0H1;
    1c12:	2305      	movs	r3, #5
    1c14:	e7d0      	b.n	1bb8 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_H0H1;
    1c16:	2303      	movs	r3, #3
    1c18:	e7ce      	b.n	1bb8 <gpio_nrfx_config+0x40>
		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
    1c1a:	0552      	lsls	r2, r2, #21
			nrf_gpio_port_out_clear(reg, BIT(pin));
    1c1c:	bf42      	ittt	mi
    1c1e:	2201      	movmi	r2, #1
    1c20:	408a      	lslmi	r2, r1
    p_reg->OUTCLR = clr_mask;
    1c22:	f8c7 250c 	strmi.w	r2, [r7, #1292]	; 0x50c
}
    1c26:	e7dc      	b.n	1be2 <gpio_nrfx_config+0x6a>
    1c28:	00f00006 	.word	0x00f00006
    1c2c:	00100006 	.word	0x00100006
    1c30:	00400002 	.word	0x00400002
    1c34:	50000300 	.word	0x50000300

00001c38 <nrf_gpio_cfg_sense_set>:
    *p_pin = pin_number & 0x1F;
    1c38:	f000 021f 	and.w	r2, r0, #31
    return pin_number >> 5;
    1c3c:	0940      	lsrs	r0, r0, #5
        case 1: return NRF_P1;
    1c3e:	4b08      	ldr	r3, [pc, #32]	; (1c60 <nrf_gpio_cfg_sense_set+0x28>)
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    1c40:	2801      	cmp	r0, #1
        case 1: return NRF_P1;
    1c42:	bf18      	it	ne
    1c44:	f04f 43a0 	movne.w	r3, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    1c48:	eb03 0382 	add.w	r3, r3, r2, lsl #2
    1c4c:	f8d3 2700 	ldr.w	r2, [r3, #1792]	; 0x700
    1c50:	f422 3240 	bic.w	r2, r2, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    1c54:	ea42 4201 	orr.w	r2, r2, r1, lsl #16
    1c58:	f8c3 2700 	str.w	r2, [r3, #1792]	; 0x700
}
    1c5c:	4770      	bx	lr
    1c5e:	bf00      	nop
    1c60:	50000300 	.word	0x50000300

00001c64 <check_level_trigger_pins>:
{
    1c64:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	struct gpio_nrfx_data *data = get_port_data(port);
    1c68:	6903      	ldr	r3, [r0, #16]
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
    1c6a:	f8d0 a004 	ldr.w	sl, [r0, #4]
	uint32_t out = data->pin_int_en;
    1c6e:	68de      	ldr	r6, [r3, #12]
        case 1: return NRF_P1;
    1c70:	f8df b07c 	ldr.w	fp, [pc, #124]	; 1cf0 <check_level_trigger_pins+0x8c>
{
    1c74:	4688      	mov	r8, r1
	out &= ~data->trig_edge & ~data->double_edge;
    1c76:	e9d3 2105 	ldrd	r2, r1, [r3, #20]
    1c7a:	430a      	orrs	r2, r1
    1c7c:	ea26 0602 	bic.w	r6, r6, r2
	uint32_t port_in = nrf_gpio_port_in_read(cfg->port);
    1c80:	f8da 2004 	ldr.w	r2, [sl, #4]
	uint32_t pin_states = ~(port_in ^ data->int_active_level);
    1c84:	691b      	ldr	r3, [r3, #16]
    return p_reg->IN;
    1c86:	f8d2 5510 	ldr.w	r5, [r2, #1296]	; 0x510
    1c8a:	405d      	eors	r5, r3
	uint32_t out = pin_states & level_pins;
    1c8c:	ea26 0505 	bic.w	r5, r6, r5
	uint32_t check_pins = level_pins;
    1c90:	4637      	mov	r7, r6
	uint32_t bit = 1U << pin;
    1c92:	2401      	movs	r4, #1
	uint32_t pin = 0U;
    1c94:	f04f 0900 	mov.w	r9, #0
	while (check_pins) {
    1c98:	b917      	cbnz	r7, 1ca0 <check_level_trigger_pins+0x3c>
}
    1c9a:	4628      	mov	r0, r5
    1c9c:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
		if (check_pins & bit) {
    1ca0:	423c      	tst	r4, r7
    1ca2:	d021      	beq.n	1ce8 <check_level_trigger_pins+0x84>
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    1ca4:	f89a 3008 	ldrb.w	r3, [sl, #8]
    1ca8:	f009 001f 	and.w	r0, r9, #31
			if (!(level_pins & bit)) {
    1cac:	4234      	tst	r4, r6
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    1cae:	ea40 1043 	orr.w	r0, r0, r3, lsl #5
			if (!(level_pins & bit)) {
    1cb2:	d114      	bne.n	1cde <check_level_trigger_pins+0x7a>
    return pin_number >> 5;
    1cb4:	0942      	lsrs	r2, r0, #5
        case 1: return NRF_P1;
    1cb6:	2a01      	cmp	r2, #1
    *p_pin = pin_number & 0x1F;
    1cb8:	f000 031f 	and.w	r3, r0, #31
        case 1: return NRF_P1;
    1cbc:	bf14      	ite	ne
    1cbe:	f04f 42a0 	movne.w	r2, #1342177280	; 0x50000000
    1cc2:	465a      	moveq	r2, fp
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    1cc4:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    1cc8:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    1ccc:	f3c3 4301 	ubfx	r3, r3, #16, #2
				if (high) {
    1cd0:	2b02      	cmp	r3, #2
					*sense_levels |= bit;
    1cd2:	bf02      	ittt	eq
    1cd4:	f8d8 3000 	ldreq.w	r3, [r8]
    1cd8:	4323      	orreq	r3, r4
    1cda:	f8c8 3000 	streq.w	r3, [r8]
			nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
    1cde:	2100      	movs	r1, #0
    1ce0:	f7ff ffaa 	bl	1c38 <nrf_gpio_cfg_sense_set>
			check_pins &= ~bit;
    1ce4:	ea27 0704 	bic.w	r7, r7, r4
		++pin;
    1ce8:	f109 0901 	add.w	r9, r9, #1
		bit <<= 1;
    1cec:	0064      	lsls	r4, r4, #1
    1cee:	e7d3      	b.n	1c98 <check_level_trigger_pins+0x34>
    1cf0:	50000300 	.word	0x50000300

00001cf4 <gpio_nrfx_pin_interrupt_configure>:
{
    1cf4:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    1cf6:	460e      	mov	r6, r1
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    1cf8:	6841      	ldr	r1, [r0, #4]
	struct gpio_nrfx_data *data = get_port_data(port);
    1cfa:	6907      	ldr	r7, [r0, #16]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    1cfc:	7a09      	ldrb	r1, [r1, #8]
    1cfe:	f006 051f 	and.w	r5, r6, #31
	if (!IS_ENABLED(CONFIG_GPIO_NRF_INT_EDGE_USING_SENSE) &&
    1d02:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    1d06:	ea45 1541 	orr.w	r5, r5, r1, lsl #5
    1d0a:	d110      	bne.n	1d2e <gpio_nrfx_pin_interrupt_configure+0x3a>
    return pin_number >> 5;
    1d0c:	0968      	lsrs	r0, r5, #5
        case 1: return NRF_P1;
    1d0e:	2801      	cmp	r0, #1
    *p_pin = pin_number & 0x1F;
    1d10:	f005 011f 	and.w	r1, r5, #31
        case 1: return NRF_P1;
    1d14:	485d      	ldr	r0, [pc, #372]	; (1e8c <gpio_nrfx_pin_interrupt_configure+0x198>)
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    1d16:	f501 71e0 	add.w	r1, r1, #448	; 0x1c0
        case 1: return NRF_P1;
    1d1a:	bf18      	it	ne
    1d1c:	f04f 40a0 	movne.w	r0, #1342177280	; 0x50000000
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    1d20:	f850 1021 	ldr.w	r1, [r0, r1, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    1d24:	07c8      	lsls	r0, r1, #31
    1d26:	d507      	bpl.n	1d38 <gpio_nrfx_pin_interrupt_configure+0x44>
		return -ENOTSUP;
    1d28:	f06f 0085 	mvn.w	r0, #133	; 0x85
    1d2c:	e093      	b.n	1e56 <gpio_nrfx_pin_interrupt_configure+0x162>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    1d2e:	f5b2 5f00 	cmp.w	r2, #8192	; 0x2000
    1d32:	68f9      	ldr	r1, [r7, #12]
    1d34:	f000 8091 	beq.w	1e5a <gpio_nrfx_pin_interrupt_configure+0x166>
    1d38:	68f8      	ldr	r0, [r7, #12]
    1d3a:	2101      	movs	r1, #1
    1d3c:	40b1      	lsls	r1, r6
    1d3e:	4301      	orrs	r1, r0
    1d40:	6978      	ldr	r0, [r7, #20]
    1d42:	60f9      	str	r1, [r7, #12]
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    1d44:	2101      	movs	r1, #1
    1d46:	40b1      	lsls	r1, r6
    1d48:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    1d4c:	69ba      	ldr	r2, [r7, #24]
    1d4e:	bf0c      	ite	eq
    1d50:	4308      	orreq	r0, r1
    1d52:	4388      	bicne	r0, r1
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
    1d54:	f5b3 2fc0 	cmp.w	r3, #393216	; 0x60000
    1d58:	bf0c      	ite	eq
    1d5a:	430a      	orreq	r2, r1
    1d5c:	438a      	bicne	r2, r1
    1d5e:	61ba      	str	r2, [r7, #24]
    1d60:	693a      	ldr	r2, [r7, #16]
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    1d62:	6178      	str	r0, [r7, #20]
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    1d64:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
    1d68:	bf0c      	ite	eq
    1d6a:	4311      	orreq	r1, r2
    1d6c:	ea22 0101 	bicne.w	r1, r2, r1
    p_reg->INTENCLR = mask;
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask)
{
    return p_reg->INTENSET & mask;
    1d70:	4a47      	ldr	r2, [pc, #284]	; (1e90 <gpio_nrfx_pin_interrupt_configure+0x19c>)
    1d72:	6139      	str	r1, [r7, #16]
    1d74:	f8d2 3304 	ldr.w	r3, [r2, #772]	; 0x304
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    1d78:	2000      	movs	r0, #0
    1d7a:	b2db      	uxtb	r3, r3
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
{
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    1d7c:	f500 71a2 	add.w	r1, r0, #324	; 0x144
    1d80:	f852 1021 	ldr.w	r1, [r2, r1, lsl #2]
    1d84:	f3c1 2105 	ubfx	r1, r1, #8, #6
		if ((nrf_gpiote_event_pin_get(NRF_GPIOTE, i) == abs_pin)
    1d88:	428d      	cmp	r5, r1
    1d8a:	d16b      	bne.n	1e64 <gpio_nrfx_pin_interrupt_configure+0x170>
		    && (intenset & BIT(i))) {
    1d8c:	fa23 f100 	lsr.w	r1, r3, r0
    1d90:	07c9      	lsls	r1, r1, #31
    1d92:	d567      	bpl.n	1e64 <gpio_nrfx_pin_interrupt_configure+0x170>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
    1d94:	0083      	lsls	r3, r0, #2
    1d96:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    1d9a:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    1d9e:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
    1da2:	f021 0101 	bic.w	r1, r1, #1
    1da6:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
			nrf_gpiote_int_disable(NRF_GPIOTE, BIT(i));
    1daa:	2301      	movs	r3, #1
    1dac:	4083      	lsls	r3, r0
    p_reg->INTENCLR = mask;
    1dae:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
			nrfx_gpiote_channel_free(i);
    1db2:	b2c0      	uxtb	r0, r0
    1db4:	f000 fec4 	bl	2b40 <nrfx_gpiote_channel_free>
	nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
    1db8:	4628      	mov	r0, r5
    1dba:	2100      	movs	r1, #0
    1dbc:	f7ff ff3c 	bl	1c38 <nrf_gpio_cfg_sense_set>
	if (data->pin_int_en & BIT(pin)) {
    1dc0:	68f8      	ldr	r0, [r7, #12]
    1dc2:	40f0      	lsrs	r0, r6
    1dc4:	f010 0001 	ands.w	r0, r0, #1
    1dc8:	d045      	beq.n	1e56 <gpio_nrfx_pin_interrupt_configure+0x162>
		if (data->trig_edge & BIT(pin)) {
    1dca:	6978      	ldr	r0, [r7, #20]
    1dcc:	40f0      	lsrs	r0, r6
    1dce:	f010 0401 	ands.w	r4, r0, #1
    1dd2:	d04e      	beq.n	1e72 <gpio_nrfx_pin_interrupt_configure+0x17e>
				if (data->double_edge & BIT(pin)) {
    1dd4:	69bb      	ldr	r3, [r7, #24]
    1dd6:	40f3      	lsrs	r3, r6
    1dd8:	07db      	lsls	r3, r3, #31
				} else if ((data->int_active_level & BIT(pin)) != 0U) {
    1dda:	bf5f      	itttt	pl
    1ddc:	6939      	ldrpl	r1, [r7, #16]
    1dde:	fa21 f606 	lsrpl.w	r6, r1, r6
    1de2:	f006 0601 	andpl.w	r6, r6, #1
    1de6:	f1c6 0602 	rsbpl	r6, r6, #2
	if (nrfx_gpiote_channel_alloc(&channel) != NRFX_SUCCESS) {
    1dea:	f10d 0007 	add.w	r0, sp, #7
				} else if ((data->int_active_level & BIT(pin)) != 0U) {
    1dee:	bf54      	ite	pl
    1df0:	b2f6      	uxtbpl	r6, r6
					pol = NRF_GPIOTE_POLARITY_TOGGLE;
    1df2:	2603      	movmi	r6, #3
	if (nrfx_gpiote_channel_alloc(&channel) != NRFX_SUCCESS) {
    1df4:	f000 fec6 	bl	2b84 <nrfx_gpiote_channel_alloc>
    1df8:	4b26      	ldr	r3, [pc, #152]	; (1e94 <gpio_nrfx_pin_interrupt_configure+0x1a0>)
    1dfa:	4298      	cmp	r0, r3
    1dfc:	d136      	bne.n	1e6c <gpio_nrfx_pin_interrupt_configure+0x178>
	nrf_gpiote_event_t evt = offsetof(NRF_GPIOTE_Type, EVENTS_IN[channel]);
    1dfe:	f89d 1007 	ldrb.w	r1, [sp, #7]
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    1e02:	008b      	lsls	r3, r1, #2
    1e04:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    1e08:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    1e0c:	022d      	lsls	r5, r5, #8
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    1e0e:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    1e12:	f422 324f 	bic.w	r2, r2, #211968	; 0x33c00
    1e16:	f422 7240 	bic.w	r2, r2, #768	; 0x300
    1e1a:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    1e1e:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    1e22:	f405 557c 	and.w	r5, r5, #16128	; 0x3f00
    1e26:	4315      	orrs	r5, r2
    return ((uint32_t)p_reg + event);
    1e28:	008a      	lsls	r2, r1, #2
    1e2a:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    1e2e:	f502 42c2 	add.w	r2, r2, #24832	; 0x6100
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    1e32:	ea45 4606 	orr.w	r6, r5, r6, lsl #16
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    1e36:	2000      	movs	r0, #0
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    1e38:	f8c3 6510 	str.w	r6, [r3, #1296]	; 0x510
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    1e3c:	6010      	str	r0, [r2, #0]
    1e3e:	6812      	ldr	r2, [r2, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    1e40:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    1e44:	f042 0201 	orr.w	r2, r2, #1
    1e48:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
    p_reg->INTENSET = mask;
    1e4c:	4a10      	ldr	r2, [pc, #64]	; (1e90 <gpio_nrfx_pin_interrupt_configure+0x19c>)
	nrf_gpiote_int_enable(NRF_GPIOTE, BIT(channel));
    1e4e:	2301      	movs	r3, #1
    1e50:	408b      	lsls	r3, r1
    1e52:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    1e56:	b003      	add	sp, #12
    1e58:	bdf0      	pop	{r4, r5, r6, r7, pc}
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    1e5a:	2001      	movs	r0, #1
    1e5c:	40b0      	lsls	r0, r6
    1e5e:	ea21 0100 	bic.w	r1, r1, r0
    1e62:	e76d      	b.n	1d40 <gpio_nrfx_pin_interrupt_configure+0x4c>
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    1e64:	3001      	adds	r0, #1
    1e66:	2808      	cmp	r0, #8
    1e68:	d188      	bne.n	1d7c <gpio_nrfx_pin_interrupt_configure+0x88>
    1e6a:	e7a5      	b.n	1db8 <gpio_nrfx_pin_interrupt_configure+0xc4>
		return -ENODEV;
    1e6c:	f06f 0012 	mvn.w	r0, #18
    1e70:	e7f1      	b.n	1e56 <gpio_nrfx_pin_interrupt_configure+0x162>
	if ((BIT(pin) & data->int_active_level) != 0U) {
    1e72:	6939      	ldr	r1, [r7, #16]
    1e74:	40f1      	lsrs	r1, r6
    1e76:	f001 0101 	and.w	r1, r1, #1
    1e7a:	f1c1 0103 	rsb	r1, r1, #3
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    1e7e:	4628      	mov	r0, r5
    1e80:	b2c9      	uxtb	r1, r1
    1e82:	f7ff fed9 	bl	1c38 <nrf_gpio_cfg_sense_set>
	int res = 0;
    1e86:	4620      	mov	r0, r4
    1e88:	e7e5      	b.n	1e56 <gpio_nrfx_pin_interrupt_configure+0x162>
    1e8a:	bf00      	nop
    1e8c:	50000300 	.word	0x50000300
    1e90:	40006000 	.word	0x40006000
    1e94:	0bad0000 	.word	0x0bad0000

00001e98 <gpiote_event_handler>:
{
    1e98:	b5f0      	push	{r4, r5, r6, r7, lr}
	uint32_t fired_triggers[GPIO_COUNT] = {0};
    1e9a:	2400      	movs	r4, #0
{
    1e9c:	b085      	sub	sp, #20
	uint32_t fired_triggers[GPIO_COUNT] = {0};
    1e9e:	e9cd 4400 	strd	r4, r4, [sp]
	uint32_t sense_levels[GPIO_COUNT] = {0};
    1ea2:	e9cd 4402 	strd	r4, r4, [sp, #8]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    1ea6:	4e26      	ldr	r6, [pc, #152]	; (1f40 <gpiote_event_handler+0xa8>)
    1ea8:	6835      	ldr	r5, [r6, #0]
	if (port_event) {
    1eaa:	b15d      	cbz	r5, 1ec4 <gpiote_event_handler+0x2c>
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(0)),
    1eac:	a902      	add	r1, sp, #8
    1eae:	4825      	ldr	r0, [pc, #148]	; (1f44 <gpiote_event_handler+0xac>)
    1eb0:	f7ff fed8 	bl	1c64 <check_level_trigger_pins>
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(1)),
    1eb4:	a903      	add	r1, sp, #12
		fired_triggers[0] =
    1eb6:	9000      	str	r0, [sp, #0]
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(1)),
    1eb8:	4823      	ldr	r0, [pc, #140]	; (1f48 <gpiote_event_handler+0xb0>)
    1eba:	f7ff fed3 	bl	1c64 <check_level_trigger_pins>
		fired_triggers[1] =
    1ebe:	9001      	str	r0, [sp, #4]
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    1ec0:	6034      	str	r4, [r6, #0]
    1ec2:	6833      	ldr	r3, [r6, #0]
    return p_reg->INTENSET & mask;
    1ec4:	4c21      	ldr	r4, [pc, #132]	; (1f4c <gpiote_event_handler+0xb4>)
{
    1ec6:	2200      	movs	r2, #0
		if (nrf_gpiote_int_enable_check(NRF_GPIOTE, BIT(i)) &&
    1ec8:	2601      	movs	r6, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    1eca:	4694      	mov	ip, r2
    return p_reg->INTENSET & mask;
    1ecc:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
    1ed0:	fa06 f102 	lsl.w	r1, r6, r2
    1ed4:	4219      	tst	r1, r3
    1ed6:	d01b      	beq.n	1f10 <gpiote_event_handler+0x78>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    1ed8:	0091      	lsls	r1, r2, #2
    1eda:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    1ede:	f501 41c2 	add.w	r1, r1, #24832	; 0x6100
    1ee2:	680b      	ldr	r3, [r1, #0]
    1ee4:	b1a3      	cbz	r3, 1f10 <gpiote_event_handler+0x78>
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    1ee6:	f502 73a2 	add.w	r3, r2, #324	; 0x144
			fired_triggers[abs_pin / 32U] |= BIT(abs_pin % 32);
    1eea:	af04      	add	r7, sp, #16
    1eec:	f854 3023 	ldr.w	r3, [r4, r3, lsl #2]
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    1ef0:	f8c1 c000 	str.w	ip, [r1]
    1ef4:	f3c3 3040 	ubfx	r0, r3, #13, #1
    1ef8:	eb07 0080 	add.w	r0, r7, r0, lsl #2
    1efc:	f3c3 2304 	ubfx	r3, r3, #8, #5
    1f00:	f850 7c10 	ldr.w	r7, [r0, #-16]
    1f04:	fa06 f303 	lsl.w	r3, r6, r3
    1f08:	433b      	orrs	r3, r7
    1f0a:	f840 3c10 	str.w	r3, [r0, #-16]
    1f0e:	680b      	ldr	r3, [r1, #0]
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    1f10:	3201      	adds	r2, #1
    1f12:	2a08      	cmp	r2, #8
    1f14:	d1da      	bne.n	1ecc <gpiote_event_handler+0x34>
	if (fired_triggers[0]) {
    1f16:	9a00      	ldr	r2, [sp, #0]
    1f18:	b11a      	cbz	r2, 1f22 <gpiote_event_handler+0x8a>
	gpio_fire_callbacks(list, port, pins);
    1f1a:	490a      	ldr	r1, [pc, #40]	; (1f44 <gpiote_event_handler+0xac>)
    1f1c:	480c      	ldr	r0, [pc, #48]	; (1f50 <gpiote_event_handler+0xb8>)
    1f1e:	f002 fae5 	bl	44ec <gpio_fire_callbacks>
	if (fired_triggers[1]) {
    1f22:	9a01      	ldr	r2, [sp, #4]
    1f24:	b11a      	cbz	r2, 1f2e <gpiote_event_handler+0x96>
	gpio_fire_callbacks(list, port, pins);
    1f26:	4908      	ldr	r1, [pc, #32]	; (1f48 <gpiote_event_handler+0xb0>)
    1f28:	480a      	ldr	r0, [pc, #40]	; (1f54 <gpiote_event_handler+0xbc>)
    1f2a:	f002 fadf 	bl	44ec <gpio_fire_callbacks>
	if (port_event) {
    1f2e:	b12d      	cbz	r5, 1f3c <gpiote_event_handler+0xa4>
		cfg_level_pins(DEVICE_DT_GET(GPIO(0)));
    1f30:	4804      	ldr	r0, [pc, #16]	; (1f44 <gpiote_event_handler+0xac>)
    1f32:	f002 fb45 	bl	45c0 <cfg_level_pins>
		cfg_level_pins(DEVICE_DT_GET(GPIO(1)));
    1f36:	4804      	ldr	r0, [pc, #16]	; (1f48 <gpiote_event_handler+0xb0>)
    1f38:	f002 fb42 	bl	45c0 <cfg_level_pins>
}
    1f3c:	b005      	add	sp, #20
    1f3e:	bdf0      	pop	{r4, r5, r6, r7, pc}
    1f40:	4000617c 	.word	0x4000617c
    1f44:	00004ab8 	.word	0x00004ab8
    1f48:	00004ad0 	.word	0x00004ad0
    1f4c:	40006000 	.word	0x40006000
    1f50:	200007e0 	.word	0x200007e0
    1f54:	200007fc 	.word	0x200007fc

00001f58 <uarte_nrfx_configure>:
	return 0;
}

static int uarte_nrfx_configure(const struct device *dev,
				const struct uart_config *cfg)
{
    1f58:	b5f0      	push	{r4, r5, r6, r7, lr}
	nrf_uarte_config_t uarte_cfg;

#if defined(UARTE_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
    1f5a:	794b      	ldrb	r3, [r1, #5]
    1f5c:	2b01      	cmp	r3, #1
    1f5e:	d02a      	beq.n	1fb6 <uarte_nrfx_configure+0x5e>
    1f60:	2b03      	cmp	r3, #3
    1f62:	d125      	bne.n	1fb0 <uarte_nrfx_configure+0x58>
	case UART_CFG_STOP_BITS_1:
		uarte_cfg.stop = NRF_UARTE_STOP_ONE;
		break;
	case UART_CFG_STOP_BITS_2:
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
    1f64:	2610      	movs	r6, #16
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    1f66:	798b      	ldrb	r3, [r1, #6]
    1f68:	2b03      	cmp	r3, #3
    1f6a:	d121      	bne.n	1fb0 <uarte_nrfx_configure+0x58>
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
    1f6c:	79cc      	ldrb	r4, [r1, #7]
    1f6e:	b12c      	cbz	r4, 1f7c <uarte_nrfx_configure+0x24>
    1f70:	2c01      	cmp	r4, #1
    1f72:	d11d      	bne.n	1fb0 <uarte_nrfx_configure+0x58>
	case UART_CFG_FLOW_CTRL_NONE:
		uarte_cfg.hwfc = NRF_UARTE_HWFC_DISABLED;
		break;
	case UART_CFG_FLOW_CTRL_RTS_CTS:
		if (IS_HWFC_PINS_USED(get_dev_config(dev)->flags)) {
    1f74:	6843      	ldr	r3, [r0, #4]
    1f76:	685b      	ldr	r3, [r3, #4]
    1f78:	079b      	lsls	r3, r3, #30
    1f7a:	d019      	beq.n	1fb0 <uarte_nrfx_configure+0x58>
	}

#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
    1f7c:	790a      	ldrb	r2, [r1, #4]
    1f7e:	b112      	cbz	r2, 1f86 <uarte_nrfx_configure+0x2e>
    1f80:	2a02      	cmp	r2, #2
    1f82:	d115      	bne.n	1fb0 <uarte_nrfx_configure+0x58>
	case UART_CFG_PARITY_NONE:
		uarte_cfg.parity = NRF_UARTE_PARITY_EXCLUDED;
		break;
	case UART_CFG_PARITY_EVEN:
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
    1f84:	220e      	movs	r2, #14
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
    1f86:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    1f88:	6845      	ldr	r5, [r0, #4]
	switch (baudrate) {
    1f8a:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    1f8e:	682d      	ldr	r5, [r5, #0]
	switch (baudrate) {
    1f90:	d065      	beq.n	205e <uarte_nrfx_configure+0x106>
    1f92:	d82d      	bhi.n	1ff0 <uarte_nrfx_configure+0x98>
    1f94:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    1f98:	d064      	beq.n	2064 <uarte_nrfx_configure+0x10c>
    1f9a:	d816      	bhi.n	1fca <uarte_nrfx_configure+0x72>
    1f9c:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    1fa0:	d062      	beq.n	2068 <uarte_nrfx_configure+0x110>
    1fa2:	d80a      	bhi.n	1fba <uarte_nrfx_configure+0x62>
    1fa4:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    1fa8:	d061      	beq.n	206e <uarte_nrfx_configure+0x116>
    1faa:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    1fae:	d061      	beq.n	2074 <uarte_nrfx_configure+0x11c>
    1fb0:	f06f 0085 	mvn.w	r0, #133	; 0x85
    1fb4:	e052      	b.n	205c <uarte_nrfx_configure+0x104>
	switch (cfg->stop_bits) {
    1fb6:	2600      	movs	r6, #0
    1fb8:	e7d5      	b.n	1f66 <uarte_nrfx_configure+0xe>
	switch (baudrate) {
    1fba:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    1fbe:	d05c      	beq.n	207a <uarte_nrfx_configure+0x122>
    1fc0:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    1fc4:	d1f4      	bne.n	1fb0 <uarte_nrfx_configure+0x58>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    1fc6:	4b37      	ldr	r3, [pc, #220]	; (20a4 <uarte_nrfx_configure+0x14c>)
    1fc8:	e03c      	b.n	2044 <uarte_nrfx_configure+0xec>
	switch (baudrate) {
    1fca:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    1fce:	d057      	beq.n	2080 <uarte_nrfx_configure+0x128>
    1fd0:	d807      	bhi.n	1fe2 <uarte_nrfx_configure+0x8a>
    1fd2:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    1fd6:	d055      	beq.n	2084 <uarte_nrfx_configure+0x12c>
    1fd8:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    1fdc:	d1e8      	bne.n	1fb0 <uarte_nrfx_configure+0x58>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    1fde:	4b32      	ldr	r3, [pc, #200]	; (20a8 <uarte_nrfx_configure+0x150>)
    1fe0:	e030      	b.n	2044 <uarte_nrfx_configure+0xec>
	switch (baudrate) {
    1fe2:	f647 2712 	movw	r7, #31250	; 0x7a12
    1fe6:	42bb      	cmp	r3, r7
    1fe8:	d1e2      	bne.n	1fb0 <uarte_nrfx_configure+0x58>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    1fea:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    1fee:	e029      	b.n	2044 <uarte_nrfx_configure+0xec>
	switch (baudrate) {
    1ff0:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    1ff4:	d048      	beq.n	2088 <uarte_nrfx_configure+0x130>
    1ff6:	d813      	bhi.n	2020 <uarte_nrfx_configure+0xc8>
    1ff8:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    1ffc:	d047      	beq.n	208e <uarte_nrfx_configure+0x136>
    1ffe:	d809      	bhi.n	2014 <uarte_nrfx_configure+0xbc>
    2000:	f64d 27c0 	movw	r7, #56000	; 0xdac0
    2004:	42bb      	cmp	r3, r7
    2006:	d044      	beq.n	2092 <uarte_nrfx_configure+0x13a>
    2008:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    200c:	d1d0      	bne.n	1fb0 <uarte_nrfx_configure+0x58>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    200e:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    2012:	e017      	b.n	2044 <uarte_nrfx_configure+0xec>
	switch (baudrate) {
    2014:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    2018:	d1ca      	bne.n	1fb0 <uarte_nrfx_configure+0x58>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    201a:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    201e:	e011      	b.n	2044 <uarte_nrfx_configure+0xec>
	switch (baudrate) {
    2020:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    2024:	d038      	beq.n	2098 <uarte_nrfx_configure+0x140>
    2026:	d808      	bhi.n	203a <uarte_nrfx_configure+0xe2>
    2028:	4f20      	ldr	r7, [pc, #128]	; (20ac <uarte_nrfx_configure+0x154>)
    202a:	42bb      	cmp	r3, r7
    202c:	d037      	beq.n	209e <uarte_nrfx_configure+0x146>
    202e:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    2032:	d1bd      	bne.n	1fb0 <uarte_nrfx_configure+0x58>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    2034:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    2038:	e004      	b.n	2044 <uarte_nrfx_configure+0xec>
	switch (baudrate) {
    203a:	4f1d      	ldr	r7, [pc, #116]	; (20b0 <uarte_nrfx_configure+0x158>)
    203c:	42bb      	cmp	r3, r7
    203e:	d1b7      	bne.n	1fb0 <uarte_nrfx_configure+0x58>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    2040:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    2044:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
		return -ENOTSUP;
	}

	nrf_uarte_configure(get_uarte_instance(dev), &uarte_cfg);

	get_dev_data(dev)->uart_config = *cfg;
    2048:	6903      	ldr	r3, [r0, #16]
    204a:	c903      	ldmia	r1, {r0, r1}
                    | (uint32_t)p_cfg->hwfc;
    204c:	4334      	orrs	r4, r6
    204e:	4322      	orrs	r2, r4
    2050:	3304      	adds	r3, #4
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    2052:	f8c5 256c 	str.w	r2, [r5, #1388]	; 0x56c
    2056:	e883 0003 	stmia.w	r3, {r0, r1}

	return 0;
    205a:	2000      	movs	r0, #0
}
    205c:	bdf0      	pop	{r4, r5, r6, r7, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    205e:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    2062:	e7ef      	b.n	2044 <uarte_nrfx_configure+0xec>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    2064:	4b13      	ldr	r3, [pc, #76]	; (20b4 <uarte_nrfx_configure+0x15c>)
    2066:	e7ed      	b.n	2044 <uarte_nrfx_configure+0xec>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    2068:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    206c:	e7ea      	b.n	2044 <uarte_nrfx_configure+0xec>
		nrf_baudrate = 0x00014000;
    206e:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    2072:	e7e7      	b.n	2044 <uarte_nrfx_configure+0xec>
	switch (baudrate) {
    2074:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    2078:	e7e4      	b.n	2044 <uarte_nrfx_configure+0xec>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    207a:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    207e:	e7e1      	b.n	2044 <uarte_nrfx_configure+0xec>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    2080:	4b0d      	ldr	r3, [pc, #52]	; (20b8 <uarte_nrfx_configure+0x160>)
    2082:	e7df      	b.n	2044 <uarte_nrfx_configure+0xec>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    2084:	4b0d      	ldr	r3, [pc, #52]	; (20bc <uarte_nrfx_configure+0x164>)
    2086:	e7dd      	b.n	2044 <uarte_nrfx_configure+0xec>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    2088:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    208c:	e7da      	b.n	2044 <uarte_nrfx_configure+0xec>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    208e:	4b0c      	ldr	r3, [pc, #48]	; (20c0 <uarte_nrfx_configure+0x168>)
    2090:	e7d8      	b.n	2044 <uarte_nrfx_configure+0xec>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    2092:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    2096:	e7d5      	b.n	2044 <uarte_nrfx_configure+0xec>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    2098:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    209c:	e7d2      	b.n	2044 <uarte_nrfx_configure+0xec>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    209e:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    20a2:	e7cf      	b.n	2044 <uarte_nrfx_configure+0xec>
    20a4:	0013b000 	.word	0x0013b000
    20a8:	004ea000 	.word	0x004ea000
    20ac:	0003d090 	.word	0x0003d090
    20b0:	000f4240 	.word	0x000f4240
    20b4:	00275000 	.word	0x00275000
    20b8:	0075c000 	.word	0x0075c000
    20bc:	003af000 	.word	0x003af000
    20c0:	013a9000 	.word	0x013a9000

000020c4 <nrf_gpio_cfg_input>:
    *p_pin = pin_number & 0x1F;
    20c4:	f000 021f 	and.w	r2, r0, #31
    return pin_number >> 5;
    20c8:	0940      	lsrs	r0, r0, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    20ca:	2801      	cmp	r0, #1
        case 1: return NRF_P1;
    20cc:	4b04      	ldr	r3, [pc, #16]	; (20e0 <nrf_gpio_cfg_input+0x1c>)
    reg->PIN_CNF[pin_number] = cnf;
    20ce:	f502 72e0 	add.w	r2, r2, #448	; 0x1c0
        case 1: return NRF_P1;
    20d2:	bf18      	it	ne
    20d4:	f04f 43a0 	movne.w	r3, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    20d8:	0089      	lsls	r1, r1, #2
    reg->PIN_CNF[pin_number] = cnf;
    20da:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    20de:	4770      	bx	lr
    20e0:	50000300 	.word	0x50000300

000020e4 <uarte_nrfx_poll_out>:
 *
 * @param dev UARTE device struct
 * @param c Character to send
 */
static void uarte_nrfx_poll_out(const struct device *dev, unsigned char c)
{
    20e4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	struct uarte_nrfx_data *data = get_dev_data(dev);
    20e6:	6906      	ldr	r6, [r0, #16]
{
    20e8:	4605      	mov	r5, r0
    20ea:	460f      	mov	r7, r1
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    20ec:	f002 fb8a 	bl	4804 <k_is_in_isr>
    20f0:	b910      	cbnz	r0, 20f8 <uarte_nrfx_poll_out+0x14>
	return !z_sys_post_kernel;
    20f2:	4b2c      	ldr	r3, [pc, #176]	; (21a4 <uarte_nrfx_poll_out+0xc0>)
	int key;

	if (isr_mode) {
    20f4:	781b      	ldrb	r3, [r3, #0]
    20f6:	b983      	cbnz	r3, 211a <uarte_nrfx_poll_out+0x36>
	__asm__ volatile(
    20f8:	f04f 0320 	mov.w	r3, #32
    20fc:	f3ef 8411 	mrs	r4, BASEPRI
    2100:	f383 8812 	msr	BASEPRI_MAX, r3
    2104:	f3bf 8f6f 	isb	sy
		while (1) {
			key = irq_lock();
			if (is_tx_ready(dev)) {
    2108:	4628      	mov	r0, r5
    210a:	f002 fac8 	bl	469e <is_tx_ready>
    210e:	bb28      	cbnz	r0, 215c <uarte_nrfx_poll_out+0x78>
	__asm__ volatile(
    2110:	f384 8811 	msr	BASEPRI, r4
    2114:	f3bf 8f6f 	isb	sy
}
    2118:	e7ee      	b.n	20f8 <uarte_nrfx_poll_out+0x14>
{
    211a:	2464      	movs	r4, #100	; 0x64
		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    211c:	4628      	mov	r0, r5
    211e:	f002 fabe 	bl	469e <is_tx_ready>
    2122:	b970      	cbnz	r0, 2142 <uarte_nrfx_poll_out+0x5e>
    2124:	2001      	movs	r0, #1
    2126:	f002 faf0 	bl	470a <nrfx_busy_wait>
    212a:	3c01      	subs	r4, #1
    212c:	d1f6      	bne.n	211c <uarte_nrfx_poll_out+0x38>
    212e:	2100      	movs	r1, #0
    2130:	2021      	movs	r0, #33	; 0x21
    2132:	f001 fbc7 	bl	38c4 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    2136:	e7f0      	b.n	211a <uarte_nrfx_poll_out+0x36>
	__asm__ volatile(
    2138:	f384 8811 	msr	BASEPRI, r4
    213c:	f3bf 8f6f 	isb	sy
}
    2140:	e7f5      	b.n	212e <uarte_nrfx_poll_out+0x4a>
	__asm__ volatile(
    2142:	f04f 0320 	mov.w	r3, #32
    2146:	f3ef 8411 	mrs	r4, BASEPRI
    214a:	f383 8812 	msr	BASEPRI_MAX, r3
    214e:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    2152:	4628      	mov	r0, r5
    2154:	f002 faa3 	bl	469e <is_tx_ready>
    2158:	2800      	cmp	r0, #0
    215a:	d0ed      	beq.n	2138 <uarte_nrfx_poll_out+0x54>
		}
	} else {
		key = wait_tx_ready(dev);
	}

	data->char_out = c;
    215c:	f806 7f10 	strb.w	r7, [r6, #16]!
	const struct uarte_nrfx_config *config = get_dev_config(dev);
    2160:	6869      	ldr	r1, [r5, #4]
	return config->uarte_regs;
    2162:	680b      	ldr	r3, [r1, #0]
NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t  const * p_buffer,
                                               size_t           length)
{
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    p_reg->TXD.MAXCNT = length;
    2164:	2201      	movs	r2, #1
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    2166:	f8c3 6544 	str.w	r6, [r3, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    216a:	f8c3 2548 	str.w	r2, [r3, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    216e:	2200      	movs	r2, #0
    2170:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    2174:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    2178:	f8c3 2158 	str.w	r2, [r3, #344]	; 0x158
    217c:	f8d3 2158 	ldr.w	r2, [r3, #344]	; 0x158
	if (get_dev_config(dev)->flags & UARTE_CFG_FLAG_LOW_POWER) {
    2180:	684a      	ldr	r2, [r1, #4]
    2182:	06d2      	lsls	r2, r2, #27
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    2184:	bf41      	itttt	mi
    2186:	2208      	movmi	r2, #8
    2188:	f8c3 2500 	strmi.w	r2, [r3, #1280]	; 0x500
    p_reg->INTENSET = mask;
    218c:	f44f 0280 	movmi.w	r2, #4194304	; 0x400000
    2190:	f8c3 2304 	strmi.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2194:	2201      	movs	r2, #1
    2196:	609a      	str	r2, [r3, #8]
	__asm__ volatile(
    2198:	f384 8811 	msr	BASEPRI, r4
    219c:	f3bf 8f6f 	isb	sy
	tx_start(dev, &data->char_out, 1);

	irq_unlock(key);
}
    21a0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    21a2:	bf00      	nop
    21a4:	20000d96 	.word	0x20000d96

000021a8 <nrf_gpio_cfg_output>:
    *p_pin = pin_number & 0x1F;
    21a8:	f000 021f 	and.w	r2, r0, #31
    return pin_number >> 5;
    21ac:	0940      	lsrs	r0, r0, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    21ae:	2801      	cmp	r0, #1
        case 1: return NRF_P1;
    21b0:	4b04      	ldr	r3, [pc, #16]	; (21c4 <nrf_gpio_cfg_output+0x1c>)
    reg->PIN_CNF[pin_number] = cnf;
    21b2:	f502 72e0 	add.w	r2, r2, #448	; 0x1c0
        case 1: return NRF_P1;
    21b6:	bf18      	it	ne
    21b8:	f04f 43a0 	movne.w	r3, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    21bc:	2103      	movs	r1, #3
    21be:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    21c2:	4770      	bx	lr
    21c4:	50000300 	.word	0x50000300

000021c8 <nrf_gpio_pin_set>:
    *p_pin = pin_number & 0x1F;
    21c8:	f000 011f 	and.w	r1, r0, #31
    return pin_number >> 5;
    21cc:	0940      	lsrs	r0, r0, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    21ce:	2801      	cmp	r0, #1
        case 1: return NRF_P1;
    21d0:	4b04      	ldr	r3, [pc, #16]	; (21e4 <nrf_gpio_pin_set+0x1c>)
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    21d2:	f04f 0201 	mov.w	r2, #1
        case 1: return NRF_P1;
    21d6:	bf18      	it	ne
    21d8:	f04f 43a0 	movne.w	r3, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    21dc:	408a      	lsls	r2, r1
    p_reg->OUTSET = set_mask;
    21de:	f8c3 2508 	str.w	r2, [r3, #1288]	; 0x508
}
    21e2:	4770      	bx	lr
    21e4:	50000300 	.word	0x50000300

000021e8 <uarte_1_init>:
#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
#endif

#ifdef CONFIG_UART_1_NRF_UARTE
UART_NRF_UARTE_DEVICE(1);
    21e8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    21ea:	2101      	movs	r1, #1
    21ec:	4607      	mov	r7, r0
    21ee:	2200      	movs	r2, #0
    21f0:	2028      	movs	r0, #40	; 0x28
    21f2:	f7fe ff99 	bl	1128 <z_arm_irq_priority_set>
    21f6:	2028      	movs	r0, #40	; 0x28
    21f8:	f7fe ff78 	bl	10ec <arch_irq_enable>
	const struct uarte_nrfx_config *config = get_dev_config(dev);
    21fc:	687d      	ldr	r5, [r7, #4]
	struct uarte_nrfx_data *data = get_dev_data(dev);
    21fe:	693e      	ldr	r6, [r7, #16]
	return config->uarte_regs;
    2200:	682c      	ldr	r4, [r5, #0]
        nrf_gpio_pin_set(pin_number);
    2202:	68a8      	ldr	r0, [r5, #8]
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    2204:	2300      	movs	r3, #0
    2206:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
	data->dev = dev;
    220a:	6037      	str	r7, [r6, #0]
    220c:	f7ff ffdc 	bl	21c8 <nrf_gpio_pin_set>
	nrf_gpio_cfg_output(cfg->pseltxd);
    2210:	68a8      	ldr	r0, [r5, #8]
    2212:	f7ff ffc9 	bl	21a8 <nrf_gpio_cfg_output>
	if (cfg->pselrxd !=  NRF_UARTE_PSEL_DISCONNECTED) {
    2216:	68e8      	ldr	r0, [r5, #12]
    2218:	1c41      	adds	r1, r0, #1
    221a:	d002      	beq.n	2222 <uarte_1_init+0x3a>
		nrf_gpio_cfg_input(cfg->pselrxd, cfg->rxd_pull);
    221c:	7e29      	ldrb	r1, [r5, #24]
    221e:	f7ff ff51 	bl	20c4 <nrf_gpio_cfg_input>
	nrf_uarte_txrx_pins_set(uarte, cfg->pseltxd, cfg->pselrxd);
    2222:	e9d5 2302 	ldrd	r2, r3, [r5, #8]
	if (cfg->pselcts != NRF_UARTE_PSEL_DISCONNECTED) {
    2226:	6928      	ldr	r0, [r5, #16]
    p_reg->PSEL.TXD = pseltxd;
    2228:	f8c4 250c 	str.w	r2, [r4, #1292]	; 0x50c
    222c:	1c42      	adds	r2, r0, #1
    p_reg->PSEL.RXD = pselrxd;
    222e:	f8c4 3514 	str.w	r3, [r4, #1300]	; 0x514
    2232:	d002      	beq.n	223a <uarte_1_init+0x52>
		nrf_gpio_cfg_input(cfg->pselcts, cfg->cts_pull);
    2234:	7e69      	ldrb	r1, [r5, #25]
    2236:	f7ff ff45 	bl	20c4 <nrf_gpio_cfg_input>
	if (cfg->pselrts != NRF_UARTE_PSEL_DISCONNECTED) {
    223a:	6968      	ldr	r0, [r5, #20]
    223c:	1c43      	adds	r3, r0, #1
    223e:	d004      	beq.n	224a <uarte_1_init+0x62>
    2240:	f7ff ffc2 	bl	21c8 <nrf_gpio_pin_set>
		nrf_gpio_cfg_output(cfg->pselrts);
    2244:	6968      	ldr	r0, [r5, #20]
    2246:	f7ff ffaf 	bl	21a8 <nrf_gpio_cfg_output>
	nrf_uarte_hwfc_pins_set(uarte, cfg->pselrts, cfg->pselcts);
    224a:	e9d5 3204 	ldrd	r3, r2, [r5, #16]
	err = uarte_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
    224e:	6939      	ldr	r1, [r7, #16]
    p_reg->PSEL.RTS = pselrts;
    2250:	f8c4 2508 	str.w	r2, [r4, #1288]	; 0x508
    2254:	4638      	mov	r0, r7
    p_reg->PSEL.CTS = pselcts;
    2256:	f8c4 3510 	str.w	r3, [r4, #1296]	; 0x510
    225a:	3104      	adds	r1, #4
    225c:	f7ff fe7c 	bl	1f58 <uarte_nrfx_configure>
	if (err) {
    2260:	4607      	mov	r7, r0
    2262:	2800      	cmp	r0, #0
    2264:	d145      	bne.n	22f2 <uarte_1_init+0x10a>
	    cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX) {
    2266:	686b      	ldr	r3, [r5, #4]
	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
    2268:	0719      	lsls	r1, r3, #28
    226a:	d519      	bpl.n	22a0 <uarte_1_init+0xb8>
	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    226c:	f106 0012 	add.w	r0, r6, #18
    2270:	f000 fcc0 	bl	2bf4 <nrfx_ppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    2274:	4b21      	ldr	r3, [pc, #132]	; (22fc <uarte_1_init+0x114>)
    2276:	4298      	cmp	r0, r3
    2278:	d13d      	bne.n	22f6 <uarte_1_init+0x10e>
	nrfx_gppi_channel_endpoints_setup(data->ppi_ch_endtx,
    227a:	7cb0      	ldrb	r0, [r6, #18]
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    227c:	00c3      	lsls	r3, r0, #3
    227e:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    2282:	f503 33f8 	add.w	r3, r3, #126976	; 0x1f000
    return (uint32_t)p_reg + (uint32_t)task;
    2286:	f104 020c 	add.w	r2, r4, #12
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    228a:	f504 7190 	add.w	r1, r4, #288	; 0x120
NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type *    p_reg,
                                                      nrf_ppi_channel_t channel,
                                                      uint32_t          eep,
                                                      uint32_t          tep)
{
    p_reg->CH[(uint32_t) channel].EEP = eep;
    228e:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    p_reg->CH[(uint32_t) channel].TEP = tep;
    2292:	f8c3 2514 	str.w	r2, [r3, #1300]	; 0x514
    p_reg->CHENSET = mask;
    2296:	4a1a      	ldr	r2, [pc, #104]	; (2300 <uarte_1_init+0x118>)
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    2298:	2301      	movs	r3, #1
    229a:	4083      	lsls	r3, r0
    229c:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    22a0:	2308      	movs	r3, #8
    22a2:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
		if (cfg->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
    22a6:	68eb      	ldr	r3, [r5, #12]
    22a8:	3301      	adds	r3, #1
    22aa:	d00c      	beq.n	22c6 <uarte_1_init+0xde>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    22ac:	2300      	movs	r3, #0
    22ae:	f8c4 3110 	str.w	r3, [r4, #272]	; 0x110
    22b2:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110
			nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
    22b6:	f106 0311 	add.w	r3, r6, #17

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    22ba:	f8c4 3534 	str.w	r3, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    22be:	2301      	movs	r3, #1
    22c0:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    22c4:	6023      	str	r3, [r4, #0]
	if (!(cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX)) {
    22c6:	686b      	ldr	r3, [r5, #4]
    22c8:	071a      	lsls	r2, r3, #28
    p_reg->INTENSET = mask;
    22ca:	bf5c      	itt	pl
    22cc:	f44f 7280 	movpl.w	r2, #256	; 0x100
    22d0:	f8c4 2304 	strpl.w	r2, [r4, #772]	; 0x304
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    22d4:	06db      	lsls	r3, r3, #27
    22d6:	bf44      	itt	mi
    22d8:	f44f 0380 	movmi.w	r3, #4194304	; 0x400000
    22dc:	f8c4 3304 	strmi.w	r3, [r4, #772]	; 0x304
	nrf_uarte_tx_buffer_set(uarte, &data->char_out, 0);
    22e0:	3610      	adds	r6, #16
    p_reg->TXD.MAXCNT = length;
    22e2:	2300      	movs	r3, #0
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    22e4:	f8c4 6544 	str.w	r6, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    22e8:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    22ec:	2301      	movs	r3, #1
    22ee:	60a3      	str	r3, [r4, #8]
    22f0:	60e3      	str	r3, [r4, #12]
UART_NRF_UARTE_DEVICE(1);
    22f2:	4638      	mov	r0, r7
    22f4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		return -EIO;
    22f6:	f06f 0704 	mvn.w	r7, #4
UART_NRF_UARTE_DEVICE(1);
    22fa:	e7fa      	b.n	22f2 <uarte_1_init+0x10a>
    22fc:	0bad0000 	.word	0x0bad0000
    2300:	4001f000 	.word	0x4001f000

00002304 <sys_clock_timeout_handler>:
static void sys_clock_timeout_handler(int32_t chan,
				      uint64_t expire_time,
				      void *user_data)
{
	uint32_t cc_value = absolute_time_to_cc(expire_time);
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2304:	4919      	ldr	r1, [pc, #100]	; (236c <sys_clock_timeout_handler+0x68>)
{
    2306:	b570      	push	{r4, r5, r6, lr}
    2308:	4604      	mov	r4, r0
	return absolute_time & COUNTER_MAX;
    230a:	f022 467f 	bic.w	r6, r2, #4278190080	; 0xff000000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    230e:	6808      	ldr	r0, [r1, #0]

	last_count += dticks * CYC_PER_TICK;
    2310:	e9c1 2300 	strd	r2, r3, [r1]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    2314:	f5a6 1300 	sub.w	r3, r6, #2097152	; 0x200000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2318:	1a10      	subs	r0, r2, r0
	if (in_anchor_range(cc_value)) {
    231a:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    231e:	f04f 0500 	mov.w	r5, #0
    2322:	d20a      	bcs.n	233a <sys_clock_timeout_handler+0x36>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    2324:	4b12      	ldr	r3, [pc, #72]	; (2370 <sys_clock_timeout_handler+0x6c>)
    2326:	6819      	ldr	r1, [r3, #0]
    2328:	060a      	lsls	r2, r1, #24
    232a:	0a0b      	lsrs	r3, r1, #8
    232c:	1992      	adds	r2, r2, r6
    232e:	4911      	ldr	r1, [pc, #68]	; (2374 <sys_clock_timeout_handler+0x70>)
    2330:	f143 0300 	adc.w	r3, r3, #0
    2334:	e9c1 2300 	strd	r2, r3, [r1]
		return true;
    2338:	2501      	movs	r5, #1
		 */
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    233a:	f001 fc27 	bl	3b8c <sys_clock_announce>
    p_reg->CC[ch] = cc_val;
}

NRF_STATIC_INLINE  uint32_t nrf_rtc_cc_get(NRF_RTC_Type const * p_reg, uint32_t ch)
{
    return p_reg->CC[ch];
    233e:	00a3      	lsls	r3, r4, #2
    2340:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    2344:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    2348:	f8d3 2540 	ldr.w	r2, [r3, #1344]	; 0x540
			   (int32_t)dticks : (dticks > 0));

	if (cc_value == get_comparator(chan)) {
    234c:	42b2      	cmp	r2, r6
    234e:	d10b      	bne.n	2368 <sys_clock_timeout_handler+0x64>
		 * If anchor was updated we can enable same CC value to trigger
		 * interrupt after full cycle. Else set event in anchor update
		 * range. Since anchor was not updated we know that it's very
		 * far from mid point so setting is done without any protection.
		 */
		if (!anchor_updated) {
    2350:	b91d      	cbnz	r5, 235a <sys_clock_timeout_handler+0x56>
    p_reg->CC[ch] = cc_val;
    2352:	f44f 0200 	mov.w	r2, #8388608	; 0x800000
    2356:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
    235a:	4b07      	ldr	r3, [pc, #28]	; (2378 <sys_clock_timeout_handler+0x74>)
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    235c:	f44f 3080 	mov.w	r0, #65536	; 0x10000
    2360:	fa00 f404 	lsl.w	r4, r0, r4
    2364:	f8c3 4344 	str.w	r4, [r3, #836]	; 0x344
			set_comparator(chan, COUNTER_HALF_SPAN);
		}
		event_enable(chan);
	}
}
    2368:	bd70      	pop	{r4, r5, r6, pc}
    236a:	bf00      	nop
    236c:	20000128 	.word	0x20000128
    2370:	2000081c 	.word	0x2000081c
    2374:	20000110 	.word	0x20000110
    2378:	40011000 	.word	0x40011000

0000237c <compare_int_lock>:
{
    237c:	b510      	push	{r4, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    237e:	2301      	movs	r3, #1
    2380:	4083      	lsls	r3, r0
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    2382:	4a11      	ldr	r2, [pc, #68]	; (23c8 <compare_int_lock+0x4c>)
    2384:	f3bf 8f5b 	dmb	ish
    2388:	43dc      	mvns	r4, r3
    238a:	e852 1f00 	ldrex	r1, [r2]
    238e:	ea01 0c04 	and.w	ip, r1, r4
    2392:	e842 ce00 	strex	lr, ip, [r2]
    2396:	f1be 0f00 	cmp.w	lr, #0
    239a:	d1f6      	bne.n	238a <compare_int_lock+0xe>
    239c:	f3bf 8f5b 	dmb	ish
	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    23a0:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    23a4:	fa02 f000 	lsl.w	r0, r2, r0
    p_reg->INTENCLR = mask;
    23a8:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    23ac:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
    23b0:	f8c2 0308 	str.w	r0, [r2, #776]	; 0x308
  __ASM volatile ("dmb 0xF":::"memory");
    23b4:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    23b8:	f3bf 8f6f 	isb	sy
	return prev & BIT(chan);
    23bc:	420b      	tst	r3, r1
}
    23be:	bf14      	ite	ne
    23c0:	2001      	movne	r0, #1
    23c2:	2000      	moveq	r0, #0
    23c4:	bd10      	pop	{r4, pc}
    23c6:	bf00      	nop
    23c8:	20000818 	.word	0x20000818

000023cc <compare_int_unlock.part.0>:
		atomic_or(&int_mask, BIT(chan));
    23cc:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    23ce:	4a12      	ldr	r2, [pc, #72]	; (2418 <compare_int_unlock.part.0+0x4c>)
    23d0:	f3bf 8f5b 	dmb	ish
    23d4:	4083      	lsls	r3, r0
    23d6:	e852 1f00 	ldrex	r1, [r2]
    23da:	4319      	orrs	r1, r3
    23dc:	e842 1c00 	strex	ip, r1, [r2]
    23e0:	f1bc 0f00 	cmp.w	ip, #0
    23e4:	d1f7      	bne.n	23d6 <compare_int_unlock.part.0+0xa>
    23e6:	f3bf 8f5b 	dmb	ish
    p_reg->INTENSET = mask;
    23ea:	4a0c      	ldr	r2, [pc, #48]	; (241c <compare_int_unlock.part.0+0x50>)
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    23ec:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    23f0:	4083      	lsls	r3, r0
    23f2:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    23f6:	4b0a      	ldr	r3, [pc, #40]	; (2420 <compare_int_unlock.part.0+0x54>)
    23f8:	f3bf 8f5b 	dmb	ish
    23fc:	681b      	ldr	r3, [r3, #0]
    23fe:	f3bf 8f5b 	dmb	ish
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    2402:	fa23 f000 	lsr.w	r0, r3, r0
    2406:	07c3      	lsls	r3, r0, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2408:	bf42      	ittt	mi
    240a:	4b06      	ldrmi	r3, [pc, #24]	; (2424 <compare_int_unlock.part.0+0x58>)
    240c:	f44f 3200 	movmi.w	r2, #131072	; 0x20000
    2410:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
}
    2414:	4770      	bx	lr
    2416:	bf00      	nop
    2418:	20000818 	.word	0x20000818
    241c:	40011000 	.word	0x40011000
    2420:	20000814 	.word	0x20000814
    2424:	e000e100 	.word	0xe000e100

00002428 <z_nrf_rtc_timer_read>:
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    2428:	4b0d      	ldr	r3, [pc, #52]	; (2460 <z_nrf_rtc_timer_read+0x38>)
    242a:	681b      	ldr	r3, [r3, #0]
    242c:	0a19      	lsrs	r1, r3, #8
    242e:	0618      	lsls	r0, r3, #24
  __ASM volatile ("dmb 0xF":::"memory");
    2430:	f3bf 8f5f 	dmb	sy
     return p_reg->COUNTER;
    2434:	4b0b      	ldr	r3, [pc, #44]	; (2464 <z_nrf_rtc_timer_read+0x3c>)
    2436:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	val += cntr;
    243a:	18c0      	adds	r0, r0, r3
    243c:	f141 0100 	adc.w	r1, r1, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    2440:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    2444:	d20a      	bcs.n	245c <z_nrf_rtc_timer_read+0x34>
		if (val < anchor) {
    2446:	4b08      	ldr	r3, [pc, #32]	; (2468 <z_nrf_rtc_timer_read+0x40>)
    2448:	e9d3 2300 	ldrd	r2, r3, [r3]
    244c:	4299      	cmp	r1, r3
    244e:	bf08      	it	eq
    2450:	4290      	cmpeq	r0, r2
    2452:	d203      	bcs.n	245c <z_nrf_rtc_timer_read+0x34>
			val += COUNTER_SPAN;
    2454:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    2458:	f141 0100 	adc.w	r1, r1, #0
}
    245c:	4770      	bx	lr
    245e:	bf00      	nop
    2460:	2000081c 	.word	0x2000081c
    2464:	40011000 	.word	0x40011000
    2468:	20000110 	.word	0x20000110

0000246c <compare_set>:
{
    246c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    2470:	b085      	sub	sp, #20
    2472:	4616      	mov	r6, r2
    2474:	461f      	mov	r7, r3
    2476:	4605      	mov	r5, r0
	key = compare_int_lock(chan);
    2478:	f7ff ff80 	bl	237c <compare_int_lock>
    247c:	9001      	str	r0, [sp, #4]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    247e:	f7ff ffd3 	bl	2428 <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    2482:	42b9      	cmp	r1, r7
    2484:	bf08      	it	eq
    2486:	42b0      	cmpeq	r0, r6
    2488:	d27f      	bcs.n	258a <compare_set+0x11e>
		if (target_time - curr_time > COUNTER_SPAN) {
    248a:	ebb6 0800 	subs.w	r8, r6, r0
    248e:	eb67 0901 	sbc.w	r9, r7, r1
    2492:	2300      	movs	r3, #0
    2494:	f04f 7280 	mov.w	r2, #16777216	; 0x1000000
    2498:	454b      	cmp	r3, r9
    249a:	bf08      	it	eq
    249c:	4542      	cmpeq	r2, r8
    249e:	f0c0 8085 	bcc.w	25ac <compare_set+0x140>
		if (target_time != cc_data[chan].target_time) {
    24a2:	4b44      	ldr	r3, [pc, #272]	; (25b4 <compare_set+0x148>)
    24a4:	eb03 1305 	add.w	r3, r3, r5, lsl #4
    24a8:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
    24ac:	429f      	cmp	r7, r3
    24ae:	bf08      	it	eq
    24b0:	4296      	cmpeq	r6, r2
    24b2:	d054      	beq.n	255e <compare_set+0xf2>
    24b4:	ea4f 0985 	mov.w	r9, r5, lsl #2
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    24b8:	f44f 3b80 	mov.w	fp, #65536	; 0x10000
    24bc:	f109 4980 	add.w	r9, r9, #1073741824	; 0x40000000
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    24c0:	f105 0850 	add.w	r8, r5, #80	; 0x50
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    24c4:	fa0b f205 	lsl.w	r2, fp, r5
    24c8:	f509 3988 	add.w	r9, r9, #69632	; 0x11000
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    24cc:	ea4f 0888 	mov.w	r8, r8, lsl #2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    24d0:	fa1f f888 	uxth.w	r8, r8
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    24d4:	9202      	str	r2, [sp, #8]
     return p_reg->COUNTER;
    24d6:	4a38      	ldr	r2, [pc, #224]	; (25b8 <compare_set+0x14c>)
    return p_reg->CC[ch];
    24d8:	f8d9 0540 	ldr.w	r0, [r9, #1344]	; 0x540
	return absolute_time & COUNTER_MAX;
    24dc:	f026 437f 	bic.w	r3, r6, #4278190080	; 0xff000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    24e0:	f108 4880 	add.w	r8, r8, #1073741824	; 0x40000000
    24e4:	f508 3888 	add.w	r8, r8, #69632	; 0x11000
	uint32_t cc_val = abs_val & COUNTER_MAX;
    24e8:	461c      	mov	r4, r3
    24ea:	4693      	mov	fp, r2
     return p_reg->COUNTER;
    24ec:	f8d2 a504 	ldr.w	sl, [r2, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    24f0:	eba0 000a 	sub.w	r0, r0, sl
    24f4:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    24f8:	f02a 417f 	bic.w	r1, sl, #4278190080	; 0xff000000
		if (counter_sub(prev_cc, now) == 1) {
    24fc:	2801      	cmp	r0, #1
    p_reg->CC[ch] = cc_val;
    24fe:	f8c9 1540 	str.w	r1, [r9, #1344]	; 0x540
    2502:	d105      	bne.n	2510 <compare_set+0xa4>
    2504:	9303      	str	r3, [sp, #12]
	z_impl_k_busy_wait(usec_to_wait);
    2506:	2013      	movs	r0, #19
    2508:	f002 fa7d 	bl	4a06 <z_impl_k_busy_wait>
    250c:	4a2a      	ldr	r2, [pc, #168]	; (25b8 <compare_set+0x14c>)
    250e:	9b03      	ldr	r3, [sp, #12]
    p_reg->EVTENSET = mask;
    2510:	9902      	ldr	r1, [sp, #8]
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    2512:	f10a 0c02 	add.w	ip, sl, #2
	return (a - b) & COUNTER_MAX;
    2516:	eba4 000c 	sub.w	r0, r4, ip
    251a:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
			cc_val = now + 2;
    251e:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    2522:	bf88      	it	hi
    2524:	4664      	movhi	r4, ip
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2526:	2000      	movs	r0, #0
    2528:	f8c8 0000 	str.w	r0, [r8]
    252c:	f8d8 0000 	ldr.w	r0, [r8]
    p_reg->EVTENSET = mask;
    2530:	f8cb 1344 	str.w	r1, [fp, #836]	; 0x344
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    2534:	f024 407f 	bic.w	r0, r4, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    2538:	f8c9 0540 	str.w	r0, [r9, #1344]	; 0x540
     return p_reg->COUNTER;
    253c:	f8db 0504 	ldr.w	r0, [fp, #1284]	; 0x504
		 (counter_sub(cc_val, now2 + 2) > COUNTER_HALF_SPAN));
    2540:	4582      	cmp	sl, r0
    2542:	d006      	beq.n	2552 <compare_set+0xe6>
	return (a - b) & COUNTER_MAX;
    2544:	1a20      	subs	r0, r4, r0
    2546:	3802      	subs	r0, #2
    2548:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	} while ((now2 != now) &&
    254c:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    2550:	d819      	bhi.n	2586 <compare_set+0x11a>
	return (a - b) & COUNTER_MAX;
    2552:	1ae4      	subs	r4, r4, r3
    2554:	f024 447f 	bic.w	r4, r4, #4278190080	; 0xff000000
			target_time += counter_sub(cc_set, cc_value);
    2558:	1932      	adds	r2, r6, r4
    255a:	f147 0300 	adc.w	r3, r7, #0
	cc_data[chan].target_time = target_time;
    255e:	4c15      	ldr	r4, [pc, #84]	; (25b4 <compare_set+0x148>)
    2560:	0129      	lsls	r1, r5, #4
    2562:	eb04 1005 	add.w	r0, r4, r5, lsl #4
    2566:	e9c0 2302 	strd	r2, r3, [r0, #8]
	cc_data[chan].callback = handler;
    256a:	9a0e      	ldr	r2, [sp, #56]	; 0x38
	cc_data[chan].user_context = user_data;
    256c:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
	cc_data[chan].callback = handler;
    256e:	5062      	str	r2, [r4, r1]
	cc_data[chan].user_context = user_data;
    2570:	6043      	str	r3, [r0, #4]
	return ret;
    2572:	2400      	movs	r4, #0
	if (key) {
    2574:	9b01      	ldr	r3, [sp, #4]
    2576:	b113      	cbz	r3, 257e <compare_set+0x112>
    2578:	4628      	mov	r0, r5
    257a:	f7ff ff27 	bl	23cc <compare_int_unlock.part.0>
}
    257e:	4620      	mov	r0, r4
    2580:	b005      	add	sp, #20
    2582:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    2586:	4620      	mov	r0, r4
    2588:	e7b0      	b.n	24ec <compare_set+0x80>
		atomic_or(&force_isr_mask, BIT(chan));
    258a:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    258c:	4a0b      	ldr	r2, [pc, #44]	; (25bc <compare_set+0x150>)
    258e:	f3bf 8f5b 	dmb	ish
    2592:	40ab      	lsls	r3, r5
    2594:	e852 1f00 	ldrex	r1, [r2]
    2598:	4319      	orrs	r1, r3
    259a:	e842 1000 	strex	r0, r1, [r2]
    259e:	2800      	cmp	r0, #0
    25a0:	d1f8      	bne.n	2594 <compare_set+0x128>
    25a2:	f3bf 8f5b 	dmb	ish
    25a6:	4632      	mov	r2, r6
    25a8:	463b      	mov	r3, r7
    25aa:	e7d8      	b.n	255e <compare_set+0xf2>
			return -EINVAL;
    25ac:	f06f 0415 	mvn.w	r4, #21
    25b0:	e7e0      	b.n	2574 <compare_set+0x108>
    25b2:	bf00      	nop
    25b4:	20000118 	.word	0x20000118
    25b8:	40011000 	.word	0x40011000
    25bc:	20000814 	.word	0x20000814

000025c0 <rtc_nrf_isr>:
 * probably better abstract that at some point (e.g. query and reset
 * it by pointer at runtime, maybe?) so we don't have this leaky
 * symbol.
 */
void rtc_nrf_isr(const void *arg)
{
    25c0:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    return p_reg->INTENSET & mask;
    25c4:	4c34      	ldr	r4, [pc, #208]	; (2698 <rtc_nrf_isr+0xd8>)
    25c6:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	ARG_UNUSED(arg);

	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    25ca:	079a      	lsls	r2, r3, #30
    25cc:	d509      	bpl.n	25e2 <rtc_nrf_isr+0x22>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    25ce:	4b33      	ldr	r3, [pc, #204]	; (269c <rtc_nrf_isr+0xdc>)
    25d0:	681a      	ldr	r2, [r3, #0]
    25d2:	b132      	cbz	r2, 25e2 <rtc_nrf_isr+0x22>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    25d4:	2200      	movs	r2, #0
    25d6:	601a      	str	r2, [r3, #0]
	    nrf_rtc_event_check(RTC, NRF_RTC_EVENT_OVERFLOW)) {
		nrf_rtc_event_clear(RTC, NRF_RTC_EVENT_OVERFLOW);
		overflow_cnt++;
    25d8:	4a31      	ldr	r2, [pc, #196]	; (26a0 <rtc_nrf_isr+0xe0>)
    25da:	681b      	ldr	r3, [r3, #0]
    25dc:	6813      	ldr	r3, [r2, #0]
    25de:	3301      	adds	r3, #1
    25e0:	6013      	str	r3, [r2, #0]
	__asm__ volatile(
    25e2:	f04f 0320 	mov.w	r3, #32
    25e6:	f3ef 8211 	mrs	r2, BASEPRI
    25ea:	f383 8812 	msr	BASEPRI_MAX, r3
    25ee:	f3bf 8f6f 	isb	sy
    return p_reg->INTENSET & mask;
    25f2:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    25f6:	03db      	lsls	r3, r3, #15
    25f8:	d512      	bpl.n	2620 <rtc_nrf_isr+0x60>
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    25fa:	f3bf 8f5b 	dmb	ish
    25fe:	4b29      	ldr	r3, [pc, #164]	; (26a4 <rtc_nrf_isr+0xe4>)
    2600:	e853 1f00 	ldrex	r1, [r3]
    2604:	f021 0001 	bic.w	r0, r1, #1
    2608:	e843 0600 	strex	r6, r0, [r3]
    260c:	2e00      	cmp	r6, #0
    260e:	d1f7      	bne.n	2600 <rtc_nrf_isr+0x40>
    2610:	f3bf 8f5b 	dmb	ish
    2614:	4b24      	ldr	r3, [pc, #144]	; (26a8 <rtc_nrf_isr+0xe8>)
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    2616:	2900      	cmp	r1, #0
    2618:	d136      	bne.n	2688 <rtc_nrf_isr+0xc8>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    261a:	6819      	ldr	r1, [r3, #0]
		if (result) {
    261c:	2900      	cmp	r1, #0
    261e:	d133      	bne.n	2688 <rtc_nrf_isr+0xc8>
{
    2620:	2300      	movs	r3, #0
	__asm__ volatile(
    2622:	f382 8811 	msr	BASEPRI, r2
    2626:	f3bf 8f6f 	isb	sy
	if (channel_processing_check_and_clear(chan)) {
    262a:	b353      	cbz	r3, 2682 <rtc_nrf_isr+0xc2>
		curr_time = z_nrf_rtc_timer_read();
    262c:	f7ff fefc 	bl	2428 <z_nrf_rtc_timer_read>
    2630:	4606      	mov	r6, r0
	__asm__ volatile(
    2632:	f04f 0320 	mov.w	r3, #32
    2636:	f3ef 8011 	mrs	r0, BASEPRI
    263a:	f383 8812 	msr	BASEPRI_MAX, r3
    263e:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    2642:	4b1a      	ldr	r3, [pc, #104]	; (26ac <rtc_nrf_isr+0xec>)
    2644:	e9d3 8902 	ldrd	r8, r9, [r3, #8]
		if (curr_time >= expire_time) {
    2648:	4549      	cmp	r1, r9
    264a:	bf08      	it	eq
    264c:	4546      	cmpeq	r6, r8
    264e:	f04f 0200 	mov.w	r2, #0
    2652:	d31e      	bcc.n	2692 <rtc_nrf_isr+0xd2>
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    2654:	f04f 36ff 	mov.w	r6, #4294967295
    2658:	f04f 37ff 	mov.w	r7, #4294967295
			user_context = cc_data[chan].user_context;
    265c:	e9d3 1500 	ldrd	r1, r5, [r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    2660:	e9c3 6702 	strd	r6, r7, [r3, #8]
			cc_data[chan].callback = NULL;
    2664:	601a      	str	r2, [r3, #0]
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    2666:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    266a:	f8c4 3348 	str.w	r3, [r4, #840]	; 0x348
	__asm__ volatile(
    266e:	f380 8811 	msr	BASEPRI, r0
    2672:	f3bf 8f6f 	isb	sy
		if (handler) {
    2676:	b121      	cbz	r1, 2682 <rtc_nrf_isr+0xc2>
			handler(chan, expire_time, user_context);
    2678:	9500      	str	r5, [sp, #0]
    267a:	4642      	mov	r2, r8
    267c:	464b      	mov	r3, r9
    267e:	2000      	movs	r0, #0
    2680:	4788      	blx	r1
	}

	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		process_channel(chan);
	}
}
    2682:	b003      	add	sp, #12
    2684:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2688:	2100      	movs	r1, #0
    268a:	6019      	str	r1, [r3, #0]
    268c:	681b      	ldr	r3, [r3, #0]
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    268e:	2301      	movs	r3, #1
}
    2690:	e7c7      	b.n	2622 <rtc_nrf_isr+0x62>
		z_nrf_rtc_timer_compare_handler_t handler = NULL;
    2692:	4611      	mov	r1, r2
    2694:	e7eb      	b.n	266e <rtc_nrf_isr+0xae>
    2696:	bf00      	nop
    2698:	40011000 	.word	0x40011000
    269c:	40011104 	.word	0x40011104
    26a0:	2000081c 	.word	0x2000081c
    26a4:	20000814 	.word	0x20000814
    26a8:	40011140 	.word	0x40011140
    26ac:	20000118 	.word	0x20000118

000026b0 <sys_clock_driver_init>:

	atomic_or(&alloc_mask, BIT(chan));
}

int sys_clock_driver_init(const struct device *dev)
{
    26b0:	b573      	push	{r0, r1, r4, r5, r6, lr}
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    26b2:	4b1a      	ldr	r3, [pc, #104]	; (271c <sys_clock_driver_init+0x6c>)
    p_reg->PRESCALER = val;
    26b4:	4d1a      	ldr	r5, [pc, #104]	; (2720 <sys_clock_driver_init+0x70>)
    26b6:	2400      	movs	r4, #0
    26b8:	f04f 30ff 	mov.w	r0, #4294967295
    26bc:	f04f 31ff 	mov.w	r1, #4294967295
    26c0:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    26c4:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    26c8:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    26cc:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    26d0:	4b14      	ldr	r3, [pc, #80]	; (2724 <sys_clock_driver_init+0x74>)
    26d2:	2602      	movs	r6, #2
    26d4:	f44f 3200 	mov.w	r2, #131072	; 0x20000

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    26d8:	2101      	movs	r1, #1
    26da:	f8c5 6304 	str.w	r6, [r5, #772]	; 0x304
    26de:	2011      	movs	r0, #17
    26e0:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    26e4:	4622      	mov	r2, r4
    26e6:	f7fe fd1f 	bl	1128 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    26ea:	2011      	movs	r0, #17
    26ec:	f7fe fcfe 	bl	10ec <arch_irq_enable>
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    26f0:	4a0d      	ldr	r2, [pc, #52]	; (2728 <sys_clock_driver_init+0x78>)
    p_reg->INTENSET = mask;
    26f2:	f8c5 6304 	str.w	r6, [r5, #772]	; 0x304
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    26f6:	2301      	movs	r3, #1
    26f8:	6013      	str	r3, [r2, #0]

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    26fa:	4a0c      	ldr	r2, [pc, #48]	; (272c <sys_clock_driver_init+0x7c>)
    26fc:	602b      	str	r3, [r5, #0]
    26fe:	6013      	str	r3, [r2, #0]

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
				(COUNTER_HALF_SPAN - 1) :
				(counter() + CYC_PER_TICK);

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    2700:	4b0b      	ldr	r3, [pc, #44]	; (2730 <sys_clock_driver_init+0x80>)
    2702:	4a0c      	ldr	r2, [pc, #48]	; (2734 <sys_clock_driver_init+0x84>)
    2704:	9300      	str	r3, [sp, #0]
    2706:	9401      	str	r4, [sp, #4]
    2708:	2300      	movs	r3, #0
    270a:	4620      	mov	r0, r4
    270c:	f7ff feae 	bl	246c <compare_set>

	z_nrf_clock_control_lf_on(mode);
    2710:	4630      	mov	r0, r6
    2712:	f7ff f993 	bl	1a3c <z_nrf_clock_control_lf_on>

	return 0;
}
    2716:	4620      	mov	r0, r4
    2718:	b002      	add	sp, #8
    271a:	bd70      	pop	{r4, r5, r6, pc}
    271c:	20000118 	.word	0x20000118
    2720:	40011000 	.word	0x40011000
    2724:	e000e100 	.word	0xe000e100
    2728:	40011008 	.word	0x40011008
    272c:	20000818 	.word	0x20000818
    2730:	00002305 	.word	0x00002305
    2734:	007fffff 	.word	0x007fffff

00002738 <sys_clock_set_timeout>:

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return;
	}

	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    2738:	4b14      	ldr	r3, [pc, #80]	; (278c <sys_clock_set_timeout+0x54>)
{
    273a:	b513      	push	{r0, r1, r4, lr}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    273c:	f1b0 3fff 	cmp.w	r0, #4294967295
    2740:	bf08      	it	eq
    2742:	4618      	moveq	r0, r3
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    2744:	1e44      	subs	r4, r0, #1
    2746:	2c00      	cmp	r4, #0
    2748:	dd1e      	ble.n	2788 <sys_clock_set_timeout+0x50>
    274a:	429c      	cmp	r4, r3
    274c:	bfa8      	it	ge
    274e:	461c      	movge	r4, r3

	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    2750:	f7ff fe6a 	bl	2428 <z_nrf_rtc_timer_read>
    2754:	4b0e      	ldr	r3, [pc, #56]	; (2790 <sys_clock_set_timeout+0x58>)
		cyc = MAX_CYCLES;
	}

	uint64_t target_time = cyc + last_count;

	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    2756:	490f      	ldr	r1, [pc, #60]	; (2794 <sys_clock_set_timeout+0x5c>)
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    2758:	e9d3 2300 	ldrd	r2, r3, [r3]
    275c:	1a80      	subs	r0, r0, r2
		ticks = 0;
    275e:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    2762:	bf28      	it	cs
    2764:	2400      	movcs	r4, #0
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    2766:	3001      	adds	r0, #1
    2768:	4404      	add	r4, r0
	uint64_t target_time = cyc + last_count;
    276a:	4808      	ldr	r0, [pc, #32]	; (278c <sys_clock_set_timeout+0x54>)
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    276c:	9100      	str	r1, [sp, #0]
	uint64_t target_time = cyc + last_count;
    276e:	4284      	cmp	r4, r0
    2770:	bf28      	it	cs
    2772:	4604      	movcs	r4, r0
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    2774:	1912      	adds	r2, r2, r4
    2776:	f04f 0000 	mov.w	r0, #0
    277a:	9001      	str	r0, [sp, #4]
    277c:	f143 0300 	adc.w	r3, r3, #0
    2780:	f7ff fe74 	bl	246c <compare_set>
}
    2784:	b002      	add	sp, #8
    2786:	bd10      	pop	{r4, pc}
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    2788:	2400      	movs	r4, #0
    278a:	e7e1      	b.n	2750 <sys_clock_set_timeout+0x18>
    278c:	007fffff 	.word	0x007fffff
    2790:	20000128 	.word	0x20000128
    2794:	00002305 	.word	0x00002305

00002798 <sys_clock_elapsed>:

uint32_t sys_clock_elapsed(void)
{
    2798:	b508      	push	{r3, lr}
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return 0;
	}

	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    279a:	f7ff fe45 	bl	2428 <z_nrf_rtc_timer_read>
    279e:	4b02      	ldr	r3, [pc, #8]	; (27a8 <sys_clock_elapsed+0x10>)
    27a0:	681b      	ldr	r3, [r3, #0]
}
    27a2:	1ac0      	subs	r0, r0, r3
    27a4:	bd08      	pop	{r3, pc}
    27a6:	bf00      	nop
    27a8:	20000128 	.word	0x20000128

000027ac <nrf52_errata_136>:
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    27ac:	4b03      	ldr	r3, [pc, #12]	; (27bc <nrf52_errata_136+0x10>)
                        return true;
                }
            }
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    27ae:	6818      	ldr	r0, [r3, #0]
                }
            }
        #endif
        return false;
    #endif
}
    27b0:	f1a0 0308 	sub.w	r3, r0, #8
    27b4:	4258      	negs	r0, r3
    27b6:	4158      	adcs	r0, r3
    27b8:	4770      	bx	lr
    27ba:	bf00      	nop
    27bc:	10000130 	.word	0x10000130

000027c0 <nrf52_errata_103>:
{
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    27c0:	4b06      	ldr	r3, [pc, #24]	; (27dc <nrf52_errata_103+0x1c>)
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    27c2:	681b      	ldr	r3, [r3, #0]
    27c4:	2b08      	cmp	r3, #8
    27c6:	d106      	bne.n	27d6 <nrf52_errata_103+0x16>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    27c8:	4b05      	ldr	r3, [pc, #20]	; (27e0 <nrf52_errata_103+0x20>)
    27ca:	681b      	ldr	r3, [r3, #0]
            {
                switch(var2)
    27cc:	2b05      	cmp	r3, #5
    27ce:	d802      	bhi.n	27d6 <nrf52_errata_103+0x16>
    27d0:	4a04      	ldr	r2, [pc, #16]	; (27e4 <nrf52_errata_103+0x24>)
    27d2:	5cd0      	ldrb	r0, [r2, r3]
    27d4:	4770      	bx	lr
                    default:
                        return false;
                }
            }
        #endif
        return false;
    27d6:	2000      	movs	r0, #0
    #endif
}
    27d8:	4770      	bx	lr
    27da:	bf00      	nop
    27dc:	10000130 	.word	0x10000130
    27e0:	10000134 	.word	0x10000134
    27e4:	00004ee8 	.word	0x00004ee8

000027e8 <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    27e8:	4a02      	ldr	r2, [pc, #8]	; (27f4 <nvmc_wait+0xc>)
    27ea:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    27ee:	2b00      	cmp	r3, #0
    27f0:	d0fb      	beq.n	27ea <nvmc_wait+0x2>
}
    27f2:	4770      	bx	lr
    27f4:	4001e000 	.word	0x4001e000

000027f8 <SystemInit>:
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
}

void SystemInit(void)
{
    27f8:	b510      	push	{r4, lr}
    #endif

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
    27fa:	f7ff ffd7 	bl	27ac <nrf52_errata_136>
    27fe:	b140      	cbz	r0, 2812 <SystemInit+0x1a>
            NRF_CLOCK->EVENTS_DONE = 0;
    2800:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2804:	2200      	movs	r2, #0
    2806:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    280a:	f8c3 2110 	str.w	r2, [r3, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    280e:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    #endif

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
    2812:	f7ff ffcb 	bl	27ac <nrf52_errata_136>
    2816:	2800      	cmp	r0, #0
    2818:	d046      	beq.n	28a8 <SystemInit+0xb0>
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    281a:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
    281e:	4b5b      	ldr	r3, [pc, #364]	; (298c <SystemInit+0x194>)
    2820:	f8d2 1404 	ldr.w	r1, [r2, #1028]	; 0x404
    2824:	f8c3 1520 	str.w	r1, [r3, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    2828:	f8d2 1408 	ldr.w	r1, [r2, #1032]	; 0x408
    282c:	f8c3 1524 	str.w	r1, [r3, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    2830:	f8d2 140c 	ldr.w	r1, [r2, #1036]	; 0x40c
    2834:	f8c3 1528 	str.w	r1, [r3, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    2838:	f8d2 1410 	ldr.w	r1, [r2, #1040]	; 0x410
    283c:	f8c3 152c 	str.w	r1, [r3, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    2840:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
    2844:	f8c3 1530 	str.w	r1, [r3, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    2848:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    284c:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    2850:	f8d2 141c 	ldr.w	r1, [r2, #1052]	; 0x41c
    2854:	f8c3 1540 	str.w	r1, [r3, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    2858:	f8d2 1420 	ldr.w	r1, [r2, #1056]	; 0x420
    285c:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    2860:	f8d2 1424 	ldr.w	r1, [r2, #1060]	; 0x424
    2864:	f8c3 1548 	str.w	r1, [r3, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    2868:	f8d2 1428 	ldr.w	r1, [r2, #1064]	; 0x428
    286c:	f8c3 154c 	str.w	r1, [r3, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    2870:	f8d2 142c 	ldr.w	r1, [r2, #1068]	; 0x42c
    2874:	f8c3 1550 	str.w	r1, [r3, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    2878:	f8d2 1430 	ldr.w	r1, [r2, #1072]	; 0x430
    287c:	f8c3 1554 	str.w	r1, [r3, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    2880:	f8d2 1434 	ldr.w	r1, [r2, #1076]	; 0x434
    2884:	f8c3 1560 	str.w	r1, [r3, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    2888:	f8d2 1438 	ldr.w	r1, [r2, #1080]	; 0x438
    288c:	f8c3 1564 	str.w	r1, [r3, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    2890:	f8d2 143c 	ldr.w	r1, [r2, #1084]	; 0x43c
    2894:	f8c3 1568 	str.w	r1, [r3, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    2898:	f8d2 1440 	ldr.w	r1, [r2, #1088]	; 0x440
    289c:	f8c3 156c 	str.w	r1, [r3, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    28a0:	f8d2 2444 	ldr.w	r2, [r2, #1092]	; 0x444
    28a4:	f8c3 2570 	str.w	r2, [r3, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_98_ENABLE_WORKAROUND
        /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_98()){
    28a8:	f7ff ff8a 	bl	27c0 <nrf52_errata_103>
    28ac:	b110      	cbz	r0, 28b4 <SystemInit+0xbc>
            *(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
    28ae:	4b38      	ldr	r3, [pc, #224]	; (2990 <SystemInit+0x198>)
    28b0:	4a38      	ldr	r2, [pc, #224]	; (2994 <SystemInit+0x19c>)
    28b2:	601a      	str	r2, [r3, #0]
    #endif

    #if NRF52_ERRATA_103_ENABLE_WORKAROUND && defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos)
        /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_103()){
    28b4:	f7ff ff84 	bl	27c0 <nrf52_errata_103>
    28b8:	b118      	cbz	r0, 28c2 <SystemInit+0xca>
            NRF_CCM->MAXPACKETSIZE = 0xFBul;
    28ba:	4b37      	ldr	r3, [pc, #220]	; (2998 <SystemInit+0x1a0>)
    28bc:	22fb      	movs	r2, #251	; 0xfb
    28be:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    #endif

    #if NRF52_ERRATA_115_ENABLE_WORKAROUND
        /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_115()){
    28c2:	f7ff ff7d 	bl	27c0 <nrf52_errata_103>
    28c6:	b148      	cbz	r0, 28dc <SystemInit+0xe4>
            *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
    28c8:	4934      	ldr	r1, [pc, #208]	; (299c <SystemInit+0x1a4>)
    28ca:	4b35      	ldr	r3, [pc, #212]	; (29a0 <SystemInit+0x1a8>)
    28cc:	680a      	ldr	r2, [r1, #0]
    28ce:	681b      	ldr	r3, [r3, #0]
    28d0:	f022 020f 	bic.w	r2, r2, #15
    28d4:	f003 030f 	and.w	r3, r3, #15
    28d8:	4313      	orrs	r3, r2
    28da:	600b      	str	r3, [r1, #0]
    #endif

    #if NRF52_ERRATA_120_ENABLE_WORKAROUND
        /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_120()){
    28dc:	f7ff ff70 	bl	27c0 <nrf52_errata_103>
    28e0:	b118      	cbz	r0, 28ea <SystemInit+0xf2>
            *(volatile uint32_t *)0x40029640ul = 0x200ul;
    28e2:	4b30      	ldr	r3, [pc, #192]	; (29a4 <SystemInit+0x1ac>)
    28e4:	f44f 7200 	mov.w	r2, #512	; 0x200
    28e8:	601a      	str	r2, [r3, #0]
    #endif

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
    28ea:	f7ff ff5f 	bl	27ac <nrf52_errata_136>
    28ee:	b148      	cbz	r0, 2904 <SystemInit+0x10c>
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    28f0:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    28f4:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    28f8:	07d2      	lsls	r2, r2, #31
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    28fa:	bf44      	itt	mi
    28fc:	f06f 0201 	mvnmi.w	r2, #1
    2900:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400
        #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2904:	4b28      	ldr	r3, [pc, #160]	; (29a8 <SystemInit+0x1b0>)
                        return true;
                }
            }
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    2906:	681b      	ldr	r3, [r3, #0]
    2908:	2b08      	cmp	r3, #8
    290a:	d10e      	bne.n	292a <SystemInit+0x132>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    290c:	4b27      	ldr	r3, [pc, #156]	; (29ac <SystemInit+0x1b4>)
    290e:	681b      	ldr	r3, [r3, #0]
            {
                switch(var2)
    2910:	2b05      	cmp	r3, #5
    2912:	d802      	bhi.n	291a <SystemInit+0x122>
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_errata_249())
    2914:	4a26      	ldr	r2, [pc, #152]	; (29b0 <SystemInit+0x1b8>)
    2916:	5cd3      	ldrb	r3, [r2, r3]
    2918:	b13b      	cbz	r3, 292a <SystemInit+0x132>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    291a:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    291e:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    2922:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2926:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    292a:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    292e:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    2932:	2a00      	cmp	r2, #0
    2934:	db03      	blt.n	293e <SystemInit+0x146>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    2936:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    293a:	2b00      	cmp	r3, #0
    293c:	da22      	bge.n	2984 <SystemInit+0x18c>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    293e:	491d      	ldr	r1, [pc, #116]	; (29b4 <SystemInit+0x1bc>)
    2940:	2301      	movs	r3, #1
    2942:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    2946:	f7ff ff4f 	bl	27e8 <nvmc_wait>
            nvmc_config(NVMC_CONFIG_WEN_Wen);
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    294a:	f04f 2010 	mov.w	r0, #268439552	; 0x10001000
    294e:	2412      	movs	r4, #18
    2950:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
            nvmc_wait();
    2954:	f7ff ff48 	bl	27e8 <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    2958:	f8c0 4204 	str.w	r4, [r0, #516]	; 0x204
            nvmc_wait();
    295c:	f7ff ff44 	bl	27e8 <nvmc_wait>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    2960:	2300      	movs	r3, #0
    2962:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    2966:	f7ff ff3f 	bl	27e8 <nvmc_wait>
  __ASM volatile ("dsb 0xF":::"memory");
    296a:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    296e:	4912      	ldr	r1, [pc, #72]	; (29b8 <SystemInit+0x1c0>)
    2970:	4b12      	ldr	r3, [pc, #72]	; (29bc <SystemInit+0x1c4>)
    2972:	68ca      	ldr	r2, [r1, #12]
    2974:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2978:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    297a:	60cb      	str	r3, [r1, #12]
    297c:	f3bf 8f4f 	dsb	sy
    __NOP();
    2980:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    2982:	e7fd      	b.n	2980 <SystemInit+0x188>
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    2984:	4b0e      	ldr	r3, [pc, #56]	; (29c0 <SystemInit+0x1c8>)
    2986:	4a0f      	ldr	r2, [pc, #60]	; (29c4 <SystemInit+0x1cc>)
    2988:	601a      	str	r2, [r3, #0]
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
}
    298a:	bd10      	pop	{r4, pc}
    298c:	4000c000 	.word	0x4000c000
    2990:	4000568c 	.word	0x4000568c
    2994:	00038148 	.word	0x00038148
    2998:	4000f000 	.word	0x4000f000
    299c:	40000ee4 	.word	0x40000ee4
    29a0:	10000258 	.word	0x10000258
    29a4:	40029640 	.word	0x40029640
    29a8:	10000130 	.word	0x10000130
    29ac:	10000134 	.word	0x10000134
    29b0:	00004ee2 	.word	0x00004ee2
    29b4:	4001e000 	.word	0x4001e000
    29b8:	e000ed00 	.word	0xe000ed00
    29bc:	05fa0004 	.word	0x05fa0004
    29c0:	2000003c 	.word	0x2000003c
    29c4:	03d09000 	.word	0x03d09000

000029c8 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    29c8:	4b04      	ldr	r3, [pc, #16]	; (29dc <nrfx_clock_init+0x14>)
    29ca:	791a      	ldrb	r2, [r3, #4]
    29cc:	b922      	cbnz	r2, 29d8 <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    29ce:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    29d0:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    29d2:	809a      	strh	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    29d4:	4802      	ldr	r0, [pc, #8]	; (29e0 <nrfx_clock_init+0x18>)
    29d6:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    29d8:	4802      	ldr	r0, [pc, #8]	; (29e4 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    29da:	4770      	bx	lr
    29dc:	20000820 	.word	0x20000820
    29e0:	0bad0000 	.word	0x0bad0000
    29e4:	0bad000c 	.word	0x0bad000c

000029e8 <nrfx_clock_start>:
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    29e8:	b110      	cbz	r0, 29f0 <nrfx_clock_start+0x8>
    29ea:	2801      	cmp	r0, #1
    29ec:	d020      	beq.n	2a30 <nrfx_clock_start+0x48>
    29ee:	4770      	bx	lr
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    29f0:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    29f4:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    29f8:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
    29fc:	f411 3f80 	tst.w	r1, #65536	; 0x10000
    2a00:	4619      	mov	r1, r3
    2a02:	d011      	beq.n	2a28 <nrfx_clock_start+0x40>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    2a04:	f002 0203 	and.w	r2, r2, #3
    {
        case NRF_CLOCK_DOMAIN_LFCLK:
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
            {
                nrf_clock_lfclk_t lfclksrc;
                if (nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc) &&
    2a08:	2a01      	cmp	r2, #1
    2a0a:	d10d      	bne.n	2a28 <nrfx_clock_start+0x40>
    p_reg->LFCLKSRC = (uint32_t)(source);
    2a0c:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a10:	4b0c      	ldr	r3, [pc, #48]	; (2a44 <nrfx_clock_start+0x5c>)
    2a12:	2200      	movs	r2, #0
    2a14:	601a      	str	r2, [r3, #0]
    2a16:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    2a18:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2a1c:	2202      	movs	r2, #2
    2a1e:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2a22:	2201      	movs	r2, #1
    2a24:	609a      	str	r2, [r3, #8]
}
    2a26:	4770      	bx	lr
    p_reg->LFCLKSRC = (uint32_t)(source);
    2a28:	2300      	movs	r3, #0
    2a2a:	f8c1 3518 	str.w	r3, [r1, #1304]	; 0x518
}
    2a2e:	e7ef      	b.n	2a10 <nrfx_clock_start+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a30:	4b05      	ldr	r3, [pc, #20]	; (2a48 <nrfx_clock_start+0x60>)
    2a32:	2200      	movs	r2, #0
    2a34:	601a      	str	r2, [r3, #0]
    2a36:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    2a38:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2a3c:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2a40:	6018      	str	r0, [r3, #0]
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    2a42:	4770      	bx	lr
    2a44:	40000104 	.word	0x40000104
    2a48:	40000100 	.word	0x40000100

00002a4c <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
    2a4c:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    2a4e:	b110      	cbz	r0, 2a56 <nrfx_clock_stop+0xa>
    2a50:	2801      	cmp	r0, #1
    2a52:	d018      	beq.n	2a86 <nrfx_clock_stop+0x3a>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    2a54:	bd38      	pop	{r3, r4, r5, pc}
    p_reg->INTENCLR = mask;
    2a56:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2a5a:	2202      	movs	r2, #2
    2a5c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a60:	4a18      	ldr	r2, [pc, #96]	; (2ac4 <nrfx_clock_stop+0x78>)
    2a62:	6010      	str	r0, [r2, #0]
    2a64:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2a66:	4a18      	ldr	r2, [pc, #96]	; (2ac8 <nrfx_clock_stop+0x7c>)
    2a68:	2101      	movs	r1, #1
    2a6a:	6011      	str	r1, [r2, #0]
    2a6c:	f242 7510 	movw	r5, #10000	; 0x2710
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2a70:	461c      	mov	r4, r3
    2a72:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
    2a76:	03db      	lsls	r3, r3, #15
    2a78:	d5ec      	bpl.n	2a54 <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    2a7a:	2001      	movs	r0, #1
    2a7c:	f001 fe45 	bl	470a <nrfx_busy_wait>
    2a80:	3d01      	subs	r5, #1
    2a82:	d1f6      	bne.n	2a72 <nrfx_clock_stop+0x26>
    2a84:	e7e6      	b.n	2a54 <nrfx_clock_stop+0x8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a86:	4b11      	ldr	r3, [pc, #68]	; (2acc <nrfx_clock_stop+0x80>)
    p_reg->INTENCLR = mask;
    2a88:	f04f 4480 	mov.w	r4, #1073741824	; 0x40000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a8c:	2200      	movs	r2, #0
    p_reg->INTENCLR = mask;
    2a8e:	f8c4 0308 	str.w	r0, [r4, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a92:	601a      	str	r2, [r3, #0]
    2a94:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2a96:	4b0e      	ldr	r3, [pc, #56]	; (2ad0 <nrfx_clock_stop+0x84>)
    2a98:	f242 7510 	movw	r5, #10000	; 0x2710
    2a9c:	6018      	str	r0, [r3, #0]
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2a9e:	f8d4 340c 	ldr.w	r3, [r4, #1036]	; 0x40c
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2aa2:	f8d4 240c 	ldr.w	r2, [r4, #1036]	; 0x40c
    2aa6:	03d2      	lsls	r2, r2, #15
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2aa8:	f003 0301 	and.w	r3, r3, #1
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2aac:	d505      	bpl.n	2aba <nrfx_clock_stop+0x6e>
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
    2aae:	b123      	cbz	r3, 2aba <nrfx_clock_stop+0x6e>
    2ab0:	2001      	movs	r0, #1
    2ab2:	f001 fe2a 	bl	470a <nrfx_busy_wait>
    2ab6:	3d01      	subs	r5, #1
    2ab8:	d1f1      	bne.n	2a9e <nrfx_clock_stop+0x52>
            m_clock_cb.hfclk_started = false;
    2aba:	4b06      	ldr	r3, [pc, #24]	; (2ad4 <nrfx_clock_stop+0x88>)
    2abc:	2200      	movs	r2, #0
    2abe:	715a      	strb	r2, [r3, #5]
    2ac0:	e7c8      	b.n	2a54 <nrfx_clock_stop+0x8>
    2ac2:	bf00      	nop
    2ac4:	40000104 	.word	0x40000104
    2ac8:	4000000c 	.word	0x4000000c
    2acc:	40000100 	.word	0x40000100
    2ad0:	40000004 	.word	0x40000004
    2ad4:	20000820 	.word	0x20000820

00002ad8 <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2ad8:	4b16      	ldr	r3, [pc, #88]	; (2b34 <nrfx_power_clock_irq_handler+0x5c>)
    2ada:	681a      	ldr	r2, [r3, #0]
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    2adc:	b510      	push	{r4, lr}
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    2ade:	b16a      	cbz	r2, 2afc <nrfx_power_clock_irq_handler+0x24>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2ae0:	2200      	movs	r2, #0
    2ae2:	601a      	str	r2, [r3, #0]
    2ae4:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    2ae6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2aea:	2201      	movs	r2, #1
    2aec:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);

#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
        if (!m_clock_cb.hfclk_started)
    2af0:	4b11      	ldr	r3, [pc, #68]	; (2b38 <nrfx_power_clock_irq_handler+0x60>)
    2af2:	7958      	ldrb	r0, [r3, #5]
    2af4:	b910      	cbnz	r0, 2afc <nrfx_power_clock_irq_handler+0x24>
        {
            m_clock_cb.hfclk_started = true;
    2af6:	715a      	strb	r2, [r3, #5]
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    2af8:	681b      	ldr	r3, [r3, #0]
    2afa:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2afc:	4b0f      	ldr	r3, [pc, #60]	; (2b3c <nrfx_power_clock_irq_handler+0x64>)
    2afe:	681a      	ldr	r2, [r3, #0]
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    2b00:	b172      	cbz	r2, 2b20 <nrfx_power_clock_irq_handler+0x48>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2b02:	2200      	movs	r2, #0
    2b04:	601a      	str	r2, [r3, #0]
    2b06:	681b      	ldr	r3, [r3, #0]
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    2b08:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2b0c:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2b10:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    2b14:	0792      	lsls	r2, r2, #30
    2b16:	d104      	bne.n	2b22 <nrfx_power_clock_irq_handler+0x4a>
    p_reg->LFCLKSRC = (uint32_t)(source);
    2b18:	2201      	movs	r2, #1
    2b1a:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2b1e:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    2b20:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    2b22:	2202      	movs	r2, #2
    2b24:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    2b28:	4b03      	ldr	r3, [pc, #12]	; (2b38 <nrfx_power_clock_irq_handler+0x60>)
}
    2b2a:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    2b2e:	681b      	ldr	r3, [r3, #0]
    2b30:	2001      	movs	r0, #1
    2b32:	4718      	bx	r3
    2b34:	40000100 	.word	0x40000100
    2b38:	20000820 	.word	0x20000820
    2b3c:	40000104 	.word	0x40000104

00002b40 <nrfx_gpiote_channel_free>:
    return m_cb.allocated_channels_mask & (1UL << index);
}

static bool is_app_channel(uint8_t index)
{
    return NRFX_GPIOTE_APP_CHANNELS_MASK & (1UL << index);
    2b40:	2301      	movs	r3, #1
    2b42:	fa03 f000 	lsl.w	r0, r3, r0

nrfx_err_t nrfx_gpiote_channel_free(uint8_t channel)
{
    nrfx_err_t err_code = NRFX_SUCCESS;

    if (!is_app_channel(channel))
    2b46:	f010 0fff 	tst.w	r0, #255	; 0xff
    2b4a:	d012      	beq.n	2b72 <nrfx_gpiote_channel_free+0x32>
	__asm__ volatile(
    2b4c:	f04f 0320 	mov.w	r3, #32
    2b50:	f3ef 8111 	mrs	r1, BASEPRI
    2b54:	f383 8812 	msr	BASEPRI_MAX, r3
    2b58:	f3bf 8f6f 	isb	sy
    m_cb.allocated_channels_mask &= ~(1UL << index);
    2b5c:	4a06      	ldr	r2, [pc, #24]	; (2b78 <nrfx_gpiote_channel_free+0x38>)
    2b5e:	6dd3      	ldr	r3, [r2, #92]	; 0x5c
    2b60:	ea23 0000 	bic.w	r0, r3, r0
    2b64:	65d0      	str	r0, [r2, #92]	; 0x5c
	__asm__ volatile(
    2b66:	f381 8811 	msr	BASEPRI, r1
    2b6a:	f3bf 8f6f 	isb	sy
    2b6e:	4803      	ldr	r0, [pc, #12]	; (2b7c <nrfx_gpiote_channel_free+0x3c>)
    2b70:	4770      	bx	lr
    {
        err_code = NRFX_ERROR_INVALID_PARAM;
    2b72:	4803      	ldr	r0, [pc, #12]	; (2b80 <nrfx_gpiote_channel_free+0x40>)
        NRFX_CRITICAL_SECTION_EXIT();
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    2b74:	4770      	bx	lr
    2b76:	bf00      	nop
    2b78:	20000828 	.word	0x20000828
    2b7c:	0bad0000 	.word	0x0bad0000
    2b80:	0bad0004 	.word	0x0bad0004

00002b84 <nrfx_gpiote_channel_alloc>:

nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel)
{
    2b84:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    2b88:	4605      	mov	r5, r0
    return m_cb.allocated_channels_mask & (1UL << index);
    2b8a:	f8df e060 	ldr.w	lr, [pc, #96]	; 2bec <nrfx_gpiote_channel_alloc+0x68>
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    2b8e:	4816      	ldr	r0, [pc, #88]	; (2be8 <nrfx_gpiote_channel_alloc+0x64>)
        NRFX_CRITICAL_SECTION_ENTER();
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
        {
            channel_allocated_set(ch_idx);
            *p_channel = ch_idx;
            err_code = NRFX_SUCCESS;
    2b90:	f8df 805c 	ldr.w	r8, [pc, #92]	; 2bf0 <nrfx_gpiote_channel_alloc+0x6c>
{
    2b94:	2400      	movs	r4, #0
    uint32_t mask = NRFX_GPIOTE_APP_CHANNELS_MASK;
    2b96:	22ff      	movs	r2, #255	; 0xff
    return m_cb.allocated_channels_mask & (1UL << index);
    2b98:	2601      	movs	r6, #1
    2b9a:	b2e3      	uxtb	r3, r4
	__asm__ volatile(
    2b9c:	f04f 0120 	mov.w	r1, #32
    2ba0:	f3ef 8c11 	mrs	ip, BASEPRI
    2ba4:	f381 8812 	msr	BASEPRI_MAX, r1
    2ba8:	f3bf 8f6f 	isb	sy
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
    2bac:	fa22 f103 	lsr.w	r1, r2, r3
    2bb0:	07c9      	lsls	r1, r1, #31
    2bb2:	d50a      	bpl.n	2bca <nrfx_gpiote_channel_alloc+0x46>
    return m_cb.allocated_channels_mask & (1UL << index);
    2bb4:	f8de 105c 	ldr.w	r1, [lr, #92]	; 0x5c
    2bb8:	fa06 f703 	lsl.w	r7, r6, r3
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
    2bbc:	4239      	tst	r1, r7
    m_cb.allocated_channels_mask |= (1UL << index);
    2bbe:	bf01      	itttt	eq
    2bc0:	4339      	orreq	r1, r7
    2bc2:	f8ce 105c 	streq.w	r1, [lr, #92]	; 0x5c
            err_code = NRFX_SUCCESS;
    2bc6:	4640      	moveq	r0, r8
            *p_channel = ch_idx;
    2bc8:	702b      	strbeq	r3, [r5, #0]
	__asm__ volatile(
    2bca:	f38c 8811 	msr	BASEPRI, ip
    2bce:	f3bf 8f6f 	isb	sy
        }
        NRFX_CRITICAL_SECTION_EXIT();

        if (err_code == NRFX_SUCCESS)
    2bd2:	4540      	cmp	r0, r8
    2bd4:	d005      	beq.n	2be2 <nrfx_gpiote_channel_alloc+0x5e>
        {
            NRFX_LOG_INFO("Allocated channel: %d.", ch_idx);
            break;
        }

        mask &= ~(1UL << ch_idx);
    2bd6:	fa06 f303 	lsl.w	r3, r6, r3
    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    2bda:	439a      	bics	r2, r3
    2bdc:	f104 0401 	add.w	r4, r4, #1
    2be0:	d1db      	bne.n	2b9a <nrfx_gpiote_channel_alloc+0x16>
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    2be2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    2be6:	bf00      	nop
    2be8:	0bad0002 	.word	0x0bad0002
    2bec:	20000828 	.word	0x20000828
    2bf0:	0bad0000 	.word	0x0bad0000

00002bf4 <nrfx_ppi_channel_alloc>:
    group_allocated_clr_all();
}


nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel)
{
    2bf4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    uint32_t mask = NRFX_PPI_PROG_APP_CHANNELS_MASK;
    2bf8:	4a14      	ldr	r2, [pc, #80]	; (2c4c <nrfx_ppi_channel_alloc+0x58>)
    return ((m_channels_allocated & nrfx_ppi_channel_to_mask(channel)) != 0);
    2bfa:	4e15      	ldr	r6, [pc, #84]	; (2c50 <nrfx_ppi_channel_alloc+0x5c>)
        NRFX_CRITICAL_SECTION_ENTER();
        if ((mask & nrfx_ppi_channel_to_mask(channel)) && (!is_allocated_channel(channel)))
        {
            channel_allocated_set(channel);
            *p_channel = channel;
            err_code   = NRFX_SUCCESS;
    2bfc:	4f15      	ldr	r7, [pc, #84]	; (2c54 <nrfx_ppi_channel_alloc+0x60>)
{
    2bfe:	4605      	mov	r5, r0
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    2c00:	4815      	ldr	r0, [pc, #84]	; (2c58 <nrfx_ppi_channel_alloc+0x64>)
{
    2c02:	2400      	movs	r4, #0
NRFX_STATIC_INLINE uint32_t nrfx_ppi_task_addr_group_disable_get(nrf_ppi_channel_group_t group);

#ifndef NRFX_DECLARE_ONLY
NRFX_STATIC_INLINE uint32_t nrfx_ppi_channel_to_mask(nrf_ppi_channel_t channel)
{
    return (1uL << (uint32_t) channel);
    2c04:	f04f 0e01 	mov.w	lr, #1
    2c08:	fa5f fc84 	uxtb.w	ip, r4
	__asm__ volatile(
    2c0c:	f04f 0320 	mov.w	r3, #32
    2c10:	f3ef 8811 	mrs	r8, BASEPRI
    2c14:	f383 8812 	msr	BASEPRI_MAX, r3
    2c18:	f3bf 8f6f 	isb	sy
    2c1c:	fa0e f30c 	lsl.w	r3, lr, ip
        if ((mask & nrfx_ppi_channel_to_mask(channel)) && (!is_allocated_channel(channel)))
    2c20:	4213      	tst	r3, r2
    2c22:	d007      	beq.n	2c34 <nrfx_ppi_channel_alloc+0x40>
    return ((m_channels_allocated & nrfx_ppi_channel_to_mask(channel)) != 0);
    2c24:	6831      	ldr	r1, [r6, #0]
        if ((mask & nrfx_ppi_channel_to_mask(channel)) && (!is_allocated_channel(channel)))
    2c26:	420b      	tst	r3, r1
    m_channels_allocated |= nrfx_ppi_channel_to_mask(channel);
    2c28:	bf01      	itttt	eq
    2c2a:	4319      	orreq	r1, r3
    2c2c:	6031      	streq	r1, [r6, #0]
            *p_channel = channel;
    2c2e:	f885 c000 	strbeq.w	ip, [r5]
            err_code   = NRFX_SUCCESS;
    2c32:	4638      	moveq	r0, r7
	__asm__ volatile(
    2c34:	f388 8811 	msr	BASEPRI, r8
    2c38:	f3bf 8f6f 	isb	sy
        }
        NRFX_CRITICAL_SECTION_EXIT();
        if (err_code == NRFX_SUCCESS)
    2c3c:	42b8      	cmp	r0, r7
    2c3e:	d003      	beq.n	2c48 <nrfx_ppi_channel_alloc+0x54>
    for (uint8_t ch_idx = NRF_PPI_CHANNEL0; mask != 0; ch_idx++)
    2c40:	439a      	bics	r2, r3
    2c42:	f104 0401 	add.w	r4, r4, #1
    2c46:	d1df      	bne.n	2c08 <nrfx_ppi_channel_alloc+0x14>
        mask &= ~nrfx_ppi_channel_to_mask(channel);
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    2c48:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    2c4c:	000fffff 	.word	0x000fffff
    2c50:	20000888 	.word	0x20000888
    2c54:	0bad0000 	.word	0x0bad0000
    2c58:	0bad0002 	.word	0x0bad0002

00002c5c <_DoInit>:
                      _DoInit();                                                                     \
                    }                                                                                \
                  } while (0);                                                                       \
                }

static void _DoInit(void) {
    2c5c:	b510      	push	{r4, lr}
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    2c5e:	4c14      	ldr	r4, [pc, #80]	; (2cb0 <_DoInit+0x54>)
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    2c60:	4a14      	ldr	r2, [pc, #80]	; (2cb4 <_DoInit+0x58>)
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    2c62:	4915      	ldr	r1, [pc, #84]	; (2cb8 <_DoInit+0x5c>)
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    2c64:	2303      	movs	r3, #3
    2c66:	6123      	str	r3, [r4, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    2c68:	6163      	str	r3, [r4, #20]
  p->aUp[0].pBuffer       = _acUpBuffer;
    2c6a:	4b14      	ldr	r3, [pc, #80]	; (2cbc <_DoInit+0x60>)
  p->aUp[0].sName         = "Terminal";
    2c6c:	61a2      	str	r2, [r4, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    2c6e:	61e3      	str	r3, [r4, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    2c70:	f44f 6380 	mov.w	r3, #1024	; 0x400
    2c74:	6223      	str	r3, [r4, #32]
  p->aUp[0].RdOff         = 0u;
    2c76:	2300      	movs	r3, #0
    2c78:	62a3      	str	r3, [r4, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    2c7a:	6263      	str	r3, [r4, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    2c7c:	62e3      	str	r3, [r4, #44]	; 0x2c
  p->aDown[0].sName         = "Terminal";
    2c7e:	6622      	str	r2, [r4, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    2c80:	4a0f      	ldr	r2, [pc, #60]	; (2cc0 <_DoInit+0x64>)
    2c82:	6662      	str	r2, [r4, #100]	; 0x64
  STRCPY((char*)&p->acID[7], "RTT");
    2c84:	1de0      	adds	r0, r4, #7
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    2c86:	2210      	movs	r2, #16
    2c88:	66a2      	str	r2, [r4, #104]	; 0x68
  p->aDown[0].RdOff         = 0u;
    2c8a:	6723      	str	r3, [r4, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    2c8c:	66e3      	str	r3, [r4, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    2c8e:	6763      	str	r3, [r4, #116]	; 0x74
  STRCPY((char*)&p->acID[7], "RTT");
    2c90:	f001 fb40 	bl	4314 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    2c94:	f3bf 8f5f 	dmb	sy
  STRCPY((char*)&p->acID[0], "SEGGER");
    2c98:	490a      	ldr	r1, [pc, #40]	; (2cc4 <_DoInit+0x68>)
    2c9a:	4620      	mov	r0, r4
    2c9c:	f001 fb3a 	bl	4314 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    2ca0:	f3bf 8f5f 	dmb	sy
  p->acID[6] = ' ';
    2ca4:	2320      	movs	r3, #32
    2ca6:	71a3      	strb	r3, [r4, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    2ca8:	f3bf 8f5f 	dmb	sy
}
    2cac:	bd10      	pop	{r4, pc}
    2cae:	bf00      	nop
    2cb0:	2000088c 	.word	0x2000088c
    2cb4:	00004eee 	.word	0x00004eee
    2cb8:	00004ef7 	.word	0x00004ef7
    2cbc:	20000996 	.word	0x20000996
    2cc0:	20000986 	.word	0x20000986
    2cc4:	00004efb 	.word	0x00004efb

00002cc8 <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    2cc8:	4b0e      	ldr	r3, [pc, #56]	; (2d04 <z_sys_init_run_level+0x3c>)
{
    2cca:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    2ccc:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    2cd0:	3001      	adds	r0, #1
    2cd2:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    2cd6:	42a6      	cmp	r6, r4
    2cd8:	d800      	bhi.n	2cdc <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    2cda:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    2cdc:	e9d4 3500 	ldrd	r3, r5, [r4]
    2ce0:	4628      	mov	r0, r5
    2ce2:	4798      	blx	r3
		if (dev != NULL) {
    2ce4:	b165      	cbz	r5, 2d00 <z_sys_init_run_level+0x38>
			if (rc != 0) {
    2ce6:	68eb      	ldr	r3, [r5, #12]
    2ce8:	b130      	cbz	r0, 2cf8 <z_sys_init_run_level+0x30>
				if (rc < 0) {
    2cea:	2800      	cmp	r0, #0
    2cec:	bfb8      	it	lt
    2cee:	4240      	neglt	r0, r0
				dev->state->init_res = rc;
    2cf0:	28ff      	cmp	r0, #255	; 0xff
    2cf2:	bfa8      	it	ge
    2cf4:	20ff      	movge	r0, #255	; 0xff
    2cf6:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    2cf8:	785a      	ldrb	r2, [r3, #1]
    2cfa:	f042 0201 	orr.w	r2, r2, #1
    2cfe:	705a      	strb	r2, [r3, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    2d00:	3408      	adds	r4, #8
    2d02:	e7e8      	b.n	2cd6 <z_sys_init_run_level+0xe>
    2d04:	00004d8c 	.word	0x00004d8c

00002d08 <z_impl_device_get_binding>:

const struct device *z_impl_device_get_binding(const char *name)
{
    2d08:	b570      	push	{r4, r5, r6, lr}
	const struct device *dev;

	/* A null string identifies no device.  So does an empty
	 * string.
	 */
	if ((name == NULL) || (name[0] == '\0')) {
    2d0a:	4605      	mov	r5, r0
    2d0c:	b910      	cbnz	r0, 2d14 <z_impl_device_get_binding+0xc>
		return NULL;
    2d0e:	2400      	movs	r4, #0
			return dev;
		}
	}

	return NULL;
}
    2d10:	4620      	mov	r0, r4
    2d12:	bd70      	pop	{r4, r5, r6, pc}
	if ((name == NULL) || (name[0] == '\0')) {
    2d14:	7803      	ldrb	r3, [r0, #0]
    2d16:	2b00      	cmp	r3, #0
    2d18:	d0f9      	beq.n	2d0e <z_impl_device_get_binding+0x6>
	for (dev = __device_start; dev != __device_end; dev++) {
    2d1a:	4a0f      	ldr	r2, [pc, #60]	; (2d58 <z_impl_device_get_binding+0x50>)
    2d1c:	4c0f      	ldr	r4, [pc, #60]	; (2d5c <z_impl_device_get_binding+0x54>)
    2d1e:	4616      	mov	r6, r2
    2d20:	4294      	cmp	r4, r2
    2d22:	d108      	bne.n	2d36 <z_impl_device_get_binding+0x2e>
	for (dev = __device_start; dev != __device_end; dev++) {
    2d24:	4c0d      	ldr	r4, [pc, #52]	; (2d5c <z_impl_device_get_binding+0x54>)
    2d26:	42b4      	cmp	r4, r6
    2d28:	d0f1      	beq.n	2d0e <z_impl_device_get_binding+0x6>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    2d2a:	4620      	mov	r0, r4
    2d2c:	f001 fd01 	bl	4732 <z_device_ready>
    2d30:	b950      	cbnz	r0, 2d48 <z_impl_device_get_binding+0x40>
	for (dev = __device_start; dev != __device_end; dev++) {
    2d32:	3418      	adds	r4, #24
    2d34:	e7f7      	b.n	2d26 <z_impl_device_get_binding+0x1e>
		if (z_device_ready(dev) && (dev->name == name)) {
    2d36:	4620      	mov	r0, r4
    2d38:	f001 fcfb 	bl	4732 <z_device_ready>
    2d3c:	b110      	cbz	r0, 2d44 <z_impl_device_get_binding+0x3c>
    2d3e:	6823      	ldr	r3, [r4, #0]
    2d40:	42ab      	cmp	r3, r5
    2d42:	d0e5      	beq.n	2d10 <z_impl_device_get_binding+0x8>
	for (dev = __device_start; dev != __device_end; dev++) {
    2d44:	3418      	adds	r4, #24
    2d46:	e7eb      	b.n	2d20 <z_impl_device_get_binding+0x18>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    2d48:	6821      	ldr	r1, [r4, #0]
    2d4a:	4628      	mov	r0, r5
    2d4c:	f001 fafc 	bl	4348 <strcmp>
    2d50:	2800      	cmp	r0, #0
    2d52:	d1ee      	bne.n	2d32 <z_impl_device_get_binding+0x2a>
    2d54:	e7dc      	b.n	2d10 <z_impl_device_get_binding+0x8>
    2d56:	bf00      	nop
    2d58:	00004ae8 	.word	0x00004ae8
    2d5c:	00004a70 	.word	0x00004a70

00002d60 <init_idle_thread>:
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */

#if defined(CONFIG_MULTITHREADING)
__boot_func
static void init_idle_thread(int i)
{
    2d60:	b530      	push	{r4, r5, lr}
	snprintk(tname, 8, "idle %02d", i);
#else
	char *tname = NULL;
#endif /* CONFIG_THREAD_NAME */

	z_setup_new_thread(thread, stack,
    2d62:	2300      	movs	r3, #0
{
    2d64:	b087      	sub	sp, #28
	z_setup_new_thread(thread, stack,
    2d66:	2201      	movs	r2, #1
    2d68:	e9cd 2304 	strd	r2, r3, [sp, #16]
    2d6c:	220f      	movs	r2, #15
    2d6e:	e9cd 3202 	strd	r3, r2, [sp, #8]
	struct k_thread *thread = &z_idle_threads[i];
    2d72:	4c0d      	ldr	r4, [pc, #52]	; (2da8 <init_idle_thread+0x48>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    2d74:	4a0d      	ldr	r2, [pc, #52]	; (2dac <init_idle_thread+0x4c>)
	z_setup_new_thread(thread, stack,
    2d76:	9301      	str	r3, [sp, #4]
    2d78:	490d      	ldr	r1, [pc, #52]	; (2db0 <init_idle_thread+0x50>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    2d7a:	2318      	movs	r3, #24
	struct k_thread *thread = &z_idle_threads[i];
    2d7c:	eb04 14c0 	add.w	r4, r4, r0, lsl #7
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    2d80:	fb03 2300 	mla	r3, r3, r0, r2
	z_setup_new_thread(thread, stack,
    2d84:	f44f 75b0 	mov.w	r5, #352	; 0x160
    2d88:	9300      	str	r3, [sp, #0]
    2d8a:	fb05 1100 	mla	r1, r5, r0, r1
    2d8e:	4b09      	ldr	r3, [pc, #36]	; (2db4 <init_idle_thread+0x54>)
    2d90:	f44f 72a0 	mov.w	r2, #320	; 0x140
    2d94:	4620      	mov	r0, r4
    2d96:	f000 f8f7 	bl	2f88 <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    2d9a:	7b63      	ldrb	r3, [r4, #13]
    2d9c:	f023 0304 	bic.w	r3, r3, #4
    2da0:	7363      	strb	r3, [r4, #13]
	z_mark_thread_as_started(thread);

#ifdef CONFIG_SMP
	thread->base.is_idle = 1U;
#endif
}
    2da2:	b007      	add	sp, #28
    2da4:	bd30      	pop	{r4, r5, pc}
    2da6:	bf00      	nop
    2da8:	20000130 	.word	0x20000130
    2dac:	20000934 	.word	0x20000934
    2db0:	20001380 	.word	0x20001380
    2db4:	000030a9 	.word	0x000030a9

00002db8 <bg_thread_main>:
{
    2db8:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    2dba:	4b0a      	ldr	r3, [pc, #40]	; (2de4 <bg_thread_main+0x2c>)
    2dbc:	2201      	movs	r2, #1
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    2dbe:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
    2dc0:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    2dc2:	f7ff ff81 	bl	2cc8 <z_sys_init_run_level>
	boot_banner();
    2dc6:	f001 fe22 	bl	4a0e <boot_banner>
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    2dca:	2003      	movs	r0, #3
    2dcc:	f7ff ff7c 	bl	2cc8 <z_sys_init_run_level>
	z_init_static_threads();
    2dd0:	f000 f90c 	bl	2fec <z_init_static_threads>
	main();
    2dd4:	f7fd fb0e 	bl	3f4 <main>
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    2dd8:	4a03      	ldr	r2, [pc, #12]	; (2de8 <bg_thread_main+0x30>)
    2dda:	7b13      	ldrb	r3, [r2, #12]
    2ddc:	f023 0301 	bic.w	r3, r3, #1
    2de0:	7313      	strb	r3, [r2, #12]
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    2de2:	bd08      	pop	{r3, pc}
    2de4:	20000d96 	.word	0x20000d96
    2de8:	200001b0 	.word	0x200001b0

00002dec <z_bss_zero>:
	(void)memset(__bss_start, 0, __bss_end - __bss_start);
    2dec:	4802      	ldr	r0, [pc, #8]	; (2df8 <z_bss_zero+0xc>)
    2dee:	4a03      	ldr	r2, [pc, #12]	; (2dfc <z_bss_zero+0x10>)
    2df0:	2100      	movs	r1, #0
    2df2:	1a12      	subs	r2, r2, r0
    2df4:	f001 babf 	b.w	4376 <memset>
    2df8:	20000110 	.word	0x20000110
    2dfc:	20000f54 	.word	0x20000f54

00002e00 <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    2e00:	b580      	push	{r7, lr}
 *
 * @return N/A
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    2e02:	f8df 80d8 	ldr.w	r8, [pc, #216]	; 2edc <z_cstart+0xdc>
    2e06:	b0a6      	sub	sp, #152	; 0x98
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    2e08:	f388 8808 	msr	MSP, r8
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    2e0c:	4d2d      	ldr	r5, [pc, #180]	; (2ec4 <z_cstart+0xc4>)
#endif
#ifdef CONFIG_USERSPACE
	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
#endif

	_current_cpu->current = dummy_thread;
    2e0e:	4e2e      	ldr	r6, [pc, #184]	; (2ec8 <z_cstart+0xc8>)
    2e10:	696b      	ldr	r3, [r5, #20]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    2e12:	f8df 90cc 	ldr.w	r9, [pc, #204]	; 2ee0 <z_cstart+0xe0>
    2e16:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2e1a:	2400      	movs	r4, #0
    2e1c:	616b      	str	r3, [r5, #20]
    2e1e:	23e0      	movs	r3, #224	; 0xe0
    2e20:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    2e24:	77ec      	strb	r4, [r5, #31]
    2e26:	762c      	strb	r4, [r5, #24]
    2e28:	766c      	strb	r4, [r5, #25]
    2e2a:	76ac      	strb	r4, [r5, #26]
    2e2c:	f885 4020 	strb.w	r4, [r5, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    2e30:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    2e32:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    2e36:	626b      	str	r3, [r5, #36]	; 0x24
    2e38:	f885 4023 	strb.w	r4, [r5, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    2e3c:	f7fe fb64 	bl	1508 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    2e40:	f7fe f936 	bl	10b0 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    2e44:	f04f 33ff 	mov.w	r3, #4294967295
    2e48:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    2e4a:	62eb      	str	r3, [r5, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    2e4c:	f7fe fc86 	bl	175c <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    2e50:	f7fe fbf6 	bl	1640 <z_arm_configure_static_mpu_regions>
	dummy_thread->base.user_options = K_ESSENTIAL;
    2e54:	f240 1301 	movw	r3, #257	; 0x101
    2e58:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    2e5c:	ab06      	add	r3, sp, #24
    2e5e:	60b3      	str	r3, [r6, #8]
	dummy_thread->stack_info.size = 0U;
    2e60:	e9cd 441f 	strd	r4, r4, [sp, #124]	; 0x7c
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    2e64:	f001 fc64 	bl	4730 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    2e68:	4620      	mov	r0, r4
    2e6a:	f7ff ff2d 	bl	2cc8 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    2e6e:	2001      	movs	r0, #1
	_kernel.ready_q.cache = &z_main_thread;
    2e70:	4d16      	ldr	r5, [pc, #88]	; (2ecc <z_cstart+0xcc>)
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    2e72:	f7ff ff29 	bl	2cc8 <z_sys_init_run_level>
	z_sched_init();
    2e76:	f000 fc8b 	bl	3790 <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    2e7a:	4b15      	ldr	r3, [pc, #84]	; (2ed0 <z_cstart+0xd0>)
    2e7c:	9305      	str	r3, [sp, #20]
    2e7e:	2301      	movs	r3, #1
    2e80:	4914      	ldr	r1, [pc, #80]	; (2ed4 <z_cstart+0xd4>)
    2e82:	9400      	str	r4, [sp, #0]
    2e84:	e9cd 4303 	strd	r4, r3, [sp, #12]
    2e88:	f44f 6280 	mov.w	r2, #1024	; 0x400
    2e8c:	464b      	mov	r3, r9
    2e8e:	e9cd 4401 	strd	r4, r4, [sp, #4]
    2e92:	4628      	mov	r0, r5
	_kernel.ready_q.cache = &z_main_thread;
    2e94:	61f5      	str	r5, [r6, #28]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    2e96:	f000 f877 	bl	2f88 <z_setup_new_thread>
    2e9a:	7b6a      	ldrb	r2, [r5, #13]
    2e9c:	f022 0204 	bic.w	r2, r2, #4
    2ea0:	736a      	strb	r2, [r5, #13]
    2ea2:	4607      	mov	r7, r0
	z_ready_thread(&z_main_thread);
    2ea4:	4628      	mov	r0, r5
    2ea6:	f001 fcf3 	bl	4890 <z_ready_thread>
		init_idle_thread(i);
    2eaa:	4620      	mov	r0, r4
    2eac:	f7ff ff58 	bl	2d60 <init_idle_thread>
		_kernel.cpus[i].idle_thread = &z_idle_threads[i];
    2eb0:	4b09      	ldr	r3, [pc, #36]	; (2ed8 <z_cstart+0xd8>)
    2eb2:	60f3      	str	r3, [r6, #12]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    2eb4:	464a      	mov	r2, r9
    2eb6:	4639      	mov	r1, r7
    2eb8:	4628      	mov	r0, r5
		_kernel.cpus[i].id = i;
    2eba:	7534      	strb	r4, [r6, #20]
		_kernel.cpus[i].irq_stack =
    2ebc:	f8c6 8004 	str.w	r8, [r6, #4]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    2ec0:	f7fe f9f4 	bl	12ac <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    2ec4:	e000ed00 	.word	0xe000ed00
    2ec8:	20000934 	.word	0x20000934
    2ecc:	200001b0 	.word	0x200001b0
    2ed0:	00004f02 	.word	0x00004f02
    2ed4:	20000f60 	.word	0x20000f60
    2ed8:	20000130 	.word	0x20000130
    2edc:	20001d00 	.word	0x20001d00
    2ee0:	00002db9 	.word	0x00002db9

00002ee4 <init_mem_slab_module>:
 * Perform any initialization that wasn't done at build time.
 *
 * @return N/A
 */
static int init_mem_slab_module(const struct device *dev)
{
    2ee4:	b570      	push	{r4, r5, r6, lr}
	int rc = 0;
	ARG_UNUSED(dev);

	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    2ee6:	4b0e      	ldr	r3, [pc, #56]	; (2f20 <init_mem_slab_module+0x3c>)
    2ee8:	4c0e      	ldr	r4, [pc, #56]	; (2f24 <init_mem_slab_module+0x40>)
    2eea:	42a3      	cmp	r3, r4
    2eec:	d301      	bcc.n	2ef2 <init_mem_slab_module+0xe>
			goto out;
		}
		z_object_init(slab);
	}

out:
    2eee:	2000      	movs	r0, #0
	return rc;
}
    2ef0:	bd70      	pop	{r4, r5, r6, pc}
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    2ef2:	e9d3 0103 	ldrd	r0, r1, [r3, #12]
    2ef6:	ea41 0200 	orr.w	r2, r1, r0
    2efa:	f012 0203 	ands.w	r2, r2, #3
    2efe:	d10b      	bne.n	2f18 <init_mem_slab_module+0x34>
	for (j = 0U; j < slab->num_blocks; j++) {
    2f00:	689d      	ldr	r5, [r3, #8]
	slab->free_list = NULL;
    2f02:	615a      	str	r2, [r3, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    2f04:	42aa      	cmp	r2, r5
    2f06:	d101      	bne.n	2f0c <init_mem_slab_module+0x28>
	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    2f08:	331c      	adds	r3, #28
    2f0a:	e7ee      	b.n	2eea <init_mem_slab_module+0x6>
		*(char **)p = slab->free_list;
    2f0c:	695e      	ldr	r6, [r3, #20]
    2f0e:	600e      	str	r6, [r1, #0]
	for (j = 0U; j < slab->num_blocks; j++) {
    2f10:	3201      	adds	r2, #1
		slab->free_list = p;
    2f12:	6159      	str	r1, [r3, #20]
		p += slab->block_size;
    2f14:	4401      	add	r1, r0
	for (j = 0U; j < slab->num_blocks; j++) {
    2f16:	e7f5      	b.n	2f04 <init_mem_slab_module+0x20>
		return -EINVAL;
    2f18:	f06f 0015 	mvn.w	r0, #21
	return rc;
    2f1c:	e7e8      	b.n	2ef0 <init_mem_slab_module+0xc>
    2f1e:	bf00      	nop
    2f20:	200000bc 	.word	0x200000bc
    2f24:	200000bc 	.word	0x200000bc

00002f28 <k_mem_slab_alloc>:

	return rc;
}

int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
{
    2f28:	b5d3      	push	{r0, r1, r4, r6, r7, lr}
    2f2a:	460c      	mov	r4, r1
    2f2c:	4616      	mov	r6, r2
    2f2e:	461f      	mov	r7, r3
	__asm__ volatile(
    2f30:	f04f 0320 	mov.w	r3, #32
    2f34:	f3ef 8111 	mrs	r1, BASEPRI
    2f38:	f383 8812 	msr	BASEPRI_MAX, r3
    2f3c:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);
	int result;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, alloc, slab, timeout);

	if (slab->free_list != NULL) {
    2f40:	6943      	ldr	r3, [r0, #20]
    2f42:	b15b      	cbz	r3, 2f5c <k_mem_slab_alloc+0x34>
		/* take a free block */
		*mem = slab->free_list;
    2f44:	6023      	str	r3, [r4, #0]
		slab->free_list = *(char **)(slab->free_list);
    2f46:	681b      	ldr	r3, [r3, #0]
    2f48:	6143      	str	r3, [r0, #20]
		slab->num_used++;
    2f4a:	6983      	ldr	r3, [r0, #24]
    2f4c:	3301      	adds	r3, #1
    2f4e:	6183      	str	r3, [r0, #24]

#ifdef CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION
		slab->max_used = MAX(slab->num_used, slab->max_used);
#endif

		result = 0;
    2f50:	2000      	movs	r0, #0
	__asm__ volatile(
    2f52:	f381 8811 	msr	BASEPRI, r1
    2f56:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, alloc, slab, timeout, result);

	k_spin_unlock(&slab->lock, key);

	return result;
    2f5a:	e011      	b.n	2f80 <k_mem_slab_alloc+0x58>
	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT) ||
    2f5c:	ea56 0207 	orrs.w	r2, r6, r7
    2f60:	d103      	bne.n	2f6a <k_mem_slab_alloc+0x42>
		*mem = NULL;
    2f62:	6023      	str	r3, [r4, #0]
		result = -ENOMEM;
    2f64:	f06f 000b 	mvn.w	r0, #11
    2f68:	e7f3      	b.n	2f52 <k_mem_slab_alloc+0x2a>
		result = z_pend_curr(&slab->lock, key, &slab->wait_q, timeout);
    2f6a:	4602      	mov	r2, r0
    2f6c:	e9cd 6700 	strd	r6, r7, [sp]
    2f70:	3008      	adds	r0, #8
    2f72:	f000 fb5f 	bl	3634 <z_pend_curr>
		if (result == 0) {
    2f76:	b918      	cbnz	r0, 2f80 <k_mem_slab_alloc+0x58>
			*mem = _current->base.swap_data;
    2f78:	4b02      	ldr	r3, [pc, #8]	; (2f84 <k_mem_slab_alloc+0x5c>)
    2f7a:	689b      	ldr	r3, [r3, #8]
    2f7c:	695b      	ldr	r3, [r3, #20]
    2f7e:	6023      	str	r3, [r4, #0]
}
    2f80:	b002      	add	sp, #8
    2f82:	bdd0      	pop	{r4, r6, r7, pc}
    2f84:	20000934 	.word	0x20000934

00002f88 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    2f88:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
	thread_base->user_options = (uint8_t)options;
    2f8c:	9e0e      	ldr	r6, [sp, #56]	; 0x38
    2f8e:	7306      	strb	r6, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    2f90:	2604      	movs	r6, #4
    2f92:	7346      	strb	r6, [r0, #13]

	thread_base->prio = priority;
    2f94:	9e0d      	ldr	r6, [sp, #52]	; 0x34
    2f96:	7386      	strb	r6, [r0, #14]
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    2f98:	f100 0558 	add.w	r5, r0, #88	; 0x58
{
    2f9c:	460f      	mov	r7, r1
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    2f9e:	1dd6      	adds	r6, r2, #7
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
	list->tail = (sys_dnode_t *)list;
    2fa0:	e9c0 5516 	strd	r5, r5, [r0, #88]	; 0x58
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    2fa4:	9a0c      	ldr	r2, [sp, #48]	; 0x30
	thread_base->pended_on = NULL;
    2fa6:	2500      	movs	r5, #0
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    2fa8:	f026 0607 	bic.w	r6, r6, #7

/** @} */

static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym)
{
	return (char *)sym + K_KERNEL_STACK_RESERVED;
    2fac:	3720      	adds	r7, #32
 */

static inline void sys_dnode_init(sys_dnode_t *node)
{
	node->next = NULL;
	node->prev = NULL;
    2fae:	e9c0 5506 	strd	r5, r5, [r0, #24]
	new_thread->stack_info.size = stack_buf_size;
    2fb2:	e9c0 7619 	strd	r7, r6, [r0, #100]	; 0x64
	thread_base->pended_on = NULL;
    2fb6:	6085      	str	r5, [r0, #8]

	thread_base->sched_locked = 0U;
    2fb8:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    2fba:	66c5      	str	r5, [r0, #108]	; 0x6c
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    2fbc:	f106 0820 	add.w	r8, r6, #32
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    2fc0:	9202      	str	r2, [sp, #8]
    2fc2:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    2fc4:	9201      	str	r2, [sp, #4]
	stack_ptr = (char *)stack + stack_obj_size;
    2fc6:	4488      	add	r8, r1
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    2fc8:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    2fca:	9200      	str	r2, [sp, #0]
    2fcc:	4642      	mov	r2, r8
{
    2fce:	4604      	mov	r4, r0
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    2fd0:	f7fe f936 	bl	1240 <arch_new_thread>
	if (!_current) {
    2fd4:	4b04      	ldr	r3, [pc, #16]	; (2fe8 <z_setup_new_thread+0x60>)
	new_thread->init_data = NULL;
    2fd6:	6565      	str	r5, [r4, #84]	; 0x54
	if (!_current) {
    2fd8:	689b      	ldr	r3, [r3, #8]
    2fda:	b103      	cbz	r3, 2fde <z_setup_new_thread+0x56>
	new_thread->resource_pool = _current->resource_pool;
    2fdc:	6f1b      	ldr	r3, [r3, #112]	; 0x70
	return stack_ptr;
    2fde:	6723      	str	r3, [r4, #112]	; 0x70
}
    2fe0:	4640      	mov	r0, r8
    2fe2:	b004      	add	sp, #16
    2fe4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    2fe8:	20000934 	.word	0x20000934

00002fec <z_init_static_threads>:
{
    2fec:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	_FOREACH_STATIC_THREAD(thread_data) {
    2ff0:	4e2a      	ldr	r6, [pc, #168]	; (309c <z_init_static_threads+0xb0>)
    2ff2:	4d2b      	ldr	r5, [pc, #172]	; (30a0 <z_init_static_threads+0xb4>)
{
    2ff4:	b086      	sub	sp, #24
    2ff6:	46b0      	mov	r8, r6
	_FOREACH_STATIC_THREAD(thread_data) {
    2ff8:	42b5      	cmp	r5, r6
    2ffa:	f105 0430 	add.w	r4, r5, #48	; 0x30
    2ffe:	d310      	bcc.n	3022 <z_init_static_threads+0x36>
	k_sched_lock();
    3000:	f000 f9d0 	bl	33a4 <k_sched_lock>
	_FOREACH_STATIC_THREAD(thread_data) {
    3004:	4c26      	ldr	r4, [pc, #152]	; (30a0 <z_init_static_threads+0xb4>)

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    3006:	f8df a09c 	ldr.w	sl, [pc, #156]	; 30a4 <z_init_static_threads+0xb8>
		} else {
			return (t * to_hz + off) / from_hz;
    300a:	f44f 4900 	mov.w	r9, #32768	; 0x8000
    300e:	f240 36e7 	movw	r6, #999	; 0x3e7
    3012:	2700      	movs	r7, #0
    3014:	4544      	cmp	r4, r8
    3016:	d321      	bcc.n	305c <z_init_static_threads+0x70>
}
    3018:	b006      	add	sp, #24
    301a:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	k_sched_unlock();
    301e:	f000 bb9b 	b.w	3758 <k_sched_unlock>
		z_setup_new_thread(
    3022:	f854 3c04 	ldr.w	r3, [r4, #-4]
    3026:	9305      	str	r3, [sp, #20]
    3028:	f854 3c10 	ldr.w	r3, [r4, #-16]
    302c:	9304      	str	r3, [sp, #16]
    302e:	f854 3c14 	ldr.w	r3, [r4, #-20]
    3032:	9303      	str	r3, [sp, #12]
    3034:	f854 3c18 	ldr.w	r3, [r4, #-24]
    3038:	9302      	str	r3, [sp, #8]
    303a:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    303e:	9301      	str	r3, [sp, #4]
    3040:	f854 3c20 	ldr.w	r3, [r4, #-32]
    3044:	9300      	str	r3, [sp, #0]
    3046:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    304a:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    304e:	f7ff ff9b 	bl	2f88 <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    3052:	f854 3c30 	ldr.w	r3, [r4, #-48]
    3056:	655d      	str	r5, [r3, #84]	; 0x54
    3058:	4625      	mov	r5, r4
    305a:	e7cd      	b.n	2ff8 <z_init_static_threads+0xc>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    305c:	6a63      	ldr	r3, [r4, #36]	; 0x24
    305e:	1c5a      	adds	r2, r3, #1
    3060:	d00d      	beq.n	307e <z_init_static_threads+0x92>
					    K_MSEC(thread_data->init_delay));
    3062:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    3066:	4630      	mov	r0, r6
    3068:	4639      	mov	r1, r7
    306a:	fbc9 0103 	smlal	r0, r1, r9, r3
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    306e:	42b9      	cmp	r1, r7
    3070:	bf08      	it	eq
    3072:	42b0      	cmpeq	r0, r6
			schedule_new_thread(thread_data->init_thread,
    3074:	6825      	ldr	r5, [r4, #0]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3076:	d104      	bne.n	3082 <z_init_static_threads+0x96>
	z_sched_start(thread);
    3078:	4628      	mov	r0, r5
    307a:	f000 fa7f 	bl	357c <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    307e:	3430      	adds	r4, #48	; 0x30
    3080:	e7c8      	b.n	3014 <z_init_static_threads+0x28>
    3082:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    3086:	2300      	movs	r3, #0
    3088:	f7fd f83a 	bl	100 <__aeabi_uldivmod>
    308c:	4602      	mov	r2, r0
    308e:	460b      	mov	r3, r1
    3090:	f105 0018 	add.w	r0, r5, #24
    3094:	4651      	mov	r1, sl
    3096:	f000 fcf1 	bl	3a7c <z_add_timeout>
    309a:	e7f0      	b.n	307e <z_init_static_threads+0x92>
    309c:	200000bc 	.word	0x200000bc
    30a0:	200000bc 	.word	0x200000bc
    30a4:	000048b1 	.word	0x000048b1

000030a8 <idle>:
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
}

void idle(void *unused1, void *unused2, void *unused3)
{
    30a8:	b508      	push	{r3, lr}
	_kernel.idle = ticks;
    30aa:	4c09      	ldr	r4, [pc, #36]	; (30d0 <idle+0x28>)
	__asm__ volatile(
    30ac:	f04f 0220 	mov.w	r2, #32
    30b0:	f3ef 8311 	mrs	r3, BASEPRI
    30b4:	f382 8812 	msr	BASEPRI_MAX, r2
    30b8:	f3bf 8f6f 	isb	sy
	int32_t ticks = z_get_next_timeout_expiry();
    30bc:	f001 fc75 	bl	49aa <z_get_next_timeout_expiry>
	_kernel.idle = ticks;
    30c0:	61a0      	str	r0, [r4, #24]
	if (pm_system_suspend(ticks) == PM_STATE_ACTIVE) {
    30c2:	f7fd fee7 	bl	e94 <pm_system_suspend>
    30c6:	2800      	cmp	r0, #0
    30c8:	d1f0      	bne.n	30ac <idle+0x4>
	arch_cpu_idle();
    30ca:	f7fd fff7 	bl	10bc <arch_cpu_idle>
}
    30ce:	e7ed      	b.n	30ac <idle+0x4>
    30d0:	20000934 	.word	0x20000934

000030d4 <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
    30d4:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    30d8:	4604      	mov	r4, r0
    30da:	4616      	mov	r6, r2
    30dc:	461f      	mov	r7, r3
    30de:	f04f 0320 	mov.w	r3, #32
    30e2:	f3ef 8811 	mrs	r8, BASEPRI
    30e6:	f383 8812 	msr	BASEPRI_MAX, r3
    30ea:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, lock, mutex, timeout);

	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    30ee:	68c3      	ldr	r3, [r0, #12]
    30f0:	4a35      	ldr	r2, [pc, #212]	; (31c8 <z_impl_k_mutex_lock+0xf4>)
    30f2:	b16b      	cbz	r3, 3110 <z_impl_k_mutex_lock+0x3c>
    30f4:	6880      	ldr	r0, [r0, #8]
    30f6:	6891      	ldr	r1, [r2, #8]
    30f8:	4288      	cmp	r0, r1
    30fa:	d019      	beq.n	3130 <z_impl_k_mutex_lock+0x5c>
		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, 0);

		return 0;
	}

	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
    30fc:	ea56 0307 	orrs.w	r3, r6, r7
    3100:	d118      	bne.n	3134 <z_impl_k_mutex_lock+0x60>
	__asm__ volatile(
    3102:	f388 8811 	msr	BASEPRI, r8
    3106:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);

		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EBUSY);

		return -EBUSY;
    310a:	f06f 000f 	mvn.w	r0, #15
    310e:	e00c      	b.n	312a <z_impl_k_mutex_lock+0x56>
					_current->base.prio :
    3110:	6891      	ldr	r1, [r2, #8]
    3112:	f991 100e 	ldrsb.w	r1, [r1, #14]
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
    3116:	6121      	str	r1, [r4, #16]
		mutex->lock_count++;
    3118:	3301      	adds	r3, #1
    311a:	60e3      	str	r3, [r4, #12]
		mutex->owner = _current;
    311c:	6893      	ldr	r3, [r2, #8]
    311e:	60a3      	str	r3, [r4, #8]
    3120:	f388 8811 	msr	BASEPRI, r8
    3124:	f3bf 8f6f 	isb	sy
		return 0;
    3128:	2000      	movs	r0, #0
	}

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EAGAIN);

	return -EAGAIN;
}
    312a:	b002      	add	sp, #8
    312c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
					_current->base.prio :
    3130:	6921      	ldr	r1, [r4, #16]
    3132:	e7f0      	b.n	3116 <z_impl_k_mutex_lock+0x42>
	new_prio = new_prio_for_inheritance(_current->base.prio,
    3134:	f991 100e 	ldrsb.w	r1, [r1, #14]
    3138:	f990 300e 	ldrsb.w	r3, [r0, #14]
	thread->base.thread_state &= ~states;
}

static inline bool z_is_under_prio_ceiling(int prio)
{
	return prio >= CONFIG_PRIORITY_CEILING;
    313c:	4299      	cmp	r1, r3
    313e:	bfa8      	it	ge
    3140:	4619      	movge	r1, r3
    3142:	f06f 027e 	mvn.w	r2, #126	; 0x7e
    3146:	4291      	cmp	r1, r2
    3148:	bfb8      	it	lt
    314a:	4611      	movlt	r1, r2
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
    314c:	428b      	cmp	r3, r1
    314e:	dd2f      	ble.n	31b0 <z_impl_k_mutex_lock+0xdc>
		return z_set_prio(mutex->owner, new_prio);
    3150:	f000 fa84 	bl	365c <z_set_prio>
    3154:	4605      	mov	r5, r0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
    3156:	e9cd 6700 	strd	r6, r7, [sp]
    315a:	481c      	ldr	r0, [pc, #112]	; (31cc <z_impl_k_mutex_lock+0xf8>)
    315c:	4622      	mov	r2, r4
    315e:	4641      	mov	r1, r8
    3160:	f000 fa68 	bl	3634 <z_pend_curr>
	if (got_mutex == 0) {
    3164:	2800      	cmp	r0, #0
    3166:	d0e0      	beq.n	312a <z_impl_k_mutex_lock+0x56>
	__asm__ volatile(
    3168:	f04f 0320 	mov.w	r3, #32
    316c:	f3ef 8611 	mrs	r6, BASEPRI
    3170:	f383 8812 	msr	BASEPRI_MAX, r3
    3174:	f3bf 8f6f 	isb	sy
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    3178:	6823      	ldr	r3, [r4, #0]
    317a:	6921      	ldr	r1, [r4, #16]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    317c:	429c      	cmp	r4, r3
    317e:	d00a      	beq.n	3196 <z_impl_k_mutex_lock+0xc2>
		new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    3180:	b14b      	cbz	r3, 3196 <z_impl_k_mutex_lock+0xc2>
    3182:	f993 300e 	ldrsb.w	r3, [r3, #14]
    3186:	4299      	cmp	r1, r3
    3188:	bfa8      	it	ge
    318a:	4619      	movge	r1, r3
    318c:	f06f 037e 	mvn.w	r3, #126	; 0x7e
    3190:	4299      	cmp	r1, r3
    3192:	bfb8      	it	lt
    3194:	4619      	movlt	r1, r3
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    3196:	68a0      	ldr	r0, [r4, #8]
	if (mutex->owner->base.prio != new_prio) {
    3198:	f990 300e 	ldrsb.w	r3, [r0, #14]
    319c:	4299      	cmp	r1, r3
    319e:	d109      	bne.n	31b4 <z_impl_k_mutex_lock+0xe0>
	if (resched) {
    31a0:	b16d      	cbz	r5, 31be <z_impl_k_mutex_lock+0xea>
		z_reschedule(&lock, key);
    31a2:	480a      	ldr	r0, [pc, #40]	; (31cc <z_impl_k_mutex_lock+0xf8>)
    31a4:	4631      	mov	r1, r6
    31a6:	f000 f8eb 	bl	3380 <z_reschedule>
	return -EAGAIN;
    31aa:	f06f 000a 	mvn.w	r0, #10
    31ae:	e7bc      	b.n	312a <z_impl_k_mutex_lock+0x56>
	bool resched = false;
    31b0:	2500      	movs	r5, #0
    31b2:	e7d0      	b.n	3156 <z_impl_k_mutex_lock+0x82>
		return z_set_prio(mutex->owner, new_prio);
    31b4:	f000 fa52 	bl	365c <z_set_prio>
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    31b8:	2800      	cmp	r0, #0
    31ba:	d1f2      	bne.n	31a2 <z_impl_k_mutex_lock+0xce>
    31bc:	e7f0      	b.n	31a0 <z_impl_k_mutex_lock+0xcc>
	__asm__ volatile(
    31be:	f386 8811 	msr	BASEPRI, r6
    31c2:	f3bf 8f6f 	isb	sy
    31c6:	e7f0      	b.n	31aa <z_impl_k_mutex_lock+0xd6>
    31c8:	20000934 	.word	0x20000934
    31cc:	20000d97 	.word	0x20000d97

000031d0 <z_impl_k_mutex_unlock>:
}
#include <syscalls/k_mutex_lock_mrsh.c>
#endif

int z_impl_k_mutex_unlock(struct k_mutex *mutex)
{
    31d0:	b538      	push	{r3, r4, r5, lr}

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, unlock, mutex);

	CHECKIF(mutex->owner == NULL) {
    31d2:	6883      	ldr	r3, [r0, #8]
{
    31d4:	4604      	mov	r4, r0
	CHECKIF(mutex->owner == NULL) {
    31d6:	2b00      	cmp	r3, #0
    31d8:	d036      	beq.n	3248 <z_impl_k_mutex_unlock+0x78>
		return -EINVAL;
	}
	/*
	 * The current thread does not own the mutex.
	 */
	CHECKIF(mutex->owner != _current) {
    31da:	4a1e      	ldr	r2, [pc, #120]	; (3254 <z_impl_k_mutex_unlock+0x84>)
    31dc:	6892      	ldr	r2, [r2, #8]
    31de:	4293      	cmp	r3, r2
    31e0:	d135      	bne.n	324e <z_impl_k_mutex_unlock+0x7e>
static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1U, "");

	--_current->base.sched_locked;
    31e2:	7bda      	ldrb	r2, [r3, #15]
    31e4:	3a01      	subs	r2, #1
    31e6:	73da      	strb	r2, [r3, #15]

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count > 1U) {
    31e8:	68c3      	ldr	r3, [r0, #12]
    31ea:	2b01      	cmp	r3, #1
    31ec:	d905      	bls.n	31fa <z_impl_k_mutex_unlock+0x2a>
		mutex->lock_count--;
    31ee:	3b01      	subs	r3, #1
    31f0:	60c3      	str	r3, [r0, #12]


k_mutex_unlock_return:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, unlock, mutex, 0);

	k_sched_unlock();
    31f2:	f000 fab1 	bl	3758 <k_sched_unlock>

	return 0;
    31f6:	2000      	movs	r0, #0
}
    31f8:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    31fa:	f04f 0320 	mov.w	r3, #32
    31fe:	f3ef 8511 	mrs	r5, BASEPRI
    3202:	f383 8812 	msr	BASEPRI_MAX, r3
    3206:	f3bf 8f6f 	isb	sy
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
    320a:	6901      	ldr	r1, [r0, #16]
    320c:	6880      	ldr	r0, [r0, #8]
	if (mutex->owner->base.prio != new_prio) {
    320e:	f990 300e 	ldrsb.w	r3, [r0, #14]
    3212:	4299      	cmp	r1, r3
    3214:	d001      	beq.n	321a <z_impl_k_mutex_unlock+0x4a>
		return z_set_prio(mutex->owner, new_prio);
    3216:	f000 fa21 	bl	365c <z_set_prio>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
    321a:	4620      	mov	r0, r4
    321c:	f001 fb97 	bl	494e <z_unpend_first_thread>
	mutex->owner = new_owner;
    3220:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
    3222:	b158      	cbz	r0, 323c <z_impl_k_mutex_unlock+0x6c>
		mutex->owner_orig_prio = new_owner->base.prio;
    3224:	f990 200e 	ldrsb.w	r2, [r0, #14]
    3228:	6122      	str	r2, [r4, #16]
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    322a:	2200      	movs	r2, #0
    322c:	6782      	str	r2, [r0, #120]	; 0x78
		z_ready_thread(new_owner);
    322e:	f001 fb2f 	bl	4890 <z_ready_thread>
		z_reschedule(&lock, key);
    3232:	4809      	ldr	r0, [pc, #36]	; (3258 <z_impl_k_mutex_unlock+0x88>)
    3234:	4629      	mov	r1, r5
    3236:	f000 f8a3 	bl	3380 <z_reschedule>
    323a:	e7da      	b.n	31f2 <z_impl_k_mutex_unlock+0x22>
		mutex->lock_count = 0U;
    323c:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    323e:	f385 8811 	msr	BASEPRI, r5
    3242:	f3bf 8f6f 	isb	sy
    3246:	e7d4      	b.n	31f2 <z_impl_k_mutex_unlock+0x22>
		return -EINVAL;
    3248:	f06f 0015 	mvn.w	r0, #21
    324c:	e7d4      	b.n	31f8 <z_impl_k_mutex_unlock+0x28>
		return -EPERM;
    324e:	f04f 30ff 	mov.w	r0, #4294967295
    3252:	e7d1      	b.n	31f8 <z_impl_k_mutex_unlock+0x28>
    3254:	20000934 	.word	0x20000934
    3258:	20000d97 	.word	0x20000d97

0000325c <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    325c:	b538      	push	{r3, r4, r5, lr}
    325e:	4604      	mov	r4, r0
	__asm__ volatile(
    3260:	f04f 0320 	mov.w	r3, #32
    3264:	f3ef 8511 	mrs	r5, BASEPRI
    3268:	f383 8812 	msr	BASEPRI_MAX, r3
    326c:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    3270:	f001 fb6d 	bl	494e <z_unpend_first_thread>

	if (thread != NULL) {
    3274:	b148      	cbz	r0, 328a <z_impl_k_sem_give+0x2e>
    3276:	2200      	movs	r2, #0
    3278:	6782      	str	r2, [r0, #120]	; 0x78
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    327a:	f001 fb09 	bl	4890 <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    327e:	4629      	mov	r1, r5
    3280:	4805      	ldr	r0, [pc, #20]	; (3298 <z_impl_k_sem_give+0x3c>)

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    3282:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    3286:	f000 b87b 	b.w	3380 <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    328a:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    328e:	429a      	cmp	r2, r3
    3290:	bf18      	it	ne
    3292:	3301      	addne	r3, #1
    3294:	60a3      	str	r3, [r4, #8]
		handle_poll_events(sem);
    3296:	e7f2      	b.n	327e <z_impl_k_sem_give+0x22>
    3298:	20000d97 	.word	0x20000d97

0000329c <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    329c:	b537      	push	{r0, r1, r2, r4, r5, lr}
    329e:	4614      	mov	r4, r2
    32a0:	461d      	mov	r5, r3
    32a2:	f04f 0320 	mov.w	r3, #32
    32a6:	f3ef 8111 	mrs	r1, BASEPRI
    32aa:	f383 8812 	msr	BASEPRI_MAX, r3
    32ae:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    32b2:	6883      	ldr	r3, [r0, #8]
    32b4:	b143      	cbz	r3, 32c8 <z_impl_k_sem_take+0x2c>
		sem->count--;
    32b6:	3b01      	subs	r3, #1
    32b8:	6083      	str	r3, [r0, #8]
	__asm__ volatile(
    32ba:	f381 8811 	msr	BASEPRI, r1
    32be:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    32c2:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    32c4:	b003      	add	sp, #12
    32c6:	bd30      	pop	{r4, r5, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    32c8:	ea54 0305 	orrs.w	r3, r4, r5
    32cc:	d106      	bne.n	32dc <z_impl_k_sem_take+0x40>
    32ce:	f381 8811 	msr	BASEPRI, r1
    32d2:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    32d6:	f06f 000f 	mvn.w	r0, #15
    32da:	e7f3      	b.n	32c4 <z_impl_k_sem_take+0x28>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    32dc:	4602      	mov	r2, r0
    32de:	e9cd 4500 	strd	r4, r5, [sp]
    32e2:	4802      	ldr	r0, [pc, #8]	; (32ec <z_impl_k_sem_take+0x50>)
    32e4:	f000 f9a6 	bl	3634 <z_pend_curr>
	return ret;
    32e8:	e7ec      	b.n	32c4 <z_impl_k_sem_take+0x28>
    32ea:	bf00      	nop
    32ec:	20000d97 	.word	0x20000d97

000032f0 <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(void)
{
    32f0:	b510      	push	{r4, lr}
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time != 0) {
    32f2:	4c08      	ldr	r4, [pc, #32]	; (3314 <z_reset_time_slice+0x24>)
    32f4:	6823      	ldr	r3, [r4, #0]
    32f6:	b15b      	cbz	r3, 3310 <z_reset_time_slice+0x20>
		_current_cpu->slice_ticks = slice_time + sys_clock_elapsed();
    32f8:	f7ff fa4e 	bl	2798 <sys_clock_elapsed>
    32fc:	4603      	mov	r3, r0
    32fe:	6820      	ldr	r0, [r4, #0]
    3300:	4a05      	ldr	r2, [pc, #20]	; (3318 <z_reset_time_slice+0x28>)
    3302:	4403      	add	r3, r0
		z_set_timeout_expiry(slice_time, false);
	}
}
    3304:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		_current_cpu->slice_ticks = slice_time + sys_clock_elapsed();
    3308:	6113      	str	r3, [r2, #16]
		z_set_timeout_expiry(slice_time, false);
    330a:	2100      	movs	r1, #0
    330c:	f001 bb5d 	b.w	49ca <z_set_timeout_expiry>
}
    3310:	bd10      	pop	{r4, pc}
    3312:	bf00      	nop
    3314:	20000964 	.word	0x20000964
    3318:	20000934 	.word	0x20000934

0000331c <k_sched_time_slice_set>:

void k_sched_time_slice_set(int32_t slice, int prio)
{
    331c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    331e:	4604      	mov	r4, r0
    3320:	460d      	mov	r5, r1
	__asm__ volatile(
    3322:	f04f 0320 	mov.w	r3, #32
    3326:	f3ef 8611 	mrs	r6, BASEPRI
    332a:	f383 8812 	msr	BASEPRI_MAX, r3
    332e:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		_current_cpu->slice_ticks = 0;
    3332:	4b10      	ldr	r3, [pc, #64]	; (3374 <k_sched_time_slice_set+0x58>)
    3334:	2200      	movs	r2, #0
			return (uint32_t)((t * to_hz + off) / from_hz);
    3336:	f44f 4700 	mov.w	r7, #32768	; 0x8000
    333a:	f240 30e7 	movw	r0, #999	; 0x3e7
    333e:	2100      	movs	r1, #0
    3340:	611a      	str	r2, [r3, #16]
    3342:	fbe7 0104 	umlal	r0, r1, r7, r4
    3346:	2300      	movs	r3, #0
    3348:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    334c:	f7fc fed8 	bl	100 <__aeabi_uldivmod>
		slice_time = k_ms_to_ticks_ceil32(slice);
		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && slice > 0) {
    3350:	2c00      	cmp	r4, #0
    3352:	4b09      	ldr	r3, [pc, #36]	; (3378 <k_sched_time_slice_set+0x5c>)
    3354:	dc09      	bgt.n	336a <k_sched_time_slice_set+0x4e>
			/* It's not possible to reliably set a 1-tick
			 * timeout if ticks aren't regular.
			 */
			slice_time = MAX(2, slice_time);
    3356:	6018      	str	r0, [r3, #0]
		}
		slice_max_prio = prio;
    3358:	4b08      	ldr	r3, [pc, #32]	; (337c <k_sched_time_slice_set+0x60>)
    335a:	601d      	str	r5, [r3, #0]
		z_reset_time_slice();
    335c:	f7ff ffc8 	bl	32f0 <z_reset_time_slice>
	__asm__ volatile(
    3360:	f386 8811 	msr	BASEPRI, r6
    3364:	f3bf 8f6f 	isb	sy
	}
}
    3368:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
			slice_time = MAX(2, slice_time);
    336a:	2802      	cmp	r0, #2
    336c:	bfb8      	it	lt
    336e:	2002      	movlt	r0, #2
    3370:	e7f1      	b.n	3356 <k_sched_time_slice_set+0x3a>
    3372:	bf00      	nop
    3374:	20000934 	.word	0x20000934
    3378:	20000964 	.word	0x20000964
    337c:	20000960 	.word	0x20000960

00003380 <z_reschedule>:
{
#ifdef CONFIG_SMP
	_current_cpu->swap_ok = 0;
#endif

	return arch_irq_unlocked(key) && !arch_is_in_isr();
    3380:	b949      	cbnz	r1, 3396 <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    3382:	f3ef 8005 	mrs	r0, IPSR
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
	if (resched(key.key) && need_swap()) {
    3386:	b930      	cbnz	r0, 3396 <z_reschedule+0x16>
	new_thread = _kernel.ready_q.cache;
    3388:	4b05      	ldr	r3, [pc, #20]	; (33a0 <z_reschedule+0x20>)
	if (resched(key.key) && need_swap()) {
    338a:	69da      	ldr	r2, [r3, #28]
    338c:	689b      	ldr	r3, [r3, #8]
    338e:	429a      	cmp	r2, r3
    3390:	d001      	beq.n	3396 <z_reschedule+0x16>
	ret = arch_swap(key);
    3392:	f7fd bf01 	b.w	1198 <arch_swap>
    3396:	f381 8811 	msr	BASEPRI, r1
    339a:	f3bf 8f6f 	isb	sy
		z_swap(lock, key);
	} else {
		k_spin_unlock(lock, key);
	}
}
    339e:	4770      	bx	lr
    33a0:	20000934 	.word	0x20000934

000033a4 <k_sched_lock>:
	__asm__ volatile(
    33a4:	f04f 0320 	mov.w	r3, #32
    33a8:	f3ef 8111 	mrs	r1, BASEPRI
    33ac:	f383 8812 	msr	BASEPRI_MAX, r3
    33b0:	f3bf 8f6f 	isb	sy
    33b4:	4b04      	ldr	r3, [pc, #16]	; (33c8 <k_sched_lock+0x24>)
    33b6:	689a      	ldr	r2, [r3, #8]
    33b8:	7bd3      	ldrb	r3, [r2, #15]
    33ba:	3b01      	subs	r3, #1
    33bc:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    33be:	f381 8811 	msr	BASEPRI, r1
    33c2:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		SYS_PORT_TRACING_FUNC(k_thread, sched_lock);

		z_sched_lock();
	}
}
    33c6:	4770      	bx	lr
    33c8:	20000934 	.word	0x20000934

000033cc <update_cache>:
{
    33cc:	b538      	push	{r3, r4, r5, lr}
    33ce:	4602      	mov	r2, r0
	thread = _priq_run_best(&_kernel.ready_q.runq);
    33d0:	480c      	ldr	r0, [pc, #48]	; (3404 <update_cache+0x38>)
    33d2:	4d0d      	ldr	r5, [pc, #52]	; (3408 <update_cache+0x3c>)
    33d4:	f001 fa52 	bl	487c <z_priq_dumb_best>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    33d8:	4604      	mov	r4, r0
    33da:	b900      	cbnz	r0, 33de <update_cache+0x12>
    33dc:	68ec      	ldr	r4, [r5, #12]
	if (preempt_ok != 0) {
    33de:	68ab      	ldr	r3, [r5, #8]
    33e0:	b94a      	cbnz	r2, 33f6 <update_cache+0x2a>
	if (z_is_thread_prevented_from_running(_current)) {
    33e2:	7b5a      	ldrb	r2, [r3, #13]
    33e4:	06d2      	lsls	r2, r2, #27
    33e6:	d106      	bne.n	33f6 <update_cache+0x2a>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    33e8:	69a2      	ldr	r2, [r4, #24]
    33ea:	b922      	cbnz	r2, 33f6 <update_cache+0x2a>
	if (is_preempt(_current) || is_metairq(thread)) {
    33ec:	89da      	ldrh	r2, [r3, #14]
    33ee:	2a7f      	cmp	r2, #127	; 0x7f
    33f0:	d901      	bls.n	33f6 <update_cache+0x2a>
		_kernel.ready_q.cache = _current;
    33f2:	61eb      	str	r3, [r5, #28]
}
    33f4:	bd38      	pop	{r3, r4, r5, pc}
		if (thread != _current) {
    33f6:	429c      	cmp	r4, r3
    33f8:	d001      	beq.n	33fe <update_cache+0x32>
			z_reset_time_slice();
    33fa:	f7ff ff79 	bl	32f0 <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    33fe:	61ec      	str	r4, [r5, #28]
}
    3400:	e7f8      	b.n	33f4 <update_cache+0x28>
    3402:	bf00      	nop
    3404:	20000954 	.word	0x20000954
    3408:	20000934 	.word	0x20000934

0000340c <move_thread_to_end_of_prio_q>:
{
    340c:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    340e:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return z_is_thread_state_set(thread, _THREAD_QUEUED);
    3412:	7b43      	ldrb	r3, [r0, #13]
    3414:	2a00      	cmp	r2, #0
{
    3416:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    3418:	da04      	bge.n	3424 <move_thread_to_end_of_prio_q+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    341a:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    341e:	7343      	strb	r3, [r0, #13]

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
    3420:	f001 fa04 	bl	482c <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    3424:	7b4b      	ldrb	r3, [r1, #13]
	return list->head == list;
    3426:	4a17      	ldr	r2, [pc, #92]	; (3484 <move_thread_to_end_of_prio_q+0x78>)
    3428:	f063 037f 	orn	r3, r3, #127	; 0x7f
    342c:	4610      	mov	r0, r2
    342e:	734b      	strb	r3, [r1, #13]
    3430:	f850 3f20 	ldr.w	r3, [r0, #32]!
 */

static inline sys_dnode_t *sys_dlist_peek_next(sys_dlist_t *list,
					       sys_dnode_t *node)
{
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3434:	6a55      	ldr	r5, [r2, #36]	; 0x24
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3436:	4283      	cmp	r3, r0
    3438:	bf08      	it	eq
    343a:	2300      	moveq	r3, #0
    343c:	2b00      	cmp	r3, #0
    343e:	bf38      	it	cc
    3440:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3442:	b1cb      	cbz	r3, 3478 <move_thread_to_end_of_prio_q+0x6c>
	int32_t b1 = thread_1->base.prio;
    3444:	f991 600e 	ldrsb.w	r6, [r1, #14]
	int32_t b2 = thread_2->base.prio;
    3448:	f993 400e 	ldrsb.w	r4, [r3, #14]
	if (b1 != b2) {
    344c:	42a6      	cmp	r6, r4
    344e:	d00f      	beq.n	3470 <move_thread_to_end_of_prio_q+0x64>
		return b2 - b1;
    3450:	1ba4      	subs	r4, r4, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    3452:	2c00      	cmp	r4, #0
    3454:	dd0c      	ble.n	3470 <move_thread_to_end_of_prio_q+0x64>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    3456:	6858      	ldr	r0, [r3, #4]

	node->prev = prev;
	node->next = successor;
    3458:	e9c1 3000 	strd	r3, r0, [r1]
	prev->next = node;
    345c:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    345e:	6059      	str	r1, [r3, #4]
	update_cache(thread == _current);
    3460:	6890      	ldr	r0, [r2, #8]
    3462:	1a43      	subs	r3, r0, r1
    3464:	4258      	negs	r0, r3
}
    3466:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    346a:	4158      	adcs	r0, r3
    346c:	f7ff bfae 	b.w	33cc <update_cache>
	return (node == list->tail) ? NULL : node->next;
    3470:	42ab      	cmp	r3, r5
    3472:	d001      	beq.n	3478 <move_thread_to_end_of_prio_q+0x6c>
    3474:	681b      	ldr	r3, [r3, #0]
    3476:	e7e4      	b.n	3442 <move_thread_to_end_of_prio_q+0x36>
	node->prev = tail;
    3478:	e9c1 0500 	strd	r0, r5, [r1]
	tail->next = node;
    347c:	6029      	str	r1, [r5, #0]
	list->tail = node;
    347e:	6251      	str	r1, [r2, #36]	; 0x24
}
    3480:	e7ee      	b.n	3460 <move_thread_to_end_of_prio_q+0x54>
    3482:	bf00      	nop
    3484:	20000934 	.word	0x20000934

00003488 <z_time_slice>:
{
    3488:	b570      	push	{r4, r5, r6, lr}
    348a:	4601      	mov	r1, r0
	__asm__ volatile(
    348c:	f04f 0320 	mov.w	r3, #32
    3490:	f3ef 8411 	mrs	r4, BASEPRI
    3494:	f383 8812 	msr	BASEPRI_MAX, r3
    3498:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    349c:	4b16      	ldr	r3, [pc, #88]	; (34f8 <z_time_slice+0x70>)
    349e:	4a17      	ldr	r2, [pc, #92]	; (34fc <z_time_slice+0x74>)
    34a0:	6898      	ldr	r0, [r3, #8]
    34a2:	6815      	ldr	r5, [r2, #0]
    34a4:	42a8      	cmp	r0, r5
    34a6:	461d      	mov	r5, r3
    34a8:	d106      	bne.n	34b8 <z_time_slice+0x30>
			z_reset_time_slice();
    34aa:	f7ff ff21 	bl	32f0 <z_reset_time_slice>
	__asm__ volatile(
    34ae:	f384 8811 	msr	BASEPRI, r4
    34b2:	f3bf 8f6f 	isb	sy
}
    34b6:	bd70      	pop	{r4, r5, r6, pc}
	pending_current = NULL;
    34b8:	2600      	movs	r6, #0
    34ba:	6016      	str	r6, [r2, #0]
	if (slice_time && sliceable(_current)) {
    34bc:	4a10      	ldr	r2, [pc, #64]	; (3500 <z_time_slice+0x78>)
    34be:	6812      	ldr	r2, [r2, #0]
    34c0:	b1ba      	cbz	r2, 34f2 <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    34c2:	89c2      	ldrh	r2, [r0, #14]
    34c4:	2a7f      	cmp	r2, #127	; 0x7f
    34c6:	d814      	bhi.n	34f2 <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
    34c8:	7b42      	ldrb	r2, [r0, #13]
    34ca:	06d2      	lsls	r2, r2, #27
    34cc:	d111      	bne.n	34f2 <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    34ce:	4a0d      	ldr	r2, [pc, #52]	; (3504 <z_time_slice+0x7c>)
    34d0:	f990 600e 	ldrsb.w	r6, [r0, #14]
    34d4:	6812      	ldr	r2, [r2, #0]
    34d6:	4296      	cmp	r6, r2
    34d8:	db0b      	blt.n	34f2 <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    34da:	4a0b      	ldr	r2, [pc, #44]	; (3508 <z_time_slice+0x80>)
    34dc:	4290      	cmp	r0, r2
    34de:	d008      	beq.n	34f2 <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
    34e0:	691a      	ldr	r2, [r3, #16]
    34e2:	428a      	cmp	r2, r1
    34e4:	dc02      	bgt.n	34ec <z_time_slice+0x64>
			move_thread_to_end_of_prio_q(_current);
    34e6:	f7ff ff91 	bl	340c <move_thread_to_end_of_prio_q>
    34ea:	e7de      	b.n	34aa <z_time_slice+0x22>
			_current_cpu->slice_ticks -= ticks;
    34ec:	1a52      	subs	r2, r2, r1
    34ee:	611a      	str	r2, [r3, #16]
    34f0:	e7dd      	b.n	34ae <z_time_slice+0x26>
		_current_cpu->slice_ticks = 0;
    34f2:	2300      	movs	r3, #0
    34f4:	612b      	str	r3, [r5, #16]
    34f6:	e7da      	b.n	34ae <z_time_slice+0x26>
    34f8:	20000934 	.word	0x20000934
    34fc:	2000095c 	.word	0x2000095c
    3500:	20000964 	.word	0x20000964
    3504:	20000960 	.word	0x20000960
    3508:	20000130 	.word	0x20000130

0000350c <ready_thread>:
{
    350c:	b470      	push	{r4, r5, r6}
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    350e:	f990 300d 	ldrsb.w	r3, [r0, #13]
    3512:	7b42      	ldrb	r2, [r0, #13]
    3514:	2b00      	cmp	r3, #0
    3516:	db2d      	blt.n	3574 <ready_thread+0x68>
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    3518:	06d3      	lsls	r3, r2, #27
    351a:	d12b      	bne.n	3574 <ready_thread+0x68>
	return !sys_dnode_is_linked(&to->node);
    351c:	6983      	ldr	r3, [r0, #24]
    351e:	bb4b      	cbnz	r3, 3574 <ready_thread+0x68>
	return list->head == list;
    3520:	4915      	ldr	r1, [pc, #84]	; (3578 <ready_thread+0x6c>)
	thread->base.thread_state |= _THREAD_QUEUED;
    3522:	f062 027f 	orn	r2, r2, #127	; 0x7f
    3526:	7342      	strb	r2, [r0, #13]
    3528:	460a      	mov	r2, r1
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    352a:	6a4d      	ldr	r5, [r1, #36]	; 0x24
	return list->head == list;
    352c:	f852 4f20 	ldr.w	r4, [r2, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3530:	4294      	cmp	r4, r2
    3532:	bf18      	it	ne
    3534:	4623      	movne	r3, r4
    3536:	2b00      	cmp	r3, #0
    3538:	bf38      	it	cc
    353a:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    353c:	b1ab      	cbz	r3, 356a <ready_thread+0x5e>
	int32_t b1 = thread_1->base.prio;
    353e:	f990 600e 	ldrsb.w	r6, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    3542:	f993 400e 	ldrsb.w	r4, [r3, #14]
	if (b1 != b2) {
    3546:	42a6      	cmp	r6, r4
    3548:	d00b      	beq.n	3562 <ready_thread+0x56>
		return b2 - b1;
    354a:	1ba4      	subs	r4, r4, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    354c:	2c00      	cmp	r4, #0
    354e:	dd08      	ble.n	3562 <ready_thread+0x56>
	sys_dnode_t *const prev = successor->prev;
    3550:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    3552:	e9c0 3200 	strd	r3, r2, [r0]
	prev->next = node;
    3556:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    3558:	6058      	str	r0, [r3, #4]
}
    355a:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    355c:	2000      	movs	r0, #0
    355e:	f7ff bf35 	b.w	33cc <update_cache>
	return (node == list->tail) ? NULL : node->next;
    3562:	42ab      	cmp	r3, r5
    3564:	d001      	beq.n	356a <ready_thread+0x5e>
    3566:	681b      	ldr	r3, [r3, #0]
    3568:	e7e8      	b.n	353c <ready_thread+0x30>
	node->prev = tail;
    356a:	e9c0 2500 	strd	r2, r5, [r0]
	tail->next = node;
    356e:	6028      	str	r0, [r5, #0]
	list->tail = node;
    3570:	6248      	str	r0, [r1, #36]	; 0x24
}
    3572:	e7f2      	b.n	355a <ready_thread+0x4e>
}
    3574:	bc70      	pop	{r4, r5, r6}
    3576:	4770      	bx	lr
    3578:	20000934 	.word	0x20000934

0000357c <z_sched_start>:
{
    357c:	b510      	push	{r4, lr}
	__asm__ volatile(
    357e:	f04f 0220 	mov.w	r2, #32
    3582:	f3ef 8411 	mrs	r4, BASEPRI
    3586:	f382 8812 	msr	BASEPRI_MAX, r2
    358a:	f3bf 8f6f 	isb	sy
	if (z_has_thread_started(thread)) {
    358e:	7b42      	ldrb	r2, [r0, #13]
    3590:	0751      	lsls	r1, r2, #29
    3592:	d404      	bmi.n	359e <z_sched_start+0x22>
	__asm__ volatile(
    3594:	f384 8811 	msr	BASEPRI, r4
    3598:	f3bf 8f6f 	isb	sy
}
    359c:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    359e:	f022 0204 	bic.w	r2, r2, #4
    35a2:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    35a4:	f7ff ffb2 	bl	350c <ready_thread>
	z_reschedule(&sched_spinlock, key);
    35a8:	4621      	mov	r1, r4
    35aa:	4802      	ldr	r0, [pc, #8]	; (35b4 <z_sched_start+0x38>)
}
    35ac:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    35b0:	f7ff bee6 	b.w	3380 <z_reschedule>
    35b4:	20000d97 	.word	0x20000d97

000035b8 <unready_thread>:
{
    35b8:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    35ba:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return z_is_thread_state_set(thread, _THREAD_QUEUED);
    35be:	7b43      	ldrb	r3, [r0, #13]
    35c0:	2a00      	cmp	r2, #0
{
    35c2:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    35c4:	da04      	bge.n	35d0 <unready_thread+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    35c6:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    35ca:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    35cc:	f001 f92e 	bl	482c <sys_dlist_remove>
	update_cache(thread == _current);
    35d0:	4b04      	ldr	r3, [pc, #16]	; (35e4 <unready_thread+0x2c>)
    35d2:	6898      	ldr	r0, [r3, #8]
    35d4:	1a43      	subs	r3, r0, r1
    35d6:	4258      	negs	r0, r3
    35d8:	4158      	adcs	r0, r3
}
    35da:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    35de:	f7ff bef5 	b.w	33cc <update_cache>
    35e2:	bf00      	nop
    35e4:	20000934 	.word	0x20000934

000035e8 <pend>:
{
    35e8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    35ec:	4606      	mov	r6, r0
    35ee:	4614      	mov	r4, r2
    35f0:	461d      	mov	r5, r3
	__asm__ volatile(
    35f2:	f04f 0320 	mov.w	r3, #32
    35f6:	f3ef 8711 	mrs	r7, BASEPRI
    35fa:	f383 8812 	msr	BASEPRI_MAX, r3
    35fe:	f3bf 8f6f 	isb	sy
		add_to_waitq_locked(thread, wait_q);
    3602:	f001 f977 	bl	48f4 <add_to_waitq_locked>
	__asm__ volatile(
    3606:	f387 8811 	msr	BASEPRI, r7
    360a:	f3bf 8f6f 	isb	sy
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    360e:	1c6b      	adds	r3, r5, #1
    3610:	bf08      	it	eq
    3612:	f1b4 3fff 	cmpeq.w	r4, #4294967295
    3616:	d008      	beq.n	362a <pend+0x42>
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    3618:	4622      	mov	r2, r4
    361a:	462b      	mov	r3, r5
    361c:	f106 0018 	add.w	r0, r6, #24
    3620:	4903      	ldr	r1, [pc, #12]	; (3630 <pend+0x48>)
}
    3622:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    3626:	f000 ba29 	b.w	3a7c <z_add_timeout>
    362a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    362e:	bf00      	nop
    3630:	000048b1 	.word	0x000048b1

00003634 <z_pend_curr>:
{
    3634:	b510      	push	{r4, lr}
	pending_current = _current;
    3636:	4b07      	ldr	r3, [pc, #28]	; (3654 <z_pend_curr+0x20>)
    3638:	6898      	ldr	r0, [r3, #8]
    363a:	4b07      	ldr	r3, [pc, #28]	; (3658 <z_pend_curr+0x24>)
{
    363c:	460c      	mov	r4, r1
	pending_current = _current;
    363e:	6018      	str	r0, [r3, #0]
{
    3640:	4611      	mov	r1, r2
	pend(_current, wait_q, timeout);
    3642:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    3646:	f7ff ffcf 	bl	35e8 <pend>
    364a:	4620      	mov	r0, r4
}
    364c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    3650:	f7fd bda2 	b.w	1198 <arch_swap>
    3654:	20000934 	.word	0x20000934
    3658:	2000095c 	.word	0x2000095c

0000365c <z_set_prio>:
{
    365c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    365e:	4604      	mov	r4, r0
	__asm__ volatile(
    3660:	f04f 0320 	mov.w	r3, #32
    3664:	f3ef 8611 	mrs	r6, BASEPRI
    3668:	f383 8812 	msr	BASEPRI_MAX, r3
    366c:	f3bf 8f6f 	isb	sy
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    3670:	7b43      	ldrb	r3, [r0, #13]
    3672:	06da      	lsls	r2, r3, #27
    3674:	b249      	sxtb	r1, r1
    3676:	d138      	bne.n	36ea <z_set_prio+0x8e>
	return !sys_dnode_is_linked(&to->node);
    3678:	6985      	ldr	r5, [r0, #24]
		if (need_sched) {
    367a:	2d00      	cmp	r5, #0
    367c:	d135      	bne.n	36ea <z_set_prio+0x8e>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    367e:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3682:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    3684:	f001 f8d2 	bl	482c <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    3688:	7b43      	ldrb	r3, [r0, #13]
				thread->base.prio = prio;
    368a:	7381      	strb	r1, [r0, #14]
	thread->base.thread_state |= _THREAD_QUEUED;
    368c:	f063 037f 	orn	r3, r3, #127	; 0x7f
    3690:	7343      	strb	r3, [r0, #13]
	return list->head == list;
    3692:	4817      	ldr	r0, [pc, #92]	; (36f0 <z_set_prio+0x94>)
    3694:	4603      	mov	r3, r0
    3696:	f853 7f20 	ldr.w	r7, [r3, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    369a:	429f      	cmp	r7, r3
    369c:	bf18      	it	ne
    369e:	463d      	movne	r5, r7
    36a0:	2d00      	cmp	r5, #0
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    36a2:	6a47      	ldr	r7, [r0, #36]	; 0x24
    36a4:	461a      	mov	r2, r3
    36a6:	462b      	mov	r3, r5
    36a8:	bf38      	it	cc
    36aa:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    36ac:	b1c3      	cbz	r3, 36e0 <z_set_prio+0x84>
	int32_t b2 = thread_2->base.prio;
    36ae:	f993 500e 	ldrsb.w	r5, [r3, #14]
	if (b1 != b2) {
    36b2:	42a9      	cmp	r1, r5
    36b4:	d010      	beq.n	36d8 <z_set_prio+0x7c>
		return b2 - b1;
    36b6:	1a6d      	subs	r5, r5, r1
		if (z_sched_prio_cmp(thread, t) > 0) {
    36b8:	2d00      	cmp	r5, #0
    36ba:	dd0d      	ble.n	36d8 <z_set_prio+0x7c>
	sys_dnode_t *const prev = successor->prev;
    36bc:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    36be:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    36c2:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    36c4:	605c      	str	r4, [r3, #4]
			update_cache(1);
    36c6:	2001      	movs	r0, #1
    36c8:	f7ff fe80 	bl	33cc <update_cache>
    36cc:	2001      	movs	r0, #1
	__asm__ volatile(
    36ce:	f386 8811 	msr	BASEPRI, r6
    36d2:	f3bf 8f6f 	isb	sy
}
    36d6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return (node == list->tail) ? NULL : node->next;
    36d8:	42bb      	cmp	r3, r7
    36da:	d001      	beq.n	36e0 <z_set_prio+0x84>
    36dc:	681b      	ldr	r3, [r3, #0]
    36de:	e7e5      	b.n	36ac <z_set_prio+0x50>
	node->prev = tail;
    36e0:	e9c4 2700 	strd	r2, r7, [r4]
	tail->next = node;
    36e4:	603c      	str	r4, [r7, #0]
	list->tail = node;
    36e6:	6244      	str	r4, [r0, #36]	; 0x24
}
    36e8:	e7ed      	b.n	36c6 <z_set_prio+0x6a>
			thread->base.prio = prio;
    36ea:	73a1      	strb	r1, [r4, #14]
    36ec:	2000      	movs	r0, #0
    36ee:	e7ee      	b.n	36ce <z_set_prio+0x72>
    36f0:	20000934 	.word	0x20000934

000036f4 <z_impl_k_thread_suspend>:
{
    36f4:	b570      	push	{r4, r5, r6, lr}
    36f6:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    36f8:	3018      	adds	r0, #24
    36fa:	f001 f940 	bl	497e <z_abort_timeout>
	__asm__ volatile(
    36fe:	f04f 0320 	mov.w	r3, #32
    3702:	f3ef 8611 	mrs	r6, BASEPRI
    3706:	f383 8812 	msr	BASEPRI_MAX, r3
    370a:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    370e:	f994 200d 	ldrsb.w	r2, [r4, #13]
	return z_is_thread_state_set(thread, _THREAD_QUEUED);
    3712:	7b63      	ldrb	r3, [r4, #13]
    3714:	2a00      	cmp	r2, #0
    3716:	da05      	bge.n	3724 <z_impl_k_thread_suspend+0x30>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3718:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    371c:	7363      	strb	r3, [r4, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    371e:	4620      	mov	r0, r4
    3720:	f001 f884 	bl	482c <sys_dlist_remove>
		update_cache(thread == _current);
    3724:	4d0b      	ldr	r5, [pc, #44]	; (3754 <z_impl_k_thread_suspend+0x60>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    3726:	7b63      	ldrb	r3, [r4, #13]
    3728:	68a8      	ldr	r0, [r5, #8]
    372a:	f043 0310 	orr.w	r3, r3, #16
    372e:	7363      	strb	r3, [r4, #13]
    3730:	1b03      	subs	r3, r0, r4
    3732:	4258      	negs	r0, r3
    3734:	4158      	adcs	r0, r3
    3736:	f7ff fe49 	bl	33cc <update_cache>
	__asm__ volatile(
    373a:	f386 8811 	msr	BASEPRI, r6
    373e:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    3742:	68ab      	ldr	r3, [r5, #8]
    3744:	42a3      	cmp	r3, r4
    3746:	d103      	bne.n	3750 <z_impl_k_thread_suspend+0x5c>
}
    3748:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    374c:	f001 b88c 	b.w	4868 <z_reschedule_unlocked>
}
    3750:	bd70      	pop	{r4, r5, r6, pc}
    3752:	bf00      	nop
    3754:	20000934 	.word	0x20000934

00003758 <k_sched_unlock>:
{
    3758:	b510      	push	{r4, lr}
	__asm__ volatile(
    375a:	f04f 0320 	mov.w	r3, #32
    375e:	f3ef 8411 	mrs	r4, BASEPRI
    3762:	f383 8812 	msr	BASEPRI_MAX, r3
    3766:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    376a:	4b08      	ldr	r3, [pc, #32]	; (378c <k_sched_unlock+0x34>)
    376c:	689a      	ldr	r2, [r3, #8]
    376e:	7bd3      	ldrb	r3, [r2, #15]
    3770:	3301      	adds	r3, #1
    3772:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    3774:	2000      	movs	r0, #0
    3776:	f7ff fe29 	bl	33cc <update_cache>
	__asm__ volatile(
    377a:	f384 8811 	msr	BASEPRI, r4
    377e:	f3bf 8f6f 	isb	sy
}
    3782:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    3786:	f001 b86f 	b.w	4868 <z_reschedule_unlocked>
    378a:	bf00      	nop
    378c:	20000934 	.word	0x20000934

00003790 <z_sched_init>:
	list->head = (sys_dnode_t *)list;
    3790:	4b04      	ldr	r3, [pc, #16]	; (37a4 <z_sched_init+0x14>)
		sys_dlist_init(&_kernel.ready_q.runq.queues[i]);
	}
#endif

#ifdef CONFIG_TIMESLICING
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    3792:	2100      	movs	r1, #0
    3794:	f103 0220 	add.w	r2, r3, #32
	list->tail = (sys_dnode_t *)list;
    3798:	e9c3 2208 	strd	r2, r2, [r3, #32]
    379c:	4608      	mov	r0, r1
    379e:	f7ff bdbd 	b.w	331c <k_sched_time_slice_set>
    37a2:	bf00      	nop
    37a4:	20000934 	.word	0x20000934

000037a8 <z_impl_k_yield>:
#include <syscalls/k_thread_deadline_set_mrsh.c>
#endif
#endif

void z_impl_k_yield(void)
{
    37a8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	__asm__ volatile(
    37aa:	f04f 0320 	mov.w	r3, #32
    37ae:	f3ef 8411 	mrs	r4, BASEPRI
    37b2:	f383 8812 	msr	BASEPRI_MAX, r3
    37b6:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if (!IS_ENABLED(CONFIG_SMP) ||
	    z_is_thread_queued(_current)) {
		dequeue_thread(&_kernel.ready_q.runq,
    37ba:	491b      	ldr	r1, [pc, #108]	; (3828 <z_impl_k_yield+0x80>)
    37bc:	6888      	ldr	r0, [r1, #8]
	thread->base.thread_state &= ~_THREAD_QUEUED;
    37be:	7b43      	ldrb	r3, [r0, #13]
    37c0:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    37c4:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    37c6:	f001 f831 	bl	482c <sys_dlist_remove>
			       _current);
	}
	queue_thread(&_kernel.ready_q.runq, _current);
    37ca:	688a      	ldr	r2, [r1, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    37cc:	7b53      	ldrb	r3, [r2, #13]
	return list->head == list;
    37ce:	4608      	mov	r0, r1
    37d0:	f063 037f 	orn	r3, r3, #127	; 0x7f
    37d4:	7353      	strb	r3, [r2, #13]
    37d6:	f850 3f20 	ldr.w	r3, [r0, #32]!
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    37da:	6a4e      	ldr	r6, [r1, #36]	; 0x24
	return sys_dlist_is_empty(list) ? NULL : list->head;
    37dc:	4283      	cmp	r3, r0
    37de:	bf08      	it	eq
    37e0:	2300      	moveq	r3, #0
    37e2:	2b00      	cmp	r3, #0
    37e4:	bf38      	it	cc
    37e6:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    37e8:	b1cb      	cbz	r3, 381e <z_impl_k_yield+0x76>
	int32_t b1 = thread_1->base.prio;
    37ea:	f992 700e 	ldrsb.w	r7, [r2, #14]
	int32_t b2 = thread_2->base.prio;
    37ee:	f993 500e 	ldrsb.w	r5, [r3, #14]
	if (b1 != b2) {
    37f2:	42af      	cmp	r7, r5
    37f4:	d00f      	beq.n	3816 <z_impl_k_yield+0x6e>
		return b2 - b1;
    37f6:	1bed      	subs	r5, r5, r7
		if (z_sched_prio_cmp(thread, t) > 0) {
    37f8:	2d00      	cmp	r5, #0
    37fa:	dd0c      	ble.n	3816 <z_impl_k_yield+0x6e>
	sys_dnode_t *const prev = successor->prev;
    37fc:	6859      	ldr	r1, [r3, #4]
	node->next = successor;
    37fe:	e9c2 3100 	strd	r3, r1, [r2]
	prev->next = node;
    3802:	600a      	str	r2, [r1, #0]
	successor->prev = node;
    3804:	605a      	str	r2, [r3, #4]
	update_cache(1);
    3806:	2001      	movs	r0, #1
    3808:	f7ff fde0 	bl	33cc <update_cache>
    380c:	4620      	mov	r0, r4
	z_swap(&sched_spinlock, key);
}
    380e:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    3812:	f7fd bcc1 	b.w	1198 <arch_swap>
	return (node == list->tail) ? NULL : node->next;
    3816:	42b3      	cmp	r3, r6
    3818:	d001      	beq.n	381e <z_impl_k_yield+0x76>
    381a:	681b      	ldr	r3, [r3, #0]
    381c:	e7e4      	b.n	37e8 <z_impl_k_yield+0x40>
	node->prev = tail;
    381e:	e9c2 0600 	strd	r0, r6, [r2]
	tail->next = node;
    3822:	6032      	str	r2, [r6, #0]
	list->tail = node;
    3824:	624a      	str	r2, [r1, #36]	; 0x24
}
    3826:	e7ee      	b.n	3806 <z_impl_k_yield+0x5e>
    3828:	20000934 	.word	0x20000934

0000382c <z_tick_sleep>:
}
#include <syscalls/k_yield_mrsh.c>
#endif

static int32_t z_tick_sleep(k_ticks_t ticks)
{
    382c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3830:	4604      	mov	r4, r0
    3832:	460d      	mov	r5, r1
	 */
	LOG_DBG("thread %p for %u ticks", _current, ticks);
#endif

	/* wait of 0 ms is treated as a 'yield' */
	if (ticks == 0) {
    3834:	ea54 0105 	orrs.w	r1, r4, r5
    3838:	d104      	bne.n	3844 <z_tick_sleep+0x18>
	z_impl_k_yield();
    383a:	f7ff ffb5 	bl	37a8 <z_impl_k_yield>
		k_yield();
		return 0;
    383e:	2000      	movs	r0, #0
		return ticks;
	}
#endif

	return 0;
}
    3840:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if (Z_TICK_ABS(ticks) <= 0) {
    3844:	f06f 0101 	mvn.w	r1, #1
    3848:	1a0a      	subs	r2, r1, r0
    384a:	f04f 31ff 	mov.w	r1, #4294967295
    384e:	eb61 0305 	sbc.w	r3, r1, r5
    3852:	2a01      	cmp	r2, #1
    3854:	f173 0300 	sbcs.w	r3, r3, #0
    3858:	da2a      	bge.n	38b0 <z_tick_sleep+0x84>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    385a:	f001 f8d0 	bl	49fe <sys_clock_tick_get_32>
    385e:	1906      	adds	r6, r0, r4
    3860:	f04f 0320 	mov.w	r3, #32
    3864:	f3ef 8811 	mrs	r8, BASEPRI
    3868:	f383 8812 	msr	BASEPRI_MAX, r3
    386c:	f3bf 8f6f 	isb	sy
	pending_current = _current;
    3870:	4f11      	ldr	r7, [pc, #68]	; (38b8 <z_tick_sleep+0x8c>)
    3872:	4b12      	ldr	r3, [pc, #72]	; (38bc <z_tick_sleep+0x90>)
    3874:	68b8      	ldr	r0, [r7, #8]
    3876:	6018      	str	r0, [r3, #0]
	unready_thread(_current);
    3878:	f7ff fe9e 	bl	35b8 <unready_thread>
	z_add_thread_timeout(_current, timeout);
    387c:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    387e:	4910      	ldr	r1, [pc, #64]	; (38c0 <z_tick_sleep+0x94>)
    3880:	4622      	mov	r2, r4
    3882:	462b      	mov	r3, r5
    3884:	3018      	adds	r0, #24
    3886:	f000 f8f9 	bl	3a7c <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    388a:	68ba      	ldr	r2, [r7, #8]
    388c:	7b53      	ldrb	r3, [r2, #13]
    388e:	f043 0310 	orr.w	r3, r3, #16
    3892:	7353      	strb	r3, [r2, #13]
    3894:	4640      	mov	r0, r8
    3896:	f7fd fc7f 	bl	1198 <arch_swap>
	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    389a:	f001 f8b0 	bl	49fe <sys_clock_tick_get_32>
    389e:	1a30      	subs	r0, r6, r0
    38a0:	eb66 0106 	sbc.w	r1, r6, r6
	if (ticks > 0) {
    38a4:	2801      	cmp	r0, #1
    38a6:	f171 0300 	sbcs.w	r3, r1, #0
		return ticks;
    38aa:	bfb8      	it	lt
    38ac:	2000      	movlt	r0, #0
    38ae:	e7c7      	b.n	3840 <z_tick_sleep+0x14>
		expected_wakeup_ticks = Z_TICK_ABS(ticks);
    38b0:	f06f 0601 	mvn.w	r6, #1
    38b4:	1a36      	subs	r6, r6, r0
    38b6:	e7d3      	b.n	3860 <z_tick_sleep+0x34>
    38b8:	20000934 	.word	0x20000934
    38bc:	2000095c 	.word	0x2000095c
    38c0:	000048b1 	.word	0x000048b1

000038c4 <z_impl_k_sleep>:

int32_t z_impl_k_sleep(k_timeout_t timeout)
{
    38c4:	b508      	push	{r3, lr}
    38c6:	460b      	mov	r3, r1
	__ASSERT(!arch_is_in_isr(), "");

	SYS_PORT_TRACING_FUNC_ENTER(k_thread, sleep, timeout);

	/* in case of K_FOREVER, we suspend */
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    38c8:	3301      	adds	r3, #1
    38ca:	bf08      	it	eq
    38cc:	f1b0 3fff 	cmpeq.w	r0, #4294967295
    38d0:	d106      	bne.n	38e0 <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
    38d2:	4b08      	ldr	r3, [pc, #32]	; (38f4 <z_impl_k_sleep+0x30>)
    38d4:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    38d6:	f7ff ff0d 	bl	36f4 <z_impl_k_thread_suspend>

		SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER);

		return (int32_t) K_TICKS_FOREVER;
    38da:	f04f 30ff 	mov.w	r0, #4294967295
	int32_t ret = k_ticks_to_ms_floor64(ticks);

	SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ret);

	return ret;
}
    38de:	bd08      	pop	{r3, pc}
	ticks = z_tick_sleep(ticks);
    38e0:	f7ff ffa4 	bl	382c <z_tick_sleep>
			return (t * to_hz + off) / from_hz;
    38e4:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    38e8:	fb80 2303 	smull	r2, r3, r0, r3
    38ec:	0bd0      	lsrs	r0, r2, #15
    38ee:	ea40 4043 	orr.w	r0, r0, r3, lsl #17
	return ret;
    38f2:	e7f4      	b.n	38de <z_impl_k_sleep+0x1a>
    38f4:	20000934 	.word	0x20000934

000038f8 <z_impl_z_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    38f8:	4b01      	ldr	r3, [pc, #4]	; (3900 <z_impl_z_current_get+0x8>)
    38fa:	6898      	ldr	r0, [r3, #8]
    38fc:	4770      	bx	lr
    38fe:	bf00      	nop
    3900:	20000934 	.word	0x20000934

00003904 <z_thread_abort>:
#endif
	}
}

void z_thread_abort(struct k_thread *thread)
{
    3904:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3908:	4604      	mov	r4, r0
    390a:	f04f 0320 	mov.w	r3, #32
    390e:	f3ef 8611 	mrs	r6, BASEPRI
    3912:	f383 8812 	msr	BASEPRI_MAX, r3
    3916:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    391a:	7b43      	ldrb	r3, [r0, #13]
    391c:	071a      	lsls	r2, r3, #28
    391e:	d505      	bpl.n	392c <z_thread_abort+0x28>
	__asm__ volatile(
    3920:	f386 8811 	msr	BASEPRI, r6
    3924:	f3bf 8f6f 	isb	sy
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
	}
	k_spin_unlock(&sched_spinlock, key);
}
    3928:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		thread->base.thread_state &= ~_THREAD_ABORTING;
    392c:	f023 0220 	bic.w	r2, r3, #32
    3930:	f042 0108 	orr.w	r1, r2, #8
		if (z_is_thread_queued(thread)) {
    3934:	09d2      	lsrs	r2, r2, #7
    3936:	d120      	bne.n	397a <z_thread_abort+0x76>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    3938:	7341      	strb	r1, [r0, #13]
		if (thread->base.pended_on != NULL) {
    393a:	68a3      	ldr	r3, [r4, #8]
    393c:	b113      	cbz	r3, 3944 <z_thread_abort+0x40>
			unpend_thread_no_timeout(thread);
    393e:	4620      	mov	r0, r4
    3940:	f000 ff7c 	bl	483c <unpend_thread_no_timeout>
	return z_abort_timeout(&thread->base.timeout);
    3944:	f104 0018 	add.w	r0, r4, #24
    3948:	f001 f819 	bl	497e <z_abort_timeout>
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    394c:	f104 0758 	add.w	r7, r4, #88	; 0x58
    3950:	f04f 0800 	mov.w	r8, #0
	return list->head == list;
    3954:	6da5      	ldr	r5, [r4, #88]	; 0x58
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3956:	42bd      	cmp	r5, r7
    3958:	d000      	beq.n	395c <z_thread_abort+0x58>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    395a:	b9b5      	cbnz	r5, 398a <z_thread_abort+0x86>
		update_cache(1);
    395c:	2001      	movs	r0, #1
    395e:	f7ff fd35 	bl	33cc <update_cache>
	if (thread == _current && !arch_is_in_isr()) {
    3962:	4b10      	ldr	r3, [pc, #64]	; (39a4 <z_thread_abort+0xa0>)
    3964:	689b      	ldr	r3, [r3, #8]
    3966:	42a3      	cmp	r3, r4
    3968:	d1da      	bne.n	3920 <z_thread_abort+0x1c>
    396a:	f3ef 8305 	mrs	r3, IPSR
    396e:	2b00      	cmp	r3, #0
    3970:	d1d6      	bne.n	3920 <z_thread_abort+0x1c>
    3972:	4630      	mov	r0, r6
    3974:	f7fd fc10 	bl	1198 <arch_swap>
	return ret;
    3978:	e7d2      	b.n	3920 <z_thread_abort+0x1c>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    397a:	f003 035f 	and.w	r3, r3, #95	; 0x5f
    397e:	f043 0308 	orr.w	r3, r3, #8
    3982:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    3984:	f000 ff52 	bl	482c <sys_dlist_remove>
}
    3988:	e7d7      	b.n	393a <z_thread_abort+0x36>
		unpend_thread_no_timeout(thread);
    398a:	4628      	mov	r0, r5
    398c:	f000 ff56 	bl	483c <unpend_thread_no_timeout>
    3990:	f105 0018 	add.w	r0, r5, #24
    3994:	f000 fff3 	bl	497e <z_abort_timeout>
    3998:	f8c5 8078 	str.w	r8, [r5, #120]	; 0x78
		ready_thread(thread);
    399c:	4628      	mov	r0, r5
    399e:	f7ff fdb5 	bl	350c <ready_thread>
    39a2:	e7d7      	b.n	3954 <z_thread_abort+0x50>
    39a4:	20000934 	.word	0x20000934

000039a8 <z_data_copy>:
 * This routine copies the data section from ROM to RAM.
 *
 * @return N/A
 */
void z_data_copy(void)
{
    39a8:	b508      	push	{r3, lr}
	(void)memcpy(&__data_region_start, &__data_region_load_start,
		 __data_region_end - __data_region_start);
    39aa:	4806      	ldr	r0, [pc, #24]	; (39c4 <z_data_copy+0x1c>)
	(void)memcpy(&__data_region_start, &__data_region_load_start,
    39ac:	4a06      	ldr	r2, [pc, #24]	; (39c8 <z_data_copy+0x20>)
    39ae:	4907      	ldr	r1, [pc, #28]	; (39cc <z_data_copy+0x24>)
    39b0:	1a12      	subs	r2, r2, r0
    39b2:	f000 fcd5 	bl	4360 <memcpy>
#else
	(void)memcpy(&_app_smem_start, &_app_smem_rom_start,
		 _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    39b6:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	(void)memcpy(&__ramfunc_start, &__ramfunc_load_start,
    39ba:	4a05      	ldr	r2, [pc, #20]	; (39d0 <z_data_copy+0x28>)
    39bc:	4905      	ldr	r1, [pc, #20]	; (39d4 <z_data_copy+0x2c>)
    39be:	4806      	ldr	r0, [pc, #24]	; (39d8 <z_data_copy+0x30>)
    39c0:	f000 bcce 	b.w	4360 <memcpy>
    39c4:	20000000 	.word	0x20000000
    39c8:	2000010c 	.word	0x2000010c
    39cc:	00004f08 	.word	0x00004f08
    39d0:	00000000 	.word	0x00000000
    39d4:	00004f08 	.word	0x00004f08
    39d8:	20000000 	.word	0x20000000

000039dc <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    39dc:	4b03      	ldr	r3, [pc, #12]	; (39ec <elapsed+0x10>)
    39de:	681b      	ldr	r3, [r3, #0]
    39e0:	b90b      	cbnz	r3, 39e6 <elapsed+0xa>
    39e2:	f7fe bed9 	b.w	2798 <sys_clock_elapsed>
}
    39e6:	2000      	movs	r0, #0
    39e8:	4770      	bx	lr
    39ea:	bf00      	nop
    39ec:	20000968 	.word	0x20000968

000039f0 <remove_timeout>:
{
    39f0:	b530      	push	{r4, r5, lr}
    39f2:	6803      	ldr	r3, [r0, #0]
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    39f4:	b168      	cbz	r0, 3a12 <remove_timeout+0x22>
    39f6:	4a0a      	ldr	r2, [pc, #40]	; (3a20 <remove_timeout+0x30>)
	return (node == list->tail) ? NULL : node->next;
    39f8:	6852      	ldr	r2, [r2, #4]
    39fa:	4290      	cmp	r0, r2
    39fc:	d009      	beq.n	3a12 <remove_timeout+0x22>
	if (next(t) != NULL) {
    39fe:	b143      	cbz	r3, 3a12 <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    3a00:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    3a04:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    3a08:	1912      	adds	r2, r2, r4
    3a0a:	eb45 0101 	adc.w	r1, r5, r1
    3a0e:	e9c3 2104 	strd	r2, r1, [r3, #16]
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
    3a12:	6842      	ldr	r2, [r0, #4]
	sys_dnode_t *const next = node->next;

	prev->next = next;
    3a14:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    3a16:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    3a18:	2300      	movs	r3, #0
	node->prev = NULL;
    3a1a:	e9c0 3300 	strd	r3, r3, [r0]
}
    3a1e:	bd30      	pop	{r4, r5, pc}
    3a20:	20000040 	.word	0x20000040

00003a24 <next_timeout>:

static int32_t next_timeout(void)
{
    3a24:	b538      	push	{r3, r4, r5, lr}
	return list->head == list;
    3a26:	4b13      	ldr	r3, [pc, #76]	; (3a74 <next_timeout+0x50>)
    3a28:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3a2a:	429c      	cmp	r4, r3
    3a2c:	bf08      	it	eq
    3a2e:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    3a30:	f7ff ffd4 	bl	39dc <elapsed>
    3a34:	4605      	mov	r5, r0
	int32_t ret = to == NULL ? MAX_WAIT
    3a36:	b1bc      	cbz	r4, 3a68 <next_timeout+0x44>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    3a38:	e9d4 0104 	ldrd	r0, r1, [r4, #16]
    3a3c:	1b40      	subs	r0, r0, r5
    3a3e:	eb61 71e5 	sbc.w	r1, r1, r5, asr #31
	int32_t ret = to == NULL ? MAX_WAIT
    3a42:	2801      	cmp	r0, #1
    3a44:	f171 0300 	sbcs.w	r3, r1, #0
    3a48:	db11      	blt.n	3a6e <next_timeout+0x4a>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    3a4a:	f06f 4200 	mvn.w	r2, #2147483648	; 0x80000000
    3a4e:	2300      	movs	r3, #0
    3a50:	4282      	cmp	r2, r0
    3a52:	eb73 0401 	sbcs.w	r4, r3, r1
    3a56:	da00      	bge.n	3a5a <next_timeout+0x36>
    3a58:	4610      	mov	r0, r2

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    3a5a:	4b07      	ldr	r3, [pc, #28]	; (3a78 <next_timeout+0x54>)
    3a5c:	691b      	ldr	r3, [r3, #16]
    3a5e:	b113      	cbz	r3, 3a66 <next_timeout+0x42>
    3a60:	4298      	cmp	r0, r3
    3a62:	bfa8      	it	ge
    3a64:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    3a66:	bd38      	pop	{r3, r4, r5, pc}
	int32_t ret = to == NULL ? MAX_WAIT
    3a68:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    3a6c:	e7f5      	b.n	3a5a <next_timeout+0x36>
    3a6e:	2000      	movs	r0, #0
    3a70:	e7f3      	b.n	3a5a <next_timeout+0x36>
    3a72:	bf00      	nop
    3a74:	20000040 	.word	0x20000040
    3a78:	20000934 	.word	0x20000934

00003a7c <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3a7c:	f1b3 3fff 	cmp.w	r3, #4294967295
    3a80:	bf08      	it	eq
    3a82:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    3a86:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3a8a:	4604      	mov	r4, r0
    3a8c:	4692      	mov	sl, r2
    3a8e:	469b      	mov	fp, r3
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3a90:	d073      	beq.n	3b7a <z_add_timeout+0xfe>
#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    3a92:	6081      	str	r1, [r0, #8]
	__asm__ volatile(
    3a94:	f04f 0320 	mov.w	r3, #32
    3a98:	f3ef 8511 	mrs	r5, BASEPRI
    3a9c:	f383 8812 	msr	BASEPRI_MAX, r3
    3aa0:	f3bf 8f6f 	isb	sy

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
		    Z_TICK_ABS(timeout.ticks) >= 0) {
    3aa4:	f06f 0301 	mvn.w	r3, #1
    3aa8:	ebb3 080a 	subs.w	r8, r3, sl
    3aac:	f04f 32ff 	mov.w	r2, #4294967295
    3ab0:	eb62 090b 	sbc.w	r9, r2, fp
		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    3ab4:	f1b8 0f00 	cmp.w	r8, #0
    3ab8:	f179 0100 	sbcs.w	r1, r9, #0
    3abc:	db1c      	blt.n	3af8 <z_add_timeout+0x7c>
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    3abe:	4830      	ldr	r0, [pc, #192]	; (3b80 <z_add_timeout+0x104>)
    3ac0:	e9d0 1000 	ldrd	r1, r0, [r0]
    3ac4:	1a5b      	subs	r3, r3, r1
    3ac6:	eb62 0200 	sbc.w	r2, r2, r0

			to->dticks = MAX(1, ticks);
    3aca:	ebb3 060a 	subs.w	r6, r3, sl
    3ace:	eb62 070b 	sbc.w	r7, r2, fp
    3ad2:	2e01      	cmp	r6, #1
    3ad4:	f177 0300 	sbcs.w	r3, r7, #0
    3ad8:	bfbc      	itt	lt
    3ada:	2601      	movlt	r6, #1
    3adc:	2700      	movlt	r7, #0
    3ade:	e9c4 6704 	strd	r6, r7, [r4, #16]
	return list->head == list;
    3ae2:	4a28      	ldr	r2, [pc, #160]	; (3b84 <z_add_timeout+0x108>)
    3ae4:	e9d2 3c00 	ldrd	r3, ip, [r2]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3ae8:	4293      	cmp	r3, r2
    3aea:	d11e      	bne.n	3b2a <z_add_timeout+0xae>
	node->prev = tail;
    3aec:	e9c4 2c00 	strd	r2, ip, [r4]
	tail->next = node;
    3af0:	f8cc 4000 	str.w	r4, [ip]
	list->tail = node;
    3af4:	6054      	str	r4, [r2, #4]
}
    3af6:	e02d      	b.n	3b54 <z_add_timeout+0xd8>
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
    3af8:	f7ff ff70 	bl	39dc <elapsed>
    3afc:	f11a 0301 	adds.w	r3, sl, #1
    3b00:	9300      	str	r3, [sp, #0]
    3b02:	f14b 0300 	adc.w	r3, fp, #0
    3b06:	9301      	str	r3, [sp, #4]
    3b08:	e9dd 2300 	ldrd	r2, r3, [sp]
    3b0c:	1812      	adds	r2, r2, r0
    3b0e:	eb43 73e0 	adc.w	r3, r3, r0, asr #31
    3b12:	e9c4 2304 	strd	r2, r3, [r4, #16]
    3b16:	e7e4      	b.n	3ae2 <z_add_timeout+0x66>
			if (t->dticks > to->dticks) {
				t->dticks -= to->dticks;
				sys_dlist_insert(&t->node, &to->node);
				break;
			}
			to->dticks -= t->dticks;
    3b18:	ebb6 0008 	subs.w	r0, r6, r8
    3b1c:	eb67 0109 	sbc.w	r1, r7, r9
	return (node == list->tail) ? NULL : node->next;
    3b20:	4563      	cmp	r3, ip
    3b22:	e9c4 0104 	strd	r0, r1, [r4, #16]
    3b26:	d0e1      	beq.n	3aec <z_add_timeout+0x70>
    3b28:	681b      	ldr	r3, [r3, #0]
		for (t = first(); t != NULL; t = next(t)) {
    3b2a:	2b00      	cmp	r3, #0
    3b2c:	d0de      	beq.n	3aec <z_add_timeout+0x70>
			if (t->dticks > to->dticks) {
    3b2e:	e9d3 8904 	ldrd	r8, r9, [r3, #16]
    3b32:	e9d4 6704 	ldrd	r6, r7, [r4, #16]
    3b36:	4546      	cmp	r6, r8
    3b38:	eb77 0109 	sbcs.w	r1, r7, r9
    3b3c:	daec      	bge.n	3b18 <z_add_timeout+0x9c>
				t->dticks -= to->dticks;
    3b3e:	ebb8 0006 	subs.w	r0, r8, r6
    3b42:	eb69 0107 	sbc.w	r1, r9, r7
    3b46:	e9c3 0104 	strd	r0, r1, [r3, #16]
	sys_dnode_t *const prev = successor->prev;
    3b4a:	6859      	ldr	r1, [r3, #4]
	node->next = successor;
    3b4c:	e9c4 3100 	strd	r3, r1, [r4]
	prev->next = node;
    3b50:	600c      	str	r4, [r1, #0]
	successor->prev = node;
    3b52:	605c      	str	r4, [r3, #4]
	return list->head == list;
    3b54:	6813      	ldr	r3, [r2, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3b56:	4293      	cmp	r3, r2
    3b58:	d00b      	beq.n	3b72 <z_add_timeout+0xf6>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    3b5a:	429c      	cmp	r4, r3
    3b5c:	d109      	bne.n	3b72 <z_add_timeout+0xf6>
			 * last announcement, and slice_ticks is based
			 * on that. It means that the time remaining for
			 * the next announcement can be less than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    3b5e:	f7ff ff61 	bl	3a24 <next_timeout>

			if (next_time == 0 ||
    3b62:	b118      	cbz	r0, 3b6c <z_add_timeout+0xf0>
			    _current_cpu->slice_ticks != next_time) {
    3b64:	4b08      	ldr	r3, [pc, #32]	; (3b88 <z_add_timeout+0x10c>)
			if (next_time == 0 ||
    3b66:	691b      	ldr	r3, [r3, #16]
    3b68:	4283      	cmp	r3, r0
    3b6a:	d002      	beq.n	3b72 <z_add_timeout+0xf6>
				sys_clock_set_timeout(next_time, false);
    3b6c:	2100      	movs	r1, #0
    3b6e:	f7fe fde3 	bl	2738 <sys_clock_set_timeout>
	__asm__ volatile(
    3b72:	f385 8811 	msr	BASEPRI, r5
    3b76:	f3bf 8f6f 	isb	sy
#else
			sys_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    3b7a:	b003      	add	sp, #12
    3b7c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    3b80:	20000230 	.word	0x20000230
    3b84:	20000040 	.word	0x20000040
    3b88:	20000934 	.word	0x20000934

00003b8c <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    3b8c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3b90:	4606      	mov	r6, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    3b92:	f7ff fc79 	bl	3488 <z_time_slice>
	__asm__ volatile(
    3b96:	f04f 0320 	mov.w	r3, #32
    3b9a:	f3ef 8411 	mrs	r4, BASEPRI
    3b9e:	f383 8812 	msr	BASEPRI_MAX, r3
    3ba2:	f3bf 8f6f 	isb	sy
#endif

	k_spinlock_key_t key = k_spin_lock(&timeout_lock);

	announce_remaining = ticks;
    3ba6:	4d2c      	ldr	r5, [pc, #176]	; (3c58 <sys_clock_announce+0xcc>)
    3ba8:	f8df a0b0 	ldr.w	sl, [pc, #176]	; 3c5c <sys_clock_announce+0xd0>
	return list->head == list;
    3bac:	f8df b0b0 	ldr.w	fp, [pc, #176]	; 3c60 <sys_clock_announce+0xd4>
    3bb0:	602e      	str	r6, [r5, #0]

	while (first() != NULL && first()->dticks <= announce_remaining) {
    3bb2:	4651      	mov	r1, sl
    3bb4:	f8d5 c000 	ldr.w	ip, [r5]
    3bb8:	f8db 0000 	ldr.w	r0, [fp]
    3bbc:	4662      	mov	r2, ip
    3bbe:	17d3      	asrs	r3, r2, #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3bc0:	4558      	cmp	r0, fp
    3bc2:	e9da 8900 	ldrd	r8, r9, [sl]
    3bc6:	e9cd 2300 	strd	r2, r3, [sp]
    3bca:	d00d      	beq.n	3be8 <sys_clock_announce+0x5c>
    3bcc:	b160      	cbz	r0, 3be8 <sys_clock_announce+0x5c>
    3bce:	e9d0 6704 	ldrd	r6, r7, [r0, #16]
    3bd2:	45b4      	cmp	ip, r6
    3bd4:	41bb      	sbcs	r3, r7
    3bd6:	da1e      	bge.n	3c16 <sys_clock_announce+0x8a>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    3bd8:	9b00      	ldr	r3, [sp, #0]
    3bda:	ebb6 0c03 	subs.w	ip, r6, r3
    3bde:	9b01      	ldr	r3, [sp, #4]
    3be0:	eb67 0603 	sbc.w	r6, r7, r3
    3be4:	e9c0 c604 	strd	ip, r6, [r0, #16]
	}

	curr_tick += announce_remaining;
    3be8:	9b00      	ldr	r3, [sp, #0]
    3bea:	eb13 0208 	adds.w	r2, r3, r8
    3bee:	9b01      	ldr	r3, [sp, #4]
	announce_remaining = 0;
    3bf0:	f04f 0600 	mov.w	r6, #0
	curr_tick += announce_remaining;
    3bf4:	eb43 0309 	adc.w	r3, r3, r9
    3bf8:	e9c1 2300 	strd	r2, r3, [r1]
	announce_remaining = 0;
    3bfc:	602e      	str	r6, [r5, #0]

	sys_clock_set_timeout(next_timeout(), false);
    3bfe:	f7ff ff11 	bl	3a24 <next_timeout>
    3c02:	4631      	mov	r1, r6
    3c04:	f7fe fd98 	bl	2738 <sys_clock_set_timeout>
	__asm__ volatile(
    3c08:	f384 8811 	msr	BASEPRI, r4
    3c0c:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    3c10:	b003      	add	sp, #12
    3c12:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		curr_tick += dt;
    3c16:	eb18 0806 	adds.w	r8, r8, r6
		t->dticks = 0;
    3c1a:	f04f 0200 	mov.w	r2, #0
    3c1e:	f04f 0300 	mov.w	r3, #0
		curr_tick += dt;
    3c22:	eb49 79e6 	adc.w	r9, r9, r6, asr #31
		t->dticks = 0;
    3c26:	e9c0 2304 	strd	r2, r3, [r0, #16]
		announce_remaining -= dt;
    3c2a:	ebac 0606 	sub.w	r6, ip, r6
		curr_tick += dt;
    3c2e:	e9ca 8900 	strd	r8, r9, [sl]
		announce_remaining -= dt;
    3c32:	602e      	str	r6, [r5, #0]
		remove_timeout(t);
    3c34:	f7ff fedc 	bl	39f0 <remove_timeout>
    3c38:	f384 8811 	msr	BASEPRI, r4
    3c3c:	f3bf 8f6f 	isb	sy
		t->fn(t);
    3c40:	6883      	ldr	r3, [r0, #8]
    3c42:	4798      	blx	r3
	__asm__ volatile(
    3c44:	f04f 0320 	mov.w	r3, #32
    3c48:	f3ef 8411 	mrs	r4, BASEPRI
    3c4c:	f383 8812 	msr	BASEPRI_MAX, r3
    3c50:	f3bf 8f6f 	isb	sy

	/* Note that we need to use the underlying arch-specific lock
	 * implementation.  The "irq_lock()" API in SMP context is
	 * actually a wrapper for a global spinlock!
	 */
	k.key = arch_irq_lock();
    3c54:	4901      	ldr	r1, [pc, #4]	; (3c5c <sys_clock_announce+0xd0>)
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    3c56:	e7ad      	b.n	3bb4 <sys_clock_announce+0x28>
    3c58:	20000968 	.word	0x20000968
    3c5c:	20000230 	.word	0x20000230
    3c60:	20000040 	.word	0x20000040

00003c64 <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    3c64:	b510      	push	{r4, lr}
    3c66:	f04f 0320 	mov.w	r3, #32
    3c6a:	f3ef 8411 	mrs	r4, BASEPRI
    3c6e:	f383 8812 	msr	BASEPRI_MAX, r3
    3c72:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + sys_clock_elapsed();
    3c76:	f7fe fd8f 	bl	2798 <sys_clock_elapsed>
    3c7a:	4b06      	ldr	r3, [pc, #24]	; (3c94 <sys_clock_tick_get+0x30>)
    3c7c:	e9d3 2300 	ldrd	r2, r3, [r3]
    3c80:	1812      	adds	r2, r2, r0
    3c82:	f143 0300 	adc.w	r3, r3, #0
	__asm__ volatile(
    3c86:	f384 8811 	msr	BASEPRI, r4
    3c8a:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    3c8e:	4610      	mov	r0, r2
    3c90:	4619      	mov	r1, r3
    3c92:	bd10      	pop	{r4, pc}
    3c94:	20000230 	.word	0x20000230

00003c98 <nrf_cc3xx_platform_init_no_rng>:
    3c98:	b510      	push	{r4, lr}
    3c9a:	4c0a      	ldr	r4, [pc, #40]	; (3cc4 <nrf_cc3xx_platform_init_no_rng+0x2c>)
    3c9c:	6823      	ldr	r3, [r4, #0]
    3c9e:	b11b      	cbz	r3, 3ca8 <nrf_cc3xx_platform_init_no_rng+0x10>
    3ca0:	2301      	movs	r3, #1
    3ca2:	6023      	str	r3, [r4, #0]
    3ca4:	2000      	movs	r0, #0
    3ca6:	bd10      	pop	{r4, pc}
    3ca8:	f000 f8d6 	bl	3e58 <CC_LibInitNoRng>
    3cac:	2800      	cmp	r0, #0
    3cae:	d0f7      	beq.n	3ca0 <nrf_cc3xx_platform_init_no_rng+0x8>
    3cb0:	3801      	subs	r0, #1
    3cb2:	2806      	cmp	r0, #6
    3cb4:	d803      	bhi.n	3cbe <nrf_cc3xx_platform_init_no_rng+0x26>
    3cb6:	4b04      	ldr	r3, [pc, #16]	; (3cc8 <nrf_cc3xx_platform_init_no_rng+0x30>)
    3cb8:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    3cbc:	bd10      	pop	{r4, pc}
    3cbe:	4803      	ldr	r0, [pc, #12]	; (3ccc <nrf_cc3xx_platform_init_no_rng+0x34>)
    3cc0:	bd10      	pop	{r4, pc}
    3cc2:	bf00      	nop
    3cc4:	2000096c 	.word	0x2000096c
    3cc8:	00004da4 	.word	0x00004da4
    3ccc:	ffff8ffe 	.word	0xffff8ffe

00003cd0 <nrf_cc3xx_platform_abort>:
    3cd0:	f3bf 8f4f 	dsb	sy
    3cd4:	4905      	ldr	r1, [pc, #20]	; (3cec <nrf_cc3xx_platform_abort+0x1c>)
    3cd6:	4b06      	ldr	r3, [pc, #24]	; (3cf0 <nrf_cc3xx_platform_abort+0x20>)
    3cd8:	68ca      	ldr	r2, [r1, #12]
    3cda:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    3cde:	4313      	orrs	r3, r2
    3ce0:	60cb      	str	r3, [r1, #12]
    3ce2:	f3bf 8f4f 	dsb	sy
    3ce6:	bf00      	nop
    3ce8:	e7fd      	b.n	3ce6 <nrf_cc3xx_platform_abort+0x16>
    3cea:	bf00      	nop
    3cec:	e000ed00 	.word	0xe000ed00
    3cf0:	05fa0004 	.word	0x05fa0004

00003cf4 <CC_PalAbort>:
    3cf4:	b4f0      	push	{r4, r5, r6, r7}
    3cf6:	4f09      	ldr	r7, [pc, #36]	; (3d1c <CC_PalAbort+0x28>)
    3cf8:	4e09      	ldr	r6, [pc, #36]	; (3d20 <CC_PalAbort+0x2c>)
    3cfa:	4c0a      	ldr	r4, [pc, #40]	; (3d24 <CC_PalAbort+0x30>)
    3cfc:	4a0a      	ldr	r2, [pc, #40]	; (3d28 <CC_PalAbort+0x34>)
    3cfe:	4d0b      	ldr	r5, [pc, #44]	; (3d2c <CC_PalAbort+0x38>)
    3d00:	490b      	ldr	r1, [pc, #44]	; (3d30 <CC_PalAbort+0x3c>)
    3d02:	f04f 33fe 	mov.w	r3, #4278124286	; 0xfefefefe
    3d06:	603b      	str	r3, [r7, #0]
    3d08:	6852      	ldr	r2, [r2, #4]
    3d0a:	6033      	str	r3, [r6, #0]
    3d0c:	6023      	str	r3, [r4, #0]
    3d0e:	2400      	movs	r4, #0
    3d10:	602b      	str	r3, [r5, #0]
    3d12:	f8c1 4500 	str.w	r4, [r1, #1280]	; 0x500
    3d16:	bcf0      	pop	{r4, r5, r6, r7}
    3d18:	4710      	bx	r2
    3d1a:	bf00      	nop
    3d1c:	5002b400 	.word	0x5002b400
    3d20:	5002b404 	.word	0x5002b404
    3d24:	5002b408 	.word	0x5002b408
    3d28:	20000048 	.word	0x20000048
    3d2c:	5002b40c 	.word	0x5002b40c
    3d30:	5002a000 	.word	0x5002a000

00003d34 <nrf_cc3xx_platform_set_abort>:
    3d34:	e9d0 1200 	ldrd	r1, r2, [r0]
    3d38:	4b01      	ldr	r3, [pc, #4]	; (3d40 <nrf_cc3xx_platform_set_abort+0xc>)
    3d3a:	e9c3 1200 	strd	r1, r2, [r3]
    3d3e:	4770      	bx	lr
    3d40:	20000048 	.word	0x20000048

00003d44 <mutex_free>:
    3d44:	b510      	push	{r4, lr}
    3d46:	4604      	mov	r4, r0
    3d48:	b130      	cbz	r0, 3d58 <mutex_free+0x14>
    3d4a:	6863      	ldr	r3, [r4, #4]
    3d4c:	06db      	lsls	r3, r3, #27
    3d4e:	d502      	bpl.n	3d56 <mutex_free+0x12>
    3d50:	2300      	movs	r3, #0
    3d52:	6023      	str	r3, [r4, #0]
    3d54:	6063      	str	r3, [r4, #4]
    3d56:	bd10      	pop	{r4, pc}
    3d58:	4b02      	ldr	r3, [pc, #8]	; (3d64 <mutex_free+0x20>)
    3d5a:	4803      	ldr	r0, [pc, #12]	; (3d68 <mutex_free+0x24>)
    3d5c:	685b      	ldr	r3, [r3, #4]
    3d5e:	4798      	blx	r3
    3d60:	e7f3      	b.n	3d4a <mutex_free+0x6>
    3d62:	bf00      	nop
    3d64:	20000048 	.word	0x20000048
    3d68:	00004dc0 	.word	0x00004dc0

00003d6c <mutex_unlock>:
    3d6c:	b168      	cbz	r0, 3d8a <mutex_unlock+0x1e>
    3d6e:	6843      	ldr	r3, [r0, #4]
    3d70:	b13b      	cbz	r3, 3d82 <mutex_unlock+0x16>
    3d72:	06db      	lsls	r3, r3, #27
    3d74:	d507      	bpl.n	3d86 <mutex_unlock+0x1a>
    3d76:	f3bf 8f5f 	dmb	sy
    3d7a:	2300      	movs	r3, #0
    3d7c:	6003      	str	r3, [r0, #0]
    3d7e:	4618      	mov	r0, r3
    3d80:	4770      	bx	lr
    3d82:	4803      	ldr	r0, [pc, #12]	; (3d90 <mutex_unlock+0x24>)
    3d84:	4770      	bx	lr
    3d86:	4803      	ldr	r0, [pc, #12]	; (3d94 <mutex_unlock+0x28>)
    3d88:	4770      	bx	lr
    3d8a:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    3d8e:	4770      	bx	lr
    3d90:	ffff8fea 	.word	0xffff8fea
    3d94:	ffff8fe9 	.word	0xffff8fe9

00003d98 <mutex_init>:
    3d98:	b510      	push	{r4, lr}
    3d9a:	4604      	mov	r4, r0
    3d9c:	b120      	cbz	r0, 3da8 <mutex_init+0x10>
    3d9e:	2200      	movs	r2, #0
    3da0:	2311      	movs	r3, #17
    3da2:	6022      	str	r2, [r4, #0]
    3da4:	6063      	str	r3, [r4, #4]
    3da6:	bd10      	pop	{r4, pc}
    3da8:	4801      	ldr	r0, [pc, #4]	; (3db0 <mutex_init+0x18>)
    3daa:	f7ff ffa3 	bl	3cf4 <CC_PalAbort>
    3dae:	e7f6      	b.n	3d9e <mutex_init+0x6>
    3db0:	00004de8 	.word	0x00004de8

00003db4 <mutex_lock>:
    3db4:	b1c0      	cbz	r0, 3de8 <mutex_lock+0x34>
    3db6:	6843      	ldr	r3, [r0, #4]
    3db8:	b1a3      	cbz	r3, 3de4 <mutex_lock+0x30>
    3dba:	06db      	lsls	r3, r3, #27
    3dbc:	d510      	bpl.n	3de0 <mutex_lock+0x2c>
    3dbe:	2201      	movs	r2, #1
    3dc0:	f3bf 8f5b 	dmb	ish
    3dc4:	e850 3f00 	ldrex	r3, [r0]
    3dc8:	e840 2100 	strex	r1, r2, [r0]
    3dcc:	2900      	cmp	r1, #0
    3dce:	d1f9      	bne.n	3dc4 <mutex_lock+0x10>
    3dd0:	f3bf 8f5b 	dmb	ish
    3dd4:	2b01      	cmp	r3, #1
    3dd6:	d0f3      	beq.n	3dc0 <mutex_lock+0xc>
    3dd8:	f3bf 8f5f 	dmb	sy
    3ddc:	2000      	movs	r0, #0
    3dde:	4770      	bx	lr
    3de0:	4803      	ldr	r0, [pc, #12]	; (3df0 <mutex_lock+0x3c>)
    3de2:	4770      	bx	lr
    3de4:	4803      	ldr	r0, [pc, #12]	; (3df4 <mutex_lock+0x40>)
    3de6:	4770      	bx	lr
    3de8:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    3dec:	4770      	bx	lr
    3dee:	bf00      	nop
    3df0:	ffff8fe9 	.word	0xffff8fe9
    3df4:	ffff8fea 	.word	0xffff8fea

00003df8 <nrf_cc3xx_platform_set_mutexes>:
    3df8:	b570      	push	{r4, r5, r6, lr}
    3dfa:	e9d0 2300 	ldrd	r2, r3, [r0]
    3dfe:	4c13      	ldr	r4, [pc, #76]	; (3e4c <nrf_cc3xx_platform_set_mutexes+0x54>)
    3e00:	4d13      	ldr	r5, [pc, #76]	; (3e50 <nrf_cc3xx_platform_set_mutexes+0x58>)
    3e02:	e9c4 2300 	strd	r2, r3, [r4]
    3e06:	e9d0 6302 	ldrd	r6, r3, [r0, #8]
    3e0a:	e9c4 6302 	strd	r6, r3, [r4, #8]
    3e0e:	4b11      	ldr	r3, [pc, #68]	; (3e54 <nrf_cc3xx_platform_set_mutexes+0x5c>)
    3e10:	6808      	ldr	r0, [r1, #0]
    3e12:	6018      	str	r0, [r3, #0]
    3e14:	6848      	ldr	r0, [r1, #4]
    3e16:	6058      	str	r0, [r3, #4]
    3e18:	6888      	ldr	r0, [r1, #8]
    3e1a:	6098      	str	r0, [r3, #8]
    3e1c:	e9d1 6003 	ldrd	r6, r0, [r1, #12]
    3e20:	f8d5 1114 	ldr.w	r1, [r5, #276]	; 0x114
    3e24:	60de      	str	r6, [r3, #12]
    3e26:	6118      	str	r0, [r3, #16]
    3e28:	06cb      	lsls	r3, r1, #27
    3e2a:	d50d      	bpl.n	3e48 <nrf_cc3xx_platform_set_mutexes+0x50>
    3e2c:	2300      	movs	r3, #0
    3e2e:	e9c5 3344 	strd	r3, r3, [r5, #272]	; 0x110
    3e32:	e9c5 336d 	strd	r3, r3, [r5, #436]	; 0x1b4
    3e36:	f505 7088 	add.w	r0, r5, #272	; 0x110
    3e3a:	4790      	blx	r2
    3e3c:	6823      	ldr	r3, [r4, #0]
    3e3e:	f505 70da 	add.w	r0, r5, #436	; 0x1b4
    3e42:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    3e46:	4718      	bx	r3
    3e48:	bd70      	pop	{r4, r5, r6, pc}
    3e4a:	bf00      	nop
    3e4c:	20000058 	.word	0x20000058
    3e50:	20000d98 	.word	0x20000d98
    3e54:	20000068 	.word	0x20000068

00003e58 <CC_LibInitNoRng>:
    3e58:	b510      	push	{r4, lr}
    3e5a:	f000 f833 	bl	3ec4 <CC_HalInit>
    3e5e:	b120      	cbz	r0, 3e6a <CC_LibInitNoRng+0x12>
    3e60:	2403      	movs	r4, #3
    3e62:	f000 f867 	bl	3f34 <CC_PalTerminate>
    3e66:	4620      	mov	r0, r4
    3e68:	bd10      	pop	{r4, pc}
    3e6a:	f000 f835 	bl	3ed8 <CC_PalInit>
    3e6e:	b990      	cbnz	r0, 3e96 <CC_LibInitNoRng+0x3e>
    3e70:	f000 f8b0 	bl	3fd4 <CC_PalPowerSaveModeSelect>
    3e74:	b990      	cbnz	r0, 3e9c <CC_LibInitNoRng+0x44>
    3e76:	4b0f      	ldr	r3, [pc, #60]	; (3eb4 <CC_LibInitNoRng+0x5c>)
    3e78:	681b      	ldr	r3, [r3, #0]
    3e7a:	0e1b      	lsrs	r3, r3, #24
    3e7c:	2bf0      	cmp	r3, #240	; 0xf0
    3e7e:	d108      	bne.n	3e92 <CC_LibInitNoRng+0x3a>
    3e80:	4a0d      	ldr	r2, [pc, #52]	; (3eb8 <CC_LibInitNoRng+0x60>)
    3e82:	4b0e      	ldr	r3, [pc, #56]	; (3ebc <CC_LibInitNoRng+0x64>)
    3e84:	6812      	ldr	r2, [r2, #0]
    3e86:	429a      	cmp	r2, r3
    3e88:	d00a      	beq.n	3ea0 <CC_LibInitNoRng+0x48>
    3e8a:	2407      	movs	r4, #7
    3e8c:	f000 f81c 	bl	3ec8 <CC_HalTerminate>
    3e90:	e7e7      	b.n	3e62 <CC_LibInitNoRng+0xa>
    3e92:	2406      	movs	r4, #6
    3e94:	e7fa      	b.n	3e8c <CC_LibInitNoRng+0x34>
    3e96:	2404      	movs	r4, #4
    3e98:	4620      	mov	r0, r4
    3e9a:	bd10      	pop	{r4, pc}
    3e9c:	2400      	movs	r4, #0
    3e9e:	e7f5      	b.n	3e8c <CC_LibInitNoRng+0x34>
    3ea0:	2001      	movs	r0, #1
    3ea2:	f000 f897 	bl	3fd4 <CC_PalPowerSaveModeSelect>
    3ea6:	4604      	mov	r4, r0
    3ea8:	2800      	cmp	r0, #0
    3eaa:	d1f7      	bne.n	3e9c <CC_LibInitNoRng+0x44>
    3eac:	4b04      	ldr	r3, [pc, #16]	; (3ec0 <CC_LibInitNoRng+0x68>)
    3eae:	6018      	str	r0, [r3, #0]
    3eb0:	e7d9      	b.n	3e66 <CC_LibInitNoRng+0xe>
    3eb2:	bf00      	nop
    3eb4:	5002b928 	.word	0x5002b928
    3eb8:	5002ba24 	.word	0x5002ba24
    3ebc:	20e00000 	.word	0x20e00000
    3ec0:	5002ba0c 	.word	0x5002ba0c

00003ec4 <CC_HalInit>:
    3ec4:	2000      	movs	r0, #0
    3ec6:	4770      	bx	lr

00003ec8 <CC_HalTerminate>:
    3ec8:	2000      	movs	r0, #0
    3eca:	4770      	bx	lr

00003ecc <CC_HalMaskInterrupt>:
    3ecc:	4b01      	ldr	r3, [pc, #4]	; (3ed4 <CC_HalMaskInterrupt+0x8>)
    3ece:	6018      	str	r0, [r3, #0]
    3ed0:	4770      	bx	lr
    3ed2:	bf00      	nop
    3ed4:	5002ba04 	.word	0x5002ba04

00003ed8 <CC_PalInit>:
    3ed8:	b510      	push	{r4, lr}
    3eda:	4811      	ldr	r0, [pc, #68]	; (3f20 <CC_PalInit+0x48>)
    3edc:	f000 f848 	bl	3f70 <CC_PalMutexCreate>
    3ee0:	b100      	cbz	r0, 3ee4 <CC_PalInit+0xc>
    3ee2:	bd10      	pop	{r4, pc}
    3ee4:	480f      	ldr	r0, [pc, #60]	; (3f24 <CC_PalInit+0x4c>)
    3ee6:	f000 f843 	bl	3f70 <CC_PalMutexCreate>
    3eea:	2800      	cmp	r0, #0
    3eec:	d1f9      	bne.n	3ee2 <CC_PalInit+0xa>
    3eee:	4c0e      	ldr	r4, [pc, #56]	; (3f28 <CC_PalInit+0x50>)
    3ef0:	4620      	mov	r0, r4
    3ef2:	f000 f83d 	bl	3f70 <CC_PalMutexCreate>
    3ef6:	2800      	cmp	r0, #0
    3ef8:	d1f3      	bne.n	3ee2 <CC_PalInit+0xa>
    3efa:	4b0c      	ldr	r3, [pc, #48]	; (3f2c <CC_PalInit+0x54>)
    3efc:	480c      	ldr	r0, [pc, #48]	; (3f30 <CC_PalInit+0x58>)
    3efe:	601c      	str	r4, [r3, #0]
    3f00:	f000 f836 	bl	3f70 <CC_PalMutexCreate>
    3f04:	4601      	mov	r1, r0
    3f06:	2800      	cmp	r0, #0
    3f08:	d1eb      	bne.n	3ee2 <CC_PalInit+0xa>
    3f0a:	f000 f82d 	bl	3f68 <CC_PalDmaInit>
    3f0e:	4604      	mov	r4, r0
    3f10:	b108      	cbz	r0, 3f16 <CC_PalInit+0x3e>
    3f12:	4620      	mov	r0, r4
    3f14:	bd10      	pop	{r4, pc}
    3f16:	f000 f83f 	bl	3f98 <CC_PalPowerSaveModeInit>
    3f1a:	4620      	mov	r0, r4
    3f1c:	e7fa      	b.n	3f14 <CC_PalInit+0x3c>
    3f1e:	bf00      	nop
    3f20:	200000a0 	.word	0x200000a0
    3f24:	20000094 	.word	0x20000094
    3f28:	2000009c 	.word	0x2000009c
    3f2c:	200000a4 	.word	0x200000a4
    3f30:	20000098 	.word	0x20000098

00003f34 <CC_PalTerminate>:
    3f34:	b508      	push	{r3, lr}
    3f36:	4808      	ldr	r0, [pc, #32]	; (3f58 <CC_PalTerminate+0x24>)
    3f38:	f000 f824 	bl	3f84 <CC_PalMutexDestroy>
    3f3c:	4807      	ldr	r0, [pc, #28]	; (3f5c <CC_PalTerminate+0x28>)
    3f3e:	f000 f821 	bl	3f84 <CC_PalMutexDestroy>
    3f42:	4807      	ldr	r0, [pc, #28]	; (3f60 <CC_PalTerminate+0x2c>)
    3f44:	f000 f81e 	bl	3f84 <CC_PalMutexDestroy>
    3f48:	4806      	ldr	r0, [pc, #24]	; (3f64 <CC_PalTerminate+0x30>)
    3f4a:	f000 f81b 	bl	3f84 <CC_PalMutexDestroy>
    3f4e:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    3f52:	f000 b80b 	b.w	3f6c <CC_PalDmaTerminate>
    3f56:	bf00      	nop
    3f58:	200000a0 	.word	0x200000a0
    3f5c:	20000094 	.word	0x20000094
    3f60:	2000009c 	.word	0x2000009c
    3f64:	20000098 	.word	0x20000098

00003f68 <CC_PalDmaInit>:
    3f68:	2000      	movs	r0, #0
    3f6a:	4770      	bx	lr

00003f6c <CC_PalDmaTerminate>:
    3f6c:	4770      	bx	lr
    3f6e:	bf00      	nop

00003f70 <CC_PalMutexCreate>:
    3f70:	b508      	push	{r3, lr}
    3f72:	4b03      	ldr	r3, [pc, #12]	; (3f80 <CC_PalMutexCreate+0x10>)
    3f74:	6802      	ldr	r2, [r0, #0]
    3f76:	681b      	ldr	r3, [r3, #0]
    3f78:	6810      	ldr	r0, [r2, #0]
    3f7a:	4798      	blx	r3
    3f7c:	2000      	movs	r0, #0
    3f7e:	bd08      	pop	{r3, pc}
    3f80:	20000058 	.word	0x20000058

00003f84 <CC_PalMutexDestroy>:
    3f84:	b508      	push	{r3, lr}
    3f86:	4b03      	ldr	r3, [pc, #12]	; (3f94 <CC_PalMutexDestroy+0x10>)
    3f88:	6802      	ldr	r2, [r0, #0]
    3f8a:	685b      	ldr	r3, [r3, #4]
    3f8c:	6810      	ldr	r0, [r2, #0]
    3f8e:	4798      	blx	r3
    3f90:	2000      	movs	r0, #0
    3f92:	bd08      	pop	{r3, pc}
    3f94:	20000058 	.word	0x20000058

00003f98 <CC_PalPowerSaveModeInit>:
    3f98:	b570      	push	{r4, r5, r6, lr}
    3f9a:	4c09      	ldr	r4, [pc, #36]	; (3fc0 <CC_PalPowerSaveModeInit+0x28>)
    3f9c:	4d09      	ldr	r5, [pc, #36]	; (3fc4 <CC_PalPowerSaveModeInit+0x2c>)
    3f9e:	6920      	ldr	r0, [r4, #16]
    3fa0:	68ab      	ldr	r3, [r5, #8]
    3fa2:	4798      	blx	r3
    3fa4:	b118      	cbz	r0, 3fae <CC_PalPowerSaveModeInit+0x16>
    3fa6:	4b08      	ldr	r3, [pc, #32]	; (3fc8 <CC_PalPowerSaveModeInit+0x30>)
    3fa8:	4808      	ldr	r0, [pc, #32]	; (3fcc <CC_PalPowerSaveModeInit+0x34>)
    3faa:	685b      	ldr	r3, [r3, #4]
    3fac:	4798      	blx	r3
    3fae:	4a08      	ldr	r2, [pc, #32]	; (3fd0 <CC_PalPowerSaveModeInit+0x38>)
    3fb0:	68eb      	ldr	r3, [r5, #12]
    3fb2:	6920      	ldr	r0, [r4, #16]
    3fb4:	2100      	movs	r1, #0
    3fb6:	6011      	str	r1, [r2, #0]
    3fb8:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    3fbc:	4718      	bx	r3
    3fbe:	bf00      	nop
    3fc0:	20000068 	.word	0x20000068
    3fc4:	20000058 	.word	0x20000058
    3fc8:	20000048 	.word	0x20000048
    3fcc:	00004e0c 	.word	0x00004e0c
    3fd0:	20000980 	.word	0x20000980

00003fd4 <CC_PalPowerSaveModeSelect>:
    3fd4:	b570      	push	{r4, r5, r6, lr}
    3fd6:	4d1a      	ldr	r5, [pc, #104]	; (4040 <CC_PalPowerSaveModeSelect+0x6c>)
    3fd8:	4e1a      	ldr	r6, [pc, #104]	; (4044 <CC_PalPowerSaveModeSelect+0x70>)
    3fda:	4604      	mov	r4, r0
    3fdc:	68b2      	ldr	r2, [r6, #8]
    3fde:	6928      	ldr	r0, [r5, #16]
    3fe0:	4790      	blx	r2
    3fe2:	b9f0      	cbnz	r0, 4022 <CC_PalPowerSaveModeSelect+0x4e>
    3fe4:	b15c      	cbz	r4, 3ffe <CC_PalPowerSaveModeSelect+0x2a>
    3fe6:	4c18      	ldr	r4, [pc, #96]	; (4048 <CC_PalPowerSaveModeSelect+0x74>)
    3fe8:	6823      	ldr	r3, [r4, #0]
    3fea:	b1ab      	cbz	r3, 4018 <CC_PalPowerSaveModeSelect+0x44>
    3fec:	2b01      	cmp	r3, #1
    3fee:	d01a      	beq.n	4026 <CC_PalPowerSaveModeSelect+0x52>
    3ff0:	3b01      	subs	r3, #1
    3ff2:	6023      	str	r3, [r4, #0]
    3ff4:	6928      	ldr	r0, [r5, #16]
    3ff6:	68f3      	ldr	r3, [r6, #12]
    3ff8:	4798      	blx	r3
    3ffa:	2000      	movs	r0, #0
    3ffc:	bd70      	pop	{r4, r5, r6, pc}
    3ffe:	4c12      	ldr	r4, [pc, #72]	; (4048 <CC_PalPowerSaveModeSelect+0x74>)
    4000:	6821      	ldr	r1, [r4, #0]
    4002:	b939      	cbnz	r1, 4014 <CC_PalPowerSaveModeSelect+0x40>
    4004:	4b11      	ldr	r3, [pc, #68]	; (404c <CC_PalPowerSaveModeSelect+0x78>)
    4006:	4a12      	ldr	r2, [pc, #72]	; (4050 <CC_PalPowerSaveModeSelect+0x7c>)
    4008:	2001      	movs	r0, #1
    400a:	f8c3 0500 	str.w	r0, [r3, #1280]	; 0x500
    400e:	6813      	ldr	r3, [r2, #0]
    4010:	2b00      	cmp	r3, #0
    4012:	d1fc      	bne.n	400e <CC_PalPowerSaveModeSelect+0x3a>
    4014:	3101      	adds	r1, #1
    4016:	6021      	str	r1, [r4, #0]
    4018:	68f3      	ldr	r3, [r6, #12]
    401a:	6928      	ldr	r0, [r5, #16]
    401c:	4798      	blx	r3
    401e:	2000      	movs	r0, #0
    4020:	bd70      	pop	{r4, r5, r6, pc}
    4022:	480c      	ldr	r0, [pc, #48]	; (4054 <CC_PalPowerSaveModeSelect+0x80>)
    4024:	bd70      	pop	{r4, r5, r6, pc}
    4026:	4a0a      	ldr	r2, [pc, #40]	; (4050 <CC_PalPowerSaveModeSelect+0x7c>)
    4028:	6813      	ldr	r3, [r2, #0]
    402a:	2b00      	cmp	r3, #0
    402c:	d1fc      	bne.n	4028 <CC_PalPowerSaveModeSelect+0x54>
    402e:	4a07      	ldr	r2, [pc, #28]	; (404c <CC_PalPowerSaveModeSelect+0x78>)
    4030:	f06f 407e 	mvn.w	r0, #4261412864	; 0xfe000000
    4034:	f8c2 3500 	str.w	r3, [r2, #1280]	; 0x500
    4038:	f7ff ff48 	bl	3ecc <CC_HalMaskInterrupt>
    403c:	6823      	ldr	r3, [r4, #0]
    403e:	e7d7      	b.n	3ff0 <CC_PalPowerSaveModeSelect+0x1c>
    4040:	20000068 	.word	0x20000068
    4044:	20000058 	.word	0x20000058
    4048:	20000980 	.word	0x20000980
    404c:	5002a000 	.word	0x5002a000
    4050:	5002b910 	.word	0x5002b910
    4054:	ffff8fe9 	.word	0xffff8fe9

00004058 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    4058:	4603      	mov	r3, r0
    405a:	b158      	cbz	r0, 4074 <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    405c:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    405e:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    4062:	2a01      	cmp	r2, #1
    4064:	d003      	beq.n	406e <sys_notify_validate+0x16>
    4066:	2a03      	cmp	r2, #3
    4068:	d104      	bne.n	4074 <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    406a:	6802      	ldr	r2, [r0, #0]
    406c:	b112      	cbz	r2, 4074 <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    406e:	2000      	movs	r0, #0
    4070:	6098      	str	r0, [r3, #8]
    4072:	4770      	bx	lr
		return -EINVAL;
    4074:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    4078:	4770      	bx	lr

0000407a <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    407a:	6842      	ldr	r2, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    407c:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    407e:	f002 0203 	and.w	r2, r2, #3
	switch (method) {
    4082:	2a03      	cmp	r2, #3
    4084:	f04f 0200 	mov.w	r2, #0
{
    4088:	4603      	mov	r3, r0
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    408a:	bf0c      	ite	eq
    408c:	6800      	ldreq	r0, [r0, #0]
	sys_notify_generic_callback rv = NULL;
    408e:	4610      	movne	r0, r2
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    4090:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    4092:	4770      	bx	lr

00004094 <arch_printk_char_out>:
}
    4094:	2000      	movs	r0, #0
    4096:	4770      	bx	lr

00004098 <printk>:
 *
 * @return N/A
 */

void printk(const char *fmt, ...)
{
    4098:	b40f      	push	{r0, r1, r2, r3}
    409a:	b507      	push	{r0, r1, r2, lr}
    409c:	a904      	add	r1, sp, #16
    409e:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    40a2:	9101      	str	r1, [sp, #4]

	if (IS_ENABLED(CONFIG_LOG_PRINTK)) {
		log_printk(fmt, ap);
	} else {
		vprintk(fmt, ap);
    40a4:	f7fc f9de 	bl	464 <vprintk>
	}
	va_end(ap);
}
    40a8:	b003      	add	sp, #12
    40aa:	f85d eb04 	ldr.w	lr, [sp], #4
    40ae:	b004      	add	sp, #16
    40b0:	4770      	bx	lr

000040b2 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    40b2:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    40b4:	f013 0307 	ands.w	r3, r3, #7
    40b8:	d105      	bne.n	40c6 <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    40ba:	6803      	ldr	r3, [r0, #0]
    40bc:	2b00      	cmp	r3, #0
		evt = EVT_START;
    40be:	bf0c      	ite	eq
    40c0:	2000      	moveq	r0, #0
    40c2:	2003      	movne	r0, #3
    40c4:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    40c6:	2b02      	cmp	r3, #2
    40c8:	d105      	bne.n	40d6 <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    40ca:	8b43      	ldrh	r3, [r0, #26]
    40cc:	2b00      	cmp	r3, #0
		evt = EVT_STOP;
    40ce:	bf14      	ite	ne
    40d0:	2000      	movne	r0, #0
    40d2:	2004      	moveq	r0, #4
    40d4:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    40d6:	2b01      	cmp	r3, #1
    40d8:	d105      	bne.n	40e6 <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    40da:	6803      	ldr	r3, [r0, #0]
    40dc:	2b00      	cmp	r3, #0
		evt = EVT_RESET;
    40de:	bf0c      	ite	eq
    40e0:	2000      	moveq	r0, #0
    40e2:	2005      	movne	r0, #5
    40e4:	4770      	bx	lr
	int evt = EVT_NOP;
    40e6:	2000      	movs	r0, #0
}
    40e8:	4770      	bx	lr

000040ea <notify_one>:
{
    40ea:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    40ee:	460d      	mov	r5, r1
    40f0:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    40f2:	4619      	mov	r1, r3
    40f4:	1d28      	adds	r0, r5, #4
{
    40f6:	4690      	mov	r8, r2
    40f8:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    40fa:	f7ff ffbe 	bl	407a <sys_notify_finalize>
	if (cb) {
    40fe:	4604      	mov	r4, r0
    4100:	b138      	cbz	r0, 4112 <notify_one+0x28>
		cb(mgr, cli, state, res);
    4102:	4633      	mov	r3, r6
    4104:	4642      	mov	r2, r8
    4106:	4629      	mov	r1, r5
    4108:	4638      	mov	r0, r7
    410a:	46a4      	mov	ip, r4
}
    410c:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    4110:	4760      	bx	ip
}
    4112:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00004116 <transition_complete>:
{
    4116:	b410      	push	{r4}
	__asm__ volatile(
    4118:	f04f 0420 	mov.w	r4, #32
    411c:	f3ef 8211 	mrs	r2, BASEPRI
    4120:	f384 8812 	msr	BASEPRI_MAX, r4
    4124:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    4128:	6141      	str	r1, [r0, #20]
}
    412a:	bc10      	pop	{r4}
	process_event(mgr, EVT_COMPLETE, key);
    412c:	2101      	movs	r1, #1
    412e:	f7fc b9a7 	b.w	480 <process_event>

00004132 <validate_args>:
{
    4132:	b510      	push	{r4, lr}
    4134:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    4136:	b140      	cbz	r0, 414a <validate_args+0x18>
    4138:	b139      	cbz	r1, 414a <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
    413a:	1d08      	adds	r0, r1, #4
    413c:	f7ff ff8c 	bl	4058 <sys_notify_validate>
	if ((rv == 0)
    4140:	b928      	cbnz	r0, 414e <validate_args+0x1c>
	    && ((cli->notify.flags
    4142:	68a3      	ldr	r3, [r4, #8]
    4144:	f033 0303 	bics.w	r3, r3, #3
    4148:	d001      	beq.n	414e <validate_args+0x1c>
		rv = -EINVAL;
    414a:	f06f 0015 	mvn.w	r0, #21
}
    414e:	bd10      	pop	{r4, pc}

00004150 <onoff_manager_init>:
{
    4150:	b538      	push	{r3, r4, r5, lr}
    4152:	460c      	mov	r4, r1
	if ((mgr == NULL)
    4154:	4605      	mov	r5, r0
    4156:	b158      	cbz	r0, 4170 <onoff_manager_init+0x20>
	    || (transitions == NULL)
    4158:	b151      	cbz	r1, 4170 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    415a:	680b      	ldr	r3, [r1, #0]
    415c:	b143      	cbz	r3, 4170 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    415e:	684b      	ldr	r3, [r1, #4]
    4160:	b133      	cbz	r3, 4170 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    4162:	221c      	movs	r2, #28
    4164:	2100      	movs	r1, #0
    4166:	f000 f906 	bl	4376 <memset>
    416a:	612c      	str	r4, [r5, #16]
	return 0;
    416c:	2000      	movs	r0, #0
}
    416e:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    4170:	f06f 0015 	mvn.w	r0, #21
    4174:	e7fb      	b.n	416e <onoff_manager_init+0x1e>

00004176 <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    4176:	b570      	push	{r4, r5, r6, lr}
    4178:	4604      	mov	r4, r0
    417a:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    417c:	f7ff ffd9 	bl	4132 <validate_args>

	if (rv < 0) {
    4180:	1e05      	subs	r5, r0, #0
    4182:	db31      	blt.n	41e8 <onoff_request+0x72>
    4184:	f04f 0320 	mov.w	r3, #32
    4188:	f3ef 8111 	mrs	r1, BASEPRI
    418c:	f383 8812 	msr	BASEPRI_MAX, r3
    4190:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    4194:	8b63      	ldrh	r3, [r4, #26]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    4196:	8b20      	ldrh	r0, [r4, #24]
	if (mgr->refs == SERVICE_REFS_MAX) {
    4198:	f64f 75ff 	movw	r5, #65535	; 0xffff
    419c:	42ab      	cmp	r3, r5
    419e:	f000 0207 	and.w	r2, r0, #7
    41a2:	d02e      	beq.n	4202 <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
    41a4:	2a02      	cmp	r2, #2
    41a6:	d10e      	bne.n	41c6 <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
    41a8:	3301      	adds	r3, #1
    41aa:	8363      	strh	r3, [r4, #26]
	rv = state;
    41ac:	4615      	mov	r5, r2
		notify = true;
    41ae:	2301      	movs	r3, #1
	__asm__ volatile(
    41b0:	f381 8811 	msr	BASEPRI, r1
    41b4:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    41b8:	b1b3      	cbz	r3, 41e8 <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
    41ba:	2300      	movs	r3, #0
    41bc:	4631      	mov	r1, r6
    41be:	4620      	mov	r0, r4
    41c0:	f7ff ff93 	bl	40ea <notify_one>
    41c4:	e010      	b.n	41e8 <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
    41c6:	0783      	lsls	r3, r0, #30
    41c8:	d001      	beq.n	41ce <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
    41ca:	2a06      	cmp	r2, #6
    41cc:	d10e      	bne.n	41ec <onoff_request+0x76>
	parent->next = child;
    41ce:	2300      	movs	r3, #0
    41d0:	6033      	str	r3, [r6, #0]
Z_GENLIST_APPEND(slist, snode)
    41d2:	6863      	ldr	r3, [r4, #4]
    41d4:	b993      	cbnz	r3, 41fc <onoff_request+0x86>
	list->head = node;
    41d6:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
    41da:	4615      	mov	r5, r2
    41dc:	b962      	cbnz	r2, 41f8 <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
    41de:	460a      	mov	r2, r1
    41e0:	4620      	mov	r0, r4
    41e2:	2102      	movs	r1, #2
    41e4:	f7fc f94c 	bl	480 <process_event>
		}
	}

	return rv;
}
    41e8:	4628      	mov	r0, r5
    41ea:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
    41ec:	2a05      	cmp	r2, #5
    41ee:	bf0c      	ite	eq
    41f0:	f06f 0585 	mvneq.w	r5, #133	; 0x85
    41f4:	f06f 0504 	mvnne.w	r5, #4
    41f8:	2300      	movs	r3, #0
    41fa:	e7d9      	b.n	41b0 <onoff_request+0x3a>
	parent->next = child;
    41fc:	601e      	str	r6, [r3, #0]
	list->tail = node;
    41fe:	6066      	str	r6, [r4, #4]
}
    4200:	e7eb      	b.n	41da <onoff_request+0x64>
		rv = -EAGAIN;
    4202:	f06f 050a 	mvn.w	r5, #10
    4206:	e7f7      	b.n	41f8 <onoff_request+0x82>

00004208 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    4208:	4604      	mov	r4, r0
    420a:	b508      	push	{r3, lr}
    420c:	4608      	mov	r0, r1
    420e:	4611      	mov	r1, r2
#ifdef CONFIG_THREAD_LOCAL_STORAGE
	z_tls_current = z_current_get();
#endif
	entry(p1, p2, p3);
    4210:	461a      	mov	r2, r3
    4212:	47a0      	blx	r4
	return z_impl_z_current_get();
    4214:	f7ff fb70 	bl	38f8 <z_impl_z_current_get>
	z_impl_k_thread_abort(thread);
    4218:	f7fd fa00 	bl	161c <z_impl_k_thread_abort>

0000421c <encode_uint>:
{
    421c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4220:	4699      	mov	r9, r3
	bool upcase = isupper((int)conv->specifier);
    4222:	78d3      	ldrb	r3, [r2, #3]
{
    4224:	4614      	mov	r4, r2
	switch (specifier) {
    4226:	2b6f      	cmp	r3, #111	; 0x6f
	return (int)(((unsigned)(a)-(unsigned)'A') < 26U);
    4228:	f1a3 0241 	sub.w	r2, r3, #65	; 0x41
{
    422c:	4606      	mov	r6, r0
    422e:	460f      	mov	r7, r1
    4230:	9201      	str	r2, [sp, #4]
	switch (specifier) {
    4232:	d02d      	beq.n	4290 <encode_uint+0x74>
    4234:	d828      	bhi.n	4288 <encode_uint+0x6c>
		return 16;
    4236:	2b58      	cmp	r3, #88	; 0x58
    4238:	bf14      	ite	ne
    423a:	250a      	movne	r5, #10
    423c:	2510      	moveq	r5, #16
	char *bp = bps + (bpe - bps);
    423e:	f8dd 8030 	ldr.w	r8, [sp, #48]	; 0x30
		unsigned int lsv = (unsigned int)(value % radix);
    4242:	46aa      	mov	sl, r5
    4244:	f04f 0b00 	mov.w	fp, #0
    4248:	4652      	mov	r2, sl
    424a:	465b      	mov	r3, fp
    424c:	4630      	mov	r0, r6
    424e:	4639      	mov	r1, r7
    4250:	f7fb ff56 	bl	100 <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    4254:	2a09      	cmp	r2, #9
    4256:	b2d3      	uxtb	r3, r2
    4258:	d81f      	bhi.n	429a <encode_uint+0x7e>
    425a:	3330      	adds	r3, #48	; 0x30
	} while ((value != 0) && (bps < bp));
    425c:	455f      	cmp	r7, fp
		*--bp = (lsv <= 9) ? ('0' + lsv)
    425e:	b2db      	uxtb	r3, r3
	} while ((value != 0) && (bps < bp));
    4260:	bf08      	it	eq
    4262:	4556      	cmpeq	r6, sl
		*--bp = (lsv <= 9) ? ('0' + lsv)
    4264:	f808 3d01 	strb.w	r3, [r8, #-1]!
	} while ((value != 0) && (bps < bp));
    4268:	d301      	bcc.n	426e <encode_uint+0x52>
    426a:	45c8      	cmp	r8, r9
    426c:	d812      	bhi.n	4294 <encode_uint+0x78>
	if (conv->flag_hash) {
    426e:	7823      	ldrb	r3, [r4, #0]
    4270:	069b      	lsls	r3, r3, #26
    4272:	d505      	bpl.n	4280 <encode_uint+0x64>
		if (radix == 8) {
    4274:	2d08      	cmp	r5, #8
    4276:	d116      	bne.n	42a6 <encode_uint+0x8a>
			conv->altform_0 = true;
    4278:	78a3      	ldrb	r3, [r4, #2]
    427a:	f043 0308 	orr.w	r3, r3, #8
			conv->altform_0c = true;
    427e:	70a3      	strb	r3, [r4, #2]
}
    4280:	4640      	mov	r0, r8
    4282:	b003      	add	sp, #12
    4284:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	switch (specifier) {
    4288:	f003 03f7 	and.w	r3, r3, #247	; 0xf7
		return 16;
    428c:	2b70      	cmp	r3, #112	; 0x70
    428e:	e7d3      	b.n	4238 <encode_uint+0x1c>
	switch (specifier) {
    4290:	2508      	movs	r5, #8
    4292:	e7d4      	b.n	423e <encode_uint+0x22>
		value /= radix;
    4294:	4606      	mov	r6, r0
    4296:	460f      	mov	r7, r1
    4298:	e7d6      	b.n	4248 <encode_uint+0x2c>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    429a:	9a01      	ldr	r2, [sp, #4]
    429c:	2a19      	cmp	r2, #25
    429e:	bf94      	ite	ls
    42a0:	3337      	addls	r3, #55	; 0x37
    42a2:	3357      	addhi	r3, #87	; 0x57
    42a4:	e7da      	b.n	425c <encode_uint+0x40>
		} else if (radix == 16) {
    42a6:	2d10      	cmp	r5, #16
    42a8:	d1ea      	bne.n	4280 <encode_uint+0x64>
			conv->altform_0c = true;
    42aa:	78a3      	ldrb	r3, [r4, #2]
    42ac:	f043 0310 	orr.w	r3, r3, #16
    42b0:	e7e5      	b.n	427e <encode_uint+0x62>

000042b2 <outs>:
{
    42b2:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    42b6:	4607      	mov	r7, r0
    42b8:	4688      	mov	r8, r1
    42ba:	4615      	mov	r5, r2
    42bc:	461e      	mov	r6, r3
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    42be:	4614      	mov	r4, r2
    42c0:	42b4      	cmp	r4, r6
    42c2:	eba4 0005 	sub.w	r0, r4, r5
    42c6:	d302      	bcc.n	42ce <outs+0x1c>
    42c8:	b93e      	cbnz	r6, 42da <outs+0x28>
    42ca:	7823      	ldrb	r3, [r4, #0]
    42cc:	b12b      	cbz	r3, 42da <outs+0x28>
		int rc = out((int)*sp++, ctx);
    42ce:	f814 0b01 	ldrb.w	r0, [r4], #1
    42d2:	4641      	mov	r1, r8
    42d4:	47b8      	blx	r7
		if (rc < 0) {
    42d6:	2800      	cmp	r0, #0
    42d8:	daf2      	bge.n	42c0 <outs+0xe>
}
    42da:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

000042de <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_DISASSEMBLY, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_PRINT_MEMORY_USAGE, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    42de:	4770      	bx	lr

000042e0 <pm_policy_next_state>:
			return pm_min_residency[i];
		}
	}

	LOG_DBG("No suitable power state found!");
	return (struct pm_state_info){PM_STATE_ACTIVE, 0, 0};
    42e0:	2200      	movs	r2, #0
    42e2:	e9c0 2200 	strd	r2, r2, [r0]
    42e6:	6082      	str	r2, [r0, #8]
}
    42e8:	4770      	bx	lr

000042ea <abort_function>:
{
    42ea:	b508      	push	{r3, lr}
	sys_reboot(SYS_REBOOT_WARM);
    42ec:	2000      	movs	r0, #0
    42ee:	f7fc fd6d 	bl	dcc <sys_reboot>

000042f2 <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    42f2:	f000 ba28 	b.w	4746 <z_fatal_error>

000042f6 <z_do_kernel_oops>:
 *   fault handler will executed insted of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    42f6:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
    42f8:	6800      	ldr	r0, [r0, #0]
    42fa:	f000 ba24 	b.w	4746 <z_fatal_error>

000042fe <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    42fe:	2100      	movs	r1, #0
    4300:	2001      	movs	r0, #1
    4302:	f7ff bff6 	b.w	42f2 <z_arm_fatal_error>

00004306 <z_arm_nmi>:
 *
 * @return N/A
 */

void z_arm_nmi(void)
{
    4306:	b508      	push	{r3, lr}
	handler();
    4308:	f7fc ff26 	bl	1158 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    430c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    4310:	f7fd b802 	b.w	1318 <z_arm_exc_exit>

00004314 <strcpy>:

char *strcpy(char *_MLIBC_RESTRICT d, const char *_MLIBC_RESTRICT s)
{
	char *dest = d;

	while (*s != '\0') {
    4314:	3901      	subs	r1, #1
    4316:	4603      	mov	r3, r0
    4318:	f811 2f01 	ldrb.w	r2, [r1, #1]!
    431c:	b90a      	cbnz	r2, 4322 <strcpy+0xe>
		*d = *s;
		d++;
		s++;
	}

	*d = '\0';
    431e:	701a      	strb	r2, [r3, #0]

	return dest;
}
    4320:	4770      	bx	lr
		*d = *s;
    4322:	f803 2b01 	strb.w	r2, [r3], #1
		s++;
    4326:	e7f7      	b.n	4318 <strcpy+0x4>

00004328 <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    4328:	4603      	mov	r3, r0
	size_t n = 0;
    432a:	2000      	movs	r0, #0

	while (*s != '\0') {
    432c:	5c1a      	ldrb	r2, [r3, r0]
    432e:	b902      	cbnz	r2, 4332 <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    4330:	4770      	bx	lr
		n++;
    4332:	3001      	adds	r0, #1
    4334:	e7fa      	b.n	432c <strlen+0x4>

00004336 <strnlen>:
 *
 * @return number of bytes in fixed-size string <s>
 */

size_t strnlen(const char *s, size_t maxlen)
{
    4336:	4603      	mov	r3, r0
	size_t n = 0;
    4338:	2000      	movs	r0, #0

	while (*s != '\0' && n < maxlen) {
    433a:	5c1a      	ldrb	r2, [r3, r0]
    433c:	b10a      	cbz	r2, 4342 <strnlen+0xc>
    433e:	4288      	cmp	r0, r1
    4340:	d100      	bne.n	4344 <strnlen+0xe>
		s++;
		n++;
	}

	return n;
}
    4342:	4770      	bx	lr
		n++;
    4344:	3001      	adds	r0, #1
    4346:	e7f8      	b.n	433a <strnlen+0x4>

00004348 <strcmp>:
 * @return negative # if <s1> < <s2>, 0 if <s1> == <s2>, else positive #
 */

int strcmp(const char *s1, const char *s2)
{
	while ((*s1 == *s2) && (*s1 != '\0')) {
    4348:	1e43      	subs	r3, r0, #1
    434a:	3901      	subs	r1, #1
    434c:	f813 2f01 	ldrb.w	r2, [r3, #1]!
    4350:	f811 0f01 	ldrb.w	r0, [r1, #1]!
    4354:	4282      	cmp	r2, r0
    4356:	d101      	bne.n	435c <strcmp+0x14>
    4358:	2a00      	cmp	r2, #0
    435a:	d1f7      	bne.n	434c <strcmp+0x4>
		s1++;
		s2++;
	}

	return *s1 - *s2;
}
    435c:	1a10      	subs	r0, r2, r0
    435e:	4770      	bx	lr

00004360 <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *_MLIBC_RESTRICT d, const void *_MLIBC_RESTRICT s, size_t n)
{
    4360:	b510      	push	{r4, lr}
    4362:	1e43      	subs	r3, r0, #1
    4364:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
    4366:	4291      	cmp	r1, r2
    4368:	d100      	bne.n	436c <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    436a:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
    436c:	f811 4b01 	ldrb.w	r4, [r1], #1
    4370:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    4374:	e7f7      	b.n	4366 <memcpy+0x6>

00004376 <memset>:
void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
	unsigned char c_byte = (unsigned char)c;
    4376:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
    4378:	4402      	add	r2, r0
	unsigned char *d_byte = (unsigned char *)buf;
    437a:	4603      	mov	r3, r0
	while (n > 0) {
    437c:	4293      	cmp	r3, r2
    437e:	d100      	bne.n	4382 <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    4380:	4770      	bx	lr
		*(d_byte++) = c_byte;
    4382:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    4386:	e7f9      	b.n	437c <memset+0x6>

00004388 <pm_power_state_set>:
#include <logging/log.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);

/* Invoke Low Power/System Off specific Tasks */
__weak void pm_power_state_set(struct pm_state_info info)
{
    4388:	b084      	sub	sp, #16
    438a:	ab04      	add	r3, sp, #16
    438c:	e903 0007 	stmdb	r3, {r0, r1, r2}
	switch (info.state) {
    4390:	f89d 3004 	ldrb.w	r3, [sp, #4]
    4394:	2b06      	cmp	r3, #6
    4396:	d108      	bne.n	43aa <pm_power_state_set+0x22>
    p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
    4398:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    439c:	2201      	movs	r2, #1
    439e:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  __ASM volatile ("dsb 0xF":::"memory");
    43a2:	f3bf 8f4f 	dsb	sy
        __WFE();
    43a6:	bf20      	wfe
    while (true)
    43a8:	e7fd      	b.n	43a6 <pm_power_state_set+0x1e>
		break;
	default:
		LOG_DBG("Unsupported power state %u", info.state);
		break;
	}
}
    43aa:	b004      	add	sp, #16
    43ac:	4770      	bx	lr

000043ae <pm_power_state_exit_post_ops>:

/* Handle SOC specific activity after Low Power Mode Exit */
__weak void pm_power_state_exit_post_ops(struct pm_state_info info)
{
    43ae:	b084      	sub	sp, #16
    43b0:	ab04      	add	r3, sp, #16
    43b2:	e903 0007 	stmdb	r3, {r0, r1, r2}
    43b6:	2300      	movs	r3, #0
    43b8:	f383 8811 	msr	BASEPRI, r3
    43bc:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
    43c0:	b004      	add	sp, #16
    43c2:	4770      	bx	lr

000043c4 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    43c4:	6902      	ldr	r2, [r0, #16]
    43c6:	b2cb      	uxtb	r3, r1
    43c8:	210c      	movs	r1, #12
    43ca:	fb03 2101 	mla	r1, r3, r1, r2
    43ce:	6c08      	ldr	r0, [r1, #64]	; 0x40
}
    43d0:	f000 0007 	and.w	r0, r0, #7
    43d4:	4770      	bx	lr

000043d6 <set_off_state>:
	__asm__ volatile(
    43d6:	f04f 0320 	mov.w	r3, #32
    43da:	f3ef 8211 	mrs	r2, BASEPRI
    43de:	f383 8812 	msr	BASEPRI_MAX, r3
    43e2:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    43e6:	6803      	ldr	r3, [r0, #0]
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    43e8:	f013 03c0 	ands.w	r3, r3, #192	; 0xc0
    43ec:	d001      	beq.n	43f2 <set_off_state+0x1c>
    43ee:	428b      	cmp	r3, r1
    43f0:	d107      	bne.n	4402 <set_off_state+0x2c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    43f2:	2301      	movs	r3, #1
    43f4:	6003      	str	r3, [r0, #0]
	int err = 0;
    43f6:	2000      	movs	r0, #0
	__asm__ volatile(
    43f8:	f382 8811 	msr	BASEPRI, r2
    43fc:	f3bf 8f6f 	isb	sy
}
    4400:	4770      	bx	lr
		err = -EPERM;
    4402:	f04f 30ff 	mov.w	r0, #4294967295
    4406:	e7f7      	b.n	43f8 <set_off_state+0x22>

00004408 <set_starting_state>:
{
    4408:	b510      	push	{r4, lr}
	__asm__ volatile(
    440a:	f04f 0320 	mov.w	r3, #32
    440e:	f3ef 8211 	mrs	r2, BASEPRI
    4412:	f383 8812 	msr	BASEPRI_MAX, r3
    4416:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    441a:	6803      	ldr	r3, [r0, #0]
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    441c:	f003 0407 	and.w	r4, r3, #7
    4420:	2c01      	cmp	r4, #1
    4422:	d106      	bne.n	4432 <set_starting_state+0x2a>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    4424:	6001      	str	r1, [r0, #0]
	int err = 0;
    4426:	2000      	movs	r0, #0
	__asm__ volatile(
    4428:	f382 8811 	msr	BASEPRI, r2
    442c:	f3bf 8f6f 	isb	sy
}
    4430:	bd10      	pop	{r4, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    4432:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
	} else if (current_ctx != ctx) {
    4436:	428b      	cmp	r3, r1
		err = -EALREADY;
    4438:	bf14      	ite	ne
    443a:	f04f 30ff 	movne.w	r0, #4294967295
    443e:	f06f 0077 	mvneq.w	r0, #119	; 0x77
    4442:	e7f1      	b.n	4428 <set_starting_state+0x20>

00004444 <set_on_state>:
	__asm__ volatile(
    4444:	f04f 0320 	mov.w	r3, #32
    4448:	f3ef 8211 	mrs	r2, BASEPRI
    444c:	f383 8812 	msr	BASEPRI_MAX, r3
    4450:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    4454:	6803      	ldr	r3, [r0, #0]
    4456:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    445a:	f043 0302 	orr.w	r3, r3, #2
    445e:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    4460:	f382 8811 	msr	BASEPRI, r2
    4464:	f3bf 8f6f 	isb	sy
}
    4468:	4770      	bx	lr

0000446a <onoff_started_callback>:
	return &data->mgr[type];
    446a:	6900      	ldr	r0, [r0, #16]
{
    446c:	b410      	push	{r4}
	return &data->mgr[type];
    446e:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    4470:	241c      	movs	r4, #28
    4472:	fb03 0004 	mla	r0, r3, r4, r0
    4476:	2100      	movs	r1, #0
}
    4478:	bc10      	pop	{r4}
	notify(mgr, 0);
    447a:	4710      	bx	r2

0000447c <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    447c:	2000      	movs	r0, #0
    447e:	f7fe bab3 	b.w	29e8 <nrfx_clock_start>

00004482 <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    4482:	2000      	movs	r0, #0
    4484:	f7fe bae2 	b.w	2a4c <nrfx_clock_stop>

00004488 <blocking_start_callback>:
{
    4488:	4610      	mov	r0, r2
		arch_syscall_invoke1(*(uintptr_t *)&sem, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    448a:	f7fe bee7 	b.w	325c <z_impl_k_sem_give>

0000448e <api_stop>:
{
    448e:	b538      	push	{r3, r4, r5, lr}
    4490:	b2cc      	uxtb	r4, r1
	err = set_off_state(&subdata->flags, ctx);
    4492:	230c      	movs	r3, #12
{
    4494:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
    4496:	4363      	muls	r3, r4
    4498:	6900      	ldr	r0, [r0, #16]
    449a:	3340      	adds	r3, #64	; 0x40
    449c:	2180      	movs	r1, #128	; 0x80
    449e:	4418      	add	r0, r3
    44a0:	f7ff ff99 	bl	43d6 <set_off_state>
	if (err < 0) {
    44a4:	2800      	cmp	r0, #0
    44a6:	db05      	blt.n	44b4 <api_stop+0x26>
	get_sub_config(dev, type)->stop();
    44a8:	6869      	ldr	r1, [r5, #4]
    44aa:	eb01 04c4 	add.w	r4, r1, r4, lsl #3
    44ae:	6863      	ldr	r3, [r4, #4]
    44b0:	4798      	blx	r3
	return 0;
    44b2:	2000      	movs	r0, #0
}
    44b4:	bd38      	pop	{r3, r4, r5, pc}

000044b6 <api_start>:
{
    44b6:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    44ba:	b2cd      	uxtb	r5, r1
	err = set_starting_state(&subdata->flags, ctx);
    44bc:	270c      	movs	r7, #12
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    44be:	6904      	ldr	r4, [r0, #16]
	err = set_starting_state(&subdata->flags, ctx);
    44c0:	436f      	muls	r7, r5
{
    44c2:	4606      	mov	r6, r0
	err = set_starting_state(&subdata->flags, ctx);
    44c4:	f107 0040 	add.w	r0, r7, #64	; 0x40
    44c8:	2180      	movs	r1, #128	; 0x80
    44ca:	4420      	add	r0, r4
{
    44cc:	4690      	mov	r8, r2
    44ce:	4699      	mov	r9, r3
	err = set_starting_state(&subdata->flags, ctx);
    44d0:	f7ff ff9a 	bl	4408 <set_starting_state>
	if (err < 0) {
    44d4:	2800      	cmp	r0, #0
    44d6:	db07      	blt.n	44e8 <api_start+0x32>
	subdata->cb = cb;
    44d8:	443c      	add	r4, r7
	subdata->user_data = user_data;
    44da:	e9c4 890e 	strd	r8, r9, [r4, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    44de:	6873      	ldr	r3, [r6, #4]
    44e0:	f853 3035 	ldr.w	r3, [r3, r5, lsl #3]
    44e4:	4798      	blx	r3
	return 0;
    44e6:	2000      	movs	r0, #0
}
    44e8:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

000044ec <gpio_fire_callbacks>:
 * @param pins The actual pin mask that triggered the interrupt
 */
static inline void gpio_fire_callbacks(sys_slist_t *list,
					const struct device *port,
					uint32_t pins)
{
    44ec:	b570      	push	{r4, r5, r6, lr}
    44ee:	460e      	mov	r6, r1
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    44f0:	6801      	ldr	r1, [r0, #0]
{
    44f2:	4615      	mov	r5, r2
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    44f4:	b189      	cbz	r1, 451a <gpio_fire_callbacks+0x2e>
	return node->next;
    44f6:	680c      	ldr	r4, [r1, #0]
    44f8:	2c00      	cmp	r4, #0
    44fa:	bf38      	it	cc
    44fc:	2400      	movcc	r4, #0
		if (cb->pin_mask & pins) {
    44fe:	688a      	ldr	r2, [r1, #8]
    4500:	402a      	ands	r2, r5
    4502:	d002      	beq.n	450a <gpio_fire_callbacks+0x1e>
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    4504:	684b      	ldr	r3, [r1, #4]
    4506:	4630      	mov	r0, r6
    4508:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    450a:	b134      	cbz	r4, 451a <gpio_fire_callbacks+0x2e>
    450c:	6823      	ldr	r3, [r4, #0]
    450e:	2b00      	cmp	r3, #0
    4510:	bf38      	it	cc
    4512:	2300      	movcc	r3, #0
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    4514:	4621      	mov	r1, r4
    4516:	461c      	mov	r4, r3
    4518:	e7f1      	b.n	44fe <gpio_fire_callbacks+0x12>
		}
	}
}
    451a:	bd70      	pop	{r4, r5, r6, pc}

0000451c <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    451c:	6843      	ldr	r3, [r0, #4]
    451e:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    4520:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    4524:	600b      	str	r3, [r1, #0]
}
    4526:	2000      	movs	r0, #0
    4528:	4770      	bx	lr

0000452a <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    452a:	6843      	ldr	r3, [r0, #4]
    452c:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
    452e:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
    4532:	4042      	eors	r2, r0
    4534:	400a      	ands	r2, r1
    4536:	4042      	eors	r2, r0
    p_reg->OUT = value;
    4538:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
}
    453c:	2000      	movs	r0, #0
    453e:	4770      	bx	lr

00004540 <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    4540:	6843      	ldr	r3, [r0, #4]
    4542:	685b      	ldr	r3, [r3, #4]
}
    4544:	2000      	movs	r0, #0
    p_reg->OUTSET = set_mask;
    4546:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
    454a:	4770      	bx	lr

0000454c <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    454c:	6843      	ldr	r3, [r0, #4]
    454e:	685b      	ldr	r3, [r3, #4]
}
    4550:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    4552:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
    4556:	4770      	bx	lr

00004558 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    4558:	6843      	ldr	r3, [r0, #4]
    455a:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    455c:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value ^ mask);
    4560:	404b      	eors	r3, r1
    p_reg->OUT = value;
    4562:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
}
    4566:	2000      	movs	r0, #0
    4568:	4770      	bx	lr

0000456a <gpio_nrfx_manage_callback>:
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    456a:	6903      	ldr	r3, [r0, #16]
Z_GENLIST_IS_EMPTY(slist)
    456c:	6858      	ldr	r0, [r3, #4]
{
    456e:	b530      	push	{r4, r5, lr}
	if (!sys_slist_is_empty(callbacks)) {
    4570:	b158      	cbz	r0, 458a <gpio_nrfx_manage_callback+0x20>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    4572:	2400      	movs	r4, #0
    4574:	4281      	cmp	r1, r0
    4576:	d113      	bne.n	45a0 <gpio_nrfx_manage_callback+0x36>
Z_GENLIST_REMOVE(slist, snode)
    4578:	6808      	ldr	r0, [r1, #0]
    457a:	b95c      	cbnz	r4, 4594 <gpio_nrfx_manage_callback+0x2a>
    457c:	689c      	ldr	r4, [r3, #8]
	list->head = node;
    457e:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    4580:	42a1      	cmp	r1, r4
    4582:	d100      	bne.n	4586 <gpio_nrfx_manage_callback+0x1c>
	list->tail = node;
    4584:	6098      	str	r0, [r3, #8]
	parent->next = child;
    4586:	2000      	movs	r0, #0
    4588:	6008      	str	r0, [r1, #0]
	if (set) {
    458a:	b972      	cbnz	r2, 45aa <gpio_nrfx_manage_callback+0x40>
	return 0;
    458c:	2000      	movs	r0, #0
}
    458e:	bd30      	pop	{r4, r5, pc}
    4590:	4628      	mov	r0, r5
    4592:	e7ef      	b.n	4574 <gpio_nrfx_manage_callback+0xa>
    4594:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
    4596:	6898      	ldr	r0, [r3, #8]
    4598:	4281      	cmp	r1, r0
	list->tail = node;
    459a:	bf08      	it	eq
    459c:	609c      	streq	r4, [r3, #8]
}
    459e:	e7f2      	b.n	4586 <gpio_nrfx_manage_callback+0x1c>
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    45a0:	6805      	ldr	r5, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    45a2:	4604      	mov	r4, r0
    45a4:	2d00      	cmp	r5, #0
    45a6:	d1f3      	bne.n	4590 <gpio_nrfx_manage_callback+0x26>
			if (!set) {
    45a8:	b13a      	cbz	r2, 45ba <gpio_nrfx_manage_callback+0x50>
Z_GENLIST_PREPEND(slist, snode)
    45aa:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
    45ac:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
    45ae:	6898      	ldr	r0, [r3, #8]
	list->head = node;
    45b0:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    45b2:	2800      	cmp	r0, #0
    45b4:	d1ea      	bne.n	458c <gpio_nrfx_manage_callback+0x22>
	list->tail = node;
    45b6:	6099      	str	r1, [r3, #8]
}
    45b8:	e7e9      	b.n	458e <gpio_nrfx_manage_callback+0x24>
				return -EINVAL;
    45ba:	f06f 0015 	mvn.w	r0, #21
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    45be:	e7e6      	b.n	458e <gpio_nrfx_manage_callback+0x24>

000045c0 <cfg_level_pins>:
{
    45c0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	const struct gpio_nrfx_data *data = get_port_data(port);
    45c4:	6907      	ldr	r7, [r0, #16]
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
    45c6:	f8d0 8004 	ldr.w	r8, [r0, #4]
	uint32_t out = data->pin_int_en;
    45ca:	68fc      	ldr	r4, [r7, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    45cc:	e9d7 3205 	ldrd	r3, r2, [r7, #20]
    45d0:	4313      	orrs	r3, r2
    45d2:	ea24 0403 	bic.w	r4, r4, r3
	uint32_t bit = 1U << pin;
    45d6:	2601      	movs	r6, #1
	uint32_t pin = 0U;
    45d8:	2500      	movs	r5, #0
	while (level_pins) {
    45da:	b90c      	cbnz	r4, 45e0 <cfg_level_pins+0x20>
}
    45dc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		if (level_pins & bit) {
    45e0:	4226      	tst	r6, r4
    45e2:	d010      	beq.n	4606 <cfg_level_pins+0x46>
	if ((BIT(pin) & data->int_active_level) != 0U) {
    45e4:	6939      	ldr	r1, [r7, #16]
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    45e6:	f898 3008 	ldrb.w	r3, [r8, #8]
	if ((BIT(pin) & data->int_active_level) != 0U) {
    45ea:	40e9      	lsrs	r1, r5
    45ec:	f001 0101 	and.w	r1, r1, #1
    45f0:	f1c1 0103 	rsb	r1, r1, #3
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    45f4:	f005 001f 	and.w	r0, r5, #31
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    45f8:	b2c9      	uxtb	r1, r1
    45fa:	ea40 1043 	orr.w	r0, r0, r3, lsl #5
    45fe:	f7fd fb1b 	bl	1c38 <nrf_gpio_cfg_sense_set>
			level_pins &= ~bit;
    4602:	ea24 0406 	bic.w	r4, r4, r6
		++pin;
    4606:	3501      	adds	r5, #1
		bit <<= 1;
    4608:	0076      	lsls	r6, r6, #1
    460a:	e7e6      	b.n	45da <cfg_level_pins+0x1a>

0000460c <uarte_nrfx_isr_int>:
	return config->uarte_regs;
    460c:	6843      	ldr	r3, [r0, #4]
    460e:	681b      	ldr	r3, [r3, #0]
    return p_reg->INTENSET & mask;
    4610:	f8d3 2304 	ldr.w	r2, [r3, #772]	; 0x304
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
    4614:	05d1      	lsls	r1, r2, #23
    4616:	d518      	bpl.n	464a <uarte_nrfx_isr_int+0x3e>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4618:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    461c:	b1aa      	cbz	r2, 464a <uarte_nrfx_isr_int+0x3e>
	__asm__ volatile(
    461e:	f04f 0120 	mov.w	r1, #32
    4622:	f3ef 8211 	mrs	r2, BASEPRI
    4626:	f381 8812 	msr	BASEPRI_MAX, r1
    462a:	f3bf 8f6f 	isb	sy
    462e:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
    4632:	b131      	cbz	r1, 4642 <uarte_nrfx_isr_int+0x36>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4634:	2100      	movs	r1, #0
    4636:	f8c3 1120 	str.w	r1, [r3, #288]	; 0x120
    463a:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    463e:	2101      	movs	r1, #1
    4640:	60d9      	str	r1, [r3, #12]
	__asm__ volatile(
    4642:	f382 8811 	msr	BASEPRI, r2
    4646:	f3bf 8f6f 	isb	sy
	if (get_dev_config(dev)->flags & UARTE_CFG_FLAG_LOW_POWER) {
    464a:	6842      	ldr	r2, [r0, #4]
    464c:	6852      	ldr	r2, [r2, #4]
    464e:	06d2      	lsls	r2, r2, #27
    4650:	d515      	bpl.n	467e <uarte_nrfx_isr_int+0x72>
	__asm__ volatile(
    4652:	f04f 0120 	mov.w	r1, #32
    4656:	f3ef 8211 	mrs	r2, BASEPRI
    465a:	f381 8812 	msr	BASEPRI_MAX, r1
    465e:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4662:	f8d3 1158 	ldr.w	r1, [r3, #344]	; 0x158
		if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
    4666:	b111      	cbz	r1, 466e <uarte_nrfx_isr_int+0x62>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    4668:	2100      	movs	r1, #0
    466a:	f8c3 1500 	str.w	r1, [r3, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    466e:	f44f 0180 	mov.w	r1, #4194304	; 0x400000
    4672:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
	__asm__ volatile(
    4676:	f382 8811 	msr	BASEPRI, r2
    467a:	f3bf 8f6f 	isb	sy
}
    467e:	4770      	bx	lr

00004680 <uarte_nrfx_config_get>:
	*cfg = get_dev_data(dev)->uart_config;
    4680:	6902      	ldr	r2, [r0, #16]
{
    4682:	460b      	mov	r3, r1
	*cfg = get_dev_data(dev)->uart_config;
    4684:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    4688:	e883 0003 	stmia.w	r3, {r0, r1}
}
    468c:	2000      	movs	r0, #0
    468e:	4770      	bx	lr

00004690 <uarte_nrfx_err_check>:
	return config->uarte_regs;
    4690:	6843      	ldr	r3, [r0, #4]
    4692:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    4694:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    4698:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    469c:	4770      	bx	lr

0000469e <is_tx_ready>:
	const struct uarte_nrfx_config *config = get_dev_config(dev);
    469e:	6842      	ldr	r2, [r0, #4]
	return config->uarte_regs;
    46a0:	6813      	ldr	r3, [r2, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    46a2:	f8d3 0158 	ldr.w	r0, [r3, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    46a6:	b940      	cbnz	r0, 46ba <is_tx_ready+0x1c>
	bool ppi_endtx = get_dev_config(dev)->flags & UARTE_CFG_FLAG_PPI_ENDTX;
    46a8:	6852      	ldr	r2, [r2, #4]
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    46aa:	0712      	lsls	r2, r2, #28
    46ac:	d406      	bmi.n	46bc <is_tx_ready+0x1e>
    46ae:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    46b2:	3800      	subs	r0, #0
    46b4:	bf18      	it	ne
    46b6:	2001      	movne	r0, #1
    46b8:	4770      	bx	lr
    46ba:	2001      	movs	r0, #1
}
    46bc:	4770      	bx	lr

000046be <uarte_nrfx_poll_in>:
	return config->uarte_regs;
    46be:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = get_dev_data(dev);
    46c0:	6902      	ldr	r2, [r0, #16]
	return config->uarte_regs;
    46c2:	681b      	ldr	r3, [r3, #0]
    46c4:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    46c8:	b148      	cbz	r0, 46de <uarte_nrfx_poll_in+0x20>
	*c = data->rx_data;
    46ca:	7c52      	ldrb	r2, [r2, #17]
    46cc:	700a      	strb	r2, [r1, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    46ce:	2000      	movs	r0, #0
    46d0:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    46d4:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    46d8:	2201      	movs	r2, #1
    46da:	601a      	str	r2, [r3, #0]
	return 0;
    46dc:	4770      	bx	lr
		return -1;
    46de:	f04f 30ff 	mov.w	r0, #4294967295
}
    46e2:	4770      	bx	lr

000046e4 <sys_clock_isr>:
/* Weak-linked noop defaults for optional driver interfaces*/

void __weak sys_clock_isr(void *arg)
{
	__ASSERT_NO_MSG(false);
}
    46e4:	4770      	bx	lr

000046e6 <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
    46e6:	4770      	bx	lr

000046e8 <sys_clock_disable>:
    46e8:	4770      	bx	lr

000046ea <k_sys_fatal_error_handler>:

extern void sys_arch_reboot(int type);

void k_sys_fatal_error_handler(unsigned int reason,
			       const z_arch_esf_t *esf)
{
    46ea:	b508      	push	{r3, lr}
	z_spm_ns_fatal_error_handler();
#endif

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
		sys_arch_reboot(0);
    46ec:	2000      	movs	r0, #0
    46ee:	f7fd f87b 	bl	17e8 <sys_arch_reboot>

000046f2 <hw_cc3xx_init_internal>:

	/* Initialize the cc3xx HW with or without RNG support */
#if CONFIG_ENTROPY_CC3XX
	res = nrf_cc3xx_platform_init();
#else
	res = nrf_cc3xx_platform_init_no_rng();
    46f2:	f7ff bad1 	b.w	3c98 <nrf_cc3xx_platform_init_no_rng>

000046f6 <hw_cc3xx_init>:

	return res;
}

static int hw_cc3xx_init(const struct device *dev)
{
    46f6:	b508      	push	{r3, lr}
	int res;

	/* Set the RTOS abort APIs */
	nrf_cc3xx_platform_abort_init();
    46f8:	f7fc fc10 	bl	f1c <nrf_cc3xx_platform_abort_init>

	/* Set the RTOS mutex APIs */
	nrf_cc3xx_platform_mutex_init();
    46fc:	f7fc fcc2 	bl	1084 <nrf_cc3xx_platform_mutex_init>

	/* Enable the hardware */
	res = hw_cc3xx_init_internal(dev);
	return res;
}
    4700:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	res = nrf_cc3xx_platform_init_no_rng();
    4704:	f7ff bac8 	b.w	3c98 <nrf_cc3xx_platform_init_no_rng>

00004708 <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    4708:	4700      	bx	r0

0000470a <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    470a:	f000 b97c 	b.w	4a06 <z_impl_k_busy_wait>

0000470e <nrfx_clock_enable>:
{
    470e:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    4710:	2000      	movs	r0, #0
    4712:	f7fc fcfb 	bl	110c <arch_irq_is_enabled>
    4716:	b918      	cbnz	r0, 4720 <nrfx_clock_enable+0x12>
}
    4718:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    471c:	f7fc bce6 	b.w	10ec <arch_irq_enable>
    4720:	bd08      	pop	{r3, pc}

00004722 <SEGGER_RTT_Init>:
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
  _DoInit();
    4722:	f7fe ba9b 	b.w	2c5c <_DoInit>

00004726 <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(const struct device *unused)
{
    4726:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	SEGGER_RTT_Init();
    4728:	f7ff fffb 	bl	4722 <SEGGER_RTT_Init>

	return 0;
}
    472c:	2000      	movs	r0, #0
    472e:	bd08      	pop	{r3, pc}

00004730 <z_device_state_init>:
}
    4730:	4770      	bx	lr

00004732 <z_device_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    4732:	b138      	cbz	r0, 4744 <z_device_ready+0x12>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    4734:	68c3      	ldr	r3, [r0, #12]
    4736:	8818      	ldrh	r0, [r3, #0]
    4738:	f3c0 0008 	ubfx	r0, r0, #0, #9
    473c:	f5a0 7380 	sub.w	r3, r0, #256	; 0x100
    4740:	4258      	negs	r0, r3
    4742:	4158      	adcs	r0, r3
}
    4744:	4770      	bx	lr

00004746 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    4746:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4748:	4605      	mov	r5, r0
    474a:	460e      	mov	r6, r1
	__asm__ volatile(
    474c:	f04f 0320 	mov.w	r3, #32
    4750:	f3ef 8711 	mrs	r7, BASEPRI
    4754:	f383 8812 	msr	BASEPRI_MAX, r3
    4758:	f3bf 8f6f 	isb	sy
	return z_impl_z_current_get();
    475c:	f7ff f8cc 	bl	38f8 <z_impl_z_current_get>
	LOG_ERR("Current thread: %p (%s)", thread,
		log_strdup(thread_name_get(thread)));

	coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    4760:	4631      	mov	r1, r6
    4762:	4604      	mov	r4, r0
    4764:	4628      	mov	r0, r5
    4766:	f7ff ffc0 	bl	46ea <k_sys_fatal_error_handler>
	__asm__ volatile(
    476a:	f387 8811 	msr	BASEPRI, r7
    476e:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    4772:	4620      	mov	r0, r4
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    4774:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    4778:	f7fc bf50 	b.w	161c <z_impl_k_thread_abort>

0000477c <k_mem_slab_init>:
{
    477c:	b530      	push	{r4, r5, lr}
	slab->num_used = 0U;
    477e:	2400      	movs	r4, #0
    4780:	6184      	str	r4, [r0, #24]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    4782:	ea41 0402 	orr.w	r4, r1, r2
    4786:	f014 0403 	ands.w	r4, r4, #3
	slab->block_size = block_size;
    478a:	e9c0 3202 	strd	r3, r2, [r0, #8]
	slab->buffer = buffer;
    478e:	6101      	str	r1, [r0, #16]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    4790:	d10c      	bne.n	47ac <k_mem_slab_init+0x30>
	slab->free_list = NULL;
    4792:	6144      	str	r4, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    4794:	42a3      	cmp	r3, r4
    4796:	d103      	bne.n	47a0 <k_mem_slab_init+0x24>
	list->tail = (sys_dnode_t *)list;
    4798:	e9c0 0000 	strd	r0, r0, [r0]
}
    479c:	2000      	movs	r0, #0
}
    479e:	bd30      	pop	{r4, r5, pc}
		*(char **)p = slab->free_list;
    47a0:	6945      	ldr	r5, [r0, #20]
    47a2:	600d      	str	r5, [r1, #0]
	for (j = 0U; j < slab->num_blocks; j++) {
    47a4:	3401      	adds	r4, #1
		slab->free_list = p;
    47a6:	6141      	str	r1, [r0, #20]
		p += slab->block_size;
    47a8:	4411      	add	r1, r2
	for (j = 0U; j < slab->num_blocks; j++) {
    47aa:	e7f3      	b.n	4794 <k_mem_slab_init+0x18>
		return -EINVAL;
    47ac:	f06f 0015 	mvn.w	r0, #21
	return rc;
    47b0:	e7f5      	b.n	479e <k_mem_slab_init+0x22>

000047b2 <k_mem_slab_free>:

void k_mem_slab_free(struct k_mem_slab *slab, void **mem)
{
    47b2:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    47b4:	4604      	mov	r4, r0
    47b6:	460d      	mov	r5, r1
	__asm__ volatile(
    47b8:	f04f 0320 	mov.w	r3, #32
    47bc:	f3ef 8611 	mrs	r6, BASEPRI
    47c0:	f383 8812 	msr	BASEPRI_MAX, r3
    47c4:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, free, slab);
	if (slab->free_list == NULL && IS_ENABLED(CONFIG_MULTITHREADING)) {
    47c8:	6947      	ldr	r7, [r0, #20]
    47ca:	b977      	cbnz	r7, 47ea <k_mem_slab_free+0x38>
		struct k_thread *pending_thread = z_unpend_first_thread(&slab->wait_q);
    47cc:	f000 f8bf 	bl	494e <z_unpend_first_thread>

		if (pending_thread != NULL) {
    47d0:	b158      	cbz	r0, 47ea <k_mem_slab_free+0x38>
			SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

			z_thread_return_value_set_with_data(pending_thread, 0, *mem);
    47d2:	682a      	ldr	r2, [r5, #0]
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    47d4:	6142      	str	r2, [r0, #20]
    47d6:	6787      	str	r7, [r0, #120]	; 0x78
			z_ready_thread(pending_thread);
    47d8:	f000 f85a 	bl	4890 <z_ready_thread>
			z_reschedule(&slab->lock, key);
    47dc:	4631      	mov	r1, r6
    47de:	f104 0008 	add.w	r0, r4, #8
	slab->num_used--;

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

	k_spin_unlock(&slab->lock, key);
}
    47e2:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
			z_reschedule(&slab->lock, key);
    47e6:	f7fe bdcb 	b.w	3380 <z_reschedule>
	**(char ***) mem = slab->free_list;
    47ea:	682b      	ldr	r3, [r5, #0]
    47ec:	6962      	ldr	r2, [r4, #20]
    47ee:	601a      	str	r2, [r3, #0]
	slab->free_list = *(char **) mem;
    47f0:	682b      	ldr	r3, [r5, #0]
    47f2:	6163      	str	r3, [r4, #20]
	slab->num_used--;
    47f4:	69a3      	ldr	r3, [r4, #24]
    47f6:	3b01      	subs	r3, #1
    47f8:	61a3      	str	r3, [r4, #24]
	__asm__ volatile(
    47fa:	f386 8811 	msr	BASEPRI, r6
    47fe:	f3bf 8f6f 	isb	sy
}
    4802:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00004804 <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    4804:	f3ef 8005 	mrs	r0, IPSR
}
    4808:	3800      	subs	r0, #0
    480a:	bf18      	it	ne
    480c:	2001      	movne	r0, #1
    480e:	4770      	bx	lr

00004810 <z_pm_save_idle_exit>:
{
    4810:	b508      	push	{r3, lr}
	pm_system_resume();
    4812:	f7fc fb19 	bl	e48 <pm_system_resume>
}
    4816:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	sys_clock_idle_exit();
    481a:	f7ff bf64 	b.w	46e6 <sys_clock_idle_exit>

0000481e <z_impl_k_mutex_init>:
{
    481e:	4603      	mov	r3, r0
	mutex->owner = NULL;
    4820:	2000      	movs	r0, #0
	mutex->lock_count = 0U;
    4822:	e9c3 0002 	strd	r0, r0, [r3, #8]
    4826:	e9c3 3300 	strd	r3, r3, [r3]
}
    482a:	4770      	bx	lr

0000482c <sys_dlist_remove>:
	sys_dnode_t *const next = node->next;
    482c:	e9d0 3200 	ldrd	r3, r2, [r0]
	prev->next = next;
    4830:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    4832:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    4834:	2300      	movs	r3, #0
	node->prev = NULL;
    4836:	e9c0 3300 	strd	r3, r3, [r0]
	sys_dnode_init(node);
}
    483a:	4770      	bx	lr

0000483c <unpend_thread_no_timeout>:
{
    483c:	b508      	push	{r3, lr}
	sys_dlist_remove(&thread->base.qnode_dlist);
    483e:	f7ff fff5 	bl	482c <sys_dlist_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    4842:	7b43      	ldrb	r3, [r0, #13]
    4844:	f023 0302 	bic.w	r3, r3, #2
    4848:	7343      	strb	r3, [r0, #13]
	thread->base.pended_on = NULL;
    484a:	2300      	movs	r3, #0
    484c:	6083      	str	r3, [r0, #8]
}
    484e:	bd08      	pop	{r3, pc}

00004850 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    4850:	4603      	mov	r3, r0
    4852:	b920      	cbnz	r0, 485e <z_reschedule_irqlock+0xe>
    4854:	f3ef 8205 	mrs	r2, IPSR
	if (resched(key)) {
    4858:	b90a      	cbnz	r2, 485e <z_reschedule_irqlock+0xe>
	ret = arch_swap(key);
    485a:	f7fc bc9d 	b.w	1198 <arch_swap>
    485e:	f383 8811 	msr	BASEPRI, r3
    4862:	f3bf 8f6f 	isb	sy
}
    4866:	4770      	bx	lr

00004868 <z_reschedule_unlocked>:
	__asm__ volatile(
    4868:	f04f 0320 	mov.w	r3, #32
    486c:	f3ef 8011 	mrs	r0, BASEPRI
    4870:	f383 8812 	msr	BASEPRI_MAX, r3
    4874:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    4878:	f7ff bfea 	b.w	4850 <z_reschedule_irqlock>

0000487c <z_priq_dumb_best>:
{
    487c:	4603      	mov	r3, r0
	return list->head == list;
    487e:	6800      	ldr	r0, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4880:	4283      	cmp	r3, r0
    4882:	d003      	beq.n	488c <z_priq_dumb_best+0x10>
	if (n != NULL) {
    4884:	2800      	cmp	r0, #0
    4886:	bf38      	it	cc
    4888:	2000      	movcc	r0, #0
    488a:	4770      	bx	lr
	struct k_thread *thread = NULL;
    488c:	2000      	movs	r0, #0
}
    488e:	4770      	bx	lr

00004890 <z_ready_thread>:
{
    4890:	b510      	push	{r4, lr}
    4892:	f04f 0320 	mov.w	r3, #32
    4896:	f3ef 8411 	mrs	r4, BASEPRI
    489a:	f383 8812 	msr	BASEPRI_MAX, r3
    489e:	f3bf 8f6f 	isb	sy
			ready_thread(thread);
    48a2:	f7fe fe33 	bl	350c <ready_thread>
	__asm__ volatile(
    48a6:	f384 8811 	msr	BASEPRI, r4
    48aa:	f3bf 8f6f 	isb	sy
}
    48ae:	bd10      	pop	{r4, pc}

000048b0 <z_thread_timeout>:
{
    48b0:	b510      	push	{r4, lr}
    48b2:	4601      	mov	r1, r0
	__asm__ volatile(
    48b4:	f04f 0320 	mov.w	r3, #32
    48b8:	f3ef 8411 	mrs	r4, BASEPRI
    48bc:	f383 8812 	msr	BASEPRI_MAX, r3
    48c0:	f3bf 8f6f 	isb	sy
		if (!killed) {
    48c4:	f810 3c0b 	ldrb.w	r3, [r0, #-11]
    48c8:	f013 0f28 	tst.w	r3, #40	; 0x28
    48cc:	d10d      	bne.n	48ea <z_thread_timeout+0x3a>
			if (thread->base.pended_on != NULL) {
    48ce:	f851 3c10 	ldr.w	r3, [r1, #-16]
	struct k_thread *thread = CONTAINER_OF(timeout,
    48d2:	3818      	subs	r0, #24
			if (thread->base.pended_on != NULL) {
    48d4:	b10b      	cbz	r3, 48da <z_thread_timeout+0x2a>
				unpend_thread_no_timeout(thread);
    48d6:	f7ff ffb1 	bl	483c <unpend_thread_no_timeout>
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    48da:	f811 3c0b 	ldrb.w	r3, [r1, #-11]
    48de:	f023 0314 	bic.w	r3, r3, #20
    48e2:	f801 3c0b 	strb.w	r3, [r1, #-11]
			ready_thread(thread);
    48e6:	f7fe fe11 	bl	350c <ready_thread>
	__asm__ volatile(
    48ea:	f384 8811 	msr	BASEPRI, r4
    48ee:	f3bf 8f6f 	isb	sy
}
    48f2:	bd10      	pop	{r4, pc}

000048f4 <add_to_waitq_locked>:
{
    48f4:	b538      	push	{r3, r4, r5, lr}
    48f6:	4604      	mov	r4, r0
    48f8:	460d      	mov	r5, r1
	unready_thread(thread);
    48fa:	f7fe fe5d 	bl	35b8 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    48fe:	7b63      	ldrb	r3, [r4, #13]
    4900:	f043 0302 	orr.w	r3, r3, #2
    4904:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    4906:	b1b5      	cbz	r5, 4936 <add_to_waitq_locked+0x42>
	return list->head == list;
    4908:	682b      	ldr	r3, [r5, #0]
		thread->base.pended_on = wait_q;
    490a:	60a5      	str	r5, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    490c:	429d      	cmp	r5, r3
    490e:	bf08      	it	eq
    4910:	2300      	moveq	r3, #0
    4912:	2b00      	cmp	r3, #0
    4914:	bf38      	it	cc
    4916:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4918:	b19b      	cbz	r3, 4942 <add_to_waitq_locked+0x4e>
	int32_t b1 = thread_1->base.prio;
    491a:	f994 100e 	ldrsb.w	r1, [r4, #14]
	int32_t b2 = thread_2->base.prio;
    491e:	f993 200e 	ldrsb.w	r2, [r3, #14]
	if (b1 != b2) {
    4922:	4291      	cmp	r1, r2
    4924:	d008      	beq.n	4938 <add_to_waitq_locked+0x44>
		return b2 - b1;
    4926:	1a52      	subs	r2, r2, r1
		if (z_sched_prio_cmp(thread, t) > 0) {
    4928:	2a00      	cmp	r2, #0
    492a:	dd05      	ble.n	4938 <add_to_waitq_locked+0x44>
	sys_dnode_t *const prev = successor->prev;
    492c:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    492e:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    4932:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    4934:	605c      	str	r4, [r3, #4]
}
    4936:	bd38      	pop	{r3, r4, r5, pc}
	return (node == list->tail) ? NULL : node->next;
    4938:	686a      	ldr	r2, [r5, #4]
    493a:	4293      	cmp	r3, r2
    493c:	d001      	beq.n	4942 <add_to_waitq_locked+0x4e>
    493e:	681b      	ldr	r3, [r3, #0]
    4940:	e7ea      	b.n	4918 <add_to_waitq_locked+0x24>
	sys_dnode_t *const tail = list->tail;
    4942:	686b      	ldr	r3, [r5, #4]
	node->prev = tail;
    4944:	e9c4 5300 	strd	r5, r3, [r4]
	tail->next = node;
    4948:	601c      	str	r4, [r3, #0]
	list->tail = node;
    494a:	606c      	str	r4, [r5, #4]
    494c:	e7f3      	b.n	4936 <add_to_waitq_locked+0x42>

0000494e <z_unpend_first_thread>:
{
    494e:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    4950:	f04f 0320 	mov.w	r3, #32
    4954:	f3ef 8511 	mrs	r5, BASEPRI
    4958:	f383 8812 	msr	BASEPRI_MAX, r3
    495c:	f3bf 8f6f 	isb	sy
		thread = _priq_wait_best(&wait_q->waitq);
    4960:	f7ff ff8c 	bl	487c <z_priq_dumb_best>
		if (thread != NULL) {
    4964:	4604      	mov	r4, r0
    4966:	b120      	cbz	r0, 4972 <z_unpend_first_thread+0x24>
			unpend_thread_no_timeout(thread);
    4968:	f7ff ff68 	bl	483c <unpend_thread_no_timeout>
    496c:	3018      	adds	r0, #24
    496e:	f000 f806 	bl	497e <z_abort_timeout>
	__asm__ volatile(
    4972:	f385 8811 	msr	BASEPRI, r5
    4976:	f3bf 8f6f 	isb	sy
}
    497a:	4620      	mov	r0, r4
    497c:	bd38      	pop	{r3, r4, r5, pc}

0000497e <z_abort_timeout>:
{
    497e:	b510      	push	{r4, lr}
	__asm__ volatile(
    4980:	f04f 0220 	mov.w	r2, #32
    4984:	f3ef 8411 	mrs	r4, BASEPRI
    4988:	f382 8812 	msr	BASEPRI_MAX, r2
    498c:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
    4990:	6803      	ldr	r3, [r0, #0]
    4992:	b13b      	cbz	r3, 49a4 <z_abort_timeout+0x26>
			remove_timeout(to);
    4994:	f7ff f82c 	bl	39f0 <remove_timeout>
			ret = 0;
    4998:	2000      	movs	r0, #0
	__asm__ volatile(
    499a:	f384 8811 	msr	BASEPRI, r4
    499e:	f3bf 8f6f 	isb	sy
}
    49a2:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
    49a4:	f06f 0015 	mvn.w	r0, #21
    49a8:	e7f7      	b.n	499a <z_abort_timeout+0x1c>

000049aa <z_get_next_timeout_expiry>:
{
    49aa:	b510      	push	{r4, lr}
	__asm__ volatile(
    49ac:	f04f 0320 	mov.w	r3, #32
    49b0:	f3ef 8411 	mrs	r4, BASEPRI
    49b4:	f383 8812 	msr	BASEPRI_MAX, r3
    49b8:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
    49bc:	f7ff f832 	bl	3a24 <next_timeout>
	__asm__ volatile(
    49c0:	f384 8811 	msr	BASEPRI, r4
    49c4:	f3bf 8f6f 	isb	sy
}
    49c8:	bd10      	pop	{r4, pc}

000049ca <z_set_timeout_expiry>:
{
    49ca:	b570      	push	{r4, r5, r6, lr}
    49cc:	4604      	mov	r4, r0
    49ce:	460d      	mov	r5, r1
	__asm__ volatile(
    49d0:	f04f 0320 	mov.w	r3, #32
    49d4:	f3ef 8611 	mrs	r6, BASEPRI
    49d8:	f383 8812 	msr	BASEPRI_MAX, r3
    49dc:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
    49e0:	f7ff f820 	bl	3a24 <next_timeout>
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
    49e4:	2801      	cmp	r0, #1
    49e6:	dd05      	ble.n	49f4 <z_set_timeout_expiry+0x2a>
    49e8:	42a0      	cmp	r0, r4
    49ea:	db03      	blt.n	49f4 <z_set_timeout_expiry+0x2a>
			sys_clock_set_timeout(MIN(ticks, next_to), is_idle);
    49ec:	4629      	mov	r1, r5
    49ee:	4620      	mov	r0, r4
    49f0:	f7fd fea2 	bl	2738 <sys_clock_set_timeout>
	__asm__ volatile(
    49f4:	f386 8811 	msr	BASEPRI, r6
    49f8:	f3bf 8f6f 	isb	sy
}
    49fc:	bd70      	pop	{r4, r5, r6, pc}

000049fe <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
    49fe:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
    4a00:	f7ff f930 	bl	3c64 <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    4a04:	bd08      	pop	{r3, pc}

00004a06 <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    4a06:	b108      	cbz	r0, 4a0c <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    4a08:	f7fc bf04 	b.w	1814 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    4a0c:	4770      	bx	lr

00004a0e <boot_banner>:
#else
	printk("*** Booting Zephyr OS version %s %s ***\n",
	       KERNEL_VERSION_STRING, BOOT_DELAY_BANNER);
#endif
#endif
}
    4a0e:	4770      	bx	lr

00004a10 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    4a10:	4770      	bx	lr
	...

00004a14 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    4a14:	f7fd bef0 	b.w	27f8 <SystemInit>
