
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

20000000 <_vector_start>:
20000000:	20020cd0 	.word	0x20020cd0
20000004:	20001319 	.word	0x20001319
20000008:	200039b5 	.word	0x200039b5
2000000c:	20001349 	.word	0x20001349
20000010:	20001349 	.word	0x20001349
20000014:	20001349 	.word	0x20001349
20000018:	20001349 	.word	0x20001349
2000001c:	20001349 	.word	0x20001349
	...
2000002c:	2000115d 	.word	0x2000115d
20000030:	20001349 	.word	0x20001349
20000034:	00000000 	.word	0x00000000
20000038:	20001105 	.word	0x20001105
2000003c:	2000398d 	.word	0x2000398d

20000040 <_irq_vector_table>:
20000040:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
20000050:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
20000060:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
20000070:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
20000080:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
20000090:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
200000a0:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
200000b0:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
200000c0:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
200000d0:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
200000e0:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
200000f0:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
20000100:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
20000110:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
20000120:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
20000130:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
20000140:	200012d9 200012d9 200012d9 200012d9     ... ... ... ... 
20000150:	200012d9                                ... 

Disassembly of section text:

20000154 <__aeabi_uldivmod>:
20000154:	b953      	cbnz	r3, 2000016c <__aeabi_uldivmod+0x18>
20000156:	b94a      	cbnz	r2, 2000016c <__aeabi_uldivmod+0x18>
20000158:	2900      	cmp	r1, #0
2000015a:	bf08      	it	eq
2000015c:	2800      	cmpeq	r0, #0
2000015e:	bf1c      	itt	ne
20000160:	f04f 31ff 	movne.w	r1, #4294967295
20000164:	f04f 30ff 	movne.w	r0, #4294967295
20000168:	f000 b970 	b.w	2000044c <__aeabi_idiv0>
2000016c:	f1ad 0c08 	sub.w	ip, sp, #8
20000170:	e96d ce04 	strd	ip, lr, [sp, #-16]!
20000174:	f000 f806 	bl	20000184 <__udivmoddi4>
20000178:	f8dd e004 	ldr.w	lr, [sp, #4]
2000017c:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
20000180:	b004      	add	sp, #16
20000182:	4770      	bx	lr

20000184 <__udivmoddi4>:
20000184:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
20000188:	9e08      	ldr	r6, [sp, #32]
2000018a:	460d      	mov	r5, r1
2000018c:	4604      	mov	r4, r0
2000018e:	468a      	mov	sl, r1
20000190:	2b00      	cmp	r3, #0
20000192:	d17f      	bne.n	20000294 <__udivmoddi4+0x110>
20000194:	428a      	cmp	r2, r1
20000196:	4617      	mov	r7, r2
20000198:	d941      	bls.n	2000021e <__udivmoddi4+0x9a>
2000019a:	fab2 f282 	clz	r2, r2
2000019e:	b14a      	cbz	r2, 200001b4 <__udivmoddi4+0x30>
200001a0:	f1c2 0120 	rsb	r1, r2, #32
200001a4:	fa05 f302 	lsl.w	r3, r5, r2
200001a8:	4097      	lsls	r7, r2
200001aa:	4094      	lsls	r4, r2
200001ac:	fa20 f101 	lsr.w	r1, r0, r1
200001b0:	ea41 0a03 	orr.w	sl, r1, r3
200001b4:	ea4f 4817 	mov.w	r8, r7, lsr #16
200001b8:	ea4f 4c14 	mov.w	ip, r4, lsr #16
200001bc:	fa1f f987 	uxth.w	r9, r7
200001c0:	fbba fef8 	udiv	lr, sl, r8
200001c4:	fb08 a31e 	mls	r3, r8, lr, sl
200001c8:	fb0e f109 	mul.w	r1, lr, r9
200001cc:	ea4c 4303 	orr.w	r3, ip, r3, lsl #16
200001d0:	4299      	cmp	r1, r3
200001d2:	d906      	bls.n	200001e2 <__udivmoddi4+0x5e>
200001d4:	18fb      	adds	r3, r7, r3
200001d6:	d202      	bcs.n	200001de <__udivmoddi4+0x5a>
200001d8:	4299      	cmp	r1, r3
200001da:	f200 8124 	bhi.w	20000426 <__udivmoddi4+0x2a2>
200001de:	f10e 3eff 	add.w	lr, lr, #4294967295
200001e2:	1a59      	subs	r1, r3, r1
200001e4:	b2a3      	uxth	r3, r4
200001e6:	fbb1 f0f8 	udiv	r0, r1, r8
200001ea:	fb08 1110 	mls	r1, r8, r0, r1
200001ee:	fb00 f909 	mul.w	r9, r0, r9
200001f2:	ea43 4401 	orr.w	r4, r3, r1, lsl #16
200001f6:	45a1      	cmp	r9, r4
200001f8:	d905      	bls.n	20000206 <__udivmoddi4+0x82>
200001fa:	193c      	adds	r4, r7, r4
200001fc:	d202      	bcs.n	20000204 <__udivmoddi4+0x80>
200001fe:	45a1      	cmp	r9, r4
20000200:	f200 810e 	bhi.w	20000420 <__udivmoddi4+0x29c>
20000204:	3801      	subs	r0, #1
20000206:	eba4 0409 	sub.w	r4, r4, r9
2000020a:	ea40 400e 	orr.w	r0, r0, lr, lsl #16
2000020e:	2100      	movs	r1, #0
20000210:	b11e      	cbz	r6, 2000021a <__udivmoddi4+0x96>
20000212:	40d4      	lsrs	r4, r2
20000214:	2300      	movs	r3, #0
20000216:	e9c6 4300 	strd	r4, r3, [r6]
2000021a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
2000021e:	b902      	cbnz	r2, 20000222 <__udivmoddi4+0x9e>
20000220:	deff      	udf	#255	; 0xff
20000222:	fab2 f282 	clz	r2, r2
20000226:	2a00      	cmp	r2, #0
20000228:	d14f      	bne.n	200002ca <__udivmoddi4+0x146>
2000022a:	1bcb      	subs	r3, r1, r7
2000022c:	ea4f 4e17 	mov.w	lr, r7, lsr #16
20000230:	fa1f f887 	uxth.w	r8, r7
20000234:	2101      	movs	r1, #1
20000236:	0c25      	lsrs	r5, r4, #16
20000238:	fbb3 fcfe 	udiv	ip, r3, lr
2000023c:	fb0e 301c 	mls	r0, lr, ip, r3
20000240:	462b      	mov	r3, r5
20000242:	fb08 f90c 	mul.w	r9, r8, ip
20000246:	ea45 4500 	orr.w	r5, r5, r0, lsl #16
2000024a:	45a9      	cmp	r9, r5
2000024c:	d90a      	bls.n	20000264 <__udivmoddi4+0xe0>
2000024e:	197d      	adds	r5, r7, r5
20000250:	bf2c      	ite	cs
20000252:	2301      	movcs	r3, #1
20000254:	2300      	movcc	r3, #0
20000256:	45a9      	cmp	r9, r5
20000258:	d902      	bls.n	20000260 <__udivmoddi4+0xdc>
2000025a:	2b00      	cmp	r3, #0
2000025c:	f000 80d9 	beq.w	20000412 <__udivmoddi4+0x28e>
20000260:	f10c 3cff 	add.w	ip, ip, #4294967295
20000264:	eba5 0509 	sub.w	r5, r5, r9
20000268:	b2a3      	uxth	r3, r4
2000026a:	fbb5 f0fe 	udiv	r0, r5, lr
2000026e:	fb0e 5510 	mls	r5, lr, r0, r5
20000272:	fb08 f800 	mul.w	r8, r8, r0
20000276:	ea43 4405 	orr.w	r4, r3, r5, lsl #16
2000027a:	45a0      	cmp	r8, r4
2000027c:	d905      	bls.n	2000028a <__udivmoddi4+0x106>
2000027e:	193c      	adds	r4, r7, r4
20000280:	d202      	bcs.n	20000288 <__udivmoddi4+0x104>
20000282:	45a0      	cmp	r8, r4
20000284:	f200 80c9 	bhi.w	2000041a <__udivmoddi4+0x296>
20000288:	3801      	subs	r0, #1
2000028a:	eba4 0408 	sub.w	r4, r4, r8
2000028e:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
20000292:	e7bd      	b.n	20000210 <__udivmoddi4+0x8c>
20000294:	428b      	cmp	r3, r1
20000296:	d908      	bls.n	200002aa <__udivmoddi4+0x126>
20000298:	2e00      	cmp	r6, #0
2000029a:	f000 80b1 	beq.w	20000400 <__udivmoddi4+0x27c>
2000029e:	2100      	movs	r1, #0
200002a0:	e9c6 0500 	strd	r0, r5, [r6]
200002a4:	4608      	mov	r0, r1
200002a6:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
200002aa:	fab3 f183 	clz	r1, r3
200002ae:	2900      	cmp	r1, #0
200002b0:	d146      	bne.n	20000340 <__udivmoddi4+0x1bc>
200002b2:	42ab      	cmp	r3, r5
200002b4:	f0c0 80a7 	bcc.w	20000406 <__udivmoddi4+0x282>
200002b8:	4282      	cmp	r2, r0
200002ba:	f240 80a4 	bls.w	20000406 <__udivmoddi4+0x282>
200002be:	4608      	mov	r0, r1
200002c0:	2e00      	cmp	r6, #0
200002c2:	d0aa      	beq.n	2000021a <__udivmoddi4+0x96>
200002c4:	e9c6 4a00 	strd	r4, sl, [r6]
200002c8:	e7a7      	b.n	2000021a <__udivmoddi4+0x96>
200002ca:	f1c2 0020 	rsb	r0, r2, #32
200002ce:	4097      	lsls	r7, r2
200002d0:	fa01 f302 	lsl.w	r3, r1, r2
200002d4:	ea4f 4e17 	mov.w	lr, r7, lsr #16
200002d8:	40c1      	lsrs	r1, r0
200002da:	fa24 f500 	lsr.w	r5, r4, r0
200002de:	fa1f f887 	uxth.w	r8, r7
200002e2:	4094      	lsls	r4, r2
200002e4:	431d      	orrs	r5, r3
200002e6:	fbb1 f0fe 	udiv	r0, r1, lr
200002ea:	0c2b      	lsrs	r3, r5, #16
200002ec:	fb0e 1110 	mls	r1, lr, r0, r1
200002f0:	fb00 fc08 	mul.w	ip, r0, r8
200002f4:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
200002f8:	459c      	cmp	ip, r3
200002fa:	d909      	bls.n	20000310 <__udivmoddi4+0x18c>
200002fc:	18fb      	adds	r3, r7, r3
200002fe:	bf2c      	ite	cs
20000300:	2101      	movcs	r1, #1
20000302:	2100      	movcc	r1, #0
20000304:	459c      	cmp	ip, r3
20000306:	d902      	bls.n	2000030e <__udivmoddi4+0x18a>
20000308:	2900      	cmp	r1, #0
2000030a:	f000 8095 	beq.w	20000438 <__udivmoddi4+0x2b4>
2000030e:	3801      	subs	r0, #1
20000310:	eba3 030c 	sub.w	r3, r3, ip
20000314:	b2ad      	uxth	r5, r5
20000316:	fbb3 f1fe 	udiv	r1, r3, lr
2000031a:	fb0e 3311 	mls	r3, lr, r1, r3
2000031e:	fb01 fc08 	mul.w	ip, r1, r8
20000322:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
20000326:	45ac      	cmp	ip, r5
20000328:	d905      	bls.n	20000336 <__udivmoddi4+0x1b2>
2000032a:	197d      	adds	r5, r7, r5
2000032c:	d202      	bcs.n	20000334 <__udivmoddi4+0x1b0>
2000032e:	45ac      	cmp	ip, r5
20000330:	f200 8089 	bhi.w	20000446 <__udivmoddi4+0x2c2>
20000334:	3901      	subs	r1, #1
20000336:	eba5 030c 	sub.w	r3, r5, ip
2000033a:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
2000033e:	e77a      	b.n	20000236 <__udivmoddi4+0xb2>
20000340:	f1c1 0420 	rsb	r4, r1, #32
20000344:	408b      	lsls	r3, r1
20000346:	fa02 f701 	lsl.w	r7, r2, r1
2000034a:	fa05 fc01 	lsl.w	ip, r5, r1
2000034e:	40e2      	lsrs	r2, r4
20000350:	fa20 f804 	lsr.w	r8, r0, r4
20000354:	40e5      	lsrs	r5, r4
20000356:	fa00 fe01 	lsl.w	lr, r0, r1
2000035a:	4313      	orrs	r3, r2
2000035c:	ea48 020c 	orr.w	r2, r8, ip
20000360:	ea4f 4813 	mov.w	r8, r3, lsr #16
20000364:	ea4f 4c12 	mov.w	ip, r2, lsr #16
20000368:	fa1f f983 	uxth.w	r9, r3
2000036c:	fbb5 faf8 	udiv	sl, r5, r8
20000370:	fb08 551a 	mls	r5, r8, sl, r5
20000374:	fb0a f009 	mul.w	r0, sl, r9
20000378:	ea4c 4c05 	orr.w	ip, ip, r5, lsl #16
2000037c:	4560      	cmp	r0, ip
2000037e:	d90a      	bls.n	20000396 <__udivmoddi4+0x212>
20000380:	eb13 0c0c 	adds.w	ip, r3, ip
20000384:	bf2c      	ite	cs
20000386:	2501      	movcs	r5, #1
20000388:	2500      	movcc	r5, #0
2000038a:	4560      	cmp	r0, ip
2000038c:	d901      	bls.n	20000392 <__udivmoddi4+0x20e>
2000038e:	2d00      	cmp	r5, #0
20000390:	d055      	beq.n	2000043e <__udivmoddi4+0x2ba>
20000392:	f10a 3aff 	add.w	sl, sl, #4294967295
20000396:	ebac 0c00 	sub.w	ip, ip, r0
2000039a:	b292      	uxth	r2, r2
2000039c:	fbbc f0f8 	udiv	r0, ip, r8
200003a0:	fb08 cc10 	mls	ip, r8, r0, ip
200003a4:	fb00 f909 	mul.w	r9, r0, r9
200003a8:	ea42 4c0c 	orr.w	ip, r2, ip, lsl #16
200003ac:	45e1      	cmp	r9, ip
200003ae:	d905      	bls.n	200003bc <__udivmoddi4+0x238>
200003b0:	eb13 0c0c 	adds.w	ip, r3, ip
200003b4:	d201      	bcs.n	200003ba <__udivmoddi4+0x236>
200003b6:	45e1      	cmp	r9, ip
200003b8:	d83b      	bhi.n	20000432 <__udivmoddi4+0x2ae>
200003ba:	3801      	subs	r0, #1
200003bc:	ea40 400a 	orr.w	r0, r0, sl, lsl #16
200003c0:	ebac 0c09 	sub.w	ip, ip, r9
200003c4:	fba0 8907 	umull	r8, r9, r0, r7
200003c8:	45cc      	cmp	ip, r9
200003ca:	4645      	mov	r5, r8
200003cc:	464a      	mov	r2, r9
200003ce:	d302      	bcc.n	200003d6 <__udivmoddi4+0x252>
200003d0:	d106      	bne.n	200003e0 <__udivmoddi4+0x25c>
200003d2:	45c6      	cmp	lr, r8
200003d4:	d204      	bcs.n	200003e0 <__udivmoddi4+0x25c>
200003d6:	3801      	subs	r0, #1
200003d8:	ebb8 0507 	subs.w	r5, r8, r7
200003dc:	eb69 0203 	sbc.w	r2, r9, r3
200003e0:	b32e      	cbz	r6, 2000042e <__udivmoddi4+0x2aa>
200003e2:	ebbe 0305 	subs.w	r3, lr, r5
200003e6:	eb6c 0c02 	sbc.w	ip, ip, r2
200003ea:	fa23 f201 	lsr.w	r2, r3, r1
200003ee:	fa0c f404 	lsl.w	r4, ip, r4
200003f2:	fa2c f301 	lsr.w	r3, ip, r1
200003f6:	2100      	movs	r1, #0
200003f8:	4314      	orrs	r4, r2
200003fa:	e9c6 4300 	strd	r4, r3, [r6]
200003fe:	e70c      	b.n	2000021a <__udivmoddi4+0x96>
20000400:	4631      	mov	r1, r6
20000402:	4630      	mov	r0, r6
20000404:	e709      	b.n	2000021a <__udivmoddi4+0x96>
20000406:	1a84      	subs	r4, r0, r2
20000408:	eb65 0303 	sbc.w	r3, r5, r3
2000040c:	2001      	movs	r0, #1
2000040e:	469a      	mov	sl, r3
20000410:	e756      	b.n	200002c0 <__udivmoddi4+0x13c>
20000412:	f1ac 0c02 	sub.w	ip, ip, #2
20000416:	443d      	add	r5, r7
20000418:	e724      	b.n	20000264 <__udivmoddi4+0xe0>
2000041a:	3802      	subs	r0, #2
2000041c:	443c      	add	r4, r7
2000041e:	e734      	b.n	2000028a <__udivmoddi4+0x106>
20000420:	3802      	subs	r0, #2
20000422:	443c      	add	r4, r7
20000424:	e6ef      	b.n	20000206 <__udivmoddi4+0x82>
20000426:	f1ae 0e02 	sub.w	lr, lr, #2
2000042a:	443b      	add	r3, r7
2000042c:	e6d9      	b.n	200001e2 <__udivmoddi4+0x5e>
2000042e:	4631      	mov	r1, r6
20000430:	e6f3      	b.n	2000021a <__udivmoddi4+0x96>
20000432:	3802      	subs	r0, #2
20000434:	449c      	add	ip, r3
20000436:	e7c1      	b.n	200003bc <__udivmoddi4+0x238>
20000438:	3802      	subs	r0, #2
2000043a:	443b      	add	r3, r7
2000043c:	e768      	b.n	20000310 <__udivmoddi4+0x18c>
2000043e:	f1aa 0a02 	sub.w	sl, sl, #2
20000442:	449c      	add	ip, r3
20000444:	e7a7      	b.n	20000396 <__udivmoddi4+0x212>
20000446:	3902      	subs	r1, #2
20000448:	443d      	add	r5, r7
2000044a:	e774      	b.n	20000336 <__udivmoddi4+0x1b2>

2000044c <__aeabi_idiv0>:
2000044c:	4770      	bx	lr
2000044e:	bf00      	nop

20000450 <main>:
#define PIN	0
#define FLAGS	0
#endif

void main(void)
{
20000450:	b570      	push	{r4, r5, r6, lr}
	if (z_syscall_trap()) {
		return (const struct device *) arch_syscall_invoke1(*(uintptr_t *)&name, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
20000452:	4817      	ldr	r0, [pc, #92]	; (200004b0 <main+0x60>)
20000454:	f001 ff1e 	bl	20002294 <z_impl_device_get_binding>
	const struct device *dev;
	bool led_is_on = true;
	int ret;

	dev = device_get_binding(LED0);
	if (dev == NULL) {
20000458:	4604      	mov	r4, r0
2000045a:	b320      	cbz	r0, 200004a6 <main+0x56>
{
	const struct gpio_driver_api *api =
		(const struct gpio_driver_api *)port->api;
	const struct gpio_driver_config *const cfg =
		(const struct gpio_driver_config *)port->config;
	struct gpio_driver_data *data =
2000045c:	68c5      	ldr	r5, [r0, #12]
	return api->pin_configure(port, pin, flags);
2000045e:	6883      	ldr	r3, [r0, #8]
20000460:	f240 6201 	movw	r2, #1537	; 0x601
20000464:	211c      	movs	r1, #28
20000466:	681b      	ldr	r3, [r3, #0]
20000468:	4798      	blx	r3
	(void)cfg;
	__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
		 "Unsupported pin");

	ret = gpio_config(port, pin, flags);
	if (ret != 0) {
2000046a:	2800      	cmp	r0, #0
2000046c:	d11a      	bne.n	200004a4 <main+0x54>
		return ret;
	}

	if ((flags & GPIO_ACTIVE_LOW) != 0) {
		data->invert |= (gpio_port_pins_t)BIT(pin);
2000046e:	682b      	ldr	r3, [r5, #0]
20000470:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
20000474:	602b      	str	r3, [r5, #0]
{
20000476:	2501      	movs	r5, #1

	(void)cfg;
	__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
		 "Unsupported pin");

	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
20000478:	68e3      	ldr	r3, [r4, #12]
2000047a:	f085 0601 	eor.w	r6, r5, #1
2000047e:	681b      	ldr	r3, [r3, #0]
20000480:	f013 5f80 	tst.w	r3, #268435456	; 0x10000000
		value = (value != 0) ? 0 : 1;
20000484:	bf18      	it	ne
20000486:	b2f5      	uxtbne	r5, r6
	if (value != 0)	{
20000488:	b175      	cbz	r5, 200004a8 <main+0x58>
	return api->port_set_bits_raw(port, pins);
2000048a:	68a3      	ldr	r3, [r4, #8]
2000048c:	68db      	ldr	r3, [r3, #12]
	return api->port_clear_bits_raw(port, pins);
2000048e:	f04f 5180 	mov.w	r1, #268435456	; 0x10000000
20000492:	4620      	mov	r0, r4
20000494:	4798      	blx	r3
		return;
	}

	while (1) {
		gpio_pin_set(dev, PIN, (int)led_is_on);
		led_is_on = !led_is_on;
20000496:	b2f5      	uxtb	r5, r6
		parm0.val = timeout;
		return (int32_t) arch_syscall_invoke2(parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SLEEP);
	}
#endif
	compiler_barrier();
	return z_impl_k_sleep(timeout);
20000498:	2100      	movs	r1, #0
2000049a:	f44f 4000 	mov.w	r0, #32768	; 0x8000
2000049e:	f002 fc7b 	bl	20002d98 <z_impl_k_sleep>
 * @return Zero if the requested time has elapsed or the number of milliseconds
 * left to sleep, if thread was woken up by \ref k_wakeup call.
 */
static inline int32_t k_msleep(int32_t ms)
{
	return k_sleep(Z_TIMEOUT_MS(ms));
200004a2:	e7e9      	b.n	20000478 <main+0x28>
	if (ret < 0) {
200004a4:	dae7      	bge.n	20000476 <main+0x26>
		k_msleep(SLEEP_TIME_MS);
	}
}
200004a6:	bd70      	pop	{r4, r5, r6, pc}
200004a8:	68a3      	ldr	r3, [r4, #8]
200004aa:	691b      	ldr	r3, [r3, #16]
200004ac:	e7ef      	b.n	2000048e <main+0x3e>
200004ae:	bf00      	nop
200004b0:	200043d0 	.word	0x200043d0

200004b4 <print_digits>:
}
#endif /* CONFIG_PRINTK */

static void print_digits(out_func_t out, void *ctx, printk_val_t num, int base,
			 bool pad_before, char pad_char, int min_width)
{
200004b4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
200004b8:	b087      	sub	sp, #28
200004ba:	460f      	mov	r7, r1
200004bc:	4619      	mov	r1, r3
	char buf[DIGITS_BUFLEN];
	int i;

	/* Print it backwards into the end of the buffer, low digits first */
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
		buf[i] = "0123456789abcdef"[num % base];
200004be:	9b10      	ldr	r3, [sp, #64]	; 0x40
{
200004c0:	4606      	mov	r6, r0
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
200004c2:	2514      	movs	r5, #20
{
200004c4:	4610      	mov	r0, r2
		buf[i] = "0123456789abcdef"[num % base];
200004c6:	4698      	mov	r8, r3
{
200004c8:	f89d b044 	ldrb.w	fp, [sp, #68]	; 0x44
200004cc:	f89d a048 	ldrb.w	sl, [sp, #72]	; 0x48
		buf[i] = "0123456789abcdef"[num % base];
200004d0:	4c1e      	ldr	r4, [pc, #120]	; (2000054c <print_digits+0x98>)
200004d2:	ea4f 79e3 	mov.w	r9, r3, asr #31
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
200004d6:	ea50 0301 	orrs.w	r3, r0, r1
200004da:	d11a      	bne.n	20000512 <print_digits+0x5e>
		num /= base;
	}

	if (i == DIGITS_BUFLEN - 1) {
200004dc:	2d14      	cmp	r5, #20
		buf[i] = '0';
200004de:	bf08      	it	eq
200004e0:	2330      	moveq	r3, #48	; 0x30
	} else {
		i++;
	}

	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
200004e2:	9c13      	ldr	r4, [sp, #76]	; 0x4c
		i++;
200004e4:	bf18      	it	ne
200004e6:	3501      	addne	r5, #1
	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
200004e8:	442c      	add	r4, r5
		buf[i] = '0';
200004ea:	bf08      	it	eq
200004ec:	f88d 3014 	strbeq.w	r3, [sp, #20]
	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
200004f0:	2c15      	cmp	r4, #21
200004f2:	d01b      	beq.n	2000052c <print_digits+0x78>
200004f4:	3c15      	subs	r4, #21

	for (/**/; pad > 0 && pad_before; pad--) {
200004f6:	2c00      	cmp	r4, #0
200004f8:	dc1a      	bgt.n	20000530 <print_digits+0x7c>
		out(pad_char, ctx);
	}
	for (/**/; i < DIGITS_BUFLEN; i++) {
		out(buf[i], ctx);
200004fa:	f81d 0005 	ldrb.w	r0, [sp, r5]
200004fe:	4639      	mov	r1, r7
	for (/**/; i < DIGITS_BUFLEN; i++) {
20000500:	3501      	adds	r5, #1
		out(buf[i], ctx);
20000502:	47b0      	blx	r6
	for (/**/; i < DIGITS_BUFLEN; i++) {
20000504:	2d15      	cmp	r5, #21
20000506:	d1f8      	bne.n	200004fa <print_digits+0x46>
	}
	for (/**/; pad > 0; pad--) {
20000508:	2c00      	cmp	r4, #0
2000050a:	dc19      	bgt.n	20000540 <print_digits+0x8c>
		out(pad_char, ctx);
	}
}
2000050c:	b007      	add	sp, #28
2000050e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		buf[i] = "0123456789abcdef"[num % base];
20000512:	4642      	mov	r2, r8
20000514:	464b      	mov	r3, r9
20000516:	f7ff fe1d 	bl	20000154 <__aeabi_uldivmod>
2000051a:	4684      	mov	ip, r0
2000051c:	460b      	mov	r3, r1
2000051e:	5ca2      	ldrb	r2, [r4, r2]
		num /= base;
20000520:	4660      	mov	r0, ip
		buf[i] = "0123456789abcdef"[num % base];
20000522:	f80d 2005 	strb.w	r2, [sp, r5]
		num /= base;
20000526:	4619      	mov	r1, r3
	for (i = DIGITS_BUFLEN - 1; num != 0; i--) {
20000528:	3d01      	subs	r5, #1
2000052a:	e7d4      	b.n	200004d6 <print_digits+0x22>
	int pad = MAX(min_width - (DIGITS_BUFLEN - i), 0);
2000052c:	2400      	movs	r4, #0
	for (/**/; i < DIGITS_BUFLEN; i++) {
2000052e:	e7e4      	b.n	200004fa <print_digits+0x46>
	for (/**/; pad > 0 && pad_before; pad--) {
20000530:	f1bb 0f00 	cmp.w	fp, #0
20000534:	d0e1      	beq.n	200004fa <print_digits+0x46>
		out(pad_char, ctx);
20000536:	4639      	mov	r1, r7
20000538:	4650      	mov	r0, sl
2000053a:	47b0      	blx	r6
	for (/**/; pad > 0 && pad_before; pad--) {
2000053c:	3c01      	subs	r4, #1
2000053e:	e7da      	b.n	200004f6 <print_digits+0x42>
		out(pad_char, ctx);
20000540:	4639      	mov	r1, r7
20000542:	4650      	mov	r0, sl
20000544:	47b0      	blx	r6
	for (/**/; pad > 0; pad--) {
20000546:	3c01      	subs	r4, #1
20000548:	e7de      	b.n	20000508 <print_digits+0x54>
2000054a:	bf00      	nop
2000054c:	200043d7 	.word	0x200043d7

20000550 <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
20000550:	680b      	ldr	r3, [r1, #0]
20000552:	3301      	adds	r3, #1
20000554:	600b      	str	r3, [r1, #0]
	return _char_out(c);
20000556:	4b01      	ldr	r3, [pc, #4]	; (2000055c <char_out+0xc>)
20000558:	681b      	ldr	r3, [r3, #0]
2000055a:	4718      	bx	r3
2000055c:	20020000 	.word	0x20020000

20000560 <__printk_hook_install>:
	_char_out = fn;
20000560:	4b01      	ldr	r3, [pc, #4]	; (20000568 <__printk_hook_install+0x8>)
20000562:	6018      	str	r0, [r3, #0]
}
20000564:	4770      	bx	lr
20000566:	bf00      	nop
20000568:	20020000 	.word	0x20020000

2000056c <z_vprintk>:
{
2000056c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
	char length_mod = 0;
20000570:	2600      	movs	r6, #0
{
20000572:	4605      	mov	r5, r0
20000574:	468b      	mov	fp, r1
20000576:	461c      	mov	r4, r3
	int min_width = -1;
20000578:	f04f 38ff 	mov.w	r8, #4294967295
	enum pad_type padding = PAD_NONE;
2000057c:	4637      	mov	r7, r6
{
2000057e:	b087      	sub	sp, #28
20000580:	f102 3aff 	add.w	sl, r2, #4294967295
			might_format = 0;
20000584:	f04f 0900 	mov.w	r9, #0
					break;
20000588:	e007      	b.n	2000059a <z_vprintk+0x2e>
		if (!might_format) {
2000058a:	f1b9 0f00 	cmp.w	r9, #0
2000058e:	d10b      	bne.n	200005a8 <z_vprintk+0x3c>
			if (*fmt != '%') {
20000590:	2825      	cmp	r0, #37	; 0x25
20000592:	f000 810a 	beq.w	200007aa <z_vprintk+0x23e>
				out((int)*fmt, ctx);
20000596:	4659      	mov	r1, fp
20000598:	47a8      	blx	r5
	while (*fmt) {
2000059a:	f81a 0f01 	ldrb.w	r0, [sl, #1]!
2000059e:	2800      	cmp	r0, #0
200005a0:	d1f3      	bne.n	2000058a <z_vprintk+0x1e>
}
200005a2:	b007      	add	sp, #28
200005a4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			switch (*fmt) {
200005a8:	287a      	cmp	r0, #122	; 0x7a
200005aa:	d80a      	bhi.n	200005c2 <z_vprintk+0x56>
200005ac:	2862      	cmp	r0, #98	; 0x62
200005ae:	d810      	bhi.n	200005d2 <z_vprintk+0x66>
200005b0:	2830      	cmp	r0, #48	; 0x30
200005b2:	d051      	beq.n	20000658 <z_vprintk+0xec>
200005b4:	d844      	bhi.n	20000640 <z_vprintk+0xd4>
200005b6:	2825      	cmp	r0, #37	; 0x25
200005b8:	f000 80f5 	beq.w	200007a6 <z_vprintk+0x23a>
200005bc:	282d      	cmp	r0, #45	; 0x2d
200005be:	f000 80fb 	beq.w	200007b8 <z_vprintk+0x24c>
					out((int)'%', ctx);
200005c2:	4659      	mov	r1, fp
200005c4:	2025      	movs	r0, #37	; 0x25
200005c6:	47a8      	blx	r5
					out((int)*fmt, ctx);
200005c8:	4659      	mov	r1, fp
200005ca:	f89a 0000 	ldrb.w	r0, [sl]
200005ce:	47a8      	blx	r5
200005d0:	e7d8      	b.n	20000584 <z_vprintk+0x18>
200005d2:	f1a0 0363 	sub.w	r3, r0, #99	; 0x63
200005d6:	2b17      	cmp	r3, #23
200005d8:	d8f3      	bhi.n	200005c2 <z_vprintk+0x56>
200005da:	a201      	add	r2, pc, #4	; (adr r2, 200005e0 <z_vprintk+0x74>)
200005dc:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
200005e0:	2000079f 	.word	0x2000079f
200005e4:	200006a1 	.word	0x200006a1
200005e8:	200005c3 	.word	0x200005c3
200005ec:	200005c3 	.word	0x200005c3
200005f0:	200005c3 	.word	0x200005c3
200005f4:	20000683 	.word	0x20000683
200005f8:	200006a1 	.word	0x200006a1
200005fc:	200005c3 	.word	0x200005c3
20000600:	200005c3 	.word	0x200005c3
20000604:	20000683 	.word	0x20000683
20000608:	200005c3 	.word	0x200005c3
2000060c:	200005c3 	.word	0x200005c3
20000610:	200005c3 	.word	0x200005c3
20000614:	2000071b 	.word	0x2000071b
20000618:	200005c3 	.word	0x200005c3
2000061c:	200005c3 	.word	0x200005c3
20000620:	20000767 	.word	0x20000767
20000624:	200005c3 	.word	0x200005c3
20000628:	200006a1 	.word	0x200006a1
2000062c:	200005c3 	.word	0x200005c3
20000630:	200005c3 	.word	0x200005c3
20000634:	20000649 	.word	0x20000649
20000638:	200005c3 	.word	0x200005c3
2000063c:	20000683 	.word	0x20000683
			switch (*fmt) {
20000640:	2839      	cmp	r0, #57	; 0x39
20000642:	d915      	bls.n	20000670 <z_vprintk+0x104>
20000644:	2858      	cmp	r0, #88	; 0x58
20000646:	d1bc      	bne.n	200005c2 <z_vprintk+0x56>
				if (*fmt == 'p') {
20000648:	f89a 3000 	ldrb.w	r3, [sl]
2000064c:	2b70      	cmp	r3, #112	; 0x70
2000064e:	d16e      	bne.n	2000072e <z_vprintk+0x1c2>
					x = va_arg(ap, unsigned int);
20000650:	2300      	movs	r3, #0
20000652:	f854 2b04 	ldr.w	r2, [r4], #4
20000656:	e075      	b.n	20000744 <z_vprintk+0x1d8>
				if (min_width < 0 && padding == PAD_NONE) {
20000658:	f1b8 0f00 	cmp.w	r8, #0
2000065c:	da0b      	bge.n	20000676 <z_vprintk+0x10a>
2000065e:	2f00      	cmp	r7, #0
20000660:	f000 80ac 	beq.w	200007bc <z_vprintk+0x250>
					min_width = *fmt - '0';
20000664:	f1a0 0830 	sub.w	r8, r0, #48	; 0x30
					padding = PAD_SPACE_BEFORE;
20000668:	2f00      	cmp	r7, #0
2000066a:	bf08      	it	eq
2000066c:	2702      	moveq	r7, #2
2000066e:	e794      	b.n	2000059a <z_vprintk+0x2e>
				if (min_width < 0) {
20000670:	f1b8 0f00 	cmp.w	r8, #0
20000674:	dbf6      	blt.n	20000664 <z_vprintk+0xf8>
					min_width = 10 * min_width + *fmt - '0';
20000676:	230a      	movs	r3, #10
20000678:	fb03 0808 	mla	r8, r3, r8, r0
2000067c:	f1a8 0830 	sub.w	r8, r8, #48	; 0x30
20000680:	e7f2      	b.n	20000668 <z_vprintk+0xfc>
				if (*fmt == 'h' && length_mod == 'h') {
20000682:	2868      	cmp	r0, #104	; 0x68
20000684:	d103      	bne.n	2000068e <z_vprintk+0x122>
20000686:	2e68      	cmp	r6, #104	; 0x68
20000688:	d106      	bne.n	20000698 <z_vprintk+0x12c>
					length_mod = 'H';
2000068a:	2648      	movs	r6, #72	; 0x48
2000068c:	e785      	b.n	2000059a <z_vprintk+0x2e>
				} else if (*fmt == 'l' && length_mod == 'l') {
2000068e:	286c      	cmp	r0, #108	; 0x6c
20000690:	d102      	bne.n	20000698 <z_vprintk+0x12c>
20000692:	2e6c      	cmp	r6, #108	; 0x6c
20000694:	f000 8094 	beq.w	200007c0 <z_vprintk+0x254>
				} else if (length_mod == 0) {
20000698:	2e00      	cmp	r6, #0
2000069a:	d192      	bne.n	200005c2 <z_vprintk+0x56>
2000069c:	4606      	mov	r6, r0
2000069e:	e77c      	b.n	2000059a <z_vprintk+0x2e>
				if (length_mod == 'z') {
200006a0:	2e7a      	cmp	r6, #122	; 0x7a
200006a2:	d106      	bne.n	200006b2 <z_vprintk+0x146>
					d = va_arg(ap, long);
200006a4:	46a1      	mov	r9, r4
200006a6:	f859 2b04 	ldr.w	r2, [r9], #4
200006aa:	17d3      	asrs	r3, r2, #31
				if (*fmt != 'u' && negative(d)) {
200006ac:	2875      	cmp	r0, #117	; 0x75
200006ae:	d123      	bne.n	200006f8 <z_vprintk+0x18c>
200006b0:	e00f      	b.n	200006d2 <z_vprintk+0x166>
				} else if (length_mod == 'l') {
200006b2:	2e6c      	cmp	r6, #108	; 0x6c
200006b4:	d0f6      	beq.n	200006a4 <z_vprintk+0x138>
				} else if (length_mod == 'L') {
200006b6:	2e4c      	cmp	r6, #76	; 0x4c
200006b8:	d105      	bne.n	200006c6 <z_vprintk+0x15a>
					long long lld = va_arg(ap, long long);
200006ba:	3407      	adds	r4, #7
200006bc:	f024 0907 	bic.w	r9, r4, #7
					d = (printk_val_t) lld;
200006c0:	e8f9 2302 	ldrd	r2, r3, [r9], #8
200006c4:	e7f2      	b.n	200006ac <z_vprintk+0x140>
				} else if (*fmt == 'u') {
200006c6:	2875      	cmp	r0, #117	; 0x75
					d = va_arg(ap, unsigned int);
200006c8:	6822      	ldr	r2, [r4, #0]
200006ca:	f104 0904 	add.w	r9, r4, #4
				} else if (*fmt == 'u') {
200006ce:	d112      	bne.n	200006f6 <z_vprintk+0x18a>
					d = va_arg(ap, unsigned int);
200006d0:	2300      	movs	r3, #0
	print_digits(out, ctx, num, 10, padding != PAD_SPACE_AFTER,
200006d2:	1ef8      	subs	r0, r7, #3
200006d4:	bf18      	it	ne
200006d6:	2001      	movne	r0, #1
200006d8:	2f01      	cmp	r7, #1
200006da:	bf0c      	ite	eq
200006dc:	2430      	moveq	r4, #48	; 0x30
200006de:	2420      	movne	r4, #32
200006e0:	9001      	str	r0, [sp, #4]
200006e2:	200a      	movs	r0, #10
200006e4:	e9cd 4802 	strd	r4, r8, [sp, #8]
200006e8:	9000      	str	r0, [sp, #0]
200006ea:	4659      	mov	r1, fp
200006ec:	4628      	mov	r0, r5
200006ee:	f7ff fee1 	bl	200004b4 <print_digits>
}
200006f2:	464c      	mov	r4, r9
200006f4:	e746      	b.n	20000584 <z_vprintk+0x18>
					d = va_arg(ap, int);
200006f6:	17d3      	asrs	r3, r2, #31
				if (*fmt != 'u' && negative(d)) {
200006f8:	2a00      	cmp	r2, #0
200006fa:	f173 0100 	sbcs.w	r1, r3, #0
200006fe:	dae8      	bge.n	200006d2 <z_vprintk+0x166>
					out((int)'-', ctx);
20000700:	4659      	mov	r1, fp
20000702:	202d      	movs	r0, #45	; 0x2d
20000704:	e9cd 2304 	strd	r2, r3, [sp, #16]
20000708:	47a8      	blx	r5
					d = -d;
2000070a:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
2000070e:	4252      	negs	r2, r2
20000710:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
					min_width--;
20000714:	f108 38ff 	add.w	r8, r8, #4294967295
20000718:	e7db      	b.n	200006d2 <z_vprintk+0x166>
				out('0', ctx);
2000071a:	4659      	mov	r1, fp
2000071c:	2030      	movs	r0, #48	; 0x30
2000071e:	47a8      	blx	r5
				out('x', ctx);
20000720:	4659      	mov	r1, fp
20000722:	2078      	movs	r0, #120	; 0x78
20000724:	47a8      	blx	r5
				min_width = sizeof(void *) * 2;
20000726:	f04f 0808 	mov.w	r8, #8
				padding = PAD_ZERO_BEFORE;
2000072a:	2701      	movs	r7, #1
2000072c:	e78c      	b.n	20000648 <z_vprintk+0xdc>
				} else if (length_mod == 'l') {
2000072e:	2e6c      	cmp	r6, #108	; 0x6c
20000730:	d08e      	beq.n	20000650 <z_vprintk+0xe4>
				} else if (length_mod == 'L') {
20000732:	2e4c      	cmp	r6, #76	; 0x4c
20000734:	d18c      	bne.n	20000650 <z_vprintk+0xe4>
					x = va_arg(ap, unsigned long long);
20000736:	1de3      	adds	r3, r4, #7
20000738:	f023 0307 	bic.w	r3, r3, #7
2000073c:	461c      	mov	r4, r3
2000073e:	685b      	ldr	r3, [r3, #4]
20000740:	f854 2b08 	ldr.w	r2, [r4], #8
	print_digits(out, ctx, num, 16, padding != PAD_SPACE_AFTER,
20000744:	1ef8      	subs	r0, r7, #3
20000746:	bf18      	it	ne
20000748:	2001      	movne	r0, #1
2000074a:	2f01      	cmp	r7, #1
2000074c:	bf0c      	ite	eq
2000074e:	2130      	moveq	r1, #48	; 0x30
20000750:	2120      	movne	r1, #32
20000752:	e9cd 1802 	strd	r1, r8, [sp, #8]
20000756:	2110      	movs	r1, #16
20000758:	9001      	str	r0, [sp, #4]
2000075a:	9100      	str	r1, [sp, #0]
2000075c:	4628      	mov	r0, r5
2000075e:	4659      	mov	r1, fp
20000760:	f7ff fea8 	bl	200004b4 <print_digits>
20000764:	e70e      	b.n	20000584 <z_vprintk+0x18>
				char *s = va_arg(ap, char *);
20000766:	f854 3b04 	ldr.w	r3, [r4], #4
				while (*s) {
2000076a:	4699      	mov	r9, r3
2000076c:	464a      	mov	r2, r9
2000076e:	f819 0b01 	ldrb.w	r0, [r9], #1
20000772:	b978      	cbnz	r0, 20000794 <z_vprintk+0x228>
				if (padding == PAD_SPACE_AFTER) {
20000774:	2f03      	cmp	r7, #3
20000776:	d125      	bne.n	200007c4 <z_vprintk+0x258>
					int remaining = min_width - (s - start);
20000778:	eba2 0903 	sub.w	r9, r2, r3
2000077c:	eba8 0909 	sub.w	r9, r8, r9
					while (remaining-- > 0) {
20000780:	f1b9 0f00 	cmp.w	r9, #0
20000784:	f77f aefe 	ble.w	20000584 <z_vprintk+0x18>
						out(' ', ctx);
20000788:	4659      	mov	r1, fp
2000078a:	2020      	movs	r0, #32
2000078c:	47a8      	blx	r5
2000078e:	f109 39ff 	add.w	r9, r9, #4294967295
20000792:	e7f5      	b.n	20000780 <z_vprintk+0x214>
					out((int)(*s++), ctx);
20000794:	4659      	mov	r1, fp
20000796:	9304      	str	r3, [sp, #16]
20000798:	47a8      	blx	r5
2000079a:	9b04      	ldr	r3, [sp, #16]
2000079c:	e7e6      	b.n	2000076c <z_vprintk+0x200>
				out(c, ctx);
2000079e:	4659      	mov	r1, fp
200007a0:	f854 0b04 	ldr.w	r0, [r4], #4
200007a4:	e713      	b.n	200005ce <z_vprintk+0x62>
				out((int)'%', ctx);
200007a6:	4659      	mov	r1, fp
200007a8:	e711      	b.n	200005ce <z_vprintk+0x62>
				length_mod = 0;
200007aa:	464e      	mov	r6, r9
				padding = PAD_NONE;
200007ac:	464f      	mov	r7, r9
				min_width = -1;
200007ae:	f04f 38ff 	mov.w	r8, #4294967295
				might_format = 1;
200007b2:	f04f 0901 	mov.w	r9, #1
200007b6:	e6f0      	b.n	2000059a <z_vprintk+0x2e>
			switch (*fmt) {
200007b8:	2703      	movs	r7, #3
200007ba:	e6ee      	b.n	2000059a <z_vprintk+0x2e>
					padding = PAD_ZERO_BEFORE;
200007bc:	2701      	movs	r7, #1
200007be:	e6ec      	b.n	2000059a <z_vprintk+0x2e>
					length_mod = 'L';
200007c0:	264c      	movs	r6, #76	; 0x4c
200007c2:	e6ea      	b.n	2000059a <z_vprintk+0x2e>
			might_format = 0;
200007c4:	4681      	mov	r9, r0
200007c6:	e6e8      	b.n	2000059a <z_vprintk+0x2e>

200007c8 <vprintk>:
#endif
	}
}
#else
void vprintk(const char *fmt, va_list ap)
{
200007c8:	b507      	push	{r0, r1, r2, lr}
200007ca:	460b      	mov	r3, r1
	struct out_context ctx = { 0 };
200007cc:	2100      	movs	r1, #0
{
200007ce:	4602      	mov	r2, r0
	struct out_context ctx = { 0 };
200007d0:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
	k_spinlock_key_t key = k_spin_lock(&lock);
#endif

	z_vprintk(char_out, &ctx, fmt, ap);
200007d2:	4803      	ldr	r0, [pc, #12]	; (200007e0 <vprintk+0x18>)
200007d4:	a901      	add	r1, sp, #4
200007d6:	f7ff fec9 	bl	2000056c <z_vprintk>

#ifdef CONFIG_PRINTK_SYNC
	k_spin_unlock(&lock, key);
#endif
}
200007da:	b003      	add	sp, #12
200007dc:	f85d fb04 	ldr.w	pc, [sp], #4
200007e0:	20000551 	.word	0x20000551

200007e4 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
200007e4:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
200007e8:	f8b0 9018 	ldrh.w	r9, [r0, #24]
{
200007ec:	4604      	mov	r4, r0
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
200007ee:	f019 0808 	ands.w	r8, r9, #8
{
200007f2:	4693      	mov	fp, r2
	if (processing) {
200007f4:	d00d      	beq.n	20000812 <process_event+0x2e>
		if (evt == EVT_COMPLETE) {
200007f6:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
200007f8:	bf0c      	ite	eq
200007fa:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
200007fe:	f049 0920 	orrne.w	r9, r9, #32
20000802:	f8a0 9018 	strh.w	r9, [r0, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
20000806:	f38b 8811 	msr	BASEPRI, fp
2000080a:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
2000080e:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
20000812:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
20000816:	2902      	cmp	r1, #2
20000818:	d107      	bne.n	2000082a <process_event+0x46>
			evt = process_recheck(mgr);
2000081a:	4620      	mov	r0, r4
2000081c:	f002 fe85 	bl	2000352a <process_recheck>
		if (evt == EVT_NOP) {
20000820:	2800      	cmp	r0, #0
20000822:	d0f0      	beq.n	20000806 <process_event+0x22>
		if (evt == EVT_COMPLETE) {
20000824:	2801      	cmp	r0, #1
20000826:	8b23      	ldrh	r3, [r4, #24]
20000828:	d150      	bne.n	200008cc <process_event+0xe8>
			res = mgr->last_res;
2000082a:	6967      	ldr	r7, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
2000082c:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
2000082e:	2f00      	cmp	r7, #0
20000830:	da15      	bge.n	2000085e <process_event+0x7a>
		*clients = mgr->clients;
20000832:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
20000834:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
20000838:	e9c4 8800 	strd	r8, r8, [r4]
2000083c:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
20000840:	8321      	strh	r1, [r4, #24]
		onoff_transition_fn transit = NULL;
20000842:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
20000844:	8b21      	ldrh	r1, [r4, #24]
20000846:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
2000084a:	45ca      	cmp	sl, r9
2000084c:	d002      	beq.n	20000854 <process_event+0x70>
		if (do_monitors
2000084e:	68a3      	ldr	r3, [r4, #8]
20000850:	2b00      	cmp	r3, #0
20000852:	d15c      	bne.n	2000090e <process_event+0x12a>
		    || !sys_slist_is_empty(&clients)
20000854:	b90d      	cbnz	r5, 2000085a <process_event+0x76>
		    || (transit != NULL)) {
20000856:	2e00      	cmp	r6, #0
20000858:	d074      	beq.n	20000944 <process_event+0x160>
2000085a:	2300      	movs	r3, #0
2000085c:	e058      	b.n	20000910 <process_event+0x12c>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
2000085e:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
20000862:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
20000864:	2a01      	cmp	r2, #1
20000866:	d820      	bhi.n	200008aa <process_event+0xc6>
		*clients = mgr->clients;
20000868:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
2000086c:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
2000086e:	6825      	ldr	r5, [r4, #0]
	list->head = NULL;
20000870:	b289      	uxth	r1, r1
	list->tail = NULL;
20000872:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
20000876:	d10c      	bne.n	20000892 <process_event+0xae>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
20000878:	2d00      	cmp	r5, #0
2000087a:	462b      	mov	r3, r5
2000087c:	bf38      	it	cc
2000087e:	2300      	movcc	r3, #0
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
20000880:	b12b      	cbz	r3, 2000088e <process_event+0xaa>
				mgr->refs += 1U;
20000882:	8b62      	ldrh	r2, [r4, #26]
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next_no_check(sys_snode_t *node);

Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
20000884:	681b      	ldr	r3, [r3, #0]
20000886:	3201      	adds	r2, #1
20000888:	8362      	strh	r2, [r4, #26]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
2000088a:	2b00      	cmp	r3, #0
2000088c:	d1f8      	bne.n	20000880 <process_event+0x9c>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
2000088e:	f041 0102 	orr.w	r1, r1, #2
		if (process_recheck(mgr) != EVT_NOP) {
20000892:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
20000894:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
20000896:	f002 fe48 	bl	2000352a <process_recheck>
2000089a:	4606      	mov	r6, r0
2000089c:	2800      	cmp	r0, #0
2000089e:	d0d1      	beq.n	20000844 <process_event+0x60>
			mgr->flags |= ONOFF_FLAG_RECHECK;
200008a0:	8b23      	ldrh	r3, [r4, #24]
200008a2:	f043 0320 	orr.w	r3, r3, #32
200008a6:	8323      	strh	r3, [r4, #24]
200008a8:	e7cb      	b.n	20000842 <process_event+0x5e>
	} else if (state == ONOFF_STATE_TO_OFF) {
200008aa:	2b04      	cmp	r3, #4
200008ac:	d10c      	bne.n	200008c8 <process_event+0xe4>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
200008ae:	f021 0107 	bic.w	r1, r1, #7
200008b2:	b289      	uxth	r1, r1
		if (process_recheck(mgr) != EVT_NOP) {
200008b4:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
200008b6:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
200008b8:	f002 fe37 	bl	2000352a <process_recheck>
200008bc:	4605      	mov	r5, r0
200008be:	2800      	cmp	r0, #0
200008c0:	d0bf      	beq.n	20000842 <process_event+0x5e>
			mgr->flags |= ONOFF_FLAG_RECHECK;
200008c2:	f041 0120 	orr.w	r1, r1, #32
200008c6:	8321      	strh	r1, [r4, #24]
200008c8:	2500      	movs	r5, #0
200008ca:	e7ba      	b.n	20000842 <process_event+0x5e>
		} else if (evt == EVT_START) {
200008cc:	2803      	cmp	r0, #3
200008ce:	d109      	bne.n	200008e4 <process_event+0x100>
			transit = mgr->transitions->start;
200008d0:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
200008d2:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
200008d6:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
200008d8:	f043 0306 	orr.w	r3, r3, #6
}
200008dc:	2500      	movs	r5, #0
	mgr->flags = (state & ONOFF_STATE_MASK)
200008de:	8323      	strh	r3, [r4, #24]
		res = 0;
200008e0:	462f      	mov	r7, r5
200008e2:	e7af      	b.n	20000844 <process_event+0x60>
		} else if (evt == EVT_STOP) {
200008e4:	2804      	cmp	r0, #4
200008e6:	d106      	bne.n	200008f6 <process_event+0x112>
			transit = mgr->transitions->stop;
200008e8:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
200008ea:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
200008ee:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
200008f0:	f043 0304 	orr.w	r3, r3, #4
200008f4:	e7f2      	b.n	200008dc <process_event+0xf8>
		} else if (evt == EVT_RESET) {
200008f6:	2805      	cmp	r0, #5
200008f8:	d106      	bne.n	20000908 <process_event+0x124>
			transit = mgr->transitions->reset;
200008fa:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
200008fc:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
20000900:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
20000902:	f043 0305 	orr.w	r3, r3, #5
20000906:	e7e9      	b.n	200008dc <process_event+0xf8>
20000908:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
2000090a:	462e      	mov	r6, r5
2000090c:	e7e8      	b.n	200008e0 <process_event+0xfc>
				   && !sys_slist_is_empty(&mgr->monitors);
2000090e:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
20000910:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
20000914:	8321      	strh	r1, [r4, #24]
20000916:	f38b 8811 	msr	BASEPRI, fp
2000091a:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
2000091e:	bb03      	cbnz	r3, 20000962 <process_event+0x17e>
	while (!sys_slist_is_empty(list)) {
20000920:	2d00      	cmp	r5, #0
20000922:	d133      	bne.n	2000098c <process_event+0x1a8>
			if (transit != NULL) {
20000924:	b116      	cbz	r6, 2000092c <process_event+0x148>
				transit(mgr, transition_complete);
20000926:	4620      	mov	r0, r4
20000928:	4920      	ldr	r1, [pc, #128]	; (200009ac <process_event+0x1c8>)
2000092a:	47b0      	blx	r6
	__asm__ volatile(
2000092c:	f04f 0320 	mov.w	r3, #32
20000930:	f3ef 8b11 	mrs	fp, BASEPRI
20000934:	f383 8811 	msr	BASEPRI, r3
20000938:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
2000093c:	8b23      	ldrh	r3, [r4, #24]
2000093e:	f023 0308 	bic.w	r3, r3, #8
20000942:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
20000944:	8b23      	ldrh	r3, [r4, #24]
20000946:	06da      	lsls	r2, r3, #27
20000948:	d528      	bpl.n	2000099c <process_event+0x1b8>
			evt = EVT_COMPLETE;
2000094a:	2101      	movs	r1, #1
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
2000094c:	f023 0310 	bic.w	r3, r3, #16
20000950:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
20000952:	f8b4 9018 	ldrh.w	r9, [r4, #24]
20000956:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
2000095a:	2900      	cmp	r1, #0
2000095c:	f47f af5b 	bne.w	20000816 <process_event+0x32>
out:
20000960:	e751      	b.n	20000806 <process_event+0x22>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
20000962:	68a1      	ldr	r1, [r4, #8]
20000964:	2900      	cmp	r1, #0
20000966:	d0db      	beq.n	20000920 <process_event+0x13c>
	return node->next;
20000968:	680b      	ldr	r3, [r1, #0]
2000096a:	2b00      	cmp	r3, #0
2000096c:	bf38      	it	cc
2000096e:	2300      	movcc	r3, #0
20000970:	4699      	mov	r9, r3
		mon->callback(mgr, mon, state, res);
20000972:	4652      	mov	r2, sl
20000974:	463b      	mov	r3, r7
20000976:	4620      	mov	r0, r4
20000978:	f8d1 b004 	ldr.w	fp, [r1, #4]
2000097c:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
2000097e:	f1b9 0f00 	cmp.w	r9, #0
20000982:	d0cd      	beq.n	20000920 <process_event+0x13c>
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
20000984:	4649      	mov	r1, r9
20000986:	f8d9 3000 	ldr.w	r3, [r9]
2000098a:	e7ee      	b.n	2000096a <process_event+0x186>
 *
 * @return A pointer to the first node of the list
 */
static inline sys_snode_t *sys_slist_get_not_empty(sys_slist_t *list);

Z_GENLIST_GET_NOT_EMPTY(slist, snode)
2000098c:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
2000098e:	463b      	mov	r3, r7
20000990:	4652      	mov	r2, sl
20000992:	4620      	mov	r0, r4
20000994:	682d      	ldr	r5, [r5, #0]
20000996:	f002 fde4 	bl	20003562 <notify_one>
2000099a:	e7c1      	b.n	20000920 <process_event+0x13c>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
2000099c:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
200009a0:	bf1e      	ittt	ne
200009a2:	f023 0320 	bicne.w	r3, r3, #32
			evt = EVT_RECHECK;
200009a6:	2102      	movne	r1, #2
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
200009a8:	8323      	strhne	r3, [r4, #24]
			evt = EVT_RECHECK;
200009aa:	e7d2      	b.n	20000952 <process_event+0x16e>
200009ac:	2000358f 	.word	0x2000358f

200009b0 <nordicsemi_nrf53_init>:
200009b0:	f04f 0320 	mov.w	r3, #32
200009b4:	f3ef 8111 	mrs	r1, BASEPRI
200009b8:	f383 8811 	msr	BASEPRI, r3
200009bc:	f3bf 8f6f 	isb	sy
	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_CACHE
#ifdef CONFIG_SOC_NRF5340_CPUAPP
	/* Enable the instruction & data cache */
	NRF_CACHE->ENABLE = CACHE_ENABLE_ENABLE_Msk;
200009c0:	2301      	movs	r3, #1
200009c2:	4a09      	ldr	r2, [pc, #36]	; (200009e8 <nordicsemi_nrf53_init+0x38>)
200009c4:	f8c2 3500 	str.w	r3, [r2, #1280]	; 0x500
#endif /* CONFIG_SOC_NRF5340_CPUNET */
#endif

#if defined(CONFIG_SOC_NRF5340_CPUAPP) && \
	!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
	*((uint32_t *)0x500046D0) = 0x1;
200009c8:	f502 525b 	add.w	r2, r2, #14016	; 0x36c0
200009cc:	3210      	adds	r2, #16
#endif

#if defined(CONFIG_SOC_DCDC_NRF53X_APP)
	NRF_REGULATORS->VREGMAIN.DCDCEN = 1;
200009ce:	6353      	str	r3, [r2, #52]	; 0x34
	*((uint32_t *)0x500046D0) = 0x1;
200009d0:	6013      	str	r3, [r2, #0]
#endif
#if defined(CONFIG_SOC_DCDC_NRF53X_NET)
	NRF_REGULATORS->VREGRADIO.DCDCEN = 1;
200009d2:	f8c2 3234 	str.w	r3, [r2, #564]	; 0x234
#endif
#if defined(CONFIG_SOC_DCDC_NRF53X_HV)
	NRF_REGULATORS->VREGH.DCDCEN = 1;
200009d6:	f8c2 3430 	str.w	r3, [r2, #1072]	; 0x430
	__asm__ volatile(
200009da:	f381 8811 	msr	BASEPRI, r1
200009de:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
200009e2:	2000      	movs	r0, #0
200009e4:	4770      	bx	lr
200009e6:	bf00      	nop
200009e8:	50001000 	.word	0x50001000

200009ec <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
200009ec:	b148      	cbz	r0, 20000a02 <arch_busy_wait+0x16>

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
200009ee:	4b05      	ldr	r3, [pc, #20]	; (20000a04 <arch_busy_wait+0x18>)
200009f0:	681a      	ldr	r2, [r3, #0]
200009f2:	4b05      	ldr	r3, [pc, #20]	; (20000a08 <arch_busy_wait+0x1c>)
200009f4:	fbb2 f2f3 	udiv	r2, r2, r3
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
200009f8:	4b04      	ldr	r3, [pc, #16]	; (20000a0c <arch_busy_wait+0x20>)
    delay_cycles(cycles);
200009fa:	4350      	muls	r0, r2
200009fc:	f043 0301 	orr.w	r3, r3, #1
20000a00:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
20000a02:	4770      	bx	lr
20000a04:	2002003c 	.word	0x2002003c
20000a08:	000f4240 	.word	0x000f4240
20000a0c:	20004240 	.word	0x20004240

20000a10 <sys_reboot>:

extern void sys_arch_reboot(int type);
extern void sys_clock_disable(void);

void sys_reboot(int type)
{
20000a10:	4604      	mov	r4, r0
20000a12:	b508      	push	{r3, lr}
	__asm__ volatile(
20000a14:	f04f 0220 	mov.w	r2, #32
20000a18:	f3ef 8311 	mrs	r3, BASEPRI
20000a1c:	f382 8811 	msr	BASEPRI, r2
20000a20:	f3bf 8f6f 	isb	sy
	(void)irq_lock();
#ifdef CONFIG_SYS_CLOCK_EXISTS
	sys_clock_disable();
20000a24:	f002 ffb4 	bl	20003990 <sys_clock_disable>
#endif

	sys_arch_reboot(type);
20000a28:	4620      	mov	r0, r4
20000a2a:	f000 fd75 	bl	20001518 <sys_arch_reboot>

	/* should never get here */
	printk("Failed to reboot: spinning endlessly...\n");
20000a2e:	4803      	ldr	r0, [pc, #12]	; (20000a3c <sys_reboot+0x2c>)
20000a30:	f002 fd6e 	bl	20003510 <printk>
 *
 * @return N/A
 */
static inline void k_cpu_idle(void)
{
	arch_cpu_idle();
20000a34:	f000 fc12 	bl	2000125c <arch_cpu_idle>
20000a38:	e7fc      	b.n	20000a34 <sys_reboot+0x24>
20000a3a:	bf00      	nop
20000a3c:	200043e8 	.word	0x200043e8

20000a40 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
20000a40:	b510      	push	{r4, lr}
20000a42:	4807      	ldr	r0, [pc, #28]	; (20000a60 <uart_console_init+0x20>)
20000a44:	f001 fc26 	bl	20002294 <z_impl_device_get_binding>
	__stdout_hook_install(console_out);
20000a48:	4c06      	ldr	r4, [pc, #24]	; (20000a64 <uart_console_init+0x24>)

	ARG_UNUSED(arg);

	/* Claim console device */
	uart_console_dev = device_get_binding(CONFIG_UART_CONSOLE_ON_DEV_NAME);
20000a4a:	4b07      	ldr	r3, [pc, #28]	; (20000a68 <uart_console_init+0x28>)
20000a4c:	6018      	str	r0, [r3, #0]
	__stdout_hook_install(console_out);
20000a4e:	4620      	mov	r0, r4
20000a50:	f000 ff24 	bl	2000189c <__stdout_hook_install>
	__printk_hook_install(console_out);
20000a54:	4620      	mov	r0, r4
20000a56:	f7ff fd83 	bl	20000560 <__printk_hook_install>

	uart_console_hook_install();

	return 0;
}
20000a5a:	2000      	movs	r0, #0
20000a5c:	bd10      	pop	{r4, pc}
20000a5e:	bf00      	nop
20000a60:	20004411 	.word	0x20004411
20000a64:	20000a6d 	.word	0x20000a6d
20000a68:	20020268 	.word	0x20020268

20000a6c <console_out>:
	if ('\n' == c) {
20000a6c:	280a      	cmp	r0, #10
{
20000a6e:	b538      	push	{r3, r4, r5, lr}
20000a70:	4604      	mov	r4, r0
20000a72:	4d07      	ldr	r5, [pc, #28]	; (20000a90 <console_out+0x24>)
	if ('\n' == c) {
20000a74:	d104      	bne.n	20000a80 <console_out+0x14>
20000a76:	6828      	ldr	r0, [r5, #0]
						unsigned char out_char)
{
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
20000a78:	6883      	ldr	r3, [r0, #8]
20000a7a:	210d      	movs	r1, #13
20000a7c:	685b      	ldr	r3, [r3, #4]
20000a7e:	4798      	blx	r3
	uart_poll_out(uart_console_dev, c);
20000a80:	6828      	ldr	r0, [r5, #0]
20000a82:	6883      	ldr	r3, [r0, #8]
20000a84:	b2e1      	uxtb	r1, r4
20000a86:	685b      	ldr	r3, [r3, #4]
20000a88:	4798      	blx	r3
}
20000a8a:	4620      	mov	r0, r4
20000a8c:	bd38      	pop	{r3, r4, r5, pc}
20000a8e:	bf00      	nop
20000a90:	20020268 	.word	0x20020268

20000a94 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = DEVICE_GET(clock_nrf)->data;
	size_t offset = (size_t)(mgr - data->mgr);
20000a94:	4a0e      	ldr	r2, [pc, #56]	; (20000ad0 <onoff_stop+0x3c>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
20000a96:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
20000a98:	1a84      	subs	r4, r0, r2
{
20000a9a:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
20000a9c:	200c      	movs	r0, #12
	size_t offset = (size_t)(mgr - data->mgr);
20000a9e:	10a3      	asrs	r3, r4, #2
20000aa0:	4c0c      	ldr	r4, [pc, #48]	; (20000ad4 <onoff_stop+0x40>)
{
20000aa2:	460e      	mov	r6, r1
	size_t offset = (size_t)(mgr - data->mgr);
20000aa4:	435c      	muls	r4, r3
20000aa6:	b2e4      	uxtb	r4, r4
	err = set_off_state(&subdata->flags, ctx);
20000aa8:	fb00 2004 	mla	r0, r0, r4, r2
20000aac:	2140      	movs	r1, #64	; 0x40
20000aae:	305c      	adds	r0, #92	; 0x5c
20000ab0:	f002 fed8 	bl	20003864 <set_off_state>
	if (err < 0) {
20000ab4:	1e01      	subs	r1, r0, #0
20000ab6:	db05      	blt.n	20000ac4 <onoff_stop+0x30>
	get_sub_config(dev, type)->stop();
20000ab8:	4b07      	ldr	r3, [pc, #28]	; (20000ad8 <onoff_stop+0x44>)
20000aba:	eb03 04c4 	add.w	r4, r3, r4, lsl #3
20000abe:	6863      	ldr	r3, [r4, #4]
20000ac0:	4798      	blx	r3
	return 0;
20000ac2:	2100      	movs	r1, #0
	int res;

	res = stop(DEVICE_GET(clock_nrf), get_subsys(mgr), CTX_ONOFF);
	notify(mgr, res);
20000ac4:	4628      	mov	r0, r5
20000ac6:	4633      	mov	r3, r6
}
20000ac8:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
20000acc:	4718      	bx	r3
20000ace:	bf00      	nop
20000ad0:	2002027c 	.word	0x2002027c
20000ad4:	b6db6db7 	.word	0xb6db6db7
20000ad8:	2000425c 	.word	0x2000425c

20000adc <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
20000adc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	err = set_starting_state(&subdata->flags, ctx);
20000ae0:	250c      	movs	r5, #12
	size_t offset = (size_t)(mgr - data->mgr);
20000ae2:	4e10      	ldr	r6, [pc, #64]	; (20000b24 <onoff_start+0x48>)
{
20000ae4:	4680      	mov	r8, r0
	size_t offset = (size_t)(mgr - data->mgr);
20000ae6:	1b84      	subs	r4, r0, r6
20000ae8:	10a3      	asrs	r3, r4, #2
20000aea:	4c0f      	ldr	r4, [pc, #60]	; (20000b28 <onoff_start+0x4c>)
{
20000aec:	460f      	mov	r7, r1
	size_t offset = (size_t)(mgr - data->mgr);
20000aee:	435c      	muls	r4, r3
20000af0:	b2e4      	uxtb	r4, r4
	err = set_starting_state(&subdata->flags, ctx);
20000af2:	4365      	muls	r5, r4
20000af4:	f105 005c 	add.w	r0, r5, #92	; 0x5c
20000af8:	2140      	movs	r1, #64	; 0x40
20000afa:	4430      	add	r0, r6
20000afc:	f002 fecb 	bl	20003896 <set_starting_state>
	if (err < 0) {
20000b00:	1e01      	subs	r1, r0, #0
20000b02:	db09      	blt.n	20000b18 <onoff_start+0x3c>
	subdata->cb = data->cb;
20000b04:	4a09      	ldr	r2, [pc, #36]	; (20000b2c <onoff_start+0x50>)
20000b06:	1973      	adds	r3, r6, r5
	subdata->user_data = data->user_data;
20000b08:	e9c3 2715 	strd	r2, r7, [r3, #84]	; 0x54
	 get_sub_config(dev, type)->start();
20000b0c:	4b08      	ldr	r3, [pc, #32]	; (20000b30 <onoff_start+0x54>)
20000b0e:	f853 3034 	ldr.w	r3, [r3, r4, lsl #3]
	err = async_start(DEVICE_GET(clock_nrf), get_subsys(mgr),
			  &data, CTX_ONOFF);
	if (err < 0) {
		notify(mgr, err);
	}
}
20000b12:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
	 get_sub_config(dev, type)->start();
20000b16:	4718      	bx	r3
		notify(mgr, err);
20000b18:	4640      	mov	r0, r8
20000b1a:	463b      	mov	r3, r7
}
20000b1c:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		notify(mgr, err);
20000b20:	4718      	bx	r3
20000b22:	bf00      	nop
20000b24:	2002027c 	.word	0x2002027c
20000b28:	b6db6db7 	.word	0xb6db6db7
20000b2c:	200038f9 	.word	0x200038f9
20000b30:	2000425c 	.word	0x2000425c

20000b34 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
20000b34:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
20000b36:	230c      	movs	r3, #12
	sub_data->cb = NULL;
20000b38:	2200      	movs	r2, #0
	clock_control_cb_t callback = sub_data->cb;
20000b3a:	434b      	muls	r3, r1
20000b3c:	4808      	ldr	r0, [pc, #32]	; (20000b60 <clkstarted_handle.constprop.0+0x2c>)
static void clkstarted_handle(const struct device *dev,
20000b3e:	b570      	push	{r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
20000b40:	18c4      	adds	r4, r0, r3
	set_on_state(&sub_data->flags);
20000b42:	335c      	adds	r3, #92	; 0x5c
	void *user_data = sub_data->user_data;
20000b44:	e9d4 5615 	ldrd	r5, r6, [r4, #84]	; 0x54
	set_on_state(&sub_data->flags);
20000b48:	4418      	add	r0, r3
	sub_data->cb = NULL;
20000b4a:	6562      	str	r2, [r4, #84]	; 0x54
	set_on_state(&sub_data->flags);
20000b4c:	f002 fec1 	bl	200038d2 <set_on_state>
	if (callback) {
20000b50:	b12d      	cbz	r5, 20000b5e <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
20000b52:	4632      	mov	r2, r6
20000b54:	462b      	mov	r3, r5
}
20000b56:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
20000b5a:	4802      	ldr	r0, [pc, #8]	; (20000b64 <clkstarted_handle.constprop.0+0x30>)
20000b5c:	4718      	bx	r3
}
20000b5e:	bd70      	pop	{r4, r5, r6, pc}
20000b60:	2002027c 	.word	0x2002027c
20000b64:	200200a8 	.word	0x200200a8

20000b68 <clock_event_handler>:

static void clock_event_handler(nrfx_clock_evt_type_t event)
{
	const struct device *dev = DEVICE_GET(clock_nrf);

	switch (event) {
20000b68:	b110      	cbz	r0, 20000b70 <clock_event_handler+0x8>
20000b6a:	2801      	cmp	r0, #1
20000b6c:	d004      	beq.n	20000b78 <clock_event_handler+0x10>
20000b6e:	4770      	bx	lr
				get_sub_data(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK);

		/* Check needed due to anomaly 201:
		 * HFCLKSTARTED may be generated twice.
		 */
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
20000b70:	4b03      	ldr	r3, [pc, #12]	; (20000b80 <clock_event_handler+0x18>)
20000b72:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
20000b74:	075b      	lsls	r3, r3, #29
20000b76:	d101      	bne.n	20000b7c <clock_event_handler+0x14>
	case NRFX_CLOCK_EVT_LFCLK_STARTED:
		if (IS_ENABLED(
			CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION)) {
			z_nrf_clock_calibration_lfclk_started();
		}
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
20000b78:	f7ff bfdc 	b.w	20000b34 <clkstarted_handle.constprop.0>
		break;
	default:
		__ASSERT_NO_MSG(0);
		break;
	}
}
20000b7c:	4770      	bx	lr
20000b7e:	bf00      	nop
20000b80:	2002027c 	.word	0x2002027c

20000b84 <nrf_gpio_pin_mcu_select.constprop.0>:
        /* FALLTHROUGH */
        case 0: return NRF_P0;
#endif
#if defined(P1_FEATURE_PINS_PRESENT)
        /* FALLTHROUGH */
        case 1: return NRF_P1;
20000b84:	4b09      	ldr	r3, [pc, #36]	; (20000bac <nrf_gpio_pin_mcu_select.constprop.0+0x28>)
20000b86:	490a      	ldr	r1, [pc, #40]	; (20000bb0 <nrf_gpio_pin_mcu_select.constprop.0+0x2c>)
}

NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;
20000b88:	f000 021f 	and.w	r2, r0, #31

    return pin_number >> 5;
20000b8c:	0940      	lsrs	r0, r0, #5
        case 1: return NRF_P1;
20000b8e:	2801      	cmp	r0, #1
20000b90:	bf08      	it	eq
20000b92:	460b      	moveq	r3, r1
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_MCUSEL_Msk;
20000b94:	eb03 0382 	add.w	r3, r3, r2, lsl #2
20000b98:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
20000b9c:	f022 42e0 	bic.w	r2, r2, #1879048192	; 0x70000000
    reg->PIN_CNF[pin_number] = cnf | (mcu << GPIO_PIN_CNF_MCUSEL_Pos);
20000ba0:	f042 5240 	orr.w	r2, r2, #805306368	; 0x30000000
20000ba4:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
}
20000ba8:	4770      	bx	lr
20000baa:	bf00      	nop
20000bac:	50842500 	.word	0x50842500
20000bb0:	50842800 	.word	0x50842800

20000bb4 <clk_init>:

static int clk_init(const struct device *dev)
{
20000bb4:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
20000bb8:	2200      	movs	r2, #0
20000bba:	2101      	movs	r1, #1
{
20000bbc:	4606      	mov	r6, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
20000bbe:	2005      	movs	r0, #5
20000bc0:	f000 fafa 	bl	200011b8 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);
	irq_enable(DT_INST_IRQN(0));
20000bc4:	2005      	movs	r0, #5
20000bc6:	f000 fad9 	bl	2000117c <arch_irq_enable>
	bool ext_clk = IS_ENABLED(CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL) ||
		    IS_ENABLED(CONFIG_CLOCK_CONTROL_NRF_K32SRC_EXT_LOW_SWING) ||
		    IS_ENABLED(CONFIG_CLOCK_CONTROL_NRF_K32SRC_EXT_FULL_SWING);

	if (ext_clk) {
		nrf_gpio_pin_mcu_select(PIN_XL1,
20000bca:	2000      	movs	r0, #0
20000bcc:	f7ff ffda 	bl	20000b84 <nrf_gpio_pin_mcu_select.constprop.0>
					NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
		nrf_gpio_pin_mcu_select(PIN_XL2,
20000bd0:	2001      	movs	r0, #1
20000bd2:	f7ff ffd7 	bl	20000b84 <nrf_gpio_pin_mcu_select.constprop.0>
					NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
	}
#endif
	nrfx_err = nrfx_clock_init(clock_event_handler);
20000bd6:	4811      	ldr	r0, [pc, #68]	; (20000c1c <clk_init+0x68>)
20000bd8:	f001 f9f4 	bl	20001fc4 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
20000bdc:	4b10      	ldr	r3, [pc, #64]	; (20000c20 <clk_init+0x6c>)
20000bde:	4298      	cmp	r0, r3
20000be0:	d119      	bne.n	20000c16 <clk_init+0x62>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
20000be2:	f003 f898 	bl	20003d16 <nrfx_clock_enable>
20000be6:	2400      	movs	r4, #0
	return &data->mgr[type];
20000be8:	f04f 081c 	mov.w	r8, #28
					 &transitions);
		if (err < 0) {
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
20000bec:	270c      	movs	r7, #12
		err = onoff_manager_init(get_onoff_manager(dev, i),
20000bee:	f8df 9034 	ldr.w	r9, [pc, #52]	; 20000c24 <clk_init+0x70>
						get_sub_data(dev, i);
20000bf2:	68f5      	ldr	r5, [r6, #12]
		err = onoff_manager_init(get_onoff_manager(dev, i),
20000bf4:	4649      	mov	r1, r9
20000bf6:	fb08 5004 	mla	r0, r8, r4, r5
20000bfa:	f002 fce5 	bl	200035c8 <onoff_manager_init>
		if (err < 0) {
20000bfe:	2800      	cmp	r0, #0
20000c00:	db07      	blt.n	20000c12 <clk_init+0x5e>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
20000c02:	2301      	movs	r3, #1
20000c04:	fb07 5504 	mla	r5, r7, r4, r5
20000c08:	441c      	add	r4, r3
	for (enum clock_control_nrf_type i = 0;
20000c0a:	2c03      	cmp	r4, #3
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
20000c0c:	65eb      	str	r3, [r5, #92]	; 0x5c
	for (enum clock_control_nrf_type i = 0;
20000c0e:	d1f0      	bne.n	20000bf2 <clk_init+0x3e>
	}

	return 0;
20000c10:	2000      	movs	r0, #0
}
20000c12:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		return -EIO;
20000c16:	f06f 0004 	mvn.w	r0, #4
20000c1a:	e7fa      	b.n	20000c12 <clk_init+0x5e>
20000c1c:	20000b69 	.word	0x20000b69
20000c20:	0bad0000 	.word	0x0bad0000
20000c24:	20004274 	.word	0x20004274

20000c28 <generic_hfclk_start>:
{
20000c28:	b508      	push	{r3, lr}
20000c2a:	f04f 0320 	mov.w	r3, #32
20000c2e:	f3ef 8111 	mrs	r1, BASEPRI
20000c32:	f383 8811 	msr	BASEPRI, r3
20000c36:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
20000c3a:	4a12      	ldr	r2, [pc, #72]	; (20000c84 <generic_hfclk_start+0x5c>)
20000c3c:	6813      	ldr	r3, [r2, #0]
20000c3e:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
20000c42:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
20000c46:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
20000c48:	d00c      	beq.n	20000c64 <generic_hfclk_start+0x3c>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
20000c4a:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
20000c4e:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
20000c52:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
20000c56:	f013 0301 	ands.w	r3, r3, #1
20000c5a:	d003      	beq.n	20000c64 <generic_hfclk_start+0x3c>
			set_on_state(get_hf_flags());
20000c5c:	480a      	ldr	r0, [pc, #40]	; (20000c88 <generic_hfclk_start+0x60>)
20000c5e:	f002 fe38 	bl	200038d2 <set_on_state>
			already_started = true;
20000c62:	2301      	movs	r3, #1
	__asm__ volatile(
20000c64:	f381 8811 	msr	BASEPRI, r1
20000c68:	f3bf 8f6f 	isb	sy
	if (already_started) {
20000c6c:	b123      	cbz	r3, 20000c78 <generic_hfclk_start+0x50>
}
20000c6e:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(DEVICE_GET(clock_nrf),
20000c72:	2000      	movs	r0, #0
20000c74:	f7ff bf5e 	b.w	20000b34 <clkstarted_handle.constprop.0>
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
20000c78:	2001      	movs	r0, #1
}
20000c7a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
20000c7e:	f001 b9b1 	b.w	20001fe4 <nrfx_clock_start>
20000c82:	bf00      	nop
20000c84:	200202f4 	.word	0x200202f4
20000c88:	200202d8 	.word	0x200202d8

20000c8c <generic_hfclk_stop>:
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
20000c8c:	4b07      	ldr	r3, [pc, #28]	; (20000cac <generic_hfclk_stop+0x20>)
20000c8e:	e8d3 2fef 	ldaex	r2, [r3]
20000c92:	f022 0102 	bic.w	r1, r2, #2
20000c96:	e8c3 1fe0 	stlex	r0, r1, [r3]
20000c9a:	2800      	cmp	r0, #0
20000c9c:	d1f7      	bne.n	20000c8e <generic_hfclk_stop+0x2>
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
20000c9e:	07d3      	lsls	r3, r2, #31
20000ca0:	d402      	bmi.n	20000ca8 <generic_hfclk_stop+0x1c>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
20000ca2:	2001      	movs	r0, #1
20000ca4:	f001 b9f2 	b.w	2000208c <nrfx_clock_stop>
}
20000ca8:	4770      	bx	lr
20000caa:	bf00      	nop
20000cac:	200202f4 	.word	0x200202f4

20000cb0 <api_blocking_start>:
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
20000cb0:	2300      	movs	r3, #0
20000cb2:	2201      	movs	r2, #1
{
20000cb4:	b510      	push	{r4, lr}
20000cb6:	b088      	sub	sp, #32
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
20000cb8:	e9cd 3206 	strd	r3, r2, [sp, #24]
	struct clock_control_async_data data = {
20000cbc:	9301      	str	r3, [sp, #4]
20000cbe:	4b09      	ldr	r3, [pc, #36]	; (20000ce4 <api_blocking_start+0x34>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
20000cc0:	ac04      	add	r4, sp, #16
	err = api_start(dev, subsys, &data);
20000cc2:	aa01      	add	r2, sp, #4
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
20000cc4:	e9cd 4404 	strd	r4, r4, [sp, #16]
	struct clock_control_async_data data = {
20000cc8:	e9cd 3402 	strd	r3, r4, [sp, #8]
	err = api_start(dev, subsys, &data);
20000ccc:	f002 fe40 	bl	20003950 <api_start>
	if (err < 0) {
20000cd0:	2800      	cmp	r0, #0
20000cd2:	db05      	blt.n	20000ce0 <api_blocking_start+0x30>
		parm0.val = timeout;
		return (int) arch_syscall_invoke3(*(uintptr_t *)&sem, parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
20000cd4:	f44f 4280 	mov.w	r2, #16384	; 0x4000
20000cd8:	2300      	movs	r3, #0
20000cda:	4620      	mov	r0, r4
20000cdc:	f002 f8a2 	bl	20002e24 <z_impl_k_sem_take>
}
20000ce0:	b008      	add	sp, #32
20000ce2:	bd10      	pop	{r4, pc}
20000ce4:	2000390b 	.word	0x2000390b

20000ce8 <z_nrf_clock_control_lf_on>:
{
20000ce8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
20000cec:	2201      	movs	r2, #1
20000cee:	4606      	mov	r6, r0
20000cf0:	4939      	ldr	r1, [pc, #228]	; (20000dd8 <z_nrf_clock_control_lf_on+0xf0>)
20000cf2:	e8d1 3fef 	ldaex	r3, [r1]
20000cf6:	e8c1 2fe0 	stlex	r0, r2, [r1]
20000cfa:	2800      	cmp	r0, #0
20000cfc:	d1f9      	bne.n	20000cf2 <z_nrf_clock_control_lf_on+0xa>
	if (atomic_set(&on, 1) == 0) {
20000cfe:	b933      	cbnz	r3, 20000d0e <z_nrf_clock_control_lf_on+0x26>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
20000d00:	4936      	ldr	r1, [pc, #216]	; (20000ddc <z_nrf_clock_control_lf_on+0xf4>)
		err = onoff_request(mgr, &cli);
20000d02:	4837      	ldr	r0, [pc, #220]	; (20000de0 <z_nrf_clock_control_lf_on+0xf8>)
20000d04:	604b      	str	r3, [r1, #4]
20000d06:	60cb      	str	r3, [r1, #12]
20000d08:	608a      	str	r2, [r1, #8]
20000d0a:	f002 fc70 	bl	200035ee <onoff_request>
	switch (start_mode) {
20000d0e:	1e73      	subs	r3, r6, #1
20000d10:	2b01      	cmp	r3, #1
20000d12:	d832      	bhi.n	20000d7a <z_nrf_clock_control_lf_on+0x92>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
20000d14:	2e01      	cmp	r6, #1
20000d16:	d107      	bne.n	20000d28 <z_nrf_clock_control_lf_on+0x40>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
20000d18:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20000d1c:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
20000d20:	f003 0303 	and.w	r3, r3, #3
20000d24:	2b02      	cmp	r3, #2
20000d26:	d028      	beq.n	20000d7a <z_nrf_clock_control_lf_on+0x92>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
20000d28:	f003 f8f0 	bl	20003f0c <k_is_in_isr>
20000d2c:	4604      	mov	r4, r0
20000d2e:	b918      	cbnz	r0, 20000d38 <z_nrf_clock_control_lf_on+0x50>
	return !z_sys_post_kernel;
20000d30:	4b2c      	ldr	r3, [pc, #176]	; (20000de4 <z_nrf_clock_control_lf_on+0xfc>)
	int key = isr_mode ? irq_lock() : 0;
20000d32:	781b      	ldrb	r3, [r3, #0]
20000d34:	2b00      	cmp	r3, #0
20000d36:	d147      	bne.n	20000dc8 <z_nrf_clock_control_lf_on+0xe0>
	__asm__ volatile(
20000d38:	f04f 0320 	mov.w	r3, #32
20000d3c:	f3ef 8511 	mrs	r5, BASEPRI
20000d40:	f383 8811 	msr	BASEPRI, r3
20000d44:	f3bf 8f6f 	isb	sy
20000d48:	2401      	movs	r4, #1
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
20000d4a:	4f27      	ldr	r7, [pc, #156]	; (20000de8 <z_nrf_clock_control_lf_on+0x100>)
 */
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
20000d4c:	f8df 809c 	ldr.w	r8, [pc, #156]	; 20000dec <z_nrf_clock_control_lf_on+0x104>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
20000d50:	f8df 909c 	ldr.w	r9, [pc, #156]	; 20000df0 <z_nrf_clock_control_lf_on+0x108>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
20000d54:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
20000d58:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
20000d5c:	f8d2 2418 	ldr.w	r2, [r2, #1048]	; 0x418
20000d60:	03d2      	lsls	r2, r2, #15
20000d62:	d50c      	bpl.n	20000d7e <z_nrf_clock_control_lf_on+0x96>
	while (!(nrfx_clock_is_running(d, (void *)&type)
20000d64:	f003 0303 	and.w	r3, r3, #3
20000d68:	2b02      	cmp	r3, #2
20000d6a:	d001      	beq.n	20000d70 <z_nrf_clock_control_lf_on+0x88>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
20000d6c:	2e01      	cmp	r6, #1
20000d6e:	d106      	bne.n	20000d7e <z_nrf_clock_control_lf_on+0x96>
	if (isr_mode) {
20000d70:	b324      	cbz	r4, 20000dbc <z_nrf_clock_control_lf_on+0xd4>
	__asm__ volatile(
20000d72:	f385 8811 	msr	BASEPRI, r5
20000d76:	f3bf 8f6f 	isb	sy
}
20000d7a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			if (isr_mode) {
20000d7e:	b1c4      	cbz	r4, 20000db2 <z_nrf_clock_control_lf_on+0xca>
 *
 * @return N/A
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
20000d80:	4628      	mov	r0, r5
20000d82:	f000 fa79 	bl	20001278 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
20000d86:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
20000d8a:	f8d2 3518 	ldr.w	r3, [r2, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
20000d8e:	b2db      	uxtb	r3, r3
20000d90:	2b01      	cmp	r3, #1
20000d92:	d1df      	bne.n	20000d54 <z_nrf_clock_control_lf_on+0x6c>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
20000d94:	6839      	ldr	r1, [r7, #0]
		    && nrf_clock_event_check(NRF_CLOCK,
20000d96:	2900      	cmp	r1, #0
20000d98:	d0dc      	beq.n	20000d54 <z_nrf_clock_control_lf_on+0x6c>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
20000d9a:	2100      	movs	r1, #0
20000d9c:	6039      	str	r1, [r7, #0]
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
20000d9e:	6839      	ldr	r1, [r7, #0]
    p_reg->LFCLKSRC = (uint32_t)(source);
20000da0:	2102      	movs	r1, #2
20000da2:	f8c2 1518 	str.w	r1, [r2, #1304]	; 0x518
20000da6:	2220      	movs	r2, #32
20000da8:	f8c8 2180 	str.w	r2, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
20000dac:	f8c9 3000 	str.w	r3, [r9]
}
20000db0:	e7d0      	b.n	20000d54 <z_nrf_clock_control_lf_on+0x6c>
	return z_impl_k_sleep(timeout);
20000db2:	2100      	movs	r1, #0
20000db4:	2021      	movs	r0, #33	; 0x21
20000db6:	f001 ffef 	bl	20002d98 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
20000dba:	e7e4      	b.n	20000d86 <z_nrf_clock_control_lf_on+0x9e>
    p_reg->INTENSET = mask;
20000dbc:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20000dc0:	2202      	movs	r2, #2
20000dc2:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
20000dc6:	e7d8      	b.n	20000d7a <z_nrf_clock_control_lf_on+0x92>
    p_reg->INTENCLR = mask;
20000dc8:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20000dcc:	2202      	movs	r2, #2
	int key = isr_mode ? irq_lock() : 0;
20000dce:	4605      	mov	r5, r0
20000dd0:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
20000dd4:	e7b9      	b.n	20000d4a <z_nrf_clock_control_lf_on+0x62>
20000dd6:	bf00      	nop
20000dd8:	200202f8 	.word	0x200202f8
20000ddc:	2002026c 	.word	0x2002026c
20000de0:	20020298 	.word	0x20020298
20000de4:	200208ce 	.word	0x200208ce
20000de8:	50005104 	.word	0x50005104
20000dec:	e000e100 	.word	0xe000e100
20000df0:	50005008 	.word	0x50005008

20000df4 <handle_next_cycle_case>:
 * counter progresses during that time it means that 1 cycle elapsed and
 * interrupt is set pending.
 */
static void handle_next_cycle_case(uint32_t t)
{
	set_comparator(t + 2);
20000df4:	1c82      	adds	r2, r0, #2

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE  void nrf_rtc_cc_set(NRF_RTC_Type * p_reg, uint32_t ch, uint32_t cc_val)
{
    p_reg->CC[ch] = cc_val;
20000df6:	4b08      	ldr	r3, [pc, #32]	; (20000e18 <handle_next_cycle_case+0x24>)
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
20000df8:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
20000dfc:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type const * p_reg)
{
     return p_reg->COUNTER;
20000e00:	f8d3 2504 	ldr.w	r2, [r3, #1284]	; 0x504
	while (t != counter()) {
20000e04:	4290      	cmp	r0, r2
20000e06:	d100      	bne.n	20000e0a <handle_next_cycle_case+0x16>
		 * generated. Trigger interrupt.
		 */
		t = counter();
		set_comparator(t + 2);
	}
}
20000e08:	4770      	bx	lr
20000e0a:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
		set_comparator(t + 2);
20000e0e:	1c82      	adds	r2, r0, #2
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
20000e10:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
20000e14:	e7f2      	b.n	20000dfc <handle_next_cycle_case+0x8>
20000e16:	bf00      	nop
20000e18:	50015000 	.word	0x50015000

20000e1c <rtc_nrf_isr>:
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
20000e1c:	2200      	movs	r2, #0
20000e1e:	4b07      	ldr	r3, [pc, #28]	; (20000e3c <rtc_nrf_isr+0x20>)
20000e20:	601a      	str	r2, [r3, #0]
20000e22:	681b      	ldr	r3, [r3, #0]
{
	ARG_UNUSED(arg);
	event_clear();

	uint32_t t = get_comparator();
	uint32_t dticks = counter_sub(t, last_count) / CYC_PER_TICK;
20000e24:	4a06      	ldr	r2, [pc, #24]	; (20000e40 <rtc_nrf_isr+0x24>)
    return p_reg->CC[ch];
20000e26:	4b07      	ldr	r3, [pc, #28]	; (20000e44 <rtc_nrf_isr+0x28>)
20000e28:	f8d3 0540 	ldr.w	r0, [r3, #1344]	; 0x540
20000e2c:	6813      	ldr	r3, [r2, #0]
	return (a - b) & COUNTER_MAX;
20000e2e:	1ac0      	subs	r0, r0, r3
20000e30:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000

	last_count += dticks * CYC_PER_TICK;
20000e34:	4403      	add	r3, r0
20000e36:	6013      	str	r3, [r2, #0]
		 * so it won't get preempted by the interrupt.
		 */
		set_absolute_alarm(last_count + CYC_PER_TICK);
	}

	z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : (dticks > 0));
20000e38:	f002 b980 	b.w	2000313c <z_clock_announce>
20000e3c:	50015140 	.word	0x50015140
20000e40:	200202fc 	.word	0x200202fc
20000e44:	50015000 	.word	0x50015000

20000e48 <z_clock_driver_init>:
}

int z_clock_driver_init(const struct device *device)
{
20000e48:	b538      	push	{r3, r4, r5, lr}
}

NRF_STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_reg, uint32_t val)
{
    NRFX_ASSERT(val <= (RTC_PRESCALER_PRESCALER_Msk >> RTC_PRESCALER_PRESCALER_Pos));
    p_reg->PRESCALER = val;
20000e4a:	2400      	movs	r4, #0
20000e4c:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
20000e50:	4d0e      	ldr	r5, [pc, #56]	; (20000e8c <z_clock_driver_init+0x44>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
20000e52:	4b0f      	ldr	r3, [pc, #60]	; (20000e90 <z_clock_driver_init+0x48>)
    p_reg->PRESCALER = val;
20000e54:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
20000e58:	601c      	str	r4, [r3, #0]
20000e5a:	681b      	ldr	r3, [r3, #0]
20000e5c:	4b0d      	ldr	r3, [pc, #52]	; (20000e94 <z_clock_driver_init+0x4c>)
	nrf_rtc_prescaler_set(RTC, 0);
	event_clear();
	NVIC_ClearPendingIRQ(RTC_IRQn);
	int_enable();

	IRQ_CONNECT(RTC_IRQn, 1, rtc_nrf_isr, 0, 0);
20000e5e:	2101      	movs	r1, #1
20000e60:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    p_reg->INTENSET = mask;
20000e64:	f44f 3380 	mov.w	r3, #65536	; 0x10000
20000e68:	4622      	mov	r2, r4
20000e6a:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
20000e6e:	2015      	movs	r0, #21
20000e70:	f000 f9a2 	bl	200011b8 <z_arm_irq_priority_set>
	irq_enable(RTC_IRQn);
20000e74:	2015      	movs	r0, #21
20000e76:	f000 f981 	bl	2000117c <arch_irq_enable>
    return (uint32_t)p_reg + task;
}

NRF_STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_reg, nrf_rtc_task_t task)
{
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
20000e7a:	2301      	movs	r3, #1
20000e7c:	4a06      	ldr	r2, [pc, #24]	; (20000e98 <z_clock_driver_init+0x50>)

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		set_comparator(counter() + CYC_PER_TICK);
	}

	z_nrf_clock_control_lf_on(mode);
20000e7e:	2002      	movs	r0, #2
20000e80:	6013      	str	r3, [r2, #0]
20000e82:	602b      	str	r3, [r5, #0]
20000e84:	f7ff ff30 	bl	20000ce8 <z_nrf_clock_control_lf_on>

	return 0;
}
20000e88:	4620      	mov	r0, r4
20000e8a:	bd38      	pop	{r3, r4, r5, pc}
20000e8c:	50015000 	.word	0x50015000
20000e90:	50015140 	.word	0x50015140
20000e94:	e000e100 	.word	0xe000e100
20000e98:	50015008 	.word	0x50015008

20000e9c <z_clock_set_timeout>:

void z_clock_set_timeout(int32_t ticks, bool idle)
{
20000e9c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
     return p_reg->COUNTER;
20000e9e:	4b2d      	ldr	r3, [pc, #180]	; (20000f54 <z_clock_set_timeout+0xb8>)

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return;
	}

	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
20000ea0:	4c2d      	ldr	r4, [pc, #180]	; (20000f58 <z_clock_set_timeout+0xbc>)
20000ea2:	f8d3 2504 	ldr.w	r2, [r3, #1284]	; 0x504
	ticks = MAX(MIN(ticks - 1, (int32_t)MAX_TICKS), 0);

	uint32_t unannounced = counter_sub(counter(), last_count);
20000ea6:	4b2d      	ldr	r3, [pc, #180]	; (20000f5c <z_clock_set_timeout+0xc0>)
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
20000ea8:	f1b0 3fff 	cmp.w	r0, #4294967295
20000eac:	bf08      	it	eq
20000eae:	4620      	moveq	r0, r4
	uint32_t unannounced = counter_sub(counter(), last_count);
20000eb0:	6819      	ldr	r1, [r3, #0]
	return (a - b) & COUNTER_MAX;
20000eb2:	1a52      	subs	r2, r2, r1
20000eb4:	f022 437f 	bic.w	r3, r2, #4278190080	; 0xff000000
	/* If we haven't announced for more than half the 24-bit wrap
	 * duration, then force an announce to avoid loss of a wrap
	 * event.  This can happen if new timeouts keep being set
	 * before the existing one triggers the interrupt.
	 */
	if (unannounced >= COUNTER_HALF_SPAN) {
20000eb8:	0212      	lsls	r2, r2, #8
20000eba:	d438      	bmi.n	20000f2e <z_clock_set_timeout+0x92>
	ticks = MAX(MIN(ticks - 1, (int32_t)MAX_TICKS), 0);
20000ebc:	3801      	subs	r0, #1
20000ebe:	ea20 70e0 	bic.w	r0, r0, r0, asr #31
20000ec2:	42a0      	cmp	r0, r4
20000ec4:	bfa8      	it	ge
20000ec6:	4620      	movge	r0, r4
	}

	/* Get the cycles from last_count to the tick boundary after
	 * the requested ticks have passed starting now.
	 */
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
20000ec8:	3301      	adds	r3, #1
20000eca:	4418      	add	r0, r3
	 */
	if (cyc > MAX_CYCLES) {
		cyc = MAX_CYCLES;
	}

	cyc += last_count;
20000ecc:	42a0      	cmp	r0, r4
20000ece:	bf94      	ite	ls
20000ed0:	180c      	addls	r4, r1, r0
20000ed2:	190c      	addhi	r4, r1, r4
    p_reg->INTENCLR = mask;
20000ed4:	f44f 3080 	mov.w	r0, #65536	; 0x10000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
20000ed8:	2600      	movs	r6, #0
    p_reg->INTENCLR = mask;
20000eda:	4a1e      	ldr	r2, [pc, #120]	; (20000f54 <z_clock_set_timeout+0xb8>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
20000edc:	4d20      	ldr	r5, [pc, #128]	; (20000f60 <z_clock_set_timeout+0xc4>)
    p_reg->INTENCLR = mask;
20000ede:	f8c2 0308 	str.w	r0, [r2, #776]	; 0x308
     return p_reg->COUNTER;
20000ee2:	f8d2 1504 	ldr.w	r1, [r2, #1284]	; 0x504
    return p_reg->CC[ch];
20000ee6:	f8d2 3540 	ldr.w	r3, [r2, #1344]	; 0x540
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
20000eea:	602e      	str	r6, [r5, #0]
	return (a - b) & COUNTER_MAX;
20000eec:	1a5b      	subs	r3, r3, r1
20000eee:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
20000ef2:	682f      	ldr	r7, [r5, #0]
	if (counter_sub(prev_val, now) == 1) {
20000ef4:	2b01      	cmp	r3, #1
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
20000ef6:	f021 477f 	bic.w	r7, r1, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
20000efa:	f8c2 7540 	str.w	r7, [r2, #1344]	; 0x540
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
20000efe:	f8c2 0344 	str.w	r0, [r2, #836]	; 0x344
	if (counter_sub(prev_val, now) == 1) {
20000f02:	d104      	bne.n	20000f0e <z_clock_set_timeout+0x72>
	z_impl_k_busy_wait(usec_to_wait);
20000f04:	200f      	movs	r0, #15
20000f06:	f003 f807 	bl	20003f18 <z_impl_k_busy_wait>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
20000f0a:	602e      	str	r6, [r5, #0]
20000f0c:	682b      	ldr	r3, [r5, #0]
20000f0e:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
20000f12:	4b14      	ldr	r3, [pc, #80]	; (20000f64 <z_clock_set_timeout+0xc8>)
20000f14:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
     return p_reg->COUNTER;
20000f18:	4b0e      	ldr	r3, [pc, #56]	; (20000f54 <z_clock_set_timeout+0xb8>)
20000f1a:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
20000f1e:	1a22      	subs	r2, r4, r0
20000f20:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
	if (diff == 1) {
20000f24:	2a01      	cmp	r2, #1
20000f26:	d104      	bne.n	20000f32 <z_clock_set_timeout+0x96>
		handle_next_cycle_case(t);
20000f28:	f7ff ff64 	bl	20000df4 <handle_next_cycle_case>
20000f2c:	e00b      	b.n	20000f46 <z_clock_set_timeout+0xaa>
		ticks = 0;
20000f2e:	2000      	movs	r0, #0
20000f30:	e7ca      	b.n	20000ec8 <z_clock_set_timeout+0x2c>
	nrf_rtc_cc_set(RTC, 0, cyc & COUNTER_MAX);
20000f32:	f024 427f 	bic.w	r2, r4, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
20000f36:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
     return p_reg->COUNTER;
20000f3a:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
20000f3e:	1a24      	subs	r4, r4, r0
20000f40:	3c02      	subs	r4, #2
	if (diff > MAX_CYCLES) {
20000f42:	0223      	lsls	r3, r4, #8
20000f44:	d4f0      	bmi.n	20000f28 <z_clock_set_timeout+0x8c>
    p_reg->INTENSET = mask;
20000f46:	f44f 3280 	mov.w	r2, #65536	; 0x10000
20000f4a:	4b02      	ldr	r3, [pc, #8]	; (20000f54 <z_clock_set_timeout+0xb8>)
20000f4c:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
	set_protected_absolute_alarm(cyc);
}
20000f50:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
20000f52:	bf00      	nop
20000f54:	50015000 	.word	0x50015000
20000f58:	007fffff 	.word	0x007fffff
20000f5c:	200202fc 	.word	0x200202fc
20000f60:	50015140 	.word	0x50015140
20000f64:	e000e100 	.word	0xe000e100

20000f68 <z_clock_elapsed>:
	__asm__ volatile(
20000f68:	f04f 0220 	mov.w	r2, #32
20000f6c:	f3ef 8311 	mrs	r3, BASEPRI
20000f70:	f382 8811 	msr	BASEPRI, r2
20000f74:	f3bf 8f6f 	isb	sy
     return p_reg->COUNTER;
20000f78:	4a06      	ldr	r2, [pc, #24]	; (20000f94 <z_clock_elapsed+0x2c>)
20000f7a:	f8d2 0504 	ldr.w	r0, [r2, #1284]	; 0x504
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return 0;
	}

	k_spinlock_key_t key = k_spin_lock(&lock);
	uint32_t ret = counter_sub(counter(), last_count) / CYC_PER_TICK;
20000f7e:	4a06      	ldr	r2, [pc, #24]	; (20000f98 <z_clock_elapsed+0x30>)
	return (a - b) & COUNTER_MAX;
20000f80:	6812      	ldr	r2, [r2, #0]
20000f82:	1a80      	subs	r0, r0, r2
20000f84:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	__asm__ volatile(
20000f88:	f383 8811 	msr	BASEPRI, r3
20000f8c:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&lock, key);
	return ret;
}
20000f90:	4770      	bx	lr
20000f92:	bf00      	nop
20000f94:	50015000 	.word	0x50015000
20000f98:	200202fc 	.word	0x200202fc

20000f9c <nrf_cc3xx_platform_abort_init>:

/** @brief Function to initialize the nrf_cc3xx_platform abort APIs.
 */
void nrf_cc3xx_platform_abort_init(void)
{
	nrf_cc3xx_platform_set_abort(&apis);
20000f9c:	4801      	ldr	r0, [pc, #4]	; (20000fa4 <nrf_cc3xx_platform_abort_init+0x8>)
20000f9e:	f002 b997 	b.w	200032d0 <nrf_cc3xx_platform_set_abort>
20000fa2:	bf00      	nop
20000fa4:	20004280 	.word	0x20004280

20000fa8 <mutex_unlock_platform>:
}


/** @brief Static function to unlock a mutex
 */
static int32_t mutex_unlock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
20000fa8:	b508      	push	{r3, lr}
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
20000faa:	b130      	cbz	r0, 20000fba <mutex_unlock_platform+0x12>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    /* Ensure that the mutex has been initialized */
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
20000fac:	6843      	ldr	r3, [r0, #4]
20000fae:	b13b      	cbz	r3, 20000fc0 <mutex_unlock_platform+0x18>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    }

    p_mutex = (struct k_mutex *)mutex->mutex;
20000fb0:	6800      	ldr	r0, [r0, #0]
	return z_impl_k_mutex_unlock(mutex);
20000fb2:	f001 fb6f 	bl	20002694 <z_impl_k_mutex_unlock>

    k_mutex_unlock(p_mutex);
    return NRF_CC3XX_PLATFORM_SUCCESS;
20000fb6:	2000      	movs	r0, #0
}
20000fb8:	bd08      	pop	{r3, pc}
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
20000fba:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
20000fbe:	e7fb      	b.n	20000fb8 <mutex_unlock_platform+0x10>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
20000fc0:	4800      	ldr	r0, [pc, #0]	; (20000fc4 <mutex_unlock_platform+0x1c>)
20000fc2:	e7f9      	b.n	20000fb8 <mutex_unlock_platform+0x10>
20000fc4:	ffff8fea 	.word	0xffff8fea

20000fc8 <mutex_free_platform>:
static void mutex_free_platform(nrf_cc3xx_platform_mutex_t *mutex) {
20000fc8:	b510      	push	{r4, lr}
    if (mutex == NULL) {
20000fca:	4604      	mov	r4, r0
20000fcc:	b918      	cbnz	r0, 20000fd6 <mutex_free_platform+0xe>
        platform_abort_apis.abort_fn(
20000fce:	4b0b      	ldr	r3, [pc, #44]	; (20000ffc <mutex_free_platform+0x34>)
20000fd0:	480b      	ldr	r0, [pc, #44]	; (20001000 <mutex_free_platform+0x38>)
20000fd2:	685b      	ldr	r3, [r3, #4]
20000fd4:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
20000fd6:	6861      	ldr	r1, [r4, #4]
20000fd8:	b159      	cbz	r1, 20000ff2 <mutex_free_platform+0x2a>
    if ((mutex->flags & NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED) != 0) {
20000fda:	f011 0102 	ands.w	r1, r1, #2
20000fde:	6820      	ldr	r0, [r4, #0]
20000fe0:	d008      	beq.n	20000ff4 <mutex_free_platform+0x2c>
        k_mem_slab_free(&mutex_slab, mutex->mutex);
20000fe2:	4601      	mov	r1, r0
20000fe4:	4807      	ldr	r0, [pc, #28]	; (20001004 <mutex_free_platform+0x3c>)
20000fe6:	f001 fab3 	bl	20002550 <k_mem_slab_free>
        mutex->mutex = NULL;
20000fea:	2300      	movs	r3, #0
20000fec:	6023      	str	r3, [r4, #0]
    mutex->flags = NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID;
20000fee:	2300      	movs	r3, #0
20000ff0:	6063      	str	r3, [r4, #4]
}
20000ff2:	bd10      	pop	{r4, pc}
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
20000ff4:	2214      	movs	r2, #20
20000ff6:	f002 fd44 	bl	20003a82 <memset>
20000ffa:	e7f8      	b.n	20000fee <mutex_free_platform+0x26>
20000ffc:	20020048 	.word	0x20020048
20001000:	20004428 	.word	0x20004428
20001004:	20020300 	.word	0x20020300

20001008 <mutex_init_platform>:
static void mutex_init_platform(nrf_cc3xx_platform_mutex_t *mutex) {
20001008:	b510      	push	{r4, lr}
    if (mutex == NULL) {
2000100a:	4604      	mov	r4, r0
2000100c:	b918      	cbnz	r0, 20001016 <mutex_init_platform+0xe>
        platform_abort_apis.abort_fn(
2000100e:	4b14      	ldr	r3, [pc, #80]	; (20001060 <mutex_init_platform+0x58>)
20001010:	4814      	ldr	r0, [pc, #80]	; (20001064 <mutex_init_platform+0x5c>)
20001012:	685b      	ldr	r3, [r3, #4]
20001014:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID &&
20001016:	6863      	ldr	r3, [r4, #4]
20001018:	b9cb      	cbnz	r3, 2000104e <mutex_init_platform+0x46>
2000101a:	6823      	ldr	r3, [r4, #0]
2000101c:	b9bb      	cbnz	r3, 2000104e <mutex_init_platform+0x46>
        ret = k_mem_slab_alloc(&mutex_slab, &mutex->mutex, K_FOREVER);
2000101e:	f04f 32ff 	mov.w	r2, #4294967295
20001022:	f04f 33ff 	mov.w	r3, #4294967295
20001026:	4621      	mov	r1, r4
20001028:	480f      	ldr	r0, [pc, #60]	; (20001068 <mutex_init_platform+0x60>)
2000102a:	f001 fa5f 	bl	200024ec <k_mem_slab_alloc>
        if(ret != 0 || mutex->mutex == NULL)
2000102e:	b908      	cbnz	r0, 20001034 <mutex_init_platform+0x2c>
20001030:	6823      	ldr	r3, [r4, #0]
20001032:	b91b      	cbnz	r3, 2000103c <mutex_init_platform+0x34>
            platform_abort_apis.abort_fn(
20001034:	4b0a      	ldr	r3, [pc, #40]	; (20001060 <mutex_init_platform+0x58>)
20001036:	480d      	ldr	r0, [pc, #52]	; (2000106c <mutex_init_platform+0x64>)
20001038:	685b      	ldr	r3, [r3, #4]
2000103a:	4798      	blx	r3
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
2000103c:	2214      	movs	r2, #20
2000103e:	2100      	movs	r1, #0
20001040:	6820      	ldr	r0, [r4, #0]
20001042:	f002 fd1e 	bl	20003a82 <memset>
        mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED;
20001046:	6863      	ldr	r3, [r4, #4]
20001048:	f043 0302 	orr.w	r3, r3, #2
2000104c:	6063      	str	r3, [r4, #4]
    p_mutex = (struct k_mutex *)mutex->mutex;
2000104e:	6820      	ldr	r0, [r4, #0]
	return z_impl_k_mutex_init(mutex);
20001050:	f002 fea9 	bl	20003da6 <z_impl_k_mutex_init>
    mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_VALID;
20001054:	6863      	ldr	r3, [r4, #4]
20001056:	f043 0301 	orr.w	r3, r3, #1
2000105a:	6063      	str	r3, [r4, #4]
}
2000105c:	bd10      	pop	{r4, pc}
2000105e:	bf00      	nop
20001060:	20020048 	.word	0x20020048
20001064:	20004428 	.word	0x20004428
20001068:	20020300 	.word	0x20020300
2000106c:	2000444e 	.word	0x2000444e

20001070 <mutex_lock_platform>:
static int32_t mutex_lock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
20001070:	b508      	push	{r3, lr}
    if(mutex == NULL) {
20001072:	b168      	cbz	r0, 20001090 <mutex_lock_platform+0x20>
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
20001074:	6843      	ldr	r3, [r0, #4]
20001076:	b173      	cbz	r3, 20001096 <mutex_lock_platform+0x26>
    p_mutex = (struct k_mutex *)mutex->mutex;
20001078:	6800      	ldr	r0, [r0, #0]
	return z_impl_k_mutex_lock(mutex, timeout);
2000107a:	f04f 33ff 	mov.w	r3, #4294967295
2000107e:	f04f 32ff 	mov.w	r2, #4294967295
20001082:	f001 fa8f 	bl	200025a4 <z_impl_k_mutex_lock>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_FAILED;
20001086:	4b05      	ldr	r3, [pc, #20]	; (2000109c <mutex_lock_platform+0x2c>)
    if (ret == 0) {
20001088:	2800      	cmp	r0, #0
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_FAILED;
2000108a:	bf18      	it	ne
2000108c:	4618      	movne	r0, r3
}
2000108e:	bd08      	pop	{r3, pc}
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
20001090:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
20001094:	e7fb      	b.n	2000108e <mutex_lock_platform+0x1e>
        return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
20001096:	4802      	ldr	r0, [pc, #8]	; (200010a0 <mutex_lock_platform+0x30>)
20001098:	e7f9      	b.n	2000108e <mutex_lock_platform+0x1e>
2000109a:	bf00      	nop
2000109c:	ffff8fe9 	.word	0xffff8fe9
200010a0:	ffff8fea 	.word	0xffff8fea

200010a4 <nrf_cc3xx_platform_mutex_init>:
};

/** @brief Function to initialize the nrf_cc3xx_platform mutex APIs
 */
void nrf_cc3xx_platform_mutex_init(void)
{
200010a4:	b508      	push	{r3, lr}
    k_mem_slab_init(&mutex_slab,
200010a6:	4906      	ldr	r1, [pc, #24]	; (200010c0 <nrf_cc3xx_platform_mutex_init+0x1c>)
200010a8:	2340      	movs	r3, #64	; 0x40
200010aa:	2214      	movs	r2, #20
200010ac:	4805      	ldr	r0, [pc, #20]	; (200010c4 <nrf_cc3xx_platform_mutex_init+0x20>)
200010ae:	f002 fe5f 	bl	20003d70 <k_mem_slab_init>
            mutex_slab_buffer,
            sizeof(struct k_mutex),
            NUM_MUTEXES);

    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
}
200010b2:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
200010b6:	4904      	ldr	r1, [pc, #16]	; (200010c8 <nrf_cc3xx_platform_mutex_init+0x24>)
200010b8:	4804      	ldr	r0, [pc, #16]	; (200010cc <nrf_cc3xx_platform_mutex_init+0x28>)
200010ba:	f002 b95b 	b.w	20003374 <nrf_cc3xx_platform_set_mutexes>
200010be:	bf00      	nop
200010c0:	2002031c 	.word	0x2002031c
200010c4:	20020300 	.word	0x20020300
200010c8:	20004298 	.word	0x20004298
200010cc:	20004288 	.word	0x20004288

200010d0 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
200010d0:	4a09      	ldr	r2, [pc, #36]	; (200010f8 <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
200010d2:	490a      	ldr	r1, [pc, #40]	; (200010fc <arch_swap+0x2c>)
	_current->arch.basepri = key;
200010d4:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
200010d6:	6809      	ldr	r1, [r1, #0]
	_current->arch.basepri = key;
200010d8:	6798      	str	r0, [r3, #120]	; 0x78
	_current->arch.swap_return_value = _k_neg_eagain;
200010da:	67d9      	str	r1, [r3, #124]	; 0x7c

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
200010dc:	4908      	ldr	r1, [pc, #32]	; (20001100 <arch_swap+0x30>)
200010de:	684b      	ldr	r3, [r1, #4]
200010e0:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
200010e4:	604b      	str	r3, [r1, #4]
200010e6:	2300      	movs	r3, #0
200010e8:	f383 8811 	msr	BASEPRI, r3
200010ec:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
200010f0:	6893      	ldr	r3, [r2, #8]
}
200010f2:	6fd8      	ldr	r0, [r3, #124]	; 0x7c
200010f4:	4770      	bx	lr
200010f6:	bf00      	nop
200010f8:	20020874 	.word	0x20020874
200010fc:	20004340 	.word	0x20004340
20001100:	e000ed00 	.word	0xe000ed00

20001104 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_TRACING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
20001104:	4913      	ldr	r1, [pc, #76]	; (20001154 <z_arm_pendsv+0x50>)
    ldr r2, [r1, #_kernel_offset_to_current]
20001106:	688a      	ldr	r2, [r1, #8]

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
20001108:	f04f 0038 	mov.w	r0, #56	; 0x38
    add r0, r2
2000110c:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
2000110e:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
20001112:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
20001116:	2020      	movs	r0, #32
    msr BASEPRI, r0
20001118:	f380 8811 	msr	BASEPRI, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
2000111c:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
20001120:	4f0d      	ldr	r7, [pc, #52]	; (20001158 <z_arm_pendsv+0x54>)
    ldr v3, =_SCS_ICSR_UNPENDSV
20001122:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
20001126:	6a4a      	ldr	r2, [r1, #36]	; 0x24

    str r2, [r1, #_kernel_offset_to_current]
20001128:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
2000112a:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
2000112c:	6f90      	ldr	r0, [r2, #120]	; 0x78
    movs r3, #0
2000112e:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
20001130:	6793      	str	r3, [r2, #120]	; 0x78
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
20001132:	f380 8811 	msr	BASEPRI, r0
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
20001136:	f102 0038 	add.w	r0, r2, #56	; 0x38
    ldmia r0, {v1-v8, ip}
2000113a:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
2000113e:	f38c 8809 	msr	PSP, ip
#endif

#ifdef CONFIG_BUILTIN_STACK_GUARD
    /* r2 contains k_thread */
    add r0, r2, #0
20001142:	f102 0000 	add.w	r0, r2, #0
    push {r2, lr}
20001146:	b504      	push	{r2, lr}
    bl configure_builtin_stack_guard
20001148:	f002 fc2a 	bl	200039a0 <configure_builtin_stack_guard>
    pop {r2, lr}
2000114c:	e8bd 4004 	ldmia.w	sp!, {r2, lr}

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (_IntExit or z_arm_svc)
     */
    bx lr
20001150:	4770      	bx	lr
20001152:	0000      	.short	0x0000
    ldr r1, =_kernel
20001154:	20020874 	.word	0x20020874
    ldr v4, =_SCS_ICSR
20001158:	e000ed04 	.word	0xe000ed04

2000115c <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #0x4    /* did we come from thread mode ? */
2000115c:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
20001160:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
20001162:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
20001166:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
2000116a:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
2000116c:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
20001170:	2902      	cmp	r1, #2
    beq _oops
20001172:	d0ff      	beq.n	20001174 <_oops>

20001174 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
20001174:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
20001176:	f002 fc19 	bl	200039ac <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
2000117a:	bd01      	pop	{r0, pc}

2000117c <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
2000117c:	b243      	sxtb	r3, r0
  if ((int32_t)(IRQn) >= 0)
2000117e:	2b00      	cmp	r3, #0
20001180:	db08      	blt.n	20001194 <arch_irq_enable+0x18>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
20001182:	2201      	movs	r2, #1
20001184:	f000 001f 	and.w	r0, r0, #31
20001188:	fa02 f000 	lsl.w	r0, r2, r0
2000118c:	4a02      	ldr	r2, [pc, #8]	; (20001198 <arch_irq_enable+0x1c>)
2000118e:	095b      	lsrs	r3, r3, #5
20001190:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
20001194:	4770      	bx	lr
20001196:	bf00      	nop
20001198:	e000e100 	.word	0xe000e100

2000119c <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
2000119c:	4b05      	ldr	r3, [pc, #20]	; (200011b4 <arch_irq_is_enabled+0x18>)
2000119e:	0942      	lsrs	r2, r0, #5
200011a0:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
200011a4:	2301      	movs	r3, #1
200011a6:	f000 001f 	and.w	r0, r0, #31
200011aa:	fa03 f000 	lsl.w	r0, r3, r0
}
200011ae:	4010      	ands	r0, r2
200011b0:	4770      	bx	lr
200011b2:	bf00      	nop
200011b4:	e000e100 	.word	0xe000e100

200011b8 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
200011b8:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
200011ba:	2b00      	cmp	r3, #0
	prio += _IRQ_PRIO_OFFSET;
200011bc:	f101 0101 	add.w	r1, r1, #1
  {
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
200011c0:	bfac      	ite	ge
200011c2:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
  }
  else
  {
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
200011c6:	4b06      	ldrlt	r3, [pc, #24]	; (200011e0 <z_arm_irq_priority_set+0x28>)
200011c8:	ea4f 1141 	mov.w	r1, r1, lsl #5
200011cc:	b2c9      	uxtb	r1, r1
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
200011ce:	bfab      	itete	ge
200011d0:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
200011d4:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
200011d8:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
200011dc:	5419      	strblt	r1, [r3, r0]
}
200011de:	4770      	bx	lr
200011e0:	e000ed14 	.word	0xe000ed14

200011e4 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
200011e4:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
200011e8:	9b00      	ldr	r3, [sp, #0]
	iframe->pc &= 0xfffffffe;
200011ea:	490b      	ldr	r1, [pc, #44]	; (20001218 <arch_new_thread+0x34>)
	iframe->a2 = (uint32_t)p1;
200011ec:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->a3 = (uint32_t)p2;
200011f0:	9b01      	ldr	r3, [sp, #4]
	iframe->pc &= 0xfffffffe;
200011f2:	f021 0101 	bic.w	r1, r1, #1
	iframe->a3 = (uint32_t)p2;
200011f6:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
200011fa:	9b02      	ldr	r3, [sp, #8]
	iframe->pc &= 0xfffffffe;
200011fc:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->a4 = (uint32_t)p3;
20001200:	f842 3c14 	str.w	r3, [r2, #-20]

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
20001204:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
20001208:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
2000120c:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
2000120e:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
20001210:	6582      	str	r2, [r0, #88]	; 0x58
	thread->arch.basepri = 0;
20001212:	6783      	str	r3, [r0, #120]	; 0x78
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
20001214:	4770      	bx	lr
20001216:	bf00      	nop
20001218:	20003681 	.word	0x20003681

2000121c <arch_switch_to_main_thread>:
#endif
}

void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
2000121c:	4604      	mov	r4, r0
2000121e:	b508      	push	{r3, lr}
20001220:	460e      	mov	r6, r1
20001222:	4615      	mov	r5, r2
	z_arm_configure_static_mpu_regions();
20001224:	f000 f9c2 	bl	200015ac <z_arm_configure_static_mpu_regions>
	z_arm_prepare_switch_to_main();

	_current = main_thread;
20001228:	4b08      	ldr	r3, [pc, #32]	; (2000124c <arch_switch_to_main_thread+0x30>)
2000122a:	609c      	str	r4, [r3, #8]
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  // without main extensions, the non-secure PSPLIM is RAZ/WI
  (void)ProcStackPtrLimit;
#else
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
2000122c:	6ea3      	ldr	r3, [r4, #104]	; 0x68
2000122e:	f383 880b 	msr	PSPLIM, r3

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
20001232:	4628      	mov	r0, r5
20001234:	f386 8809 	msr	PSP, r6
20001238:	2100      	movs	r1, #0
2000123a:	b663      	cpsie	if
2000123c:	f381 8811 	msr	BASEPRI, r1
20001240:	f3bf 8f6f 	isb	sy
20001244:	2200      	movs	r2, #0
20001246:	2300      	movs	r3, #0
20001248:	f002 fa1a 	bl	20003680 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
2000124c:	20020874 	.word	0x20020874

20001250 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
20001250:	4901      	ldr	r1, [pc, #4]	; (20001258 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
20001252:	2210      	movs	r2, #16
	str	r2, [r1]
20001254:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
20001256:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
20001258:	e000ed10 	.word	0xe000ed10

2000125c <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
2000125c:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
2000125e:	4040      	eors	r0, r0
	msr	BASEPRI, r0
20001260:	f380 8811 	msr	BASEPRI, r0
	isb
20001264:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
20001268:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
2000126c:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
2000126e:	b662      	cpsie	i
	isb
20001270:	f3bf 8f6f 	isb	sy

	bx	lr
20001274:	4770      	bx	lr
20001276:	bf00      	nop

20001278 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
20001278:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
2000127a:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
2000127c:	f381 8811 	msr	BASEPRI, r1

	wfe
20001280:	bf20      	wfe

	msr	BASEPRI, r0
20001282:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
20001286:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
20001288:	4770      	bx	lr
2000128a:	bf00      	nop

2000128c <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
2000128c:	bf30      	wfi
    b z_SysNmiOnReset
2000128e:	f7ff bffd 	b.w	2000128c <z_SysNmiOnReset>
20001292:	bf00      	nop

20001294 <z_arm_prep_c>:
#else
#define VECTOR_ADDRESS CONFIG_SRAM_BASE_ADDRESS
#endif
static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
20001294:	4a0e      	ldr	r2, [pc, #56]	; (200012d0 <z_arm_prep_c+0x3c>)
 * This routine prepares for the execution of and runs C code.
 *
 * @return N/A
 */
void z_arm_prep_c(void)
{
20001296:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
20001298:	4b0e      	ldr	r3, [pc, #56]	; (200012d4 <z_arm_prep_c+0x40>)
2000129a:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
2000129e:	609a      	str	r2, [r3, #8]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
200012a0:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
200012a4:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
200012a8:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
200012ac:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
200012b0:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
  __ASM volatile ("MRS %0, control" : "=r" (result) );
200012b4:	f3ef 8314 	mrs	r3, CONTROL
	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
200012b8:	f023 0304 	bic.w	r3, r3, #4
  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
200012bc:	f383 8814 	msr	CONTROL, r3
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
200012c0:	f001 f82a 	bl	20002318 <z_bss_zero>
	z_data_copy();
200012c4:	f001 f832 	bl	2000232c <z_data_copy>
#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
200012c8:	f000 f938 	bl	2000153c <z_arm_interrupt_init>
	z_cstart();
200012cc:	f001 f86c 	bl	200023a8 <z_cstart>
200012d0:	20000000 	.word	0x20000000
200012d4:	e000ed00 	.word	0xe000ed00

200012d8 <_isr_wrapper>:
 * @return N/A
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
200012d8:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
200012da:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
200012dc:	4a0b      	ldr	r2, [pc, #44]	; (2000130c <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
200012de:	6a10      	ldr	r0, [r2, #32]
	cmp r0, #0
200012e0:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_sys_power_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
200012e2:	bf1e      	ittt	ne
	movne	r1, #0
200012e4:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
200012e6:	6211      	strne	r1, [r2, #32]
		blne	z_sys_power_save_idle_exit
200012e8:	f002 fd40 	blne	20003d6c <z_sys_power_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
200012ec:	b662      	cpsie	i
#endif

#endif /* CONFIG_SYS_POWER_MANAGEMENT */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
200012ee:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
200012f2:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
200012f6:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	 * interface function.
	 */
	cpsie i
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
200012fa:	4905      	ldr	r1, [pc, #20]	; (20001310 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
200012fc:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
200012fe:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
20001300:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
20001302:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
20001306:	4903      	ldr	r1, [pc, #12]	; (20001314 <_isr_wrapper+0x3c>)
	bx r1
20001308:	4708      	bx	r1
2000130a:	0000      	.short	0x0000
	ldr r2, =_kernel
2000130c:	20020874 	.word	0x20020874
	ldr r1, =_sw_isr_table
20001310:	20004018 	.word	0x20004018
	ldr r1, =z_arm_int_exit
20001314:	200014fd 	.word	0x200014fd

20001318 <__start>:
 * search for a __start symbol instead, so create that alias here.
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_platform_init
20001318:	f002 fa99 	bl	2000384e <z_platform_init>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
2000131c:	2020      	movs	r0, #32
    msr BASEPRI, r0
2000131e:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
20001322:	4808      	ldr	r0, [pc, #32]	; (20001344 <__start+0x2c>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
20001324:	f44f 6100 	mov.w	r1, #2048	; 0x800
    adds r0, r0, r1
20001328:	1840      	adds	r0, r0, r1
    msr PSP, r0
2000132a:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
2000132e:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
20001332:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
20001334:	4308      	orrs	r0, r1
    msr CONTROL, r0
20001336:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
2000133a:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
2000133e:	f7ff ffa9 	bl	20001294 <z_arm_prep_c>
20001342:	0000      	.short	0x0000
    ldr r0, =z_interrupt_stacks
20001344:	20020e10 	.word	0x20020e10

20001348 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
20001348:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
2000134c:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
20001350:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
20001352:	4672      	mov	r2, lr
	bl z_arm_fault
20001354:	f000 f852 	bl	200013fc <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
20001358:	bd01      	pop	{r0, pc}
2000135a:	bf00      	nop

2000135c <mem_manage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
2000135c:	4b0c      	ldr	r3, [pc, #48]	; (20001390 <mem_manage_fault.isra.0+0x34>)
2000135e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error (context area might be"
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
20001360:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
20001362:	6a9a      	ldr	r2, [r3, #40]	; 0x28
20001364:	0792      	lsls	r2, r2, #30
20001366:	d508      	bpl.n	2000137a <mem_manage_fault.isra.0+0x1e>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		mmfar = SCB->MMFAR;
20001368:	6b5a      	ldr	r2, [r3, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
2000136a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
2000136c:	0612      	lsls	r2, r2, #24
2000136e:	d504      	bpl.n	2000137a <mem_manage_fault.isra.0+0x1e>
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
			if (from_hard_fault) {
20001370:	b118      	cbz	r0, 2000137a <mem_manage_fault.isra.0+0x1e>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
20001372:	6a9a      	ldr	r2, [r3, #40]	; 0x28
20001374:	f022 0280 	bic.w	r2, r2, #128	; 0x80
20001378:	629a      	str	r2, [r3, #40]	; 0x28

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf);
2000137a:	2000      	movs	r0, #0
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
2000137c:	4b04      	ldr	r3, [pc, #16]	; (20001390 <mem_manage_fault.isra.0+0x34>)
2000137e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
20001380:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_MSTKERR_Msk) {
20001382:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
20001384:	6a9a      	ldr	r2, [r3, #40]	; 0x28
20001386:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
2000138a:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf);
2000138c:	7008      	strb	r0, [r1, #0]

	return reason;
}
2000138e:	4770      	bx	lr
20001390:	e000ed00 	.word	0xe000ed00

20001394 <bus_fault.isra.0>:
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
20001394:	4b0d      	ldr	r3, [pc, #52]	; (200013cc <bus_fault.isra.0+0x38>)
20001396:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error");
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
20001398:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
2000139a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
2000139c:	0592      	lsls	r2, r2, #22
2000139e:	d508      	bpl.n	200013b2 <bus_fault.isra.0+0x1e>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
200013a0:	6b9a      	ldr	r2, [r3, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
200013a2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
200013a4:	0412      	lsls	r2, r2, #16
200013a6:	d504      	bpl.n	200013b2 <bus_fault.isra.0+0x1e>
			PR_EXC("  BFAR Address: 0x%x", bfar);
			if (from_hard_fault) {
200013a8:	b118      	cbz	r0, 200013b2 <bus_fault.isra.0+0x1e>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
200013aa:	6a9a      	ldr	r2, [r3, #40]	; 0x28
200013ac:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
200013b0:	629a      	str	r2, [r3, #40]	; 0x28
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;

	*recoverable = memory_fault_recoverable(esf);
200013b2:	2000      	movs	r0, #0
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
200013b4:	4b05      	ldr	r3, [pc, #20]	; (200013cc <bus_fault.isra.0+0x38>)
200013b6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
200013b8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
200013ba:	05d2      	lsls	r2, r2, #23
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
200013bc:	bf58      	it	pl
200013be:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
200013c0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
200013c2:	f442 427f 	orr.w	r2, r2, #65280	; 0xff00
200013c6:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf);
200013c8:	7008      	strb	r0, [r1, #0]

	return reason;
}
200013ca:	4770      	bx	lr
200013cc:	e000ed00 	.word	0xe000ed00

200013d0 <usage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
200013d0:	4b09      	ldr	r3, [pc, #36]	; (200013f8 <usage_fault.isra.0+0x28>)
200013d2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
200013d4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unaligned memory access");
	}
#if defined(CONFIG_ARMV8_M_MAINLINE)
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
200013d6:	6a98      	ldr	r0, [r3, #40]	; 0x28
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
200013d8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
200013da:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
200013dc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
200013de:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
200013e0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
200013e2:	f410 1080 	ands.w	r0, r0, #1048576	; 0x100000
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
200013e6:	ea6f 4202 	mvn.w	r2, r2, lsl #16
200013ea:	ea6f 4212 	mvn.w	r2, r2, lsr #16

	return reason;
}
200013ee:	bf18      	it	ne
200013f0:	2002      	movne	r0, #2
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
200013f2:	629a      	str	r2, [r3, #40]	; 0x28
}
200013f4:	4770      	bx	lr
200013f6:	bf00      	nop
200013f8:	e000ed00 	.word	0xe000ed00

200013fc <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
200013fc:	b570      	push	{r4, r5, r6, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
200013fe:	4b36      	ldr	r3, [pc, #216]	; (200014d8 <z_arm_fault+0xdc>)
{
20001400:	460e      	mov	r6, r1
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
20001402:	685b      	ldr	r3, [r3, #4]
20001404:	2500      	movs	r5, #0
{
20001406:	b08a      	sub	sp, #40	; 0x28
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
20001408:	f3c3 0308 	ubfx	r3, r3, #0, #9
2000140c:	f385 8811 	msr	BASEPRI, r5
20001410:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
20001414:	f002 417f 	and.w	r1, r2, #4278190080	; 0xff000000
20001418:	f1b1 4f7f 	cmp.w	r1, #4278190080	; 0xff000000
2000141c:	d111      	bne.n	20001442 <z_arm_fault+0x46>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
2000141e:	f002 010c 	and.w	r1, r2, #12
20001422:	2908      	cmp	r1, #8
20001424:	d00d      	beq.n	20001442 <z_arm_fault+0x46>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
20001426:	0711      	lsls	r1, r2, #28
20001428:	d401      	bmi.n	2000142e <z_arm_fault+0x32>
			ptr_esf = (z_arch_esf_t *)msp;
2000142a:	4606      	mov	r6, r0
			*nested_exc = true;
2000142c:	2501      	movs	r5, #1
	*recoverable = false;
2000142e:	2200      	movs	r2, #0
20001430:	3b03      	subs	r3, #3
20001432:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
20001436:	2b03      	cmp	r3, #3
20001438:	d847      	bhi.n	200014ca <z_arm_fault+0xce>
2000143a:	e8df f003 	tbb	[pc, r3]
2000143e:	3e04      	.short	0x3e04
20001440:	3b42      	.short	0x3b42
		return NULL;
20001442:	462e      	mov	r6, r5
20001444:	e7f3      	b.n	2000142e <z_arm_fault+0x32>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
20001446:	4b24      	ldr	r3, [pc, #144]	; (200014d8 <z_arm_fault+0xdc>)
20001448:	6ada      	ldr	r2, [r3, #44]	; 0x2c
2000144a:	0792      	lsls	r2, r2, #30
2000144c:	d43d      	bmi.n	200014ca <z_arm_fault+0xce>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
2000144e:	6adc      	ldr	r4, [r3, #44]	; 0x2c
20001450:	f014 4480 	ands.w	r4, r4, #1073741824	; 0x40000000
20001454:	d008      	beq.n	20001468 <z_arm_fault+0x6c>
		if (SCB_MMFSR != 0) {
20001456:	3328      	adds	r3, #40	; 0x28
20001458:	781b      	ldrb	r3, [r3, #0]
2000145a:	b1eb      	cbz	r3, 20001498 <z_arm_fault+0x9c>
			reason = mem_manage_fault(esf, 1, recoverable);
2000145c:	2001      	movs	r0, #1
2000145e:	f10d 0107 	add.w	r1, sp, #7
		reason = mem_manage_fault(esf, 0, recoverable);
20001462:	f7ff ff7b 	bl	2000135c <mem_manage_fault.isra.0>
		reason = usage_fault(esf);
20001466:	4604      	mov	r4, r0
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
20001468:	f89d 3007 	ldrb.w	r3, [sp, #7]
2000146c:	b993      	cbnz	r3, 20001494 <z_arm_fault+0x98>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
2000146e:	2220      	movs	r2, #32
20001470:	4631      	mov	r1, r6
20001472:	a802      	add	r0, sp, #8
20001474:	f002 fada 	bl	20003a2c <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
20001478:	9b09      	ldr	r3, [sp, #36]	; 0x24
2000147a:	b345      	cbz	r5, 200014ce <z_arm_fault+0xd2>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
2000147c:	f3c3 0208 	ubfx	r2, r3, #0, #9
20001480:	b922      	cbnz	r2, 2000148c <z_arm_fault+0x90>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
20001482:	ea6f 2353 	mvn.w	r3, r3, lsr #9
20001486:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
2000148a:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
2000148c:	4620      	mov	r0, r4
2000148e:	a902      	add	r1, sp, #8
20001490:	f002 fa8a 	bl	200039a8 <z_arm_fatal_error>
}
20001494:	b00a      	add	sp, #40	; 0x28
20001496:	bd70      	pop	{r4, r5, r6, pc}
		} else if (SCB_BFSR != 0) {
20001498:	4b10      	ldr	r3, [pc, #64]	; (200014dc <z_arm_fault+0xe0>)
2000149a:	781b      	ldrb	r3, [r3, #0]
2000149c:	b12b      	cbz	r3, 200014aa <z_arm_fault+0xae>
			reason = bus_fault(esf, 1, recoverable);
2000149e:	2001      	movs	r0, #1
200014a0:	f10d 0107 	add.w	r1, sp, #7
		reason = bus_fault(esf, 0, recoverable);
200014a4:	f7ff ff76 	bl	20001394 <bus_fault.isra.0>
200014a8:	e7dd      	b.n	20001466 <z_arm_fault+0x6a>
		} else if (SCB_UFSR != 0) {
200014aa:	4b0d      	ldr	r3, [pc, #52]	; (200014e0 <z_arm_fault+0xe4>)
200014ac:	8818      	ldrh	r0, [r3, #0]
200014ae:	b284      	uxth	r4, r0
200014b0:	2c00      	cmp	r4, #0
200014b2:	d0d9      	beq.n	20001468 <z_arm_fault+0x6c>
		reason = usage_fault(esf);
200014b4:	f7ff ff8c 	bl	200013d0 <usage_fault.isra.0>
200014b8:	e7d5      	b.n	20001466 <z_arm_fault+0x6a>
		reason = mem_manage_fault(esf, 0, recoverable);
200014ba:	2000      	movs	r0, #0
200014bc:	f10d 0107 	add.w	r1, sp, #7
200014c0:	e7cf      	b.n	20001462 <z_arm_fault+0x66>
		reason = bus_fault(esf, 0, recoverable);
200014c2:	2000      	movs	r0, #0
200014c4:	f10d 0107 	add.w	r1, sp, #7
200014c8:	e7ec      	b.n	200014a4 <z_arm_fault+0xa8>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
200014ca:	2400      	movs	r4, #0
200014cc:	e7cc      	b.n	20001468 <z_arm_fault+0x6c>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
200014ce:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
200014d2:	f023 0301 	bic.w	r3, r3, #1
200014d6:	e7d8      	b.n	2000148a <z_arm_fault+0x8e>
200014d8:	e000ed00 	.word	0xe000ed00
200014dc:	e000ed29 	.word	0xe000ed29
200014e0:	e000ed2a 	.word	0xe000ed2a

200014e4 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
200014e4:	4b04      	ldr	r3, [pc, #16]	; (200014f8 <z_arm_fault_init+0x14>)
200014e6:	695a      	ldr	r2, [r3, #20]
200014e8:	f042 0210 	orr.w	r2, r2, #16
200014ec:	615a      	str	r2, [r3, #20]
	 *
	 * For Non-Secure Firmware this could allow the Non-Secure Main
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
200014ee:	695a      	ldr	r2, [r3, #20]
200014f0:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
200014f4:	615a      	str	r2, [r3, #20]
#endif /* CONFIG_BUILTIN_STACK_GUARD */
}
200014f6:	4770      	bx	lr
200014f8:	e000ed00 	.word	0xe000ed00

200014fc <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
200014fc:	4b04      	ldr	r3, [pc, #16]	; (20001510 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
200014fe:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
20001500:	6a58      	ldr	r0, [r3, #36]	; 0x24
	cmp r0, r1
20001502:	4288      	cmp	r0, r1
	beq _EXIT_EXC
20001504:	d003      	beq.n	2000150e <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
20001506:	4903      	ldr	r1, [pc, #12]	; (20001514 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
20001508:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
2000150c:	600a      	str	r2, [r1, #0]

2000150e <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
2000150e:	4770      	bx	lr
	ldr r3, =_kernel
20001510:	20020874 	.word	0x20020874
	ldr r1, =_SCS_ICSR
20001514:	e000ed04 	.word	0xe000ed04

20001518 <sys_arch_reboot>:
  __ASM volatile ("dsb 0xF":::"memory");
20001518:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2000151c:	4905      	ldr	r1, [pc, #20]	; (20001534 <sys_arch_reboot+0x1c>)
2000151e:	4b06      	ldr	r3, [pc, #24]	; (20001538 <sys_arch_reboot+0x20>)
20001520:	68ca      	ldr	r2, [r1, #12]
20001522:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
20001526:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
20001528:	60cb      	str	r3, [r1, #12]
2000152a:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
2000152e:	bf00      	nop
  for(;;)                                                           /* wait until reset */
20001530:	e7fd      	b.n	2000152e <sys_arch_reboot+0x16>
20001532:	bf00      	nop
20001534:	e000ed00 	.word	0xe000ed00
20001538:	05fa0004 	.word	0x05fa0004

2000153c <z_arm_interrupt_init>:
 * @return N/A
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
2000153c:	2300      	movs	r3, #0
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2000153e:	2120      	movs	r1, #32
20001540:	4803      	ldr	r0, [pc, #12]	; (20001550 <z_arm_interrupt_init+0x14>)
20001542:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
20001544:	3301      	adds	r3, #1
20001546:	2b45      	cmp	r3, #69	; 0x45
20001548:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
2000154c:	d1f9      	bne.n	20001542 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
2000154e:	4770      	bx	lr
20001550:	e000e100 	.word	0xe000e100

20001554 <z_impl_k_thread_abort>:
#include <kswap.h>
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
20001554:	b510      	push	{r4, lr}
20001556:	4604      	mov	r4, r0
	z_thread_single_abort(thread);
20001558:	f001 faa2 	bl	20002aa0 <z_thread_single_abort>

	if (_current == thread) {
2000155c:	4b11      	ldr	r3, [pc, #68]	; (200015a4 <z_impl_k_thread_abort+0x50>)
2000155e:	689b      	ldr	r3, [r3, #8]
20001560:	42a3      	cmp	r3, r4
20001562:	d107      	bne.n	20001574 <z_impl_k_thread_abort+0x20>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
20001564:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
20001568:	b183      	cbz	r3, 2000158c <z_impl_k_thread_abort+0x38>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
2000156a:	4a0f      	ldr	r2, [pc, #60]	; (200015a8 <z_impl_k_thread_abort+0x54>)
2000156c:	6853      	ldr	r3, [r2, #4]
2000156e:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
20001572:	6053      	str	r3, [r2, #4]
	__asm__ volatile(
20001574:	f04f 0320 	mov.w	r3, #32
20001578:	f3ef 8011 	mrs	r0, BASEPRI
2000157c:	f383 8811 	msr	BASEPRI, r3
20001580:	f3bf 8f6f 	isb	sy
		}
	}

	/* The abort handler might have altered the ready queue. */
	z_reschedule_unlocked();
}
20001584:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	(void) z_pend_curr_irqlock(arch_irq_lock(), wait_q, timeout);
}

static inline void z_reschedule_unlocked(void)
{
	(void) z_reschedule_irqlock(arch_irq_lock());
20001588:	f002 bc14 	b.w	20003db4 <z_reschedule_irqlock>
2000158c:	f04f 0320 	mov.w	r3, #32
20001590:	f3ef 8011 	mrs	r0, BASEPRI
20001594:	f383 8811 	msr	BASEPRI, r3
20001598:	f3bf 8f6f 	isb	sy

static inline int z_swap_irqlock(unsigned int key)
{
	int ret;
	z_check_stack_sentinel();
	ret = arch_swap(key);
2000159c:	f7ff fd98 	bl	200010d0 <arch_swap>
	return ret;
200015a0:	e7e8      	b.n	20001574 <z_impl_k_thread_abort+0x20>
200015a2:	bf00      	nop
200015a4:	20020874 	.word	0x20020874
200015a8:	e000ed00 	.word	0xe000ed00

200015ac <z_arm_configure_static_mpu_regions>:
 *
 * For some MPU architectures, such as the unmodified ARMv8-M MPU,
 * the function must execute with MPU enabled.
 */
void z_arm_configure_static_mpu_regions(void)
{
200015ac:	b510      	push	{r4, lr}
		.size = (uint32_t)&_nocache_ram_size,
		.attr = K_MEM_PARTITION_P_RW_U_NA_NOCACHE,
		};
#endif /* CONFIG_NOCACHE_MEMORY */
#if defined(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT)
		const struct k_mem_partition ramfunc_region =
200015ae:	4b0e      	ldr	r3, [pc, #56]	; (200015e8 <z_arm_configure_static_mpu_regions+0x3c>)
{
200015b0:	b088      	sub	sp, #32
		const struct k_mem_partition ramfunc_region =
200015b2:	9302      	str	r3, [sp, #8]
200015b4:	4b0d      	ldr	r3, [pc, #52]	; (200015ec <z_arm_configure_static_mpu_regions+0x40>)
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
200015b6:	4c0e      	ldr	r4, [pc, #56]	; (200015f0 <z_arm_configure_static_mpu_regions+0x44>)
		const struct k_mem_partition ramfunc_region =
200015b8:	9303      	str	r3, [sp, #12]
200015ba:	4b0e      	ldr	r3, [pc, #56]	; (200015f4 <z_arm_configure_static_mpu_regions+0x48>)
	arm_core_mpu_configure_static_mpu_regions(static_regions,
200015bc:	4a0e      	ldr	r2, [pc, #56]	; (200015f8 <z_arm_configure_static_mpu_regions+0x4c>)
		const struct k_mem_partition ramfunc_region =
200015be:	9304      	str	r3, [sp, #16]
	const struct k_mem_partition *static_regions[] = {
200015c0:	ab02      	add	r3, sp, #8
200015c2:	9301      	str	r3, [sp, #4]
	arm_core_mpu_configure_static_mpu_regions(static_regions,
200015c4:	a801      	add	r0, sp, #4
200015c6:	4623      	mov	r3, r4
200015c8:	2101      	movs	r1, #1
200015ca:	f000 f907 	bl	200017dc <arm_core_mpu_configure_static_mpu_regions>
	/* Define a constant array of k_mem_partition objects that holds the
	 * boundaries of the areas, inside which dynamic region programming
	 * is allowed. The information is passed to the underlying driver at
	 * initialization.
	 */
	const struct k_mem_partition dyn_region_areas[] = {
200015ce:	2300      	movs	r3, #0
200015d0:	9307      	str	r3, [sp, #28]
		{
		.start = _MPU_DYNAMIC_REGIONS_AREA_START,
200015d2:	4b0a      	ldr	r3, [pc, #40]	; (200015fc <z_arm_configure_static_mpu_regions+0x50>)
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
		}
	};

	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
200015d4:	2101      	movs	r1, #1
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
200015d6:	1ae4      	subs	r4, r4, r3
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
200015d8:	a805      	add	r0, sp, #20
	const struct k_mem_partition dyn_region_areas[] = {
200015da:	9305      	str	r3, [sp, #20]
200015dc:	9406      	str	r4, [sp, #24]
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
200015de:	f000 f907 	bl	200017f0 <arm_core_mpu_mark_areas_for_dynamic_regions>
		ARRAY_SIZE(dyn_region_areas));
#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */
}
200015e2:	b008      	add	sp, #32
200015e4:	bd10      	pop	{r4, pc}
200015e6:	bf00      	nop
200015e8:	20020000 	.word	0x20020000
200015ec:	00000000 	.word	0x00000000
200015f0:	20030000 	.word	0x20030000
200015f4:	00010006 	.word	0x00010006
200015f8:	20020000 	.word	0x20020000
200015fc:	20020160 	.word	0x20020160

20001600 <region_init>:
 * Note:
 *   The caller must provide a valid region index.
 */
static void region_init(const uint32_t index,
	const struct arm_mpu_region *region_conf)
{
20001600:	b510      	push	{r4, lr}
	ARM_MPU_SetRegion(
		/* RNR */
		index,
		/* RBAR */
		(region_conf->base & MPU_RBAR_BASE_Msk)
20001602:	680b      	ldr	r3, [r1, #0]
		| (region_conf->attr.rbar &
20001604:	7a0c      	ldrb	r4, [r1, #8]
		(region_conf->base & MPU_RBAR_BASE_Msk)
20001606:	f023 021f 	bic.w	r2, r3, #31
		| (region_conf->attr.rbar &
2000160a:	f004 031f 	and.w	r3, r4, #31
2000160e:	431a      	orrs	r2, r3
			(MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)),
		/* RLAR */
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
20001610:	68cb      	ldr	r3, [r1, #12]
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
20001612:	0964      	lsrs	r4, r4, #5
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
20001614:	f023 031f 	bic.w	r3, r3, #31
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/   
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
  mpu->RNR = rnr;
20001618:	4904      	ldr	r1, [pc, #16]	; (2000162c <region_init+0x2c>)
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
2000161a:	ea43 0344 	orr.w	r3, r3, r4, lsl #1
			& MPU_RLAR_AttrIndx_Msk)
		| MPU_RLAR_EN_Msk
2000161e:	f043 0301 	orr.w	r3, r3, #1
20001622:	6088      	str	r0, [r1, #8]
  mpu->RBAR = rbar;
20001624:	60ca      	str	r2, [r1, #12]
  mpu->RLAR = rlar;
20001626:	610b      	str	r3, [r1, #16]
	);

	LOG_DBG("[%d] 0x%08x 0x%08x 0x%08x 0x%08x",
			index, region_conf->base, region_conf->attr.rbar,
			region_conf->attr.mair_idx, region_conf->attr.r_limit);
}
20001628:	bd10      	pop	{r4, pc}
2000162a:	bf00      	nop
2000162c:	e000ed90 	.word	0xe000ed90

20001630 <mpu_configure_regions_and_partition.constprop.0>:
 * sanity check of the memory regions to be programmed.
 *
 * The function performs a full partition of the background memory
 * area, effectively, leaving no space in this area uncovered by MPU.
 */
static int mpu_configure_regions_and_partition(const struct k_mem_partition
20001630:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
20001634:	4607      	mov	r7, r0
20001636:	4688      	mov	r8, r1
20001638:	4614      	mov	r4, r2
	bool do_sanity_check)
{
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
2000163a:	2600      	movs	r6, #0
	MPU->RNR = index;
2000163c:	4d4a      	ldr	r5, [pc, #296]	; (20001768 <mpu_configure_regions_and_partition.constprop.0+0x138>)
static int mpu_configure_regions_and_partition(const struct k_mem_partition
2000163e:	b085      	sub	sp, #20
	for (i = 0; i < regions_num; i++) {
20001640:	4546      	cmp	r6, r8
20001642:	da0b      	bge.n	2000165c <mpu_configure_regions_and_partition.constprop.0+0x2c>
		if (regions[i]->size == 0U) {
20001644:	f857 3026 	ldr.w	r3, [r7, r6, lsl #2]
20001648:	f8d3 9004 	ldr.w	r9, [r3, #4]
2000164c:	f1b9 0f00 	cmp.w	r9, #0
20001650:	d03a      	beq.n	200016c8 <mpu_configure_regions_and_partition.constprop.0+0x98>
		&&
20001652:	f1b9 0f1f 	cmp.w	r9, #31
20001656:	d805      	bhi.n	20001664 <mpu_configure_regions_and_partition.constprop.0+0x34>

			reg_index =
				mpu_configure_region(reg_index, regions[i]);

			if (reg_index == -EINVAL) {
				return reg_index;
20001658:	f06f 0415 	mvn.w	r4, #21
			reg_index++;
		}
	}

	return reg_index;
}
2000165c:	4620      	mov	r0, r4
2000165e:	b005      	add	sp, #20
20001660:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		&&
20001664:	f019 0f1f 	tst.w	r9, #31
20001668:	d1f6      	bne.n	20001658 <mpu_configure_regions_and_partition.constprop.0+0x28>
		((part->start &
2000166a:	f8d3 a000 	ldr.w	sl, [r3]
		&&
2000166e:	f01a 0f1f 	tst.w	sl, #31
20001672:	d1f1      	bne.n	20001658 <mpu_configure_regions_and_partition.constprop.0+0x28>
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
20001674:	4650      	mov	r0, sl
20001676:	f002 f9c4 	bl	20003a02 <arm_cmse_mpu_region_get>
2000167a:	4683      	mov	fp, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
2000167c:	eb09 000a 	add.w	r0, r9, sl
20001680:	3801      	subs	r0, #1
20001682:	f002 f9be 	bl	20003a02 <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
20001686:	4583      	cmp	fp, r0
20001688:	d1e6      	bne.n	20001658 <mpu_configure_regions_and_partition.constprop.0+0x28>
		if ((u_reg_index == -EINVAL) ||
2000168a:	f11b 0f16 	cmn.w	fp, #22
2000168e:	d0e3      	beq.n	20001658 <mpu_configure_regions_and_partition.constprop.0+0x28>
			(u_reg_index > (reg_index - 1))) {
20001690:	1e63      	subs	r3, r4, #1
		if ((u_reg_index == -EINVAL) ||
20001692:	455b      	cmp	r3, fp
20001694:	dbe0      	blt.n	20001658 <mpu_configure_regions_and_partition.constprop.0+0x28>
	MPU->RNR = index;
20001696:	f8c5 b008 	str.w	fp, [r5, #8]
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
2000169a:	68e8      	ldr	r0, [r5, #12]
	MPU->RNR = index;
2000169c:	f8c5 b008 	str.w	fp, [r5, #8]
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
200016a0:	692b      	ldr	r3, [r5, #16]
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
200016a2:	f857 1026 	ldr.w	r1, [r7, r6, lsl #2]
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
200016a6:	f020 001f 	bic.w	r0, r0, #31
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
200016aa:	f043 0a1f 	orr.w	sl, r3, #31
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
200016ae:	e9d1 3200 	ldrd	r3, r2, [r1]
200016b2:	441a      	add	r2, r3
		if ((regions[i]->start == u_reg_base) &&
200016b4:	4298      	cmp	r0, r3
		uint32_t reg_last = regions[i]->start + regions[i]->size - 1;
200016b6:	f102 39ff 	add.w	r9, r2, #4294967295
		if ((regions[i]->start == u_reg_base) &&
200016ba:	d118      	bne.n	200016ee <mpu_configure_regions_and_partition.constprop.0+0xbe>
200016bc:	45ca      	cmp	sl, r9
200016be:	d105      	bne.n	200016cc <mpu_configure_regions_and_partition.constprop.0+0x9c>
			mpu_configure_region(u_reg_index, regions[i]);
200016c0:	fa5f f08b 	uxtb.w	r0, fp
200016c4:	f002 f97d 	bl	200039c2 <mpu_configure_region>
	for (i = 0; i < regions_num; i++) {
200016c8:	3601      	adds	r6, #1
200016ca:	e7b9      	b.n	20001640 <mpu_configure_regions_and_partition.constprop.0+0x10>
	MPU->RNR = index;
200016cc:	f8c5 b008 	str.w	fp, [r5, #8]
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
200016d0:	68eb      	ldr	r3, [r5, #12]
		| (base & MPU_RBAR_BASE_Msk);
200016d2:	f022 021f 	bic.w	r2, r2, #31
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
200016d6:	f003 031f 	and.w	r3, r3, #31
		| (base & MPU_RBAR_BASE_Msk);
200016da:	431a      	orrs	r2, r3
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
200016dc:	60ea      	str	r2, [r5, #12]
				mpu_configure_region(reg_index, regions[i]);
200016de:	b2e0      	uxtb	r0, r4
				mpu_configure_region(reg_index, regions[i]);
200016e0:	f002 f96f 	bl	200039c2 <mpu_configure_region>
			if (reg_index == -EINVAL) {
200016e4:	f110 0f16 	cmn.w	r0, #22
200016e8:	d0b6      	beq.n	20001658 <mpu_configure_regions_and_partition.constprop.0+0x28>
			reg_index++;
200016ea:	1c44      	adds	r4, r0, #1
200016ec:	e7ec      	b.n	200016c8 <mpu_configure_regions_and_partition.constprop.0+0x98>
	MPU->RNR = index;
200016ee:	f8c5 b008 	str.w	fp, [r5, #8]
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
200016f2:	692a      	ldr	r2, [r5, #16]
200016f4:	3b01      	subs	r3, #1
200016f6:	f023 031f 	bic.w	r3, r3, #31
200016fa:	f002 021f 	and.w	r2, r2, #31
		| (limit & MPU_RLAR_LIMIT_Msk);
200016fe:	4313      	orrs	r3, r2
		} else if (reg_last == u_reg_last) {
20001700:	45ca      	cmp	sl, r9
20001702:	b2e0      	uxtb	r0, r4
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
20001704:	612b      	str	r3, [r5, #16]
		} else if (reg_last == u_reg_last) {
20001706:	d0eb      	beq.n	200016e0 <mpu_configure_regions_and_partition.constprop.0+0xb0>
				mpu_configure_region(reg_index, regions[i]);
20001708:	f002 f95b 	bl	200039c2 <mpu_configure_region>
			if (reg_index == -EINVAL) {
2000170c:	f110 0f16 	cmn.w	r0, #22
20001710:	d0a2      	beq.n	20001658 <mpu_configure_regions_and_partition.constprop.0+0x28>
	MPU->RNR = index;
20001712:	f8c5 b008 	str.w	fp, [r5, #8]
	attr->rbar = MPU->RBAR &
20001716:	68ea      	ldr	r2, [r5, #12]
20001718:	f89d 3008 	ldrb.w	r3, [sp, #8]
			REGION_LIMIT_ADDR((regions[i]->start +
2000171c:	f10a 3aff 	add.w	sl, sl, #4294967295
	attr->rbar = MPU->RBAR &
20001720:	f362 0304 	bfi	r3, r2, #0, #5
20001724:	f88d 3008 	strb.w	r3, [sp, #8]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
20001728:	692b      	ldr	r3, [r5, #16]
2000172a:	f89d 2008 	ldrb.w	r2, [sp, #8]
2000172e:	085b      	lsrs	r3, r3, #1
20001730:	f363 1247 	bfi	r2, r3, #5, #3
			fill_region.base = regions[i]->start +
20001734:	f857 3026 	ldr.w	r3, [r7, r6, lsl #2]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
20001738:	f88d 2008 	strb.w	r2, [sp, #8]
			fill_region.base = regions[i]->start +
2000173c:	e9d3 1300 	ldrd	r1, r3, [r3]
20001740:	440b      	add	r3, r1
20001742:	9300      	str	r3, [sp, #0]
			REGION_LIMIT_ADDR((regions[i]->start +
20001744:	f023 031f 	bic.w	r3, r3, #31
			reg_index++;
20001748:	3001      	adds	r0, #1
			REGION_LIMIT_ADDR((regions[i]->start +
2000174a:	4453      	add	r3, sl
2000174c:	eba3 0309 	sub.w	r3, r3, r9
20001750:	b2c0      	uxtb	r0, r0
20001752:	f023 031f 	bic.w	r3, r3, #31

static int region_allocate_and_init(const uint8_t index,
	const struct arm_mpu_region *region_conf)
{
	/* Attempt to allocate new region index. */
	if (index > (get_num_regions() - 1)) {
20001756:	280f      	cmp	r0, #15
			fill_region.attr.r_limit =
20001758:	9303      	str	r3, [sp, #12]
2000175a:	f63f af7d 	bhi.w	20001658 <mpu_configure_regions_and_partition.constprop.0+0x28>
	}

	LOG_DBG("Program MPU region at index 0x%x", index);

	/* Program region */
	region_init(index, region_conf);
2000175e:	4669      	mov	r1, sp
20001760:	f7ff ff4e 	bl	20001600 <region_init>
20001764:	e7c1      	b.n	200016ea <mpu_configure_regions_and_partition.constprop.0+0xba>
20001766:	bf00      	nop
20001768:	e000ed90 	.word	0xe000ed90

2000176c <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
2000176c:	2205      	movs	r2, #5
2000176e:	4b03      	ldr	r3, [pc, #12]	; (2000177c <arm_core_mpu_enable+0x10>)
20001770:	605a      	str	r2, [r3, #4]
  __ASM volatile ("dsb 0xF":::"memory");
20001772:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
20001776:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
2000177a:	4770      	bx	lr
2000177c:	e000ed90 	.word	0xe000ed90

20001780 <arm_core_mpu_disable>:
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
__STATIC_FORCEINLINE void __DMB(void)
{
  __ASM volatile ("dmb 0xF":::"memory");
20001780:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
20001784:	2200      	movs	r2, #0
20001786:	4b01      	ldr	r3, [pc, #4]	; (2000178c <arm_core_mpu_disable+0xc>)
20001788:	605a      	str	r2, [r3, #4]
}
2000178a:	4770      	bx	lr
2000178c:	e000ed90 	.word	0xe000ed90

20001790 <arm_mpu_init>:
 *
 * This function provides the default configuration mechanism for the Memory
 * Protection Unit (MPU).
 */
static int arm_mpu_init(const struct device *arg)
{
20001790:	b538      	push	{r3, r4, r5, lr}
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
20001792:	4c0e      	ldr	r4, [pc, #56]	; (200017cc <arm_mpu_init+0x3c>)
20001794:	6825      	ldr	r5, [r4, #0]
20001796:	2d10      	cmp	r5, #16
20001798:	d814      	bhi.n	200017c4 <arm_mpu_init+0x34>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
2000179a:	f7ff fff1 	bl	20001780 <arm_core_mpu_disable>

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
2000179e:	2000      	movs	r0, #0
	MPU->MAIR0 =
200017a0:	4b0b      	ldr	r3, [pc, #44]	; (200017d0 <arm_mpu_init+0x40>)
200017a2:	4a0c      	ldr	r2, [pc, #48]	; (200017d4 <arm_mpu_init+0x44>)
200017a4:	631a      	str	r2, [r3, #48]	; 0x30
200017a6:	4285      	cmp	r5, r0
200017a8:	d105      	bne.n	200017b6 <arm_mpu_init+0x26>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
200017aa:	4b0b      	ldr	r3, [pc, #44]	; (200017d8 <arm_mpu_init+0x48>)
200017ac:	701d      	strb	r5, [r3, #0]


	arm_core_mpu_enable();
200017ae:	f7ff ffdd 	bl	2000176c <arm_core_mpu_enable>
	__ASSERT(
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */
	return 0;
200017b2:	2000      	movs	r0, #0
}
200017b4:	bd38      	pop	{r3, r4, r5, pc}
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
200017b6:	6861      	ldr	r1, [r4, #4]
200017b8:	eb01 1100 	add.w	r1, r1, r0, lsl #4
200017bc:	f7ff ff20 	bl	20001600 <region_init>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
200017c0:	3001      	adds	r0, #1
200017c2:	e7f0      	b.n	200017a6 <arm_mpu_init+0x16>
		return -1;
200017c4:	f04f 30ff 	mov.w	r0, #4294967295
200017c8:	e7f4      	b.n	200017b4 <arm_mpu_init+0x24>
200017ca:	bf00      	nop
200017cc:	200042ac 	.word	0x200042ac
200017d0:	e000ed90 	.word	0xe000ed90
200017d4:	0044ffaa 	.word	0x0044ffaa
200017d8:	200208cc 	.word	0x200208cc

200017dc <arm_core_mpu_configure_static_mpu_regions>:
{
200017dc:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct k_mem_partition
	*static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
200017de:	4c03      	ldr	r4, [pc, #12]	; (200017ec <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * given boundaries.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions_and_partition(static_regions,
200017e0:	7822      	ldrb	r2, [r4, #0]
200017e2:	f7ff ff25 	bl	20001630 <mpu_configure_regions_and_partition.constprop.0>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
200017e6:	7020      	strb	r0, [r4, #0]
}
200017e8:	bd10      	pop	{r4, pc}
200017ea:	bf00      	nop
200017ec:	200208cc 	.word	0x200208cc

200017f0 <arm_core_mpu_mark_areas_for_dynamic_regions>:
{
200017f0:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
200017f4:	4d26      	ldr	r5, [pc, #152]	; (20001890 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa0>)
200017f6:	468a      	mov	sl, r1
{
	/* In ARMv8-M architecture we need to store the index values
	 * and the default configuration of the MPU regions, inside
	 * which dynamic memory regions may be programmed at run-time.
	 */
	for (int i = 0; i < dyn_region_areas_num; i++) {
200017f8:	4606      	mov	r6, r0
200017fa:	f04f 0800 	mov.w	r8, #0
200017fe:	46ab      	mov	fp, r5
	MPU->RNR = index;
20001800:	4f24      	ldr	r7, [pc, #144]	; (20001894 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa4>)
	for (int i = 0; i < dyn_region_areas_num; i++) {
20001802:	45d0      	cmp	r8, sl
20001804:	da1b      	bge.n	2000183e <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
		if (dyn_region_areas[i].size == 0U) {
20001806:	f8d6 9004 	ldr.w	r9, [r6, #4]
2000180a:	f1b9 0f00 	cmp.w	r9, #0
2000180e:	d039      	beq.n	20001884 <arm_core_mpu_mark_areas_for_dynamic_regions+0x94>
		}
		/* Non-empty area */

		/* Retrieve HW MPU region index */
		dyn_reg_info[i].index =
			get_region_index(dyn_region_areas[i].start,
20001810:	6831      	ldr	r1, [r6, #0]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
20001812:	4608      	mov	r0, r1
20001814:	9101      	str	r1, [sp, #4]
20001816:	f002 f8f4 	bl	20003a02 <arm_cmse_mpu_region_get>
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
2000181a:	9901      	ldr	r1, [sp, #4]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
2000181c:	4604      	mov	r4, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
2000181e:	eb09 0001 	add.w	r0, r9, r1
20001822:	3801      	subs	r0, #1
20001824:	f002 f8ed 	bl	20003a02 <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
20001828:	4284      	cmp	r4, r0
2000182a:	f04f 0214 	mov.w	r2, #20
2000182e:	4b1a      	ldr	r3, [pc, #104]	; (20001898 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa8>)
20001830:	d008      	beq.n	20001844 <arm_core_mpu_mark_areas_for_dynamic_regions+0x54>
		dyn_reg_info[i].index =
20001832:	f06f 0315 	mvn.w	r3, #21
20001836:	fb02 f808 	mul.w	r8, r2, r8
2000183a:	f84b 3008 	str.w	r3, [fp, r8]
}
2000183e:	b003      	add	sp, #12
20001840:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
					dyn_region_areas[i].size);

		if (dyn_reg_info[i].index == -EINVAL) {
20001844:	f114 0f16 	cmn.w	r4, #22
		dyn_reg_info[i].index =
20001848:	602c      	str	r4, [r5, #0]
		if (dyn_reg_info[i].index == -EINVAL) {
2000184a:	d0f8      	beq.n	2000183e <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>

			return -EINVAL;
		}

		if (dyn_reg_info[i].index >= static_regions_num) {
2000184c:	7819      	ldrb	r1, [r3, #0]
2000184e:	42a1      	cmp	r1, r4
20001850:	ddf5      	ble.n	2000183e <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
	attr->rbar = MPU->RBAR &
20001852:	fb02 b008 	mla	r0, r2, r8, fp
	MPU->RNR = index;
20001856:	60bc      	str	r4, [r7, #8]
	MPU->RNR = index;
20001858:	60bc      	str	r4, [r7, #8]
	attr->rbar = MPU->RBAR &
2000185a:	68fc      	ldr	r4, [r7, #12]
2000185c:	f100 0108 	add.w	r1, r0, #8
20001860:	7b00      	ldrb	r0, [r0, #12]
20001862:	f364 0004 	bfi	r0, r4, #0, #5
20001866:	7108      	strb	r0, [r1, #4]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
20001868:	6938      	ldr	r0, [r7, #16]
2000186a:	790c      	ldrb	r4, [r1, #4]
2000186c:	0840      	lsrs	r0, r0, #1
2000186e:	f360 1447 	bfi	r4, r0, #5, #3
20001872:	710c      	strb	r4, [r1, #4]
	region_conf->base = (MPU->RBAR & MPU_RBAR_BASE_Msk);
20001874:	68f9      	ldr	r1, [r7, #12]
20001876:	f021 011f 	bic.w	r1, r1, #31
2000187a:	6069      	str	r1, [r5, #4]
	region_conf->attr.r_limit = MPU->RLAR & MPU_RLAR_LIMIT_Msk;
2000187c:	6939      	ldr	r1, [r7, #16]
2000187e:	f021 011f 	bic.w	r1, r1, #31
20001882:	6129      	str	r1, [r5, #16]
	for (int i = 0; i < dyn_region_areas_num; i++) {
20001884:	f108 0801 	add.w	r8, r8, #1
20001888:	3514      	adds	r5, #20
2000188a:	360c      	adds	r6, #12
2000188c:	e7b9      	b.n	20001802 <arm_core_mpu_mark_areas_for_dynamic_regions+0x12>
2000188e:	bf00      	nop
20001890:	2002081c 	.word	0x2002081c
20001894:	e000ed90 	.word	0xe000ed90
20001898:	200208cc 	.word	0x200208cc

2000189c <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
2000189c:	4b01      	ldr	r3, [pc, #4]	; (200018a4 <__stdout_hook_install+0x8>)
2000189e:	6018      	str	r0, [r3, #0]
}
200018a0:	4770      	bx	lr
200018a2:	bf00      	nop
200018a4:	20020024 	.word	0x20020024

200018a8 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
200018a8:	b508      	push	{r3, lr}
	static bool gpio_initialized;

	if (!gpio_initialized) {
200018aa:	4b09      	ldr	r3, [pc, #36]	; (200018d0 <gpio_nrfx_init+0x28>)
200018ac:	781a      	ldrb	r2, [r3, #0]
200018ae:	b96a      	cbnz	r2, 200018cc <gpio_nrfx_init+0x24>
		gpio_initialized = true;
200018b0:	2101      	movs	r1, #1
		IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
200018b2:	200d      	movs	r0, #13
		gpio_initialized = true;
200018b4:	7019      	strb	r1, [r3, #0]
		IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
200018b6:	2105      	movs	r1, #5
200018b8:	f7ff fc7e 	bl	200011b8 <z_arm_irq_priority_set>
			    gpiote_event_handler, NULL, 0);

		irq_enable(DT_IRQN(GPIOTE_NODE));
200018bc:	200d      	movs	r0, #13
200018be:	f7ff fc5d 	bl	2000117c <arch_irq_enable>
    return ((uint32_t)p_reg + event);
}

NRF_STATIC_INLINE void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask)
{
    p_reg->INTENSET = mask;
200018c2:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
200018c6:	4b03      	ldr	r3, [pc, #12]	; (200018d4 <gpio_nrfx_init+0x2c>)
200018c8:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
		nrf_gpiote_int_enable(NRF_GPIOTE, NRF_GPIOTE_INT_PORT_MASK);
	}

	return 0;
}
200018cc:	2000      	movs	r0, #0
200018ce:	bd08      	pop	{r3, pc}
200018d0:	200208cd 	.word	0x200208cd
200018d4:	5000d000 	.word	0x5000d000

200018d8 <gpio_nrfx_config>:
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
200018d8:	4b2a      	ldr	r3, [pc, #168]	; (20001984 <gpio_nrfx_config+0xac>)
{
200018da:	b5f0      	push	{r4, r5, r6, r7, lr}
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
200018dc:	6844      	ldr	r4, [r0, #4]
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
200018de:	482a      	ldr	r0, [pc, #168]	; (20001988 <gpio_nrfx_config+0xb0>)
200018e0:	4013      	ands	r3, r2
200018e2:	4283      	cmp	r3, r0
200018e4:	d03f      	beq.n	20001966 <gpio_nrfx_config+0x8e>
200018e6:	d80d      	bhi.n	20001904 <gpio_nrfx_config+0x2c>
200018e8:	2b06      	cmp	r3, #6
200018ea:	d015      	beq.n	20001918 <gpio_nrfx_config+0x40>
200018ec:	d805      	bhi.n	200018fa <gpio_nrfx_config+0x22>
200018ee:	b19b      	cbz	r3, 20001918 <gpio_nrfx_config+0x40>
200018f0:	2b02      	cmp	r3, #2
200018f2:	d03a      	beq.n	2000196a <gpio_nrfx_config+0x92>
200018f4:	f06f 0015 	mvn.w	r0, #21
200018f8:	e034      	b.n	20001964 <gpio_nrfx_config+0x8c>
200018fa:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
200018fe:	d1f9      	bne.n	200018f4 <gpio_nrfx_config+0x1c>
		drive = NRF_GPIO_PIN_H0S1;
20001900:	2301      	movs	r3, #1
20001902:	e009      	b.n	20001918 <gpio_nrfx_config+0x40>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
20001904:	4821      	ldr	r0, [pc, #132]	; (2000198c <gpio_nrfx_config+0xb4>)
20001906:	4283      	cmp	r3, r0
20001908:	d031      	beq.n	2000196e <gpio_nrfx_config+0x96>
2000190a:	f5b3 0fa0 	cmp.w	r3, #5242880	; 0x500000
2000190e:	d030      	beq.n	20001972 <gpio_nrfx_config+0x9a>
20001910:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
20001914:	d1ee      	bne.n	200018f4 <gpio_nrfx_config+0x1c>
		drive = NRF_GPIO_PIN_S0H1;
20001916:	2302      	movs	r3, #2
	if ((flags & GPIO_PULL_UP) != 0) {
20001918:	06d0      	lsls	r0, r2, #27
		pull = NRF_GPIO_PIN_PULLUP;
2000191a:	bf4c      	ite	mi
2000191c:	2603      	movmi	r6, #3
		pull = NRF_GPIO_PIN_NOPULL;
2000191e:	f3c2 1640 	ubfxpl	r6, r2, #5, #1
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
20001922:	f482 7580 	eor.w	r5, r2, #256	; 0x100
	if ((flags & GPIO_OUTPUT) != 0) {
20001926:	0597      	lsls	r7, r2, #22
	dir = ((flags & GPIO_OUTPUT) != 0)
20001928:	f3c2 2040 	ubfx	r0, r2, #9, #1
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
2000192c:	f3c5 2500 	ubfx	r5, r5, #8, #1
	if ((flags & GPIO_OUTPUT) != 0) {
20001930:	d506      	bpl.n	20001940 <gpio_nrfx_config+0x68>
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
20001932:	f412 6f00 	tst.w	r2, #2048	; 0x800
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
20001936:	6867      	ldr	r7, [r4, #4]
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
20001938:	d01d      	beq.n	20001976 <gpio_nrfx_config+0x9e>
			nrf_gpio_port_out_set(reg, BIT(pin));
2000193a:	2201      	movs	r2, #1
2000193c:	408a      	lsls	r2, r1
    p_reg->OUTSET = set_mask;
2000193e:	60ba      	str	r2, [r7, #8]
    return pin_number >> 5;
20001940:	7a27      	ldrb	r7, [r4, #8]
        case 1: return NRF_P1;
20001942:	4a13      	ldr	r2, [pc, #76]	; (20001990 <gpio_nrfx_config+0xb8>)
20001944:	4c13      	ldr	r4, [pc, #76]	; (20001994 <gpio_nrfx_config+0xbc>)
    *p_pin = pin_number & 0x1F;
20001946:	f001 011f 	and.w	r1, r1, #31
        case 1: return NRF_P1;
2000194a:	2f01      	cmp	r7, #1
2000194c:	bf08      	it	eq
2000194e:	4614      	moveq	r4, r2
                               | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
20001950:	ea40 0245 	orr.w	r2, r0, r5, lsl #1
	return 0;
20001954:	2000      	movs	r0, #0
20001956:	ea42 2303 	orr.w	r3, r2, r3, lsl #8
2000195a:	ea43 0386 	orr.w	r3, r3, r6, lsl #2
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
2000195e:	3180      	adds	r1, #128	; 0x80
20001960:	f844 3021 	str.w	r3, [r4, r1, lsl #2]
}
20001964:	bdf0      	pop	{r4, r5, r6, r7, pc}
		drive = NRF_GPIO_PIN_H0D1;
20001966:	2307      	movs	r3, #7
20001968:	e7d6      	b.n	20001918 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_D0S1;
2000196a:	2304      	movs	r3, #4
2000196c:	e7d4      	b.n	20001918 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_D0H1;
2000196e:	2305      	movs	r3, #5
20001970:	e7d2      	b.n	20001918 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_H0H1;
20001972:	2303      	movs	r3, #3
20001974:	e7d0      	b.n	20001918 <gpio_nrfx_config+0x40>
		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
20001976:	0552      	lsls	r2, r2, #21
			nrf_gpio_port_out_clear(reg, BIT(pin));
20001978:	bf42      	ittt	mi
2000197a:	2201      	movmi	r2, #1
2000197c:	408a      	lslmi	r2, r1
    p_reg->OUTCLR = clr_mask;
2000197e:	60fa      	strmi	r2, [r7, #12]
}
20001980:	e7de      	b.n	20001940 <gpio_nrfx_config+0x68>
20001982:	bf00      	nop
20001984:	00f00006 	.word	0x00f00006
20001988:	00100006 	.word	0x00100006
2000198c:	00400002 	.word	0x00400002
20001990:	50842800 	.word	0x50842800
20001994:	50842500 	.word	0x50842500

20001998 <nrf_gpio_cfg_sense_set>:
{
20001998:	b510      	push	{r4, lr}
        case 1: return NRF_P1;
2000199a:	4b09      	ldr	r3, [pc, #36]	; (200019c0 <nrf_gpio_cfg_sense_set+0x28>)
2000199c:	4c09      	ldr	r4, [pc, #36]	; (200019c4 <nrf_gpio_cfg_sense_set+0x2c>)
    *p_pin = pin_number & 0x1F;
2000199e:	f000 021f 	and.w	r2, r0, #31
    return pin_number >> 5;
200019a2:	0940      	lsrs	r0, r0, #5
        case 1: return NRF_P1;
200019a4:	2801      	cmp	r0, #1
200019a6:	bf08      	it	eq
200019a8:	4623      	moveq	r3, r4
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
200019aa:	eb03 0382 	add.w	r3, r3, r2, lsl #2
200019ae:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
200019b2:	f422 3240 	bic.w	r2, r2, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
200019b6:	ea42 4201 	orr.w	r2, r2, r1, lsl #16
200019ba:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
}
200019be:	bd10      	pop	{r4, pc}
200019c0:	50842500 	.word	0x50842500
200019c4:	50842800 	.word	0x50842800

200019c8 <gpio_nrfx_pin_interrupt_configure>:
{
200019c8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
200019ca:	460d      	mov	r5, r1
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
200019cc:	6841      	ldr	r1, [r0, #4]
	struct gpio_nrfx_data *data = get_port_data(port);
200019ce:	68c7      	ldr	r7, [r0, #12]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
200019d0:	7a08      	ldrb	r0, [r1, #8]
200019d2:	f005 061f 	and.w	r6, r5, #31
	if ((mode == GPIO_INT_MODE_EDGE) &&
200019d6:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
200019da:	ea46 1640 	orr.w	r6, r6, r0, lsl #5
200019de:	d111      	bne.n	20001a04 <gpio_nrfx_pin_interrupt_configure+0x3c>
        case 1: return NRF_P1;
200019e0:	4c6b      	ldr	r4, [pc, #428]	; (20001b90 <gpio_nrfx_pin_interrupt_configure+0x1c8>)
200019e2:	f8df c1b8 	ldr.w	ip, [pc, #440]	; 20001b9c <gpio_nrfx_pin_interrupt_configure+0x1d4>
    return pin_number >> 5;
200019e6:	0970      	lsrs	r0, r6, #5
        case 1: return NRF_P1;
200019e8:	2801      	cmp	r0, #1
200019ea:	bf14      	ite	ne
200019ec:	4620      	movne	r0, r4
200019ee:	4660      	moveq	r0, ip
    *p_pin = pin_number & 0x1F;
200019f0:	f006 011f 	and.w	r1, r6, #31
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
200019f4:	3180      	adds	r1, #128	; 0x80
200019f6:	f850 1021 	ldr.w	r1, [r0, r1, lsl #2]
200019fa:	07cc      	lsls	r4, r1, #31
200019fc:	d507      	bpl.n	20001a0e <gpio_nrfx_pin_interrupt_configure+0x46>
		return -ENOTSUP;
200019fe:	f06f 0022 	mvn.w	r0, #34	; 0x22
20001a02:	e0b7      	b.n	20001b74 <gpio_nrfx_pin_interrupt_configure+0x1ac>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
20001a04:	f5b2 5f00 	cmp.w	r2, #8192	; 0x2000
20001a08:	68f9      	ldr	r1, [r7, #12]
20001a0a:	f000 80a4 	beq.w	20001b56 <gpio_nrfx_pin_interrupt_configure+0x18e>
20001a0e:	2101      	movs	r1, #1
20001a10:	68f8      	ldr	r0, [r7, #12]
20001a12:	40a9      	lsls	r1, r5
20001a14:	4301      	orrs	r1, r0
20001a16:	60f9      	str	r1, [r7, #12]
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
20001a18:	2101      	movs	r1, #1
20001a1a:	6978      	ldr	r0, [r7, #20]
20001a1c:	40a9      	lsls	r1, r5
20001a1e:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
20001a22:	69ba      	ldr	r2, [r7, #24]
20001a24:	bf0c      	ite	eq
20001a26:	4308      	orreq	r0, r1
20001a28:	4388      	bicne	r0, r1
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
20001a2a:	f5b3 2fc0 	cmp.w	r3, #393216	; 0x60000
20001a2e:	bf0c      	ite	eq
20001a30:	430a      	orreq	r2, r1
20001a32:	438a      	bicne	r2, r1
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
20001a34:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
20001a38:	f04f 0300 	mov.w	r3, #0
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
20001a3c:	61ba      	str	r2, [r7, #24]
20001a3e:	693a      	ldr	r2, [r7, #16]
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
20001a40:	6178      	str	r0, [r7, #20]
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
20001a42:	bf0c      	ite	eq
20001a44:	4311      	orreq	r1, r2
20001a46:	ea22 0101 	bicne.w	r1, r2, r1
    p_reg->INTENCLR = mask;
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask)
{
    return p_reg->INTENSET & mask;
20001a4a:	4a52      	ldr	r2, [pc, #328]	; (20001b94 <gpio_nrfx_pin_interrupt_configure+0x1cc>)
20001a4c:	6139      	str	r1, [r7, #16]
20001a4e:	f8d2 1304 	ldr.w	r1, [r2, #772]	; 0x304
20001a52:	b2c9      	uxtb	r1, r1
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
{
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
20001a54:	f503 70a2 	add.w	r0, r3, #324	; 0x144
20001a58:	f852 0020 	ldr.w	r0, [r2, r0, lsl #2]
20001a5c:	f3c0 2005 	ubfx	r0, r0, #8, #6
		if ((nrf_gpiote_event_pin_get(NRF_GPIOTE, i) == abs_pin)
20001a60:	4286      	cmp	r6, r0
20001a62:	d17d      	bne.n	20001b60 <gpio_nrfx_pin_interrupt_configure+0x198>
		    && (intenset & BIT(i))) {
20001a64:	fa21 f003 	lsr.w	r0, r1, r3
20001a68:	07c0      	lsls	r0, r0, #31
20001a6a:	d579      	bpl.n	20001b60 <gpio_nrfx_pin_interrupt_configure+0x198>
			(void)atomic_and(mask, ~BIT(i));
20001a6c:	2101      	movs	r1, #1
20001a6e:	4099      	lsls	r1, r3
20001a70:	43cc      	mvns	r4, r1
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
20001a72:	4849      	ldr	r0, [pc, #292]	; (20001b98 <gpio_nrfx_pin_interrupt_configure+0x1d0>)
20001a74:	e8d0 cfef 	ldaex	ip, [r0]
20001a78:	ea0c 0c04 	and.w	ip, ip, r4
20001a7c:	e8c0 cfee 	stlex	lr, ip, [r0]
20001a80:	f1be 0f00 	cmp.w	lr, #0
20001a84:	d1f6      	bne.n	20001a74 <gpio_nrfx_pin_interrupt_configure+0xac>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
20001a86:	009b      	lsls	r3, r3, #2
20001a88:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
20001a8c:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
20001a90:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
20001a94:	f020 0001 	bic.w	r0, r0, #1
20001a98:	f8c3 0510 	str.w	r0, [r3, #1296]	; 0x510
    p_reg->INTENCLR = mask;
20001a9c:	f8c2 1308 	str.w	r1, [r2, #776]	; 0x308
	nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
20001aa0:	2100      	movs	r1, #0
20001aa2:	4630      	mov	r0, r6
20001aa4:	f7ff ff78 	bl	20001998 <nrf_gpio_cfg_sense_set>
	if (data->pin_int_en & BIT(pin)) {
20001aa8:	68fb      	ldr	r3, [r7, #12]
20001aaa:	40eb      	lsrs	r3, r5
20001aac:	f013 0301 	ands.w	r3, r3, #1
20001ab0:	d04f      	beq.n	20001b52 <gpio_nrfx_pin_interrupt_configure+0x18a>
		if (data->trig_edge & BIT(pin)) {
20001ab2:	697b      	ldr	r3, [r7, #20]
20001ab4:	40eb      	lsrs	r3, r5
20001ab6:	f013 0401 	ands.w	r4, r3, #1
20001aba:	d05c      	beq.n	20001b76 <gpio_nrfx_pin_interrupt_configure+0x1ae>
			if (data->double_edge & BIT(pin)) {
20001abc:	69bb      	ldr	r3, [r7, #24]
				pol = NRF_GPIOTE_POLARITY_TOGGLE;
20001abe:	2200      	movs	r2, #0
			if (data->double_edge & BIT(pin)) {
20001ac0:	40eb      	lsrs	r3, r5
20001ac2:	07db      	lsls	r3, r3, #31
			} else if ((data->int_active_level & BIT(pin)) != 0U) {
20001ac4:	bf54      	ite	pl
20001ac6:	6939      	ldrpl	r1, [r7, #16]
				pol = NRF_GPIOTE_POLARITY_TOGGLE;
20001ac8:	2503      	movmi	r5, #3
		atomic_val_t prev = atomic_or(mask, BIT(channel));
20001aca:	f04f 0701 	mov.w	r7, #1
			} else if ((data->int_active_level & BIT(pin)) != 0U) {
20001ace:	bf5e      	ittt	pl
20001ad0:	fa21 f505 	lsrpl.w	r5, r1, r5
20001ad4:	f005 0501 	andpl.w	r5, r5, #1
20001ad8:	f1c5 0502 	rsbpl	r5, r5, #2
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
20001adc:	492e      	ldr	r1, [pc, #184]	; (20001b98 <gpio_nrfx_pin_interrupt_configure+0x1d0>)
20001ade:	bf58      	it	pl
20001ae0:	b2ed      	uxtbpl	r5, r5
		atomic_val_t prev = atomic_or(mask, BIT(channel));
20001ae2:	fa07 f402 	lsl.w	r4, r7, r2
20001ae6:	e8d1 0fef 	ldaex	r0, [r1]
20001aea:	ea40 0304 	orr.w	r3, r0, r4
20001aee:	e8c1 3fec 	stlex	ip, r3, [r1]
20001af2:	f1bc 0f00 	cmp.w	ip, #0
20001af6:	d1f6      	bne.n	20001ae6 <gpio_nrfx_pin_interrupt_configure+0x11e>
		if ((prev & BIT(channel)) == 0) {
20001af8:	40d0      	lsrs	r0, r2
20001afa:	f010 0301 	ands.w	r3, r0, #1
20001afe:	d134      	bne.n	20001b6a <gpio_nrfx_pin_interrupt_configure+0x1a2>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
20001b00:	0091      	lsls	r1, r2, #2
20001b02:	f101 41a0 	add.w	r1, r1, #1342177280	; 0x50000000
20001b06:	f501 4150 	add.w	r1, r1, #53248	; 0xd000
20001b0a:	f8d1 0510 	ldr.w	r0, [r1, #1296]	; 0x510
			nrf_gpiote_event_t evt =
20001b0e:	3240      	adds	r2, #64	; 0x40
20001b10:	f420 304f 	bic.w	r0, r0, #211968	; 0x33c00
20001b14:	f420 7040 	bic.w	r0, r0, #768	; 0x300
20001b18:	f8c1 0510 	str.w	r0, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
20001b1c:	0236      	lsls	r6, r6, #8
20001b1e:	0092      	lsls	r2, r2, #2
20001b20:	f8d1 0510 	ldr.w	r0, [r1, #1296]	; 0x510
20001b24:	f406 567c 	and.w	r6, r6, #16128	; 0x3f00
    return ((uint32_t)p_reg + event);
20001b28:	b292      	uxth	r2, r2
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
20001b2a:	ea46 4605 	orr.w	r6, r6, r5, lsl #16
    return ((uint32_t)p_reg + event);
20001b2e:	f102 42a0 	add.w	r2, r2, #1342177280	; 0x50000000
20001b32:	f502 4250 	add.w	r2, r2, #53248	; 0xd000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
20001b36:	4306      	orrs	r6, r0
20001b38:	f8c1 6510 	str.w	r6, [r1, #1296]	; 0x510
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
20001b3c:	6013      	str	r3, [r2, #0]
20001b3e:	6812      	ldr	r2, [r2, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
20001b40:	f8d1 2510 	ldr.w	r2, [r1, #1296]	; 0x510
20001b44:	f042 0201 	orr.w	r2, r2, #1
20001b48:	f8c1 2510 	str.w	r2, [r1, #1296]	; 0x510
    p_reg->INTENSET = mask;
20001b4c:	4a11      	ldr	r2, [pc, #68]	; (20001b94 <gpio_nrfx_pin_interrupt_configure+0x1cc>)
20001b4e:	f8c2 4304 	str.w	r4, [r2, #772]	; 0x304
	int res = 0;
20001b52:	4618      	mov	r0, r3
20001b54:	e00e      	b.n	20001b74 <gpio_nrfx_pin_interrupt_configure+0x1ac>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
20001b56:	2001      	movs	r0, #1
20001b58:	40a8      	lsls	r0, r5
20001b5a:	ea21 0100 	bic.w	r1, r1, r0
20001b5e:	e75a      	b.n	20001a16 <gpio_nrfx_pin_interrupt_configure+0x4e>
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
20001b60:	3301      	adds	r3, #1
20001b62:	2b08      	cmp	r3, #8
20001b64:	f47f af76 	bne.w	20001a54 <gpio_nrfx_pin_interrupt_configure+0x8c>
20001b68:	e79a      	b.n	20001aa0 <gpio_nrfx_pin_interrupt_configure+0xd8>
	for (uint8_t channel = 0; channel < GPIOTE_CH_NUM; ++channel) {
20001b6a:	3201      	adds	r2, #1
20001b6c:	2a08      	cmp	r2, #8
20001b6e:	d1b8      	bne.n	20001ae2 <gpio_nrfx_pin_interrupt_configure+0x11a>
	return -ENODEV;
20001b70:	f06f 0012 	mvn.w	r0, #18
}
20001b74:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	if ((BIT(pin) & data->int_active_level) != 0U) {
20001b76:	6939      	ldr	r1, [r7, #16]
			nrf_gpio_cfg_sense_set(abs_pin, sense);
20001b78:	4630      	mov	r0, r6
	if ((BIT(pin) & data->int_active_level) != 0U) {
20001b7a:	40e9      	lsrs	r1, r5
20001b7c:	f001 0101 	and.w	r1, r1, #1
20001b80:	f1c1 0103 	rsb	r1, r1, #3
			nrf_gpio_cfg_sense_set(abs_pin, sense);
20001b84:	b2c9      	uxtb	r1, r1
20001b86:	f7ff ff07 	bl	20001998 <nrf_gpio_cfg_sense_set>
	int res = 0;
20001b8a:	4620      	mov	r0, r4
20001b8c:	e7f2      	b.n	20001b74 <gpio_nrfx_pin_interrupt_configure+0x1ac>
20001b8e:	bf00      	nop
20001b90:	50842500 	.word	0x50842500
20001b94:	5000d000 	.word	0x5000d000
20001b98:	20020868 	.word	0x20020868
20001b9c:	50842800 	.word	0x50842800

20001ba0 <gpiote_event_handler>:
{
20001ba0:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
	uint32_t fired_triggers[GPIO_COUNT] = {0};
20001ba2:	2600      	movs	r6, #0
20001ba4:	e9cd 6600 	strd	r6, r6, [sp]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
20001ba8:	4d26      	ldr	r5, [pc, #152]	; (20001c44 <gpiote_event_handler+0xa4>)
20001baa:	682c      	ldr	r4, [r5, #0]
	if (port_event) {
20001bac:	b14c      	cbz	r4, 20001bc2 <gpiote_event_handler+0x22>
			check_level_trigger_pins(DEVICE_GET(gpio_nrfx_p0));
20001bae:	4826      	ldr	r0, [pc, #152]	; (20001c48 <gpiote_event_handler+0xa8>)
20001bb0:	f001 fff0 	bl	20003b94 <check_level_trigger_pins>
		fired_triggers[0] =
20001bb4:	9000      	str	r0, [sp, #0]
			check_level_trigger_pins(DEVICE_GET(gpio_nrfx_p1));
20001bb6:	4825      	ldr	r0, [pc, #148]	; (20001c4c <gpiote_event_handler+0xac>)
20001bb8:	f001 ffec 	bl	20003b94 <check_level_trigger_pins>
		fired_triggers[1] =
20001bbc:	9001      	str	r0, [sp, #4]
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
20001bbe:	602e      	str	r6, [r5, #0]
20001bc0:	682b      	ldr	r3, [r5, #0]
{
20001bc2:	2200      	movs	r2, #0
		if (nrf_gpiote_int_enable_check(NRF_GPIOTE, BIT(i)) &&
20001bc4:	2601      	movs	r6, #1
20001bc6:	4694      	mov	ip, r2
    return p_reg->INTENSET & mask;
20001bc8:	4d21      	ldr	r5, [pc, #132]	; (20001c50 <gpiote_event_handler+0xb0>)
20001bca:	f8d5 3304 	ldr.w	r3, [r5, #772]	; 0x304
20001bce:	fa06 f102 	lsl.w	r1, r6, r2
20001bd2:	4219      	tst	r1, r3
20001bd4:	d01b      	beq.n	20001c0e <gpiote_event_handler+0x6e>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
20001bd6:	0091      	lsls	r1, r2, #2
20001bd8:	f101 41a0 	add.w	r1, r1, #1342177280	; 0x50000000
20001bdc:	f501 4151 	add.w	r1, r1, #53504	; 0xd100
20001be0:	680b      	ldr	r3, [r1, #0]
20001be2:	b1a3      	cbz	r3, 20001c0e <gpiote_event_handler+0x6e>
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
20001be4:	f502 73a2 	add.w	r3, r2, #324	; 0x144
20001be8:	f855 3023 	ldr.w	r3, [r5, r3, lsl #2]
			fired_triggers[abs_pin / 32U] |= BIT(abs_pin % 32);
20001bec:	af02      	add	r7, sp, #8
20001bee:	f3c3 3040 	ubfx	r0, r3, #13, #1
20001bf2:	eb07 0080 	add.w	r0, r7, r0, lsl #2
20001bf6:	f850 7c08 	ldr.w	r7, [r0, #-8]
20001bfa:	f3c3 2304 	ubfx	r3, r3, #8, #5
20001bfe:	fa06 f303 	lsl.w	r3, r6, r3
20001c02:	433b      	orrs	r3, r7
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
20001c04:	f8c1 c000 	str.w	ip, [r1]
20001c08:	f840 3c08 	str.w	r3, [r0, #-8]
20001c0c:	680b      	ldr	r3, [r1, #0]
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
20001c0e:	3201      	adds	r2, #1
20001c10:	2a08      	cmp	r2, #8
20001c12:	d1da      	bne.n	20001bca <gpiote_event_handler+0x2a>
	if (fired_triggers[0]) {
20001c14:	9a00      	ldr	r2, [sp, #0]
20001c16:	b11a      	cbz	r2, 20001c20 <gpiote_event_handler+0x80>
	gpio_fire_callbacks(list, port, pins);
20001c18:	490b      	ldr	r1, [pc, #44]	; (20001c48 <gpiote_event_handler+0xa8>)
20001c1a:	480e      	ldr	r0, [pc, #56]	; (20001c54 <gpiote_event_handler+0xb4>)
20001c1c:	f001 ff57 	bl	20003ace <gpio_fire_callbacks>
	if (fired_triggers[1]) {
20001c20:	9a01      	ldr	r2, [sp, #4]
20001c22:	b11a      	cbz	r2, 20001c2c <gpiote_event_handler+0x8c>
	gpio_fire_callbacks(list, port, pins);
20001c24:	4909      	ldr	r1, [pc, #36]	; (20001c4c <gpiote_event_handler+0xac>)
20001c26:	480c      	ldr	r0, [pc, #48]	; (20001c58 <gpiote_event_handler+0xb8>)
20001c28:	f001 ff51 	bl	20003ace <gpio_fire_callbacks>
	if (port_event) {
20001c2c:	b144      	cbz	r4, 20001c40 <gpiote_event_handler+0xa0>
		cfg_level_pins(DEVICE_GET(gpio_nrfx_p0));
20001c2e:	4806      	ldr	r0, [pc, #24]	; (20001c48 <gpiote_event_handler+0xa8>)
20001c30:	f001 ffd8 	bl	20003be4 <cfg_level_pins>
		cfg_level_pins(DEVICE_GET(gpio_nrfx_p1));
20001c34:	4805      	ldr	r0, [pc, #20]	; (20001c4c <gpiote_event_handler+0xac>)
}
20001c36:	b003      	add	sp, #12
20001c38:	e8bd 40f0 	ldmia.w	sp!, {r4, r5, r6, r7, lr}
		cfg_level_pins(DEVICE_GET(gpio_nrfx_p1));
20001c3c:	f001 bfd2 	b.w	20003be4 <cfg_level_pins>
}
20001c40:	b003      	add	sp, #12
20001c42:	bdf0      	pop	{r4, r5, r6, r7, pc}
20001c44:	5000d17c 	.word	0x5000d17c
20001c48:	200200d8 	.word	0x200200d8
20001c4c:	200200e8 	.word	0x200200e8
20001c50:	5000d000 	.word	0x5000d000
20001c54:	20020834 	.word	0x20020834
20001c58:	20020850 	.word	0x20020850

20001c5c <uarte_nrfx_configure>:
	return 0;
}

static int uarte_nrfx_configure(const struct device *dev,
				const struct uart_config *cfg)
{
20001c5c:	b5f0      	push	{r4, r5, r6, r7, lr}
	nrf_uarte_config_t uarte_cfg;

#if defined(UARTE_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
20001c5e:	794b      	ldrb	r3, [r1, #5]
20001c60:	2b01      	cmp	r3, #1
20001c62:	d02b      	beq.n	20001cbc <uarte_nrfx_configure+0x60>
20001c64:	2b03      	cmp	r3, #3
20001c66:	d126      	bne.n	20001cb6 <uarte_nrfx_configure+0x5a>
	case UART_CFG_STOP_BITS_1:
		uarte_cfg.stop = NRF_UARTE_STOP_ONE;
		break;
	case UART_CFG_STOP_BITS_2:
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
20001c68:	2710      	movs	r7, #16
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
20001c6a:	798b      	ldrb	r3, [r1, #6]
20001c6c:	2b03      	cmp	r3, #3
20001c6e:	d122      	bne.n	20001cb6 <uarte_nrfx_configure+0x5a>
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
20001c70:	79cd      	ldrb	r5, [r1, #7]
20001c72:	b125      	cbz	r5, 20001c7e <uarte_nrfx_configure+0x22>
20001c74:	2d01      	cmp	r5, #1
20001c76:	d11e      	bne.n	20001cb6 <uarte_nrfx_configure+0x5a>
	case UART_CFG_FLOW_CTRL_NONE:
		uarte_cfg.hwfc = NRF_UARTE_HWFC_DISABLED;
		break;
	case UART_CFG_FLOW_CTRL_RTS_CTS:
		if (get_dev_config(dev)->rts_cts_pins_set) {
20001c78:	6843      	ldr	r3, [r0, #4]
20001c7a:	791b      	ldrb	r3, [r3, #4]
20001c7c:	b1db      	cbz	r3, 20001cb6 <uarte_nrfx_configure+0x5a>
	}

#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
20001c7e:	790a      	ldrb	r2, [r1, #4]
20001c80:	2a01      	cmp	r2, #1
20001c82:	d01d      	beq.n	20001cc0 <uarte_nrfx_configure+0x64>
20001c84:	2a02      	cmp	r2, #2
20001c86:	d01f      	beq.n	20001cc8 <uarte_nrfx_configure+0x6c>
20001c88:	b9aa      	cbnz	r2, 20001cb6 <uarte_nrfx_configure+0x5a>
20001c8a:	4614      	mov	r4, r2
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
20001c8c:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
20001c8e:	6846      	ldr	r6, [r0, #4]
	switch (baudrate) {
20001c90:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
20001c94:	6836      	ldr	r6, [r6, #0]
	switch (baudrate) {
20001c96:	d06e      	beq.n	20001d76 <uarte_nrfx_configure+0x11a>
20001c98:	d833      	bhi.n	20001d02 <uarte_nrfx_configure+0xa6>
20001c9a:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
20001c9e:	d06d      	beq.n	20001d7c <uarte_nrfx_configure+0x120>
20001ca0:	d81c      	bhi.n	20001cdc <uarte_nrfx_configure+0x80>
20001ca2:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
20001ca6:	d06b      	beq.n	20001d80 <uarte_nrfx_configure+0x124>
20001ca8:	d810      	bhi.n	20001ccc <uarte_nrfx_configure+0x70>
20001caa:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
20001cae:	d06a      	beq.n	20001d86 <uarte_nrfx_configure+0x12a>
20001cb0:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
20001cb4:	d06a      	beq.n	20001d8c <uarte_nrfx_configure+0x130>
20001cb6:	f06f 0022 	mvn.w	r0, #34	; 0x22
20001cba:	e05b      	b.n	20001d74 <uarte_nrfx_configure+0x118>
	switch (cfg->stop_bits) {
20001cbc:	2700      	movs	r7, #0
20001cbe:	e7d4      	b.n	20001c6a <uarte_nrfx_configure+0xe>
		uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_ODD;
20001cc0:	f44f 7480 	mov.w	r4, #256	; 0x100
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
20001cc4:	220e      	movs	r2, #14
20001cc6:	e7e1      	b.n	20001c8c <uarte_nrfx_configure+0x30>
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
20001cc8:	2400      	movs	r4, #0
20001cca:	e7fb      	b.n	20001cc4 <uarte_nrfx_configure+0x68>
	switch (baudrate) {
20001ccc:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
20001cd0:	d05f      	beq.n	20001d92 <uarte_nrfx_configure+0x136>
20001cd2:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
20001cd6:	d1ee      	bne.n	20001cb6 <uarte_nrfx_configure+0x5a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
20001cd8:	4b38      	ldr	r3, [pc, #224]	; (20001dbc <uarte_nrfx_configure+0x160>)
20001cda:	e03e      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
	switch (baudrate) {
20001cdc:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
20001ce0:	d05a      	beq.n	20001d98 <uarte_nrfx_configure+0x13c>
20001ce2:	d807      	bhi.n	20001cf4 <uarte_nrfx_configure+0x98>
20001ce4:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
20001ce8:	d058      	beq.n	20001d9c <uarte_nrfx_configure+0x140>
20001cea:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
20001cee:	d1e2      	bne.n	20001cb6 <uarte_nrfx_configure+0x5a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
20001cf0:	4b33      	ldr	r3, [pc, #204]	; (20001dc0 <uarte_nrfx_configure+0x164>)
20001cf2:	e032      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
	switch (baudrate) {
20001cf4:	f647 2c12 	movw	ip, #31250	; 0x7a12
20001cf8:	4563      	cmp	r3, ip
20001cfa:	d1dc      	bne.n	20001cb6 <uarte_nrfx_configure+0x5a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
20001cfc:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
20001d00:	e02b      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
	switch (baudrate) {
20001d02:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
20001d06:	d04b      	beq.n	20001da0 <uarte_nrfx_configure+0x144>
20001d08:	d813      	bhi.n	20001d32 <uarte_nrfx_configure+0xd6>
20001d0a:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
20001d0e:	d04a      	beq.n	20001da6 <uarte_nrfx_configure+0x14a>
20001d10:	d809      	bhi.n	20001d26 <uarte_nrfx_configure+0xca>
20001d12:	f64d 2cc0 	movw	ip, #56000	; 0xdac0
20001d16:	4563      	cmp	r3, ip
20001d18:	d047      	beq.n	20001daa <uarte_nrfx_configure+0x14e>
20001d1a:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
20001d1e:	d1ca      	bne.n	20001cb6 <uarte_nrfx_configure+0x5a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
20001d20:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
20001d24:	e019      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
	switch (baudrate) {
20001d26:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
20001d2a:	d1c4      	bne.n	20001cb6 <uarte_nrfx_configure+0x5a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
20001d2c:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
20001d30:	e013      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
	switch (baudrate) {
20001d32:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
20001d36:	d03b      	beq.n	20001db0 <uarte_nrfx_configure+0x154>
20001d38:	d809      	bhi.n	20001d4e <uarte_nrfx_configure+0xf2>
20001d3a:	f8df c098 	ldr.w	ip, [pc, #152]	; 20001dd4 <uarte_nrfx_configure+0x178>
20001d3e:	4563      	cmp	r3, ip
20001d40:	d039      	beq.n	20001db6 <uarte_nrfx_configure+0x15a>
20001d42:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
20001d46:	d1b6      	bne.n	20001cb6 <uarte_nrfx_configure+0x5a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
20001d48:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
20001d4c:	e005      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
	switch (baudrate) {
20001d4e:	f8df c088 	ldr.w	ip, [pc, #136]	; 20001dd8 <uarte_nrfx_configure+0x17c>
20001d52:	4563      	cmp	r3, ip
20001d54:	d1af      	bne.n	20001cb6 <uarte_nrfx_configure+0x5a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
20001d56:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
20001d5a:	f8c6 3524 	str.w	r3, [r6, #1316]	; 0x524
		return -ENOTSUP;
	}

	nrf_uarte_configure(get_uarte_instance(dev), &uarte_cfg);

	get_dev_data(dev)->uart_config = *cfg;
20001d5e:	68c3      	ldr	r3, [r0, #12]
                    | (uint32_t)p_cfg->hwfc;
20001d60:	432c      	orrs	r4, r5
                    | (uint32_t)p_cfg->stop
20001d62:	433a      	orrs	r2, r7
                    | (uint32_t)p_cfg->hwfc;
20001d64:	4322      	orrs	r2, r4
20001d66:	3304      	adds	r3, #4
20001d68:	c903      	ldmia	r1, {r0, r1}
    p_reg->CONFIG = (uint32_t)p_cfg->parity
20001d6a:	f8c6 256c 	str.w	r2, [r6, #1388]	; 0x56c
20001d6e:	e883 0003 	stmia.w	r3, {r0, r1}

	return 0;
20001d72:	2000      	movs	r0, #0
}
20001d74:	bdf0      	pop	{r4, r5, r6, r7, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
20001d76:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
20001d7a:	e7ee      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
20001d7c:	4b11      	ldr	r3, [pc, #68]	; (20001dc4 <uarte_nrfx_configure+0x168>)
20001d7e:	e7ec      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
20001d80:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
20001d84:	e7e9      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
		nrf_baudrate = 0x00014000;
20001d86:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
20001d8a:	e7e6      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
	switch (baudrate) {
20001d8c:	f44f 331c 	mov.w	r3, #159744	; 0x27000
20001d90:	e7e3      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
20001d92:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
20001d96:	e7e0      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
20001d98:	4b0b      	ldr	r3, [pc, #44]	; (20001dc8 <uarte_nrfx_configure+0x16c>)
20001d9a:	e7de      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
20001d9c:	4b0b      	ldr	r3, [pc, #44]	; (20001dcc <uarte_nrfx_configure+0x170>)
20001d9e:	e7dc      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
20001da0:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
20001da4:	e7d9      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
20001da6:	4b0a      	ldr	r3, [pc, #40]	; (20001dd0 <uarte_nrfx_configure+0x174>)
20001da8:	e7d7      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
20001daa:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
20001dae:	e7d4      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
20001db0:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
20001db4:	e7d1      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
20001db6:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
20001dba:	e7ce      	b.n	20001d5a <uarte_nrfx_configure+0xfe>
20001dbc:	0013b000 	.word	0x0013b000
20001dc0:	004ea000 	.word	0x004ea000
20001dc4:	00275000 	.word	0x00275000
20001dc8:	0075c000 	.word	0x0075c000
20001dcc:	003af000 	.word	0x003af000
20001dd0:	013a9000 	.word	0x013a9000
20001dd4:	0003d090 	.word	0x0003d090
20001dd8:	000f4240 	.word	0x000f4240

20001ddc <nrf_gpio_cfg_output>:
        case 1: return NRF_P1;
20001ddc:	4b07      	ldr	r3, [pc, #28]	; (20001dfc <nrf_gpio_cfg_output+0x20>)
20001dde:	4908      	ldr	r1, [pc, #32]	; (20001e00 <nrf_gpio_cfg_output+0x24>)
    *p_pin = pin_number & 0x1F;
20001de0:	f000 021f 	and.w	r2, r0, #31
    return pin_number >> 5;
20001de4:	0940      	lsrs	r0, r0, #5
        case 1: return NRF_P1;
20001de6:	2801      	cmp	r0, #1
20001de8:	bf14      	ite	ne
20001dea:	4618      	movne	r0, r3
20001dec:	4608      	moveq	r0, r1
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
20001dee:	f102 0380 	add.w	r3, r2, #128	; 0x80
20001df2:	2203      	movs	r2, #3
20001df4:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
}
20001df8:	4770      	bx	lr
20001dfa:	bf00      	nop
20001dfc:	50842500 	.word	0x50842500
20001e00:	50842800 	.word	0x50842800

20001e04 <nrf_gpio_pin_set>:
        case 1: return NRF_P1;
20001e04:	4b06      	ldr	r3, [pc, #24]	; (20001e20 <nrf_gpio_pin_set+0x1c>)
20001e06:	4907      	ldr	r1, [pc, #28]	; (20001e24 <nrf_gpio_pin_set+0x20>)
    *p_pin = pin_number & 0x1F;
20001e08:	f000 021f 	and.w	r2, r0, #31
    return pin_number >> 5;
20001e0c:	0940      	lsrs	r0, r0, #5
        case 1: return NRF_P1;
20001e0e:	2801      	cmp	r0, #1
20001e10:	bf14      	ite	ne
20001e12:	4618      	movne	r0, r3
20001e14:	4608      	moveq	r0, r1
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
20001e16:	2301      	movs	r3, #1
20001e18:	4093      	lsls	r3, r2
    p_reg->OUTSET = set_mask;
20001e1a:	6083      	str	r3, [r0, #8]
}
20001e1c:	4770      	bx	lr
20001e1e:	bf00      	nop
20001e20:	50842500 	.word	0x50842500
20001e24:	50842800 	.word	0x50842800

20001e28 <uarte_0_init>:
				.tx_buffer = uarte##idx##_tx_buffer,	       \
				.tx_buff_size = sizeof(uarte##idx##_tx_buffer),\
			};))

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
20001e28:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
20001e2a:	2700      	movs	r7, #0
	return config->uarte_regs;
20001e2c:	6843      	ldr	r3, [r0, #4]
	struct uarte_nrfx_data *data = get_dev_data(dev);
20001e2e:	68c6      	ldr	r6, [r0, #12]
	return config->uarte_regs;
20001e30:	681c      	ldr	r4, [r3, #0]
UART_NRF_UARTE_DEVICE(0);
20001e32:	4605      	mov	r5, r0
20001e34:	f8c4 7500 	str.w	r7, [r4, #1280]	; 0x500
	data->dev = dev;
20001e38:	6030      	str	r0, [r6, #0]
        nrf_gpio_pin_set(pin_number);
20001e3a:	2014      	movs	r0, #20
20001e3c:	f7ff ffe2 	bl	20001e04 <nrf_gpio_pin_set>
	nrf_gpio_cfg_output(config->pseltxd);
20001e40:	2014      	movs	r0, #20
20001e42:	f7ff ffcb 	bl	20001ddc <nrf_gpio_cfg_output>
    p_reg->PSEL.TXD = pseltxd;
20001e46:	2214      	movs	r2, #20
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
20001e48:	4b15      	ldr	r3, [pc, #84]	; (20001ea0 <uarte_0_init+0x78>)
        nrf_gpio_pin_set(pin_number);
20001e4a:	2013      	movs	r0, #19
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
20001e4c:	f8c3 7258 	str.w	r7, [r3, #600]	; 0x258
20001e50:	f8c4 250c 	str.w	r2, [r4, #1292]	; 0x50c
    p_reg->PSEL.RXD = pselrxd;
20001e54:	2216      	movs	r2, #22
20001e56:	f8c4 2514 	str.w	r2, [r4, #1300]	; 0x514
20001e5a:	f8c3 7254 	str.w	r7, [r3, #596]	; 0x254
        nrf_gpio_pin_set(pin_number);
20001e5e:	f7ff ffd1 	bl	20001e04 <nrf_gpio_pin_set>
		nrf_gpio_cfg_output(config->pselrts);
20001e62:	2013      	movs	r0, #19
20001e64:	f7ff ffba 	bl	20001ddc <nrf_gpio_cfg_output>
    p_reg->PSEL.RTS = pselrts;
20001e68:	2313      	movs	r3, #19
20001e6a:	f8c4 3508 	str.w	r3, [r4, #1288]	; 0x508
    p_reg->PSEL.CTS = pselcts;
20001e6e:	2315      	movs	r3, #21
	err = uarte_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
20001e70:	68e9      	ldr	r1, [r5, #12]
20001e72:	4628      	mov	r0, r5
20001e74:	f8c4 3510 	str.w	r3, [r4, #1296]	; 0x510
20001e78:	3104      	adds	r1, #4
20001e7a:	f7ff feef 	bl	20001c5c <uarte_nrfx_configure>
	if (err) {
20001e7e:	b968      	cbnz	r0, 20001e9c <uarte_0_init+0x74>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
20001e80:	2308      	movs	r3, #8
20001e82:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
20001e86:	f8c4 0110 	str.w	r0, [r4, #272]	; 0x110
20001e8a:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110
NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    p_reg->RXD.MAXCNT = length;
20001e8e:	2301      	movs	r3, #1
		nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
20001e90:	3610      	adds	r6, #16
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
20001e92:	f8c4 6534 	str.w	r6, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
20001e96:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
20001e9a:	6023      	str	r3, [r4, #0]
UART_NRF_UARTE_DEVICE(0);
20001e9c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
20001e9e:	bf00      	nop
20001ea0:	50842500 	.word	0x50842500

20001ea4 <nrf53_errata_42>:
        return false;
    #else
        #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
            #if defined(NRF_APPLICATION)
                uint32_t var1 = *(uint32_t *)0x00FF0130ul;
                uint32_t var2 = *(uint32_t *)0x00FF0134ul;
20001ea4:	4b05      	ldr	r3, [pc, #20]	; (20001ebc <nrf53_errata_42+0x18>)
20001ea6:	6818      	ldr	r0, [r3, #0]
                uint32_t var1 = *(uint32_t *)0x00FF0130ul;
20001ea8:	3b04      	subs	r3, #4
            #endif
        #endif
        #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
            #if defined (NRF_APPLICATION)
                if (var1 == 0x07)
20001eaa:	681b      	ldr	r3, [r3, #0]
20001eac:	2b07      	cmp	r3, #7
20001eae:	d103      	bne.n	20001eb8 <nrf53_errata_42+0x14>
                {
                    switch(var2)
20001eb0:	1e83      	subs	r3, r0, #2
20001eb2:	4258      	negs	r0, r3
20001eb4:	4158      	adcs	r0, r3
20001eb6:	4770      	bx	lr
                            return false;
                    }
                }
            #endif
        #endif
        return false;
20001eb8:	2000      	movs	r0, #0
    #endif
}
20001eba:	4770      	bx	lr
20001ebc:	00ff0134 	.word	0x00ff0134

20001ec0 <SystemCoreClockUpdate>:
void SystemCoreClockUpdate(void)
{
#if defined(NRF_TRUSTZONE_NONSECURE)
    SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_NS->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
#else
    SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_S->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
20001ec0:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20001ec4:	f8d3 2558 	ldr.w	r2, [r3, #1368]	; 0x558
20001ec8:	4b03      	ldr	r3, [pc, #12]	; (20001ed8 <SystemCoreClockUpdate+0x18>)
20001eca:	f002 0203 	and.w	r2, r2, #3
20001ece:	40d3      	lsrs	r3, r2
20001ed0:	4a02      	ldr	r2, [pc, #8]	; (20001edc <SystemCoreClockUpdate+0x1c>)
20001ed2:	6013      	str	r3, [r2, #0]
#endif
}
20001ed4:	4770      	bx	lr
20001ed6:	bf00      	nop
20001ed8:	07a12000 	.word	0x07a12000
20001edc:	2002003c 	.word	0x2002003c

20001ee0 <SystemInit>:

void SystemInit(void)
{
20001ee0:	b508      	push	{r3, lr}
          SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
        #endif

        /* Workaround for Errata 97 "ERASEPROTECT, APPROTECT, or startup problems" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_97())
20001ee2:	f7ff ffdf 	bl	20001ea4 <nrf53_errata_42>
20001ee6:	b148      	cbz	r0, 20001efc <SystemInit+0x1c>
        {
            if (*((volatile uint32_t *)0x50004A20ul) == 0)
20001ee8:	4b30      	ldr	r3, [pc, #192]	; (20001fac <SystemInit+0xcc>)
20001eea:	681a      	ldr	r2, [r3, #0]
20001eec:	b932      	cbnz	r2, 20001efc <SystemInit+0x1c>
            {
                *((volatile uint32_t *)0x50004A20ul) = 0xDul;
20001eee:	210d      	movs	r1, #13
20001ef0:	6019      	str	r1, [r3, #0]
                *((volatile uint32_t *)0x5000491Cul) = 0x1ul;
20001ef2:	2101      	movs	r1, #1
20001ef4:	f5a3 7382 	sub.w	r3, r3, #260	; 0x104
20001ef8:	6019      	str	r1, [r3, #0]
                *((volatile uint32_t *)0x5000491Cul) = 0x0ul;
20001efa:	601a      	str	r2, [r3, #0]
{
20001efc:	2200      	movs	r2, #0
20001efe:	00d3      	lsls	r3, r2, #3
20001f00:	f503 037f 	add.w	r3, r3, #16711680	; 0xff0000
        }

        /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
         until one ADDR is not initialized. */
        uint32_t index = 0;
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
20001f04:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
20001f08:	3101      	adds	r1, #1
20001f0a:	d007      	beq.n	20001f1c <SystemInit+0x3c>
            #if defined ( __ICCARM__ )
                /* IAR will complain about the order of volatile pointer accesses. */
                #pragma diag_suppress=Pa082
            #endif
            *NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
20001f0c:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
20001f10:	3201      	adds	r2, #1
            *NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
20001f12:	f8d3 3304 	ldr.w	r3, [r3, #772]	; 0x304
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
20001f16:	2a20      	cmp	r2, #32
            *NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
20001f18:	600b      	str	r3, [r1, #0]
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
20001f1a:	d1f0      	bne.n	20001efe <SystemInit+0x1e>
        }

        /* errata 64 must be before errata 42, as errata 42 is dependant on the changes in errata 64*/
        /* Workaround for Errata 64 "VREGMAIN has invalid configuration when CPU is running at 128 MHz" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_64())
20001f1c:	f7ff ffc2 	bl	20001ea4 <nrf53_errata_42>
20001f20:	2800      	cmp	r0, #0
20001f22:	d13c      	bne.n	20001f9e <SystemInit+0xbe>
            *((volatile uint32_t *)0x5000473Cul) = 0x3ul;
        }

        /* Workaround for Errata 42 "Reset value of HFCLKCTRL is invalid" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_42())
20001f24:	f7ff ffbe 	bl	20001ea4 <nrf53_errata_42>
20001f28:	b138      	cbz	r0, 20001f3a <SystemInit+0x5a>
        {
            *((volatile uint32_t *)0x50039530ul) = 0xBEEF0044ul;
20001f2a:	4b21      	ldr	r3, [pc, #132]	; (20001fb0 <SystemInit+0xd0>)
20001f2c:	4a21      	ldr	r2, [pc, #132]	; (20001fb4 <SystemInit+0xd4>)
20001f2e:	601a      	str	r2, [r3, #0]
            NRF_CLOCK_S->HFCLKCTRL = CLOCK_HFCLKCTRL_HCLK_Div2 << CLOCK_HFCLKCTRL_HCLK_Pos;
20001f30:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20001f34:	2201      	movs	r2, #1
20001f36:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558
        }

        /* Workaround for Errata 46 "Higher power consumption of LFRC" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_46())
20001f3a:	f7ff ffb3 	bl	20001ea4 <nrf53_errata_42>
20001f3e:	b110      	cbz	r0, 20001f46 <SystemInit+0x66>
        {
            *((volatile uint32_t *)0x5003254Cul) = 0;
20001f40:	2200      	movs	r2, #0
20001f42:	4b1d      	ldr	r3, [pc, #116]	; (20001fb8 <SystemInit+0xd8>)
20001f44:	601a      	str	r2, [r3, #0]
        }

        /* Workaround for Errata 49 "SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_49())
20001f46:	f7ff ffad 	bl	20001ea4 <nrf53_errata_42>
20001f4a:	b150      	cbz	r0, 20001f62 <SystemInit+0x82>
        {
            if (NRF_RESET_S->RESETREAS & RESET_RESETREAS_RESETPIN_Msk)
20001f4c:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20001f50:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
20001f54:	07d1      	lsls	r1, r2, #31
            {
                NRF_POWER_S->EVENTS_SLEEPENTER = 0;
20001f56:	bf42      	ittt	mi
20001f58:	2200      	movmi	r2, #0
20001f5a:	f8c3 2114 	strmi.w	r2, [r3, #276]	; 0x114
                NRF_POWER_S->EVENTS_SLEEPEXIT = 0;
20001f5e:	f8c3 2118 	strmi.w	r2, [r3, #280]	; 0x118
            }
        }

        /* Workaround for Errata 55 "Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_55())
20001f62:	f7ff ff9f 	bl	20001ea4 <nrf53_errata_42>
20001f66:	b148      	cbz	r0, 20001f7c <SystemInit+0x9c>
        {
            if (NRF_RESET_S->RESETREAS & RESET_RESETREAS_RESETPIN_Msk){
20001f68:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20001f6c:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
20001f70:	07d2      	lsls	r2, r2, #31
                NRF_RESET_S->RESETREAS = ~RESET_RESETREAS_RESETPIN_Msk;
20001f72:	bf44      	itt	mi
20001f74:	f06f 0201 	mvnmi.w	r2, #1
20001f78:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400
            }
        }

        /* Workaround for Errata 69 "VREGMAIN configuration is not retained in System OFF" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_69())
20001f7c:	f7ff ff92 	bl	20001ea4 <nrf53_errata_42>
20001f80:	b110      	cbz	r0, 20001f88 <SystemInit+0xa8>
        {
            *((volatile uint32_t *)0x5000470Cul) =0x65ul;
20001f82:	2265      	movs	r2, #101	; 0x65
20001f84:	4b0d      	ldr	r3, [pc, #52]	; (20001fbc <SystemInit+0xdc>)
20001f86:	601a      	str	r2, [r3, #0]

        #endif

        /* Allow Non-Secure code to run FPU instructions.
         * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
        SCB->NSACR |= (3UL << 10);
20001f88:	4a0d      	ldr	r2, [pc, #52]	; (20001fc0 <SystemInit+0xe0>)
20001f8a:	f8d2 308c 	ldr.w	r3, [r2, #140]	; 0x8c
20001f8e:	f443 6340 	orr.w	r3, r3, #3072	; 0xc00
20001f92:	f8c2 308c 	str.w	r3, [r2, #140]	; 0x8c
        __DSB();
        __ISB();
    #endif

    SystemCoreClockUpdate();
}
20001f96:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    SystemCoreClockUpdate();
20001f9a:	f7ff bf91 	b.w	20001ec0 <SystemCoreClockUpdate>
            *((volatile uint32_t *)0x5000470Cul) = 0x29ul;
20001f9e:	2229      	movs	r2, #41	; 0x29
20001fa0:	4b06      	ldr	r3, [pc, #24]	; (20001fbc <SystemInit+0xdc>)
20001fa2:	601a      	str	r2, [r3, #0]
            *((volatile uint32_t *)0x5000473Cul) = 0x3ul;
20001fa4:	2203      	movs	r2, #3
20001fa6:	631a      	str	r2, [r3, #48]	; 0x30
20001fa8:	e7bc      	b.n	20001f24 <SystemInit+0x44>
20001faa:	bf00      	nop
20001fac:	50004a20 	.word	0x50004a20
20001fb0:	50039530 	.word	0x50039530
20001fb4:	beef0044 	.word	0xbeef0044
20001fb8:	5003254c 	.word	0x5003254c
20001fbc:	5000470c 	.word	0x5000470c
20001fc0:	e000ed00 	.word	0xe000ed00

20001fc4 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
20001fc4:	4b04      	ldr	r3, [pc, #16]	; (20001fd8 <nrfx_clock_init+0x14>)
20001fc6:	791a      	ldrb	r2, [r3, #4]
20001fc8:	b922      	cbnz	r2, 20001fd4 <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
20001fca:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
20001fcc:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
20001fce:	711a      	strb	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
20001fd0:	4802      	ldr	r0, [pc, #8]	; (20001fdc <nrfx_clock_init+0x18>)
20001fd2:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
20001fd4:	4802      	ldr	r0, [pc, #8]	; (20001fe0 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
20001fd6:	4770      	bx	lr
20001fd8:	2002086c 	.word	0x2002086c
20001fdc:	0bad0000 	.word	0x0bad0000
20001fe0:	0bad000c 	.word	0x0bad000c

20001fe4 <nrfx_clock_start>:
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
20001fe4:	2803      	cmp	r0, #3
20001fe6:	d847      	bhi.n	20002078 <nrfx_clock_start+0x94>
20001fe8:	e8df f000 	tbb	[pc, r0]
20001fec:	3a2d2202 	.word	0x3a2d2202
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
20001ff0:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
20001ff4:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
20001ff8:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
20001ffc:	03c9      	lsls	r1, r1, #15
20001ffe:	d511      	bpl.n	20002024 <nrfx_clock_start+0x40>
    {
        case NRF_CLOCK_DOMAIN_LFCLK:
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
            {
                nrf_clock_lfclk_t lfclksrc;
                if (nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc) &&
20002000:	f003 0303 	and.w	r3, r3, #3
20002004:	2b02      	cmp	r3, #2
20002006:	d10d      	bne.n	20002024 <nrfx_clock_start+0x40>
    p_reg->LFCLKSRC = (uint32_t)(source);
20002008:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
2000200c:	2200      	movs	r2, #0
2000200e:	4b1b      	ldr	r3, [pc, #108]	; (2000207c <nrfx_clock_start+0x98>)
20002010:	601a      	str	r2, [r3, #0]
20002012:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
20002014:	2202      	movs	r2, #2
20002016:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
2000201a:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
2000201e:	2201      	movs	r2, #1
20002020:	609a      	str	r2, [r3, #8]
}
20002022:	4770      	bx	lr
    p_reg->LFCLKSRC = (uint32_t)(source);
20002024:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20002028:	2201      	movs	r2, #1
2000202a:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
2000202e:	e7ed      	b.n	2000200c <nrfx_clock_start+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
20002030:	2200      	movs	r2, #0
20002032:	4b13      	ldr	r3, [pc, #76]	; (20002080 <nrfx_clock_start+0x9c>)
20002034:	601a      	str	r2, [r3, #0]
20002036:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
20002038:	2201      	movs	r2, #1
2000203a:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
2000203e:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
20002042:	601a      	str	r2, [r3, #0]
}
20002044:	4770      	bx	lr
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
20002046:	2200      	movs	r2, #0
20002048:	4b0e      	ldr	r3, [pc, #56]	; (20002084 <nrfx_clock_start+0xa0>)
2000204a:	601a      	str	r2, [r3, #0]
2000204c:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
2000204e:	f44f 7200 	mov.w	r2, #512	; 0x200
20002052:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20002056:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
2000205a:	2201      	movs	r2, #1
2000205c:	621a      	str	r2, [r3, #32]
}
2000205e:	4770      	bx	lr
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
20002060:	2200      	movs	r2, #0
20002062:	4b09      	ldr	r3, [pc, #36]	; (20002088 <nrfx_clock_start+0xa4>)
20002064:	601a      	str	r2, [r3, #0]
20002066:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
20002068:	f44f 7280 	mov.w	r2, #256	; 0x100
2000206c:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20002070:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
20002074:	2201      	movs	r2, #1
20002076:	619a      	str	r2, [r3, #24]
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
20002078:	4770      	bx	lr
2000207a:	bf00      	nop
2000207c:	50005104 	.word	0x50005104
20002080:	50005100 	.word	0x50005100
20002084:	50005124 	.word	0x50005124
20002088:	50005120 	.word	0x50005120

2000208c <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
2000208c:	b570      	push	{r4, r5, r6, lr}
2000208e:	4604      	mov	r4, r0
20002090:	2803      	cmp	r0, #3
20002092:	d83e      	bhi.n	20002112 <nrfx_clock_stop+0x86>
20002094:	e8df f000 	tbb	[pc, r0]
20002098:	4b3e2202 	.word	0x4b3e2202
    p_reg->INTENCLR = mask;
2000209c:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
200020a0:	2202      	movs	r2, #2
200020a2:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
200020a6:	2200      	movs	r2, #0
200020a8:	f503 7382 	add.w	r3, r3, #260	; 0x104
200020ac:	601a      	str	r2, [r3, #0]
200020ae:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
200020b0:	4b28      	ldr	r3, [pc, #160]	; (20002154 <nrfx_clock_stop+0xc8>)
200020b2:	2201      	movs	r2, #1
200020b4:	f242 7510 	movw	r5, #10000	; 0x2710
            if ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_STATE_Msk)
200020b8:	f04f 2650 	mov.w	r6, #1342197760	; 0x50005000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
200020bc:	601a      	str	r2, [r3, #0]
    switch (domain)
200020be:	2c02      	cmp	r4, #2
200020c0:	d042      	beq.n	20002148 <nrfx_clock_stop+0xbc>
200020c2:	2c03      	cmp	r4, #3
200020c4:	d043      	beq.n	2000214e <nrfx_clock_stop+0xc2>
200020c6:	bb24      	cbnz	r4, 20002112 <nrfx_clock_stop+0x86>
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
200020c8:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
                       (clk_src != NRF_CLOCK_HFCLK_HIGH_ACCURACY)), 10000, 1, stopped);
    }
    else
    {
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
200020cc:	03db      	lsls	r3, r3, #15
200020ce:	d520      	bpl.n	20002112 <nrfx_clock_stop+0x86>
200020d0:	2001      	movs	r0, #1
200020d2:	f001 fe1e 	bl	20003d12 <nrfx_busy_wait>
200020d6:	3d01      	subs	r5, #1
200020d8:	d1f1      	bne.n	200020be <nrfx_clock_stop+0x32>
200020da:	e01a      	b.n	20002112 <nrfx_clock_stop+0x86>
    p_reg->INTENCLR = mask;
200020dc:	2301      	movs	r3, #1
200020de:	f04f 2450 	mov.w	r4, #1342197760	; 0x50005000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
200020e2:	2100      	movs	r1, #0
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
200020e4:	f242 7510 	movw	r5, #10000	; 0x2710
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
200020e8:	4a1b      	ldr	r2, [pc, #108]	; (20002158 <nrfx_clock_stop+0xcc>)
    p_reg->INTENCLR = mask;
200020ea:	f8c4 3308 	str.w	r3, [r4, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
200020ee:	6011      	str	r1, [r2, #0]
200020f0:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
200020f2:	4a1a      	ldr	r2, [pc, #104]	; (2000215c <nrfx_clock_stop+0xd0>)
200020f4:	6013      	str	r3, [r2, #0]
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
200020f6:	f8d4 340c 	ldr.w	r3, [r4, #1036]	; 0x40c
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
200020fa:	f8d4 240c 	ldr.w	r2, [r4, #1036]	; 0x40c
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
200020fe:	f003 0301 	and.w	r3, r3, #1
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
20002102:	03d2      	lsls	r2, r2, #15
20002104:	d505      	bpl.n	20002112 <nrfx_clock_stop+0x86>
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
20002106:	b123      	cbz	r3, 20002112 <nrfx_clock_stop+0x86>
20002108:	2001      	movs	r0, #1
2000210a:	f001 fe02 	bl	20003d12 <nrfx_busy_wait>
2000210e:	3d01      	subs	r5, #1
20002110:	d1f1      	bne.n	200020f6 <nrfx_clock_stop+0x6a>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
20002112:	bd70      	pop	{r4, r5, r6, pc}
    p_reg->INTENCLR = mask;
20002114:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20002118:	f44f 7200 	mov.w	r2, #512	; 0x200
2000211c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
20002120:	2200      	movs	r2, #0
20002122:	f503 7392 	add.w	r3, r3, #292	; 0x124
20002126:	601a      	str	r2, [r3, #0]
20002128:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
2000212a:	4b0d      	ldr	r3, [pc, #52]	; (20002160 <nrfx_clock_stop+0xd4>)
2000212c:	e7c1      	b.n	200020b2 <nrfx_clock_stop+0x26>
    p_reg->INTENCLR = mask;
2000212e:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20002132:	f44f 7280 	mov.w	r2, #256	; 0x100
20002136:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
2000213a:	2200      	movs	r2, #0
2000213c:	f503 7390 	add.w	r3, r3, #288	; 0x120
20002140:	601a      	str	r2, [r3, #0]
20002142:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
20002144:	4b07      	ldr	r3, [pc, #28]	; (20002164 <nrfx_clock_stop+0xd8>)
20002146:	e7b4      	b.n	200020b2 <nrfx_clock_stop+0x26>
            if ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_STATE_Msk)
20002148:	f8d6 345c 	ldr.w	r3, [r6, #1116]	; 0x45c
2000214c:	e7be      	b.n	200020cc <nrfx_clock_stop+0x40>
            return (p_reg->HFCLKAUDIOSTAT & CLOCK_HFCLKAUDIOSTAT_STATE_Msk) ==
2000214e:	f8d6 3454 	ldr.w	r3, [r6, #1108]	; 0x454
20002152:	e7bb      	b.n	200020cc <nrfx_clock_stop+0x40>
20002154:	5000500c 	.word	0x5000500c
20002158:	50005100 	.word	0x50005100
2000215c:	50005004 	.word	0x50005004
20002160:	50005024 	.word	0x50005024
20002164:	5000501c 	.word	0x5000501c

20002168 <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
20002168:	4b26      	ldr	r3, [pc, #152]	; (20002204 <nrfx_power_clock_irq_handler+0x9c>)
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
2000216a:	b510      	push	{r4, lr}
2000216c:	681a      	ldr	r2, [r3, #0]
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
2000216e:	b152      	cbz	r2, 20002186 <nrfx_power_clock_irq_handler+0x1e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
20002170:	2000      	movs	r0, #0
20002172:	6018      	str	r0, [r3, #0]
20002174:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
20002176:	2201      	movs	r2, #1
20002178:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
2000217c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
20002180:	4b21      	ldr	r3, [pc, #132]	; (20002208 <nrfx_power_clock_irq_handler+0xa0>)
20002182:	681b      	ldr	r3, [r3, #0]
20002184:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
20002186:	4b21      	ldr	r3, [pc, #132]	; (2000220c <nrfx_power_clock_irq_handler+0xa4>)
20002188:	681a      	ldr	r2, [r3, #0]
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
2000218a:	b18a      	cbz	r2, 200021b0 <nrfx_power_clock_irq_handler+0x48>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
2000218c:	2200      	movs	r2, #0
2000218e:	601a      	str	r2, [r3, #0]
20002190:	681b      	ldr	r3, [r3, #0]
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
20002192:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20002196:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
2000219a:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
2000219e:	f002 0203 	and.w	r2, r2, #3
200021a2:	2a01      	cmp	r2, #1
200021a4:	f04f 0102 	mov.w	r1, #2
200021a8:	d124      	bne.n	200021f4 <nrfx_power_clock_irq_handler+0x8c>
    p_reg->LFCLKSRC = (uint32_t)(source);
200021aa:	f8c3 1518 	str.w	r1, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
200021ae:	609a      	str	r2, [r3, #8]
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
200021b0:	4b17      	ldr	r3, [pc, #92]	; (20002210 <nrfx_power_clock_irq_handler+0xa8>)
200021b2:	681a      	ldr	r2, [r3, #0]
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_CAL_DONE);
    }
#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)

#if NRF_CLOCK_HAS_HFCLKAUDIO
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED))
200021b4:	b162      	cbz	r2, 200021d0 <nrfx_power_clock_irq_handler+0x68>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
200021b6:	2200      	movs	r2, #0
200021b8:	601a      	str	r2, [r3, #0]
200021ba:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
200021bc:	f44f 7280 	mov.w	r2, #256	; 0x100
200021c0:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
200021c4:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HFAUDIO_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLKAUDIO_STARTED);
200021c8:	4b0f      	ldr	r3, [pc, #60]	; (20002208 <nrfx_power_clock_irq_handler+0xa0>)
200021ca:	2004      	movs	r0, #4
200021cc:	681b      	ldr	r3, [r3, #0]
200021ce:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
200021d0:	4b10      	ldr	r3, [pc, #64]	; (20002214 <nrfx_power_clock_irq_handler+0xac>)
200021d2:	681a      	ldr	r2, [r3, #0]
    }
#endif

#if NRF_CLOCK_HAS_HFCLK192M
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED))
200021d4:	b1aa      	cbz	r2, 20002202 <nrfx_power_clock_irq_handler+0x9a>
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
200021d6:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
200021da:	2200      	movs	r2, #0
200021dc:	601a      	str	r2, [r3, #0]
200021de:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
200021e0:	f44f 7200 	mov.w	r2, #512	; 0x200
200021e4:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
200021e8:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
200021ec:	4b06      	ldr	r3, [pc, #24]	; (20002208 <nrfx_power_clock_irq_handler+0xa0>)
200021ee:	2005      	movs	r0, #5
200021f0:	681b      	ldr	r3, [r3, #0]
200021f2:	4718      	bx	r3
200021f4:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
200021f8:	4b03      	ldr	r3, [pc, #12]	; (20002208 <nrfx_power_clock_irq_handler+0xa0>)
200021fa:	2001      	movs	r0, #1
200021fc:	681b      	ldr	r3, [r3, #0]
200021fe:	4798      	blx	r3
20002200:	e7d6      	b.n	200021b0 <nrfx_power_clock_irq_handler+0x48>
}
20002202:	bd10      	pop	{r4, pc}
20002204:	50005100 	.word	0x50005100
20002208:	2002086c 	.word	0x2002086c
2000220c:	50005104 	.word	0x50005104
20002210:	50005120 	.word	0x50005120
20002214:	50005124 	.word	0x50005124

20002218 <z_sys_init_run_level>:
 * off and the next one begins.
 *
 * @param level init level to run.
 */
void z_sys_init_run_level(int32_t level)
{
20002218:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
2000221a:	4b10      	ldr	r3, [pc, #64]	; (2000225c <z_sys_init_run_level+0x44>)
			/* Initialization failed.
			 * Set the init status bit so device is not declared ready.
			 */
			sys_bitfield_set_bit(
				(mem_addr_t) __device_init_status_start,
				(dev - __device_start));
2000221c:	4f10      	ldr	r7, [pc, #64]	; (20002260 <z_sys_init_run_level+0x48>)
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
2000221e:	f853 5020 	ldr.w	r5, [r3, r0, lsl #2]
20002222:	3001      	adds	r0, #1
20002224:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
20002228:	42ae      	cmp	r6, r5
2000222a:	d800      	bhi.n	2000222e <z_sys_init_run_level+0x16>
		}
	}
}
2000222c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		if ((entry->init(dev) != 0) && (dev != NULL)) {
2000222e:	e9d5 3400 	ldrd	r3, r4, [r5]
20002232:	4620      	mov	r0, r4
20002234:	4798      	blx	r3
20002236:	b170      	cbz	r0, 20002256 <z_sys_init_run_level+0x3e>
20002238:	b16c      	cbz	r4, 20002256 <z_sys_init_run_level+0x3e>

static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit)
{
	uint32_t temp = *(volatile uint32_t *)addr;

	*(volatile uint32_t *)addr = temp | (1 << bit);
2000223a:	2301      	movs	r3, #1
				(dev - __device_start));
2000223c:	1be4      	subs	r4, r4, r7
	void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
{
	/* Doing memory offsets in terms of 32-bit values to prevent
	 * alignment issues
	 */
	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
2000223e:	4a09      	ldr	r2, [pc, #36]	; (20002264 <z_sys_init_run_level+0x4c>)
20002240:	1124      	asrs	r4, r4, #4
20002242:	0961      	lsrs	r1, r4, #5
	uint32_t temp = *(volatile uint32_t *)addr;
20002244:	f852 0021 	ldr.w	r0, [r2, r1, lsl #2]
	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
20002248:	f004 041f 	and.w	r4, r4, #31
	*(volatile uint32_t *)addr = temp | (1 << bit);
2000224c:	fa03 f404 	lsl.w	r4, r3, r4
20002250:	4304      	orrs	r4, r0
20002252:	f842 4021 	str.w	r4, [r2, r1, lsl #2]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
20002256:	3508      	adds	r5, #8
20002258:	e7e6      	b.n	20002228 <z_sys_init_run_level+0x10>
2000225a:	bf00      	nop
2000225c:	2000432c 	.word	0x2000432c
20002260:	200200a8 	.word	0x200200a8
20002264:	20020108 	.word	0x20020108

20002268 <z_device_ready>:

bool z_device_ready(const struct device *dev)
{
	/* Set bit indicates device failed initialization */
	return !(sys_bitfield_test_bit((mem_addr_t)__device_init_status_start,
					(dev - __device_start)));
20002268:	4b08      	ldr	r3, [pc, #32]	; (2000228c <z_device_ready+0x24>)
2000226a:	1ac0      	subs	r0, r0, r3
2000226c:	1100      	asrs	r0, r0, #4
}

static ALWAYS_INLINE
	int sys_bitfield_test_bit(mem_addr_t addr, unsigned int bit)
{
	return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
2000226e:	4b08      	ldr	r3, [pc, #32]	; (20002290 <z_device_ready+0x28>)
20002270:	0942      	lsrs	r2, r0, #5
	uint32_t temp = *(volatile uint32_t *)addr;
20002272:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
	return temp & (1 << bit);
20002276:	2301      	movs	r3, #1
	return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
20002278:	f000 001f 	and.w	r0, r0, #31
	return temp & (1 << bit);
2000227c:	fa03 f000 	lsl.w	r0, r3, r0
	return !(sys_bitfield_test_bit((mem_addr_t)__device_init_status_start,
20002280:	4210      	tst	r0, r2
}
20002282:	bf0c      	ite	eq
20002284:	4618      	moveq	r0, r3
20002286:	2000      	movne	r0, #0
20002288:	4770      	bx	lr
2000228a:	bf00      	nop
2000228c:	200200a8 	.word	0x200200a8
20002290:	20020108 	.word	0x20020108

20002294 <z_impl_device_get_binding>:
	for (dev = __device_start; dev != __device_end; dev++) {
20002294:	4911      	ldr	r1, [pc, #68]	; (200022dc <z_impl_device_get_binding+0x48>)
{
20002296:	b570      	push	{r4, r5, r6, lr}
20002298:	4605      	mov	r5, r0
2000229a:	460e      	mov	r6, r1
	for (dev = __device_start; dev != __device_end; dev++) {
2000229c:	4c10      	ldr	r4, [pc, #64]	; (200022e0 <z_impl_device_get_binding+0x4c>)
2000229e:	428c      	cmp	r4, r1
200022a0:	d104      	bne.n	200022ac <z_impl_device_get_binding+0x18>
	for (dev = __device_start; dev != __device_end; dev++) {
200022a2:	4c0f      	ldr	r4, [pc, #60]	; (200022e0 <z_impl_device_get_binding+0x4c>)
200022a4:	42b4      	cmp	r4, r6
200022a6:	d10a      	bne.n	200022be <z_impl_device_get_binding+0x2a>
	return NULL;
200022a8:	2400      	movs	r4, #0
200022aa:	e014      	b.n	200022d6 <z_impl_device_get_binding+0x42>
		if (z_device_ready(dev) && (dev->name == name)) {
200022ac:	4620      	mov	r0, r4
200022ae:	f7ff ffdb 	bl	20002268 <z_device_ready>
200022b2:	b110      	cbz	r0, 200022ba <z_impl_device_get_binding+0x26>
200022b4:	6823      	ldr	r3, [r4, #0]
200022b6:	42ab      	cmp	r3, r5
200022b8:	d00d      	beq.n	200022d6 <z_impl_device_get_binding+0x42>
	for (dev = __device_start; dev != __device_end; dev++) {
200022ba:	3410      	adds	r4, #16
200022bc:	e7ef      	b.n	2000229e <z_impl_device_get_binding+0xa>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
200022be:	4620      	mov	r0, r4
200022c0:	f7ff ffd2 	bl	20002268 <z_device_ready>
200022c4:	b908      	cbnz	r0, 200022ca <z_impl_device_get_binding+0x36>
	for (dev = __device_start; dev != __device_end; dev++) {
200022c6:	3410      	adds	r4, #16
200022c8:	e7ec      	b.n	200022a4 <z_impl_device_get_binding+0x10>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
200022ca:	4628      	mov	r0, r5
200022cc:	6821      	ldr	r1, [r4, #0]
200022ce:	f001 fba1 	bl	20003a14 <strcmp>
200022d2:	2800      	cmp	r0, #0
200022d4:	d1f7      	bne.n	200022c6 <z_impl_device_get_binding+0x32>
}
200022d6:	4620      	mov	r0, r4
200022d8:	bd70      	pop	{r4, r5, r6, pc}
200022da:	bf00      	nop
200022dc:	20020108 	.word	0x20020108
200022e0:	200200a8 	.word	0x200200a8

200022e4 <idle>:
#else
#define IDLE_YIELD_IF_COOP() do { } while (false)
#endif

void idle(void *unused1, void *unused2, void *unused3)
{
200022e4:	b508      	push	{r3, lr}
	_kernel.idle = ticks;
200022e6:	4d0b      	ldr	r5, [pc, #44]	; (20002314 <idle+0x30>)
200022e8:	f04f 0220 	mov.w	r2, #32
200022ec:	f3ef 8311 	mrs	r3, BASEPRI
200022f0:	f382 8811 	msr	BASEPRI, r2
200022f4:	f3bf 8f6f 	isb	sy
	int32_t ticks = z_get_next_timeout_expiry();
200022f8:	f001 fe26 	bl	20003f48 <z_get_next_timeout_expiry>
	z_set_timeout_expiry((ticks < IDLE_THRESH) ? 1 : ticks, true);
200022fc:	2101      	movs	r1, #1
	int32_t ticks = z_get_next_timeout_expiry();
200022fe:	4604      	mov	r4, r0
	z_set_timeout_expiry((ticks < IDLE_THRESH) ? 1 : ticks, true);
20002300:	2802      	cmp	r0, #2
20002302:	bfd8      	it	le
20002304:	4608      	movle	r0, r1
20002306:	f001 fe2f 	bl	20003f68 <z_set_timeout_expiry>
	_kernel.idle = ticks;
2000230a:	622c      	str	r4, [r5, #32]
	arch_cpu_idle();
2000230c:	f7fe ffa6 	bl	2000125c <arch_cpu_idle>
}
20002310:	e7ea      	b.n	200022e8 <idle+0x4>
20002312:	bf00      	nop
20002314:	20020874 	.word	0x20020874

20002318 <z_bss_zero>:
 *
 * @return N/A
 */
void z_bss_zero(void)
{
	(void)memset(__bss_start, 0, __bss_end - __bss_start);
20002318:	4802      	ldr	r0, [pc, #8]	; (20002324 <z_bss_zero+0xc>)
2000231a:	4a03      	ldr	r2, [pc, #12]	; (20002328 <z_bss_zero+0x10>)
2000231c:	2100      	movs	r1, #0
2000231e:	1a12      	subs	r2, r2, r0
20002320:	f001 bbaf 	b.w	20003a82 <memset>
20002324:	20020160 	.word	0x20020160
20002328:	200208d0 	.word	0x200208d0

2000232c <z_data_copy>:
 * This routine copies the data section from ROM to RAM.
 *
 * @return N/A
 */
void z_data_copy(void)
{
2000232c:	b508      	push	{r3, lr}
	(void)memcpy(&__data_ram_start, &__data_rom_start,
		 __data_ram_end - __data_ram_start);
2000232e:	4806      	ldr	r0, [pc, #24]	; (20002348 <z_data_copy+0x1c>)
	(void)memcpy(&__data_ram_start, &__data_rom_start,
20002330:	4a06      	ldr	r2, [pc, #24]	; (2000234c <z_data_copy+0x20>)
20002332:	4907      	ldr	r1, [pc, #28]	; (20002350 <z_data_copy+0x24>)
20002334:	1a12      	subs	r2, r2, r0
20002336:	f001 fb79 	bl	20003a2c <memcpy>
#else
	(void)memcpy(&_app_smem_start, &_app_smem_rom_start,
		 _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
2000233a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	(void)memcpy(&_ramfunc_ram_start, &_ramfunc_rom_start,
2000233e:	4a05      	ldr	r2, [pc, #20]	; (20002354 <z_data_copy+0x28>)
20002340:	4905      	ldr	r1, [pc, #20]	; (20002358 <z_data_copy+0x2c>)
20002342:	4806      	ldr	r0, [pc, #24]	; (2000235c <z_data_copy+0x30>)
20002344:	f001 bb72 	b.w	20003a2c <memcpy>
20002348:	20020000 	.word	0x20020000
2000234c:	2002015c 	.word	0x2002015c
20002350:	200044d4 	.word	0x200044d4
20002354:	00000000 	.word	0x00000000
20002358:	200044d4 	.word	0x200044d4
2000235c:	20020000 	.word	0x20020000

20002360 <bg_thread_main>:
	static const unsigned int boot_delay = CONFIG_BOOT_DELAY;
#else
	static const unsigned int boot_delay;
#endif

	z_sys_post_kernel = true;
20002360:	2201      	movs	r2, #1
{
20002362:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
20002364:	4b0b      	ldr	r3, [pc, #44]	; (20002394 <bg_thread_main+0x34>)

	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
20002366:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
20002368:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
2000236a:	f7ff ff55 	bl	20002218 <z_sys_init_run_level>
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
2000236e:	4a0a      	ldr	r2, [pc, #40]	; (20002398 <bg_thread_main+0x38>)
20002370:	490a      	ldr	r1, [pc, #40]	; (2000239c <bg_thread_main+0x3c>)
20002372:	480b      	ldr	r0, [pc, #44]	; (200023a0 <bg_thread_main+0x40>)
20002374:	f001 f8cc 	bl	20003510 <printk>
	__do_global_ctors_aux();
	__do_init_array_aux();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
20002378:	2003      	movs	r0, #3
2000237a:	f7ff ff4d 	bl	20002218 <z_sys_init_run_level>

	z_init_static_threads();
2000237e:	f000 fdab 	bl	20002ed8 <z_init_static_threads>
	z_timestamp_main = k_cycle_get_32();
#endif

	extern void main(void);

	main();
20002382:	f7fe f865 	bl	20000450 <main>

	/* Mark nonessenrial since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
20002386:	4a07      	ldr	r2, [pc, #28]	; (200023a4 <bg_thread_main+0x44>)
20002388:	7b13      	ldrb	r3, [r2, #12]
2000238a:	f023 0301 	bic.w	r3, r3, #1
2000238e:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
20002390:	bd08      	pop	{r3, pc}
20002392:	bf00      	nop
20002394:	200208ce 	.word	0x200208ce
20002398:	200044ce 	.word	0x200044ce
2000239c:	2000449c 	.word	0x2000449c
200023a0:	200044a8 	.word	0x200044a8
200023a4:	200201e0 	.word	0x200201e0

200023a8 <z_cstart>:
 * cleared/zeroed.
 *
 * @return Does not return
 */
FUNC_NORETURN void z_cstart(void)
{
200023a8:	e92d 4880 	stmdb	sp!, {r7, fp, lr}
 * @return N/A
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
		(uint32_t)(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) +
200023ac:	4b34      	ldr	r3, [pc, #208]	; (20002480 <z_cstart+0xd8>)
200023ae:	b0a7      	sub	sp, #156	; 0x9c
	uint32_t msp =
200023b0:	f503 6900 	add.w	r9, r3, #2048	; 0x800
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
200023b4:	f389 8808 	msr	MSP, r9
  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
200023b8:	f383 880a 	msr	MSPLIM, r3
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
200023bc:	2400      	movs	r4, #0
200023be:	23e0      	movs	r3, #224	; 0xe0
200023c0:	4d30      	ldr	r5, [pc, #192]	; (20002484 <z_cstart+0xdc>)
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
200023c2:	f04f 0b01 	mov.w	fp, #1
200023c6:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
200023ca:	77ec      	strb	r4, [r5, #31]
200023cc:	762c      	strb	r4, [r5, #24]
200023ce:	766c      	strb	r4, [r5, #25]
200023d0:	76ac      	strb	r4, [r5, #26]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
200023d2:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	_kernel.ready_q.cache = &z_main_thread;
200023d4:	4e2c      	ldr	r6, [pc, #176]	; (20002488 <z_cstart+0xe0>)
200023d6:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
200023da:	626b      	str	r3, [r5, #36]	; 0x24

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
200023dc:	f7ff f882 	bl	200014e4 <z_arm_fault_init>
	z_arm_cpu_idle_init();
200023e0:	f7fe ff36 	bl	20001250 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
200023e4:	f04f 33ff 	mov.w	r3, #4294967295
200023e8:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
200023ea:	62eb      	str	r3, [r5, #44]	; 0x2c
{
	dummy_thread->base.thread_state = _THREAD_DUMMY;
#ifdef CONFIG_SCHED_CPU_MASK
	dummy_thread->base.cpu_mask = -1;
#endif
	dummy_thread->base.user_options = K_ESSENTIAL;
200023ec:	f240 1301 	movw	r3, #257	; 0x101
#endif
#ifdef CONFIG_USERSPACE
	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
#endif

	_current_cpu->current = dummy_thread;
200023f0:	4d26      	ldr	r5, [pc, #152]	; (2000248c <z_cstart+0xe4>)
	dummy_thread->base.user_options = K_ESSENTIAL;
200023f2:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
200023f6:	ab06      	add	r3, sp, #24
200023f8:	60ab      	str	r3, [r5, #8]

	z_dummy_thread_init(&dummy_thread);
#endif

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
200023fa:	4620      	mov	r0, r4
	dummy_thread->stack_info.size = 0U;
200023fc:	e9cd 4420 	strd	r4, r4, [sp, #128]	; 0x80
20002400:	f7ff ff0a 	bl	20002218 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
20002404:	2001      	movs	r0, #1
20002406:	f7ff ff07 	bl	20002218 <z_sys_init_run_level>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
2000240a:	f8df a098 	ldr.w	sl, [pc, #152]	; 200024a4 <z_cstart+0xfc>
	z_sched_init();
2000240e:	f000 fc69 	bl	20002ce4 <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
20002412:	4b1f      	ldr	r3, [pc, #124]	; (20002490 <z_cstart+0xe8>)
	_kernel.ready_q.cache = &z_main_thread;
20002414:	626e      	str	r6, [r5, #36]	; 0x24
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
20002416:	f44f 6280 	mov.w	r2, #1024	; 0x400
2000241a:	491e      	ldr	r1, [pc, #120]	; (20002494 <z_cstart+0xec>)
2000241c:	9305      	str	r3, [sp, #20]
2000241e:	4630      	mov	r0, r6
20002420:	4653      	mov	r3, sl
20002422:	e9cd 4b03 	strd	r4, fp, [sp, #12]
20002426:	e9cd 4401 	strd	r4, r4, [sp, #4]
2000242a:	9400      	str	r4, [sp, #0]
2000242c:	f000 fd24 	bl	20002e78 <z_setup_new_thread>
	sys_trace_thread_resume(thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
20002430:	7b73      	ldrb	r3, [r6, #13]
20002432:	4680      	mov	r8, r0
20002434:	f023 0304 	bic.w	r3, r3, #4
	z_ready_thread(&z_main_thread);
20002438:	4630      	mov	r0, r6
2000243a:	7373      	strb	r3, [r6, #13]
2000243c:	f001 fce6 	bl	20003e0c <z_ready_thread>
	z_setup_new_thread(thread, stack,
20002440:	230f      	movs	r3, #15
20002442:	4f15      	ldr	r7, [pc, #84]	; (20002498 <z_cstart+0xf0>)
20002444:	f44f 72a0 	mov.w	r2, #320	; 0x140
20002448:	e9cd 4302 	strd	r4, r3, [sp, #8]
2000244c:	4913      	ldr	r1, [pc, #76]	; (2000249c <z_cstart+0xf4>)
2000244e:	4b14      	ldr	r3, [pc, #80]	; (200024a0 <z_cstart+0xf8>)
20002450:	4638      	mov	r0, r7
20002452:	e9cd b404 	strd	fp, r4, [sp, #16]
20002456:	e9cd 4400 	strd	r4, r4, [sp]
2000245a:	f000 fd0d 	bl	20002e78 <z_setup_new_thread>
2000245e:	7b7b      	ldrb	r3, [r7, #13]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
20002460:	4652      	mov	r2, sl
20002462:	f023 0304 	bic.w	r3, r3, #4
20002466:	737b      	strb	r3, [r7, #13]
 * @return N/A
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
20002468:	f105 0318 	add.w	r3, r5, #24
2000246c:	4641      	mov	r1, r8
2000246e:	4630      	mov	r0, r6
	list->tail = (sys_dnode_t *)list;
20002470:	e9c5 3306 	strd	r3, r3, [r5, #24]
		_kernel.cpus[i].idle_thread = &z_idle_threads[i];
20002474:	60ef      	str	r7, [r5, #12]
		_kernel.cpus[i].id = i;
20002476:	752c      	strb	r4, [r5, #20]
		_kernel.cpus[i].irq_stack =
20002478:	f8c5 9004 	str.w	r9, [r5, #4]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
2000247c:	f7fe fece 	bl	2000121c <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
20002480:	20020e10 	.word	0x20020e10
20002484:	e000ed00 	.word	0xe000ed00
20002488:	200201e0 	.word	0x200201e0
2000248c:	20020874 	.word	0x20020874
20002490:	200044cf 	.word	0x200044cf
20002494:	200208d0 	.word	0x200208d0
20002498:	20020160 	.word	0x20020160
2000249c:	20020cd0 	.word	0x20020cd0
200024a0:	200022e5 	.word	0x200022e5
200024a4:	20002361 	.word	0x20002361

200024a8 <init_mem_slab_module>:
 * Perform any initialization that wasn't done at build time.
 *
 * @return N/A
 */
static int init_mem_slab_module(const struct device *dev)
{
200024a8:	b570      	push	{r4, r5, r6, lr}
	int rc = 0;
	ARG_UNUSED(dev);

	Z_STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
200024aa:	4b0e      	ldr	r3, [pc, #56]	; (200024e4 <init_mem_slab_module+0x3c>)
200024ac:	4c0e      	ldr	r4, [pc, #56]	; (200024e8 <init_mem_slab_module+0x40>)
200024ae:	42a3      	cmp	r3, r4
200024b0:	d301      	bcc.n	200024b6 <init_mem_slab_module+0xe>
		}
		SYS_TRACING_OBJ_INIT(k_mem_slab, slab);
		z_object_init(slab);
	}

out:
200024b2:	2000      	movs	r0, #0
	return rc;
}
200024b4:	bd70      	pop	{r4, r5, r6, pc}
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
200024b6:	e9d3 0103 	ldrd	r0, r1, [r3, #12]
200024ba:	ea41 0200 	orr.w	r2, r1, r0
200024be:	f012 0203 	ands.w	r2, r2, #3
200024c2:	d10b      	bne.n	200024dc <init_mem_slab_module+0x34>
	for (j = 0U; j < slab->num_blocks; j++) {
200024c4:	689d      	ldr	r5, [r3, #8]
	slab->free_list = NULL;
200024c6:	615a      	str	r2, [r3, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
200024c8:	42aa      	cmp	r2, r5
200024ca:	d101      	bne.n	200024d0 <init_mem_slab_module+0x28>
	Z_STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
200024cc:	331c      	adds	r3, #28
200024ce:	e7ee      	b.n	200024ae <init_mem_slab_module+0x6>
		*(char **)p = slab->free_list;
200024d0:	695e      	ldr	r6, [r3, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
200024d2:	3201      	adds	r2, #1
		*(char **)p = slab->free_list;
200024d4:	600e      	str	r6, [r1, #0]
		slab->free_list = p;
200024d6:	6159      	str	r1, [r3, #20]
		p += slab->block_size;
200024d8:	4401      	add	r1, r0
	for (j = 0U; j < slab->num_blocks; j++) {
200024da:	e7f5      	b.n	200024c8 <init_mem_slab_module+0x20>
		return -EINVAL;
200024dc:	f06f 0015 	mvn.w	r0, #21
	return rc;
200024e0:	e7e8      	b.n	200024b4 <init_mem_slab_module+0xc>
200024e2:	bf00      	nop
200024e4:	2002010c 	.word	0x2002010c
200024e8:	2002010c 	.word	0x2002010c

200024ec <k_mem_slab_alloc>:
out:
	return rc;
}

int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
{
200024ec:	b5d3      	push	{r0, r1, r4, r6, r7, lr}
200024ee:	460c      	mov	r4, r1
200024f0:	4616      	mov	r6, r2
200024f2:	461f      	mov	r7, r3
200024f4:	f04f 0320 	mov.w	r3, #32
200024f8:	f3ef 8111 	mrs	r1, BASEPRI
200024fc:	f383 8811 	msr	BASEPRI, r3
20002500:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	int result;

	if (slab->free_list != NULL) {
20002504:	6943      	ldr	r3, [r0, #20]
20002506:	b15b      	cbz	r3, 20002520 <k_mem_slab_alloc+0x34>
		/* take a free block */
		*mem = slab->free_list;
20002508:	6023      	str	r3, [r4, #0]
		slab->free_list = *(char **)(slab->free_list);
2000250a:	681b      	ldr	r3, [r3, #0]
2000250c:	6143      	str	r3, [r0, #20]
		slab->num_used++;
2000250e:	6983      	ldr	r3, [r0, #24]
20002510:	3301      	adds	r3, #1
20002512:	6183      	str	r3, [r0, #24]
		result = 0;
20002514:	2000      	movs	r0, #0
	__asm__ volatile(
20002516:	f381 8811 	msr	BASEPRI, r1
2000251a:	f3bf 8f6f 	isb	sy
		return result;
	}

	k_spin_unlock(&lock, key);

	return result;
2000251e:	e011      	b.n	20002544 <k_mem_slab_alloc+0x58>
	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
20002520:	ea56 0207 	orrs.w	r2, r6, r7
20002524:	d103      	bne.n	2000252e <k_mem_slab_alloc+0x42>
		result = -ENOMEM;
20002526:	f06f 000b 	mvn.w	r0, #11
		*mem = NULL;
2000252a:	6023      	str	r3, [r4, #0]
		result = -ENOMEM;
2000252c:	e7f3      	b.n	20002516 <k_mem_slab_alloc+0x2a>
		result = z_pend_curr(&lock, key, &slab->wait_q, timeout);
2000252e:	4602      	mov	r2, r0
20002530:	e9cd 6700 	strd	r6, r7, [sp]
20002534:	4804      	ldr	r0, [pc, #16]	; (20002548 <k_mem_slab_alloc+0x5c>)
20002536:	f000 fb4f 	bl	20002bd8 <z_pend_curr>
		if (result == 0) {
2000253a:	b918      	cbnz	r0, 20002544 <k_mem_slab_alloc+0x58>
			*mem = _current->base.swap_data;
2000253c:	4b03      	ldr	r3, [pc, #12]	; (2000254c <k_mem_slab_alloc+0x60>)
2000253e:	689b      	ldr	r3, [r3, #8]
20002540:	695b      	ldr	r3, [r3, #20]
20002542:	6023      	str	r3, [r4, #0]
}
20002544:	b002      	add	sp, #8
20002546:	bdd0      	pop	{r4, r6, r7, pc}
20002548:	200208cf 	.word	0x200208cf
2000254c:	20020874 	.word	0x20020874

20002550 <k_mem_slab_free>:

void k_mem_slab_free(struct k_mem_slab *slab, void **mem)
{
20002550:	b570      	push	{r4, r5, r6, lr}
20002552:	4604      	mov	r4, r0
20002554:	460d      	mov	r5, r1
	__asm__ volatile(
20002556:	f04f 0320 	mov.w	r3, #32
2000255a:	f3ef 8611 	mrs	r6, BASEPRI
2000255e:	f383 8811 	msr	BASEPRI, r3
20002562:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *pending_thread = z_unpend_first_thread(&slab->wait_q);
20002566:	f001 fcac 	bl	20003ec2 <z_unpend_first_thread>

	if (pending_thread != NULL) {
2000256a:	b158      	cbz	r0, 20002584 <k_mem_slab_free+0x34>
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
2000256c:	2100      	movs	r1, #0
		z_thread_return_value_set_with_data(pending_thread, 0, *mem);
2000256e:	682a      	ldr	r2, [r5, #0]
20002570:	67c1      	str	r1, [r0, #124]	; 0x7c
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
20002572:	6142      	str	r2, [r0, #20]
		z_ready_thread(pending_thread);
20002574:	f001 fc4a 	bl	20003e0c <z_ready_thread>
		z_reschedule(&lock, key);
20002578:	4631      	mov	r1, r6
		**(char ***)mem = slab->free_list;
		slab->free_list = *(char **)mem;
		slab->num_used--;
		k_spin_unlock(&lock, key);
	}
}
2000257a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule(&lock, key);
2000257e:	4808      	ldr	r0, [pc, #32]	; (200025a0 <k_mem_slab_free+0x50>)
20002580:	f000 b910 	b.w	200027a4 <z_reschedule>
		**(char ***)mem = slab->free_list;
20002584:	682b      	ldr	r3, [r5, #0]
20002586:	6962      	ldr	r2, [r4, #20]
20002588:	601a      	str	r2, [r3, #0]
		slab->free_list = *(char **)mem;
2000258a:	682b      	ldr	r3, [r5, #0]
2000258c:	6163      	str	r3, [r4, #20]
		slab->num_used--;
2000258e:	69a3      	ldr	r3, [r4, #24]
20002590:	3b01      	subs	r3, #1
20002592:	61a3      	str	r3, [r4, #24]
	__asm__ volatile(
20002594:	f386 8811 	msr	BASEPRI, r6
20002598:	f3bf 8f6f 	isb	sy
}
2000259c:	bd70      	pop	{r4, r5, r6, pc}
2000259e:	bf00      	nop
200025a0:	200208cf 	.word	0x200208cf

200025a4 <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
200025a4:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
200025a8:	4604      	mov	r4, r0
200025aa:	4616      	mov	r6, r2
200025ac:	461f      	mov	r7, r3
	__asm__ volatile(
200025ae:	f04f 0320 	mov.w	r3, #32
200025b2:	f3ef 8811 	mrs	r8, BASEPRI
200025b6:	f383 8811 	msr	BASEPRI, r3
200025ba:	f3bf 8f6f 	isb	sy
	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	sys_trace_mutex_lock(mutex);
	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
200025be:	68c3      	ldr	r3, [r0, #12]
200025c0:	4a32      	ldr	r2, [pc, #200]	; (2000268c <z_impl_k_mutex_lock+0xe8>)
200025c2:	b16b      	cbz	r3, 200025e0 <z_impl_k_mutex_lock+0x3c>
200025c4:	6880      	ldr	r0, [r0, #8]
200025c6:	6891      	ldr	r1, [r2, #8]
200025c8:	4288      	cmp	r0, r1
200025ca:	d019      	beq.n	20002600 <z_impl_k_mutex_lock+0x5c>
		sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);

		return 0;
	}

	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
200025cc:	ea56 0307 	orrs.w	r3, r6, r7
200025d0:	d118      	bne.n	20002604 <z_impl_k_mutex_lock+0x60>
	__asm__ volatile(
200025d2:	f388 8811 	msr	BASEPRI, r8
200025d6:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);
		return -EBUSY;
200025da:	f06f 000f 	mvn.w	r0, #15
200025de:	e00c      	b.n	200025fa <z_impl_k_mutex_lock+0x56>
					_current->base.prio :
200025e0:	6891      	ldr	r1, [r2, #8]
200025e2:	f991 100e 	ldrsb.w	r1, [r1, #14]
		mutex->lock_count++;
200025e6:	3301      	adds	r3, #1
200025e8:	60e3      	str	r3, [r4, #12]
		mutex->owner = _current;
200025ea:	6893      	ldr	r3, [r2, #8]
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
200025ec:	6121      	str	r1, [r4, #16]
		mutex->owner = _current;
200025ee:	60a3      	str	r3, [r4, #8]
200025f0:	f388 8811 	msr	BASEPRI, r8
200025f4:	f3bf 8f6f 	isb	sy
		return 0;
200025f8:	2000      	movs	r0, #0
		k_spin_unlock(&lock, key);
	}

	sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);
	return -EAGAIN;
}
200025fa:	b002      	add	sp, #8
200025fc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
					_current->base.prio :
20002600:	6921      	ldr	r1, [r4, #16]
20002602:	e7f0      	b.n	200025e6 <z_impl_k_mutex_lock+0x42>
	new_prio = new_prio_for_inheritance(_current->base.prio,
20002604:	f990 300e 	ldrsb.w	r3, [r0, #14]
20002608:	f991 100e 	ldrsb.w	r1, [r1, #14]
2000260c:	4299      	cmp	r1, r3
2000260e:	bfa8      	it	ge
20002610:	4619      	movge	r1, r3
20002612:	ea21 71e1 	bic.w	r1, r1, r1, asr #31
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
20002616:	4299      	cmp	r1, r3
20002618:	da2c      	bge.n	20002674 <z_impl_k_mutex_lock+0xd0>
		return z_set_prio(mutex->owner, new_prio);
2000261a:	f000 fb1f 	bl	20002c5c <z_set_prio>
2000261e:	4605      	mov	r5, r0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
20002620:	4622      	mov	r2, r4
20002622:	4641      	mov	r1, r8
20002624:	e9cd 6700 	strd	r6, r7, [sp]
20002628:	4819      	ldr	r0, [pc, #100]	; (20002690 <z_impl_k_mutex_lock+0xec>)
2000262a:	f000 fad5 	bl	20002bd8 <z_pend_curr>
	if (got_mutex == 0) {
2000262e:	2800      	cmp	r0, #0
20002630:	d0e3      	beq.n	200025fa <z_impl_k_mutex_lock+0x56>
	__asm__ volatile(
20002632:	f04f 0320 	mov.w	r3, #32
20002636:	f3ef 8611 	mrs	r6, BASEPRI
2000263a:	f383 8811 	msr	BASEPRI, r3
2000263e:	f3bf 8f6f 	isb	sy
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
20002642:	6823      	ldr	r3, [r4, #0]
20002644:	6921      	ldr	r1, [r4, #16]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
20002646:	42a3      	cmp	r3, r4
20002648:	d007      	beq.n	2000265a <z_impl_k_mutex_lock+0xb6>
		new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
2000264a:	b133      	cbz	r3, 2000265a <z_impl_k_mutex_lock+0xb6>
2000264c:	f993 300e 	ldrsb.w	r3, [r3, #14]
20002650:	4299      	cmp	r1, r3
20002652:	bfa8      	it	ge
20002654:	4619      	movge	r1, r3
20002656:	ea21 71e1 	bic.w	r1, r1, r1, asr #31
	resched = adjust_owner_prio(mutex, new_prio) || resched;
2000265a:	68a0      	ldr	r0, [r4, #8]
	if (mutex->owner->base.prio != new_prio) {
2000265c:	f990 300e 	ldrsb.w	r3, [r0, #14]
20002660:	4299      	cmp	r1, r3
20002662:	d109      	bne.n	20002678 <z_impl_k_mutex_lock+0xd4>
	if (resched) {
20002664:	b16d      	cbz	r5, 20002682 <z_impl_k_mutex_lock+0xde>
		z_reschedule(&lock, key);
20002666:	4631      	mov	r1, r6
20002668:	4809      	ldr	r0, [pc, #36]	; (20002690 <z_impl_k_mutex_lock+0xec>)
2000266a:	f000 f89b 	bl	200027a4 <z_reschedule>
	return -EAGAIN;
2000266e:	f06f 000a 	mvn.w	r0, #10
20002672:	e7c2      	b.n	200025fa <z_impl_k_mutex_lock+0x56>
	bool resched = false;
20002674:	2500      	movs	r5, #0
20002676:	e7d3      	b.n	20002620 <z_impl_k_mutex_lock+0x7c>
		return z_set_prio(mutex->owner, new_prio);
20002678:	f000 faf0 	bl	20002c5c <z_set_prio>
	resched = adjust_owner_prio(mutex, new_prio) || resched;
2000267c:	2800      	cmp	r0, #0
2000267e:	d1f2      	bne.n	20002666 <z_impl_k_mutex_lock+0xc2>
20002680:	e7f0      	b.n	20002664 <z_impl_k_mutex_lock+0xc0>
	__asm__ volatile(
20002682:	f386 8811 	msr	BASEPRI, r6
20002686:	f3bf 8f6f 	isb	sy
2000268a:	e7f0      	b.n	2000266e <z_impl_k_mutex_lock+0xca>
2000268c:	20020874 	.word	0x20020874
20002690:	200208cf 	.word	0x200208cf

20002694 <z_impl_k_mutex_unlock>:
}
#include <syscalls/k_mutex_lock_mrsh.c>
#endif

int z_impl_k_mutex_unlock(struct k_mutex *mutex)
{
20002694:	b538      	push	{r3, r4, r5, lr}
	struct k_thread *new_owner;

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	CHECKIF(mutex->owner == NULL) {
20002696:	6883      	ldr	r3, [r0, #8]
{
20002698:	4604      	mov	r4, r0
	CHECKIF(mutex->owner == NULL) {
2000269a:	2b00      	cmp	r3, #0
2000269c:	d036      	beq.n	2000270c <z_impl_k_mutex_unlock+0x78>
		return -EINVAL;
	}
	/*
	 * The current thread does not own the mutex.
	 */
	CHECKIF(mutex->owner != _current) {
2000269e:	4a1e      	ldr	r2, [pc, #120]	; (20002718 <z_impl_k_mutex_unlock+0x84>)
200026a0:	6892      	ldr	r2, [r2, #8]
200026a2:	4293      	cmp	r3, r2
200026a4:	d135      	bne.n	20002712 <z_impl_k_mutex_unlock+0x7e>
{
#ifdef CONFIG_PREEMPT_ENABLED
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1, "");

	--_current->base.sched_locked;
200026a6:	7bda      	ldrb	r2, [r3, #15]
200026a8:	3a01      	subs	r2, #1
200026aa:	73da      	strb	r2, [r3, #15]

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count - 1U != 0U) {
200026ac:	68c3      	ldr	r3, [r0, #12]
200026ae:	2b01      	cmp	r3, #1
200026b0:	d005      	beq.n	200026be <z_impl_k_mutex_unlock+0x2a>
		mutex->lock_count--;
200026b2:	3b01      	subs	r3, #1
200026b4:	60c3      	str	r3, [r0, #12]
		k_spin_unlock(&lock, key);
	}


k_mutex_unlock_return:
	k_sched_unlock();
200026b6:	f000 f8d5 	bl	20002864 <k_sched_unlock>
	sys_trace_end_call(SYS_TRACE_ID_MUTEX_UNLOCK);

	return 0;
200026ba:	2000      	movs	r0, #0
}
200026bc:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
200026be:	f04f 0320 	mov.w	r3, #32
200026c2:	f3ef 8511 	mrs	r5, BASEPRI
200026c6:	f383 8811 	msr	BASEPRI, r3
200026ca:	f3bf 8f6f 	isb	sy
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
200026ce:	6901      	ldr	r1, [r0, #16]
200026d0:	6880      	ldr	r0, [r0, #8]
	if (mutex->owner->base.prio != new_prio) {
200026d2:	f990 300e 	ldrsb.w	r3, [r0, #14]
200026d6:	4299      	cmp	r1, r3
200026d8:	d001      	beq.n	200026de <z_impl_k_mutex_unlock+0x4a>
		return z_set_prio(mutex->owner, new_prio);
200026da:	f000 fabf 	bl	20002c5c <z_set_prio>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
200026de:	4620      	mov	r0, r4
200026e0:	f001 fbef 	bl	20003ec2 <z_unpend_first_thread>
	mutex->owner = new_owner;
200026e4:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
200026e6:	b158      	cbz	r0, 20002700 <z_impl_k_mutex_unlock+0x6c>
		mutex->owner_orig_prio = new_owner->base.prio;
200026e8:	f990 200e 	ldrsb.w	r2, [r0, #14]
200026ec:	6122      	str	r2, [r4, #16]
200026ee:	2200      	movs	r2, #0
200026f0:	67c2      	str	r2, [r0, #124]	; 0x7c
		z_ready_thread(new_owner);
200026f2:	f001 fb8b 	bl	20003e0c <z_ready_thread>
		z_reschedule(&lock, key);
200026f6:	4629      	mov	r1, r5
200026f8:	4808      	ldr	r0, [pc, #32]	; (2000271c <z_impl_k_mutex_unlock+0x88>)
200026fa:	f000 f853 	bl	200027a4 <z_reschedule>
200026fe:	e7da      	b.n	200026b6 <z_impl_k_mutex_unlock+0x22>
		mutex->lock_count = 0U;
20002700:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
20002702:	f385 8811 	msr	BASEPRI, r5
20002706:	f3bf 8f6f 	isb	sy
2000270a:	e7d4      	b.n	200026b6 <z_impl_k_mutex_unlock+0x22>
		return -EINVAL;
2000270c:	f06f 0015 	mvn.w	r0, #21
20002710:	e7d4      	b.n	200026bc <z_impl_k_mutex_unlock+0x28>
		return -EPERM;
20002712:	f04f 30ff 	mov.w	r0, #4294967295
20002716:	e7d1      	b.n	200026bc <z_impl_k_mutex_unlock+0x28>
20002718:	20020874 	.word	0x20020874
2000271c:	200208cf 	.word	0x200208cf

20002720 <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(void)
{
20002720:	b510      	push	{r4, lr}
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time != 0) {
20002722:	4c08      	ldr	r4, [pc, #32]	; (20002744 <z_reset_time_slice+0x24>)
20002724:	6823      	ldr	r3, [r4, #0]
20002726:	b15b      	cbz	r3, 20002740 <z_reset_time_slice+0x20>
		_current_cpu->slice_ticks = slice_time + z_clock_elapsed();
20002728:	f7fe fc1e 	bl	20000f68 <z_clock_elapsed>
2000272c:	4603      	mov	r3, r0
2000272e:	6820      	ldr	r0, [r4, #0]
20002730:	4a05      	ldr	r2, [pc, #20]	; (20002748 <z_reset_time_slice+0x28>)
20002732:	4403      	add	r3, r0
		z_set_timeout_expiry(slice_time, false);
20002734:	2100      	movs	r1, #0
	}
}
20002736:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		_current_cpu->slice_ticks = slice_time + z_clock_elapsed();
2000273a:	6113      	str	r3, [r2, #16]
		z_set_timeout_expiry(slice_time, false);
2000273c:	f001 bc14 	b.w	20003f68 <z_set_timeout_expiry>
}
20002740:	bd10      	pop	{r4, pc}
20002742:	bf00      	nop
20002744:	200208ac 	.word	0x200208ac
20002748:	20020874 	.word	0x20020874

2000274c <k_sched_time_slice_set>:

void k_sched_time_slice_set(int32_t slice, int prio)
{
2000274c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
2000274e:	4605      	mov	r5, r0
20002750:	460c      	mov	r4, r1
	__asm__ volatile(
20002752:	f04f 0320 	mov.w	r3, #32
20002756:	f3ef 8611 	mrs	r6, BASEPRI
2000275a:	f383 8811 	msr	BASEPRI, r3
2000275e:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		_current_cpu->slice_ticks = 0;
20002762:	2200      	movs	r2, #0
		} else {
			return t * (to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
20002764:	f44f 4700 	mov.w	r7, #32768	; 0x8000
20002768:	f240 30e7 	movw	r0, #999	; 0x3e7
2000276c:	2100      	movs	r1, #0
2000276e:	4b0a      	ldr	r3, [pc, #40]	; (20002798 <k_sched_time_slice_set+0x4c>)
20002770:	fbe7 0105 	umlal	r0, r1, r7, r5
20002774:	611a      	str	r2, [r3, #16]
20002776:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
2000277a:	2300      	movs	r3, #0
2000277c:	f7fd fcea 	bl	20000154 <__aeabi_uldivmod>
		slice_time = k_ms_to_ticks_ceil32(slice);
20002780:	4b06      	ldr	r3, [pc, #24]	; (2000279c <k_sched_time_slice_set+0x50>)
20002782:	6018      	str	r0, [r3, #0]
		slice_max_prio = prio;
20002784:	4b06      	ldr	r3, [pc, #24]	; (200027a0 <k_sched_time_slice_set+0x54>)
20002786:	601c      	str	r4, [r3, #0]
		z_reset_time_slice();
20002788:	f7ff ffca 	bl	20002720 <z_reset_time_slice>
	__asm__ volatile(
2000278c:	f386 8811 	msr	BASEPRI, r6
20002790:	f3bf 8f6f 	isb	sy
	}
}
20002794:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
20002796:	bf00      	nop
20002798:	20020874 	.word	0x20020874
2000279c:	200208ac 	.word	0x200208ac
200027a0:	200208a8 	.word	0x200208a8

200027a4 <z_reschedule>:
{
#ifdef CONFIG_SMP
	_current_cpu->swap_ok = 0;
#endif

	return arch_irq_unlocked(key) && !arch_is_in_isr();
200027a4:	b949      	cbnz	r1, 200027ba <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
200027a6:	f3ef 8005 	mrs	r0, IPSR
200027aa:	b930      	cbnz	r0, 200027ba <z_reschedule+0x16>
	return _kernel.ready_q.cache;
200027ac:	4b05      	ldr	r3, [pc, #20]	; (200027c4 <z_reschedule+0x20>)
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
	if (resched(key.key) && need_swap()) {
200027ae:	6a5a      	ldr	r2, [r3, #36]	; 0x24
200027b0:	689b      	ldr	r3, [r3, #8]
200027b2:	429a      	cmp	r2, r3
200027b4:	d001      	beq.n	200027ba <z_reschedule+0x16>
	ret = arch_swap(key);
200027b6:	f7fe bc8b 	b.w	200010d0 <arch_swap>
200027ba:	f381 8811 	msr	BASEPRI, r1
200027be:	f3bf 8f6f 	isb	sy
		z_swap(lock, key);
	} else {
		k_spin_unlock(lock, key);
	}
}
200027c2:	4770      	bx	lr
200027c4:	20020874 	.word	0x20020874

200027c8 <k_sched_lock>:
	__asm__ volatile(
200027c8:	f04f 0320 	mov.w	r3, #32
200027cc:	f3ef 8111 	mrs	r1, BASEPRI
200027d0:	f383 8811 	msr	BASEPRI, r3
200027d4:	f3bf 8f6f 	isb	sy
	--_current->base.sched_locked;
200027d8:	4b04      	ldr	r3, [pc, #16]	; (200027ec <k_sched_lock+0x24>)
200027da:	689a      	ldr	r2, [r3, #8]
200027dc:	7bd3      	ldrb	r3, [r2, #15]
200027de:	3b01      	subs	r3, #1
200027e0:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
200027e2:	f381 8811 	msr	BASEPRI, r1
200027e6:	f3bf 8f6f 	isb	sy
void k_sched_lock(void)
{
	LOCKED(&sched_spinlock) {
		z_sched_lock();
	}
}
200027ea:	4770      	bx	lr
200027ec:	20020874 	.word	0x20020874

200027f0 <z_priq_dumb_remove>:
}

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
#if defined(CONFIG_SWAP_NONATOMIC) && defined(CONFIG_SCHED_DUMB)
	if (pq == &_kernel.ready_q.runq && thread == _current &&
200027f0:	4b09      	ldr	r3, [pc, #36]	; (20002818 <z_priq_dumb_remove+0x28>)
200027f2:	f103 0228 	add.w	r2, r3, #40	; 0x28
200027f6:	4282      	cmp	r2, r0
200027f8:	d105      	bne.n	20002806 <z_priq_dumb_remove+0x16>
200027fa:	689b      	ldr	r3, [r3, #8]
200027fc:	428b      	cmp	r3, r1
200027fe:	d102      	bne.n	20002806 <z_priq_dumb_remove+0x16>
20002800:	7b4b      	ldrb	r3, [r1, #13]
20002802:	06db      	lsls	r3, r3, #27
20002804:	d106      	bne.n	20002814 <z_priq_dumb_remove+0x24>
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	node->prev->next = node->next;
20002806:	e9d1 3200 	ldrd	r3, r2, [r1]
2000280a:	6013      	str	r3, [r2, #0]
	node->next->prev = node->prev;
2000280c:	605a      	str	r2, [r3, #4]
	node->next = NULL;
2000280e:	2300      	movs	r3, #0
	node->prev = NULL;
20002810:	e9c1 3300 	strd	r3, r3, [r1]
#endif

	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
}
20002814:	4770      	bx	lr
20002816:	bf00      	nop
20002818:	20020874 	.word	0x20020874

2000281c <update_cache>:
{
2000281c:	b570      	push	{r4, r5, r6, lr}
	struct k_thread *thread = _priq_run_best(&_kernel.ready_q.runq);
2000281e:	4c10      	ldr	r4, [pc, #64]	; (20002860 <update_cache+0x44>)
{
20002820:	4606      	mov	r6, r0
	struct k_thread *thread = _priq_run_best(&_kernel.ready_q.runq);
20002822:	f104 0028 	add.w	r0, r4, #40	; 0x28
20002826:	f001 fae7 	bl	20003df8 <z_priq_dumb_best>
2000282a:	4605      	mov	r5, r0
	if (_current->base.thread_state & _THREAD_ABORTING) {
2000282c:	68a3      	ldr	r3, [r4, #8]
2000282e:	7b59      	ldrb	r1, [r3, #13]
20002830:	0688      	lsls	r0, r1, #26
		_current->base.thread_state |= _THREAD_DEAD;
20002832:	bf44      	itt	mi
20002834:	f041 0108 	orrmi.w	r1, r1, #8
20002838:	7359      	strbmi	r1, [r3, #13]
	return thread ? thread : _current_cpu->idle_thread;
2000283a:	b905      	cbnz	r5, 2000283e <update_cache+0x22>
2000283c:	68e5      	ldr	r5, [r4, #12]
	if (preempt_ok != 0) {
2000283e:	b94e      	cbnz	r6, 20002854 <update_cache+0x38>
	if (z_is_thread_prevented_from_running(_current)) {
20002840:	7b5a      	ldrb	r2, [r3, #13]
20002842:	06d2      	lsls	r2, r2, #27
20002844:	d106      	bne.n	20002854 <update_cache+0x38>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
20002846:	69aa      	ldr	r2, [r5, #24]
20002848:	b922      	cbnz	r2, 20002854 <update_cache+0x38>
	if (is_preempt(_current) || is_metairq(thread)) {
2000284a:	89da      	ldrh	r2, [r3, #14]
2000284c:	2a7f      	cmp	r2, #127	; 0x7f
2000284e:	d901      	bls.n	20002854 <update_cache+0x38>
		_kernel.ready_q.cache = _current;
20002850:	6263      	str	r3, [r4, #36]	; 0x24
}
20002852:	bd70      	pop	{r4, r5, r6, pc}
		if (thread != _current) {
20002854:	42ab      	cmp	r3, r5
20002856:	d001      	beq.n	2000285c <update_cache+0x40>
			z_reset_time_slice();
20002858:	f7ff ff62 	bl	20002720 <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
2000285c:	6265      	str	r5, [r4, #36]	; 0x24
}
2000285e:	e7f8      	b.n	20002852 <update_cache+0x36>
20002860:	20020874 	.word	0x20020874

20002864 <k_sched_unlock>:
{
20002864:	b510      	push	{r4, lr}
	__asm__ volatile(
20002866:	f04f 0320 	mov.w	r3, #32
2000286a:	f3ef 8411 	mrs	r4, BASEPRI
2000286e:	f383 8811 	msr	BASEPRI, r3
20002872:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
20002876:	4b08      	ldr	r3, [pc, #32]	; (20002898 <k_sched_unlock+0x34>)
		update_cache(0);
20002878:	2000      	movs	r0, #0
		++_current->base.sched_locked;
2000287a:	689a      	ldr	r2, [r3, #8]
2000287c:	7bd3      	ldrb	r3, [r2, #15]
2000287e:	3301      	adds	r3, #1
20002880:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
20002882:	f7ff ffcb 	bl	2000281c <update_cache>
	__asm__ volatile(
20002886:	f384 8811 	msr	BASEPRI, r4
2000288a:	f3bf 8f6f 	isb	sy
}
2000288e:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
20002892:	f001 ba9b 	b.w	20003dcc <z_reschedule_unlocked>
20002896:	bf00      	nop
20002898:	20020874 	.word	0x20020874

2000289c <ready_thread>:
{
2000289c:	b470      	push	{r4, r5, r6}
	return !((z_is_thread_prevented_from_running(thread)) != 0 ||
2000289e:	7b43      	ldrb	r3, [r0, #13]
200028a0:	06db      	lsls	r3, r3, #27
200028a2:	d12a      	bne.n	200028fa <ready_thread+0x5e>

int z_abort_timeout(struct _timeout *to);

static inline bool z_is_inactive_timeout(struct _timeout *t)
{
	return !sys_dnode_is_linked(&t->node);
200028a4:	6983      	ldr	r3, [r0, #24]
	if (z_is_thread_ready(thread)) {
200028a6:	bb43      	cbnz	r3, 200028fa <ready_thread+0x5e>
	return list->head == list;
200028a8:	4a15      	ldr	r2, [pc, #84]	; (20002900 <ready_thread+0x64>)
200028aa:	4611      	mov	r1, r2
200028ac:	f851 4f28 	ldr.w	r4, [r1, #40]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
200028b0:	428c      	cmp	r4, r1
200028b2:	bf18      	it	ne
200028b4:	4623      	movne	r3, r4
200028b6:	2b00      	cmp	r3, #0
200028b8:	bf38      	it	cc
200028ba:	2300      	movcc	r3, #0
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
200028bc:	6ad4      	ldr	r4, [r2, #44]	; 0x2c
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
200028be:	b1b3      	cbz	r3, 200028ee <ready_thread+0x52>
	if (thread_1->base.prio < thread_2->base.prio) {
200028c0:	f990 600e 	ldrsb.w	r6, [r0, #14]
200028c4:	f993 500e 	ldrsb.w	r5, [r3, #14]
200028c8:	42ae      	cmp	r6, r5
200028ca:	db03      	blt.n	200028d4 <ready_thread+0x38>
	return (node == list->tail) ? NULL : node->next;
200028cc:	42a3      	cmp	r3, r4
200028ce:	d00e      	beq.n	200028ee <ready_thread+0x52>
200028d0:	681b      	ldr	r3, [r3, #0]
200028d2:	e7f4      	b.n	200028be <ready_thread+0x22>
	node->prev = successor->prev;
200028d4:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
200028d6:	e9c0 3200 	strd	r3, r2, [r0]
	successor->prev->next = node;
200028da:	6010      	str	r0, [r2, #0]
	successor->prev = node;
200028dc:	6058      	str	r0, [r3, #4]
	thread->base.thread_state |= states;
200028de:	7b43      	ldrb	r3, [r0, #13]
200028e0:	f063 037f 	orn	r3, r3, #127	; 0x7f
200028e4:	7343      	strb	r3, [r0, #13]
}
200028e6:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
200028e8:	2000      	movs	r0, #0
200028ea:	f7ff bf97 	b.w	2000281c <update_cache>
	node->prev = list->tail;
200028ee:	e9c0 1400 	strd	r1, r4, [r0]
	list->tail->next = node;
200028f2:	6ad3      	ldr	r3, [r2, #44]	; 0x2c
200028f4:	6018      	str	r0, [r3, #0]
	list->tail = node;
200028f6:	62d0      	str	r0, [r2, #44]	; 0x2c
}
200028f8:	e7f1      	b.n	200028de <ready_thread+0x42>
}
200028fa:	bc70      	pop	{r4, r5, r6}
200028fc:	4770      	bx	lr
200028fe:	bf00      	nop
20002900:	20020874 	.word	0x20020874

20002904 <z_sched_start>:
{
20002904:	b510      	push	{r4, lr}
	__asm__ volatile(
20002906:	f04f 0220 	mov.w	r2, #32
2000290a:	f3ef 8411 	mrs	r4, BASEPRI
2000290e:	f382 8811 	msr	BASEPRI, r2
20002912:	f3bf 8f6f 	isb	sy
	if (z_has_thread_started(thread)) {
20002916:	7b42      	ldrb	r2, [r0, #13]
20002918:	0751      	lsls	r1, r2, #29
2000291a:	d404      	bmi.n	20002926 <z_sched_start+0x22>
	__asm__ volatile(
2000291c:	f384 8811 	msr	BASEPRI, r4
20002920:	f3bf 8f6f 	isb	sy
}
20002924:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
20002926:	f022 0204 	bic.w	r2, r2, #4
2000292a:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
2000292c:	f7ff ffb6 	bl	2000289c <ready_thread>
	z_reschedule(&sched_spinlock, key);
20002930:	4621      	mov	r1, r4
}
20002932:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
20002936:	4801      	ldr	r0, [pc, #4]	; (2000293c <z_sched_start+0x38>)
20002938:	f7ff bf34 	b.w	200027a4 <z_reschedule>
2000293c:	200208cf 	.word	0x200208cf

20002940 <move_thread_to_end_of_prio_q>:
{
20002940:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
20002942:	f990 300d 	ldrsb.w	r3, [r0, #13]
{
20002946:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
20002948:	2b00      	cmp	r3, #0
2000294a:	da02      	bge.n	20002952 <move_thread_to_end_of_prio_q+0x12>
		_priq_run_remove(&_kernel.ready_q.runq, thread);
2000294c:	4817      	ldr	r0, [pc, #92]	; (200029ac <move_thread_to_end_of_prio_q+0x6c>)
2000294e:	f7ff ff4f 	bl	200027f0 <z_priq_dumb_remove>
	return list->head == list;
20002952:	4a17      	ldr	r2, [pc, #92]	; (200029b0 <move_thread_to_end_of_prio_q+0x70>)
20002954:	4610      	mov	r0, r2
20002956:	f850 3f28 	ldr.w	r3, [r0, #40]!
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
2000295a:	6ad4      	ldr	r4, [r2, #44]	; 0x2c
	return sys_dlist_is_empty(list) ? NULL : list->head;
2000295c:	4283      	cmp	r3, r0
2000295e:	bf08      	it	eq
20002960:	2300      	moveq	r3, #0
20002962:	2b00      	cmp	r3, #0
20002964:	bf38      	it	cc
20002966:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
20002968:	b1d3      	cbz	r3, 200029a0 <move_thread_to_end_of_prio_q+0x60>
	if (thread_1->base.prio < thread_2->base.prio) {
2000296a:	f991 600e 	ldrsb.w	r6, [r1, #14]
2000296e:	f993 500e 	ldrsb.w	r5, [r3, #14]
20002972:	42ae      	cmp	r6, r5
20002974:	db03      	blt.n	2000297e <move_thread_to_end_of_prio_q+0x3e>
	return (node == list->tail) ? NULL : node->next;
20002976:	42a3      	cmp	r3, r4
20002978:	d012      	beq.n	200029a0 <move_thread_to_end_of_prio_q+0x60>
2000297a:	681b      	ldr	r3, [r3, #0]
2000297c:	e7f4      	b.n	20002968 <move_thread_to_end_of_prio_q+0x28>
	node->prev = successor->prev;
2000297e:	6858      	ldr	r0, [r3, #4]
	node->next = successor;
20002980:	e9c1 3000 	strd	r3, r0, [r1]
	successor->prev->next = node;
20002984:	6001      	str	r1, [r0, #0]
	successor->prev = node;
20002986:	6059      	str	r1, [r3, #4]
	thread->base.thread_state |= states;
20002988:	7b4b      	ldrb	r3, [r1, #13]
	update_cache(thread == _current);
2000298a:	6890      	ldr	r0, [r2, #8]
2000298c:	f063 037f 	orn	r3, r3, #127	; 0x7f
20002990:	734b      	strb	r3, [r1, #13]
20002992:	1a43      	subs	r3, r0, r1
20002994:	4258      	negs	r0, r3
20002996:	4158      	adcs	r0, r3
}
20002998:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
2000299c:	f7ff bf3e 	b.w	2000281c <update_cache>
	node->prev = list->tail;
200029a0:	e9c1 0400 	strd	r0, r4, [r1]
	list->tail->next = node;
200029a4:	6ad3      	ldr	r3, [r2, #44]	; 0x2c
200029a6:	6019      	str	r1, [r3, #0]
	list->tail = node;
200029a8:	62d1      	str	r1, [r2, #44]	; 0x2c
}
200029aa:	e7ed      	b.n	20002988 <move_thread_to_end_of_prio_q+0x48>
200029ac:	2002089c 	.word	0x2002089c
200029b0:	20020874 	.word	0x20020874

200029b4 <z_time_slice>:
{
200029b4:	4601      	mov	r1, r0
200029b6:	b570      	push	{r4, r5, r6, lr}
	__asm__ volatile(
200029b8:	f04f 0320 	mov.w	r3, #32
200029bc:	f3ef 8411 	mrs	r4, BASEPRI
200029c0:	f383 8811 	msr	BASEPRI, r3
200029c4:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
200029c8:	4b16      	ldr	r3, [pc, #88]	; (20002a24 <z_time_slice+0x70>)
200029ca:	4a17      	ldr	r2, [pc, #92]	; (20002a28 <z_time_slice+0x74>)
200029cc:	6898      	ldr	r0, [r3, #8]
200029ce:	6815      	ldr	r5, [r2, #0]
200029d0:	42a8      	cmp	r0, r5
200029d2:	461d      	mov	r5, r3
200029d4:	d106      	bne.n	200029e4 <z_time_slice+0x30>
			z_reset_time_slice();
200029d6:	f7ff fea3 	bl	20002720 <z_reset_time_slice>
	__asm__ volatile(
200029da:	f384 8811 	msr	BASEPRI, r4
200029de:	f3bf 8f6f 	isb	sy
}
200029e2:	bd70      	pop	{r4, r5, r6, pc}
	pending_current = NULL;
200029e4:	2600      	movs	r6, #0
200029e6:	6016      	str	r6, [r2, #0]
	if (slice_time && sliceable(_current)) {
200029e8:	4a10      	ldr	r2, [pc, #64]	; (20002a2c <z_time_slice+0x78>)
200029ea:	6812      	ldr	r2, [r2, #0]
200029ec:	b1ba      	cbz	r2, 20002a1e <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
200029ee:	89c2      	ldrh	r2, [r0, #14]
200029f0:	2a7f      	cmp	r2, #127	; 0x7f
200029f2:	d814      	bhi.n	20002a1e <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
200029f4:	7b42      	ldrb	r2, [r0, #13]
200029f6:	06d2      	lsls	r2, r2, #27
200029f8:	d111      	bne.n	20002a1e <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
200029fa:	4a0d      	ldr	r2, [pc, #52]	; (20002a30 <z_time_slice+0x7c>)
200029fc:	f990 600e 	ldrsb.w	r6, [r0, #14]
20002a00:	6812      	ldr	r2, [r2, #0]
20002a02:	4296      	cmp	r6, r2
20002a04:	db0b      	blt.n	20002a1e <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
20002a06:	4a0b      	ldr	r2, [pc, #44]	; (20002a34 <z_time_slice+0x80>)
20002a08:	4290      	cmp	r0, r2
20002a0a:	d008      	beq.n	20002a1e <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
20002a0c:	691a      	ldr	r2, [r3, #16]
20002a0e:	428a      	cmp	r2, r1
20002a10:	dc02      	bgt.n	20002a18 <z_time_slice+0x64>
			move_thread_to_end_of_prio_q(_current);
20002a12:	f7ff ff95 	bl	20002940 <move_thread_to_end_of_prio_q>
20002a16:	e7de      	b.n	200029d6 <z_time_slice+0x22>
			_current_cpu->slice_ticks -= ticks;
20002a18:	1a52      	subs	r2, r2, r1
20002a1a:	611a      	str	r2, [r3, #16]
20002a1c:	e7dd      	b.n	200029da <z_time_slice+0x26>
		_current_cpu->slice_ticks = 0;
20002a1e:	2300      	movs	r3, #0
20002a20:	612b      	str	r3, [r5, #16]
20002a22:	e7da      	b.n	200029da <z_time_slice+0x26>
20002a24:	20020874 	.word	0x20020874
20002a28:	200208a4 	.word	0x200208a4
20002a2c:	200208ac 	.word	0x200208ac
20002a30:	200208a8 	.word	0x200208a8
20002a34:	20020160 	.word	0x20020160

20002a38 <z_impl_k_thread_suspend>:
{
20002a38:	b570      	push	{r4, r5, r6, lr}
20002a3a:	4604      	mov	r4, r0
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
20002a3c:	3018      	adds	r0, #24
20002a3e:	f001 fa6d 	bl	20003f1c <z_abort_timeout>
	__asm__ volatile(
20002a42:	f04f 0320 	mov.w	r3, #32
20002a46:	f3ef 8611 	mrs	r6, BASEPRI
20002a4a:	f383 8811 	msr	BASEPRI, r3
20002a4e:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
20002a52:	f994 300d 	ldrsb.w	r3, [r4, #13]
20002a56:	2b00      	cmp	r3, #0
20002a58:	da07      	bge.n	20002a6a <z_impl_k_thread_suspend+0x32>
			_priq_run_remove(&_kernel.ready_q.runq, thread);
20002a5a:	4621      	mov	r1, r4
20002a5c:	480e      	ldr	r0, [pc, #56]	; (20002a98 <z_impl_k_thread_suspend+0x60>)
20002a5e:	f7ff fec7 	bl	200027f0 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
20002a62:	7b63      	ldrb	r3, [r4, #13]
20002a64:	f003 037f 	and.w	r3, r3, #127	; 0x7f
20002a68:	7363      	strb	r3, [r4, #13]
		update_cache(thread == _current);
20002a6a:	4d0c      	ldr	r5, [pc, #48]	; (20002a9c <z_impl_k_thread_suspend+0x64>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
20002a6c:	7b63      	ldrb	r3, [r4, #13]
20002a6e:	68a8      	ldr	r0, [r5, #8]
20002a70:	f043 0310 	orr.w	r3, r3, #16
20002a74:	7363      	strb	r3, [r4, #13]
20002a76:	1b03      	subs	r3, r0, r4
20002a78:	4258      	negs	r0, r3
20002a7a:	4158      	adcs	r0, r3
20002a7c:	f7ff fece 	bl	2000281c <update_cache>
	__asm__ volatile(
20002a80:	f386 8811 	msr	BASEPRI, r6
20002a84:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
20002a88:	68ab      	ldr	r3, [r5, #8]
20002a8a:	42a3      	cmp	r3, r4
20002a8c:	d103      	bne.n	20002a96 <z_impl_k_thread_suspend+0x5e>
}
20002a8e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
20002a92:	f001 b99b 	b.w	20003dcc <z_reschedule_unlocked>
}
20002a96:	bd70      	pop	{r4, r5, r6, pc}
20002a98:	2002089c 	.word	0x2002089c
20002a9c:	20020874 	.word	0x20020874

20002aa0 <z_thread_single_abort>:
	if (thread->fn_abort != NULL) {
20002aa0:	6e03      	ldr	r3, [r0, #96]	; 0x60
{
20002aa2:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
20002aa6:	4604      	mov	r4, r0
	if (thread->fn_abort != NULL) {
20002aa8:	b103      	cbz	r3, 20002aac <z_thread_single_abort+0xc>
		thread->fn_abort();
20002aaa:	4798      	blx	r3
20002aac:	f104 0018 	add.w	r0, r4, #24
20002ab0:	f001 fa34 	bl	20003f1c <z_abort_timeout>
	__asm__ volatile(
20002ab4:	f04f 0320 	mov.w	r3, #32
20002ab8:	f3ef 8611 	mrs	r6, BASEPRI
20002abc:	f383 8811 	msr	BASEPRI, r3
20002ac0:	f3bf 8f6f 	isb	sy
	return !((z_is_thread_prevented_from_running(thread)) != 0 ||
20002ac4:	7b63      	ldrb	r3, [r4, #13]
20002ac6:	06d8      	lsls	r0, r3, #27
20002ac8:	d123      	bne.n	20002b12 <z_thread_single_abort+0x72>
		if (z_is_thread_ready(thread)) {
20002aca:	69a2      	ldr	r2, [r4, #24]
20002acc:	bb0a      	cbnz	r2, 20002b12 <z_thread_single_abort+0x72>
			if (z_is_thread_queued(thread)) {
20002ace:	0619      	lsls	r1, r3, #24
20002ad0:	d507      	bpl.n	20002ae2 <z_thread_single_abort+0x42>
				_priq_run_remove(&_kernel.ready_q.runq,
20002ad2:	4621      	mov	r1, r4
20002ad4:	481e      	ldr	r0, [pc, #120]	; (20002b50 <z_thread_single_abort+0xb0>)
20002ad6:	f7ff fe8b 	bl	200027f0 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
20002ada:	7b63      	ldrb	r3, [r4, #13]
20002adc:	f003 037f 	and.w	r3, r3, #127	; 0x7f
20002ae0:	7363      	strb	r3, [r4, #13]
			update_cache(thread == _current);
20002ae2:	4b1c      	ldr	r3, [pc, #112]	; (20002b54 <z_thread_single_abort+0xb4>)
20002ae4:	6898      	ldr	r0, [r3, #8]
20002ae6:	1b02      	subs	r2, r0, r4
20002ae8:	4250      	negs	r0, r2
20002aea:	4150      	adcs	r0, r2
20002aec:	f7ff fe96 	bl	2000281c <update_cache>
			waiter->base.pended_on = NULL;
20002af0:	2700      	movs	r7, #0
		thread->base.thread_state |= mask;
20002af2:	7b63      	ldrb	r3, [r4, #13]
	sys_dlist_init(&w->waitq);
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
20002af4:	f104 0830 	add.w	r8, r4, #48	; 0x30
20002af8:	f043 0308 	orr.w	r3, r3, #8
20002afc:	7363      	strb	r3, [r4, #13]
	return list->head == list;
20002afe:	6b25      	ldr	r5, [r4, #48]	; 0x30
	return sys_dlist_is_empty(list) ? NULL : list->head;
20002b00:	4545      	cmp	r5, r8
20002b02:	d000      	beq.n	20002b06 <z_thread_single_abort+0x66>
		while ((waiter = z_waitq_head(&thread->base.join_waiters)) !=
20002b04:	b995      	cbnz	r5, 20002b2c <z_thread_single_abort+0x8c>
	__asm__ volatile(
20002b06:	f386 8811 	msr	BASEPRI, r6
20002b0a:	f3bf 8f6f 	isb	sy
}
20002b0e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
			if (z_is_thread_pending(thread)) {
20002b12:	079b      	lsls	r3, r3, #30
20002b14:	d5ec      	bpl.n	20002af0 <z_thread_single_abort+0x50>
				_priq_wait_remove(&pended_on(thread)->waitq,
20002b16:	4621      	mov	r1, r4
20002b18:	68a0      	ldr	r0, [r4, #8]
20002b1a:	f7ff fe69 	bl	200027f0 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
20002b1e:	7b63      	ldrb	r3, [r4, #13]
20002b20:	f023 0302 	bic.w	r3, r3, #2
20002b24:	7363      	strb	r3, [r4, #13]
				thread->base.pended_on = NULL;
20002b26:	2300      	movs	r3, #0
20002b28:	60a3      	str	r3, [r4, #8]
20002b2a:	e7e1      	b.n	20002af0 <z_thread_single_abort+0x50>
20002b2c:	f105 0018 	add.w	r0, r5, #24
20002b30:	f001 f9f4 	bl	20003f1c <z_abort_timeout>
			_priq_wait_remove(&pended_on(waiter)->waitq, waiter);
20002b34:	68a8      	ldr	r0, [r5, #8]
20002b36:	4629      	mov	r1, r5
20002b38:	f7ff fe5a 	bl	200027f0 <z_priq_dumb_remove>
20002b3c:	7b6b      	ldrb	r3, [r5, #13]
			ready_thread(waiter);
20002b3e:	4628      	mov	r0, r5
20002b40:	f023 0302 	bic.w	r3, r3, #2
20002b44:	736b      	strb	r3, [r5, #13]
			waiter->base.pended_on = NULL;
20002b46:	60af      	str	r7, [r5, #8]
20002b48:	67ef      	str	r7, [r5, #124]	; 0x7c
			ready_thread(waiter);
20002b4a:	f7ff fea7 	bl	2000289c <ready_thread>
20002b4e:	e7d6      	b.n	20002afe <z_thread_single_abort+0x5e>
20002b50:	2002089c 	.word	0x2002089c
20002b54:	20020874 	.word	0x20020874

20002b58 <unready_thread>:
{
20002b58:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
20002b5a:	f990 300d 	ldrsb.w	r3, [r0, #13]
{
20002b5e:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
20002b60:	2b00      	cmp	r3, #0
20002b62:	da06      	bge.n	20002b72 <unready_thread+0x1a>
		_priq_run_remove(&_kernel.ready_q.runq, thread);
20002b64:	4807      	ldr	r0, [pc, #28]	; (20002b84 <unready_thread+0x2c>)
20002b66:	f7ff fe43 	bl	200027f0 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
20002b6a:	7b4b      	ldrb	r3, [r1, #13]
20002b6c:	f003 037f 	and.w	r3, r3, #127	; 0x7f
20002b70:	734b      	strb	r3, [r1, #13]
	update_cache(thread == _current);
20002b72:	4b05      	ldr	r3, [pc, #20]	; (20002b88 <unready_thread+0x30>)
20002b74:	6898      	ldr	r0, [r3, #8]
20002b76:	1a43      	subs	r3, r0, r1
20002b78:	4258      	negs	r0, r3
20002b7a:	4158      	adcs	r0, r3
}
20002b7c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
20002b80:	f7ff be4c 	b.w	2000281c <update_cache>
20002b84:	2002089c 	.word	0x2002089c
20002b88:	20020874 	.word	0x20020874

20002b8c <pend>:
{
20002b8c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
20002b90:	4606      	mov	r6, r0
20002b92:	4614      	mov	r4, r2
20002b94:	461d      	mov	r5, r3
	__asm__ volatile(
20002b96:	f04f 0320 	mov.w	r3, #32
20002b9a:	f3ef 8711 	mrs	r7, BASEPRI
20002b9e:	f383 8811 	msr	BASEPRI, r3
20002ba2:	f3bf 8f6f 	isb	sy
		add_to_waitq_locked(thread, wait_q);
20002ba6:	f001 f961 	bl	20003e6c <add_to_waitq_locked>
	__asm__ volatile(
20002baa:	f387 8811 	msr	BASEPRI, r7
20002bae:	f3bf 8f6f 	isb	sy
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
20002bb2:	1c6b      	adds	r3, r5, #1
20002bb4:	bf08      	it	eq
20002bb6:	f1b4 3fff 	cmpeq.w	r4, #4294967295
20002bba:	d008      	beq.n	20002bce <pend+0x42>
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
20002bbc:	4622      	mov	r2, r4
20002bbe:	462b      	mov	r3, r5
20002bc0:	f106 0018 	add.w	r0, r6, #24
20002bc4:	4903      	ldr	r1, [pc, #12]	; (20002bd4 <pend+0x48>)
}
20002bc6:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
20002bca:	f000 ba2f 	b.w	2000302c <z_add_timeout>
20002bce:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
20002bd2:	bf00      	nop
20002bd4:	20003e2d 	.word	0x20003e2d

20002bd8 <z_pend_curr>:
{
20002bd8:	b510      	push	{r4, lr}
20002bda:	460c      	mov	r4, r1
	pending_current = _current;
20002bdc:	4b06      	ldr	r3, [pc, #24]	; (20002bf8 <z_pend_curr+0x20>)
{
20002bde:	4611      	mov	r1, r2
	pending_current = _current;
20002be0:	6898      	ldr	r0, [r3, #8]
20002be2:	4b06      	ldr	r3, [pc, #24]	; (20002bfc <z_pend_curr+0x24>)
20002be4:	6018      	str	r0, [r3, #0]
	pend(_current, wait_q, timeout);
20002be6:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
20002bea:	f7ff ffcf 	bl	20002b8c <pend>
20002bee:	4620      	mov	r0, r4
}
20002bf0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
20002bf4:	f7fe ba6c 	b.w	200010d0 <arch_swap>
20002bf8:	20020874 	.word	0x20020874
20002bfc:	200208a4 	.word	0x200208a4

20002c00 <z_tick_sleep.part.0>:
	z_impl_k_yield();
}
#include <syscalls/k_yield_mrsh.c>
#endif

static int32_t z_tick_sleep(int32_t ticks)
20002c00:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
20002c02:	4605      	mov	r5, r0
#else
	ticks += _TICK_ALIGN;
	timeout = (k_ticks_t) ticks;
#endif

	expected_wakeup_time = ticks + z_tick_get_32();
20002c04:	f001 f9ca 	bl	20003f9c <z_tick_get_32>
20002c08:	182c      	adds	r4, r5, r0
	__asm__ volatile(
20002c0a:	f04f 0320 	mov.w	r3, #32
20002c0e:	f3ef 8711 	mrs	r7, BASEPRI
20002c12:	f383 8811 	msr	BASEPRI, r3
20002c16:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

#if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC)
	pending_current = _current;
20002c1a:	4e0d      	ldr	r6, [pc, #52]	; (20002c50 <z_tick_sleep.part.0+0x50>)
20002c1c:	4b0d      	ldr	r3, [pc, #52]	; (20002c54 <z_tick_sleep.part.0+0x54>)
20002c1e:	68b0      	ldr	r0, [r6, #8]
20002c20:	6018      	str	r0, [r3, #0]
#endif
	unready_thread(_current);
20002c22:	f7ff ff99 	bl	20002b58 <unready_thread>
	z_add_thread_timeout(_current, timeout);
20002c26:	68b0      	ldr	r0, [r6, #8]
20002c28:	490b      	ldr	r1, [pc, #44]	; (20002c58 <z_tick_sleep.part.0+0x58>)
20002c2a:	462a      	mov	r2, r5
20002c2c:	17eb      	asrs	r3, r5, #31
20002c2e:	3018      	adds	r0, #24
20002c30:	f000 f9fc 	bl	2000302c <z_add_timeout>
	z_mark_thread_as_suspended(_current);
20002c34:	68b2      	ldr	r2, [r6, #8]
20002c36:	4638      	mov	r0, r7
	thread->base.thread_state |= _THREAD_SUSPENDED;
20002c38:	7b53      	ldrb	r3, [r2, #13]
20002c3a:	f043 0310 	orr.w	r3, r3, #16
20002c3e:	7353      	strb	r3, [r2, #13]
20002c40:	f7fe fa46 	bl	200010d0 <arch_swap>

	(void)z_swap(&sched_spinlock, key);

	__ASSERT(!z_is_thread_state_set(_current, _THREAD_SUSPENDED), "");

	ticks = expected_wakeup_time - z_tick_get_32();
20002c44:	f001 f9aa 	bl	20003f9c <z_tick_get_32>
20002c48:	1a20      	subs	r0, r4, r0
		return ticks;
	}
#endif

	return 0;
}
20002c4a:	ea20 70e0 	bic.w	r0, r0, r0, asr #31
20002c4e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
20002c50:	20020874 	.word	0x20020874
20002c54:	200208a4 	.word	0x200208a4
20002c58:	20003e2d 	.word	0x20003e2d

20002c5c <z_set_prio>:
{
20002c5c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
20002c60:	4604      	mov	r4, r0
20002c62:	f04f 0320 	mov.w	r3, #32
20002c66:	f3ef 8811 	mrs	r8, BASEPRI
20002c6a:	f383 8811 	msr	BASEPRI, r3
20002c6e:	f3bf 8f6f 	isb	sy
	return !((z_is_thread_prevented_from_running(thread)) != 0 ||
20002c72:	7b43      	ldrb	r3, [r0, #13]
20002c74:	b24e      	sxtb	r6, r1
20002c76:	06db      	lsls	r3, r3, #27
20002c78:	d12e      	bne.n	20002cd8 <z_set_prio+0x7c>
	return !sys_dnode_is_linked(&t->node);
20002c7a:	6985      	ldr	r5, [r0, #24]
		if (need_sched) {
20002c7c:	bb65      	cbnz	r5, 20002cd8 <z_set_prio+0x7c>
				_priq_run_remove(&_kernel.ready_q.runq, thread);
20002c7e:	4f18      	ldr	r7, [pc, #96]	; (20002ce0 <z_set_prio+0x84>)
20002c80:	4621      	mov	r1, r4
20002c82:	f107 0028 	add.w	r0, r7, #40	; 0x28
20002c86:	f7ff fdb3 	bl	200027f0 <z_priq_dumb_remove>
	return list->head == list;
20002c8a:	6abb      	ldr	r3, [r7, #40]	; 0x28
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
20002c8c:	6afa      	ldr	r2, [r7, #44]	; 0x2c
	return sys_dlist_is_empty(list) ? NULL : list->head;
20002c8e:	4283      	cmp	r3, r0
20002c90:	bf18      	it	ne
20002c92:	461d      	movne	r5, r3
20002c94:	2d00      	cmp	r5, #0
20002c96:	bf38      	it	cc
20002c98:	2500      	movcc	r5, #0
				thread->base.prio = prio;
20002c9a:	73a6      	strb	r6, [r4, #14]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
20002c9c:	b1b5      	cbz	r5, 20002ccc <z_set_prio+0x70>
	if (thread_1->base.prio < thread_2->base.prio) {
20002c9e:	f995 100e 	ldrsb.w	r1, [r5, #14]
20002ca2:	42b1      	cmp	r1, r6
20002ca4:	dc03      	bgt.n	20002cae <z_set_prio+0x52>
	return (node == list->tail) ? NULL : node->next;
20002ca6:	42aa      	cmp	r2, r5
20002ca8:	d010      	beq.n	20002ccc <z_set_prio+0x70>
20002caa:	682d      	ldr	r5, [r5, #0]
20002cac:	e7f6      	b.n	20002c9c <z_set_prio+0x40>
	node->prev = successor->prev;
20002cae:	686a      	ldr	r2, [r5, #4]
	node->next = successor;
20002cb0:	e9c4 5200 	strd	r5, r2, [r4]
	successor->prev->next = node;
20002cb4:	6014      	str	r4, [r2, #0]
	successor->prev = node;
20002cb6:	606c      	str	r4, [r5, #4]
			update_cache(1);
20002cb8:	2001      	movs	r0, #1
20002cba:	f7ff fdaf 	bl	2000281c <update_cache>
20002cbe:	2001      	movs	r0, #1
	__asm__ volatile(
20002cc0:	f388 8811 	msr	BASEPRI, r8
20002cc4:	f3bf 8f6f 	isb	sy
}
20002cc8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	node->prev = list->tail;
20002ccc:	e9c4 0200 	strd	r0, r2, [r4]
	list->tail->next = node;
20002cd0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
20002cd2:	601c      	str	r4, [r3, #0]
	list->tail = node;
20002cd4:	62fc      	str	r4, [r7, #44]	; 0x2c
}
20002cd6:	e7ef      	b.n	20002cb8 <z_set_prio+0x5c>
			thread->base.prio = prio;
20002cd8:	2000      	movs	r0, #0
20002cda:	73a6      	strb	r6, [r4, #14]
20002cdc:	e7f0      	b.n	20002cc0 <z_set_prio+0x64>
20002cde:	bf00      	nop
20002ce0:	20020874 	.word	0x20020874

20002ce4 <z_sched_init>:
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
20002ce4:	2100      	movs	r1, #0
	list->head = (sys_dnode_t *)list;
20002ce6:	4b04      	ldr	r3, [pc, #16]	; (20002cf8 <z_sched_init+0x14>)
20002ce8:	4608      	mov	r0, r1
20002cea:	f103 0228 	add.w	r2, r3, #40	; 0x28
	list->tail = (sys_dnode_t *)list;
20002cee:	e9c3 220a 	strd	r2, r2, [r3, #40]	; 0x28
20002cf2:	f7ff bd2b 	b.w	2000274c <k_sched_time_slice_set>
20002cf6:	bf00      	nop
20002cf8:	20020874 	.word	0x20020874

20002cfc <z_impl_k_yield>:
{
20002cfc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	if (!z_is_idle_thread_object(_current)) {
20002cfe:	4c24      	ldr	r4, [pc, #144]	; (20002d90 <z_impl_k_yield+0x94>)
20002d00:	4b24      	ldr	r3, [pc, #144]	; (20002d94 <z_impl_k_yield+0x98>)
20002d02:	68a2      	ldr	r2, [r4, #8]
20002d04:	429a      	cmp	r2, r3
20002d06:	d030      	beq.n	20002d6a <z_impl_k_yield+0x6e>
	__asm__ volatile(
20002d08:	f04f 0320 	mov.w	r3, #32
20002d0c:	f3ef 8511 	mrs	r5, BASEPRI
20002d10:	f383 8811 	msr	BASEPRI, r3
20002d14:	f3bf 8f6f 	isb	sy
				_priq_run_remove(&_kernel.ready_q.runq,
20002d18:	68a1      	ldr	r1, [r4, #8]
20002d1a:	f104 0028 	add.w	r0, r4, #40	; 0x28
20002d1e:	f7ff fd67 	bl	200027f0 <z_priq_dumb_remove>
	return list->head == list;
20002d22:	6aa3      	ldr	r3, [r4, #40]	; 0x28
			_priq_run_add(&_kernel.ready_q.runq, _current);
20002d24:	68a2      	ldr	r2, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
20002d26:	4283      	cmp	r3, r0
20002d28:	bf08      	it	eq
20002d2a:	2300      	moveq	r3, #0
20002d2c:	2b00      	cmp	r3, #0
20002d2e:	bf38      	it	cc
20002d30:	2300      	movcc	r3, #0
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
20002d32:	6ae1      	ldr	r1, [r4, #44]	; 0x2c
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
20002d34:	b32b      	cbz	r3, 20002d82 <z_impl_k_yield+0x86>
	if (thread_1->base.prio < thread_2->base.prio) {
20002d36:	f992 700e 	ldrsb.w	r7, [r2, #14]
20002d3a:	f993 600e 	ldrsb.w	r6, [r3, #14]
20002d3e:	42b7      	cmp	r7, r6
20002d40:	db03      	blt.n	20002d4a <z_impl_k_yield+0x4e>
	return (node == list->tail) ? NULL : node->next;
20002d42:	428b      	cmp	r3, r1
20002d44:	d01d      	beq.n	20002d82 <z_impl_k_yield+0x86>
20002d46:	681b      	ldr	r3, [r3, #0]
20002d48:	e7f4      	b.n	20002d34 <z_impl_k_yield+0x38>
	node->prev = successor->prev;
20002d4a:	6859      	ldr	r1, [r3, #4]
	node->next = successor;
20002d4c:	e9c2 3100 	strd	r3, r1, [r2]
	successor->prev->next = node;
20002d50:	600a      	str	r2, [r1, #0]
	successor->prev = node;
20002d52:	605a      	str	r2, [r3, #4]
	thread->base.thread_state |= states;
20002d54:	7b53      	ldrb	r3, [r2, #13]
			update_cache(1);
20002d56:	2001      	movs	r0, #1
20002d58:	f063 037f 	orn	r3, r3, #127	; 0x7f
20002d5c:	7353      	strb	r3, [r2, #13]
20002d5e:	f7ff fd5d 	bl	2000281c <update_cache>
	__asm__ volatile(
20002d62:	f385 8811 	msr	BASEPRI, r5
20002d66:	f3bf 8f6f 	isb	sy
	__asm__ volatile(
20002d6a:	f04f 0320 	mov.w	r3, #32
20002d6e:	f3ef 8011 	mrs	r0, BASEPRI
20002d72:	f383 8811 	msr	BASEPRI, r3
20002d76:	f3bf 8f6f 	isb	sy
}
20002d7a:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
20002d7e:	f7fe b9a7 	b.w	200010d0 <arch_swap>
	node->prev = list->tail;
20002d82:	e9c2 0100 	strd	r0, r1, [r2]
	list->tail->next = node;
20002d86:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
20002d88:	601a      	str	r2, [r3, #0]
	list->tail = node;
20002d8a:	62e2      	str	r2, [r4, #44]	; 0x2c
}
20002d8c:	e7e2      	b.n	20002d54 <z_impl_k_yield+0x58>
20002d8e:	bf00      	nop
20002d90:	20020874 	.word	0x20020874
20002d94:	20020160 	.word	0x20020160

20002d98 <z_impl_k_sleep>:

int32_t z_impl_k_sleep(k_timeout_t timeout)
{
20002d98:	460b      	mov	r3, r1
	k_ticks_t ticks;

	__ASSERT(!arch_is_in_isr(), "");
	sys_trace_void(SYS_TRACE_ID_SLEEP);

	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
20002d9a:	3301      	adds	r3, #1
20002d9c:	bf08      	it	eq
20002d9e:	f1b0 3fff 	cmpeq.w	r0, #4294967295
{
20002da2:	b510      	push	{r4, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
20002da4:	d106      	bne.n	20002db4 <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
20002da6:	4b0b      	ldr	r3, [pc, #44]	; (20002dd4 <z_impl_k_sleep+0x3c>)
20002da8:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
20002daa:	f7ff fe45 	bl	20002a38 <z_impl_k_thread_suspend>
		return (int32_t) K_TICKS_FOREVER;
20002dae:	f04f 30ff 	mov.w	r0, #4294967295
#endif

	ticks = z_tick_sleep(ticks);
	sys_trace_end_call(SYS_TRACE_ID_SLEEP);
	return k_ticks_to_ms_floor64(ticks);
}
20002db2:	bd10      	pop	{r4, pc}
	ticks = z_tick_sleep(ticks);
20002db4:	4604      	mov	r4, r0
	if (ticks == 0) {
20002db6:	b948      	cbnz	r0, 20002dcc <z_impl_k_sleep+0x34>
	z_impl_k_yield();
20002db8:	f7ff ffa0 	bl	20002cfc <z_impl_k_yield>
		} else {
			return (t * to_hz + off) / from_hz;
20002dbc:	f44f 707a 	mov.w	r0, #1000	; 0x3e8
20002dc0:	fb84 3400 	smull	r3, r4, r4, r0
20002dc4:	0bd8      	lsrs	r0, r3, #15
20002dc6:	ea40 4044 	orr.w	r0, r0, r4, lsl #17
	return k_ticks_to_ms_floor64(ticks);
20002dca:	e7f2      	b.n	20002db2 <z_impl_k_sleep+0x1a>
20002dcc:	f7ff ff18 	bl	20002c00 <z_tick_sleep.part.0>
20002dd0:	4604      	mov	r4, r0
20002dd2:	e7f3      	b.n	20002dbc <z_impl_k_sleep+0x24>
20002dd4:	20020874 	.word	0x20020874

20002dd8 <z_impl_k_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
20002dd8:	4b01      	ldr	r3, [pc, #4]	; (20002de0 <z_impl_k_current_get+0x8>)
20002dda:	6898      	ldr	r0, [r3, #8]
20002ddc:	4770      	bx	lr
20002dde:	bf00      	nop
20002de0:	20020874 	.word	0x20020874

20002de4 <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
20002de4:	b538      	push	{r3, r4, r5, lr}
20002de6:	4604      	mov	r4, r0
20002de8:	f04f 0320 	mov.w	r3, #32
20002dec:	f3ef 8511 	mrs	r5, BASEPRI
20002df0:	f383 8811 	msr	BASEPRI, r3
20002df4:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	sys_trace_semaphore_give(sem);
	thread = z_unpend_first_thread(&sem->wait_q);
20002df8:	f001 f863 	bl	20003ec2 <z_unpend_first_thread>

	if (thread != NULL) {
20002dfc:	b148      	cbz	r0, 20002e12 <z_impl_k_sem_give+0x2e>
20002dfe:	2200      	movs	r2, #0
20002e00:	67c2      	str	r2, [r0, #124]	; 0x7c
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
20002e02:	f001 f803 	bl	20003e0c <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
20002e06:	4629      	mov	r1, r5
	sys_trace_end_call(SYS_TRACE_ID_SEMA_GIVE);
}
20002e08:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
20002e0c:	4804      	ldr	r0, [pc, #16]	; (20002e20 <z_impl_k_sem_give+0x3c>)
20002e0e:	f7ff bcc9 	b.w	200027a4 <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
20002e12:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
20002e16:	429a      	cmp	r2, r3
20002e18:	bf18      	it	ne
20002e1a:	3301      	addne	r3, #1
20002e1c:	60a3      	str	r3, [r4, #8]
		handle_poll_events(sem);
20002e1e:	e7f2      	b.n	20002e06 <z_impl_k_sem_give+0x22>
20002e20:	200208cf 	.word	0x200208cf

20002e24 <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
20002e24:	b537      	push	{r0, r1, r2, r4, r5, lr}
20002e26:	4614      	mov	r4, r2
20002e28:	461d      	mov	r5, r3
20002e2a:	f04f 0320 	mov.w	r3, #32
20002e2e:	f3ef 8111 	mrs	r1, BASEPRI
20002e32:	f383 8811 	msr	BASEPRI, r3
20002e36:	f3bf 8f6f 	isb	sy
		  K_TIMEOUT_EQ(timeout, K_NO_WAIT)), "");

	k_spinlock_key_t key = k_spin_lock(&lock);
	sys_trace_semaphore_take(sem);

	if (likely(sem->count > 0U)) {
20002e3a:	6883      	ldr	r3, [r0, #8]
20002e3c:	b143      	cbz	r3, 20002e50 <z_impl_k_sem_take+0x2c>
		sem->count--;
20002e3e:	3b01      	subs	r3, #1
20002e40:	6083      	str	r3, [r0, #8]
	__asm__ volatile(
20002e42:	f381 8811 	msr	BASEPRI, r1
20002e46:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
20002e4a:	2000      	movs	r0, #0
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);

out:
	sys_trace_end_call(SYS_TRACE_ID_SEMA_TAKE);
	return ret;
}
20002e4c:	b003      	add	sp, #12
20002e4e:	bd30      	pop	{r4, r5, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
20002e50:	ea54 0305 	orrs.w	r3, r4, r5
20002e54:	d106      	bne.n	20002e64 <z_impl_k_sem_take+0x40>
20002e56:	f381 8811 	msr	BASEPRI, r1
20002e5a:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
20002e5e:	f06f 000f 	mvn.w	r0, #15
20002e62:	e7f3      	b.n	20002e4c <z_impl_k_sem_take+0x28>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
20002e64:	4602      	mov	r2, r0
20002e66:	e9cd 4500 	strd	r4, r5, [sp]
20002e6a:	4802      	ldr	r0, [pc, #8]	; (20002e74 <z_impl_k_sem_take+0x50>)
20002e6c:	f7ff feb4 	bl	20002bd8 <z_pend_curr>
	return ret;
20002e70:	e7ec      	b.n	20002e4c <z_impl_k_sem_take+0x28>
20002e72:	bf00      	nop
20002e74:	200208cf 	.word	0x200208cf

20002e78 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
20002e78:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
	sys_dlist_init(&w->waitq);
20002e7c:	f100 0530 	add.w	r5, r0, #48	; 0x30
	list->tail = (sys_dnode_t *)list;
20002e80:	e9c0 550c 	strd	r5, r5, [r0, #48]	; 0x30
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */

	thread_base->user_options = (uint8_t)options;
20002e84:	9d0e      	ldr	r5, [sp, #56]	; 0x38
{
20002e86:	4604      	mov	r4, r0
	thread_base->user_options = (uint8_t)options;
20002e88:	7305      	strb	r5, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
20002e8a:	2504      	movs	r5, #4
20002e8c:	7345      	strb	r5, [r0, #13]

	thread_base->prio = priority;
20002e8e:	9d0d      	ldr	r5, [sp, #52]	; 0x34
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
20002e90:	1dd6      	adds	r6, r2, #7
	thread_base->prio = priority;
20002e92:	7385      	strb	r5, [r0, #14]

	thread_base->sched_locked = 0U;
20002e94:	2500      	movs	r5, #0
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
20002e96:	9a0c      	ldr	r2, [sp, #48]	; 0x30
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
20002e98:	f026 0607 	bic.w	r6, r6, #7
	node->prev = NULL;
20002e9c:	e9c0 5506 	strd	r5, r5, [r0, #24]
	new_thread->stack_info.size = stack_buf_size;
20002ea0:	e9c0 161a 	strd	r1, r6, [r0, #104]	; 0x68
	thread_base->sched_locked = 0U;
20002ea4:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
20002ea6:	6705      	str	r5, [r0, #112]	; 0x70
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
20002ea8:	9202      	str	r2, [sp, #8]
20002eaa:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
	stack_ptr = (char *)stack + stack_obj_size;
20002eac:	eb01 0806 	add.w	r8, r1, r6
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
20002eb0:	9201      	str	r2, [sp, #4]
20002eb2:	9a0a      	ldr	r2, [sp, #40]	; 0x28
20002eb4:	9200      	str	r2, [sp, #0]
20002eb6:	4642      	mov	r2, r8
20002eb8:	f7fe f994 	bl	200011e4 <arch_new_thread>
	if (!_current) {
20002ebc:	4b05      	ldr	r3, [pc, #20]	; (20002ed4 <z_setup_new_thread+0x5c>)
	new_thread->fn_abort = NULL;
20002ebe:	e9c4 5517 	strd	r5, r5, [r4, #92]	; 0x5c
	if (!_current) {
20002ec2:	689b      	ldr	r3, [r3, #8]
20002ec4:	b103      	cbz	r3, 20002ec8 <z_setup_new_thread+0x50>
	new_thread->resource_pool = _current->resource_pool;
20002ec6:	6f5b      	ldr	r3, [r3, #116]	; 0x74
}
20002ec8:	4640      	mov	r0, r8
20002eca:	6763      	str	r3, [r4, #116]	; 0x74
20002ecc:	b004      	add	sp, #16
20002ece:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
20002ed2:	bf00      	nop
20002ed4:	20020874 	.word	0x20020874

20002ed8 <z_init_static_threads>:
{
20002ed8:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	_FOREACH_STATIC_THREAD(thread_data) {
20002edc:	4e2a      	ldr	r6, [pc, #168]	; (20002f88 <z_init_static_threads+0xb0>)
20002ede:	4d2b      	ldr	r5, [pc, #172]	; (20002f8c <z_init_static_threads+0xb4>)
20002ee0:	46b0      	mov	r8, r6
{
20002ee2:	b086      	sub	sp, #24
	_FOREACH_STATIC_THREAD(thread_data) {
20002ee4:	42b5      	cmp	r5, r6
20002ee6:	f105 0430 	add.w	r4, r5, #48	; 0x30
20002eea:	d310      	bcc.n	20002f0e <z_init_static_threads+0x36>
	k_sched_lock();
20002eec:	f7ff fc6c 	bl	200027c8 <k_sched_lock>
20002ef0:	f44f 4900 	mov.w	r9, #32768	; 0x8000
20002ef4:	f240 36e7 	movw	r6, #999	; 0x3e7
20002ef8:	2700      	movs	r7, #0
	_FOREACH_STATIC_THREAD(thread_data) {
20002efa:	4c24      	ldr	r4, [pc, #144]	; (20002f8c <z_init_static_threads+0xb4>)
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
20002efc:	f8df a090 	ldr.w	sl, [pc, #144]	; 20002f90 <z_init_static_threads+0xb8>
20002f00:	4544      	cmp	r4, r8
20002f02:	d321      	bcc.n	20002f48 <z_init_static_threads+0x70>
}
20002f04:	b006      	add	sp, #24
20002f06:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	k_sched_unlock();
20002f0a:	f7ff bcab 	b.w	20002864 <k_sched_unlock>
		z_setup_new_thread(
20002f0e:	f854 3c04 	ldr.w	r3, [r4, #-4]
20002f12:	9305      	str	r3, [sp, #20]
20002f14:	f854 3c10 	ldr.w	r3, [r4, #-16]
20002f18:	9304      	str	r3, [sp, #16]
20002f1a:	f854 3c14 	ldr.w	r3, [r4, #-20]
20002f1e:	9303      	str	r3, [sp, #12]
20002f20:	f854 3c18 	ldr.w	r3, [r4, #-24]
20002f24:	9302      	str	r3, [sp, #8]
20002f26:	f854 3c1c 	ldr.w	r3, [r4, #-28]
20002f2a:	9301      	str	r3, [sp, #4]
20002f2c:	f854 3c20 	ldr.w	r3, [r4, #-32]
20002f30:	9300      	str	r3, [sp, #0]
20002f32:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
20002f36:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
20002f3a:	f7ff ff9d 	bl	20002e78 <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
20002f3e:	f854 3c30 	ldr.w	r3, [r4, #-48]
20002f42:	65dd      	str	r5, [r3, #92]	; 0x5c
20002f44:	4625      	mov	r5, r4
20002f46:	e7cd      	b.n	20002ee4 <z_init_static_threads+0xc>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
20002f48:	6a63      	ldr	r3, [r4, #36]	; 0x24
20002f4a:	1c5a      	adds	r2, r3, #1
20002f4c:	d00d      	beq.n	20002f6a <z_init_static_threads+0x92>
20002f4e:	4630      	mov	r0, r6
20002f50:	4639      	mov	r1, r7
					    K_MSEC(thread_data->init_delay));
20002f52:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
20002f56:	fbc9 0103 	smlal	r0, r1, r9, r3
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
20002f5a:	42b9      	cmp	r1, r7
20002f5c:	bf08      	it	eq
20002f5e:	42b0      	cmpeq	r0, r6
			schedule_new_thread(thread_data->init_thread,
20002f60:	6825      	ldr	r5, [r4, #0]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
20002f62:	d104      	bne.n	20002f6e <z_init_static_threads+0x96>
	z_sched_start(thread);
20002f64:	4628      	mov	r0, r5
20002f66:	f7ff fccd 	bl	20002904 <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
20002f6a:	3430      	adds	r4, #48	; 0x30
20002f6c:	e7c8      	b.n	20002f00 <z_init_static_threads+0x28>
20002f6e:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
20002f72:	2300      	movs	r3, #0
20002f74:	f7fd f8ee 	bl	20000154 <__aeabi_uldivmod>
20002f78:	4602      	mov	r2, r0
20002f7a:	460b      	mov	r3, r1
20002f7c:	f105 0018 	add.w	r0, r5, #24
20002f80:	4651      	mov	r1, sl
20002f82:	f000 f853 	bl	2000302c <z_add_timeout>
20002f86:	e7f0      	b.n	20002f6a <z_init_static_threads+0x92>
20002f88:	2002010c 	.word	0x2002010c
20002f8c:	2002010c 	.word	0x2002010c
20002f90:	20003e2d 	.word	0x20003e2d

20002f94 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? z_clock_elapsed() : 0;
20002f94:	4b03      	ldr	r3, [pc, #12]	; (20002fa4 <elapsed+0x10>)
20002f96:	681b      	ldr	r3, [r3, #0]
20002f98:	b90b      	cbnz	r3, 20002f9e <elapsed+0xa>
20002f9a:	f7fd bfe5 	b.w	20000f68 <z_clock_elapsed>
}
20002f9e:	2000      	movs	r0, #0
20002fa0:	4770      	bx	lr
20002fa2:	bf00      	nop
20002fa4:	200208b0 	.word	0x200208b0

20002fa8 <remove_timeout>:
{
20002fa8:	b530      	push	{r4, r5, lr}
20002faa:	6803      	ldr	r3, [r0, #0]
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
20002fac:	b168      	cbz	r0, 20002fca <remove_timeout+0x22>
20002fae:	4a0a      	ldr	r2, [pc, #40]	; (20002fd8 <remove_timeout+0x30>)
	return (node == list->tail) ? NULL : node->next;
20002fb0:	6852      	ldr	r2, [r2, #4]
20002fb2:	4290      	cmp	r0, r2
20002fb4:	d009      	beq.n	20002fca <remove_timeout+0x22>
	if (next(t) != NULL) {
20002fb6:	b143      	cbz	r3, 20002fca <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
20002fb8:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
20002fbc:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
20002fc0:	1912      	adds	r2, r2, r4
20002fc2:	eb45 0101 	adc.w	r1, r5, r1
20002fc6:	e9c3 2104 	strd	r2, r1, [r3, #16]
	node->prev->next = node->next;
20002fca:	6842      	ldr	r2, [r0, #4]
20002fcc:	6013      	str	r3, [r2, #0]
	node->next->prev = node->prev;
20002fce:	605a      	str	r2, [r3, #4]
	node->next = NULL;
20002fd0:	2300      	movs	r3, #0
	node->prev = NULL;
20002fd2:	e9c0 3300 	strd	r3, r3, [r0]
}
20002fd6:	bd30      	pop	{r4, r5, pc}
20002fd8:	20020040 	.word	0x20020040

20002fdc <next_timeout>:

static int32_t next_timeout(void)
{
20002fdc:	b538      	push	{r3, r4, r5, lr}
	return list->head == list;
20002fde:	4b11      	ldr	r3, [pc, #68]	; (20003024 <next_timeout+0x48>)
20002fe0:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
20002fe2:	429c      	cmp	r4, r3
20002fe4:	bf08      	it	eq
20002fe6:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
20002fe8:	f7ff ffd4 	bl	20002f94 <elapsed>
20002fec:	4605      	mov	r5, r0
	int32_t ret = to == NULL ? MAX_WAIT
20002fee:	b1ac      	cbz	r4, 2000301c <next_timeout+0x40>
		: MIN(MAX_WAIT, MAX(0, to->dticks - ticks_elapsed));
20002ff0:	e9d4 0104 	ldrd	r0, r1, [r4, #16]
20002ff4:	1b40      	subs	r0, r0, r5
20002ff6:	eb61 71e5 	sbc.w	r1, r1, r5, asr #31
	int32_t ret = to == NULL ? MAX_WAIT
20002ffa:	f1b0 4f00 	cmp.w	r0, #2147483648	; 0x80000000
20002ffe:	f171 0300 	sbcs.w	r3, r1, #0
20003002:	da0b      	bge.n	2000301c <next_timeout+0x40>
		: MIN(MAX_WAIT, MAX(0, to->dticks - ticks_elapsed));
20003004:	2800      	cmp	r0, #0
20003006:	f171 0300 	sbcs.w	r3, r1, #0
2000300a:	da00      	bge.n	2000300e <next_timeout+0x32>
2000300c:	2000      	movs	r0, #0

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
2000300e:	4b06      	ldr	r3, [pc, #24]	; (20003028 <next_timeout+0x4c>)
20003010:	691b      	ldr	r3, [r3, #16]
20003012:	b113      	cbz	r3, 2000301a <next_timeout+0x3e>
20003014:	4298      	cmp	r0, r3
20003016:	bfa8      	it	ge
20003018:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
2000301a:	bd38      	pop	{r3, r4, r5, pc}
	int32_t ret = to == NULL ? MAX_WAIT
2000301c:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
20003020:	e7f5      	b.n	2000300e <next_timeout+0x32>
20003022:	bf00      	nop
20003024:	20020040 	.word	0x20020040
20003028:	20020874 	.word	0x20020874

2000302c <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
2000302c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
20003030:	9101      	str	r1, [sp, #4]
20003032:	4619      	mov	r1, r3
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
20003034:	1c4b      	adds	r3, r1, #1
20003036:	bf08      	it	eq
20003038:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
2000303c:	4682      	mov	sl, r0
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
2000303e:	d06b      	beq.n	20003118 <z_add_timeout+0xec>
#ifdef CONFIG_LEGACY_TIMEOUT_API
	k_ticks_t ticks = timeout;
#else
	k_ticks_t ticks = timeout.ticks + 1;

	if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) && Z_TICK_ABS(ticks) >= 0) {
20003040:	f06f 0301 	mvn.w	r3, #1
20003044:	f04f 3bff 	mov.w	fp, #4294967295
	k_ticks_t ticks = timeout.ticks + 1;
20003048:	1c54      	adds	r4, r2, #1
2000304a:	f141 0500 	adc.w	r5, r1, #0
	if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) && Z_TICK_ABS(ticks) >= 0) {
2000304e:	ebb3 0804 	subs.w	r8, r3, r4
20003052:	eb6b 0905 	sbc.w	r9, fp, r5
20003056:	f1b8 0f00 	cmp.w	r8, #0
2000305a:	f179 0300 	sbcs.w	r3, r9, #0
2000305e:	db0f      	blt.n	20003080 <z_add_timeout+0x54>
		ticks = Z_TICK_ABS(ticks) - (curr_tick + elapsed());
20003060:	f7ff ff98 	bl	20002f94 <elapsed>
20003064:	f06f 0301 	mvn.w	r3, #1
20003068:	4a32      	ldr	r2, [pc, #200]	; (20003134 <z_add_timeout+0x108>)
2000306a:	e9d2 1c00 	ldrd	r1, ip, [r2]
2000306e:	1a5b      	subs	r3, r3, r1
20003070:	eb6b 020c 	sbc.w	r2, fp, ip
20003074:	1b1e      	subs	r6, r3, r4
20003076:	eb62 0705 	sbc.w	r7, r2, r5
2000307a:	1a34      	subs	r4, r6, r0
2000307c:	eb67 75e0 	sbc.w	r5, r7, r0, asr #31
	}
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
20003080:	9b01      	ldr	r3, [sp, #4]
20003082:	f8ca 3008 	str.w	r3, [sl, #8]
	__asm__ volatile(
20003086:	f04f 0320 	mov.w	r3, #32
2000308a:	f3ef 8611 	mrs	r6, BASEPRI
2000308e:	f383 8811 	msr	BASEPRI, r3
20003092:	f3bf 8f6f 	isb	sy
	ticks = MAX(1, ticks);

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		to->dticks = ticks + elapsed();
20003096:	f7ff ff7d 	bl	20002f94 <elapsed>
	ticks = MAX(1, ticks);
2000309a:	2c01      	cmp	r4, #1
2000309c:	f175 0300 	sbcs.w	r3, r5, #0
200030a0:	bfbc      	itt	lt
200030a2:	2401      	movlt	r4, #1
200030a4:	2500      	movlt	r5, #0
	return list->head == list;
200030a6:	4b24      	ldr	r3, [pc, #144]	; (20003138 <z_add_timeout+0x10c>)
		to->dticks = ticks + elapsed();
200030a8:	1824      	adds	r4, r4, r0
200030aa:	681a      	ldr	r2, [r3, #0]
200030ac:	eb45 75e0 	adc.w	r5, r5, r0, asr #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
200030b0:	429a      	cmp	r2, r3
200030b2:	e9ca 4504 	strd	r4, r5, [sl, #16]
200030b6:	d001      	beq.n	200030bc <z_add_timeout+0x90>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
200030b8:	685f      	ldr	r7, [r3, #4]
		for (t = first(); t != NULL; t = next(t)) {
200030ba:	b952      	cbnz	r2, 200030d2 <z_add_timeout+0xa6>
	node->prev = list->tail;
200030bc:	685a      	ldr	r2, [r3, #4]
	node->next = list;
200030be:	f8ca 3000 	str.w	r3, [sl]
	node->prev = list->tail;
200030c2:	f8ca 2004 	str.w	r2, [sl, #4]
	list->tail->next = node;
200030c6:	685a      	ldr	r2, [r3, #4]
200030c8:	f8c2 a000 	str.w	sl, [r2]
	list->tail = node;
200030cc:	f8c3 a004 	str.w	sl, [r3, #4]
}
200030d0:	e014      	b.n	200030fc <z_add_timeout+0xd0>
			if (t->dticks > to->dticks) {
200030d2:	e9d2 8904 	ldrd	r8, r9, [r2, #16]
200030d6:	e9da 4504 	ldrd	r4, r5, [sl, #16]
200030da:	4544      	cmp	r4, r8
200030dc:	eb75 0109 	sbcs.w	r1, r5, r9
200030e0:	da1d      	bge.n	2000311e <z_add_timeout+0xf2>
				t->dticks -= to->dticks;
200030e2:	ebb8 0004 	subs.w	r0, r8, r4
200030e6:	eb69 0105 	sbc.w	r1, r9, r5
200030ea:	e9c2 0104 	strd	r0, r1, [r2, #16]
	node->prev = successor->prev;
200030ee:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
200030f0:	e9ca 2100 	strd	r2, r1, [sl]
	successor->prev->next = node;
200030f4:	f8c1 a000 	str.w	sl, [r1]
	successor->prev = node;
200030f8:	f8c2 a004 	str.w	sl, [r2, #4]
	return list->head == list;
200030fc:	681a      	ldr	r2, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
200030fe:	429a      	cmp	r2, r3
20003100:	d006      	beq.n	20003110 <z_add_timeout+0xe4>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
20003102:	4592      	cmp	sl, r2
20003104:	d104      	bne.n	20003110 <z_add_timeout+0xe4>
			z_clock_set_timeout(next_timeout(), false);
20003106:	f7ff ff69 	bl	20002fdc <next_timeout>
2000310a:	2100      	movs	r1, #0
2000310c:	f7fd fec6 	bl	20000e9c <z_clock_set_timeout>
	__asm__ volatile(
20003110:	f386 8811 	msr	BASEPRI, r6
20003114:	f3bf 8f6f 	isb	sy
		}
	}
}
20003118:	b003      	add	sp, #12
2000311a:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			to->dticks -= t->dticks;
2000311e:	ebb4 0008 	subs.w	r0, r4, r8
20003122:	eb65 0109 	sbc.w	r1, r5, r9
	return (node == list->tail) ? NULL : node->next;
20003126:	42ba      	cmp	r2, r7
20003128:	e9ca 0104 	strd	r0, r1, [sl, #16]
2000312c:	d0c6      	beq.n	200030bc <z_add_timeout+0x90>
2000312e:	6812      	ldr	r2, [r2, #0]
20003130:	e7c3      	b.n	200030ba <z_add_timeout+0x8e>
20003132:	bf00      	nop
20003134:	20020260 	.word	0x20020260
20003138:	20020040 	.word	0x20020040

2000313c <z_clock_announce>:
		}
	}
}

void z_clock_announce(int32_t ticks)
{
2000313c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
20003140:	4606      	mov	r6, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
20003142:	f7ff fc37 	bl	200029b4 <z_time_slice>
	__asm__ volatile(
20003146:	f04f 0320 	mov.w	r3, #32
2000314a:	f3ef 8411 	mrs	r4, BASEPRI
2000314e:	f383 8811 	msr	BASEPRI, r3
20003152:	f3bf 8f6f 	isb	sy
#endif

	k_spinlock_key_t key = k_spin_lock(&timeout_lock);

	announce_remaining = ticks;
20003156:	f8df a0b0 	ldr.w	sl, [pc, #176]	; 20003208 <z_clock_announce+0xcc>
2000315a:	4d2a      	ldr	r5, [pc, #168]	; (20003204 <z_clock_announce+0xc8>)
2000315c:	4651      	mov	r1, sl
	return list->head == list;
2000315e:	f8df b0ac 	ldr.w	fp, [pc, #172]	; 2000320c <z_clock_announce+0xd0>
20003162:	602e      	str	r6, [r5, #0]
20003164:	f8d5 c000 	ldr.w	ip, [r5]
20003168:	f8db 0000 	ldr.w	r0, [fp]
2000316c:	4662      	mov	r2, ip
2000316e:	e9da 8900 	ldrd	r8, r9, [sl]
20003172:	17d3      	asrs	r3, r2, #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
20003174:	4558      	cmp	r0, fp
20003176:	e9cd 2300 	strd	r2, r3, [sp]
2000317a:	d00d      	beq.n	20003198 <z_clock_announce+0x5c>

	while (first() != NULL && first()->dticks <= announce_remaining) {
2000317c:	b160      	cbz	r0, 20003198 <z_clock_announce+0x5c>
2000317e:	e9d0 6704 	ldrd	r6, r7, [r0, #16]
20003182:	45b4      	cmp	ip, r6
20003184:	41bb      	sbcs	r3, r7
20003186:	da1d      	bge.n	200031c4 <z_clock_announce+0x88>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
20003188:	9b00      	ldr	r3, [sp, #0]
2000318a:	ebb6 0c03 	subs.w	ip, r6, r3
2000318e:	9b01      	ldr	r3, [sp, #4]
20003190:	eb67 0603 	sbc.w	r6, r7, r3
20003194:	e9c0 c604 	strd	ip, r6, [r0, #16]
	}

	curr_tick += announce_remaining;
	announce_remaining = 0;
20003198:	2600      	movs	r6, #0
	curr_tick += announce_remaining;
2000319a:	9b00      	ldr	r3, [sp, #0]
	announce_remaining = 0;
2000319c:	602e      	str	r6, [r5, #0]
	curr_tick += announce_remaining;
2000319e:	eb13 0208 	adds.w	r2, r3, r8
200031a2:	9b01      	ldr	r3, [sp, #4]
200031a4:	eb43 0309 	adc.w	r3, r3, r9
200031a8:	e9c1 2300 	strd	r2, r3, [r1]

	z_clock_set_timeout(next_timeout(), false);
200031ac:	f7ff ff16 	bl	20002fdc <next_timeout>
200031b0:	4631      	mov	r1, r6
200031b2:	f7fd fe73 	bl	20000e9c <z_clock_set_timeout>
	__asm__ volatile(
200031b6:	f384 8811 	msr	BASEPRI, r4
200031ba:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
200031be:	b003      	add	sp, #12
200031c0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		t->dticks = 0;
200031c4:	2200      	movs	r2, #0
200031c6:	2300      	movs	r3, #0
		curr_tick += dt;
200031c8:	eb18 0806 	adds.w	r8, r8, r6
200031cc:	eb49 79e6 	adc.w	r9, r9, r6, asr #31
		t->dticks = 0;
200031d0:	e9c0 2304 	strd	r2, r3, [r0, #16]
		announce_remaining -= dt;
200031d4:	ebac 0606 	sub.w	r6, ip, r6
		curr_tick += dt;
200031d8:	e9ca 8900 	strd	r8, r9, [sl]
		announce_remaining -= dt;
200031dc:	602e      	str	r6, [r5, #0]
		remove_timeout(t);
200031de:	f7ff fee3 	bl	20002fa8 <remove_timeout>
200031e2:	f384 8811 	msr	BASEPRI, r4
200031e6:	f3bf 8f6f 	isb	sy
		t->fn(t);
200031ea:	6883      	ldr	r3, [r0, #8]
200031ec:	4798      	blx	r3
	__asm__ volatile(
200031ee:	f04f 0320 	mov.w	r3, #32
200031f2:	f3ef 8411 	mrs	r4, BASEPRI
200031f6:	f383 8811 	msr	BASEPRI, r3
200031fa:	f3bf 8f6f 	isb	sy

	/* Note that we need to use the underlying arch-specific lock
	 * implementation.  The "irq_lock()" API in SMP context is
	 * actually a wrapper for a global spinlock!
	 */
	k.key = arch_irq_lock();
200031fe:	4902      	ldr	r1, [pc, #8]	; (20003208 <z_clock_announce+0xcc>)
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
20003200:	e7b0      	b.n	20003164 <z_clock_announce+0x28>
20003202:	bf00      	nop
20003204:	200208b0 	.word	0x200208b0
20003208:	20020260 	.word	0x20020260
2000320c:	20020040 	.word	0x20020040

20003210 <z_tick_get>:

int64_t z_tick_get(void)
{
20003210:	b510      	push	{r4, lr}
20003212:	f04f 0320 	mov.w	r3, #32
20003216:	f3ef 8411 	mrs	r4, BASEPRI
2000321a:	f383 8811 	msr	BASEPRI, r3
2000321e:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + z_clock_elapsed();
20003222:	f7fd fea1 	bl	20000f68 <z_clock_elapsed>
20003226:	4b06      	ldr	r3, [pc, #24]	; (20003240 <z_tick_get+0x30>)
20003228:	e9d3 2300 	ldrd	r2, r3, [r3]
2000322c:	1812      	adds	r2, r2, r0
2000322e:	f143 0300 	adc.w	r3, r3, #0
	__asm__ volatile(
20003232:	f384 8811 	msr	BASEPRI, r4
20003236:	f3bf 8f6f 	isb	sy
	}
	return t;
}
2000323a:	4610      	mov	r0, r2
2000323c:	4619      	mov	r1, r3
2000323e:	bd10      	pop	{r4, pc}
20003240:	20020260 	.word	0x20020260

20003244 <statics_init>:
	z_waitq_init(&h->wait_q);
	sys_heap_init(&h->heap, mem, bytes);
}

static int statics_init(const struct device *unused)
{
20003244:	b538      	push	{r3, r4, r5, lr}
	ARG_UNUSED(unused);
	Z_STRUCT_SECTION_FOREACH(k_heap, h) {
20003246:	4c06      	ldr	r4, [pc, #24]	; (20003260 <statics_init+0x1c>)
20003248:	4d06      	ldr	r5, [pc, #24]	; (20003264 <statics_init+0x20>)
2000324a:	42ac      	cmp	r4, r5
2000324c:	d301      	bcc.n	20003252 <statics_init+0xe>
		k_heap_init(h, h->heap.init_mem, h->heap.init_bytes);
	}
	return 0;
}
2000324e:	2000      	movs	r0, #0
20003250:	bd38      	pop	{r3, r4, r5, pc}
		k_heap_init(h, h->heap.init_mem, h->heap.init_bytes);
20003252:	4620      	mov	r0, r4
20003254:	e9d4 1201 	ldrd	r1, r2, [r4, #4]
20003258:	f000 fea4 	bl	20003fa4 <k_heap_init>
	Z_STRUCT_SECTION_FOREACH(k_heap, h) {
2000325c:	3414      	adds	r4, #20
2000325e:	e7f4      	b.n	2000324a <statics_init+0x6>
20003260:	2002010c 	.word	0x2002010c
20003264:	2002010c 	.word	0x2002010c

20003268 <nrf_cc3xx_platform_init_no_rng>:
20003268:	b510      	push	{r4, lr}
2000326a:	4c0a      	ldr	r4, [pc, #40]	; (20003294 <nrf_cc3xx_platform_init_no_rng+0x2c>)
2000326c:	6823      	ldr	r3, [r4, #0]
2000326e:	b11b      	cbz	r3, 20003278 <nrf_cc3xx_platform_init_no_rng+0x10>
20003270:	2301      	movs	r3, #1
20003272:	2000      	movs	r0, #0
20003274:	6023      	str	r3, [r4, #0]
20003276:	bd10      	pop	{r4, pc}
20003278:	f000 f898 	bl	200033ac <CC_LibInitNoRng>
2000327c:	2800      	cmp	r0, #0
2000327e:	d0f7      	beq.n	20003270 <nrf_cc3xx_platform_init_no_rng+0x8>
20003280:	3801      	subs	r0, #1
20003282:	2807      	cmp	r0, #7
20003284:	d803      	bhi.n	2000328e <nrf_cc3xx_platform_init_no_rng+0x26>
20003286:	4b04      	ldr	r3, [pc, #16]	; (20003298 <nrf_cc3xx_platform_init_no_rng+0x30>)
20003288:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
2000328c:	bd10      	pop	{r4, pc}
2000328e:	4803      	ldr	r0, [pc, #12]	; (2000329c <nrf_cc3xx_platform_init_no_rng+0x34>)
20003290:	bd10      	pop	{r4, pc}
20003292:	bf00      	nop
20003294:	200208b4 	.word	0x200208b4
20003298:	20004344 	.word	0x20004344
2000329c:	ffff8ffe 	.word	0xffff8ffe

200032a0 <nrf_cc3xx_platform_abort>:
200032a0:	f3bf 8f4f 	dsb	sy
200032a4:	4905      	ldr	r1, [pc, #20]	; (200032bc <nrf_cc3xx_platform_abort+0x1c>)
200032a6:	4b06      	ldr	r3, [pc, #24]	; (200032c0 <nrf_cc3xx_platform_abort+0x20>)
200032a8:	68ca      	ldr	r2, [r1, #12]
200032aa:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
200032ae:	4313      	orrs	r3, r2
200032b0:	60cb      	str	r3, [r1, #12]
200032b2:	f3bf 8f4f 	dsb	sy
200032b6:	bf00      	nop
200032b8:	e7fd      	b.n	200032b6 <nrf_cc3xx_platform_abort+0x16>
200032ba:	bf00      	nop
200032bc:	e000ed00 	.word	0xe000ed00
200032c0:	05fa0004 	.word	0x05fa0004

200032c4 <CC_PalAbort>:
200032c4:	4b01      	ldr	r3, [pc, #4]	; (200032cc <CC_PalAbort+0x8>)
200032c6:	685b      	ldr	r3, [r3, #4]
200032c8:	4718      	bx	r3
200032ca:	bf00      	nop
200032cc:	20020048 	.word	0x20020048

200032d0 <nrf_cc3xx_platform_set_abort>:
200032d0:	4b02      	ldr	r3, [pc, #8]	; (200032dc <nrf_cc3xx_platform_set_abort+0xc>)
200032d2:	e9d0 1200 	ldrd	r1, r2, [r0]
200032d6:	e9c3 1200 	strd	r1, r2, [r3]
200032da:	4770      	bx	lr
200032dc:	20020048 	.word	0x20020048

200032e0 <mutex_unlock>:
200032e0:	b148      	cbz	r0, 200032f6 <mutex_unlock+0x16>
200032e2:	6843      	ldr	r3, [r0, #4]
200032e4:	b12b      	cbz	r3, 200032f2 <mutex_unlock+0x12>
200032e6:	f3bf 8f5f 	dmb	sy
200032ea:	2300      	movs	r3, #0
200032ec:	6003      	str	r3, [r0, #0]
200032ee:	4618      	mov	r0, r3
200032f0:	4770      	bx	lr
200032f2:	4802      	ldr	r0, [pc, #8]	; (200032fc <mutex_unlock+0x1c>)
200032f4:	4770      	bx	lr
200032f6:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
200032fa:	4770      	bx	lr
200032fc:	ffff8fea 	.word	0xffff8fea

20003300 <mutex_free>:
20003300:	b510      	push	{r4, lr}
20003302:	4604      	mov	r4, r0
20003304:	b128      	cbz	r0, 20003312 <mutex_free+0x12>
20003306:	6863      	ldr	r3, [r4, #4]
20003308:	b113      	cbz	r3, 20003310 <mutex_free+0x10>
2000330a:	2300      	movs	r3, #0
2000330c:	6023      	str	r3, [r4, #0]
2000330e:	6063      	str	r3, [r4, #4]
20003310:	bd10      	pop	{r4, pc}
20003312:	4b02      	ldr	r3, [pc, #8]	; (2000331c <mutex_free+0x1c>)
20003314:	4802      	ldr	r0, [pc, #8]	; (20003320 <mutex_free+0x20>)
20003316:	685b      	ldr	r3, [r3, #4]
20003318:	4798      	blx	r3
2000331a:	e7f4      	b.n	20003306 <mutex_free+0x6>
2000331c:	20020048 	.word	0x20020048
20003320:	20004364 	.word	0x20004364

20003324 <mutex_init>:
20003324:	b510      	push	{r4, lr}
20003326:	4604      	mov	r4, r0
20003328:	b130      	cbz	r0, 20003338 <mutex_init+0x14>
2000332a:	2200      	movs	r2, #0
2000332c:	6863      	ldr	r3, [r4, #4]
2000332e:	6022      	str	r2, [r4, #0]
20003330:	f043 0301 	orr.w	r3, r3, #1
20003334:	6063      	str	r3, [r4, #4]
20003336:	bd10      	pop	{r4, pc}
20003338:	4801      	ldr	r0, [pc, #4]	; (20003340 <mutex_init+0x1c>)
2000333a:	f7ff ffc3 	bl	200032c4 <CC_PalAbort>
2000333e:	e7f4      	b.n	2000332a <mutex_init+0x6>
20003340:	2000438c 	.word	0x2000438c

20003344 <mutex_lock>:
20003344:	b180      	cbz	r0, 20003368 <mutex_lock+0x24>
20003346:	6843      	ldr	r3, [r0, #4]
20003348:	b163      	cbz	r3, 20003364 <mutex_lock+0x20>
2000334a:	2201      	movs	r2, #1
2000334c:	e8d0 3fef 	ldaex	r3, [r0]
20003350:	e8c0 2fe1 	stlex	r1, r2, [r0]
20003354:	2900      	cmp	r1, #0
20003356:	d1f9      	bne.n	2000334c <mutex_lock+0x8>
20003358:	2b01      	cmp	r3, #1
2000335a:	d0f7      	beq.n	2000334c <mutex_lock+0x8>
2000335c:	f3bf 8f5f 	dmb	sy
20003360:	2000      	movs	r0, #0
20003362:	4770      	bx	lr
20003364:	4802      	ldr	r0, [pc, #8]	; (20003370 <mutex_lock+0x2c>)
20003366:	4770      	bx	lr
20003368:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
2000336c:	4770      	bx	lr
2000336e:	bf00      	nop
20003370:	ffff8fea 	.word	0xffff8fea

20003374 <nrf_cc3xx_platform_set_mutexes>:
20003374:	b470      	push	{r4, r5, r6}
20003376:	4b0b      	ldr	r3, [pc, #44]	; (200033a4 <nrf_cc3xx_platform_set_mutexes+0x30>)
20003378:	6806      	ldr	r6, [r0, #0]
2000337a:	68c2      	ldr	r2, [r0, #12]
2000337c:	e9d0 5401 	ldrd	r5, r4, [r0, #4]
20003380:	e9c3 4202 	strd	r4, r2, [r3, #8]
20003384:	e9c3 6500 	strd	r6, r5, [r3]
20003388:	e9d1 0203 	ldrd	r0, r2, [r1, #12]
2000338c:	680e      	ldr	r6, [r1, #0]
2000338e:	4b06      	ldr	r3, [pc, #24]	; (200033a8 <nrf_cc3xx_platform_set_mutexes+0x34>)
20003390:	e9d1 5401 	ldrd	r5, r4, [r1, #4]
20003394:	e9c3 6500 	strd	r6, r5, [r3]
20003398:	e9c3 4002 	strd	r4, r0, [r3, #8]
2000339c:	611a      	str	r2, [r3, #16]
2000339e:	bc70      	pop	{r4, r5, r6}
200033a0:	4770      	bx	lr
200033a2:	bf00      	nop
200033a4:	20020058 	.word	0x20020058
200033a8:	20020068 	.word	0x20020068

200033ac <CC_LibInitNoRng>:
200033ac:	b508      	push	{r3, lr}
200033ae:	f000 f80f 	bl	200033d0 <CC_HalInit>
200033b2:	b928      	cbnz	r0, 200033c0 <CC_LibInitNoRng+0x14>
200033b4:	f000 f80e 	bl	200033d4 <CC_PalInit>
200033b8:	b930      	cbnz	r0, 200033c8 <CC_LibInitNoRng+0x1c>
200033ba:	4a04      	ldr	r2, [pc, #16]	; (200033cc <CC_LibInitNoRng+0x20>)
200033bc:	6010      	str	r0, [r2, #0]
200033be:	bd08      	pop	{r3, pc}
200033c0:	f000 f836 	bl	20003430 <CC_PalTerminate>
200033c4:	2003      	movs	r0, #3
200033c6:	bd08      	pop	{r3, pc}
200033c8:	2004      	movs	r0, #4
200033ca:	bd08      	pop	{r3, pc}
200033cc:	50845a0c 	.word	0x50845a0c

200033d0 <CC_HalInit>:
200033d0:	2000      	movs	r0, #0
200033d2:	4770      	bx	lr

200033d4 <CC_PalInit>:
200033d4:	b510      	push	{r4, lr}
200033d6:	4811      	ldr	r0, [pc, #68]	; (2000341c <CC_PalInit+0x48>)
200033d8:	f000 f848 	bl	2000346c <CC_PalMutexCreate>
200033dc:	b100      	cbz	r0, 200033e0 <CC_PalInit+0xc>
200033de:	bd10      	pop	{r4, pc}
200033e0:	480f      	ldr	r0, [pc, #60]	; (20003420 <CC_PalInit+0x4c>)
200033e2:	f000 f843 	bl	2000346c <CC_PalMutexCreate>
200033e6:	2800      	cmp	r0, #0
200033e8:	d1f9      	bne.n	200033de <CC_PalInit+0xa>
200033ea:	4c0e      	ldr	r4, [pc, #56]	; (20003424 <CC_PalInit+0x50>)
200033ec:	4620      	mov	r0, r4
200033ee:	f000 f83d 	bl	2000346c <CC_PalMutexCreate>
200033f2:	2800      	cmp	r0, #0
200033f4:	d1f3      	bne.n	200033de <CC_PalInit+0xa>
200033f6:	4b0c      	ldr	r3, [pc, #48]	; (20003428 <CC_PalInit+0x54>)
200033f8:	480c      	ldr	r0, [pc, #48]	; (2000342c <CC_PalInit+0x58>)
200033fa:	601c      	str	r4, [r3, #0]
200033fc:	f000 f836 	bl	2000346c <CC_PalMutexCreate>
20003400:	4601      	mov	r1, r0
20003402:	2800      	cmp	r0, #0
20003404:	d1eb      	bne.n	200033de <CC_PalInit+0xa>
20003406:	f000 f82d 	bl	20003464 <CC_PalDmaInit>
2000340a:	4604      	mov	r4, r0
2000340c:	b108      	cbz	r0, 20003412 <CC_PalInit+0x3e>
2000340e:	4620      	mov	r0, r4
20003410:	bd10      	pop	{r4, pc}
20003412:	f000 f83f 	bl	20003494 <CC_PalPowerSaveModeInit>
20003416:	4620      	mov	r0, r4
20003418:	e7fa      	b.n	20003410 <CC_PalInit+0x3c>
2000341a:	bf00      	nop
2000341c:	200200a0 	.word	0x200200a0
20003420:	20020094 	.word	0x20020094
20003424:	2002009c 	.word	0x2002009c
20003428:	200200a4 	.word	0x200200a4
2000342c:	20020098 	.word	0x20020098

20003430 <CC_PalTerminate>:
20003430:	b508      	push	{r3, lr}
20003432:	4808      	ldr	r0, [pc, #32]	; (20003454 <CC_PalTerminate+0x24>)
20003434:	f000 f824 	bl	20003480 <CC_PalMutexDestroy>
20003438:	4807      	ldr	r0, [pc, #28]	; (20003458 <CC_PalTerminate+0x28>)
2000343a:	f000 f821 	bl	20003480 <CC_PalMutexDestroy>
2000343e:	4807      	ldr	r0, [pc, #28]	; (2000345c <CC_PalTerminate+0x2c>)
20003440:	f000 f81e 	bl	20003480 <CC_PalMutexDestroy>
20003444:	4806      	ldr	r0, [pc, #24]	; (20003460 <CC_PalTerminate+0x30>)
20003446:	f000 f81b 	bl	20003480 <CC_PalMutexDestroy>
2000344a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
2000344e:	f000 b80b 	b.w	20003468 <CC_PalDmaTerminate>
20003452:	bf00      	nop
20003454:	200200a0 	.word	0x200200a0
20003458:	20020094 	.word	0x20020094
2000345c:	2002009c 	.word	0x2002009c
20003460:	20020098 	.word	0x20020098

20003464 <CC_PalDmaInit>:
20003464:	2000      	movs	r0, #0
20003466:	4770      	bx	lr

20003468 <CC_PalDmaTerminate>:
20003468:	4770      	bx	lr
2000346a:	bf00      	nop

2000346c <CC_PalMutexCreate>:
2000346c:	b508      	push	{r3, lr}
2000346e:	4b03      	ldr	r3, [pc, #12]	; (2000347c <CC_PalMutexCreate+0x10>)
20003470:	6802      	ldr	r2, [r0, #0]
20003472:	681b      	ldr	r3, [r3, #0]
20003474:	6810      	ldr	r0, [r2, #0]
20003476:	4798      	blx	r3
20003478:	2000      	movs	r0, #0
2000347a:	bd08      	pop	{r3, pc}
2000347c:	20020058 	.word	0x20020058

20003480 <CC_PalMutexDestroy>:
20003480:	b508      	push	{r3, lr}
20003482:	4b03      	ldr	r3, [pc, #12]	; (20003490 <CC_PalMutexDestroy+0x10>)
20003484:	6802      	ldr	r2, [r0, #0]
20003486:	685b      	ldr	r3, [r3, #4]
20003488:	6810      	ldr	r0, [r2, #0]
2000348a:	4798      	blx	r3
2000348c:	2000      	movs	r0, #0
2000348e:	bd08      	pop	{r3, pc}
20003490:	20020058 	.word	0x20020058

20003494 <CC_PalPowerSaveModeInit>:
20003494:	b570      	push	{r4, r5, r6, lr}
20003496:	4c09      	ldr	r4, [pc, #36]	; (200034bc <CC_PalPowerSaveModeInit+0x28>)
20003498:	4d09      	ldr	r5, [pc, #36]	; (200034c0 <CC_PalPowerSaveModeInit+0x2c>)
2000349a:	6920      	ldr	r0, [r4, #16]
2000349c:	68ab      	ldr	r3, [r5, #8]
2000349e:	4798      	blx	r3
200034a0:	b118      	cbz	r0, 200034aa <CC_PalPowerSaveModeInit+0x16>
200034a2:	4b08      	ldr	r3, [pc, #32]	; (200034c4 <CC_PalPowerSaveModeInit+0x30>)
200034a4:	4808      	ldr	r0, [pc, #32]	; (200034c8 <CC_PalPowerSaveModeInit+0x34>)
200034a6:	685b      	ldr	r3, [r3, #4]
200034a8:	4798      	blx	r3
200034aa:	2100      	movs	r1, #0
200034ac:	4a07      	ldr	r2, [pc, #28]	; (200034cc <CC_PalPowerSaveModeInit+0x38>)
200034ae:	68eb      	ldr	r3, [r5, #12]
200034b0:	6011      	str	r1, [r2, #0]
200034b2:	6920      	ldr	r0, [r4, #16]
200034b4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
200034b8:	4718      	bx	r3
200034ba:	bf00      	nop
200034bc:	20020068 	.word	0x20020068
200034c0:	20020058 	.word	0x20020058
200034c4:	20020048 	.word	0x20020048
200034c8:	200043b0 	.word	0x200043b0
200034cc:	200208c8 	.word	0x200208c8

200034d0 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
200034d0:	4603      	mov	r3, r0
200034d2:	b158      	cbz	r0, 200034ec <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
200034d4:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
200034d6:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
200034da:	2a01      	cmp	r2, #1
200034dc:	d003      	beq.n	200034e6 <sys_notify_validate+0x16>
200034de:	2a03      	cmp	r2, #3
200034e0:	d104      	bne.n	200034ec <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
200034e2:	6802      	ldr	r2, [r0, #0]
200034e4:	b112      	cbz	r2, 200034ec <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
200034e6:	2000      	movs	r0, #0
200034e8:	6098      	str	r0, [r3, #8]
200034ea:	4770      	bx	lr
		return -EINVAL;
200034ec:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
200034f0:	4770      	bx	lr

200034f2 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
200034f2:	6842      	ldr	r2, [r0, #4]

sys_notify_generic_callback sys_notify_finalize(struct sys_notify *notify,
						    int res)
{
200034f4:	4603      	mov	r3, r0
	return method & SYS_NOTIFY_METHOD_MASK;
200034f6:	f002 0203 	and.w	r2, r2, #3

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
	switch (method) {
200034fa:	2a03      	cmp	r2, #3
200034fc:	f04f 0200 	mov.w	r2, #0
	notify->result = res;
20003500:	6081      	str	r1, [r0, #8]
	sys_notify_generic_callback rv = 0;
20003502:	bf14      	ite	ne
20003504:	4610      	movne	r0, r2
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
20003506:	6800      	ldreq	r0, [r0, #0]
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
20003508:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
2000350a:	4770      	bx	lr

2000350c <arch_printk_char_out>:
}
2000350c:	2000      	movs	r0, #0
2000350e:	4770      	bx	lr

20003510 <printk>:
 * @param fmt formatted string to output
 *
 * @return N/A
 */
void printk(const char *fmt, ...)
{
20003510:	b40f      	push	{r0, r1, r2, r3}
20003512:	b507      	push	{r0, r1, r2, lr}
20003514:	a904      	add	r1, sp, #16
20003516:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
2000351a:	9101      	str	r1, [sp, #4]

	if (IS_ENABLED(CONFIG_LOG_PRINTK)) {
		log_printk(fmt, ap);
	} else {
		vprintk(fmt, ap);
2000351c:	f7fd f954 	bl	200007c8 <vprintk>
	}
	va_end(ap);
}
20003520:	b003      	add	sp, #12
20003522:	f85d eb04 	ldr.w	lr, [sp], #4
20003526:	b004      	add	sp, #16
20003528:	4770      	bx	lr

2000352a <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
2000352a:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
2000352c:	f013 0307 	ands.w	r3, r3, #7
20003530:	d105      	bne.n	2000353e <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
20003532:	6803      	ldr	r3, [r0, #0]
20003534:	2b00      	cmp	r3, #0
		evt = EVT_START;
20003536:	bf0c      	ite	eq
20003538:	2000      	moveq	r0, #0
2000353a:	2003      	movne	r0, #3
2000353c:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
2000353e:	2b02      	cmp	r3, #2
20003540:	d105      	bne.n	2000354e <process_recheck+0x24>
		   && (mgr->refs == 0)) {
20003542:	8b43      	ldrh	r3, [r0, #26]
20003544:	2b00      	cmp	r3, #0
		evt = EVT_STOP;
20003546:	bf14      	ite	ne
20003548:	2000      	movne	r0, #0
2000354a:	2004      	moveq	r0, #4
2000354c:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
2000354e:	2b01      	cmp	r3, #1
20003550:	d105      	bne.n	2000355e <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
20003552:	6803      	ldr	r3, [r0, #0]
20003554:	2b00      	cmp	r3, #0
		evt = EVT_RESET;
20003556:	bf0c      	ite	eq
20003558:	2000      	moveq	r0, #0
2000355a:	2005      	movne	r0, #5
2000355c:	4770      	bx	lr
	int evt = EVT_NOP;
2000355e:	2000      	movs	r0, #0
}
20003560:	4770      	bx	lr

20003562 <notify_one>:
{
20003562:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
20003566:	460d      	mov	r5, r1
20003568:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
2000356a:	4619      	mov	r1, r3
2000356c:	1d28      	adds	r0, r5, #4
{
2000356e:	4690      	mov	r8, r2
20003570:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
20003572:	f7ff ffbe 	bl	200034f2 <sys_notify_finalize>
	if (cb) {
20003576:	4604      	mov	r4, r0
20003578:	b138      	cbz	r0, 2000358a <notify_one+0x28>
		cb(mgr, cli, state, res);
2000357a:	4633      	mov	r3, r6
2000357c:	4642      	mov	r2, r8
2000357e:	4629      	mov	r1, r5
20003580:	4638      	mov	r0, r7
20003582:	46a4      	mov	ip, r4
}
20003584:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
20003588:	4760      	bx	ip
}
2000358a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

2000358e <transition_complete>:
{
2000358e:	b410      	push	{r4}
	__asm__ volatile(
20003590:	f04f 0420 	mov.w	r4, #32
20003594:	f3ef 8211 	mrs	r2, BASEPRI
20003598:	f384 8811 	msr	BASEPRI, r4
2000359c:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
200035a0:	6141      	str	r1, [r0, #20]
}
200035a2:	bc10      	pop	{r4}
	process_event(mgr, EVT_COMPLETE, key);
200035a4:	2101      	movs	r1, #1
200035a6:	f7fd b91d 	b.w	200007e4 <process_event>

200035aa <validate_args>:
{
200035aa:	b510      	push	{r4, lr}
200035ac:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
200035ae:	b140      	cbz	r0, 200035c2 <validate_args+0x18>
200035b0:	b139      	cbz	r1, 200035c2 <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
200035b2:	1d08      	adds	r0, r1, #4
200035b4:	f7ff ff8c 	bl	200034d0 <sys_notify_validate>
	if ((rv == 0)
200035b8:	b928      	cbnz	r0, 200035c6 <validate_args+0x1c>
	    && ((cli->notify.flags
200035ba:	68a3      	ldr	r3, [r4, #8]
200035bc:	f033 0303 	bics.w	r3, r3, #3
200035c0:	d001      	beq.n	200035c6 <validate_args+0x1c>
		rv = -EINVAL;
200035c2:	f06f 0015 	mvn.w	r0, #21
}
200035c6:	bd10      	pop	{r4, pc}

200035c8 <onoff_manager_init>:
{
200035c8:	b538      	push	{r3, r4, r5, lr}
200035ca:	460c      	mov	r4, r1
	if ((mgr == NULL)
200035cc:	4605      	mov	r5, r0
200035ce:	b158      	cbz	r0, 200035e8 <onoff_manager_init+0x20>
	    || (transitions == NULL)
200035d0:	b151      	cbz	r1, 200035e8 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
200035d2:	680b      	ldr	r3, [r1, #0]
200035d4:	b143      	cbz	r3, 200035e8 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
200035d6:	684b      	ldr	r3, [r1, #4]
200035d8:	b133      	cbz	r3, 200035e8 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
200035da:	221c      	movs	r2, #28
200035dc:	2100      	movs	r1, #0
200035de:	f000 fa50 	bl	20003a82 <memset>
	return 0;
200035e2:	2000      	movs	r0, #0
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
200035e4:	612c      	str	r4, [r5, #16]
}
200035e6:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
200035e8:	f06f 0015 	mvn.w	r0, #21
200035ec:	e7fb      	b.n	200035e6 <onoff_manager_init+0x1e>

200035ee <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
200035ee:	b570      	push	{r4, r5, r6, lr}
200035f0:	4604      	mov	r4, r0
200035f2:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
200035f4:	f7ff ffd9 	bl	200035aa <validate_args>

	if (rv < 0) {
200035f8:	1e05      	subs	r5, r0, #0
200035fa:	db31      	blt.n	20003660 <onoff_request+0x72>
200035fc:	f04f 0320 	mov.w	r3, #32
20003600:	f3ef 8111 	mrs	r1, BASEPRI
20003604:	f383 8811 	msr	BASEPRI, r3
20003608:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
2000360c:	f64f 75ff 	movw	r5, #65535	; 0xffff
20003610:	8b63      	ldrh	r3, [r4, #26]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
20003612:	8b20      	ldrh	r0, [r4, #24]
	if (mgr->refs == SERVICE_REFS_MAX) {
20003614:	42ab      	cmp	r3, r5
20003616:	f000 0207 	and.w	r2, r0, #7
2000361a:	d02e      	beq.n	2000367a <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
2000361c:	2a02      	cmp	r2, #2
2000361e:	d10e      	bne.n	2000363e <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
20003620:	3301      	adds	r3, #1
20003622:	8363      	strh	r3, [r4, #26]
	rv = state;
20003624:	4615      	mov	r5, r2
		notify = true;
20003626:	2301      	movs	r3, #1
	__asm__ volatile(
20003628:	f381 8811 	msr	BASEPRI, r1
2000362c:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
20003630:	b1b3      	cbz	r3, 20003660 <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
20003632:	2300      	movs	r3, #0
20003634:	4631      	mov	r1, r6
20003636:	4620      	mov	r0, r4
20003638:	f7ff ff93 	bl	20003562 <notify_one>
2000363c:	e010      	b.n	20003660 <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
2000363e:	0783      	lsls	r3, r0, #30
20003640:	d001      	beq.n	20003646 <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
20003642:	2a06      	cmp	r2, #6
20003644:	d10e      	bne.n	20003664 <onoff_request+0x76>
	parent->next = child;
20003646:	2300      	movs	r3, #0
20003648:	6033      	str	r3, [r6, #0]
Z_GENLIST_APPEND(slist, snode)
2000364a:	6863      	ldr	r3, [r4, #4]
2000364c:	b993      	cbnz	r3, 20003674 <onoff_request+0x86>
	list->head = node;
2000364e:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
20003652:	4615      	mov	r5, r2
20003654:	b962      	cbnz	r2, 20003670 <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
20003656:	460a      	mov	r2, r1
20003658:	4620      	mov	r0, r4
2000365a:	2102      	movs	r1, #2
2000365c:	f7fd f8c2 	bl	200007e4 <process_event>
		}
	}

	return rv;
}
20003660:	4628      	mov	r0, r5
20003662:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
20003664:	2a05      	cmp	r2, #5
20003666:	bf0c      	ite	eq
20003668:	f06f 0522 	mvneq.w	r5, #34	; 0x22
2000366c:	f06f 0504 	mvnne.w	r5, #4
20003670:	2300      	movs	r3, #0
20003672:	e7d9      	b.n	20003628 <onoff_request+0x3a>
	parent->next = child;
20003674:	601e      	str	r6, [r3, #0]
	list->tail = node;
20003676:	6066      	str	r6, [r4, #4]
}
20003678:	e7eb      	b.n	20003652 <onoff_request+0x64>
		rv = -EAGAIN;
2000367a:	f06f 050a 	mvn.w	r5, #10
2000367e:	e7f7      	b.n	20003670 <onoff_request+0x82>

20003680 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
20003680:	4604      	mov	r4, r0
20003682:	b508      	push	{r3, lr}
20003684:	4608      	mov	r0, r1
20003686:	4611      	mov	r1, r2
	entry(p1, p2, p3);
20003688:	461a      	mov	r2, r3
2000368a:	47a0      	blx	r4
	return z_impl_k_current_get();
2000368c:	f7ff fba4 	bl	20002dd8 <z_impl_k_current_get>
	z_impl_k_thread_abort(thread);
20003690:	f7fd ff60 	bl	20001554 <z_impl_k_thread_abort>

20003694 <chunk_field>:
				 enum chunk_fields f)
{
	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];

	if (big_heap(h)) {
20003694:	6883      	ldr	r3, [r0, #8]
	void *cmem = &buf[c];
20003696:	eb00 01c1 	add.w	r1, r0, r1, lsl #3
	if (big_heap(h)) {
2000369a:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
		return ((uint32_t *)cmem)[f];
2000369e:	bf2c      	ite	cs
200036a0:	f851 0022 	ldrcs.w	r0, [r1, r2, lsl #2]
	} else {
		return ((uint16_t *)cmem)[f];
200036a4:	f831 0012 	ldrhcc.w	r0, [r1, r2, lsl #1]
	}
}
200036a8:	4770      	bx	lr

200036aa <chunk_set>:
			     enum chunk_fields f, chunkid_t val)
{
	CHECK(c <= h->len);

	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];
200036aa:	eb00 01c1 	add.w	r1, r0, r1, lsl #3

	if (big_heap(h)) {
200036ae:	6880      	ldr	r0, [r0, #8]
200036b0:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
		CHECK(val == (uint32_t)val);
		((uint32_t *)cmem)[f] = val;
200036b4:	bf2c      	ite	cs
200036b6:	f841 3022 	strcs.w	r3, [r1, r2, lsl #2]
	} else {
		CHECK(val == (uint16_t)val);
		((uint16_t *)cmem)[f] = val;
200036ba:	f821 3012 	strhcc.w	r3, [r1, r2, lsl #1]
	}
}
200036be:	4770      	bx	lr

200036c0 <chunk_size>:
	return chunk_field(h, c, SIZE_AND_USED) & 1;
}

static inline size_t chunk_size(struct z_heap *h, chunkid_t c)
{
	return chunk_field(h, c, SIZE_AND_USED) >> 1;
200036c0:	2201      	movs	r2, #1
{
200036c2:	b508      	push	{r3, lr}
	return chunk_field(h, c, SIZE_AND_USED) >> 1;
200036c4:	f7ff ffe6 	bl	20003694 <chunk_field>
}
200036c8:	0840      	lsrs	r0, r0, #1
200036ca:	bd08      	pop	{r3, pc}

200036cc <set_chunk_used>:
static inline void set_chunk_used(struct z_heap *h, chunkid_t c, bool used)
{
	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];

	if (big_heap(h)) {
200036cc:	6883      	ldr	r3, [r0, #8]
	void *cmem = &buf[c];
200036ce:	eb00 01c1 	add.w	r1, r0, r1, lsl #3
	if (big_heap(h)) {
200036d2:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
200036d6:	d308      	bcc.n	200036ea <set_chunk_used+0x1e>
		if (used) {
200036d8:	684b      	ldr	r3, [r1, #4]
200036da:	b11a      	cbz	r2, 200036e4 <set_chunk_used+0x18>
			((uint32_t *)cmem)[SIZE_AND_USED] |= 1;
200036dc:	f043 0301 	orr.w	r3, r3, #1
		} else {
			((uint32_t *)cmem)[SIZE_AND_USED] &= ~1;
200036e0:	604b      	str	r3, [r1, #4]
200036e2:	4770      	bx	lr
200036e4:	f023 0301 	bic.w	r3, r3, #1
200036e8:	e7fa      	b.n	200036e0 <set_chunk_used+0x14>
		}
	} else {
		if (used) {
200036ea:	884b      	ldrh	r3, [r1, #2]
200036ec:	b11a      	cbz	r2, 200036f6 <set_chunk_used+0x2a>
			((uint16_t *)cmem)[SIZE_AND_USED] |= 1;
200036ee:	f043 0301 	orr.w	r3, r3, #1
		} else {
			((uint16_t *)cmem)[SIZE_AND_USED] &= ~1;
200036f2:	804b      	strh	r3, [r1, #2]
		}
	}
}
200036f4:	4770      	bx	lr
			((uint16_t *)cmem)[SIZE_AND_USED] &= ~1;
200036f6:	f023 0301 	bic.w	r3, r3, #1
200036fa:	e7fa      	b.n	200036f2 <set_chunk_used+0x26>

200036fc <set_chunk_size>:
 * when its size is modified, and potential set_chunk_used() is always
 * invoked after set_chunk_size().
 */
static inline void set_chunk_size(struct z_heap *h, chunkid_t c, size_t size)
{
	chunk_set(h, c, SIZE_AND_USED, size << 1);
200036fc:	0053      	lsls	r3, r2, #1
200036fe:	2201      	movs	r2, #1
20003700:	f7ff bfd3 	b.w	200036aa <chunk_set>

20003704 <bucket_idx>:
	return big_heap(h) && chunk_size(h, c) == 1;
}

static inline size_t chunk_header_bytes(struct z_heap *h)
{
	return big_heap(h) ? 8 : 4;
20003704:	6880      	ldr	r0, [r0, #8]
	return bytes_to_chunksz(h, 1);
}

static inline int bucket_idx(struct z_heap *h, size_t sz)
{
	size_t usable_sz = sz - min_chunk_size(h) + 1;
20003706:	3101      	adds	r1, #1
	return (bytes + CHUNK_UNIT - 1) / CHUNK_UNIT;
20003708:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
2000370c:	bf2c      	ite	cs
2000370e:	2002      	movcs	r0, #2
20003710:	2001      	movcc	r0, #1
	size_t usable_sz = sz - min_chunk_size(h) + 1;
20003712:	1a08      	subs	r0, r1, r0
	return 31 - __builtin_clz(usable_sz);
20003714:	fab0 f080 	clz	r0, r0
}
20003718:	f1c0 001f 	rsb	r0, r0, #31
2000371c:	4770      	bx	lr

2000371e <free_list_add>:
		set_prev_free_chunk(h, second, c);
	}
}

static void free_list_add(struct z_heap *h, chunkid_t c)
{
2000371e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
20003722:	4604      	mov	r4, r0
20003724:	460d      	mov	r5, r1
	return sizeof(void *) > 4 || chunks > 0x7fff;
20003726:	f7ff ffcb 	bl	200036c0 <chunk_size>
	return big_heap(h) && chunk_size(h, c) == 1;
2000372a:	68a3      	ldr	r3, [r4, #8]
2000372c:	4601      	mov	r1, r0
2000372e:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
20003732:	d301      	bcc.n	20003738 <free_list_add+0x1a>
	if (!solo_free_header(h, c)) {
20003734:	2801      	cmp	r0, #1
20003736:	d035      	beq.n	200037a4 <free_list_add+0x86>
		int bidx = bucket_idx(h, chunk_size(h, c));
20003738:	4620      	mov	r0, r4
2000373a:	f7ff ffe3 	bl	20003704 <bucket_idx>
	if (b->next == 0) {
2000373e:	eb04 0280 	add.w	r2, r4, r0, lsl #2
20003742:	6916      	ldr	r6, [r2, #16]
20003744:	b99e      	cbnz	r6, 2000376e <free_list_add+0x50>
		h->avail_buckets |= (1 << bidx);
20003746:	2301      	movs	r3, #1
20003748:	fa03 f000 	lsl.w	r0, r3, r0
2000374c:	68e3      	ldr	r3, [r4, #12]
	chunk_set(h, c, FREE_PREV, prev);
2000374e:	4629      	mov	r1, r5
20003750:	4303      	orrs	r3, r0
20003752:	60e3      	str	r3, [r4, #12]
20003754:	4620      	mov	r0, r4
		b->next = c;
20003756:	6115      	str	r5, [r2, #16]
20003758:	462b      	mov	r3, r5
2000375a:	2202      	movs	r2, #2
2000375c:	f7ff ffa5 	bl	200036aa <chunk_set>
	chunk_set(h, c, FREE_NEXT, next);
20003760:	2203      	movs	r2, #3
20003762:	4629      	mov	r1, r5
	chunk_set(h, c, FREE_PREV, prev);
20003764:	4620      	mov	r0, r4
		free_list_add_bidx(h, c, bidx);
	}
}
20003766:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
2000376a:	f7ff bf9e 	b.w	200036aa <chunk_set>
	return chunk_field(h, c, FREE_PREV);
2000376e:	2202      	movs	r2, #2
20003770:	4631      	mov	r1, r6
20003772:	4620      	mov	r0, r4
20003774:	f7ff ff8e 	bl	20003694 <chunk_field>
20003778:	4607      	mov	r7, r0
	chunk_set(h, c, FREE_PREV, prev);
2000377a:	4603      	mov	r3, r0
2000377c:	2202      	movs	r2, #2
2000377e:	4629      	mov	r1, r5
20003780:	4620      	mov	r0, r4
20003782:	f7ff ff92 	bl	200036aa <chunk_set>
	chunk_set(h, c, FREE_NEXT, next);
20003786:	4633      	mov	r3, r6
20003788:	2203      	movs	r2, #3
2000378a:	4629      	mov	r1, r5
2000378c:	4620      	mov	r0, r4
2000378e:	f7ff ff8c 	bl	200036aa <chunk_set>
20003792:	2203      	movs	r2, #3
20003794:	4639      	mov	r1, r7
20003796:	462b      	mov	r3, r5
20003798:	4620      	mov	r0, r4
2000379a:	f7ff ff86 	bl	200036aa <chunk_set>
	chunk_set(h, c, FREE_PREV, prev);
2000379e:	2202      	movs	r2, #2
200037a0:	4631      	mov	r1, r6
200037a2:	e7df      	b.n	20003764 <free_list_add+0x46>
200037a4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

200037a8 <sys_heap_init>:
	return big_heap_bytes(size) ? 8 : 4;
200037a8:	f5b2 2f80 	cmp.w	r2, #262144	; 0x40000
	set_chunk_used(h, c, true);
	return mem;
}

void sys_heap_init(struct sys_heap *heap, void *mem, size_t bytes)
{
200037ac:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
200037ae:	bf2c      	ite	cs
200037b0:	2508      	movcs	r5, #8
200037b2:	2504      	movcc	r5, #4
	CHECK(end > addr);
	__ASSERT(buf_sz > chunksz(sizeof(struct z_heap)), "heap size is too small");

	struct z_heap *h = (struct z_heap *)addr;
	heap->heap = h;
	h->chunk0_hdr_area = 0;
200037b4:	2300      	movs	r3, #0
	bytes -= heap_footer_bytes(bytes);
200037b6:	1b55      	subs	r5, r2, r5
	h->chunk0_hdr_area = 0;
200037b8:	2200      	movs	r2, #0
	uintptr_t addr = ROUND_UP(mem, CHUNK_UNIT);
200037ba:	1dcc      	adds	r4, r1, #7
200037bc:	f024 0407 	bic.w	r4, r4, #7
	heap->heap = h;
200037c0:	6004      	str	r4, [r0, #0]
	h->chunk0_hdr_area = 0;
200037c2:	e9c4 2300 	strd	r2, r3, [r4]
	h->len = buf_sz;
	h->avail_buckets = 0;
200037c6:	2300      	movs	r3, #0
	uintptr_t end = ROUND_DOWN((uint8_t *)mem + bytes, CHUNK_UNIT);
200037c8:	440d      	add	r5, r1
200037ca:	f025 0507 	bic.w	r5, r5, #7
	size_t buf_sz = (end - addr) / CHUNK_UNIT;
200037ce:	1b2d      	subs	r5, r5, r4
200037d0:	08ed      	lsrs	r5, r5, #3

	int nb_buckets = bucket_idx(h, buf_sz) + 1;
200037d2:	4629      	mov	r1, r5
200037d4:	4620      	mov	r0, r4
	h->len = buf_sz;
200037d6:	60a5      	str	r5, [r4, #8]
	h->avail_buckets = 0;
200037d8:	60e3      	str	r3, [r4, #12]
	int nb_buckets = bucket_idx(h, buf_sz) + 1;
200037da:	f7ff ff93 	bl	20003704 <bucket_idx>
	size_t chunk0_size = chunksz(sizeof(struct z_heap) +
200037de:	0086      	lsls	r6, r0, #2
	int nb_buckets = bucket_idx(h, buf_sz) + 1;
200037e0:	1c41      	adds	r1, r0, #1
				     nb_buckets * sizeof(struct z_heap_bucket));

	__ASSERT(chunk0_size + min_chunk_size(h) < buf_sz, "heap size is too small");

	for (int i = 0; i < nb_buckets; i++) {
		h->buckets[i].next = 0;
200037e2:	4618      	mov	r0, r3
	return (bytes + CHUNK_UNIT - 1) / CHUNK_UNIT;
200037e4:	361b      	adds	r6, #27
200037e6:	08f6      	lsrs	r6, r6, #3
	for (int i = 0; i < nb_buckets; i++) {
200037e8:	f104 0210 	add.w	r2, r4, #16
200037ec:	428b      	cmp	r3, r1
200037ee:	db29      	blt.n	20003844 <sys_heap_init+0x9c>
	}

	/* chunk containing our struct z_heap */
	set_chunk_size(h, 0, chunk0_size);
200037f0:	4632      	mov	r2, r6
200037f2:	4620      	mov	r0, r4
200037f4:	2100      	movs	r1, #0
200037f6:	f7ff ff81 	bl	200036fc <set_chunk_size>
	set_chunk_used(h, 0, true);

	/* chunk containing the free heap */
	set_chunk_size(h, chunk0_size, buf_sz - chunk0_size);
200037fa:	1baf      	subs	r7, r5, r6
	set_chunk_used(h, 0, true);
200037fc:	4620      	mov	r0, r4
200037fe:	2201      	movs	r2, #1
20003800:	2100      	movs	r1, #0
20003802:	f7ff ff63 	bl	200036cc <set_chunk_used>
	set_chunk_size(h, chunk0_size, buf_sz - chunk0_size);
20003806:	463a      	mov	r2, r7
20003808:	4631      	mov	r1, r6
2000380a:	f7ff ff77 	bl	200036fc <set_chunk_size>
	chunk_set(h, c, LEFT_SIZE, size);
2000380e:	4633      	mov	r3, r6
20003810:	4631      	mov	r1, r6
20003812:	4620      	mov	r0, r4
20003814:	2200      	movs	r2, #0
20003816:	f7ff ff48 	bl	200036aa <chunk_set>
	set_left_chunk_size(h, chunk0_size, chunk0_size);

	/* the end marker chunk */
	set_chunk_size(h, buf_sz, 0);
2000381a:	4629      	mov	r1, r5
2000381c:	4620      	mov	r0, r4
2000381e:	2200      	movs	r2, #0
20003820:	f7ff ff6c 	bl	200036fc <set_chunk_size>
20003824:	463b      	mov	r3, r7
20003826:	4629      	mov	r1, r5
20003828:	4620      	mov	r0, r4
2000382a:	2200      	movs	r2, #0
2000382c:	f7ff ff3d 	bl	200036aa <chunk_set>
	set_left_chunk_size(h, buf_sz, buf_sz - chunk0_size);
	set_chunk_used(h, buf_sz, true);
20003830:	4629      	mov	r1, r5
20003832:	4620      	mov	r0, r4
20003834:	2201      	movs	r2, #1
20003836:	f7ff ff49 	bl	200036cc <set_chunk_used>

	free_list_add(h, chunk0_size);
2000383a:	4631      	mov	r1, r6
}
2000383c:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
	free_list_add(h, chunk0_size);
20003840:	f7ff bf6d 	b.w	2000371e <free_list_add>
		h->buckets[i].next = 0;
20003844:	f842 0b04 	str.w	r0, [r2], #4
	for (int i = 0; i < nb_buckets; i++) {
20003848:	3301      	adds	r3, #1
2000384a:	e7cf      	b.n	200037ec <sys_heap_init+0x44>

2000384c <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM(CONFIG_OUTPUT_PRINT_MEMORY_USAGE, 1);
GEN_ABSOLUTE_SYM(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM(CONFIG_REBOOT, 1);
GEN_ABSOLUTE_SYM(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
2000384c:	4770      	bx	lr

2000384e <z_platform_init>:

void z_platform_init(void)
{
	SystemInit();
2000384e:	f7fe bb47 	b.w	20001ee0 <SystemInit>

20003852 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
20003852:	b2cb      	uxtb	r3, r1
20003854:	210c      	movs	r1, #12
20003856:	68c2      	ldr	r2, [r0, #12]
20003858:	fb03 2101 	mla	r1, r3, r1, r2
2000385c:	6dc8      	ldr	r0, [r1, #92]	; 0x5c
}
2000385e:	f000 0007 	and.w	r0, r0, #7
20003862:	4770      	bx	lr

20003864 <set_off_state>:
	__asm__ volatile(
20003864:	f04f 0320 	mov.w	r3, #32
20003868:	f3ef 8211 	mrs	r2, BASEPRI
2000386c:	f383 8811 	msr	BASEPRI, r3
20003870:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
20003874:	6803      	ldr	r3, [r0, #0]
	if ((current_ctx != 0) && (current_ctx != ctx)) {
20003876:	f013 03c0 	ands.w	r3, r3, #192	; 0xc0
2000387a:	d001      	beq.n	20003880 <set_off_state+0x1c>
2000387c:	428b      	cmp	r3, r1
2000387e:	d107      	bne.n	20003890 <set_off_state+0x2c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
20003880:	2301      	movs	r3, #1
20003882:	6003      	str	r3, [r0, #0]
	int err = 0;
20003884:	2000      	movs	r0, #0
	__asm__ volatile(
20003886:	f382 8811 	msr	BASEPRI, r2
2000388a:	f3bf 8f6f 	isb	sy
}
2000388e:	4770      	bx	lr
		err = -EPERM;
20003890:	f04f 30ff 	mov.w	r0, #4294967295
20003894:	e7f7      	b.n	20003886 <set_off_state+0x22>

20003896 <set_starting_state>:
{
20003896:	b510      	push	{r4, lr}
	__asm__ volatile(
20003898:	f04f 0320 	mov.w	r3, #32
2000389c:	f3ef 8211 	mrs	r2, BASEPRI
200038a0:	f383 8811 	msr	BASEPRI, r3
200038a4:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
200038a8:	6803      	ldr	r3, [r0, #0]
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
200038aa:	f003 0407 	and.w	r4, r3, #7
200038ae:	2c01      	cmp	r4, #1
200038b0:	d106      	bne.n	200038c0 <set_starting_state+0x2a>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
200038b2:	6001      	str	r1, [r0, #0]
	int err = 0;
200038b4:	2000      	movs	r0, #0
	__asm__ volatile(
200038b6:	f382 8811 	msr	BASEPRI, r2
200038ba:	f3bf 8f6f 	isb	sy
}
200038be:	bd10      	pop	{r4, pc}
	uint32_t current_ctx = GET_CTX(*flags);
200038c0:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
	} else if (current_ctx != ctx) {
200038c4:	428b      	cmp	r3, r1
		err = -EBUSY;
200038c6:	bf14      	ite	ne
200038c8:	f04f 30ff 	movne.w	r0, #4294967295
200038cc:	f06f 000f 	mvneq.w	r0, #15
200038d0:	e7f1      	b.n	200038b6 <set_starting_state+0x20>

200038d2 <set_on_state>:
	__asm__ volatile(
200038d2:	f04f 0320 	mov.w	r3, #32
200038d6:	f3ef 8211 	mrs	r2, BASEPRI
200038da:	f383 8811 	msr	BASEPRI, r3
200038de:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
200038e2:	6803      	ldr	r3, [r0, #0]
200038e4:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
200038e8:	f043 0302 	orr.w	r3, r3, #2
200038ec:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
200038ee:	f382 8811 	msr	BASEPRI, r2
200038f2:	f3bf 8f6f 	isb	sy
}
200038f6:	4770      	bx	lr

200038f8 <onoff_started_callback>:
{
200038f8:	b410      	push	{r4}
	notify(mgr, 0);
200038fa:	241c      	movs	r4, #28
	return &data->mgr[type];
200038fc:	68c0      	ldr	r0, [r0, #12]
200038fe:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
20003900:	fb03 0004 	mla	r0, r3, r4, r0
20003904:	2100      	movs	r1, #0
}
20003906:	bc10      	pop	{r4}
	notify(mgr, 0);
20003908:	4710      	bx	r2

2000390a <blocking_start_callback>:
{
2000390a:	4610      	mov	r0, r2
		arch_syscall_invoke1(*(uintptr_t *)&sem, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
2000390c:	f7ff ba6a 	b.w	20002de4 <z_impl_k_sem_give>

20003910 <hfclk192m_stop>:
	nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK192M);
20003910:	2002      	movs	r0, #2
20003912:	f7fe bbbb 	b.w	2000208c <nrfx_clock_stop>

20003916 <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
20003916:	2000      	movs	r0, #0
20003918:	f7fe bbb8 	b.w	2000208c <nrfx_clock_stop>

2000391c <hfclk192m_start>:
	nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK192M);
2000391c:	2002      	movs	r0, #2
2000391e:	f7fe bb61 	b.w	20001fe4 <nrfx_clock_start>

20003922 <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
20003922:	2000      	movs	r0, #0
20003924:	f7fe bb5e 	b.w	20001fe4 <nrfx_clock_start>

20003928 <api_stop>:
{
20003928:	b538      	push	{r3, r4, r5, lr}
	err = set_off_state(&subdata->flags, ctx);
2000392a:	230c      	movs	r3, #12
2000392c:	b2cc      	uxtb	r4, r1
2000392e:	4363      	muls	r3, r4
{
20003930:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
20003932:	68c0      	ldr	r0, [r0, #12]
20003934:	335c      	adds	r3, #92	; 0x5c
20003936:	2180      	movs	r1, #128	; 0x80
20003938:	4418      	add	r0, r3
2000393a:	f7ff ff93 	bl	20003864 <set_off_state>
	if (err < 0) {
2000393e:	2800      	cmp	r0, #0
20003940:	db05      	blt.n	2000394e <api_stop+0x26>
	get_sub_config(dev, type)->stop();
20003942:	6869      	ldr	r1, [r5, #4]
20003944:	eb01 04c4 	add.w	r4, r1, r4, lsl #3
20003948:	6863      	ldr	r3, [r4, #4]
2000394a:	4798      	blx	r3
	return 0;
2000394c:	2000      	movs	r0, #0
}
2000394e:	bd38      	pop	{r3, r4, r5, pc}

20003950 <api_start>:
{
20003950:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	err = set_starting_state(&subdata->flags, ctx);
20003954:	f04f 080c 	mov.w	r8, #12
20003958:	b2cd      	uxtb	r5, r1
2000395a:	fb08 f805 	mul.w	r8, r8, r5
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
2000395e:	68c4      	ldr	r4, [r0, #12]
{
20003960:	4606      	mov	r6, r0
	err = set_starting_state(&subdata->flags, ctx);
20003962:	f108 005c 	add.w	r0, r8, #92	; 0x5c
20003966:	2180      	movs	r1, #128	; 0x80
20003968:	4420      	add	r0, r4
{
2000396a:	4617      	mov	r7, r2
	err = set_starting_state(&subdata->flags, ctx);
2000396c:	f7ff ff93 	bl	20003896 <set_starting_state>
	if (err < 0) {
20003970:	2800      	cmp	r0, #0
20003972:	db09      	blt.n	20003988 <api_start+0x38>
	subdata->cb = data->cb;
20003974:	687b      	ldr	r3, [r7, #4]
20003976:	4444      	add	r4, r8
20003978:	6563      	str	r3, [r4, #84]	; 0x54
	subdata->user_data = data->user_data;
2000397a:	68bb      	ldr	r3, [r7, #8]
2000397c:	65a3      	str	r3, [r4, #88]	; 0x58
	 get_sub_config(dev, type)->start();
2000397e:	6873      	ldr	r3, [r6, #4]
20003980:	f853 3035 	ldr.w	r3, [r3, r5, lsl #3]
20003984:	4798      	blx	r3
	return 0;
20003986:	2000      	movs	r0, #0
}
20003988:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

2000398c <z_clock_isr>:
/* Weak-linked noop defaults for optional driver interfaces: */

void __weak z_clock_isr(void *arg)
{
	__ASSERT_NO_MSG(false);
}
2000398c:	4770      	bx	lr

2000398e <z_clock_idle_exit>:
{
}

void __weak z_clock_idle_exit(void)
{
}
2000398e:	4770      	bx	lr

20003990 <sys_clock_disable>:
20003990:	4770      	bx	lr

20003992 <abort_function>:
	sys_reboot(SYS_REBOOT_WARM);
20003992:	2000      	movs	r0, #0
20003994:	f7fd b83c 	b.w	20000a10 <sys_reboot>

20003998 <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
20003998:	2100      	movs	r1, #0
2000399a:	2001      	movs	r0, #1
2000399c:	f000 b804 	b.w	200039a8 <z_arm_fatal_error>

200039a0 <configure_builtin_stack_guard>:
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
200039a0:	6e83      	ldr	r3, [r0, #104]	; 0x68
200039a2:	f383 880b 	msr	PSPLIM, r3
}
200039a6:	4770      	bx	lr

200039a8 <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
200039a8:	f000 b9c5 	b.w	20003d36 <z_fatal_error>

200039ac <z_do_kernel_oops>:
 *   fault handler will executed insted of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
200039ac:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
200039ae:	6800      	ldr	r0, [r0, #0]
200039b0:	f000 b9c1 	b.w	20003d36 <z_fatal_error>

200039b4 <z_arm_nmi>:
 *
 * @return N/A
 */

void z_arm_nmi(void)
{
200039b4:	b508      	push	{r3, lr}
	handler();
200039b6:	f7fd fc69 	bl	2000128c <z_SysNmiOnReset>
	z_arm_int_exit();
}
200039ba:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
200039be:	f7fd bd9d 	b.w	200014fc <z_arm_exc_exit>

200039c2 <mpu_configure_region>:
{
200039c2:	b530      	push	{r4, r5, lr}
	get_region_attr_from_k_mem_partition_info(&region_conf.attr,
200039c4:	684b      	ldr	r3, [r1, #4]
	region_conf.base = new_region->start;
200039c6:	680c      	ldr	r4, [r1, #0]
{
200039c8:	b085      	sub	sp, #20
	p_attr->rbar = attr->rbar &
200039ca:	890a      	ldrh	r2, [r1, #8]
200039cc:	7a8d      	ldrb	r5, [r1, #10]
	region_conf.base = new_region->start;
200039ce:	9400      	str	r4, [sp, #0]
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
200039d0:	3b01      	subs	r3, #1
200039d2:	f024 041f 	bic.w	r4, r4, #31
200039d6:	4423      	add	r3, r4
	p_attr->rbar = attr->rbar &
200039d8:	f002 021f 	and.w	r2, r2, #31
200039dc:	ea42 1245 	orr.w	r2, r2, r5, lsl #5
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
200039e0:	f023 031f 	bic.w	r3, r3, #31
	if (index > (get_num_regions() - 1)) {
200039e4:	280f      	cmp	r0, #15
200039e6:	4604      	mov	r4, r0
	p_attr->rbar = attr->rbar &
200039e8:	f88d 2008 	strb.w	r2, [sp, #8]
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
200039ec:	9303      	str	r3, [sp, #12]
200039ee:	d805      	bhi.n	200039fc <mpu_configure_region+0x3a>
	region_init(index, region_conf);
200039f0:	4669      	mov	r1, sp
200039f2:	f7fd fe05 	bl	20001600 <region_init>
}
200039f6:	4620      	mov	r0, r4
200039f8:	b005      	add	sp, #20
200039fa:	bd30      	pop	{r4, r5, pc}
		return -EINVAL;
200039fc:	f06f 0415 	mvn.w	r4, #21
	return region_allocate_and_init(index,
20003a00:	e7f9      	b.n	200039f6 <mpu_configure_region+0x34>

20003a02 <arm_cmse_mpu_region_get>:
__CMSE_TT_ASM ()

__extension__ static __inline __attribute__ ((__always_inline__))
cmse_address_info_t
cmse_TT (void *__p)
__CMSE_TT_ASM ()
20003a02:	e840 f300 	tt	r3, r0

int arm_cmse_mpu_region_get(uint32_t addr)
{
	cmse_address_info_t addr_info =	cmse_TT((void *)addr);

	if (addr_info.flags.mpu_region_valid) {
20003a06:	f413 3f80 	tst.w	r3, #65536	; 0x10000
20003a0a:	b2d8      	uxtb	r0, r3
		return addr_info.flags.mpu_region;
	}

	return -EINVAL;
}
20003a0c:	bf08      	it	eq
20003a0e:	f06f 0015 	mvneq.w	r0, #21
20003a12:	4770      	bx	lr

20003a14 <strcmp>:
 * @return negative # if <s1> < <s2>, 0 if <s1> == <s2>, else positive #
 */

int strcmp(const char *s1, const char *s2)
{
	while ((*s1 == *s2) && (*s1 != '\0')) {
20003a14:	1e43      	subs	r3, r0, #1
20003a16:	3901      	subs	r1, #1
20003a18:	f813 2f01 	ldrb.w	r2, [r3, #1]!
20003a1c:	f811 0f01 	ldrb.w	r0, [r1, #1]!
20003a20:	4282      	cmp	r2, r0
20003a22:	d101      	bne.n	20003a28 <strcmp+0x14>
20003a24:	2a00      	cmp	r2, #0
20003a26:	d1f7      	bne.n	20003a18 <strcmp+0x4>
		s1++;
		s2++;
	}

	return *s1 - *s2;
}
20003a28:	1a10      	subs	r0, r2, r0
20003a2a:	4770      	bx	lr

20003a2c <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *_MLIBC_RESTRICT d, const void *_MLIBC_RESTRICT s, size_t n)
{
20003a2c:	b5f0      	push	{r4, r5, r6, r7, lr}

	unsigned char *d_byte = (unsigned char *)d;
	const unsigned char *s_byte = (const unsigned char *)s;
	const uintptr_t mask = sizeof(mem_word_t) - 1;

	if ((((uintptr_t)d ^ (uintptr_t)s_byte) & mask) == 0) {
20003a2e:	ea81 0400 	eor.w	r4, r1, r0
20003a32:	07a5      	lsls	r5, r4, #30
20003a34:	4603      	mov	r3, r0
20003a36:	d00b      	beq.n	20003a50 <memcpy+0x24>
20003a38:	3b01      	subs	r3, #1
20003a3a:	440a      	add	r2, r1
		s_byte = (unsigned char *)s_word;
	}

	/* do byte-sized copying until finished */

	while (n > 0) {
20003a3c:	4291      	cmp	r1, r2
20003a3e:	d11b      	bne.n	20003a78 <memcpy+0x4c>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
20003a40:	bdf0      	pop	{r4, r5, r6, r7, pc}
			if (n == 0) {
20003a42:	2a00      	cmp	r2, #0
20003a44:	d0fc      	beq.n	20003a40 <memcpy+0x14>
			*(d_byte++) = *(s_byte++);
20003a46:	f811 4b01 	ldrb.w	r4, [r1], #1
			n--;
20003a4a:	3a01      	subs	r2, #1
			*(d_byte++) = *(s_byte++);
20003a4c:	f803 4b01 	strb.w	r4, [r3], #1
		while (((uintptr_t)d_byte) & mask) {
20003a50:	079c      	lsls	r4, r3, #30
20003a52:	d1f6      	bne.n	20003a42 <memcpy+0x16>
20003a54:	f022 0403 	bic.w	r4, r2, #3
20003a58:	1f1d      	subs	r5, r3, #4
20003a5a:	0896      	lsrs	r6, r2, #2
20003a5c:	190f      	adds	r7, r1, r4
		while (n >= sizeof(mem_word_t)) {
20003a5e:	42b9      	cmp	r1, r7
20003a60:	d105      	bne.n	20003a6e <memcpy+0x42>
20003a62:	f06f 0503 	mvn.w	r5, #3
20003a66:	4423      	add	r3, r4
20003a68:	fb05 2206 	mla	r2, r5, r6, r2
20003a6c:	e7e4      	b.n	20003a38 <memcpy+0xc>
			*(d_word++) = *(s_word++);
20003a6e:	f851 cb04 	ldr.w	ip, [r1], #4
20003a72:	f845 cf04 	str.w	ip, [r5, #4]!
			n -= sizeof(mem_word_t);
20003a76:	e7f2      	b.n	20003a5e <memcpy+0x32>
		*(d_byte++) = *(s_byte++);
20003a78:	f811 4b01 	ldrb.w	r4, [r1], #1
20003a7c:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
20003a80:	e7dc      	b.n	20003a3c <memcpy+0x10>

20003a82 <memset>:

void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
20003a82:	4603      	mov	r3, r0
{
20003a84:	b570      	push	{r4, r5, r6, lr}
	unsigned char c_byte = (unsigned char)c;
20003a86:	b2c9      	uxtb	r1, r1

	while (((uintptr_t)d_byte) & (sizeof(mem_word_t) - 1)) {
20003a88:	079c      	lsls	r4, r3, #30
20003a8a:	d111      	bne.n	20003ab0 <memset+0x2e>
	/* do word-sized initialization as long as possible */

	mem_word_t *d_word = (mem_word_t *)d_byte;
	mem_word_t c_word = (mem_word_t)c_byte;

	c_word |= c_word << 8;
20003a8c:	ea41 2401 	orr.w	r4, r1, r1, lsl #8
	c_word |= c_word << 16;
20003a90:	f022 0603 	bic.w	r6, r2, #3
20003a94:	ea44 4504 	orr.w	r5, r4, r4, lsl #16
#if Z_MEM_WORD_T_WIDTH > 32
	c_word |= c_word << 32;
#endif

	while (n >= sizeof(mem_word_t)) {
20003a98:	441e      	add	r6, r3
20003a9a:	0894      	lsrs	r4, r2, #2
20003a9c:	42b3      	cmp	r3, r6
20003a9e:	d10d      	bne.n	20003abc <memset+0x3a>
20003aa0:	f06f 0503 	mvn.w	r5, #3
20003aa4:	fb05 2204 	mla	r2, r5, r4, r2
20003aa8:	441a      	add	r2, r3

	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;

	while (n > 0) {
20003aaa:	4293      	cmp	r3, r2
20003aac:	d109      	bne.n	20003ac2 <memset+0x40>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
20003aae:	bd70      	pop	{r4, r5, r6, pc}
		if (n == 0) {
20003ab0:	2a00      	cmp	r2, #0
20003ab2:	d0fc      	beq.n	20003aae <memset+0x2c>
		*(d_byte++) = c_byte;
20003ab4:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
20003ab8:	3a01      	subs	r2, #1
20003aba:	e7e5      	b.n	20003a88 <memset+0x6>
		*(d_word++) = c_word;
20003abc:	f843 5b04 	str.w	r5, [r3], #4
		n -= sizeof(mem_word_t);
20003ac0:	e7ec      	b.n	20003a9c <memset+0x1a>
		*(d_byte++) = c_byte;
20003ac2:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
20003ac6:	e7f0      	b.n	20003aaa <memset+0x28>

20003ac8 <_stdout_hook_default>:
}
20003ac8:	f04f 30ff 	mov.w	r0, #4294967295
20003acc:	4770      	bx	lr

20003ace <gpio_fire_callbacks>:
 * @param pins The actual pin mask that triggered the interrupt
 */
static inline void gpio_fire_callbacks(sys_slist_t *list,
					const struct device *port,
					uint32_t pins)
{
20003ace:	b570      	push	{r4, r5, r6, lr}
20003ad0:	460e      	mov	r6, r1
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
20003ad2:	6801      	ldr	r1, [r0, #0]
{
20003ad4:	4615      	mov	r5, r2
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
20003ad6:	b189      	cbz	r1, 20003afc <gpio_fire_callbacks+0x2e>
	return node->next;
20003ad8:	680c      	ldr	r4, [r1, #0]
20003ada:	2c00      	cmp	r4, #0
20003adc:	bf38      	it	cc
20003ade:	2400      	movcc	r4, #0
		if (cb->pin_mask & pins) {
20003ae0:	688a      	ldr	r2, [r1, #8]
20003ae2:	402a      	ands	r2, r5
20003ae4:	d002      	beq.n	20003aec <gpio_fire_callbacks+0x1e>
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
20003ae6:	4630      	mov	r0, r6
20003ae8:	684b      	ldr	r3, [r1, #4]
20003aea:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
20003aec:	b134      	cbz	r4, 20003afc <gpio_fire_callbacks+0x2e>
20003aee:	6823      	ldr	r3, [r4, #0]
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
20003af0:	4621      	mov	r1, r4
20003af2:	2b00      	cmp	r3, #0
20003af4:	bf38      	it	cc
20003af6:	2300      	movcc	r3, #0
20003af8:	461c      	mov	r4, r3
20003afa:	e7f1      	b.n	20003ae0 <gpio_fire_callbacks+0x12>
		}
	}
}
20003afc:	bd70      	pop	{r4, r5, r6, pc}

20003afe <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
20003afe:	6843      	ldr	r3, [r0, #4]
}
20003b00:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
20003b02:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
20003b04:	691b      	ldr	r3, [r3, #16]
	*value = nrf_gpio_port_in_read(reg);
20003b06:	600b      	str	r3, [r1, #0]
}
20003b08:	4770      	bx	lr

20003b0a <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
20003b0a:	6843      	ldr	r3, [r0, #4]
20003b0c:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
20003b0e:	6858      	ldr	r0, [r3, #4]
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
20003b10:	4042      	eors	r2, r0
20003b12:	400a      	ands	r2, r1
20003b14:	4042      	eors	r2, r0
    p_reg->OUT = value;
20003b16:	605a      	str	r2, [r3, #4]
}
20003b18:	2000      	movs	r0, #0
20003b1a:	4770      	bx	lr

20003b1c <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
20003b1c:	6843      	ldr	r3, [r0, #4]
}
20003b1e:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
20003b20:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTSET = set_mask;
20003b22:	6099      	str	r1, [r3, #8]
}
20003b24:	4770      	bx	lr

20003b26 <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
20003b26:	6843      	ldr	r3, [r0, #4]
}
20003b28:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
20003b2a:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTCLR = clr_mask;
20003b2c:	60d9      	str	r1, [r3, #12]
}
20003b2e:	4770      	bx	lr

20003b30 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
20003b30:	6843      	ldr	r3, [r0, #4]
}
20003b32:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
20003b34:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
20003b36:	6853      	ldr	r3, [r2, #4]
	nrf_gpio_port_out_write(reg, value ^ mask);
20003b38:	404b      	eors	r3, r1
    p_reg->OUT = value;
20003b3a:	6053      	str	r3, [r2, #4]
}
20003b3c:	4770      	bx	lr

20003b3e <gpio_nrfx_manage_callback>:
	return gpio_manage_callback(&get_port_data(port)->callbacks,
20003b3e:	68c3      	ldr	r3, [r0, #12]
{
20003b40:	b530      	push	{r4, r5, lr}
Z_GENLIST_IS_EMPTY(slist)
20003b42:	6858      	ldr	r0, [r3, #4]
	if (!sys_slist_is_empty(callbacks)) {
20003b44:	b158      	cbz	r0, 20003b5e <gpio_nrfx_manage_callback+0x20>
 * @return true if node was removed
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

Z_GENLIST_FIND_AND_REMOVE(slist, snode)
20003b46:	2400      	movs	r4, #0
20003b48:	4281      	cmp	r1, r0
20003b4a:	d113      	bne.n	20003b74 <gpio_nrfx_manage_callback+0x36>
Z_GENLIST_REMOVE(slist, snode)
20003b4c:	6808      	ldr	r0, [r1, #0]
20003b4e:	b95c      	cbnz	r4, 20003b68 <gpio_nrfx_manage_callback+0x2a>
20003b50:	689c      	ldr	r4, [r3, #8]
	list->head = node;
20003b52:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
20003b54:	42a1      	cmp	r1, r4
20003b56:	d100      	bne.n	20003b5a <gpio_nrfx_manage_callback+0x1c>
	list->tail = node;
20003b58:	6098      	str	r0, [r3, #8]
	parent->next = child;
20003b5a:	2000      	movs	r0, #0
20003b5c:	6008      	str	r0, [r1, #0]
	if (set) {
20003b5e:	b972      	cbnz	r2, 20003b7e <gpio_nrfx_manage_callback+0x40>
	return 0;
20003b60:	2000      	movs	r0, #0
}
20003b62:	bd30      	pop	{r4, r5, pc}
20003b64:	4628      	mov	r0, r5
20003b66:	e7ef      	b.n	20003b48 <gpio_nrfx_manage_callback+0xa>
20003b68:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
20003b6a:	6898      	ldr	r0, [r3, #8]
20003b6c:	4281      	cmp	r1, r0
	list->tail = node;
20003b6e:	bf08      	it	eq
20003b70:	609c      	streq	r4, [r3, #8]
}
20003b72:	e7f2      	b.n	20003b5a <gpio_nrfx_manage_callback+0x1c>
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
20003b74:	6805      	ldr	r5, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
20003b76:	4604      	mov	r4, r0
20003b78:	2d00      	cmp	r5, #0
20003b7a:	d1f3      	bne.n	20003b64 <gpio_nrfx_manage_callback+0x26>
			if (!set) {
20003b7c:	b13a      	cbz	r2, 20003b8e <gpio_nrfx_manage_callback+0x50>
Z_GENLIST_PREPEND(slist, snode)
20003b7e:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
20003b80:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
20003b82:	6898      	ldr	r0, [r3, #8]
	list->head = node;
20003b84:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
20003b86:	2800      	cmp	r0, #0
20003b88:	d1ea      	bne.n	20003b60 <gpio_nrfx_manage_callback+0x22>
	list->tail = node;
20003b8a:	6099      	str	r1, [r3, #8]
}
20003b8c:	e7e9      	b.n	20003b62 <gpio_nrfx_manage_callback+0x24>
				return -EINVAL;
20003b8e:	f06f 0015 	mvn.w	r0, #21
	return gpio_manage_callback(&get_port_data(port)->callbacks,
20003b92:	e7e6      	b.n	20003b62 <gpio_nrfx_manage_callback+0x24>

20003b94 <check_level_trigger_pins>:
{
20003b94:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint32_t bit = 1U << pin;
20003b98:	2601      	movs	r6, #1
	uint32_t pin = 0U;
20003b9a:	2700      	movs	r7, #0
	struct gpio_nrfx_data *data = get_port_data(port);
20003b9c:	68c3      	ldr	r3, [r0, #12]
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
20003b9e:	f8d0 8004 	ldr.w	r8, [r0, #4]
	uint32_t out = data->pin_int_en;
20003ba2:	68dc      	ldr	r4, [r3, #12]
	out &= ~data->trig_edge & ~data->double_edge;
20003ba4:	e9d3 2105 	ldrd	r2, r1, [r3, #20]
20003ba8:	430a      	orrs	r2, r1
20003baa:	ea24 0402 	bic.w	r4, r4, r2
	uint32_t port_in = nrf_gpio_port_in_read(cfg->port);
20003bae:	f8d8 2004 	ldr.w	r2, [r8, #4]
	uint32_t pin_states = ~(port_in ^ data->int_active_level);
20003bb2:	691b      	ldr	r3, [r3, #16]
    return p_reg->IN;
20003bb4:	6915      	ldr	r5, [r2, #16]
20003bb6:	405d      	eors	r5, r3
	uint32_t out = pin_states & level_pins;
20003bb8:	ea24 0505 	bic.w	r5, r4, r5
	while (level_pins) {
20003bbc:	b914      	cbnz	r4, 20003bc4 <check_level_trigger_pins+0x30>
}
20003bbe:	4628      	mov	r0, r5
20003bc0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		if (level_pins & bit) {
20003bc4:	4234      	tst	r4, r6
20003bc6:	d00a      	beq.n	20003bde <check_level_trigger_pins+0x4a>
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
20003bc8:	f898 3008 	ldrb.w	r3, [r8, #8]
20003bcc:	f007 001f 	and.w	r0, r7, #31
			nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
20003bd0:	2100      	movs	r1, #0
20003bd2:	ea40 1043 	orr.w	r0, r0, r3, lsl #5
20003bd6:	f7fd fedf 	bl	20001998 <nrf_gpio_cfg_sense_set>
			level_pins &= ~bit;
20003bda:	ea24 0406 	bic.w	r4, r4, r6
		++pin;
20003bde:	3701      	adds	r7, #1
		bit <<= 1;
20003be0:	0076      	lsls	r6, r6, #1
20003be2:	e7eb      	b.n	20003bbc <check_level_trigger_pins+0x28>

20003be4 <cfg_level_pins>:
{
20003be4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint32_t bit = 1U << pin;
20003be8:	2601      	movs	r6, #1
	uint32_t pin = 0U;
20003bea:	2500      	movs	r5, #0
	const struct gpio_nrfx_data *data = get_port_data(port);
20003bec:	68c7      	ldr	r7, [r0, #12]
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
20003bee:	f8d0 8004 	ldr.w	r8, [r0, #4]
	uint32_t out = data->pin_int_en;
20003bf2:	68fc      	ldr	r4, [r7, #12]
	out &= ~data->trig_edge & ~data->double_edge;
20003bf4:	e9d7 3205 	ldrd	r3, r2, [r7, #20]
20003bf8:	4313      	orrs	r3, r2
20003bfa:	ea24 0403 	bic.w	r4, r4, r3
	while (level_pins) {
20003bfe:	b90c      	cbnz	r4, 20003c04 <cfg_level_pins+0x20>
}
20003c00:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		if (level_pins & bit) {
20003c04:	4226      	tst	r6, r4
20003c06:	d010      	beq.n	20003c2a <cfg_level_pins+0x46>
	if ((BIT(pin) & data->int_active_level) != 0U) {
20003c08:	6939      	ldr	r1, [r7, #16]
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
20003c0a:	f898 3008 	ldrb.w	r3, [r8, #8]
	if ((BIT(pin) & data->int_active_level) != 0U) {
20003c0e:	40e9      	lsrs	r1, r5
20003c10:	f001 0101 	and.w	r1, r1, #1
20003c14:	f1c1 0103 	rsb	r1, r1, #3
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
20003c18:	f005 001f 	and.w	r0, r5, #31
			nrf_gpio_cfg_sense_set(abs_pin, sense);
20003c1c:	b2c9      	uxtb	r1, r1
20003c1e:	ea40 1043 	orr.w	r0, r0, r3, lsl #5
20003c22:	f7fd feb9 	bl	20001998 <nrf_gpio_cfg_sense_set>
			level_pins &= ~bit;
20003c26:	ea24 0406 	bic.w	r4, r4, r6
		++pin;
20003c2a:	3501      	adds	r5, #1
		bit <<= 1;
20003c2c:	0076      	lsls	r6, r6, #1
20003c2e:	e7e6      	b.n	20003bfe <cfg_level_pins+0x1a>

20003c30 <uarte_nrfx_config_get>:
{
20003c30:	460b      	mov	r3, r1
	*cfg = get_dev_data(dev)->uart_config;
20003c32:	68c2      	ldr	r2, [r0, #12]
20003c34:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
20003c38:	e883 0003 	stmia.w	r3, {r0, r1}
}
20003c3c:	2000      	movs	r0, #0
20003c3e:	4770      	bx	lr

20003c40 <uarte_nrfx_err_check>:
	return config->uarte_regs;
20003c40:	6843      	ldr	r3, [r0, #4]
20003c42:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
20003c44:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
20003c48:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
20003c4c:	4770      	bx	lr

20003c4e <uarte_nrfx_poll_in>:
	return config->uarte_regs;
20003c4e:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = get_dev_data(dev);
20003c50:	68c2      	ldr	r2, [r0, #12]
	return config->uarte_regs;
20003c52:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
20003c54:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
20003c58:	b148      	cbz	r0, 20003c6e <uarte_nrfx_poll_in+0x20>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
20003c5a:	2000      	movs	r0, #0
	*c = data->rx_data;
20003c5c:	7c12      	ldrb	r2, [r2, #16]
20003c5e:	700a      	strb	r2, [r1, #0]
20003c60:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
20003c64:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
20003c68:	2201      	movs	r2, #1
20003c6a:	601a      	str	r2, [r3, #0]
	return 0;
20003c6c:	4770      	bx	lr
		return -1;
20003c6e:	f04f 30ff 	mov.w	r0, #4294967295
}
20003c72:	4770      	bx	lr

20003c74 <uarte_nrfx_poll_out>:
{
20003c74:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
	return config->uarte_regs;
20003c78:	6843      	ldr	r3, [r0, #4]
{
20003c7a:	f88d 1007 	strb.w	r1, [sp, #7]
	return config->uarte_regs;
20003c7e:	681c      	ldr	r4, [r3, #0]
	struct uarte_nrfx_data *data = get_dev_data(dev);
20003c80:	68c6      	ldr	r6, [r0, #12]
	if (!k_is_in_isr()) {
20003c82:	f000 f943 	bl	20003f0c <k_is_in_isr>
20003c86:	bb98      	cbnz	r0, 20003cf0 <uarte_nrfx_poll_out+0x7c>
		lock = &data->poll_out_lock;
20003c88:	2564      	movs	r5, #100	; 0x64
	return __atomic_compare_exchange_n(target, &old_value, new_value,
20003c8a:	f04f 0801 	mov.w	r8, #1
20003c8e:	f106 070c 	add.w	r7, r6, #12
20003c92:	e8d7 3fef 	ldaex	r3, [r7]
20003c96:	2b00      	cmp	r3, #0
20003c98:	d103      	bne.n	20003ca2 <uarte_nrfx_poll_out+0x2e>
20003c9a:	e8c7 8fe2 	stlex	r2, r8, [r7]
20003c9e:	2a00      	cmp	r2, #0
20003ca0:	d1f7      	bne.n	20003c92 <uarte_nrfx_poll_out+0x1e>
		while (atomic_cas((atomic_t *) lock,
20003ca2:	d007      	beq.n	20003cb4 <uarte_nrfx_poll_out+0x40>
	return z_impl_k_sleep(timeout);
20003ca4:	2021      	movs	r0, #33	; 0x21
20003ca6:	2100      	movs	r1, #0
20003ca8:	3d01      	subs	r5, #1
20003caa:	f7ff f875 	bl	20002d98 <z_impl_k_sleep>
			if (--safety_cnt == 0) {
20003cae:	f015 05ff 	ands.w	r5, r5, #255	; 0xff
20003cb2:	d1ee      	bne.n	20003c92 <uarte_nrfx_poll_out+0x1e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
20003cb4:	2300      	movs	r3, #0
20003cb6:	f8c4 3120 	str.w	r3, [r4, #288]	; 0x120
20003cba:	f8d4 3120 	ldr.w	r3, [r4, #288]	; 0x120
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
20003cbe:	f10d 0307 	add.w	r3, sp, #7
20003cc2:	f8c4 3544 	str.w	r3, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
20003cc6:	2301      	movs	r3, #1
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
20003cc8:	f44f 757a 	mov.w	r5, #1000	; 0x3e8
    p_reg->TXD.MAXCNT = length;
20003ccc:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
20003cd0:	60a3      	str	r3, [r4, #8]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
20003cd2:	f8d4 3120 	ldr.w	r3, [r4, #288]	; 0x120
	NRFX_WAIT_FOR(nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX),
20003cd6:	b923      	cbnz	r3, 20003ce2 <uarte_nrfx_poll_out+0x6e>
20003cd8:	2001      	movs	r0, #1
20003cda:	f000 f81a 	bl	20003d12 <nrfx_busy_wait>
20003cde:	3d01      	subs	r5, #1
20003ce0:	d1f7      	bne.n	20003cd2 <uarte_nrfx_poll_out+0x5e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
20003ce2:	2301      	movs	r3, #1
20003ce4:	60e3      	str	r3, [r4, #12]
	*lock = 0;
20003ce6:	2300      	movs	r3, #0
20003ce8:	60f3      	str	r3, [r6, #12]
}
20003cea:	b002      	add	sp, #8
20003cec:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		*lock = 1;
20003cf0:	2301      	movs	r3, #1
20003cf2:	60f3      	str	r3, [r6, #12]
20003cf4:	e7de      	b.n	20003cb4 <uarte_nrfx_poll_out+0x40>

20003cf6 <k_sys_fatal_error_handler>:
	ARG_UNUSED(reason);

	LOG_PANIC();

	LOG_ERR("Resetting system");
	sys_arch_reboot(0);
20003cf6:	2000      	movs	r0, #0
{
20003cf8:	b508      	push	{r3, lr}
	sys_arch_reboot(0);
20003cfa:	f7fd fc0d 	bl	20001518 <sys_arch_reboot>

20003cfe <hw_cc3xx_init>:
#include <nrf_cc3xx_platform.h>

#if CONFIG_HW_CC3XX

static int hw_cc3xx_init(const struct device *dev)
{
20003cfe:	b508      	push	{r3, lr}
	int res;

	__ASSERT_NO_MSG(dev != NULL);

	/* Set the RTOS abort APIs */
	nrf_cc3xx_platform_abort_init();
20003d00:	f7fd f94c 	bl	20000f9c <nrf_cc3xx_platform_abort_init>

	/* Set the RTOS mutex APIs */
	nrf_cc3xx_platform_mutex_init();
20003d04:	f7fd f9ce 	bl	200010a4 <nrf_cc3xx_platform_mutex_init>
	res = nrf_cc3xx_platform_init();
#else
	res = nrf_cc3xx_platform_init_no_rng();
#endif
	return res;
}
20003d08:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	res = nrf_cc3xx_platform_init_no_rng();
20003d0c:	f7ff baac 	b.w	20003268 <nrf_cc3xx_platform_init_no_rng>

20003d10 <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
20003d10:	4700      	bx	r0

20003d12 <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
20003d12:	f000 b901 	b.w	20003f18 <z_impl_k_busy_wait>

20003d16 <nrfx_clock_enable>:
{
20003d16:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
20003d18:	2005      	movs	r0, #5
20003d1a:	f7fd fa3f 	bl	2000119c <arch_irq_is_enabled>
20003d1e:	b910      	cbnz	r0, 20003d26 <nrfx_clock_enable+0x10>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
20003d20:	2005      	movs	r0, #5
20003d22:	f7fd fa2b 	bl	2000117c <arch_irq_enable>
}

#if NRF_CLOCK_HAS_HFCLKSRC
NRF_STATIC_INLINE void nrf_clock_hf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source)
{
    p_reg->HFCLKSRC = (uint32_t)(source);
20003d26:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
20003d2a:	2201      	movs	r2, #1
20003d2c:	f8c3 2514 	str.w	r2, [r3, #1300]	; 0x514
                                   >> CLOCK_HFCLK192MCTRL_HCLK192M_Pos);
}

NRF_STATIC_INLINE void nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source)
{
    p_reg->HFCLK192MSRC = (uint32_t)(source);
20003d30:	f8c3 2580 	str.w	r2, [r3, #1408]	; 0x580
}
20003d34:	bd08      	pop	{r3, pc}

20003d36 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
20003d36:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
20003d38:	4605      	mov	r5, r0
20003d3a:	460e      	mov	r6, r1
	__asm__ volatile(
20003d3c:	f04f 0320 	mov.w	r3, #32
20003d40:	f3ef 8711 	mrs	r7, BASEPRI
20003d44:	f383 8811 	msr	BASEPRI, r3
20003d48:	f3bf 8f6f 	isb	sy
	return z_impl_k_current_get();
20003d4c:	f7ff f844 	bl	20002dd8 <z_impl_k_current_get>
	LOG_ERR("Current thread: %p (%s)", thread,
		log_strdup(thread_name_get(thread)));

	z_coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
20003d50:	4631      	mov	r1, r6
20003d52:	4604      	mov	r4, r0
20003d54:	4628      	mov	r0, r5
20003d56:	f7ff ffce 	bl	20003cf6 <k_sys_fatal_error_handler>
	__asm__ volatile(
20003d5a:	f387 8811 	msr	BASEPRI, r7
20003d5e:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
20003d62:	4620      	mov	r0, r4
#endif /*CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION */
	}

	arch_irq_unlock(key);
	k_thread_abort(thread);
}
20003d64:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
20003d68:	f7fd bbf4 	b.w	20001554 <z_impl_k_thread_abort>

20003d6c <z_sys_power_save_idle_exit>:
	z_clock_idle_exit();
20003d6c:	f7ff be0f 	b.w	2000398e <z_clock_idle_exit>

20003d70 <k_mem_slab_init>:
{
20003d70:	b530      	push	{r4, r5, lr}
	slab->num_used = 0U;
20003d72:	2400      	movs	r4, #0
20003d74:	6184      	str	r4, [r0, #24]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
20003d76:	ea41 0402 	orr.w	r4, r1, r2
20003d7a:	f014 0403 	ands.w	r4, r4, #3
	slab->block_size = block_size;
20003d7e:	e9c0 3202 	strd	r3, r2, [r0, #8]
	slab->buffer = buffer;
20003d82:	6101      	str	r1, [r0, #16]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
20003d84:	d10c      	bne.n	20003da0 <k_mem_slab_init+0x30>
	slab->free_list = NULL;
20003d86:	6144      	str	r4, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
20003d88:	42a3      	cmp	r3, r4
20003d8a:	d103      	bne.n	20003d94 <k_mem_slab_init+0x24>
	list->tail = (sys_dnode_t *)list;
20003d8c:	e9c0 0000 	strd	r0, r0, [r0]
}
20003d90:	2000      	movs	r0, #0
}
20003d92:	bd30      	pop	{r4, r5, pc}
		*(char **)p = slab->free_list;
20003d94:	6945      	ldr	r5, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
20003d96:	3401      	adds	r4, #1
		*(char **)p = slab->free_list;
20003d98:	600d      	str	r5, [r1, #0]
		slab->free_list = p;
20003d9a:	6141      	str	r1, [r0, #20]
		p += slab->block_size;
20003d9c:	4411      	add	r1, r2
	for (j = 0U; j < slab->num_blocks; j++) {
20003d9e:	e7f3      	b.n	20003d88 <k_mem_slab_init+0x18>
		return -EINVAL;
20003da0:	f06f 0015 	mvn.w	r0, #21
	return rc;
20003da4:	e7f5      	b.n	20003d92 <k_mem_slab_init+0x22>

20003da6 <z_impl_k_mutex_init>:
{
20003da6:	4603      	mov	r3, r0
	mutex->owner = NULL;
20003da8:	2000      	movs	r0, #0
20003daa:	e9c3 3300 	strd	r3, r3, [r3]
	mutex->lock_count = 0U;
20003dae:	e9c3 0002 	strd	r0, r0, [r3, #8]
}
20003db2:	4770      	bx	lr

20003db4 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
20003db4:	4603      	mov	r3, r0
20003db6:	b920      	cbnz	r0, 20003dc2 <z_reschedule_irqlock+0xe>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
20003db8:	f3ef 8205 	mrs	r2, IPSR
20003dbc:	b90a      	cbnz	r2, 20003dc2 <z_reschedule_irqlock+0xe>
20003dbe:	f7fd b987 	b.w	200010d0 <arch_swap>
20003dc2:	f383 8811 	msr	BASEPRI, r3
20003dc6:	f3bf 8f6f 	isb	sy
}
20003dca:	4770      	bx	lr

20003dcc <z_reschedule_unlocked>:
	__asm__ volatile(
20003dcc:	f04f 0320 	mov.w	r3, #32
20003dd0:	f3ef 8011 	mrs	r0, BASEPRI
20003dd4:	f383 8811 	msr	BASEPRI, r3
20003dd8:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
20003ddc:	f7ff bfea 	b.w	20003db4 <z_reschedule_irqlock>

20003de0 <unpend_thread_no_timeout>:
{
20003de0:	4601      	mov	r1, r0
20003de2:	b508      	push	{r3, lr}
	_priq_wait_remove(&pended_on(thread)->waitq, thread);
20003de4:	6880      	ldr	r0, [r0, #8]
20003de6:	f7fe fd03 	bl	200027f0 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
20003dea:	7b4b      	ldrb	r3, [r1, #13]
20003dec:	f023 0302 	bic.w	r3, r3, #2
20003df0:	734b      	strb	r3, [r1, #13]
	thread->base.pended_on = NULL;
20003df2:	2300      	movs	r3, #0
20003df4:	608b      	str	r3, [r1, #8]
}
20003df6:	bd08      	pop	{r3, pc}

20003df8 <z_priq_dumb_best>:
{
20003df8:	4603      	mov	r3, r0
	return list->head == list;
20003dfa:	6800      	ldr	r0, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
20003dfc:	4283      	cmp	r3, r0
20003dfe:	d003      	beq.n	20003e08 <z_priq_dumb_best+0x10>
	if (n != NULL) {
20003e00:	2800      	cmp	r0, #0
20003e02:	bf38      	it	cc
20003e04:	2000      	movcc	r0, #0
20003e06:	4770      	bx	lr
	struct k_thread *thread = NULL;
20003e08:	2000      	movs	r0, #0
}
20003e0a:	4770      	bx	lr

20003e0c <z_ready_thread>:
{
20003e0c:	b510      	push	{r4, lr}
20003e0e:	f04f 0320 	mov.w	r3, #32
20003e12:	f3ef 8411 	mrs	r4, BASEPRI
20003e16:	f383 8811 	msr	BASEPRI, r3
20003e1a:	f3bf 8f6f 	isb	sy
		ready_thread(thread);
20003e1e:	f7fe fd3d 	bl	2000289c <ready_thread>
	__asm__ volatile(
20003e22:	f384 8811 	msr	BASEPRI, r4
20003e26:	f3bf 8f6f 	isb	sy
}
20003e2a:	bd10      	pop	{r4, pc}

20003e2c <z_thread_timeout>:
{
20003e2c:	b570      	push	{r4, r5, r6, lr}
20003e2e:	4604      	mov	r4, r0
	__asm__ volatile(
20003e30:	f04f 0320 	mov.w	r3, #32
20003e34:	f3ef 8611 	mrs	r6, BASEPRI
20003e38:	f383 8811 	msr	BASEPRI, r3
20003e3c:	f3bf 8f6f 	isb	sy
		if (thread->base.pended_on != NULL) {
20003e40:	f850 3c10 	ldr.w	r3, [r0, #-16]
		struct k_thread *thread = CONTAINER_OF(timeout,
20003e44:	f1a0 0518 	sub.w	r5, r0, #24
		if (thread->base.pended_on != NULL) {
20003e48:	b113      	cbz	r3, 20003e50 <z_thread_timeout+0x24>
			unpend_thread_no_timeout(thread);
20003e4a:	4628      	mov	r0, r5
20003e4c:	f7ff ffc8 	bl	20003de0 <unpend_thread_no_timeout>
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
20003e50:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
		ready_thread(thread);
20003e54:	4628      	mov	r0, r5
20003e56:	f023 0314 	bic.w	r3, r3, #20
20003e5a:	f804 3c0b 	strb.w	r3, [r4, #-11]
20003e5e:	f7fe fd1d 	bl	2000289c <ready_thread>
	__asm__ volatile(
20003e62:	f386 8811 	msr	BASEPRI, r6
20003e66:	f3bf 8f6f 	isb	sy
}
20003e6a:	bd70      	pop	{r4, r5, r6, pc}

20003e6c <add_to_waitq_locked>:
{
20003e6c:	b538      	push	{r3, r4, r5, lr}
20003e6e:	4604      	mov	r4, r0
20003e70:	460d      	mov	r5, r1
	unready_thread(thread);
20003e72:	f7fe fe71 	bl	20002b58 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
20003e76:	7b63      	ldrb	r3, [r4, #13]
20003e78:	f043 0302 	orr.w	r3, r3, #2
20003e7c:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
20003e7e:	b1c5      	cbz	r5, 20003eb2 <add_to_waitq_locked+0x46>
	return list->head == list;
20003e80:	682b      	ldr	r3, [r5, #0]
		thread->base.pended_on = wait_q;
20003e82:	60a5      	str	r5, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
20003e84:	429d      	cmp	r5, r3
20003e86:	bf08      	it	eq
20003e88:	2300      	moveq	r3, #0
20003e8a:	2b00      	cmp	r3, #0
20003e8c:	bf38      	it	cc
20003e8e:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
20003e90:	b183      	cbz	r3, 20003eb4 <add_to_waitq_locked+0x48>
	if (thread_1->base.prio < thread_2->base.prio) {
20003e92:	f994 100e 	ldrsb.w	r1, [r4, #14]
20003e96:	f993 200e 	ldrsb.w	r2, [r3, #14]
20003e9a:	4291      	cmp	r1, r2
20003e9c:	db04      	blt.n	20003ea8 <add_to_waitq_locked+0x3c>
	return (node == list->tail) ? NULL : node->next;
20003e9e:	686a      	ldr	r2, [r5, #4]
20003ea0:	429a      	cmp	r2, r3
20003ea2:	d007      	beq.n	20003eb4 <add_to_waitq_locked+0x48>
20003ea4:	681b      	ldr	r3, [r3, #0]
20003ea6:	e7f3      	b.n	20003e90 <add_to_waitq_locked+0x24>
	node->prev = successor->prev;
20003ea8:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
20003eaa:	e9c4 3200 	strd	r3, r2, [r4]
	successor->prev->next = node;
20003eae:	6014      	str	r4, [r2, #0]
	successor->prev = node;
20003eb0:	605c      	str	r4, [r3, #4]
}
20003eb2:	bd38      	pop	{r3, r4, r5, pc}
	node->prev = list->tail;
20003eb4:	686b      	ldr	r3, [r5, #4]
	node->next = list;
20003eb6:	6025      	str	r5, [r4, #0]
	node->prev = list->tail;
20003eb8:	6063      	str	r3, [r4, #4]
	list->tail->next = node;
20003eba:	686b      	ldr	r3, [r5, #4]
20003ebc:	601c      	str	r4, [r3, #0]
	list->tail = node;
20003ebe:	606c      	str	r4, [r5, #4]
20003ec0:	e7f7      	b.n	20003eb2 <add_to_waitq_locked+0x46>

20003ec2 <z_unpend_first_thread>:
{
20003ec2:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
20003ec4:	f04f 0320 	mov.w	r3, #32
20003ec8:	f3ef 8211 	mrs	r2, BASEPRI
20003ecc:	f383 8811 	msr	BASEPRI, r3
20003ed0:	f3bf 8f6f 	isb	sy
		ret = _priq_wait_best(&wait_q->waitq);
20003ed4:	f7ff ff90 	bl	20003df8 <z_priq_dumb_best>
20003ed8:	4604      	mov	r4, r0
	__asm__ volatile(
20003eda:	f382 8811 	msr	BASEPRI, r2
20003ede:	f3bf 8f6f 	isb	sy

static inline struct k_thread *z_unpend1_no_timeout(_wait_q_t *wait_q)
{
	struct k_thread *thread = z_find_first_thread_to_unpend(wait_q, NULL);

	if (thread != NULL) {
20003ee2:	b188      	cbz	r0, 20003f08 <z_unpend_first_thread+0x46>
	__asm__ volatile(
20003ee4:	f04f 0320 	mov.w	r3, #32
20003ee8:	f3ef 8511 	mrs	r5, BASEPRI
20003eec:	f383 8811 	msr	BASEPRI, r3
20003ef0:	f3bf 8f6f 	isb	sy
		unpend_thread_no_timeout(thread);
20003ef4:	f7ff ff74 	bl	20003de0 <unpend_thread_no_timeout>
	__asm__ volatile(
20003ef8:	f385 8811 	msr	BASEPRI, r5
20003efc:	f3bf 8f6f 	isb	sy
	return z_abort_timeout(&thread->base.timeout);
20003f00:	f104 0018 	add.w	r0, r4, #24
20003f04:	f000 f80a 	bl	20003f1c <z_abort_timeout>
}
20003f08:	4620      	mov	r0, r4
20003f0a:	bd38      	pop	{r3, r4, r5, pc}

20003f0c <k_is_in_isr>:
20003f0c:	f3ef 8005 	mrs	r0, IPSR
}
20003f10:	3800      	subs	r0, #0
20003f12:	bf18      	it	ne
20003f14:	2001      	movne	r0, #1
20003f16:	4770      	bx	lr

20003f18 <z_impl_k_busy_wait>:
	arch_busy_wait(usec_to_wait);
20003f18:	f7fc bd68 	b.w	200009ec <arch_busy_wait>

20003f1c <z_abort_timeout>:
{
20003f1c:	b510      	push	{r4, lr}
	__asm__ volatile(
20003f1e:	f04f 0220 	mov.w	r2, #32
20003f22:	f3ef 8411 	mrs	r4, BASEPRI
20003f26:	f382 8811 	msr	BASEPRI, r2
20003f2a:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
20003f2e:	6803      	ldr	r3, [r0, #0]
20003f30:	b13b      	cbz	r3, 20003f42 <z_abort_timeout+0x26>
			remove_timeout(to);
20003f32:	f7ff f839 	bl	20002fa8 <remove_timeout>
			ret = 0;
20003f36:	2000      	movs	r0, #0
	__asm__ volatile(
20003f38:	f384 8811 	msr	BASEPRI, r4
20003f3c:	f3bf 8f6f 	isb	sy
}
20003f40:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
20003f42:	f06f 0015 	mvn.w	r0, #21
20003f46:	e7f7      	b.n	20003f38 <z_abort_timeout+0x1c>

20003f48 <z_get_next_timeout_expiry>:
{
20003f48:	b510      	push	{r4, lr}
	__asm__ volatile(
20003f4a:	f04f 0320 	mov.w	r3, #32
20003f4e:	f3ef 8411 	mrs	r4, BASEPRI
20003f52:	f383 8811 	msr	BASEPRI, r3
20003f56:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
20003f5a:	f7ff f83f 	bl	20002fdc <next_timeout>
	__asm__ volatile(
20003f5e:	f384 8811 	msr	BASEPRI, r4
20003f62:	f3bf 8f6f 	isb	sy
}
20003f66:	bd10      	pop	{r4, pc}

20003f68 <z_set_timeout_expiry>:
{
20003f68:	b570      	push	{r4, r5, r6, lr}
20003f6a:	4604      	mov	r4, r0
20003f6c:	460d      	mov	r5, r1
	__asm__ volatile(
20003f6e:	f04f 0320 	mov.w	r3, #32
20003f72:	f3ef 8611 	mrs	r6, BASEPRI
20003f76:	f383 8811 	msr	BASEPRI, r3
20003f7a:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
20003f7e:	f7ff f82d 	bl	20002fdc <next_timeout>
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
20003f82:	2801      	cmp	r0, #1
20003f84:	dd05      	ble.n	20003f92 <z_set_timeout_expiry+0x2a>
20003f86:	42a0      	cmp	r0, r4
20003f88:	dd03      	ble.n	20003f92 <z_set_timeout_expiry+0x2a>
			z_clock_set_timeout(ticks, is_idle);
20003f8a:	4629      	mov	r1, r5
20003f8c:	4620      	mov	r0, r4
20003f8e:	f7fc ff85 	bl	20000e9c <z_clock_set_timeout>
	__asm__ volatile(
20003f92:	f386 8811 	msr	BASEPRI, r6
20003f96:	f3bf 8f6f 	isb	sy
}
20003f9a:	bd70      	pop	{r4, r5, r6, pc}

20003f9c <z_tick_get_32>:

uint32_t z_tick_get_32(void)
{
20003f9c:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)z_tick_get();
20003f9e:	f7ff f937 	bl	20003210 <z_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
20003fa2:	bd08      	pop	{r3, pc}

20003fa4 <k_heap_init>:
{
20003fa4:	b410      	push	{r4}
	sys_dlist_init(&w->waitq);
20003fa6:	f100 040c 	add.w	r4, r0, #12
	list->tail = (sys_dnode_t *)list;
20003faa:	e9c0 4403 	strd	r4, r4, [r0, #12]
}
20003fae:	bc10      	pop	{r4}
	sys_heap_init(&h->heap, mem, bytes);
20003fb0:	f7ff bbfa 	b.w	200037a8 <sys_heap_init>

20003fb4 <_OffsetAbsSyms>:
#include "offsets_aarch64.c"
#else
#include "offsets_aarch32.c"
#endif

GEN_ABS_SYM_END
20003fb4:	4770      	bx	lr
