
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_table>:

nrfx_err_t nrfx_spis_init(nrfx_spis_t const *        p_instance,
                          nrfx_spis_config_t const * p_config,
                          nrfx_spis_event_handler_t  event_handler,
                          void *                     p_context)
{
   0:	10 1e 00 20 e9 3d 00 00 83 95 00 00 bd 3d 00 00     ... .=.......=..
    NRFX_ASSERT(p_config);
  10:	bd 3d 00 00 bd 3d 00 00 bd 3d 00 00 bd 3d 00 00     .=...=...=...=..
	...
    NRFX_ASSERT(event_handler);
  2c:	91 36 00 00 bd 3d 00 00 00 00 00 00 39 36 00 00     .6...=......96..
    spis_cb_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    nrfx_err_t err_code;

    NRF_SPIS_Type * p_spis = p_instance->p_reg;

    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
  3c:	bd 3d 00 00                                         .=..

00000040 <_irq_vector_table>:
  40:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
#endif // NRFX_CHECK(NRFX_PRS_ENABLED)

    p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg;
  50:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
        nrf_gpio_cfg(p_config->sck_pin,
  60:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
        if (p_config->mosi_pin != NRFX_SPIS_PIN_NOT_USED)
  70:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
        if (p_config->miso_pin != NRFX_SPIS_PIN_NOT_USED)
  80:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
        nrf_gpio_cfg(p_config->csn_pin,
  90:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
        uint32_t mosi_pin = (p_config->mosi_pin != NRFX_SPIS_PIN_NOT_USED)
  a0:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
                            : NRF_SPIS_PIN_NOT_CONNECTED;
  b0:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
    p_reg->PSELCSN  = csn_pin;
#else
    p_reg->PSEL.SCK  = sck_pin;
    p_reg->PSEL.MOSI = mosi_pin;
    p_reg->PSEL.MISO = miso_pin;
    p_reg->PSEL.CSN  = csn_pin;
  c0:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
{
#if defined (NRF51)
    p_reg->TXDPTR = (uint32_t)p_buffer;
    p_reg->MAXTX  = length;
#else
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
  d0:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
                                          nrf_spis_bit_order_t spi_bit_order)
{
    uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ?
        SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst);

    switch (spi_mode)
  e0:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
    case NRF_SPIS_MODE_3:
        config |= (SPIS_CONFIG_CPOL_ActiveLow  << SPIS_CONFIG_CPOL_Pos) |
                  (SPIS_CONFIG_CPHA_Trailing   << SPIS_CONFIG_CPHA_Pos);
        break;
    }
    p_reg->CONFIG = config;
  f0:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..

    // Enable END_ACQUIRE shortcut.
    nrf_spis_shorts_enable(p_spis, NRF_SPIS_SHORT_END_ACQUIRE);

    p_cb->spi_state = SPIS_STATE_INIT;
    p_cb->handler   = event_handler;
 100:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
 110:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
    p_reg->SHORTS |= mask;
 120:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
    p_reg->INTENSET = mask;
 130:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
    p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
 140:	11 37 00 00 11 37 00 00 11 37 00 00 11 37 00 00     .7...7...7...7..
        break;
 150:	11 37 00 00                                         .7..

Disassembly of section text:

00000154 <__aeabi_uldivmod>:
        config |= (SPIS_CONFIG_CPOL_ActiveLow  << SPIS_CONFIG_CPOL_Pos) |
     154:	b953      	cbnz	r3, 16c <__aeabi_uldivmod+0x18>
        break;
     156:	b94a      	cbnz	r2, 16c <__aeabi_uldivmod+0x18>
        return err_code;
     158:	2900      	cmp	r1, #0
     15a:	bf08      	it	eq
        return err_code;
     15c:	2800      	cmpeq	r0, #0
     15e:	bf1c      	itt	ne
     160:	f04f 31ff 	movne.w	r1, #4294967295
     164:	f04f 30ff 	movne.w	r0, #4294967295
     168:	f000 b80c 	b.w	184 <__aeabi_idiv0>
     16c:	f1ad 0c08 	sub.w	ip, sp, #8
     170:	e96d ce04 	strd	ip, lr, [sp, #-16]!
     174:	f000 f808 	bl	188 <__udivmoddi4>
     178:	f8dd e004 	ldr.w	lr, [sp, #4]
     17c:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     180:	b004      	add	sp, #16
     182:	4770      	bx	lr

00000184 <__aeabi_idiv0>:
     184:	4770      	bx	lr
     186:	bf00      	nop

00000188 <__udivmoddi4>:
     188:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     18c:	4686      	mov	lr, r0
     18e:	468c      	mov	ip, r1
     190:	4608      	mov	r0, r1
     192:	9e08      	ldr	r6, [sp, #32]
     194:	4615      	mov	r5, r2
     196:	4674      	mov	r4, lr
     198:	4619      	mov	r1, r3
     19a:	2b00      	cmp	r3, #0
     19c:	f040 80c1 	bne.w	322 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xa2>
     1a0:	4285      	cmp	r5, r0
     1a2:	fab2 f282 	clz	r2, r2
     1a6:	d945      	bls.n	234 <CONFIG_SRAM_SIZE+0x74>
     1a8:	b14a      	cbz	r2, 1be <__udivmoddi4+0x36>
     1aa:	f1c2 0320 	rsb	r3, r2, #32
     1ae:	fa00 fc02 	lsl.w	ip, r0, r2
     1b2:	4095      	lsls	r5, r2
     1b4:	4094      	lsls	r4, r2
     1b6:	fa2e f303 	lsr.w	r3, lr, r3
     1ba:	ea43 0c0c 	orr.w	ip, r3, ip
     1be:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     1c2:	b2a8      	uxth	r0, r5
     1c4:	0c23      	lsrs	r3, r4, #16
     1c6:	fbbc f8fe 	udiv	r8, ip, lr
     1ca:	fb0e cc18 	mls	ip, lr, r8, ip
     1ce:	fb08 f900 	mul.w	r9, r8, r0
     1d2:	ea43 430c 	orr.w	r3, r3, ip, lsl #16
     1d6:	4599      	cmp	r9, r3
     1d8:	d928      	bls.n	22c <CONFIG_SRAM_SIZE+0x6c>
     1da:	18eb      	adds	r3, r5, r3
     1dc:	f108 37ff 	add.w	r7, r8, #4294967295
     1e0:	d204      	bcs.n	1ec <CONFIG_SRAM_SIZE+0x2c>
     1e2:	4599      	cmp	r9, r3
     1e4:	d902      	bls.n	1ec <CONFIG_SRAM_SIZE+0x2c>
     1e6:	f1a8 0702 	sub.w	r7, r8, #2
     1ea:	442b      	add	r3, r5
     1ec:	eba3 0309 	sub.w	r3, r3, r9
     1f0:	b2a4      	uxth	r4, r4
     1f2:	fbb3 fcfe 	udiv	ip, r3, lr
     1f6:	fb0e 331c 	mls	r3, lr, ip, r3
     1fa:	fb0c f000 	mul.w	r0, ip, r0
     1fe:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     202:	42a0      	cmp	r0, r4
     204:	d914      	bls.n	230 <CONFIG_SRAM_SIZE+0x70>
     206:	192c      	adds	r4, r5, r4
     208:	f10c 33ff 	add.w	r3, ip, #4294967295
     20c:	d204      	bcs.n	218 <CONFIG_SRAM_SIZE+0x58>
     20e:	42a0      	cmp	r0, r4
     210:	d902      	bls.n	218 <CONFIG_SRAM_SIZE+0x58>
     212:	f1ac 0302 	sub.w	r3, ip, #2
     216:	442c      	add	r4, r5
     218:	1a24      	subs	r4, r4, r0
     21a:	ea43 4007 	orr.w	r0, r3, r7, lsl #16
     21e:	b11e      	cbz	r6, 228 <CONFIG_SRAM_SIZE+0x68>
     220:	40d4      	lsrs	r4, r2
     222:	2300      	movs	r3, #0
     224:	6034      	str	r4, [r6, #0]
     226:	6073      	str	r3, [r6, #4]
     228:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     22c:	4647      	mov	r7, r8
     22e:	e7dd      	b.n	1ec <CONFIG_SRAM_SIZE+0x2c>
     230:	4663      	mov	r3, ip
     232:	e7f1      	b.n	218 <CONFIG_SRAM_SIZE+0x58>
     234:	bb92      	cbnz	r2, 29c <CONFIG_PM_PARTITION_SIZE_PROVISION+0x1c>
     236:	1b43      	subs	r3, r0, r5
     238:	2101      	movs	r1, #1
     23a:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     23e:	b2af      	uxth	r7, r5
     240:	0c20      	lsrs	r0, r4, #16
     242:	fbb3 fcfe 	udiv	ip, r3, lr
     246:	fb0e 331c 	mls	r3, lr, ip, r3
     24a:	fb0c f807 	mul.w	r8, ip, r7
     24e:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
     252:	4598      	cmp	r8, r3
     254:	d961      	bls.n	31a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x9a>
     256:	18eb      	adds	r3, r5, r3
     258:	f10c 30ff 	add.w	r0, ip, #4294967295
     25c:	d204      	bcs.n	268 <CONFIG_SRAM_SIZE+0xa8>
     25e:	4598      	cmp	r8, r3
     260:	d902      	bls.n	268 <CONFIG_SRAM_SIZE+0xa8>
     262:	f1ac 0002 	sub.w	r0, ip, #2
     266:	442b      	add	r3, r5
     268:	eba3 0308 	sub.w	r3, r3, r8
     26c:	b2a4      	uxth	r4, r4
     26e:	fbb3 fcfe 	udiv	ip, r3, lr
     272:	fb0e 331c 	mls	r3, lr, ip, r3
     276:	fb0c f707 	mul.w	r7, ip, r7
     27a:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     27e:	42a7      	cmp	r7, r4
     280:	d94d      	bls.n	31e <CONFIG_PM_PARTITION_SIZE_PROVISION+0x9e>
     282:	192c      	adds	r4, r5, r4
     284:	f10c 33ff 	add.w	r3, ip, #4294967295
     288:	d204      	bcs.n	294 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x14>
     28a:	42a7      	cmp	r7, r4
     28c:	d902      	bls.n	294 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x14>
     28e:	f1ac 0302 	sub.w	r3, ip, #2
     292:	442c      	add	r4, r5
     294:	1be4      	subs	r4, r4, r7
     296:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
     29a:	e7c0      	b.n	21e <CONFIG_SRAM_SIZE+0x5e>
     29c:	f1c2 0320 	rsb	r3, r2, #32
     2a0:	4095      	lsls	r5, r2
     2a2:	4094      	lsls	r4, r2
     2a4:	fa20 f103 	lsr.w	r1, r0, r3
     2a8:	fa2e f303 	lsr.w	r3, lr, r3
     2ac:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     2b0:	4090      	lsls	r0, r2
     2b2:	b2af      	uxth	r7, r5
     2b4:	4303      	orrs	r3, r0
     2b6:	fbb1 fcfe 	udiv	ip, r1, lr
     2ba:	fb0e 101c 	mls	r0, lr, ip, r1
     2be:	0c19      	lsrs	r1, r3, #16
     2c0:	fb0c f807 	mul.w	r8, ip, r7
     2c4:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
     2c8:	4588      	cmp	r8, r1
     2ca:	d922      	bls.n	312 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x92>
     2cc:	1869      	adds	r1, r5, r1
     2ce:	f10c 30ff 	add.w	r0, ip, #4294967295
     2d2:	d204      	bcs.n	2de <CONFIG_PM_PARTITION_SIZE_PROVISION+0x5e>
     2d4:	4588      	cmp	r8, r1
     2d6:	d902      	bls.n	2de <CONFIG_PM_PARTITION_SIZE_PROVISION+0x5e>
     2d8:	f1ac 0002 	sub.w	r0, ip, #2
     2dc:	4429      	add	r1, r5
     2de:	eba1 0108 	sub.w	r1, r1, r8
     2e2:	b29b      	uxth	r3, r3
     2e4:	fbb1 fcfe 	udiv	ip, r1, lr
     2e8:	fb0e 111c 	mls	r1, lr, ip, r1
     2ec:	fb0c f707 	mul.w	r7, ip, r7
     2f0:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
     2f4:	429f      	cmp	r7, r3
     2f6:	d90e      	bls.n	316 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x96>
     2f8:	18eb      	adds	r3, r5, r3
     2fa:	f10c 31ff 	add.w	r1, ip, #4294967295
     2fe:	d204      	bcs.n	30a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x8a>
     300:	429f      	cmp	r7, r3
     302:	d902      	bls.n	30a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x8a>
     304:	f1ac 0102 	sub.w	r1, ip, #2
     308:	442b      	add	r3, r5
     30a:	1bdb      	subs	r3, r3, r7
     30c:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
     310:	e793      	b.n	23a <CONFIG_SRAM_SIZE+0x7a>
     312:	4660      	mov	r0, ip
     314:	e7e3      	b.n	2de <CONFIG_PM_PARTITION_SIZE_PROVISION+0x5e>
     316:	4661      	mov	r1, ip
     318:	e7f7      	b.n	30a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x8a>
     31a:	4660      	mov	r0, ip
     31c:	e7a4      	b.n	268 <CONFIG_SRAM_SIZE+0xa8>
     31e:	4663      	mov	r3, ip
     320:	e7b8      	b.n	294 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x14>
     322:	4283      	cmp	r3, r0
     324:	d906      	bls.n	334 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xb4>
     326:	b916      	cbnz	r6, 32e <CONFIG_PM_PARTITION_SIZE_PROVISION+0xae>
     328:	2100      	movs	r1, #0
     32a:	4608      	mov	r0, r1
     32c:	e77c      	b.n	228 <CONFIG_SRAM_SIZE+0x68>
     32e:	e9c6 e000 	strd	lr, r0, [r6]
     332:	e7f9      	b.n	328 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xa8>
     334:	fab3 f783 	clz	r7, r3
     338:	b98f      	cbnz	r7, 35e <CONFIG_PM_PARTITION_SIZE_PROVISION+0xde>
     33a:	4283      	cmp	r3, r0
     33c:	d301      	bcc.n	342 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xc2>
     33e:	4572      	cmp	r2, lr
     340:	d808      	bhi.n	354 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd4>
     342:	ebbe 0402 	subs.w	r4, lr, r2
     346:	eb60 0303 	sbc.w	r3, r0, r3
     34a:	2001      	movs	r0, #1
     34c:	469c      	mov	ip, r3
     34e:	b91e      	cbnz	r6, 358 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd8>
     350:	2100      	movs	r1, #0
     352:	e769      	b.n	228 <CONFIG_SRAM_SIZE+0x68>
     354:	4638      	mov	r0, r7
     356:	e7fa      	b.n	34e <CONFIG_PM_PARTITION_SIZE_PROVISION+0xce>
     358:	e9c6 4c00 	strd	r4, ip, [r6]
     35c:	e7f8      	b.n	350 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd0>
     35e:	f1c7 0c20 	rsb	ip, r7, #32
     362:	40bb      	lsls	r3, r7
     364:	fa0e f507 	lsl.w	r5, lr, r7
     368:	fa22 f40c 	lsr.w	r4, r2, ip
     36c:	fa2e f10c 	lsr.w	r1, lr, ip
     370:	40ba      	lsls	r2, r7
     372:	431c      	orrs	r4, r3
     374:	fa20 f30c 	lsr.w	r3, r0, ip
     378:	40b8      	lsls	r0, r7
     37a:	ea4f 4914 	mov.w	r9, r4, lsr #16
     37e:	4301      	orrs	r1, r0
     380:	fa1f fe84 	uxth.w	lr, r4
     384:	fbb3 f8f9 	udiv	r8, r3, r9
     388:	fb09 3018 	mls	r0, r9, r8, r3
     38c:	0c0b      	lsrs	r3, r1, #16
     38e:	fb08 fa0e 	mul.w	sl, r8, lr
     392:	ea43 4300 	orr.w	r3, r3, r0, lsl #16
     396:	459a      	cmp	sl, r3
     398:	d940      	bls.n	41c <CONFIG_FLASH_SIZE+0x1c>
     39a:	18e3      	adds	r3, r4, r3
     39c:	f108 30ff 	add.w	r0, r8, #4294967295
     3a0:	d204      	bcs.n	3ac <CONFIG_PM_PARTITION_SIZE_PROVISION+0x12c>
     3a2:	459a      	cmp	sl, r3
     3a4:	d902      	bls.n	3ac <CONFIG_PM_PARTITION_SIZE_PROVISION+0x12c>
     3a6:	f1a8 0002 	sub.w	r0, r8, #2
     3aa:	4423      	add	r3, r4
     3ac:	eba3 030a 	sub.w	r3, r3, sl
     3b0:	b289      	uxth	r1, r1
     3b2:	fbb3 f8f9 	udiv	r8, r3, r9
     3b6:	fb09 3318 	mls	r3, r9, r8, r3
     3ba:	fb08 fe0e 	mul.w	lr, r8, lr
     3be:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
     3c2:	458e      	cmp	lr, r1
     3c4:	d92c      	bls.n	420 <CONFIG_FLASH_SIZE+0x20>
     3c6:	1861      	adds	r1, r4, r1
     3c8:	f108 33ff 	add.w	r3, r8, #4294967295
     3cc:	d204      	bcs.n	3d8 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x158>
     3ce:	458e      	cmp	lr, r1
     3d0:	d902      	bls.n	3d8 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x158>
     3d2:	f1a8 0302 	sub.w	r3, r8, #2
     3d6:	4421      	add	r1, r4
     3d8:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
     3dc:	eba1 010e 	sub.w	r1, r1, lr
     3e0:	fba0 9802 	umull	r9, r8, r0, r2
     3e4:	4541      	cmp	r1, r8
     3e6:	46ce      	mov	lr, r9
     3e8:	4643      	mov	r3, r8
     3ea:	d302      	bcc.n	3f2 <CONFIG_LOG_FAILURE_REPORT_PERIOD+0xa>
     3ec:	d106      	bne.n	3fc <CONFIG_LOG_FAILURE_REPORT_PERIOD+0x14>
     3ee:	454d      	cmp	r5, r9
     3f0:	d204      	bcs.n	3fc <CONFIG_LOG_FAILURE_REPORT_PERIOD+0x14>
     3f2:	3801      	subs	r0, #1
     3f4:	ebb9 0e02 	subs.w	lr, r9, r2
     3f8:	eb68 0304 	sbc.w	r3, r8, r4
     3fc:	2e00      	cmp	r6, #0
     3fe:	d0a7      	beq.n	350 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd0>
     400:	ebb5 020e 	subs.w	r2, r5, lr
     404:	eb61 0103 	sbc.w	r1, r1, r3
     408:	fa01 fc0c 	lsl.w	ip, r1, ip
     40c:	fa22 f307 	lsr.w	r3, r2, r7
     410:	40f9      	lsrs	r1, r7
     412:	ea4c 0303 	orr.w	r3, ip, r3
     416:	e9c6 3100 	strd	r3, r1, [r6]
     41a:	e799      	b.n	350 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd0>
     41c:	4640      	mov	r0, r8
     41e:	e7c5      	b.n	3ac <CONFIG_PM_PARTITION_SIZE_PROVISION+0x12c>
     420:	4643      	mov	r3, r8
     422:	e7d9      	b.n	3d8 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x158>

00000424 <main>:
 * @brief Function for application main entry.
 *
 * @return Nothing.
 */
int main(void)
{
     424:	b510      	push	{r4, lr}
//                                    m_rx_buffer_slave, sizeof(m_rx_buffer_slave));
//     NRFX_ASSERT(status == NRFX_SUCCESS);

    while (1)
    {
        printk("test\n");
     426:	4c05      	ldr	r4, [pc, #20]	; (43c <main+0x18>)
     428:	4620      	mov	r0, r4
     42a:	f008 fe4e 	bl	90ca <printk>
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm0 = { .val = timeout };
		return (int32_t) arch_syscall_invoke2(parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SLEEP);
	}
#endif
	compiler_barrier();
	return z_impl_k_sleep(timeout);
     42e:	2100      	movs	r1, #0
     430:	f44f 4000 	mov.w	r0, #32768	; 0x8000
     434:	f007 ff50 	bl	82d8 <z_impl_k_sleep>
    while (1)
     438:	e7f6      	b.n	428 <main+0x4>
     43a:	bf00      	nop
     43c:	0000a2b4 	.word	0x0000a2b4

00000440 <cbvprintf_package>:
	return cb(str, strl, ctx);
}

int cbvprintf_package(void *packaged, size_t len, uint32_t flags,
		      const char *fmt, va_list ap)
{
     440:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     444:	b091      	sub	sp, #68	; 0x44
     446:	9300      	str	r3, [sp, #0]
	const char *s;
	bool parsing = false;
	/* Flag indicates that rw strings are stored as array with positions,
	 * instead of appending them to the package.
	 */
	bool rws_pos_en = !!(flags & CBPRINTF_PACKAGE_ADD_RW_STR_POS);
     448:	f002 0304 	and.w	r3, r2, #4
     44c:	9301      	str	r3, [sp, #4]
	/* Get number of first read only strings present in the string.
	 * There is always at least 1 (fmt) but flags can indicate more, e.g
	 * fixed prefix appended to all strings.
	 */
	int fros_cnt = 1 + Z_CBPRINTF_PACKAGE_FIRST_RO_STR_CNT_GET(flags);
     44e:	f3c2 03c2 	ubfx	r3, r2, #3, #3
     452:	3301      	adds	r3, #1
     454:	9304      	str	r3, [sp, #16]
	bool is_str_arg = false;
	union cbprintf_package_hdr *pkg_hdr = packaged;

	/* Buffer must be aligned at least to size of a pointer. */
	if ((uintptr_t)packaged % sizeof(void *)) {
     456:	0783      	lsls	r3, r0, #30
{
     458:	4605      	mov	r5, r0
     45a:	460e      	mov	r6, r1
     45c:	f8dd 9068 	ldr.w	r9, [sp, #104]	; 0x68
     460:	9202      	str	r2, [sp, #8]
	if ((uintptr_t)packaged % sizeof(void *)) {
     462:	f040 81fe 	bne.w	862 <CONFIG_ISR_STACK_SIZE+0x62>
	 * which is guaranteed to be at least 4 bytes, we just reserve
	 * multiple of pointer size for the above to preserve alignment.
	 *
	 * Refer to union cbprintf_package_hdr for more details.
	 */
	buf += sizeof(*pkg_hdr);
     466:	1d04      	adds	r4, r0, #4
	 * When buf0 is NULL we don't store anything.
	 * Instead we count the needed space to store the data.
	 * In this case, incoming len argument indicates the anticipated
	 * buffer "misalignment" offset.
	 */
	if (buf0 == NULL) {
     468:	b130      	cbz	r0, 478 <cbvprintf_package+0x38>

	/*
	 * Otherwise we must ensure we can store at least
	 * the pointer to the format string itself.
	 */
	if (buf0 != NULL && BUF_OFFSET + sizeof(char *) > len) {
     46a:	2907      	cmp	r1, #7
     46c:	d809      	bhi.n	482 <cbvprintf_package+0x42>
		return -ENOSPC;
     46e:	f06f 001b 	mvn.w	r0, #27
	return BUF_OFFSET;

#undef BUF_OFFSET
#undef STR_POS_RO_FLAG
#undef STR_POS_MASK
}
     472:	b011      	add	sp, #68	; 0x44
     474:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		buf += len % CBPRINTF_PACKAGE_ALIGNMENT;
     478:	f001 0607 	and.w	r6, r1, #7
     47c:	1d34      	adds	r4, r6, #4
		len = CBPRINTF_PACKAGE_ALIGNMENT - (len % CBPRINTF_PACKAGE_ALIGNMENT);
     47e:	f1c6 0608 	rsb	r6, r6, #8
	unsigned int s_ro_cnt = 0; /* number of ro strings */
     482:	f04f 0800 	mov.w	r8, #0
	align = VA_STACK_ALIGN(char *);
     486:	f04f 0b04 	mov.w	fp, #4
	s = fmt--;
     48a:	9b00      	ldr	r3, [sp, #0]
	unsigned int s_idx = 0;    /* index into str_ptr_pos[] */
     48c:	4647      	mov	r7, r8
	s = fmt--;
     48e:	1e59      	subs	r1, r3, #1
	int arg_idx	      = -1; /* Argument index. Preincremented thus starting from -1.*/
     490:	f04f 32ff 	mov.w	r2, #4294967295
	bool parsing = false;
     494:	4643      	mov	r3, r8
	size = sizeof(char *);
     496:	46da      	mov	sl, fp
	unsigned int s_rw_cnt = 0; /* number of rw strings */
     498:	f8cd 800c 	str.w	r8, [sp, #12]
			if (buf0 != NULL) {
     49c:	b10d      	cbz	r5, 4a2 <cbvprintf_package+0x62>
				*(const char **)buf = s;
     49e:	9800      	ldr	r0, [sp, #0]
     4a0:	6020      	str	r0, [r4, #0]
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     4a2:	9804      	ldr	r0, [sp, #16]
     4a4:	2800      	cmp	r0, #0
     4a6:	f300 80e1 	bgt.w	66c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x184>
#else
	#define RO_START 0
	#define RO_END 0
#endif

	return (((const char *)addr >= (const char *)RO_START) &&
     4aa:	489c      	ldr	r0, [pc, #624]	; (71c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x234>)
     4ac:	f8dd c000 	ldr.w	ip, [sp]
     4b0:	4584      	cmp	ip, r0
     4b2:	d303      	bcc.n	4bc <cbvprintf_package+0x7c>
     4b4:	489a      	ldr	r0, [pc, #616]	; (720 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x238>)
     4b6:	4584      	cmp	ip, r0
     4b8:	f0c0 80d8 	bcc.w	66c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x184>
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
     4bc:	f8dd c008 	ldr.w	ip, [sp, #8]
				uint32_t s_ptr_idx = BUF_OFFSET / sizeof(int);
     4c0:	eba4 0e05 	sub.w	lr, r4, r5
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
     4c4:	f01c 0f02 	tst.w	ip, #2
				uint32_t s_ptr_idx = BUF_OFFSET / sizeof(int);
     4c8:	ea4f 009e 	mov.w	r0, lr, lsr #2
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
     4cc:	f000 80e9 	beq.w	6a2 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x1ba>
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     4d0:	f04f 0c00 	mov.w	ip, #0
     4d4:	e0d3      	b.n	67e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x196>
			switch (*fmt) {
     4d6:	287a      	cmp	r0, #122	; 0x7a
     4d8:	d864      	bhi.n	5a4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xbc>
     4da:	284b      	cmp	r0, #75	; 0x4b
     4dc:	d80f      	bhi.n	4fe <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x16>
     4de:	2847      	cmp	r0, #71	; 0x47
     4e0:	d860      	bhi.n	5a4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xbc>
     4e2:	2829      	cmp	r0, #41	; 0x29
     4e4:	d82f      	bhi.n	546 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x5e>
     4e6:	2825      	cmp	r0, #37	; 0x25
     4e8:	d05b      	beq.n	5a2 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xba>
     4ea:	d85b      	bhi.n	5a4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xbc>
     4ec:	2820      	cmp	r0, #32
     4ee:	d07f      	beq.n	5f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x108>
     4f0:	f1a0 0923 	sub.w	r9, r0, #35	; 0x23
     4f4:	f1d9 0300 	rsbs	r3, r9, #0
     4f8:	eb43 0309 	adc.w	r3, r3, r9
     4fc:	e078      	b.n	5f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x108>
     4fe:	f1a0 0e4c 	sub.w	lr, r0, #76	; 0x4c
     502:	f1be 0f2e 	cmp.w	lr, #46	; 0x2e
     506:	d84d      	bhi.n	5a4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xbc>
     508:	e8df f00e 	tbb	[pc, lr]
     50c:	4c4c4c72 	.word	0x4c4c4c72
     510:	4c4c4c4c 	.word	0x4c4c4c4c
     514:	4c4c4c4c 	.word	0x4c4c4c4c
     518:	4c4c4c4e 	.word	0x4c4c4c4e
     51c:	4c4c4c4c 	.word	0x4c4c4c4c
     520:	4e4c5c4c 	.word	0x4e4c5c4c
     524:	5c5c5c4e 	.word	0x5c5c5c4e
     528:	4c6f4e72 	.word	0x4c6f4e72
     52c:	4e184c72 	.word	0x4e184c72
     530:	814c4c18 	.word	0x814c4c18
     534:	4c4c4e7e 	.word	0x4c4c4e7e
     538:	4c4e      	.short	0x4c4e
     53a:	7e          	.byte	0x7e
     53b:	00          	.byte	0x00
     53c:	2000      	movs	r0, #0
     53e:	2300      	movs	r3, #0
				align = VA_STACK_ALIGN(void *);
     540:	f04f 0b04 	mov.w	fp, #4
     544:	e03c      	b.n	5c0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xd8>
			switch (*fmt) {
     546:	f1a0 0e2a 	sub.w	lr, r0, #42	; 0x2a
     54a:	2001      	movs	r0, #1
     54c:	fa5f fe8e 	uxtb.w	lr, lr
     550:	fa00 fe0e 	lsl.w	lr, r0, lr
     554:	f64f 70da 	movw	r0, #65498	; 0xffda
     558:	ea1e 0f00 	tst.w	lr, r0
     55c:	d148      	bne.n	5f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x108>
     55e:	f01e 5062 	ands.w	r0, lr, #947912704	; 0x38800000
     562:	d12f      	bne.n	5c4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xdc>
     564:	f01e 0301 	ands.w	r3, lr, #1
     568:	d042      	beq.n	5f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x108>
		buf = (void *) ROUND_UP(buf, align);
     56a:	3c01      	subs	r4, #1
     56c:	445c      	add	r4, fp
     56e:	f1cb 0e00 	rsb	lr, fp, #0
     572:	ea04 040e 	and.w	r4, r4, lr
		if (buf0 != NULL && BUF_OFFSET + size > len) {
     576:	2d00      	cmp	r5, #0
     578:	d05e      	beq.n	638 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x150>
     57a:	ebaa 0e05 	sub.w	lr, sl, r5
     57e:	44a6      	add	lr, r4
     580:	45b6      	cmp	lr, r6
     582:	f63f af74 	bhi.w	46e <cbvprintf_package+0x2e>
		if (is_str_arg) {
     586:	2800      	cmp	r0, #0
     588:	d168      	bne.n	65c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x174>
		} else if (size == sizeof(int)) {
     58a:	f1ba 0f04 	cmp.w	sl, #4
     58e:	d143      	bne.n	618 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x130>
			int v = va_arg(ap, int);
     590:	46e1      	mov	r9, ip
     592:	f859 0b04 	ldr.w	r0, [r9], #4
				*(int *)buf = v;
     596:	6020      	str	r0, [r4, #0]
			buf += sizeof(int);
     598:	46cc      	mov	ip, r9
     59a:	f04f 0a04 	mov.w	sl, #4
     59e:	3404      	adds	r4, #4
     5a0:	e026      	b.n	5f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x108>
				arg_idx--;
     5a2:	3a01      	subs	r2, #1
				parsing = false;
     5a4:	2300      	movs	r3, #0
				continue;
     5a6:	e023      	b.n	5f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x108>
				if (fmt[-1] == 'l') {
     5a8:	f811 3c01 	ldrb.w	r3, [r1, #-1]
     5ac:	2b6c      	cmp	r3, #108	; 0x6c
     5ae:	d130      	bne.n	612 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x12a>
					if (fmt[-2] == 'l') {
     5b0:	2000      	movs	r0, #0
     5b2:	f811 3c02 	ldrb.w	r3, [r1, #-2]
     5b6:	2b6c      	cmp	r3, #108	; 0x6c
				parsing = false;
     5b8:	4603      	mov	r3, r0
					if (fmt[-2] == 'l') {
     5ba:	d1c1      	bne.n	540 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x58>
						align = VA_STACK_ALIGN(long long);
     5bc:	f04f 0b08 	mov.w	fp, #8
				size = sizeof(void *);
     5c0:	46da      	mov	sl, fp
     5c2:	e7d2      	b.n	56a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x82>
					v.ld = va_arg(ap, long double);
     5c4:	f10c 0907 	add.w	r9, ip, #7
     5c8:	f029 0c07 	bic.w	ip, r9, #7
				buf = (void *) ROUND_UP(buf, align);
     5cc:	3407      	adds	r4, #7
     5ce:	f024 0407 	bic.w	r4, r4, #7
					v.ld = va_arg(ap, long double);
     5d2:	e8fc ab02 	ldrd	sl, fp, [ip], #8
				if (buf0 != NULL) {
     5d6:	b135      	cbz	r5, 5e6 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xfe>
					if (BUF_OFFSET + size > len) {
     5d8:	9805      	ldr	r0, [sp, #20]
     5da:	4420      	add	r0, r4
     5dc:	42b0      	cmp	r0, r6
     5de:	f63f af46 	bhi.w	46e <cbvprintf_package+0x2e>
						*(long double *)buf = v.ld;
     5e2:	e9c4 ab00 	strd	sl, fp, [r4]
				parsing = false;
     5e6:	2300      	movs	r3, #0
				buf += size;
     5e8:	3408      	adds	r4, #8
			switch (*fmt) {
     5ea:	f04f 0b08 	mov.w	fp, #8
     5ee:	46da      	mov	sl, fp
			if (*++fmt == '\0') {
     5f0:	f811 0f01 	ldrb.w	r0, [r1, #1]!
     5f4:	2800      	cmp	r0, #0
     5f6:	f000 80bc 	beq.w	772 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x28a>
			if (!parsing) {
     5fa:	2b00      	cmp	r3, #0
     5fc:	f47f af6b 	bne.w	4d6 <cbvprintf_package+0x96>
				if (*fmt == '%') {
     600:	2825      	cmp	r0, #37	; 0x25
     602:	d1f5      	bne.n	5f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x108>
					parsing = true;
     604:	2301      	movs	r3, #1
					arg_idx++;
     606:	3201      	adds	r2, #1
				align = VA_STACK_ALIGN(size_t);
     608:	f04f 0b04 	mov.w	fp, #4
     60c:	e7ef      	b.n	5ee <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x106>
			switch (*fmt) {
     60e:	4618      	mov	r0, r3
     610:	e795      	b.n	53e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x56>
     612:	2000      	movs	r0, #0
				parsing = false;
     614:	4603      	mov	r3, r0
     616:	e7a8      	b.n	56a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x82>
		} else if (size == sizeof(long long)) {
     618:	f1ba 0f08 	cmp.w	sl, #8
     61c:	f040 809b 	bne.w	756 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x26e>
			long long v = va_arg(ap, long long);
     620:	f10c 0907 	add.w	r9, ip, #7
     624:	f029 0c07 	bic.w	ip, r9, #7
     628:	e8fc 9a02 	ldrd	r9, sl, [ip], #8
					*(long long *)buf = v;
     62c:	e9c4 9a00 	strd	r9, sl, [r4]
			buf += sizeof(long long);
     630:	f04f 0a08 	mov.w	sl, #8
     634:	3408      	adds	r4, #8
     636:	e7db      	b.n	5f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x108>
		if (is_str_arg) {
     638:	b980      	cbnz	r0, 65c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x174>
		} else if (size == sizeof(int)) {
     63a:	f1ba 0f04 	cmp.w	sl, #4
     63e:	d102      	bne.n	646 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x15e>
			int v = va_arg(ap, int);
     640:	f10c 0904 	add.w	r9, ip, #4
			if (buf0 != NULL) {
     644:	e7a8      	b.n	598 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xb0>
		} else if (size == sizeof(long long)) {
     646:	f1ba 0f08 	cmp.w	sl, #8
     64a:	f040 8084 	bne.w	756 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x26e>
			long long v = va_arg(ap, long long);
     64e:	f10c 0907 	add.w	r9, ip, #7
     652:	f029 0907 	bic.w	r9, r9, #7
     656:	f109 0c08 	add.w	ip, r9, #8
			if (buf0 != NULL) {
     65a:	e7e9      	b.n	630 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x148>
			s = va_arg(ap, char *);
     65c:	46e1      	mov	r9, ip
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     65e:	9804      	ldr	r0, [sp, #16]
     660:	3801      	subs	r0, #1
     662:	9004      	str	r0, [sp, #16]
			s = va_arg(ap, char *);
     664:	f859 0b04 	ldr.w	r0, [r9], #4
     668:	9000      	str	r0, [sp, #0]
     66a:	e717      	b.n	49c <cbvprintf_package+0x5c>
			if (is_ro && !do_ro) {
     66c:	9802      	ldr	r0, [sp, #8]
     66e:	0780      	lsls	r0, r0, #30
     670:	d548      	bpl.n	704 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x21c>
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     672:	f04f 0c01 	mov.w	ip, #1
				uint32_t s_ptr_idx = BUF_OFFSET / sizeof(int);
     676:	eba4 0e05 	sub.w	lr, r4, r5
     67a:	ea4f 009e 	mov.w	r0, lr, lsr #2
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
     67e:	f5be 7f00 	cmp.w	lr, #512	; 0x200
     682:	d31d      	bcc.n	6c0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x1d8>
					__ASSERT(false, "String with too many arguments");
     684:	4927      	ldr	r1, [pc, #156]	; (724 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x23c>)
     686:	f240 237b 	movw	r3, #635	; 0x27b
     68a:	4a27      	ldr	r2, [pc, #156]	; (728 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x240>)
     68c:	4827      	ldr	r0, [pc, #156]	; (72c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x244>)
     68e:	f008 fe0a 	bl	92a6 <assert_print>
     692:	4827      	ldr	r0, [pc, #156]	; (730 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x248>)
     694:	f008 fe07 	bl	92a6 <assert_print>
     698:	f240 217b 	movw	r1, #635	; 0x27b
					__ASSERT(false, "str_ptr_pos[] too small");
     69c:	4822      	ldr	r0, [pc, #136]	; (728 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x240>)
     69e:	f008 fdfb 	bl	9298 <assert_post_action>
				if (s_idx >= ARRAY_SIZE(str_ptr_pos)) {
     6a2:	2f0f      	cmp	r7, #15
     6a4:	d80e      	bhi.n	6c4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x1dc>
				if (buf0 != NULL) {
     6a6:	2d00      	cmp	r5, #0
     6a8:	d046      	beq.n	738 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x250>
					str_ptr_pos[s_idx] = s_ptr_idx;
     6aa:	f107 0c40 	add.w	ip, r7, #64	; 0x40
     6ae:	44ec      	add	ip, sp
     6b0:	f80c 0c20 	strb.w	r0, [ip, #-32]
					str_ptr_arg[s_idx] = arg_idx;
     6b4:	f80c 2c10 	strb.w	r2, [ip, #-16]
						s_rw_cnt++;
     6b8:	9803      	ldr	r0, [sp, #12]
     6ba:	3001      	adds	r0, #1
     6bc:	9003      	str	r0, [sp, #12]
     6be:	e020      	b.n	702 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x21a>
				if (s_idx >= ARRAY_SIZE(str_ptr_pos)) {
     6c0:	2f0f      	cmp	r7, #15
     6c2:	d90c      	bls.n	6de <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x1f6>
					__ASSERT(false, "str_ptr_pos[] too small");
     6c4:	4917      	ldr	r1, [pc, #92]	; (724 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x23c>)
     6c6:	f44f 7320 	mov.w	r3, #640	; 0x280
     6ca:	4a17      	ldr	r2, [pc, #92]	; (728 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x240>)
     6cc:	4817      	ldr	r0, [pc, #92]	; (72c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x244>)
     6ce:	f008 fdea 	bl	92a6 <assert_print>
     6d2:	4818      	ldr	r0, [pc, #96]	; (734 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x24c>)
     6d4:	f008 fde7 	bl	92a6 <assert_print>
     6d8:	f44f 7120 	mov.w	r1, #640	; 0x280
     6dc:	e7de      	b.n	69c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x1b4>
				if (buf0 != NULL) {
     6de:	b1bd      	cbz	r5, 710 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x228>
					str_ptr_pos[s_idx] = s_ptr_idx;
     6e0:	f107 0e40 	add.w	lr, r7, #64	; 0x40
     6e4:	44ee      	add	lr, sp
     6e6:	b2c0      	uxtb	r0, r0
     6e8:	f80e 0c20 	strb.w	r0, [lr, #-32]
					str_ptr_arg[s_idx] = arg_idx;
     6ec:	f80e 2c10 	strb.w	r2, [lr, #-16]
					if (is_ro) {
     6f0:	f1bc 0f00 	cmp.w	ip, #0
     6f4:	d0e0      	beq.n	6b8 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x1d0>
						str_ptr_pos[s_idx] |= STR_POS_RO_FLAG;
     6f6:	f060 007f 	orn	r0, r0, #127	; 0x7f
     6fa:	f80e 0c20 	strb.w	r0, [lr, #-32]
						s_ro_cnt++;
     6fe:	f108 0801 	add.w	r8, r8, #1
				s_idx++;
     702:	3701      	adds	r7, #1
					if (BUF_OFFSET + size > len) {
     704:	f1c5 0008 	rsb	r0, r5, #8
     708:	46cc      	mov	ip, r9
			buf += sizeof(char *);
     70a:	3404      	adds	r4, #4
					if (BUF_OFFSET + size > len) {
     70c:	9005      	str	r0, [sp, #20]
     70e:	e76f      	b.n	5f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x108>
				} else if (is_ro) {
     710:	f1bc 0f00 	cmp.w	ip, #0
     714:	d010      	beq.n	738 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x250>
					len += 1;
     716:	3601      	adds	r6, #1
     718:	e7f3      	b.n	702 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x21a>
     71a:	bf00      	nop
     71c:	00009c5c 	.word	0x00009c5c
     720:	0000bd24 	.word	0x0000bd24
     724:	0000a5f9 	.word	0x0000a5f9
     728:	0000a2ba 	.word	0x0000a2ba
     72c:	0000a2e8 	.word	0x0000a2e8
     730:	0000a305 	.word	0x0000a305
     734:	0000a326 	.word	0x0000a326
				} else if (rws_pos_en) {
     738:	9801      	ldr	r0, [sp, #4]
					len += 2;
     73a:	3602      	adds	r6, #2
				} else if (rws_pos_en) {
     73c:	2800      	cmp	r0, #0
     73e:	d1e0      	bne.n	702 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x21a>
					len += strlen(s) + 1 + 1;
     740:	9800      	ldr	r0, [sp, #0]
     742:	e9cd 3106 	strd	r3, r1, [sp, #24]
     746:	9205      	str	r2, [sp, #20]
     748:	f008 ff52 	bl	95f0 <strlen>
     74c:	e9dd 3106 	ldrd	r3, r1, [sp, #24]
     750:	9a05      	ldr	r2, [sp, #20]
     752:	4406      	add	r6, r0
     754:	e7d5      	b.n	702 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x21a>
			__ASSERT(false, "unexpected size %u", size);
     756:	f240 23c5 	movw	r3, #709	; 0x2c5
     75a:	4a43      	ldr	r2, [pc, #268]	; (868 <CONFIG_ISR_STACK_SIZE+0x68>)
     75c:	4943      	ldr	r1, [pc, #268]	; (86c <CONFIG_ISR_STACK_SIZE+0x6c>)
     75e:	4844      	ldr	r0, [pc, #272]	; (870 <CONFIG_ISR_STACK_SIZE+0x70>)
     760:	f008 fda1 	bl	92a6 <assert_print>
     764:	4651      	mov	r1, sl
     766:	4843      	ldr	r0, [pc, #268]	; (874 <CONFIG_ISR_STACK_SIZE+0x74>)
     768:	f008 fd9d 	bl	92a6 <assert_print>
     76c:	f240 21c5 	movw	r1, #709	; 0x2c5
     770:	e794      	b.n	69c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x1b4>
	if (BUF_OFFSET / sizeof(int) > 255) {
     772:	1b63      	subs	r3, r4, r5
     774:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
     778:	d30c      	bcc.n	794 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2ac>
		__ASSERT(false, "too many format args");
     77a:	493c      	ldr	r1, [pc, #240]	; (86c <CONFIG_ISR_STACK_SIZE+0x6c>)
     77c:	f240 23d1 	movw	r3, #721	; 0x2d1
     780:	4a39      	ldr	r2, [pc, #228]	; (868 <CONFIG_ISR_STACK_SIZE+0x68>)
     782:	483b      	ldr	r0, [pc, #236]	; (870 <CONFIG_ISR_STACK_SIZE+0x70>)
     784:	f008 fd8f 	bl	92a6 <assert_print>
     788:	483b      	ldr	r0, [pc, #236]	; (878 <CONFIG_ISR_STACK_SIZE+0x78>)
     78a:	f008 fd8c 	bl	92a6 <assert_print>
     78e:	f240 21d1 	movw	r1, #721	; 0x2d1
     792:	e783      	b.n	69c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x1b4>
	if (buf0 == NULL) {
     794:	b91d      	cbnz	r5, 79e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2b6>
		return BUF_OFFSET + len - CBPRINTF_PACKAGE_ALIGNMENT;
     796:	f1a6 0408 	sub.w	r4, r6, #8
     79a:	18e0      	adds	r0, r4, r3
     79c:	e669      	b.n	472 <cbvprintf_package+0x32>
	if (rws_pos_en) {
     79e:	9a01      	ldr	r2, [sp, #4]
	pkg_hdr->desc.len = BUF_OFFSET / sizeof(int);
     7a0:	089b      	lsrs	r3, r3, #2
	*(char **)buf0 = NULL;
     7a2:	6028      	str	r0, [r5, #0]
	pkg_hdr->desc.len = BUF_OFFSET / sizeof(int);
     7a4:	702b      	strb	r3, [r5, #0]
		pkg_hdr->desc.rw_str_cnt = s_rw_cnt;
     7a6:	f89d 300c 	ldrb.w	r3, [sp, #12]
	if (rws_pos_en) {
     7aa:	b1c2      	cbz	r2, 7de <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2f6>
		pkg_hdr->desc.rw_str_cnt = s_rw_cnt;
     7ac:	70eb      	strb	r3, [r5, #3]
	pkg_hdr->desc.ro_str_cnt = s_ro_cnt;
     7ae:	f885 8002 	strb.w	r8, [r5, #2]
	if (s_ro_cnt) {
     7b2:	f1b8 0f00 	cmp.w	r8, #0
     7b6:	d005      	beq.n	7c4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2dc>
		for (i = 0; i < s_idx; i++) {
     7b8:	2200      	movs	r2, #0
     7ba:	a808      	add	r0, sp, #32
			if (BUF_OFFSET + 1 > len) {
     7bc:	f1c5 0c01 	rsb	ip, r5, #1
		for (i = 0; i < s_idx; i++) {
     7c0:	4297      	cmp	r7, r2
     7c2:	d10e      	bne.n	7e2 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2fa>
			*buf++ = str_ptr_arg[i];
     7c4:	f04f 0a00 	mov.w	sl, #0
		if (BUF_OFFSET + 1 + size > len) {
     7c8:	f1c5 0301 	rsb	r3, r5, #1
     7cc:	f10d 0920 	add.w	r9, sp, #32
     7d0:	9302      	str	r3, [sp, #8]
			*buf++ = str_ptr_arg[i];
     7d2:	f10d 0b30 	add.w	fp, sp, #48	; 0x30
	for (i = 0; i < s_idx; i++) {
     7d6:	4557      	cmp	r7, sl
     7d8:	d112      	bne.n	800 <CONFIG_ISR_STACK_SIZE>
	return BUF_OFFSET;
     7da:	1b60      	subs	r0, r4, r5
     7dc:	e649      	b.n	472 <cbvprintf_package+0x32>
		pkg_hdr->desc.str_cnt = s_rw_cnt;
     7de:	706b      	strb	r3, [r5, #1]
		pkg_hdr->desc.rw_str_cnt = 0;
     7e0:	e7e5      	b.n	7ae <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2c6>
			if (!(str_ptr_pos[i] & STR_POS_RO_FLAG)) {
     7e2:	f810 3b01 	ldrb.w	r3, [r0], #1
     7e6:	0619      	lsls	r1, r3, #24
     7e8:	d508      	bpl.n	7fc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x314>
			if (BUF_OFFSET + 1 > len) {
     7ea:	eb04 0e0c 	add.w	lr, r4, ip
     7ee:	45b6      	cmp	lr, r6
			uint8_t pos = str_ptr_pos[i] & STR_POS_MASK;
     7f0:	f003 037f 	and.w	r3, r3, #127	; 0x7f
			if (BUF_OFFSET + 1 > len) {
     7f4:	f63f ae3b 	bhi.w	46e <cbvprintf_package+0x2e>
			*buf++ = pos;
     7f8:	f804 3b01 	strb.w	r3, [r4], #1
		for (i = 0; i < s_idx; i++) {
     7fc:	3201      	adds	r2, #1
     7fe:	e7df      	b.n	7c0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2d8>
		if (s_ro_cnt && str_ptr_pos[i] & STR_POS_RO_FLAG) {
     800:	f1b8 0f00 	cmp.w	r8, #0
     804:	d003      	beq.n	80e <CONFIG_ISR_STACK_SIZE+0xe>
     806:	f999 2000 	ldrsb.w	r2, [r9]
     80a:	2a00      	cmp	r2, #0
     80c:	db17      	blt.n	83e <CONFIG_ISR_STACK_SIZE+0x3e>
		if (rws_pos_en) {
     80e:	9b01      	ldr	r3, [sp, #4]
     810:	b1d3      	cbz	r3, 848 <CONFIG_ISR_STACK_SIZE+0x48>
			*buf++ = str_ptr_arg[i];
     812:	f81a 200b 	ldrb.w	r2, [sl, fp]
     816:	f804 2b01 	strb.w	r2, [r4], #1
			size = 0;
     81a:	2200      	movs	r2, #0
		if (BUF_OFFSET + 1 + size > len) {
     81c:	9b02      	ldr	r3, [sp, #8]
     81e:	1898      	adds	r0, r3, r2
     820:	4420      	add	r0, r4
     822:	42b0      	cmp	r0, r6
     824:	f63f ae23 	bhi.w	46e <cbvprintf_package+0x2e>
		*buf++ = str_ptr_pos[i];
     828:	f899 0000 	ldrb.w	r0, [r9]
		memcpy(buf, s, size);
     82c:	9900      	ldr	r1, [sp, #0]
		*buf++ = str_ptr_pos[i];
     82e:	f804 0b01 	strb.w	r0, [r4], #1
		memcpy(buf, s, size);
     832:	4620      	mov	r0, r4
     834:	9203      	str	r2, [sp, #12]
     836:	f008 feeb 	bl	9610 <memcpy>
		buf += size;
     83a:	9a03      	ldr	r2, [sp, #12]
     83c:	4414      	add	r4, r2
	for (i = 0; i < s_idx; i++) {
     83e:	f10a 0a01 	add.w	sl, sl, #1
     842:	f109 0901 	add.w	r9, r9, #1
     846:	e7c6      	b.n	7d6 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2ee>
			s = *(char **)(buf0 + str_ptr_pos[i] * sizeof(int));
     848:	f899 2000 	ldrb.w	r2, [r9]
     84c:	f855 3022 	ldr.w	r3, [r5, r2, lsl #2]
     850:	9300      	str	r3, [sp, #0]
			*(char **)(buf0 + str_ptr_pos[i] * sizeof(int)) = NULL;
     852:	9b01      	ldr	r3, [sp, #4]
			size = strlen(s) + 1;
     854:	9800      	ldr	r0, [sp, #0]
			*(char **)(buf0 + str_ptr_pos[i] * sizeof(int)) = NULL;
     856:	f845 3022 	str.w	r3, [r5, r2, lsl #2]
			size = strlen(s) + 1;
     85a:	f008 fec9 	bl	95f0 <strlen>
     85e:	1c42      	adds	r2, r0, #1
     860:	e7dc      	b.n	81c <CONFIG_ISR_STACK_SIZE+0x1c>
		return -EFAULT;
     862:	f06f 000d 	mvn.w	r0, #13
     866:	e604      	b.n	472 <cbvprintf_package+0x32>
     868:	0000a2ba 	.word	0x0000a2ba
     86c:	0000a5f9 	.word	0x0000a5f9
     870:	0000a2e8 	.word	0x0000a2e8
     874:	0000a340 	.word	0x0000a340
     878:	0000a355 	.word	0x0000a355

0000087c <cbprintf_package_convert>:
			     cbprintf_convert_cb cb,
			     void *ctx,
			     uint32_t flags,
			     uint16_t *strl,
			     size_t strl_len)
{
     87c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     880:	b095      	sub	sp, #84	; 0x54
     882:	af00      	add	r7, sp, #0
	__ASSERT_NO_MSG(in_packaged != NULL);
     884:	4604      	mov	r4, r0
{
     886:	e9c7 1208 	strd	r1, r2, [r7, #32]
     88a:	f8d7 b078 	ldr.w	fp, [r7, #120]	; 0x78
     88e:	61bb      	str	r3, [r7, #24]
	__ASSERT_NO_MSG(in_packaged != NULL);
     890:	b958      	cbnz	r0, 8aa <cbprintf_package_convert+0x2e>
     892:	49aa      	ldr	r1, [pc, #680]	; (b3c <cbprintf_package_convert+0x2c0>)
     894:	f44f 7365 	mov.w	r3, #916	; 0x394
     898:	4aa9      	ldr	r2, [pc, #676]	; (b40 <cbprintf_package_convert+0x2c4>)
     89a:	48aa      	ldr	r0, [pc, #680]	; (b44 <cbprintf_package_convert+0x2c8>)
     89c:	f008 fd03 	bl	92a6 <assert_print>
     8a0:	f44f 7165 	mov.w	r1, #916	; 0x394
			continue;
		}

		if (is_ro) {
			if (flags & CBPRINTF_PACKAGE_CONVERT_RO_STR) {
				__ASSERT_NO_MSG(scpy_cnt < sizeof(cpy_str_pos));
     8a4:	48a6      	ldr	r0, [pc, #664]	; (b40 <cbprintf_package_convert+0x2c4>)
     8a6:	f008 fcf7 	bl	9298 <assert_post_action>
	bool fmt_present = flags & CBPRINTF_PACKAGE_CONVERT_PTR_CHECK ? true : false;
     8aa:	f3cb 03c0 	ubfx	r3, fp, #3, #1
     8ae:	613b      	str	r3, [r7, #16]
	in_len = in_len != 0 ? in_len : get_package_len(in_packaged);
     8b0:	6a3b      	ldr	r3, [r7, #32]
     8b2:	b953      	cbnz	r3, 8ca <cbprintf_package_convert+0x4e>
	buf += ros_nbr;
     8b4:	7803      	ldrb	r3, [r0, #0]
	s_nbr     = buf[1];
     8b6:	7846      	ldrb	r6, [r0, #1]
	buf += ros_nbr;
     8b8:	7880      	ldrb	r0, [r0, #2]
	for (int i = 0; i < s_nbr; i++) {
     8ba:	6a3d      	ldr	r5, [r7, #32]
	buf += ros_nbr;
     8bc:	eb00 0083 	add.w	r0, r0, r3, lsl #2
     8c0:	4420      	add	r0, r4
	for (int i = 0; i < s_nbr; i++) {
     8c2:	42ae      	cmp	r6, r5
     8c4:	d81a      	bhi.n	8fc <cbprintf_package_convert+0x80>
	return (size_t)(uintptr_t)(buf - start);
     8c6:	1b03      	subs	r3, r0, r4
     8c8:	623b      	str	r3, [r7, #32]
	ros_nbr = in_desc->ro_str_cnt;
     8ca:	f894 9002 	ldrb.w	r9, [r4, #2]
	rws_nbr = in_desc->rw_str_cnt;
     8ce:	78e3      	ldrb	r3, [r4, #3]
	ros_nbr = in_desc->ro_str_cnt;
     8d0:	464e      	mov	r6, r9
	rws_nbr = in_desc->rw_str_cnt;
     8d2:	617b      	str	r3, [r7, #20]
	ro_cpy = ros_nbr &&
     8d4:	f1b9 0f00 	cmp.w	r9, #0
     8d8:	d002      	beq.n	8e0 <cbprintf_package_convert+0x64>
     8da:	f01b 0f01 	tst.w	fp, #1
     8de:	d116      	bne.n	90e <cbprintf_package_convert+0x92>
	rw_cpy = rws_nbr > 0 &&
     8e0:	697b      	ldr	r3, [r7, #20]
     8e2:	bb53      	cbnz	r3, 93a <cbprintf_package_convert+0xbe>
		if (cb) {
     8e4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
     8e6:	b11b      	cbz	r3, 8f0 <cbprintf_package_convert+0x74>
			cb(in_packaged, in_len, ctx);
     8e8:	4620      	mov	r0, r4
     8ea:	69ba      	ldr	r2, [r7, #24]
     8ec:	6a39      	ldr	r1, [r7, #32]
     8ee:	4798      	blx	r3
		return in_len;
     8f0:	6a3d      	ldr	r5, [r7, #32]

	/* Empty call (can be interpreted as flushing) */
	(void)cb(NULL, 0, ctx);

	return out_len;
}
     8f2:	4628      	mov	r0, r5
     8f4:	3754      	adds	r7, #84	; 0x54
     8f6:	46bd      	mov	sp, r7
     8f8:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		buf++;
     8fc:	f100 0801 	add.w	r8, r0, #1
		buf += strlen((const char *)buf) + 1;
     900:	4640      	mov	r0, r8
     902:	f008 fe75 	bl	95f0 <strlen>
     906:	3001      	adds	r0, #1
     908:	4440      	add	r0, r8
	for (int i = 0; i < s_nbr; i++) {
     90a:	3501      	adds	r5, #1
     90c:	e7d9      	b.n	8c2 <cbprintf_package_convert+0x46>
	rw_cpy = rws_nbr > 0 &&
     90e:	6863      	ldr	r3, [r4, #4]
     910:	f894 a000 	ldrb.w	sl, [r4]
	const char *fmt = *(const char **)(buf + sizeof(void *));
     914:	61fb      	str	r3, [r7, #28]
	if (cb == NULL) {
     916:	6a7b      	ldr	r3, [r7, #36]	; 0x24
	args_size = in_desc->len * sizeof(int);
     918:	ea4f 028a 	mov.w	r2, sl, lsl #2
     91c:	60fa      	str	r2, [r7, #12]
	uint8_t *str_pos = &buf[args_size];
     91e:	eb04 0a8a 	add.w	sl, r4, sl, lsl #2
	if (cb == NULL) {
     922:	2b00      	cmp	r3, #0
     924:	f040 8105 	bne.w	b32 <cbprintf_package_convert+0x2b6>
		out_len = (int)in_len;
     928:	46d0      	mov	r8, sl
	size_t strl_cnt = 0;
     92a:	2600      	movs	r6, #0
		out_len = (int)in_len;
     92c:	6a3d      	ldr	r5, [r7, #32]
		if (ro_cpy) {
     92e:	eb09 030a 	add.w	r3, r9, sl
			for (int i = 0; i < ros_nbr; i++) {
     932:	4598      	cmp	r8, r3
     934:	d14e      	bne.n	9d4 <cbprintf_package_convert+0x158>
     936:	44ca      	add	sl, r9
     938:	e013      	b.n	962 <cbprintf_package_convert+0xe6>
	rw_cpy = rws_nbr > 0 &&
     93a:	f01b 0f02 	tst.w	fp, #2
     93e:	d0d1      	beq.n	8e4 <cbprintf_package_convert+0x68>
	args_size = in_desc->len * sizeof(int);
     940:	f894 a000 	ldrb.w	sl, [r4]
     944:	ea4f 038a 	mov.w	r3, sl, lsl #2
     948:	60fb      	str	r3, [r7, #12]
	const char *fmt = *(const char **)(buf + sizeof(void *));
     94a:	6863      	ldr	r3, [r4, #4]
	uint8_t *str_pos = &buf[args_size];
     94c:	eb04 0a8a 	add.w	sl, r4, sl, lsl #2
	const char *fmt = *(const char **)(buf + sizeof(void *));
     950:	61fb      	str	r3, [r7, #28]
	if (cb == NULL) {
     952:	6a7b      	ldr	r3, [r7, #36]	; 0x24
     954:	2b00      	cmp	r3, #0
     956:	d178      	bne.n	a4a <cbprintf_package_convert+0x1ce>
		out_len = (int)in_len;
     958:	6a3d      	ldr	r5, [r7, #32]
			if (ros_nbr && flags & CBPRINTF_PACKAGE_CONVERT_KEEP_RO_STR) {
     95a:	f1b9 0f00 	cmp.w	r9, #0
     95e:	d14e      	bne.n	9fe <cbprintf_package_convert+0x182>
	size_t strl_cnt = 0;
     960:	464e      	mov	r6, r9
		for (int i = 0; i < rws_nbr; i++) {
     962:	f01b 0f05 	tst.w	fp, #5
     966:	bf0c      	ite	eq
     968:	2302      	moveq	r3, #2
     96a:	2301      	movne	r3, #1
     96c:	627b      	str	r3, [r7, #36]	; 0x24
     96e:	697b      	ldr	r3, [r7, #20]
     970:	eb0a 0943 	add.w	r9, sl, r3, lsl #1
			} else if (flags & CBPRINTF_PACKAGE_CONVERT_RW_STR) {
     974:	f00b 0302 	and.w	r3, fp, #2
     978:	623b      	str	r3, [r7, #32]
		for (int i = 0; i < rws_nbr; i++) {
     97a:	45ca      	cmp	sl, r9
     97c:	d0b9      	beq.n	8f2 <cbprintf_package_convert+0x76>
			uint8_t arg_idx = *str_pos++;
     97e:	f81a 1b02 	ldrb.w	r1, [sl], #2
			const char *str = *(const char **)&buf32[arg_pos];
     982:	f81a 3c01 	ldrb.w	r3, [sl, #-1]
     986:	f854 8023 	ldr.w	r8, [r4, r3, lsl #2]
     98a:	4b6f      	ldr	r3, [pc, #444]	; (b48 <cbprintf_package_convert+0x2cc>)
     98c:	4598      	cmp	r8, r3
     98e:	d302      	bcc.n	996 <cbprintf_package_convert+0x11a>
     990:	4b6e      	ldr	r3, [pc, #440]	; (b4c <cbprintf_package_convert+0x2d0>)
     992:	4598      	cmp	r8, r3
     994:	d339      	bcc.n	a0a <cbprintf_package_convert+0x18e>
			if (fmt_present && is_ptr(fmt, arg_idx)) {
     996:	693b      	ldr	r3, [r7, #16]
     998:	2b00      	cmp	r3, #0
     99a:	d043      	beq.n	a24 <cbprintf_package_convert+0x1a8>
     99c:	69f8      	ldr	r0, [r7, #28]
     99e:	f008 fb58 	bl	9052 <is_ptr>
     9a2:	2800      	cmp	r0, #0
     9a4:	d03e      	beq.n	a24 <cbprintf_package_convert+0x1a8>
				LOG_WRN("(unsigned) char * used for %%p argument. "
     9a6:	46e8      	mov	r8, sp
     9a8:	b08a      	sub	sp, #40	; 0x28
     9aa:	466a      	mov	r2, sp
     9ac:	4b68      	ldr	r3, [pc, #416]	; (b50 <cbprintf_package_convert+0x2d4>)
     9ae:	6153      	str	r3, [r2, #20]
     9b0:	69fb      	ldr	r3, [r7, #28]
     9b2:	e9c2 3106 	strd	r3, r1, [r2, #24]
     9b6:	f44f 7300 	mov.w	r3, #512	; 0x200
     9ba:	8413      	strh	r3, [r2, #32]
     9bc:	4b65      	ldr	r3, [pc, #404]	; (b54 <cbprintf_package_convert+0x2d8>)
     9be:	f842 3f10 	str.w	r3, [r2, #16]!
		(void) arch_syscall_invoke4(parm0.x, parm1.x, parm2.x, parm3.x, K_SYSCALL_Z_LOG_MSG_STATIC_CREATE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_z_log_msg_static_create(source, desc, package, data);
     9c2:	2300      	movs	r3, #0
     9c4:	f44f 5112 	mov.w	r1, #9344	; 0x2480
     9c8:	4863      	ldr	r0, [pc, #396]	; (b58 <cbprintf_package_convert+0x2dc>)
     9ca:	f001 ff2d 	bl	2828 <z_impl_z_log_msg_static_create>
				out_len -= 2;
     9ce:	3d02      	subs	r5, #2
     9d0:	46c5      	mov	sp, r8
				continue;
     9d2:	e7d2      	b.n	97a <cbprintf_package_convert+0xfe>
				const char *str = *(const char **)&buf32[*str_pos];
     9d4:	f818 2b01 	ldrb.w	r2, [r8], #1
     9d8:	627b      	str	r3, [r7, #36]	; 0x24
		return 1 + strlen(str);
     9da:	f854 0022 	ldr.w	r0, [r4, r2, lsl #2]
     9de:	f008 fe07 	bl	95f0 <strlen>
				if (strl && strl_cnt < strl_len) {
     9e2:	6ffa      	ldr	r2, [r7, #124]	; 0x7c
     9e4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
		return 1 + strlen(str);
     9e6:	3001      	adds	r0, #1
				if (strl && strl_cnt < strl_len) {
     9e8:	b13a      	cbz	r2, 9fa <cbprintf_package_convert+0x17e>
     9ea:	f8d7 2080 	ldr.w	r2, [r7, #128]	; 0x80
     9ee:	4296      	cmp	r6, r2
					strl[strl_cnt++] = (uint16_t)len;
     9f0:	bf3e      	ittt	cc
     9f2:	6ffa      	ldrcc	r2, [r7, #124]	; 0x7c
     9f4:	f822 0016 	strhcc.w	r0, [r2, r6, lsl #1]
     9f8:	3601      	addcc	r6, #1
				out_len += len;
     9fa:	4405      	add	r5, r0
			for (int i = 0; i < ros_nbr; i++) {
     9fc:	e799      	b.n	932 <cbprintf_package_convert+0xb6>
			if (ros_nbr && flags & CBPRINTF_PACKAGE_CONVERT_KEEP_RO_STR) {
     9fe:	f01b 0604 	ands.w	r6, fp, #4
	size_t strl_cnt = 0;
     a02:	bf1c      	itt	ne
     a04:	6a7e      	ldrne	r6, [r7, #36]	; 0x24
				str_pos += ros_nbr;
     a06:	44ca      	addne	sl, r9
     a08:	e7ab      	b.n	962 <cbprintf_package_convert+0xe6>
			if (fmt_present && is_ptr(fmt, arg_idx)) {
     a0a:	693b      	ldr	r3, [r7, #16]
     a0c:	b123      	cbz	r3, a18 <cbprintf_package_convert+0x19c>
     a0e:	69f8      	ldr	r0, [r7, #28]
     a10:	f008 fb1f 	bl	9052 <is_ptr>
     a14:	2800      	cmp	r0, #0
     a16:	d1c6      	bne.n	9a6 <cbprintf_package_convert+0x12a>
				if (flags & CBPRINTF_PACKAGE_CONVERT_RO_STR) {
     a18:	f01b 0f01 	tst.w	fp, #1
     a1c:	d105      	bne.n	a2a <cbprintf_package_convert+0x1ae>
					out_len -= drop_ro_str_pos ? 2 : 1;
     a1e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
     a20:	1aed      	subs	r5, r5, r3
     a22:	e7aa      	b.n	97a <cbprintf_package_convert+0xfe>
			} else if (flags & CBPRINTF_PACKAGE_CONVERT_RW_STR) {
     a24:	6a3b      	ldr	r3, [r7, #32]
     a26:	2b00      	cmp	r3, #0
     a28:	d0a7      	beq.n	97a <cbprintf_package_convert+0xfe>
		return 1 + strlen(str);
     a2a:	4640      	mov	r0, r8
     a2c:	f008 fde0 	bl	95f0 <strlen>
				if (strl && strl_cnt < strl_len) {
     a30:	6ffb      	ldr	r3, [r7, #124]	; 0x7c
     a32:	b143      	cbz	r3, a46 <cbprintf_package_convert+0x1ca>
     a34:	f8d7 3080 	ldr.w	r3, [r7, #128]	; 0x80
     a38:	429e      	cmp	r6, r3
					strl[strl_cnt++] = (uint16_t)len;
     a3a:	bf3f      	itttt	cc
     a3c:	6ffa      	ldrcc	r2, [r7, #124]	; 0x7c
		return 1 + strlen(str);
     a3e:	1c43      	addcc	r3, r0, #1
					strl[strl_cnt++] = (uint16_t)len;
     a40:	f822 3016 	strhcc.w	r3, [r2, r6, lsl #1]
     a44:	3601      	addcc	r6, #1
				out_len += (len - 1);
     a46:	4405      	add	r5, r0
		for (int i = 0; i < rws_nbr; i++) {
     a48:	e797      	b.n	97a <cbprintf_package_convert+0xfe>
	} else if (ros_nbr && flags & CBPRINTF_PACKAGE_CONVERT_KEEP_RO_STR) {
     a4a:	f1b9 0f00 	cmp.w	r9, #0
     a4e:	f000 8085 	beq.w	b5c <cbprintf_package_convert+0x2e0>
     a52:	f01b 0604 	ands.w	r6, fp, #4
     a56:	f000 8084 	beq.w	b62 <cbprintf_package_convert+0x2e6>
		keep_cnt = ros_nbr;
     a5a:	46c8      	mov	r8, r9
		scpy_cnt = 0;
     a5c:	2600      	movs	r6, #0
		dst = keep_str_pos;
     a5e:	f107 0040 	add.w	r0, r7, #64	; 0x40
		memcpy(dst, str_pos, ros_nbr);
     a62:	464a      	mov	r2, r9
     a64:	4651      	mov	r1, sl
     a66:	f008 fdd3 	bl	9610 <memcpy>
	str_pos += ros_nbr;
     a6a:	697b      	ldr	r3, [r7, #20]
     a6c:	44ca      	add	sl, r9
	for (int i = 0; i < rws_nbr; i++) {
     a6e:	005b      	lsls	r3, r3, #1
     a70:	60bb      	str	r3, [r7, #8]
     a72:	697b      	ldr	r3, [r7, #20]
     a74:	eb0a 0343 	add.w	r3, sl, r3, lsl #1
     a78:	617b      	str	r3, [r7, #20]
			if (flags & CBPRINTF_PACKAGE_CONVERT_RW_STR) {
     a7a:	f00b 0302 	and.w	r3, fp, #2
     a7e:	607b      	str	r3, [r7, #4]
	for (int i = 0; i < rws_nbr; i++) {
     a80:	697b      	ldr	r3, [r7, #20]
     a82:	459a      	cmp	sl, r3
     a84:	d16f      	bne.n	b66 <cbprintf_package_convert+0x2ea>
	out_desc.len = in_desc->len;
     a86:	7823      	ldrb	r3, [r4, #0]
	out_desc.rw_str_cnt = (flags & CBPRINTF_PACKAGE_CONVERT_RW_STR) ? 0 : (keep_cnt / 2);
     a88:	f01b 0f02 	tst.w	fp, #2
	out_desc.len = in_desc->len;
     a8c:	617b      	str	r3, [r7, #20]
	out_desc.str_cnt = in_desc->str_cnt + scpy_cnt;
     a8e:	7863      	ldrb	r3, [r4, #1]
	out_desc.rw_str_cnt = (flags & CBPRINTF_PACKAGE_CONVERT_RW_STR) ? 0 : (keep_cnt / 2);
     a90:	bf18      	it	ne
     a92:	2100      	movne	r1, #0
	out_desc.str_cnt = in_desc->str_cnt + scpy_cnt;
     a94:	eb06 0203 	add.w	r2, r6, r3
	out_desc.rw_str_cnt = (flags & CBPRINTF_PACKAGE_CONVERT_RW_STR) ? 0 : (keep_cnt / 2);
     a98:	bf08      	it	eq
     a9a:	ea4f 0158 	moveq.w	r1, r8, lsr #1
	out_desc.ro_str_cnt = (flags & CBPRINTF_PACKAGE_CONVERT_RO_STR) ? 0 :
     a9e:	f01b 0f01 	tst.w	fp, #1
	out_desc.str_cnt = in_desc->str_cnt + scpy_cnt;
     aa2:	b2d2      	uxtb	r2, r2
	out_desc.ro_str_cnt = (flags & CBPRINTF_PACKAGE_CONVERT_RO_STR) ? 0 :
     aa4:	f040 80e2 	bne.w	c6c <cbprintf_package_convert+0x3f0>
     aa8:	f01b 0f04 	tst.w	fp, #4
     aac:	bf14      	ite	ne
     aae:	4640      	movne	r0, r8
     ab0:	2000      	moveq	r0, #0
     ab2:	613b      	str	r3, [r7, #16]
	struct cbprintf_package_desc in_desc_backup = *in_desc;
     ab4:	78a3      	ldrb	r3, [r4, #2]
     ab6:	f894 b003 	ldrb.w	fp, [r4, #3]
     aba:	61fb      	str	r3, [r7, #28]
	*in_desc = out_desc;
     abc:	7062      	strb	r2, [r4, #1]
     abe:	70a0      	strb	r0, [r4, #2]
     ac0:	70e1      	strb	r1, [r4, #3]
	rv = cb(in_packaged, args_size, ctx);
     ac2:	4620      	mov	r0, r4
     ac4:	69ba      	ldr	r2, [r7, #24]
     ac6:	68f9      	ldr	r1, [r7, #12]
     ac8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
     aca:	4798      	blx	r3
	if (rv < 0) {
     acc:	1e05      	subs	r5, r0, #0
     ace:	f6ff af10 	blt.w	8f2 <cbprintf_package_convert+0x76>
	*in_desc = in_desc_backup;
     ad2:	697b      	ldr	r3, [r7, #20]
	rv = cb(keep_str_pos, keep_cnt, ctx);
     ad4:	4641      	mov	r1, r8
	*in_desc = in_desc_backup;
     ad6:	7023      	strb	r3, [r4, #0]
     ad8:	693b      	ldr	r3, [r7, #16]
	rv = cb(keep_str_pos, keep_cnt, ctx);
     ada:	69ba      	ldr	r2, [r7, #24]
	*in_desc = in_desc_backup;
     adc:	7063      	strb	r3, [r4, #1]
     ade:	69fb      	ldr	r3, [r7, #28]
     ae0:	f884 b003 	strb.w	fp, [r4, #3]
     ae4:	70a3      	strb	r3, [r4, #2]
	rv = cb(keep_str_pos, keep_cnt, ctx);
     ae6:	f107 0040 	add.w	r0, r7, #64	; 0x40
     aea:	6a7b      	ldr	r3, [r7, #36]	; 0x24
     aec:	4798      	blx	r3
	if (rv < 0) {
     aee:	f1b0 0800 	subs.w	r8, r0, #0
     af2:	f2c0 80e8 	blt.w	cc6 <cbprintf_package_convert+0x44a>
	size_t strs_len = in_len - (args_size + ros_nbr + 2 * rws_nbr);
     af6:	6a3b      	ldr	r3, [r7, #32]
	rv = cb(str_pos, strs_len, ctx);
     af8:	4650      	mov	r0, sl
	size_t strs_len = in_len - (args_size + ros_nbr + 2 * rws_nbr);
     afa:	eba3 0109 	sub.w	r1, r3, r9
     afe:	68fb      	ldr	r3, [r7, #12]
	rv = cb(str_pos, strs_len, ctx);
     b00:	69ba      	ldr	r2, [r7, #24]
	size_t strs_len = in_len - (args_size + ros_nbr + 2 * rws_nbr);
     b02:	1ac9      	subs	r1, r1, r3
	rv = cb(str_pos, strs_len, ctx);
     b04:	68bb      	ldr	r3, [r7, #8]
     b06:	1ac9      	subs	r1, r1, r3
     b08:	6a7b      	ldr	r3, [r7, #36]	; 0x24
     b0a:	4798      	blx	r3
	if (rv < 0) {
     b0c:	2800      	cmp	r0, #0
     b0e:	f2c0 80dc 	blt.w	cca <cbprintf_package_convert+0x44e>
	for (int i = 0; i < scpy_cnt; i++) {
     b12:	f04f 0b00 	mov.w	fp, #0
	out_len += rv;
     b16:	44a8      	add	r8, r5
	out_len += rv;
     b18:	eb08 0500 	add.w	r5, r8, r0
		uint8_t loc = cpy_str_pos[i];
     b1c:	f107 0a30 	add.w	sl, r7, #48	; 0x30
	for (int i = 0; i < scpy_cnt; i++) {
     b20:	45b3      	cmp	fp, r6
     b22:	f2c0 80a5 	blt.w	c70 <cbprintf_package_convert+0x3f4>
	(void)cb(NULL, 0, ctx);
     b26:	2100      	movs	r1, #0
     b28:	69ba      	ldr	r2, [r7, #24]
     b2a:	4608      	mov	r0, r1
     b2c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
     b2e:	4798      	blx	r3
	return out_len;
     b30:	e6df      	b.n	8f2 <cbprintf_package_convert+0x76>
	if (cb == NULL) {
     b32:	f04f 0800 	mov.w	r8, #0
     b36:	f107 0030 	add.w	r0, r7, #48	; 0x30
     b3a:	e792      	b.n	a62 <cbprintf_package_convert+0x1e6>
     b3c:	0000a36c 	.word	0x0000a36c
     b40:	0000a2ba 	.word	0x0000a2ba
     b44:	0000a2e8 	.word	0x0000a2e8
     b48:	00009c5c 	.word	0x00009c5c
     b4c:	0000bd24 	.word	0x0000bd24
     b50:	0000a387 	.word	0x0000a387
     b54:	01000004 	.word	0x01000004
     b58:	00009fa4 	.word	0x00009fa4
		scpy_cnt = 0;
     b5c:	464e      	mov	r6, r9
		keep_cnt = 0;
     b5e:	46c8      	mov	r8, r9
     b60:	e783      	b.n	a6a <cbprintf_package_convert+0x1ee>
     b62:	46b0      	mov	r8, r6
     b64:	e781      	b.n	a6a <cbprintf_package_convert+0x1ee>
		uint8_t arg_idx = *str_pos++;
     b66:	f81a 1b02 	ldrb.w	r1, [sl], #2
     b6a:	4b59      	ldr	r3, [pc, #356]	; (cd0 <cbprintf_package_convert+0x454>)
		uint8_t arg_pos = *str_pos++;
     b6c:	f81a 5c01 	ldrb.w	r5, [sl, #-1]
		const char *str = *(const char **)&buf32[arg_pos];
     b70:	f854 2025 	ldr.w	r2, [r4, r5, lsl #2]
     b74:	429a      	cmp	r2, r3
     b76:	d302      	bcc.n	b7e <cbprintf_package_convert+0x302>
     b78:	4b56      	ldr	r3, [pc, #344]	; (cd4 <cbprintf_package_convert+0x458>)
     b7a:	429a      	cmp	r2, r3
     b7c:	d316      	bcc.n	bac <cbprintf_package_convert+0x330>
		if (fmt_present && is_ptr(fmt, arg_idx)) {
     b7e:	693b      	ldr	r3, [r7, #16]
     b80:	b12b      	cbz	r3, b8e <cbprintf_package_convert+0x312>
     b82:	69f8      	ldr	r0, [r7, #28]
     b84:	f008 fa65 	bl	9052 <is_ptr>
     b88:	2800      	cmp	r0, #0
     b8a:	f47f af79 	bne.w	a80 <cbprintf_package_convert+0x204>
			if (flags & CBPRINTF_PACKAGE_CONVERT_RW_STR) {
     b8e:	687b      	ldr	r3, [r7, #4]
     b90:	2b00      	cmp	r3, #0
     b92:	d04a      	beq.n	c2a <cbprintf_package_convert+0x3ae>
				__ASSERT_NO_MSG(scpy_cnt < sizeof(cpy_str_pos));
     b94:	2e0f      	cmp	r6, #15
     b96:	d93e      	bls.n	c16 <cbprintf_package_convert+0x39a>
     b98:	494f      	ldr	r1, [pc, #316]	; (cd8 <cbprintf_package_convert+0x45c>)
     b9a:	f44f 6389 	mov.w	r3, #1096	; 0x448
     b9e:	4a4f      	ldr	r2, [pc, #316]	; (cdc <cbprintf_package_convert+0x460>)
     ba0:	484f      	ldr	r0, [pc, #316]	; (ce0 <cbprintf_package_convert+0x464>)
     ba2:	f008 fb80 	bl	92a6 <assert_print>
     ba6:	f44f 6189 	mov.w	r1, #1096	; 0x448
     baa:	e67b      	b.n	8a4 <cbprintf_package_convert+0x28>
		if (fmt_present && is_ptr(fmt, arg_idx)) {
     bac:	693b      	ldr	r3, [r7, #16]
     bae:	b12b      	cbz	r3, bbc <cbprintf_package_convert+0x340>
     bb0:	69f8      	ldr	r0, [r7, #28]
     bb2:	f008 fa4e 	bl	9052 <is_ptr>
     bb6:	2800      	cmp	r0, #0
     bb8:	f47f af62 	bne.w	a80 <cbprintf_package_convert+0x204>
			if (flags & CBPRINTF_PACKAGE_CONVERT_RO_STR) {
     bbc:	f01b 0f01 	tst.w	fp, #1
     bc0:	d00b      	beq.n	bda <cbprintf_package_convert+0x35e>
				__ASSERT_NO_MSG(scpy_cnt < sizeof(cpy_str_pos));
     bc2:	2e0f      	cmp	r6, #15
     bc4:	d927      	bls.n	c16 <cbprintf_package_convert+0x39a>
     bc6:	4944      	ldr	r1, [pc, #272]	; (cd8 <cbprintf_package_convert+0x45c>)
     bc8:	f240 433e 	movw	r3, #1086	; 0x43e
     bcc:	4a43      	ldr	r2, [pc, #268]	; (cdc <cbprintf_package_convert+0x460>)
     bce:	4844      	ldr	r0, [pc, #272]	; (ce0 <cbprintf_package_convert+0x464>)
     bd0:	f008 fb69 	bl	92a6 <assert_print>
     bd4:	f240 413e 	movw	r1, #1086	; 0x43e
     bd8:	e664      	b.n	8a4 <cbprintf_package_convert+0x28>
			} else if (flags & CBPRINTF_PACKAGE_CONVERT_KEEP_RO_STR) {
     bda:	f01b 0f04 	tst.w	fp, #4
     bde:	f43f af4f 	beq.w	a80 <cbprintf_package_convert+0x204>
				__ASSERT_NO_MSG(keep_cnt < sizeof(keep_str_pos));
     be2:	f1b8 0f0f 	cmp.w	r8, #15
     be6:	d909      	bls.n	bfc <cbprintf_package_convert+0x380>
     be8:	493e      	ldr	r1, [pc, #248]	; (ce4 <cbprintf_package_convert+0x468>)
     bea:	f240 4341 	movw	r3, #1089	; 0x441
     bee:	4a3b      	ldr	r2, [pc, #236]	; (cdc <cbprintf_package_convert+0x460>)
     bf0:	483b      	ldr	r0, [pc, #236]	; (ce0 <cbprintf_package_convert+0x464>)
     bf2:	f008 fb58 	bl	92a6 <assert_print>
     bf6:	f240 4141 	movw	r1, #1089	; 0x441
     bfa:	e653      	b.n	8a4 <cbprintf_package_convert+0x28>
				keep_str_pos[keep_cnt++] = arg_pos;
     bfc:	f108 0328 	add.w	r3, r8, #40	; 0x28
     c00:	f107 0128 	add.w	r1, r7, #40	; 0x28
     c04:	f108 0201 	add.w	r2, r8, #1
     c08:	eb03 0801 	add.w	r8, r3, r1
     c0c:	f808 5c10 	strb.w	r5, [r8, #-16]
     c10:	fa5f f882 	uxtb.w	r8, r2
     c14:	e734      	b.n	a80 <cbprintf_package_convert+0x204>
				cpy_str_pos[scpy_cnt++] = arg_pos;
     c16:	f106 0328 	add.w	r3, r6, #40	; 0x28
     c1a:	f107 0128 	add.w	r1, r7, #40	; 0x28
     c1e:	1c72      	adds	r2, r6, #1
     c20:	185e      	adds	r6, r3, r1
     c22:	f806 5c20 	strb.w	r5, [r6, #-32]
     c26:	b2d6      	uxtb	r6, r2
     c28:	e72a      	b.n	a80 <cbprintf_package_convert+0x204>
				__ASSERT_NO_MSG(keep_cnt < sizeof(keep_str_pos));
     c2a:	f1b8 0f0f 	cmp.w	r8, #15
     c2e:	d909      	bls.n	c44 <cbprintf_package_convert+0x3c8>
     c30:	492c      	ldr	r1, [pc, #176]	; (ce4 <cbprintf_package_convert+0x468>)
     c32:	f240 434b 	movw	r3, #1099	; 0x44b
     c36:	4a29      	ldr	r2, [pc, #164]	; (cdc <cbprintf_package_convert+0x460>)
     c38:	4829      	ldr	r0, [pc, #164]	; (ce0 <cbprintf_package_convert+0x464>)
     c3a:	f008 fb34 	bl	92a6 <assert_print>
     c3e:	f240 414b 	movw	r1, #1099	; 0x44b
     c42:	e62f      	b.n	8a4 <cbprintf_package_convert+0x28>
				keep_str_pos[keep_cnt++] = arg_idx;
     c44:	f108 0328 	add.w	r3, r8, #40	; 0x28
     c48:	f107 0028 	add.w	r0, r7, #40	; 0x28
     c4c:	f108 0201 	add.w	r2, r8, #1
     c50:	1818      	adds	r0, r3, r0
				keep_str_pos[keep_cnt++] = arg_pos;
     c52:	f107 0350 	add.w	r3, r7, #80	; 0x50
     c56:	f108 0802 	add.w	r8, r8, #2
     c5a:	fa53 f282 	uxtab	r2, r3, r2
				keep_str_pos[keep_cnt++] = arg_idx;
     c5e:	f800 1c10 	strb.w	r1, [r0, #-16]
				keep_str_pos[keep_cnt++] = arg_pos;
     c62:	fa5f f888 	uxtb.w	r8, r8
     c66:	f802 5c10 	strb.w	r5, [r2, #-16]
	for (int i = 0; i < rws_nbr; i++) {
     c6a:	e709      	b.n	a80 <cbprintf_package_convert+0x204>
	out_desc.ro_str_cnt = (flags & CBPRINTF_PACKAGE_CONVERT_RO_STR) ? 0 :
     c6c:	2000      	movs	r0, #0
     c6e:	e720      	b.n	ab2 <cbprintf_package_convert+0x236>
		uint8_t loc = cpy_str_pos[i];
     c70:	f81b 300a 	ldrb.w	r3, [fp, sl]
		const char *str = *(const char **)&buf32[loc];
     c74:	f854 9023 	ldr.w	r9, [r4, r3, lsl #2]
		uint8_t loc = cpy_str_pos[i];
     c78:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
		uint16_t str_len = strl ? strl[i] : 0;
     c7c:	6ffb      	ldr	r3, [r7, #124]	; 0x7c
     c7e:	b1fb      	cbz	r3, cc0 <cbprintf_package_convert+0x444>
     c80:	f833 801b 	ldrh.w	r8, [r3, fp, lsl #1]
		rv = cb(&loc, 1, ctx);
     c84:	2101      	movs	r1, #1
     c86:	69ba      	ldr	r2, [r7, #24]
     c88:	6a7b      	ldr	r3, [r7, #36]	; 0x24
     c8a:	f107 002f 	add.w	r0, r7, #47	; 0x2f
     c8e:	4798      	blx	r3
		if (rv < 0) {
     c90:	2800      	cmp	r0, #0
     c92:	db1a      	blt.n	cca <cbprintf_package_convert+0x44e>
		out_len += rv;
     c94:	4405      	add	r5, r0
	strl = strl > 0 ? strl : strlen(str) + 1;
     c96:	f1b8 0f00 	cmp.w	r8, #0
     c9a:	d106      	bne.n	caa <cbprintf_package_convert+0x42e>
     c9c:	4648      	mov	r0, r9
     c9e:	f008 fca7 	bl	95f0 <strlen>
     ca2:	f100 0801 	add.w	r8, r0, #1
     ca6:	fa1f f888 	uxth.w	r8, r8
	return cb(str, strl, ctx);
     caa:	4641      	mov	r1, r8
     cac:	4648      	mov	r0, r9
     cae:	69ba      	ldr	r2, [r7, #24]
     cb0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
     cb2:	4798      	blx	r3
		if (rv < 0) {
     cb4:	2800      	cmp	r0, #0
     cb6:	db08      	blt.n	cca <cbprintf_package_convert+0x44e>
		out_len += rv;
     cb8:	4405      	add	r5, r0
	for (int i = 0; i < scpy_cnt; i++) {
     cba:	f10b 0b01 	add.w	fp, fp, #1
     cbe:	e72f      	b.n	b20 <cbprintf_package_convert+0x2a4>
		uint16_t str_len = strl ? strl[i] : 0;
     cc0:	f8d7 807c 	ldr.w	r8, [r7, #124]	; 0x7c
     cc4:	e7de      	b.n	c84 <cbprintf_package_convert+0x408>
     cc6:	4645      	mov	r5, r8
     cc8:	e613      	b.n	8f2 <cbprintf_package_convert+0x76>
     cca:	4605      	mov	r5, r0
     ccc:	e611      	b.n	8f2 <cbprintf_package_convert+0x76>
     cce:	bf00      	nop
     cd0:	00009c5c 	.word	0x00009c5c
     cd4:	0000bd24 	.word	0x0000bd24
     cd8:	0000a42a 	.word	0x0000a42a
     cdc:	0000a2ba 	.word	0x0000a2ba
     ce0:	0000a2e8 	.word	0x0000a2e8
     ce4:	0000a449 	.word	0x0000a449

00000ce8 <__printk_hook_install>:
 * routine that outputs one ASCII character at a time.
 * @param fn putc routine to install
 */
void __printk_hook_install(int (*fn)(int c))
{
	_char_out = fn;
     ce8:	4b01      	ldr	r3, [pc, #4]	; (cf0 <__printk_hook_install+0x8>)
     cea:	6018      	str	r0, [r3, #0]
}
     cec:	4770      	bx	lr
     cee:	bf00      	nop
     cf0:	20000000 	.word	0x20000000

00000cf4 <vsnprintk>:

	return ret;
}

int vsnprintk(char *str, size_t size, const char *fmt, va_list ap)
{
     cf4:	b530      	push	{r4, r5, lr}
	struct str_context ctx = { str, size, 0 };
     cf6:	2500      	movs	r5, #0
{
     cf8:	b087      	sub	sp, #28
	struct str_context ctx = { str, size, 0 };
     cfa:	e9cd 0103 	strd	r0, r1, [sp, #12]
{
     cfe:	4604      	mov	r4, r0
int cbvprintf(cbprintf_cb out, void *ctx, const char *format, va_list ap);
#else
static inline
int cbvprintf(cbprintf_cb out, void *ctx, const char *format, va_list ap)
{
	return z_cbvprintf_impl(out, ctx, format, ap, 0);
     d00:	9500      	str	r5, [sp, #0]
     d02:	a903      	add	r1, sp, #12
     d04:	4805      	ldr	r0, [pc, #20]	; (d1c <vsnprintk+0x28>)
	struct str_context ctx = { str, size, 0 };
     d06:	9505      	str	r5, [sp, #20]
     d08:	f000 fac8 	bl	129c <z_cbvprintf_impl>

	cbvprintf(str_out, &ctx, fmt, ap);

	if (ctx.count < ctx.max) {
     d0c:	e9dd 3004 	ldrd	r3, r0, [sp, #16]
     d10:	4298      	cmp	r0, r3
		str[ctx.count] = '\0';
     d12:	bfb8      	it	lt
     d14:	5425      	strblt	r5, [r4, r0]
	}

	return ctx.count;
}
     d16:	b007      	add	sp, #28
     d18:	bd30      	pop	{r4, r5, pc}
     d1a:	bf00      	nop
     d1c:	000090a1 	.word	0x000090a1

00000d20 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     d20:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
     d24:	4604      	mov	r4, r0
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     d26:	8ba3      	ldrh	r3, [r4, #28]
{
     d28:	4608      	mov	r0, r1
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     d2a:	0719      	lsls	r1, r3, #28
{
     d2c:	4615      	mov	r5, r2
	if (processing) {
     d2e:	d412      	bmi.n	d56 <process_event+0x36>

	sys_slist_init(&clients);
	do {
		onoff_transition_fn transit = NULL;

		if (evt == EVT_RECHECK) {
     d30:	2802      	cmp	r0, #2
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     d32:	f003 0107 	and.w	r1, r3, #7
		if (evt == EVT_RECHECK) {
     d36:	d164      	bne.n	e02 <process_event+0xe2>
			evt = process_recheck(mgr);
     d38:	4620      	mov	r0, r4
     d3a:	f008 f9ea 	bl	9112 <process_recheck>
		}

		if (evt == EVT_NOP) {
     d3e:	b188      	cbz	r0, d64 <process_event+0x44>
			break;
		}

		res = 0;
		if (evt == EVT_COMPLETE) {
     d40:	3801      	subs	r0, #1
     d42:	2804      	cmp	r0, #4
     d44:	f200 8134 	bhi.w	fb0 <process_event+0x290>
     d48:	e8df f010 	tbh	[pc, r0, lsl #1]
     d4c:	0132005b 	.word	0x0132005b
     d50:	00d10081 	.word	0x00d10081
     d54:	0101      	.short	0x0101
		if (evt == EVT_COMPLETE) {
     d56:	2801      	cmp	r0, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     d58:	bf0c      	ite	eq
     d5a:	f043 0110 	orreq.w	r1, r3, #16
			mgr->flags |= ONOFF_FLAG_RECHECK;
     d5e:	f043 0120 	orrne.w	r1, r3, #32
     d62:	83a1      	strh	r1, [r4, #28]

		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
     d64:	3414      	adds	r4, #20
static ALWAYS_INLINE void k_spin_unlock(struct k_spinlock *l,
					k_spinlock_key_t key)
{
	ARG_UNUSED(l);
#ifdef CONFIG_SPIN_VALIDATE
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
     d66:	4620      	mov	r0, r4
     d68:	f006 f83e 	bl	6de8 <z_spin_unlock_valid>
     d6c:	2800      	cmp	r0, #0
     d6e:	f040 819b 	bne.w	10a8 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0xa8>
     d72:	4998      	ldr	r1, [pc, #608]	; (fd4 <process_event+0x2b4>)
     d74:	23c2      	movs	r3, #194	; 0xc2
     d76:	4a98      	ldr	r2, [pc, #608]	; (fd8 <process_event+0x2b8>)
     d78:	4898      	ldr	r0, [pc, #608]	; (fdc <process_event+0x2bc>)
     d7a:	f008 fa94 	bl	92a6 <assert_print>
     d7e:	4621      	mov	r1, r4
     d80:	e0b0      	b.n	ee4 <process_event+0x1c4>
     d82:	f003 0207 	and.w	r2, r3, #7
		   || (state == ONOFF_STATE_RESETTING)) {
     d86:	1f50      	subs	r0, r2, #5
	} else if ((state == ONOFF_STATE_TO_ON)
     d88:	2801      	cmp	r0, #1
     d8a:	d81e      	bhi.n	dca <process_event+0xaa>
 *
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
     d8c:	2000      	movs	r0, #0
		if (state == ONOFF_STATE_TO_ON) {
     d8e:	2a06      	cmp	r2, #6
		*clients = mgr->clients;
     d90:	6827      	ldr	r7, [r4, #0]
	list->tail = NULL;
     d92:	e9c4 0000 	strd	r0, r0, [r4]
		if (state == ONOFF_STATE_TO_ON) {
     d96:	d114      	bne.n	dc2 <process_event+0xa2>
		*clients = mgr->clients;
     d98:	463a      	mov	r2, r7
     d9a:	e003      	b.n	da4 <process_event+0x84>
				mgr->refs += 1U;
     d9c:	8be0      	ldrh	r0, [r4, #30]
     d9e:	3001      	adds	r0, #1
     da0:	83e0      	strh	r0, [r4, #30]

#define SYS_SLIST_STATIC_INIT(ptr_to_list) {NULL, NULL}

static inline sys_snode_t *z_snode_next_peek(sys_snode_t *node)
{
	return node->next;
     da2:	6812      	ldr	r2, [r2, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     da4:	2a00      	cmp	r2, #0
     da6:	d1f9      	bne.n	d9c <process_event+0x7c>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     da8:	f023 0307 	bic.w	r3, r3, #7
     dac:	f043 0202 	orr.w	r2, r3, #2
		if (process_recheck(mgr) != EVT_NOP) {
     db0:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     db2:	83a2      	strh	r2, [r4, #28]
		if (process_recheck(mgr) != EVT_NOP) {
     db4:	f008 f9ad 	bl	9112 <process_recheck>
     db8:	b390      	cbz	r0, e20 <process_event+0x100>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     dba:	f042 0220 	orr.w	r2, r2, #32
     dbe:	83a2      	strh	r2, [r4, #28]
     dc0:	e02e      	b.n	e20 <process_event+0x100>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     dc2:	f023 0307 	bic.w	r3, r3, #7
     dc6:	b29a      	uxth	r2, r3
}
     dc8:	e7f2      	b.n	db0 <process_event+0x90>
	} else if (state == ONOFF_STATE_TO_OFF) {
     dca:	2a04      	cmp	r2, #4
     dcc:	d133      	bne.n	e36 <process_event+0x116>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     dce:	f023 0307 	bic.w	r3, r3, #7
     dd2:	b29a      	uxth	r2, r3
		if (process_recheck(mgr) != EVT_NOP) {
     dd4:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     dd6:	83a2      	strh	r2, [r4, #28]
		if (process_recheck(mgr) != EVT_NOP) {
     dd8:	f008 f99b 	bl	9112 <process_recheck>
     ddc:	b110      	cbz	r0, de4 <process_event+0xc4>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     dde:	f042 0220 	orr.w	r2, r2, #32
     de2:	83a2      	strh	r2, [r4, #28]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     de4:	8ba3      	ldrh	r3, [r4, #28]
     de6:	f003 0907 	and.w	r9, r3, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     dea:	4589      	cmp	r9, r1
     dec:	f040 80ea 	bne.w	fc4 <process_event+0x2a4>
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     df0:	8ba1      	ldrh	r1, [r4, #28]
     df2:	06ca      	lsls	r2, r1, #27
     df4:	f140 814f 	bpl.w	1096 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x96>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     df8:	f021 0310 	bic.w	r3, r1, #16
     dfc:	83a3      	strh	r3, [r4, #28]
		state = mgr->flags & ONOFF_STATE_MASK;
     dfe:	f001 0107 	and.w	r1, r1, #7
			res = mgr->last_res;
     e02:	f8d4 8018 	ldr.w	r8, [r4, #24]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     e06:	8ba3      	ldrh	r3, [r4, #28]
	if (res < 0) {
     e08:	f1b8 0f00 	cmp.w	r8, #0
     e0c:	dab9      	bge.n	d82 <process_event+0x62>
	list->head = NULL;
     e0e:	2200      	movs	r2, #0
		*clients = mgr->clients;
     e10:	6827      	ldr	r7, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     e12:	f023 0307 	bic.w	r3, r3, #7
	list->tail = NULL;
     e16:	e9c4 2200 	strd	r2, r2, [r4]
     e1a:	f043 0301 	orr.w	r3, r3, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
     e1e:	83a3      	strh	r3, [r4, #28]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     e20:	8ba3      	ldrh	r3, [r4, #28]
     e22:	f003 0907 	and.w	r9, r3, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     e26:	4589      	cmp	r9, r1
     e28:	f040 80cd 	bne.w	fc6 <process_event+0x2a6>
		    || !sys_slist_is_empty(&clients)
     e2c:	2f00      	cmp	r7, #0
     e2e:	d0df      	beq.n	df0 <process_event+0xd0>
     e30:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     e32:	46b2      	mov	sl, r6
     e34:	e044      	b.n	ec0 <process_event+0x1a0>
		__ASSERT_NO_MSG(false);
     e36:	496a      	ldr	r1, [pc, #424]	; (fe0 <process_event+0x2c0>)
     e38:	f240 131b 	movw	r3, #283	; 0x11b
     e3c:	4a69      	ldr	r2, [pc, #420]	; (fe4 <process_event+0x2c4>)
     e3e:	4867      	ldr	r0, [pc, #412]	; (fdc <process_event+0x2bc>)
     e40:	f008 fa31 	bl	92a6 <assert_print>
     e44:	f240 111b 	movw	r1, #283	; 0x11b
			__ASSERT_NO_MSG(state == ONOFF_STATE_OFF);
     e48:	4866      	ldr	r0, [pc, #408]	; (fe4 <process_event+0x2c4>)
     e4a:	f008 fa25 	bl	9298 <assert_post_action>
     e4e:	b149      	cbz	r1, e64 <process_event+0x144>
     e50:	4965      	ldr	r1, [pc, #404]	; (fe8 <process_event+0x2c8>)
     e52:	f44f 73ab 	mov.w	r3, #342	; 0x156
     e56:	4a63      	ldr	r2, [pc, #396]	; (fe4 <process_event+0x2c4>)
     e58:	4860      	ldr	r0, [pc, #384]	; (fdc <process_event+0x2bc>)
     e5a:	f008 fa24 	bl	92a6 <assert_print>
     e5e:	f44f 71ab 	mov.w	r1, #342	; 0x156
     e62:	e7f1      	b.n	e48 <process_event+0x128>
			__ASSERT_NO_MSG(!sys_slist_is_empty(&mgr->clients));
     e64:	6823      	ldr	r3, [r4, #0]
     e66:	b94b      	cbnz	r3, e7c <process_event+0x15c>
     e68:	4960      	ldr	r1, [pc, #384]	; (fec <process_event+0x2cc>)
     e6a:	f240 1357 	movw	r3, #343	; 0x157
     e6e:	4a5d      	ldr	r2, [pc, #372]	; (fe4 <process_event+0x2c4>)
     e70:	485a      	ldr	r0, [pc, #360]	; (fdc <process_event+0x2bc>)
     e72:	f008 fa18 	bl	92a6 <assert_print>
     e76:	f240 1157 	movw	r1, #343	; 0x157
     e7a:	e7e5      	b.n	e48 <process_event+0x128>
			transit = mgr->transitions->start;
     e7c:	6923      	ldr	r3, [r4, #16]
     e7e:	681e      	ldr	r6, [r3, #0]
			__ASSERT_NO_MSG(transit != NULL);
     e80:	b94e      	cbnz	r6, e96 <process_event+0x176>
     e82:	495b      	ldr	r1, [pc, #364]	; (ff0 <process_event+0x2d0>)
     e84:	f44f 73ad 	mov.w	r3, #346	; 0x15a
     e88:	4a56      	ldr	r2, [pc, #344]	; (fe4 <process_event+0x2c4>)
     e8a:	4854      	ldr	r0, [pc, #336]	; (fdc <process_event+0x2bc>)
     e8c:	f008 fa0b 	bl	92a6 <assert_print>
     e90:	f44f 71ad 	mov.w	r1, #346	; 0x15a
     e94:	e7d8      	b.n	e48 <process_event+0x128>
	mgr->flags = (state & ONOFF_STATE_MASK)
     e96:	460f      	mov	r7, r1
		res = 0;
     e98:	4688      	mov	r8, r1
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     e9a:	f04f 0906 	mov.w	r9, #6
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     e9e:	8ba3      	ldrh	r3, [r4, #28]
     ea0:	f023 0307 	bic.w	r3, r3, #7
     ea4:	f043 0306 	orr.w	r3, r3, #6
     ea8:	b29b      	uxth	r3, r3
	mgr->flags = (state & ONOFF_STATE_MASK)
     eaa:	83a3      	strh	r3, [r4, #28]
				   && !sys_slist_is_empty(&mgr->monitors);
     eac:	68a2      	ldr	r2, [r4, #8]
     eae:	2a00      	cmp	r2, #0
     eb0:	f040 808b 	bne.w	fca <process_event+0x2aa>
		    || !sys_slist_is_empty(&clients)
     eb4:	2f00      	cmp	r7, #0
     eb6:	f040 808b 	bne.w	fd0 <process_event+0x2b0>
		    || (transit != NULL)) {
     eba:	2e00      	cmp	r6, #0
     ebc:	d098      	beq.n	df0 <process_event+0xd0>
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     ebe:	46ba      	mov	sl, r7
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     ec0:	f043 0308 	orr.w	r3, r3, #8
			k_spin_unlock(&mgr->lock, key);
     ec4:	f104 0b14 	add.w	fp, r4, #20
     ec8:	4658      	mov	r0, fp
			mgr->flags = flags;
     eca:	83a3      	strh	r3, [r4, #28]
     ecc:	f005 ff8c 	bl	6de8 <z_spin_unlock_valid>
     ed0:	2800      	cmp	r0, #0
     ed2:	f040 8097 	bne.w	1004 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x4>
     ed6:	493f      	ldr	r1, [pc, #252]	; (fd4 <process_event+0x2b4>)
     ed8:	23c2      	movs	r3, #194	; 0xc2
     eda:	4a3f      	ldr	r2, [pc, #252]	; (fd8 <process_event+0x2b8>)
     edc:	483f      	ldr	r0, [pc, #252]	; (fdc <process_event+0x2bc>)
     ede:	f008 f9e2 	bl	92a6 <assert_print>
     ee2:	4659      	mov	r1, fp
     ee4:	4843      	ldr	r0, [pc, #268]	; (ff4 <process_event+0x2d4>)
     ee6:	f008 f9de 	bl	92a6 <assert_print>
     eea:	21c2      	movs	r1, #194	; 0xc2
     eec:	e0ae      	b.n	104c <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x4c>
			__ASSERT_NO_MSG(state == ONOFF_STATE_ON);
     eee:	2902      	cmp	r1, #2
     ef0:	d009      	beq.n	f06 <process_event+0x1e6>
     ef2:	4941      	ldr	r1, [pc, #260]	; (ff8 <process_event+0x2d8>)
     ef4:	f240 135d 	movw	r3, #349	; 0x15d
     ef8:	4a3a      	ldr	r2, [pc, #232]	; (fe4 <process_event+0x2c4>)
     efa:	4838      	ldr	r0, [pc, #224]	; (fdc <process_event+0x2bc>)
     efc:	f008 f9d3 	bl	92a6 <assert_print>
     f00:	f240 115d 	movw	r1, #349	; 0x15d
     f04:	e7a0      	b.n	e48 <process_event+0x128>
			__ASSERT_NO_MSG(mgr->refs == 0);
     f06:	8be7      	ldrh	r7, [r4, #30]
     f08:	b14f      	cbz	r7, f1e <process_event+0x1fe>
     f0a:	493c      	ldr	r1, [pc, #240]	; (ffc <process_event+0x2dc>)
     f0c:	f44f 73af 	mov.w	r3, #350	; 0x15e
     f10:	4a34      	ldr	r2, [pc, #208]	; (fe4 <process_event+0x2c4>)
     f12:	4832      	ldr	r0, [pc, #200]	; (fdc <process_event+0x2bc>)
     f14:	f008 f9c7 	bl	92a6 <assert_print>
     f18:	f44f 71af 	mov.w	r1, #350	; 0x15e
     f1c:	e794      	b.n	e48 <process_event+0x128>
			transit = mgr->transitions->stop;
     f1e:	6923      	ldr	r3, [r4, #16]
     f20:	685e      	ldr	r6, [r3, #4]
			__ASSERT_NO_MSG(transit != NULL);
     f22:	b94e      	cbnz	r6, f38 <process_event+0x218>
     f24:	4932      	ldr	r1, [pc, #200]	; (ff0 <process_event+0x2d0>)
     f26:	f240 1361 	movw	r3, #353	; 0x161
     f2a:	4a2e      	ldr	r2, [pc, #184]	; (fe4 <process_event+0x2c4>)
     f2c:	482b      	ldr	r0, [pc, #172]	; (fdc <process_event+0x2bc>)
     f2e:	f008 f9ba 	bl	92a6 <assert_print>
     f32:	f240 1161 	movw	r1, #353	; 0x161
     f36:	e787      	b.n	e48 <process_event+0x128>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     f38:	8ba3      	ldrh	r3, [r4, #28]
		res = 0;
     f3a:	46b8      	mov	r8, r7
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     f3c:	f023 0307 	bic.w	r3, r3, #7
     f40:	f043 0304 	orr.w	r3, r3, #4
     f44:	b29b      	uxth	r3, r3
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     f46:	f04f 0904 	mov.w	r9, #4
	mgr->flags = (state & ONOFF_STATE_MASK)
     f4a:	83a3      	strh	r3, [r4, #28]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     f4c:	e7ae      	b.n	eac <process_event+0x18c>
			__ASSERT_NO_MSG(state == ONOFF_STATE_ERROR);
     f4e:	2901      	cmp	r1, #1
     f50:	d009      	beq.n	f66 <process_event+0x246>
     f52:	492b      	ldr	r1, [pc, #172]	; (1000 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE>)
     f54:	f44f 73b2 	mov.w	r3, #356	; 0x164
     f58:	4a22      	ldr	r2, [pc, #136]	; (fe4 <process_event+0x2c4>)
     f5a:	4820      	ldr	r0, [pc, #128]	; (fdc <process_event+0x2bc>)
     f5c:	f008 f9a3 	bl	92a6 <assert_print>
     f60:	f44f 71b2 	mov.w	r1, #356	; 0x164
     f64:	e770      	b.n	e48 <process_event+0x128>
			__ASSERT_NO_MSG(!sys_slist_is_empty(&mgr->clients));
     f66:	6823      	ldr	r3, [r4, #0]
     f68:	b94b      	cbnz	r3, f7e <process_event+0x25e>
     f6a:	4920      	ldr	r1, [pc, #128]	; (fec <process_event+0x2cc>)
     f6c:	f240 1365 	movw	r3, #357	; 0x165
     f70:	4a1c      	ldr	r2, [pc, #112]	; (fe4 <process_event+0x2c4>)
     f72:	481a      	ldr	r0, [pc, #104]	; (fdc <process_event+0x2bc>)
     f74:	f008 f997 	bl	92a6 <assert_print>
     f78:	f240 1165 	movw	r1, #357	; 0x165
     f7c:	e764      	b.n	e48 <process_event+0x128>
			transit = mgr->transitions->reset;
     f7e:	6923      	ldr	r3, [r4, #16]
     f80:	689e      	ldr	r6, [r3, #8]
			__ASSERT_NO_MSG(transit != NULL);
     f82:	b94e      	cbnz	r6, f98 <process_event+0x278>
     f84:	491a      	ldr	r1, [pc, #104]	; (ff0 <process_event+0x2d0>)
     f86:	f44f 73b4 	mov.w	r3, #360	; 0x168
     f8a:	4a16      	ldr	r2, [pc, #88]	; (fe4 <process_event+0x2c4>)
     f8c:	4813      	ldr	r0, [pc, #76]	; (fdc <process_event+0x2bc>)
     f8e:	f008 f98a 	bl	92a6 <assert_print>
     f92:	f44f 71b4 	mov.w	r1, #360	; 0x168
     f96:	e757      	b.n	e48 <process_event+0x128>
	mgr->flags = (state & ONOFF_STATE_MASK)
     f98:	2700      	movs	r7, #0
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     f9a:	8ba3      	ldrh	r3, [r4, #28]
		res = 0;
     f9c:	46b8      	mov	r8, r7
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     f9e:	f023 0307 	bic.w	r3, r3, #7
     fa2:	f043 0305 	orr.w	r3, r3, #5
     fa6:	b29b      	uxth	r3, r3
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     fa8:	f04f 0905 	mov.w	r9, #5
	mgr->flags = (state & ONOFF_STATE_MASK)
     fac:	83a3      	strh	r3, [r4, #28]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     fae:	e77d      	b.n	eac <process_event+0x18c>
			__ASSERT_NO_MSG(false);
     fb0:	490b      	ldr	r1, [pc, #44]	; (fe0 <process_event+0x2c0>)
     fb2:	f240 136b 	movw	r3, #363	; 0x16b
     fb6:	4a0b      	ldr	r2, [pc, #44]	; (fe4 <process_event+0x2c4>)
     fb8:	4808      	ldr	r0, [pc, #32]	; (fdc <process_event+0x2bc>)
     fba:	f008 f974 	bl	92a6 <assert_print>
     fbe:	f240 116b 	movw	r1, #363	; 0x16b
     fc2:	e741      	b.n	e48 <process_event+0x128>
				   && !sys_slist_is_empty(&mgr->monitors);
     fc4:	2700      	movs	r7, #0
     fc6:	2600      	movs	r6, #0
     fc8:	e770      	b.n	eac <process_event+0x18c>
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     fca:	f04f 0a01 	mov.w	sl, #1
     fce:	e777      	b.n	ec0 <process_event+0x1a0>
     fd0:	4692      	mov	sl, r2
     fd2:	e775      	b.n	ec0 <process_event+0x1a0>
     fd4:	0000a54a 	.word	0x0000a54a
     fd8:	0000a51d 	.word	0x0000a51d
     fdc:	0000a2e8 	.word	0x0000a2e8
     fe0:	0000a5f9 	.word	0x0000a5f9
     fe4:	0000a47a 	.word	0x0000a47a
     fe8:	0000a49c 	.word	0x0000a49c
     fec:	0000a4a8 	.word	0x0000a4a8
     ff0:	0000a4cb 	.word	0x0000a4cb
     ff4:	0000a561 	.word	0x0000a561
     ff8:	0000a4e2 	.word	0x0000a4e2
     ffc:	0000a4f8 	.word	0x0000a4f8
    1000:	0000a507 	.word	0x0000a507
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
    1004:	f385 8811 	msr	BASEPRI, r5
    1008:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
    100c:	f1ba 0f00 	cmp.w	sl, #0
    1010:	d11e      	bne.n	1050 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x50>
	while (!sys_slist_is_empty(list)) {
    1012:	2f00      	cmp	r7, #0
    1014:	d12f      	bne.n	1076 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x76>
			if (transit != NULL) {
    1016:	b116      	cbz	r6, 101e <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x1e>
				transit(mgr, transition_complete);
    1018:	4620      	mov	r0, r4
    101a:	4926      	ldr	r1, [pc, #152]	; (10b4 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0xb4>)
    101c:	47b0      	blx	r6
	__asm__ volatile(
    101e:	f04f 0320 	mov.w	r3, #32
    1022:	f3ef 8511 	mrs	r5, BASEPRI
    1026:	f383 8812 	msr	BASEPRI_MAX, r3
    102a:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    102e:	4658      	mov	r0, fp
    1030:	f005 fecc 	bl	6dcc <z_spin_lock_valid>
    1034:	bb38      	cbnz	r0, 1086 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x86>
    1036:	2394      	movs	r3, #148	; 0x94
    1038:	4a1f      	ldr	r2, [pc, #124]	; (10b8 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0xb8>)
    103a:	4920      	ldr	r1, [pc, #128]	; (10bc <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0xbc>)
    103c:	4820      	ldr	r0, [pc, #128]	; (10c0 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0xc0>)
    103e:	f008 f932 	bl	92a6 <assert_print>
    1042:	4659      	mov	r1, fp
    1044:	481f      	ldr	r0, [pc, #124]	; (10c4 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0xc4>)
    1046:	f008 f92e 	bl	92a6 <assert_print>
    104a:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    104c:	481a      	ldr	r0, [pc, #104]	; (10b8 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0xb8>)
    104e:	e6fc      	b.n	e4a <process_event+0x12a>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
    1050:	68a1      	ldr	r1, [r4, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    1052:	2900      	cmp	r1, #0
    1054:	d0dd      	beq.n	1012 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x12>
	return node->next;
    1056:	680d      	ldr	r5, [r1, #0]
    1058:	2900      	cmp	r1, #0
    105a:	d0da      	beq.n	1012 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x12>
		mon->callback(mgr, mon, state, res);
    105c:	4643      	mov	r3, r8
    105e:	464a      	mov	r2, r9
    1060:	4620      	mov	r0, r4
    1062:	f8d1 a004 	ldr.w	sl, [r1, #4]
    1066:	47d0      	blx	sl
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    1068:	b11d      	cbz	r5, 1072 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x72>
    106a:	682b      	ldr	r3, [r5, #0]
    106c:	4629      	mov	r1, r5
    106e:	461d      	mov	r5, r3
    1070:	e7f2      	b.n	1058 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x58>
    1072:	462b      	mov	r3, r5
    1074:	e7fa      	b.n	106c <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x6c>
    1076:	4639      	mov	r1, r7
		notify_one(mgr, cli, state, res);
    1078:	4643      	mov	r3, r8
    107a:	464a      	mov	r2, r9
    107c:	4620      	mov	r0, r4
    107e:	683f      	ldr	r7, [r7, #0]
    1080:	f008 f873 	bl	916a <notify_one>
    1084:	e7c5      	b.n	1012 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x12>
	z_spin_lock_set_owner(l);
    1086:	4658      	mov	r0, fp
    1088:	f005 febc 	bl	6e04 <z_spin_lock_set_owner>
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
    108c:	8ba3      	ldrh	r3, [r4, #28]
    108e:	f023 0308 	bic.w	r3, r3, #8
    1092:	83a3      	strh	r3, [r4, #28]
    1094:	e6ac      	b.n	df0 <process_event+0xd0>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
    1096:	068b      	lsls	r3, r1, #26
    1098:	f57f ae64 	bpl.w	d64 <process_event+0x44>
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
    109c:	f021 0320 	bic.w	r3, r1, #32
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
    10a0:	83a3      	strh	r3, [r4, #28]
		state = mgr->flags & ONOFF_STATE_MASK;
    10a2:	f001 0107 	and.w	r1, r1, #7
		if (evt == EVT_RECHECK) {
    10a6:	e647      	b.n	d38 <process_event+0x18>
	__asm__ volatile(
    10a8:	f385 8811 	msr	BASEPRI, r5
    10ac:	f3bf 8f6f 	isb	sy
}
    10b0:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
    10b4:	000010c9 	.word	0x000010c9
    10b8:	0000a51d 	.word	0x0000a51d
    10bc:	0000a576 	.word	0x0000a576
    10c0:	0000a2e8 	.word	0x0000a2e8
    10c4:	0000a58b 	.word	0x0000a58b

000010c8 <transition_complete>:
{
    10c8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    10ca:	4604      	mov	r4, r0
    10cc:	460d      	mov	r5, r1
	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
    10ce:	f100 0614 	add.w	r6, r0, #20
	__asm__ volatile(
    10d2:	f04f 0320 	mov.w	r3, #32
    10d6:	f3ef 8711 	mrs	r7, BASEPRI
    10da:	f383 8812 	msr	BASEPRI_MAX, r3
    10de:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    10e2:	4630      	mov	r0, r6
    10e4:	f005 fe72 	bl	6dcc <z_spin_lock_valid>
    10e8:	b968      	cbnz	r0, 1106 <transition_complete+0x3e>
    10ea:	2394      	movs	r3, #148	; 0x94
    10ec:	4a0b      	ldr	r2, [pc, #44]	; (111c <transition_complete+0x54>)
    10ee:	490c      	ldr	r1, [pc, #48]	; (1120 <transition_complete+0x58>)
    10f0:	480c      	ldr	r0, [pc, #48]	; (1124 <transition_complete+0x5c>)
    10f2:	f008 f8d8 	bl	92a6 <assert_print>
    10f6:	4631      	mov	r1, r6
    10f8:	480b      	ldr	r0, [pc, #44]	; (1128 <transition_complete+0x60>)
    10fa:	f008 f8d4 	bl	92a6 <assert_print>
    10fe:	2194      	movs	r1, #148	; 0x94
    1100:	4806      	ldr	r0, [pc, #24]	; (111c <transition_complete+0x54>)
    1102:	f008 f8c9 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    1106:	4630      	mov	r0, r6
    1108:	f005 fe7c 	bl	6e04 <z_spin_lock_set_owner>
	mgr->last_res = res;
    110c:	61a5      	str	r5, [r4, #24]
	process_event(mgr, EVT_COMPLETE, key);
    110e:	463a      	mov	r2, r7
    1110:	4620      	mov	r0, r4
}
    1112:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
	process_event(mgr, EVT_COMPLETE, key);
    1116:	2101      	movs	r1, #1
    1118:	f7ff be02 	b.w	d20 <process_event>
    111c:	0000a51d 	.word	0x0000a51d
    1120:	0000a576 	.word	0x0000a576
    1124:	0000a2e8 	.word	0x0000a2e8
    1128:	0000a58b 	.word	0x0000a58b

0000112c <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    112c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    1130:	4604      	mov	r4, r0
    1132:	460f      	mov	r7, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    1134:	f008 f809 	bl	914a <validate_args>

	if (rv < 0) {
    1138:	1e05      	subs	r5, r0, #0
    113a:	db67      	blt.n	120c <onoff_request+0xe0>
		return rv;
	}

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
    113c:	f104 0914 	add.w	r9, r4, #20
    1140:	f04f 0320 	mov.w	r3, #32
    1144:	f3ef 8a11 	mrs	sl, BASEPRI
    1148:	f383 8812 	msr	BASEPRI_MAX, r3
    114c:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    1150:	4648      	mov	r0, r9
    1152:	f005 fe3b 	bl	6dcc <z_spin_lock_valid>
    1156:	4680      	mov	r8, r0
    1158:	b960      	cbnz	r0, 1174 <onoff_request+0x48>
    115a:	2394      	movs	r3, #148	; 0x94
    115c:	4a37      	ldr	r2, [pc, #220]	; (123c <onoff_request+0x110>)
    115e:	4938      	ldr	r1, [pc, #224]	; (1240 <onoff_request+0x114>)
    1160:	4838      	ldr	r0, [pc, #224]	; (1244 <onoff_request+0x118>)
    1162:	f008 f8a0 	bl	92a6 <assert_print>
    1166:	4649      	mov	r1, r9
    1168:	4837      	ldr	r0, [pc, #220]	; (1248 <onoff_request+0x11c>)
    116a:	f008 f89c 	bl	92a6 <assert_print>
    116e:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    1170:	4832      	ldr	r0, [pc, #200]	; (123c <onoff_request+0x110>)
    1172:	e040      	b.n	11f6 <onoff_request+0xca>
	z_spin_lock_set_owner(l);
    1174:	4648      	mov	r0, r9
    1176:	f005 fe45 	bl	6e04 <z_spin_lock_set_owner>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    117a:	f64f 72ff 	movw	r2, #65535	; 0xffff
    117e:	8be3      	ldrh	r3, [r4, #30]
    1180:	8ba6      	ldrh	r6, [r4, #28]
    1182:	4293      	cmp	r3, r2
    1184:	f006 0607 	and.w	r6, r6, #7
    1188:	d043      	beq.n	1212 <onoff_request+0xe6>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
    118a:	2e02      	cmp	r6, #2
    118c:	d113      	bne.n	11b6 <onoff_request+0x8a>
	rv = state;
    118e:	4635      	mov	r5, r6
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
    1190:	3301      	adds	r3, #1
    1192:	83e3      	strh	r3, [r4, #30]
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    1194:	4648      	mov	r0, r9
    1196:	f005 fe27 	bl	6de8 <z_spin_unlock_valid>
    119a:	2800      	cmp	r0, #0
    119c:	d13f      	bne.n	121e <onoff_request+0xf2>
    119e:	23c2      	movs	r3, #194	; 0xc2
    11a0:	4a26      	ldr	r2, [pc, #152]	; (123c <onoff_request+0x110>)
    11a2:	492a      	ldr	r1, [pc, #168]	; (124c <onoff_request+0x120>)
    11a4:	4827      	ldr	r0, [pc, #156]	; (1244 <onoff_request+0x118>)
    11a6:	f008 f87e 	bl	92a6 <assert_print>
    11aa:	4649      	mov	r1, r9
    11ac:	4828      	ldr	r0, [pc, #160]	; (1250 <onoff_request+0x124>)
    11ae:	f008 f87a 	bl	92a6 <assert_print>
    11b2:	21c2      	movs	r1, #194	; 0xc2
    11b4:	e7dc      	b.n	1170 <onoff_request+0x44>
	} else if ((state == ONOFF_STATE_OFF)
    11b6:	2e06      	cmp	r6, #6
    11b8:	d813      	bhi.n	11e2 <onoff_request+0xb6>
    11ba:	e8df f006 	tbb	[pc, r6]
    11be:	2d09      	.short	0x2d09
    11c0:	04091212 	.word	0x04091212
    11c4:	09          	.byte	0x09
    11c5:	00          	.byte	0x00
	if (state == ONOFF_STATE_ON) {
    11c6:	f06f 0585 	mvn.w	r5, #133	; 0x85
    11ca:	f04f 0800 	mov.w	r8, #0
    11ce:	e7e1      	b.n	1194 <onoff_request+0x68>
	parent->next = child;
    11d0:	2300      	movs	r3, #0
    11d2:	603b      	str	r3, [r7, #0]
 *
 * @return A pointer on the last node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_tail(sys_slist_t *list)
{
	return list->tail;
    11d4:	6863      	ldr	r3, [r4, #4]
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
				    sys_snode_t *node);

Z_GENLIST_APPEND(slist, snode)
    11d6:	b983      	cbnz	r3, 11fa <onoff_request+0xce>
	list->head = node;
    11d8:	e9c4 7700 	strd	r7, r7, [r4]
out:
	if (add_client) {
		sys_slist_append(&mgr->clients, &cli->node);
	}

	if (start) {
    11dc:	b186      	cbz	r6, 1200 <onoff_request+0xd4>
	rv = state;
    11de:	4635      	mov	r5, r6
    11e0:	e7f3      	b.n	11ca <onoff_request+0x9e>
		__ASSERT_NO_MSG(state == ONOFF_STATE_ERROR);
    11e2:	491c      	ldr	r1, [pc, #112]	; (1254 <onoff_request+0x128>)
    11e4:	4817      	ldr	r0, [pc, #92]	; (1244 <onoff_request+0x118>)
    11e6:	f44f 73e4 	mov.w	r3, #456	; 0x1c8
    11ea:	4a1b      	ldr	r2, [pc, #108]	; (1258 <onoff_request+0x12c>)
    11ec:	f008 f85b 	bl	92a6 <assert_print>
    11f0:	f44f 71e4 	mov.w	r1, #456	; 0x1c8
    11f4:	4818      	ldr	r0, [pc, #96]	; (1258 <onoff_request+0x12c>)
    11f6:	f008 f84f 	bl	9298 <assert_post_action>
	parent->next = child;
    11fa:	601f      	str	r7, [r3, #0]
	list->tail = node;
    11fc:	6067      	str	r7, [r4, #4]
}
    11fe:	e7ed      	b.n	11dc <onoff_request+0xb0>
		process_event(mgr, EVT_RECHECK, key);
    1200:	4652      	mov	r2, sl
    1202:	2102      	movs	r1, #2
    1204:	4620      	mov	r0, r4
    1206:	f7ff fd8b 	bl	d20 <process_event>
    120a:	4635      	mov	r5, r6
			notify_one(mgr, cli, state, 0);
		}
	}

	return rv;
}
    120c:	4628      	mov	r0, r5
    120e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		rv = -EAGAIN;
    1212:	f06f 050a 	mvn.w	r5, #10
    1216:	e7d8      	b.n	11ca <onoff_request+0x9e>
	if (state == ONOFF_STATE_ON) {
    1218:	f06f 0504 	mvn.w	r5, #4
    121c:	e7d5      	b.n	11ca <onoff_request+0x9e>
	__asm__ volatile(
    121e:	f38a 8811 	msr	BASEPRI, sl
    1222:	f3bf 8f6f 	isb	sy
		if (notify) {
    1226:	f1b8 0f00 	cmp.w	r8, #0
    122a:	d0ef      	beq.n	120c <onoff_request+0xe0>
			notify_one(mgr, cli, state, 0);
    122c:	2300      	movs	r3, #0
    122e:	4632      	mov	r2, r6
    1230:	4639      	mov	r1, r7
    1232:	4620      	mov	r0, r4
    1234:	f007 ff99 	bl	916a <notify_one>
    1238:	e7e8      	b.n	120c <onoff_request+0xe0>
    123a:	bf00      	nop
    123c:	0000a51d 	.word	0x0000a51d
    1240:	0000a576 	.word	0x0000a576
    1244:	0000a2e8 	.word	0x0000a2e8
    1248:	0000a58b 	.word	0x0000a58b
    124c:	0000a54a 	.word	0x0000a54a
    1250:	0000a561 	.word	0x0000a561
    1254:	0000a507 	.word	0x0000a507
    1258:	0000a47a 	.word	0x0000a47a

0000125c <sys_notify_finalize>:
	return rv;
}

sys_notify_generic_callback sys_notify_finalize(struct sys_notify *notify,
						    int res)
{
    125c:	b508      	push	{r3, lr}
};

/** @internal */
static inline uint32_t sys_notify_get_method(const struct sys_notify *notify)
{
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    125e:	6842      	ldr	r2, [r0, #4]
    1260:	4603      	mov	r3, r0

	return method & SYS_NOTIFY_METHOD_MASK;
    1262:	f002 0203 	and.w	r2, r2, #3

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
	switch (method) {
    1266:	2a03      	cmp	r2, #3
	notify->result = res;
    1268:	6081      	str	r1, [r0, #8]
	switch (method) {
    126a:	d002      	beq.n	1272 <sys_notify_finalize+0x16>
    126c:	b12a      	cbz	r2, 127a <sys_notify_finalize+0x1e>
    126e:	2000      	movs	r0, #0
    1270:	e000      	b.n	1274 <sys_notify_finalize+0x18>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    1272:	6800      	ldr	r0, [r0, #0]
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    1274:	2200      	movs	r2, #0
    1276:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    1278:	bd08      	pop	{r3, pc}
		__ASSERT_NO_MSG(false);
    127a:	4905      	ldr	r1, [pc, #20]	; (1290 <sys_notify_finalize+0x34>)
    127c:	4805      	ldr	r0, [pc, #20]	; (1294 <sys_notify_finalize+0x38>)
    127e:	2345      	movs	r3, #69	; 0x45
    1280:	4a05      	ldr	r2, [pc, #20]	; (1298 <sys_notify_finalize+0x3c>)
    1282:	f008 f810 	bl	92a6 <assert_print>
    1286:	2145      	movs	r1, #69	; 0x45
    1288:	4803      	ldr	r0, [pc, #12]	; (1298 <sys_notify_finalize+0x3c>)
    128a:	f008 f805 	bl	9298 <assert_post_action>
    128e:	bf00      	nop
    1290:	0000a5f9 	.word	0x0000a5f9
    1294:	0000a2e8 	.word	0x0000a2e8
    1298:	0000a5a3 	.word	0x0000a5a3

0000129c <z_cbvprintf_impl>:
	return (int)count;
}

int z_cbvprintf_impl(cbprintf_cb out, void *ctx, const char *fp,
		     va_list ap, uint32_t flags)
{
    129c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    12a0:	4681      	mov	r9, r0
    12a2:	468b      	mov	fp, r1
    12a4:	4617      	mov	r7, r2
    12a6:	461c      	mov	r4, r3
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
    12a8:	2500      	movs	r5, #0
{
    12aa:	b095      	sub	sp, #84	; 0x54
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
    12ac:	7838      	ldrb	r0, [r7, #0]
    12ae:	b908      	cbnz	r0, 12b4 <z_cbvprintf_impl+0x18>
			OUTC(' ');
			--width;
		}
	}

	return count;
    12b0:	4628      	mov	r0, r5
    12b2:	e357      	b.n	1964 <z_cbvprintf_impl+0x6c8>
			OUTC(*fp++);
    12b4:	1c7b      	adds	r3, r7, #1
		if (*fp != '%') {
    12b6:	2825      	cmp	r0, #37	; 0x25
			OUTC(*fp++);
    12b8:	9303      	str	r3, [sp, #12]
		if (*fp != '%') {
    12ba:	d006      	beq.n	12ca <z_cbvprintf_impl+0x2e>
			OUTC('%');
    12bc:	4659      	mov	r1, fp
    12be:	47c8      	blx	r9
    12c0:	2800      	cmp	r0, #0
    12c2:	f2c0 834f 	blt.w	1964 <z_cbvprintf_impl+0x6c8>
    12c6:	3501      	adds	r5, #1
		if (bps == NULL) {
    12c8:	e1fb      	b.n	16c2 <z_cbvprintf_impl+0x426>
		} state = {
    12ca:	2218      	movs	r2, #24
    12cc:	2100      	movs	r1, #0
    12ce:	a80e      	add	r0, sp, #56	; 0x38
    12d0:	f008 f9a9 	bl	9626 <memset>
	if (*sp == '%') {
    12d4:	787b      	ldrb	r3, [r7, #1]
    12d6:	2b25      	cmp	r3, #37	; 0x25
    12d8:	d07d      	beq.n	13d6 <z_cbvprintf_impl+0x13a>
    12da:	2300      	movs	r3, #0
    12dc:	4698      	mov	r8, r3
    12de:	469e      	mov	lr, r3
    12e0:	469c      	mov	ip, r3
    12e2:	461e      	mov	r6, r3
    12e4:	1c78      	adds	r0, r7, #1
    12e6:	4601      	mov	r1, r0
		switch (*sp) {
    12e8:	f810 2b01 	ldrb.w	r2, [r0], #1
    12ec:	2a2b      	cmp	r2, #43	; 0x2b
    12ee:	f000 80a1 	beq.w	1434 <z_cbvprintf_impl+0x198>
    12f2:	f200 8098 	bhi.w	1426 <z_cbvprintf_impl+0x18a>
    12f6:	2a20      	cmp	r2, #32
    12f8:	f000 809f 	beq.w	143a <z_cbvprintf_impl+0x19e>
    12fc:	2a23      	cmp	r2, #35	; 0x23
    12fe:	f000 809f 	beq.w	1440 <z_cbvprintf_impl+0x1a4>
    1302:	b12b      	cbz	r3, 1310 <z_cbvprintf_impl+0x74>
    1304:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
    1308:	f043 0340 	orr.w	r3, r3, #64	; 0x40
    130c:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
    1310:	f1b8 0f00 	cmp.w	r8, #0
    1314:	d005      	beq.n	1322 <z_cbvprintf_impl+0x86>
    1316:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
    131a:	f043 0320 	orr.w	r3, r3, #32
    131e:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
    1322:	f1be 0f00 	cmp.w	lr, #0
    1326:	d005      	beq.n	1334 <z_cbvprintf_impl+0x98>
    1328:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
    132c:	f043 0310 	orr.w	r3, r3, #16
    1330:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
    1334:	f1bc 0f00 	cmp.w	ip, #0
    1338:	d005      	beq.n	1346 <z_cbvprintf_impl+0xaa>
    133a:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
    133e:	f043 0308 	orr.w	r3, r3, #8
    1342:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
    1346:	b12e      	cbz	r6, 1354 <z_cbvprintf_impl+0xb8>
    1348:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
    134c:	f043 0304 	orr.w	r3, r3, #4
    1350:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
	if (conv->flag_zero && conv->flag_dash) {
    1354:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
    1358:	f003 0044 	and.w	r0, r3, #68	; 0x44
    135c:	2844      	cmp	r0, #68	; 0x44
    135e:	d103      	bne.n	1368 <z_cbvprintf_impl+0xcc>
		conv->flag_zero = false;
    1360:	f36f 1386 	bfc	r3, #6, #1
    1364:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
	conv->width_present = true;
    1368:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
	if (*sp == '*') {
    136c:	2a2a      	cmp	r2, #42	; 0x2a
	conv->width_present = true;
    136e:	f043 0380 	orr.w	r3, r3, #128	; 0x80
    1372:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
	if (*sp == '*') {
    1376:	d17f      	bne.n	1478 <z_cbvprintf_impl+0x1dc>
		conv->width_star = true;
    1378:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
		return ++sp;
    137c:	1c4b      	adds	r3, r1, #1
		conv->width_star = true;
    137e:	f042 0201 	orr.w	r2, r2, #1
    1382:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
	conv->prec_present = (*sp == '.');
    1386:	781a      	ldrb	r2, [r3, #0]
    1388:	2a2e      	cmp	r2, #46	; 0x2e
    138a:	bf0c      	ite	eq
    138c:	2101      	moveq	r1, #1
    138e:	2100      	movne	r1, #0
    1390:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
    1394:	f361 0241 	bfi	r2, r1, #1, #1
    1398:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
	if (!conv->prec_present) {
    139c:	d178      	bne.n	1490 <z_cbvprintf_impl+0x1f4>
	if (*sp == '*') {
    139e:	785a      	ldrb	r2, [r3, #1]
    13a0:	2a2a      	cmp	r2, #42	; 0x2a
    13a2:	d06e      	beq.n	1482 <z_cbvprintf_impl+0x1e6>
	size_t val = 0;
    13a4:	2200      	movs	r2, #0
		val = 10U * val + *sp++ - '0';
    13a6:	f04f 0c0a 	mov.w	ip, #10
	++sp;
    13aa:	3301      	adds	r3, #1
			(((unsigned)c) <= (unsigned)'~'));
}

static inline int isdigit(int a)
{
	return (int)(((unsigned)(a)-(unsigned)'0') < 10U);
    13ac:	4619      	mov	r1, r3
    13ae:	f811 0b01 	ldrb.w	r0, [r1], #1
    13b2:	f1a0 0630 	sub.w	r6, r0, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
    13b6:	2e09      	cmp	r6, #9
    13b8:	f240 8095 	bls.w	14e6 <z_cbvprintf_impl+0x24a>
	conv->unsupported |= ((conv->prec_value < 0)
    13bc:	f89d 1040 	ldrb.w	r1, [sp, #64]	; 0x40
	conv->prec_value = prec;
    13c0:	9212      	str	r2, [sp, #72]	; 0x48
	conv->unsupported |= ((conv->prec_value < 0)
    13c2:	f3c1 0040 	ubfx	r0, r1, #1, #1
    13c6:	ea40 70d2 	orr.w	r0, r0, r2, lsr #31
    13ca:	460a      	mov	r2, r1
    13cc:	f360 0241 	bfi	r2, r0, #1, #1
    13d0:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
	return sp;
    13d4:	e05c      	b.n	1490 <z_cbvprintf_impl+0x1f4>
		conv->specifier = *sp++;
    13d6:	1cba      	adds	r2, r7, #2
    13d8:	9203      	str	r2, [sp, #12]
    13da:	f88d 3043 	strb.w	r3, [sp, #67]	; 0x43
		if (conv->width_star) {
    13de:	f89d 3041 	ldrb.w	r3, [sp, #65]	; 0x41
    13e2:	07da      	lsls	r2, r3, #31
    13e4:	f140 812e 	bpl.w	1644 <z_cbvprintf_impl+0x3a8>
			width = va_arg(ap, int);
    13e8:	f854 8b04 	ldr.w	r8, [r4], #4
			if (width < 0) {
    13ec:	f1b8 0f00 	cmp.w	r8, #0
    13f0:	da07      	bge.n	1402 <z_cbvprintf_impl+0x166>
				conv->flag_dash = true;
    13f2:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
				width = -width;
    13f6:	f1c8 0800 	rsb	r8, r8, #0
				conv->flag_dash = true;
    13fa:	f042 0204 	orr.w	r2, r2, #4
    13fe:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
		if (conv->prec_star) {
    1402:	075e      	lsls	r6, r3, #29
    1404:	f140 8127 	bpl.w	1656 <z_cbvprintf_impl+0x3ba>
			int arg = va_arg(ap, int);
    1408:	f854 ab04 	ldr.w	sl, [r4], #4
			if (arg < 0) {
    140c:	f1ba 0f00 	cmp.w	sl, #0
    1410:	f280 8126 	bge.w	1660 <z_cbvprintf_impl+0x3c4>
				conv->prec_present = false;
    1414:	f89d 3041 	ldrb.w	r3, [sp, #65]	; 0x41
    1418:	f36f 0341 	bfc	r3, #1, #1
    141c:	f88d 3041 	strb.w	r3, [sp, #65]	; 0x41
		int precision = -1;
    1420:	f04f 3aff 	mov.w	sl, #4294967295
    1424:	e11c      	b.n	1660 <z_cbvprintf_impl+0x3c4>
		switch (*sp) {
    1426:	2a2d      	cmp	r2, #45	; 0x2d
    1428:	d00d      	beq.n	1446 <z_cbvprintf_impl+0x1aa>
    142a:	2a30      	cmp	r2, #48	; 0x30
    142c:	f47f af69 	bne.w	1302 <z_cbvprintf_impl+0x66>
    1430:	2301      	movs	r3, #1
	} while (loop);
    1432:	e758      	b.n	12e6 <z_cbvprintf_impl+0x4a>
		switch (*sp) {
    1434:	f04f 0c01 	mov.w	ip, #1
    1438:	e755      	b.n	12e6 <z_cbvprintf_impl+0x4a>
    143a:	f04f 0e01 	mov.w	lr, #1
    143e:	e752      	b.n	12e6 <z_cbvprintf_impl+0x4a>
    1440:	f04f 0801 	mov.w	r8, #1
    1444:	e74f      	b.n	12e6 <z_cbvprintf_impl+0x4a>
    1446:	2601      	movs	r6, #1
    1448:	e74d      	b.n	12e6 <z_cbvprintf_impl+0x4a>
		val = 10U * val + *sp++ - '0';
    144a:	4603      	mov	r3, r0
    144c:	fb0e 6202 	mla	r2, lr, r2, r6
    1450:	3a30      	subs	r2, #48	; 0x30
    1452:	4618      	mov	r0, r3
    1454:	f810 6b01 	ldrb.w	r6, [r0], #1
    1458:	f1a6 0c30 	sub.w	ip, r6, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
    145c:	f1bc 0f09 	cmp.w	ip, #9
    1460:	d9f3      	bls.n	144a <z_cbvprintf_impl+0x1ae>
	if (sp != wp) {
    1462:	4299      	cmp	r1, r3
    1464:	d08f      	beq.n	1386 <z_cbvprintf_impl+0xea>
		conv->unsupported |= ((conv->width_value < 0)
    1466:	f89d 1040 	ldrb.w	r1, [sp, #64]	; 0x40
		conv->width_value = width;
    146a:	9211      	str	r2, [sp, #68]	; 0x44
				      || (width != (size_t)conv->width_value));
    146c:	0fd2      	lsrs	r2, r2, #31
		conv->unsupported |= ((conv->width_value < 0)
    146e:	f362 0141 	bfi	r1, r2, #1, #1
    1472:	f88d 1040 	strb.w	r1, [sp, #64]	; 0x40
    1476:	e786      	b.n	1386 <z_cbvprintf_impl+0xea>
    1478:	460b      	mov	r3, r1
	size_t val = 0;
    147a:	2200      	movs	r2, #0
		val = 10U * val + *sp++ - '0';
    147c:	f04f 0e0a 	mov.w	lr, #10
    1480:	e7e7      	b.n	1452 <z_cbvprintf_impl+0x1b6>
		conv->prec_star = true;
    1482:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
		return ++sp;
    1486:	3302      	adds	r3, #2
		conv->prec_star = true;
    1488:	f042 0204 	orr.w	r2, r2, #4
    148c:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
	switch (*sp) {
    1490:	781a      	ldrb	r2, [r3, #0]
    1492:	2a6c      	cmp	r2, #108	; 0x6c
    1494:	d047      	beq.n	1526 <z_cbvprintf_impl+0x28a>
    1496:	d82b      	bhi.n	14f0 <z_cbvprintf_impl+0x254>
    1498:	2a68      	cmp	r2, #104	; 0x68
    149a:	d031      	beq.n	1500 <z_cbvprintf_impl+0x264>
    149c:	2a6a      	cmp	r2, #106	; 0x6a
    149e:	d04b      	beq.n	1538 <z_cbvprintf_impl+0x29c>
    14a0:	2a4c      	cmp	r2, #76	; 0x4c
    14a2:	d051      	beq.n	1548 <z_cbvprintf_impl+0x2ac>
	conv->specifier = *sp++;
    14a4:	461a      	mov	r2, r3
    14a6:	f812 3b01 	ldrb.w	r3, [r2], #1
	switch (conv->specifier) {
    14aa:	2b78      	cmp	r3, #120	; 0x78
	conv->specifier = *sp++;
    14ac:	9203      	str	r2, [sp, #12]
    14ae:	f88d 3043 	strb.w	r3, [sp, #67]	; 0x43
		if (conv->length_mod == LENGTH_UPPER_L) {
    14b2:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
	switch (conv->specifier) {
    14b6:	f200 80be 	bhi.w	1636 <z_cbvprintf_impl+0x39a>
    14ba:	2b6d      	cmp	r3, #109	; 0x6d
    14bc:	d851      	bhi.n	1562 <z_cbvprintf_impl+0x2c6>
    14be:	2b69      	cmp	r3, #105	; 0x69
    14c0:	f200 80b9 	bhi.w	1636 <z_cbvprintf_impl+0x39a>
    14c4:	2b57      	cmp	r3, #87	; 0x57
    14c6:	d867      	bhi.n	1598 <z_cbvprintf_impl+0x2fc>
    14c8:	2b41      	cmp	r3, #65	; 0x41
    14ca:	d003      	beq.n	14d4 <z_cbvprintf_impl+0x238>
    14cc:	3b45      	subs	r3, #69	; 0x45
    14ce:	2b02      	cmp	r3, #2
    14d0:	f200 80b1 	bhi.w	1636 <z_cbvprintf_impl+0x39a>
		conv->specifier_cat = SPECIFIER_FP;
    14d4:	2204      	movs	r2, #4
    14d6:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
    14da:	f362 0302 	bfi	r3, r2, #0, #3
    14de:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
			unsupported = true;
    14e2:	2301      	movs	r3, #1
			break;
    14e4:	e073      	b.n	15ce <z_cbvprintf_impl+0x332>
		val = 10U * val + *sp++ - '0';
    14e6:	fb0c 0202 	mla	r2, ip, r2, r0
    14ea:	460b      	mov	r3, r1
    14ec:	3a30      	subs	r2, #48	; 0x30
    14ee:	e75d      	b.n	13ac <z_cbvprintf_impl+0x110>
	switch (*sp) {
    14f0:	2a74      	cmp	r2, #116	; 0x74
    14f2:	d025      	beq.n	1540 <z_cbvprintf_impl+0x2a4>
    14f4:	2a7a      	cmp	r2, #122	; 0x7a
    14f6:	d1d5      	bne.n	14a4 <z_cbvprintf_impl+0x208>
		conv->length_mod = LENGTH_Z;
    14f8:	2106      	movs	r1, #6
    14fa:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
    14fe:	e00c      	b.n	151a <z_cbvprintf_impl+0x27e>
		if (*++sp == 'h') {
    1500:	785a      	ldrb	r2, [r3, #1]
    1502:	2a68      	cmp	r2, #104	; 0x68
    1504:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
    1508:	d106      	bne.n	1518 <z_cbvprintf_impl+0x27c>
			conv->length_mod = LENGTH_HH;
    150a:	2101      	movs	r1, #1
			conv->length_mod = LENGTH_LL;
    150c:	f361 02c6 	bfi	r2, r1, #3, #4
    1510:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
			++sp;
    1514:	3302      	adds	r3, #2
    1516:	e7c5      	b.n	14a4 <z_cbvprintf_impl+0x208>
			conv->length_mod = LENGTH_H;
    1518:	2102      	movs	r1, #2
    151a:	f361 02c6 	bfi	r2, r1, #3, #4
    151e:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
		if (*++sp == 'h') {
    1522:	3301      	adds	r3, #1
    1524:	e7be      	b.n	14a4 <z_cbvprintf_impl+0x208>
		if (*++sp == 'l') {
    1526:	785a      	ldrb	r2, [r3, #1]
    1528:	2a6c      	cmp	r2, #108	; 0x6c
    152a:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
    152e:	d101      	bne.n	1534 <z_cbvprintf_impl+0x298>
			conv->length_mod = LENGTH_LL;
    1530:	2104      	movs	r1, #4
    1532:	e7eb      	b.n	150c <z_cbvprintf_impl+0x270>
			conv->length_mod = LENGTH_L;
    1534:	2103      	movs	r1, #3
    1536:	e7f0      	b.n	151a <z_cbvprintf_impl+0x27e>
		conv->length_mod = LENGTH_J;
    1538:	2105      	movs	r1, #5
    153a:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
    153e:	e7ec      	b.n	151a <z_cbvprintf_impl+0x27e>
		conv->length_mod = LENGTH_T;
    1540:	2107      	movs	r1, #7
    1542:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
    1546:	e7e8      	b.n	151a <z_cbvprintf_impl+0x27e>
		conv->unsupported = true;
    1548:	f8bd 2040 	ldrh.w	r2, [sp, #64]	; 0x40
    154c:	f422 42f0 	bic.w	r2, r2, #30720	; 0x7800
    1550:	f022 0202 	bic.w	r2, r2, #2
    1554:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
    1558:	f042 0202 	orr.w	r2, r2, #2
    155c:	f8ad 2040 	strh.w	r2, [sp, #64]	; 0x40
		break;
    1560:	e7df      	b.n	1522 <z_cbvprintf_impl+0x286>
	switch (conv->specifier) {
    1562:	3b6e      	subs	r3, #110	; 0x6e
    1564:	b2d9      	uxtb	r1, r3
    1566:	2301      	movs	r3, #1
    1568:	408b      	lsls	r3, r1
    156a:	f240 4182 	movw	r1, #1154	; 0x482
    156e:	420b      	tst	r3, r1
    1570:	d137      	bne.n	15e2 <z_cbvprintf_impl+0x346>
    1572:	f013 0f24 	tst.w	r3, #36	; 0x24
    1576:	d151      	bne.n	161c <z_cbvprintf_impl+0x380>
    1578:	07d8      	lsls	r0, r3, #31
    157a:	d55c      	bpl.n	1636 <z_cbvprintf_impl+0x39a>
		conv->specifier_cat = SPECIFIER_PTR;
    157c:	2103      	movs	r1, #3
    157e:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
    1582:	f361 0302 	bfi	r3, r1, #0, #3
    1586:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
		if (conv->length_mod == LENGTH_UPPER_L) {
    158a:	f002 0378 	and.w	r3, r2, #120	; 0x78
    158e:	f1a3 0140 	sub.w	r1, r3, #64	; 0x40
    1592:	424b      	negs	r3, r1
    1594:	414b      	adcs	r3, r1
    1596:	e01a      	b.n	15ce <z_cbvprintf_impl+0x332>
    1598:	2001      	movs	r0, #1
	switch (conv->specifier) {
    159a:	f1a3 0158 	sub.w	r1, r3, #88	; 0x58
    159e:	b2c9      	uxtb	r1, r1
    15a0:	fa00 f101 	lsl.w	r1, r0, r1
    15a4:	f411 4f62 	tst.w	r1, #57856	; 0xe200
    15a8:	d194      	bne.n	14d4 <z_cbvprintf_impl+0x238>
    15aa:	f640 0601 	movw	r6, #2049	; 0x801
    15ae:	4231      	tst	r1, r6
    15b0:	d11d      	bne.n	15ee <z_cbvprintf_impl+0x352>
    15b2:	f411 3f04 	tst.w	r1, #135168	; 0x21000
    15b6:	d03e      	beq.n	1636 <z_cbvprintf_impl+0x39a>
		conv->specifier_cat = SPECIFIER_SINT;
    15b8:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
    15bc:	f360 0302 	bfi	r3, r0, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
    15c0:	f002 0278 	and.w	r2, r2, #120	; 0x78
    15c4:	2a40      	cmp	r2, #64	; 0x40
		conv->specifier_cat = SPECIFIER_SINT;
    15c6:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
		if (conv->length_mod == LENGTH_UPPER_L) {
    15ca:	d034      	beq.n	1636 <z_cbvprintf_impl+0x39a>
	bool unsupported = false;
    15cc:	2300      	movs	r3, #0
	conv->unsupported |= unsupported;
    15ce:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
    15d2:	f3c2 0140 	ubfx	r1, r2, #1, #1
    15d6:	430b      	orrs	r3, r1
    15d8:	f363 0241 	bfi	r2, r3, #1, #1
    15dc:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
	return sp;
    15e0:	e6fd      	b.n	13de <z_cbvprintf_impl+0x142>
		conv->specifier_cat = SPECIFIER_UINT;
    15e2:	2102      	movs	r1, #2
    15e4:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
    15e8:	f361 0302 	bfi	r3, r1, #0, #3
    15ec:	e7e8      	b.n	15c0 <z_cbvprintf_impl+0x324>
    15ee:	2002      	movs	r0, #2
    15f0:	f89d 1042 	ldrb.w	r1, [sp, #66]	; 0x42
		if (conv->length_mod == LENGTH_UPPER_L) {
    15f4:	f002 0278 	and.w	r2, r2, #120	; 0x78
		conv->specifier_cat = SPECIFIER_UINT;
    15f8:	f360 0102 	bfi	r1, r0, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
    15fc:	2a40      	cmp	r2, #64	; 0x40
		conv->specifier_cat = SPECIFIER_UINT;
    15fe:	f88d 1042 	strb.w	r1, [sp, #66]	; 0x42
			conv->invalid = true;
    1602:	bf02      	ittt	eq
    1604:	f89d 1040 	ldrbeq.w	r1, [sp, #64]	; 0x40
    1608:	f041 0101 	orreq.w	r1, r1, #1
    160c:	f88d 1040 	strbeq.w	r1, [sp, #64]	; 0x40
		if (conv->specifier == 'c') {
    1610:	2b63      	cmp	r3, #99	; 0x63
    1612:	d1db      	bne.n	15cc <z_cbvprintf_impl+0x330>
			unsupported = (conv->length_mod != LENGTH_NONE);
    1614:	1e13      	subs	r3, r2, #0
    1616:	bf18      	it	ne
    1618:	2301      	movne	r3, #1
    161a:	e7d8      	b.n	15ce <z_cbvprintf_impl+0x332>
		conv->specifier_cat = SPECIFIER_PTR;
    161c:	2103      	movs	r1, #3
    161e:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
		if (conv->length_mod != LENGTH_NONE) {
    1622:	f012 0f78 	tst.w	r2, #120	; 0x78
		conv->specifier_cat = SPECIFIER_PTR;
    1626:	f361 0302 	bfi	r3, r1, #0, #3
    162a:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
		if (conv->length_mod != LENGTH_NONE) {
    162e:	bf14      	ite	ne
    1630:	2301      	movne	r3, #1
    1632:	2300      	moveq	r3, #0
    1634:	e7cb      	b.n	15ce <z_cbvprintf_impl+0x332>
		conv->invalid = true;
    1636:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
    163a:	f043 0301 	orr.w	r3, r3, #1
    163e:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
		break;
    1642:	e7c3      	b.n	15cc <z_cbvprintf_impl+0x330>
		} else if (conv->width_present) {
    1644:	f99d 2040 	ldrsb.w	r2, [sp, #64]	; 0x40
    1648:	2a00      	cmp	r2, #0
		int width = -1;
    164a:	bfac      	ite	ge
    164c:	f04f 38ff 	movge.w	r8, #4294967295
			width = conv->width_value;
    1650:	f8dd 8044 	ldrlt.w	r8, [sp, #68]	; 0x44
    1654:	e6d5      	b.n	1402 <z_cbvprintf_impl+0x166>
		} else if (conv->prec_present) {
    1656:	0798      	lsls	r0, r3, #30
    1658:	f57f aee2 	bpl.w	1420 <z_cbvprintf_impl+0x184>
			precision = conv->prec_value;
    165c:	f8dd a048 	ldr.w	sl, [sp, #72]	; 0x48
		conv->pad0_value = 0;
    1660:	2300      	movs	r3, #0
		conv->pad0_pre_exp = 0;
    1662:	e9cd 3311 	strd	r3, r3, [sp, #68]	; 0x44
			= (enum specifier_cat_enum)conv->specifier_cat;
    1666:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
			= (enum length_mod_enum)conv->length_mod;
    166a:	f89d 1041 	ldrb.w	r1, [sp, #65]	; 0x41
		enum specifier_cat_enum specifier_cat
    166e:	f003 0307 	and.w	r3, r3, #7
		if (specifier_cat == SPECIFIER_SINT) {
    1672:	2b01      	cmp	r3, #1
			= (enum length_mod_enum)conv->length_mod;
    1674:	f3c1 01c3 	ubfx	r1, r1, #3, #4
		if (specifier_cat == SPECIFIER_SINT) {
    1678:	d133      	bne.n	16e2 <z_cbvprintf_impl+0x446>
			switch (length_mod) {
    167a:	1ecb      	subs	r3, r1, #3
    167c:	2b04      	cmp	r3, #4
    167e:	d804      	bhi.n	168a <z_cbvprintf_impl+0x3ee>
    1680:	e8df f003 	tbb	[pc, r3]
    1684:	21464621 	.word	0x21464621
    1688:	21          	.byte	0x21
    1689:	00          	.byte	0x00
				value->sint = va_arg(ap, int);
    168a:	6823      	ldr	r3, [r4, #0]
			if (length_mod == LENGTH_HH) {
    168c:	2901      	cmp	r1, #1
				value->sint = va_arg(ap, int);
    168e:	ea4f 72e3 	mov.w	r2, r3, asr #31
    1692:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
			if (length_mod == LENGTH_HH) {
    1696:	d11c      	bne.n	16d2 <z_cbvprintf_impl+0x436>
				value->sint = (signed char)value->sint;
    1698:	f99d 3038 	ldrsb.w	r3, [sp, #56]	; 0x38
    169c:	17da      	asrs	r2, r3, #31
    169e:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
				value->sint = va_arg(ap, int);
    16a2:	3404      	adds	r4, #4
		if (conv->invalid || conv->unsupported) {
    16a4:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
    16a8:	f013 0603 	ands.w	r6, r3, #3
    16ac:	d050      	beq.n	1750 <z_cbvprintf_impl+0x4b4>
			OUTS(sp, fp);
    16ae:	463a      	mov	r2, r7
    16b0:	4659      	mov	r1, fp
    16b2:	4648      	mov	r0, r9
    16b4:	9b03      	ldr	r3, [sp, #12]
    16b6:	f007 fdd8 	bl	926a <outs>
    16ba:	2800      	cmp	r0, #0
    16bc:	f2c0 8152 	blt.w	1964 <z_cbvprintf_impl+0x6c8>
    16c0:	4405      	add	r5, r0
			continue;
    16c2:	9f03      	ldr	r7, [sp, #12]
    16c4:	e5f2      	b.n	12ac <z_cbvprintf_impl+0x10>
					(sint_value_type)va_arg(ap, ptrdiff_t);
    16c6:	f854 3b04 	ldr.w	r3, [r4], #4
    16ca:	17da      	asrs	r2, r3, #31
				value->uint = (unsigned char)value->uint;
    16cc:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
    16d0:	e7e8      	b.n	16a4 <z_cbvprintf_impl+0x408>
			} else if (length_mod == LENGTH_H) {
    16d2:	2902      	cmp	r1, #2
    16d4:	d1e5      	bne.n	16a2 <z_cbvprintf_impl+0x406>
				value->sint = (short)value->sint;
    16d6:	b21a      	sxth	r2, r3
    16d8:	f343 33c0 	sbfx	r3, r3, #15, #1
    16dc:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
    16e0:	e7df      	b.n	16a2 <z_cbvprintf_impl+0x406>
		} else if (specifier_cat == SPECIFIER_UINT) {
    16e2:	2b02      	cmp	r3, #2
    16e4:	d124      	bne.n	1730 <z_cbvprintf_impl+0x494>
			switch (length_mod) {
    16e6:	1ecb      	subs	r3, r1, #3
    16e8:	2b04      	cmp	r3, #4
    16ea:	d804      	bhi.n	16f6 <z_cbvprintf_impl+0x45a>
    16ec:	e8df f003 	tbb	[pc, r3]
    16f0:	18101018 	.word	0x18101018
    16f4:	18          	.byte	0x18
    16f5:	00          	.byte	0x00
			if (length_mod == LENGTH_HH) {
    16f6:	2901      	cmp	r1, #1
    16f8:	f04f 0200 	mov.w	r2, #0
				value->uint = va_arg(ap, unsigned int);
    16fc:	f854 3b04 	ldr.w	r3, [r4], #4
			if (length_mod == LENGTH_HH) {
    1700:	d014      	beq.n	172c <z_cbvprintf_impl+0x490>
			} else if (length_mod == LENGTH_H) {
    1702:	2902      	cmp	r1, #2
				value->uint = va_arg(ap, unsigned int);
    1704:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
			} else if (length_mod == LENGTH_H) {
    1708:	d1cc      	bne.n	16a4 <z_cbvprintf_impl+0x408>
				value->uint = (unsigned short)value->uint;
    170a:	b29b      	uxth	r3, r3
			value->ptr = va_arg(ap, void *);
    170c:	930e      	str	r3, [sp, #56]	; 0x38
    170e:	e7c9      	b.n	16a4 <z_cbvprintf_impl+0x408>
					(uint_value_type)va_arg(ap,
    1710:	3407      	adds	r4, #7
    1712:	f024 0407 	bic.w	r4, r4, #7
				value->uint =
    1716:	e8f4 2302 	ldrd	r2, r3, [r4], #8
    171a:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
			if (length_mod == LENGTH_HH) {
    171e:	e7c1      	b.n	16a4 <z_cbvprintf_impl+0x408>
					(uint_value_type)va_arg(ap, size_t);
    1720:	f854 3b04 	ldr.w	r3, [r4], #4
    1724:	930e      	str	r3, [sp, #56]	; 0x38
    1726:	2300      	movs	r3, #0
    1728:	930f      	str	r3, [sp, #60]	; 0x3c
			} else if (length_mod == LENGTH_H) {
    172a:	e7bb      	b.n	16a4 <z_cbvprintf_impl+0x408>
				value->uint = (unsigned char)value->uint;
    172c:	b2db      	uxtb	r3, r3
    172e:	e7cd      	b.n	16cc <z_cbvprintf_impl+0x430>
		} else if (specifier_cat == SPECIFIER_FP) {
    1730:	2b04      	cmp	r3, #4
    1732:	d108      	bne.n	1746 <z_cbvprintf_impl+0x4aa>
					(sint_value_type)va_arg(ap, long long);
    1734:	3407      	adds	r4, #7
				value->ldbl = va_arg(ap, long double);
    1736:	f024 0407 	bic.w	r4, r4, #7
    173a:	e9d4 2300 	ldrd	r2, r3, [r4]
    173e:	3408      	adds	r4, #8
    1740:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
    1744:	e7ae      	b.n	16a4 <z_cbvprintf_impl+0x408>
		} else if (specifier_cat == SPECIFIER_PTR) {
    1746:	2b03      	cmp	r3, #3
    1748:	d1ac      	bne.n	16a4 <z_cbvprintf_impl+0x408>
			value->ptr = va_arg(ap, void *);
    174a:	f854 3b04 	ldr.w	r3, [r4], #4
    174e:	e7dd      	b.n	170c <z_cbvprintf_impl+0x470>
		switch (conv->specifier) {
    1750:	f89d 0043 	ldrb.w	r0, [sp, #67]	; 0x43
    1754:	2878      	cmp	r0, #120	; 0x78
    1756:	d8b4      	bhi.n	16c2 <z_cbvprintf_impl+0x426>
    1758:	2862      	cmp	r0, #98	; 0x62
    175a:	d81c      	bhi.n	1796 <z_cbvprintf_impl+0x4fa>
    175c:	2825      	cmp	r0, #37	; 0x25
    175e:	f43f adad 	beq.w	12bc <z_cbvprintf_impl+0x20>
    1762:	2858      	cmp	r0, #88	; 0x58
    1764:	d1ad      	bne.n	16c2 <z_cbvprintf_impl+0x426>
			bps = encode_uint(value->uint, conv, buf, bpe);
    1766:	e9dd 010e 	ldrd	r0, r1, [sp, #56]	; 0x38
    176a:	f10d 0336 	add.w	r3, sp, #54	; 0x36
    176e:	9300      	str	r3, [sp, #0]
    1770:	aa10      	add	r2, sp, #64	; 0x40
    1772:	ab08      	add	r3, sp, #32
    1774:	f007 fd33 	bl	91de <encode_uint>
			if (precision >= 0) {
    1778:	f1ba 0f00 	cmp.w	sl, #0
			bps = encode_uint(value->uint, conv, buf, bpe);
    177c:	4607      	mov	r7, r0
			if (precision >= 0) {
    177e:	f280 8099 	bge.w	18b4 <z_cbvprintf_impl+0x618>
		if (bps == NULL) {
    1782:	2f00      	cmp	r7, #0
    1784:	d09d      	beq.n	16c2 <z_cbvprintf_impl+0x426>
		size_t nj_len = (bpe - bps);
    1786:	f10d 0336 	add.w	r3, sp, #54	; 0x36
    178a:	1bd8      	subs	r0, r3, r7
		if (sign != 0) {
    178c:	2e00      	cmp	r6, #0
    178e:	f000 80c0 	beq.w	1912 <z_cbvprintf_impl+0x676>
			nj_len += 1U;
    1792:	3001      	adds	r0, #1
    1794:	e0bd      	b.n	1912 <z_cbvprintf_impl+0x676>
		switch (conv->specifier) {
    1796:	3863      	subs	r0, #99	; 0x63
    1798:	2815      	cmp	r0, #21
    179a:	d892      	bhi.n	16c2 <z_cbvprintf_impl+0x426>
    179c:	a201      	add	r2, pc, #4	; (adr r2, 17a4 <z_cbvprintf_impl+0x508>)
    179e:	f852 f020 	ldr.w	pc, [r2, r0, lsl #2]
    17a2:	bf00      	nop
    17a4:	00001879 	.word	0x00001879
    17a8:	0000188b 	.word	0x0000188b
    17ac:	000016c3 	.word	0x000016c3
    17b0:	000016c3 	.word	0x000016c3
    17b4:	000016c3 	.word	0x000016c3
    17b8:	000016c3 	.word	0x000016c3
    17bc:	0000188b 	.word	0x0000188b
    17c0:	000016c3 	.word	0x000016c3
    17c4:	000016c3 	.word	0x000016c3
    17c8:	000016c3 	.word	0x000016c3
    17cc:	000016c3 	.word	0x000016c3
    17d0:	00001917 	.word	0x00001917
    17d4:	000018af 	.word	0x000018af
    17d8:	000018d5 	.word	0x000018d5
    17dc:	000016c3 	.word	0x000016c3
    17e0:	000016c3 	.word	0x000016c3
    17e4:	000017fd 	.word	0x000017fd
    17e8:	000016c3 	.word	0x000016c3
    17ec:	000018af 	.word	0x000018af
    17f0:	000016c3 	.word	0x000016c3
    17f4:	000016c3 	.word	0x000016c3
    17f8:	000018af 	.word	0x000018af
			if (precision >= 0) {
    17fc:	f1ba 0f00 	cmp.w	sl, #0
			bps = (const char *)value->ptr;
    1800:	9f0e      	ldr	r7, [sp, #56]	; 0x38
			if (precision >= 0) {
    1802:	db35      	blt.n	1870 <z_cbvprintf_impl+0x5d4>
				len = strnlen(bps, precision);
    1804:	4651      	mov	r1, sl
    1806:	4638      	mov	r0, r7
    1808:	f007 fef9 	bl	95fe <strnlen>
			bpe = bps + len;
    180c:	eb07 0a00 	add.w	sl, r7, r0
		if (bps == NULL) {
    1810:	2f00      	cmp	r7, #0
    1812:	f43f af56 	beq.w	16c2 <z_cbvprintf_impl+0x426>
		char sign = 0;
    1816:	2600      	movs	r6, #0
		if (conv->altform_0c) {
    1818:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
    181c:	f013 0210 	ands.w	r2, r3, #16
    1820:	9205      	str	r2, [sp, #20]
    1822:	f000 8092 	beq.w	194a <z_cbvprintf_impl+0x6ae>
			nj_len += 2U;
    1826:	3002      	adds	r0, #2
		if (conv->pad_fp) {
    1828:	065b      	lsls	r3, r3, #25
		nj_len += conv->pad0_value;
    182a:	9a11      	ldr	r2, [sp, #68]	; 0x44
			nj_len += conv->pad0_pre_exp;
    182c:	bf48      	it	mi
    182e:	9b12      	ldrmi	r3, [sp, #72]	; 0x48
		nj_len += conv->pad0_value;
    1830:	4410      	add	r0, r2
			nj_len += conv->pad0_pre_exp;
    1832:	bf48      	it	mi
    1834:	18c0      	addmi	r0, r0, r3
		if (width > 0) {
    1836:	f1b8 0f00 	cmp.w	r8, #0
		nj_len += conv->pad0_value;
    183a:	9204      	str	r2, [sp, #16]
		if (width > 0) {
    183c:	f340 809f 	ble.w	197e <z_cbvprintf_impl+0x6e2>
			if (!conv->flag_dash) {
    1840:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
			width -= (int)nj_len;
    1844:	eba8 0800 	sub.w	r8, r8, r0
			if (!conv->flag_dash) {
    1848:	f3c2 0380 	ubfx	r3, r2, #2, #1
    184c:	0750      	lsls	r0, r2, #29
    184e:	9306      	str	r3, [sp, #24]
    1850:	f100 8095 	bmi.w	197e <z_cbvprintf_impl+0x6e2>
				if (conv->flag_zero) {
    1854:	0651      	lsls	r1, r2, #25
    1856:	f140 8088 	bpl.w	196a <z_cbvprintf_impl+0x6ce>
					if (sign != 0) {
    185a:	b13e      	cbz	r6, 186c <z_cbvprintf_impl+0x5d0>
						OUTC(sign);
    185c:	4659      	mov	r1, fp
    185e:	4630      	mov	r0, r6
    1860:	47c8      	blx	r9
    1862:	2800      	cmp	r0, #0
    1864:	db7e      	blt.n	1964 <z_cbvprintf_impl+0x6c8>
    1866:	9b06      	ldr	r3, [sp, #24]
    1868:	3501      	adds	r5, #1
    186a:	461e      	mov	r6, r3
					pad = '0';
    186c:	2230      	movs	r2, #48	; 0x30
    186e:	e07d      	b.n	196c <z_cbvprintf_impl+0x6d0>
				len = strlen(bps);
    1870:	4638      	mov	r0, r7
    1872:	f007 febd 	bl	95f0 <strlen>
    1876:	e7c9      	b.n	180c <z_cbvprintf_impl+0x570>
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
    1878:	9b0e      	ldr	r3, [sp, #56]	; 0x38
		char sign = 0;
    187a:	2600      	movs	r6, #0
		size_t nj_len = (bpe - bps);
    187c:	2001      	movs	r0, #1
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
    187e:	f88d 3020 	strb.w	r3, [sp, #32]
			bps = buf;
    1882:	af08      	add	r7, sp, #32
			bpe = buf + 1;
    1884:	f10d 0a21 	add.w	sl, sp, #33	; 0x21
    1888:	e7c6      	b.n	1818 <z_cbvprintf_impl+0x57c>
			if (conv->flag_plus) {
    188a:	0719      	lsls	r1, r3, #28
			} else if (conv->flag_space) {
    188c:	bf5a      	itte	pl
    188e:	f3c3 1300 	ubfxpl	r3, r3, #4, #1
    1892:	015e      	lslpl	r6, r3, #5
				sign = '+';
    1894:	262b      	movmi	r6, #43	; 0x2b
			sint = value->sint;
    1896:	e9dd 230e 	ldrd	r2, r3, [sp, #56]	; 0x38
			if (sint < 0) {
    189a:	2b00      	cmp	r3, #0
    189c:	f6bf af63 	bge.w	1766 <z_cbvprintf_impl+0x4ca>
				value->uint = (uint_value_type)-sint;
    18a0:	4252      	negs	r2, r2
    18a2:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
				sign = '-';
    18a6:	262d      	movs	r6, #45	; 0x2d
				value->uint = (uint_value_type)-sint;
    18a8:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
    18ac:	e75b      	b.n	1766 <z_cbvprintf_impl+0x4ca>
		switch (conv->specifier) {
    18ae:	2600      	movs	r6, #0
    18b0:	e759      	b.n	1766 <z_cbvprintf_impl+0x4ca>
		char sign = 0;
    18b2:	2600      	movs	r6, #0
				conv->flag_zero = false;
    18b4:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
				size_t len = bpe - bps;
    18b8:	f10d 0336 	add.w	r3, sp, #54	; 0x36
    18bc:	1bdb      	subs	r3, r3, r7
				conv->flag_zero = false;
    18be:	f36f 1286 	bfc	r2, #6, #1
				if (len < (size_t)precision) {
    18c2:	459a      	cmp	sl, r3
				conv->flag_zero = false;
    18c4:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
				if (len < (size_t)precision) {
    18c8:	f67f af5b 	bls.w	1782 <z_cbvprintf_impl+0x4e6>
					conv->pad0_value = precision - (int)len;
    18cc:	ebaa 0303 	sub.w	r3, sl, r3
    18d0:	9311      	str	r3, [sp, #68]	; 0x44
    18d2:	e756      	b.n	1782 <z_cbvprintf_impl+0x4e6>
			if (value->ptr != NULL) {
    18d4:	980e      	ldr	r0, [sp, #56]	; 0x38
    18d6:	b390      	cbz	r0, 193e <z_cbvprintf_impl+0x6a2>
				bps = encode_uint((uintptr_t)value->ptr, conv,
    18d8:	f10d 0336 	add.w	r3, sp, #54	; 0x36
    18dc:	9300      	str	r3, [sp, #0]
    18de:	2100      	movs	r1, #0
    18e0:	ab08      	add	r3, sp, #32
    18e2:	aa10      	add	r2, sp, #64	; 0x40
    18e4:	f007 fc7b 	bl	91de <encode_uint>
				conv->altform_0c = true;
    18e8:	f8bd 3042 	ldrh.w	r3, [sp, #66]	; 0x42
			if (precision >= 0) {
    18ec:	f1ba 0f00 	cmp.w	sl, #0
				conv->altform_0c = true;
    18f0:	f003 03ef 	and.w	r3, r3, #239	; 0xef
    18f4:	f443 43f0 	orr.w	r3, r3, #30720	; 0x7800
    18f8:	f043 0310 	orr.w	r3, r3, #16
				bps = encode_uint((uintptr_t)value->ptr, conv,
    18fc:	4607      	mov	r7, r0
				conv->altform_0c = true;
    18fe:	f8ad 3042 	strh.w	r3, [sp, #66]	; 0x42
			if (precision >= 0) {
    1902:	dad6      	bge.n	18b2 <z_cbvprintf_impl+0x616>
		if (bps == NULL) {
    1904:	2800      	cmp	r0, #0
    1906:	f43f aedc 	beq.w	16c2 <z_cbvprintf_impl+0x426>
		char sign = 0;
    190a:	2600      	movs	r6, #0
		size_t nj_len = (bpe - bps);
    190c:	f10d 0336 	add.w	r3, sp, #54	; 0x36
    1910:	1a18      	subs	r0, r3, r0
		if (sign != 0) {
    1912:	469a      	mov	sl, r3
    1914:	e780      	b.n	1818 <z_cbvprintf_impl+0x57c>
				store_count(conv, value->ptr, count);
    1916:	9b0e      	ldr	r3, [sp, #56]	; 0x38
	switch ((enum length_mod_enum)conv->length_mod) {
    1918:	2907      	cmp	r1, #7
    191a:	f63f aed2 	bhi.w	16c2 <z_cbvprintf_impl+0x426>
    191e:	e8df f001 	tbb	[pc, r1]
    1922:	040c      	.short	0x040c
    1924:	08080c06 	.word	0x08080c06
    1928:	0c0c      	.short	0x0c0c
		*(signed char *)dp = (signed char)count;
    192a:	701d      	strb	r5, [r3, #0]
		if (bps == NULL) {
    192c:	e6c9      	b.n	16c2 <z_cbvprintf_impl+0x426>
		*(short *)dp = (short)count;
    192e:	801d      	strh	r5, [r3, #0]
		if (bps == NULL) {
    1930:	e6c7      	b.n	16c2 <z_cbvprintf_impl+0x426>
		*(intmax_t *)dp = (intmax_t)count;
    1932:	17ea      	asrs	r2, r5, #31
    1934:	e9c3 5200 	strd	r5, r2, [r3]
		if (bps == NULL) {
    1938:	e6c3      	b.n	16c2 <z_cbvprintf_impl+0x426>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
    193a:	601d      	str	r5, [r3, #0]
		if (bps == NULL) {
    193c:	e6c1      	b.n	16c2 <z_cbvprintf_impl+0x426>
    193e:	4f2f      	ldr	r7, [pc, #188]	; (19fc <z_cbvprintf_impl+0x760>)
		char sign = 0;
    1940:	4606      	mov	r6, r0
			bpe = bps + 5;
    1942:	f107 0a05 	add.w	sl, r7, #5
		size_t nj_len = (bpe - bps);
    1946:	2005      	movs	r0, #5
    1948:	e766      	b.n	1818 <z_cbvprintf_impl+0x57c>
		} else if (conv->altform_0) {
    194a:	071a      	lsls	r2, r3, #28
			nj_len += 1U;
    194c:	bf48      	it	mi
    194e:	3001      	addmi	r0, #1
    1950:	e76a      	b.n	1828 <z_cbvprintf_impl+0x58c>
					OUTC(pad);
    1952:	4610      	mov	r0, r2
    1954:	9307      	str	r3, [sp, #28]
    1956:	9206      	str	r2, [sp, #24]
    1958:	4659      	mov	r1, fp
    195a:	47c8      	blx	r9
    195c:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
    1960:	2800      	cmp	r0, #0
    1962:	da04      	bge.n	196e <z_cbvprintf_impl+0x6d2>
#undef OUTS
#undef OUTC
}
    1964:	b015      	add	sp, #84	; 0x54
    1966:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				char pad = ' ';
    196a:	2220      	movs	r2, #32
					pad = '0';
    196c:	4643      	mov	r3, r8
				while (width-- > 0) {
    196e:	4619      	mov	r1, r3
    1970:	2900      	cmp	r1, #0
    1972:	f103 33ff 	add.w	r3, r3, #4294967295
    1976:	dcec      	bgt.n	1952 <z_cbvprintf_impl+0x6b6>
    1978:	4445      	add	r5, r8
    197a:	4698      	mov	r8, r3
    197c:	1a6d      	subs	r5, r5, r1
		if (sign != 0) {
    197e:	b12e      	cbz	r6, 198c <z_cbvprintf_impl+0x6f0>
			OUTC(sign);
    1980:	4659      	mov	r1, fp
    1982:	4630      	mov	r0, r6
    1984:	47c8      	blx	r9
    1986:	2800      	cmp	r0, #0
    1988:	dbec      	blt.n	1964 <z_cbvprintf_impl+0x6c8>
    198a:	3501      	adds	r5, #1
			if (conv->altform_0c | conv->altform_0) {
    198c:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
    1990:	06da      	lsls	r2, r3, #27
    1992:	d401      	bmi.n	1998 <z_cbvprintf_impl+0x6fc>
    1994:	071b      	lsls	r3, r3, #28
    1996:	d505      	bpl.n	19a4 <z_cbvprintf_impl+0x708>
				OUTC('0');
    1998:	4659      	mov	r1, fp
    199a:	2030      	movs	r0, #48	; 0x30
    199c:	47c8      	blx	r9
    199e:	2800      	cmp	r0, #0
    19a0:	dbe0      	blt.n	1964 <z_cbvprintf_impl+0x6c8>
    19a2:	3501      	adds	r5, #1
			if (conv->altform_0c) {
    19a4:	9b05      	ldr	r3, [sp, #20]
    19a6:	b133      	cbz	r3, 19b6 <z_cbvprintf_impl+0x71a>
				OUTC(conv->specifier);
    19a8:	4659      	mov	r1, fp
    19aa:	f89d 0043 	ldrb.w	r0, [sp, #67]	; 0x43
    19ae:	47c8      	blx	r9
    19b0:	2800      	cmp	r0, #0
    19b2:	dbd7      	blt.n	1964 <z_cbvprintf_impl+0x6c8>
    19b4:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
    19b6:	9e04      	ldr	r6, [sp, #16]
    19b8:	442e      	add	r6, r5
    19ba:	e005      	b.n	19c8 <z_cbvprintf_impl+0x72c>
				OUTC('0');
    19bc:	4659      	mov	r1, fp
    19be:	2030      	movs	r0, #48	; 0x30
    19c0:	47c8      	blx	r9
    19c2:	2800      	cmp	r0, #0
    19c4:	dbce      	blt.n	1964 <z_cbvprintf_impl+0x6c8>
    19c6:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
    19c8:	1b73      	subs	r3, r6, r5
    19ca:	2b00      	cmp	r3, #0
    19cc:	dcf6      	bgt.n	19bc <z_cbvprintf_impl+0x720>
			OUTS(bps, bpe);
    19ce:	4653      	mov	r3, sl
    19d0:	463a      	mov	r2, r7
    19d2:	4659      	mov	r1, fp
    19d4:	4648      	mov	r0, r9
    19d6:	f007 fc48 	bl	926a <outs>
    19da:	2800      	cmp	r0, #0
    19dc:	dbc2      	blt.n	1964 <z_cbvprintf_impl+0x6c8>
    19de:	4405      	add	r5, r0
		while (width > 0) {
    19e0:	44a8      	add	r8, r5
    19e2:	eba8 0305 	sub.w	r3, r8, r5
    19e6:	2b00      	cmp	r3, #0
    19e8:	f77f ae6b 	ble.w	16c2 <z_cbvprintf_impl+0x426>
			OUTC(' ');
    19ec:	4659      	mov	r1, fp
    19ee:	2020      	movs	r0, #32
    19f0:	47c8      	blx	r9
    19f2:	2800      	cmp	r0, #0
    19f4:	dbb6      	blt.n	1964 <z_cbvprintf_impl+0x6c8>
    19f6:	3501      	adds	r5, #1
			--width;
    19f8:	e7f3      	b.n	19e2 <z_cbvprintf_impl+0x746>
    19fa:	bf00      	nop
    19fc:	0000a5c6 	.word	0x0000a5c6

00001a00 <mpsc_pbuf_init>:
	}
}

void mpsc_pbuf_init(struct mpsc_pbuf_buffer *buffer,
		    const struct mpsc_pbuf_buffer_config *cfg)
{
    1a00:	b538      	push	{r3, r4, r5, lr}
    1a02:	460d      	mov	r5, r1
    1a04:	4604      	mov	r4, r0
	int err;

	memset(buffer, 0, offsetof(struct mpsc_pbuf_buffer, buf));
    1a06:	2220      	movs	r2, #32
    1a08:	2100      	movs	r1, #0
    1a0a:	f007 fe0c 	bl	9626 <memset>
	buffer->get_wlen = cfg->get_wlen;
	buffer->notify_drop = cfg->notify_drop;
	buffer->buf = cfg->buf;
	buffer->size = cfg->size;
	buffer->max_usage = 0;
    1a0e:	2200      	movs	r2, #0
	buffer->get_wlen = cfg->get_wlen;
    1a10:	68eb      	ldr	r3, [r5, #12]
    1a12:	61e3      	str	r3, [r4, #28]
	buffer->notify_drop = cfg->notify_drop;
    1a14:	68ab      	ldr	r3, [r5, #8]
    1a16:	61a3      	str	r3, [r4, #24]
	buffer->buf = cfg->buf;
    1a18:	682b      	ldr	r3, [r5, #0]
    1a1a:	6223      	str	r3, [r4, #32]
	buffer->size = cfg->size;
    1a1c:	686b      	ldr	r3, [r5, #4]
	buffer->max_usage = 0;
    1a1e:	62a2      	str	r2, [r4, #40]	; 0x28
	buffer->size = cfg->size;
    1a20:	6263      	str	r3, [r4, #36]	; 0x24
	buffer->flags = cfg->flags;
    1a22:	692a      	ldr	r2, [r5, #16]
 * @param x value to check
 * @return true if @p x is a power of two, false otherwise
 */
static inline bool is_power_of_two(unsigned int x)
{
	return (x != 0U) && ((x & (x - 1U)) == 0U);
    1a24:	b123      	cbz	r3, 1a30 <mpsc_pbuf_init+0x30>
    1a26:	1e59      	subs	r1, r3, #1
    1a28:	4219      	tst	r1, r3

	if (is_power_of_two(buffer->size)) {
		buffer->flags |= MPSC_PBUF_SIZE_POW2;
    1a2a:	bf08      	it	eq
    1a2c:	f042 0201 	orreq.w	r2, r2, #1
	buffer->flags = cfg->flags;
    1a30:	6122      	str	r2, [r4, #16]
		union { uintptr_t x; unsigned int val; } parm2 = { .val = limit };
		return (int) arch_syscall_invoke3(parm0.x, parm1.x, parm2.x, K_SYSCALL_K_SEM_INIT);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_init(sem, initial_count, limit);
    1a32:	2201      	movs	r2, #1
    1a34:	2100      	movs	r1, #0
    1a36:	f104 002c 	add.w	r0, r4, #44	; 0x2c
    1a3a:	f008 f8bf 	bl	9bbc <z_impl_k_sem_init>
	}

	err = k_sem_init(&buffer->sem, 0, 1);
	__ASSERT_NO_MSG(err == 0);
    1a3e:	b148      	cbz	r0, 1a54 <mpsc_pbuf_init+0x54>
    1a40:	4905      	ldr	r1, [pc, #20]	; (1a58 <mpsc_pbuf_init+0x58>)
    1a42:	4806      	ldr	r0, [pc, #24]	; (1a5c <mpsc_pbuf_init+0x5c>)
    1a44:	232e      	movs	r3, #46	; 0x2e
    1a46:	4a06      	ldr	r2, [pc, #24]	; (1a60 <mpsc_pbuf_init+0x60>)
    1a48:	f007 fc2d 	bl	92a6 <assert_print>
    1a4c:	212e      	movs	r1, #46	; 0x2e
    1a4e:	4804      	ldr	r0, [pc, #16]	; (1a60 <mpsc_pbuf_init+0x60>)
    1a50:	f007 fc22 	bl	9298 <assert_post_action>
	ARG_UNUSED(err);
}
    1a54:	bd38      	pop	{r3, r4, r5, pc}
    1a56:	bf00      	nop
    1a58:	0000a5f2 	.word	0x0000a5f2
    1a5c:	0000a2e8 	.word	0x0000a2e8
    1a60:	0000a5cc 	.word	0x0000a5cc

00001a64 <mpsc_pbuf_alloc>:

}

union mpsc_pbuf_generic *mpsc_pbuf_alloc(struct mpsc_pbuf_buffer *buffer,
					 size_t wlen, k_timeout_t timeout)
{
    1a64:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1a68:	b087      	sub	sp, #28
    1a6a:	e9cd 2301 	strd	r2, r3, [sp, #4]
	uint32_t free_wlen;
	bool valid_drop;

	MPSC_PBUF_DBG(buffer, "alloc %d words, ", (int)wlen);

	if (wlen > (buffer->size - 1)) {
    1a6e:	6a43      	ldr	r3, [r0, #36]	; 0x24
{
    1a70:	4604      	mov	r4, r0
	if (wlen > (buffer->size - 1)) {
    1a72:	3b01      	subs	r3, #1
    1a74:	428b      	cmp	r3, r1
{
    1a76:	460f      	mov	r7, r1
	if (wlen > (buffer->size - 1)) {
    1a78:	f0c0 80a0 	bcc.w	1bbc <mpsc_pbuf_alloc+0x158>
	union mpsc_pbuf_generic *dropped_item = NULL;
    1a7c:	2600      	movs	r6, #0
	union mpsc_pbuf_generic *item = NULL;
    1a7e:	46b2      	mov	sl, r6
	do {
		k_spinlock_key_t key;
		bool wrap;

		cont = false;
		key = k_spin_lock(&buffer->lock);
    1a80:	f100 0514 	add.w	r5, r0, #20
	__asm__ volatile(
    1a84:	f04f 0320 	mov.w	r3, #32
    1a88:	f3ef 8b11 	mrs	fp, BASEPRI
    1a8c:	f383 8812 	msr	BASEPRI_MAX, r3
    1a90:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    1a94:	4628      	mov	r0, r5
	k.key = arch_irq_lock();
    1a96:	46d9      	mov	r9, fp
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    1a98:	f005 f998 	bl	6dcc <z_spin_lock_valid>
    1a9c:	b958      	cbnz	r0, 1ab6 <mpsc_pbuf_alloc+0x52>
    1a9e:	2394      	movs	r3, #148	; 0x94
    1aa0:	4a49      	ldr	r2, [pc, #292]	; (1bc8 <mpsc_pbuf_alloc+0x164>)
    1aa2:	494a      	ldr	r1, [pc, #296]	; (1bcc <mpsc_pbuf_alloc+0x168>)
    1aa4:	484a      	ldr	r0, [pc, #296]	; (1bd0 <mpsc_pbuf_alloc+0x16c>)
    1aa6:	f007 fbfe 	bl	92a6 <assert_print>
    1aaa:	4629      	mov	r1, r5
    1aac:	4849      	ldr	r0, [pc, #292]	; (1bd4 <mpsc_pbuf_alloc+0x170>)
    1aae:	f007 fbfa 	bl	92a6 <assert_print>
    1ab2:	2194      	movs	r1, #148	; 0x94
    1ab4:	e050      	b.n	1b58 <mpsc_pbuf_alloc+0xf4>
	z_spin_lock_set_owner(l);
    1ab6:	4628      	mov	r0, r5
    1ab8:	f005 f9a4 	bl	6e04 <z_spin_lock_set_owner>
		wrap = free_space(buffer, &free_wlen);
    1abc:	a905      	add	r1, sp, #20
    1abe:	4620      	mov	r0, r4
    1ac0:	f007 fbfe 	bl	92c0 <free_space>

		if (free_wlen >= wlen) {
    1ac4:	9905      	ldr	r1, [sp, #20]
		wrap = free_space(buffer, &free_wlen);
    1ac6:	4680      	mov	r8, r0
		if (free_wlen >= wlen) {
    1ac8:	42b9      	cmp	r1, r7
    1aca:	d328      	bcc.n	1b1e <mpsc_pbuf_alloc+0xba>
			item =
			    (union mpsc_pbuf_generic *)&buffer->buf[buffer->tmp_wr_idx];
    1acc:	6822      	ldr	r2, [r4, #0]
			item =
    1ace:	6a23      	ldr	r3, [r4, #32]
			item->hdr.valid = 0;
			item->hdr.busy = 0;
			buffer->tmp_wr_idx = idx_inc(buffer,
    1ad0:	4620      	mov	r0, r4
			item->hdr.valid = 0;
    1ad2:	f813 1022 	ldrb.w	r1, [r3, r2, lsl #2]
			item =
    1ad6:	eb03 0a82 	add.w	sl, r3, r2, lsl #2
			item->hdr.valid = 0;
    1ada:	f021 0103 	bic.w	r1, r1, #3
    1ade:	f803 1022 	strb.w	r1, [r3, r2, lsl #2]
			buffer->tmp_wr_idx = idx_inc(buffer,
    1ae2:	6821      	ldr	r1, [r4, #0]
    1ae4:	463a      	mov	r2, r7
    1ae6:	f007 fc0d 	bl	9304 <idx_inc>
		cont = false;
    1aea:	f04f 0800 	mov.w	r8, #0
			buffer->tmp_wr_idx = idx_inc(buffer,
    1aee:	6020      	str	r0, [r4, #0]
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    1af0:	4628      	mov	r0, r5
    1af2:	f005 f979 	bl	6de8 <z_spin_unlock_valid>
    1af6:	b320      	cbz	r0, 1b42 <mpsc_pbuf_alloc+0xde>
	__asm__ volatile(
    1af8:	f389 8811 	msr	BASEPRI, r9
    1afc:	f3bf 8f6f 	isb	sy
			cont = dropped_item != NULL;
		}

		k_spin_unlock(&buffer->lock, key);

		if (cont && dropped_item && valid_drop) {
    1b00:	f1b8 0f00 	cmp.w	r8, #0
    1b04:	d05c      	beq.n	1bc0 <mpsc_pbuf_alloc+0x15c>
    1b06:	b146      	cbz	r6, 1b1a <mpsc_pbuf_alloc+0xb6>
    1b08:	f89d 3013 	ldrb.w	r3, [sp, #19]
    1b0c:	2b00      	cmp	r3, #0
    1b0e:	d0b9      	beq.n	1a84 <mpsc_pbuf_alloc+0x20>
			/* Notify about item being dropped. */
			if (buffer->notify_drop) {
    1b10:	69a3      	ldr	r3, [r4, #24]
    1b12:	b113      	cbz	r3, 1b1a <mpsc_pbuf_alloc+0xb6>
				buffer->notify_drop(buffer, dropped_item);
    1b14:	4631      	mov	r1, r6
    1b16:	4620      	mov	r0, r4
    1b18:	4798      	blx	r3
{
    1b1a:	2600      	movs	r6, #0
    1b1c:	e7b2      	b.n	1a84 <mpsc_pbuf_alloc+0x20>
		} else if (wrap) {
    1b1e:	b118      	cbz	r0, 1b28 <mpsc_pbuf_alloc+0xc4>
			add_skip_item(buffer, free_wlen);
    1b20:	4620      	mov	r0, r4
    1b22:	f007 fbfd 	bl	9320 <add_skip_item>
			cont = true;
    1b26:	e7e3      	b.n	1af0 <mpsc_pbuf_alloc+0x8c>
		} else if (!K_TIMEOUT_EQ(timeout, K_NO_WAIT) &&
    1b28:	e9dd 3201 	ldrd	r3, r2, [sp, #4]
    1b2c:	4313      	orrs	r3, r2
    1b2e:	d036      	beq.n	1b9e <mpsc_pbuf_alloc+0x13a>
    1b30:	9103      	str	r1, [sp, #12]
			   !k_is_in_isr()) {
    1b32:	f008 f825 	bl	9b80 <k_is_in_isr>
		} else if (!K_TIMEOUT_EQ(timeout, K_NO_WAIT) &&
    1b36:	9903      	ldr	r1, [sp, #12]
    1b38:	bb88      	cbnz	r0, 1b9e <mpsc_pbuf_alloc+0x13a>
    1b3a:	4628      	mov	r0, r5
    1b3c:	f005 f954 	bl	6de8 <z_spin_unlock_valid>
    1b40:	b968      	cbnz	r0, 1b5e <mpsc_pbuf_alloc+0xfa>
    1b42:	23c2      	movs	r3, #194	; 0xc2
    1b44:	4a20      	ldr	r2, [pc, #128]	; (1bc8 <mpsc_pbuf_alloc+0x164>)
    1b46:	4924      	ldr	r1, [pc, #144]	; (1bd8 <mpsc_pbuf_alloc+0x174>)
    1b48:	4821      	ldr	r0, [pc, #132]	; (1bd0 <mpsc_pbuf_alloc+0x16c>)
    1b4a:	f007 fbac 	bl	92a6 <assert_print>
    1b4e:	4629      	mov	r1, r5
    1b50:	4822      	ldr	r0, [pc, #136]	; (1bdc <mpsc_pbuf_alloc+0x178>)
    1b52:	f007 fba8 	bl	92a6 <assert_print>
    1b56:	21c2      	movs	r1, #194	; 0xc2
    1b58:	481b      	ldr	r0, [pc, #108]	; (1bc8 <mpsc_pbuf_alloc+0x164>)
    1b5a:	f007 fb9d 	bl	9298 <assert_post_action>
    1b5e:	f38b 8811 	msr	BASEPRI, fp
    1b62:	f3bf 8f6f 	isb	sy
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm1 = { .val = timeout };
		return (int) arch_syscall_invoke3(parm0.x, parm1.split.lo, parm1.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    1b66:	f104 002c 	add.w	r0, r4, #44	; 0x2c
    1b6a:	e9dd 2301 	ldrd	r2, r3, [sp, #4]
    1b6e:	f005 fb1f 	bl	71b0 <z_impl_k_sem_take>
    1b72:	4680      	mov	r8, r0
	__asm__ volatile(
    1b74:	f04f 0320 	mov.w	r3, #32
    1b78:	f3ef 8911 	mrs	r9, BASEPRI
    1b7c:	f383 8812 	msr	BASEPRI_MAX, r3
    1b80:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    1b84:	4628      	mov	r0, r5
    1b86:	f005 f921 	bl	6dcc <z_spin_lock_valid>
    1b8a:	2800      	cmp	r0, #0
    1b8c:	d087      	beq.n	1a9e <mpsc_pbuf_alloc+0x3a>
			if (err == 0) {
    1b8e:	fab8 f888 	clz	r8, r8
	z_spin_lock_set_owner(l);
    1b92:	4628      	mov	r0, r5
    1b94:	f005 f936 	bl	6e04 <z_spin_lock_set_owner>
    1b98:	ea4f 1858 	mov.w	r8, r8, lsr #5
    1b9c:	e7a8      	b.n	1af0 <mpsc_pbuf_alloc+0x8c>
			bool user_drop = buffer->flags & MPSC_PBUF_MODE_OVERWRITE;
    1b9e:	6922      	ldr	r2, [r4, #16]
			dropped_item = drop_item_locked(buffer, free_wlen,
    1ba0:	4620      	mov	r0, r4
    1ba2:	f10d 0313 	add.w	r3, sp, #19
    1ba6:	f3c2 0240 	ubfx	r2, r2, #1, #1
    1baa:	f007 fbdc 	bl	9366 <drop_item_locked>
			cont = dropped_item != NULL;
    1bae:	f1b0 0800 	subs.w	r8, r0, #0
    1bb2:	4606      	mov	r6, r0
    1bb4:	bf18      	it	ne
    1bb6:	f04f 0801 	movne.w	r8, #1
    1bba:	e799      	b.n	1af0 <mpsc_pbuf_alloc+0x8c>
		return NULL;
    1bbc:	f04f 0a00 	mov.w	sl, #0
		/* During test fill with 0's to simplify message comparison */
		memset(item, 0, sizeof(int) * wlen);
	}

	return item;
}
    1bc0:	4650      	mov	r0, sl
    1bc2:	b007      	add	sp, #28
    1bc4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    1bc8:	0000a51d 	.word	0x0000a51d
    1bcc:	0000a576 	.word	0x0000a576
    1bd0:	0000a2e8 	.word	0x0000a2e8
    1bd4:	0000a58b 	.word	0x0000a58b
    1bd8:	0000a54a 	.word	0x0000a54a
    1bdc:	0000a561 	.word	0x0000a561

00001be0 <mpsc_pbuf_commit>:

void mpsc_pbuf_commit(struct mpsc_pbuf_buffer *buffer,
		       union mpsc_pbuf_generic *item)
{
    1be0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    1be4:	4604      	mov	r4, r0
	uint32_t wlen = buffer->get_wlen(item);
    1be6:	69c3      	ldr	r3, [r0, #28]
    1be8:	4608      	mov	r0, r1
{
    1bea:	460e      	mov	r6, r1
	uint32_t wlen = buffer->get_wlen(item);
    1bec:	4798      	blx	r3

	k_spinlock_key_t key = k_spin_lock(&buffer->lock);
    1bee:	f104 0514 	add.w	r5, r4, #20
	uint32_t wlen = buffer->get_wlen(item);
    1bf2:	4607      	mov	r7, r0
    1bf4:	f04f 0320 	mov.w	r3, #32
    1bf8:	f3ef 8811 	mrs	r8, BASEPRI
    1bfc:	f383 8812 	msr	BASEPRI_MAX, r3
    1c00:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    1c04:	4628      	mov	r0, r5
    1c06:	f005 f8e1 	bl	6dcc <z_spin_lock_valid>
    1c0a:	b968      	cbnz	r0, 1c28 <mpsc_pbuf_commit+0x48>
    1c0c:	2394      	movs	r3, #148	; 0x94
    1c0e:	4a19      	ldr	r2, [pc, #100]	; (1c74 <mpsc_pbuf_commit+0x94>)
    1c10:	4919      	ldr	r1, [pc, #100]	; (1c78 <mpsc_pbuf_commit+0x98>)
    1c12:	481a      	ldr	r0, [pc, #104]	; (1c7c <mpsc_pbuf_commit+0x9c>)
    1c14:	f007 fb47 	bl	92a6 <assert_print>
    1c18:	4629      	mov	r1, r5
    1c1a:	4819      	ldr	r0, [pc, #100]	; (1c80 <mpsc_pbuf_commit+0xa0>)
    1c1c:	f007 fb43 	bl	92a6 <assert_print>
    1c20:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    1c22:	4814      	ldr	r0, [pc, #80]	; (1c74 <mpsc_pbuf_commit+0x94>)
    1c24:	f007 fb38 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    1c28:	4628      	mov	r0, r5
    1c2a:	f005 f8eb 	bl	6e04 <z_spin_lock_set_owner>

	item->hdr.valid = 1;
    1c2e:	7833      	ldrb	r3, [r6, #0]
	buffer->wr_idx = idx_inc(buffer, buffer->wr_idx, wlen);
    1c30:	463a      	mov	r2, r7
	item->hdr.valid = 1;
    1c32:	f043 0301 	orr.w	r3, r3, #1
    1c36:	7033      	strb	r3, [r6, #0]
	buffer->wr_idx = idx_inc(buffer, buffer->wr_idx, wlen);
    1c38:	6861      	ldr	r1, [r4, #4]
    1c3a:	4620      	mov	r0, r4
    1c3c:	f007 fb62 	bl	9304 <idx_inc>
    1c40:	6060      	str	r0, [r4, #4]
	max_utilization_update(buffer);
    1c42:	4620      	mov	r0, r4
    1c44:	f007 fb82 	bl	934c <max_utilization_update>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    1c48:	4628      	mov	r0, r5
    1c4a:	f005 f8cd 	bl	6de8 <z_spin_unlock_valid>
    1c4e:	b958      	cbnz	r0, 1c68 <mpsc_pbuf_commit+0x88>
    1c50:	23c2      	movs	r3, #194	; 0xc2
    1c52:	4a08      	ldr	r2, [pc, #32]	; (1c74 <mpsc_pbuf_commit+0x94>)
    1c54:	490b      	ldr	r1, [pc, #44]	; (1c84 <mpsc_pbuf_commit+0xa4>)
    1c56:	4809      	ldr	r0, [pc, #36]	; (1c7c <mpsc_pbuf_commit+0x9c>)
    1c58:	f007 fb25 	bl	92a6 <assert_print>
    1c5c:	4629      	mov	r1, r5
    1c5e:	480a      	ldr	r0, [pc, #40]	; (1c88 <mpsc_pbuf_commit+0xa8>)
    1c60:	f007 fb21 	bl	92a6 <assert_print>
    1c64:	21c2      	movs	r1, #194	; 0xc2
    1c66:	e7dc      	b.n	1c22 <mpsc_pbuf_commit+0x42>
	__asm__ volatile(
    1c68:	f388 8811 	msr	BASEPRI, r8
    1c6c:	f3bf 8f6f 	isb	sy
	k_spin_unlock(&buffer->lock, key);
	MPSC_PBUF_DBG(buffer, "committed %p ", item);
}
    1c70:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    1c74:	0000a51d 	.word	0x0000a51d
    1c78:	0000a576 	.word	0x0000a576
    1c7c:	0000a2e8 	.word	0x0000a2e8
    1c80:	0000a58b 	.word	0x0000a58b
    1c84:	0000a54a 	.word	0x0000a54a
    1c88:	0000a561 	.word	0x0000a561

00001c8c <mpsc_pbuf_claim>:
		}
	} while (cont);
}

const union mpsc_pbuf_generic *mpsc_pbuf_claim(struct mpsc_pbuf_buffer *buffer)
{
    1c8c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    1c90:	4604      	mov	r4, r0
	do {
		uint32_t a;
		k_spinlock_key_t key;

		cont = false;
		key = k_spin_lock(&buffer->lock);
    1c92:	f100 0714 	add.w	r7, r0, #20
	__asm__ volatile(
    1c96:	f04f 0320 	mov.w	r3, #32
    1c9a:	f3ef 8811 	mrs	r8, BASEPRI
    1c9e:	f383 8812 	msr	BASEPRI_MAX, r3
    1ca2:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    1ca6:	4638      	mov	r0, r7
    1ca8:	f005 f890 	bl	6dcc <z_spin_lock_valid>
    1cac:	4605      	mov	r5, r0
    1cae:	b968      	cbnz	r0, 1ccc <mpsc_pbuf_claim+0x40>
    1cb0:	2394      	movs	r3, #148	; 0x94
    1cb2:	4a33      	ldr	r2, [pc, #204]	; (1d80 <mpsc_pbuf_claim+0xf4>)
    1cb4:	4933      	ldr	r1, [pc, #204]	; (1d84 <mpsc_pbuf_claim+0xf8>)
    1cb6:	4834      	ldr	r0, [pc, #208]	; (1d88 <mpsc_pbuf_claim+0xfc>)
    1cb8:	f007 faf5 	bl	92a6 <assert_print>
    1cbc:	4639      	mov	r1, r7
    1cbe:	4833      	ldr	r0, [pc, #204]	; (1d8c <mpsc_pbuf_claim+0x100>)
    1cc0:	f007 faf1 	bl	92a6 <assert_print>
    1cc4:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    1cc6:	482e      	ldr	r0, [pc, #184]	; (1d80 <mpsc_pbuf_claim+0xf4>)
    1cc8:	f007 fae6 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    1ccc:	4638      	mov	r0, r7
    1cce:	f005 f899 	bl	6e04 <z_spin_lock_set_owner>
	if (buffer->tmp_rd_idx <= buffer->wr_idx) {
    1cd2:	e9d4 3201 	ldrd	r3, r2, [r4, #4]
    1cd6:	429a      	cmp	r2, r3
	*res = buffer->size - buffer->tmp_rd_idx;
    1cd8:	bf88      	it	hi
    1cda:	6a63      	ldrhi	r3, [r4, #36]	; 0x24
    1cdc:	1a9b      	subs	r3, r3, r2
		(void)available(buffer, &a);
		item = (union mpsc_pbuf_generic *)
			&buffer->buf[buffer->tmp_rd_idx];

		if (!a || is_invalid(item)) {
    1cde:	2b00      	cmp	r3, #0
    1ce0:	d03f      	beq.n	1d62 <mpsc_pbuf_claim+0xd6>
		item = (union mpsc_pbuf_generic *)
    1ce2:	6a21      	ldr	r1, [r4, #32]
	return !item->hdr.valid && !item->hdr.busy;
    1ce4:	f811 3022 	ldrb.w	r3, [r1, r2, lsl #2]
		item = (union mpsc_pbuf_generic *)
    1ce8:	eb01 0982 	add.w	r9, r1, r2, lsl #2
		if (!a || is_invalid(item)) {
    1cec:	f013 0003 	ands.w	r0, r3, #3
    1cf0:	d03a      	beq.n	1d68 <mpsc_pbuf_claim+0xdc>
	if (item->hdr.busy && !item->hdr.valid) {
    1cf2:	2802      	cmp	r0, #2
    1cf4:	d103      	bne.n	1cfe <mpsc_pbuf_claim+0x72>
		return item->skip.len;
    1cf6:	f851 6022 	ldr.w	r6, [r1, r2, lsl #2]
			item = NULL;
		} else {
			uint32_t skip = get_skip(item);

			if (skip || !is_valid(item)) {
    1cfa:	08b6      	lsrs	r6, r6, #2
    1cfc:	d105      	bne.n	1d0a <mpsc_pbuf_claim+0x7e>
    1cfe:	07d8      	lsls	r0, r3, #31
    1d00:	d41f      	bmi.n	1d42 <mpsc_pbuf_claim+0xb6>
				uint32_t inc =
					skip ? skip : buffer->get_wlen(item);
    1d02:	4648      	mov	r0, r9
    1d04:	69e3      	ldr	r3, [r4, #28]
    1d06:	4798      	blx	r3
    1d08:	4606      	mov	r6, r0

				buffer->tmp_rd_idx =
				      idx_inc(buffer, buffer->tmp_rd_idx, inc);
    1d0a:	68a1      	ldr	r1, [r4, #8]
    1d0c:	4632      	mov	r2, r6
    1d0e:	4620      	mov	r0, r4
    1d10:	f007 faf8 	bl	9304 <idx_inc>
				buffer->rd_idx =
					idx_inc(buffer, buffer->rd_idx, inc);
    1d14:	68e1      	ldr	r1, [r4, #12]
				buffer->tmp_rd_idx =
    1d16:	60a0      	str	r0, [r4, #8]
					idx_inc(buffer, buffer->rd_idx, inc);
    1d18:	4632      	mov	r2, r6
    1d1a:	4620      	mov	r0, r4
    1d1c:	f007 faf2 	bl	9304 <idx_inc>
				buffer->rd_idx =
    1d20:	60e0      	str	r0, [r4, #12]
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    1d22:	4638      	mov	r0, r7
    1d24:	f005 f860 	bl	6de8 <z_spin_unlock_valid>
    1d28:	bb00      	cbnz	r0, 1d6c <mpsc_pbuf_claim+0xe0>
    1d2a:	23c2      	movs	r3, #194	; 0xc2
    1d2c:	4a14      	ldr	r2, [pc, #80]	; (1d80 <mpsc_pbuf_claim+0xf4>)
    1d2e:	4918      	ldr	r1, [pc, #96]	; (1d90 <mpsc_pbuf_claim+0x104>)
    1d30:	4815      	ldr	r0, [pc, #84]	; (1d88 <mpsc_pbuf_claim+0xfc>)
    1d32:	f007 fab8 	bl	92a6 <assert_print>
    1d36:	4639      	mov	r1, r7
    1d38:	4816      	ldr	r0, [pc, #88]	; (1d94 <mpsc_pbuf_claim+0x108>)
    1d3a:	f007 fab4 	bl	92a6 <assert_print>
    1d3e:	21c2      	movs	r1, #194	; 0xc2
    1d40:	e7c1      	b.n	1cc6 <mpsc_pbuf_claim+0x3a>
				cont = true;
			} else {
				item->hdr.busy = 1;
    1d42:	f043 0302 	orr.w	r3, r3, #2
    1d46:	f801 3022 	strb.w	r3, [r1, r2, lsl #2]
				buffer->tmp_rd_idx =
					idx_inc(buffer, buffer->tmp_rd_idx,
    1d4a:	69e3      	ldr	r3, [r4, #28]
    1d4c:	4648      	mov	r0, r9
    1d4e:	68a5      	ldr	r5, [r4, #8]
    1d50:	4798      	blx	r3
    1d52:	4629      	mov	r1, r5
    1d54:	4602      	mov	r2, r0
    1d56:	4620      	mov	r0, r4
    1d58:	f007 fad4 	bl	9304 <idx_inc>
		cont = false;
    1d5c:	2500      	movs	r5, #0
				buffer->tmp_rd_idx =
    1d5e:	60a0      	str	r0, [r4, #8]
    1d60:	e7df      	b.n	1d22 <mpsc_pbuf_claim+0x96>
		cont = false;
    1d62:	461d      	mov	r5, r3
			item = NULL;
    1d64:	46a9      	mov	r9, r5
    1d66:	e7dc      	b.n	1d22 <mpsc_pbuf_claim+0x96>
		cont = false;
    1d68:	4605      	mov	r5, r0
    1d6a:	e7fb      	b.n	1d64 <mpsc_pbuf_claim+0xd8>
	__asm__ volatile(
    1d6c:	f388 8811 	msr	BASEPRI, r8
    1d70:	f3bf 8f6f 	isb	sy

		if (!cont) {
			MPSC_PBUF_DBG(buffer, "claimed: %p ", item);
		}
		k_spin_unlock(&buffer->lock, key);
	} while (cont);
    1d74:	2d00      	cmp	r5, #0
    1d76:	d18e      	bne.n	1c96 <mpsc_pbuf_claim+0xa>

	return item;
}
    1d78:	4648      	mov	r0, r9
    1d7a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    1d7e:	bf00      	nop
    1d80:	0000a51d 	.word	0x0000a51d
    1d84:	0000a576 	.word	0x0000a576
    1d88:	0000a2e8 	.word	0x0000a2e8
    1d8c:	0000a58b 	.word	0x0000a58b
    1d90:	0000a54a 	.word	0x0000a54a
    1d94:	0000a561 	.word	0x0000a561

00001d98 <mpsc_pbuf_free>:

void mpsc_pbuf_free(struct mpsc_pbuf_buffer *buffer,
		     const union mpsc_pbuf_generic *item)
{
    1d98:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    1d9c:	4604      	mov	r4, r0
	uint32_t wlen = buffer->get_wlen(item);
    1d9e:	69c3      	ldr	r3, [r0, #28]
    1da0:	4608      	mov	r0, r1
{
    1da2:	460d      	mov	r5, r1
	uint32_t wlen = buffer->get_wlen(item);
    1da4:	4798      	blx	r3
	k_spinlock_key_t key = k_spin_lock(&buffer->lock);
    1da6:	f104 0614 	add.w	r6, r4, #20
	uint32_t wlen = buffer->get_wlen(item);
    1daa:	4607      	mov	r7, r0
	__asm__ volatile(
    1dac:	f04f 0320 	mov.w	r3, #32
    1db0:	f3ef 8811 	mrs	r8, BASEPRI
    1db4:	f383 8812 	msr	BASEPRI_MAX, r3
    1db8:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    1dbc:	4630      	mov	r0, r6
    1dbe:	f005 f805 	bl	6dcc <z_spin_lock_valid>
    1dc2:	b968      	cbnz	r0, 1de0 <mpsc_pbuf_free+0x48>
    1dc4:	2394      	movs	r3, #148	; 0x94
    1dc6:	4a23      	ldr	r2, [pc, #140]	; (1e54 <mpsc_pbuf_free+0xbc>)
    1dc8:	4923      	ldr	r1, [pc, #140]	; (1e58 <mpsc_pbuf_free+0xc0>)
    1dca:	4824      	ldr	r0, [pc, #144]	; (1e5c <mpsc_pbuf_free+0xc4>)
    1dcc:	f007 fa6b 	bl	92a6 <assert_print>
    1dd0:	4631      	mov	r1, r6
    1dd2:	4823      	ldr	r0, [pc, #140]	; (1e60 <mpsc_pbuf_free+0xc8>)
    1dd4:	f007 fa67 	bl	92a6 <assert_print>
    1dd8:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    1dda:	481e      	ldr	r0, [pc, #120]	; (1e54 <mpsc_pbuf_free+0xbc>)
    1ddc:	f007 fa5c 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    1de0:	4630      	mov	r0, r6
    1de2:	f005 f80f 	bl	6e04 <z_spin_lock_set_owner>
	union mpsc_pbuf_generic *witem = (union mpsc_pbuf_generic *)item;

	witem->hdr.valid = 0;
    1de6:	782b      	ldrb	r3, [r5, #0]
    1de8:	f36f 0300 	bfc	r3, #0, #1
    1dec:	702b      	strb	r3, [r5, #0]
	if (!(buffer->flags & MPSC_PBUF_MODE_OVERWRITE) ||
    1dee:	6923      	ldr	r3, [r4, #16]
    1df0:	079b      	lsls	r3, r3, #30
    1df2:	d505      	bpl.n	1e00 <mpsc_pbuf_free+0x68>
		 ((uint32_t *)item == &buffer->buf[buffer->rd_idx])) {
    1df4:	68e2      	ldr	r2, [r4, #12]
    1df6:	6a23      	ldr	r3, [r4, #32]
    1df8:	eb03 0382 	add.w	r3, r3, r2, lsl #2
	if (!(buffer->flags & MPSC_PBUF_MODE_OVERWRITE) ||
    1dfc:	429d      	cmp	r5, r3
    1dfe:	d119      	bne.n	1e34 <mpsc_pbuf_free+0x9c>
		witem->hdr.busy = 0;
    1e00:	782b      	ldrb	r3, [r5, #0]
		buffer->rd_idx = idx_inc(buffer, buffer->rd_idx, wlen);
    1e02:	463a      	mov	r2, r7
		witem->hdr.busy = 0;
    1e04:	f36f 0341 	bfc	r3, #1, #1
    1e08:	702b      	strb	r3, [r5, #0]
		buffer->rd_idx = idx_inc(buffer, buffer->rd_idx, wlen);
    1e0a:	68e1      	ldr	r1, [r4, #12]
    1e0c:	4620      	mov	r0, r4
    1e0e:	f007 fa79 	bl	9304 <idx_inc>
    1e12:	60e0      	str	r0, [r4, #12]
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    1e14:	4630      	mov	r0, r6
    1e16:	f004 ffe7 	bl	6de8 <z_spin_unlock_valid>
    1e1a:	b980      	cbnz	r0, 1e3e <mpsc_pbuf_free+0xa6>
    1e1c:	23c2      	movs	r3, #194	; 0xc2
    1e1e:	4a0d      	ldr	r2, [pc, #52]	; (1e54 <mpsc_pbuf_free+0xbc>)
    1e20:	4910      	ldr	r1, [pc, #64]	; (1e64 <mpsc_pbuf_free+0xcc>)
    1e22:	480e      	ldr	r0, [pc, #56]	; (1e5c <mpsc_pbuf_free+0xc4>)
    1e24:	f007 fa3f 	bl	92a6 <assert_print>
    1e28:	4631      	mov	r1, r6
    1e2a:	480f      	ldr	r0, [pc, #60]	; (1e68 <mpsc_pbuf_free+0xd0>)
    1e2c:	f007 fa3b 	bl	92a6 <assert_print>
    1e30:	21c2      	movs	r1, #194	; 0xc2
    1e32:	e7d2      	b.n	1dda <mpsc_pbuf_free+0x42>
	} else {
		witem->skip.len = wlen;
    1e34:	682b      	ldr	r3, [r5, #0]
    1e36:	f367 039f 	bfi	r3, r7, #2, #30
    1e3a:	602b      	str	r3, [r5, #0]
    1e3c:	e7ea      	b.n	1e14 <mpsc_pbuf_free+0x7c>
	__asm__ volatile(
    1e3e:	f388 8811 	msr	BASEPRI, r8
    1e42:	f3bf 8f6f 	isb	sy
		(void) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    1e46:	f104 002c 	add.w	r0, r4, #44	; 0x2c
	}
	MPSC_PBUF_DBG(buffer, "freed: %p ", item);

	k_spin_unlock(&buffer->lock, key);
	k_sem_give(&buffer->sem);
}
    1e4a:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    1e4e:	f005 b971 	b.w	7134 <z_impl_k_sem_give>
    1e52:	bf00      	nop
    1e54:	0000a51d 	.word	0x0000a51d
    1e58:	0000a576 	.word	0x0000a576
    1e5c:	0000a2e8 	.word	0x0000a2e8
    1e60:	0000a58b 	.word	0x0000a58b
    1e64:	0000a54a 	.word	0x0000a54a
    1e68:	0000a561 	.word	0x0000a561

00001e6c <sys_reboot>:
#include <zephyr/sys/printk.h>

extern void sys_arch_reboot(int type);

FUNC_NORETURN void sys_reboot(int type)
{
    1e6c:	b508      	push	{r3, lr}
	__asm__ volatile(
    1e6e:	f04f 0220 	mov.w	r2, #32
    1e72:	f3ef 8311 	mrs	r3, BASEPRI
    1e76:	f382 8812 	msr	BASEPRI_MAX, r2
    1e7a:	f3bf 8f6f 	isb	sy
	(void)irq_lock();
	sys_clock_disable();

	sys_arch_reboot(type);
    1e7e:	f001 ffe3 	bl	3e48 <sys_arch_reboot>

	/* should never get here */
	printk("Failed to reboot: spinning endlessly...\n");
    1e82:	4803      	ldr	r0, [pc, #12]	; (1e90 <sys_reboot+0x24>)
    1e84:	f007 f921 	bl	90ca <printk>
 * @note In some architectures, before returning, the function unmasks interrupts
 * unconditionally.
 */
static inline void k_cpu_idle(void)
{
	arch_cpu_idle();
    1e88:	f001 faae 	bl	33e8 <arch_cpu_idle>
    1e8c:	e7fc      	b.n	1e88 <sys_reboot+0x1c>
    1e8e:	bf00      	nop
    1e90:	0000a5fb 	.word	0x0000a5fb

00001e94 <nrf_gpio_pin_control_select.constprop.0>:

#if NRF_GPIO_HAS_SEL
NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl)
{
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_MCUSEL_Msk;
    1e94:	4b05      	ldr	r3, [pc, #20]	; (1eac <nrf_gpio_pin_control_select.constprop.0+0x18>)
    1e96:	eb03 0080 	add.w	r0, r3, r0, lsl #2
    1e9a:	f8d0 3200 	ldr.w	r3, [r0, #512]	; 0x200
    1e9e:	f023 43e0 	bic.w	r3, r3, #1879048192	; 0x70000000
    reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_MCUSEL_Pos);
    1ea2:	f043 5340 	orr.w	r3, r3, #805306368	; 0x30000000
    1ea6:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
}
    1eaa:	4770      	bx	lr
    1eac:	50842500 	.word	0x50842500

00001eb0 <nordicsemi_nrf53_init>:
	return true;
}
#endif /* CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND */

static int nordicsemi_nrf53_init(const struct device *arg)
{
    1eb0:	b538      	push	{r3, r4, r5, lr}
    1eb2:	f04f 0320 	mov.w	r3, #32
    1eb6:	f3ef 8511 	mrs	r5, BASEPRI
    1eba:	f383 8812 	msr	BASEPRI_MAX, r3
    1ebe:	f3bf 8f6f 	isb	sy

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_cache_enable(NRF_CACHE_Type * p_reg)
{
    p_reg->ENABLE = CACHE_ENABLE_ENABLE_Enabled;
    1ec2:	2101      	movs	r1, #1
    1ec4:	4b1a      	ldr	r3, [pc, #104]	; (1f30 <nordicsemi_nrf53_init+0x80>)
}

NRF_STATIC_INLINE void nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS_Type *     p_reg,
                                                    nrf_oscillators_lfxo_cap_t cap)
{
    p_reg->XOSC32KI.INTCAP = (uint32_t)cap;
    1ec6:	4a1b      	ldr	r2, [pc, #108]	; (1f34 <nordicsemi_nrf53_init+0x84>)
    1ec8:	f8c3 1500 	str.w	r1, [r3, #1280]	; 0x500
    1ecc:	2302      	movs	r3, #2
#if !defined(CONFIG_BUILD_WITH_TFM)
	/* This can only be done from secure code.
	 * This is handled by the TF-M platform so we skip it when TF-M is
	 * enabled.
	 */
	nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL);
    1ece:	2000      	movs	r0, #0
    1ed0:	f8c2 36d0 	str.w	r3, [r2, #1744]	; 0x6d0
    1ed4:	f7ff ffde 	bl	1e94 <nrf_gpio_pin_control_select.constprop.0>
	nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL);
    1ed8:	4608      	mov	r0, r1
    1eda:	f7ff ffdb 	bl	1e94 <nrf_gpio_pin_control_select.constprop.0>
	*((volatile uint32_t *)0x5000470C) = 0x7Eul;
    1ede:	237e      	movs	r3, #126	; 0x7e
	*((volatile uint32_t *)0x50002118) = 0x7Ful;
    1ee0:	207f      	movs	r0, #127	; 0x7f
	*((volatile uint32_t *)0x5000470C) = 0x7Eul;
    1ee2:	f8c2 370c 	str.w	r3, [r2, #1804]	; 0x70c
	*((volatile uint32_t *)0x5000493C) = 0x7Eul;
    1ee6:	f8c2 393c 	str.w	r3, [r2, #2364]	; 0x93c
	*((volatile uint32_t *)0x50002118) = 0x7Ful;
    1eea:	4b13      	ldr	r3, [pc, #76]	; (1f38 <nordicsemi_nrf53_init+0x88>)
	*((volatile uint32_t *)0x50039E04) = 0x0ul;
    1eec:	4c13      	ldr	r4, [pc, #76]	; (1f3c <nordicsemi_nrf53_init+0x8c>)
	*((volatile uint32_t *)0x50002118) = 0x7Ful;
    1eee:	f8c3 0118 	str.w	r0, [r3, #280]	; 0x118
	*((volatile uint32_t *)0x50039E04) = 0x0ul;
    1ef2:	2000      	movs	r0, #0
    1ef4:	f8c4 0e04 	str.w	r0, [r4, #3588]	; 0xe04
	*((volatile uint32_t *)0x50039E08) = 0x0ul;
    1ef8:	f8c4 0e08 	str.w	r0, [r4, #3592]	; 0xe08
	*((volatile uint32_t *)0x50101110) = 0x0ul;
    1efc:	f504 2448 	add.w	r4, r4, #819200	; 0xc8000
    1f00:	f8c4 0110 	str.w	r0, [r4, #272]	; 0x110
	*((volatile uint32_t *)0x50002124) = 0x0ul;
    1f04:	f8c3 0124 	str.w	r0, [r3, #292]	; 0x124
	*((volatile uint32_t *)0x5000212C) = 0x0ul;
    1f08:	f8c3 012c 	str.w	r0, [r3, #300]	; 0x12c
	*((volatile uint32_t *)0x502012A0) = 0x0ul;
    1f0c:	f503 13ff 	add.w	r3, r3, #2088960	; 0x1fe000
    1f10:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
    1f14:	f8c3 02a0 	str.w	r0, [r3, #672]	; 0x2a0
NRF_STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bool enable)
{
#if defined(REGULATORS_DCDCEN_DCDCEN_Msk)
    p_reg->DCDCEN = (enable ? REGULATORS_DCDCEN_DCDCEN_Msk : 0);
#else
    p_reg->VREGMAIN.DCDCEN = (enable ? REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Msk : 0);
    1f18:	f8c2 1704 	str.w	r1, [r2, #1796]	; 0x704
#endif

#if NRF_REGULATORS_HAS_DCDCEN_RADIO
NRF_STATIC_INLINE void nrf_regulators_dcdcen_radio_set(NRF_REGULATORS_Type * p_reg, bool enable)
{
    p_reg->VREGRADIO.DCDCEN = (enable) ? REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Enabled :
    1f1c:	f8c2 1904 	str.w	r1, [r2, #2308]	; 0x904
    p_reg->VREGH.DCDCEN = (enable) ? REGULATORS_VREGH_DCDCEN_DCDCEN_Enabled :
    1f20:	f8c2 1b00 	str.w	r1, [r2, #2816]	; 0xb00
	__asm__ volatile(
    1f24:	f385 8811 	msr	BASEPRI, r5
    1f28:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    1f2c:	bd38      	pop	{r3, r4, r5, pc}
    1f2e:	bf00      	nop
    1f30:	50001000 	.word	0x50001000
    1f34:	50004000 	.word	0x50004000
    1f38:	50002000 	.word	0x50002000
    1f3c:	50039000 	.word	0x50039000

00001f40 <z_arm_on_enter_cpu_idle>:
	uint8_t oldest = (current + 1) % ARRAY_SIZE(timestamps);
    1f40:	2305      	movs	r3, #5
{
    1f42:	b5f0      	push	{r4, r5, r6, r7, lr}
	uint8_t oldest = (current + 1) % ARRAY_SIZE(timestamps);
    1f44:	4d1d      	ldr	r5, [pc, #116]	; (1fbc <z_arm_on_enter_cpu_idle+0x7c>)
{
    1f46:	b087      	sub	sp, #28
	uint8_t oldest = (current + 1) % ARRAY_SIZE(timestamps);
    1f48:	782c      	ldrb	r4, [r5, #0]
    1f4a:	4f1d      	ldr	r7, [pc, #116]	; (1fc0 <z_arm_on_enter_cpu_idle+0x80>)
    1f4c:	3401      	adds	r4, #1
    1f4e:	fbb4 f3f3 	udiv	r3, r4, r3
    1f52:	eb03 0383 	add.w	r3, r3, r3, lsl #2
    1f56:	1ae4      	subs	r4, r4, r3
#ifndef _ASMLANGUAGE
extern uint32_t sys_clock_cycle_get_32(void);

static inline uint32_t arch_k_cycle_get_32(void)
{
	return sys_clock_cycle_get_32();
    1f58:	f007 fc76 	bl	9848 <sys_clock_cycle_get_32>
	if (timestamps_filled &&
    1f5c:	4a19      	ldr	r2, [pc, #100]	; (1fc4 <z_arm_on_enter_cpu_idle+0x84>)
    1f5e:	4e1a      	ldr	r6, [pc, #104]	; (1fc8 <z_arm_on_enter_cpu_idle+0x88>)
    1f60:	7813      	ldrb	r3, [r2, #0]
    1f62:	b1ab      	cbz	r3, 1f90 <z_arm_on_enter_cpu_idle+0x50>
	    (now - timestamps[oldest]) < (window_cycles + 1)) {
    1f64:	f857 3024 	ldr.w	r3, [r7, r4, lsl #2]
    1f68:	1ac0      	subs	r0, r0, r3
	if (timestamps_filled &&
    1f6a:	2807      	cmp	r0, #7
    1f6c:	d810      	bhi.n	1f90 <z_arm_on_enter_cpu_idle+0x50>
		if (!suppress_warning) {
    1f6e:	7833      	ldrb	r3, [r6, #0]
    1f70:	b95b      	cbnz	r3, 1f8a <z_arm_on_enter_cpu_idle+0x4a>
			LOG_WRN("Anomaly 160 trigger conditions detected.");
    1f72:	4a16      	ldr	r2, [pc, #88]	; (1fcc <z_arm_on_enter_cpu_idle+0x8c>)
    1f74:	9205      	str	r2, [sp, #20]
    1f76:	2202      	movs	r2, #2
    1f78:	9204      	str	r2, [sp, #16]
    1f7a:	f44f 5184 	mov.w	r1, #4224	; 0x1080
    1f7e:	4814      	ldr	r0, [pc, #80]	; (1fd0 <z_arm_on_enter_cpu_idle+0x90>)
    1f80:	aa04      	add	r2, sp, #16
    1f82:	f000 fc51 	bl	2828 <z_impl_z_log_msg_static_create>
			suppress_warning = true;
    1f86:	2301      	movs	r3, #1
    1f88:	7033      	strb	r3, [r6, #0]
		return false;
    1f8a:	2000      	movs	r0, #0
}
    1f8c:	b007      	add	sp, #28
    1f8e:	bdf0      	pop	{r4, r5, r6, r7, pc}
	suppress_warning = false;
    1f90:	2100      	movs	r1, #0
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE bool nrf_power_event_check(NRF_POWER_Type const * p_reg, nrf_power_event_t event)
{
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    1f92:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    1f96:	7031      	strb	r1, [r6, #0]
    1f98:	f8d3 0114 	ldr.w	r0, [r3, #276]	; 0x114
	if (nrf_power_event_check(NRF_POWER, NRF_POWER_EVENT_SLEEPENTER)) {
    1f9c:	b138      	cbz	r0, 1fae <z_arm_on_enter_cpu_idle+0x6e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    1f9e:	f8c3 1114 	str.w	r1, [r3, #276]	; 0x114
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    1fa2:	f8d3 3114 	ldr.w	r3, [r3, #276]	; 0x114
	uint8_t oldest = (current + 1) % ARRAY_SIZE(timestamps);
    1fa6:	702c      	strb	r4, [r5, #0]
		if (current == 0) {
    1fa8:	b90c      	cbnz	r4, 1fae <z_arm_on_enter_cpu_idle+0x6e>
			timestamps_filled = true;
    1faa:	2301      	movs	r3, #1
    1fac:	7013      	strb	r3, [r2, #0]
	timestamps[current] = k_cycle_get_32();
    1fae:	782c      	ldrb	r4, [r5, #0]
    1fb0:	f007 fc4a 	bl	9848 <sys_clock_cycle_get_32>
    1fb4:	f847 0024 	str.w	r0, [r7, r4, lsl #2]
	return true;
    1fb8:	2001      	movs	r0, #1
    1fba:	e7e7      	b.n	1f8c <z_arm_on_enter_cpu_idle+0x4c>
    1fbc:	200010c6 	.word	0x200010c6
    1fc0:	20000768 	.word	0x20000768
    1fc4:	200010c5 	.word	0x200010c5
    1fc8:	200010c4 	.word	0x200010c4
    1fcc:	0000a624 	.word	0x0000a624
    1fd0:	00009ff4 	.word	0x00009ff4

00001fd4 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    1fd4:	b148      	cbz	r0, 1fea <arch_busy_wait+0x16>

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    1fd6:	4b05      	ldr	r3, [pc, #20]	; (1fec <arch_busy_wait+0x18>)
    1fd8:	4a05      	ldr	r2, [pc, #20]	; (1ff0 <arch_busy_wait+0x1c>)
    1fda:	681b      	ldr	r3, [r3, #0]
    1fdc:	fbb3 f3f2 	udiv	r3, r3, r2
    delay_cycles(cycles);
    1fe0:	4358      	muls	r0, r3
    1fe2:	4b04      	ldr	r3, [pc, #16]	; (1ff4 <arch_busy_wait+0x20>)
    1fe4:	f043 0301 	orr.w	r3, r3, #1
    1fe8:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    1fea:	4770      	bx	lr
    1fec:	20000054 	.word	0x20000054
    1ff0:	000f4240 	.word	0x000f4240
    1ff4:	0000a020 	.word	0x0000a020

00001ff8 <pm_state_set>:
/* Invoke Low Power/System Off specific Tasks */
__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
{
	ARG_UNUSED(substate_id);

	switch (state) {
    1ff8:	2806      	cmp	r0, #6
    1ffa:	d107      	bne.n	200c <CONFIG_NRF_SPU_RAM_REGION_SIZE+0xc>
    p_reg->SYSTEMOFF = REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk;
    1ffc:	2201      	movs	r2, #1
    1ffe:	4b04      	ldr	r3, [pc, #16]	; (2010 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x10>)
    2000:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    2004:	f3bf 8f4f 	dsb	sy
        __WFE();
    2008:	bf20      	wfe
    while (true)
    200a:	e7fd      	b.n	2008 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x8>
		break;
	default:
		LOG_DBG("Unsupported power state %u", state);
		break;
	}
}
    200c:	4770      	bx	lr
    200e:	bf00      	nop
    2010:	50004000 	.word	0x50004000

00002014 <ppi_ipc_to_rtc.isra.0>:
    return (nrf_ipc_task_t)(NRFX_OFFSETOF(NRF_IPC_Type, TASKS_SEND[index]));
}

NRF_STATIC_INLINE nrf_ipc_event_t nrf_ipc_receive_event_get(uint8_t index)
{
    NRFX_ASSERT(index < IPC_CH_NUM);
    2014:	2a0f      	cmp	r2, #15
/* Setup or clear connection from IPC_RECEIVE to RTC_CAPTURE
 *
 * @param channels Details about channels
 * @param setup If true connection is setup, else it is cleared.
 */
static void ppi_ipc_to_rtc(union rtc_sync_channels channels, bool setup)
    2016:	b570      	push	{r4, r5, r6, lr}
    2018:	4605      	mov	r5, r0
    201a:	461e      	mov	r6, r3
    201c:	4608      	mov	r0, r1
    201e:	d90b      	bls.n	2038 <ppi_ipc_to_rtc.isra.0+0x24>
    2020:	491d      	ldr	r1, [pc, #116]	; (2098 <ppi_ipc_to_rtc.isra.0+0x84>)
    2022:	481e      	ldr	r0, [pc, #120]	; (209c <ppi_ipc_to_rtc.isra.0+0x88>)
    2024:	f240 13e7 	movw	r3, #487	; 0x1e7
    2028:	4a1d      	ldr	r2, [pc, #116]	; (20a0 <ppi_ipc_to_rtc.isra.0+0x8c>)
    202a:	f007 f93c 	bl	92a6 <assert_print>
    202e:	f240 11e7 	movw	r1, #487	; 0x1e7
    2032:	481b      	ldr	r0, [pc, #108]	; (20a0 <ppi_ipc_to_rtc.isra.0+0x8c>)
    *((volatile uint32_t *)(eep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
}

__STATIC_INLINE void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep)
{
    NRFX_ASSERT(tep);
    2034:	f007 f930 	bl	9298 <assert_post_action>
    return (nrf_ipc_event_t)(NRFX_OFFSETOF(NRF_IPC_Type, EVENTS_RECEIVE[index]));
    2038:	0094      	lsls	r4, r2, #2
{
	nrf_ipc_event_t ipc_evt = nrf_ipc_receive_event_get(channels.ch.ipc_in);
	uint32_t task_addr = z_nrf_rtc_timer_capture_task_address_get(channels.ch.rtc);
    203a:	f002 ffef 	bl	501c <z_nrf_rtc_timer_capture_task_address_get>

	if (setup) {
    203e:	f504 72c0 	add.w	r2, r4, #384	; 0x180
    2042:	b1ae      	cbz	r6, 2070 <ppi_ipc_to_rtc.isra.0+0x5c>
    2044:	b950      	cbnz	r0, 205c <ppi_ipc_to_rtc.isra.0+0x48>
    2046:	4917      	ldr	r1, [pc, #92]	; (20a4 <ppi_ipc_to_rtc.isra.0+0x90>)
    2048:	f240 234e 	movw	r3, #590	; 0x24e
    204c:	4a16      	ldr	r2, [pc, #88]	; (20a8 <ppi_ipc_to_rtc.isra.0+0x94>)
    204e:	4813      	ldr	r0, [pc, #76]	; (209c <ppi_ipc_to_rtc.isra.0+0x88>)
    2050:	f007 f929 	bl	92a6 <assert_print>
    2054:	f240 214e 	movw	r1, #590	; 0x24e
    2058:	4813      	ldr	r0, [pc, #76]	; (20a8 <ppi_ipc_to_rtc.isra.0+0x94>)
    205a:	e7eb      	b.n	2034 <ppi_ipc_to_rtc.isra.0+0x20>
    *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
    205c:	f102 42a0 	add.w	r2, r2, #1342177280	; 0x50000000
    *((volatile uint32_t *)(tep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
    2060:	f045 4500 	orr.w	r5, r5, #2147483648	; 0x80000000
    2064:	f502 3228 	add.w	r2, r2, #172032	; 0x2a000
    2068:	f8c0 5080 	str.w	r5, [r0, #128]	; 0x80
    206c:	6015      	str	r5, [r2, #0]
		nrf_ipc_publish_set(NRF_IPC, ipc_evt, channels.ch.ppi);
	} else {
		nrfx_gppi_task_endpoint_clear(channels.ch.ppi, task_addr);
		nrf_ipc_publish_clear(NRF_IPC, ipc_evt);
	}
}
    206e:	bd70      	pop	{r4, r5, r6, pc}
    *((volatile uint32_t *)(eep + 0x80uL)) = 0;
}

__STATIC_INLINE void nrfx_gppi_task_endpoint_clear(uint8_t channel, uint32_t tep)
{
    NRFX_ASSERT(tep);
    2070:	b948      	cbnz	r0, 2086 <ppi_ipc_to_rtc.isra.0+0x72>
    2072:	490c      	ldr	r1, [pc, #48]	; (20a4 <ppi_ipc_to_rtc.isra.0+0x90>)
    2074:	f240 2363 	movw	r3, #611	; 0x263
    2078:	4a0b      	ldr	r2, [pc, #44]	; (20a8 <ppi_ipc_to_rtc.isra.0+0x94>)
    207a:	4808      	ldr	r0, [pc, #32]	; (209c <ppi_ipc_to_rtc.isra.0+0x88>)
    207c:	f007 f913 	bl	92a6 <assert_print>
    2080:	f240 2163 	movw	r1, #611	; 0x263
    2084:	e7e8      	b.n	2058 <ppi_ipc_to_rtc.isra.0+0x44>
    *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
    2086:	f102 42a0 	add.w	r2, r2, #1342177280	; 0x50000000
    208a:	f502 3228 	add.w	r2, r2, #172032	; 0x2a000
    (void)channel;
    *((volatile uint32_t *)(tep + 0x80uL)) = 0;
    208e:	f8c0 6080 	str.w	r6, [r0, #128]	; 0x80
    2092:	6016      	str	r6, [r2, #0]
    2094:	e7eb      	b.n	206e <ppi_ipc_to_rtc.isra.0+0x5a>
    2096:	bf00      	nop
    2098:	0000a683 	.word	0x0000a683
    209c:	0000a2e8 	.word	0x0000a2e8
    20a0:	0000a651 	.word	0x0000a651
    20a4:	0000a6c6 	.word	0x0000a6c6
    20a8:	0000a68e 	.word	0x0000a68e

000020ac <sync_rtc_setup>:
	return mbox_set_enabled(&channel, true);
}

/* Setup RTC synchronization. */
static int sync_rtc_setup(const struct device *unused)
{
    20ac:	b5f0      	push	{r4, r5, r6, r7, lr}
    20ae:	b083      	sub	sp, #12
    20b0:	af00      	add	r7, sp, #0
	nrfx_err_t err;
	union rtc_sync_channels channels;
	int32_t sync_rtc_ch;
	int rv;

	err = nrfx_dppi_channel_alloc(&channels.ch.ppi);
    20b2:	1d38      	adds	r0, r7, #4
    20b4:	f003 fe6c 	bl	5d90 <nrfx_dppi_channel_alloc>
	if (err != NRFX_SUCCESS) {
    20b8:	4b24      	ldr	r3, [pc, #144]	; (214c <sync_rtc_setup+0xa0>)
    20ba:	4298      	cmp	r0, r3
    20bc:	d143      	bne.n	2146 <sync_rtc_setup+0x9a>
		rv = -ENODEV;
		goto bail;
	}

	sync_rtc_ch = z_nrf_rtc_timer_chan_alloc();
    20be:	f003 f973 	bl	53a8 <z_nrf_rtc_timer_chan_alloc>
	if (sync_rtc_ch < 0) {
    20c2:	1e04      	subs	r4, r0, #0
    20c4:	da13      	bge.n	20ee <sync_rtc_setup+0x42>
		nrfx_dppi_channel_free(channels.ch.ppi);
    20c6:	7938      	ldrb	r0, [r7, #4]
    20c8:	f003 fe68 	bl	5d9c <nrfx_dppi_channel_free>
		irq_unlock(key);
	}

bail:
	if (rv != 0) {
		LOG_ERR("Failed synchronized RTC setup (err: %d)", rv);
    20cc:	466d      	mov	r5, sp
    20ce:	b088      	sub	sp, #32
    20d0:	466a      	mov	r2, sp
    20d2:	4b1f      	ldr	r3, [pc, #124]	; (2150 <sync_rtc_setup+0xa4>)
    20d4:	e9c2 3405 	strd	r3, r4, [r2, #20]
    20d8:	2303      	movs	r3, #3
    20da:	f842 3f10 	str.w	r3, [r2, #16]!
    20de:	2300      	movs	r3, #0
    20e0:	f44f 51c2 	mov.w	r1, #6208	; 0x1840
    20e4:	481b      	ldr	r0, [pc, #108]	; (2154 <sync_rtc_setup+0xa8>)
    20e6:	f000 fb9f 	bl	2828 <z_impl_z_log_msg_static_create>
    20ea:	46ad      	mov	sp, r5
	}

	return rv;
    20ec:	e027      	b.n	213e <sync_rtc_setup+0x92>
	channels.ch.ipc_out = CONFIG_NRF53_SYNC_RTC_IPM_OUT;
    20ee:	f640 0307 	movw	r3, #2055	; 0x807
 */
static inline int mbox_register_callback(const struct mbox_channel *channel,
					 mbox_callback_t cb,
					 void *user_data)
{
	const struct mbox_driver_api *api =
    20f2:	4d19      	ldr	r5, [pc, #100]	; (2158 <sync_rtc_setup+0xac>)
	channels.ch.rtc = (uint8_t)sync_rtc_ch;
    20f4:	717c      	strb	r4, [r7, #5]
		(const struct mbox_driver_api *)channel->dev->api;

	if (api->register_callback == NULL) {
    20f6:	68ae      	ldr	r6, [r5, #8]
	channels.ch.ipc_out = CONFIG_NRF53_SYNC_RTC_IPM_OUT;
    20f8:	80fb      	strh	r3, [r7, #6]
    20fa:	6874      	ldr	r4, [r6, #4]
	rv = mbox_rx_init((void *)channels.raw);
    20fc:	687b      	ldr	r3, [r7, #4]
    20fe:	b914      	cbnz	r4, 2106 <sync_rtc_setup+0x5a>
		return -ENOSYS;
    2100:	f06f 0457 	mvn.w	r4, #87	; 0x57
    2104:	e7e2      	b.n	20cc <sync_rtc_setup+0x20>
	}

	return api->register_callback(channel->dev, channel->id, cb, user_data);
    2106:	2108      	movs	r1, #8
    2108:	4628      	mov	r0, r5
    210a:	4a14      	ldr	r2, [pc, #80]	; (215c <sync_rtc_setup+0xb0>)
    210c:	47a0      	blx	r4
	if (err < 0) {
    210e:	1e04      	subs	r4, r0, #0
    2110:	dbdc      	blt.n	20cc <sync_rtc_setup+0x20>
static inline int z_impl_mbox_set_enabled(const struct mbox_channel *channel, bool enable)
{
	const struct mbox_driver_api *api =
		(const struct mbox_driver_api *)channel->dev->api;

	if (api->set_enabled == NULL) {
    2112:	6933      	ldr	r3, [r6, #16]
    2114:	2b00      	cmp	r3, #0
    2116:	d0f3      	beq.n	2100 <sync_rtc_setup+0x54>
		return -ENOSYS;
	}

	return api->set_enabled(channel->dev, channel->id, enable);
    2118:	2201      	movs	r2, #1
    211a:	2108      	movs	r1, #8
    211c:	4628      	mov	r0, r5
    211e:	4798      	blx	r3
	if (rv < 0) {
    2120:	1e04      	subs	r4, r0, #0
    2122:	dbd3      	blt.n	20cc <sync_rtc_setup+0x20>
	nrfx_gppi_channels_enable(BIT(channels.ch.ppi));
    2124:	2301      	movs	r3, #1
    2126:	7938      	ldrb	r0, [r7, #4]
    p_reg->CHENCLR = 0xFFFFFFFFuL;
}

NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask)
{
    p_reg->CHENSET = mask;
    2128:	4a0d      	ldr	r2, [pc, #52]	; (2160 <sync_rtc_setup+0xb4>)
    212a:	fa03 f100 	lsl.w	r1, r3, r0
    212e:	f8c2 1504 	str.w	r1, [r2, #1284]	; 0x504
		ppi_ipc_to_rtc(channels, true);
    2132:	79fa      	ldrb	r2, [r7, #7]
    2134:	7979      	ldrb	r1, [r7, #5]
    2136:	f7ff ff6d 	bl	2014 <ppi_ipc_to_rtc.isra.0>
	if (rv != 0) {
    213a:	2c00      	cmp	r4, #0
    213c:	d1c6      	bne.n	20cc <sync_rtc_setup+0x20>
}
    213e:	4620      	mov	r0, r4
    2140:	370c      	adds	r7, #12
    2142:	46bd      	mov	sp, r7
    2144:	bdf0      	pop	{r4, r5, r6, r7, pc}
		rv = -ENODEV;
    2146:	f06f 0412 	mvn.w	r4, #18
    214a:	e7bf      	b.n	20cc <sync_rtc_setup+0x20>
    214c:	0bad0000 	.word	0x0bad0000
    2150:	0000a6ca 	.word	0x0000a6ca
    2154:	00009ffc 	.word	0x00009ffc
    2158:	00009d24 	.word	0x00009d24
    215c:	00002215 	.word	0x00002215
    2160:	50017000 	.word	0x50017000

00002164 <rtc_cb>:
{
    2164:	b570      	push	{r4, r5, r6, lr}
    2166:	9e04      	ldr	r6, [sp, #16]
    2168:	f3c6 4407 	ubfx	r4, r6, #16, #8
static void ppi_rtc_to_ipc(union rtc_sync_channels channels, bool setup)
    216c:	b2f5      	uxtb	r5, r6
	uint32_t evt_addr = z_nrf_rtc_timer_compare_evt_address_get(channels.ch.rtc);
    216e:	f3c6 2607 	ubfx	r6, r6, #8, #8
    2172:	4630      	mov	r0, r6
    2174:	f002 ff38 	bl	4fe8 <z_nrf_rtc_timer_compare_evt_address_get>
    NRFX_ASSERT(index < IPC_CH_NUM);
    2178:	2c0f      	cmp	r4, #15
    217a:	d90b      	bls.n	2194 <rtc_cb+0x30>
    217c:	491b      	ldr	r1, [pc, #108]	; (21ec <rtc_cb+0x88>)
    217e:	481c      	ldr	r0, [pc, #112]	; (21f0 <rtc_cb+0x8c>)
    2180:	f240 13e1 	movw	r3, #481	; 0x1e1
    2184:	4a1b      	ldr	r2, [pc, #108]	; (21f4 <rtc_cb+0x90>)
    2186:	f007 f88e 	bl	92a6 <assert_print>
    218a:	f240 11e1 	movw	r1, #481	; 0x1e1
    218e:	4819      	ldr	r0, [pc, #100]	; (21f4 <rtc_cb+0x90>)
    NRFX_ASSERT(eep);
    2190:	f007 f882 	bl	9298 <assert_post_action>
    return (nrf_ipc_task_t)(NRFX_OFFSETOF(NRF_IPC_Type, TASKS_SEND[index]));
    2194:	00a4      	lsls	r4, r4, #2
    2196:	b2e4      	uxtb	r4, r4
    2198:	b950      	cbnz	r0, 21b0 <rtc_cb+0x4c>
    219a:	4917      	ldr	r1, [pc, #92]	; (21f8 <rtc_cb+0x94>)
    219c:	4814      	ldr	r0, [pc, #80]	; (21f0 <rtc_cb+0x8c>)
    219e:	f44f 7317 	mov.w	r3, #604	; 0x25c
    21a2:	4a16      	ldr	r2, [pc, #88]	; (21fc <rtc_cb+0x98>)
    21a4:	f007 f87f 	bl	92a6 <assert_print>
    21a8:	f44f 7117 	mov.w	r1, #604	; 0x25c
    21ac:	4813      	ldr	r0, [pc, #76]	; (21fc <rtc_cb+0x98>)
    21ae:	e7ef      	b.n	2190 <rtc_cb+0x2c>
    *((volatile uint32_t *)(eep + 0x80uL)) = 0;
    21b0:	2200      	movs	r2, #0
    *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
    21b2:	4b13      	ldr	r3, [pc, #76]	; (2200 <rtc_cb+0x9c>)
    21b4:	f8c0 2080 	str.w	r2, [r0, #128]	; 0x80
    21b8:	511a      	str	r2, [r3, r4]
	nrfx_gppi_channels_disable(BIT(channels.ch.ppi));
    21ba:	2301      	movs	r3, #1
}

NRF_STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask)
{
    p_reg->CHENCLR = mask;
    21bc:	4a11      	ldr	r2, [pc, #68]	; (2204 <rtc_cb+0xa0>)
    21be:	40ab      	lsls	r3, r5
    21c0:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
	z_nrf_rtc_timer_chan_free(channels.ch.rtc);
    21c4:	4630      	mov	r0, r6
    21c6:	f003 f90d 	bl	53e4 <z_nrf_rtc_timer_chan_free>
	err = nrfx_dppi_channel_free(channels.ch.ppi);
    21ca:	4628      	mov	r0, r5
    21cc:	f003 fde6 	bl	5d9c <nrfx_dppi_channel_free>
	__ASSERT_NO_MSG(err == NRFX_SUCCESS);
    21d0:	4b0d      	ldr	r3, [pc, #52]	; (2208 <rtc_cb+0xa4>)
    21d2:	4298      	cmp	r0, r3
    21d4:	d008      	beq.n	21e8 <rtc_cb+0x84>
    21d6:	490d      	ldr	r1, [pc, #52]	; (220c <rtc_cb+0xa8>)
    21d8:	4805      	ldr	r0, [pc, #20]	; (21f0 <rtc_cb+0x8c>)
    21da:	2374      	movs	r3, #116	; 0x74
    21dc:	4a0c      	ldr	r2, [pc, #48]	; (2210 <rtc_cb+0xac>)
    21de:	f007 f862 	bl	92a6 <assert_print>
    21e2:	2174      	movs	r1, #116	; 0x74
    21e4:	480a      	ldr	r0, [pc, #40]	; (2210 <rtc_cb+0xac>)
    21e6:	e7d3      	b.n	2190 <rtc_cb+0x2c>
}
    21e8:	bd70      	pop	{r4, r5, r6, pc}
    21ea:	bf00      	nop
    21ec:	0000a683 	.word	0x0000a683
    21f0:	0000a2e8 	.word	0x0000a2e8
    21f4:	0000a651 	.word	0x0000a651
    21f8:	0000a6f2 	.word	0x0000a6f2
    21fc:	0000a68e 	.word	0x0000a68e
    2200:	5002a080 	.word	0x5002a080
    2204:	50017000 	.word	0x50017000
    2208:	0bad0000 	.word	0x0bad0000
    220c:	0000a72d 	.word	0x0000a72d
    2210:	0000a6f6 	.word	0x0000a6f6

00002214 <mbox_callback>:
{
    2214:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    2218:	4614      	mov	r4, r2
	if (api->set_enabled == NULL) {
    221a:	6883      	ldr	r3, [r0, #8]
    221c:	691b      	ldr	r3, [r3, #16]
    221e:	b94b      	cbnz	r3, 2234 <mbox_callback+0x20>
	__ASSERT_NO_MSG(err == 0);
    2220:	4927      	ldr	r1, [pc, #156]	; (22c0 <mbox_callback+0xac>)
    2222:	4828      	ldr	r0, [pc, #160]	; (22c4 <mbox_callback+0xb0>)
    2224:	23ca      	movs	r3, #202	; 0xca
    2226:	4a28      	ldr	r2, [pc, #160]	; (22c8 <mbox_callback+0xb4>)
    2228:	f007 f83d 	bl	92a6 <assert_print>
    222c:	21ca      	movs	r1, #202	; 0xca
    222e:	4826      	ldr	r0, [pc, #152]	; (22c8 <mbox_callback+0xb4>)
    NRFX_ASSERT(index < IPC_CH_NUM);
    2230:	f007 f832 	bl	9298 <assert_post_action>
	return api->set_enabled(channel->dev, channel->id, enable);
    2234:	2200      	movs	r2, #0
    2236:	4798      	blx	r3
    2238:	4606      	mov	r6, r0
    223a:	2800      	cmp	r0, #0
    223c:	d1f0      	bne.n	2220 <mbox_callback+0xc>
	cc = z_nrf_rtc_timer_compare_read(channels.ch.rtc);
    223e:	f3c4 2907 	ubfx	r9, r4, #8, #8
    2242:	4648      	mov	r0, r9
    2244:	f002 ff04 	bl	5050 <z_nrf_rtc_timer_compare_read>
	ppi_ipc_to_rtc(channels, false);
    2248:	fa5f f884 	uxtb.w	r8, r4
    224c:	4633      	mov	r3, r6
    224e:	4649      	mov	r1, r9
    2250:	0e22      	lsrs	r2, r4, #24
	cc = z_nrf_rtc_timer_compare_read(channels.ch.rtc);
    2252:	4607      	mov	r7, r0
	ppi_ipc_to_rtc(channels, false);
    2254:	4640      	mov	r0, r8
    2256:	f7ff fedd 	bl	2014 <ppi_ipc_to_rtc.isra.0>
		ppi_rtc_to_ipc(channels, true);
    225a:	f3c4 4507 	ubfx	r5, r4, #16, #8
	uint32_t evt_addr = z_nrf_rtc_timer_compare_evt_address_get(channels.ch.rtc);
    225e:	4648      	mov	r0, r9
    2260:	f002 fec2 	bl	4fe8 <z_nrf_rtc_timer_compare_evt_address_get>
    2264:	2d0f      	cmp	r5, #15
    2266:	d90a      	bls.n	227e <mbox_callback+0x6a>
    2268:	4918      	ldr	r1, [pc, #96]	; (22cc <mbox_callback+0xb8>)
    226a:	4816      	ldr	r0, [pc, #88]	; (22c4 <mbox_callback+0xb0>)
    226c:	f240 13e1 	movw	r3, #481	; 0x1e1
    2270:	4a17      	ldr	r2, [pc, #92]	; (22d0 <mbox_callback+0xbc>)
    2272:	f007 f818 	bl	92a6 <assert_print>
    2276:	f240 11e1 	movw	r1, #481	; 0x1e1
    227a:	4815      	ldr	r0, [pc, #84]	; (22d0 <mbox_callback+0xbc>)
    227c:	e7d8      	b.n	2230 <mbox_callback+0x1c>
    *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
    227e:	4a15      	ldr	r2, [pc, #84]	; (22d4 <mbox_callback+0xc0>)
    return (nrf_ipc_task_t)(NRFX_OFFSETOF(NRF_IPC_Type, TASKS_SEND[index]));
    2280:	00ad      	lsls	r5, r5, #2
    *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
    2282:	b2ed      	uxtb	r5, r5
            ((uint32_t)channel | IPC_SUBSCRIBE_SEND_EN_Msk);
    2284:	f048 4300 	orr.w	r3, r8, #2147483648	; 0x80000000
    *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
    2288:	5153      	str	r3, [r2, r5]
    NRFX_ASSERT(eep);
    228a:	b950      	cbnz	r0, 22a2 <mbox_callback+0x8e>
    228c:	4912      	ldr	r1, [pc, #72]	; (22d8 <mbox_callback+0xc4>)
    228e:	480d      	ldr	r0, [pc, #52]	; (22c4 <mbox_callback+0xb0>)
    2290:	f44f 7312 	mov.w	r3, #584	; 0x248
    2294:	4a11      	ldr	r2, [pc, #68]	; (22dc <mbox_callback+0xc8>)
    2296:	f007 f806 	bl	92a6 <assert_print>
    229a:	f44f 7112 	mov.w	r1, #584	; 0x248
    229e:	480f      	ldr	r0, [pc, #60]	; (22dc <mbox_callback+0xc8>)
    22a0:	e7c6      	b.n	2230 <mbox_callback+0x1c>
    *((volatile uint32_t *)(eep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
    22a2:	f8c0 3080 	str.w	r3, [r0, #128]	; 0x80
		z_nrf_rtc_timer_set(channels.ch.rtc, cc + cc + RTC_SYNC_ARBITRARY_DELAY,
    22a6:	4b0e      	ldr	r3, [pc, #56]	; (22e0 <mbox_callback+0xcc>)
    22a8:	f107 0232 	add.w	r2, r7, #50	; 0x32
    22ac:	9300      	str	r3, [sp, #0]
    22ae:	4648      	mov	r0, r9
    22b0:	4633      	mov	r3, r6
    22b2:	9401      	str	r4, [sp, #4]
    22b4:	0052      	lsls	r2, r2, #1
    22b6:	f002 ff93 	bl	51e0 <z_nrf_rtc_timer_set>
}
    22ba:	b003      	add	sp, #12
    22bc:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    22c0:	0000a5f2 	.word	0x0000a5f2
    22c4:	0000a2e8 	.word	0x0000a2e8
    22c8:	0000a6f6 	.word	0x0000a6f6
    22cc:	0000a683 	.word	0x0000a683
    22d0:	0000a651 	.word	0x0000a651
    22d4:	5002a080 	.word	0x5002a080
    22d8:	0000a6f2 	.word	0x0000a6f2
    22dc:	0000a68e 	.word	0x0000a68e
    22e0:	00002165 	.word	0x00002165

000022e4 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    22e4:	f003 ba54 	b.w	5790 <SystemInit>

000022e8 <z_log_init.isra.0>:
	}

	return mask;
}

static uint32_t z_log_init(bool blocking, bool can_sleep)
    22e8:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
 */
static inline int log_backend_count_get(void)
{
	int cnt;

	STRUCT_SECTION_COUNT(log_backend, &cnt);
    22ec:	f8df a0fc 	ldr.w	sl, [pc, #252]	; 23ec <z_log_init.isra.0+0x104>
    22f0:	4f3f      	ldr	r7, [pc, #252]	; (23f0 <z_log_init.isra.0+0x108>)
    22f2:	4681      	mov	r9, r0
    22f4:	ebaa 0307 	sub.w	r3, sl, r7

	if (IS_ENABLED(CONFIG_LOG_FRONTEND_ONLY)) {
		return 0;
	}

	__ASSERT_NO_MSG(log_backend_count_get() < LOG_FILTERS_NUM_OF_SLOTS);
    22f8:	2b9f      	cmp	r3, #159	; 0x9f
static uint32_t z_log_init(bool blocking, bool can_sleep)
    22fa:	4688      	mov	r8, r1
	__ASSERT_NO_MSG(log_backend_count_get() < LOG_FILTERS_NUM_OF_SLOTS);
    22fc:	d90b      	bls.n	2316 <z_log_init.isra.0+0x2e>
    22fe:	493d      	ldr	r1, [pc, #244]	; (23f4 <z_log_init.isra.0+0x10c>)
    2300:	f240 1315 	movw	r3, #277	; 0x115
    2304:	4a3c      	ldr	r2, [pc, #240]	; (23f8 <z_log_init.isra.0+0x110>)
    2306:	483d      	ldr	r0, [pc, #244]	; (23fc <z_log_init.isra.0+0x114>)
    2308:	f006 ffcd 	bl	92a6 <assert_print>
    230c:	f240 1115 	movw	r1, #277	; 0x115
		z_log_links_initiate();
	}


	/* Assign ids to backends. */
	STRUCT_SECTION_FOREACH(log_backend, backend) {
    2310:	4839      	ldr	r0, [pc, #228]	; (23f8 <z_log_init.isra.0+0x110>)
    2312:	f006 ffc1 	bl	9298 <assert_post_action>
	if (atomic_inc(&initialized) != 0) {
    2316:	483a      	ldr	r0, [pc, #232]	; (2400 <z_log_init.isra.0+0x118>)
    2318:	f007 f8a5 	bl	9466 <atomic_inc>
    231c:	4606      	mov	r6, r0
    231e:	2800      	cmp	r0, #0
    2320:	d134      	bne.n	238c <z_log_init.isra.0+0xa4>
	STRUCT_SECTION_FOREACH(log_backend, backend) {
    2322:	463c      	mov	r4, r7
	uint32_t mask = 0;
    2324:	4605      	mov	r5, r0
			if (log_backend_is_ready(backend) == 0) {
				log_backend_enable(backend,
						   backend->cb->ctx,
						   CONFIG_LOG_MAX_LEVEL);
			} else {
				mask |= BIT(i);
    2326:	f04f 0b01 	mov.w	fp, #1
	STRUCT_SECTION_FOREACH(log_backend, backend) {
    232a:	4554      	cmp	r4, sl
    232c:	d927      	bls.n	237e <z_log_init.isra.0+0x96>
    232e:	4935      	ldr	r1, [pc, #212]	; (2404 <z_log_init.isra.0+0x11c>)
    2330:	f44f 7391 	mov.w	r3, #290	; 0x122
    2334:	4a30      	ldr	r2, [pc, #192]	; (23f8 <z_log_init.isra.0+0x110>)
    2336:	4831      	ldr	r0, [pc, #196]	; (23fc <z_log_init.isra.0+0x114>)
    2338:	f006 ffb5 	bl	92a6 <assert_print>
    233c:	4832      	ldr	r0, [pc, #200]	; (2408 <z_log_init.isra.0+0x120>)
    233e:	f006 ffb2 	bl	92a6 <assert_print>
    2342:	f44f 7191 	mov.w	r1, #290	; 0x122
    2346:	e7e3      	b.n	2310 <z_log_init.isra.0+0x28>
		if (backend->autostart) {
    2348:	7b23      	ldrb	r3, [r4, #12]
    234a:	b173      	cbz	r3, 236a <z_log_init.isra.0+0x82>
	if (backend->api->init) {
    234c:	6823      	ldr	r3, [r4, #0]
    234e:	68db      	ldr	r3, [r3, #12]
    2350:	b10b      	cbz	r3, 2356 <z_log_init.isra.0+0x6e>
		backend->api->init(backend);
    2352:	4620      	mov	r0, r4
    2354:	4798      	blx	r3
	if (backend->api->is_ready != NULL) {
    2356:	6823      	ldr	r3, [r4, #0]
    2358:	691b      	ldr	r3, [r3, #16]
    235a:	b943      	cbnz	r3, 236e <z_log_init.isra.0+0x86>
				log_backend_enable(backend,
    235c:	6863      	ldr	r3, [r4, #4]
    235e:	2204      	movs	r2, #4
    2360:	4620      	mov	r0, r4
    2362:	6819      	ldr	r1, [r3, #0]
    2364:	f000 fa3a 	bl	27dc <log_backend_enable>
			}

			i++;
    2368:	3601      	adds	r6, #1
	STRUCT_SECTION_FOREACH(log_backend, backend) {
    236a:	3410      	adds	r4, #16
    236c:	e7dd      	b.n	232a <z_log_init.isra.0+0x42>
		return backend->api->is_ready(backend);
    236e:	4620      	mov	r0, r4
    2370:	4798      	blx	r3
			if (log_backend_is_ready(backend) == 0) {
    2372:	2800      	cmp	r0, #0
    2374:	d0f2      	beq.n	235c <z_log_init.isra.0+0x74>
				mask |= BIT(i);
    2376:	fa0b f306 	lsl.w	r3, fp, r6
    237a:	431d      	orrs	r5, r3
    237c:	e7f4      	b.n	2368 <z_log_init.isra.0+0x80>
	STRUCT_SECTION_FOREACH(log_backend, backend) {
    237e:	d3e3      	bcc.n	2348 <z_log_init.isra.0+0x60>
		}
	}

	/* If blocking init, wait until all backends are activated. */
	if (blocking) {
    2380:	f1b9 0f00 	cmp.w	r9, #0
    2384:	d002      	beq.n	238c <z_log_init.isra.0+0xa4>
		mask_cpy &= ~BIT(i);
    2386:	f04f 0a01 	mov.w	sl, #1
		while (mask) {
    238a:	b90d      	cbnz	r5, 2390 <z_log_init.isra.0+0xa8>
			}
		}
	}

	return mask;
}
    238c:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
    2390:	46a9      	mov	r9, r5
		uint32_t i = __builtin_ctz(mask_cpy);
    2392:	fa95 f4a5 	rbit	r4, r5
    2396:	fab4 f484 	clz	r4, r4
		mask_cpy &= ~BIT(i);
    239a:	fa0a f304 	lsl.w	r3, sl, r4
		if (backend->autostart && (log_backend_is_ready(backend) == 0)) {
    239e:	0126      	lsls	r6, r4, #4
    23a0:	eb07 1404 	add.w	r4, r7, r4, lsl #4
		mask_cpy &= ~BIT(i);
    23a4:	ea6f 0b03 	mvn.w	fp, r3
    23a8:	ea25 0503 	bic.w	r5, r5, r3
		if (backend->autostart && (log_backend_is_ready(backend) == 0)) {
    23ac:	7b23      	ldrb	r3, [r4, #12]
    23ae:	b15b      	cbz	r3, 23c8 <z_log_init.isra.0+0xe0>
	if (backend->api->is_ready != NULL) {
    23b0:	59bb      	ldr	r3, [r7, r6]
    23b2:	691b      	ldr	r3, [r3, #16]
    23b4:	b9a3      	cbnz	r3, 23e0 <z_log_init.isra.0+0xf8>
					   backend->cb->ctx,
    23b6:	443e      	add	r6, r7
			log_backend_enable(backend,
    23b8:	6873      	ldr	r3, [r6, #4]
    23ba:	2204      	movs	r2, #4
    23bc:	4620      	mov	r0, r4
    23be:	6819      	ldr	r1, [r3, #0]
			mask &= ~BIT(i);
    23c0:	ea09 090b 	and.w	r9, r9, fp
			log_backend_enable(backend,
    23c4:	f000 fa0a 	bl	27dc <log_backend_enable>
	while (mask_cpy) {
    23c8:	2d00      	cmp	r5, #0
    23ca:	d1e2      	bne.n	2392 <z_log_init.isra.0+0xaa>
			if (IS_ENABLED(CONFIG_MULTITHREADING) && can_sleep) {
    23cc:	f1b8 0f00 	cmp.w	r8, #0
    23d0:	d004      	beq.n	23dc <z_log_init.isra.0+0xf4>
	return z_impl_k_sleep(timeout);
    23d2:	f44f 70a4 	mov.w	r0, #328	; 0x148
    23d6:	2100      	movs	r1, #0
    23d8:	f005 ff7e 	bl	82d8 <z_impl_k_sleep>
    23dc:	464d      	mov	r5, r9
    23de:	e7d4      	b.n	238a <z_log_init.isra.0+0xa2>
		return backend->api->is_ready(backend);
    23e0:	4620      	mov	r0, r4
    23e2:	4798      	blx	r3
		if (backend->autostart && (log_backend_is_ready(backend) == 0)) {
    23e4:	2800      	cmp	r0, #0
    23e6:	d1ef      	bne.n	23c8 <z_log_init.isra.0+0xe0>
    23e8:	e7e5      	b.n	23b6 <z_log_init.isra.0+0xce>
    23ea:	bf00      	nop
    23ec:	0000a01c 	.word	0x0000a01c
    23f0:	0000a00c 	.word	0x0000a00c
    23f4:	0000a777 	.word	0x0000a777
    23f8:	0000a74a 	.word	0x0000a74a
    23fc:	0000a2e8 	.word	0x0000a2e8
    2400:	20000790 	.word	0x20000790
    2404:	0000a79b 	.word	0x0000a79b
    2408:	0000a7bc 	.word	0x0000a7bc

0000240c <log_format_func_t_get>:
}
    240c:	4b01      	ldr	r3, [pc, #4]	; (2414 <log_format_func_t_get+0x8>)
    240e:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    2412:	4770      	bx	lr
    2414:	0000a03c 	.word	0x0000a03c

00002418 <log_set_timestamp_func>:
		thread_set(process_tid);
	}
}

int log_set_timestamp_func(log_timestamp_get_t timestamp_getter, uint32_t freq)
{
    2418:	b508      	push	{r3, lr}
    241a:	4603      	mov	r3, r0
    241c:	4608      	mov	r0, r1
	if (timestamp_getter == NULL) {
    241e:	b12b      	cbz	r3, 242c <log_set_timestamp_func+0x14>
		return -EINVAL;
	}

	timestamp_func = timestamp_getter;
    2420:	4a04      	ldr	r2, [pc, #16]	; (2434 <log_set_timestamp_func+0x1c>)
    2422:	6013      	str	r3, [r2, #0]
	if (CONFIG_LOG_PROCESSING_LATENCY_US) {
		proc_latency = (freq * CONFIG_LOG_PROCESSING_LATENCY_US) / 1000000;
	}

	if (IS_ENABLED(CONFIG_LOG_OUTPUT)) {
		log_output_timestamp_freq_set(freq);
    2424:	f000 fce0 	bl	2de8 <log_output_timestamp_freq_set>
	}

	return 0;
    2428:	2000      	movs	r0, #0
}
    242a:	bd08      	pop	{r3, pc}
		return -EINVAL;
    242c:	f06f 0015 	mvn.w	r0, #21
    2430:	e7fb      	b.n	242a <log_set_timestamp_func+0x12>
    2432:	bf00      	nop
    2434:	20000004 	.word	0x20000004

00002438 <z_log_notify_backend_enabled>:
	 */
	if (IS_ENABLED(CONFIG_LOG_PROCESS_THREAD) && !backend_attached) {
		k_sem_give(&log_process_thread_sem);
	}

	backend_attached = true;
    2438:	2201      	movs	r2, #1
    243a:	4b01      	ldr	r3, [pc, #4]	; (2440 <z_log_notify_backend_enabled+0x8>)
    243c:	701a      	strb	r2, [r3, #0]
}
    243e:	4770      	bx	lr
    2440:	200010c7 	.word	0x200010c7

00002444 <z_log_dropped>:
}
#include <syscalls/log_buffered_cnt_mrsh.c>
#endif

void z_log_dropped(bool buffered)
{
    2444:	b510      	push	{r4, lr}
    2446:	4604      	mov	r4, r0
	atomic_inc(&dropped_cnt);
    2448:	4806      	ldr	r0, [pc, #24]	; (2464 <z_log_dropped+0x20>)
    244a:	f007 f80c 	bl	9466 <atomic_inc>
	if (buffered) {
    244e:	b13c      	cbz	r4, 2460 <z_log_dropped+0x1c>
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_sub(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_sub(target, value, __ATOMIC_SEQ_CST);
    2450:	4b05      	ldr	r3, [pc, #20]	; (2468 <z_log_dropped+0x24>)
    2452:	e8d3 1fef 	ldaex	r1, [r3]
    2456:	3901      	subs	r1, #1
    2458:	e8c3 1fe2 	stlex	r2, r1, [r3]
    245c:	2a00      	cmp	r2, #0
    245e:	d1f8      	bne.n	2452 <z_log_dropped+0xe>
		atomic_dec(&buffered_cnt);
	}
}
    2460:	bd10      	pop	{r4, pc}
    2462:	bf00      	nop
    2464:	20000788 	.word	0x20000788
    2468:	2000078c 	.word	0x2000078c

0000246c <z_log_dropped_read_and_clear>:

uint32_t z_log_dropped_read_and_clear(void)
{
	return atomic_set(&dropped_cnt, 0);
}
    246c:	2000      	movs	r0, #0
    246e:	4601      	mov	r1, r0
{
	/* This builtin, as described by Intel, is not a traditional
	 * test-and-set operation, but rather an atomic exchange operation. It
	 * writes value into *ptr, and returns the previous contents of *ptr.
	 */
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    2470:	4b03      	ldr	r3, [pc, #12]	; (2480 <z_log_dropped_read_and_clear+0x14>)
    2472:	e8d3 0fef 	ldaex	r0, [r3]
    2476:	e8c3 1fe2 	stlex	r2, r1, [r3]
    247a:	2a00      	cmp	r2, #0
    247c:	d1f9      	bne.n	2472 <z_log_dropped_read_and_clear+0x6>
    247e:	4770      	bx	lr
    2480:	20000788 	.word	0x20000788

00002484 <dropped_notify>:
{
    2484:	b570      	push	{r4, r5, r6, lr}
	uint32_t dropped = z_log_dropped_read_and_clear();
    2486:	f7ff fff1 	bl	246c <z_log_dropped_read_and_clear>
    248a:	4605      	mov	r5, r0
	STRUCT_SECTION_FOREACH(log_backend, backend) {
    248c:	4c0f      	ldr	r4, [pc, #60]	; (24cc <dropped_notify+0x48>)
    248e:	4e10      	ldr	r6, [pc, #64]	; (24d0 <dropped_notify+0x4c>)
    2490:	42b4      	cmp	r4, r6
    2492:	d919      	bls.n	24c8 <dropped_notify+0x44>
    2494:	490f      	ldr	r1, [pc, #60]	; (24d4 <dropped_notify+0x50>)
    2496:	f240 13cd 	movw	r3, #461	; 0x1cd
    249a:	4a0f      	ldr	r2, [pc, #60]	; (24d8 <dropped_notify+0x54>)
    249c:	480f      	ldr	r0, [pc, #60]	; (24dc <dropped_notify+0x58>)
    249e:	f006 ff02 	bl	92a6 <assert_print>
    24a2:	480f      	ldr	r0, [pc, #60]	; (24e0 <dropped_notify+0x5c>)
    24a4:	f006 feff 	bl	92a6 <assert_print>
    24a8:	f240 11cd 	movw	r1, #461	; 0x1cd
    24ac:	480a      	ldr	r0, [pc, #40]	; (24d8 <dropped_notify+0x54>)
    24ae:	f006 fef3 	bl	9298 <assert_post_action>
 */
static inline bool log_backend_is_active(
				const struct log_backend *const backend)
{
	__ASSERT_NO_MSG(backend != NULL);
	return backend->cb->active;
    24b2:	6863      	ldr	r3, [r4, #4]
		if (log_backend_is_active(backend)) {
    24b4:	795b      	ldrb	r3, [r3, #5]
    24b6:	b12b      	cbz	r3, 24c4 <dropped_notify+0x40>
	if (backend->api->dropped != NULL) {
    24b8:	6823      	ldr	r3, [r4, #0]
    24ba:	685b      	ldr	r3, [r3, #4]
    24bc:	b113      	cbz	r3, 24c4 <dropped_notify+0x40>
		backend->api->dropped(backend, cnt);
    24be:	4629      	mov	r1, r5
    24c0:	4620      	mov	r0, r4
    24c2:	4798      	blx	r3
	STRUCT_SECTION_FOREACH(log_backend, backend) {
    24c4:	3410      	adds	r4, #16
    24c6:	e7e3      	b.n	2490 <dropped_notify+0xc>
    24c8:	d3f3      	bcc.n	24b2 <dropped_notify+0x2e>
}
    24ca:	bd70      	pop	{r4, r5, r6, pc}
    24cc:	0000a00c 	.word	0x0000a00c
    24d0:	0000a01c 	.word	0x0000a01c
    24d4:	0000a79b 	.word	0x0000a79b
    24d8:	0000a74a 	.word	0x0000a74a
    24dc:	0000a2e8 	.word	0x0000a2e8
    24e0:	0000a7bc 	.word	0x0000a7bc

000024e4 <z_log_msg_init>:
{
	return dropped_cnt > 0;
}

void z_log_msg_init(void)
{
    24e4:	b510      	push	{r4, lr}
	mpsc_pbuf_init(&log_buffer, &mpsc_config);
    24e6:	4c04      	ldr	r4, [pc, #16]	; (24f8 <z_log_msg_init+0x14>)
    24e8:	4904      	ldr	r1, [pc, #16]	; (24fc <z_log_msg_init+0x18>)
    24ea:	4620      	mov	r0, r4
    24ec:	f7ff fa88 	bl	1a00 <mpsc_pbuf_init>
	curr_log_buffer = &log_buffer;
    24f0:	4b03      	ldr	r3, [pc, #12]	; (2500 <z_log_msg_init+0x1c>)
    24f2:	601c      	str	r4, [r3, #0]
}
    24f4:	bd10      	pop	{r4, pc}
    24f6:	bf00      	nop
    24f8:	2000014c 	.word	0x2000014c
    24fc:	0000a028 	.word	0x0000a028
    2500:	20000780 	.word	0x20000780

00002504 <log_core_init>:
{
    2504:	b508      	push	{r3, lr}
	panic_mode = false;
    2506:	2300      	movs	r3, #0
    2508:	4a06      	ldr	r2, [pc, #24]	; (2524 <log_core_init+0x20>)
		log_set_timestamp_func(default_get_timestamp,
    250a:	f44f 4100 	mov.w	r1, #32768	; 0x8000
	panic_mode = false;
    250e:	7013      	strb	r3, [r2, #0]
	dropped_cnt = 0;
    2510:	4a05      	ldr	r2, [pc, #20]	; (2528 <log_core_init+0x24>)
		log_set_timestamp_func(default_get_timestamp,
    2512:	4806      	ldr	r0, [pc, #24]	; (252c <log_core_init+0x28>)
	dropped_cnt = 0;
    2514:	6013      	str	r3, [r2, #0]
		log_set_timestamp_func(default_get_timestamp,
    2516:	f7ff ff7f 	bl	2418 <log_set_timestamp_func>
}
    251a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		z_log_msg_init();
    251e:	f7ff bfe1 	b.w	24e4 <z_log_msg_init>
    2522:	bf00      	nop
    2524:	200010c8 	.word	0x200010c8
    2528:	20000788 	.word	0x20000788
    252c:	00009463 	.word	0x00009463

00002530 <z_log_msg_alloc>:
	return (struct log_msg *)mpsc_pbuf_alloc(buffer, wlen,
				K_MSEC(CONFIG_LOG_BLOCK_IN_THREAD_TIMEOUT_MS));
}

struct log_msg *z_log_msg_alloc(uint32_t wlen)
{
    2530:	4601      	mov	r1, r0
	return (struct log_msg *)mpsc_pbuf_alloc(buffer, wlen,
    2532:	2200      	movs	r2, #0
    2534:	2300      	movs	r3, #0
    2536:	4801      	ldr	r0, [pc, #4]	; (253c <z_log_msg_alloc+0xc>)
    2538:	f7ff ba94 	b.w	1a64 <mpsc_pbuf_alloc>
    253c:	2000014c 	.word	0x2000014c

00002540 <z_log_msg_local_claim>:
	msg_commit(&log_buffer, msg);
}

union log_msg_generic *z_log_msg_local_claim(void)
{
	return (union log_msg_generic *)mpsc_pbuf_claim(&log_buffer);
    2540:	4801      	ldr	r0, [pc, #4]	; (2548 <z_log_msg_local_claim+0x8>)
    2542:	f7ff bba3 	b.w	1c8c <mpsc_pbuf_claim>
    2546:	bf00      	nop
    2548:	2000014c 	.word	0x2000014c

0000254c <z_log_msg_free>:
	return z_log_msg_local_claim();
}

static void msg_free(struct mpsc_pbuf_buffer *buffer, const union log_msg_generic *msg)
{
	mpsc_pbuf_free(buffer, &msg->buf);
    254c:	4b02      	ldr	r3, [pc, #8]	; (2558 <z_log_msg_free+0xc>)
}

void z_log_msg_free(union log_msg_generic *msg)
{
    254e:	4601      	mov	r1, r0
	mpsc_pbuf_free(buffer, &msg->buf);
    2550:	6818      	ldr	r0, [r3, #0]
    2552:	f7ff bc21 	b.w	1d98 <mpsc_pbuf_free>
    2556:	bf00      	nop
    2558:	20000780 	.word	0x20000780

0000255c <z_log_msg_pending>:
	msg_free(curr_log_buffer, msg);
}

static bool msg_pending(struct mpsc_pbuf_buffer *buffer)
{
	return mpsc_pbuf_is_pending(buffer);
    255c:	4801      	ldr	r0, [pc, #4]	; (2564 <z_log_msg_pending+0x8>)
    255e:	f006 bf5c 	b.w	941a <mpsc_pbuf_is_pending>
    2562:	bf00      	nop
    2564:	2000014c 	.word	0x2000014c

00002568 <z_impl_log_process>:
{
    2568:	b570      	push	{r4, r5, r6, lr}
	if (!backend_attached) {
    256a:	4b2e      	ldr	r3, [pc, #184]	; (2624 <z_impl_log_process+0xbc>)
    256c:	7818      	ldrb	r0, [r3, #0]
    256e:	2800      	cmp	r0, #0
    2570:	d057      	beq.n	2622 <z_impl_log_process+0xba>
	return z_log_msg_local_claim();
    2572:	f7ff ffe5 	bl	2540 <z_log_msg_local_claim>
	if (msg) {
    2576:	4605      	mov	r5, r0
    2578:	b340      	cbz	r0, 25cc <z_impl_log_process+0x64>
	return __atomic_fetch_sub(target, value, __ATOMIC_SEQ_CST);
    257a:	4b2b      	ldr	r3, [pc, #172]	; (2628 <z_impl_log_process+0xc0>)
    257c:	e8d3 1fef 	ldaex	r1, [r3]
    2580:	3901      	subs	r1, #1
    2582:	e8c3 1fe2 	stlex	r2, r1, [r3]
    2586:	2a00      	cmp	r2, #0
    2588:	d1f8      	bne.n	257c <z_impl_log_process+0x14>
	STRUCT_SECTION_FOREACH(log_backend, backend) {
    258a:	4c28      	ldr	r4, [pc, #160]	; (262c <z_impl_log_process+0xc4>)
    258c:	4e28      	ldr	r6, [pc, #160]	; (2630 <z_impl_log_process+0xc8>)
    258e:	42b4      	cmp	r4, r6
    2590:	d918      	bls.n	25c4 <z_impl_log_process+0x5c>
    2592:	4928      	ldr	r1, [pc, #160]	; (2634 <z_impl_log_process+0xcc>)
    2594:	f240 13c1 	movw	r3, #449	; 0x1c1
    2598:	4a27      	ldr	r2, [pc, #156]	; (2638 <z_impl_log_process+0xd0>)
    259a:	4828      	ldr	r0, [pc, #160]	; (263c <z_impl_log_process+0xd4>)
    259c:	f006 fe83 	bl	92a6 <assert_print>
    25a0:	4827      	ldr	r0, [pc, #156]	; (2640 <z_impl_log_process+0xd8>)
    25a2:	f006 fe80 	bl	92a6 <assert_print>
    25a6:	f240 11c1 	movw	r1, #449	; 0x1c1
    25aa:	4823      	ldr	r0, [pc, #140]	; (2638 <z_impl_log_process+0xd0>)
    25ac:	f006 fe74 	bl	9298 <assert_post_action>
	return backend->cb->active;
    25b0:	6863      	ldr	r3, [r4, #4]
		if (log_backend_is_active(backend) &&
    25b2:	795b      	ldrb	r3, [r3, #5]
    25b4:	b123      	cbz	r3, 25c0 <z_impl_log_process+0x58>
	backend->api->process(backend, msg);
    25b6:	6823      	ldr	r3, [r4, #0]
    25b8:	4629      	mov	r1, r5
    25ba:	4620      	mov	r0, r4
    25bc:	681b      	ldr	r3, [r3, #0]
    25be:	4798      	blx	r3
	STRUCT_SECTION_FOREACH(log_backend, backend) {
    25c0:	3410      	adds	r4, #16
    25c2:	e7e4      	b.n	258e <z_impl_log_process+0x26>
    25c4:	d3f4      	bcc.n	25b0 <z_impl_log_process+0x48>
		z_log_msg_free(msg);
    25c6:	4628      	mov	r0, r5
    25c8:	f7ff ffc0 	bl	254c <z_log_msg_free>
	return dropped_cnt > 0;
    25cc:	4b1d      	ldr	r3, [pc, #116]	; (2644 <z_impl_log_process+0xdc>)
    25ce:	4c1e      	ldr	r4, [pc, #120]	; (2648 <z_impl_log_process+0xe0>)
		if ((dropped_pend || unordered_pend) &&
    25d0:	681b      	ldr	r3, [r3, #0]
    25d2:	2b00      	cmp	r3, #0
    25d4:	dd19      	ble.n	260a <z_impl_log_process+0xa2>
	return z_impl_k_uptime_ticks();
    25d6:	f007 fb17 	bl	9c08 <z_impl_k_uptime_ticks>
			/* Faster algorithm but source is first multiplied by target frequency
			 * and it can overflow even though final result would not overflow.
			 * Kconfig option shall prevent use of this algorithm when there is a
			 * risk of overflow.
			 */
			return ((t * to_hz + off) / from_hz);
    25da:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    25de:	fba0 0302 	umull	r0, r3, r0, r2
    25e2:	fb02 3101 	mla	r1, r2, r1, r3
    25e6:	0bc3      	lsrs	r3, r0, #15
    25e8:	ea43 4341 	orr.w	r3, r3, r1, lsl #17
		   (k_uptime_get() - last_failure_report) > CONFIG_LOG_FAILURE_REPORT_PERIOD) {
    25ec:	e9d4 2000 	ldrd	r2, r0, [r4]
    25f0:	1a9b      	subs	r3, r3, r2
		if ((dropped_pend || unordered_pend) &&
    25f2:	f240 32e9 	movw	r2, #1001	; 0x3e9
    25f6:	ea4f 31d1 	mov.w	r1, r1, lsr #15
		   (k_uptime_get() - last_failure_report) > CONFIG_LOG_FAILURE_REPORT_PERIOD) {
    25fa:	eb61 0100 	sbc.w	r1, r1, r0
		if ((dropped_pend || unordered_pend) &&
    25fe:	4293      	cmp	r3, r2
    2600:	f171 0100 	sbcs.w	r1, r1, #0
    2604:	d301      	bcc.n	260a <z_impl_log_process+0xa2>
				dropped_notify();
    2606:	f7ff ff3d 	bl	2484 <dropped_notify>
		last_failure_report += CONFIG_LOG_FAILURE_REPORT_PERIOD;
    260a:	e9d4 3200 	ldrd	r3, r2, [r4]
    260e:	f513 737a 	adds.w	r3, r3, #1000	; 0x3e8
    2612:	f142 0200 	adc.w	r2, r2, #0
    2616:	e9c4 3200 	strd	r3, r2, [r4]
}
    261a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	return z_log_msg_pending();
    261e:	f7ff bf9d 	b.w	255c <z_log_msg_pending>
}
    2622:	bd70      	pop	{r4, r5, r6, pc}
    2624:	200010c7 	.word	0x200010c7
    2628:	2000078c 	.word	0x2000078c
    262c:	0000a00c 	.word	0x0000a00c
    2630:	0000a01c 	.word	0x0000a01c
    2634:	0000a79b 	.word	0x0000a79b
    2638:	0000a74a 	.word	0x0000a74a
    263c:	0000a2e8 	.word	0x0000a2e8
    2640:	0000a7bc 	.word	0x0000a7bc
    2644:	20000788 	.word	0x20000788
    2648:	200005f0 	.word	0x200005f0

0000264c <z_log_msg_post_finalize>:
{
    264c:	b513      	push	{r0, r1, r4, lr}
	atomic_val_t cnt = atomic_inc(&buffered_cnt);
    264e:	482a      	ldr	r0, [pc, #168]	; (26f8 <z_log_msg_post_finalize+0xac>)
    2650:	f006 ff09 	bl	9466 <atomic_inc>
	if (panic_mode) {
    2654:	4b29      	ldr	r3, [pc, #164]	; (26fc <z_log_msg_post_finalize+0xb0>)
    2656:	781b      	ldrb	r3, [r3, #0]
    2658:	2b00      	cmp	r3, #0
    265a:	d034      	beq.n	26c6 <z_log_msg_post_finalize+0x7a>
	__asm__ volatile(
    265c:	f04f 0320 	mov.w	r3, #32
    2660:	f3ef 8411 	mrs	r4, BASEPRI
    2664:	f383 8812 	msr	BASEPRI_MAX, r3
    2668:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    266c:	4824      	ldr	r0, [pc, #144]	; (2700 <z_log_msg_post_finalize+0xb4>)
    266e:	f004 fbad 	bl	6dcc <z_spin_lock_valid>
    2672:	b968      	cbnz	r0, 2690 <z_log_msg_post_finalize+0x44>
    2674:	2394      	movs	r3, #148	; 0x94
    2676:	4a23      	ldr	r2, [pc, #140]	; (2704 <z_log_msg_post_finalize+0xb8>)
    2678:	4923      	ldr	r1, [pc, #140]	; (2708 <z_log_msg_post_finalize+0xbc>)
    267a:	4824      	ldr	r0, [pc, #144]	; (270c <z_log_msg_post_finalize+0xc0>)
    267c:	f006 fe13 	bl	92a6 <assert_print>
    2680:	491f      	ldr	r1, [pc, #124]	; (2700 <z_log_msg_post_finalize+0xb4>)
    2682:	4823      	ldr	r0, [pc, #140]	; (2710 <z_log_msg_post_finalize+0xc4>)
    2684:	f006 fe0f 	bl	92a6 <assert_print>
    2688:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    268a:	481e      	ldr	r0, [pc, #120]	; (2704 <z_log_msg_post_finalize+0xb8>)
    268c:	f006 fe04 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    2690:	481b      	ldr	r0, [pc, #108]	; (2700 <z_log_msg_post_finalize+0xb4>)
    2692:	f004 fbb7 	bl	6e04 <z_spin_lock_set_owner>
	if (z_syscall_trap()) {
		return (bool) arch_syscall_invoke0(K_SYSCALL_LOG_PROCESS);
	}
#endif
	compiler_barrier();
	return z_impl_log_process();
    2696:	f7ff ff67 	bl	2568 <z_impl_log_process>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    269a:	4819      	ldr	r0, [pc, #100]	; (2700 <z_log_msg_post_finalize+0xb4>)
    269c:	f004 fba4 	bl	6de8 <z_spin_unlock_valid>
    26a0:	b958      	cbnz	r0, 26ba <z_log_msg_post_finalize+0x6e>
    26a2:	23c2      	movs	r3, #194	; 0xc2
    26a4:	4a17      	ldr	r2, [pc, #92]	; (2704 <z_log_msg_post_finalize+0xb8>)
    26a6:	491b      	ldr	r1, [pc, #108]	; (2714 <z_log_msg_post_finalize+0xc8>)
    26a8:	4818      	ldr	r0, [pc, #96]	; (270c <z_log_msg_post_finalize+0xc0>)
    26aa:	f006 fdfc 	bl	92a6 <assert_print>
    26ae:	4914      	ldr	r1, [pc, #80]	; (2700 <z_log_msg_post_finalize+0xb4>)
    26b0:	4819      	ldr	r0, [pc, #100]	; (2718 <z_log_msg_post_finalize+0xcc>)
    26b2:	f006 fdf8 	bl	92a6 <assert_print>
    26b6:	21c2      	movs	r1, #194	; 0xc2
    26b8:	e7e7      	b.n	268a <z_log_msg_post_finalize+0x3e>
	__asm__ volatile(
    26ba:	f384 8811 	msr	BASEPRI, r4
    26be:	f3bf 8f6f 	isb	sy
}
    26c2:	b002      	add	sp, #8
    26c4:	bd10      	pop	{r4, pc}
	} else if (proc_tid != NULL) {
    26c6:	4b15      	ldr	r3, [pc, #84]	; (271c <z_log_msg_post_finalize+0xd0>)
    26c8:	681b      	ldr	r3, [r3, #0]
    26ca:	2b00      	cmp	r3, #0
    26cc:	d0f9      	beq.n	26c2 <z_log_msg_post_finalize+0x76>
		if (cnt == 0) {
    26ce:	b938      	cbnz	r0, 26e0 <z_log_msg_post_finalize+0x94>
			k_timer_start(&log_process_thread_timer,
    26d0:	2200      	movs	r2, #0
    26d2:	2300      	movs	r3, #0
	z_impl_k_timer_start(timer, duration, period);
    26d4:	4812      	ldr	r0, [pc, #72]	; (2720 <z_log_msg_post_finalize+0xd4>)
    26d6:	e9cd 2300 	strd	r2, r3, [sp]
    26da:	f006 faab 	bl	8c34 <z_impl_k_timer_start>
    26de:	e7f0      	b.n	26c2 <z_log_msg_post_finalize+0x76>
		} else if (CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD &&
    26e0:	280a      	cmp	r0, #10
    26e2:	d1ee      	bne.n	26c2 <z_log_msg_post_finalize+0x76>
	z_impl_k_timer_stop(timer);
    26e4:	480e      	ldr	r0, [pc, #56]	; (2720 <z_log_msg_post_finalize+0xd4>)
    26e6:	f007 fa95 	bl	9c14 <z_impl_k_timer_stop>
	z_impl_k_sem_give(sem);
    26ea:	480e      	ldr	r0, [pc, #56]	; (2724 <z_log_msg_post_finalize+0xd8>)
}
    26ec:	b002      	add	sp, #8
    26ee:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    26f2:	f004 bd1f 	b.w	7134 <z_impl_k_sem_give>
    26f6:	bf00      	nop
    26f8:	2000078c 	.word	0x2000078c
    26fc:	200010c8 	.word	0x200010c8
    2700:	2000077c 	.word	0x2000077c
    2704:	0000a51d 	.word	0x0000a51d
    2708:	0000a576 	.word	0x0000a576
    270c:	0000a2e8 	.word	0x0000a2e8
    2710:	0000a58b 	.word	0x0000a58b
    2714:	0000a54a 	.word	0x0000a54a
    2718:	0000a561 	.word	0x0000a561
    271c:	20000784 	.word	0x20000784
    2720:	200005f8 	.word	0x200005f8
    2724:	200001dc 	.word	0x200001dc

00002728 <z_log_msg_commit>:
{
    2728:	b510      	push	{r4, lr}
	msg->hdr.timestamp = timestamp_func();
    272a:	4b06      	ldr	r3, [pc, #24]	; (2744 <z_log_msg_commit+0x1c>)
{
    272c:	4604      	mov	r4, r0
	msg->hdr.timestamp = timestamp_func();
    272e:	681b      	ldr	r3, [r3, #0]
    2730:	4798      	blx	r3
	mpsc_pbuf_commit(buffer, &m->buf);
    2732:	4621      	mov	r1, r4
	msg->hdr.timestamp = timestamp_func();
    2734:	60a0      	str	r0, [r4, #8]
	mpsc_pbuf_commit(buffer, &m->buf);
    2736:	4804      	ldr	r0, [pc, #16]	; (2748 <z_log_msg_commit+0x20>)
    2738:	f7ff fa52 	bl	1be0 <mpsc_pbuf_commit>
}
    273c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_log_msg_post_finalize();
    2740:	f7ff bf84 	b.w	264c <z_log_msg_post_finalize>
    2744:	20000004 	.word	0x20000004
    2748:	2000014c 	.word	0x2000014c

0000274c <z_impl_log_panic>:
{
    274c:	b570      	push	{r4, r5, r6, lr}
	if (panic_mode) {
    274e:	4d15      	ldr	r5, [pc, #84]	; (27a4 <z_impl_log_panic+0x58>)
    2750:	7829      	ldrb	r1, [r5, #0]
    2752:	bb29      	cbnz	r1, 27a0 <z_impl_log_panic+0x54>
	(void)z_log_init(true, false);
    2754:	2001      	movs	r0, #1
    2756:	f7ff fdc7 	bl	22e8 <z_log_init.isra.0>
	STRUCT_SECTION_FOREACH(log_backend, backend) {
    275a:	4c13      	ldr	r4, [pc, #76]	; (27a8 <z_impl_log_panic+0x5c>)
    275c:	4e13      	ldr	r6, [pc, #76]	; (27ac <z_impl_log_panic+0x60>)
    275e:	42b4      	cmp	r4, r6
    2760:	d917      	bls.n	2792 <z_impl_log_panic+0x46>
    2762:	4913      	ldr	r1, [pc, #76]	; (27b0 <z_impl_log_panic+0x64>)
    2764:	f44f 73c2 	mov.w	r3, #388	; 0x184
    2768:	4a12      	ldr	r2, [pc, #72]	; (27b4 <z_impl_log_panic+0x68>)
    276a:	4813      	ldr	r0, [pc, #76]	; (27b8 <z_impl_log_panic+0x6c>)
    276c:	f006 fd9b 	bl	92a6 <assert_print>
    2770:	4812      	ldr	r0, [pc, #72]	; (27bc <z_impl_log_panic+0x70>)
    2772:	f006 fd98 	bl	92a6 <assert_print>
    2776:	f44f 71c2 	mov.w	r1, #388	; 0x184
    277a:	480e      	ldr	r0, [pc, #56]	; (27b4 <z_impl_log_panic+0x68>)
    277c:	f006 fd8c 	bl	9298 <assert_post_action>
	return backend->cb->active;
    2780:	6863      	ldr	r3, [r4, #4]
		if (log_backend_is_active(backend)) {
    2782:	795b      	ldrb	r3, [r3, #5]
    2784:	b11b      	cbz	r3, 278e <z_impl_log_panic+0x42>
	backend->api->panic(backend);
    2786:	6823      	ldr	r3, [r4, #0]
    2788:	4620      	mov	r0, r4
    278a:	689b      	ldr	r3, [r3, #8]
    278c:	4798      	blx	r3
	STRUCT_SECTION_FOREACH(log_backend, backend) {
    278e:	3410      	adds	r4, #16
    2790:	e7e5      	b.n	275e <z_impl_log_panic+0x12>
    2792:	d3f5      	bcc.n	2780 <z_impl_log_panic+0x34>
    2794:	f7ff fee8 	bl	2568 <z_impl_log_process>
		while (log_process() == true) {
    2798:	2800      	cmp	r0, #0
    279a:	d1fb      	bne.n	2794 <z_impl_log_panic+0x48>
	panic_mode = true;
    279c:	2301      	movs	r3, #1
    279e:	702b      	strb	r3, [r5, #0]
}
    27a0:	bd70      	pop	{r4, r5, r6, pc}
    27a2:	bf00      	nop
    27a4:	200010c8 	.word	0x200010c8
    27a8:	0000a00c 	.word	0x0000a00c
    27ac:	0000a01c 	.word	0x0000a01c
    27b0:	0000a79b 	.word	0x0000a79b
    27b4:	0000a74a 	.word	0x0000a74a
    27b8:	0000a2e8 	.word	0x0000a2e8
    27bc:	0000a7bc 	.word	0x0000a7bc

000027c0 <log_source_name_get>:
 * @return Source ID.
 */
static inline uint32_t log_const_source_id(
				const struct log_source_const_data *data)
{
	return ((const uint8_t *)data - (uint8_t *)__log_const_start)/
    27c0:	4a04      	ldr	r2, [pc, #16]	; (27d4 <log_source_name_get+0x14>)
    27c2:	4b05      	ldr	r3, [pc, #20]	; (27d8 <log_source_name_get+0x18>)
    27c4:	1a9b      	subs	r3, r3, r2
}

const char *log_source_name_get(uint32_t domain_id, uint32_t source_id)
{
	if (z_log_is_local_domain(domain_id)) {
		if (source_id < log_src_cnt_get(domain_id)) {
    27c6:	ebb1 0fd3 	cmp.w	r1, r3, lsr #3
			return __log_const_start[source_id].name;
    27ca:	bf34      	ite	cc
    27cc:	f852 0031 	ldrcc.w	r0, [r2, r1, lsl #3]
		} else {
			return NULL;
    27d0:	2000      	movcs	r0, #0
		}
	}

	return link_source_name_get(domain_id, source_id);
}
    27d2:	4770      	bx	lr
    27d4:	00009f84 	.word	0x00009f84
    27d8:	0000a00c 	.word	0x0000a00c

000027dc <log_backend_enable>:
			uint32_t level)
{
	/* As first slot in filtering mask is reserved, backend ID has offset.*/
	uint32_t id = LOG_FILTER_FIRST_BACKEND_SLOT_IDX;

	id += backend - log_backend_get(0);
    27dc:	4b0e      	ldr	r3, [pc, #56]	; (2818 <log_backend_enable+0x3c>)
{
    27de:	b510      	push	{r4, lr}
	id += backend - log_backend_get(0);
    27e0:	1ac3      	subs	r3, r0, r3
    27e2:	111b      	asrs	r3, r3, #4
    27e4:	3301      	adds	r3, #1

	log_backend_id_set(backend, id);
    27e6:	b2db      	uxtb	r3, r3
	__ASSERT_NO_MSG(backend != NULL);
    27e8:	b948      	cbnz	r0, 27fe <log_backend_enable+0x22>
    27ea:	490c      	ldr	r1, [pc, #48]	; (281c <log_backend_enable+0x40>)
    27ec:	480c      	ldr	r0, [pc, #48]	; (2820 <log_backend_enable+0x44>)
    27ee:	23de      	movs	r3, #222	; 0xde
    27f0:	4a0c      	ldr	r2, [pc, #48]	; (2824 <log_backend_enable+0x48>)
    27f2:	f006 fd58 	bl	92a6 <assert_print>
    27f6:	21de      	movs	r1, #222	; 0xde
    27f8:	480a      	ldr	r0, [pc, #40]	; (2824 <log_backend_enable+0x48>)
    27fa:	f006 fd4d 	bl	9298 <assert_post_action>
	backend->cb->id = id;
    27fe:	6844      	ldr	r4, [r0, #4]
    2800:	7123      	strb	r3, [r4, #4]
	backend->cb->level = level;
    2802:	6843      	ldr	r3, [r0, #4]
    2804:	719a      	strb	r2, [r3, #6]
	backend->cb->active = true;
    2806:	2201      	movs	r2, #1
	backend->cb->ctx = ctx;
    2808:	6843      	ldr	r3, [r0, #4]
    280a:	6019      	str	r1, [r3, #0]
	backend->cb->active = true;
    280c:	6843      	ldr	r3, [r0, #4]
    280e:	715a      	strb	r2, [r3, #5]
	backend_filter_set(backend, level);
	log_backend_activate(backend, ctx);

	z_log_notify_backend_enabled();
}
    2810:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_log_notify_backend_enabled();
    2814:	f7ff be10 	b.w	2438 <z_log_notify_backend_enabled>
    2818:	0000a00c 	.word	0x0000a00c
    281c:	0000a85f 	.word	0x0000a85f
    2820:	0000a2e8 	.word	0x0000a2e8
    2824:	0000a827 	.word	0x0000a827

00002828 <z_impl_z_log_msg_static_create>:
}

void z_impl_z_log_msg_static_create(const void *source,
			      const struct log_msg_desc desc,
			      uint8_t *package, const void *data)
{
    2828:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 *
 * @return Length.
 */
static inline uint32_t log_msg_get_total_wlen(const struct log_msg_desc desc)
{
	return Z_LOG_MSG2_ALIGNED_WLEN(desc.package_len, desc.data_len);
    282c:	f3c1 44cb 	ubfx	r4, r1, #19, #12
    2830:	b08f      	sub	sp, #60	; 0x3c
    2832:	f3c1 2649 	ubfx	r6, r1, #9, #10
    2836:	460d      	mov	r5, r1
    2838:	4690      	mov	r8, r2
    283a:	4699      	mov	r9, r3
    283c:	9005      	str	r0, [sp, #20]
    283e:	3417      	adds	r4, #23

	struct log_msg_desc out_desc = desc;
	int inlen = desc.package_len;
	struct log_msg *msg;

	if (inlen > 0) {
    2840:	2e00      	cmp	r6, #0
    2842:	d03d      	beq.n	28c0 <z_impl_z_log_msg_static_create+0x98>
	return cbprintf_package_convert(in_packaged, in_len,
    2844:	f04f 0b04 	mov.w	fp, #4
    2848:	f04f 0a0a 	mov.w	sl, #10
	struct z_cbprintf_buf_desc buf_desc = {
    284c:	2200      	movs	r2, #0
	return cbprintf_package_convert(in_packaged, in_len,
    284e:	af09      	add	r7, sp, #36	; 0x24
		uint32_t flags = CBPRINTF_PACKAGE_CONVERT_RW_STR |
				 CBPRINTF_PACKAGE_CONVERT_PTR_CHECK;
		uint16_t strl[4];
		int len;

		len = cbprintf_package_copy(package, inlen,
    2850:	4631      	mov	r1, r6
    2852:	ab0b      	add	r3, sp, #44	; 0x2c
    2854:	4640      	mov	r0, r8
    2856:	f8cd b008 	str.w	fp, [sp, #8]
    285a:	9701      	str	r7, [sp, #4]
    285c:	f8cd a000 	str.w	sl, [sp]
	struct z_cbprintf_buf_desc buf_desc = {
    2860:	e9cd 220b 	strd	r2, r2, [sp, #44]	; 0x2c
    2864:	920d      	str	r2, [sp, #52]	; 0x34
	return cbprintf_package_convert(in_packaged, in_len,
    2866:	9607      	str	r6, [sp, #28]
    2868:	f7fe f808 	bl	87c <cbprintf_package_convert>
					    strl, ARRAY_SIZE(strl));

		/* Update package length with calculated value (which may be extended
		 * when strings are copied into the package.
		 */
		out_desc.package_len = len;
    286c:	f3c0 0309 	ubfx	r3, r0, #0, #10
    2870:	1918      	adds	r0, r3, r4
    2872:	f020 0007 	bic.w	r0, r0, #7
		msg = z_log_msg_alloc(log_msg_get_total_wlen(out_desc));
    2876:	0880      	lsrs	r0, r0, #2
		out_desc.package_len = len;
    2878:	461e      	mov	r6, r3
		msg = z_log_msg_alloc(log_msg_get_total_wlen(out_desc));
    287a:	f363 2552 	bfi	r5, r3, #9, #10
    287e:	9306      	str	r3, [sp, #24]
    2880:	f7ff fe56 	bl	2530 <z_log_msg_alloc>
		if (msg) {
    2884:	4604      	mov	r4, r0
    2886:	b308      	cbz	r0, 28cc <z_impl_z_log_msg_static_create+0xa4>
	struct z_cbprintf_buf_desc buf_desc = {
    2888:	2200      	movs	r2, #0
    288a:	9b06      	ldr	r3, [sp, #24]
			len = cbprintf_package_copy(package, inlen,
						    msg->data, out_desc.package_len,
    288c:	3010      	adds	r0, #16
    288e:	900b      	str	r0, [sp, #44]	; 0x2c
    2890:	930c      	str	r3, [sp, #48]	; 0x30
    2892:	920d      	str	r2, [sp, #52]	; 0x34
	return cbprintf_package_convert(in_packaged, in_len,
    2894:	4640      	mov	r0, r8
    2896:	e9cd 7b01 	strd	r7, fp, [sp, #4]
    289a:	4a12      	ldr	r2, [pc, #72]	; (28e4 <z_impl_z_log_msg_static_create+0xbc>)
    289c:	9907      	ldr	r1, [sp, #28]
    289e:	f8cd a000 	str.w	sl, [sp]
    28a2:	ab0b      	add	r3, sp, #44	; 0x2c
    28a4:	f7fd ffea 	bl	87c <cbprintf_package_convert>
						    flags, strl, ARRAY_SIZE(strl));
			__ASSERT_NO_MSG(len >= 0);
    28a8:	2800      	cmp	r0, #0
    28aa:	da0f      	bge.n	28cc <z_impl_z_log_msg_static_create+0xa4>
    28ac:	490e      	ldr	r1, [pc, #56]	; (28e8 <z_impl_z_log_msg_static_create+0xc0>)
    28ae:	480f      	ldr	r0, [pc, #60]	; (28ec <z_impl_z_log_msg_static_create+0xc4>)
    28b0:	2349      	movs	r3, #73	; 0x49
    28b2:	4a0f      	ldr	r2, [pc, #60]	; (28f0 <z_impl_z_log_msg_static_create+0xc8>)
    28b4:	f006 fcf7 	bl	92a6 <assert_print>
    28b8:	2149      	movs	r1, #73	; 0x49
    28ba:	480d      	ldr	r0, [pc, #52]	; (28f0 <z_impl_z_log_msg_static_create+0xc8>)
    28bc:	f006 fcec 	bl	9298 <assert_post_action>
    28c0:	f024 0007 	bic.w	r0, r4, #7
		}
	} else {
		msg = z_log_msg_alloc(log_msg_get_total_wlen(out_desc));
    28c4:	0880      	lsrs	r0, r0, #2
    28c6:	f7ff fe33 	bl	2530 <z_log_msg_alloc>
    28ca:	4604      	mov	r4, r0
	}

	z_log_msg_finalize(msg, source, out_desc, data);
    28cc:	f366 2552 	bfi	r5, r6, #9, #10
    28d0:	464b      	mov	r3, r9
    28d2:	462a      	mov	r2, r5
    28d4:	4620      	mov	r0, r4
    28d6:	9905      	ldr	r1, [sp, #20]
}
    28d8:	b00f      	add	sp, #60	; 0x3c
    28da:	e8bd 4ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
	z_log_msg_finalize(msg, source, out_desc, data);
    28de:	f006 bdfb 	b.w	94d8 <z_log_msg_finalize>
    28e2:	bf00      	nop
    28e4:	000094ad 	.word	0x000094ad
    28e8:	0000a8ac 	.word	0x0000a8ac
    28ec:	0000a2e8 	.word	0x0000a2e8
    28f0:	0000a87f 	.word	0x0000a87f

000028f4 <z_impl_z_log_msg_runtime_vcreate>:
#endif

void z_impl_z_log_msg_runtime_vcreate(uint8_t domain_id, const void *source,
				uint8_t level, const void *data, size_t dlen,
				uint32_t package_flags, const char *fmt, va_list ap)
{
    28f4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    28f8:	b087      	sub	sp, #28
    28fa:	4604      	mov	r4, r0
    28fc:	e9dd 5a10 	ldrd	r5, sl, [sp, #64]	; 0x40
    2900:	e9dd 6912 	ldrd	r6, r9, [sp, #72]	; 0x48
    2904:	460f      	mov	r7, r1
    2906:	4693      	mov	fp, r2
    2908:	4698      	mov	r8, r3
	int plen;

	if (fmt) {
    290a:	b1ae      	cbz	r6, 2938 <z_impl_z_log_msg_runtime_vcreate+0x44>
		va_list ap2;

		va_copy(ap2, ap);
		plen = cbvprintf_package(NULL, Z_LOG_MSG2_ALIGN_OFFSET,
    290c:	2110      	movs	r1, #16
    290e:	4633      	mov	r3, r6
    2910:	4652      	mov	r2, sl
    2912:	2000      	movs	r0, #0
    2914:	f8cd 9000 	str.w	r9, [sp]
		va_copy(ap2, ap);
    2918:	f8cd 9014 	str.w	r9, [sp, #20]
		plen = cbvprintf_package(NULL, Z_LOG_MSG2_ALIGN_OFFSET,
    291c:	f7fd fd90 	bl	440 <cbvprintf_package>
					 package_flags, fmt, ap2);
		__ASSERT_NO_MSG(plen >= 0);
    2920:	1e01      	subs	r1, r0, #0
    2922:	da0a      	bge.n	293a <z_impl_z_log_msg_runtime_vcreate+0x46>
    2924:	4920      	ldr	r1, [pc, #128]	; (29a8 <z_impl_z_log_msg_runtime_vcreate+0xb4>)
    2926:	2368      	movs	r3, #104	; 0x68
    2928:	4a20      	ldr	r2, [pc, #128]	; (29ac <z_impl_z_log_msg_runtime_vcreate+0xb8>)
    292a:	4821      	ldr	r0, [pc, #132]	; (29b0 <z_impl_z_log_msg_runtime_vcreate+0xbc>)
    292c:	f006 fcbb 	bl	92a6 <assert_print>
    2930:	2168      	movs	r1, #104	; 0x68
		pkg = msg->data;
	}

	if (pkg && fmt) {
		plen = cbvprintf_package(pkg, (size_t)plen, package_flags, fmt, ap);
		__ASSERT_NO_MSG(plen >= 0);
    2932:	481e      	ldr	r0, [pc, #120]	; (29ac <z_impl_z_log_msg_runtime_vcreate+0xb8>)
    2934:	f006 fcb0 	bl	9298 <assert_post_action>
		plen = 0;
    2938:	4631      	mov	r1, r6
	struct log_msg_desc desc =
    293a:	4b1e      	ldr	r3, [pc, #120]	; (29b4 <z_impl_z_log_msg_runtime_vcreate+0xc0>)
    293c:	f004 0407 	and.w	r4, r4, #7
    2940:	f00b 0b07 	and.w	fp, fp, #7
    2944:	00e4      	lsls	r4, r4, #3
    2946:	ea03 2341 	and.w	r3, r3, r1, lsl #9
	size_t msg_wlen = Z_LOG_MSG2_ALIGNED_WLEN(plen, dlen);
    294a:	f105 0017 	add.w	r0, r5, #23
	struct log_msg_desc desc =
    294e:	ea44 148b 	orr.w	r4, r4, fp, lsl #6
    2952:	431c      	orrs	r4, r3
	size_t msg_wlen = Z_LOG_MSG2_ALIGNED_WLEN(plen, dlen);
    2954:	4408      	add	r0, r1
	struct log_msg_desc desc =
    2956:	4b18      	ldr	r3, [pc, #96]	; (29b8 <z_impl_z_log_msg_runtime_vcreate+0xc4>)
	size_t msg_wlen = Z_LOG_MSG2_ALIGNED_WLEN(plen, dlen);
    2958:	f020 0007 	bic.w	r0, r0, #7
	struct log_msg_desc desc =
    295c:	ea03 43c5 	and.w	r3, r3, r5, lsl #19
		msg = z_log_msg_alloc(msg_wlen);
    2960:	0880      	lsrs	r0, r0, #2
	struct log_msg_desc desc =
    2962:	431c      	orrs	r4, r3
	size_t msg_wlen = Z_LOG_MSG2_ALIGNED_WLEN(plen, dlen);
    2964:	9103      	str	r1, [sp, #12]
		msg = z_log_msg_alloc(msg_wlen);
    2966:	f7ff fde3 	bl	2530 <z_log_msg_alloc>
			pkg = msg ? msg->data : NULL;
    296a:	4605      	mov	r5, r0
    296c:	b190      	cbz	r0, 2994 <z_impl_z_log_msg_runtime_vcreate+0xa0>
	if (pkg && fmt) {
    296e:	b18e      	cbz	r6, 2994 <z_impl_z_log_msg_runtime_vcreate+0xa0>
		plen = cbvprintf_package(pkg, (size_t)plen, package_flags, fmt, ap);
    2970:	4633      	mov	r3, r6
    2972:	4652      	mov	r2, sl
    2974:	9903      	ldr	r1, [sp, #12]
    2976:	f8cd 9000 	str.w	r9, [sp]
    297a:	3010      	adds	r0, #16
    297c:	f7fd fd60 	bl	440 <cbvprintf_package>
		__ASSERT_NO_MSG(plen >= 0);
    2980:	2800      	cmp	r0, #0
    2982:	da07      	bge.n	2994 <z_impl_z_log_msg_runtime_vcreate+0xa0>
    2984:	4908      	ldr	r1, [pc, #32]	; (29a8 <z_impl_z_log_msg_runtime_vcreate+0xb4>)
    2986:	2382      	movs	r3, #130	; 0x82
    2988:	4a08      	ldr	r2, [pc, #32]	; (29ac <z_impl_z_log_msg_runtime_vcreate+0xb8>)
    298a:	4809      	ldr	r0, [pc, #36]	; (29b0 <z_impl_z_log_msg_runtime_vcreate+0xbc>)
    298c:	f006 fc8b 	bl	92a6 <assert_print>
    2990:	2182      	movs	r1, #130	; 0x82
    2992:	e7ce      	b.n	2932 <z_impl_z_log_msg_runtime_vcreate+0x3e>
	if (IS_ENABLED(CONFIG_LOG_FRONTEND)) {
		log_frontend_msg(source, desc, pkg, data);
	}

	if (BACKENDS_IN_USE()) {
		z_log_msg_finalize(msg, source, desc, data);
    2994:	4643      	mov	r3, r8
    2996:	4622      	mov	r2, r4
    2998:	4639      	mov	r1, r7
    299a:	4628      	mov	r0, r5
	}
}
    299c:	b007      	add	sp, #28
    299e:	e8bd 4ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
		z_log_msg_finalize(msg, source, desc, data);
    29a2:	f006 bd99 	b.w	94d8 <z_log_msg_finalize>
    29a6:	bf00      	nop
    29a8:	0000a8ab 	.word	0x0000a8ab
    29ac:	0000a87f 	.word	0x0000a87f
    29b0:	0000a2e8 	.word	0x0000a2e8
    29b4:	0007fe00 	.word	0x0007fe00
    29b8:	7ff80000 	.word	0x7ff80000

000029bc <print_formatted>:
	return 0;
}

static int print_formatted(const struct log_output *output,
			   const char *fmt, ...)
{
    29bc:	b40e      	push	{r1, r2, r3}
    29be:	b503      	push	{r0, r1, lr}
    29c0:	ab03      	add	r3, sp, #12
    29c2:	f853 2b04 	ldr.w	r2, [r3], #4
    29c6:	4601      	mov	r1, r0
	va_list args;
	int length = 0;

	va_start(args, fmt);
	length = cbvprintf(out_func, (void *)output, fmt, args);
    29c8:	4804      	ldr	r0, [pc, #16]	; (29dc <print_formatted+0x20>)
	va_start(args, fmt);
    29ca:	9301      	str	r3, [sp, #4]
	length = cbvprintf(out_func, (void *)output, fmt, args);
    29cc:	f006 fdab 	bl	9526 <cbvprintf>
	va_end(args);

	return length;
}
    29d0:	b002      	add	sp, #8
    29d2:	f85d eb04 	ldr.w	lr, [sp], #4
    29d6:	b003      	add	sp, #12
    29d8:	4770      	bx	lr
    29da:	bf00      	nop
    29dc:	000029fd 	.word	0x000029fd

000029e0 <newline_print>:
	if (IS_ENABLED(CONFIG_LOG_BACKEND_NET) &&
	    flags & LOG_OUTPUT_FLAG_FORMAT_SYSLOG) {
		return;
	}

	if ((flags & LOG_OUTPUT_FLAG_CRLF_NONE) != 0U) {
    29e0:	06ca      	lsls	r2, r1, #27
    29e2:	d405      	bmi.n	29f0 <newline_print+0x10>
		return;
	}

	if ((flags & LOG_OUTPUT_FLAG_CRLF_LFONLY) != 0U) {
    29e4:	068b      	lsls	r3, r1, #26
		print_formatted(ctx, "\n");
    29e6:	bf4c      	ite	mi
    29e8:	4902      	ldrmi	r1, [pc, #8]	; (29f4 <newline_print+0x14>)
	} else {
		print_formatted(ctx, "\r\n");
    29ea:	4903      	ldrpl	r1, [pc, #12]	; (29f8 <newline_print+0x18>)
    29ec:	f7ff bfe6 	b.w	29bc <print_formatted>
	}
}
    29f0:	4770      	bx	lr
    29f2:	bf00      	nop
    29f4:	0000bb18 	.word	0x0000bb18
    29f8:	0000a8b5 	.word	0x0000a8b5

000029fc <out_func>:
{
    29fc:	b538      	push	{r3, r4, r5, lr}
	if (out_ctx->control_block->offset == out_ctx->size) {
    29fe:	684b      	ldr	r3, [r1, #4]
{
    2a00:	4605      	mov	r5, r0
	if (out_ctx->control_block->offset == out_ctx->size) {
    2a02:	681a      	ldr	r2, [r3, #0]
    2a04:	68cb      	ldr	r3, [r1, #12]
{
    2a06:	460c      	mov	r4, r1
	if (out_ctx->control_block->offset == out_ctx->size) {
    2a08:	429a      	cmp	r2, r3
    2a0a:	d102      	bne.n	2a12 <out_func+0x16>
		log_output_flush(out_ctx);
    2a0c:	4608      	mov	r0, r1
    2a0e:	f006 fd91 	bl	9534 <log_output_flush>
	return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST);
    2a12:	6863      	ldr	r3, [r4, #4]
    2a14:	e8d3 2fef 	ldaex	r2, [r3]
    2a18:	1c51      	adds	r1, r2, #1
    2a1a:	e8c3 1fe0 	stlex	r0, r1, [r3]
    2a1e:	2800      	cmp	r0, #0
    2a20:	d1f8      	bne.n	2a14 <out_func+0x18>
	out_ctx->buf[idx] = (uint8_t)c;
    2a22:	68a3      	ldr	r3, [r4, #8]
    2a24:	549d      	strb	r5, [r3, r2]
	__ASSERT_NO_MSG(out_ctx->control_block->offset <= out_ctx->size);
    2a26:	6863      	ldr	r3, [r4, #4]
    2a28:	681a      	ldr	r2, [r3, #0]
    2a2a:	68e3      	ldr	r3, [r4, #12]
    2a2c:	429a      	cmp	r2, r3
    2a2e:	d909      	bls.n	2a44 <out_func+0x48>
    2a30:	4905      	ldr	r1, [pc, #20]	; (2a48 <out_func+0x4c>)
    2a32:	4806      	ldr	r0, [pc, #24]	; (2a4c <out_func+0x50>)
    2a34:	2379      	movs	r3, #121	; 0x79
    2a36:	4a06      	ldr	r2, [pc, #24]	; (2a50 <out_func+0x54>)
    2a38:	f006 fc35 	bl	92a6 <assert_print>
    2a3c:	2179      	movs	r1, #121	; 0x79
    2a3e:	4804      	ldr	r0, [pc, #16]	; (2a50 <out_func+0x54>)
    2a40:	f006 fc2a 	bl	9298 <assert_post_action>
}
    2a44:	2000      	movs	r0, #0
    2a46:	bd38      	pop	{r3, r4, r5, pc}
    2a48:	0000a8e7 	.word	0x0000a8e7
    2a4c:	0000a2e8 	.word	0x0000a2e8
    2a50:	0000a8b8 	.word	0x0000a8b8

00002a54 <log_output_process>:
			uint8_t level,
			const uint8_t *package,
			const uint8_t *data,
			size_t data_len,
			uint32_t flags)
{
    2a54:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    2a58:	b089      	sub	sp, #36	; 0x24
    2a5a:	469b      	mov	fp, r3
    2a5c:	e9dd 7615 	ldrd	r7, r6, [sp, #84]	; 0x54
    2a60:	f89d 3048 	ldrb.w	r3, [sp, #72]	; 0x48
    2a64:	4604      	mov	r4, r0
    2a66:	9304      	str	r3, [sp, #16]
    2a68:	e9dd 9313 	ldrd	r9, r3, [sp, #76]	; 0x4c
    2a6c:	9305      	str	r3, [sp, #20]
	bool raw_string = (level == LOG_LEVEL_INTERNAL_RAW_STRING);
	uint32_t prefix_offset;
	cbprintf_cb cb;

	if (!raw_string) {
    2a6e:	9b04      	ldr	r3, [sp, #16]
{
    2a70:	460d      	mov	r5, r1
    2a72:	9206      	str	r2, [sp, #24]
	if (!raw_string) {
    2a74:	2b00      	cmp	r3, #0
    2a76:	f000 8087 	beq.w	2b88 <log_output_process+0x134>
	bool level_on = flags & LOG_OUTPUT_FLAG_LEVEL;
    2a7a:	f006 0308 	and.w	r3, r6, #8
    2a7e:	9307      	str	r3, [sp, #28]
	const char *tag = IS_ENABLED(CONFIG_LOG) ? z_log_get_tag() : NULL;
    2a80:	f006 fd12 	bl	94a8 <z_log_get_tag>
	bool stamp = flags & LOG_OUTPUT_FLAG_TIMESTAMP;
    2a84:	f006 0a02 	and.w	sl, r6, #2
	if (tag) {
    2a88:	4602      	mov	r2, r0
    2a8a:	2800      	cmp	r0, #0
    2a8c:	d04b      	beq.n	2b26 <log_output_process+0xd2>
		length += print_formatted(output, "%s ", tag);
    2a8e:	4620      	mov	r0, r4
    2a90:	498d      	ldr	r1, [pc, #564]	; (2cc8 <log_output_process+0x274>)
    2a92:	f7ff ff93 	bl	29bc <print_formatted>
    2a96:	4680      	mov	r8, r0
	if (stamp) {
    2a98:	f1ba 0f00 	cmp.w	sl, #0
    2a9c:	d008      	beq.n	2ab0 <log_output_process+0x5c>
	if (!format) {
    2a9e:	f016 0f44 	tst.w	r6, #68	; 0x44
    2aa2:	d142      	bne.n	2b2a <log_output_process+0xd6>
		length = print_formatted(output, "[%08lu] ", timestamp);
    2aa4:	462a      	mov	r2, r5
    2aa6:	4620      	mov	r0, r4
    2aa8:	4988      	ldr	r1, [pc, #544]	; (2ccc <log_output_process+0x278>)
    2aaa:	f7ff ff87 	bl	29bc <print_formatted>
		length += timestamp_print(output, flags, timestamp);
    2aae:	4480      	add	r8, r0
	if (color) {
    2ab0:	f006 0301 	and.w	r3, r6, #1
    2ab4:	b15b      	cbz	r3, 2ace <log_output_process+0x7a>
		const char *log_color = start && (colors[level] != NULL) ?
    2ab6:	4b86      	ldr	r3, [pc, #536]	; (2cd0 <log_output_process+0x27c>)
    2ab8:	9a04      	ldr	r2, [sp, #16]
		print_formatted(output, "%s", log_color);
    2aba:	4620      	mov	r0, r4
		const char *log_color = start && (colors[level] != NULL) ?
    2abc:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
		print_formatted(output, "%s", log_color);
    2ac0:	4b84      	ldr	r3, [pc, #528]	; (2cd4 <log_output_process+0x280>)
    2ac2:	4985      	ldr	r1, [pc, #532]	; (2cd8 <log_output_process+0x284>)
    2ac4:	2a00      	cmp	r2, #0
    2ac6:	bf08      	it	eq
    2ac8:	461a      	moveq	r2, r3
    2aca:	f7ff ff77 	bl	29bc <print_formatted>
	if (level_on) {
    2ace:	f006 0308 	and.w	r3, r6, #8
    2ad2:	2b00      	cmp	r3, #0
    2ad4:	d055      	beq.n	2b82 <log_output_process+0x12e>
		total += print_formatted(output, "<%s> ", severity[level]);
    2ad6:	4b81      	ldr	r3, [pc, #516]	; (2cdc <log_output_process+0x288>)
    2ad8:	9a04      	ldr	r2, [sp, #16]
    2ada:	4620      	mov	r0, r4
    2adc:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    2ae0:	497f      	ldr	r1, [pc, #508]	; (2ce0 <log_output_process+0x28c>)
    2ae2:	f7ff ff6b 	bl	29bc <print_formatted>
    2ae6:	4605      	mov	r5, r0
	if (domain) {
    2ae8:	9b06      	ldr	r3, [sp, #24]
    2aea:	b12b      	cbz	r3, 2af8 <log_output_process+0xa4>
		total += print_formatted(output, "%s/", domain);
    2aec:	461a      	mov	r2, r3
    2aee:	4620      	mov	r0, r4
    2af0:	497c      	ldr	r1, [pc, #496]	; (2ce4 <log_output_process+0x290>)
    2af2:	f7ff ff63 	bl	29bc <print_formatted>
    2af6:	4405      	add	r5, r0
	if (source) {
    2af8:	f1bb 0f00 	cmp.w	fp, #0
    2afc:	d005      	beq.n	2b0a <log_output_process+0xb6>
		total += print_formatted(output,
    2afe:	465a      	mov	r2, fp
    2b00:	4620      	mov	r0, r4
    2b02:	4979      	ldr	r1, [pc, #484]	; (2ce8 <log_output_process+0x294>)
    2b04:	f7ff ff5a 	bl	29bc <print_formatted>
    2b08:	4405      	add	r5, r0
	length += ids_print(output, level_on, func_on, domain, source, level);
    2b0a:	4445      	add	r5, r8
		 * appending <CR> to the new line character).
		 */
		cb = ((uintptr_t)source == 1) ? out_func : cr_out_func;
	}

	if (package) {
    2b0c:	f1b9 0f00 	cmp.w	r9, #0
    2b10:	d14a      	bne.n	2ba8 <log_output_process+0x154>

		(void)err;
		__ASSERT_NO_MSG(err >= 0);
	}

	if (data_len) {
    2b12:	2f00      	cmp	r7, #0
    2b14:	d161      	bne.n	2bda <log_output_process+0x186>
	if (color) {
    2b16:	07f3      	lsls	r3, r6, #31
    2b18:	f100 80cf 	bmi.w	2cba <log_output_process+0x266>
	newline_print(output, flags);
    2b1c:	4631      	mov	r1, r6
    2b1e:	4620      	mov	r0, r4
    2b20:	f7ff ff5e 	bl	29e0 <newline_print>
}
    2b24:	e0c3      	b.n	2cae <log_output_process+0x25a>
	uint32_t length = 0U;
    2b26:	4680      	mov	r8, r0
    2b28:	e7b6      	b.n	2a98 <log_output_process+0x44>
	} else if (freq != 0U) {
    2b2a:	4b70      	ldr	r3, [pc, #448]	; (2cec <log_output_process+0x298>)
    2b2c:	6818      	ldr	r0, [r3, #0]
    2b2e:	2800      	cmp	r0, #0
    2b30:	d0bd      	beq.n	2aae <log_output_process+0x5a>
		timestamp /= timestamp_div;
    2b32:	4b6f      	ldr	r3, [pc, #444]	; (2cf0 <log_output_process+0x29c>)
		ms = (remainder * 1000U) / freq;
    2b34:	f44f 7e7a 	mov.w	lr, #1000	; 0x3e8
		timestamp /= timestamp_div;
    2b38:	681b      	ldr	r3, [r3, #0]
    2b3a:	f44f 6261 	mov.w	r2, #3600	; 0xe10
    2b3e:	fbb5 f5f3 	udiv	r5, r5, r3
		total_seconds = timestamp / freq;
    2b42:	fbb5 f3f0 	udiv	r3, r5, r0
		remainder = timestamp % freq;
    2b46:	fb00 5513 	mls	r5, r0, r3, r5
		ms = (remainder * 1000U) / freq;
    2b4a:	fb0e f505 	mul.w	r5, lr, r5
    2b4e:	fbb3 faf2 	udiv	sl, r3, r2
		us = (1000 * (remainder * 1000U - (ms * freq))) / freq;
    2b52:	fbb5 fcf0 	udiv	ip, r5, r0
		mins = seconds / 60U;
    2b56:	213c      	movs	r1, #60	; 0x3c
    2b58:	fb02 321a 	mls	r2, r2, sl, r3
		us = (1000 * (remainder * 1000U - (ms * freq))) / freq;
    2b5c:	fb00 551c 	mls	r5, r0, ip, r5
		mins = seconds / 60U;
    2b60:	fbb2 f3f1 	udiv	r3, r2, r1
		us = (1000 * (remainder * 1000U - (ms * freq))) / freq;
    2b64:	fb0e f505 	mul.w	r5, lr, r5
    2b68:	fbb5 f5f0 	udiv	r5, r5, r0
				length = print_formatted(output,
    2b6c:	fb01 2213 	mls	r2, r1, r3, r2
    2b70:	4620      	mov	r0, r4
    2b72:	9200      	str	r2, [sp, #0]
    2b74:	e9cd c501 	strd	ip, r5, [sp, #4]
    2b78:	4652      	mov	r2, sl
    2b7a:	495e      	ldr	r1, [pc, #376]	; (2cf4 <log_output_process+0x2a0>)
    2b7c:	f7ff ff1e 	bl	29bc <print_formatted>
    2b80:	e795      	b.n	2aae <log_output_process+0x5a>
	int total = 0;
    2b82:	f006 0508 	and.w	r5, r6, #8
    2b86:	e7af      	b.n	2ae8 <log_output_process+0x94>
		cb = ((uintptr_t)source == 1) ? out_func : cr_out_func;
    2b88:	f1bb 0f01 	cmp.w	fp, #1
    2b8c:	d107      	bne.n	2b9e <log_output_process+0x14a>
	if (package) {
    2b8e:	f1b9 0f00 	cmp.w	r9, #0
    2b92:	d11d      	bne.n	2bd0 <log_output_process+0x17c>
	if (data_len) {
    2b94:	2f00      	cmp	r7, #0
    2b96:	f000 808a 	beq.w	2cae <log_output_process+0x25a>
		prefix_offset = 0;
    2b9a:	2500      	movs	r5, #0
    2b9c:	e01d      	b.n	2bda <log_output_process+0x186>
	if (package) {
    2b9e:	f1b9 0f00 	cmp.w	r9, #0
    2ba2:	d0f7      	beq.n	2b94 <log_output_process+0x140>
		cb = ((uintptr_t)source == 1) ? out_func : cr_out_func;
    2ba4:	4854      	ldr	r0, [pc, #336]	; (2cf8 <log_output_process+0x2a4>)
    2ba6:	e014      	b.n	2bd2 <log_output_process+0x17e>
		cb = out_func;
    2ba8:	4854      	ldr	r0, [pc, #336]	; (2cfc <log_output_process+0x2a8>)
		return cbpprintf_external(out, cbvprintf_tagged_args,
					  ctx, packaged);
	}
#endif

	return cbpprintf_external(out, cbvprintf, ctx, packaged);
    2baa:	464b      	mov	r3, r9
    2bac:	4622      	mov	r2, r4
    2bae:	4954      	ldr	r1, [pc, #336]	; (2d00 <log_output_process+0x2ac>)
    2bb0:	f006 fa1e 	bl	8ff0 <cbpprintf_external>
		__ASSERT_NO_MSG(err >= 0);
    2bb4:	2800      	cmp	r0, #0
    2bb6:	da0e      	bge.n	2bd6 <log_output_process+0x182>
    2bb8:	4952      	ldr	r1, [pc, #328]	; (2d04 <log_output_process+0x2b0>)
    2bba:	4853      	ldr	r0, [pc, #332]	; (2d08 <log_output_process+0x2b4>)
    2bbc:	f44f 7300 	mov.w	r3, #512	; 0x200
    2bc0:	4a52      	ldr	r2, [pc, #328]	; (2d0c <log_output_process+0x2b8>)
    2bc2:	f006 fb70 	bl	92a6 <assert_print>
    2bc6:	f44f 7100 	mov.w	r1, #512	; 0x200
    2bca:	4850      	ldr	r0, [pc, #320]	; (2d0c <log_output_process+0x2b8>)
    2bcc:	f006 fb64 	bl	9298 <assert_post_action>
		cb = ((uintptr_t)source == 1) ? out_func : cr_out_func;
    2bd0:	484a      	ldr	r0, [pc, #296]	; (2cfc <log_output_process+0x2a8>)
		prefix_offset = 0;
    2bd2:	9d04      	ldr	r5, [sp, #16]
    2bd4:	e7e9      	b.n	2baa <log_output_process+0x156>
	if (data_len) {
    2bd6:	2f00      	cmp	r7, #0
    2bd8:	d065      	beq.n	2ca6 <log_output_process+0x252>
		print_formatted(output, " ");
    2bda:	f8df 9134 	ldr.w	r9, [pc, #308]	; 2d10 <log_output_process+0x2bc>
			print_formatted(output, "%02x ", data[i]);
    2bde:	f8df a134 	ldr.w	sl, [pc, #308]	; 2d14 <log_output_process+0x2c0>
		length = MIN(len, HEXDUMP_BYTES_IN_LINE);
    2be2:	2f10      	cmp	r7, #16
	newline_print(output, flags);
    2be4:	4631      	mov	r1, r6
    2be6:	4620      	mov	r0, r4
		length = MIN(len, HEXDUMP_BYTES_IN_LINE);
    2be8:	46b8      	mov	r8, r7
	for (int i = 0; i < prefix_offset; i++) {
    2bea:	f04f 0b00 	mov.w	fp, #0
		length = MIN(len, HEXDUMP_BYTES_IN_LINE);
    2bee:	bf28      	it	cs
    2bf0:	f04f 0810 	movcs.w	r8, #16
	newline_print(output, flags);
    2bf4:	f7ff fef4 	bl	29e0 <newline_print>
	for (int i = 0; i < prefix_offset; i++) {
    2bf8:	455d      	cmp	r5, fp
    2bfa:	dc42      	bgt.n	2c82 <log_output_process+0x22e>
			print_formatted(output, "%02x ", data[i]);
    2bfc:	9b05      	ldr	r3, [sp, #20]
    2bfe:	4651      	mov	r1, sl
    2c00:	4620      	mov	r0, r4
    2c02:	781a      	ldrb	r2, [r3, #0]
    2c04:	f7ff feda 	bl	29bc <print_formatted>
	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    2c08:	f04f 0b01 	mov.w	fp, #1
		if (i > 0 && !(i % 8)) {
    2c0c:	f01b 0f07 	tst.w	fp, #7
    2c10:	d103      	bne.n	2c1a <log_output_process+0x1c6>
			print_formatted(output, " ");
    2c12:	4649      	mov	r1, r9
    2c14:	4620      	mov	r0, r4
    2c16:	f7ff fed1 	bl	29bc <print_formatted>
		if (i < length) {
    2c1a:	45d8      	cmp	r8, fp
    2c1c:	d938      	bls.n	2c90 <log_output_process+0x23c>
			print_formatted(output, "%02x ", data[i]);
    2c1e:	9b05      	ldr	r3, [sp, #20]
    2c20:	4651      	mov	r1, sl
    2c22:	4620      	mov	r0, r4
    2c24:	f813 200b 	ldrb.w	r2, [r3, fp]
    2c28:	f7ff fec8 	bl	29bc <print_formatted>
	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    2c2c:	f10b 0b01 	add.w	fp, fp, #1
    2c30:	f1bb 0f10 	cmp.w	fp, #16
    2c34:	d1ea      	bne.n	2c0c <log_output_process+0x1b8>
	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    2c36:	f04f 0b00 	mov.w	fp, #0
	print_formatted(output, "|");
    2c3a:	4620      	mov	r0, r4
    2c3c:	4936      	ldr	r1, [pc, #216]	; (2d18 <log_output_process+0x2c4>)
    2c3e:	f7ff febd 	bl	29bc <print_formatted>
		if (i < length) {
    2c42:	465a      	mov	r2, fp
			unsigned char c = (unsigned char)data[i];
    2c44:	9b05      	ldr	r3, [sp, #20]
			print_formatted(output, "%c",
    2c46:	4620      	mov	r0, r4
			unsigned char c = (unsigned char)data[i];
    2c48:	5c9a      	ldrb	r2, [r3, r2]
	return (int)((((unsigned)c) >= ' ') &&
    2c4a:	f1a2 0120 	sub.w	r1, r2, #32
			print_formatted(output, "%c",
    2c4e:	295f      	cmp	r1, #95	; 0x5f
    2c50:	bf28      	it	cs
    2c52:	222e      	movcs	r2, #46	; 0x2e
    2c54:	4931      	ldr	r1, [pc, #196]	; (2d1c <log_output_process+0x2c8>)
    2c56:	f7ff feb1 	bl	29bc <print_formatted>
	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    2c5a:	f10b 0b01 	add.w	fp, fp, #1
    2c5e:	f1bb 0f10 	cmp.w	fp, #16
    2c62:	d01a      	beq.n	2c9a <log_output_process+0x246>
		if (i > 0 && !(i % 8)) {
    2c64:	f01b 0f07 	tst.w	fp, #7
    2c68:	d103      	bne.n	2c72 <log_output_process+0x21e>
			print_formatted(output, " ");
    2c6a:	4649      	mov	r1, r9
    2c6c:	4620      	mov	r0, r4
    2c6e:	f7ff fea5 	bl	29bc <print_formatted>
		if (i < length) {
    2c72:	45d8      	cmp	r8, fp
    2c74:	465a      	mov	r2, fp
    2c76:	d8e5      	bhi.n	2c44 <log_output_process+0x1f0>
			print_formatted(output, " ");
    2c78:	4649      	mov	r1, r9
    2c7a:	4620      	mov	r0, r4
    2c7c:	f7ff fe9e 	bl	29bc <print_formatted>
    2c80:	e7eb      	b.n	2c5a <log_output_process+0x206>
		print_formatted(output, " ");
    2c82:	4649      	mov	r1, r9
    2c84:	4620      	mov	r0, r4
    2c86:	f7ff fe99 	bl	29bc <print_formatted>
	for (int i = 0; i < prefix_offset; i++) {
    2c8a:	f10b 0b01 	add.w	fp, fp, #1
    2c8e:	e7b3      	b.n	2bf8 <log_output_process+0x1a4>
			print_formatted(output, "   ");
    2c90:	4620      	mov	r0, r4
    2c92:	4923      	ldr	r1, [pc, #140]	; (2d20 <log_output_process+0x2cc>)
    2c94:	f7ff fe92 	bl	29bc <print_formatted>
    2c98:	e7c8      	b.n	2c2c <log_output_process+0x1d8>
		data += length;
    2c9a:	9b05      	ldr	r3, [sp, #20]
	} while (len);
    2c9c:	ebb7 0708 	subs.w	r7, r7, r8
		data += length;
    2ca0:	4443      	add	r3, r8
    2ca2:	9305      	str	r3, [sp, #20]
	} while (len);
    2ca4:	d19d      	bne.n	2be2 <log_output_process+0x18e>
		log_msg_hexdump(output, (uint8_t *)data, data_len, prefix_offset, flags);
	}

	if (!raw_string) {
    2ca6:	9b04      	ldr	r3, [sp, #16]
    2ca8:	2b00      	cmp	r3, #0
    2caa:	f47f af34 	bne.w	2b16 <log_output_process+0xc2>
		postfix_print(output, flags, level);
	}

	log_output_flush(output);
    2cae:	4620      	mov	r0, r4
}
    2cb0:	b009      	add	sp, #36	; 0x24
    2cb2:	e8bd 4ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
	log_output_flush(output);
    2cb6:	f006 bc3d 	b.w	9534 <log_output_flush>
		print_formatted(output, "%s", log_color);
    2cba:	4620      	mov	r0, r4
    2cbc:	4a05      	ldr	r2, [pc, #20]	; (2cd4 <log_output_process+0x280>)
    2cbe:	4906      	ldr	r1, [pc, #24]	; (2cd8 <log_output_process+0x284>)
    2cc0:	f7ff fe7c 	bl	29bc <print_formatted>
}
    2cc4:	e72a      	b.n	2b1c <log_output_process+0xc8>
    2cc6:	bf00      	nop
    2cc8:	0000a91c 	.word	0x0000a91c
    2ccc:	0000a920 	.word	0x0000a920
    2cd0:	0000a04c 	.word	0x0000a04c
    2cd4:	0000a917 	.word	0x0000a917
    2cd8:	0000a945 	.word	0x0000a945
    2cdc:	0000a060 	.word	0x0000a060
    2ce0:	0000a948 	.word	0x0000a948
    2ce4:	0000a94e 	.word	0x0000a94e
    2ce8:	0000a952 	.word	0x0000a952
    2cec:	20000798 	.word	0x20000798
    2cf0:	20000794 	.word	0x20000794
    2cf4:	0000a929 	.word	0x0000a929
    2cf8:	0000954f 	.word	0x0000954f
    2cfc:	000029fd 	.word	0x000029fd
    2d00:	00009527 	.word	0x00009527
    2d04:	0000a957 	.word	0x0000a957
    2d08:	0000a2e8 	.word	0x0000a2e8
    2d0c:	0000a8b8 	.word	0x0000a8b8
    2d10:	0000a968 	.word	0x0000a968
    2d14:	0000a960 	.word	0x0000a960
    2d18:	0000a96a 	.word	0x0000a96a
    2d1c:	0000a96c 	.word	0x0000a96c
    2d20:	0000a966 	.word	0x0000a966

00002d24 <log_output_msg_process>:

void log_output_msg_process(const struct log_output *output,
			    struct log_msg *msg, uint32_t flags)
{
    2d24:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 *
 * @return Log level.
 */
static inline uint8_t log_msg_get_level(struct log_msg *msg)
{
	return msg->hdr.desc.level;
    2d28:	880f      	ldrh	r7, [r1, #0]
 *
 * @return Pointer to the source data.
 */
static inline const void *log_msg_get_source(struct log_msg *msg)
{
	return msg->hdr.source;
    2d2a:	684b      	ldr	r3, [r1, #4]
    2d2c:	4605      	mov	r5, r0
    2d2e:	460c      	mov	r4, r1
    2d30:	4690      	mov	r8, r2
 *
 * @return Timestamp.
 */
static inline log_timestamp_t log_msg_get_timestamp(struct log_msg *msg)
{
	return msg->hdr.timestamp;
    2d32:	688e      	ldr	r6, [r1, #8]
    2d34:	b086      	sub	sp, #24
	return msg->hdr.desc.level;
    2d36:	f3c7 1782 	ubfx	r7, r7, #6, #3
		/* Remote domain is converting source pointer to ID */
		source_id = (int16_t)(uintptr_t)log_msg_get_source(msg);
	} else {
		void *source = (void *)log_msg_get_source(msg);

		if (source != NULL) {
    2d3a:	b15b      	cbz	r3, 2d54 <log_output_msg_process+0x30>
    2d3c:	4a13      	ldr	r2, [pc, #76]	; (2d8c <log_output_msg_process+0x68>)
    2d3e:	1a9b      	subs	r3, r3, r2
			source_id = IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING) ?
    2d40:	f343 01cf 	sbfx	r1, r3, #3, #16
		} else {
			source_id = -1;
		}
	}

	const char *sname = source_id >= 0 ? log_source_name_get(domain_id, source_id) : NULL;
    2d44:	2900      	cmp	r1, #0
    2d46:	db1f      	blt.n	2d88 <log_output_msg_process+0x64>
	return msg->hdr.desc.domain;
    2d48:	7820      	ldrb	r0, [r4, #0]
    2d4a:	f3c0 00c2 	ubfx	r0, r0, #3, #3
    2d4e:	f7ff fd37 	bl	27c0 <log_source_name_get>
    2d52:	4603      	mov	r3, r0
 *
 * @return pointer to the package.
 */
static inline uint8_t *log_msg_get_package(struct log_msg *msg, size_t *len)
{
	*len = msg->hdr.desc.package_len;
    2d54:	4621      	mov	r1, r4
    2d56:	f851 2b10 	ldr.w	r2, [r1], #16
	*len = msg->hdr.desc.data_len;
    2d5a:	8860      	ldrh	r0, [r4, #2]
	*len = msg->hdr.desc.package_len;
    2d5c:	f3c2 2249 	ubfx	r2, r2, #9, #10
	size_t plen, dlen;
	uint8_t *package = log_msg_get_package(msg, &plen);
	uint8_t *data = log_msg_get_data(msg, &dlen);

	log_output_process(output, timestamp, NULL, sname, level,
    2d60:	2a00      	cmp	r2, #0
	return msg->data + msg->hdr.desc.package_len;
    2d62:	eb01 0402 	add.w	r4, r1, r2
    2d66:	bf08      	it	eq
    2d68:	2100      	moveq	r1, #0
	*len = msg->hdr.desc.data_len;
    2d6a:	f3c0 00cb 	ubfx	r0, r0, #3, #12
    2d6e:	e9cd 0803 	strd	r0, r8, [sp, #12]
    2d72:	e9cd 1401 	strd	r1, r4, [sp, #4]
    2d76:	2200      	movs	r2, #0
    2d78:	4631      	mov	r1, r6
    2d7a:	4628      	mov	r0, r5
    2d7c:	9700      	str	r7, [sp, #0]
    2d7e:	f7ff fe69 	bl	2a54 <log_output_process>
			   plen > 0 ? package : NULL, data, dlen, flags);
}
    2d82:	b006      	add	sp, #24
    2d84:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	const char *sname = source_id >= 0 ? log_source_name_get(domain_id, source_id) : NULL;
    2d88:	2300      	movs	r3, #0
    2d8a:	e7e3      	b.n	2d54 <log_output_msg_process+0x30>
    2d8c:	00009f84 	.word	0x00009f84

00002d90 <log_output_dropped_process>:
	static const char postfix[] =
			" messages dropped ---\r\n" DROPPED_COLOR_POSTFIX;
	log_output_func_t outf = output->func;

	cnt = MIN(cnt, 9999);
	len = snprintk(buf, sizeof(buf), "%d", cnt);
    2d90:	f242 730f 	movw	r3, #9999	; 0x270f
{
    2d94:	b573      	push	{r0, r1, r4, r5, r6, lr}
	len = snprintk(buf, sizeof(buf), "%d", cnt);
    2d96:	428b      	cmp	r3, r1
    2d98:	bf28      	it	cs
    2d9a:	460b      	movcs	r3, r1
	log_output_func_t outf = output->func;
    2d9c:	6805      	ldr	r5, [r0, #0]
{
    2d9e:	4604      	mov	r4, r0
	len = snprintk(buf, sizeof(buf), "%d", cnt);
    2da0:	2105      	movs	r1, #5
    2da2:	4668      	mov	r0, sp
    2da4:	4a0d      	ldr	r2, [pc, #52]	; (2ddc <log_output_dropped_process+0x4c>)
    2da6:	f006 f99d 	bl	90e4 <snprintk>
    2daa:	4606      	mov	r6, r0

	buffer_write(outf, (uint8_t *)prefix, sizeof(prefix) - 1,
    2dac:	6863      	ldr	r3, [r4, #4]
    2dae:	4628      	mov	r0, r5
    2db0:	220b      	movs	r2, #11
    2db2:	685b      	ldr	r3, [r3, #4]
    2db4:	490a      	ldr	r1, [pc, #40]	; (2de0 <log_output_dropped_process+0x50>)
    2db6:	f006 fba9 	bl	950c <buffer_write>
		     output->control_block->ctx);
	buffer_write(outf, buf, len, output->control_block->ctx);
    2dba:	6863      	ldr	r3, [r4, #4]
    2dbc:	4632      	mov	r2, r6
    2dbe:	4669      	mov	r1, sp
    2dc0:	4628      	mov	r0, r5
    2dc2:	685b      	ldr	r3, [r3, #4]
    2dc4:	f006 fba2 	bl	950c <buffer_write>
	buffer_write(outf, (uint8_t *)postfix, sizeof(postfix) - 1,
    2dc8:	6863      	ldr	r3, [r4, #4]
    2dca:	221b      	movs	r2, #27
    2dcc:	4628      	mov	r0, r5
    2dce:	685b      	ldr	r3, [r3, #4]
    2dd0:	4904      	ldr	r1, [pc, #16]	; (2de4 <log_output_dropped_process+0x54>)
    2dd2:	f006 fb9b 	bl	950c <buffer_write>
		     output->control_block->ctx);
}
    2dd6:	b002      	add	sp, #8
    2dd8:	bd70      	pop	{r4, r5, r6, pc}
    2dda:	bf00      	nop
    2ddc:	0000b7ab 	.word	0x0000b7ab
    2de0:	0000a98b 	.word	0x0000a98b
    2de4:	0000a96f 	.word	0x0000a96f

00002de8 <log_output_timestamp_freq_set>:
{
	timestamp_div = 1U;
	/* There is no point to have frequency higher than 1MHz (ns are not
	 * printed) and too high frequency leads to overflows in calculations.
	 */
	while (frequency > 1000000) {
    2de8:	2100      	movs	r1, #0
    2dea:	2301      	movs	r3, #1
    2dec:	4a06      	ldr	r2, [pc, #24]	; (2e08 <log_output_timestamp_freq_set+0x20>)
    2dee:	4290      	cmp	r0, r2
    2df0:	d806      	bhi.n	2e00 <log_output_timestamp_freq_set+0x18>
    2df2:	4a06      	ldr	r2, [pc, #24]	; (2e0c <log_output_timestamp_freq_set+0x24>)
    2df4:	b901      	cbnz	r1, 2df8 <log_output_timestamp_freq_set+0x10>
	timestamp_div = 1U;
    2df6:	2301      	movs	r3, #1
    2df8:	6013      	str	r3, [r2, #0]
		frequency /= 2U;
		timestamp_div *= 2U;
	}

	freq = frequency;
    2dfa:	4b05      	ldr	r3, [pc, #20]	; (2e10 <log_output_timestamp_freq_set+0x28>)
    2dfc:	6018      	str	r0, [r3, #0]
}
    2dfe:	4770      	bx	lr
		timestamp_div *= 2U;
    2e00:	2101      	movs	r1, #1
		frequency /= 2U;
    2e02:	0840      	lsrs	r0, r0, #1
		timestamp_div *= 2U;
    2e04:	005b      	lsls	r3, r3, #1
    2e06:	e7f2      	b.n	2dee <log_output_timestamp_freq_set+0x6>
    2e08:	000f4240 	.word	0x000f4240
    2e0c:	20000794 	.word	0x20000794
    2e10:	20000798 	.word	0x20000798

00002e14 <format_set>:
	log_output_func(&log_output_uart, &msg->log, flags);
}

static int format_set(const struct log_backend *const backend, uint32_t log_type)
{
	log_format_current = log_type;
    2e14:	4b01      	ldr	r3, [pc, #4]	; (2e1c <format_set+0x8>)
	return 0;
}
    2e16:	2000      	movs	r0, #0
	log_format_current = log_type;
    2e18:	6019      	str	r1, [r3, #0]
}
    2e1a:	4770      	bx	lr
    2e1c:	200007b0 	.word	0x200007b0

00002e20 <panic>:
	}
}

static void panic(struct log_backend const *const backend)
{
	in_panic = true;
    2e20:	2201      	movs	r2, #1
    2e22:	4b02      	ldr	r3, [pc, #8]	; (2e2c <panic+0xc>)
 * @param output	Log output instance.
 */
static inline void
log_backend_std_panic(const struct log_output *const output)
{
	log_output_flush(output);
    2e24:	4802      	ldr	r0, [pc, #8]	; (2e30 <panic+0x10>)
    2e26:	701a      	strb	r2, [r3, #0]
    2e28:	f006 bb84 	b.w	9534 <log_output_flush>
    2e2c:	200010ca 	.word	0x200010ca
    2e30:	0000a090 	.word	0x0000a090

00002e34 <dropped>:
 * @param cnt		Number of dropped messages.
 */
static inline void
log_backend_std_dropped(const struct log_output *const output, uint32_t cnt)
{
	log_output_dropped_process(output, cnt);
    2e34:	4801      	ldr	r0, [pc, #4]	; (2e3c <dropped+0x8>)
    2e36:	f7ff bfab 	b.w	2d90 <log_output_dropped_process>
    2e3a:	bf00      	nop
    2e3c:	0000a090 	.word	0x0000a090

00002e40 <process>:
{
    2e40:	b510      	push	{r4, lr}
	log_format_func_t log_output_func = log_format_func_t_get(log_format_current);
    2e42:	4b06      	ldr	r3, [pc, #24]	; (2e5c <process+0x1c>)
{
    2e44:	460c      	mov	r4, r1
	log_format_func_t log_output_func = log_format_func_t_get(log_format_current);
    2e46:	6818      	ldr	r0, [r3, #0]
    2e48:	f7ff fae0 	bl	240c <log_format_func_t_get>
	log_output_func(&log_output_uart, &msg->log, flags);
    2e4c:	4621      	mov	r1, r4
}
    2e4e:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	log_format_func_t log_output_func = log_format_func_t_get(log_format_current);
    2e52:	4603      	mov	r3, r0
	log_output_func(&log_output_uart, &msg->log, flags);
    2e54:	220f      	movs	r2, #15
    2e56:	4802      	ldr	r0, [pc, #8]	; (2e60 <process+0x20>)
    2e58:	4718      	bx	r3
    2e5a:	bf00      	nop
    2e5c:	200007b0 	.word	0x200007b0
    2e60:	0000a090 	.word	0x0000a090

00002e64 <char_out>:
{
    2e64:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2e66:	460d      	mov	r5, r1
    2e68:	4604      	mov	r4, r0
					unsigned char out_char)
{
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    2e6a:	4f06      	ldr	r7, [pc, #24]	; (2e84 <char_out+0x20>)
    2e6c:	1846      	adds	r6, r0, r1
		for (size_t i = 0; i < length; i++) {
    2e6e:	42b4      	cmp	r4, r6
    2e70:	d101      	bne.n	2e76 <char_out+0x12>
}
    2e72:	4628      	mov	r0, r5
    2e74:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
			uart_poll_out(uart_dev, data[i]);
    2e76:	f814 1b01 	ldrb.w	r1, [r4], #1
    2e7a:	68bb      	ldr	r3, [r7, #8]
    2e7c:	4801      	ldr	r0, [pc, #4]	; (2e84 <char_out+0x20>)
    2e7e:	685b      	ldr	r3, [r3, #4]
    2e80:	4798      	blx	r3
		for (size_t i = 0; i < length; i++) {
    2e82:	e7f4      	b.n	2e6e <char_out+0xa>
    2e84:	00009d0c 	.word	0x00009d0c

00002e88 <log_backend_uart_init>:
{
    2e88:	b508      	push	{r3, lr}
 */
__syscall bool device_is_ready(const struct device *dev);

static inline bool z_impl_device_is_ready(const struct device *dev)
{
	return z_device_is_ready(dev);
    2e8a:	4807      	ldr	r0, [pc, #28]	; (2ea8 <log_backend_uart_init+0x20>)
    2e8c:	f006 fe44 	bl	9b18 <z_device_is_ready>
	__ASSERT_NO_MSG(device_is_ready(uart_dev));
    2e90:	b948      	cbnz	r0, 2ea6 <log_backend_uart_init+0x1e>
    2e92:	4906      	ldr	r1, [pc, #24]	; (2eac <log_backend_uart_init+0x24>)
    2e94:	4806      	ldr	r0, [pc, #24]	; (2eb0 <log_backend_uart_init+0x28>)
    2e96:	2370      	movs	r3, #112	; 0x70
    2e98:	4a06      	ldr	r2, [pc, #24]	; (2eb4 <log_backend_uart_init+0x2c>)
    2e9a:	f006 fa04 	bl	92a6 <assert_print>
    2e9e:	2170      	movs	r1, #112	; 0x70
    2ea0:	4804      	ldr	r0, [pc, #16]	; (2eb4 <log_backend_uart_init+0x2c>)
    2ea2:	f006 f9f9 	bl	9298 <assert_post_action>
}
    2ea6:	bd08      	pop	{r3, pc}
    2ea8:	00009d0c 	.word	0x00009d0c
    2eac:	0000a9f5 	.word	0x0000a9f5
    2eb0:	0000a2e8 	.word	0x0000a2e8
    2eb4:	0000a9b7 	.word	0x0000a9b7

00002eb8 <pm_state_notify>:
/*
 * Function called to notify when the system is entering / exiting a
 * power state
 */
static inline void pm_state_notify(bool entering_state)
{
    2eb8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    2ebc:	4605      	mov	r5, r0
	__asm__ volatile(
    2ebe:	f04f 0320 	mov.w	r3, #32
    2ec2:	f3ef 8611 	mrs	r6, BASEPRI
    2ec6:	f383 8812 	msr	BASEPRI_MAX, r3
    2eca:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    2ece:	4820      	ldr	r0, [pc, #128]	; (2f50 <pm_state_notify+0x98>)
    2ed0:	f003 ff7c 	bl	6dcc <z_spin_lock_valid>
    2ed4:	b968      	cbnz	r0, 2ef2 <pm_state_notify+0x3a>
    2ed6:	2394      	movs	r3, #148	; 0x94
    2ed8:	4a1e      	ldr	r2, [pc, #120]	; (2f54 <pm_state_notify+0x9c>)
    2eda:	491f      	ldr	r1, [pc, #124]	; (2f58 <pm_state_notify+0xa0>)
    2edc:	481f      	ldr	r0, [pc, #124]	; (2f5c <pm_state_notify+0xa4>)
    2ede:	f006 f9e2 	bl	92a6 <assert_print>
    2ee2:	491b      	ldr	r1, [pc, #108]	; (2f50 <pm_state_notify+0x98>)
    2ee4:	481e      	ldr	r0, [pc, #120]	; (2f60 <pm_state_notify+0xa8>)
    2ee6:	f006 f9de 	bl	92a6 <assert_print>
    2eea:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    2eec:	4819      	ldr	r0, [pc, #100]	; (2f54 <pm_state_notify+0x9c>)
    2eee:	f006 f9d3 	bl	9298 <assert_post_action>
		} else {
			callback = notifier->state_exit;
		}

		if (callback) {
			callback(z_cpus_pm_state[_current_cpu->id].state);
    2ef2:	f04f 090c 	mov.w	r9, #12
	z_spin_lock_set_owner(l);
    2ef6:	4816      	ldr	r0, [pc, #88]	; (2f50 <pm_state_notify+0x98>)
    2ef8:	f003 ff84 	bl	6e04 <z_spin_lock_set_owner>
	return list->head;
    2efc:	4b19      	ldr	r3, [pc, #100]	; (2f64 <pm_state_notify+0xac>)
    2efe:	4f1a      	ldr	r7, [pc, #104]	; (2f68 <pm_state_notify+0xb0>)
    2f00:	681c      	ldr	r4, [r3, #0]
    2f02:	f8df 8068 	ldr.w	r8, [pc, #104]	; 2f6c <pm_state_notify+0xb4>
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    2f06:	b97c      	cbnz	r4, 2f28 <pm_state_notify+0x70>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    2f08:	4811      	ldr	r0, [pc, #68]	; (2f50 <pm_state_notify+0x98>)
    2f0a:	f003 ff6d 	bl	6de8 <z_spin_unlock_valid>
    2f0e:	b9c8      	cbnz	r0, 2f44 <pm_state_notify+0x8c>
    2f10:	23c2      	movs	r3, #194	; 0xc2
    2f12:	4a10      	ldr	r2, [pc, #64]	; (2f54 <pm_state_notify+0x9c>)
    2f14:	4916      	ldr	r1, [pc, #88]	; (2f70 <pm_state_notify+0xb8>)
    2f16:	4811      	ldr	r0, [pc, #68]	; (2f5c <pm_state_notify+0xa4>)
    2f18:	f006 f9c5 	bl	92a6 <assert_print>
    2f1c:	490c      	ldr	r1, [pc, #48]	; (2f50 <pm_state_notify+0x98>)
    2f1e:	4815      	ldr	r0, [pc, #84]	; (2f74 <pm_state_notify+0xbc>)
    2f20:	f006 f9c1 	bl	92a6 <assert_print>
    2f24:	21c2      	movs	r1, #194	; 0xc2
    2f26:	e7e1      	b.n	2eec <pm_state_notify+0x34>
			callback = notifier->state_exit;
    2f28:	e9d4 2301 	ldrd	r2, r3, [r4, #4]
			callback = notifier->state_entry;
    2f2c:	2d00      	cmp	r5, #0
    2f2e:	bf18      	it	ne
    2f30:	4613      	movne	r3, r2
		if (callback) {
    2f32:	b12b      	cbz	r3, 2f40 <pm_state_notify+0x88>
			callback(z_cpus_pm_state[_current_cpu->id].state);
    2f34:	f898 2014 	ldrb.w	r2, [r8, #20]
    2f38:	fb09 f202 	mul.w	r2, r9, r2
    2f3c:	5cb8      	ldrb	r0, [r7, r2]
    2f3e:	4798      	blx	r3
	return node->next;
    2f40:	6824      	ldr	r4, [r4, #0]
    2f42:	e7e0      	b.n	2f06 <pm_state_notify+0x4e>
	__asm__ volatile(
    2f44:	f386 8811 	msr	BASEPRI, r6
    2f48:	f3bf 8f6f 	isb	sy
		}
	}
	k_spin_unlock(&pm_notifier_lock, pm_notifier_key);
}
    2f4c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    2f50:	200007b4 	.word	0x200007b4
    2f54:	0000a51d 	.word	0x0000a51d
    2f58:	0000a576 	.word	0x0000a576
    2f5c:	0000a2e8 	.word	0x0000a2e8
    2f60:	0000a58b 	.word	0x0000a58b
    2f64:	200007d4 	.word	0x200007d4
    2f68:	200007c8 	.word	0x200007c8
    2f6c:	20000ea0 	.word	0x20000ea0
    2f70:	0000a54a 	.word	0x0000a54a
    2f74:	0000a561 	.word	0x0000a561

00002f78 <pm_system_resume>:
 *
 * @return true if the bit was set, false if it wasn't.
 */
static inline bool atomic_test_and_clear_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);
    2f78:	2201      	movs	r2, #1

void pm_system_resume(void)
{
    2f7a:	b570      	push	{r4, r5, r6, lr}
	uint8_t id = CURRENT_CPU;
    2f7c:	4b16      	ldr	r3, [pc, #88]	; (2fd8 <pm_system_resume+0x60>)
    2f7e:	7d1c      	ldrb	r4, [r3, #20]
    2f80:	f004 031f 	and.w	r3, r4, #31
    2f84:	409a      	lsls	r2, r3
	atomic_val_t old;

	old = atomic_and(ATOMIC_ELEM(target, bit), ~mask);
    2f86:	43d0      	mvns	r0, r2
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    2f88:	4b14      	ldr	r3, [pc, #80]	; (2fdc <pm_system_resume+0x64>)
    2f8a:	0961      	lsrs	r1, r4, #5
    2f8c:	eb03 0381 	add.w	r3, r3, r1, lsl #2
    2f90:	e8d3 1fef 	ldaex	r1, [r3]
    2f94:	ea01 0500 	and.w	r5, r1, r0
    2f98:	e8c3 5fe6 	stlex	r6, r5, [r3]
    2f9c:	2e00      	cmp	r6, #0
    2f9e:	d1f7      	bne.n	2f90 <pm_system_resume+0x18>
	 * that caused the wake. This hook will be called from the ISR.
	 * For such CPU LPS states, do post operations and restores here.
	 * The kernel scheduler will get control after the ISR finishes
	 * and it may schedule another thread.
	 */
	if (atomic_test_and_clear_bit(z_post_ops_required, id)) {
    2fa0:	420a      	tst	r2, r1
    2fa2:	d013      	beq.n	2fcc <pm_system_resume+0x54>
	if (pm_state_exit_post_ops != NULL) {
    2fa4:	4b0e      	ldr	r3, [pc, #56]	; (2fe0 <pm_system_resume+0x68>)
    2fa6:	4d0f      	ldr	r5, [pc, #60]	; (2fe4 <pm_system_resume+0x6c>)
    2fa8:	b18b      	cbz	r3, 2fce <pm_system_resume+0x56>
		pm_state_exit_post_ops(info->state, info->substate_id);
    2faa:	230c      	movs	r3, #12
    2fac:	4363      	muls	r3, r4
    2fae:	18ea      	adds	r2, r5, r3
    2fb0:	7851      	ldrb	r1, [r2, #1]
    2fb2:	5ce8      	ldrb	r0, [r5, r3]
    2fb4:	f006 fa3c 	bl	9430 <pm_state_exit_post_ops>
		pm_exit_pos_ops(&z_cpus_pm_state[id]);
		pm_state_notify(false);
    2fb8:	2000      	movs	r0, #0
    2fba:	f7ff ff7d 	bl	2eb8 <pm_state_notify>
		z_cpus_pm_state[id] = (struct pm_state_info){PM_STATE_ACTIVE,
    2fbe:	230c      	movs	r3, #12
    2fc0:	435c      	muls	r4, r3
    2fc2:	2300      	movs	r3, #0
    2fc4:	192a      	adds	r2, r5, r4
    2fc6:	512b      	str	r3, [r5, r4]
    2fc8:	e9c2 3301 	strd	r3, r3, [r2, #4]
			0, 0};
	}
}
    2fcc:	bd70      	pop	{r4, r5, r6, pc}
    2fce:	f383 8811 	msr	BASEPRI, r3
    2fd2:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    2fd6:	e7ef      	b.n	2fb8 <pm_system_resume+0x40>
    2fd8:	20000ea0 	.word	0x20000ea0
    2fdc:	200007dc 	.word	0x200007dc
    2fe0:	00009431 	.word	0x00009431
    2fe4:	200007c8 	.word	0x200007c8

00002fe8 <pm_system_suspend>:

	return true;
}

bool pm_system_suspend(int32_t ticks)
{
    2fe8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint8_t id = CURRENT_CPU;
    2fec:	4b45      	ldr	r3, [pc, #276]	; (3104 <pm_system_suspend+0x11c>)
{
    2fee:	4607      	mov	r7, r0
	uint8_t id = CURRENT_CPU;
    2ff0:	7d1d      	ldrb	r5, [r3, #20]
	__asm__ volatile(
    2ff2:	f04f 0320 	mov.w	r3, #32
    2ff6:	f3ef 8811 	mrs	r8, BASEPRI
    2ffa:	f383 8812 	msr	BASEPRI_MAX, r3
    2ffe:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    3002:	4841      	ldr	r0, [pc, #260]	; (3108 <pm_system_suspend+0x120>)
    3004:	f003 fee2 	bl	6dcc <z_spin_lock_valid>
    3008:	b968      	cbnz	r0, 3026 <pm_system_suspend+0x3e>
    300a:	2394      	movs	r3, #148	; 0x94
    300c:	4a3f      	ldr	r2, [pc, #252]	; (310c <pm_system_suspend+0x124>)
    300e:	4940      	ldr	r1, [pc, #256]	; (3110 <pm_system_suspend+0x128>)
    3010:	4840      	ldr	r0, [pc, #256]	; (3114 <pm_system_suspend+0x12c>)
    3012:	f006 f948 	bl	92a6 <assert_print>
    3016:	493c      	ldr	r1, [pc, #240]	; (3108 <pm_system_suspend+0x120>)
    3018:	483f      	ldr	r0, [pc, #252]	; (3118 <pm_system_suspend+0x130>)
    301a:	f006 f944 	bl	92a6 <assert_print>
    301e:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    3020:	483a      	ldr	r0, [pc, #232]	; (310c <pm_system_suspend+0x124>)
    3022:	f006 f939 	bl	9298 <assert_post_action>
	k_spinlock_key_t key;

	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);

	key = k_spin_lock(&pm_forced_state_lock);
	if (z_cpus_pm_forced_state[id].state != PM_STATE_ACTIVE) {
    3026:	240c      	movs	r4, #12
    3028:	436c      	muls	r4, r5
	z_spin_lock_set_owner(l);
    302a:	4837      	ldr	r0, [pc, #220]	; (3108 <pm_system_suspend+0x120>)
    302c:	f003 feea 	bl	6e04 <z_spin_lock_set_owner>
    3030:	4b3a      	ldr	r3, [pc, #232]	; (311c <pm_system_suspend+0x134>)
    3032:	4e3b      	ldr	r6, [pc, #236]	; (3120 <pm_system_suspend+0x138>)
    3034:	5d19      	ldrb	r1, [r3, r4]
    3036:	191a      	adds	r2, r3, r4
    3038:	b1b9      	cbz	r1, 306a <pm_system_suspend+0x82>
		z_cpus_pm_state[id] = z_cpus_pm_forced_state[id];
    303a:	ca07      	ldmia	r2, {r0, r1, r2}
    303c:	eb06 0c04 	add.w	ip, r6, r4
    3040:	e88c 0007 	stmia.w	ip, {r0, r1, r2}
		z_cpus_pm_forced_state[id].state = PM_STATE_ACTIVE;
    3044:	2200      	movs	r2, #0
    3046:	551a      	strb	r2, [r3, r4]
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    3048:	482f      	ldr	r0, [pc, #188]	; (3108 <pm_system_suspend+0x120>)
    304a:	f003 fecd 	bl	6de8 <z_spin_unlock_valid>
    304e:	4604      	mov	r4, r0
    3050:	b9b0      	cbnz	r0, 3080 <pm_system_suspend+0x98>
    3052:	23c2      	movs	r3, #194	; 0xc2
    3054:	4a2d      	ldr	r2, [pc, #180]	; (310c <pm_system_suspend+0x124>)
    3056:	4933      	ldr	r1, [pc, #204]	; (3124 <pm_system_suspend+0x13c>)
    3058:	482e      	ldr	r0, [pc, #184]	; (3114 <pm_system_suspend+0x12c>)
    305a:	f006 f924 	bl	92a6 <assert_print>
    305e:	492a      	ldr	r1, [pc, #168]	; (3108 <pm_system_suspend+0x120>)
    3060:	4831      	ldr	r0, [pc, #196]	; (3128 <pm_system_suspend+0x140>)
    3062:	f006 f920 	bl	92a6 <assert_print>
    3066:	21c2      	movs	r1, #194	; 0xc2
    3068:	e7da      	b.n	3020 <pm_system_suspend+0x38>
	} else {
		const struct pm_state_info *info;

		info = pm_policy_next_state(id, ticks);
    306a:	4639      	mov	r1, r7
    306c:	4628      	mov	r0, r5
    306e:	f000 f865 	bl	313c <pm_policy_next_state>
		if (info != NULL) {
    3072:	2800      	cmp	r0, #0
    3074:	d0e8      	beq.n	3048 <pm_system_suspend+0x60>
			z_cpus_pm_state[id] = *info;
    3076:	c807      	ldmia	r0, {r0, r1, r2}
    3078:	4434      	add	r4, r6
    307a:	e884 0007 	stmia.w	r4, {r0, r1, r2}
    307e:	e7e3      	b.n	3048 <pm_system_suspend+0x60>
	__asm__ volatile(
    3080:	f388 8811 	msr	BASEPRI, r8
    3084:	f3bf 8f6f 	isb	sy
		}
	}
	k_spin_unlock(&pm_forced_state_lock, key);

	if (z_cpus_pm_state[id].state == PM_STATE_ACTIVE) {
    3088:	230c      	movs	r3, #12
    308a:	436b      	muls	r3, r5
    308c:	18f2      	adds	r2, r6, r3
    308e:	5cf3      	ldrb	r3, [r6, r3]
    3090:	b3ab      	cbz	r3, 30fe <pm_system_suspend+0x116>
		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);
		return false;
	}

	if (ticks != K_TICKS_FOREVER) {
    3092:	1c7b      	adds	r3, r7, #1
    3094:	d00f      	beq.n	30b6 <pm_system_suspend+0xce>
			return (uint32_t)((t * to_hz + off) / from_hz);
    3096:	f44f 4c00 	mov.w	ip, #32768	; 0x8000
    309a:	2100      	movs	r1, #0
    309c:	f8d2 e008 	ldr.w	lr, [r2, #8]
    30a0:	4822      	ldr	r0, [pc, #136]	; (312c <pm_system_suspend+0x144>)
    30a2:	2300      	movs	r3, #0
    30a4:	fbee 010c 	umlal	r0, r1, lr, ip
    30a8:	4a21      	ldr	r2, [pc, #132]	; (3130 <pm_system_suspend+0x148>)
    30aa:	f7fd f853 	bl	154 <__aeabi_uldivmod>
		/*
		 * We need to set the timer to interrupt a little bit early to
		 * accommodate the time required by the CPU to fully wake up.
		 */
		z_set_timeout_expiry(ticks -
    30ae:	2101      	movs	r1, #1
    30b0:	1a38      	subs	r0, r7, r0
    30b2:	f005 fbd3 	bl	885c <z_set_timeout_expiry>
	 * state. We don't want to be scheduled out yet, first we need
	 * to send a notification about leaving the idle state. So,
	 * we lock the scheduler here and unlock just after we have
	 * sent the notification in pm_system_resume().
	 */
	k_sched_lock();
    30b6:	f004 fb0b 	bl	76d0 <k_sched_lock>
	pm_stats_start();
	/* Enter power state */
	pm_state_notify(true);
    30ba:	2001      	movs	r0, #1
    30bc:	f7ff fefc 	bl	2eb8 <pm_state_notify>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    30c0:	4b1c      	ldr	r3, [pc, #112]	; (3134 <pm_system_suspend+0x14c>)
 */
static inline void atomic_set_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);

	(void)atomic_or(ATOMIC_ELEM(target, bit), mask);
    30c2:	096a      	lsrs	r2, r5, #5
    30c4:	eb03 0382 	add.w	r3, r3, r2, lsl #2
	atomic_val_t mask = ATOMIC_MASK(bit);
    30c8:	2201      	movs	r2, #1
    30ca:	f005 011f 	and.w	r1, r5, #31
    30ce:	408a      	lsls	r2, r1
    30d0:	e8d3 0fef 	ldaex	r0, [r3]
    30d4:	4310      	orrs	r0, r2
    30d6:	e8c3 0fe1 	stlex	r1, r0, [r3]
    30da:	2900      	cmp	r1, #0
    30dc:	d1f8      	bne.n	30d0 <pm_system_suspend+0xe8>
	if (pm_state_set != NULL) {
    30de:	4b16      	ldr	r3, [pc, #88]	; (3138 <pm_system_suspend+0x150>)
    30e0:	b133      	cbz	r3, 30f0 <pm_system_suspend+0x108>
		pm_state_set(info->state, info->substate_id);
    30e2:	230c      	movs	r3, #12
    30e4:	436b      	muls	r3, r5
    30e6:	18f2      	adds	r2, r6, r3
    30e8:	7851      	ldrb	r1, [r2, #1]
    30ea:	5cf0      	ldrb	r0, [r6, r3]
    30ec:	f7fe ff84 	bl	1ff8 <pm_state_set>
	if (atomic_add(&z_cpus_active, 1) == 0) {
		pm_resume_devices();
	}
#endif
	pm_stats_update(z_cpus_pm_state[id].state);
	pm_system_resume();
    30f0:	f7ff ff42 	bl	2f78 <pm_system_resume>
	k_sched_unlock();
    30f4:	f004 fb58 	bl	77a8 <k_sched_unlock>
	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);

	return true;
}
    30f8:	4620      	mov	r0, r4
    30fa:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		return false;
    30fe:	461c      	mov	r4, r3
    3100:	e7fa      	b.n	30f8 <pm_system_suspend+0x110>
    3102:	bf00      	nop
    3104:	20000ea0 	.word	0x20000ea0
    3108:	200007b8 	.word	0x200007b8
    310c:	0000a51d 	.word	0x0000a51d
    3110:	0000a576 	.word	0x0000a576
    3114:	0000a2e8 	.word	0x0000a2e8
    3118:	0000a58b 	.word	0x0000a58b
    311c:	200007bc 	.word	0x200007bc
    3120:	200007c8 	.word	0x200007c8
    3124:	0000a54a 	.word	0x0000a54a
    3128:	0000a561 	.word	0x0000a561
    312c:	000f423f 	.word	0x000f423f
    3130:	000f4240 	.word	0x000f4240
    3134:	200007dc 	.word	0x200007dc
    3138:	00001ff9 	.word	0x00001ff9

0000313c <pm_policy_next_state>:
	}
}

#ifdef CONFIG_PM_POLICY_DEFAULT
const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks)
{
    313c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3140:	b085      	sub	sp, #20
    3142:	460e      	mov	r6, r1
	uint8_t num_cpu_states;
	const struct pm_state_info *cpu_states;

	num_cpu_states = pm_state_cpu_get_all(cpu, &cpu_states);
    3144:	a903      	add	r1, sp, #12
    3146:	f000 f843 	bl	31d0 <pm_state_cpu_get_all>
    314a:	f44f 4700 	mov.w	r7, #32768	; 0x8000
    314e:	4604      	mov	r4, r0
    3150:	f04f 0b00 	mov.w	fp, #0

		min_residency = k_us_to_ticks_ceil32(state->min_residency_us);
		exit_latency = k_us_to_ticks_ceil32(state->exit_latency_us);

		/* skip state if it brings too much latency */
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
    3154:	4b1b      	ldr	r3, [pc, #108]	; (31c4 <pm_policy_next_state+0x88>)
    3156:	9d03      	ldr	r5, [sp, #12]
    3158:	f8d3 a000 	ldr.w	sl, [r3]
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
    315c:	1e43      	subs	r3, r0, #1
    315e:	b21b      	sxth	r3, r3
    3160:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    3164:	f8df 8060 	ldr.w	r8, [pc, #96]	; 31c8 <pm_policy_next_state+0x8c>
    3168:	eb05 0583 	add.w	r5, r5, r3, lsl #2
    316c:	b924      	cbnz	r4, 3178 <pm_policy_next_state+0x3c>
		    (ticks >= (min_residency + exit_latency))) {
			return state;
		}
	}

	return NULL;
    316e:	46a1      	mov	r9, r4
}
    3170:	4648      	mov	r0, r9
    3172:	b005      	add	sp, #20
    3174:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    3178:	46c4      	mov	ip, r8
    317a:	4659      	mov	r1, fp
    317c:	6868      	ldr	r0, [r5, #4]
    317e:	2300      	movs	r3, #0
    3180:	fbe0 c107 	umlal	ip, r1, r0, r7
    3184:	4a11      	ldr	r2, [pc, #68]	; (31cc <pm_policy_next_state+0x90>)
    3186:	4660      	mov	r0, ip
    3188:	f7fc ffe4 	bl	154 <__aeabi_uldivmod>
    318c:	46c4      	mov	ip, r8
    318e:	4659      	mov	r1, fp
    3190:	9001      	str	r0, [sp, #4]
    3192:	68a8      	ldr	r0, [r5, #8]
    3194:	2300      	movs	r3, #0
    3196:	fbe0 c107 	umlal	ip, r1, r0, r7
    319a:	4a0c      	ldr	r2, [pc, #48]	; (31cc <pm_policy_next_state+0x90>)
    319c:	4660      	mov	r0, ip
    319e:	f7fc ffd9 	bl	154 <__aeabi_uldivmod>
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
    31a2:	f1ba 3fff 	cmp.w	sl, #4294967295
		const struct pm_state_info *state = &cpu_states[i];
    31a6:	46a9      	mov	r9, r5
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
    31a8:	d001      	beq.n	31ae <pm_policy_next_state+0x72>
    31aa:	4582      	cmp	sl, r0
    31ac:	d905      	bls.n	31ba <pm_policy_next_state+0x7e>
		if ((ticks == K_TICKS_FOREVER) ||
    31ae:	1c73      	adds	r3, r6, #1
    31b0:	d0de      	beq.n	3170 <pm_policy_next_state+0x34>
		    (ticks >= (min_residency + exit_latency))) {
    31b2:	9b01      	ldr	r3, [sp, #4]
    31b4:	4418      	add	r0, r3
		if ((ticks == K_TICKS_FOREVER) ||
    31b6:	42b0      	cmp	r0, r6
    31b8:	d9da      	bls.n	3170 <pm_policy_next_state+0x34>
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
    31ba:	3c01      	subs	r4, #1
    31bc:	b2a4      	uxth	r4, r4
    31be:	3d0c      	subs	r5, #12
    31c0:	e7d4      	b.n	316c <pm_policy_next_state+0x30>
    31c2:	bf00      	nop
    31c4:	20000008 	.word	0x20000008
    31c8:	000f423f 	.word	0x000f423f
    31cc:	000f4240 	.word	0x000f4240

000031d0 <pm_state_cpu_get_all>:
	DT_FOREACH_CHILD_SEP(DT_PATH(cpus), DT_NUM_CPU_POWER_STATES, (,))
};

uint8_t pm_state_cpu_get_all(uint8_t cpu, const struct pm_state_info **states)
{
	if (cpu >= ARRAY_SIZE(cpus_states)) {
    31d0:	b908      	cbnz	r0, 31d6 <pm_state_cpu_get_all+0x6>
		return 0;
	}

	*states = cpus_states[cpu];
    31d2:	4b02      	ldr	r3, [pc, #8]	; (31dc <pm_state_cpu_get_all+0xc>)
    31d4:	600b      	str	r3, [r1, #0]

	return states_per_cpu[cpu];
}
    31d6:	2000      	movs	r0, #0
    31d8:	4770      	bx	lr
    31da:	bf00      	nop
    31dc:	0000a0a0 	.word	0x0000a0a0

000031e0 <nrf_cc3xx_platform_abort_init>:

/** @brief Function to initialize the nrf_cc3xx_platform abort APIs.
 */
void nrf_cc3xx_platform_abort_init(void)
{
	nrf_cc3xx_platform_set_abort(&apis);
    31e0:	4801      	ldr	r0, [pc, #4]	; (31e8 <nrf_cc3xx_platform_abort_init+0x8>)
    31e2:	f005 bdc3 	b.w	8d6c <nrf_cc3xx_platform_set_abort>
    31e6:	bf00      	nop
    31e8:	0000a0a0 	.word	0x0000a0a0

000031ec <mutex_free_platform>:
}


/** @brief Static function to free a mutex
 */
static void mutex_free_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    31ec:	b538      	push	{r3, r4, r5, lr}
    /* Ensure that the mutex is valid (not NULL) */
    if (mutex == NULL) {
    31ee:	4604      	mov	r4, r0
    31f0:	b918      	cbnz	r0, 31fa <mutex_free_platform+0xe>
        platform_abort_apis.abort_fn(
    31f2:	4b0f      	ldr	r3, [pc, #60]	; (3230 <mutex_free_platform+0x44>)
    31f4:	480f      	ldr	r0, [pc, #60]	; (3234 <mutex_free_platform+0x48>)
    31f6:	685b      	ldr	r3, [r3, #4]
    31f8:	4798      	blx	r3
            "mutex_init called with NULL parameter");
    }

    /* Check if we are freeing a mutex that is atomic */
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
    31fa:	6861      	ldr	r1, [r4, #4]
    31fc:	f5b1 3f68 	cmp.w	r1, #237568	; 0x3a000
    3200:	d00f      	beq.n	3222 <mutex_free_platform+0x36>
    3202:	f5b1 0f68 	cmp.w	r1, #15204352	; 0xe80000
    3206:	d00c      	beq.n	3222 <mutex_free_platform+0x36>
        /*Nothing to free*/
        return;
    }

    /* Check if we are freeing a mutex that isn't initialized */
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    3208:	4d0b      	ldr	r5, [pc, #44]	; (3238 <mutex_free_platform+0x4c>)
    320a:	42a9      	cmp	r1, r5
    320c:	d009      	beq.n	3222 <mutex_free_platform+0x36>
        /*Nothing to free*/
        return;
    }

    /* Check if the mutex was allocated or being statically defined */
    if ((mutex->flags & NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED) != 0) {
    320e:	f411 6168 	ands.w	r1, r1, #3712	; 0xe80
    3212:	d007      	beq.n	3224 <mutex_free_platform+0x38>
        k_mem_slab_free(&mutex_slab, &mutex->mutex);
    3214:	4621      	mov	r1, r4
    3216:	4809      	ldr	r0, [pc, #36]	; (323c <mutex_free_platform+0x50>)
    3218:	f003 fc9e 	bl	6b58 <k_mem_slab_free>
        mutex->mutex = NULL;
    321c:	2300      	movs	r3, #0
    321e:	6023      	str	r3, [r4, #0]
    else {
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    }

    /* Reset the mutex to invalid state */
    mutex->flags = NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID;
    3220:	6065      	str	r5, [r4, #4]
}
    3222:	bd38      	pop	{r3, r4, r5, pc}
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    3224:	2214      	movs	r2, #20
    3226:	6820      	ldr	r0, [r4, #0]
    3228:	f006 f9fd 	bl	9626 <memset>
    322c:	e7f8      	b.n	3220 <mutex_free_platform+0x34>
    322e:	bf00      	nop
    3230:	200000e0 	.word	0x200000e0
    3234:	0000aa2c 	.word	0x0000aa2c
    3238:	a95c5f2c 	.word	0xa95c5f2c
    323c:	20000ce0 	.word	0x20000ce0

00003240 <mutex_lock_platform>:


/** @brief Static function to lock a mutex
 */
static int32_t mutex_lock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    3240:	b508      	push	{r3, lr}
    int ret;
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
    3242:	b360      	cbz	r0, 329e <mutex_lock_platform+0x5e>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    switch (mutex->flags) {
    3244:	6843      	ldr	r3, [r0, #4]
    3246:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    324a:	d00e      	beq.n	326a <mutex_lock_platform+0x2a>
    324c:	f5b3 0f68 	cmp.w	r3, #15204352	; 0xe80000
    3250:	d018      	beq.n	3284 <mutex_lock_platform+0x44>

#endif /* defined(NRF5340_XXAA_APPLICATION) */

    default:
        /* Ensure that the mutex has been initialized */
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    3252:	4a14      	ldr	r2, [pc, #80]	; (32a4 <mutex_lock_platform+0x64>)
    3254:	4293      	cmp	r3, r2
    3256:	d020      	beq.n	329a <mutex_lock_platform+0x5a>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
        }

        p_mutex = (struct k_mutex *)mutex->mutex;
    3258:	6800      	ldr	r0, [r0, #0]
	return z_impl_k_mutex_lock(mutex, timeout);
    325a:	f04f 32ff 	mov.w	r2, #4294967295
    325e:	f04f 33ff 	mov.w	r3, #4294967295
    3262:	f003 fe09 	bl	6e78 <z_impl_k_mutex_lock>

        ret = k_mutex_lock(p_mutex, K_FOREVER);
        if (ret == 0) {
    3266:	b158      	cbz	r0, 3280 <mutex_lock_platform+0x40>
    3268:	e015      	b.n	3296 <mutex_lock_platform+0x56>
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    326a:	2201      	movs	r2, #1
    326c:	6803      	ldr	r3, [r0, #0]
    326e:	e8d3 1fef 	ldaex	r1, [r3]
    3272:	2900      	cmp	r1, #0
    3274:	d103      	bne.n	327e <mutex_lock_platform+0x3e>
    3276:	e8c3 2fe0 	stlex	r0, r2, [r3]
    327a:	2800      	cmp	r0, #0
    327c:	d1f7      	bne.n	326e <mutex_lock_platform+0x2e>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    327e:	d10a      	bne.n	3296 <mutex_lock_platform+0x56>
            return NRF_CC3XX_PLATFORM_SUCCESS;
    3280:	2000      	movs	r0, #0
        } else {
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_FAILED;
        }
    }
}
    3282:	bd08      	pop	{r3, pc}
        return nrf_mutex_lock(NRF_MUTEX, *((uint8_t *)mutex->mutex)) ?
    3284:	6803      	ldr	r3, [r0, #0]

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrf_mutex_lock(NRF_MUTEX_Type * p_reg, uint8_t mutex)
{
    return (p_reg->MUTEX[mutex] == MUTEX_MUTEX_MUTEX_Unlocked);
    3286:	4a08      	ldr	r2, [pc, #32]	; (32a8 <mutex_lock_platform+0x68>)
    3288:	781b      	ldrb	r3, [r3, #0]
    328a:	f503 7380 	add.w	r3, r3, #256	; 0x100
    328e:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
                       NRF_CC3XX_PLATFORM_SUCCESS :
    3292:	2b00      	cmp	r3, #0
    3294:	d0f4      	beq.n	3280 <mutex_lock_platform+0x40>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    3296:	4805      	ldr	r0, [pc, #20]	; (32ac <mutex_lock_platform+0x6c>)
    3298:	e7f3      	b.n	3282 <mutex_lock_platform+0x42>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    329a:	4805      	ldr	r0, [pc, #20]	; (32b0 <mutex_lock_platform+0x70>)
    329c:	e7f1      	b.n	3282 <mutex_lock_platform+0x42>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    329e:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    32a2:	e7ee      	b.n	3282 <mutex_lock_platform+0x42>
    32a4:	a95c5f2c 	.word	0xa95c5f2c
    32a8:	50030000 	.word	0x50030000
    32ac:	ffff8fe9 	.word	0xffff8fe9
    32b0:	ffff8fea 	.word	0xffff8fea

000032b4 <mutex_unlock_platform>:

/** @brief Static function to unlock a mutex
 */
static int32_t mutex_unlock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    32b4:	b508      	push	{r3, lr}
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
    32b6:	b320      	cbz	r0, 3302 <mutex_unlock_platform+0x4e>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    switch (mutex->flags)
    32b8:	6843      	ldr	r3, [r0, #4]
    32ba:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    32be:	d009      	beq.n	32d4 <mutex_unlock_platform+0x20>
    32c0:	f5b3 0f68 	cmp.w	r3, #15204352	; 0xe80000
    32c4:	d013      	beq.n	32ee <mutex_unlock_platform+0x3a>

#endif /* defined(NRF5340_XXAA_APPLICATION) */

    default:
        /* Ensure that the mutex has been initialized */
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    32c6:	4a11      	ldr	r2, [pc, #68]	; (330c <mutex_unlock_platform+0x58>)
    32c8:	4293      	cmp	r3, r2
    32ca:	d01d      	beq.n	3308 <mutex_unlock_platform+0x54>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
        }

        p_mutex = (struct k_mutex *)mutex->mutex;
    32cc:	6800      	ldr	r0, [r0, #0]
	return z_impl_k_mutex_unlock(mutex);
    32ce:	f003 fea3 	bl	7018 <z_impl_k_mutex_unlock>
    32d2:	e014      	b.n	32fe <mutex_unlock_platform+0x4a>
    32d4:	2200      	movs	r2, #0
    32d6:	6803      	ldr	r3, [r0, #0]
    32d8:	e8d3 1fef 	ldaex	r1, [r3]
    32dc:	2901      	cmp	r1, #1
    32de:	d103      	bne.n	32e8 <mutex_unlock_platform+0x34>
    32e0:	e8c3 2fe0 	stlex	r0, r2, [r3]
    32e4:	2800      	cmp	r0, #0
    32e6:	d1f7      	bne.n	32d8 <mutex_unlock_platform+0x24>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    32e8:	d009      	beq.n	32fe <mutex_unlock_platform+0x4a>
    32ea:	4809      	ldr	r0, [pc, #36]	; (3310 <mutex_unlock_platform+0x5c>)

        k_mutex_unlock(p_mutex);
        return NRF_CC3XX_PLATFORM_SUCCESS;
    }
}
    32ec:	bd08      	pop	{r3, pc}
}

NRF_STATIC_INLINE void nrf_mutex_unlock(NRF_MUTEX_Type * p_reg, uint8_t mutex)
{
    p_reg->MUTEX[mutex] = MUTEX_MUTEX_MUTEX_Unlocked;
    32ee:	2100      	movs	r1, #0
        nrf_mutex_unlock(NRF_MUTEX, *((uint8_t *)mutex->mutex));
    32f0:	6803      	ldr	r3, [r0, #0]
    32f2:	4a08      	ldr	r2, [pc, #32]	; (3314 <mutex_unlock_platform+0x60>)
    32f4:	781b      	ldrb	r3, [r3, #0]
    32f6:	f503 7380 	add.w	r3, r3, #256	; 0x100
    32fa:	f842 1023 	str.w	r1, [r2, r3, lsl #2]
        return NRF_CC3XX_PLATFORM_SUCCESS;
    32fe:	2000      	movs	r0, #0
    3300:	e7f4      	b.n	32ec <mutex_unlock_platform+0x38>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    3302:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    3306:	e7f1      	b.n	32ec <mutex_unlock_platform+0x38>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    3308:	4803      	ldr	r0, [pc, #12]	; (3318 <mutex_unlock_platform+0x64>)
    330a:	e7ef      	b.n	32ec <mutex_unlock_platform+0x38>
    330c:	a95c5f2c 	.word	0xa95c5f2c
    3310:	ffff8fe9 	.word	0xffff8fe9
    3314:	50030000 	.word	0x50030000
    3318:	ffff8fea 	.word	0xffff8fea

0000331c <mutex_init_platform>:
static void mutex_init_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    331c:	b510      	push	{r4, lr}
    if (mutex == NULL) {
    331e:	4604      	mov	r4, r0
    3320:	b918      	cbnz	r0, 332a <mutex_init_platform+0xe>
        platform_abort_apis.abort_fn(
    3322:	4b1d      	ldr	r3, [pc, #116]	; (3398 <mutex_init_platform+0x7c>)
    3324:	481d      	ldr	r0, [pc, #116]	; (339c <mutex_init_platform+0x80>)
    3326:	685b      	ldr	r3, [r3, #4]
    3328:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
    332a:	6863      	ldr	r3, [r4, #4]
    332c:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    3330:	d02f      	beq.n	3392 <mutex_init_platform+0x76>
    3332:	f5b3 0f68 	cmp.w	r3, #15204352	; 0xe80000
    3336:	d02c      	beq.n	3392 <mutex_init_platform+0x76>
    if ((mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID && mutex->mutex == NULL) ||
    3338:	4a19      	ldr	r2, [pc, #100]	; (33a0 <mutex_init_platform+0x84>)
    333a:	4293      	cmp	r3, r2
    333c:	d119      	bne.n	3372 <mutex_init_platform+0x56>
    333e:	6823      	ldr	r3, [r4, #0]
    3340:	bb03      	cbnz	r3, 3384 <mutex_init_platform+0x68>
        ret = k_mem_slab_alloc(&mutex_slab, &mutex->mutex, K_FOREVER);
    3342:	f04f 32ff 	mov.w	r2, #4294967295
    3346:	f04f 33ff 	mov.w	r3, #4294967295
    334a:	4621      	mov	r1, r4
    334c:	4815      	ldr	r0, [pc, #84]	; (33a4 <mutex_init_platform+0x88>)
    334e:	f003 fb99 	bl	6a84 <k_mem_slab_alloc>
        if(ret != 0 || mutex->mutex == NULL)
    3352:	b908      	cbnz	r0, 3358 <mutex_init_platform+0x3c>
    3354:	6823      	ldr	r3, [r4, #0]
    3356:	b91b      	cbnz	r3, 3360 <mutex_init_platform+0x44>
            platform_abort_apis.abort_fn(
    3358:	4b0f      	ldr	r3, [pc, #60]	; (3398 <mutex_init_platform+0x7c>)
    335a:	4813      	ldr	r0, [pc, #76]	; (33a8 <mutex_init_platform+0x8c>)
    335c:	685b      	ldr	r3, [r3, #4]
    335e:	4798      	blx	r3
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    3360:	2214      	movs	r2, #20
    3362:	2100      	movs	r1, #0
    3364:	6820      	ldr	r0, [r4, #0]
    3366:	f006 f95e 	bl	9626 <memset>
        mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED;
    336a:	f44f 6368 	mov.w	r3, #3712	; 0xe80
    336e:	6063      	str	r3, [r4, #4]
    3370:	e008      	b.n	3384 <mutex_init_platform+0x68>
    switch(flags){
    3372:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    3376:	d80d      	bhi.n	3394 <mutex_init_platform+0x78>
    3378:	2b3a      	cmp	r3, #58	; 0x3a
    337a:	d003      	beq.n	3384 <mutex_init_platform+0x68>
    337c:	f640 62ba 	movw	r2, #3770	; 0xeba
    3380:	4293      	cmp	r3, r2
    3382:	d1de      	bne.n	3342 <mutex_init_platform+0x26>
    p_mutex = (struct k_mutex *)mutex->mutex;
    3384:	6820      	ldr	r0, [r4, #0]
	return z_impl_k_mutex_init(mutex);
    3386:	f006 fc12 	bl	9bae <z_impl_k_mutex_init>
    mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_VALID;
    338a:	6863      	ldr	r3, [r4, #4]
    338c:	f043 033a 	orr.w	r3, r3, #58	; 0x3a
    3390:	6063      	str	r3, [r4, #4]
}
    3392:	bd10      	pop	{r4, pc}
    switch(flags){
    3394:	4a05      	ldr	r2, [pc, #20]	; (33ac <mutex_init_platform+0x90>)
    3396:	e7f3      	b.n	3380 <mutex_init_platform+0x64>
    3398:	200000e0 	.word	0x200000e0
    339c:	0000aa2c 	.word	0x0000aa2c
    33a0:	a95c5f2c 	.word	0xa95c5f2c
    33a4:	20000ce0 	.word	0x20000ce0
    33a8:	0000aa52 	.word	0x0000aa52
    33ac:	3a00003a 	.word	0x3a00003a

000033b0 <nrf_cc3xx_platform_mutex_init>:
};

/** @brief Function to initialize the nrf_cc3xx_platform mutex APIs
 */
void nrf_cc3xx_platform_mutex_init(void)
{
    33b0:	b508      	push	{r3, lr}
    k_mem_slab_init(&mutex_slab,
    33b2:	4906      	ldr	r1, [pc, #24]	; (33cc <nrf_cc3xx_platform_mutex_init+0x1c>)
    33b4:	2340      	movs	r3, #64	; 0x40
    33b6:	2214      	movs	r2, #20
    33b8:	4805      	ldr	r0, [pc, #20]	; (33d0 <nrf_cc3xx_platform_mutex_init+0x20>)
    33ba:	f006 fbd2 	bl	9b62 <k_mem_slab_init>
                mutex_slab_buffer,
                sizeof(struct k_mutex),
                NUM_MUTEXES);

    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
}
    33be:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
    33c2:	4904      	ldr	r1, [pc, #16]	; (33d4 <nrf_cc3xx_platform_mutex_init+0x24>)
    33c4:	4804      	ldr	r0, [pc, #16]	; (33d8 <nrf_cc3xx_platform_mutex_init+0x28>)
    33c6:	f005 bd43 	b.w	8e50 <nrf_cc3xx_platform_set_mutexes>
    33ca:	bf00      	nop
    33cc:	200007e0 	.word	0x200007e0
    33d0:	20000ce0 	.word	0x20000ce0
    33d4:	0000a0a8 	.word	0x0000a0a8
    33d8:	0000a0bc 	.word	0x0000a0bc

000033dc <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    33dc:	4901      	ldr	r1, [pc, #4]	; (33e4 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    33de:	2210      	movs	r2, #16
	str	r2, [r1]
    33e0:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    33e2:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    33e4:	e000ed10 	.word	0xe000ed10

000033e8 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    33e8:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    33ea:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    33ec:	f380 8811 	msr	BASEPRI, r0
	isb
    33f0:	f3bf 8f6f 	isb	sy
	 * (i.e. if the caller sets _kernel.idle).
	 */
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */

	/* Enter low power state */
	_sleep_if_allowed wfi
    33f4:	b501      	push	{r0, lr}
    33f6:	f7fe fda3 	bl	1f40 <z_arm_on_enter_cpu_idle>
    33fa:	2800      	cmp	r0, #0
    33fc:	d002      	beq.n	3404 <_skip_0>
    33fe:	f3bf 8f4f 	dsb	sy
    3402:	bf30      	wfi

00003404 <_skip_0>:
    3404:	e8bd 4001 	ldmia.w	sp!, {r0, lr}

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    3408:	b662      	cpsie	i
	isb
    340a:	f3bf 8f6f 	isb	sy

	bx	lr
    340e:	4770      	bx	lr

00003410 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    3410:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    3412:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    3414:	f381 8811 	msr	BASEPRI, r1

	_sleep_if_allowed wfe
    3418:	b501      	push	{r0, lr}
    341a:	f7fe fd91 	bl	1f40 <z_arm_on_enter_cpu_idle>
    341e:	2800      	cmp	r0, #0
    3420:	d002      	beq.n	3428 <_skip_1>
    3422:	f3bf 8f4f 	dsb	sy
    3426:	bf20      	wfe

00003428 <_skip_1>:
    3428:	e8bd 4001 	ldmia.w	sp!, {r0, lr}

	msr	BASEPRI, r0
    342c:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    3430:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    3432:	4770      	bx	lr

00003434 <z_arm_fatal_error>:
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
		esf->basic.pc);
}

void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    3434:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    3438:	4681      	mov	r9, r0

	if (esf != NULL) {
    343a:	460c      	mov	r4, r1
{
    343c:	af00      	add	r7, sp, #0
	if (esf != NULL) {
    343e:	2900      	cmp	r1, #0
    3440:	d04c      	beq.n	34dc <z_arm_fatal_error+0xa8>
	LOG_ERR("r0/a1:  0x%08x  r1/a2:  0x%08x  r2/a3:  0x%08x",
    3442:	e9d1 1200 	ldrd	r1, r2, [r1]
    3446:	466e      	mov	r6, sp
    3448:	b08a      	sub	sp, #40	; 0x28
    344a:	68a3      	ldr	r3, [r4, #8]
    344c:	466d      	mov	r5, sp
    344e:	f04f 0a05 	mov.w	sl, #5
    3452:	46a8      	mov	r8, r5
    3454:	4825      	ldr	r0, [pc, #148]	; (34ec <z_arm_fatal_error+0xb8>)
    3456:	e9c5 2307 	strd	r2, r3, [r5, #28]
    345a:	e9c5 0105 	strd	r0, r1, [r5, #20]
    345e:	f848 af10 	str.w	sl, [r8, #16]!
    3462:	2300      	movs	r3, #0
    3464:	4642      	mov	r2, r8
    3466:	f44f 5121 	mov.w	r1, #10304	; 0x2840
    346a:	4821      	ldr	r0, [pc, #132]	; (34f0 <z_arm_fatal_error+0xbc>)
    346c:	f7ff f9dc 	bl	2828 <z_impl_z_log_msg_static_create>
	LOG_ERR("r3/a4:  0x%08x r12/ip:  0x%08x r14/lr:  0x%08x",
    3470:	e9d4 1203 	ldrd	r1, r2, [r4, #12]
    3474:	46b5      	mov	sp, r6
    3476:	6963      	ldr	r3, [r4, #20]
    3478:	46ad      	mov	sp, r5
    347a:	481e      	ldr	r0, [pc, #120]	; (34f4 <z_arm_fatal_error+0xc0>)
    347c:	e9c5 2307 	strd	r2, r3, [r5, #28]
    3480:	e9c5 0105 	strd	r0, r1, [r5, #20]
    3484:	f8c5 a010 	str.w	sl, [r5, #16]
    3488:	2300      	movs	r3, #0
    348a:	4642      	mov	r2, r8
    348c:	f44f 5121 	mov.w	r1, #10304	; 0x2840
    3490:	4817      	ldr	r0, [pc, #92]	; (34f0 <z_arm_fatal_error+0xbc>)
    3492:	f7ff f9c9 	bl	2828 <z_impl_z_log_msg_static_create>
    3496:	46b5      	mov	sp, r6
	LOG_ERR(" xpsr:  0x%08x", esf->basic.xpsr);
    3498:	b088      	sub	sp, #32
    349a:	69e3      	ldr	r3, [r4, #28]
    349c:	466d      	mov	r5, sp
    349e:	f04f 0a03 	mov.w	sl, #3
    34a2:	46a8      	mov	r8, r5
    34a4:	4a14      	ldr	r2, [pc, #80]	; (34f8 <z_arm_fatal_error+0xc4>)
    34a6:	e9c5 2305 	strd	r2, r3, [r5, #20]
    34aa:	f848 af10 	str.w	sl, [r8, #16]!
    34ae:	2300      	movs	r3, #0
    34b0:	4642      	mov	r2, r8
    34b2:	f44f 51c2 	mov.w	r1, #6208	; 0x1840
    34b6:	480e      	ldr	r0, [pc, #56]	; (34f0 <z_arm_fatal_error+0xbc>)
    34b8:	f7ff f9b6 	bl	2828 <z_impl_z_log_msg_static_create>
    34bc:	46b5      	mov	sp, r6
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
    34be:	69a3      	ldr	r3, [r4, #24]
    34c0:	46ad      	mov	sp, r5
    34c2:	4a0e      	ldr	r2, [pc, #56]	; (34fc <z_arm_fatal_error+0xc8>)
    34c4:	f8c5 a010 	str.w	sl, [r5, #16]
    34c8:	e9c5 2305 	strd	r2, r3, [r5, #20]
    34cc:	2300      	movs	r3, #0
    34ce:	4642      	mov	r2, r8
    34d0:	f44f 51c2 	mov.w	r1, #6208	; 0x1840
    34d4:	4806      	ldr	r0, [pc, #24]	; (34f0 <z_arm_fatal_error+0xbc>)
    34d6:	f7ff f9a7 	bl	2828 <z_impl_z_log_msg_static_create>
    34da:	46b5      	mov	sp, r6
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    34dc:	4621      	mov	r1, r4
    34de:	4648      	mov	r0, r9
    34e0:	f003 f926 	bl	6730 <z_fatal_error>
}
    34e4:	46bd      	mov	sp, r7
    34e6:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    34ea:	bf00      	nop
    34ec:	0000aa7f 	.word	0x0000aa7f
    34f0:	00009fe4 	.word	0x00009fe4
    34f4:	0000aaae 	.word	0x0000aaae
    34f8:	0000aadd 	.word	0x0000aadd
    34fc:	0000aaec 	.word	0x0000aaec

00003500 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    3500:	b240      	sxtb	r0, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    3502:	2800      	cmp	r0, #0
    3504:	db07      	blt.n	3516 <arch_irq_enable+0x16>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    3506:	2301      	movs	r3, #1
    3508:	0941      	lsrs	r1, r0, #5
    350a:	4a03      	ldr	r2, [pc, #12]	; (3518 <arch_irq_enable+0x18>)
    350c:	f000 001f 	and.w	r0, r0, #31
    3510:	4083      	lsls	r3, r0
    3512:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
}
    3516:	4770      	bx	lr
    3518:	e000e100 	.word	0xe000e100

0000351c <arch_irq_disable>:

void arch_irq_disable(unsigned int irq)
{
	NVIC_DisableIRQ((IRQn_Type)irq);
    351c:	b240      	sxtb	r0, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    351e:	2800      	cmp	r0, #0
    3520:	db0c      	blt.n	353c <arch_irq_disable+0x20>
  {
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    3522:	2201      	movs	r2, #1
    3524:	4906      	ldr	r1, [pc, #24]	; (3540 <arch_irq_disable+0x24>)
    3526:	0943      	lsrs	r3, r0, #5
    3528:	f000 001f 	and.w	r0, r0, #31
    352c:	4082      	lsls	r2, r0
    352e:	3320      	adds	r3, #32
    3530:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    3534:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    3538:	f3bf 8f6f 	isb	sy
}
    353c:	4770      	bx	lr
    353e:	bf00      	nop
    3540:	e000e100 	.word	0xe000e100

00003544 <arch_irq_is_enabled>:

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    3544:	4b05      	ldr	r3, [pc, #20]	; (355c <arch_irq_is_enabled+0x18>)
    3546:	0942      	lsrs	r2, r0, #5
    3548:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    354c:	2301      	movs	r3, #1
    354e:	f000 001f 	and.w	r0, r0, #31
    3552:	fa03 f000 	lsl.w	r0, r3, r0
}
    3556:	4010      	ands	r0, r2
    3558:	4770      	bx	lr
    355a:	bf00      	nop
    355c:	e000e100 	.word	0xe000e100

00003560 <z_arm_irq_priority_set>:
 * The priority is verified if ASSERT_ON is enabled. The maximum number
 * of priority levels is a little complex, as there are some hardware
 * priority levels which are reserved.
 */
void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
{
    3560:	b538      	push	{r3, r4, r5, lr}
			prio = _EXC_ZERO_LATENCY_IRQS_PRIO;
		} else {
			/* Use caller supplied prio level as-is */
		}
	} else {
		prio += _IRQ_PRIO_OFFSET;
    3562:	1c4b      	adds	r3, r1, #1
	/* The last priority level is also used by PendSV exception, but
	 * allow other interrupts to use the same level, even if it ends up
	 * affecting performance (can still be useful on systems with a
	 * reduced set of priorities, like Cortex-M0/M0+).
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
    3564:	2b07      	cmp	r3, #7
{
    3566:	4604      	mov	r4, r0
    3568:	460d      	mov	r5, r1
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
    356a:	d90f      	bls.n	358c <z_arm_irq_priority_set+0x2c>
    356c:	235b      	movs	r3, #91	; 0x5b
    356e:	4a10      	ldr	r2, [pc, #64]	; (35b0 <z_arm_irq_priority_set+0x50>)
    3570:	4910      	ldr	r1, [pc, #64]	; (35b4 <z_arm_irq_priority_set+0x54>)
    3572:	4811      	ldr	r0, [pc, #68]	; (35b8 <z_arm_irq_priority_set+0x58>)
    3574:	f005 fe97 	bl	92a6 <assert_print>
    3578:	4629      	mov	r1, r5
    357a:	4810      	ldr	r0, [pc, #64]	; (35bc <z_arm_irq_priority_set+0x5c>)
    357c:	2307      	movs	r3, #7
    357e:	4622      	mov	r2, r4
    3580:	f005 fe91 	bl	92a6 <assert_print>
    3584:	215b      	movs	r1, #91	; 0x5b
    3586:	480a      	ldr	r0, [pc, #40]	; (35b0 <z_arm_irq_priority_set+0x50>)
    3588:	f005 fe86 	bl	9298 <assert_post_action>
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    358c:	b240      	sxtb	r0, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    358e:	2800      	cmp	r0, #0
  {
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    3590:	bfac      	ite	ge
    3592:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
  }
  else
  {
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    3596:	4a0a      	ldrlt	r2, [pc, #40]	; (35c0 <z_arm_irq_priority_set+0x60>)
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    3598:	ea4f 1343 	mov.w	r3, r3, lsl #5
    359c:	b2db      	uxtb	r3, r3
    359e:	bfab      	itete	ge
    35a0:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    35a4:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    35a8:	f880 3300 	strbge.w	r3, [r0, #768]	; 0x300
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    35ac:	5413      	strblt	r3, [r2, r0]
}
    35ae:	bd38      	pop	{r3, r4, r5, pc}
    35b0:	0000ab1a 	.word	0x0000ab1a
    35b4:	0000ab50 	.word	0x0000ab50
    35b8:	0000a2e8 	.word	0x0000a2e8
    35bc:	0000ab6b 	.word	0x0000ab6b
    35c0:	e000ed14 	.word	0xe000ed14

000035c4 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    35c4:	bf30      	wfi
    b z_SysNmiOnReset
    35c6:	f7ff bffd 	b.w	35c4 <z_SysNmiOnReset>
    35ca:	bf00      	nop

000035cc <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    35cc:	4a0b      	ldr	r2, [pc, #44]	; (35fc <z_arm_prep_c+0x30>)
 *
 * This routine prepares for the execution of and runs C code.
 *
 */
void z_arm_prep_c(void)
{
    35ce:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    35d0:	4b0b      	ldr	r3, [pc, #44]	; (3600 <z_arm_prep_c+0x34>)
    35d2:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    35d6:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    35d8:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    35dc:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    35e0:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    35e4:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    35e8:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    35ec:	f003 f972 	bl	68d4 <z_bss_zero>
	z_data_copy();
    35f0:	f004 ff74 	bl	84dc <z_data_copy>
#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    35f4:	f000 fbec 	bl	3dd0 <z_arm_interrupt_init>
	z_cstart();
    35f8:	f003 f9ac 	bl	6954 <z_cstart>
    35fc:	00000000 	.word	0x00000000
    3600:	e000ed00 	.word	0xe000ed00

00003604 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    3604:	4a09      	ldr	r2, [pc, #36]	; (362c <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    3606:	490a      	ldr	r1, [pc, #40]	; (3630 <arch_swap+0x2c>)
	_current->arch.basepri = key;
    3608:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    360a:	6809      	ldr	r1, [r1, #0]
	_current->arch.basepri = key;
    360c:	6758      	str	r0, [r3, #116]	; 0x74
	_current->arch.swap_return_value = _k_neg_eagain;
    360e:	6799      	str	r1, [r3, #120]	; 0x78

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    3610:	4908      	ldr	r1, [pc, #32]	; (3634 <arch_swap+0x30>)
    3612:	684b      	ldr	r3, [r1, #4]
    3614:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    3618:	604b      	str	r3, [r1, #4]
    361a:	2300      	movs	r3, #0
    361c:	f383 8811 	msr	BASEPRI, r3
    3620:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    3624:	6893      	ldr	r3, [r2, #8]
}
    3626:	6f98      	ldr	r0, [r3, #120]	; 0x78
    3628:	4770      	bx	lr
    362a:	bf00      	nop
    362c:	20000ea0 	.word	0x20000ea0
    3630:	0000a1f8 	.word	0x0000a1f8
    3634:	e000ed00 	.word	0xe000ed00

00003638 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    3638:	4913      	ldr	r1, [pc, #76]	; (3688 <z_arm_pendsv+0x50>)
    ldr r2, [r1, #_kernel_offset_to_current]
    363a:	688a      	ldr	r2, [r1, #8]
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    363c:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    3640:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    3642:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    3646:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    364a:	2020      	movs	r0, #32
    msr BASEPRI_MAX, r0
    364c:	f380 8812 	msr	BASEPRI_MAX, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    3650:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    3654:	4f0d      	ldr	r7, [pc, #52]	; (368c <z_arm_pendsv+0x54>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    3656:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    365a:	69ca      	ldr	r2, [r1, #28]

    str r2, [r1, #_kernel_offset_to_current]
    365c:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    365e:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    3660:	6f50      	ldr	r0, [r2, #116]	; 0x74
    movs r3, #0
    3662:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    3664:	6753      	str	r3, [r2, #116]	; 0x74
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    3666:	f380 8811 	msr	BASEPRI, r0
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    366a:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    366e:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    3672:	f38c 8809 	msr	PSP, ip
#endif

#ifdef CONFIG_BUILTIN_STACK_GUARD
    /* r2 contains k_thread */
    add r0, r2, #0
    3676:	f102 0000 	add.w	r0, r2, #0
    push {r2, lr}
    367a:	b504      	push	{r2, lr}
    bl configure_builtin_stack_guard
    367c:	f005 ff88 	bl	9590 <configure_builtin_stack_guard>
    pop {r2, lr}
    3680:	e8bd 4004 	ldmia.w	sp!, {r2, lr}

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    3684:	4770      	bx	lr
    3686:	0000      	.short	0x0000
    ldr r1, =_kernel
    3688:	20000ea0 	.word	0x20000ea0
    ldr v4, =_SCS_ICSR
    368c:	e000ed04 	.word	0xe000ed04

00003690 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    3690:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    3694:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    3696:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    369a:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    369e:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    36a0:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    36a4:	2902      	cmp	r1, #2
    beq _oops
    36a6:	d0ff      	beq.n	36a8 <_oops>

000036a8 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    36a8:	b501      	push	{r0, lr}
    push {r1, r2}
    push {r4-r11}
    mov  r1, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    bl z_do_kernel_oops
    36aa:	f005 ff62 	bl	9572 <z_do_kernel_oops>
     * the MSP to its value prior to entering the function
     */
    add sp, #40
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    pop {r0, pc}
    36ae:	bd01      	pop	{r0, pc}

000036b0 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    36b0:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    36b4:	9b00      	ldr	r3, [sp, #0]
	iframe->pc &= 0xfffffffe;
    36b6:	490b      	ldr	r1, [pc, #44]	; (36e4 <arch_new_thread+0x34>)
	iframe->a2 = (uint32_t)p1;
    36b8:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->a3 = (uint32_t)p2;
    36bc:	9b01      	ldr	r3, [sp, #4]
	iframe->pc &= 0xfffffffe;
    36be:	f021 0101 	bic.w	r1, r1, #1
	iframe->a3 = (uint32_t)p2;
    36c2:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    36c6:	9b02      	ldr	r3, [sp, #8]
	iframe->pc &= 0xfffffffe;
    36c8:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->a4 = (uint32_t)p3;
    36cc:	f842 3c14 	str.w	r3, [r2, #-20]

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    36d0:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    36d4:	f842 3c04 	str.w	r3, [r2, #-4]
		((uintptr_t)iframe - sizeof(struct __fpu_sf));
	memset(iframe, 0, sizeof(struct __fpu_sf));
#endif

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    36d8:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    36da:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    36dc:	6502      	str	r2, [r0, #80]	; 0x50
	thread->arch.basepri = 0;
    36de:	6743      	str	r3, [r0, #116]	; 0x74
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    36e0:	4770      	bx	lr
    36e2:	bf00      	nop
    36e4:	000090ff 	.word	0x000090ff

000036e8 <arch_switch_to_main_thread>:
void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    36e8:	4b08      	ldr	r3, [pc, #32]	; (370c <arch_switch_to_main_thread+0x24>)
    36ea:	6098      	str	r0, [r3, #8]
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  // without main extensions, the non-secure PSPLIM is RAZ/WI
  (void)ProcStackPtrLimit;
#else
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    36ec:	6e43      	ldr	r3, [r0, #100]	; 0x64
    36ee:	f383 880b 	msr	PSPLIM, r3

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    36f2:	4610      	mov	r0, r2
    36f4:	f381 8809 	msr	PSP, r1
    36f8:	2100      	movs	r1, #0
    36fa:	b663      	cpsie	if
    36fc:	f381 8811 	msr	BASEPRI, r1
    3700:	f3bf 8f6f 	isb	sy
    3704:	2200      	movs	r2, #0
    3706:	2300      	movs	r3, #0
    3708:	f005 fcf9 	bl	90fe <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    370c:	20000ea0 	.word	0x20000ea0

00003710 <_isr_wrapper>:
 *
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    3710:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    3712:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    3714:	4a0b      	ldr	r2, [pc, #44]	; (3744 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    3716:	6990      	ldr	r0, [r2, #24]
	cmp r0, #0
    3718:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    371a:	bf1e      	ittt	ne
	movne	r1, #0
    371c:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    371e:	6191      	strne	r1, [r2, #24]
		blne	z_pm_save_idle_exit
    3720:	f006 fa36 	blne	9b90 <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    3724:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    3726:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    372a:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    372e:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    3732:	4905      	ldr	r1, [pc, #20]	; (3748 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    3734:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    3736:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    3738:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    373a:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    373e:	4903      	ldr	r1, [pc, #12]	; (374c <_isr_wrapper+0x3c>)
	bx r1
    3740:	4708      	bx	r1
    3742:	0000      	.short	0x0000
	ldr r2, =_kernel
    3744:	20000ea0 	.word	0x20000ea0
	ldr r1, =_sw_isr_table
    3748:	00009d3c 	.word	0x00009d3c
	ldr r1, =z_arm_int_exit
    374c:	00003751 	.word	0x00003751

00003750 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    3750:	4b04      	ldr	r3, [pc, #16]	; (3764 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    3752:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    3754:	69d8      	ldr	r0, [r3, #28]
	cmp r0, r1
    3756:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    3758:	d003      	beq.n	3762 <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    375a:	4903      	ldr	r1, [pc, #12]	; (3768 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    375c:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    3760:	600a      	str	r2, [r1, #0]

00003762 <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    3762:	4770      	bx	lr
	ldr r3, =_kernel
    3764:	20000ea0 	.word	0x20000ea0
	ldr r1, =_SCS_ICSR
    3768:	e000ed04 	.word	0xe000ed04

0000376c <mem_manage_fault.constprop.0>:
 *
 * See z_arm_fault_dump() for example.
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
    376c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3770:	b086      	sub	sp, #24
    3772:	4606      	mov	r6, r0
    3774:	460d      	mov	r5, r1
    3776:	af00      	add	r7, sp, #0
			      bool *recoverable)
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");
    3778:	2402      	movs	r4, #2
    377a:	4b4b      	ldr	r3, [pc, #300]	; (38a8 <mem_manage_fault.constprop.0+0x13c>)
    377c:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3780:	617b      	str	r3, [r7, #20]
    3782:	484a      	ldr	r0, [pc, #296]	; (38ac <mem_manage_fault.constprop.0+0x140>)
    3784:	613c      	str	r4, [r7, #16]
    3786:	f107 0210 	add.w	r2, r7, #16
    378a:	f005 ff05 	bl	9598 <z_log_msg_static_create.constprop.0>

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    378e:	4b48      	ldr	r3, [pc, #288]	; (38b0 <mem_manage_fault.constprop.0+0x144>)
    3790:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    3792:	06db      	lsls	r3, r3, #27
    3794:	d509      	bpl.n	37aa <mem_manage_fault.constprop.0+0x3e>
		PR_FAULT_INFO("  Stacking error (context area might be"
    3796:	4b47      	ldr	r3, [pc, #284]	; (38b4 <mem_manage_fault.constprop.0+0x148>)
    3798:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    379c:	e9c7 4304 	strd	r4, r3, [r7, #16]
    37a0:	4842      	ldr	r0, [pc, #264]	; (38ac <mem_manage_fault.constprop.0+0x140>)
    37a2:	f107 0210 	add.w	r2, r7, #16
    37a6:	f005 fef7 	bl	9598 <z_log_msg_static_create.constprop.0>
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    37aa:	4b41      	ldr	r3, [pc, #260]	; (38b0 <mem_manage_fault.constprop.0+0x144>)
    37ac:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    37ae:	0718      	lsls	r0, r3, #28
    37b0:	d50a      	bpl.n	37c8 <mem_manage_fault.constprop.0+0x5c>
		PR_FAULT_INFO("  Unstacking error");
    37b2:	4b41      	ldr	r3, [pc, #260]	; (38b8 <mem_manage_fault.constprop.0+0x14c>)
    37b4:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    37b8:	617b      	str	r3, [r7, #20]
    37ba:	2302      	movs	r3, #2
    37bc:	483b      	ldr	r0, [pc, #236]	; (38ac <mem_manage_fault.constprop.0+0x140>)
    37be:	613b      	str	r3, [r7, #16]
    37c0:	f107 0210 	add.w	r2, r7, #16
    37c4:	f005 fee8 	bl	9598 <z_log_msg_static_create.constprop.0>
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    37c8:	4c39      	ldr	r4, [pc, #228]	; (38b0 <mem_manage_fault.constprop.0+0x144>)
    37ca:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    37cc:	0799      	lsls	r1, r3, #30
    37ce:	d522      	bpl.n	3816 <mem_manage_fault.constprop.0+0xaa>
		PR_FAULT_INFO("  Data Access Violation");
    37d0:	46e8      	mov	r8, sp
    37d2:	4b3a      	ldr	r3, [pc, #232]	; (38bc <mem_manage_fault.constprop.0+0x150>)
    37d4:	f107 0210 	add.w	r2, r7, #16
    37d8:	617b      	str	r3, [r7, #20]
    37da:	2302      	movs	r3, #2
    37dc:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    37e0:	613b      	str	r3, [r7, #16]
    37e2:	4832      	ldr	r0, [pc, #200]	; (38ac <mem_manage_fault.constprop.0+0x140>)
    37e4:	f005 fed8 	bl	9598 <z_log_msg_static_create.constprop.0>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		uint32_t temp = SCB->MMFAR;
    37e8:	6b63      	ldr	r3, [r4, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    37ea:	6aa2      	ldr	r2, [r4, #40]	; 0x28
    37ec:	0612      	lsls	r2, r2, #24
    37ee:	d512      	bpl.n	3816 <mem_manage_fault.constprop.0+0xaa>
			mmfar = temp;
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
    37f0:	b088      	sub	sp, #32
    37f2:	466a      	mov	r2, sp
    37f4:	4932      	ldr	r1, [pc, #200]	; (38c0 <mem_manage_fault.constprop.0+0x154>)
    37f6:	482d      	ldr	r0, [pc, #180]	; (38ac <mem_manage_fault.constprop.0+0x140>)
    37f8:	e9c2 1305 	strd	r1, r3, [r2, #20]
    37fc:	2303      	movs	r3, #3
    37fe:	f44f 51c2 	mov.w	r1, #6208	; 0x1840
    3802:	f842 3f10 	str.w	r3, [r2, #16]!
    3806:	f005 fec7 	bl	9598 <z_log_msg_static_create.constprop.0>
    380a:	46c5      	mov	sp, r8
			if (from_hard_fault != 0) {
    380c:	b11e      	cbz	r6, 3816 <mem_manage_fault.constprop.0+0xaa>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    380e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    3810:	f023 0380 	bic.w	r3, r3, #128	; 0x80
    3814:	62a3      	str	r3, [r4, #40]	; 0x28
			}
		}
	}
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    3816:	4b26      	ldr	r3, [pc, #152]	; (38b0 <mem_manage_fault.constprop.0+0x144>)
    3818:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    381a:	07db      	lsls	r3, r3, #31
    381c:	d50a      	bpl.n	3834 <mem_manage_fault.constprop.0+0xc8>
		PR_FAULT_INFO("  Instruction Access Violation");
    381e:	4b29      	ldr	r3, [pc, #164]	; (38c4 <mem_manage_fault.constprop.0+0x158>)
    3820:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3824:	617b      	str	r3, [r7, #20]
    3826:	2302      	movs	r3, #2
    3828:	4820      	ldr	r0, [pc, #128]	; (38ac <mem_manage_fault.constprop.0+0x140>)
    382a:	613b      	str	r3, [r7, #16]
    382c:	f107 0210 	add.w	r2, r7, #16
    3830:	f005 feb2 	bl	9598 <z_log_msg_static_create.constprop.0>
	}
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    3834:	4b1e      	ldr	r3, [pc, #120]	; (38b0 <mem_manage_fault.constprop.0+0x144>)
    3836:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    3838:	069e      	lsls	r6, r3, #26
    383a:	d50a      	bpl.n	3852 <mem_manage_fault.constprop.0+0xe6>
		PR_FAULT_INFO(
    383c:	4b22      	ldr	r3, [pc, #136]	; (38c8 <mem_manage_fault.constprop.0+0x15c>)
    383e:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3842:	617b      	str	r3, [r7, #20]
    3844:	2302      	movs	r3, #2
    3846:	4819      	ldr	r0, [pc, #100]	; (38ac <mem_manage_fault.constprop.0+0x140>)
    3848:	613b      	str	r3, [r7, #16]
    384a:	f107 0210 	add.w	r2, r7, #16
    384e:	f005 fea3 	bl	9598 <z_log_msg_static_create.constprop.0>
	 * crossed into an area beyond the thread stack.]
	 *
	 * Data Access Violation errors may or may not be caused by
	 * thread stack overflows.
	 */
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    3852:	4b17      	ldr	r3, [pc, #92]	; (38b0 <mem_manage_fault.constprop.0+0x144>)
    3854:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    3856:	06d4      	lsls	r4, r2, #27
    3858:	d402      	bmi.n	3860 <mem_manage_fault.constprop.0+0xf4>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    385a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    385c:	0790      	lsls	r0, r2, #30
    385e:	d511      	bpl.n	3884 <mem_manage_fault.constprop.0+0x118>
					"Stacking error not a stack fail\n");
			}
		}
#else
	(void)mmfar;
	__ASSERT(!(SCB->CFSR & SCB_CFSR_MSTKERR_Msk),
    3860:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    3862:	06d9      	lsls	r1, r3, #27
    3864:	d50e      	bpl.n	3884 <mem_manage_fault.constprop.0+0x118>
    3866:	4919      	ldr	r1, [pc, #100]	; (38cc <mem_manage_fault.constprop.0+0x160>)
    3868:	f44f 73ae 	mov.w	r3, #348	; 0x15c
    386c:	4a18      	ldr	r2, [pc, #96]	; (38d0 <mem_manage_fault.constprop.0+0x164>)
    386e:	4819      	ldr	r0, [pc, #100]	; (38d4 <mem_manage_fault.constprop.0+0x168>)
    3870:	f005 fd19 	bl	92a6 <assert_print>
    3874:	4818      	ldr	r0, [pc, #96]	; (38d8 <mem_manage_fault.constprop.0+0x16c>)
    3876:	f005 fd16 	bl	92a6 <assert_print>
    387a:	f44f 71ae 	mov.w	r1, #348	; 0x15c
    387e:	4814      	ldr	r0, [pc, #80]	; (38d0 <mem_manage_fault.constprop.0+0x164>)
    3880:	f005 fd0a 	bl	9298 <assert_post_action>

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf, true);
    3884:	2000      	movs	r0, #0
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    3886:	4b0a      	ldr	r3, [pc, #40]	; (38b0 <mem_manage_fault.constprop.0+0x144>)

	return reason;
}
    3888:	3718      	adds	r7, #24
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    388a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    388c:	0692      	lsls	r2, r2, #26
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
    388e:	bf42      	ittt	mi
    3890:	6a5a      	ldrmi	r2, [r3, #36]	; 0x24
    3892:	f422 5200 	bicmi.w	r2, r2, #8192	; 0x2000
    3896:	625a      	strmi	r2, [r3, #36]	; 0x24
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    3898:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    389a:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    389e:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    38a0:	7028      	strb	r0, [r5, #0]
}
    38a2:	46bd      	mov	sp, r7
    38a4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    38a8:	0000abab 	.word	0x0000abab
    38ac:	00009fe4 	.word	0x00009fe4
    38b0:	e000ed00 	.word	0xe000ed00
    38b4:	0000abc1 	.word	0x0000abc1
    38b8:	0000abf4 	.word	0x0000abf4
    38bc:	0000ac07 	.word	0x0000ac07
    38c0:	0000ac1f 	.word	0x0000ac1f
    38c4:	0000ac35 	.word	0x0000ac35
    38c8:	0000ac54 	.word	0x0000ac54
    38cc:	0000acbd 	.word	0x0000acbd
    38d0:	0000ac83 	.word	0x0000ac83
    38d4:	0000a2e8 	.word	0x0000a2e8
    38d8:	0000ad07 	.word	0x0000ad07

000038dc <bus_fault.constprop.0>:
 * See z_arm_fault_dump() for example.
 *
 * @return error code to identify the fatal error reason.
 *
 */
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    38dc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    38e0:	b086      	sub	sp, #24
    38e2:	4606      	mov	r6, r0
    38e4:	460d      	mov	r5, r1
    38e6:	af00      	add	r7, sp, #0
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");
    38e8:	2402      	movs	r4, #2
    38ea:	4b3e      	ldr	r3, [pc, #248]	; (39e4 <bus_fault.constprop.0+0x108>)
    38ec:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    38f0:	617b      	str	r3, [r7, #20]
    38f2:	483d      	ldr	r0, [pc, #244]	; (39e8 <bus_fault.constprop.0+0x10c>)
    38f4:	613c      	str	r4, [r7, #16]
    38f6:	f107 0210 	add.w	r2, r7, #16
    38fa:	f005 fe4d 	bl	9598 <z_log_msg_static_create.constprop.0>

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    38fe:	4b3b      	ldr	r3, [pc, #236]	; (39ec <bus_fault.constprop.0+0x110>)
    3900:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    3902:	04d9      	lsls	r1, r3, #19
    3904:	d509      	bpl.n	391a <bus_fault.constprop.0+0x3e>
		PR_FAULT_INFO("  Stacking error");
    3906:	4b3a      	ldr	r3, [pc, #232]	; (39f0 <bus_fault.constprop.0+0x114>)
    3908:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    390c:	e9c7 4304 	strd	r4, r3, [r7, #16]
    3910:	4835      	ldr	r0, [pc, #212]	; (39e8 <bus_fault.constprop.0+0x10c>)
    3912:	f107 0210 	add.w	r2, r7, #16
    3916:	f005 fe3f 	bl	9598 <z_log_msg_static_create.constprop.0>
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    391a:	4b34      	ldr	r3, [pc, #208]	; (39ec <bus_fault.constprop.0+0x110>)
    391c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    391e:	051a      	lsls	r2, r3, #20
    3920:	d50a      	bpl.n	3938 <bus_fault.constprop.0+0x5c>
		PR_FAULT_INFO("  Unstacking error");
    3922:	4b34      	ldr	r3, [pc, #208]	; (39f4 <bus_fault.constprop.0+0x118>)
    3924:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3928:	617b      	str	r3, [r7, #20]
    392a:	2302      	movs	r3, #2
    392c:	482e      	ldr	r0, [pc, #184]	; (39e8 <bus_fault.constprop.0+0x10c>)
    392e:	613b      	str	r3, [r7, #16]
    3930:	f107 0210 	add.w	r2, r7, #16
    3934:	f005 fe30 	bl	9598 <z_log_msg_static_create.constprop.0>
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    3938:	4c2c      	ldr	r4, [pc, #176]	; (39ec <bus_fault.constprop.0+0x110>)
    393a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    393c:	059b      	lsls	r3, r3, #22
    393e:	d522      	bpl.n	3986 <bus_fault.constprop.0+0xaa>
		PR_FAULT_INFO("  Precise data bus error");
    3940:	46e8      	mov	r8, sp
    3942:	4b2d      	ldr	r3, [pc, #180]	; (39f8 <bus_fault.constprop.0+0x11c>)
    3944:	4828      	ldr	r0, [pc, #160]	; (39e8 <bus_fault.constprop.0+0x10c>)
    3946:	617b      	str	r3, [r7, #20]
    3948:	2302      	movs	r3, #2
    394a:	f107 0210 	add.w	r2, r7, #16
    394e:	613b      	str	r3, [r7, #16]
    3950:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3954:	f005 fe20 	bl	9598 <z_log_msg_static_create.constprop.0>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
    3958:	6ba3      	ldr	r3, [r4, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    395a:	6aa2      	ldr	r2, [r4, #40]	; 0x28
    395c:	0410      	lsls	r0, r2, #16
    395e:	d512      	bpl.n	3986 <bus_fault.constprop.0+0xaa>
			PR_EXC("  BFAR Address: 0x%x", bfar);
    3960:	b088      	sub	sp, #32
    3962:	466a      	mov	r2, sp
    3964:	4925      	ldr	r1, [pc, #148]	; (39fc <bus_fault.constprop.0+0x120>)
    3966:	4820      	ldr	r0, [pc, #128]	; (39e8 <bus_fault.constprop.0+0x10c>)
    3968:	e9c2 1305 	strd	r1, r3, [r2, #20]
    396c:	2303      	movs	r3, #3
    396e:	f44f 51c2 	mov.w	r1, #6208	; 0x1840
    3972:	f842 3f10 	str.w	r3, [r2, #16]!
    3976:	f005 fe0f 	bl	9598 <z_log_msg_static_create.constprop.0>
    397a:	46c5      	mov	sp, r8
			if (from_hard_fault != 0) {
    397c:	b11e      	cbz	r6, 3986 <bus_fault.constprop.0+0xaa>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    397e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    3980:	f423 4300 	bic.w	r3, r3, #32768	; 0x8000
    3984:	62a3      	str	r3, [r4, #40]	; 0x28
			}
		}
	}
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    3986:	4b19      	ldr	r3, [pc, #100]	; (39ec <bus_fault.constprop.0+0x110>)
    3988:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    398a:	0559      	lsls	r1, r3, #21
    398c:	d50a      	bpl.n	39a4 <bus_fault.constprop.0+0xc8>
		PR_FAULT_INFO("  Imprecise data bus error");
    398e:	4b1c      	ldr	r3, [pc, #112]	; (3a00 <bus_fault.constprop.0+0x124>)
    3990:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3994:	617b      	str	r3, [r7, #20]
    3996:	2302      	movs	r3, #2
    3998:	4813      	ldr	r0, [pc, #76]	; (39e8 <bus_fault.constprop.0+0x10c>)
    399a:	613b      	str	r3, [r7, #16]
    399c:	f107 0210 	add.w	r2, r7, #16
    39a0:	f005 fdfa 	bl	9598 <z_log_msg_static_create.constprop.0>
	}
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    39a4:	4b11      	ldr	r3, [pc, #68]	; (39ec <bus_fault.constprop.0+0x110>)
    39a6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    39a8:	05d2      	lsls	r2, r2, #23
    39aa:	d515      	bpl.n	39d8 <bus_fault.constprop.0+0xfc>
		PR_FAULT_INFO("  Instruction bus error");
    39ac:	4b15      	ldr	r3, [pc, #84]	; (3a04 <bus_fault.constprop.0+0x128>)
#if !defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	}
#else
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    39ae:	617b      	str	r3, [r7, #20]
    39b0:	2302      	movs	r3, #2
    39b2:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    39b6:	480c      	ldr	r0, [pc, #48]	; (39e8 <bus_fault.constprop.0+0x10c>)
    39b8:	613b      	str	r3, [r7, #16]
    39ba:	f107 0210 	add.w	r2, r7, #16
    39be:	f005 fdeb 	bl	9598 <z_log_msg_static_create.constprop.0>
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;

	*recoverable = memory_fault_recoverable(esf, true);
    39c2:	2000      	movs	r0, #0
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    39c4:	4a09      	ldr	r2, [pc, #36]	; (39ec <bus_fault.constprop.0+0x110>)

	return reason;
}
    39c6:	3718      	adds	r7, #24
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    39c8:	6a93      	ldr	r3, [r2, #40]	; 0x28
    39ca:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    39ce:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    39d0:	7028      	strb	r0, [r5, #0]
}
    39d2:	46bd      	mov	sp, r7
    39d4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    39d8:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    39da:	049b      	lsls	r3, r3, #18
    39dc:	d5f1      	bpl.n	39c2 <bus_fault.constprop.0+0xe6>
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    39de:	4b0a      	ldr	r3, [pc, #40]	; (3a08 <bus_fault.constprop.0+0x12c>)
    39e0:	e7e5      	b.n	39ae <bus_fault.constprop.0+0xd2>
    39e2:	bf00      	nop
    39e4:	0000ad6b 	.word	0x0000ad6b
    39e8:	00009fe4 	.word	0x00009fe4
    39ec:	e000ed00 	.word	0xe000ed00
    39f0:	0000ad81 	.word	0x0000ad81
    39f4:	0000abf4 	.word	0x0000abf4
    39f8:	0000ad92 	.word	0x0000ad92
    39fc:	0000adab 	.word	0x0000adab
    3a00:	0000adc0 	.word	0x0000adc0
    3a04:	0000addb 	.word	0x0000addb
    3a08:	0000ac54 	.word	0x0000ac54

00003a0c <usage_fault.constprop.0>:
 *
 * See z_arm_fault_dump() for example.
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t usage_fault(const z_arch_esf_t *esf)
    3a0c:	b510      	push	{r4, lr}
    3a0e:	b086      	sub	sp, #24
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");
    3a10:	2402      	movs	r4, #2
    3a12:	4b3a      	ldr	r3, [pc, #232]	; (3afc <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x64>)
    3a14:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3a18:	4839      	ldr	r0, [pc, #228]	; (3b00 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x68>)
    3a1a:	aa04      	add	r2, sp, #16
    3a1c:	9305      	str	r3, [sp, #20]
    3a1e:	9404      	str	r4, [sp, #16]
    3a20:	f005 fdba 	bl	9598 <z_log_msg_static_create.constprop.0>

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    3a24:	4b37      	ldr	r3, [pc, #220]	; (3b04 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x6c>)
    3a26:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    3a28:	019b      	lsls	r3, r3, #6
    3a2a:	d508      	bpl.n	3a3e <usage_fault.constprop.0+0x32>
		PR_FAULT_INFO("  Division by zero");
    3a2c:	4b36      	ldr	r3, [pc, #216]	; (3b08 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x70>)
    3a2e:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3a32:	4833      	ldr	r0, [pc, #204]	; (3b00 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x68>)
    3a34:	aa04      	add	r2, sp, #16
    3a36:	e9cd 4304 	strd	r4, r3, [sp, #16]
    3a3a:	f005 fdad 	bl	9598 <z_log_msg_static_create.constprop.0>
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    3a3e:	4b31      	ldr	r3, [pc, #196]	; (3b04 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x6c>)
    3a40:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    3a42:	01dc      	lsls	r4, r3, #7
    3a44:	d509      	bpl.n	3a5a <usage_fault.constprop.0+0x4e>
		PR_FAULT_INFO("  Unaligned memory access");
    3a46:	4b31      	ldr	r3, [pc, #196]	; (3b0c <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x74>)
    3a48:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3a4c:	9305      	str	r3, [sp, #20]
    3a4e:	2302      	movs	r3, #2
    3a50:	482b      	ldr	r0, [pc, #172]	; (3b00 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x68>)
    3a52:	aa04      	add	r2, sp, #16
    3a54:	9304      	str	r3, [sp, #16]
    3a56:	f005 fd9f 	bl	9598 <z_log_msg_static_create.constprop.0>
	}
#if defined(CONFIG_ARMV8_M_MAINLINE)
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    3a5a:	4b2a      	ldr	r3, [pc, #168]	; (3b04 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x6c>)
    3a5c:	6a9c      	ldr	r4, [r3, #40]	; 0x28
    3a5e:	f414 1480 	ands.w	r4, r4, #1048576	; 0x100000
    3a62:	d009      	beq.n	3a78 <usage_fault.constprop.0+0x6c>
		PR_FAULT_INFO("  Stack overflow (context area not valid)");
    3a64:	2402      	movs	r4, #2
    3a66:	4b2a      	ldr	r3, [pc, #168]	; (3b10 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x78>)
    3a68:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3a6c:	4824      	ldr	r0, [pc, #144]	; (3b00 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x68>)
    3a6e:	aa04      	add	r2, sp, #16
    3a70:	9305      	str	r3, [sp, #20]
    3a72:	9404      	str	r4, [sp, #16]
    3a74:	f005 fd90 	bl	9598 <z_log_msg_static_create.constprop.0>
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    3a78:	4b22      	ldr	r3, [pc, #136]	; (3b04 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x6c>)
    3a7a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    3a7c:	0318      	lsls	r0, r3, #12
    3a7e:	d509      	bpl.n	3a94 <usage_fault.constprop.0+0x88>
		PR_FAULT_INFO("  No coprocessor instructions");
    3a80:	4b24      	ldr	r3, [pc, #144]	; (3b14 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x7c>)
    3a82:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3a86:	9305      	str	r3, [sp, #20]
    3a88:	2302      	movs	r3, #2
    3a8a:	481d      	ldr	r0, [pc, #116]	; (3b00 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x68>)
    3a8c:	aa04      	add	r2, sp, #16
    3a8e:	9304      	str	r3, [sp, #16]
    3a90:	f005 fd82 	bl	9598 <z_log_msg_static_create.constprop.0>
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    3a94:	4b1b      	ldr	r3, [pc, #108]	; (3b04 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x6c>)
    3a96:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    3a98:	0359      	lsls	r1, r3, #13
    3a9a:	d509      	bpl.n	3ab0 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x18>
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
    3a9c:	4b1e      	ldr	r3, [pc, #120]	; (3b18 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x80>)
    3a9e:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3aa2:	9305      	str	r3, [sp, #20]
    3aa4:	2302      	movs	r3, #2
    3aa6:	4816      	ldr	r0, [pc, #88]	; (3b00 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x68>)
    3aa8:	aa04      	add	r2, sp, #16
    3aaa:	9304      	str	r3, [sp, #16]
    3aac:	f005 fd74 	bl	9598 <z_log_msg_static_create.constprop.0>
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    3ab0:	4b14      	ldr	r3, [pc, #80]	; (3b04 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x6c>)
    3ab2:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    3ab4:	039a      	lsls	r2, r3, #14
    3ab6:	d509      	bpl.n	3acc <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x34>
		PR_FAULT_INFO("  Illegal use of the EPSR");
    3ab8:	4b18      	ldr	r3, [pc, #96]	; (3b1c <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x84>)
    3aba:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3abe:	9305      	str	r3, [sp, #20]
    3ac0:	2302      	movs	r3, #2
    3ac2:	480f      	ldr	r0, [pc, #60]	; (3b00 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x68>)
    3ac4:	aa04      	add	r2, sp, #16
    3ac6:	9304      	str	r3, [sp, #16]
    3ac8:	f005 fd66 	bl	9598 <z_log_msg_static_create.constprop.0>
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    3acc:	4b0d      	ldr	r3, [pc, #52]	; (3b04 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x6c>)
    3ace:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    3ad0:	03db      	lsls	r3, r3, #15
    3ad2:	d509      	bpl.n	3ae8 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x50>
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
    3ad4:	4b12      	ldr	r3, [pc, #72]	; (3b20 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x88>)
    3ad6:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3ada:	9305      	str	r3, [sp, #20]
    3adc:	2302      	movs	r3, #2
    3ade:	4808      	ldr	r0, [pc, #32]	; (3b00 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x68>)
    3ae0:	aa04      	add	r2, sp, #16
    3ae2:	9304      	str	r3, [sp, #16]
    3ae4:	f005 fd58 	bl	9598 <z_log_msg_static_create.constprop.0>
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    3ae8:	4a06      	ldr	r2, [pc, #24]	; (3b04 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x6c>)

	return reason;
}
    3aea:	4620      	mov	r0, r4
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    3aec:	6a93      	ldr	r3, [r2, #40]	; 0x28
    3aee:	ea6f 4303 	mvn.w	r3, r3, lsl #16
    3af2:	ea6f 4313 	mvn.w	r3, r3, lsr #16
    3af6:	6293      	str	r3, [r2, #40]	; 0x28
}
    3af8:	b006      	add	sp, #24
    3afa:	bd10      	pop	{r4, pc}
    3afc:	0000adf3 	.word	0x0000adf3
    3b00:	00009fe4 	.word	0x00009fe4
    3b04:	e000ed00 	.word	0xe000ed00
    3b08:	0000ae0b 	.word	0x0000ae0b
    3b0c:	0000ae1e 	.word	0x0000ae1e
    3b10:	0000ae38 	.word	0x0000ae38
    3b14:	0000ae62 	.word	0x0000ae62
    3b18:	0000ae80 	.word	0x0000ae80
    3b1c:	0000aea5 	.word	0x0000aea5
    3b20:	0000aebf 	.word	0x0000aebf

00003b24 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    3b24:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    3b28:	b08b      	sub	sp, #44	; 0x2c
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    3b2a:	4b8a      	ldr	r3, [pc, #552]	; (3d54 <z_arm_fault+0x230>)
{
    3b2c:	4605      	mov	r5, r0
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    3b2e:	6858      	ldr	r0, [r3, #4]
    3b30:	2600      	movs	r6, #0
{
    3b32:	af00      	add	r7, sp, #0
    3b34:	f3c0 0308 	ubfx	r3, r0, #0, #9
    3b38:	f386 8811 	msr	BASEPRI, r6
    3b3c:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    3b40:	f002 447f 	and.w	r4, r2, #4278190080	; 0xff000000
    3b44:	f1b4 4f7f 	cmp.w	r4, #4278190080	; 0xff000000
    3b48:	d10e      	bne.n	3b68 <z_arm_fault+0x44>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    3b4a:	f002 040c 	and.w	r4, r2, #12
    3b4e:	2c08      	cmp	r4, #8
    3b50:	d119      	bne.n	3b86 <z_arm_fault+0x62>
		PR_EXC("SPSEL in thread mode does not indicate PSP");
    3b52:	4b81      	ldr	r3, [pc, #516]	; (3d58 <z_arm_fault+0x234>)
    3b54:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3b58:	61fb      	str	r3, [r7, #28]
    3b5a:	2302      	movs	r3, #2
    3b5c:	487f      	ldr	r0, [pc, #508]	; (3d5c <z_arm_fault+0x238>)
    3b5e:	61bb      	str	r3, [r7, #24]
    3b60:	f107 0218 	add.w	r2, r7, #24
    3b64:	f005 fd18 	bl	9598 <z_log_msg_static_create.constprop.0>

	/* Retrieve the Exception Stack Frame (ESF) to be supplied
	 * as argument to the remainder of the fault handling process.
	 */
	 esf = get_esf(msp, psp, exc_return, &nested_exc);
	__ASSERT(esf != NULL,
    3b68:	497d      	ldr	r1, [pc, #500]	; (3d60 <z_arm_fault+0x23c>)
    3b6a:	f44f 6384 	mov.w	r3, #1056	; 0x420
    3b6e:	4a7d      	ldr	r2, [pc, #500]	; (3d64 <z_arm_fault+0x240>)
    3b70:	487d      	ldr	r0, [pc, #500]	; (3d68 <z_arm_fault+0x244>)
    3b72:	f005 fb98 	bl	92a6 <assert_print>
    3b76:	487d      	ldr	r0, [pc, #500]	; (3d6c <z_arm_fault+0x248>)
    3b78:	f005 fb95 	bl	92a6 <assert_print>
    3b7c:	f44f 6184 	mov.w	r1, #1056	; 0x420
			__ASSERT(0,
    3b80:	4878      	ldr	r0, [pc, #480]	; (3d64 <z_arm_fault+0x240>)
    3b82:	f005 fb89 	bl	9298 <assert_post_action>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    3b86:	0714      	lsls	r4, r2, #28
			ptr_esf =  (z_arch_esf_t *)psp;
    3b88:	bf4c      	ite	mi
    3b8a:	460d      	movmi	r5, r1
			*nested_exc = true;
    3b8c:	2601      	movpl	r6, #1
	__ASSERT(esf != NULL,
    3b8e:	2d00      	cmp	r5, #0
    3b90:	d0ea      	beq.n	3b68 <z_arm_fault+0x44>
	*recoverable = false;
    3b92:	2200      	movs	r2, #0
    3b94:	71fa      	strb	r2, [r7, #7]
	switch (fault) {
    3b96:	1eda      	subs	r2, r3, #3
    3b98:	2a09      	cmp	r2, #9
    3b9a:	f200 80ba 	bhi.w	3d12 <z_arm_fault+0x1ee>
    3b9e:	e8df f002 	tbb	[pc, r2]
    3ba2:	ad05      	.short	0xad05
    3ba4:	b8b890b0 	.word	0xb8b890b0
    3ba8:	b3b8b8b8 	.word	0xb3b8b8b8
	PR_FAULT_INFO("***** HARD FAULT *****");
    3bac:	46e9      	mov	r9, sp
    3bae:	f04f 0802 	mov.w	r8, #2
    3bb2:	4b6f      	ldr	r3, [pc, #444]	; (3d70 <z_arm_fault+0x24c>)
    3bb4:	f107 0218 	add.w	r2, r7, #24
    3bb8:	61fb      	str	r3, [r7, #28]
    3bba:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3bbe:	4867      	ldr	r0, [pc, #412]	; (3d5c <z_arm_fault+0x238>)
    3bc0:	f8c7 8018 	str.w	r8, [r7, #24]
    3bc4:	f005 fce8 	bl	9598 <z_log_msg_static_create.constprop.0>
	*recoverable = false;
    3bc8:	2300      	movs	r3, #0
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    3bca:	4c62      	ldr	r4, [pc, #392]	; (3d54 <z_arm_fault+0x230>)
	*recoverable = false;
    3bcc:	71fb      	strb	r3, [r7, #7]
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    3bce:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    3bd0:	079a      	lsls	r2, r3, #30
    3bd2:	d50b      	bpl.n	3bec <z_arm_fault+0xc8>
		PR_EXC("  Bus fault on vector table read");
    3bd4:	4b67      	ldr	r3, [pc, #412]	; (3d74 <z_arm_fault+0x250>)
		PR_EXC("  Debug event");
    3bd6:	e9c7 8306 	strd	r8, r3, [r7, #24]
	PR_FAULT_INFO(
    3bda:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3bde:	485f      	ldr	r0, [pc, #380]	; (3d5c <z_arm_fault+0x238>)
    3be0:	f107 0218 	add.w	r2, r7, #24
    3be4:	f005 fcd8 	bl	9598 <z_log_msg_static_create.constprop.0>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    3be8:	2400      	movs	r4, #0
    3bea:	e038      	b.n	3c5e <z_arm_fault+0x13a>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    3bec:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    3bee:	2b00      	cmp	r3, #0
    3bf0:	da01      	bge.n	3bf6 <z_arm_fault+0xd2>
		PR_EXC("  Debug event");
    3bf2:	4b61      	ldr	r3, [pc, #388]	; (3d78 <z_arm_fault+0x254>)
    3bf4:	e7ef      	b.n	3bd6 <z_arm_fault+0xb2>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    3bf6:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    3bf8:	005b      	lsls	r3, r3, #1
    3bfa:	d572      	bpl.n	3ce2 <z_arm_fault+0x1be>
		PR_EXC("  Fault escalation (see below)");
    3bfc:	4b5f      	ldr	r3, [pc, #380]	; (3d7c <z_arm_fault+0x258>)
    3bfe:	f107 0218 	add.w	r2, r7, #24
    3c02:	e9c7 8306 	strd	r8, r3, [r7, #24]
    3c06:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    3c0a:	4854      	ldr	r0, [pc, #336]	; (3d5c <z_arm_fault+0x238>)
    3c0c:	f005 fcc4 	bl	9598 <z_log_msg_static_create.constprop.0>
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    3c10:	6963      	ldr	r3, [r4, #20]
	uint16_t *ret_addr = (uint16_t *)esf->basic.pc;
    3c12:	69aa      	ldr	r2, [r5, #24]
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    3c14:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    3c18:	6163      	str	r3, [r4, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    3c1a:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    3c1e:	f3bf 8f6f 	isb	sy
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    3c22:	6963      	ldr	r3, [r4, #20]
	uint16_t fault_insn = *(ret_addr - 1);
    3c24:	f832 2c02 	ldrh.w	r2, [r2, #-2]
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    3c28:	f423 7380 	bic.w	r3, r3, #256	; 0x100
    3c2c:	6163      	str	r3, [r4, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    3c2e:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    3c32:	f3bf 8f6f 	isb	sy
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    3c36:	f64d 7302 	movw	r3, #57090	; 0xdf02
    3c3a:	429a      	cmp	r2, r3
    3c3c:	d12b      	bne.n	3c96 <z_arm_fault+0x172>
			PR_EXC("ARCH_EXCEPT with reason %x\n", esf->basic.r0);
    3c3e:	b088      	sub	sp, #32
    3c40:	682b      	ldr	r3, [r5, #0]
    3c42:	466a      	mov	r2, sp
    3c44:	494e      	ldr	r1, [pc, #312]	; (3d80 <z_arm_fault+0x25c>)
    3c46:	4845      	ldr	r0, [pc, #276]	; (3d5c <z_arm_fault+0x238>)
    3c48:	e9c2 1305 	strd	r1, r3, [r2, #20]
    3c4c:	2303      	movs	r3, #3
    3c4e:	f44f 51c2 	mov.w	r1, #6208	; 0x1840
    3c52:	f842 3f10 	str.w	r3, [r2, #16]!
    3c56:	f005 fc9f 	bl	9598 <z_log_msg_static_create.constprop.0>
    3c5a:	46cd      	mov	sp, r9
			reason = esf->basic.r0;
    3c5c:	682c      	ldr	r4, [r5, #0]
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    3c5e:	79fb      	ldrb	r3, [r7, #7]
    3c60:	b9ab      	cbnz	r3, 3c8e <z_arm_fault+0x16a>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    3c62:	2220      	movs	r2, #32
    3c64:	4629      	mov	r1, r5
    3c66:	f107 0008 	add.w	r0, r7, #8
    3c6a:	f005 fcd1 	bl	9610 <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    3c6e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    3c70:	2e00      	cmp	r6, #0
    3c72:	d069      	beq.n	3d48 <z_arm_fault+0x224>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    3c74:	f3c3 0208 	ubfx	r2, r3, #0, #9
    3c78:	b922      	cbnz	r2, 3c84 <z_arm_fault+0x160>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    3c7a:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    3c7e:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    3c82:	627b      	str	r3, [r7, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    3c84:	4620      	mov	r0, r4
    3c86:	f107 0108 	add.w	r1, r7, #8
    3c8a:	f7ff fbd3 	bl	3434 <z_arm_fatal_error>
}
    3c8e:	372c      	adds	r7, #44	; 0x2c
    3c90:	46bd      	mov	sp, r7
    3c92:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
		} else if ((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) != 0) {
    3c96:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    3c98:	b2db      	uxtb	r3, r3
    3c9a:	b12b      	cbz	r3, 3ca8 <z_arm_fault+0x184>
			reason = mem_manage_fault(esf, 1, recoverable);
    3c9c:	2001      	movs	r0, #1
    3c9e:	1df9      	adds	r1, r7, #7
		reason = mem_manage_fault(esf, 0, recoverable);
    3ca0:	f7ff fd64 	bl	376c <mem_manage_fault.constprop.0>
    3ca4:	4604      	mov	r4, r0
		break;
    3ca6:	e7da      	b.n	3c5e <z_arm_fault+0x13a>
		} else if ((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) != 0) {
    3ca8:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    3caa:	f413 4f7f 	tst.w	r3, #65280	; 0xff00
    3cae:	d004      	beq.n	3cba <z_arm_fault+0x196>
			reason = bus_fault(esf, 1, recoverable);
    3cb0:	2001      	movs	r0, #1
    3cb2:	1df9      	adds	r1, r7, #7
		reason = bus_fault(esf, 0, recoverable);
    3cb4:	f7ff fe12 	bl	38dc <bus_fault.constprop.0>
    3cb8:	e7f4      	b.n	3ca4 <z_arm_fault+0x180>
		} else if ((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) != 0) {
    3cba:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    3cbc:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
    3cc0:	d302      	bcc.n	3cc8 <z_arm_fault+0x1a4>
		reason = usage_fault(esf);
    3cc2:	f7ff fea3 	bl	3a0c <usage_fault.constprop.0>
    3cc6:	e7ed      	b.n	3ca4 <z_arm_fault+0x180>
			__ASSERT(0,
    3cc8:	492e      	ldr	r1, [pc, #184]	; (3d84 <z_arm_fault+0x260>)
    3cca:	f240 23f2 	movw	r3, #754	; 0x2f2
    3cce:	4a25      	ldr	r2, [pc, #148]	; (3d64 <z_arm_fault+0x240>)
    3cd0:	4825      	ldr	r0, [pc, #148]	; (3d68 <z_arm_fault+0x244>)
    3cd2:	f005 fae8 	bl	92a6 <assert_print>
    3cd6:	482c      	ldr	r0, [pc, #176]	; (3d88 <z_arm_fault+0x264>)
    3cd8:	f005 fae5 	bl	92a6 <assert_print>
    3cdc:	f240 21f2 	movw	r1, #754	; 0x2f2
    3ce0:	e74e      	b.n	3b80 <z_arm_fault+0x5c>
		__ASSERT(0,
    3ce2:	4928      	ldr	r1, [pc, #160]	; (3d84 <z_arm_fault+0x260>)
    3ce4:	f240 23f6 	movw	r3, #758	; 0x2f6
    3ce8:	4a1e      	ldr	r2, [pc, #120]	; (3d64 <z_arm_fault+0x240>)
    3cea:	481f      	ldr	r0, [pc, #124]	; (3d68 <z_arm_fault+0x244>)
    3cec:	f005 fadb 	bl	92a6 <assert_print>
    3cf0:	4826      	ldr	r0, [pc, #152]	; (3d8c <z_arm_fault+0x268>)
    3cf2:	f005 fad8 	bl	92a6 <assert_print>
    3cf6:	f240 21f6 	movw	r1, #758	; 0x2f6
    3cfa:	e741      	b.n	3b80 <z_arm_fault+0x5c>
		reason = mem_manage_fault(esf, 0, recoverable);
    3cfc:	2000      	movs	r0, #0
    3cfe:	1df9      	adds	r1, r7, #7
    3d00:	e7ce      	b.n	3ca0 <z_arm_fault+0x17c>
		reason = bus_fault(esf, 0, recoverable);
    3d02:	2000      	movs	r0, #0
    3d04:	1df9      	adds	r1, r7, #7
    3d06:	e7d5      	b.n	3cb4 <z_arm_fault+0x190>
	PR_FAULT_INFO(
    3d08:	4b21      	ldr	r3, [pc, #132]	; (3d90 <z_arm_fault+0x26c>)
    3d0a:	61fb      	str	r3, [r7, #28]
    3d0c:	2302      	movs	r3, #2
    3d0e:	61bb      	str	r3, [r7, #24]
    3d10:	e763      	b.n	3bda <z_arm_fault+0xb6>
	PR_FAULT_INFO("***** %s %d) *****",
    3d12:	4a20      	ldr	r2, [pc, #128]	; (3d94 <z_arm_fault+0x270>)
    3d14:	466c      	mov	r4, sp
    3d16:	f410 7ff8 	tst.w	r0, #496	; 0x1f0
    3d1a:	b08a      	sub	sp, #40	; 0x28
    3d1c:	491e      	ldr	r1, [pc, #120]	; (3d98 <z_arm_fault+0x274>)
    3d1e:	bf18      	it	ne
    3d20:	4611      	movne	r1, r2
    3d22:	466a      	mov	r2, sp
    3d24:	3b10      	subs	r3, #16
    3d26:	61d3      	str	r3, [r2, #28]
    3d28:	f44f 7300 	mov.w	r3, #512	; 0x200
    3d2c:	481b      	ldr	r0, [pc, #108]	; (3d9c <z_arm_fault+0x278>)
    3d2e:	8413      	strh	r3, [r2, #32]
    3d30:	4b1b      	ldr	r3, [pc, #108]	; (3da0 <z_arm_fault+0x27c>)
    3d32:	e9c2 0105 	strd	r0, r1, [r2, #20]
    3d36:	f44f 5111 	mov.w	r1, #9280	; 0x2440
    3d3a:	4808      	ldr	r0, [pc, #32]	; (3d5c <z_arm_fault+0x238>)
    3d3c:	f842 3f10 	str.w	r3, [r2, #16]!
    3d40:	f005 fc2a 	bl	9598 <z_log_msg_static_create.constprop.0>
    3d44:	46a5      	mov	sp, r4
}
    3d46:	e74f      	b.n	3be8 <z_arm_fault+0xc4>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    3d48:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    3d4c:	f023 0301 	bic.w	r3, r3, #1
    3d50:	e797      	b.n	3c82 <z_arm_fault+0x15e>
    3d52:	bf00      	nop
    3d54:	e000ed00 	.word	0xe000ed00
    3d58:	0000af18 	.word	0x0000af18
    3d5c:	00009fe4 	.word	0x00009fe4
    3d60:	0000af43 	.word	0x0000af43
    3d64:	0000ac83 	.word	0x0000ac83
    3d68:	0000a2e8 	.word	0x0000a2e8
    3d6c:	0000af56 	.word	0x0000af56
    3d70:	0000af94 	.word	0x0000af94
    3d74:	0000afab 	.word	0x0000afab
    3d78:	0000afcc 	.word	0x0000afcc
    3d7c:	0000afda 	.word	0x0000afda
    3d80:	0000aff9 	.word	0x0000aff9
    3d84:	0000a5f9 	.word	0x0000a5f9
    3d88:	0000b015 	.word	0x0000b015
    3d8c:	0000b039 	.word	0x0000b039
    3d90:	0000b069 	.word	0x0000b069
    3d94:	0000aeff 	.word	0x0000aeff
    3d98:	0000aeea 	.word	0x0000aeea
    3d9c:	0000b08d 	.word	0x0000b08d
    3da0:	01000004 	.word	0x01000004

00003da4 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    3da4:	4b04      	ldr	r3, [pc, #16]	; (3db8 <z_arm_fault_init+0x14>)
    3da6:	695a      	ldr	r2, [r3, #20]
    3da8:	f042 0210 	orr.w	r2, r2, #16
    3dac:	615a      	str	r2, [r3, #20]
	 *
	 * For Non-Secure Firmware this could allow the Non-Secure Main
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
    3dae:	695a      	ldr	r2, [r3, #20]
    3db0:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
    3db4:	615a      	str	r2, [r3, #20]
#endif /* CONFIG_BUILTIN_STACK_GUARD */
#ifdef CONFIG_TRAP_UNALIGNED_ACCESS
	SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif /* CONFIG_TRAP_UNALIGNED_ACCESS */
}
    3db6:	4770      	bx	lr
    3db8:	e000ed00 	.word	0xe000ed00

00003dbc <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    3dbc:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    3dc0:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    3dc4:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    3dc6:	4672      	mov	r2, lr
	bl z_arm_fault
    3dc8:	f7ff feac 	bl	3b24 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    3dcc:	bd01      	pop	{r0, pc}
    3dce:	bf00      	nop

00003dd0 <z_arm_interrupt_init>:
 *
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    3dd0:	2300      	movs	r3, #0
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    3dd2:	2120      	movs	r1, #32
    3dd4:	4803      	ldr	r0, [pc, #12]	; (3de4 <z_arm_interrupt_init+0x14>)
    3dd6:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    3dd8:	3301      	adds	r3, #1
    3dda:	2b45      	cmp	r3, #69	; 0x45
    3ddc:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    3de0:	d1f9      	bne.n	3dd6 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    3de2:	4770      	bx	lr
    3de4:	e000e100 	.word	0xe000e100

00003de8 <__start>:
    strb r0, [r1]
#endif /* CONFIG_DEBUG_THREAD_INFO */

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    3de8:	2000      	movs	r0, #0
    msr CONTROL, r0
    3dea:	f380 8814 	msr	CONTROL, r0
    isb
    3dee:	f3bf 8f6f 	isb	sy
#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
    /* Clear SPLIM registers */
    movs.n r0, #0
    3df2:	2000      	movs	r0, #0
    msr MSPLIM, r0
    3df4:	f380 880a 	msr	MSPLIM, r0
    msr PSPLIM, r0
    3df8:	f380 880b 	msr	PSPLIM, r0
#if defined(CONFIG_PM_S2RAM)
    bl arch_pm_s2ram_resume
#endif /* CONFIG_PM_S2RAM */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    3dfc:	f7fe fa72 	bl	22e4 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    3e00:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    3e02:	490e      	ldr	r1, [pc, #56]	; (3e3c <__start+0x54>)
    str r0, [r1]
    3e04:	6008      	str	r0, [r1, #0]
    dsb
    3e06:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    3e0a:	480d      	ldr	r0, [pc, #52]	; (3e40 <__start+0x58>)
    msr msp, r0
    3e0c:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    3e10:	f000 f83e 	bl	3e90 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    3e14:	2020      	movs	r0, #32
    msr BASEPRI, r0
    3e16:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    3e1a:	480a      	ldr	r0, [pc, #40]	; (3e44 <__start+0x5c>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    3e1c:	f44f 6100 	mov.w	r1, #2048	; 0x800
    adds r0, r0, r1
    3e20:	1840      	adds	r0, r0, r1
    msr PSP, r0
    3e22:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    3e26:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    3e2a:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    3e2c:	4308      	orrs	r0, r1
    msr CONTROL, r0
    3e2e:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    3e32:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    3e36:	f7ff fbc9 	bl	35cc <z_arm_prep_c>
    3e3a:	0000      	.short	0x0000
    ldr r1, =_SCS_MPU_CTRL
    3e3c:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    3e40:	20001e10 	.word	0x20001e10
    ldr r0, =z_interrupt_stacks
    3e44:	200010d0 	.word	0x200010d0

00003e48 <sys_arch_reboot>:
  __ASM volatile ("dsb 0xF":::"memory");
    3e48:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    3e4c:	4905      	ldr	r1, [pc, #20]	; (3e64 <sys_arch_reboot+0x1c>)
    3e4e:	4b06      	ldr	r3, [pc, #24]	; (3e68 <sys_arch_reboot+0x20>)
    3e50:	68ca      	ldr	r2, [r1, #12]
    3e52:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    3e56:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    3e58:	60cb      	str	r3, [r1, #12]
    3e5a:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    3e5e:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    3e60:	e7fd      	b.n	3e5e <sys_arch_reboot+0x16>
    3e62:	bf00      	nop
    3e64:	e000ed00 	.word	0xe000ed00
    3e68:	05fa0004 	.word	0x05fa0004

00003e6c <z_arm_clear_arm_mpu_config>:
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);

	for (i = 0; i < num_regions; i++) {
    3e6c:	2300      	movs	r3, #0
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
  mpu->RNR = rnr;
  mpu->RLAR = 0U;
    3e6e:	4618      	mov	r0, r3
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    3e70:	4906      	ldr	r1, [pc, #24]	; (3e8c <z_arm_clear_arm_mpu_config+0x20>)
    3e72:	f8d1 2090 	ldr.w	r2, [r1, #144]	; 0x90
	int num_regions =
    3e76:	f3c2 2207 	ubfx	r2, r2, #8, #8
	for (i = 0; i < num_regions; i++) {
    3e7a:	4293      	cmp	r3, r2
    3e7c:	db00      	blt.n	3e80 <z_arm_clear_arm_mpu_config+0x14>
		ARM_MPU_ClrRegion(i);
	}
}
    3e7e:	4770      	bx	lr
  mpu->RNR = rnr;
    3e80:	f8c1 3098 	str.w	r3, [r1, #152]	; 0x98
  mpu->RLAR = 0U;
    3e84:	f8c1 00a0 	str.w	r0, [r1, #160]	; 0xa0
	for (i = 0; i < num_regions; i++) {
    3e88:	3301      	adds	r3, #1
    3e8a:	e7f6      	b.n	3e7a <z_arm_clear_arm_mpu_config+0xe>
    3e8c:	e000ed00 	.word	0xe000ed00

00003e90 <z_arm_init_arch_hw_at_boot>:
 * This routine resets Cortex-M system control block
 * components and core registers.
 *
 */
void z_arm_init_arch_hw_at_boot(void)
{
    3e90:	b510      	push	{r4, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    3e92:	b672      	cpsid	i
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    3e94:	2400      	movs	r4, #0
    3e96:	f384 8813 	msr	FAULTMASK, r4

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    3e9a:	f7ff ffe7 	bl	3e6c <z_arm_clear_arm_mpu_config>
    3e9e:	4623      	mov	r3, r4
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    3ea0:	f04f 30ff 	mov.w	r0, #4294967295
    3ea4:	4a0c      	ldr	r2, [pc, #48]	; (3ed8 <z_arm_init_arch_hw_at_boot+0x48>)
    3ea6:	f103 0120 	add.w	r1, r3, #32
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    3eaa:	3301      	adds	r3, #1
    3eac:	2b10      	cmp	r3, #16
		NVIC->ICER[i] = 0xFFFFFFFF;
    3eae:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    3eb2:	d1f8      	bne.n	3ea6 <z_arm_init_arch_hw_at_boot+0x16>
    3eb4:	2300      	movs	r3, #0
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    3eb6:	f04f 30ff 	mov.w	r0, #4294967295
    3eba:	4a07      	ldr	r2, [pc, #28]	; (3ed8 <z_arm_init_arch_hw_at_boot+0x48>)
    3ebc:	f103 0160 	add.w	r1, r3, #96	; 0x60
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    3ec0:	3301      	adds	r3, #1
    3ec2:	2b10      	cmp	r3, #16
		NVIC->ICPR[i] = 0xFFFFFFFF;
    3ec4:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    3ec8:	d1f8      	bne.n	3ebc <z_arm_init_arch_hw_at_boot+0x2c>
  __ASM volatile ("cpsie i" : : : "memory");
    3eca:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    3ecc:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    3ed0:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    3ed4:	bd10      	pop	{r4, pc}
    3ed6:	bf00      	nop
    3ed8:	e000e100 	.word	0xe000e100

00003edc <z_impl_k_thread_abort>:
#include <zephyr/wait_q.h>
#include <zephyr/sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
	if (_current == thread) {
    3edc:	4b08      	ldr	r3, [pc, #32]	; (3f00 <z_impl_k_thread_abort+0x24>)
    3ede:	689b      	ldr	r3, [r3, #8]
    3ee0:	4283      	cmp	r3, r0
    3ee2:	d10b      	bne.n	3efc <z_impl_k_thread_abort+0x20>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    3ee4:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    3ee8:	b143      	cbz	r3, 3efc <z_impl_k_thread_abort+0x20>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    3eea:	4b06      	ldr	r3, [pc, #24]	; (3f04 <z_impl_k_thread_abort+0x28>)
    3eec:	685a      	ldr	r2, [r3, #4]
    3eee:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
    3ef2:	605a      	str	r2, [r3, #4]
			/* Clear any system calls that may be pending
			 * as they have a higher priority than the PendSV
			 * handler and will check the stack of the thread
			 * being aborted.
			 */
			SCB->SHCSR &= ~SCB_SHCSR_SVCALLPENDED_Msk;
    3ef4:	6a5a      	ldr	r2, [r3, #36]	; 0x24
    3ef6:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    3efa:	625a      	str	r2, [r3, #36]	; 0x24
		}
	}

	z_thread_abort(thread);
    3efc:	f004 ba26 	b.w	834c <z_thread_abort>
    3f00:	20000ea0 	.word	0x20000ea0
    3f04:	e000ed00 	.word	0xe000ed00

00003f08 <z_arm_configure_static_mpu_regions>:
 *
 * For some MPU architectures, such as the unmodified ARMv8-M MPU,
 * the function must execute with MPU enabled.
 */
void z_arm_configure_static_mpu_regions(void)
{
    3f08:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	 * into account the unused SRAM area, as well.
	 */
#ifdef CONFIG_AARCH32_ARMV8_R
	arm_core_mpu_disable();
#endif
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    3f0a:	4c09      	ldr	r4, [pc, #36]	; (3f30 <z_arm_configure_static_mpu_regions+0x28>)
    3f0c:	4a09      	ldr	r2, [pc, #36]	; (3f34 <z_arm_configure_static_mpu_regions+0x2c>)
    3f0e:	4623      	mov	r3, r4
    3f10:	2101      	movs	r1, #1
    3f12:	4809      	ldr	r0, [pc, #36]	; (3f38 <z_arm_configure_static_mpu_regions+0x30>)
    3f14:	f000 f92a 	bl	416c <arm_core_mpu_configure_static_mpu_regions>
	/* Define a constant array of z_arm_mpu_partition objects that holds the
	 * boundaries of the areas, inside which dynamic region programming
	 * is allowed. The information is passed to the underlying driver at
	 * initialization.
	 */
	const struct z_arm_mpu_partition dyn_region_areas[] = {
    3f18:	2300      	movs	r3, #0
    3f1a:	9303      	str	r3, [sp, #12]
		{
		.start = _MPU_DYNAMIC_REGIONS_AREA_START,
    3f1c:	4b07      	ldr	r3, [pc, #28]	; (3f3c <z_arm_configure_static_mpu_regions+0x34>)
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
		}
	};

	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    3f1e:	2101      	movs	r1, #1
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
    3f20:	1ae4      	subs	r4, r4, r3
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    3f22:	a801      	add	r0, sp, #4
	const struct z_arm_mpu_partition dyn_region_areas[] = {
    3f24:	9301      	str	r3, [sp, #4]
    3f26:	9402      	str	r4, [sp, #8]
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    3f28:	f000 f944 	bl	41b4 <arm_core_mpu_mark_areas_for_dynamic_regions>
		ARRAY_SIZE(dyn_region_areas));
#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */
}
    3f2c:	b004      	add	sp, #16
    3f2e:	bd10      	pop	{r4, pc}
    3f30:	20070000 	.word	0x20070000
    3f34:	20000000 	.word	0x20000000
    3f38:	0000a0cc 	.word	0x0000a0cc
    3f3c:	200001f0 	.word	0x200001f0

00003f40 <region_init>:
 * Note:
 *   The caller must provide a valid region index.
 */
static void region_init(const uint32_t index,
	const struct arm_mpu_region *region_conf)
{
    3f40:	b510      	push	{r4, lr}
	mpu_set_region(
		/* RNR */
		index,
		/* RBAR */
		(region_conf->base & MPU_RBAR_BASE_Msk)
		| (region_conf->attr.rbar &
    3f42:	7a0c      	ldrb	r4, [r1, #8]
		(region_conf->base & MPU_RBAR_BASE_Msk)
    3f44:	680b      	ldr	r3, [r1, #0]
		| (region_conf->attr.rbar &
    3f46:	f004 021f 	and.w	r2, r4, #31
		(region_conf->base & MPU_RBAR_BASE_Msk)
    3f4a:	f023 031f 	bic.w	r3, r3, #31
		| (region_conf->attr.rbar &
    3f4e:	431a      	orrs	r2, r3
			(MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)),
		/* RLAR */
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    3f50:	68cb      	ldr	r3, [r1, #12]
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    3f52:	0964      	lsrs	r4, r4, #5
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    3f54:	f023 031f 	bic.w	r3, r3, #31
	MPU->RNR = rnr;
    3f58:	4905      	ldr	r1, [pc, #20]	; (3f70 <region_init+0x30>)
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    3f5a:	ea43 0344 	orr.w	r3, r3, r4, lsl #1
			& MPU_RLAR_AttrIndx_Msk)
		| MPU_RLAR_EN_Msk
    3f5e:	f043 0301 	orr.w	r3, r3, #1
	MPU->RNR = rnr;
    3f62:	f8c1 0098 	str.w	r0, [r1, #152]	; 0x98
	MPU->RBAR = rbar;
    3f66:	f8c1 209c 	str.w	r2, [r1, #156]	; 0x9c
	MPU->RLAR = rlar;
    3f6a:	f8c1 30a0 	str.w	r3, [r1, #160]	; 0xa0
	);

	LOG_DBG("[%d] 0x%08x 0x%08x 0x%08x 0x%08x",
			index, region_conf->base, region_conf->attr.rbar,
			region_conf->attr.mair_idx, region_conf->attr.r_limit);
}
    3f6e:	bd10      	pop	{r4, pc}
    3f70:	e000ed00 	.word	0xe000ed00

00003f74 <region_allocate_and_init.part.0>:
#include "arm_mpu_v8_internal.h"
#else
#error "Unsupported ARM CPU"
#endif

static int region_allocate_and_init(const uint8_t index,
    3f74:	b580      	push	{r7, lr}
    3f76:	af00      	add	r7, sp, #0
{
	/* Attempt to allocate new region index. */
	if (index > (get_num_regions() - 1U)) {

		/* No available MPU region index. */
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    3f78:	b088      	sub	sp, #32
    3f7a:	466a      	mov	r2, sp
    3f7c:	4b07      	ldr	r3, [pc, #28]	; (3f9c <region_allocate_and_init.part.0+0x28>)
    3f7e:	e9c2 3005 	strd	r3, r0, [r2, #20]
    3f82:	2303      	movs	r3, #3
    3f84:	f842 3f10 	str.w	r3, [r2, #16]!
    3f88:	2300      	movs	r3, #0
    3f8a:	f44f 51c2 	mov.w	r1, #6208	; 0x1840
    3f8e:	4804      	ldr	r0, [pc, #16]	; (3fa0 <region_allocate_and_init.part.0+0x2c>)
    3f90:	f7fe fc4a 	bl	2828 <z_impl_z_log_msg_static_create>

	/* Program region */
	region_init(index, region_conf);

	return index;
}
    3f94:	f06f 0015 	mvn.w	r0, #21
    3f98:	46bd      	mov	sp, r7
    3f9a:	bd80      	pop	{r7, pc}
    3f9c:	0000b0a4 	.word	0x0000b0a4
    3fa0:	00009fdc 	.word	0x00009fdc

00003fa4 <mpu_configure_regions_and_partition.constprop.0>:
 * sanity check of the memory regions to be programmed.
 *
 * The function performs a full partition of the background memory
 * area, effectively, leaving no space in this area uncovered by MPU.
 */
static int mpu_configure_regions_and_partition(const struct z_arm_mpu_partition
    3fa4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3fa8:	4614      	mov	r4, r2
	bool do_sanity_check)
{
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    3faa:	4606      	mov	r6, r0
    3fac:	f04f 0900 	mov.w	r9, #0
static int mpu_configure_regions_and_partition(const struct z_arm_mpu_partition
    3fb0:	b087      	sub	sp, #28
	MPU->RNR = rnr;
    3fb2:	4d5f      	ldr	r5, [pc, #380]	; (4130 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x130>)
static int mpu_configure_regions_and_partition(const struct z_arm_mpu_partition
    3fb4:	af00      	add	r7, sp, #0
    3fb6:	6079      	str	r1, [r7, #4]
	for (i = 0; i < regions_num; i++) {
    3fb8:	687b      	ldr	r3, [r7, #4]
    3fba:	4599      	cmp	r9, r3
    3fbc:	da35      	bge.n	402a <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x2a>
		if (regions[i].size == 0U) {
    3fbe:	f8d6 8004 	ldr.w	r8, [r6, #4]
    3fc2:	f1b8 0f00 	cmp.w	r8, #0
    3fc6:	d054      	beq.n	4072 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x72>
		&&
    3fc8:	f1b8 0f1f 	cmp.w	r8, #31
    3fcc:	d91b      	bls.n	4006 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x6>
		&&
    3fce:	f018 0f1f 	tst.w	r8, #31
    3fd2:	d118      	bne.n	4006 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x6>
		((part->start &
    3fd4:	f8d6 b000 	ldr.w	fp, [r6]
		&&
    3fd8:	f01b 0f1f 	tst.w	fp, #31
    3fdc:	d113      	bne.n	4006 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x6>
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    3fde:	4658      	mov	r0, fp
    3fe0:	f005 fadd 	bl	959e <arm_cmse_mpu_region_get>
    3fe4:	4682      	mov	sl, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    3fe6:	eb08 000b 	add.w	r0, r8, fp
    3fea:	3801      	subs	r0, #1
    3fec:	f005 fad7 	bl	959e <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    3ff0:	4582      	cmp	sl, r0
    3ff2:	d01f      	beq.n	4034 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x34>

		/* Derive the index of the underlying MPU region,
		 * inside which the new region will be configured.
		 */
		int u_reg_index =
			get_region_index(regions[i].start, regions[i].size);
    3ff4:	f06f 0a15 	mvn.w	sl, #21

		if ((u_reg_index == -EINVAL) ||
			(u_reg_index > (reg_index - 1))) {
			LOG_ERR("Invalid underlying region index %u",
    3ff8:	466c      	mov	r4, sp
    3ffa:	b088      	sub	sp, #32
    3ffc:	466a      	mov	r2, sp
    3ffe:	494d      	ldr	r1, [pc, #308]	; (4134 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x134>)
    4000:	e9c2 1a05 	strd	r1, sl, [r2, #20]
    4004:	e005      	b.n	4012 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x12>
			LOG_ERR("Partition %u: sanity check failed.", i);
    4006:	466c      	mov	r4, sp
    4008:	b088      	sub	sp, #32
    400a:	466a      	mov	r2, sp
    400c:	4b4a      	ldr	r3, [pc, #296]	; (4138 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x138>)
    400e:	e9c2 3905 	strd	r3, r9, [r2, #20]
			LOG_ERR("Invalid underlying region index %u",
    4012:	2303      	movs	r3, #3
    4014:	f842 3f10 	str.w	r3, [r2, #16]!
    4018:	2300      	movs	r3, #0
    401a:	f44f 51c2 	mov.w	r1, #6208	; 0x1840
    401e:	4847      	ldr	r0, [pc, #284]	; (413c <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x13c>)
    4020:	f7fe fc02 	bl	2828 <z_impl_z_log_msg_static_create>
    4024:	46a5      	mov	sp, r4
			return -EINVAL;
    4026:	f06f 0415 	mvn.w	r4, #21
			reg_index++;
		}
	}

	return reg_index;
}
    402a:	4620      	mov	r0, r4
    402c:	371c      	adds	r7, #28
    402e:	46bd      	mov	sp, r7
    4030:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		if ((u_reg_index == -EINVAL) ||
    4034:	f11a 0f16 	cmn.w	sl, #22
    4038:	d0de      	beq.n	3ff8 <mpu_configure_regions_and_partition.constprop.0+0x54>
    403a:	4554      	cmp	r4, sl
    403c:	dddc      	ble.n	3ff8 <mpu_configure_regions_and_partition.constprop.0+0x54>
	MPU->RNR = rnr;
    403e:	f8c5 a098 	str.w	sl, [r5, #152]	; 0x98
	return MPU->RBAR;
    4042:	f8d5 009c 	ldr.w	r0, [r5, #156]	; 0x9c
	MPU->RNR = rnr;
    4046:	f8c5 a098 	str.w	sl, [r5, #152]	; 0x98
	return MPU->RLAR;
    404a:	f8d5 20a0 	ldr.w	r2, [r5, #160]	; 0xa0
	return mpu_get_rbar() & MPU_RBAR_BASE_Msk;
    404e:	f020 001f 	bic.w	r0, r0, #31
	return (mpu_get_rlar() & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    4052:	f042 081f 	orr.w	r8, r2, #31
		uint32_t reg_last = regions[i].start + regions[i].size - 1;
    4056:	e9d6 2100 	ldrd	r2, r1, [r6]
    405a:	4411      	add	r1, r2
		if ((regions[i].start == u_reg_base) &&
    405c:	4290      	cmp	r0, r2
		uint32_t reg_last = regions[i].start + regions[i].size - 1;
    405e:	f101 3bff 	add.w	fp, r1, #4294967295
		if ((regions[i].start == u_reg_base) &&
    4062:	d11e      	bne.n	40a2 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0xa2>
    4064:	45d8      	cmp	r8, fp
    4066:	d108      	bne.n	407a <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x7a>
			mpu_configure_region(u_reg_index, &regions[i]);
    4068:	4631      	mov	r1, r6
    406a:	fa5f f08a 	uxtb.w	r0, sl
    406e:	f005 fa9f 	bl	95b0 <mpu_configure_region>
	for (i = 0; i < regions_num; i++) {
    4072:	f109 0901 	add.w	r9, r9, #1
    4076:	360c      	adds	r6, #12
    4078:	e79e      	b.n	3fb8 <mpu_configure_regions_and_partition.constprop.0+0x14>
	MPU->RNR = rnr;
    407a:	f8c5 a098 	str.w	sl, [r5, #152]	; 0x98
	return MPU->RBAR;
    407e:	f8d5 309c 	ldr.w	r3, [r5, #156]	; 0x9c
		     | (base & MPU_RBAR_BASE_Msk));
    4082:	f021 011f 	bic.w	r1, r1, #31
	mpu_set_rbar((mpu_get_rbar() & (~MPU_RBAR_BASE_Msk))
    4086:	f003 031f 	and.w	r3, r3, #31
		     | (base & MPU_RBAR_BASE_Msk));
    408a:	430b      	orrs	r3, r1
				mpu_configure_region(reg_index, &regions[i]);
    408c:	4631      	mov	r1, r6
	MPU->RBAR = rbar;
    408e:	f8c5 309c 	str.w	r3, [r5, #156]	; 0x9c
				mpu_configure_region(reg_index, &regions[i]);
    4092:	b2e0      	uxtb	r0, r4
				mpu_configure_region(reg_index, &regions[i]);
    4094:	f005 fa8c 	bl	95b0 <mpu_configure_region>
			if (reg_index == -EINVAL) {
    4098:	f110 0f16 	cmn.w	r0, #22
    409c:	d0c3      	beq.n	4026 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x26>
			reg_index++;
    409e:	1c44      	adds	r4, r0, #1
    40a0:	e7e7      	b.n	4072 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x72>
				regions[i].start - 1);
    40a2:	3a01      	subs	r2, #1
		} else if (reg_last == u_reg_last) {
    40a4:	45d8      	cmp	r8, fp
				mpu_configure_region(reg_index, &regions[i]);
    40a6:	b2e0      	uxtb	r0, r4
		     | (limit & MPU_RLAR_LIMIT_Msk));
    40a8:	f022 021f 	bic.w	r2, r2, #31
	MPU->RNR = rnr;
    40ac:	f8c5 a098 	str.w	sl, [r5, #152]	; 0x98
		} else if (reg_last == u_reg_last) {
    40b0:	d108      	bne.n	40c4 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0xc4>
	return MPU->RLAR;
    40b2:	f8d5 30a0 	ldr.w	r3, [r5, #160]	; 0xa0
				mpu_configure_region(reg_index, &regions[i]);
    40b6:	4631      	mov	r1, r6
	mpu_set_rlar((mpu_get_rlar() & (~MPU_RLAR_LIMIT_Msk))
    40b8:	f003 031f 	and.w	r3, r3, #31
		     | (limit & MPU_RLAR_LIMIT_Msk));
    40bc:	4313      	orrs	r3, r2
	MPU->RLAR = rlar;
    40be:	f8c5 30a0 	str.w	r3, [r5, #160]	; 0xa0
			reg_index =
    40c2:	e7e7      	b.n	4094 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x94>
	return MPU->RLAR;
    40c4:	f8d5 10a0 	ldr.w	r1, [r5, #160]	; 0xa0
	mpu_set_rlar((mpu_get_rlar() & (~MPU_RLAR_LIMIT_Msk))
    40c8:	f001 011f 	and.w	r1, r1, #31
		     | (limit & MPU_RLAR_LIMIT_Msk));
    40cc:	430a      	orrs	r2, r1
	MPU->RLAR = rlar;
    40ce:	f8c5 20a0 	str.w	r2, [r5, #160]	; 0xa0
				mpu_configure_region(reg_index, &regions[i]);
    40d2:	4631      	mov	r1, r6
    40d4:	f005 fa6c 	bl	95b0 <mpu_configure_region>
			if (reg_index == -EINVAL) {
    40d8:	f110 0f16 	cmn.w	r0, #22
    40dc:	d0a3      	beq.n	4026 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x26>
	MPU->RNR = rnr;
    40de:	f8c5 a098 	str.w	sl, [r5, #152]	; 0x98
	return MPU->RBAR;
    40e2:	f8d5 209c 	ldr.w	r2, [r5, #156]	; 0x9c
	attr->rbar = mpu_get_rbar() &
    40e6:	7c3b      	ldrb	r3, [r7, #16]
			REGION_LIMIT_ADDR((regions[i].start +
    40e8:	f108 38ff 	add.w	r8, r8, #4294967295
	attr->rbar = mpu_get_rbar() &
    40ec:	f362 0304 	bfi	r3, r2, #0, #5
    40f0:	743b      	strb	r3, [r7, #16]
	return MPU->RLAR;
    40f2:	f8d5 30a0 	ldr.w	r3, [r5, #160]	; 0xa0
	attr->mair_idx = (mpu_get_rlar() & MPU_RLAR_AttrIndx_Msk) >>
    40f6:	7c3a      	ldrb	r2, [r7, #16]
    40f8:	085b      	lsrs	r3, r3, #1
    40fa:	f363 1247 	bfi	r2, r3, #5, #3
    40fe:	743a      	strb	r2, [r7, #16]
			fill_region.base = regions[i].start +
    4100:	e9d6 3200 	ldrd	r3, r2, [r6]
    4104:	4413      	add	r3, r2
    4106:	60bb      	str	r3, [r7, #8]
			REGION_LIMIT_ADDR((regions[i].start +
    4108:	f023 031f 	bic.w	r3, r3, #31
			reg_index++;
    410c:	1c44      	adds	r4, r0, #1
			REGION_LIMIT_ADDR((regions[i].start +
    410e:	4443      	add	r3, r8
    4110:	eba3 030b 	sub.w	r3, r3, fp
				region_allocate_and_init(reg_index,
    4114:	b2e0      	uxtb	r0, r4
			REGION_LIMIT_ADDR((regions[i].start +
    4116:	f023 031f 	bic.w	r3, r3, #31
	if (index > (get_num_regions() - 1U)) {
    411a:	2807      	cmp	r0, #7
			fill_region.attr.r_limit =
    411c:	617b      	str	r3, [r7, #20]
    411e:	d902      	bls.n	4126 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x126>
    4120:	f7ff ff28 	bl	3f74 <region_allocate_and_init.part.0>
			if (reg_index == -EINVAL) {
    4124:	e7b8      	b.n	4098 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x98>
	region_init(index, region_conf);
    4126:	f107 0108 	add.w	r1, r7, #8
    412a:	f7ff ff09 	bl	3f40 <region_init>
    412e:	e7b6      	b.n	409e <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x9e>
    4130:	e000ed00 	.word	0xe000ed00
    4134:	0000b0ed 	.word	0x0000b0ed
    4138:	0000b0ca 	.word	0x0000b0ca
    413c:	00009fdc 	.word	0x00009fdc

00004140 <arm_core_mpu_enable>:
	 * background region for privileged software access if desired.
	 */
#if defined(CONFIG_MPU_DISABLE_BACKGROUND_MAP)
	MPU->CTRL = MPU_CTRL_ENABLE_Msk;
#else
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    4140:	2205      	movs	r2, #5
    4142:	4b04      	ldr	r3, [pc, #16]	; (4154 <arm_core_mpu_enable+0x14>)
    4144:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
  __ASM volatile ("dsb 0xF":::"memory");
    4148:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    414c:	f3bf 8f6f 	isb	sy
#endif

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    4150:	4770      	bx	lr
    4152:	bf00      	nop
    4154:	e000ed00 	.word	0xe000ed00

00004158 <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    4158:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    415c:	2200      	movs	r2, #0
    415e:	4b02      	ldr	r3, [pc, #8]	; (4168 <arm_core_mpu_disable+0x10>)
    4160:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
}
    4164:	4770      	bx	lr
    4166:	bf00      	nop
    4168:	e000ed00 	.word	0xe000ed00

0000416c <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	*static_regions, const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    416c:	b538      	push	{r3, r4, r5, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    416e:	4d0c      	ldr	r5, [pc, #48]	; (41a0 <arm_core_mpu_configure_static_mpu_regions+0x34>)
    4170:	460c      	mov	r4, r1
	 * given boundaries.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions_and_partition(static_regions,
    4172:	782a      	ldrb	r2, [r5, #0]
    4174:	f7ff ff16 	bl	3fa4 <mpu_configure_regions_and_partition.constprop.0>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    4178:	7028      	strb	r0, [r5, #0]
	if (mpu_configure_static_mpu_regions(static_regions, regions_num,
    417a:	3016      	adds	r0, #22
    417c:	d10f      	bne.n	419e <arm_core_mpu_configure_static_mpu_regions+0x32>
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
    417e:	f44f 738d 	mov.w	r3, #282	; 0x11a
    4182:	4a08      	ldr	r2, [pc, #32]	; (41a4 <arm_core_mpu_configure_static_mpu_regions+0x38>)
    4184:	4908      	ldr	r1, [pc, #32]	; (41a8 <arm_core_mpu_configure_static_mpu_regions+0x3c>)
    4186:	4809      	ldr	r0, [pc, #36]	; (41ac <arm_core_mpu_configure_static_mpu_regions+0x40>)
    4188:	f005 f88d 	bl	92a6 <assert_print>
    418c:	4621      	mov	r1, r4
    418e:	4808      	ldr	r0, [pc, #32]	; (41b0 <arm_core_mpu_configure_static_mpu_regions+0x44>)
    4190:	f005 f889 	bl	92a6 <assert_print>
    4194:	f44f 718d 	mov.w	r1, #282	; 0x11a
    4198:	4802      	ldr	r0, [pc, #8]	; (41a4 <arm_core_mpu_configure_static_mpu_regions+0x38>)
    419a:	f005 f87d 	bl	9298 <assert_post_action>
			regions_num);
	}
}
    419e:	bd38      	pop	{r3, r4, r5, pc}
    41a0:	200010cb 	.word	0x200010cb
    41a4:	0000b110 	.word	0x0000b110
    41a8:	0000a5f9 	.word	0x0000a5f9
    41ac:	0000a2e8 	.word	0x0000a2e8
    41b0:	0000b147 	.word	0x0000b147

000041b4 <arm_core_mpu_mark_areas_for_dynamic_regions>:
 * @brief mark memory areas for dynamic region configuration
 */
void arm_core_mpu_mark_areas_for_dynamic_regions(
	const struct z_arm_mpu_partition dyn_region_areas[],
	const uint8_t dyn_region_areas_num)
{
    41b4:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    41b8:	4e31      	ldr	r6, [pc, #196]	; (4280 <arm_core_mpu_mark_areas_for_dynamic_regions+0xcc>)
    41ba:	4689      	mov	r9, r1
{
	/* In ARMv8-M architecture we need to store the index values
	 * and the default configuration of the MPU regions, inside
	 * which dynamic memory regions may be programmed at run-time.
	 */
	for (int i = 0; i < dyn_region_areas_num; i++) {
    41bc:	4605      	mov	r5, r0
    41be:	f04f 0800 	mov.w	r8, #0
    41c2:	46b3      	mov	fp, r6
	MPU->RNR = rnr;
    41c4:	4f2f      	ldr	r7, [pc, #188]	; (4284 <arm_core_mpu_mark_areas_for_dynamic_regions+0xd0>)
	for (int i = 0; i < dyn_region_areas_num; i++) {
    41c6:	45c8      	cmp	r8, r9
    41c8:	db02      	blt.n	41d0 <arm_core_mpu_mark_areas_for_dynamic_regions+0x1c>
						 dyn_region_areas_num) == -EINVAL) {

		__ASSERT(0, "Marking %u areas for dynamic regions failed\n",
			dyn_region_areas_num);
	}
}
    41ca:	b003      	add	sp, #12
    41cc:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		if (dyn_region_areas[i].size == 0U) {
    41d0:	f8d5 a004 	ldr.w	sl, [r5, #4]
    41d4:	f1ba 0f00 	cmp.w	sl, #0
    41d8:	d04c      	beq.n	4274 <arm_core_mpu_mark_areas_for_dynamic_regions+0xc0>
		}
		/* Non-empty area */

		/* Retrieve HW MPU region index */
		dyn_reg_info[i].index =
			get_region_index(dyn_region_areas[i].start,
    41da:	6829      	ldr	r1, [r5, #0]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    41dc:	4608      	mov	r0, r1
    41de:	9101      	str	r1, [sp, #4]
    41e0:	f005 f9dd 	bl	959e <arm_cmse_mpu_region_get>
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    41e4:	9901      	ldr	r1, [sp, #4]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    41e6:	4604      	mov	r4, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    41e8:	eb0a 0001 	add.w	r0, sl, r1
    41ec:	3801      	subs	r0, #1
    41ee:	f005 f9d6 	bl	959e <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    41f2:	4284      	cmp	r4, r0
    41f4:	f04f 0214 	mov.w	r2, #20
    41f8:	4b23      	ldr	r3, [pc, #140]	; (4288 <arm_core_mpu_mark_areas_for_dynamic_regions+0xd4>)
    41fa:	d015      	beq.n	4228 <arm_core_mpu_mark_areas_for_dynamic_regions+0x74>
		dyn_reg_info[i].index =
    41fc:	fb02 f308 	mul.w	r3, r2, r8
    4200:	f06f 0215 	mvn.w	r2, #21
    4204:	f84b 2003 	str.w	r2, [fp, r3]
		__ASSERT(0, "Marking %u areas for dynamic regions failed\n",
    4208:	f44f 7395 	mov.w	r3, #298	; 0x12a
    420c:	4a1f      	ldr	r2, [pc, #124]	; (428c <arm_core_mpu_mark_areas_for_dynamic_regions+0xd8>)
    420e:	4920      	ldr	r1, [pc, #128]	; (4290 <arm_core_mpu_mark_areas_for_dynamic_regions+0xdc>)
    4210:	4820      	ldr	r0, [pc, #128]	; (4294 <arm_core_mpu_mark_areas_for_dynamic_regions+0xe0>)
    4212:	f005 f848 	bl	92a6 <assert_print>
    4216:	4649      	mov	r1, r9
    4218:	481f      	ldr	r0, [pc, #124]	; (4298 <arm_core_mpu_mark_areas_for_dynamic_regions+0xe4>)
    421a:	f005 f844 	bl	92a6 <assert_print>
    421e:	f44f 7195 	mov.w	r1, #298	; 0x12a
    4222:	481a      	ldr	r0, [pc, #104]	; (428c <arm_core_mpu_mark_areas_for_dynamic_regions+0xd8>)
    4224:	f005 f838 	bl	9298 <assert_post_action>
					dyn_region_areas[i].size);

		if (dyn_reg_info[i].index == -EINVAL) {
    4228:	f114 0f16 	cmn.w	r4, #22
		dyn_reg_info[i].index =
    422c:	6034      	str	r4, [r6, #0]
		if (dyn_reg_info[i].index == -EINVAL) {
    422e:	d0eb      	beq.n	4208 <arm_core_mpu_mark_areas_for_dynamic_regions+0x54>

			return -EINVAL;
		}

		if (dyn_reg_info[i].index >= static_regions_num) {
    4230:	7819      	ldrb	r1, [r3, #0]
    4232:	42a1      	cmp	r1, r4
    4234:	dde8      	ble.n	4208 <arm_core_mpu_mark_areas_for_dynamic_regions+0x54>
	attr->rbar = mpu_get_rbar() &
    4236:	fb02 b008 	mla	r0, r2, r8, fp
	MPU->RNR = rnr;
    423a:	f8c7 4098 	str.w	r4, [r7, #152]	; 0x98
    423e:	f8c7 4098 	str.w	r4, [r7, #152]	; 0x98
	return MPU->RBAR;
    4242:	f8d7 409c 	ldr.w	r4, [r7, #156]	; 0x9c
	attr->rbar = mpu_get_rbar() &
    4246:	f100 0108 	add.w	r1, r0, #8
    424a:	7b00      	ldrb	r0, [r0, #12]
    424c:	f364 0004 	bfi	r0, r4, #0, #5
    4250:	7108      	strb	r0, [r1, #4]
	return MPU->RLAR;
    4252:	f8d7 00a0 	ldr.w	r0, [r7, #160]	; 0xa0
	attr->mair_idx = (mpu_get_rlar() & MPU_RLAR_AttrIndx_Msk) >>
    4256:	790c      	ldrb	r4, [r1, #4]
    4258:	0840      	lsrs	r0, r0, #1
    425a:	f360 1447 	bfi	r4, r0, #5, #3
    425e:	710c      	strb	r4, [r1, #4]
	return MPU->RBAR;
    4260:	f8d7 109c 	ldr.w	r1, [r7, #156]	; 0x9c
	region_conf->base = mpu_get_rbar() & MPU_RBAR_BASE_Msk;
    4264:	f021 011f 	bic.w	r1, r1, #31
    4268:	6071      	str	r1, [r6, #4]
	return MPU->RLAR;
    426a:	f8d7 10a0 	ldr.w	r1, [r7, #160]	; 0xa0
	region_conf->attr.r_limit = mpu_get_rlar() & MPU_RLAR_LIMIT_Msk;
    426e:	f021 011f 	bic.w	r1, r1, #31
    4272:	6131      	str	r1, [r6, #16]
	for (int i = 0; i < dyn_region_areas_num; i++) {
    4274:	f108 0801 	add.w	r8, r8, #1
    4278:	3614      	adds	r6, #20
    427a:	350c      	adds	r5, #12
    427c:	e7a3      	b.n	41c6 <arm_core_mpu_mark_areas_for_dynamic_regions+0x12>
    427e:	bf00      	nop
    4280:	20000d00 	.word	0x20000d00
    4284:	e000ed00 	.word	0xe000ed00
    4288:	200010cb 	.word	0x200010cb
    428c:	0000b110 	.word	0x0000b110
    4290:	0000a5f9 	.word	0x0000a5f9
    4294:	0000a2e8 	.word	0x0000a2e8
    4298:	0000b173 	.word	0x0000b173

0000429c <z_arm_mpu_init>:
 *
 * This function provides the default configuration mechanism for the Memory
 * Protection Unit (MPU).
 */
int z_arm_mpu_init(void)
{
    429c:	b538      	push	{r3, r4, r5, lr}
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    429e:	4d1f      	ldr	r5, [pc, #124]	; (431c <z_arm_mpu_init+0x80>)
    42a0:	682c      	ldr	r4, [r5, #0]
    42a2:	2c08      	cmp	r4, #8
    42a4:	d910      	bls.n	42c8 <z_arm_mpu_init+0x2c>
		 * what is supported by hardware. As this operation
		 * is executed during system (pre-kernel) initialization,
		 * we want to ensure we can detect an attempt to
		 * perform invalid configuration.
		 */
		__ASSERT(0,
    42a6:	f240 1351 	movw	r3, #337	; 0x151
    42aa:	4a1d      	ldr	r2, [pc, #116]	; (4320 <z_arm_mpu_init+0x84>)
    42ac:	491d      	ldr	r1, [pc, #116]	; (4324 <z_arm_mpu_init+0x88>)
    42ae:	481e      	ldr	r0, [pc, #120]	; (4328 <z_arm_mpu_init+0x8c>)
    42b0:	f004 fff9 	bl	92a6 <assert_print>
    42b4:	4621      	mov	r1, r4
    42b6:	2208      	movs	r2, #8
    42b8:	481c      	ldr	r0, [pc, #112]	; (432c <z_arm_mpu_init+0x90>)
    42ba:	f004 fff4 	bl	92a6 <assert_print>
    42be:	f240 1151 	movw	r1, #337	; 0x151
	defined(CONFIG_CPU_CORTEX_M4)
	__ASSERT(
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos == 8,
		"Invalid number of MPU regions\n");
#elif defined(NUM_MPU_REGIONS)
	__ASSERT(
    42c2:	4817      	ldr	r0, [pc, #92]	; (4320 <z_arm_mpu_init+0x84>)
    42c4:	f004 ffe8 	bl	9298 <assert_post_action>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    42c8:	2000      	movs	r0, #0
	arm_core_mpu_disable();
    42ca:	f7ff ff45 	bl	4158 <arm_core_mpu_disable>
	MPU->MAIR0 = mair0;
    42ce:	4b18      	ldr	r3, [pc, #96]	; (4330 <z_arm_mpu_init+0x94>)
    42d0:	4a18      	ldr	r2, [pc, #96]	; (4334 <z_arm_mpu_init+0x98>)
    42d2:	f8c3 20c0 	str.w	r2, [r3, #192]	; 0xc0
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    42d6:	4284      	cmp	r4, r0
    42d8:	d117      	bne.n	430a <z_arm_mpu_init+0x6e>
	static_regions_num = mpu_config.num_regions;
    42da:	4b17      	ldr	r3, [pc, #92]	; (4338 <z_arm_mpu_init+0x9c>)
    42dc:	701c      	strb	r4, [r3, #0]
	arm_core_mpu_enable();
    42de:	f7ff ff2f 	bl	4140 <arm_core_mpu_enable>
	__ASSERT(
    42e2:	4b13      	ldr	r3, [pc, #76]	; (4330 <z_arm_mpu_init+0x94>)
    42e4:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
    42e8:	f3c3 2307 	ubfx	r3, r3, #8, #8
    42ec:	2b08      	cmp	r3, #8
    42ee:	d013      	beq.n	4318 <z_arm_mpu_init+0x7c>
    42f0:	4912      	ldr	r1, [pc, #72]	; (433c <z_arm_mpu_init+0xa0>)
    42f2:	f240 13bb 	movw	r3, #443	; 0x1bb
    42f6:	4a0a      	ldr	r2, [pc, #40]	; (4320 <z_arm_mpu_init+0x84>)
    42f8:	480b      	ldr	r0, [pc, #44]	; (4328 <z_arm_mpu_init+0x8c>)
    42fa:	f004 ffd4 	bl	92a6 <assert_print>
    42fe:	4810      	ldr	r0, [pc, #64]	; (4340 <z_arm_mpu_init+0xa4>)
    4300:	f004 ffd1 	bl	92a6 <assert_print>
    4304:	f240 11bb 	movw	r1, #443	; 0x1bb
    4308:	e7db      	b.n	42c2 <z_arm_mpu_init+0x26>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
    430a:	6869      	ldr	r1, [r5, #4]
    430c:	eb01 1100 	add.w	r1, r1, r0, lsl #4
    4310:	f7ff fe16 	bl	3f40 <region_init>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    4314:	3001      	adds	r0, #1
    4316:	e7de      	b.n	42d6 <z_arm_mpu_init+0x3a>
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
}
    4318:	2000      	movs	r0, #0
    431a:	bd38      	pop	{r3, r4, r5, pc}
    431c:	0000a0d8 	.word	0x0000a0d8
    4320:	0000b110 	.word	0x0000b110
    4324:	0000a5f9 	.word	0x0000a5f9
    4328:	0000a2e8 	.word	0x0000a2e8
    432c:	0000b1a2 	.word	0x0000b1a2
    4330:	e000ed00 	.word	0xe000ed00
    4334:	0044ffaa 	.word	0x0044ffaa
    4338:	200010cb 	.word	0x200010cb
    433c:	0000b1d6 	.word	0x0000b1d6
    4340:	0000b226 	.word	0x0000b226

00004344 <__stdout_hook_install>:

static int (*_stdout_hook)(int c) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int c))
{
	_stdout_hook = hook;
    4344:	4b01      	ldr	r3, [pc, #4]	; (434c <__stdout_hook_install+0x8>)
    4346:	6018      	str	r0, [r3, #0]
}
    4348:	4770      	bx	lr
    434a:	bf00      	nop
    434c:	2000002c 	.word	0x2000002c

00004350 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    4350:	b537      	push	{r0, r1, r2, r4, r5, lr}
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    4352:	2340      	movs	r3, #64	; 0x40
{
    4354:	460c      	mov	r4, r1
	size_t offset = (size_t)(mgr - data->mgr);
    4356:	490a      	ldr	r1, [pc, #40]	; (4380 <onoff_start+0x30>)
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    4358:	9300      	str	r3, [sp, #0]
	size_t offset = (size_t)(mgr - data->mgr);
    435a:	1a41      	subs	r1, r0, r1
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    435c:	1149      	asrs	r1, r1, #5
{
    435e:	4605      	mov	r5, r0
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    4360:	4623      	mov	r3, r4
    4362:	4a08      	ldr	r2, [pc, #32]	; (4384 <onoff_start+0x34>)
    4364:	4808      	ldr	r0, [pc, #32]	; (4388 <onoff_start+0x38>)
    4366:	f005 f97d 	bl	9664 <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    436a:	1e01      	subs	r1, r0, #0
    436c:	da05      	bge.n	437a <onoff_start+0x2a>
		notify(mgr, err);
    436e:	4628      	mov	r0, r5
    4370:	4623      	mov	r3, r4
	}
}
    4372:	b003      	add	sp, #12
    4374:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
		notify(mgr, err);
    4378:	4718      	bx	r3
}
    437a:	b003      	add	sp, #12
    437c:	bd30      	pop	{r4, r5, pc}
    437e:	bf00      	nop
    4380:	20000d28 	.word	0x20000d28
    4384:	000096d3 	.word	0x000096d3
    4388:	00009cc4 	.word	0x00009cc4

0000438c <get_status>:
	__ASSERT_NO_MSG(type < CLOCK_CONTROL_NRF_TYPE_COUNT);
    438c:	b2c9      	uxtb	r1, r1
    438e:	2903      	cmp	r1, #3
{
    4390:	b508      	push	{r3, lr}
	__ASSERT_NO_MSG(type < CLOCK_CONTROL_NRF_TYPE_COUNT);
    4392:	d909      	bls.n	43a8 <get_status+0x1c>
    4394:	4909      	ldr	r1, [pc, #36]	; (43bc <get_status+0x30>)
    4396:	480a      	ldr	r0, [pc, #40]	; (43c0 <get_status+0x34>)
    4398:	237a      	movs	r3, #122	; 0x7a
    439a:	4a0a      	ldr	r2, [pc, #40]	; (43c4 <get_status+0x38>)
    439c:	f004 ff83 	bl	92a6 <assert_print>
    43a0:	217a      	movs	r1, #122	; 0x7a
    43a2:	4808      	ldr	r0, [pc, #32]	; (43c4 <get_status+0x38>)
    43a4:	f004 ff78 	bl	9298 <assert_post_action>
	return GET_STATUS(get_sub_data(dev, type)->flags);
    43a8:	220c      	movs	r2, #12
    43aa:	6903      	ldr	r3, [r0, #16]
    43ac:	fb01 3302 	mla	r3, r1, r2, r3
    43b0:	f8d3 0088 	ldr.w	r0, [r3, #136]	; 0x88
}
    43b4:	f000 0007 	and.w	r0, r0, #7
    43b8:	bd08      	pop	{r3, pc}
    43ba:	bf00      	nop
    43bc:	0000b293 	.word	0x0000b293
    43c0:	0000a2e8 	.word	0x0000a2e8
    43c4:	0000b256 	.word	0x0000b256

000043c8 <stop>:
{
    43c8:	b570      	push	{r4, r5, r6, lr}
    43ca:	b2c9      	uxtb	r1, r1
	__ASSERT_NO_MSG(type < CLOCK_CONTROL_NRF_TYPE_COUNT);
    43cc:	2903      	cmp	r1, #3
	struct nrf_clock_control_data *data = dev->data;
    43ce:	6903      	ldr	r3, [r0, #16]
	__ASSERT_NO_MSG(type < CLOCK_CONTROL_NRF_TYPE_COUNT);
    43d0:	d90b      	bls.n	43ea <stop+0x22>
    43d2:	491a      	ldr	r1, [pc, #104]	; (443c <stop+0x74>)
    43d4:	481a      	ldr	r0, [pc, #104]	; (4440 <stop+0x78>)
    43d6:	f240 135d 	movw	r3, #349	; 0x15d
    43da:	4a1a      	ldr	r2, [pc, #104]	; (4444 <stop+0x7c>)
    43dc:	f004 ff63 	bl	92a6 <assert_print>
    43e0:	f240 115d 	movw	r1, #349	; 0x15d
    43e4:	4817      	ldr	r0, [pc, #92]	; (4444 <stop+0x7c>)
    43e6:	f004 ff57 	bl	9298 <assert_post_action>
	__asm__ volatile(
    43ea:	f04f 0420 	mov.w	r4, #32
    43ee:	f3ef 8511 	mrs	r5, BASEPRI
    43f2:	f384 8812 	msr	BASEPRI_MAX, r4
    43f6:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    43fa:	260c      	movs	r6, #12
    43fc:	fb06 3401 	mla	r4, r6, r1, r3
    4400:	f8d4 4088 	ldr.w	r4, [r4, #136]	; 0x88
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    4404:	f014 04c0 	ands.w	r4, r4, #192	; 0xc0
    4408:	d008      	beq.n	441c <stop+0x54>
    440a:	42a2      	cmp	r2, r4
    440c:	d006      	beq.n	441c <stop+0x54>
	__asm__ volatile(
    440e:	f385 8811 	msr	BASEPRI, r5
    4412:	f3bf 8f6f 	isb	sy
		err = -EPERM;
    4416:	f04f 30ff 	mov.w	r0, #4294967295
}
    441a:	bd70      	pop	{r4, r5, r6, pc}
		*flags = CLOCK_CONTROL_STATUS_OFF;
    441c:	2201      	movs	r2, #1
    441e:	4371      	muls	r1, r6
    4420:	440b      	add	r3, r1
    4422:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    4426:	f385 8811 	msr	BASEPRI, r5
    442a:	f3bf 8f6f 	isb	sy
	get_sub_config(dev, type)->stop();
    442e:	6843      	ldr	r3, [r0, #4]
    4430:	440b      	add	r3, r1
    4432:	685b      	ldr	r3, [r3, #4]
    4434:	4798      	blx	r3
	return 0;
    4436:	2000      	movs	r0, #0
    4438:	e7ef      	b.n	441a <stop+0x52>
    443a:	bf00      	nop
    443c:	0000b293 	.word	0x0000b293
    4440:	0000a2e8 	.word	0x0000a2e8
    4444:	0000b256 	.word	0x0000b256

00004448 <onoff_stop>:
{
    4448:	b570      	push	{r4, r5, r6, lr}
    444a:	460d      	mov	r5, r1
	size_t offset = (size_t)(mgr - data->mgr);
    444c:	4906      	ldr	r1, [pc, #24]	; (4468 <onoff_stop+0x20>)
{
    444e:	4604      	mov	r4, r0
	size_t offset = (size_t)(mgr - data->mgr);
    4450:	1a41      	subs	r1, r0, r1
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    4452:	1149      	asrs	r1, r1, #5
    4454:	2240      	movs	r2, #64	; 0x40
    4456:	4805      	ldr	r0, [pc, #20]	; (446c <onoff_stop+0x24>)
    4458:	f7ff ffb6 	bl	43c8 <stop>
	notify(mgr, res);
    445c:	462b      	mov	r3, r5
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    445e:	4601      	mov	r1, r0
	notify(mgr, res);
    4460:	4620      	mov	r0, r4
}
    4462:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    4466:	4718      	bx	r3
    4468:	20000d28 	.word	0x20000d28
    446c:	00009cc4 	.word	0x00009cc4

00004470 <clk_init>:
#endif /* NRF_CLOCK_HAS_HFCLKAUDIO */
#endif
}

static int clk_init(const struct device *dev)
{
    4470:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    4474:	2200      	movs	r2, #0
    4476:	2101      	movs	r1, #1
{
    4478:	4606      	mov	r6, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    447a:	2005      	movs	r0, #5
    447c:	f7ff f870 	bl	3560 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);

	nrfx_err = nrfx_clock_init(clock_event_handler);
    4480:	4811      	ldr	r0, [pc, #68]	; (44c8 <clk_init+0x58>)
    4482:	f001 fb45 	bl	5b10 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    4486:	4b11      	ldr	r3, [pc, #68]	; (44cc <clk_init+0x5c>)
    4488:	4298      	cmp	r0, r3
    448a:	d119      	bne.n	44c0 <clk_init+0x50>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    448c:	f001 fb64 	bl	5b58 <nrfx_clock_enable>
    4490:	2400      	movs	r4, #0
					 &transitions);
		if (err < 0) {
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    4492:	f04f 080c 	mov.w	r8, #12
    4496:	2701      	movs	r7, #1
		err = onoff_manager_init(get_onoff_manager(dev, i),
    4498:	f8df 9034 	ldr.w	r9, [pc, #52]	; 44d0 <clk_init+0x60>
	struct nrf_clock_control_data *data = dev->data;
    449c:	6935      	ldr	r5, [r6, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    449e:	4649      	mov	r1, r9
    44a0:	eb05 1044 	add.w	r0, r5, r4, lsl #5
    44a4:	f004 fe77 	bl	9196 <onoff_manager_init>
		if (err < 0) {
    44a8:	2800      	cmp	r0, #0
    44aa:	db07      	blt.n	44bc <clk_init+0x4c>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    44ac:	fb08 5504 	mla	r5, r8, r4, r5
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
    44b0:	3401      	adds	r4, #1
    44b2:	2c04      	cmp	r4, #4
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    44b4:	f8c5 7088 	str.w	r7, [r5, #136]	; 0x88
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
    44b8:	d1f0      	bne.n	449c <clk_init+0x2c>
	}

	return 0;
    44ba:	2000      	movs	r0, #0
}
    44bc:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		return -EIO;
    44c0:	f06f 0004 	mvn.w	r0, #4
    44c4:	e7fa      	b.n	44bc <clk_init+0x4c>
    44c6:	bf00      	nop
    44c8:	0000450d 	.word	0x0000450d
    44cc:	0bad0000 	.word	0x0bad0000
    44d0:	0000a100 	.word	0x0000a100

000044d4 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    44d4:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    44d6:	230c      	movs	r3, #12
	sub_data->cb = NULL;
    44d8:	2200      	movs	r2, #0
static void clkstarted_handle(const struct device *dev,
    44da:	b570      	push	{r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    44dc:	434b      	muls	r3, r1
    44de:	4809      	ldr	r0, [pc, #36]	; (4504 <clkstarted_handle.constprop.0+0x30>)
    44e0:	18c4      	adds	r4, r0, r3
	set_on_state(&sub_data->flags);
    44e2:	3388      	adds	r3, #136	; 0x88
	void *user_data = sub_data->user_data;
    44e4:	e9d4 5620 	ldrd	r5, r6, [r4, #128]	; 0x80
	set_on_state(&sub_data->flags);
    44e8:	4418      	add	r0, r3
	sub_data->cb = NULL;
    44ea:	f8c4 2080 	str.w	r2, [r4, #128]	; 0x80
	set_on_state(&sub_data->flags);
    44ee:	f005 f8a6 	bl	963e <set_on_state>
	if (callback) {
    44f2:	b12d      	cbz	r5, 4500 <clkstarted_handle.constprop.0+0x2c>
		callback(dev, (clock_control_subsys_t)type, user_data);
    44f4:	4632      	mov	r2, r6
    44f6:	462b      	mov	r3, r5
}
    44f8:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    44fc:	4802      	ldr	r0, [pc, #8]	; (4508 <clkstarted_handle.constprop.0+0x34>)
    44fe:	4718      	bx	r3
}
    4500:	bd70      	pop	{r4, r5, r6, pc}
    4502:	bf00      	nop
    4504:	20000d28 	.word	0x20000d28
    4508:	00009cc4 	.word	0x00009cc4

0000450c <clock_event_handler>:
{
    450c:	b508      	push	{r3, lr}
	switch (event) {
    450e:	2805      	cmp	r0, #5
    4510:	d820      	bhi.n	4554 <clock_event_handler+0x48>
    4512:	e8df f000 	tbb	[pc, r0]
    4516:	1103      	.short	0x1103
    4518:	0d0f131f 	.word	0x0d0f131f
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    451c:	4b13      	ldr	r3, [pc, #76]	; (456c <clock_event_handler+0x60>)
    451e:	f8d3 0088 	ldr.w	r0, [r3, #136]	; 0x88
    4522:	f010 0007 	ands.w	r0, r0, #7
    4526:	d11f      	bne.n	4568 <clock_event_handler+0x5c>
}
    4528:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    452c:	f7ff bfd2 	b.w	44d4 <clkstarted_handle.constprop.0>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK192M);
    4530:	2002      	movs	r0, #2
    4532:	e7f9      	b.n	4528 <clock_event_handler+0x1c>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_HFCLKAUDIO);
    4534:	2003      	movs	r0, #3
    4536:	e7f7      	b.n	4528 <clock_event_handler+0x1c>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    4538:	2001      	movs	r0, #1
    453a:	e7f5      	b.n	4528 <clock_event_handler+0x1c>
			__ASSERT_NO_MSG(false);
    453c:	490c      	ldr	r1, [pc, #48]	; (4570 <clock_event_handler+0x64>)
    453e:	f240 236e 	movw	r3, #622	; 0x26e
    4542:	4a0c      	ldr	r2, [pc, #48]	; (4574 <clock_event_handler+0x68>)
    4544:	480c      	ldr	r0, [pc, #48]	; (4578 <clock_event_handler+0x6c>)
    4546:	f004 feae 	bl	92a6 <assert_print>
    454a:	f240 216e 	movw	r1, #622	; 0x26e
		__ASSERT_NO_MSG(0);
    454e:	4809      	ldr	r0, [pc, #36]	; (4574 <clock_event_handler+0x68>)
    4550:	f004 fea2 	bl	9298 <assert_post_action>
    4554:	4906      	ldr	r1, [pc, #24]	; (4570 <clock_event_handler+0x64>)
    4556:	f240 2372 	movw	r3, #626	; 0x272
    455a:	4a06      	ldr	r2, [pc, #24]	; (4574 <clock_event_handler+0x68>)
    455c:	4806      	ldr	r0, [pc, #24]	; (4578 <clock_event_handler+0x6c>)
    455e:	f004 fea2 	bl	92a6 <assert_print>
    4562:	f240 2172 	movw	r1, #626	; 0x272
    4566:	e7f2      	b.n	454e <clock_event_handler+0x42>
}
    4568:	bd08      	pop	{r3, pc}
    456a:	bf00      	nop
    456c:	20000d28 	.word	0x20000d28
    4570:	0000a5f9 	.word	0x0000a5f9
    4574:	0000b256 	.word	0x0000b256
    4578:	0000a2e8 	.word	0x0000a2e8

0000457c <generic_hfclk_start>:
{
    457c:	b508      	push	{r3, lr}
	__asm__ volatile(
    457e:	f04f 0320 	mov.w	r3, #32
    4582:	f3ef 8111 	mrs	r1, BASEPRI
    4586:	f383 8812 	msr	BASEPRI_MAX, r3
    458a:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    458e:	4a12      	ldr	r2, [pc, #72]	; (45d8 <generic_hfclk_start+0x5c>)
    4590:	6813      	ldr	r3, [r2, #0]
    4592:	f043 0002 	orr.w	r0, r3, #2
    4596:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    4598:	07da      	lsls	r2, r3, #31
    459a:	d408      	bmi.n	45ae <generic_hfclk_start+0x32>
	__asm__ volatile(
    459c:	f381 8811 	msr	BASEPRI, r1
    45a0:	f3bf 8f6f 	isb	sy
}
    45a4:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    45a8:	2001      	movs	r0, #1
    45aa:	f001 baff 	b.w	5bac <nrfx_clock_start>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    45ae:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    45b2:	f8d3 240c 	ldr.w	r2, [r3, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    45b6:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    45ba:	07d3      	lsls	r3, r2, #31
    45bc:	d5ee      	bpl.n	459c <generic_hfclk_start+0x20>
			set_on_state(get_hf_flags());
    45be:	4807      	ldr	r0, [pc, #28]	; (45dc <generic_hfclk_start+0x60>)
    45c0:	f005 f83d 	bl	963e <set_on_state>
    45c4:	f381 8811 	msr	BASEPRI, r1
    45c8:	f3bf 8f6f 	isb	sy
}
    45cc:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    45d0:	2000      	movs	r0, #0
    45d2:	f7ff bf7f 	b.w	44d4 <clkstarted_handle.constprop.0>
    45d6:	bf00      	nop
    45d8:	20000dd8 	.word	0x20000dd8
    45dc:	20000db0 	.word	0x20000db0

000045e0 <api_blocking_start>:
{
    45e0:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    45e2:	2200      	movs	r2, #0
    45e4:	2301      	movs	r3, #1
    45e6:	e9cd 2302 	strd	r2, r3, [sp, #8]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    45ea:	466b      	mov	r3, sp
    45ec:	4a08      	ldr	r2, [pc, #32]	; (4610 <api_blocking_start+0x30>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    45ee:	f8cd d000 	str.w	sp, [sp]
    45f2:	f8cd d004 	str.w	sp, [sp, #4]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    45f6:	f005 f865 	bl	96c4 <api_start>
	if (err < 0) {
    45fa:	2800      	cmp	r0, #0
    45fc:	db05      	blt.n	460a <api_blocking_start+0x2a>
	return z_impl_k_sem_take(sem, timeout);
    45fe:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    4602:	2300      	movs	r3, #0
    4604:	4668      	mov	r0, sp
    4606:	f002 fdd3 	bl	71b0 <z_impl_k_sem_take>
}
    460a:	b005      	add	sp, #20
    460c:	f85d fb04 	ldr.w	pc, [sp], #4
    4610:	00009703 	.word	0x00009703

00004614 <generic_hfclk_stop>:
{
    4614:	b510      	push	{r4, lr}
	__asm__ volatile(
    4616:	f04f 0320 	mov.w	r3, #32
    461a:	f3ef 8411 	mrs	r4, BASEPRI
    461e:	f383 8812 	msr	BASEPRI_MAX, r3
    4622:	f3bf 8f6f 	isb	sy
	hfclk_users &= ~HF_USER_GENERIC;
    4626:	4a07      	ldr	r2, [pc, #28]	; (4644 <generic_hfclk_stop+0x30>)
    4628:	6813      	ldr	r3, [r2, #0]
    462a:	f023 0102 	bic.w	r1, r3, #2
	if (!(hfclk_users & HF_USER_BT)) {
    462e:	07db      	lsls	r3, r3, #31
	hfclk_users &= ~HF_USER_GENERIC;
    4630:	6011      	str	r1, [r2, #0]
	if (!(hfclk_users & HF_USER_BT)) {
    4632:	d402      	bmi.n	463a <generic_hfclk_stop+0x26>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    4634:	2001      	movs	r0, #1
    4636:	f001 fb37 	bl	5ca8 <nrfx_clock_stop>
	__asm__ volatile(
    463a:	f384 8811 	msr	BASEPRI, r4
    463e:	f3bf 8f6f 	isb	sy
}
    4642:	bd10      	pop	{r4, pc}
    4644:	20000dd8 	.word	0x20000dd8

00004648 <z_nrf_clock_control_lf_on>:
{
    4648:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    464c:	2201      	movs	r2, #1
    464e:	4606      	mov	r6, r0
    4650:	4943      	ldr	r1, [pc, #268]	; (4760 <z_nrf_clock_control_lf_on+0x118>)
    4652:	e8d1 3fef 	ldaex	r3, [r1]
    4656:	e8c1 2fe0 	stlex	r0, r2, [r1]
    465a:	2800      	cmp	r0, #0
    465c:	d1f9      	bne.n	4652 <z_nrf_clock_control_lf_on+0xa>
	if (atomic_set(&on, 1) == 0) {
    465e:	b9a3      	cbnz	r3, 468a <z_nrf_clock_control_lf_on+0x42>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    4660:	4940      	ldr	r1, [pc, #256]	; (4764 <z_nrf_clock_control_lf_on+0x11c>)
		err = onoff_request(mgr, &cli);
    4662:	4841      	ldr	r0, [pc, #260]	; (4768 <z_nrf_clock_control_lf_on+0x120>)
    4664:	604b      	str	r3, [r1, #4]
    4666:	60cb      	str	r3, [r1, #12]
    4668:	608a      	str	r2, [r1, #8]
    466a:	f7fc fd5f 	bl	112c <onoff_request>
		__ASSERT_NO_MSG(err >= 0);
    466e:	2800      	cmp	r0, #0
    4670:	da0b      	bge.n	468a <z_nrf_clock_control_lf_on+0x42>
    4672:	493e      	ldr	r1, [pc, #248]	; (476c <z_nrf_clock_control_lf_on+0x124>)
    4674:	f44f 730c 	mov.w	r3, #560	; 0x230
    4678:	4a3d      	ldr	r2, [pc, #244]	; (4770 <z_nrf_clock_control_lf_on+0x128>)
    467a:	483e      	ldr	r0, [pc, #248]	; (4774 <z_nrf_clock_control_lf_on+0x12c>)
    467c:	f004 fe13 	bl	92a6 <assert_print>
    4680:	f44f 710c 	mov.w	r1, #560	; 0x230
		__ASSERT_NO_MSG(false);
    4684:	483a      	ldr	r0, [pc, #232]	; (4770 <z_nrf_clock_control_lf_on+0x128>)
    4686:	f004 fe07 	bl	9298 <assert_post_action>
	switch (start_mode) {
    468a:	b376      	cbz	r6, 46ea <z_nrf_clock_control_lf_on+0xa2>
    468c:	1e73      	subs	r3, r6, #1
    468e:	2b01      	cmp	r3, #1
    4690:	d85c      	bhi.n	474c <z_nrf_clock_control_lf_on+0x104>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    4692:	2e01      	cmp	r6, #1
    4694:	d107      	bne.n	46a6 <z_nrf_clock_control_lf_on+0x5e>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    4696:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    469a:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    469e:	f003 0303 	and.w	r3, r3, #3
    46a2:	2b02      	cmp	r3, #2
    46a4:	d021      	beq.n	46ea <z_nrf_clock_control_lf_on+0xa2>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    46a6:	f005 fa6b 	bl	9b80 <k_is_in_isr>
    46aa:	4605      	mov	r5, r0
    46ac:	b9f8      	cbnz	r0, 46ee <z_nrf_clock_control_lf_on+0xa6>
	return !z_sys_post_kernel;
    46ae:	4b32      	ldr	r3, [pc, #200]	; (4778 <z_nrf_clock_control_lf_on+0x130>)
    46b0:	781b      	ldrb	r3, [r3, #0]
    46b2:	b1e3      	cbz	r3, 46ee <z_nrf_clock_control_lf_on+0xa6>
    p_reg->INTENCLR = mask;
    46b4:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    46b8:	2202      	movs	r2, #2
	int key = isr_mode ? irq_lock() : 0;
    46ba:	4607      	mov	r7, r0
    46bc:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    46c0:	f04f 2450 	mov.w	r4, #1342197760	; 0x50005000
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    46c4:	f8df 80b4 	ldr.w	r8, [pc, #180]	; 477c <z_nrf_clock_control_lf_on+0x134>
    46c8:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    46cc:	f8d4 2418 	ldr.w	r2, [r4, #1048]	; 0x418
    46d0:	03d2      	lsls	r2, r2, #15
    46d2:	d516      	bpl.n	4702 <z_nrf_clock_control_lf_on+0xba>
	while (!(nrfx_clock_is_running(d, (void *)&type)
    46d4:	f003 0303 	and.w	r3, r3, #3
    46d8:	2b02      	cmp	r3, #2
    46da:	d001      	beq.n	46e0 <z_nrf_clock_control_lf_on+0x98>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    46dc:	2e01      	cmp	r6, #1
    46de:	d110      	bne.n	4702 <z_nrf_clock_control_lf_on+0xba>
	if (isr_mode) {
    46e0:	b375      	cbz	r5, 4740 <z_nrf_clock_control_lf_on+0xf8>
    46e2:	f387 8811 	msr	BASEPRI, r7
    46e6:	f3bf 8f6f 	isb	sy
}
    46ea:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	__asm__ volatile(
    46ee:	f04f 0320 	mov.w	r3, #32
    46f2:	f3ef 8711 	mrs	r7, BASEPRI
    46f6:	f383 8812 	msr	BASEPRI_MAX, r3
    46fa:	f3bf 8f6f 	isb	sy
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    46fe:	2501      	movs	r5, #1
    4700:	e7de      	b.n	46c0 <z_nrf_clock_control_lf_on+0x78>
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    4702:	b1c5      	cbz	r5, 4736 <z_nrf_clock_control_lf_on+0xee>
 *
 * @param key Interrupt locking key obtained from irq_lock().
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    4704:	4638      	mov	r0, r7
    4706:	f7fe fe83 	bl	3410 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    470a:	f8d4 3518 	ldr.w	r3, [r4, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    470e:	b2db      	uxtb	r3, r3
    4710:	2b01      	cmp	r3, #1
    4712:	d1d9      	bne.n	46c8 <z_nrf_clock_control_lf_on+0x80>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    4714:	f8d4 2104 	ldr.w	r2, [r4, #260]	; 0x104
		    && nrf_clock_event_check(NRF_CLOCK,
    4718:	2a00      	cmp	r2, #0
    471a:	d0d5      	beq.n	46c8 <z_nrf_clock_control_lf_on+0x80>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    471c:	2200      	movs	r2, #0
    471e:	f8c4 2104 	str.w	r2, [r4, #260]	; 0x104
    4722:	f8d4 2104 	ldr.w	r2, [r4, #260]	; 0x104
    p_reg->LFCLKSRC = (uint32_t)(source);
    4726:	2202      	movs	r2, #2
    4728:	f8c4 2518 	str.w	r2, [r4, #1304]	; 0x518
    472c:	2220      	movs	r2, #32
    472e:	f8c8 2180 	str.w	r2, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4732:	60a3      	str	r3, [r4, #8]
}
    4734:	e7c8      	b.n	46c8 <z_nrf_clock_control_lf_on+0x80>
	return z_impl_k_sleep(timeout);
    4736:	2100      	movs	r1, #0
    4738:	2021      	movs	r0, #33	; 0x21
    473a:	f003 fdcd 	bl	82d8 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    473e:	e7e4      	b.n	470a <z_nrf_clock_control_lf_on+0xc2>
    p_reg->INTENSET = mask;
    4740:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    4744:	2202      	movs	r2, #2
    4746:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    474a:	e7ce      	b.n	46ea <z_nrf_clock_control_lf_on+0xa2>
		__ASSERT_NO_MSG(false);
    474c:	490c      	ldr	r1, [pc, #48]	; (4780 <z_nrf_clock_control_lf_on+0x138>)
    474e:	f240 2342 	movw	r3, #578	; 0x242
    4752:	4a07      	ldr	r2, [pc, #28]	; (4770 <z_nrf_clock_control_lf_on+0x128>)
    4754:	4807      	ldr	r0, [pc, #28]	; (4774 <z_nrf_clock_control_lf_on+0x12c>)
    4756:	f004 fda6 	bl	92a6 <assert_print>
    475a:	f240 2142 	movw	r1, #578	; 0x242
    475e:	e791      	b.n	4684 <z_nrf_clock_control_lf_on+0x3c>
    4760:	20000d24 	.word	0x20000d24
    4764:	20000d14 	.word	0x20000d14
    4768:	20000d48 	.word	0x20000d48
    476c:	0000a957 	.word	0x0000a957
    4770:	0000b256 	.word	0x0000b256
    4774:	0000a2e8 	.word	0x0000a2e8
    4778:	200010ce 	.word	0x200010ce
    477c:	e000e100 	.word	0xe000e100
    4780:	0000a5f9 	.word	0x0000a5f9

00004784 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    4784:	b508      	push	{r3, lr}
    4786:	4807      	ldr	r0, [pc, #28]	; (47a4 <uart_console_init+0x20>)
    4788:	f005 f9c6 	bl	9b18 <z_device_is_ready>

	ARG_UNUSED(arg);

	if (!device_is_ready(uart_console_dev)) {
    478c:	b138      	cbz	r0, 479e <uart_console_init+0x1a>
	__stdout_hook_install(console_out);
    478e:	4806      	ldr	r0, [pc, #24]	; (47a8 <uart_console_init+0x24>)
    4790:	f7ff fdd8 	bl	4344 <__stdout_hook_install>
	__printk_hook_install(console_out);
    4794:	4804      	ldr	r0, [pc, #16]	; (47a8 <uart_console_init+0x24>)
    4796:	f7fc faa7 	bl	ce8 <__printk_hook_install>
		return -ENODEV;
	}

	uart_console_hook_install();

	return 0;
    479a:	2000      	movs	r0, #0
}
    479c:	bd08      	pop	{r3, pc}
		return -ENODEV;
    479e:	f06f 0012 	mvn.w	r0, #18
    47a2:	e7fb      	b.n	479c <uart_console_init+0x18>
    47a4:	00009d0c 	.word	0x00009d0c
    47a8:	000047ad 	.word	0x000047ad

000047ac <console_out>:
	if ('\n' == c) {
    47ac:	280a      	cmp	r0, #10
{
    47ae:	b538      	push	{r3, r4, r5, lr}
    47b0:	4604      	mov	r4, r0
    47b2:	4d07      	ldr	r5, [pc, #28]	; (47d0 <console_out+0x24>)
	if ('\n' == c) {
    47b4:	d104      	bne.n	47c0 <console_out+0x14>
    47b6:	68ab      	ldr	r3, [r5, #8]
    47b8:	210d      	movs	r1, #13
    47ba:	4628      	mov	r0, r5
    47bc:	685b      	ldr	r3, [r3, #4]
    47be:	4798      	blx	r3
    47c0:	68ab      	ldr	r3, [r5, #8]
    47c2:	4803      	ldr	r0, [pc, #12]	; (47d0 <console_out+0x24>)
    47c4:	685b      	ldr	r3, [r3, #4]
    47c6:	b2e1      	uxtb	r1, r4
    47c8:	4798      	blx	r3
}
    47ca:	4620      	mov	r0, r4
    47cc:	bd38      	pop	{r3, r4, r5, pc}
    47ce:	bf00      	nop
    47d0:	00009d0c 	.word	0x00009d0c

000047d4 <gpio_nrfx_manage_callback>:
}

static int gpio_nrfx_manage_callback(const struct device *port,
				     struct gpio_callback *callback,
				     bool set)
{
    47d4:	b510      	push	{r4, lr}
	return port->data;
    47d6:	6903      	ldr	r3, [r0, #16]
 */
static inline int gpio_manage_callback(sys_slist_t *callbacks,
					struct gpio_callback *callback,
					bool set)
{
	__ASSERT(callback, "No callback!");
    47d8:	b961      	cbnz	r1, 47f4 <gpio_nrfx_manage_callback+0x20>
    47da:	4920      	ldr	r1, [pc, #128]	; (485c <gpio_nrfx_manage_callback+0x88>)
    47dc:	232a      	movs	r3, #42	; 0x2a
    47de:	4a20      	ldr	r2, [pc, #128]	; (4860 <gpio_nrfx_manage_callback+0x8c>)
    47e0:	4820      	ldr	r0, [pc, #128]	; (4864 <gpio_nrfx_manage_callback+0x90>)
    47e2:	f004 fd60 	bl	92a6 <assert_print>
    47e6:	4820      	ldr	r0, [pc, #128]	; (4868 <gpio_nrfx_manage_callback+0x94>)
    47e8:	f004 fd5d 	bl	92a6 <assert_print>
    47ec:	212a      	movs	r1, #42	; 0x2a
	__ASSERT(callback->handler, "No callback handler!");
    47ee:	481c      	ldr	r0, [pc, #112]	; (4860 <gpio_nrfx_manage_callback+0x8c>)
    47f0:	f004 fd52 	bl	9298 <assert_post_action>
    47f4:	6848      	ldr	r0, [r1, #4]
    47f6:	b950      	cbnz	r0, 480e <gpio_nrfx_manage_callback+0x3a>
    47f8:	491c      	ldr	r1, [pc, #112]	; (486c <gpio_nrfx_manage_callback+0x98>)
    47fa:	232b      	movs	r3, #43	; 0x2b
    47fc:	4a18      	ldr	r2, [pc, #96]	; (4860 <gpio_nrfx_manage_callback+0x8c>)
    47fe:	4819      	ldr	r0, [pc, #100]	; (4864 <gpio_nrfx_manage_callback+0x90>)
    4800:	f004 fd51 	bl	92a6 <assert_print>
    4804:	481a      	ldr	r0, [pc, #104]	; (4870 <gpio_nrfx_manage_callback+0x9c>)
    4806:	f004 fd4e 	bl	92a6 <assert_print>
    480a:	212b      	movs	r1, #43	; 0x2b
    480c:	e7ef      	b.n	47ee <gpio_nrfx_manage_callback+0x1a>
	return list->head;
    480e:	6858      	ldr	r0, [r3, #4]

	if (!sys_slist_is_empty(callbacks)) {
    4810:	b1f8      	cbz	r0, 4852 <gpio_nrfx_manage_callback+0x7e>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    4812:	4288      	cmp	r0, r1
    4814:	d119      	bne.n	484a <gpio_nrfx_manage_callback+0x76>
Z_GENLIST_REMOVE(slist, snode)
    4816:	689c      	ldr	r4, [r3, #8]
	return node->next;
    4818:	6808      	ldr	r0, [r1, #0]
Z_GENLIST_REMOVE(slist, snode)
    481a:	42a1      	cmp	r1, r4
	list->head = node;
    481c:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    481e:	d100      	bne.n	4822 <gpio_nrfx_manage_callback+0x4e>
	list->tail = node;
    4820:	6098      	str	r0, [r3, #8]
	parent->next = child;
    4822:	2000      	movs	r0, #0
    4824:	6008      	str	r0, [r1, #0]
		}
	} else if (!set) {
		return -EINVAL;
	}

	if (set) {
    4826:	b12a      	cbz	r2, 4834 <gpio_nrfx_manage_callback+0x60>
	return list->head;
    4828:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
    482a:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
    482c:	689a      	ldr	r2, [r3, #8]
	list->head = node;
    482e:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    4830:	b902      	cbnz	r2, 4834 <gpio_nrfx_manage_callback+0x60>
	list->tail = node;
    4832:	6099      	str	r1, [r3, #8]
		sys_slist_prepend(callbacks, &callback->node);
	}

	return 0;
    4834:	2000      	movs	r0, #0
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    4836:	e010      	b.n	485a <gpio_nrfx_manage_callback+0x86>
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    4838:	4281      	cmp	r1, r0
    483a:	d106      	bne.n	484a <gpio_nrfx_manage_callback+0x76>
	return node->next;
    483c:	6808      	ldr	r0, [r1, #0]
	parent->next = child;
    483e:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
    4840:	6898      	ldr	r0, [r3, #8]
    4842:	4281      	cmp	r1, r0
    4844:	d1ed      	bne.n	4822 <gpio_nrfx_manage_callback+0x4e>
	list->tail = node;
    4846:	609c      	str	r4, [r3, #8]
}
    4848:	e7eb      	b.n	4822 <gpio_nrfx_manage_callback+0x4e>
	return node->next;
    484a:	4604      	mov	r4, r0
    484c:	6800      	ldr	r0, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    484e:	2800      	cmp	r0, #0
    4850:	d1f2      	bne.n	4838 <gpio_nrfx_manage_callback+0x64>
			if (!set) {
    4852:	2a00      	cmp	r2, #0
    4854:	d1e8      	bne.n	4828 <gpio_nrfx_manage_callback+0x54>
				return -EINVAL;
    4856:	f06f 0015 	mvn.w	r0, #21
				     callback, set);
}
    485a:	bd10      	pop	{r4, pc}
    485c:	0000b32d 	.word	0x0000b32d
    4860:	0000b2f1 	.word	0x0000b2f1
    4864:	0000a2e8 	.word	0x0000a2e8
    4868:	0000b336 	.word	0x0000b336
    486c:	0000b345 	.word	0x0000b345
    4870:	0000b357 	.word	0x0000b357

00004874 <gpio_nrfx_pin_interrupt_configure>:
{
    4874:	b530      	push	{r4, r5, lr}
	return port->config;
    4876:	6840      	ldr	r0, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    4878:	f001 041f 	and.w	r4, r1, #31
    487c:	7b05      	ldrb	r5, [r0, #12]
	if (mode == GPIO_INT_MODE_DISABLED) {
    487e:	f5b2 1f00 	cmp.w	r2, #2097152	; 0x200000
{
    4882:	b085      	sub	sp, #20
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    4884:	ea44 1445 	orr.w	r4, r4, r5, lsl #5
	if (mode == GPIO_INT_MODE_DISABLED) {
    4888:	d105      	bne.n	4896 <gpio_nrfx_pin_interrupt_configure+0x22>
		nrfx_gpiote_trigger_disable(abs_pin);
    488a:	4620      	mov	r0, r4
    488c:	f001 fd5a 	bl	6344 <nrfx_gpiote_trigger_disable>
		return 0;
    4890:	2000      	movs	r0, #0
}
    4892:	b005      	add	sp, #20
    4894:	bd30      	pop	{r4, r5, pc}
	nrfx_gpiote_trigger_config_t trigger_config = {
    4896:	2500      	movs	r5, #0
	if (mode == GPIO_INT_MODE_LEVEL) {
    4898:	f5b2 0f80 	cmp.w	r2, #4194304	; 0x400000
	nrfx_gpiote_trigger_config_t trigger_config = {
    489c:	e9cd 5502 	strd	r5, r5, [sp, #8]
	if (mode == GPIO_INT_MODE_LEVEL) {
    48a0:	d114      	bne.n	48cc <gpio_nrfx_pin_interrupt_configure+0x58>
		return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
    48a2:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
	nrfx_gpiote_trigger_config_t trigger_config = {
    48a6:	bf0c      	ite	eq
    48a8:	2304      	moveq	r3, #4
    48aa:	2305      	movne	r3, #5
    48ac:	f88d 3008 	strb.w	r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    48b0:	2300      	movs	r3, #0
    48b2:	4620      	mov	r0, r4
    48b4:	4619      	mov	r1, r3
    48b6:	aa02      	add	r2, sp, #8
    48b8:	f001 fb4c 	bl	5f54 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    48bc:	4b2a      	ldr	r3, [pc, #168]	; (4968 <gpio_nrfx_pin_interrupt_configure+0xf4>)
    48be:	4298      	cmp	r0, r3
    48c0:	d14f      	bne.n	4962 <gpio_nrfx_pin_interrupt_configure+0xee>
	nrfx_gpiote_trigger_enable(abs_pin, true);
    48c2:	2101      	movs	r1, #1
    48c4:	4620      	mov	r0, r4
    48c6:	f001 fcd1 	bl	626c <nrfx_gpiote_trigger_enable>
	return 0;
    48ca:	e7e1      	b.n	4890 <gpio_nrfx_pin_interrupt_configure+0x1c>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    48cc:	f1b3 6fc0 	cmp.w	r3, #100663296	; 0x6000000
    48d0:	d024      	beq.n	491c <gpio_nrfx_pin_interrupt_configure+0xa8>
    48d2:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    48d6:	bf14      	ite	ne
    48d8:	2301      	movne	r3, #1
    48da:	2302      	moveq	r3, #2
	nrfx_gpiote_trigger_config_t trigger_config = {
    48dc:	f88d 3008 	strb.w	r3, [sp, #8]
	if (!(BIT(pin) & get_port_cfg(port)->edge_sense) &&
    48e0:	6883      	ldr	r3, [r0, #8]
    48e2:	40cb      	lsrs	r3, r1
    48e4:	07d8      	lsls	r0, r3, #31
    48e6:	d4e3      	bmi.n	48b0 <gpio_nrfx_pin_interrupt_configure+0x3c>
    48e8:	f1b2 7fa0 	cmp.w	r2, #20971520	; 0x1400000
    48ec:	d1e0      	bne.n	48b0 <gpio_nrfx_pin_interrupt_configure+0x3c>
NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number)
{
    uint32_t port = pin_number >> 5;
    uint32_t mask = 0;

    switch (port)
    48ee:	0962      	lsrs	r2, r4, #5
    48f0:	f004 031f 	and.w	r3, r4, #31
    48f4:	d014      	beq.n	4920 <gpio_nrfx_pin_interrupt_configure+0xac>
    48f6:	2a01      	cmp	r2, #1
    48f8:	d104      	bne.n	4904 <gpio_nrfx_pin_interrupt_configure+0x90>
#endif
    }

    pin_number &= 0x1F;

    return (mask & (1UL << pin_number)) ? true : false;
    48fa:	f64f 72ff 	movw	r2, #65535	; 0xffff
    48fe:	40da      	lsrs	r2, r3
    NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
    4900:	07d1      	lsls	r1, r2, #31
    4902:	d414      	bmi.n	492e <gpio_nrfx_pin_interrupt_configure+0xba>
    4904:	4919      	ldr	r1, [pc, #100]	; (496c <gpio_nrfx_pin_interrupt_configure+0xf8>)
    4906:	481a      	ldr	r0, [pc, #104]	; (4970 <gpio_nrfx_pin_interrupt_configure+0xfc>)
    4908:	f240 2347 	movw	r3, #583	; 0x247
    490c:	4a19      	ldr	r2, [pc, #100]	; (4974 <gpio_nrfx_pin_interrupt_configure+0x100>)
    490e:	f004 fcca 	bl	92a6 <assert_print>
    4912:	f240 2147 	movw	r1, #583	; 0x247
    4916:	4817      	ldr	r0, [pc, #92]	; (4974 <gpio_nrfx_pin_interrupt_configure+0x100>)
    4918:	f004 fcbe 	bl	9298 <assert_post_action>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    491c:	2303      	movs	r3, #3
    491e:	e7dd      	b.n	48dc <gpio_nrfx_pin_interrupt_configure+0x68>
    return (mask & (1UL << pin_number)) ? true : false;
    4920:	f04f 32ff 	mov.w	r2, #4294967295
    4924:	40da      	lsrs	r2, r3
    NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
    4926:	07d2      	lsls	r2, r2, #31
    4928:	d5ec      	bpl.n	4904 <gpio_nrfx_pin_interrupt_configure+0x90>
        case 0: return NRF_P0;
    492a:	4a13      	ldr	r2, [pc, #76]	; (4978 <gpio_nrfx_pin_interrupt_configure+0x104>)
    492c:	e000      	b.n	4930 <gpio_nrfx_pin_interrupt_configure+0xbc>
        case 1: return NRF_P1;
    492e:	4a13      	ldr	r2, [pc, #76]	; (497c <gpio_nrfx_pin_interrupt_configure+0x108>)
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    4930:	3380      	adds	r3, #128	; 0x80
    4932:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    4936:	07db      	lsls	r3, r3, #31
    4938:	d4ba      	bmi.n	48b0 <gpio_nrfx_pin_interrupt_configure+0x3c>
		err = nrfx_gpiote_channel_get(abs_pin, &ch);
    493a:	f10d 0507 	add.w	r5, sp, #7
    493e:	4629      	mov	r1, r5
    4940:	4620      	mov	r0, r4
    4942:	f001 fc2d 	bl	61a0 <nrfx_gpiote_channel_get>
		if (err == NRFX_ERROR_INVALID_PARAM) {
    4946:	4b0e      	ldr	r3, [pc, #56]	; (4980 <gpio_nrfx_pin_interrupt_configure+0x10c>)
    4948:	4298      	cmp	r0, r3
    494a:	d001      	beq.n	4950 <gpio_nrfx_pin_interrupt_configure+0xdc>
		trigger_config.p_in_channel = &ch;
    494c:	9503      	str	r5, [sp, #12]
    494e:	e7af      	b.n	48b0 <gpio_nrfx_pin_interrupt_configure+0x3c>
			err = nrfx_gpiote_channel_alloc(&ch);
    4950:	4628      	mov	r0, r5
    4952:	f001 fc85 	bl	6260 <nrfx_gpiote_channel_alloc>
			if (err != NRFX_SUCCESS) {
    4956:	4b04      	ldr	r3, [pc, #16]	; (4968 <gpio_nrfx_pin_interrupt_configure+0xf4>)
    4958:	4298      	cmp	r0, r3
    495a:	d0f7      	beq.n	494c <gpio_nrfx_pin_interrupt_configure+0xd8>
				return -ENOMEM;
    495c:	f06f 000b 	mvn.w	r0, #11
    4960:	e797      	b.n	4892 <gpio_nrfx_pin_interrupt_configure+0x1e>
		return -EINVAL;
    4962:	f06f 0015 	mvn.w	r0, #21
    4966:	e794      	b.n	4892 <gpio_nrfx_pin_interrupt_configure+0x1e>
    4968:	0bad0000 	.word	0x0bad0000
    496c:	0000b3a1 	.word	0x0000b3a1
    4970:	0000a2e8 	.word	0x0000a2e8
    4974:	0000b36e 	.word	0x0000b36e
    4978:	50842500 	.word	0x50842500
    497c:	50842800 	.word	0x50842800
    4980:	0bad0004 	.word	0x0bad0004

00004984 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    4984:	b510      	push	{r4, lr}
	nrfx_err_t err;

	if (nrfx_gpiote_is_init()) {
    4986:	f001 fc5b 	bl	6240 <nrfx_gpiote_is_init>
    498a:	4604      	mov	r4, r0
    498c:	b968      	cbnz	r0, 49aa <gpio_nrfx_init+0x26>
		return 0;
	}

	err = nrfx_gpiote_init(0/*not used*/);
    498e:	f001 fc2f 	bl	61f0 <nrfx_gpiote_init>
	if (err != NRFX_SUCCESS) {
    4992:	4b08      	ldr	r3, [pc, #32]	; (49b4 <gpio_nrfx_init+0x30>)
    4994:	4298      	cmp	r0, r3
    4996:	d10a      	bne.n	49ae <gpio_nrfx_init+0x2a>
		return -EIO;
	}

	nrfx_gpiote_global_callback_set(nrfx_gpio_handler, NULL);
    4998:	4621      	mov	r1, r4
    499a:	4807      	ldr	r0, [pc, #28]	; (49b8 <gpio_nrfx_init+0x34>)
    499c:	f001 fbfa 	bl	6194 <nrfx_gpiote_global_callback_set>

	IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    49a0:	4622      	mov	r2, r4
    49a2:	2105      	movs	r1, #5
    49a4:	200d      	movs	r0, #13
    49a6:	f7fe fddb 	bl	3560 <z_arm_irq_priority_set>
		return 0;
    49aa:	2000      	movs	r0, #0
		    nrfx_isr, nrfx_gpiote_irq_handler, 0);

	return 0;
}
    49ac:	bd10      	pop	{r4, pc}
		return -EIO;
    49ae:	f06f 0004 	mvn.w	r0, #4
    49b2:	e7fb      	b.n	49ac <gpio_nrfx_init+0x28>
    49b4:	0bad0000 	.word	0x0bad0000
    49b8:	000049bd 	.word	0x000049bd

000049bc <nrfx_gpio_handler>:
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    49bc:	0942      	lsrs	r2, r0, #5
{
    49be:	4603      	mov	r3, r0
    49c0:	b570      	push	{r4, r5, r6, lr}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    49c2:	d002      	beq.n	49ca <nrfx_gpio_handler+0xe>
    49c4:	2a01      	cmp	r2, #1
    49c6:	d01e      	beq.n	4a06 <nrfx_gpio_handler+0x4a>
}
    49c8:	bd70      	pop	{r4, r5, r6, pc}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    49ca:	4e14      	ldr	r6, [pc, #80]	; (4a1c <nrfx_gpio_handler+0x60>)
	gpio_fire_callbacks(list, port, BIT(pin));
    49cc:	6932      	ldr	r2, [r6, #16]
    49ce:	6851      	ldr	r1, [r2, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    49d0:	2900      	cmp	r1, #0
    49d2:	d0f9      	beq.n	49c8 <nrfx_gpio_handler+0xc>
    49d4:	2501      	movs	r5, #1
}

NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;
    49d6:	f003 031f 	and.w	r3, r3, #31
	return node->next;
    49da:	680c      	ldr	r4, [r1, #0]
    49dc:	409d      	lsls	r5, r3
    49de:	2900      	cmp	r1, #0
    49e0:	d0f2      	beq.n	49c8 <nrfx_gpio_handler+0xc>
		if (cb->pin_mask & pins) {
    49e2:	688a      	ldr	r2, [r1, #8]
    49e4:	402a      	ands	r2, r5
    49e6:	d012      	beq.n	4a0e <nrfx_gpio_handler+0x52>
			__ASSERT(cb->handler, "No callback handler!");
    49e8:	684b      	ldr	r3, [r1, #4]
    49ea:	b973      	cbnz	r3, 4a0a <nrfx_gpio_handler+0x4e>
    49ec:	490c      	ldr	r1, [pc, #48]	; (4a20 <nrfx_gpio_handler+0x64>)
    49ee:	234d      	movs	r3, #77	; 0x4d
    49f0:	4a0c      	ldr	r2, [pc, #48]	; (4a24 <nrfx_gpio_handler+0x68>)
    49f2:	480d      	ldr	r0, [pc, #52]	; (4a28 <nrfx_gpio_handler+0x6c>)
    49f4:	f004 fc57 	bl	92a6 <assert_print>
    49f8:	480c      	ldr	r0, [pc, #48]	; (4a2c <nrfx_gpio_handler+0x70>)
    49fa:	f004 fc54 	bl	92a6 <assert_print>
    49fe:	214d      	movs	r1, #77	; 0x4d
    4a00:	4808      	ldr	r0, [pc, #32]	; (4a24 <nrfx_gpio_handler+0x68>)
    4a02:	f004 fc49 	bl	9298 <assert_post_action>
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    4a06:	4e0a      	ldr	r6, [pc, #40]	; (4a30 <nrfx_gpio_handler+0x74>)
    4a08:	e7e0      	b.n	49cc <nrfx_gpio_handler+0x10>
			cb->handler(port, cb, cb->pin_mask & pins);
    4a0a:	4630      	mov	r0, r6
    4a0c:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    4a0e:	b11c      	cbz	r4, 4a18 <nrfx_gpio_handler+0x5c>
    4a10:	6823      	ldr	r3, [r4, #0]
    4a12:	4621      	mov	r1, r4
    4a14:	461c      	mov	r4, r3
    4a16:	e7e2      	b.n	49de <nrfx_gpio_handler+0x22>
    4a18:	4623      	mov	r3, r4
    4a1a:	e7fa      	b.n	4a12 <nrfx_gpio_handler+0x56>
    4a1c:	00009cf4 	.word	0x00009cf4
    4a20:	0000b3c4 	.word	0x0000b3c4
    4a24:	0000b2f1 	.word	0x0000b2f1
    4a28:	0000a2e8 	.word	0x0000a2e8
    4a2c:	0000b357 	.word	0x0000b357
    4a30:	00009cdc 	.word	0x00009cdc

00004a34 <gpio_nrfx_pin_configure>:
{
    4a34:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
	return port->config;
    4a38:	f8d0 8004 	ldr.w	r8, [r0, #4]
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    4a3c:	f001 051f 	and.w	r5, r1, #31
    4a40:	f898 300c 	ldrb.w	r3, [r8, #12]
{
    4a44:	4614      	mov	r4, r2
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    4a46:	ea45 1543 	orr.w	r5, r5, r3, lsl #5
{
    4a4a:	460f      	mov	r7, r1
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    4a4c:	4628      	mov	r0, r5
    4a4e:	f10d 0103 	add.w	r1, sp, #3
    4a52:	f001 fba5 	bl	61a0 <nrfx_gpiote_channel_get>
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    4a56:	f414 3f40 	tst.w	r4, #196608	; 0x30000
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    4a5a:	4606      	mov	r6, r0
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    4a5c:	d115      	bne.n	4a8a <gpio_nrfx_pin_configure+0x56>
		(void)nrfx_gpiote_pin_uninit(abs_pin);
    4a5e:	4628      	mov	r0, r5
    4a60:	f001 fc9a 	bl	6398 <nrfx_gpiote_pin_uninit>
		if (free_ch) {
    4a64:	4b48      	ldr	r3, [pc, #288]	; (4b88 <gpio_nrfx_pin_configure+0x154>)
    4a66:	429e      	cmp	r6, r3
    4a68:	d170      	bne.n	4b4c <gpio_nrfx_pin_configure+0x118>
			err = nrfx_gpiote_channel_free(ch);
    4a6a:	f89d 0003 	ldrb.w	r0, [sp, #3]
    4a6e:	f001 fbf1 	bl	6254 <nrfx_gpiote_channel_free>
			__ASSERT_NO_MSG(err == NRFX_SUCCESS);
    4a72:	42b0      	cmp	r0, r6
    4a74:	d06a      	beq.n	4b4c <gpio_nrfx_pin_configure+0x118>
    4a76:	4945      	ldr	r1, [pc, #276]	; (4b8c <gpio_nrfx_pin_configure+0x158>)
    4a78:	236a      	movs	r3, #106	; 0x6a
    4a7a:	4a45      	ldr	r2, [pc, #276]	; (4b90 <gpio_nrfx_pin_configure+0x15c>)
    4a7c:	4845      	ldr	r0, [pc, #276]	; (4b94 <gpio_nrfx_pin_configure+0x160>)
    4a7e:	f004 fc12 	bl	92a6 <assert_print>
    4a82:	216a      	movs	r1, #106	; 0x6a
		__ASSERT_NO_MSG(err == NRFX_SUCCESS);
    4a84:	4842      	ldr	r0, [pc, #264]	; (4b90 <gpio_nrfx_pin_configure+0x15c>)
    4a86:	f004 fc07 	bl	9298 <assert_post_action>
	nrfx_gpiote_trigger_config_t trigger_config = {
    4a8a:	2300      	movs	r3, #0
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    4a8c:	4628      	mov	r0, r5
    4a8e:	4619      	mov	r1, r3
    4a90:	aa02      	add	r2, sp, #8
	nrfx_gpiote_trigger_config_t trigger_config = {
    4a92:	e9cd 3302 	strd	r3, r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    4a96:	f001 fa5d 	bl	5f54 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    4a9a:	4b3b      	ldr	r3, [pc, #236]	; (4b88 <gpio_nrfx_pin_configure+0x154>)
    4a9c:	4298      	cmp	r0, r3
    4a9e:	d004      	beq.n	4aaa <gpio_nrfx_pin_configure+0x76>
		return NRF_GPIO_PIN_PULLUP;
    4aa0:	f06f 0015 	mvn.w	r0, #21
}
    4aa4:	b004      	add	sp, #16
    4aa6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if (free_ch) {
    4aaa:	4286      	cmp	r6, r0
    4aac:	d10d      	bne.n	4aca <gpio_nrfx_pin_configure+0x96>
		err = nrfx_gpiote_channel_free(ch);
    4aae:	f89d 0003 	ldrb.w	r0, [sp, #3]
    4ab2:	f001 fbcf 	bl	6254 <nrfx_gpiote_channel_free>
		__ASSERT_NO_MSG(err == NRFX_SUCCESS);
    4ab6:	42b0      	cmp	r0, r6
    4ab8:	d007      	beq.n	4aca <gpio_nrfx_pin_configure+0x96>
    4aba:	4934      	ldr	r1, [pc, #208]	; (4b8c <gpio_nrfx_pin_configure+0x158>)
    4abc:	237c      	movs	r3, #124	; 0x7c
    4abe:	4a34      	ldr	r2, [pc, #208]	; (4b90 <gpio_nrfx_pin_configure+0x15c>)
    4ac0:	4834      	ldr	r0, [pc, #208]	; (4b94 <gpio_nrfx_pin_configure+0x160>)
    4ac2:	f004 fbf0 	bl	92a6 <assert_print>
    4ac6:	217c      	movs	r1, #124	; 0x7c
    4ac8:	e7dc      	b.n	4a84 <gpio_nrfx_pin_configure+0x50>
	if (flags & GPIO_OUTPUT) {
    4aca:	03a6      	lsls	r6, r4, #14
    4acc:	d54c      	bpl.n	4b68 <gpio_nrfx_pin_configure+0x134>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    4ace:	f240 3306 	movw	r3, #774	; 0x306
    4ad2:	4023      	ands	r3, r4
    4ad4:	f5b3 7f83 	cmp.w	r3, #262	; 0x106
    4ad8:	d019      	beq.n	4b0e <gpio_nrfx_pin_configure+0xda>
    4ada:	d80c      	bhi.n	4af6 <gpio_nrfx_pin_configure+0xc2>
    4adc:	2b06      	cmp	r3, #6
    4ade:	d017      	beq.n	4b10 <gpio_nrfx_pin_configure+0xdc>
    4ae0:	d804      	bhi.n	4aec <gpio_nrfx_pin_configure+0xb8>
    4ae2:	b1ab      	cbz	r3, 4b10 <gpio_nrfx_pin_configure+0xdc>
    4ae4:	2b02      	cmp	r3, #2
    4ae6:	d1db      	bne.n	4aa0 <gpio_nrfx_pin_configure+0x6c>
		*drive = NRF_GPIO_PIN_D0S1;
    4ae8:	2304      	movs	r3, #4
    4aea:	e011      	b.n	4b10 <gpio_nrfx_pin_configure+0xdc>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    4aec:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
    4af0:	d1d6      	bne.n	4aa0 <gpio_nrfx_pin_configure+0x6c>
		*drive = NRF_GPIO_PIN_H0S1;
    4af2:	2301      	movs	r3, #1
    4af4:	e00c      	b.n	4b10 <gpio_nrfx_pin_configure+0xdc>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    4af6:	f240 2202 	movw	r2, #514	; 0x202
    4afa:	4293      	cmp	r3, r2
    4afc:	d028      	beq.n	4b50 <gpio_nrfx_pin_configure+0x11c>
    4afe:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
    4b02:	d027      	beq.n	4b54 <gpio_nrfx_pin_configure+0x120>
    4b04:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    4b08:	d1ca      	bne.n	4aa0 <gpio_nrfx_pin_configure+0x6c>
		*drive = NRF_GPIO_PIN_S0H1;
    4b0a:	2302      	movs	r3, #2
    4b0c:	e000      	b.n	4b10 <gpio_nrfx_pin_configure+0xdc>
		*drive = NRF_GPIO_PIN_H0D1;
    4b0e:	2307      	movs	r3, #7
		nrfx_gpiote_output_config_t output_config = {
    4b10:	f88d 3004 	strb.w	r3, [sp, #4]
				NRF_GPIO_PIN_INPUT_CONNECT :
    4b14:	f484 3380 	eor.w	r3, r4, #65536	; 0x10000
    4b18:	f3c3 4300 	ubfx	r3, r3, #16, #1
	if (flags & GPIO_PULL_UP) {
    4b1c:	06e0      	lsls	r0, r4, #27
		nrfx_gpiote_output_config_t output_config = {
    4b1e:	f88d 3005 	strb.w	r3, [sp, #5]
		return NRF_GPIO_PIN_PULLUP;
    4b22:	bf4c      	ite	mi
    4b24:	2303      	movmi	r3, #3
	} else if (flags & GPIO_PULL_DOWN) {
    4b26:	f3c4 1340 	ubfxpl	r3, r4, #5, #1
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    4b2a:	0321      	lsls	r1, r4, #12
		nrfx_gpiote_output_config_t output_config = {
    4b2c:	f88d 3006 	strb.w	r3, [sp, #6]
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    4b30:	d512      	bpl.n	4b58 <gpio_nrfx_pin_configure+0x124>
			nrf_gpio_port_out_set(cfg->port, BIT(pin));
    4b32:	2301      	movs	r3, #1
    4b34:	f8d8 2004 	ldr.w	r2, [r8, #4]
    4b38:	40bb      	lsls	r3, r7
    p_reg->OUTSET = set_mask;
    4b3a:	6093      	str	r3, [r2, #8]
		err = nrfx_gpiote_output_configure(abs_pin, &output_config, NULL);
    4b3c:	2200      	movs	r2, #0
    4b3e:	4628      	mov	r0, r5
    4b40:	a901      	add	r1, sp, #4
    4b42:	f001 faaf 	bl	60a4 <nrfx_gpiote_output_configure>
		return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    4b46:	4b10      	ldr	r3, [pc, #64]	; (4b88 <gpio_nrfx_pin_configure+0x154>)
    4b48:	4298      	cmp	r0, r3
    4b4a:	d1a9      	bne.n	4aa0 <gpio_nrfx_pin_configure+0x6c>
    4b4c:	2000      	movs	r0, #0
    4b4e:	e7a9      	b.n	4aa4 <gpio_nrfx_pin_configure+0x70>
		*drive = NRF_GPIO_PIN_D0H1;
    4b50:	2305      	movs	r3, #5
    4b52:	e7dd      	b.n	4b10 <gpio_nrfx_pin_configure+0xdc>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    4b54:	2303      	movs	r3, #3
    4b56:	e7db      	b.n	4b10 <gpio_nrfx_pin_configure+0xdc>
		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
    4b58:	0362      	lsls	r2, r4, #13
			nrf_gpio_port_out_clear(cfg->port, BIT(pin));
    4b5a:	bf41      	itttt	mi
    4b5c:	2301      	movmi	r3, #1
    4b5e:	f8d8 2004 	ldrmi.w	r2, [r8, #4]
    4b62:	40bb      	lslmi	r3, r7
    p_reg->OUTCLR = clr_mask;
    4b64:	60d3      	strmi	r3, [r2, #12]
}
    4b66:	e7e9      	b.n	4b3c <gpio_nrfx_pin_configure+0x108>
	if (flags & GPIO_PULL_UP) {
    4b68:	06e3      	lsls	r3, r4, #27
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    4b6a:	f04f 0300 	mov.w	r3, #0
		return NRF_GPIO_PIN_PULLUP;
    4b6e:	bf4c      	ite	mi
    4b70:	2403      	movmi	r4, #3
	} else if (flags & GPIO_PULL_DOWN) {
    4b72:	f3c4 1440 	ubfxpl	r4, r4, #5, #1
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    4b76:	461a      	mov	r2, r3
    4b78:	4628      	mov	r0, r5
    4b7a:	a901      	add	r1, sp, #4
	nrfx_gpiote_input_config_t input_config = {
    4b7c:	f88d 4004 	strb.w	r4, [sp, #4]
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    4b80:	f001 f9e8 	bl	5f54 <nrfx_gpiote_input_configure>
    4b84:	e7df      	b.n	4b46 <gpio_nrfx_pin_configure+0x112>
    4b86:	bf00      	nop
    4b88:	0bad0000 	.word	0x0bad0000
    4b8c:	0000a72d 	.word	0x0000a72d
    4b90:	0000b3d0 	.word	0x0000b3d0
    4b94:	0000a2e8 	.word	0x0000a2e8

00004b98 <uarte_nrfx_configure>:
	return 0;
}

static int uarte_nrfx_configure(const struct device *dev,
				const struct uart_config *cfg)
{
    4b98:	b5f0      	push	{r4, r5, r6, r7, lr}
	struct uarte_nrfx_data *data = dev->data;
	nrf_uarte_config_t uarte_cfg;

#if defined(UARTE_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
    4b9a:	794b      	ldrb	r3, [r1, #5]
    4b9c:	2b01      	cmp	r3, #1
    4b9e:	d029      	beq.n	4bf4 <uarte_nrfx_configure+0x5c>
    4ba0:	2b03      	cmp	r3, #3
    4ba2:	d124      	bne.n	4bee <uarte_nrfx_configure+0x56>
	case UART_CFG_STOP_BITS_1:
		uarte_cfg.stop = NRF_UARTE_STOP_ONE;
		break;
	case UART_CFG_STOP_BITS_2:
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
    4ba4:	2710      	movs	r7, #16
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    4ba6:	798b      	ldrb	r3, [r1, #6]
    4ba8:	2b03      	cmp	r3, #3
    4baa:	d120      	bne.n	4bee <uarte_nrfx_configure+0x56>
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
    4bac:	79ce      	ldrb	r6, [r1, #7]
    4bae:	b10e      	cbz	r6, 4bb4 <uarte_nrfx_configure+0x1c>
    4bb0:	2e01      	cmp	r6, #1
    4bb2:	d11c      	bne.n	4bee <uarte_nrfx_configure+0x56>
	}

#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
    4bb4:	790a      	ldrb	r2, [r1, #4]
    4bb6:	2a01      	cmp	r2, #1
    4bb8:	d01e      	beq.n	4bf8 <uarte_nrfx_configure+0x60>
    4bba:	2a02      	cmp	r2, #2
    4bbc:	d020      	beq.n	4c00 <uarte_nrfx_configure+0x68>
    4bbe:	b9b2      	cbnz	r2, 4bee <uarte_nrfx_configure+0x56>
    4bc0:	4614      	mov	r4, r2
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
    4bc2:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    4bc4:	6845      	ldr	r5, [r0, #4]
	switch (baudrate) {
    4bc6:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    4bca:	f8d5 c000 	ldr.w	ip, [r5]
	switch (baudrate) {
    4bce:	d06e      	beq.n	4cae <uarte_nrfx_configure+0x116>
    4bd0:	d833      	bhi.n	4c3a <uarte_nrfx_configure+0xa2>
    4bd2:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    4bd6:	d06d      	beq.n	4cb4 <uarte_nrfx_configure+0x11c>
    4bd8:	d81c      	bhi.n	4c14 <uarte_nrfx_configure+0x7c>
    4bda:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    4bde:	d06b      	beq.n	4cb8 <uarte_nrfx_configure+0x120>
    4be0:	d810      	bhi.n	4c04 <uarte_nrfx_configure+0x6c>
    4be2:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    4be6:	d06a      	beq.n	4cbe <uarte_nrfx_configure+0x126>
    4be8:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    4bec:	d06a      	beq.n	4cc4 <uarte_nrfx_configure+0x12c>
		return -ENOTSUP;
    4bee:	f06f 0085 	mvn.w	r0, #133	; 0x85
    4bf2:	e05b      	b.n	4cac <uarte_nrfx_configure+0x114>
	switch (cfg->stop_bits) {
    4bf4:	2700      	movs	r7, #0
    4bf6:	e7d6      	b.n	4ba6 <uarte_nrfx_configure+0xe>
		uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_ODD;
    4bf8:	f44f 7480 	mov.w	r4, #256	; 0x100
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
    4bfc:	220e      	movs	r2, #14
    4bfe:	e7e0      	b.n	4bc2 <uarte_nrfx_configure+0x2a>
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
    4c00:	2400      	movs	r4, #0
    4c02:	e7fb      	b.n	4bfc <uarte_nrfx_configure+0x64>
	switch (baudrate) {
    4c04:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    4c08:	d05f      	beq.n	4cca <uarte_nrfx_configure+0x132>
    4c0a:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    4c0e:	d1ee      	bne.n	4bee <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    4c10:	4b38      	ldr	r3, [pc, #224]	; (4cf4 <uarte_nrfx_configure+0x15c>)
    4c12:	e03c      	b.n	4c8e <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    4c14:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    4c18:	d05a      	beq.n	4cd0 <uarte_nrfx_configure+0x138>
    4c1a:	d807      	bhi.n	4c2c <uarte_nrfx_configure+0x94>
    4c1c:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    4c20:	d058      	beq.n	4cd4 <uarte_nrfx_configure+0x13c>
    4c22:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    4c26:	d1e2      	bne.n	4bee <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    4c28:	4b33      	ldr	r3, [pc, #204]	; (4cf8 <uarte_nrfx_configure+0x160>)
    4c2a:	e030      	b.n	4c8e <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    4c2c:	f647 2512 	movw	r5, #31250	; 0x7a12
    4c30:	42ab      	cmp	r3, r5
    4c32:	d1dc      	bne.n	4bee <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    4c34:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    4c38:	e029      	b.n	4c8e <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    4c3a:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    4c3e:	d04b      	beq.n	4cd8 <uarte_nrfx_configure+0x140>
    4c40:	d813      	bhi.n	4c6a <uarte_nrfx_configure+0xd2>
    4c42:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    4c46:	d04a      	beq.n	4cde <uarte_nrfx_configure+0x146>
    4c48:	d809      	bhi.n	4c5e <uarte_nrfx_configure+0xc6>
    4c4a:	f64d 25c0 	movw	r5, #56000	; 0xdac0
    4c4e:	42ab      	cmp	r3, r5
    4c50:	d047      	beq.n	4ce2 <uarte_nrfx_configure+0x14a>
    4c52:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    4c56:	d1ca      	bne.n	4bee <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    4c58:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    4c5c:	e017      	b.n	4c8e <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    4c5e:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    4c62:	d1c4      	bne.n	4bee <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    4c64:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    4c68:	e011      	b.n	4c8e <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    4c6a:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    4c6e:	d03b      	beq.n	4ce8 <uarte_nrfx_configure+0x150>
    4c70:	d808      	bhi.n	4c84 <uarte_nrfx_configure+0xec>
    4c72:	4d22      	ldr	r5, [pc, #136]	; (4cfc <uarte_nrfx_configure+0x164>)
    4c74:	42ab      	cmp	r3, r5
    4c76:	d03a      	beq.n	4cee <uarte_nrfx_configure+0x156>
    4c78:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    4c7c:	d1b7      	bne.n	4bee <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    4c7e:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    4c82:	e004      	b.n	4c8e <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    4c84:	4d1e      	ldr	r5, [pc, #120]	; (4d00 <uarte_nrfx_configure+0x168>)
    4c86:	42ab      	cmp	r3, r5
    4c88:	d1b1      	bne.n	4bee <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    4c8a:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
	struct uarte_nrfx_data *data = dev->data;
    4c8e:	6905      	ldr	r5, [r0, #16]
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    4c90:	f8cc 3524 	str.w	r3, [ip, #1316]	; 0x524
	return config->uarte_regs;
    4c94:	6843      	ldr	r3, [r0, #4]
                    | (uint32_t)p_cfg->stop
    4c96:	433a      	orrs	r2, r7
    4c98:	681b      	ldr	r3, [r3, #0]
                    | (uint32_t)p_cfg->hwfc;
    4c9a:	4334      	orrs	r4, r6
    4c9c:	4322      	orrs	r2, r4
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    4c9e:	f8c3 256c 	str.w	r2, [r3, #1388]	; 0x56c
		return -ENOTSUP;
	}

	nrf_uarte_configure(get_uarte_instance(dev), &uarte_cfg);

	data->uart_config = *cfg;
    4ca2:	1d2b      	adds	r3, r5, #4
    4ca4:	c903      	ldmia	r1, {r0, r1}
    4ca6:	e883 0003 	stmia.w	r3, {r0, r1}

	return 0;
    4caa:	2000      	movs	r0, #0
}
    4cac:	bdf0      	pop	{r4, r5, r6, r7, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    4cae:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    4cb2:	e7ec      	b.n	4c8e <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    4cb4:	4b13      	ldr	r3, [pc, #76]	; (4d04 <uarte_nrfx_configure+0x16c>)
    4cb6:	e7ea      	b.n	4c8e <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    4cb8:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    4cbc:	e7e7      	b.n	4c8e <uarte_nrfx_configure+0xf6>
		nrf_baudrate = 0x00014000;
    4cbe:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    4cc2:	e7e4      	b.n	4c8e <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    4cc4:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    4cc8:	e7e1      	b.n	4c8e <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    4cca:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    4cce:	e7de      	b.n	4c8e <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    4cd0:	4b0d      	ldr	r3, [pc, #52]	; (4d08 <uarte_nrfx_configure+0x170>)
    4cd2:	e7dc      	b.n	4c8e <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    4cd4:	4b0d      	ldr	r3, [pc, #52]	; (4d0c <uarte_nrfx_configure+0x174>)
    4cd6:	e7da      	b.n	4c8e <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    4cd8:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    4cdc:	e7d7      	b.n	4c8e <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    4cde:	4b0c      	ldr	r3, [pc, #48]	; (4d10 <uarte_nrfx_configure+0x178>)
    4ce0:	e7d5      	b.n	4c8e <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    4ce2:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    4ce6:	e7d2      	b.n	4c8e <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    4ce8:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    4cec:	e7cf      	b.n	4c8e <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    4cee:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    4cf2:	e7cc      	b.n	4c8e <uarte_nrfx_configure+0xf6>
    4cf4:	0013b000 	.word	0x0013b000
    4cf8:	004ea000 	.word	0x004ea000
    4cfc:	0003d090 	.word	0x0003d090
    4d00:	000f4240 	.word	0x000f4240
    4d04:	00275000 	.word	0x00275000
    4d08:	0075c000 	.word	0x0075c000
    4d0c:	003af000 	.word	0x003af000
    4d10:	013a9000 	.word	0x013a9000

00004d14 <uarte_0_init>:
		(__attribute__((__section__(LINKER_DT_NODE_REGION_NAME(	       \
			DT_PHANDLE(UARTE(idx), memory_regions)))))),	       \
		())

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
    4d14:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    4d18:	4680      	mov	r8, r0
    4d1a:	b087      	sub	sp, #28
    4d1c:	2200      	movs	r2, #0
    4d1e:	2101      	movs	r1, #1
    4d20:	2008      	movs	r0, #8
    4d22:	f7fe fc1d 	bl	3560 <z_arm_irq_priority_set>
    4d26:	2008      	movs	r0, #8
    4d28:	f7fe fbea 	bl	3500 <arch_irq_enable>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    4d2c:	2100      	movs	r1, #0
	const struct uarte_nrfx_config *config = dev->config;
    4d2e:	f8d8 7004 	ldr.w	r7, [r8, #4]
	struct uarte_nrfx_data *data = dev->data;
    4d32:	f8d8 6010 	ldr.w	r6, [r8, #16]
	return config->uarte_regs;
    4d36:	683c      	ldr	r4, [r7, #0]
				      uint8_t id)
{
	int ret;
	const struct pinctrl_state *state;

	ret = pinctrl_lookup_state(config, id, &state);
    4d38:	466a      	mov	r2, sp
    4d3a:	f8c4 1500 	str.w	r1, [r4, #1280]	; 0x500
	data->dev = dev;
    4d3e:	f8c6 8000 	str.w	r8, [r6]
	err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
    4d42:	f8d7 900c 	ldr.w	r9, [r7, #12]
    4d46:	4648      	mov	r0, r9
    4d48:	f004 fd82 	bl	9850 <pinctrl_lookup_state>
	if (ret < 0) {
    4d4c:	1e05      	subs	r5, r0, #0
    4d4e:	db25      	blt.n	4d9c <uarte_0_init+0x88>
		return ret;
	}

	return pinctrl_apply_state_direct(config, state);
    4d50:	9b00      	ldr	r3, [sp, #0]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    4d52:	f8d9 2000 	ldr.w	r2, [r9]
    4d56:	7919      	ldrb	r1, [r3, #4]
    4d58:	6818      	ldr	r0, [r3, #0]
    4d5a:	f004 fd8c 	bl	9876 <pinctrl_configure_pins>
	if (err < 0) {
    4d5e:	1e05      	subs	r5, r0, #0
    4d60:	db1c      	blt.n	4d9c <uarte_0_init+0x88>
	err = uarte_nrfx_configure(dev, &data->uart_config);
    4d62:	4640      	mov	r0, r8
    4d64:	1d31      	adds	r1, r6, #4
    4d66:	f7ff ff17 	bl	4b98 <uarte_nrfx_configure>
	if (err) {
    4d6a:	4605      	mov	r5, r0
    4d6c:	b9b0      	cbnz	r0, 4d9c <uarte_0_init+0x88>
	    cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX) {
    4d6e:	687b      	ldr	r3, [r7, #4]
	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
    4d70:	0799      	lsls	r1, r3, #30
    4d72:	d533      	bpl.n	4ddc <uarte_0_init+0xc8>
	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    4d74:	f106 0018 	add.w	r0, r6, #24
    4d78:	f001 f80a 	bl	5d90 <nrfx_dppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    4d7c:	4b2b      	ldr	r3, [pc, #172]	; (4e2c <uarte_0_init+0x118>)
    4d7e:	4298      	cmp	r0, r3
    4d80:	d010      	beq.n	4da4 <uarte_0_init+0x90>
		LOG_ERR("Failed to allocate PPI Channel");
    4d82:	4b2b      	ldr	r3, [pc, #172]	; (4e30 <uarte_0_init+0x11c>)
    4d84:	9305      	str	r3, [sp, #20]
    4d86:	2302      	movs	r3, #2
    4d88:	9304      	str	r3, [sp, #16]
    4d8a:	462b      	mov	r3, r5
		return -EIO;
    4d8c:	f06f 0504 	mvn.w	r5, #4
    4d90:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    4d94:	4827      	ldr	r0, [pc, #156]	; (4e34 <uarte_0_init+0x120>)
    4d96:	aa04      	add	r2, sp, #16
    4d98:	f7fd fd46 	bl	2828 <z_impl_z_log_msg_static_create>
UART_NRF_UARTE_DEVICE(0);
    4d9c:	4628      	mov	r0, r5
    4d9e:	b007      	add	sp, #28
    4da0:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    4da4:	7e33      	ldrb	r3, [r6, #24]
    NRFX_ASSERT(tep);
    4da6:	f114 0f0c 	cmn.w	r4, #12
    *((volatile uint32_t *)(eep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
    4daa:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
    4dae:	f8c4 31a0 	str.w	r3, [r4, #416]	; 0x1a0
    NRFX_ASSERT(tep);
    4db2:	d10b      	bne.n	4dcc <uarte_0_init+0xb8>
    4db4:	4920      	ldr	r1, [pc, #128]	; (4e38 <uarte_0_init+0x124>)
    4db6:	4821      	ldr	r0, [pc, #132]	; (4e3c <uarte_0_init+0x128>)
    4db8:	f240 234e 	movw	r3, #590	; 0x24e
    4dbc:	4a20      	ldr	r2, [pc, #128]	; (4e40 <uarte_0_init+0x12c>)
    4dbe:	f004 fa72 	bl	92a6 <assert_print>
    4dc2:	f240 214e 	movw	r1, #590	; 0x24e
    4dc6:	481e      	ldr	r0, [pc, #120]	; (4e40 <uarte_0_init+0x12c>)
    4dc8:	f004 fa66 	bl	9298 <assert_post_action>
    *((volatile uint32_t *)(tep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
    4dcc:	f8c4 308c 	str.w	r3, [r4, #140]	; 0x8c
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    4dd0:	2301      	movs	r3, #1
    4dd2:	7e32      	ldrb	r2, [r6, #24]
    4dd4:	4093      	lsls	r3, r2
    p_reg->CHENSET = mask;
    4dd6:	4a1b      	ldr	r2, [pc, #108]	; (4e44 <uarte_0_init+0x130>)
    4dd8:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    4ddc:	2308      	movs	r3, #8
    4dde:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
		if (!cfg->disable_rx) {
    4de2:	7a3b      	ldrb	r3, [r7, #8]
    4de4:	b953      	cbnz	r3, 4dfc <uarte_0_init+0xe8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4de6:	f8c4 3110 	str.w	r3, [r4, #272]	; 0x110
    4dea:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    4dee:	6973      	ldr	r3, [r6, #20]
    4df0:	f8c4 3534 	str.w	r3, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    4df4:	2301      	movs	r3, #1
    4df6:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4dfa:	6023      	str	r3, [r4, #0]
	if (!(cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX)) {
    4dfc:	687b      	ldr	r3, [r7, #4]
    4dfe:	079a      	lsls	r2, r3, #30
    p_reg->INTENSET = mask;
    4e00:	bf5c      	itt	pl
    4e02:	f44f 7380 	movpl.w	r3, #256	; 0x100
    4e06:	f8c4 3304 	strpl.w	r3, [r4, #772]	; 0x304
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    4e0a:	687b      	ldr	r3, [r7, #4]
    4e0c:	06db      	lsls	r3, r3, #27
    4e0e:	bf44      	itt	mi
    4e10:	f44f 0380 	movmi.w	r3, #4194304	; 0x400000
    4e14:	f8c4 3304 	strmi.w	r3, [r4, #772]	; 0x304
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    4e18:	6933      	ldr	r3, [r6, #16]
    4e1a:	f8c4 3544 	str.w	r3, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    4e1e:	2300      	movs	r3, #0
    4e20:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4e24:	2301      	movs	r3, #1
    4e26:	60a3      	str	r3, [r4, #8]
    4e28:	60e3      	str	r3, [r4, #12]
UART_NRF_UARTE_DEVICE(0);
    4e2a:	e7b7      	b.n	4d9c <uarte_0_init+0x88>
    4e2c:	0bad0000 	.word	0x0bad0000
    4e30:	0000b414 	.word	0x0000b414
    4e34:	0000a004 	.word	0x0000a004
    4e38:	0000a6c6 	.word	0x0000a6c6
    4e3c:	0000a2e8 	.word	0x0000a2e8
    4e40:	0000a68e 	.word	0x0000a68e
    4e44:	50017000 	.word	0x50017000

00004e48 <uarte_nrfx_poll_out>:
{
    4e48:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4e4a:	4604      	mov	r4, r0
    4e4c:	460d      	mov	r5, r1
	struct uarte_nrfx_data *data = dev->data;
    4e4e:	6907      	ldr	r7, [r0, #16]
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    4e50:	f004 fe96 	bl	9b80 <k_is_in_isr>
    4e54:	b9b0      	cbnz	r0, 4e84 <uarte_nrfx_poll_out+0x3c>
	return !z_sys_post_kernel;
    4e56:	4b2e      	ldr	r3, [pc, #184]	; (4f10 <uarte_nrfx_poll_out+0xc8>)
    4e58:	781b      	ldrb	r3, [r3, #0]
    4e5a:	b19b      	cbz	r3, 4e84 <uarte_nrfx_poll_out+0x3c>
{
    4e5c:	2664      	movs	r6, #100	; 0x64
		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    4e5e:	6860      	ldr	r0, [r4, #4]
    4e60:	f004 fc9c 	bl	979c <is_tx_ready.isra.0>
    4e64:	bb00      	cbnz	r0, 4ea8 <uarte_nrfx_poll_out+0x60>
    4e66:	2001      	movs	r0, #1
    4e68:	f004 fddb 	bl	9a22 <nrfx_busy_wait>
    4e6c:	3e01      	subs	r6, #1
    4e6e:	d1f6      	bne.n	4e5e <uarte_nrfx_poll_out+0x16>
    4e70:	2100      	movs	r1, #0
    4e72:	2021      	movs	r0, #33	; 0x21
    4e74:	f003 fa30 	bl	82d8 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    4e78:	e7f0      	b.n	4e5c <uarte_nrfx_poll_out+0x14>
	__asm__ volatile(
    4e7a:	f386 8811 	msr	BASEPRI, r6
    4e7e:	f3bf 8f6f 	isb	sy
}
    4e82:	e7f5      	b.n	4e70 <uarte_nrfx_poll_out+0x28>
	__asm__ volatile(
    4e84:	f04f 0320 	mov.w	r3, #32
    4e88:	f3ef 8611 	mrs	r6, BASEPRI
    4e8c:	f383 8812 	msr	BASEPRI_MAX, r3
    4e90:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    4e94:	6860      	ldr	r0, [r4, #4]
    4e96:	4631      	mov	r1, r6
    4e98:	f004 fc80 	bl	979c <is_tx_ready.isra.0>
    4e9c:	b990      	cbnz	r0, 4ec4 <uarte_nrfx_poll_out+0x7c>
	__asm__ volatile(
    4e9e:	f386 8811 	msr	BASEPRI, r6
    4ea2:	f3bf 8f6f 	isb	sy
}
    4ea6:	e7ed      	b.n	4e84 <uarte_nrfx_poll_out+0x3c>
	__asm__ volatile(
    4ea8:	f04f 0320 	mov.w	r3, #32
    4eac:	f3ef 8611 	mrs	r6, BASEPRI
    4eb0:	f383 8812 	msr	BASEPRI_MAX, r3
    4eb4:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    4eb8:	6860      	ldr	r0, [r4, #4]
    4eba:	4631      	mov	r1, r6
    4ebc:	f004 fc6e 	bl	979c <is_tx_ready.isra.0>
    4ec0:	2800      	cmp	r0, #0
    4ec2:	d0da      	beq.n	4e7a <uarte_nrfx_poll_out+0x32>
	*data->char_out = c;
    4ec4:	693b      	ldr	r3, [r7, #16]
    4ec6:	701d      	strb	r5, [r3, #0]
	const struct uarte_nrfx_config *config = dev->config;
    4ec8:	6862      	ldr	r2, [r4, #4]
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    4eca:	6938      	ldr	r0, [r7, #16]
	return config->uarte_regs;
    4ecc:	6813      	ldr	r3, [r2, #0]
    4ece:	f8c3 0544 	str.w	r0, [r3, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    4ed2:	2001      	movs	r0, #1
    4ed4:	f8c3 0548 	str.w	r0, [r3, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4ed8:	2000      	movs	r0, #0
    4eda:	f8c3 0120 	str.w	r0, [r3, #288]	; 0x120
    4ede:	f8d3 5120 	ldr.w	r5, [r3, #288]	; 0x120
    4ee2:	f8c3 0158 	str.w	r0, [r3, #344]	; 0x158
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    4ee6:	6852      	ldr	r2, [r2, #4]
    4ee8:	f8d3 0158 	ldr.w	r0, [r3, #344]	; 0x158
    4eec:	06d2      	lsls	r2, r2, #27
    4eee:	d508      	bpl.n	4f02 <uarte_nrfx_poll_out+0xba>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    4ef0:	2008      	movs	r0, #8
	return config->uarte_regs;
    4ef2:	6862      	ldr	r2, [r4, #4]
    4ef4:	6812      	ldr	r2, [r2, #0]
    4ef6:	f8c2 0500 	str.w	r0, [r2, #1280]	; 0x500
    p_reg->INTENSET = mask;
    4efa:	f44f 0280 	mov.w	r2, #4194304	; 0x400000
    4efe:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4f02:	2201      	movs	r2, #1
    4f04:	609a      	str	r2, [r3, #8]
	__asm__ volatile(
    4f06:	f381 8811 	msr	BASEPRI, r1
    4f0a:	f3bf 8f6f 	isb	sy
}
    4f0e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    4f10:	200010ce 	.word	0x200010ce

00004f14 <compare_int_lock>:
#endif
}

static bool compare_int_lock(int32_t chan)
{
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    4f14:	2301      	movs	r3, #1
    4f16:	4083      	lsls	r3, r0
{
    4f18:	b570      	push	{r4, r5, r6, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    4f1a:	43dc      	mvns	r4, r3
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    4f1c:	4a0b      	ldr	r2, [pc, #44]	; (4f4c <compare_int_lock+0x38>)
    4f1e:	e8d2 1fef 	ldaex	r1, [r2]
    4f22:	ea01 0504 	and.w	r5, r1, r4
    4f26:	e8c2 5fe6 	stlex	r6, r5, [r2]
    4f2a:	2e00      	cmp	r6, #0
    4f2c:	d1f7      	bne.n	4f1e <compare_int_lock+0xa>

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    4f2e:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    4f32:	4082      	lsls	r2, r0
    p_reg->INTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->INTENCLR = mask;
    4f34:	4806      	ldr	r0, [pc, #24]	; (4f50 <compare_int_lock+0x3c>)
    4f36:	f8c0 2308 	str.w	r2, [r0, #776]	; 0x308
    4f3a:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    4f3e:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    4f42:	420b      	tst	r3, r1
}
    4f44:	bf14      	ite	ne
    4f46:	2001      	movne	r0, #1
    4f48:	2000      	moveq	r0, #0
    4f4a:	bd70      	pop	{r4, r5, r6, pc}
    4f4c:	20000dfc 	.word	0x20000dfc
    4f50:	50015000 	.word	0x50015000

00004f54 <sys_clock_timeout_handler>:
}

static void sys_clock_timeout_handler(int32_t chan,
				      uint64_t expire_time,
				      void *user_data)
{
    4f54:	b470      	push	{r4, r5, r6}
	uint32_t cc_value = absolute_time_to_cc(expire_time);
	uint32_t dticks = (uint32_t)(expire_time - last_count) / CYC_PER_TICK;
    4f56:	490e      	ldr	r1, [pc, #56]	; (4f90 <sys_clock_timeout_handler+0x3c>)
	return absolute_time & COUNTER_MAX;
    4f58:	f022 467f 	bic.w	r6, r2, #4278190080	; 0xff000000
	uint32_t dticks = (uint32_t)(expire_time - last_count) / CYC_PER_TICK;
    4f5c:	e9d1 3400 	ldrd	r3, r4, [r1]
    4f60:	1ad0      	subs	r0, r2, r3

	last_count += dticks * CYC_PER_TICK;
    4f62:	18c3      	adds	r3, r0, r3
    4f64:	f144 0400 	adc.w	r4, r4, #0
    4f68:	e9c1 3400 	strd	r3, r4, [r1]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    4f6c:	f5a6 1300 	sub.w	r3, r6, #2097152	; 0x200000
	if (in_anchor_range(cc_value)) {
    4f70:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    4f74:	d209      	bcs.n	4f8a <sys_clock_timeout_handler+0x36>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    4f76:	4b07      	ldr	r3, [pc, #28]	; (4f94 <sys_clock_timeout_handler+0x40>)
    4f78:	681b      	ldr	r3, [r3, #0]
    4f7a:	0a1a      	lsrs	r2, r3, #8
    4f7c:	061b      	lsls	r3, r3, #24
    4f7e:	199c      	adds	r4, r3, r6
    4f80:	4b05      	ldr	r3, [pc, #20]	; (4f98 <sys_clock_timeout_handler+0x44>)
    4f82:	f142 0500 	adc.w	r5, r2, #0
    4f86:	e9c3 4500 	strd	r4, r5, [r3]
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(dticks);
}
    4f8a:	bc70      	pop	{r4, r5, r6}
	sys_clock_announce(dticks);
    4f8c:	f003 bcb6 	b.w	88fc <sys_clock_announce>
    4f90:	20000650 	.word	0x20000650
    4f94:	20000e00 	.word	0x20000e00
    4f98:	20000658 	.word	0x20000658

00004f9c <compare_int_unlock>:
	if (key) {
    4f9c:	b1d9      	cbz	r1, 4fd6 <compare_int_unlock+0x3a>
		atomic_or(&int_mask, BIT(chan));
    4f9e:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    4fa0:	4a0d      	ldr	r2, [pc, #52]	; (4fd8 <compare_int_unlock+0x3c>)
    4fa2:	4083      	lsls	r3, r0
    4fa4:	e8d2 cfef 	ldaex	ip, [r2]
    4fa8:	ea4c 0c03 	orr.w	ip, ip, r3
    4fac:	e8c2 cfe1 	stlex	r1, ip, [r2]
    4fb0:	2900      	cmp	r1, #0
    4fb2:	d1f7      	bne.n	4fa4 <compare_int_unlock+0x8>
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    4fb4:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    p_reg->INTENSET = mask;
    4fb8:	4a08      	ldr	r2, [pc, #32]	; (4fdc <compare_int_unlock+0x40>)
    4fba:	4083      	lsls	r3, r0
    4fbc:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    4fc0:	4b07      	ldr	r3, [pc, #28]	; (4fe0 <compare_int_unlock+0x44>)
    4fc2:	e8d3 3faf 	lda	r3, [r3]
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    4fc6:	40c3      	lsrs	r3, r0
    4fc8:	07db      	lsls	r3, r3, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    4fca:	bf42      	ittt	mi
    4fcc:	f44f 1200 	movmi.w	r2, #2097152	; 0x200000
    4fd0:	4b04      	ldrmi	r3, [pc, #16]	; (4fe4 <compare_int_unlock+0x48>)
    4fd2:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
}
    4fd6:	4770      	bx	lr
    4fd8:	20000dfc 	.word	0x20000dfc
    4fdc:	50015000 	.word	0x50015000
    4fe0:	20000df4 	.word	0x20000df4
    4fe4:	e000e100 	.word	0xe000e100

00004fe8 <z_nrf_rtc_timer_compare_evt_address_get>:
	__ASSERT_NO_MSG(chan >= 0 && chan < CHAN_COUNT);
    4fe8:	2801      	cmp	r0, #1
{
    4fea:	b508      	push	{r3, lr}
	__ASSERT_NO_MSG(chan >= 0 && chan < CHAN_COUNT);
    4fec:	d909      	bls.n	5002 <z_nrf_rtc_timer_compare_evt_address_get+0x1a>
    4fee:	4907      	ldr	r1, [pc, #28]	; (500c <z_nrf_rtc_timer_compare_evt_address_get+0x24>)
    4ff0:	4807      	ldr	r0, [pc, #28]	; (5010 <z_nrf_rtc_timer_compare_evt_address_get+0x28>)
    4ff2:	237d      	movs	r3, #125	; 0x7d
    4ff4:	4a07      	ldr	r2, [pc, #28]	; (5014 <z_nrf_rtc_timer_compare_evt_address_get+0x2c>)
    4ff6:	f004 f956 	bl	92a6 <assert_print>
    4ffa:	217d      	movs	r1, #125	; 0x7d
    4ffc:	4805      	ldr	r0, [pc, #20]	; (5014 <z_nrf_rtc_timer_compare_evt_address_get+0x2c>)
    4ffe:	f004 f94b 	bl	9298 <assert_post_action>
    p_reg->EVTENCLR = mask;
}

NRF_STATIC_INLINE nrf_rtc_event_t nrf_rtc_compare_event_get(uint8_t index)
{
    return (nrf_rtc_event_t)NRFX_OFFSETOF(NRF_RTC_Type, EVENTS_COMPARE[index]);
    5002:	0083      	lsls	r3, r0, #2
}
    5004:	4804      	ldr	r0, [pc, #16]	; (5018 <z_nrf_rtc_timer_compare_evt_address_get+0x30>)
    5006:	4418      	add	r0, r3
    5008:	bd08      	pop	{r3, pc}
    500a:	bf00      	nop
    500c:	0000b47e 	.word	0x0000b47e
    5010:	0000a2e8 	.word	0x0000a2e8
    5014:	0000b44d 	.word	0x0000b44d
    5018:	50015140 	.word	0x50015140

0000501c <z_nrf_rtc_timer_capture_task_address_get>:
	__ASSERT_NO_MSG(chan >= 0 && chan < CHAN_COUNT);
    501c:	2801      	cmp	r0, #1
{
    501e:	b508      	push	{r3, lr}
	__ASSERT_NO_MSG(chan >= 0 && chan < CHAN_COUNT);
    5020:	d909      	bls.n	5036 <z_nrf_rtc_timer_capture_task_address_get+0x1a>
    5022:	4907      	ldr	r1, [pc, #28]	; (5040 <z_nrf_rtc_timer_capture_task_address_get+0x24>)
    5024:	4807      	ldr	r0, [pc, #28]	; (5044 <z_nrf_rtc_timer_capture_task_address_get+0x28>)
    5026:	2384      	movs	r3, #132	; 0x84
    5028:	4a07      	ldr	r2, [pc, #28]	; (5048 <z_nrf_rtc_timer_capture_task_address_get+0x2c>)
    502a:	f004 f93c 	bl	92a6 <assert_print>
    502e:	2184      	movs	r1, #132	; 0x84
    5030:	4805      	ldr	r0, [pc, #20]	; (5048 <z_nrf_rtc_timer_capture_task_address_get+0x2c>)
    5032:	f004 f931 	bl	9298 <assert_post_action>
	return nrf_rtc_task_address_get(RTC, task);
    5036:	2800      	cmp	r0, #0
}
    5038:	4804      	ldr	r0, [pc, #16]	; (504c <z_nrf_rtc_timer_capture_task_address_get+0x30>)
    503a:	bf08      	it	eq
    503c:	2000      	moveq	r0, #0
    503e:	bd08      	pop	{r3, pc}
    5040:	0000b47e 	.word	0x0000b47e
    5044:	0000a2e8 	.word	0x0000a2e8
    5048:	0000b44d 	.word	0x0000b44d
    504c:	50015044 	.word	0x50015044

00005050 <z_nrf_rtc_timer_compare_read>:
	__ASSERT_NO_MSG(chan >= 0 && chan < CHAN_COUNT);
    5050:	2801      	cmp	r0, #1
{
    5052:	b508      	push	{r3, lr}
	__ASSERT_NO_MSG(chan >= 0 && chan < CHAN_COUNT);
    5054:	d909      	bls.n	506a <z_nrf_rtc_timer_compare_read+0x1a>
    5056:	4908      	ldr	r1, [pc, #32]	; (5078 <z_nrf_rtc_timer_compare_read+0x28>)
    5058:	4808      	ldr	r0, [pc, #32]	; (507c <z_nrf_rtc_timer_compare_read+0x2c>)
    505a:	23ba      	movs	r3, #186	; 0xba
    505c:	4a08      	ldr	r2, [pc, #32]	; (5080 <z_nrf_rtc_timer_compare_read+0x30>)
    505e:	f004 f922 	bl	92a6 <assert_print>
    5062:	21ba      	movs	r1, #186	; 0xba
    5064:	4806      	ldr	r0, [pc, #24]	; (5080 <z_nrf_rtc_timer_compare_read+0x30>)
    5066:	f004 f917 	bl	9298 <assert_post_action>
    return p_reg->CC[ch];
    506a:	4b06      	ldr	r3, [pc, #24]	; (5084 <z_nrf_rtc_timer_compare_read+0x34>)
    506c:	f500 70a8 	add.w	r0, r0, #336	; 0x150
    5070:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
}
    5074:	bd08      	pop	{r3, pc}
    5076:	bf00      	nop
    5078:	0000b47e 	.word	0x0000b47e
    507c:	0000a2e8 	.word	0x0000a2e8
    5080:	0000b44d 	.word	0x0000b44d
    5084:	50015000 	.word	0x50015000

00005088 <z_nrf_rtc_timer_read>:
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    5088:	4b0d      	ldr	r3, [pc, #52]	; (50c0 <z_nrf_rtc_timer_read+0x38>)
    508a:	6818      	ldr	r0, [r3, #0]
    508c:	0a01      	lsrs	r1, r0, #8
    508e:	0600      	lsls	r0, r0, #24
  __ASM volatile ("dmb 0xF":::"memory");
    5090:	f3bf 8f5f 	dmb	sy
     return p_reg->COUNTER;
    5094:	4b0b      	ldr	r3, [pc, #44]	; (50c4 <z_nrf_rtc_timer_read+0x3c>)
    5096:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	val += cntr;
    509a:	1818      	adds	r0, r3, r0
    509c:	f141 0100 	adc.w	r1, r1, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    50a0:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    50a4:	d20a      	bcs.n	50bc <z_nrf_rtc_timer_read+0x34>
		if (val < anchor) {
    50a6:	4b08      	ldr	r3, [pc, #32]	; (50c8 <z_nrf_rtc_timer_read+0x40>)
    50a8:	e9d3 2300 	ldrd	r2, r3, [r3]
    50ac:	4290      	cmp	r0, r2
    50ae:	eb71 0303 	sbcs.w	r3, r1, r3
    50b2:	d203      	bcs.n	50bc <z_nrf_rtc_timer_read+0x34>
			val += COUNTER_SPAN;
    50b4:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    50b8:	f141 0100 	adc.w	r1, r1, #0
}
    50bc:	4770      	bx	lr
    50be:	bf00      	nop
    50c0:	20000e00 	.word	0x20000e00
    50c4:	50015000 	.word	0x50015000
    50c8:	20000658 	.word	0x20000658

000050cc <compare_set>:
{
    50cc:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    50d0:	4616      	mov	r6, r2
    50d2:	461f      	mov	r7, r3
    50d4:	4604      	mov	r4, r0
	key = compare_int_lock(chan);
    50d6:	f7ff ff1d 	bl	4f14 <compare_int_lock>
    50da:	9000      	str	r0, [sp, #0]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    50dc:	f7ff ffd4 	bl	5088 <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    50e0:	42b0      	cmp	r0, r6
    50e2:	eb71 0307 	sbcs.w	r3, r1, r7
    50e6:	d250      	bcs.n	518a <compare_set+0xbe>
		if (target_time - curr_time > COUNTER_HALF_SPAN) {
    50e8:	4b38      	ldr	r3, [pc, #224]	; (51cc <compare_set+0x100>)
    50ea:	1a30      	subs	r0, r6, r0
    50ec:	eb67 0101 	sbc.w	r1, r7, r1
    50f0:	4298      	cmp	r0, r3
    50f2:	f171 0100 	sbcs.w	r1, r1, #0
    50f6:	d265      	bcs.n	51c4 <compare_set+0xf8>
		if (target_time != cc_data[chan].target_time) {
    50f8:	4b35      	ldr	r3, [pc, #212]	; (51d0 <compare_set+0x104>)
    50fa:	eb03 1304 	add.w	r3, r3, r4, lsl #4
    50fe:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
    5102:	429f      	cmp	r7, r3
    5104:	bf08      	it	eq
    5106:	4296      	cmpeq	r6, r2
    5108:	d049      	beq.n	519e <compare_set+0xd2>
	nrf_rtc_event_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    510a:	f44f 3980 	mov.w	r9, #65536	; 0x10000
    p_reg->EVTENCLR = mask;
    510e:	4931      	ldr	r1, [pc, #196]	; (51d4 <compare_set+0x108>)
    5110:	fa09 f904 	lsl.w	r9, r9, r4
	event_clear(chan);
    5114:	4620      	mov	r0, r4
	return absolute_time & COUNTER_MAX;
    5116:	f026 4b7f 	bic.w	fp, r6, #4278190080	; 0xff000000
    511a:	f8c1 9348 	str.w	r9, [r1, #840]	; 0x348
	event_clear(chan);
    511e:	f004 fb87 	bl	9830 <event_clear>
	uint32_t cc_inc = MIN_CYCLES_FROM_NOW;
    5122:	f04f 0a03 	mov.w	sl, #3
	uint32_t cc_val = req_cc;
    5126:	4658      	mov	r0, fp
	return nrf_rtc_event_check(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    5128:	f104 0550 	add.w	r5, r4, #80	; 0x50
    512c:	00ad      	lsls	r5, r5, #2
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    512e:	b2ad      	uxth	r5, r5
    5130:	f105 2550 	add.w	r5, r5, #1342197760	; 0x50005000
    p_reg->CC[ch] = cc_val;
    5134:	f504 73a8 	add.w	r3, r4, #336	; 0x150
		if (counter_sub(cc_val, now + MIN_CYCLES_FROM_NOW) >
    5138:	4a27      	ldr	r2, [pc, #156]	; (51d8 <compare_set+0x10c>)
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    513a:	f505 3580 	add.w	r5, r5, #65536	; 0x10000
    p_reg->CC[ch] = cc_val;
    513e:	9301      	str	r3, [sp, #4]
    5140:	f8dd c004 	ldr.w	ip, [sp, #4]
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    5144:	f020 437f 	bic.w	r3, r0, #4278190080	; 0xff000000
    5148:	f841 302c 	str.w	r3, [r1, ip, lsl #2]
    p_reg->EVTENSET = mask;
    514c:	f8c1 9344 	str.w	r9, [r1, #836]	; 0x344
     return p_reg->COUNTER;
    5150:	f8d1 8504 	ldr.w	r8, [r1, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    5154:	eba0 0008 	sub.w	r0, r0, r8
    5158:	3803      	subs	r0, #3
    515a:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
		if (counter_sub(cc_val, now + MIN_CYCLES_FROM_NOW) >
    515e:	4290      	cmp	r0, r2
    5160:	d91d      	bls.n	519e <compare_set+0xd2>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5162:	6828      	ldr	r0, [r5, #0]
			if (event_check(chan)) {
    5164:	b160      	cbz	r0, 5180 <compare_set+0xb4>
     return p_reg->COUNTER;
    5166:	f8d1 8504 	ldr.w	r8, [r1, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    516a:	eba8 000b 	sub.w	r0, r8, fp
    516e:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
				if (counter_sub(now, req_cc) > COUNTER_HALF_SPAN) {
    5172:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    5176:	d912      	bls.n	519e <compare_set+0xd2>
					event_clear(chan);
    5178:	4620      	mov	r0, r4
    517a:	f004 fb59 	bl	9830 <event_clear>
    517e:	4a16      	ldr	r2, [pc, #88]	; (51d8 <compare_set+0x10c>)
			cc_val = now + cc_inc;
    5180:	eb0a 0008 	add.w	r0, sl, r8
			cc_inc++;
    5184:	f10a 0a01 	add.w	sl, sl, #1
	for (;;) {
    5188:	e7da      	b.n	5140 <compare_set+0x74>
		atomic_or(&force_isr_mask, BIT(chan));
    518a:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    518c:	4a13      	ldr	r2, [pc, #76]	; (51dc <compare_set+0x110>)
    518e:	40a3      	lsls	r3, r4
    5190:	e8d2 0fef 	ldaex	r0, [r2]
    5194:	4318      	orrs	r0, r3
    5196:	e8c2 0fe1 	stlex	r1, r0, [r2]
    519a:	2900      	cmp	r1, #0
    519c:	d1f8      	bne.n	5190 <compare_set+0xc4>
	return ret;
    519e:	2500      	movs	r5, #0
	cc_data[chan].target_time = target_time;
    51a0:	490b      	ldr	r1, [pc, #44]	; (51d0 <compare_set+0x104>)
	cc_data[chan].callback = handler;
    51a2:	980c      	ldr	r0, [sp, #48]	; 0x30
	cc_data[chan].target_time = target_time;
    51a4:	0123      	lsls	r3, r4, #4
    51a6:	eb01 1204 	add.w	r2, r1, r4, lsl #4
	cc_data[chan].callback = handler;
    51aa:	50c8      	str	r0, [r1, r3]
	cc_data[chan].target_time = target_time;
    51ac:	e9c2 6702 	strd	r6, r7, [r2, #8]
	cc_data[chan].user_context = user_data;
    51b0:	9b0d      	ldr	r3, [sp, #52]	; 0x34
    51b2:	6053      	str	r3, [r2, #4]
	compare_int_unlock(chan, key);
    51b4:	4620      	mov	r0, r4
    51b6:	9900      	ldr	r1, [sp, #0]
    51b8:	f7ff fef0 	bl	4f9c <compare_int_unlock>
}
    51bc:	4628      	mov	r0, r5
    51be:	b003      	add	sp, #12
    51c0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			return -EINVAL;
    51c4:	f06f 0515 	mvn.w	r5, #21
    51c8:	e7f4      	b.n	51b4 <compare_set+0xe8>
    51ca:	bf00      	nop
    51cc:	00800001 	.word	0x00800001
    51d0:	20000630 	.word	0x20000630
    51d4:	50015000 	.word	0x50015000
    51d8:	007ffffd 	.word	0x007ffffd
    51dc:	20000df4 	.word	0x20000df4

000051e0 <z_nrf_rtc_timer_set>:
	__ASSERT_NO_MSG(chan > 0 && chan < CHAN_COUNT);
    51e0:	2801      	cmp	r0, #1
{
    51e2:	b510      	push	{r4, lr}
	__ASSERT_NO_MSG(chan > 0 && chan < CHAN_COUNT);
    51e4:	d00b      	beq.n	51fe <z_nrf_rtc_timer_set+0x1e>
    51e6:	4908      	ldr	r1, [pc, #32]	; (5208 <z_nrf_rtc_timer_set+0x28>)
    51e8:	4808      	ldr	r0, [pc, #32]	; (520c <z_nrf_rtc_timer_set+0x2c>)
    51ea:	f44f 73b6 	mov.w	r3, #364	; 0x16c
    51ee:	4a08      	ldr	r2, [pc, #32]	; (5210 <z_nrf_rtc_timer_set+0x30>)
    51f0:	f004 f859 	bl	92a6 <assert_print>
    51f4:	f44f 71b6 	mov.w	r1, #364	; 0x16c
    51f8:	4805      	ldr	r0, [pc, #20]	; (5210 <z_nrf_rtc_timer_set+0x30>)
    51fa:	f004 f84d 	bl	9298 <assert_post_action>
}
    51fe:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	return compare_set(chan, target_time, handler, user_data);
    5202:	f7ff bf63 	b.w	50cc <compare_set>
    5206:	bf00      	nop
    5208:	0000b49a 	.word	0x0000b49a
    520c:	0000a2e8 	.word	0x0000a2e8
    5210:	0000b44d 	.word	0x0000b44d

00005214 <sys_clock_driver_init>:
{
	return (uint32_t)z_nrf_rtc_timer_read();
}

static int sys_clock_driver_init(const struct device *dev)
{
    5214:	b573      	push	{r0, r1, r4, r5, r6, lr}
    p_reg->INTENSET = mask;
    5216:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    p_reg->PRESCALER = val;
    521a:	2500      	movs	r5, #0
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    521c:	f04f 30ff 	mov.w	r0, #4294967295
    5220:	f04f 31ff 	mov.w	r1, #4294967295
    5224:	4c19      	ldr	r4, [pc, #100]	; (528c <sys_clock_driver_init+0x78>)
    5226:	4b1a      	ldr	r3, [pc, #104]	; (5290 <sys_clock_driver_init+0x7c>)
    5228:	f8c4 5508 	str.w	r5, [r4, #1288]	; 0x508
    522c:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    5230:	f8c4 2304 	str.w	r2, [r4, #772]	; 0x304
    5234:	e9c3 0106 	strd	r0, r1, [r3, #24]
    5238:	f44f 3300 	mov.w	r3, #131072	; 0x20000
    523c:	2602      	movs	r6, #2
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    523e:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
    5242:	f8c4 3304 	str.w	r3, [r4, #772]	; 0x304
    5246:	4b13      	ldr	r3, [pc, #76]	; (5294 <sys_clock_driver_init+0x80>)

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    5248:	2101      	movs	r1, #1
    524a:	f8c4 6304 	str.w	r6, [r4, #772]	; 0x304
    524e:	2015      	movs	r0, #21
    5250:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    5254:	462a      	mov	r2, r5
    5256:	f7fe f983 	bl	3560 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    525a:	2015      	movs	r0, #21
    525c:	f7fe f950 	bl	3500 <arch_irq_enable>
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    5260:	2301      	movs	r3, #1

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    5262:	2203      	movs	r2, #3
    5264:	60a3      	str	r3, [r4, #8]
    5266:	6023      	str	r3, [r4, #0]
    5268:	4b0b      	ldr	r3, [pc, #44]	; (5298 <sys_clock_driver_init+0x84>)
	}

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
		MAX_CYCLES : CYC_PER_TICK;

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    526a:	4628      	mov	r0, r5
	int_mask = BIT_MASK(CHAN_COUNT);
    526c:	601a      	str	r2, [r3, #0]
		alloc_mask = BIT_MASK(EXT_CHAN_COUNT) << 1;
    526e:	4b0b      	ldr	r3, [pc, #44]	; (529c <sys_clock_driver_init+0x88>)
	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    5270:	4a0b      	ldr	r2, [pc, #44]	; (52a0 <sys_clock_driver_init+0x8c>)
		alloc_mask = BIT_MASK(EXT_CHAN_COUNT) << 1;
    5272:	601e      	str	r6, [r3, #0]
	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    5274:	4b0b      	ldr	r3, [pc, #44]	; (52a4 <sys_clock_driver_init+0x90>)
    5276:	9501      	str	r5, [sp, #4]
    5278:	9300      	str	r3, [sp, #0]
    527a:	2300      	movs	r3, #0
    527c:	f7ff ff26 	bl	50cc <compare_set>

	z_nrf_clock_control_lf_on(mode);
    5280:	4630      	mov	r0, r6
    5282:	f7ff f9e1 	bl	4648 <z_nrf_clock_control_lf_on>

	return 0;
}
    5286:	4628      	mov	r0, r5
    5288:	b002      	add	sp, #8
    528a:	bd70      	pop	{r4, r5, r6, pc}
    528c:	50015000 	.word	0x50015000
    5290:	20000630 	.word	0x20000630
    5294:	e000e100 	.word	0xe000e100
    5298:	20000dfc 	.word	0x20000dfc
    529c:	20000df8 	.word	0x20000df8
    52a0:	007fffff 	.word	0x007fffff
    52a4:	00004f55 	.word	0x00004f55

000052a8 <rtc_nrf_isr>:
{
    52a8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    return p_reg->INTENSET & mask;
    52ac:	4b39      	ldr	r3, [pc, #228]	; (5394 <rtc_nrf_isr+0xec>)
    52ae:	b085      	sub	sp, #20
    52b0:	f8d3 2304 	ldr.w	r2, [r3, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    52b4:	0792      	lsls	r2, r2, #30
    52b6:	d50b      	bpl.n	52d0 <rtc_nrf_isr+0x28>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    52b8:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    52bc:	b142      	cbz	r2, 52d0 <rtc_nrf_isr+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    52be:	2200      	movs	r2, #0
    52c0:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
		overflow_cnt++;
    52c4:	4a34      	ldr	r2, [pc, #208]	; (5398 <rtc_nrf_isr+0xf0>)
    52c6:	f8d3 3104 	ldr.w	r3, [r3, #260]	; 0x104
    52ca:	6813      	ldr	r3, [r2, #0]
    52cc:	3301      	adds	r3, #1
    52ce:	6013      	str	r3, [r2, #0]
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    52d0:	4d32      	ldr	r5, [pc, #200]	; (539c <rtc_nrf_isr+0xf4>)
    52d2:	2400      	movs	r4, #0
    52d4:	46a8      	mov	r8, r5
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    52d6:	f44f 3680 	mov.w	r6, #65536	; 0x10000
    return p_reg->INTENSET & mask;
    52da:	4f2e      	ldr	r7, [pc, #184]	; (5394 <rtc_nrf_isr+0xec>)
    52dc:	f8d7 3304 	ldr.w	r3, [r7, #772]	; 0x304
    52e0:	fa06 f904 	lsl.w	r9, r6, r4
    52e4:	ea19 0f03 	tst.w	r9, r3
    52e8:	d02e      	beq.n	5348 <rtc_nrf_isr+0xa0>
		if ((atomic_and(&force_isr_mask, ~BIT(chan)) & BIT(chan)) ||
    52ea:	2301      	movs	r3, #1
    52ec:	40a3      	lsls	r3, r4
    52ee:	43db      	mvns	r3, r3
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    52f0:	492b      	ldr	r1, [pc, #172]	; (53a0 <rtc_nrf_isr+0xf8>)
    52f2:	e8d1 2fef 	ldaex	r2, [r1]
    52f6:	ea02 0003 	and.w	r0, r2, r3
    52fa:	e8c1 0fec 	stlex	ip, r0, [r1]
    52fe:	f1bc 0f00 	cmp.w	ip, #0
    5302:	d1f6      	bne.n	52f2 <rtc_nrf_isr+0x4a>
    5304:	fa22 f304 	lsr.w	r3, r2, r4
    5308:	07db      	lsls	r3, r3, #31
    530a:	d403      	bmi.n	5314 <rtc_nrf_isr+0x6c>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    530c:	4b25      	ldr	r3, [pc, #148]	; (53a4 <rtc_nrf_isr+0xfc>)
    530e:	f853 3024 	ldr.w	r3, [r3, r4, lsl #2]
    5312:	b1cb      	cbz	r3, 5348 <rtc_nrf_isr+0xa0>
			event_clear(chan);
    5314:	4620      	mov	r0, r4
    5316:	f004 fa8b 	bl	9830 <event_clear>
		curr_time = z_nrf_rtc_timer_read();
    531a:	f7ff feb5 	bl	5088 <z_nrf_rtc_timer_read>
	__asm__ volatile(
    531e:	f04f 0220 	mov.w	r2, #32
    5322:	f3ef 8311 	mrs	r3, BASEPRI
    5326:	f382 8812 	msr	BASEPRI_MAX, r2
    532a:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    532e:	eb08 1c04 	add.w	ip, r8, r4, lsl #4
    5332:	e9dc ab02 	ldrd	sl, fp, [ip, #8]
		if (curr_time >= expire_time) {
    5336:	4550      	cmp	r0, sl
    5338:	eb71 010b 	sbcs.w	r1, r1, fp
    533c:	9302      	str	r3, [sp, #8]
    533e:	d20a      	bcs.n	5356 <rtc_nrf_isr+0xae>
	__asm__ volatile(
    5340:	f383 8811 	msr	BASEPRI, r3
    5344:	f3bf 8f6f 	isb	sy
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    5348:	3510      	adds	r5, #16
    534a:	b114      	cbz	r4, 5352 <rtc_nrf_isr+0xaa>
}
    534c:	b005      	add	sp, #20
    534e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    5352:	2401      	movs	r4, #1
    5354:	e7c2      	b.n	52dc <rtc_nrf_isr+0x34>
			cc_data[chan].callback = NULL;
    5356:	2000      	movs	r0, #0
			user_context = cc_data[chan].user_context;
    5358:	e9d5 1300 	ldrd	r1, r3, [r5]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    535c:	f04f 32ff 	mov.w	r2, #4294967295
			user_context = cc_data[chan].user_context;
    5360:	9303      	str	r3, [sp, #12]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    5362:	f04f 33ff 	mov.w	r3, #4294967295
			cc_data[chan].callback = NULL;
    5366:	6028      	str	r0, [r5, #0]
    p_reg->EVTENCLR = mask;
    5368:	480a      	ldr	r0, [pc, #40]	; (5394 <rtc_nrf_isr+0xec>)
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    536a:	e9cc 2302 	strd	r2, r3, [ip, #8]
    536e:	f8c0 9348 	str.w	r9, [r0, #840]	; 0x348
			event_clear(chan);
    5372:	4620      	mov	r0, r4
    5374:	f004 fa5c 	bl	9830 <event_clear>
    5378:	9b02      	ldr	r3, [sp, #8]
    537a:	f383 8811 	msr	BASEPRI, r3
    537e:	f3bf 8f6f 	isb	sy
		if (handler) {
    5382:	2900      	cmp	r1, #0
    5384:	d0e0      	beq.n	5348 <rtc_nrf_isr+0xa0>
			handler(chan, expire_time, user_context);
    5386:	9b03      	ldr	r3, [sp, #12]
    5388:	4652      	mov	r2, sl
    538a:	9300      	str	r3, [sp, #0]
    538c:	465b      	mov	r3, fp
    538e:	4788      	blx	r1
    5390:	e7da      	b.n	5348 <rtc_nrf_isr+0xa0>
    5392:	bf00      	nop
    5394:	50015000 	.word	0x50015000
    5398:	20000e00 	.word	0x20000e00
    539c:	20000630 	.word	0x20000630
    53a0:	20000df4 	.word	0x20000df4
    53a4:	50015140 	.word	0x50015140

000053a8 <z_nrf_rtc_timer_chan_alloc>:
{
    53a8:	b570      	push	{r4, r5, r6, lr}
		prev = atomic_and(&alloc_mask, ~BIT(chan));
    53aa:	2401      	movs	r4, #1
		chan = alloc_mask ? 31 - __builtin_clz(alloc_mask) : -1;
    53ac:	4b0c      	ldr	r3, [pc, #48]	; (53e0 <z_nrf_rtc_timer_chan_alloc+0x38>)
    53ae:	6818      	ldr	r0, [r3, #0]
    53b0:	b190      	cbz	r0, 53d8 <z_nrf_rtc_timer_chan_alloc+0x30>
    53b2:	fab0 f080 	clz	r0, r0
    53b6:	f1c0 001f 	rsb	r0, r0, #31
		prev = atomic_and(&alloc_mask, ~BIT(chan));
    53ba:	fa04 f100 	lsl.w	r1, r4, r0
    53be:	43c9      	mvns	r1, r1
    53c0:	e8d3 2fef 	ldaex	r2, [r3]
    53c4:	ea02 0501 	and.w	r5, r2, r1
    53c8:	e8c3 5fe6 	stlex	r6, r5, [r3]
    53cc:	2e00      	cmp	r6, #0
    53ce:	d1f7      	bne.n	53c0 <z_nrf_rtc_timer_chan_alloc+0x18>
	} while (!(prev & BIT(chan)));
    53d0:	40c2      	lsrs	r2, r0
    53d2:	07d2      	lsls	r2, r2, #31
    53d4:	d5eb      	bpl.n	53ae <z_nrf_rtc_timer_chan_alloc+0x6>
}
    53d6:	bd70      	pop	{r4, r5, r6, pc}
			return -ENOMEM;
    53d8:	f06f 000b 	mvn.w	r0, #11
    53dc:	e7fb      	b.n	53d6 <z_nrf_rtc_timer_chan_alloc+0x2e>
    53de:	bf00      	nop
    53e0:	20000df8 	.word	0x20000df8

000053e4 <z_nrf_rtc_timer_chan_free>:
	__ASSERT_NO_MSG(chan > 0 && chan < CHAN_COUNT);
    53e4:	2801      	cmp	r0, #1
{
    53e6:	b508      	push	{r3, lr}
	__ASSERT_NO_MSG(chan > 0 && chan < CHAN_COUNT);
    53e8:	d00b      	beq.n	5402 <z_nrf_rtc_timer_chan_free+0x1e>
    53ea:	490b      	ldr	r1, [pc, #44]	; (5418 <z_nrf_rtc_timer_chan_free+0x34>)
    53ec:	480b      	ldr	r0, [pc, #44]	; (541c <z_nrf_rtc_timer_chan_free+0x38>)
    53ee:	f240 2329 	movw	r3, #553	; 0x229
    53f2:	4a0b      	ldr	r2, [pc, #44]	; (5420 <z_nrf_rtc_timer_chan_free+0x3c>)
    53f4:	f003 ff57 	bl	92a6 <assert_print>
    53f8:	f240 2129 	movw	r1, #553	; 0x229
    53fc:	4808      	ldr	r0, [pc, #32]	; (5420 <z_nrf_rtc_timer_chan_free+0x3c>)
    53fe:	f003 ff4b 	bl	9298 <assert_post_action>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    5402:	4b08      	ldr	r3, [pc, #32]	; (5424 <z_nrf_rtc_timer_chan_free+0x40>)
    5404:	e8d3 1fef 	ldaex	r1, [r3]
    5408:	f041 0102 	orr.w	r1, r1, #2
    540c:	e8c3 1fe2 	stlex	r2, r1, [r3]
    5410:	2a00      	cmp	r2, #0
    5412:	d1f7      	bne.n	5404 <z_nrf_rtc_timer_chan_free+0x20>
}
    5414:	bd08      	pop	{r3, pc}
    5416:	bf00      	nop
    5418:	0000b49a 	.word	0x0000b49a
    541c:	0000a2e8 	.word	0x0000a2e8
    5420:	0000b44d 	.word	0x0000b44d
    5424:	20000df8 	.word	0x20000df8

00005428 <sys_clock_set_timeout>:
	if (ticks == K_TICKS_FOREVER) {
    5428:	1c43      	adds	r3, r0, #1
{
    542a:	b513      	push	{r0, r1, r4, lr}
	if (ticks == K_TICKS_FOREVER) {
    542c:	d021      	beq.n	5472 <sys_clock_set_timeout+0x4a>
		cyc = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
    542e:	2801      	cmp	r0, #1
    5430:	dd21      	ble.n	5476 <sys_clock_set_timeout+0x4e>
    5432:	4a12      	ldr	r2, [pc, #72]	; (547c <sys_clock_set_timeout+0x54>)
    5434:	4b12      	ldr	r3, [pc, #72]	; (5480 <sys_clock_set_timeout+0x58>)
    5436:	4290      	cmp	r0, r2
    5438:	bfd4      	ite	le
    543a:	4604      	movle	r4, r0
    543c:	461c      	movgt	r4, r3
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    543e:	f7ff fe23 	bl	5088 <z_nrf_rtc_timer_read>
    5442:	4b10      	ldr	r3, [pc, #64]	; (5484 <sys_clock_set_timeout+0x5c>)
	if (cyc > MAX_CYCLES) {
    5444:	490e      	ldr	r1, [pc, #56]	; (5480 <sys_clock_set_timeout+0x58>)
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    5446:	e9d3 2300 	ldrd	r2, r3, [r3]
    544a:	1a80      	subs	r0, r0, r2
		cyc = 0;
    544c:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    5450:	bf28      	it	cs
    5452:	2400      	movcs	r4, #0
	cyc += unannounced;
    5454:	4404      	add	r4, r0
	if (cyc > MAX_CYCLES) {
    5456:	428c      	cmp	r4, r1
    5458:	bf28      	it	cs
    545a:	460c      	movcs	r4, r1
	uint64_t target_time = cyc + last_count;
    545c:	2000      	movs	r0, #0
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    545e:	490a      	ldr	r1, [pc, #40]	; (5488 <sys_clock_set_timeout+0x60>)
	uint64_t target_time = cyc + last_count;
    5460:	18a2      	adds	r2, r4, r2
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    5462:	9001      	str	r0, [sp, #4]
    5464:	9100      	str	r1, [sp, #0]
    5466:	f143 0300 	adc.w	r3, r3, #0
    546a:	f7ff fe2f 	bl	50cc <compare_set>
}
    546e:	b002      	add	sp, #8
    5470:	bd10      	pop	{r4, pc}
		cyc = MAX_TICKS * CYC_PER_TICK;
    5472:	4c03      	ldr	r4, [pc, #12]	; (5480 <sys_clock_set_timeout+0x58>)
    5474:	e7e3      	b.n	543e <sys_clock_set_timeout+0x16>
		cyc = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
    5476:	2401      	movs	r4, #1
    5478:	e7e1      	b.n	543e <sys_clock_set_timeout+0x16>
    547a:	bf00      	nop
    547c:	007ffffe 	.word	0x007ffffe
    5480:	007fffff 	.word	0x007fffff
    5484:	20000650 	.word	0x20000650
    5488:	00004f55 	.word	0x00004f55

0000548c <sys_clock_elapsed>:
{
    548c:	b508      	push	{r3, lr}
	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    548e:	f7ff fdfb 	bl	5088 <z_nrf_rtc_timer_read>
    5492:	4b02      	ldr	r3, [pc, #8]	; (549c <sys_clock_elapsed+0x10>)
    5494:	681b      	ldr	r3, [r3, #0]
}
    5496:	1ac0      	subs	r0, r0, r3
    5498:	bd08      	pop	{r3, pc}
    549a:	bf00      	nop
    549c:	20000650 	.word	0x20000650

000054a0 <nrf_gpio_pin_port_decode>:
{
    54a0:	b508      	push	{r3, lr}
    NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
    54a2:	6803      	ldr	r3, [r0, #0]
    switch (port)
    54a4:	095a      	lsrs	r2, r3, #5
    54a6:	d00d      	beq.n	54c4 <nrf_gpio_pin_port_decode+0x24>
    54a8:	2a01      	cmp	r2, #1
    54aa:	d013      	beq.n	54d4 <nrf_gpio_pin_port_decode+0x34>
    NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
    54ac:	490e      	ldr	r1, [pc, #56]	; (54e8 <nrf_gpio_pin_port_decode+0x48>)
    54ae:	480f      	ldr	r0, [pc, #60]	; (54ec <nrf_gpio_pin_port_decode+0x4c>)
    54b0:	f240 2347 	movw	r3, #583	; 0x247
    54b4:	4a0e      	ldr	r2, [pc, #56]	; (54f0 <nrf_gpio_pin_port_decode+0x50>)
    54b6:	f003 fef6 	bl	92a6 <assert_print>
    54ba:	f240 2147 	movw	r1, #583	; 0x247
    54be:	480c      	ldr	r0, [pc, #48]	; (54f0 <nrf_gpio_pin_port_decode+0x50>)
    54c0:	f003 feea 	bl	9298 <assert_post_action>
    return (mask & (1UL << pin_number)) ? true : false;
    54c4:	f04f 32ff 	mov.w	r2, #4294967295
    54c8:	fa22 f303 	lsr.w	r3, r2, r3
    NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
    54cc:	07d9      	lsls	r1, r3, #31
    54ce:	d5ed      	bpl.n	54ac <nrf_gpio_pin_port_decode+0xc>
        case 0: return NRF_P0;
    54d0:	4808      	ldr	r0, [pc, #32]	; (54f4 <nrf_gpio_pin_port_decode+0x54>)
    54d2:	e008      	b.n	54e6 <nrf_gpio_pin_port_decode+0x46>
    return (mask & (1UL << pin_number)) ? true : false;
    54d4:	f64f 72ff 	movw	r2, #65535	; 0xffff
    pin_number &= 0x1F;
    54d8:	f003 031f 	and.w	r3, r3, #31
    return (mask & (1UL << pin_number)) ? true : false;
    54dc:	40da      	lsrs	r2, r3
    NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
    54de:	07d2      	lsls	r2, r2, #31
    54e0:	d5e4      	bpl.n	54ac <nrf_gpio_pin_port_decode+0xc>
    *p_pin = pin_number & 0x1F;
    54e2:	6003      	str	r3, [r0, #0]
        case 1: return NRF_P1;
    54e4:	4804      	ldr	r0, [pc, #16]	; (54f8 <nrf_gpio_pin_port_decode+0x58>)
}
    54e6:	bd08      	pop	{r3, pc}
    54e8:	0000b3a1 	.word	0x0000b3a1
    54ec:	0000a2e8 	.word	0x0000a2e8
    54f0:	0000b36e 	.word	0x0000b36e
    54f4:	50842500 	.word	0x50842500
    54f8:	50842800 	.word	0x50842800

000054fc <mbox_nrf_init>:

	nrfx_ipc_config_load(&ch_config);
}

static int mbox_nrf_init(const struct device *dev)
{
    54fc:	b510      	push	{r4, lr}
    54fe:	4604      	mov	r4, r0
	struct mbox_nrf_data *data = dev->data;
    5500:	6902      	ldr	r2, [r0, #16]
{
    5502:	b0a8      	sub	sp, #160	; 0xa0

	data->dev = dev;
    5504:	f8c2 0080 	str.w	r0, [r2, #128]	; 0x80

	nrfx_ipc_init(0, mbox_dispatcher, (void *) data);
    5508:	4925      	ldr	r1, [pc, #148]	; (55a0 <mbox_nrf_init+0xa4>)
    550a:	2000      	movs	r0, #0
    550c:	f001 f846 	bl	659c <nrfx_ipc_init>

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    5510:	2200      	movs	r2, #0
    5512:	2101      	movs	r1, #1
    5514:	202a      	movs	r0, #42	; 0x2a
    5516:	f7fe f823 	bl	3560 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_ipc_irq_handler, 0);

	enable_dt_channels(dev);
    551a:	6864      	ldr	r4, [r4, #4]
	nrfx_ipc_config_t ch_config = { 0 };
    551c:	2284      	movs	r2, #132	; 0x84
    551e:	2100      	movs	r1, #0
    5520:	a807      	add	r0, sp, #28
    5522:	f004 f880 	bl	9626 <memset>
	if (conf->tx_mask >= BIT(IPC_CONF_NUM)) {
    5526:	6863      	ldr	r3, [r4, #4]
    5528:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
    552c:	d30a      	bcc.n	5544 <mbox_nrf_init+0x48>
		LOG_WRN("tx_mask too big (or IPC_CONF_NUM too small)");
    552e:	4b1d      	ldr	r3, [pc, #116]	; (55a4 <mbox_nrf_init+0xa8>)
    5530:	9305      	str	r3, [sp, #20]
    5532:	2302      	movs	r3, #2
    5534:	9304      	str	r3, [sp, #16]
    5536:	2300      	movs	r3, #0
    5538:	f44f 5184 	mov.w	r1, #4224	; 0x1080
    553c:	481a      	ldr	r0, [pc, #104]	; (55a8 <mbox_nrf_init+0xac>)
    553e:	aa04      	add	r2, sp, #16
    5540:	f7fd f972 	bl	2828 <z_impl_z_log_msg_static_create>
	if (conf->rx_mask >= BIT(IPC_CONF_NUM)) {
    5544:	6823      	ldr	r3, [r4, #0]
    5546:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
    554a:	d30a      	bcc.n	5562 <mbox_nrf_init+0x66>
		LOG_WRN("rx_mask too big (or IPC_CONF_NUM too small)");
    554c:	4b17      	ldr	r3, [pc, #92]	; (55ac <mbox_nrf_init+0xb0>)
    554e:	9305      	str	r3, [sp, #20]
    5550:	2302      	movs	r3, #2
    5552:	9304      	str	r3, [sp, #16]
    5554:	2300      	movs	r3, #0
    5556:	f44f 5184 	mov.w	r1, #4224	; 0x1080
    555a:	4813      	ldr	r0, [pc, #76]	; (55a8 <mbox_nrf_init+0xac>)
    555c:	aa04      	add	r2, sp, #16
    555e:	f7fd f963 	bl	2828 <z_impl_z_log_msg_static_create>
	ch_config.receive_events_enabled = 0;
    5562:	2300      	movs	r3, #0
			ch_config.send_task_config[ch] = BIT(ch);
    5564:	2001      	movs	r0, #1
	ch_config.receive_events_enabled = 0;
    5566:	9327      	str	r3, [sp, #156]	; 0x9c
	for (size_t ch = 0; ch < IPC_CONF_NUM; ch++) {
    5568:	aa07      	add	r2, sp, #28
		if (conf->tx_mask & BIT(ch)) {
    556a:	6861      	ldr	r1, [r4, #4]
	for (size_t ch = 0; ch < IPC_CONF_NUM; ch++) {
    556c:	3204      	adds	r2, #4
		if (conf->tx_mask & BIT(ch)) {
    556e:	40d9      	lsrs	r1, r3
    5570:	07c9      	lsls	r1, r1, #31
			ch_config.send_task_config[ch] = BIT(ch);
    5572:	bf44      	itt	mi
    5574:	fa00 f103 	lslmi.w	r1, r0, r3
    5578:	f842 1c04 	strmi.w	r1, [r2, #-4]
		if (conf->rx_mask & BIT(ch)) {
    557c:	6821      	ldr	r1, [r4, #0]
    557e:	40d9      	lsrs	r1, r3
    5580:	07c9      	lsls	r1, r1, #31
			ch_config.receive_event_config[ch] = BIT(ch);
    5582:	bf48      	it	mi
    5584:	fa00 f103 	lslmi.w	r1, r0, r3
	for (size_t ch = 0; ch < IPC_CONF_NUM; ch++) {
    5588:	f103 0301 	add.w	r3, r3, #1
			ch_config.receive_event_config[ch] = BIT(ch);
    558c:	bf48      	it	mi
    558e:	63d1      	strmi	r1, [r2, #60]	; 0x3c
	for (size_t ch = 0; ch < IPC_CONF_NUM; ch++) {
    5590:	2b10      	cmp	r3, #16
    5592:	d1ea      	bne.n	556a <mbox_nrf_init+0x6e>
	nrfx_ipc_config_load(&ch_config);
    5594:	a807      	add	r0, sp, #28
    5596:	f001 f819 	bl	65cc <nrfx_ipc_config_load>

	return 0;
}
    559a:	2000      	movs	r0, #0
    559c:	b028      	add	sp, #160	; 0xa0
    559e:	bd10      	pop	{r4, pc}
    55a0:	000056a5 	.word	0x000056a5
    55a4:	0000b4b5 	.word	0x0000b4b5
    55a8:	00009fd4 	.word	0x00009fd4
    55ac:	0000b4e1 	.word	0x0000b4e1

000055b0 <mbox_nrf_set_enabled>:
{
    55b0:	b530      	push	{r4, r5, lr}
	return ((ch < IPC_CONF_NUM) && (conf->rx_mask & BIT(ch)));
    55b2:	290f      	cmp	r1, #15
{
    55b4:	460c      	mov	r4, r1
	struct mbox_nrf_data *data = dev->data;
    55b6:	6905      	ldr	r5, [r0, #16]
{
    55b8:	b087      	sub	sp, #28
	return ((ch < IPC_CONF_NUM) && (conf->rx_mask & BIT(ch)));
    55ba:	d842      	bhi.n	5642 <mbox_nrf_set_enabled+0x92>
    55bc:	6843      	ldr	r3, [r0, #4]
    55be:	681b      	ldr	r3, [r3, #0]
    55c0:	40cb      	lsrs	r3, r1
    55c2:	07db      	lsls	r3, r3, #31
    55c4:	d53d      	bpl.n	5642 <mbox_nrf_set_enabled+0x92>
	if ((enable == 0 && (!(data->enabled_mask & BIT(channel)))) ||
    55c6:	f8d5 3084 	ldr.w	r3, [r5, #132]	; 0x84
    55ca:	40cb      	lsrs	r3, r1
    55cc:	f003 0301 	and.w	r3, r3, #1
    55d0:	b91a      	cbnz	r2, 55da <mbox_nrf_set_enabled+0x2a>
    55d2:	bb13      	cbnz	r3, 561a <mbox_nrf_set_enabled+0x6a>
		return -EALREADY;
    55d4:	f06f 0077 	mvn.w	r0, #119	; 0x77
    55d8:	e031      	b.n	563e <mbox_nrf_set_enabled+0x8e>
	    (enable != 0 &&   (data->enabled_mask & BIT(channel)))) {
    55da:	2b00      	cmp	r3, #0
    55dc:	d1fa      	bne.n	55d4 <mbox_nrf_set_enabled+0x24>
	if (enable && (data->cb[channel] == NULL)) {
    55de:	f855 3021 	ldr.w	r3, [r5, r1, lsl #2]
    55e2:	b94b      	cbnz	r3, 55f8 <mbox_nrf_set_enabled+0x48>
		LOG_WRN("Enabling channel without a registered callback\n");
    55e4:	4a18      	ldr	r2, [pc, #96]	; (5648 <mbox_nrf_set_enabled+0x98>)
    55e6:	9205      	str	r2, [sp, #20]
    55e8:	2202      	movs	r2, #2
    55ea:	9204      	str	r2, [sp, #16]
    55ec:	f44f 5184 	mov.w	r1, #4224	; 0x1080
    55f0:	4816      	ldr	r0, [pc, #88]	; (564c <mbox_nrf_set_enabled+0x9c>)
    55f2:	aa04      	add	r2, sp, #16
    55f4:	f7fd f918 	bl	2828 <z_impl_z_log_msg_static_create>
	if (enable && data->enabled_mask == 0) {
    55f8:	f8d5 3084 	ldr.w	r3, [r5, #132]	; 0x84
    55fc:	b913      	cbnz	r3, 5604 <mbox_nrf_set_enabled+0x54>
		irq_enable(DT_INST_IRQN(0));
    55fe:	202a      	movs	r0, #42	; 0x2a
    5600:	f7fd ff7e 	bl	3500 <arch_irq_enable>
		data->enabled_mask |= BIT(channel);
    5604:	2201      	movs	r2, #1
    5606:	f8d5 3084 	ldr.w	r3, [r5, #132]	; 0x84
    560a:	40a2      	lsls	r2, r4
    560c:	4313      	orrs	r3, r2
    560e:	f8c5 3084 	str.w	r3, [r5, #132]	; 0x84
		nrfx_ipc_receive_event_enable(channel);
    5612:	b2e0      	uxtb	r0, r4
    5614:	f001 f81c 	bl	6650 <nrfx_ipc_receive_event_enable>
    5618:	e00a      	b.n	5630 <mbox_nrf_set_enabled+0x80>
		nrfx_ipc_receive_event_disable(channel);
    561a:	b2c8      	uxtb	r0, r1
    561c:	f001 f836 	bl	668c <nrfx_ipc_receive_event_disable>
		data->enabled_mask &= ~BIT(channel);
    5620:	2201      	movs	r2, #1
    5622:	f8d5 3084 	ldr.w	r3, [r5, #132]	; 0x84
    5626:	40a2      	lsls	r2, r4
    5628:	ea23 0302 	bic.w	r3, r3, r2
    562c:	f8c5 3084 	str.w	r3, [r5, #132]	; 0x84
	if (data->enabled_mask == 0) {
    5630:	f8d5 3084 	ldr.w	r3, [r5, #132]	; 0x84
    5634:	b913      	cbnz	r3, 563c <mbox_nrf_set_enabled+0x8c>
		irq_disable(DT_INST_IRQN(0));
    5636:	202a      	movs	r0, #42	; 0x2a
    5638:	f7fd ff70 	bl	351c <arch_irq_disable>
	return 0;
    563c:	2000      	movs	r0, #0
}
    563e:	b007      	add	sp, #28
    5640:	bd30      	pop	{r4, r5, pc}
		return -EINVAL;
    5642:	f06f 0015 	mvn.w	r0, #21
    5646:	e7fa      	b.n	563e <mbox_nrf_set_enabled+0x8e>
    5648:	0000b50d 	.word	0x0000b50d
    564c:	00009fd4 	.word	0x00009fd4

00005650 <mbox_nrf_send>:
{
    5650:	b530      	push	{r4, r5, lr}
    5652:	4605      	mov	r5, r0
    5654:	460c      	mov	r4, r1
    5656:	b087      	sub	sp, #28
	if (msg) {
    5658:	b152      	cbz	r2, 5670 <mbox_nrf_send+0x20>
		LOG_WRN("Sending data not supported");
    565a:	4b10      	ldr	r3, [pc, #64]	; (569c <mbox_nrf_send+0x4c>)
    565c:	9305      	str	r3, [sp, #20]
    565e:	2302      	movs	r3, #2
    5660:	9304      	str	r3, [sp, #16]
    5662:	2300      	movs	r3, #0
    5664:	f44f 5184 	mov.w	r1, #4224	; 0x1080
    5668:	480d      	ldr	r0, [pc, #52]	; (56a0 <mbox_nrf_send+0x50>)
    566a:	aa04      	add	r2, sp, #16
    566c:	f7fd f8dc 	bl	2828 <z_impl_z_log_msg_static_create>
	return ((ch < IPC_CONF_NUM) && (conf->tx_mask & BIT(ch)));
    5670:	2c0f      	cmp	r4, #15
    5672:	d80f      	bhi.n	5694 <mbox_nrf_send+0x44>
    5674:	686b      	ldr	r3, [r5, #4]
    5676:	685b      	ldr	r3, [r3, #4]
    5678:	40e3      	lsrs	r3, r4
    567a:	07db      	lsls	r3, r3, #31
    567c:	d50a      	bpl.n	5694 <mbox_nrf_send+0x44>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    567e:	2301      	movs	r3, #1
	return 0;
    5680:	2000      	movs	r0, #0
    return (nrf_ipc_task_t)(NRFX_OFFSETOF(NRF_IPC_Type, TASKS_SEND[index]));
    5682:	00a4      	lsls	r4, r4, #2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5684:	b2e4      	uxtb	r4, r4
    5686:	f104 44a0 	add.w	r4, r4, #1342177280	; 0x50000000
    568a:	f504 3428 	add.w	r4, r4, #172032	; 0x2a000
    568e:	6023      	str	r3, [r4, #0]
}
    5690:	b007      	add	sp, #28
    5692:	bd30      	pop	{r4, r5, pc}
		return -EINVAL;
    5694:	f06f 0015 	mvn.w	r0, #21
    5698:	e7fa      	b.n	5690 <mbox_nrf_send+0x40>
    569a:	bf00      	nop
    569c:	0000b53d 	.word	0x0000b53d
    56a0:	00009fd4 	.word	0x00009fd4

000056a4 <mbox_dispatcher>:
{
    56a4:	b570      	push	{r4, r5, r6, lr}
	const struct device *dev = data->dev;
    56a6:	f8d1 6080 	ldr.w	r6, [r1, #128]	; 0x80
	return ((ch < IPC_CONF_NUM) && (conf->rx_mask & BIT(ch)));
    56aa:	280f      	cmp	r0, #15
{
    56ac:	4604      	mov	r4, r0
    56ae:	460d      	mov	r5, r1
    56b0:	6873      	ldr	r3, [r6, #4]
    56b2:	b086      	sub	sp, #24
	return ((ch < IPC_CONF_NUM) && (conf->rx_mask & BIT(ch)));
    56b4:	d803      	bhi.n	56be <mbox_dispatcher+0x1a>
    56b6:	681b      	ldr	r3, [r3, #0]
    56b8:	40c3      	lsrs	r3, r0
    56ba:	07db      	lsls	r3, r3, #31
    56bc:	d40a      	bmi.n	56d4 <mbox_dispatcher+0x30>
		LOG_WRN("RX event on illegal channel");
    56be:	4b15      	ldr	r3, [pc, #84]	; (5714 <mbox_dispatcher+0x70>)
    56c0:	9305      	str	r3, [sp, #20]
    56c2:	2302      	movs	r3, #2
    56c4:	9304      	str	r3, [sp, #16]
    56c6:	2300      	movs	r3, #0
    56c8:	f44f 5184 	mov.w	r1, #4224	; 0x1080
    56cc:	4812      	ldr	r0, [pc, #72]	; (5718 <mbox_dispatcher+0x74>)
    56ce:	aa04      	add	r2, sp, #16
    56d0:	f7fd f8aa 	bl	2828 <z_impl_z_log_msg_static_create>
	if (!(data->enabled_mask & BIT(channel))) {
    56d4:	f8d5 3084 	ldr.w	r3, [r5, #132]	; 0x84
    56d8:	40e3      	lsrs	r3, r4
    56da:	f013 0301 	ands.w	r3, r3, #1
    56de:	d109      	bne.n	56f4 <mbox_dispatcher+0x50>
		LOG_WRN("RX event on disabled channel");
    56e0:	4a0e      	ldr	r2, [pc, #56]	; (571c <mbox_dispatcher+0x78>)
    56e2:	9205      	str	r2, [sp, #20]
    56e4:	2202      	movs	r2, #2
    56e6:	9204      	str	r2, [sp, #16]
    56e8:	f44f 5184 	mov.w	r1, #4224	; 0x1080
    56ec:	480a      	ldr	r0, [pc, #40]	; (5718 <mbox_dispatcher+0x74>)
    56ee:	aa04      	add	r2, sp, #16
    56f0:	f7fd f89a 	bl	2828 <z_impl_z_log_msg_static_create>
	if (data->cb[channel] != NULL) {
    56f4:	eb05 0284 	add.w	r2, r5, r4, lsl #2
    56f8:	f855 5024 	ldr.w	r5, [r5, r4, lsl #2]
    56fc:	b145      	cbz	r5, 5710 <mbox_dispatcher+0x6c>
		data->cb[channel](dev, channel, data->user_data[channel], NULL);
    56fe:	2300      	movs	r3, #0
    5700:	4621      	mov	r1, r4
    5702:	4630      	mov	r0, r6
    5704:	46ac      	mov	ip, r5
    5706:	6c12      	ldr	r2, [r2, #64]	; 0x40
}
    5708:	b006      	add	sp, #24
    570a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		data->cb[channel](dev, channel, data->user_data[channel], NULL);
    570e:	4760      	bx	ip
}
    5710:	b006      	add	sp, #24
    5712:	bd70      	pop	{r4, r5, r6, pc}
    5714:	0000b558 	.word	0x0000b558
    5718:	00009fd4 	.word	0x00009fd4
    571c:	0000b574 	.word	0x0000b574

00005720 <k_sys_fatal_error_handler>:

extern void sys_arch_reboot(int type);

void k_sys_fatal_error_handler(unsigned int reason,
			       const z_arch_esf_t *esf)
{
    5720:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
	z_impl_log_panic();
    5722:	f7fd f813 	bl	274c <z_impl_log_panic>
	ARG_UNUSED(reason);

	LOG_PANIC();

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
    5726:	4b07      	ldr	r3, [pc, #28]	; (5744 <k_sys_fatal_error_handler+0x24>)
    5728:	9305      	str	r3, [sp, #20]
    572a:	2302      	movs	r3, #2
    572c:	9304      	str	r3, [sp, #16]
    572e:	4806      	ldr	r0, [pc, #24]	; (5748 <k_sys_fatal_error_handler+0x28>)
    5730:	2300      	movs	r3, #0
    5732:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    5736:	aa04      	add	r2, sp, #16
    5738:	f7fd f876 	bl	2828 <z_impl_z_log_msg_static_create>
		sys_arch_reboot(0);
    573c:	2000      	movs	r0, #0
    573e:	f7fe fb83 	bl	3e48 <sys_arch_reboot>
		for (;;) {
			/* Spin endlessly */
		}
	}

	CODE_UNREACHABLE;
    5742:	bf00      	nop
    5744:	0000b5aa 	.word	0x0000b5aa
    5748:	00009fb4 	.word	0x00009fb4

0000574c <nrf53_errata_42>:
            #if defined(NRF_APPLICATION)
                #if defined(NRF_TRUSTZONE_NONSECURE)
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
                #else
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
    574c:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    5750:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
    5754:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
                #endif
            #endif
        #endif
        #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
            #if defined (NRF_APPLICATION)
                if (var1 == 0x07)
    5758:	2a07      	cmp	r2, #7
    575a:	d105      	bne.n	5768 <nrf53_errata_42+0x1c>
                {
                    switch(var2)
    575c:	3b02      	subs	r3, #2
    575e:	2b03      	cmp	r3, #3
    5760:	d802      	bhi.n	5768 <nrf53_errata_42+0x1c>
    5762:	4a02      	ldr	r2, [pc, #8]	; (576c <nrf53_errata_42+0x20>)
    5764:	5cd0      	ldrb	r0, [r2, r3]
    5766:	4770      	bx	lr
                    {
                        case 0x02ul:
                            return true;
                        case 0x03ul:
                            return false;
    5768:	2000      	movs	r0, #0
                }
            #endif
        #endif
        return false;
    #endif
}
    576a:	4770      	bx	lr
    576c:	0000b5cb 	.word	0x0000b5cb

00005770 <SystemCoreClockUpdate>:
void SystemCoreClockUpdate(void)
{
#if defined(NRF_TRUSTZONE_NONSECURE)
    SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_NS->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
#else
    SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_S->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
    5770:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    5774:	f8d3 2558 	ldr.w	r2, [r3, #1368]	; 0x558
    5778:	4b03      	ldr	r3, [pc, #12]	; (5788 <SystemCoreClockUpdate+0x18>)
    577a:	f002 0203 	and.w	r2, r2, #3
    577e:	40d3      	lsrs	r3, r2
    5780:	4a02      	ldr	r2, [pc, #8]	; (578c <SystemCoreClockUpdate+0x1c>)
    5782:	6013      	str	r3, [r2, #0]
#endif
}
    5784:	4770      	bx	lr
    5786:	bf00      	nop
    5788:	07a12000 	.word	0x07a12000
    578c:	20000054 	.word	0x20000054

00005790 <SystemInit>:

void SystemInit(void)
{
    5790:	b508      	push	{r3, lr}
            SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
        #endif

        /* Workaround for Errata 97 "ERASEPROTECT, APPROTECT, or startup problems" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_97())
    5792:	f7ff ffdb 	bl	574c <nrf53_errata_42>
    5796:	b158      	cbz	r0, 57b0 <SystemInit+0x20>
        {
            if (*((volatile uint32_t *)0x50004A20ul) == 0)
    5798:	4b4f      	ldr	r3, [pc, #316]	; (58d8 <SystemInit+0x148>)
    579a:	f8d3 2a20 	ldr.w	r2, [r3, #2592]	; 0xa20
    579e:	b93a      	cbnz	r2, 57b0 <SystemInit+0x20>
            {
                *((volatile uint32_t *)0x50004A20ul) = 0xDul;
    57a0:	210d      	movs	r1, #13
    57a2:	f8c3 1a20 	str.w	r1, [r3, #2592]	; 0xa20
                *((volatile uint32_t *)0x5000491Cul) = 0x1ul;
    57a6:	2101      	movs	r1, #1
    57a8:	f8c3 191c 	str.w	r1, [r3, #2332]	; 0x91c
                *((volatile uint32_t *)0x5000491Cul) = 0x0ul;
    57ac:	f8c3 291c 	str.w	r2, [r3, #2332]	; 0x91c
{
    57b0:	2200      	movs	r2, #0
    57b2:	00d3      	lsls	r3, r2, #3
    57b4:	f503 037f 	add.w	r3, r3, #16711680	; 0xff0000
        }

        /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
         until one ADDR is not initialized. */
        uint32_t index = 0;
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    57b8:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
    57bc:	3101      	adds	r1, #1
    57be:	d007      	beq.n	57d0 <SystemInit+0x40>
            #if defined ( __ICCARM__ )
                /* IAR will complain about the order of volatile pointer accesses. */
                #pragma diag_suppress=Pa082
            #endif
            *((volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR) = NRF_FICR_S->TRIMCNF[index].DATA;
    57c0:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    57c4:	3201      	adds	r2, #1
            *((volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR) = NRF_FICR_S->TRIMCNF[index].DATA;
    57c6:	f8d3 3304 	ldr.w	r3, [r3, #772]	; 0x304
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    57ca:	2a20      	cmp	r2, #32
            *((volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR) = NRF_FICR_S->TRIMCNF[index].DATA;
    57cc:	600b      	str	r3, [r1, #0]
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    57ce:	d1f0      	bne.n	57b2 <SystemInit+0x22>
        }

        /* errata 64 must be before errata 42, as errata 42 is dependant on the changes in errata 64*/
        /* Workaround for Errata 64 "VREGMAIN has invalid configuration when CPU is running at 128 MHz" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_64())
    57d0:	f7ff ffbc 	bl	574c <nrf53_errata_42>
    57d4:	2800      	cmp	r0, #0
    57d6:	d176      	bne.n	58c6 <SystemInit+0x136>
            *((volatile uint32_t *)0x5000473Cul) = 0x3ul;
        }

        /* Workaround for Errata 42 "Reset value of HFCLKCTRL is invalid" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_42())
    57d8:	f7ff ffb8 	bl	574c <nrf53_errata_42>
    57dc:	b140      	cbz	r0, 57f0 <SystemInit+0x60>
        {
            *((volatile uint32_t *)0x50039530ul) = 0xBEEF0044ul;
    57de:	4b3f      	ldr	r3, [pc, #252]	; (58dc <SystemInit+0x14c>)
    57e0:	4a3f      	ldr	r2, [pc, #252]	; (58e0 <SystemInit+0x150>)
    57e2:	f8c3 2530 	str.w	r2, [r3, #1328]	; 0x530
            NRF_CLOCK_S->HFCLKCTRL = CLOCK_HFCLKCTRL_HCLK_Div2 << CLOCK_HFCLKCTRL_HCLK_Pos;
    57e6:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    57ea:	2201      	movs	r2, #1
    57ec:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558
            #if defined(NRF_APPLICATION)
                #if defined(NRF_TRUSTZONE_NONSECURE)
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
                #else
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
    57f0:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    57f4:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
    57f8:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
                #endif
            #endif
        #endif
        #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
            #if defined (NRF_APPLICATION)
                if (var1 == 0x07)
    57fc:	2a07      	cmp	r2, #7
    57fe:	d109      	bne.n	5814 <SystemInit+0x84>
                {
                    switch(var2)
    5800:	3b02      	subs	r3, #2
    5802:	2b03      	cmp	r3, #3
    5804:	d806      	bhi.n	5814 <SystemInit+0x84>
        }

        /* Workaround for Errata 46 "Higher power consumption of LFRC" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_46())
    5806:	4a37      	ldr	r2, [pc, #220]	; (58e4 <SystemInit+0x154>)
    5808:	5cd3      	ldrb	r3, [r2, r3]
    580a:	b11b      	cbz	r3, 5814 <SystemInit+0x84>
        {
            *((volatile uint32_t *)0x5003254Cul) = 0;
    580c:	2200      	movs	r2, #0
    580e:	4b36      	ldr	r3, [pc, #216]	; (58e8 <SystemInit+0x158>)
    5810:	f8c3 254c 	str.w	r2, [r3, #1356]	; 0x54c
        }

        /* Workaround for Errata 49 "SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_49())
    5814:	f7ff ff9a 	bl	574c <nrf53_errata_42>
    5818:	b150      	cbz	r0, 5830 <SystemInit+0xa0>
        {
            if (NRF_RESET_S->RESETREAS & RESET_RESETREAS_RESETPIN_Msk)
    581a:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    581e:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    5822:	07d1      	lsls	r1, r2, #31
            {
                NRF_POWER_S->EVENTS_SLEEPENTER = 0;
    5824:	bf42      	ittt	mi
    5826:	2200      	movmi	r2, #0
    5828:	f8c3 2114 	strmi.w	r2, [r3, #276]	; 0x114
                NRF_POWER_S->EVENTS_SLEEPEXIT = 0;
    582c:	f8c3 2118 	strmi.w	r2, [r3, #280]	; 0x118
            #if defined(NRF_APPLICATION)
                #if defined(NRF_TRUSTZONE_NONSECURE)
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
                #else
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
    5830:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    5834:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
    5838:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
            #endif
        #endif
        #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
            #if defined (NRF_APPLICATION)\
             || defined (NRF_NETWORK)
                if (var1 == 0x07)
    583c:	2a07      	cmp	r2, #7
    583e:	d109      	bne.n	5854 <SystemInit+0xc4>

        /* Workaround for Errata 55 "Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_55())
        {
            if (NRF_RESET_S->RESETREAS & RESET_RESETREAS_RESETPIN_Msk){
    5840:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    5844:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    5848:	07d2      	lsls	r2, r2, #31
                NRF_RESET_S->RESETREAS = ~RESET_RESETREAS_RESETPIN_Msk;
    584a:	bf44      	itt	mi
    584c:	f06f 0201 	mvnmi.w	r2, #1
    5850:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400
            }
        }

        /* Workaround for Errata 69 "VREGMAIN configuration is not retained in System OFF" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_69())
    5854:	f7ff ff7a 	bl	574c <nrf53_errata_42>
    5858:	b118      	cbz	r0, 5862 <SystemInit+0xd2>
        {
            *((volatile uint32_t *)0x5000470Cul) =0x65ul;
    585a:	2265      	movs	r2, #101	; 0x65
    585c:	4b1e      	ldr	r3, [pc, #120]	; (58d8 <SystemInit+0x148>)
    585e:	f8c3 270c 	str.w	r2, [r3, #1804]	; 0x70c
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
    5862:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    5866:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
    586a:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
                if (var1 == 0x07)
    586e:	2a07      	cmp	r2, #7
    5870:	d116      	bne.n	58a0 <SystemInit+0x110>
        }

        if (nrf53_errata_140())
        {
            if (*(volatile uint32_t *)0x50032420 & 0x80000000)
    5872:	4b1d      	ldr	r3, [pc, #116]	; (58e8 <SystemInit+0x158>)
    5874:	f8d3 3420 	ldr.w	r3, [r3, #1056]	; 0x420
    5878:	2b00      	cmp	r3, #0
    587a:	da11      	bge.n	58a0 <SystemInit+0x110>
            {
                /* Reset occured during calibration */
                NRF_CLOCK_S->LFCLKSRC = CLOCK_LFCLKSRC_SRC_LFSYNT;
    587c:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    5880:	2203      	movs	r2, #3
    5882:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
                NRF_CLOCK_S->TASKS_LFCLKSTART = 1;
    5886:	2201      	movs	r2, #1
    5888:	609a      	str	r2, [r3, #8]
                while (NRF_CLOCK_S->EVENTS_LFCLKSTARTED == 0) {}
    588a:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    588e:	2a00      	cmp	r2, #0
    5890:	d0fb      	beq.n	588a <SystemInit+0xfa>
                NRF_CLOCK_S->EVENTS_LFCLKSTARTED = 0;
    5892:	2200      	movs	r2, #0
    5894:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
                NRF_CLOCK_S->TASKS_LFCLKSTOP = 1;
    5898:	2201      	movs	r2, #1
    589a:	60da      	str	r2, [r3, #12]
                NRF_CLOCK_S->LFCLKSRC = CLOCK_LFCLKSRC_SRC_LFRC;
    589c:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518

        #endif

        /* Allow Non-Secure code to run FPU instructions.
         * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
        SCB->NSACR |= (3UL << 10);
    58a0:	4a12      	ldr	r2, [pc, #72]	; (58ec <SystemInit+0x15c>)
    58a2:	f8d2 308c 	ldr.w	r3, [r2, #140]	; 0x8c
    58a6:	f443 6340 	orr.w	r3, r3, #3072	; 0xc00
    58aa:	f8c2 308c 	str.w	r3, [r2, #140]	; 0x8c
                /* Do nothing, allow user code to handle APPROTECT. Use this if you want to enable authenticated debug. */

        #else
            /* Load APPROTECT soft branch from UICR.
               If UICR->APPROTECT is disabled, CTRLAP->APPROTECT will be disabled. */
            NRF_CTRLAP_S->APPROTECT.DISABLE = NRF_UICR_S->APPROTECT;
    58ae:	4a10      	ldr	r2, [pc, #64]	; (58f0 <SystemInit+0x160>)
    58b0:	4b10      	ldr	r3, [pc, #64]	; (58f4 <SystemInit+0x164>)
    58b2:	6811      	ldr	r1, [r2, #0]
    58b4:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
                /* Do nothing, allow user code to handle SECURE APPROTECT. Use this if you want to enable authenticated debug. */

        #else
            /* Load SECURE APPROTECT soft branch from UICR.
               If UICR->SECUREAPPROTECT is disabled, CTRLAP->SECUREAPPROTECT will be disabled. */
            NRF_CTRLAP_S->SECUREAPPROTECT.DISABLE = NRF_UICR_S->SECUREAPPROTECT;
    58b8:	69d2      	ldr	r2, [r2, #28]
    58ba:	f8c3 254c 	str.w	r2, [r3, #1356]	; 0x54c
        __DSB();
        __ISB();
    #endif

    SystemCoreClockUpdate();
}
    58be:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    SystemCoreClockUpdate();
    58c2:	f7ff bf55 	b.w	5770 <SystemCoreClockUpdate>
            *((volatile uint32_t *)0x5000470Cul) = 0x29ul;
    58c6:	2229      	movs	r2, #41	; 0x29
    58c8:	4b03      	ldr	r3, [pc, #12]	; (58d8 <SystemInit+0x148>)
    58ca:	f8c3 270c 	str.w	r2, [r3, #1804]	; 0x70c
            *((volatile uint32_t *)0x5000473Cul) = 0x3ul;
    58ce:	2203      	movs	r2, #3
    58d0:	f8c3 273c 	str.w	r2, [r3, #1852]	; 0x73c
    58d4:	e780      	b.n	57d8 <SystemInit+0x48>
    58d6:	bf00      	nop
    58d8:	50004000 	.word	0x50004000
    58dc:	50039000 	.word	0x50039000
    58e0:	beef0044 	.word	0xbeef0044
    58e4:	0000b5c7 	.word	0x0000b5c7
    58e8:	50032000 	.word	0x50032000
    58ec:	e000ed00 	.word	0xe000ed00
    58f0:	00ff8000 	.word	0x00ff8000
    58f4:	50006000 	.word	0x50006000

000058f8 <nrfx_flag32_alloc>:
{
    return (mask & NRFX_BIT(bitpos)) ? false : true;
}

nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag)
{
    58f8:	b570      	push	{r4, r5, r6, lr}
        idx = 31 - NRF_CLZ(prev_mask);
        if (idx < 0) {
            return NRFX_ERROR_NO_MEM;
        }

        new_mask = prev_mask & ~NRFX_BIT(idx);
    58fa:	2501      	movs	r5, #1
        prev_mask = *p_mask;
    58fc:	6802      	ldr	r2, [r0, #0]
        idx = 31 - NRF_CLZ(prev_mask);
    58fe:	fab2 f382 	clz	r3, r2
    5902:	f1c3 031f 	rsb	r3, r3, #31
    5906:	b2db      	uxtb	r3, r3
        new_mask = prev_mask & ~NRFX_BIT(idx);
    5908:	fa05 f403 	lsl.w	r4, r5, r3
    590c:	ea22 0404 	bic.w	r4, r2, r4
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    5910:	e8d0 6fef 	ldaex	r6, [r0]
    5914:	4296      	cmp	r6, r2
    5916:	d104      	bne.n	5922 <nrfx_flag32_alloc+0x2a>
    5918:	e8c0 4fec 	stlex	ip, r4, [r0]
    591c:	f1bc 0f00 	cmp.w	ip, #0
    5920:	d1f6      	bne.n	5910 <nrfx_flag32_alloc+0x18>
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    5922:	d1eb      	bne.n	58fc <nrfx_flag32_alloc+0x4>

    *p_flag = idx;

    return NRFX_SUCCESS;
}
    5924:	4801      	ldr	r0, [pc, #4]	; (592c <nrfx_flag32_alloc+0x34>)
    *p_flag = idx;
    5926:	700b      	strb	r3, [r1, #0]
}
    5928:	bd70      	pop	{r4, r5, r6, pc}
    592a:	bf00      	nop
    592c:	0bad0000 	.word	0x0bad0000

00005930 <nrfx_flag32_free>:

nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag)
{
    5930:	b510      	push	{r4, lr}
    uint32_t new_mask, prev_mask;

    if ((NRFX_BIT(flag) & *p_mask))
    5932:	6803      	ldr	r3, [r0, #0]
    5934:	40cb      	lsrs	r3, r1
    5936:	07db      	lsls	r3, r3, #31
    5938:	d410      	bmi.n	595c <nrfx_flag32_free+0x2c>
        return NRFX_ERROR_INVALID_PARAM;
    }

    do {
        prev_mask = *p_mask;
        new_mask = prev_mask | NRFX_BIT(flag);
    593a:	2301      	movs	r3, #1
    593c:	408b      	lsls	r3, r1
        prev_mask = *p_mask;
    593e:	6802      	ldr	r2, [r0, #0]
        new_mask = prev_mask | NRFX_BIT(flag);
    5940:	ea43 0102 	orr.w	r1, r3, r2
    5944:	e8d0 4fef 	ldaex	r4, [r0]
    5948:	4294      	cmp	r4, r2
    594a:	d104      	bne.n	5956 <nrfx_flag32_free+0x26>
    594c:	e8c0 1fec 	stlex	ip, r1, [r0]
    5950:	f1bc 0f00 	cmp.w	ip, #0
    5954:	d1f6      	bne.n	5944 <nrfx_flag32_free+0x14>
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    5956:	d1f2      	bne.n	593e <nrfx_flag32_free+0xe>

    return NRFX_SUCCESS;
    5958:	4801      	ldr	r0, [pc, #4]	; (5960 <nrfx_flag32_free+0x30>)
}
    595a:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    595c:	4801      	ldr	r0, [pc, #4]	; (5964 <nrfx_flag32_free+0x34>)
    595e:	e7fc      	b.n	595a <nrfx_flag32_free+0x2a>
    5960:	0bad0000 	.word	0x0bad0000
    5964:	0bad0004 	.word	0x0bad0004

00005968 <clock_stop>:
}
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)

static void clock_stop(nrf_clock_domain_t domain)
{
    switch (domain)
    5968:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    596c:	2200      	movs	r2, #0
{
    596e:	b573      	push	{r0, r1, r4, r5, r6, lr}
    switch (domain)
    5970:	2803      	cmp	r0, #3
    5972:	d838      	bhi.n	59e6 <clock_stop+0x7e>
    5974:	e8df f000 	tbb	[pc, r0]
    5978:	2c210d02 	.word	0x2c210d02
    p_reg->INTENCLR = mask;
    597c:	2102      	movs	r1, #2
    597e:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5982:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    5986:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    598a:	2201      	movs	r2, #1
    598c:	60da      	str	r2, [r3, #12]
            return;
    }

    bool stopped;
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    598e:	2400      	movs	r4, #0
    5990:	e009      	b.n	59a6 <clock_stop+0x3e>
    p_reg->INTENCLR = mask;
    5992:	2101      	movs	r1, #1
    5994:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5998:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    599c:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    59a0:	f10d 0407 	add.w	r4, sp, #7
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    59a4:	6059      	str	r1, [r3, #4]
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    59a6:	2301      	movs	r3, #1
    59a8:	f88d 3007 	strb.w	r3, [sp, #7]
    switch (domain)
    59ac:	2803      	cmp	r0, #3
    59ae:	f200 8097 	bhi.w	5ae0 <clock_stop+0x178>
    59b2:	e8df f000 	tbb	[pc, r0]
    59b6:	4422      	.short	0x4422
    59b8:	8665      	.short	0x8665
    p_reg->INTENCLR = mask;
    59ba:	f44f 7100 	mov.w	r1, #512	; 0x200
    59be:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    59c2:	f8c3 2124 	str.w	r2, [r3, #292]	; 0x124
    59c6:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    59ca:	2201      	movs	r2, #1
    59cc:	625a      	str	r2, [r3, #36]	; 0x24
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    59ce:	e7de      	b.n	598e <clock_stop+0x26>
    p_reg->INTENCLR = mask;
    59d0:	f44f 7180 	mov.w	r1, #256	; 0x100
    59d4:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    59d8:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    59dc:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    59e0:	2201      	movs	r2, #1
    59e2:	61da      	str	r2, [r3, #28]
    59e4:	e7d3      	b.n	598e <clock_stop+0x26>
            NRFX_ASSERT(0);
    59e6:	4946      	ldr	r1, [pc, #280]	; (5b00 <clock_stop+0x198>)
    59e8:	4846      	ldr	r0, [pc, #280]	; (5b04 <clock_stop+0x19c>)
    59ea:	23d8      	movs	r3, #216	; 0xd8
    59ec:	4a46      	ldr	r2, [pc, #280]	; (5b08 <clock_stop+0x1a0>)
    59ee:	f003 fc5a 	bl	92a6 <assert_print>
    59f2:	21d8      	movs	r1, #216	; 0xd8
    59f4:	4844      	ldr	r0, [pc, #272]	; (5b08 <clock_stop+0x1a0>)
            NRFX_ASSERT(0);
    59f6:	f003 fc4f 	bl	9298 <assert_post_action>
    switch (domain)
    59fa:	f242 7510 	movw	r5, #10000	; 0x2710
    59fe:	f04f 2650 	mov.w	r6, #1342197760	; 0x50005000
            if (p_clk_src != NULL)
    5a02:	b194      	cbz	r4, 5a2a <clock_stop+0xc2>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    5a04:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    5a08:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    5a0c:	7023      	strb	r3, [r4, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    5a0e:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    5a12:	03d9      	lsls	r1, r3, #15
    5a14:	d507      	bpl.n	5a26 <clock_stop+0xbe>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    5a16:	f89d 0007 	ldrb.w	r0, [sp, #7]
    5a1a:	2801      	cmp	r0, #1
    5a1c:	d103      	bne.n	5a26 <clock_stop+0xbe>
    5a1e:	f004 f800 	bl	9a22 <nrfx_busy_wait>
    5a22:	3d01      	subs	r5, #1
    5a24:	d1ed      	bne.n	5a02 <clock_stop+0x9a>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    5a26:	b002      	add	sp, #8
    5a28:	bd70      	pop	{r4, r5, r6, pc}
    5a2a:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    5a2e:	03da      	lsls	r2, r3, #15
    5a30:	d5f9      	bpl.n	5a26 <clock_stop+0xbe>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    5a32:	2001      	movs	r0, #1
    5a34:	f003 fff5 	bl	9a22 <nrfx_busy_wait>
    5a38:	3d01      	subs	r5, #1
    5a3a:	d1f6      	bne.n	5a2a <clock_stop+0xc2>
    5a3c:	e7f3      	b.n	5a26 <clock_stop+0xbe>
    switch (domain)
    5a3e:	f242 7510 	movw	r5, #10000	; 0x2710
    5a42:	f04f 2650 	mov.w	r6, #1342197760	; 0x50005000
            if (p_clk_src != NULL)
    5a46:	b18c      	cbz	r4, 5a6c <clock_stop+0x104>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    5a48:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    5a4c:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    5a50:	7023      	strb	r3, [r4, #0]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    5a52:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    5a56:	03db      	lsls	r3, r3, #15
    5a58:	d5e5      	bpl.n	5a26 <clock_stop+0xbe>
    5a5a:	f89d 0007 	ldrb.w	r0, [sp, #7]
    5a5e:	2801      	cmp	r0, #1
    5a60:	d1e1      	bne.n	5a26 <clock_stop+0xbe>
    5a62:	f003 ffde 	bl	9a22 <nrfx_busy_wait>
    5a66:	3d01      	subs	r5, #1
    5a68:	d1ed      	bne.n	5a46 <clock_stop+0xde>
    5a6a:	e7dc      	b.n	5a26 <clock_stop+0xbe>
    5a6c:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    5a70:	03d8      	lsls	r0, r3, #15
    5a72:	d5d8      	bpl.n	5a26 <clock_stop+0xbe>
    5a74:	2001      	movs	r0, #1
    5a76:	f003 ffd4 	bl	9a22 <nrfx_busy_wait>
    5a7a:	3d01      	subs	r5, #1
    5a7c:	d1f6      	bne.n	5a6c <clock_stop+0x104>
    5a7e:	e7d2      	b.n	5a26 <clock_stop+0xbe>
    switch (domain)
    5a80:	f242 7510 	movw	r5, #10000	; 0x2710
    5a84:	f04f 2650 	mov.w	r6, #1342197760	; 0x50005000
            if (p_clk_src != NULL)
    5a88:	b18c      	cbz	r4, 5aae <clock_stop+0x146>
                    (nrf_clock_hfclk_t)((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_SRC_Msk)
    5a8a:	f8d6 345c 	ldr.w	r3, [r6, #1116]	; 0x45c
    5a8e:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    5a92:	7023      	strb	r3, [r4, #0]
            if ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_STATE_Msk)
    5a94:	f8d6 345c 	ldr.w	r3, [r6, #1116]	; 0x45c
    5a98:	03d9      	lsls	r1, r3, #15
    5a9a:	d5c4      	bpl.n	5a26 <clock_stop+0xbe>
    5a9c:	f89d 0007 	ldrb.w	r0, [sp, #7]
    5aa0:	2801      	cmp	r0, #1
    5aa2:	d1c0      	bne.n	5a26 <clock_stop+0xbe>
    5aa4:	f003 ffbd 	bl	9a22 <nrfx_busy_wait>
    5aa8:	3d01      	subs	r5, #1
    5aaa:	d1ed      	bne.n	5a88 <clock_stop+0x120>
    5aac:	e7bb      	b.n	5a26 <clock_stop+0xbe>
    5aae:	f8d6 345c 	ldr.w	r3, [r6, #1116]	; 0x45c
    5ab2:	03da      	lsls	r2, r3, #15
    5ab4:	d5b7      	bpl.n	5a26 <clock_stop+0xbe>
    5ab6:	2001      	movs	r0, #1
    5ab8:	f003 ffb3 	bl	9a22 <nrfx_busy_wait>
    5abc:	3d01      	subs	r5, #1
    5abe:	d1f6      	bne.n	5aae <clock_stop+0x146>
    5ac0:	e7b1      	b.n	5a26 <clock_stop+0xbe>
    switch (domain)
    5ac2:	f242 7510 	movw	r5, #10000	; 0x2710
            return (p_reg->HFCLKAUDIOSTAT & CLOCK_HFCLKAUDIOSTAT_STATE_Msk) ==
    5ac6:	f04f 2650 	mov.w	r6, #1342197760	; 0x50005000
    5aca:	f8d6 3454 	ldr.w	r3, [r6, #1108]	; 0x454
    5ace:	03db      	lsls	r3, r3, #15
    5ad0:	d5a9      	bpl.n	5a26 <clock_stop+0xbe>
    5ad2:	b984      	cbnz	r4, 5af6 <clock_stop+0x18e>
    5ad4:	2001      	movs	r0, #1
    5ad6:	f003 ffa4 	bl	9a22 <nrfx_busy_wait>
    5ada:	3d01      	subs	r5, #1
    5adc:	d1f5      	bne.n	5aca <clock_stop+0x162>
    5ade:	e7a2      	b.n	5a26 <clock_stop+0xbe>
            NRFX_ASSERT(0);
    5ae0:	4907      	ldr	r1, [pc, #28]	; (5b00 <clock_stop+0x198>)
    5ae2:	4808      	ldr	r0, [pc, #32]	; (5b04 <clock_stop+0x19c>)
    5ae4:	f240 3347 	movw	r3, #839	; 0x347
    5ae8:	4a08      	ldr	r2, [pc, #32]	; (5b0c <clock_stop+0x1a4>)
    5aea:	f003 fbdc 	bl	92a6 <assert_print>
    5aee:	f240 3147 	movw	r1, #839	; 0x347
    5af2:	4806      	ldr	r0, [pc, #24]	; (5b0c <clock_stop+0x1a4>)
    5af4:	e77f      	b.n	59f6 <clock_stop+0x8e>
    5af6:	f89d 0007 	ldrb.w	r0, [sp, #7]
    5afa:	2801      	cmp	r0, #1
    5afc:	d0eb      	beq.n	5ad6 <clock_stop+0x16e>
    5afe:	e792      	b.n	5a26 <clock_stop+0xbe>
    5b00:	0000a5f9 	.word	0x0000a5f9
    5b04:	0000a2e8 	.word	0x0000a2e8
    5b08:	0000b5cf 	.word	0x0000b5cf
    5b0c:	0000b60c 	.word	0x0000b60c

00005b10 <nrfx_clock_init>:
    }
    return is_correct_clk;
}

nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    5b10:	b508      	push	{r3, lr}
    NRFX_ASSERT(event_handler);
    5b12:	b958      	cbnz	r0, 5b2c <nrfx_clock_init+0x1c>
    5b14:	490a      	ldr	r1, [pc, #40]	; (5b40 <nrfx_clock_init+0x30>)
    5b16:	480b      	ldr	r0, [pc, #44]	; (5b44 <nrfx_clock_init+0x34>)
    5b18:	f240 1315 	movw	r3, #277	; 0x115
    5b1c:	4a0a      	ldr	r2, [pc, #40]	; (5b48 <nrfx_clock_init+0x38>)
    5b1e:	f003 fbc2 	bl	92a6 <assert_print>
    5b22:	f240 1115 	movw	r1, #277	; 0x115
    5b26:	4808      	ldr	r0, [pc, #32]	; (5b48 <nrfx_clock_init+0x38>)
    5b28:	f003 fbb6 	bl	9298 <assert_post_action>

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    5b2c:	4b07      	ldr	r3, [pc, #28]	; (5b4c <nrfx_clock_init+0x3c>)
    5b2e:	791a      	ldrb	r2, [r3, #4]
    5b30:	b922      	cbnz	r2, 5b3c <nrfx_clock_init+0x2c>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    5b32:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    5b34:	6018      	str	r0, [r3, #0]
    nrfx_err_t err_code = NRFX_SUCCESS;
    5b36:	4806      	ldr	r0, [pc, #24]	; (5b50 <nrfx_clock_init+0x40>)
        m_clock_cb.module_initialized = true;
    5b38:	711a      	strb	r2, [r3, #4]
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    5b3a:	bd08      	pop	{r3, pc}
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    5b3c:	4805      	ldr	r0, [pc, #20]	; (5b54 <nrfx_clock_init+0x44>)
    return err_code;
    5b3e:	e7fc      	b.n	5b3a <nrfx_clock_init+0x2a>
    5b40:	0000b640 	.word	0x0000b640
    5b44:	0000a2e8 	.word	0x0000a2e8
    5b48:	0000b5cf 	.word	0x0000b5cf
    5b4c:	20000e8c 	.word	0x20000e8c
    5b50:	0bad0000 	.word	0x0bad0000
    5b54:	0bad000c 	.word	0x0bad000c

00005b58 <nrfx_clock_enable>:

void nrfx_clock_enable(void)
{
    5b58:	b508      	push	{r3, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    5b5a:	4b10      	ldr	r3, [pc, #64]	; (5b9c <nrfx_clock_enable+0x44>)
    5b5c:	791b      	ldrb	r3, [r3, #4]
    5b5e:	b95b      	cbnz	r3, 5b78 <nrfx_clock_enable+0x20>
    5b60:	490f      	ldr	r1, [pc, #60]	; (5ba0 <nrfx_clock_enable+0x48>)
    5b62:	4810      	ldr	r0, [pc, #64]	; (5ba4 <nrfx_clock_enable+0x4c>)
    5b64:	f44f 7397 	mov.w	r3, #302	; 0x12e
    5b68:	4a0f      	ldr	r2, [pc, #60]	; (5ba8 <nrfx_clock_enable+0x50>)
    5b6a:	f003 fb9c 	bl	92a6 <assert_print>
    5b6e:	f44f 7197 	mov.w	r1, #302	; 0x12e
    5b72:	480d      	ldr	r0, [pc, #52]	; (5ba8 <nrfx_clock_enable+0x50>)
    5b74:	f003 fb90 	bl	9298 <assert_post_action>
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    5b78:	2005      	movs	r0, #5
    5b7a:	f7fd fce3 	bl	3544 <arch_irq_is_enabled>
    5b7e:	b910      	cbnz	r0, 5b86 <nrfx_clock_enable+0x2e>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    5b80:	2005      	movs	r0, #5
    5b82:	f7fd fcbd 	bl	3500 <arch_irq_enable>
    p_reg->LFCLKSRC = (uint32_t)(source);
    5b86:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    5b8a:	2201      	movs	r2, #1
    5b8c:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}

#if NRF_CLOCK_HAS_HFCLKSRC
NRF_STATIC_INLINE void nrf_clock_hf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source)
{
    p_reg->HFCLKSRC = (uint32_t)(source);
    5b90:	f8c3 2514 	str.w	r2, [r3, #1300]	; 0x514
                                   >> CLOCK_HFCLK192MCTRL_HCLK192M_Pos);
}

NRF_STATIC_INLINE void nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source)
{
    p_reg->HFCLK192MSRC = (uint32_t)(source);
    5b94:	f8c3 2580 	str.w	r2, [r3, #1408]	; 0x580
#if NRFX_CHECK(NRFX_POWER_ENABLED)
    nrfx_clock_irq_enabled = true;
#endif

    NRFX_LOG_INFO("Module enabled.");
}
    5b98:	bd08      	pop	{r3, pc}
    5b9a:	bf00      	nop
    5b9c:	20000e8c 	.word	0x20000e8c
    5ba0:	0000b64e 	.word	0x0000b64e
    5ba4:	0000a2e8 	.word	0x0000a2e8
    5ba8:	0000b5cf 	.word	0x0000b5cf

00005bac <nrfx_clock_start>:
    m_clock_cb.module_initialized = false;
    NRFX_LOG_INFO("Uninitialized.");
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    5bac:	b508      	push	{r3, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    5bae:	4b39      	ldr	r3, [pc, #228]	; (5c94 <nrfx_clock_start+0xe8>)
    5bb0:	791b      	ldrb	r3, [r3, #4]
    5bb2:	b95b      	cbnz	r3, 5bcc <nrfx_clock_start+0x20>
    5bb4:	4938      	ldr	r1, [pc, #224]	; (5c98 <nrfx_clock_start+0xec>)
    5bb6:	f44f 73b4 	mov.w	r3, #360	; 0x168
    5bba:	4a38      	ldr	r2, [pc, #224]	; (5c9c <nrfx_clock_start+0xf0>)
    5bbc:	4838      	ldr	r0, [pc, #224]	; (5ca0 <nrfx_clock_start+0xf4>)
    5bbe:	f003 fb72 	bl	92a6 <assert_print>
    5bc2:	f44f 71b4 	mov.w	r1, #360	; 0x168
            nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_HFAUDIO_STARTED_MASK);
            nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKAUDIOSTART);
            break;
#endif
        default:
            NRFX_ASSERT(0);
    5bc6:	4835      	ldr	r0, [pc, #212]	; (5c9c <nrfx_clock_start+0xf0>)
    5bc8:	f003 fb66 	bl	9298 <assert_post_action>
    switch (domain)
    5bcc:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    5bd0:	2803      	cmp	r0, #3
    5bd2:	d854      	bhi.n	5c7e <nrfx_clock_start+0xd2>
    5bd4:	e8df f000 	tbb	[pc, r0]
    5bd8:	473b3102 	.word	0x473b3102
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    5bdc:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    5be0:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
    5be4:	03c9      	lsls	r1, r1, #15
    5be6:	d512      	bpl.n	5c0e <nrfx_clock_start+0x62>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    5be8:	f002 0303 	and.w	r3, r2, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    5bec:	2b02      	cmp	r3, #2
    5bee:	d11d      	bne.n	5c2c <nrfx_clock_start+0x80>
    p_reg->LFCLKSRC = (uint32_t)(source);
    5bf0:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    5bf4:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5bf8:	2300      	movs	r3, #0
    5bfa:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
    5bfe:	f8d2 3104 	ldr.w	r3, [r2, #260]	; 0x104
    p_reg->INTENSET = mask;
    5c02:	2302      	movs	r3, #2
    5c04:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5c08:	2301      	movs	r3, #1
    5c0a:	6093      	str	r3, [r2, #8]
}
    5c0c:	e00d      	b.n	5c2a <nrfx_clock_start+0x7e>
            return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
    5c0e:	f8d3 2414 	ldr.w	r2, [r3, #1044]	; 0x414
                else if (nrf_clock_start_task_check(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK))
    5c12:	07d2      	lsls	r2, r2, #31
    5c14:	d50f      	bpl.n	5c36 <nrfx_clock_start+0x8a>
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    5c16:	f8d3 241c 	ldr.w	r2, [r3, #1052]	; 0x41c
    5c1a:	f002 0203 	and.w	r2, r2, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    5c1e:	3a01      	subs	r2, #1
    5c20:	2a01      	cmp	r2, #1
    5c22:	d805      	bhi.n	5c30 <nrfx_clock_start+0x84>
    p_reg->INTENSET = mask;
    5c24:	2202      	movs	r2, #2
    5c26:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
            break;
    }
}
    5c2a:	bd08      	pop	{r3, pc}
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    5c2c:	2b01      	cmp	r3, #1
    5c2e:	d002      	beq.n	5c36 <nrfx_clock_start+0x8a>
        clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    5c30:	2000      	movs	r0, #0
    5c32:	f7ff fe99 	bl	5968 <clock_stop>
        *p_lfclksrc = clock_initial_lfclksrc_get();
    5c36:	2301      	movs	r3, #1
    5c38:	e7da      	b.n	5bf0 <nrfx_clock_start+0x44>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5c3a:	2200      	movs	r2, #0
    5c3c:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    5c40:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENSET = mask;
    5c44:	2201      	movs	r2, #1
    5c46:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5c4a:	601a      	str	r2, [r3, #0]
}
    5c4c:	e7ed      	b.n	5c2a <nrfx_clock_start+0x7e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5c4e:	2200      	movs	r2, #0
    5c50:	f8c3 2124 	str.w	r2, [r3, #292]	; 0x124
    5c54:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    p_reg->INTENSET = mask;
    5c58:	f44f 7200 	mov.w	r2, #512	; 0x200
    5c5c:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5c60:	2201      	movs	r2, #1
    5c62:	621a      	str	r2, [r3, #32]
}
    5c64:	e7e1      	b.n	5c2a <nrfx_clock_start+0x7e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5c66:	2200      	movs	r2, #0
    5c68:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    5c6c:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    p_reg->INTENSET = mask;
    5c70:	f44f 7280 	mov.w	r2, #256	; 0x100
    5c74:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5c78:	2201      	movs	r2, #1
    5c7a:	619a      	str	r2, [r3, #24]
}
    5c7c:	e7d5      	b.n	5c2a <nrfx_clock_start+0x7e>
            NRFX_ASSERT(0);
    5c7e:	4909      	ldr	r1, [pc, #36]	; (5ca4 <nrfx_clock_start+0xf8>)
    5c80:	f44f 73d3 	mov.w	r3, #422	; 0x1a6
    5c84:	4a05      	ldr	r2, [pc, #20]	; (5c9c <nrfx_clock_start+0xf0>)
    5c86:	4806      	ldr	r0, [pc, #24]	; (5ca0 <nrfx_clock_start+0xf4>)
    5c88:	f003 fb0d 	bl	92a6 <assert_print>
    5c8c:	f44f 71d3 	mov.w	r1, #422	; 0x1a6
    5c90:	e799      	b.n	5bc6 <nrfx_clock_start+0x1a>
    5c92:	bf00      	nop
    5c94:	20000e8c 	.word	0x20000e8c
    5c98:	0000b64e 	.word	0x0000b64e
    5c9c:	0000b5cf 	.word	0x0000b5cf
    5ca0:	0000a2e8 	.word	0x0000a2e8
    5ca4:	0000a5f9 	.word	0x0000a5f9

00005ca8 <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
    5ca8:	b508      	push	{r3, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    5caa:	4b09      	ldr	r3, [pc, #36]	; (5cd0 <nrfx_clock_stop+0x28>)
    5cac:	791b      	ldrb	r3, [r3, #4]
    5cae:	b95b      	cbnz	r3, 5cc8 <nrfx_clock_stop+0x20>
    5cb0:	4908      	ldr	r1, [pc, #32]	; (5cd4 <nrfx_clock_stop+0x2c>)
    5cb2:	4809      	ldr	r0, [pc, #36]	; (5cd8 <nrfx_clock_stop+0x30>)
    5cb4:	f240 13ad 	movw	r3, #429	; 0x1ad
    5cb8:	4a08      	ldr	r2, [pc, #32]	; (5cdc <nrfx_clock_stop+0x34>)
    5cba:	f003 faf4 	bl	92a6 <assert_print>
    5cbe:	f240 11ad 	movw	r1, #429	; 0x1ad
    5cc2:	4806      	ldr	r0, [pc, #24]	; (5cdc <nrfx_clock_stop+0x34>)
    5cc4:	f003 fae8 	bl	9298 <assert_post_action>
    clock_stop(domain);
}
    5cc8:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    clock_stop(domain);
    5ccc:	f7ff be4c 	b.w	5968 <clock_stop>
    5cd0:	20000e8c 	.word	0x20000e8c
    5cd4:	0000b64e 	.word	0x0000b64e
    5cd8:	0000a2e8 	.word	0x0000a2e8
    5cdc:	0000b5cf 	.word	0x0000b5cf

00005ce0 <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    5ce0:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    5ce4:	b510      	push	{r4, lr}
    5ce6:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    5cea:	b152      	cbz	r2, 5d02 <nrfx_power_clock_irq_handler+0x22>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5cec:	2000      	movs	r0, #0
    5cee:	f8c3 0100 	str.w	r0, [r3, #256]	; 0x100
    5cf2:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENCLR = mask;
    5cf6:	2201      	movs	r2, #1
    5cf8:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    5cfc:	4b23      	ldr	r3, [pc, #140]	; (5d8c <nrfx_power_clock_irq_handler+0xac>)
    5cfe:	681b      	ldr	r3, [r3, #0]
    5d00:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    5d02:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    5d06:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    5d0a:	b18a      	cbz	r2, 5d30 <nrfx_power_clock_irq_handler+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5d0c:	2200      	movs	r2, #0
    5d0e:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    5d12:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    5d16:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    5d1a:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    5d1e:	f002 0203 	and.w	r2, r2, #3
    5d22:	2a01      	cmp	r2, #1
    5d24:	f04f 0102 	mov.w	r1, #2
    5d28:	d128      	bne.n	5d7c <nrfx_power_clock_irq_handler+0x9c>
    p_reg->LFCLKSRC = (uint32_t)(source);
    5d2a:	f8c3 1518 	str.w	r1, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5d2e:	609a      	str	r2, [r3, #8]
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    5d30:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    5d34:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_CAL_DONE);
    }
#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)

#if NRF_CLOCK_HAS_HFCLKAUDIO
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED))
    5d38:	b162      	cbz	r2, 5d54 <nrfx_power_clock_irq_handler+0x74>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5d3a:	2200      	movs	r2, #0
    5d3c:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    5d40:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    p_reg->INTENCLR = mask;
    5d44:	f44f 7280 	mov.w	r2, #256	; 0x100
    5d48:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HFAUDIO_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLKAUDIO_STARTED);
    5d4c:	4b0f      	ldr	r3, [pc, #60]	; (5d8c <nrfx_power_clock_irq_handler+0xac>)
    5d4e:	2004      	movs	r0, #4
    5d50:	681b      	ldr	r3, [r3, #0]
    5d52:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    5d54:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    5d58:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    }
#endif

#if NRF_CLOCK_HAS_HFCLK192M
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED))
    5d5c:	b1aa      	cbz	r2, 5d8a <nrfx_power_clock_irq_handler+0xaa>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5d5e:	2200      	movs	r2, #0
    5d60:	f8c3 2124 	str.w	r2, [r3, #292]	; 0x124
    5d64:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    p_reg->INTENCLR = mask;
    5d68:	f44f 7200 	mov.w	r2, #512	; 0x200
    5d6c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLK192MSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    5d70:	4b06      	ldr	r3, [pc, #24]	; (5d8c <nrfx_power_clock_irq_handler+0xac>)
    5d72:	2005      	movs	r0, #5
    }
#endif
}
    5d74:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    5d78:	681b      	ldr	r3, [r3, #0]
    5d7a:	4718      	bx	r3
    5d7c:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    5d80:	4b02      	ldr	r3, [pc, #8]	; (5d8c <nrfx_power_clock_irq_handler+0xac>)
    5d82:	2001      	movs	r0, #1
    5d84:	681b      	ldr	r3, [r3, #0]
    5d86:	4798      	blx	r3
    5d88:	e7d2      	b.n	5d30 <nrfx_power_clock_irq_handler+0x50>
}
    5d8a:	bd10      	pop	{r4, pc}
    5d8c:	20000e8c 	.word	0x20000e8c

00005d90 <nrfx_dppi_channel_alloc>:
    // Clear all allocated groups.
    m_allocated_groups = DPPI_AVAILABLE_GROUPS_MASK;
}

nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel)
{
    5d90:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_allocated_channels, p_channel);
    5d92:	4801      	ldr	r0, [pc, #4]	; (5d98 <nrfx_dppi_channel_alloc+0x8>)
    5d94:	f7ff bdb0 	b.w	58f8 <nrfx_flag32_alloc>
    5d98:	20000058 	.word	0x20000058

00005d9c <nrfx_dppi_channel_free>:
}

nrfx_err_t nrfx_dppi_channel_free(uint8_t channel)
{
    nrf_dppi_channels_disable(NRF_DPPIC, NRFX_BIT(channel));
    5d9c:	2301      	movs	r3, #1
    p_reg->CHENCLR = mask;
    5d9e:	4a04      	ldr	r2, [pc, #16]	; (5db0 <nrfx_dppi_channel_free+0x14>)
    5da0:	4083      	lsls	r3, r0
{
    5da2:	4601      	mov	r1, r0
    5da4:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
    return nrfx_flag32_free(&m_allocated_channels, channel);
    5da8:	4802      	ldr	r0, [pc, #8]	; (5db4 <nrfx_dppi_channel_free+0x18>)
    5daa:	f7ff bdc1 	b.w	5930 <nrfx_flag32_free>
    5dae:	bf00      	nop
    5db0:	50017000 	.word	0x50017000
    5db4:	20000058 	.word	0x20000058

00005db8 <pin_in_use_by_te>:
 *
 * @return True if pin uses GPIOTE task/event.
 */
static bool pin_in_use_by_te(uint32_t pin)
{
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    5db8:	4b03      	ldr	r3, [pc, #12]	; (5dc8 <pin_in_use_by_te+0x10>)
    5dba:	3008      	adds	r0, #8
    5dbc:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    5dc0:	f3c0 1040 	ubfx	r0, r0, #5, #1
    5dc4:	4770      	bx	lr
    5dc6:	bf00      	nop
    5dc8:	2000005c 	.word	0x2000005c

00005dcc <pin_has_trigger>:
 *
 * @return True if pin has trigger.
 */
static bool pin_has_trigger(uint32_t pin)
{
    return PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]) != NRFX_GPIOTE_TRIGGER_NONE;
    5dcc:	4b04      	ldr	r3, [pc, #16]	; (5de0 <pin_has_trigger+0x14>)
    5dce:	3008      	adds	r0, #8
    5dd0:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    5dd4:	f010 001c 	ands.w	r0, r0, #28
    5dd8:	bf18      	it	ne
    5dda:	2001      	movne	r0, #1
    5ddc:	4770      	bx	lr
    5dde:	bf00      	nop
    5de0:	2000005c 	.word	0x2000005c

00005de4 <pin_is_output>:
 *
 * @return True if pin is output.
 */
static bool pin_is_output(uint32_t pin)
{
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    5de4:	4b03      	ldr	r3, [pc, #12]	; (5df4 <pin_is_output+0x10>)
    5de6:	3008      	adds	r0, #8
    5de8:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    5dec:	f3c0 0040 	ubfx	r0, r0, #1, #1
    5df0:	4770      	bx	lr
    5df2:	bf00      	nop
    5df4:	2000005c 	.word	0x2000005c

00005df8 <call_handler>:
    nrf_gpiote_event_t event = nrfx_gpiote_in_event_get(pin);
    return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}

static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger)
{
    5df8:	b570      	push	{r4, r5, r6, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    5dfa:	4c0d      	ldr	r4, [pc, #52]	; (5e30 <call_handler+0x38>)
    5dfc:	f100 0308 	add.w	r3, r0, #8
    5e00:	f834 3013 	ldrh.w	r3, [r4, r3, lsl #1]
{
    5e04:	4605      	mov	r5, r0
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    5e06:	05da      	lsls	r2, r3, #23
{
    5e08:	460e      	mov	r6, r1
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    5e0a:	d507      	bpl.n	5e1c <call_handler+0x24>
    5e0c:	f3c3 2343 	ubfx	r3, r3, #9, #4
    nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin);

    if (handler)
    {
        handler->handler(pin, trigger, handler->p_context);
    5e10:	eb04 02c3 	add.w	r2, r4, r3, lsl #3
    5e14:	6852      	ldr	r2, [r2, #4]
    5e16:	f854 3033 	ldr.w	r3, [r4, r3, lsl #3]
    5e1a:	4798      	blx	r3
    }
    if (m_cb.global_handler.handler)
    5e1c:	68a3      	ldr	r3, [r4, #8]
    5e1e:	b12b      	cbz	r3, 5e2c <call_handler+0x34>
    {
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    5e20:	4631      	mov	r1, r6
    5e22:	4628      	mov	r0, r5
    5e24:	68e2      	ldr	r2, [r4, #12]
    }
}
    5e26:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    5e2a:	4718      	bx	r3
}
    5e2c:	bd70      	pop	{r4, r5, r6, pc}
    5e2e:	bf00      	nop
    5e30:	2000005c 	.word	0x2000005c

00005e34 <release_handler>:
{
    5e34:	b510      	push	{r4, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    5e36:	4a18      	ldr	r2, [pc, #96]	; (5e98 <release_handler+0x64>)
    5e38:	3008      	adds	r0, #8
    5e3a:	f832 3010 	ldrh.w	r3, [r2, r0, lsl #1]
    5e3e:	05d9      	lsls	r1, r3, #23
    5e40:	d51d      	bpl.n	5e7e <release_handler+0x4a>
    5e42:	f3c3 2143 	ubfx	r1, r3, #9, #4
    m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK;
    5e46:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    5e4a:	f822 3010 	strh.w	r3, [r2, r0, lsl #1]
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    5e4e:	2000      	movs	r0, #0
    5e50:	f102 040e 	add.w	r4, r2, #14
        if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id)
    5e54:	f834 3f02 	ldrh.w	r3, [r4, #2]!
    5e58:	f413 7f80 	tst.w	r3, #256	; 0x100
    5e5c:	d003      	beq.n	5e66 <release_handler+0x32>
    5e5e:	f3c3 2343 	ubfx	r3, r3, #9, #4
    5e62:	4299      	cmp	r1, r3
    5e64:	d00b      	beq.n	5e7e <release_handler+0x4a>
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    5e66:	3001      	adds	r0, #1
    5e68:	2830      	cmp	r0, #48	; 0x30
    5e6a:	d1f3      	bne.n	5e54 <release_handler+0x20>
        m_cb.handlers[handler_id].handler = NULL;
    5e6c:	2300      	movs	r3, #0
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    5e6e:	480b      	ldr	r0, [pc, #44]	; (5e9c <release_handler+0x68>)
        m_cb.handlers[handler_id].handler = NULL;
    5e70:	f842 3031 	str.w	r3, [r2, r1, lsl #3]
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    5e74:	f7ff fd5c 	bl	5930 <nrfx_flag32_free>
        NRFX_ASSERT(err == NRFX_SUCCESS);
    5e78:	4b09      	ldr	r3, [pc, #36]	; (5ea0 <release_handler+0x6c>)
    5e7a:	4298      	cmp	r0, r3
    5e7c:	d100      	bne.n	5e80 <release_handler+0x4c>
}
    5e7e:	bd10      	pop	{r4, pc}
        NRFX_ASSERT(err == NRFX_SUCCESS);
    5e80:	4908      	ldr	r1, [pc, #32]	; (5ea4 <release_handler+0x70>)
    5e82:	4809      	ldr	r0, [pc, #36]	; (5ea8 <release_handler+0x74>)
    5e84:	f44f 7399 	mov.w	r3, #306	; 0x132
    5e88:	4a08      	ldr	r2, [pc, #32]	; (5eac <release_handler+0x78>)
    5e8a:	f003 fa0c 	bl	92a6 <assert_print>
    5e8e:	f44f 7199 	mov.w	r1, #306	; 0x132
    5e92:	4806      	ldr	r0, [pc, #24]	; (5eac <release_handler+0x78>)
    5e94:	f003 fa00 	bl	9298 <assert_post_action>
    5e98:	2000005c 	.word	0x2000005c
    5e9c:	200000d0 	.word	0x200000d0
    5ea0:	0bad0000 	.word	0x0bad0000
    5ea4:	0000a72d 	.word	0x0000a72d
    5ea8:	0000a2e8 	.word	0x0000a2e8
    5eac:	0000b681 	.word	0x0000b681

00005eb0 <pin_handler_trigger_uninit>:
{
    5eb0:	b538      	push	{r3, r4, r5, lr}
    5eb2:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    5eb4:	f7ff ff80 	bl	5db8 <pin_in_use_by_te>
    5eb8:	4c0b      	ldr	r4, [pc, #44]	; (5ee8 <pin_handler_trigger_uninit+0x38>)
    5eba:	f102 0508 	add.w	r5, r2, #8
    5ebe:	b160      	cbz	r0, 5eda <pin_handler_trigger_uninit+0x2a>
                         ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}

NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
    p_reg->CONFIG[idx] = 0;
    5ec0:	2100      	movs	r1, #0
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    5ec2:	f834 3015 	ldrh.w	r3, [r4, r5, lsl #1]
        nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin));
    5ec6:	0b5b      	lsrs	r3, r3, #13
    5ec8:	009b      	lsls	r3, r3, #2
    5eca:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    5ece:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    5ed2:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
#if defined(NRF9160_XXAA) || defined(NRF5340_XXAA)
    p_reg->CONFIG[idx] = 0;
    5ed6:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    release_handler(pin);
    5eda:	4610      	mov	r0, r2
    5edc:	f7ff ffaa 	bl	5e34 <release_handler>
    m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED;
    5ee0:	2300      	movs	r3, #0
    5ee2:	f824 3015 	strh.w	r3, [r4, r5, lsl #1]
}
    5ee6:	bd38      	pop	{r3, r4, r5, pc}
    5ee8:	2000005c 	.word	0x2000005c

00005eec <nrf_gpio_pin_port_decode>:
{
    5eec:	b508      	push	{r3, lr}
    NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
    5eee:	6802      	ldr	r2, [r0, #0]
{
    5ef0:	4601      	mov	r1, r0
    NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
    5ef2:	4610      	mov	r0, r2
    5ef4:	f003 fd97 	bl	9a26 <nrf_gpio_pin_present_check>
    5ef8:	b958      	cbnz	r0, 5f12 <nrf_gpio_pin_port_decode+0x26>
    5efa:	4910      	ldr	r1, [pc, #64]	; (5f3c <nrf_gpio_pin_port_decode+0x50>)
    5efc:	f240 2347 	movw	r3, #583	; 0x247
    5f00:	4a0f      	ldr	r2, [pc, #60]	; (5f40 <nrf_gpio_pin_port_decode+0x54>)
    5f02:	4810      	ldr	r0, [pc, #64]	; (5f44 <nrf_gpio_pin_port_decode+0x58>)
    5f04:	f003 f9cf 	bl	92a6 <assert_print>
    5f08:	f240 2147 	movw	r1, #583	; 0x247
            NRFX_ASSERT(0);
    5f0c:	480c      	ldr	r0, [pc, #48]	; (5f40 <nrf_gpio_pin_port_decode+0x54>)
    5f0e:	f003 f9c3 	bl	9298 <assert_post_action>
    *p_pin = pin_number & 0x1F;
    5f12:	f002 031f 	and.w	r3, r2, #31
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    5f16:	0952      	lsrs	r2, r2, #5
    *p_pin = pin_number & 0x1F;
    5f18:	600b      	str	r3, [r1, #0]
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    5f1a:	d00b      	beq.n	5f34 <nrf_gpio_pin_port_decode+0x48>
    5f1c:	2a01      	cmp	r2, #1
    5f1e:	d00b      	beq.n	5f38 <nrf_gpio_pin_port_decode+0x4c>
            NRFX_ASSERT(0);
    5f20:	4909      	ldr	r1, [pc, #36]	; (5f48 <nrf_gpio_pin_port_decode+0x5c>)
    5f22:	f44f 7313 	mov.w	r3, #588	; 0x24c
    5f26:	4a06      	ldr	r2, [pc, #24]	; (5f40 <nrf_gpio_pin_port_decode+0x54>)
    5f28:	4806      	ldr	r0, [pc, #24]	; (5f44 <nrf_gpio_pin_port_decode+0x58>)
    5f2a:	f003 f9bc 	bl	92a6 <assert_print>
    5f2e:	f44f 7113 	mov.w	r1, #588	; 0x24c
    5f32:	e7eb      	b.n	5f0c <nrf_gpio_pin_port_decode+0x20>
        case 0: return NRF_P0;
    5f34:	4805      	ldr	r0, [pc, #20]	; (5f4c <nrf_gpio_pin_port_decode+0x60>)
}
    5f36:	bd08      	pop	{r3, pc}
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    5f38:	4805      	ldr	r0, [pc, #20]	; (5f50 <nrf_gpio_pin_port_decode+0x64>)
    5f3a:	e7fc      	b.n	5f36 <nrf_gpio_pin_port_decode+0x4a>
    5f3c:	0000b3a1 	.word	0x0000b3a1
    5f40:	0000b36e 	.word	0x0000b36e
    5f44:	0000a2e8 	.word	0x0000a2e8
    5f48:	0000a5f9 	.word	0x0000a5f9
    5f4c:	50842500 	.word	0x50842500
    5f50:	50842800 	.word	0x50842800

00005f54 <nrfx_gpiote_input_configure>:
{
    5f54:	b5f0      	push	{r4, r5, r6, r7, lr}
    5f56:	4604      	mov	r4, r0
    5f58:	4617      	mov	r7, r2
    5f5a:	461d      	mov	r5, r3
    5f5c:	b085      	sub	sp, #20
    if (p_input_config)
    5f5e:	b1d9      	cbz	r1, 5f98 <nrfx_gpiote_input_configure+0x44>
        if (pin_is_task_output(pin))
    5f60:	f003 fd72 	bl	9a48 <pin_is_task_output>
    5f64:	bb00      	cbnz	r0, 5fa8 <nrfx_gpiote_input_configure+0x54>
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    5f66:	460b      	mov	r3, r1
    5f68:	e9cd 0000 	strd	r0, r0, [sp]
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT;
    5f6c:	f88d 000e 	strb.w	r0, [sp, #14]
        nrf_gpio_pin_input_t input_connect = NRF_GPIO_PIN_INPUT_CONNECT;
    5f70:	f88d 000f 	strb.w	r0, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    5f74:	f10d 020f 	add.w	r2, sp, #15
    5f78:	f10d 010e 	add.w	r1, sp, #14
    5f7c:	4620      	mov	r0, r4
    5f7e:	f003 fd6e 	bl	9a5e <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    5f82:	4a44      	ldr	r2, [pc, #272]	; (6094 <nrfx_gpiote_input_configure+0x140>)
    5f84:	f104 0108 	add.w	r1, r4, #8
        m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT;
    5f88:	f832 3011 	ldrh.w	r3, [r2, r1, lsl #1]
    5f8c:	f023 0302 	bic.w	r3, r3, #2
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    5f90:	f043 0301 	orr.w	r3, r3, #1
    5f94:	f822 3011 	strh.w	r3, [r2, r1, lsl #1]
    if (p_trigger_config)
    5f98:	b36f      	cbz	r7, 5ff6 <nrfx_gpiote_input_configure+0xa2>
        if (pin_is_output(pin))
    5f9a:	4620      	mov	r0, r4
        nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger;
    5f9c:	783e      	ldrb	r6, [r7, #0]
        bool use_evt = p_trigger_config->p_in_channel ? true : false;
    5f9e:	687a      	ldr	r2, [r7, #4]
        if (pin_is_output(pin))
    5fa0:	f7ff ff20 	bl	5de4 <pin_is_output>
    5fa4:	b110      	cbz	r0, 5fac <nrfx_gpiote_input_configure+0x58>
            if (use_evt)
    5fa6:	b1da      	cbz	r2, 5fe0 <nrfx_gpiote_input_configure+0x8c>
            return NRFX_ERROR_INVALID_PARAM;
    5fa8:	483b      	ldr	r0, [pc, #236]	; (6098 <nrfx_gpiote_input_configure+0x144>)
    5faa:	e026      	b.n	5ffa <nrfx_gpiote_input_configure+0xa6>
            m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED);
    5fac:	4839      	ldr	r0, [pc, #228]	; (6094 <nrfx_gpiote_input_configure+0x140>)
    5fae:	f104 0c08 	add.w	ip, r4, #8
    5fb2:	f830 101c 	ldrh.w	r1, [r0, ip, lsl #1]
    5fb6:	f021 0120 	bic.w	r1, r1, #32
    5fba:	04c9      	lsls	r1, r1, #19
    5fbc:	0cc9      	lsrs	r1, r1, #19
    5fbe:	f820 101c 	strh.w	r1, [r0, ip, lsl #1]
            if (use_evt)
    5fc2:	b16a      	cbz	r2, 5fe0 <nrfx_gpiote_input_configure+0x8c>
                if (!edge)
    5fc4:	2e03      	cmp	r6, #3
    5fc6:	d8ef      	bhi.n	5fa8 <nrfx_gpiote_input_configure+0x54>
                uint8_t ch = *p_trigger_config->p_in_channel;
    5fc8:	687b      	ldr	r3, [r7, #4]
    5fca:	781f      	ldrb	r7, [r3, #0]
                if (trigger == NRFX_GPIOTE_TRIGGER_NONE)
    5fcc:	00ba      	lsls	r2, r7, #2
    5fce:	f102 42a0 	add.w	r2, r2, #1342177280	; 0x50000000
    5fd2:	f502 4250 	add.w	r2, r2, #53248	; 0xd000
    5fd6:	b996      	cbnz	r6, 5ffe <nrfx_gpiote_input_configure+0xaa>
    p_reg->CONFIG[idx] = 0;
    5fd8:	f8c2 6510 	str.w	r6, [r2, #1296]	; 0x510
    p_reg->CONFIG[idx] = 0;
    5fdc:	f8c2 6510 	str.w	r6, [r2, #1296]	; 0x510
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    5fe0:	4a2c      	ldr	r2, [pc, #176]	; (6094 <nrfx_gpiote_input_configure+0x140>)
    5fe2:	f104 0108 	add.w	r1, r4, #8
        m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK;
    5fe6:	f832 3011 	ldrh.w	r3, [r2, r1, lsl #1]
    5fea:	f023 031c 	bic.w	r3, r3, #28
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    5fee:	ea43 0386 	orr.w	r3, r3, r6, lsl #2
    5ff2:	f822 3011 	strh.w	r3, [r2, r1, lsl #1]
    if (p_handler_config)
    5ff6:	bb15      	cbnz	r5, 603e <nrfx_gpiote_input_configure+0xea>
        err = NRFX_SUCCESS;
    5ff8:	4828      	ldr	r0, [pc, #160]	; (609c <nrfx_gpiote_input_configure+0x148>)
}
    5ffa:	b005      	add	sp, #20
    5ffc:	bdf0      	pop	{r4, r5, r6, r7, pc}
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    5ffe:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
                    m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    6002:	ea41 3147 	orr.w	r1, r1, r7, lsl #13
    6006:	f023 0303 	bic.w	r3, r3, #3
    600a:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    600e:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
    6012:	f041 0120 	orr.w	r1, r1, #32
    6016:	f423 334f 	bic.w	r3, r3, #211968	; 0x33c00
    601a:	f423 7340 	bic.w	r3, r3, #768	; 0x300
    601e:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    6022:	0223      	lsls	r3, r4, #8
    6024:	f8d2 e510 	ldr.w	lr, [r2, #1296]	; 0x510
    6028:	f403 537c 	and.w	r3, r3, #16128	; 0x3f00
    602c:	ea43 4306 	orr.w	r3, r3, r6, lsl #16
    6030:	ea43 030e 	orr.w	r3, r3, lr
    6034:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
    6038:	f820 101c 	strh.w	r1, [r0, ip, lsl #1]
    603c:	e7d0      	b.n	5fe0 <nrfx_gpiote_input_configure+0x8c>
    release_handler(pin);
    603e:	4620      	mov	r0, r4
        err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context);
    6040:	e9d5 6700 	ldrd	r6, r7, [r5]
    release_handler(pin);
    6044:	f7ff fef6 	bl	5e34 <release_handler>
    if (!handler)
    6048:	2e00      	cmp	r6, #0
    604a:	d0d5      	beq.n	5ff8 <nrfx_gpiote_input_configure+0xa4>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    604c:	4d11      	ldr	r5, [pc, #68]	; (6094 <nrfx_gpiote_input_configure+0x140>)
    604e:	e9d5 2300 	ldrd	r2, r3, [r5]
    6052:	4296      	cmp	r6, r2
    6054:	d101      	bne.n	605a <nrfx_gpiote_input_configure+0x106>
    6056:	429f      	cmp	r7, r3
    6058:	d019      	beq.n	608e <nrfx_gpiote_input_configure+0x13a>
        err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id);
    605a:	4811      	ldr	r0, [pc, #68]	; (60a0 <nrfx_gpiote_input_configure+0x14c>)
    605c:	f10d 010f 	add.w	r1, sp, #15
    6060:	f7ff fc4a 	bl	58f8 <nrfx_flag32_alloc>
        if (err != NRFX_SUCCESS)
    6064:	4b0d      	ldr	r3, [pc, #52]	; (609c <nrfx_gpiote_input_configure+0x148>)
    6066:	4298      	cmp	r0, r3
    6068:	d1c7      	bne.n	5ffa <nrfx_gpiote_input_configure+0xa6>
        handler_id = (int32_t)id;
    606a:	f89d 200f 	ldrb.w	r2, [sp, #15]
    m_cb.handlers[handler_id].p_context = p_context;
    606e:	eb05 03c2 	add.w	r3, r5, r2, lsl #3
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    6072:	f104 0008 	add.w	r0, r4, #8
    m_cb.handlers[handler_id].p_context = p_context;
    6076:	605f      	str	r7, [r3, #4]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    6078:	f835 3010 	ldrh.w	r3, [r5, r0, lsl #1]
    m_cb.handlers[handler_id].handler = handler;
    607c:	f845 6032 	str.w	r6, [r5, r2, lsl #3]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    6080:	ea43 2342 	orr.w	r3, r3, r2, lsl #9
    6084:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    6088:	f825 3010 	strh.w	r3, [r5, r0, lsl #1]
    return NRFX_SUCCESS;
    608c:	e7b4      	b.n	5ff8 <nrfx_gpiote_input_configure+0xa4>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    608e:	2200      	movs	r2, #0
    6090:	e7ed      	b.n	606e <nrfx_gpiote_input_configure+0x11a>
    6092:	bf00      	nop
    6094:	2000005c 	.word	0x2000005c
    6098:	0bad0004 	.word	0x0bad0004
    609c:	0bad0000 	.word	0x0bad0000
    60a0:	200000d0 	.word	0x200000d0

000060a4 <nrfx_gpiote_output_configure>:
{
    60a4:	b5f0      	push	{r4, r5, r6, r7, lr}
    60a6:	4604      	mov	r4, r0
    60a8:	4615      	mov	r5, r2
    60aa:	b085      	sub	sp, #20
    if (p_config)
    60ac:	b321      	cbz	r1, 60f8 <nrfx_gpiote_output_configure+0x54>
    return !pin_is_output(pin);
    60ae:	f7ff fe99 	bl	5de4 <pin_is_output>
        if (pin_is_input(pin) && pin_in_use_by_te(pin))
    60b2:	b920      	cbnz	r0, 60be <nrfx_gpiote_output_configure+0x1a>
    60b4:	4620      	mov	r0, r4
    60b6:	f7ff fe7f 	bl	5db8 <pin_in_use_by_te>
    60ba:	2800      	cmp	r0, #0
    60bc:	d161      	bne.n	6182 <nrfx_gpiote_output_configure+0xde>
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    60be:	4620      	mov	r0, r4
    60c0:	f7ff fe84 	bl	5dcc <pin_has_trigger>
    60c4:	b110      	cbz	r0, 60cc <nrfx_gpiote_output_configure+0x28>
    60c6:	784b      	ldrb	r3, [r1, #1]
    60c8:	2b01      	cmp	r3, #1
    60ca:	d05a      	beq.n	6182 <nrfx_gpiote_output_configure+0xde>
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_OUTPUT;
    60cc:	2301      	movs	r3, #1
    60ce:	f88d 300f 	strb.w	r3, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &p_config->input_connect, &p_config->pull,
    60d2:	2300      	movs	r3, #0
    60d4:	1c4a      	adds	r2, r1, #1
    60d6:	e9cd 1300 	strd	r1, r3, [sp]
    60da:	4620      	mov	r0, r4
    60dc:	1c8b      	adds	r3, r1, #2
    60de:	f10d 010f 	add.w	r1, sp, #15
    60e2:	f003 fcbc 	bl	9a5e <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT;
    60e6:	4a28      	ldr	r2, [pc, #160]	; (6188 <nrfx_gpiote_output_configure+0xe4>)
    60e8:	f104 0108 	add.w	r1, r4, #8
    60ec:	f832 3011 	ldrh.w	r3, [r2, r1, lsl #1]
    60f0:	f043 0303 	orr.w	r3, r3, #3
    60f4:	f822 3011 	strh.w	r3, [r2, r1, lsl #1]
    if (p_task_config)
    60f8:	b915      	cbnz	r5, 6100 <nrfx_gpiote_output_configure+0x5c>
    return NRFX_SUCCESS;
    60fa:	4824      	ldr	r0, [pc, #144]	; (618c <nrfx_gpiote_output_configure+0xe8>)
}
    60fc:	b005      	add	sp, #20
    60fe:	bdf0      	pop	{r4, r5, r6, r7, pc}
    return !pin_is_output(pin);
    6100:	4620      	mov	r0, r4
    6102:	f7ff fe6f 	bl	5de4 <pin_is_output>
        if (pin_is_input(pin))
    6106:	2800      	cmp	r0, #0
    6108:	d03b      	beq.n	6182 <nrfx_gpiote_output_configure+0xde>
        uint32_t ch = p_task_config->task_ch;
    610a:	f895 c000 	ldrb.w	ip, [r5]
    p_reg->CONFIG[idx] = 0;
    610e:	2300      	movs	r3, #0
    6110:	4661      	mov	r1, ip
        m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK);
    6112:	4e1d      	ldr	r6, [pc, #116]	; (6188 <nrfx_gpiote_output_configure+0xe4>)
    6114:	f104 0708 	add.w	r7, r4, #8
    6118:	f836 0017 	ldrh.w	r0, [r6, r7, lsl #1]
    611c:	0089      	lsls	r1, r1, #2
    611e:	f020 0020 	bic.w	r0, r0, #32
    6122:	f101 41a0 	add.w	r1, r1, #1342177280	; 0x50000000
    6126:	04c0      	lsls	r0, r0, #19
    6128:	f501 4150 	add.w	r1, r1, #53248	; 0xd000
    612c:	0cc0      	lsrs	r0, r0, #19
    612e:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    6132:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    p_reg->CONFIG[idx] = 0;
    6136:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
        if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE)
    613a:	786a      	ldrb	r2, [r5, #1]
    613c:	2a00      	cmp	r2, #0
    613e:	d0dc      	beq.n	60fa <nrfx_gpiote_output_configure+0x56>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
    6140:	f8d1 3510 	ldr.w	r3, [r1, #1296]	; 0x510
                                      p_task_config->init_val);
    6144:	78ad      	ldrb	r5, [r5, #2]
    6146:	f423 1399 	bic.w	r3, r3, #1253376	; 0x132000
    614a:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    614e:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    6152:	f8d1 e510 	ldr.w	lr, [r1, #1296]	; 0x510
    6156:	0223      	lsls	r3, r4, #8
    6158:	f403 537c 	and.w	r3, r3, #16128	; 0x3f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    615c:	0412      	lsls	r2, r2, #16
    615e:	f402 3240 	and.w	r2, r2, #196608	; 0x30000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    6162:	ea43 030e 	orr.w	r3, r3, lr
    6166:	4313      	orrs	r3, r2
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    6168:	052a      	lsls	r2, r5, #20
    616a:	f402 1280 	and.w	r2, r2, #1048576	; 0x100000
            m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    616e:	ea40 304c 	orr.w	r0, r0, ip, lsl #13
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    6172:	4313      	orrs	r3, r2
    6174:	f040 0020 	orr.w	r0, r0, #32
    6178:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    617c:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    6180:	e7bb      	b.n	60fa <nrfx_gpiote_output_configure+0x56>
{
    6182:	4803      	ldr	r0, [pc, #12]	; (6190 <nrfx_gpiote_output_configure+0xec>)
    6184:	e7ba      	b.n	60fc <nrfx_gpiote_output_configure+0x58>
    6186:	bf00      	nop
    6188:	2000005c 	.word	0x2000005c
    618c:	0bad0000 	.word	0x0bad0000
    6190:	0bad0004 	.word	0x0bad0004

00006194 <nrfx_gpiote_global_callback_set>:
    m_cb.global_handler.handler = handler;
    6194:	4b01      	ldr	r3, [pc, #4]	; (619c <nrfx_gpiote_global_callback_set+0x8>)
    m_cb.global_handler.p_context = p_context;
    6196:	e9c3 0102 	strd	r0, r1, [r3, #8]
}
    619a:	4770      	bx	lr
    619c:	2000005c 	.word	0x2000005c

000061a0 <nrfx_gpiote_channel_get>:
{
    61a0:	4602      	mov	r2, r0
    61a2:	b508      	push	{r3, lr}
    NRFX_ASSERT(p_channel);
    61a4:	b959      	cbnz	r1, 61be <nrfx_gpiote_channel_get+0x1e>
    61a6:	490c      	ldr	r1, [pc, #48]	; (61d8 <nrfx_gpiote_channel_get+0x38>)
    61a8:	480c      	ldr	r0, [pc, #48]	; (61dc <nrfx_gpiote_channel_get+0x3c>)
    61aa:	f240 2335 	movw	r3, #565	; 0x235
    61ae:	4a0c      	ldr	r2, [pc, #48]	; (61e0 <nrfx_gpiote_channel_get+0x40>)
    61b0:	f003 f879 	bl	92a6 <assert_print>
    61b4:	f240 2135 	movw	r1, #565	; 0x235
    61b8:	4809      	ldr	r0, [pc, #36]	; (61e0 <nrfx_gpiote_channel_get+0x40>)
    61ba:	f003 f86d 	bl	9298 <assert_post_action>
    if (pin_in_use_by_te(pin))
    61be:	f7ff fdfb 	bl	5db8 <pin_in_use_by_te>
    61c2:	b138      	cbz	r0, 61d4 <nrfx_gpiote_channel_get+0x34>
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    61c4:	4b07      	ldr	r3, [pc, #28]	; (61e4 <nrfx_gpiote_channel_get+0x44>)
    61c6:	3208      	adds	r2, #8
    61c8:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
        return NRFX_SUCCESS;
    61cc:	4806      	ldr	r0, [pc, #24]	; (61e8 <nrfx_gpiote_channel_get+0x48>)
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    61ce:	0b5b      	lsrs	r3, r3, #13
    61d0:	700b      	strb	r3, [r1, #0]
}
    61d2:	bd08      	pop	{r3, pc}
        return NRFX_ERROR_INVALID_PARAM;
    61d4:	4805      	ldr	r0, [pc, #20]	; (61ec <nrfx_gpiote_channel_get+0x4c>)
    61d6:	e7fc      	b.n	61d2 <nrfx_gpiote_channel_get+0x32>
    61d8:	0000b6bf 	.word	0x0000b6bf
    61dc:	0000a2e8 	.word	0x0000a2e8
    61e0:	0000b681 	.word	0x0000b681
    61e4:	2000005c 	.word	0x2000005c
    61e8:	0bad0000 	.word	0x0bad0000
    61ec:	0bad0004 	.word	0x0bad0004

000061f0 <nrfx_gpiote_init>:
{
    61f0:	b538      	push	{r3, r4, r5, lr}
    if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    61f2:	4c0f      	ldr	r4, [pc, #60]	; (6230 <nrfx_gpiote_init+0x40>)
    61f4:	f894 5078 	ldrb.w	r5, [r4, #120]	; 0x78
    61f8:	b9bd      	cbnz	r5, 622a <nrfx_gpiote_init+0x3a>
    memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags));
    61fa:	2260      	movs	r2, #96	; 0x60
    61fc:	4629      	mov	r1, r5
    61fe:	f104 0010 	add.w	r0, r4, #16
    6202:	f003 fa10 	bl	9626 <memset>
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE));
    6206:	200d      	movs	r0, #13
    6208:	f7fd f97a 	bl	3500 <arch_irq_enable>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    620c:	4b09      	ldr	r3, [pc, #36]	; (6234 <nrfx_gpiote_init+0x44>)
    return err_code;
    620e:	480a      	ldr	r0, [pc, #40]	; (6238 <nrfx_gpiote_init+0x48>)
    6210:	f8c3 517c 	str.w	r5, [r3, #380]	; 0x17c
    6214:	f8d3 217c 	ldr.w	r2, [r3, #380]	; 0x17c
    p_reg->INTENSET = mask;
    6218:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    621c:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    m_cb.state = NRFX_DRV_STATE_INITIALIZED;
    6220:	2301      	movs	r3, #1
    6222:	f884 3078 	strb.w	r3, [r4, #120]	; 0x78
    m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS);
    6226:	6763      	str	r3, [r4, #116]	; 0x74
}
    6228:	bd38      	pop	{r3, r4, r5, pc}
        return err_code;
    622a:	4804      	ldr	r0, [pc, #16]	; (623c <nrfx_gpiote_init+0x4c>)
    622c:	e7fc      	b.n	6228 <nrfx_gpiote_init+0x38>
    622e:	bf00      	nop
    6230:	2000005c 	.word	0x2000005c
    6234:	5000d000 	.word	0x5000d000
    6238:	0bad0000 	.word	0x0bad0000
    623c:	0bad0005 	.word	0x0bad0005

00006240 <nrfx_gpiote_is_init>:
    return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false;
    6240:	4b03      	ldr	r3, [pc, #12]	; (6250 <nrfx_gpiote_is_init+0x10>)
    6242:	f893 0078 	ldrb.w	r0, [r3, #120]	; 0x78
}
    6246:	3800      	subs	r0, #0
    6248:	bf18      	it	ne
    624a:	2001      	movne	r0, #1
    624c:	4770      	bx	lr
    624e:	bf00      	nop
    6250:	2000005c 	.word	0x2000005c

00006254 <nrfx_gpiote_channel_free>:
{
    6254:	4601      	mov	r1, r0
    return nrfx_flag32_free(&m_cb.available_channels_mask, channel);
    6256:	4801      	ldr	r0, [pc, #4]	; (625c <nrfx_gpiote_channel_free+0x8>)
    6258:	f7ff bb6a 	b.w	5930 <nrfx_flag32_free>
    625c:	200000cc 	.word	0x200000cc

00006260 <nrfx_gpiote_channel_alloc>:
{
    6260:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel);
    6262:	4801      	ldr	r0, [pc, #4]	; (6268 <nrfx_gpiote_channel_alloc+0x8>)
    6264:	f7ff bb48 	b.w	58f8 <nrfx_flag32_alloc>
    6268:	200000cc 	.word	0x200000cc

0000626c <nrfx_gpiote_trigger_enable>:
{
    626c:	b537      	push	{r0, r1, r2, r4, r5, lr}
    626e:	4604      	mov	r4, r0
    NRFX_ASSERT(pin_has_trigger(pin));
    6270:	f7ff fdac 	bl	5dcc <pin_has_trigger>
    6274:	b958      	cbnz	r0, 628e <nrfx_gpiote_trigger_enable+0x22>
    6276:	492d      	ldr	r1, [pc, #180]	; (632c <nrfx_gpiote_trigger_enable+0xc0>)
    6278:	f240 33df 	movw	r3, #991	; 0x3df
    627c:	4a2c      	ldr	r2, [pc, #176]	; (6330 <nrfx_gpiote_trigger_enable+0xc4>)
    627e:	482d      	ldr	r0, [pc, #180]	; (6334 <nrfx_gpiote_trigger_enable+0xc8>)
    6280:	f003 f811 	bl	92a6 <assert_print>
    6284:	f240 31df 	movw	r1, #991	; 0x3df
        NRFX_ASSERT(int_enable);
    6288:	4829      	ldr	r0, [pc, #164]	; (6330 <nrfx_gpiote_trigger_enable+0xc4>)
    628a:	f003 f805 	bl	9298 <assert_post_action>
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    628e:	4620      	mov	r0, r4
    6290:	f7ff fd92 	bl	5db8 <pin_in_use_by_te>
    6294:	4a28      	ldr	r2, [pc, #160]	; (6338 <nrfx_gpiote_trigger_enable+0xcc>)
    6296:	f104 0508 	add.w	r5, r4, #8
    629a:	b1f8      	cbz	r0, 62dc <nrfx_gpiote_trigger_enable+0x70>
    return !pin_is_output(pin);
    629c:	4620      	mov	r0, r4
    629e:	f7ff fda1 	bl	5de4 <pin_is_output>
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    62a2:	b9d8      	cbnz	r0, 62dc <nrfx_gpiote_trigger_enable+0x70>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    62a4:	f832 2015 	ldrh.w	r2, [r2, r5, lsl #1]
    62a8:	0b52      	lsrs	r2, r2, #13
#endif

NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
{
    NRFX_ASSERT(index < GPIOTE_CH_NUM);
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    62aa:	0093      	lsls	r3, r2, #2
    return ((uint32_t)p_reg + event);
    62ac:	f103 44a0 	add.w	r4, r3, #1342177280	; 0x50000000
    62b0:	f504 4451 	add.w	r4, r4, #53504	; 0xd100
    62b4:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    62b8:	6020      	str	r0, [r4, #0]
    62ba:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    62be:	6820      	ldr	r0, [r4, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    62c0:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    62c4:	f040 0001 	orr.w	r0, r0, #1
    62c8:	f8c3 0510 	str.w	r0, [r3, #1296]	; 0x510
        if (int_enable)
    62cc:	b121      	cbz	r1, 62d8 <nrfx_gpiote_trigger_enable+0x6c>
            nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch));
    62ce:	2301      	movs	r3, #1
    62d0:	4093      	lsls	r3, r2
    p_reg->INTENSET = mask;
    62d2:	4a1a      	ldr	r2, [pc, #104]	; (633c <nrfx_gpiote_trigger_enable+0xd0>)
    62d4:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    62d8:	b003      	add	sp, #12
    62da:	bd30      	pop	{r4, r5, pc}
        NRFX_ASSERT(int_enable);
    62dc:	b949      	cbnz	r1, 62f2 <nrfx_gpiote_trigger_enable+0x86>
    62de:	4918      	ldr	r1, [pc, #96]	; (6340 <nrfx_gpiote_trigger_enable+0xd4>)
    62e0:	f240 33ee 	movw	r3, #1006	; 0x3ee
    62e4:	4a12      	ldr	r2, [pc, #72]	; (6330 <nrfx_gpiote_trigger_enable+0xc4>)
    62e6:	4813      	ldr	r0, [pc, #76]	; (6334 <nrfx_gpiote_trigger_enable+0xc8>)
    62e8:	f002 ffdd 	bl	92a6 <assert_print>
    62ec:	f240 31ee 	movw	r1, #1006	; 0x3ee
    62f0:	e7ca      	b.n	6288 <nrfx_gpiote_trigger_enable+0x1c>
    nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    62f2:	f832 3015 	ldrh.w	r3, [r2, r5, lsl #1]
    62f6:	f3c3 0382 	ubfx	r3, r3, #2, #3
    if (trigger == NRFX_GPIOTE_TRIGGER_LOW)
    62fa:	2b04      	cmp	r3, #4
    62fc:	d011      	beq.n	6322 <nrfx_gpiote_trigger_enable+0xb6>
    else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH)
    62fe:	2b05      	cmp	r3, #5
    6300:	d011      	beq.n	6326 <nrfx_gpiote_trigger_enable+0xba>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    6302:	a801      	add	r0, sp, #4
    6304:	9401      	str	r4, [sp, #4]
    6306:	f7ff fdf1 	bl	5eec <nrf_gpio_pin_port_decode>
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    630a:	9b01      	ldr	r3, [sp, #4]
    return p_reg->IN;
    630c:	6901      	ldr	r1, [r0, #16]
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    630e:	40d9      	lsrs	r1, r3
    6310:	f001 0101 	and.w	r1, r1, #1
    6314:	3102      	adds	r1, #2
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    6316:	4620      	mov	r0, r4
}
    6318:	b003      	add	sp, #12
    631a:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    631e:	f003 bbeb 	b.w	9af8 <nrf_gpio_cfg_sense_set>
        sense = NRF_GPIO_PIN_SENSE_LOW;
    6322:	2103      	movs	r1, #3
    6324:	e7f7      	b.n	6316 <nrfx_gpiote_trigger_enable+0xaa>
        sense = NRF_GPIO_PIN_SENSE_HIGH;
    6326:	2102      	movs	r1, #2
    6328:	e7f5      	b.n	6316 <nrfx_gpiote_trigger_enable+0xaa>
    632a:	bf00      	nop
    632c:	0000b6c9 	.word	0x0000b6c9
    6330:	0000b681 	.word	0x0000b681
    6334:	0000a2e8 	.word	0x0000a2e8
    6338:	2000005c 	.word	0x2000005c
    633c:	5000d000 	.word	0x5000d000
    6340:	0000b6de 	.word	0x0000b6de

00006344 <nrfx_gpiote_trigger_disable>:
{
    6344:	b508      	push	{r3, lr}
    6346:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    6348:	f7ff fd36 	bl	5db8 <pin_in_use_by_te>
    634c:	b1c8      	cbz	r0, 6382 <nrfx_gpiote_trigger_disable+0x3e>
    return !pin_is_output(pin);
    634e:	4610      	mov	r0, r2
    6350:	f7ff fd48 	bl	5de4 <pin_is_output>
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    6354:	b9a8      	cbnz	r0, 6382 <nrfx_gpiote_trigger_disable+0x3e>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    6356:	4b0e      	ldr	r3, [pc, #56]	; (6390 <nrfx_gpiote_trigger_disable+0x4c>)
    6358:	3208      	adds	r2, #8
    635a:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    635e:	2201      	movs	r2, #1
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    6360:	0b5b      	lsrs	r3, r3, #13
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    6362:	409a      	lsls	r2, r3
    p_reg->INTENCLR = mask;
    6364:	490b      	ldr	r1, [pc, #44]	; (6394 <nrfx_gpiote_trigger_disable+0x50>)
    6366:	009b      	lsls	r3, r3, #2
    6368:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    636c:	f8c1 2308 	str.w	r2, [r1, #776]	; 0x308
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    6370:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    6374:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    6378:	f022 0203 	bic.w	r2, r2, #3
    637c:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    6380:	bd08      	pop	{r3, pc}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    6382:	2100      	movs	r1, #0
}
    6384:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    6388:	4610      	mov	r0, r2
    638a:	f003 bbb5 	b.w	9af8 <nrf_gpio_cfg_sense_set>
    638e:	bf00      	nop
    6390:	2000005c 	.word	0x2000005c
    6394:	5000d000 	.word	0x5000d000

00006398 <nrfx_gpiote_pin_uninit>:
{
    6398:	b513      	push	{r0, r1, r4, lr}
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    639a:	4b10      	ldr	r3, [pc, #64]	; (63dc <nrfx_gpiote_pin_uninit+0x44>)
    639c:	f100 0208 	add.w	r2, r0, #8
    63a0:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
{
    63a4:	4604      	mov	r4, r0
    if (!pin_in_use(pin))
    63a6:	07db      	lsls	r3, r3, #31
    63a8:	d516      	bpl.n	63d8 <nrfx_gpiote_pin_uninit+0x40>
    nrfx_gpiote_trigger_disable(pin);
    63aa:	f7ff ffcb 	bl	6344 <nrfx_gpiote_trigger_disable>
    pin_handler_trigger_uninit(pin);
    63ae:	4620      	mov	r0, r4
    63b0:	f7ff fd7e 	bl	5eb0 <pin_handler_trigger_uninit>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    63b4:	a801      	add	r0, sp, #4
    63b6:	9401      	str	r4, [sp, #4]
    63b8:	f7ff fd98 	bl	5eec <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    63bc:	9b01      	ldr	r3, [sp, #4]
    63be:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    63c2:	f8d0 3200 	ldr.w	r3, [r0, #512]	; 0x200
    63c6:	f003 43e0 	and.w	r3, r3, #1879048192	; 0x70000000
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    63ca:	f043 0302 	orr.w	r3, r3, #2
    reg->PIN_CNF[pin_number] = cnf;
    63ce:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
    nrf_gpio_cfg(
    63d2:	4803      	ldr	r0, [pc, #12]	; (63e0 <nrfx_gpiote_pin_uninit+0x48>)
}
    63d4:	b002      	add	sp, #8
    63d6:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    63d8:	4802      	ldr	r0, [pc, #8]	; (63e4 <nrfx_gpiote_pin_uninit+0x4c>)
    63da:	e7fb      	b.n	63d4 <nrfx_gpiote_pin_uninit+0x3c>
    63dc:	2000005c 	.word	0x2000005c
    63e0:	0bad0000 	.word	0x0bad0000
    63e4:	0bad0004 	.word	0x0bad0004

000063e8 <nrfx_gpiote_irq_handler>:
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    }
}

void nrfx_gpiote_irq_handler(void)
{
    63e8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    uint32_t status = 0;
    63ec:	2600      	movs	r6, #0
    uint32_t i;
    nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0;
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
    63ee:	2201      	movs	r2, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    63f0:	4634      	mov	r4, r6
{
    63f2:	4b64      	ldr	r3, [pc, #400]	; (6584 <nrfx_gpiote_irq_handler+0x19c>)
    return p_reg->INTENSET & mask;
    63f4:	4864      	ldr	r0, [pc, #400]	; (6588 <nrfx_gpiote_irq_handler+0x1a0>)

    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    63f6:	4965      	ldr	r1, [pc, #404]	; (658c <nrfx_gpiote_irq_handler+0x1a4>)
{
    63f8:	b087      	sub	sp, #28
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    63fa:	681d      	ldr	r5, [r3, #0]
    {
        if (nrf_gpiote_event_check(NRF_GPIOTE, event) &&
    63fc:	b135      	cbz	r5, 640c <nrfx_gpiote_irq_handler+0x24>
    return p_reg->INTENSET & mask;
    63fe:	f8d0 5304 	ldr.w	r5, [r0, #772]	; 0x304
    6402:	4215      	tst	r5, r2
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    6404:	bf1e      	ittt	ne
    6406:	601c      	strne	r4, [r3, #0]
    6408:	681d      	ldrne	r5, [r3, #0]
            nrf_gpiote_int_enable_check(NRF_GPIOTE, mask))
        {
            nrf_gpiote_event_clear(NRF_GPIOTE, event);
            status |= mask;
    640a:	4316      	orrne	r6, r2
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    640c:	3304      	adds	r3, #4
    640e:	428b      	cmp	r3, r1
        }
        mask <<= 1;
    6410:	ea4f 0242 	mov.w	r2, r2, lsl #1
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    6414:	d1f1      	bne.n	63fa <nrfx_gpiote_irq_handler+0x12>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6416:	f8df a170 	ldr.w	sl, [pc, #368]	; 6588 <nrfx_gpiote_irq_handler+0x1a0>
    641a:	f8da 317c 	ldr.w	r3, [sl, #380]	; 0x17c
         * in ascending order. */
        event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t));
    }

    /* handle PORT event */
    if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
    641e:	2b00      	cmp	r3, #0
    6420:	f000 8093 	beq.w	654a <nrfx_gpiote_irq_handler+0x162>
        *p_masks = gpio_regs[i]->LATCH;
    6424:	f8df 8168 	ldr.w	r8, [pc, #360]	; 6590 <nrfx_gpiote_irq_handler+0x1a8>
    6428:	f8d8 3020 	ldr.w	r3, [r8, #32]
    642c:	9304      	str	r3, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    642e:	f8c8 3020 	str.w	r3, [r8, #32]
        *p_masks = gpio_regs[i]->LATCH;
    6432:	4b58      	ldr	r3, [pc, #352]	; (6594 <nrfx_gpiote_irq_handler+0x1ac>)
    6434:	6a1a      	ldr	r2, [r3, #32]
    6436:	9205      	str	r2, [sp, #20]
        gpio_regs[i]->LATCH = *p_masks;
    6438:	621a      	str	r2, [r3, #32]
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    643a:	f04f 0900 	mov.w	r9, #0
            while (latch[i])
    643e:	f10d 0b10 	add.w	fp, sp, #16
    6442:	ea4f 1349 	mov.w	r3, r9, lsl #5
    6446:	9300      	str	r3, [sp, #0]
    6448:	e04a      	b.n	64e0 <nrfx_gpiote_irq_handler+0xf8>
                uint32_t pin = NRF_CTZ(latch[i]);
    644a:	fa94 f4a4 	rbit	r4, r4
    644e:	fab4 f484 	clz	r4, r4
                pin += 32 * i;
    6452:	9b00      	ldr	r3, [sp, #0]
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    6454:	4a50      	ldr	r2, [pc, #320]	; (6598 <nrfx_gpiote_irq_handler+0x1b0>)
                pin += 32 * i;
    6456:	441c      	add	r4, r3
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    6458:	f104 0308 	add.w	r3, r4, #8
    645c:	f832 7013 	ldrh.w	r7, [r2, r3, lsl #1]
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
    uint8_t * p_mask8 = (uint8_t *)p_mask;
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    bit = BITMASK_RELBIT_GET(bit);
    p_mask8[byte_idx] &= ~(1 << bit);
    6460:	2301      	movs	r3, #1
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    6462:	08e0      	lsrs	r0, r4, #3
    bit = BITMASK_RELBIT_GET(bit);
    6464:	f004 0107 	and.w	r1, r4, #7
    p_mask8[byte_idx] &= ~(1 << bit);
    6468:	fa03 f101 	lsl.w	r1, r3, r1
    646c:	f81b 3000 	ldrb.w	r3, [fp, r0]
    6470:	08ba      	lsrs	r2, r7, #2
    6472:	ea23 0301 	bic.w	r3, r3, r1
    6476:	f80b 3000 	strb.w	r3, [fp, r0]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    647a:	a803      	add	r0, sp, #12
    647c:	9201      	str	r2, [sp, #4]
    647e:	9403      	str	r4, [sp, #12]
    6480:	f7ff fd34 	bl	5eec <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    6484:	9b03      	ldr	r3, [sp, #12]
    if (is_level(trigger))
    6486:	9a01      	ldr	r2, [sp, #4]
    6488:	3380      	adds	r3, #128	; 0x80
    648a:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    648e:	f3c7 0582 	ubfx	r5, r7, #2, #3
    if (is_level(trigger))
    6492:	0752      	lsls	r2, r2, #29
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    6494:	462f      	mov	r7, r5
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    6496:	f3c3 4301 	ubfx	r3, r3, #16, #2
    if (is_level(trigger))
    649a:	d52b      	bpl.n	64f4 <nrfx_gpiote_irq_handler+0x10c>
        call_handler(pin, trigger);
    649c:	4639      	mov	r1, r7
    649e:	4620      	mov	r0, r4
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    64a0:	b2dd      	uxtb	r5, r3
    64a2:	f7ff fca9 	bl	5df8 <call_handler>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    64a6:	a803      	add	r0, sp, #12
    64a8:	9403      	str	r4, [sp, #12]
    64aa:	f7ff fd1f 	bl	5eec <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    64ae:	9b03      	ldr	r3, [sp, #12]
    64b0:	3380      	adds	r3, #128	; 0x80
    64b2:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
        if (nrf_gpio_pin_sense_get(pin) == sense)
    64b6:	f3c3 4301 	ubfx	r3, r3, #16, #2
    64ba:	429d      	cmp	r5, r3
    64bc:	d107      	bne.n	64ce <nrfx_gpiote_irq_handler+0xe6>
            nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    64be:	2100      	movs	r1, #0
    64c0:	4620      	mov	r0, r4
    64c2:	f003 fb19 	bl	9af8 <nrf_gpio_cfg_sense_set>
            nrf_gpio_cfg_sense_set(pin, sense);
    64c6:	4629      	mov	r1, r5
    64c8:	4620      	mov	r0, r4
    64ca:	f003 fb15 	bl	9af8 <nrf_gpio_cfg_sense_set>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    64ce:	a803      	add	r0, sp, #12
    64d0:	9403      	str	r4, [sp, #12]
    64d2:	f7ff fd0b 	bl	5eec <nrf_gpio_pin_port_decode>
    reg->LATCH = (1 << pin_number);
    64d6:	2201      	movs	r2, #1
    64d8:	9b03      	ldr	r3, [sp, #12]
    64da:	fa02 f303 	lsl.w	r3, r2, r3
    64de:	6203      	str	r3, [r0, #32]
            while (latch[i])
    64e0:	f85b 4029 	ldr.w	r4, [fp, r9, lsl #2]
    64e4:	2c00      	cmp	r4, #0
    64e6:	d1b0      	bne.n	644a <nrfx_gpiote_irq_handler+0x62>
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    64e8:	f1b9 0f00 	cmp.w	r9, #0
    64ec:	d11d      	bne.n	652a <nrfx_gpiote_irq_handler+0x142>
    64ee:	f04f 0901 	mov.w	r9, #1
    64f2:	e7a6      	b.n	6442 <nrfx_gpiote_irq_handler+0x5a>
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    64f4:	2b02      	cmp	r3, #2
    64f6:	d10c      	bne.n	6512 <nrfx_gpiote_irq_handler+0x12a>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    64f8:	2103      	movs	r1, #3
    64fa:	4620      	mov	r0, r4
    64fc:	f003 fafc 	bl	9af8 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    6500:	f005 0305 	and.w	r3, r5, #5
    6504:	2b01      	cmp	r3, #1
    6506:	d1e2      	bne.n	64ce <nrfx_gpiote_irq_handler+0xe6>
            call_handler(pin, trigger);
    6508:	4639      	mov	r1, r7
    650a:	4620      	mov	r0, r4
    650c:	f7ff fc74 	bl	5df8 <call_handler>
    6510:	e7dd      	b.n	64ce <nrfx_gpiote_irq_handler+0xe6>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    6512:	2102      	movs	r1, #2
    6514:	4620      	mov	r0, r4
    6516:	9301      	str	r3, [sp, #4]
    6518:	f003 faee 	bl	9af8 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    651c:	2d03      	cmp	r5, #3
    651e:	d0f3      	beq.n	6508 <nrfx_gpiote_irq_handler+0x120>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    6520:	9b01      	ldr	r3, [sp, #4]
    6522:	2b03      	cmp	r3, #3
    6524:	d1d3      	bne.n	64ce <nrfx_gpiote_irq_handler+0xe6>
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    6526:	2d02      	cmp	r5, #2
    6528:	e7ed      	b.n	6506 <nrfx_gpiote_irq_handler+0x11e>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    652a:	f8ca 417c 	str.w	r4, [sl, #380]	; 0x17c
    652e:	f8da 317c 	ldr.w	r3, [sl, #380]	; 0x17c
        *p_masks = gpio_regs[i]->LATCH;
    6532:	f8d8 3020 	ldr.w	r3, [r8, #32]
    6536:	4917      	ldr	r1, [pc, #92]	; (6594 <nrfx_gpiote_irq_handler+0x1ac>)
    6538:	9304      	str	r3, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    653a:	f8c8 3020 	str.w	r3, [r8, #32]
        *p_masks = gpio_regs[i]->LATCH;
    653e:	6a0a      	ldr	r2, [r1, #32]
        if (latch[port_idx])
    6540:	4313      	orrs	r3, r2
    6542:	9205      	str	r2, [sp, #20]
        gpio_regs[i]->LATCH = *p_masks;
    6544:	620a      	str	r2, [r1, #32]
    6546:	f47f af78 	bne.w	643a <nrfx_gpiote_irq_handler+0x52>
        mask &= ~NRFX_BIT(ch);
    654a:	2401      	movs	r4, #1
    while (mask)
    654c:	b916      	cbnz	r6, 6554 <nrfx_gpiote_irq_handler+0x16c>
        port_event_handle();
    }

    /* Process pin events. */
    gpiote_evt_handle(status);
}
    654e:	b007      	add	sp, #28
    6550:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        uint32_t ch = NRF_CTZ(mask);
    6554:	fa96 f3a6 	rbit	r3, r6
    6558:	fab3 f383 	clz	r3, r3
        mask &= ~NRFX_BIT(ch);
    655c:	fa04 f203 	lsl.w	r2, r4, r3
    6560:	009b      	lsls	r3, r3, #2
    6562:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    6566:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    656a:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    656e:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    6572:	f3c0 2005 	ubfx	r0, r0, #8, #6
    6576:	f3c1 4101 	ubfx	r1, r1, #16, #2
        mask &= ~NRFX_BIT(ch);
    657a:	ea26 0602 	bic.w	r6, r6, r2
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    657e:	f7ff fc3b 	bl	5df8 <call_handler>
    6582:	e7e3      	b.n	654c <nrfx_gpiote_irq_handler+0x164>
    6584:	5000d100 	.word	0x5000d100
    6588:	5000d000 	.word	0x5000d000
    658c:	5000d120 	.word	0x5000d120
    6590:	50842500 	.word	0x50842500
    6594:	50842800 	.word	0x50842800
    6598:	2000005c 	.word	0x2000005c

0000659c <nrfx_ipc_init>:
} ipc_control_block_t;

static ipc_control_block_t m_ipc_cb;

nrfx_err_t nrfx_ipc_init(uint8_t irq_priority, nrfx_ipc_handler_t handler, void * p_context)
{
    659c:	b570      	push	{r4, r5, r6, lr}
    if (m_ipc_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    659e:	4c08      	ldr	r4, [pc, #32]	; (65c0 <nrfx_ipc_init+0x24>)
{
    65a0:	460e      	mov	r6, r1
    if (m_ipc_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    65a2:	7923      	ldrb	r3, [r4, #4]
{
    65a4:	4615      	mov	r5, r2
    if (m_ipc_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    65a6:	b943      	cbnz	r3, 65ba <nrfx_ipc_init+0x1e>
    {
        return NRFX_ERROR_ALREADY_INITIALIZED;
    }

    NRFX_IRQ_PRIORITY_SET(IPC_IRQn, irq_priority);
    NRFX_IRQ_ENABLE(IPC_IRQn);
    65a8:	202a      	movs	r0, #42	; 0x2a
    65aa:	f7fc ffa9 	bl	3500 <arch_irq_enable>

    m_ipc_cb.state = NRFX_DRV_STATE_INITIALIZED;
    65ae:	2301      	movs	r3, #1
    m_ipc_cb.handler = handler;
    m_ipc_cb.p_context = p_context;

    return NRFX_SUCCESS;
    65b0:	4804      	ldr	r0, [pc, #16]	; (65c4 <nrfx_ipc_init+0x28>)
    m_ipc_cb.state = NRFX_DRV_STATE_INITIALIZED;
    65b2:	7123      	strb	r3, [r4, #4]
    m_ipc_cb.handler = handler;
    65b4:	6026      	str	r6, [r4, #0]
    m_ipc_cb.p_context = p_context;
    65b6:	60a5      	str	r5, [r4, #8]
}
    65b8:	bd70      	pop	{r4, r5, r6, pc}
        return NRFX_ERROR_ALREADY_INITIALIZED;
    65ba:	4803      	ldr	r0, [pc, #12]	; (65c8 <nrfx_ipc_init+0x2c>)
    65bc:	e7fc      	b.n	65b8 <nrfx_ipc_init+0x1c>
    65be:	bf00      	nop
    65c0:	20000e94 	.word	0x20000e94
    65c4:	0bad0000 	.word	0x0bad0000
    65c8:	0bad000c 	.word	0x0bad000c

000065cc <nrfx_ipc_config_load>:

void nrfx_ipc_config_load(const nrfx_ipc_config_t * p_config)
{
    65cc:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(p_config);
    65ce:	b948      	cbnz	r0, 65e4 <nrfx_ipc_config_load+0x18>
    65d0:	4919      	ldr	r1, [pc, #100]	; (6638 <nrfx_ipc_config_load+0x6c>)
    65d2:	2345      	movs	r3, #69	; 0x45
    65d4:	4a19      	ldr	r2, [pc, #100]	; (663c <nrfx_ipc_config_load+0x70>)
    65d6:	481a      	ldr	r0, [pc, #104]	; (6640 <nrfx_ipc_config_load+0x74>)
    65d8:	f002 fe65 	bl	92a6 <assert_print>
    65dc:	2145      	movs	r1, #69	; 0x45
    NRFX_ASSERT(m_ipc_cb.state == NRFX_DRV_STATE_INITIALIZED);
    65de:	4817      	ldr	r0, [pc, #92]	; (663c <nrfx_ipc_config_load+0x70>)
    65e0:	f002 fe5a 	bl	9298 <assert_post_action>
    65e4:	4b17      	ldr	r3, [pc, #92]	; (6644 <nrfx_ipc_config_load+0x78>)
    65e6:	791b      	ldrb	r3, [r3, #4]
    65e8:	2b01      	cmp	r3, #1
    65ea:	d007      	beq.n	65fc <nrfx_ipc_config_load+0x30>
    65ec:	4916      	ldr	r1, [pc, #88]	; (6648 <nrfx_ipc_config_load+0x7c>)
    65ee:	2346      	movs	r3, #70	; 0x46
    65f0:	4a12      	ldr	r2, [pc, #72]	; (663c <nrfx_ipc_config_load+0x70>)
    65f2:	4813      	ldr	r0, [pc, #76]	; (6640 <nrfx_ipc_config_load+0x74>)
    65f4:	f002 fe57 	bl	92a6 <assert_print>
    65f8:	2146      	movs	r1, #70	; 0x46
    65fa:	e7f0      	b.n	65de <nrfx_ipc_config_load+0x12>

    uint32_t i;
    for (i = 0; i < IPC_CONF_NUM; ++i)
    65fc:	2300      	movs	r3, #0
    p_reg->SEND_CNF[index] = channels_mask;
    65fe:	4a13      	ldr	r2, [pc, #76]	; (664c <nrfx_ipc_config_load+0x80>)
    {
        nrf_ipc_send_config_set(NRF_IPC, i, p_config->send_task_config[i]);
    6600:	f850 4023 	ldr.w	r4, [r0, r3, lsl #2]
    6604:	f503 71a2 	add.w	r1, r3, #324	; 0x144
    for (i = 0; i < IPC_CONF_NUM; ++i)
    6608:	3301      	adds	r3, #1
    660a:	2b10      	cmp	r3, #16
    660c:	f842 4021 	str.w	r4, [r2, r1, lsl #2]
    6610:	d1f6      	bne.n	6600 <nrfx_ipc_config_load+0x34>
    }

    for (i = 0; i < IPC_CONF_NUM; ++i)
    6612:	2300      	movs	r3, #0
    p_reg->RECEIVE_CNF[index] = channels_mask;
    6614:	4a0d      	ldr	r2, [pc, #52]	; (664c <nrfx_ipc_config_load+0x80>)
    6616:	f100 013c 	add.w	r1, r0, #60	; 0x3c
    661a:	f503 74b2 	add.w	r4, r3, #356	; 0x164
    {
        nrf_ipc_receive_config_set(NRF_IPC, i, p_config->receive_event_config[i]);
    661e:	f851 5f04 	ldr.w	r5, [r1, #4]!
    for (i = 0; i < IPC_CONF_NUM; ++i)
    6622:	3301      	adds	r3, #1
    6624:	2b10      	cmp	r3, #16
    6626:	f842 5024 	str.w	r5, [r2, r4, lsl #2]
    662a:	d1f6      	bne.n	661a <nrfx_ipc_config_load+0x4e>
    }

    nrf_ipc_int_enable(NRF_IPC, p_config->receive_events_enabled);
    662c:	f8d0 3080 	ldr.w	r3, [r0, #128]	; 0x80
    p_reg->INTENSET = mask;
    6630:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    6634:	bd38      	pop	{r3, r4, r5, pc}
    6636:	bf00      	nop
    6638:	0000b730 	.word	0x0000b730
    663c:	0000b6f5 	.word	0x0000b6f5
    6640:	0000a2e8 	.word	0x0000a2e8
    6644:	20000e94 	.word	0x20000e94
    6648:	0000b739 	.word	0x0000b739
    664c:	5002a000 	.word	0x5002a000

00006650 <nrfx_ipc_receive_event_enable>:
    nrf_ipc_int_disable(NRF_IPC, 0xFFFFFFFF);
    m_ipc_cb.state = NRFX_DRV_STATE_UNINITIALIZED;
}

void nrfx_ipc_receive_event_enable(uint8_t event_index)
{
    6650:	b508      	push	{r3, lr}
    NRFX_ASSERT(m_ipc_cb.state == NRFX_DRV_STATE_INITIALIZED);
    6652:	4b09      	ldr	r3, [pc, #36]	; (6678 <nrfx_ipc_receive_event_enable+0x28>)
    6654:	791b      	ldrb	r3, [r3, #4]
    6656:	2b01      	cmp	r3, #1
    6658:	d009      	beq.n	666e <nrfx_ipc_receive_event_enable+0x1e>
    665a:	4908      	ldr	r1, [pc, #32]	; (667c <nrfx_ipc_receive_event_enable+0x2c>)
    665c:	4808      	ldr	r0, [pc, #32]	; (6680 <nrfx_ipc_receive_event_enable+0x30>)
    665e:	236b      	movs	r3, #107	; 0x6b
    6660:	4a08      	ldr	r2, [pc, #32]	; (6684 <nrfx_ipc_receive_event_enable+0x34>)
    6662:	f002 fe20 	bl	92a6 <assert_print>
    6666:	216b      	movs	r1, #107	; 0x6b
    6668:	4806      	ldr	r0, [pc, #24]	; (6684 <nrfx_ipc_receive_event_enable+0x34>)
    666a:	f002 fe15 	bl	9298 <assert_post_action>
    666e:	4a06      	ldr	r2, [pc, #24]	; (6688 <nrfx_ipc_receive_event_enable+0x38>)
    nrf_ipc_int_enable(NRF_IPC, (1UL << event_index));
    6670:	4083      	lsls	r3, r0
    6672:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    6676:	bd08      	pop	{r3, pc}
    6678:	20000e94 	.word	0x20000e94
    667c:	0000b739 	.word	0x0000b739
    6680:	0000a2e8 	.word	0x0000a2e8
    6684:	0000b6f5 	.word	0x0000b6f5
    6688:	5002a000 	.word	0x5002a000

0000668c <nrfx_ipc_receive_event_disable>:

void nrfx_ipc_receive_event_disable(uint8_t event_index)
{
    668c:	b508      	push	{r3, lr}
    NRFX_ASSERT(m_ipc_cb.state == NRFX_DRV_STATE_INITIALIZED);
    668e:	4b09      	ldr	r3, [pc, #36]	; (66b4 <nrfx_ipc_receive_event_disable+0x28>)
    6690:	791b      	ldrb	r3, [r3, #4]
    6692:	2b01      	cmp	r3, #1
    6694:	d009      	beq.n	66aa <nrfx_ipc_receive_event_disable+0x1e>
    6696:	4908      	ldr	r1, [pc, #32]	; (66b8 <nrfx_ipc_receive_event_disable+0x2c>)
    6698:	4808      	ldr	r0, [pc, #32]	; (66bc <nrfx_ipc_receive_event_disable+0x30>)
    669a:	2371      	movs	r3, #113	; 0x71
    669c:	4a08      	ldr	r2, [pc, #32]	; (66c0 <nrfx_ipc_receive_event_disable+0x34>)
    669e:	f002 fe02 	bl	92a6 <assert_print>
    66a2:	2171      	movs	r1, #113	; 0x71
    66a4:	4806      	ldr	r0, [pc, #24]	; (66c0 <nrfx_ipc_receive_event_disable+0x34>)
    66a6:	f002 fdf7 	bl	9298 <assert_post_action>
    p_reg->INTENCLR = mask;
    66aa:	4a06      	ldr	r2, [pc, #24]	; (66c4 <nrfx_ipc_receive_event_disable+0x38>)
    nrf_ipc_int_disable(NRF_IPC, (1UL << event_index));
    66ac:	4083      	lsls	r3, r0
    66ae:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
}
    66b2:	bd08      	pop	{r3, pc}
    66b4:	20000e94 	.word	0x20000e94
    66b8:	0000b739 	.word	0x0000b739
    66bc:	0000a2e8 	.word	0x0000a2e8
    66c0:	0000b6f5 	.word	0x0000b6f5
    66c4:	5002a000 	.word	0x5002a000

000066c8 <nrfx_ipc_irq_handler>:
    channel_bitmask |= nrf_ipc_send_config_get(NRF_IPC, send_index);
    nrf_ipc_send_config_set(NRF_IPC, send_index, channel_bitmask);
}

void nrfx_ipc_irq_handler(void)
{
    66c8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    uint32_t bitmask = events_map;

    while (bitmask)
    {
        uint8_t event_idx = NRF_CTZ(bitmask);
        bitmask &= ~(1UL << event_idx);
    66ca:	2601      	movs	r6, #1
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    66cc:	2700      	movs	r7, #0
    return p_reg->INTPEND;
    66ce:	4b12      	ldr	r3, [pc, #72]	; (6718 <nrfx_ipc_irq_handler+0x50>)
        nrf_ipc_event_clear(NRF_IPC, nrf_ipc_receive_event_get(event_idx));
#if NRFX_CHECK(NRFX_CONFIG_API_VER_2_10)
        if (m_ipc_cb.handler)
    66d0:	4d12      	ldr	r5, [pc, #72]	; (671c <nrfx_ipc_irq_handler+0x54>)
    66d2:	f8d3 430c 	ldr.w	r4, [r3, #780]	; 0x30c
    while (bitmask)
    66d6:	b904      	cbnz	r4, 66da <nrfx_ipc_irq_handler+0x12>
    if (m_ipc_cb.handler)
    {
        m_ipc_cb.handler(events_map, m_ipc_cb.p_context);
#endif
    }
}
    66d8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        uint8_t event_idx = NRF_CTZ(bitmask);
    66da:	fa94 f0a4 	rbit	r0, r4
    66de:	fab0 f080 	clz	r0, r0
        bitmask &= ~(1UL << event_idx);
    66e2:	fa06 f300 	lsl.w	r3, r6, r0
    NRFX_ASSERT(index < IPC_CH_NUM);
    66e6:	280f      	cmp	r0, #15
    66e8:	ea24 0403 	bic.w	r4, r4, r3
    66ec:	dd0b      	ble.n	6706 <nrfx_ipc_irq_handler+0x3e>
    66ee:	490c      	ldr	r1, [pc, #48]	; (6720 <nrfx_ipc_irq_handler+0x58>)
    66f0:	480c      	ldr	r0, [pc, #48]	; (6724 <nrfx_ipc_irq_handler+0x5c>)
    66f2:	f240 13e7 	movw	r3, #487	; 0x1e7
    66f6:	4a0c      	ldr	r2, [pc, #48]	; (6728 <nrfx_ipc_irq_handler+0x60>)
    66f8:	f002 fdd5 	bl	92a6 <assert_print>
    66fc:	f240 11e7 	movw	r1, #487	; 0x1e7
    6700:	4809      	ldr	r0, [pc, #36]	; (6728 <nrfx_ipc_irq_handler+0x60>)
    6702:	f002 fdc9 	bl	9298 <assert_post_action>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6706:	4b09      	ldr	r3, [pc, #36]	; (672c <nrfx_ipc_irq_handler+0x64>)
    return (nrf_ipc_event_t)(NRFX_OFFSETOF(NRF_IPC_Type, EVENTS_RECEIVE[index]));
    6708:	0082      	lsls	r2, r0, #2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    670a:	509f      	str	r7, [r3, r2]
        if (m_ipc_cb.handler)
    670c:	682b      	ldr	r3, [r5, #0]
    670e:	2b00      	cmp	r3, #0
    6710:	d0e1      	beq.n	66d6 <nrfx_ipc_irq_handler+0xe>
            m_ipc_cb.handler(event_idx, m_ipc_cb.p_context);
    6712:	68a9      	ldr	r1, [r5, #8]
    6714:	4798      	blx	r3
    6716:	e7de      	b.n	66d6 <nrfx_ipc_irq_handler+0xe>
    6718:	5002a000 	.word	0x5002a000
    671c:	20000e94 	.word	0x20000e94
    6720:	0000a683 	.word	0x0000a683
    6724:	0000a2e8 	.word	0x0000a2e8
    6728:	0000a651 	.word	0x0000a651
    672c:	5002a100 	.word	0x5002a100

00006730 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    6730:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    6734:	b086      	sub	sp, #24
    6736:	4604      	mov	r4, r0
    6738:	460e      	mov	r6, r1
    673a:	af00      	add	r7, sp, #0
	__asm__ volatile(
    673c:	f04f 0320 	mov.w	r3, #32
    6740:	f3ef 8811 	mrs	r8, BASEPRI
    6744:	f383 8812 	msr	BASEPRI_MAX, r3
    6748:	f3bf 8f6f 	isb	sy
	return z_impl_z_current_get();
    674c:	f001 fdf8 	bl	8340 <z_impl_z_current_get>
    6750:	2c04      	cmp	r4, #4
    6752:	bf98      	it	ls
    6754:	4b34      	ldrls	r3, [pc, #208]	; (6828 <z_fatal_error+0xf8>)
			k_current_get() : NULL;

	/* twister looks for the "ZEPHYR FATAL ERROR" string, don't
	 * change it without also updating twister
	 */
	LOG_ERR(">>> ZEPHYR FATAL ERROR %d: %s on CPU %d", reason,
    6756:	46e9      	mov	r9, sp
    6758:	b08a      	sub	sp, #40	; 0x28
    675a:	4605      	mov	r5, r0
    675c:	466a      	mov	r2, sp
    675e:	bf94      	ite	ls
    6760:	f853 3024 	ldrls.w	r3, [r3, r4, lsl #2]
    6764:	4b31      	ldrhi	r3, [pc, #196]	; (682c <z_fatal_error+0xfc>)
    6766:	61d3      	str	r3, [r2, #28]
    6768:	f240 3301 	movw	r3, #769	; 0x301
    676c:	f04f 0a00 	mov.w	sl, #0
    6770:	8493      	strh	r3, [r2, #36]	; 0x24
    6772:	492f      	ldr	r1, [pc, #188]	; (6830 <z_fatal_error+0x100>)
    6774:	4b2f      	ldr	r3, [pc, #188]	; (6834 <z_fatal_error+0x104>)
    6776:	e9c2 1405 	strd	r1, r4, [r2, #20]
    677a:	f8c2 a020 	str.w	sl, [r2, #32]
    677e:	f842 3f10 	str.w	r3, [r2, #16]!
    6782:	f44f 5131 	mov.w	r1, #11328	; 0x2c40
    6786:	4653      	mov	r3, sl
    6788:	482b      	ldr	r0, [pc, #172]	; (6838 <z_fatal_error+0x108>)
    678a:	f7fc f84d 	bl	2828 <z_impl_z_log_msg_static_create>
    678e:	46cd      	mov	sp, r9
	 * an IRQ or exception was being handled, or thread context.
	 *
	 * See #17656
	 */
#if defined(CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION)
	if ((esf != NULL) && arch_is_in_nested_exception(esf)) {
    6790:	b17e      	cbz	r6, 67b2 <z_fatal_error+0x82>
 * @return true if execution state was in handler mode, before
 *              the current exception occurred, otherwise false.
 */
static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf)
{
	return (esf->basic.xpsr & IPSR_ISR_Msk) ? (true) : (false);
    6792:	69f3      	ldr	r3, [r6, #28]
    6794:	f3c3 0308 	ubfx	r3, r3, #0, #9
    6798:	b15b      	cbz	r3, 67b2 <z_fatal_error+0x82>
		LOG_ERR("Fault during interrupt handling\n");
    679a:	4b28      	ldr	r3, [pc, #160]	; (683c <z_fatal_error+0x10c>)
    679c:	617b      	str	r3, [r7, #20]
    679e:	2302      	movs	r3, #2
    67a0:	613b      	str	r3, [r7, #16]
    67a2:	f44f 5182 	mov.w	r1, #4160	; 0x1040
    67a6:	4653      	mov	r3, sl
    67a8:	4823      	ldr	r0, [pc, #140]	; (6838 <z_fatal_error+0x108>)
    67aa:	f107 0210 	add.w	r2, r7, #16
    67ae:	f7fc f83b 	bl	2828 <z_impl_z_log_msg_static_create>
	const char *thread_name = (thread != NULL) ? k_thread_name_get(thread) : NULL;
    67b2:	b12d      	cbz	r5, 67c0 <z_fatal_error+0x90>
    67b4:	4628      	mov	r0, r5
    67b6:	f003 f9e9 	bl	9b8c <k_thread_name_get>
	if ((thread_name == NULL) || (thread_name[0] == '\0')) {
    67ba:	b108      	cbz	r0, 67c0 <z_fatal_error+0x90>
    67bc:	7803      	ldrb	r3, [r0, #0]
    67be:	b903      	cbnz	r3, 67c2 <z_fatal_error+0x92>
		thread_name = "unknown";
    67c0:	481f      	ldr	r0, [pc, #124]	; (6840 <z_fatal_error+0x110>)
	}
#endif

	LOG_ERR("Current thread: %p (%s)", thread,
    67c2:	46e9      	mov	r9, sp
    67c4:	b08a      	sub	sp, #40	; 0x28
    67c6:	466a      	mov	r2, sp
    67c8:	4b1e      	ldr	r3, [pc, #120]	; (6844 <z_fatal_error+0x114>)
    67ca:	61d0      	str	r0, [r2, #28]
    67cc:	e9c2 3505 	strd	r3, r5, [r2, #20]
    67d0:	f240 3301 	movw	r3, #769	; 0x301
    67d4:	8413      	strh	r3, [r2, #32]
    67d6:	4b1c      	ldr	r3, [pc, #112]	; (6848 <z_fatal_error+0x118>)
    67d8:	f842 3f10 	str.w	r3, [r2, #16]!
    67dc:	2300      	movs	r3, #0
    67de:	f44f 5111 	mov.w	r1, #9280	; 0x2440
    67e2:	4815      	ldr	r0, [pc, #84]	; (6838 <z_fatal_error+0x108>)
    67e4:	f7fc f820 	bl	2828 <z_impl_z_log_msg_static_create>

#ifndef CONFIG_XTENSA
	coredump(reason, esf, thread);
#endif

	k_sys_fatal_error_handler(reason, esf);
    67e8:	4631      	mov	r1, r6
    67ea:	46cd      	mov	sp, r9
    67ec:	4620      	mov	r0, r4
    67ee:	f7fe ff97 	bl	5720 <k_sys_fatal_error_handler>
	 *
	 * Note that k_thread_abort() returns on some architectures but
	 * not others; e.g. on ARC, x86_64, Xtensa with ASM2, ARM
	 */
	if (!IS_ENABLED(CONFIG_TEST)) {
		__ASSERT(reason != K_ERR_KERNEL_PANIC,
    67f2:	2c04      	cmp	r4, #4
    67f4:	d10c      	bne.n	6810 <z_fatal_error+0xe0>
    67f6:	4915      	ldr	r1, [pc, #84]	; (684c <z_fatal_error+0x11c>)
    67f8:	2393      	movs	r3, #147	; 0x93
    67fa:	4a15      	ldr	r2, [pc, #84]	; (6850 <z_fatal_error+0x120>)
    67fc:	4815      	ldr	r0, [pc, #84]	; (6854 <z_fatal_error+0x124>)
    67fe:	f002 fd52 	bl	92a6 <assert_print>
    6802:	4815      	ldr	r0, [pc, #84]	; (6858 <z_fatal_error+0x128>)
    6804:	f002 fd4f 	bl	92a6 <assert_print>
    6808:	2193      	movs	r1, #147	; 0x93
    680a:	4811      	ldr	r0, [pc, #68]	; (6850 <z_fatal_error+0x120>)
    680c:	f002 fd44 	bl	9298 <assert_post_action>
	__asm__ volatile(
    6810:	f388 8811 	msr	BASEPRI, r8
    6814:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    6818:	4628      	mov	r0, r5
    681a:	f7fd fb5f 	bl	3edc <z_impl_k_thread_abort>
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    681e:	3718      	adds	r7, #24
    6820:	46bd      	mov	sp, r7
    6822:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    6826:	bf00      	nop
    6828:	0000a1fc 	.word	0x0000a1fc
    682c:	0000b770 	.word	0x0000b770
    6830:	0000b786 	.word	0x0000b786
    6834:	01000005 	.word	0x01000005
    6838:	00009fe4 	.word	0x00009fe4
    683c:	0000b7ae 	.word	0x0000b7ae
    6840:	0000b77e 	.word	0x0000b77e
    6844:	0000b7cf 	.word	0x0000b7cf
    6848:	01000004 	.word	0x01000004
    684c:	0000b809 	.word	0x0000b809
    6850:	0000b7e7 	.word	0x0000b7e7
    6854:	0000a2e8 	.word	0x0000a2e8
    6858:	0000b826 	.word	0x0000b826

0000685c <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    685c:	4b0f      	ldr	r3, [pc, #60]	; (689c <z_sys_init_run_level+0x40>)
{
    685e:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    6860:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    6864:	3001      	adds	r0, #1
    6866:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    686a:	42a6      	cmp	r6, r4
    686c:	d800      	bhi.n	6870 <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    686e:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    6870:	e9d4 3500 	ldrd	r3, r5, [r4]
    6874:	4628      	mov	r0, r5
    6876:	4798      	blx	r3
		if (dev != NULL) {
    6878:	b16d      	cbz	r5, 6896 <z_sys_init_run_level+0x3a>
			if (rc != 0) {
    687a:	b138      	cbz	r0, 688c <z_sys_init_run_level+0x30>
				if (rc < 0) {
    687c:	2800      	cmp	r0, #0
    687e:	bfb8      	it	lt
    6880:	4240      	neglt	r0, r0
				if (rc > UINT8_MAX) {
    6882:	28ff      	cmp	r0, #255	; 0xff
    6884:	bfa8      	it	ge
    6886:	20ff      	movge	r0, #255	; 0xff
				dev->state->init_res = rc;
    6888:	68eb      	ldr	r3, [r5, #12]
    688a:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    688c:	68ea      	ldr	r2, [r5, #12]
    688e:	7853      	ldrb	r3, [r2, #1]
    6890:	f043 0301 	orr.w	r3, r3, #1
    6894:	7053      	strb	r3, [r2, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    6896:	3408      	adds	r4, #8
    6898:	e7e7      	b.n	686a <z_sys_init_run_level+0xe>
    689a:	bf00      	nop
    689c:	0000a210 	.word	0x0000a210

000068a0 <bg_thread_main>:
	 * may perform memory management tasks (except for z_phys_map() which
	 * is allowed at any time)
	 */
	z_mem_manage_init();
#endif /* CONFIG_MMU */
	z_sys_post_kernel = true;
    68a0:	2201      	movs	r2, #1
{
    68a2:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    68a4:	4b09      	ldr	r3, [pc, #36]	; (68cc <bg_thread_main+0x2c>)

	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    68a6:	2003      	movs	r0, #3
	z_sys_post_kernel = true;
    68a8:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    68aa:	f7ff ffd7 	bl	685c <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    68ae:	f003 f9ce 	bl	9c4e <boot_banner>
	void z_cpp_init_static(void);
	z_cpp_init_static();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(INIT_LEVEL_APPLICATION);
    68b2:	2004      	movs	r0, #4
    68b4:	f7ff ffd2 	bl	685c <z_sys_init_run_level>

	z_init_static_threads();
    68b8:	f000 fa04 	bl	6cc4 <z_init_static_threads>
	extern int main(void);
#else
	extern void main(void);
#endif

	(void)main();
    68bc:	f7f9 fdb2 	bl	424 <main>

	/* Mark nonessential since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    68c0:	4a03      	ldr	r2, [pc, #12]	; (68d0 <bg_thread_main+0x30>)
    68c2:	7b13      	ldrb	r3, [r2, #12]
    68c4:	f023 0301 	bic.w	r3, r3, #1
    68c8:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    68ca:	bd08      	pop	{r3, pc}
    68cc:	200010ce 	.word	0x200010ce
    68d0:	200006e0 	.word	0x200006e0

000068d4 <z_bss_zero>:
{
    68d4:	b508      	push	{r3, lr}
	z_early_memset(__bss_start, 0, __bss_end - __bss_start);
    68d6:	4803      	ldr	r0, [pc, #12]	; (68e4 <z_bss_zero+0x10>)
    68d8:	4a03      	ldr	r2, [pc, #12]	; (68e8 <z_bss_zero+0x14>)
    68da:	2100      	movs	r1, #0
    68dc:	1a12      	subs	r2, r2, r0
    68de:	f003 f926 	bl	9b2e <z_early_memset>
}
    68e2:	bd08      	pop	{r3, pc}
    68e4:	200001f0 	.word	0x200001f0
    68e8:	200010d0 	.word	0x200010d0

000068ec <z_init_cpu>:

#else
	char *tname = NULL;
#endif /* CONFIG_THREAD_NAME */

	z_setup_new_thread(thread, stack,
    68ec:	2300      	movs	r3, #0
    68ee:	2201      	movs	r2, #1
	thread->base.is_idle = 1U;
#endif
}

void z_init_cpu(int id)
{
    68f0:	b570      	push	{r4, r5, r6, lr}
    68f2:	b086      	sub	sp, #24
	z_setup_new_thread(thread, stack,
    68f4:	e9cd 2304 	strd	r2, r3, [sp, #16]
    68f8:	220f      	movs	r2, #15
    68fa:	9301      	str	r3, [sp, #4]
    68fc:	e9cd 3202 	strd	r3, r2, [sp, #8]
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    6900:	2318      	movs	r3, #24
	z_setup_new_thread(thread, stack,
    6902:	f44f 72a0 	mov.w	r2, #320	; 0x140
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    6906:	4d0e      	ldr	r5, [pc, #56]	; (6940 <z_init_cpu+0x54>)
	struct k_thread *thread = &z_idle_threads[i];
    6908:	4e0e      	ldr	r6, [pc, #56]	; (6944 <z_init_cpu+0x58>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    690a:	fb03 5500 	mla	r5, r3, r0, r5
	z_setup_new_thread(thread, stack,
    690e:	490e      	ldr	r1, [pc, #56]	; (6948 <z_init_cpu+0x5c>)
	struct k_thread *thread = &z_idle_threads[i];
    6910:	eb06 16c0 	add.w	r6, r6, r0, lsl #7
{
    6914:	4604      	mov	r4, r0
	z_setup_new_thread(thread, stack,
    6916:	fb02 1100 	mla	r1, r2, r0, r1
    691a:	4b0c      	ldr	r3, [pc, #48]	; (694c <z_init_cpu+0x60>)
    691c:	4630      	mov	r0, r6
    691e:	9500      	str	r5, [sp, #0]
    6920:	f000 f97c 	bl	6c1c <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    6924:	7b73      	ldrb	r3, [r6, #13]
	init_idle_thread(id);
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
	_kernel.cpus[id].id = id;
    6926:	752c      	strb	r4, [r5, #20]
    6928:	f023 0304 	bic.w	r3, r3, #4
    692c:	7373      	strb	r3, [r6, #13]
	_kernel.cpus[id].irq_stack =
		(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) +
    692e:	4b08      	ldr	r3, [pc, #32]	; (6950 <z_init_cpu+0x64>)
    6930:	3401      	adds	r4, #1
    6932:	eb03 23c4 	add.w	r3, r3, r4, lsl #11
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
    6936:	60ee      	str	r6, [r5, #12]
	_kernel.cpus[id].irq_stack =
    6938:	606b      	str	r3, [r5, #4]
		 K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[id]));
#ifdef CONFIG_SCHED_THREAD_USAGE_ALL
	_kernel.cpus[id].usage.track_usage =
		CONFIG_SCHED_THREAD_USAGE_AUTO_ENABLE;
#endif
}
    693a:	b006      	add	sp, #24
    693c:	bd70      	pop	{r4, r5, r6, pc}
    693e:	bf00      	nop
    6940:	20000ea0 	.word	0x20000ea0
    6944:	20000660 	.word	0x20000660
    6948:	200018d0 	.word	0x200018d0
    694c:	00006e15 	.word	0x00006e15
    6950:	200010d0 	.word	0x200010d0

00006954 <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    6954:	b580      	push	{r7, lr}
	/* gcov hook needed to get the coverage report.*/
	gcov_static_init();

	/* initialize early init calls */
	z_sys_init_run_level(INIT_LEVEL_EARLY);
    6956:	2000      	movs	r0, #0
{
    6958:	b0a6      	sub	sp, #152	; 0x98
	z_sys_init_run_level(INIT_LEVEL_EARLY);
    695a:	f7ff ff7f 	bl	685c <z_sys_init_run_level>
 *
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
		(uint32_t)(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) +
    695e:	4b2e      	ldr	r3, [pc, #184]	; (6a18 <z_cstart+0xc4>)
	uint32_t msp =
    6960:	f503 6200 	add.w	r2, r3, #2048	; 0x800
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    6964:	f382 8808 	msr	MSP, r2
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  // without main extensions, the non-secure MSPLIM is RAZ/WI
  (void)MainStackPtrLimit;
#else
  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
    6968:	f383 880a 	msr	MSPLIM, r3
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    696c:	2400      	movs	r4, #0
    696e:	23e0      	movs	r3, #224	; 0xe0
    6970:	4d2a      	ldr	r5, [pc, #168]	; (6a1c <z_cstart+0xc8>)

#ifdef CONFIG_TIMESLICE_PER_THREAD
	dummy_thread->base.slice_ticks = 0;
#endif

	_current_cpu->current = dummy_thread;
    6972:	4e2b      	ldr	r6, [pc, #172]	; (6a20 <z_cstart+0xcc>)
    6974:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    6978:	77ec      	strb	r4, [r5, #31]
    697a:	762c      	strb	r4, [r5, #24]
    697c:	766c      	strb	r4, [r5, #25]
    697e:	76ac      	strb	r4, [r5, #26]
    6980:	f885 4020 	strb.w	r4, [r5, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    6984:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    6986:	4f27      	ldr	r7, [pc, #156]	; (6a24 <z_cstart+0xd0>)
    6988:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    698c:	626b      	str	r3, [r5, #36]	; 0x24
    698e:	f885 4023 	strb.w	r4, [r5, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    6992:	f7fd fa07 	bl	3da4 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    6996:	f7fc fd21 	bl	33dc <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    699a:	f04f 33ff 	mov.w	r3, #4294967295
    699e:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    69a0:	62eb      	str	r3, [r5, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    69a2:	f7fd fc7b 	bl	429c <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    69a6:	f7fd faaf 	bl	3f08 <z_arm_configure_static_mpu_regions>

	/* perform any architecture-specific initialization */
	arch_kernel_init();

	LOG_CORE_INIT();
    69aa:	f7fb fdab 	bl	2504 <log_core_init>
	dummy_thread->base.user_options = K_ESSENTIAL;
    69ae:	f240 1301 	movw	r3, #257	; 0x101
    69b2:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    69b6:	ab06      	add	r3, sp, #24
    69b8:	60b3      	str	r3, [r6, #8]
	dummy_thread->stack_info.size = 0U;
    69ba:	e9cd 441f 	strd	r4, r4, [sp, #124]	; 0x7c
	dummy_thread->resource_pool = NULL;
    69be:	9422      	str	r4, [sp, #136]	; 0x88
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    69c0:	f003 f8a9 	bl	9b16 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_1);
    69c4:	2001      	movs	r0, #1
    69c6:	f7ff ff49 	bl	685c <z_sys_init_run_level>
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_2);
    69ca:	2002      	movs	r0, #2
	_kernel.ready_q.cache = &z_main_thread;
    69cc:	4d16      	ldr	r5, [pc, #88]	; (6a28 <z_cstart+0xd4>)
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_2);
    69ce:	f7ff ff45 	bl	685c <z_sys_init_run_level>
	z_sched_init();
    69d2:	f001 fb3b 	bl	804c <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    69d6:	4b15      	ldr	r3, [pc, #84]	; (6a2c <z_cstart+0xd8>)
	_kernel.ready_q.cache = &z_main_thread;
    69d8:	61f5      	str	r5, [r6, #28]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    69da:	9305      	str	r3, [sp, #20]
    69dc:	2301      	movs	r3, #1
    69de:	4914      	ldr	r1, [pc, #80]	; (6a30 <z_cstart+0xdc>)
    69e0:	f44f 6280 	mov.w	r2, #1024	; 0x400
    69e4:	e9cd 4303 	strd	r4, r3, [sp, #12]
    69e8:	4628      	mov	r0, r5
    69ea:	463b      	mov	r3, r7
    69ec:	e9cd 4401 	strd	r4, r4, [sp, #4]
    69f0:	9400      	str	r4, [sp, #0]
    69f2:	f000 f913 	bl	6c1c <z_setup_new_thread>
    69f6:	4606      	mov	r6, r0
    69f8:	7b6a      	ldrb	r2, [r5, #13]
	z_ready_thread(&z_main_thread);
    69fa:	4628      	mov	r0, r5
    69fc:	f022 0204 	bic.w	r2, r2, #4
    6a00:	736a      	strb	r2, [r5, #13]
    6a02:	f000 fd45 	bl	7490 <z_ready_thread>
	z_init_cpu(0);
    6a06:	4620      	mov	r0, r4
    6a08:	f7ff ff70 	bl	68ec <z_init_cpu>
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    6a0c:	463a      	mov	r2, r7
    6a0e:	4631      	mov	r1, r6
    6a10:	4628      	mov	r0, r5
    6a12:	f7fc fe69 	bl	36e8 <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    6a16:	bf00      	nop
    6a18:	200010d0 	.word	0x200010d0
    6a1c:	e000ed00 	.word	0xe000ed00
    6a20:	20000ea0 	.word	0x20000ea0
    6a24:	000068a1 	.word	0x000068a1
    6a28:	200006e0 	.word	0x200006e0
    6a2c:	0000b8a5 	.word	0x0000b8a5
    6a30:	20001a10 	.word	0x20001a10

00006a34 <init_mem_slab_module>:
 *
 * @return 0 on success, fails otherwise.
 */
static int init_mem_slab_module(const struct device *dev)
{
	int rc = 0;
    6a34:	2000      	movs	r0, #0
{
    6a36:	b538      	push	{r3, r4, r5, lr}
	ARG_UNUSED(dev);

	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    6a38:	4c0c      	ldr	r4, [pc, #48]	; (6a6c <init_mem_slab_module+0x38>)
    6a3a:	4d0d      	ldr	r5, [pc, #52]	; (6a70 <init_mem_slab_module+0x3c>)
    6a3c:	42ac      	cmp	r4, r5
    6a3e:	d913      	bls.n	6a68 <init_mem_slab_module+0x34>
    6a40:	490c      	ldr	r1, [pc, #48]	; (6a74 <init_mem_slab_module+0x40>)
    6a42:	233d      	movs	r3, #61	; 0x3d
    6a44:	4a0c      	ldr	r2, [pc, #48]	; (6a78 <init_mem_slab_module+0x44>)
    6a46:	480d      	ldr	r0, [pc, #52]	; (6a7c <init_mem_slab_module+0x48>)
    6a48:	f002 fc2d 	bl	92a6 <assert_print>
    6a4c:	480c      	ldr	r0, [pc, #48]	; (6a80 <init_mem_slab_module+0x4c>)
    6a4e:	f002 fc2a 	bl	92a6 <assert_print>
    6a52:	213d      	movs	r1, #61	; 0x3d
    6a54:	4808      	ldr	r0, [pc, #32]	; (6a78 <init_mem_slab_module+0x44>)
    6a56:	f002 fc1f 	bl	9298 <assert_post_action>
		rc = create_free_list(slab);
    6a5a:	4620      	mov	r0, r4
    6a5c:	f003 f86b 	bl	9b36 <create_free_list>
		if (rc < 0) {
    6a60:	2800      	cmp	r0, #0
    6a62:	db02      	blt.n	6a6a <init_mem_slab_module+0x36>
	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    6a64:	3420      	adds	r4, #32
    6a66:	e7e9      	b.n	6a3c <init_mem_slab_module+0x8>
    6a68:	d3f7      	bcc.n	6a5a <init_mem_slab_module+0x26>
		z_object_init(slab);
	}

out:
	return rc;
}
    6a6a:	bd38      	pop	{r3, r4, r5, pc}
    6a6c:	2000018c 	.word	0x2000018c
    6a70:	2000018c 	.word	0x2000018c
    6a74:	0000b8d2 	.word	0x0000b8d2
    6a78:	0000b8ad 	.word	0x0000b8ad
    6a7c:	0000a2e8 	.word	0x0000a2e8
    6a80:	0000a7bc 	.word	0x0000a7bc

00006a84 <k_mem_slab_alloc>:

	return rc;
}

int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
{
    6a84:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    6a88:	4604      	mov	r4, r0
    6a8a:	460e      	mov	r6, r1
    6a8c:	4690      	mov	r8, r2
    6a8e:	461f      	mov	r7, r3
	k_spinlock_key_t key = k_spin_lock(&slab->lock);
    6a90:	f100 0508 	add.w	r5, r0, #8
	__asm__ volatile(
    6a94:	f04f 0320 	mov.w	r3, #32
    6a98:	f3ef 8911 	mrs	r9, BASEPRI
    6a9c:	f383 8812 	msr	BASEPRI_MAX, r3
    6aa0:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    6aa4:	4628      	mov	r0, r5
    6aa6:	f000 f991 	bl	6dcc <z_spin_lock_valid>
    6aaa:	b968      	cbnz	r0, 6ac8 <k_mem_slab_alloc+0x44>
    6aac:	2394      	movs	r3, #148	; 0x94
    6aae:	4a23      	ldr	r2, [pc, #140]	; (6b3c <k_mem_slab_alloc+0xb8>)
    6ab0:	4923      	ldr	r1, [pc, #140]	; (6b40 <k_mem_slab_alloc+0xbc>)
    6ab2:	4824      	ldr	r0, [pc, #144]	; (6b44 <k_mem_slab_alloc+0xc0>)
    6ab4:	f002 fbf7 	bl	92a6 <assert_print>
    6ab8:	4629      	mov	r1, r5
    6aba:	4823      	ldr	r0, [pc, #140]	; (6b48 <k_mem_slab_alloc+0xc4>)
    6abc:	f002 fbf3 	bl	92a6 <assert_print>
    6ac0:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    6ac2:	481e      	ldr	r0, [pc, #120]	; (6b3c <k_mem_slab_alloc+0xb8>)
    6ac4:	f002 fbe8 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    6ac8:	4628      	mov	r0, r5
    6aca:	f000 f99b 	bl	6e04 <z_spin_lock_set_owner>
	int result;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, alloc, slab, timeout);

	if (slab->free_list != NULL) {
    6ace:	69a3      	ldr	r3, [r4, #24]
    6ad0:	b1b3      	cbz	r3, 6b00 <k_mem_slab_alloc+0x7c>
		/* take a free block */
		*mem = slab->free_list;
    6ad2:	6033      	str	r3, [r6, #0]
		slab->free_list = *(char **)(slab->free_list);
    6ad4:	681b      	ldr	r3, [r3, #0]
    6ad6:	61a3      	str	r3, [r4, #24]
		slab->num_used++;
    6ad8:	69e3      	ldr	r3, [r4, #28]
    6ada:	3301      	adds	r3, #1
    6adc:	61e3      	str	r3, [r4, #28]

#ifdef CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION
		slab->max_used = MAX(slab->num_used, slab->max_used);
#endif

		result = 0;
    6ade:	2400      	movs	r4, #0
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    6ae0:	4628      	mov	r0, r5
    6ae2:	f000 f981 	bl	6de8 <z_spin_unlock_valid>
    6ae6:	bb18      	cbnz	r0, 6b30 <k_mem_slab_alloc+0xac>
    6ae8:	23c2      	movs	r3, #194	; 0xc2
    6aea:	4a14      	ldr	r2, [pc, #80]	; (6b3c <k_mem_slab_alloc+0xb8>)
    6aec:	4917      	ldr	r1, [pc, #92]	; (6b4c <k_mem_slab_alloc+0xc8>)
    6aee:	4815      	ldr	r0, [pc, #84]	; (6b44 <k_mem_slab_alloc+0xc0>)
    6af0:	f002 fbd9 	bl	92a6 <assert_print>
    6af4:	4629      	mov	r1, r5
    6af6:	4816      	ldr	r0, [pc, #88]	; (6b50 <k_mem_slab_alloc+0xcc>)
    6af8:	f002 fbd5 	bl	92a6 <assert_print>
    6afc:	21c2      	movs	r1, #194	; 0xc2
    6afe:	e7e0      	b.n	6ac2 <k_mem_slab_alloc+0x3e>
	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT) ||
    6b00:	ea58 0207 	orrs.w	r2, r8, r7
    6b04:	d103      	bne.n	6b0e <k_mem_slab_alloc+0x8a>
		   !IS_ENABLED(CONFIG_MULTITHREADING)) {
		/* don't wait for a free block to become available */
		*mem = NULL;
		result = -ENOMEM;
    6b06:	f06f 040b 	mvn.w	r4, #11
		*mem = NULL;
    6b0a:	6033      	str	r3, [r6, #0]
		result = -ENOMEM;
    6b0c:	e7e8      	b.n	6ae0 <k_mem_slab_alloc+0x5c>
	} else {
		SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_mem_slab, alloc, slab, timeout);

		/* wait for a free block or timeout */
		result = z_pend_curr(&slab->lock, key, &slab->wait_q, timeout);
    6b0e:	4622      	mov	r2, r4
    6b10:	4649      	mov	r1, r9
    6b12:	4628      	mov	r0, r5
    6b14:	e9cd 8700 	strd	r8, r7, [sp]
    6b18:	f001 f814 	bl	7b44 <z_pend_curr>
		if (result == 0) {
    6b1c:	4604      	mov	r4, r0
    6b1e:	b918      	cbnz	r0, 6b28 <k_mem_slab_alloc+0xa4>
			*mem = _current->base.swap_data;
    6b20:	4b0c      	ldr	r3, [pc, #48]	; (6b54 <k_mem_slab_alloc+0xd0>)
    6b22:	689b      	ldr	r3, [r3, #8]
    6b24:	695b      	ldr	r3, [r3, #20]
    6b26:	6033      	str	r3, [r6, #0]
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, alloc, slab, timeout, result);

	k_spin_unlock(&slab->lock, key);

	return result;
}
    6b28:	4620      	mov	r0, r4
    6b2a:	b003      	add	sp, #12
    6b2c:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
	__asm__ volatile(
    6b30:	f389 8811 	msr	BASEPRI, r9
    6b34:	f3bf 8f6f 	isb	sy
	return result;
    6b38:	e7f6      	b.n	6b28 <k_mem_slab_alloc+0xa4>
    6b3a:	bf00      	nop
    6b3c:	0000a51d 	.word	0x0000a51d
    6b40:	0000a576 	.word	0x0000a576
    6b44:	0000a2e8 	.word	0x0000a2e8
    6b48:	0000a58b 	.word	0x0000a58b
    6b4c:	0000a54a 	.word	0x0000a54a
    6b50:	0000a561 	.word	0x0000a561
    6b54:	20000ea0 	.word	0x20000ea0

00006b58 <k_mem_slab_free>:

void k_mem_slab_free(struct k_mem_slab *slab, void **mem)
{
    6b58:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6b5c:	4604      	mov	r4, r0
    6b5e:	460e      	mov	r6, r1
	k_spinlock_key_t key = k_spin_lock(&slab->lock);
    6b60:	f100 0508 	add.w	r5, r0, #8
	__asm__ volatile(
    6b64:	f04f 0320 	mov.w	r3, #32
    6b68:	f3ef 8711 	mrs	r7, BASEPRI
    6b6c:	f383 8812 	msr	BASEPRI_MAX, r3
    6b70:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    6b74:	4628      	mov	r0, r5
    6b76:	f000 f929 	bl	6dcc <z_spin_lock_valid>
    6b7a:	b968      	cbnz	r0, 6b98 <k_mem_slab_free+0x40>
    6b7c:	2394      	movs	r3, #148	; 0x94
    6b7e:	4a21      	ldr	r2, [pc, #132]	; (6c04 <k_mem_slab_free+0xac>)
    6b80:	4921      	ldr	r1, [pc, #132]	; (6c08 <k_mem_slab_free+0xb0>)
    6b82:	4822      	ldr	r0, [pc, #136]	; (6c0c <k_mem_slab_free+0xb4>)
    6b84:	f002 fb8f 	bl	92a6 <assert_print>
    6b88:	4629      	mov	r1, r5
    6b8a:	4821      	ldr	r0, [pc, #132]	; (6c10 <k_mem_slab_free+0xb8>)
    6b8c:	f002 fb8b 	bl	92a6 <assert_print>
    6b90:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    6b92:	481c      	ldr	r0, [pc, #112]	; (6c04 <k_mem_slab_free+0xac>)
    6b94:	f002 fb80 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    6b98:	4628      	mov	r0, r5
    6b9a:	f000 f933 	bl	6e04 <z_spin_lock_set_owner>

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, free, slab);
	if (slab->free_list == NULL && IS_ENABLED(CONFIG_MULTITHREADING)) {
    6b9e:	f8d4 8018 	ldr.w	r8, [r4, #24]
    6ba2:	f1b8 0f00 	cmp.w	r8, #0
    6ba6:	d10f      	bne.n	6bc8 <k_mem_slab_free+0x70>
		struct k_thread *pending_thread = z_unpend_first_thread(&slab->wait_q);
    6ba8:	4620      	mov	r0, r4
    6baa:	f001 f9ff 	bl	7fac <z_unpend_first_thread>

		if (pending_thread != NULL) {
    6bae:	b158      	cbz	r0, 6bc8 <k_mem_slab_free+0x70>
			SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

			z_thread_return_value_set_with_data(pending_thread, 0, *mem);
    6bb0:	6832      	ldr	r2, [r6, #0]
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    6bb2:	f8c0 8078 	str.w	r8, [r0, #120]	; 0x78
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    6bb6:	6142      	str	r2, [r0, #20]
			z_ready_thread(pending_thread);
    6bb8:	f000 fc6a 	bl	7490 <z_ready_thread>
			z_reschedule(&slab->lock, key);
    6bbc:	4639      	mov	r1, r7
    6bbe:	4628      	mov	r0, r5
	slab->num_used--;

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

	k_spin_unlock(&slab->lock, key);
}
    6bc0:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
			z_reschedule(&slab->lock, key);
    6bc4:	f000 bcf0 	b.w	75a8 <z_reschedule>
	**(char ***) mem = slab->free_list;
    6bc8:	6833      	ldr	r3, [r6, #0]
    6bca:	69a2      	ldr	r2, [r4, #24]
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    6bcc:	4628      	mov	r0, r5
    6bce:	601a      	str	r2, [r3, #0]
	slab->free_list = *(char **) mem;
    6bd0:	6833      	ldr	r3, [r6, #0]
    6bd2:	61a3      	str	r3, [r4, #24]
	slab->num_used--;
    6bd4:	69e3      	ldr	r3, [r4, #28]
    6bd6:	3b01      	subs	r3, #1
    6bd8:	61e3      	str	r3, [r4, #28]
    6bda:	f000 f905 	bl	6de8 <z_spin_unlock_valid>
    6bde:	b958      	cbnz	r0, 6bf8 <k_mem_slab_free+0xa0>
    6be0:	23c2      	movs	r3, #194	; 0xc2
    6be2:	4a08      	ldr	r2, [pc, #32]	; (6c04 <k_mem_slab_free+0xac>)
    6be4:	490b      	ldr	r1, [pc, #44]	; (6c14 <k_mem_slab_free+0xbc>)
    6be6:	4809      	ldr	r0, [pc, #36]	; (6c0c <k_mem_slab_free+0xb4>)
    6be8:	f002 fb5d 	bl	92a6 <assert_print>
    6bec:	4629      	mov	r1, r5
    6bee:	480a      	ldr	r0, [pc, #40]	; (6c18 <k_mem_slab_free+0xc0>)
    6bf0:	f002 fb59 	bl	92a6 <assert_print>
    6bf4:	21c2      	movs	r1, #194	; 0xc2
    6bf6:	e7cc      	b.n	6b92 <k_mem_slab_free+0x3a>
	__asm__ volatile(
    6bf8:	f387 8811 	msr	BASEPRI, r7
    6bfc:	f3bf 8f6f 	isb	sy
}
    6c00:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    6c04:	0000a51d 	.word	0x0000a51d
    6c08:	0000a576 	.word	0x0000a576
    6c0c:	0000a2e8 	.word	0x0000a2e8
    6c10:	0000a58b 	.word	0x0000a58b
    6c14:	0000a54a 	.word	0x0000a54a
    6c18:	0000a561 	.word	0x0000a561

00006c1c <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    6c1c:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
    6c1e:	9e0b      	ldr	r6, [sp, #44]	; 0x2c
    6c20:	4604      	mov	r4, r0
	char *stack_ptr;

	Z_ASSERT_VALID_PRIO(prio, entry);
    6c22:	2e0f      	cmp	r6, #15
    6c24:	d12a      	bne.n	6c7c <z_setup_new_thread+0x60>
    6c26:	4821      	ldr	r0, [pc, #132]	; (6cac <z_setup_new_thread+0x90>)
    6c28:	4283      	cmp	r3, r0
    6c2a:	d12b      	bne.n	6c84 <z_setup_new_thread+0x68>
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    6c2c:	f104 0058 	add.w	r0, r4, #88	; 0x58
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
	list->tail = (sys_dnode_t *)list;
    6c30:	e9c4 0016 	strd	r0, r0, [r4, #88]	; 0x58
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
	thread_base->user_options = (uint8_t)options;
    6c34:	980c      	ldr	r0, [sp, #48]	; 0x30
	thread_base->pended_on = NULL;
    6c36:	2500      	movs	r5, #0
	thread_base->user_options = (uint8_t)options;
    6c38:	7320      	strb	r0, [r4, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    6c3a:	2004      	movs	r0, #4
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    6c3c:	3207      	adds	r2, #7
    6c3e:	f022 0207 	bic.w	r2, r2, #7
	new_thread->stack_info.size = stack_buf_size;
    6c42:	e9c4 1219 	strd	r1, r2, [r4, #100]	; 0x64

	thread_base->prio = priority;
    6c46:	73a6      	strb	r6, [r4, #14]
	stack_ptr = (char *)stack + stack_obj_size;
    6c48:	188e      	adds	r6, r1, r2
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    6c4a:	9a0a      	ldr	r2, [sp, #40]	; 0x28
	thread_base->thread_state = (uint8_t)initial_state;
    6c4c:	7360      	strb	r0, [r4, #13]
 */

static inline void sys_dnode_init(sys_dnode_t *node)
{
	node->next = NULL;
	node->prev = NULL;
    6c4e:	e9c4 5506 	strd	r5, r5, [r4, #24]
	thread_base->pended_on = NULL;
    6c52:	60a5      	str	r5, [r4, #8]

	thread_base->sched_locked = 0U;
    6c54:	73e5      	strb	r5, [r4, #15]
	new_thread->stack_info.delta = delta;
    6c56:	66e5      	str	r5, [r4, #108]	; 0x6c
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    6c58:	9202      	str	r2, [sp, #8]
    6c5a:	9a09      	ldr	r2, [sp, #36]	; 0x24
    6c5c:	4620      	mov	r0, r4
    6c5e:	9201      	str	r2, [sp, #4]
    6c60:	9a08      	ldr	r2, [sp, #32]
    6c62:	9200      	str	r2, [sp, #0]
    6c64:	4632      	mov	r2, r6
    6c66:	f7fc fd23 	bl	36b0 <arch_new_thread>
	if (!_current) {
    6c6a:	4b11      	ldr	r3, [pc, #68]	; (6cb0 <z_setup_new_thread+0x94>)
	new_thread->init_data = NULL;
    6c6c:	6565      	str	r5, [r4, #84]	; 0x54
	if (!_current) {
    6c6e:	689b      	ldr	r3, [r3, #8]
    6c70:	b103      	cbz	r3, 6c74 <z_setup_new_thread+0x58>
	new_thread->resource_pool = _current->resource_pool;
    6c72:	6f1b      	ldr	r3, [r3, #112]	; 0x70
}
    6c74:	4630      	mov	r0, r6
    6c76:	6723      	str	r3, [r4, #112]	; 0x70
    6c78:	b004      	add	sp, #16
    6c7a:	bd70      	pop	{r4, r5, r6, pc}
	Z_ASSERT_VALID_PRIO(prio, entry);
    6c7c:	f106 0010 	add.w	r0, r6, #16
    6c80:	281e      	cmp	r0, #30
    6c82:	d9d3      	bls.n	6c2c <z_setup_new_thread+0x10>
    6c84:	f44f 7306 	mov.w	r3, #536	; 0x218
    6c88:	4a0a      	ldr	r2, [pc, #40]	; (6cb4 <z_setup_new_thread+0x98>)
    6c8a:	490b      	ldr	r1, [pc, #44]	; (6cb8 <z_setup_new_thread+0x9c>)
    6c8c:	480b      	ldr	r0, [pc, #44]	; (6cbc <z_setup_new_thread+0xa0>)
    6c8e:	f002 fb0a 	bl	92a6 <assert_print>
    6c92:	4631      	mov	r1, r6
    6c94:	480a      	ldr	r0, [pc, #40]	; (6cc0 <z_setup_new_thread+0xa4>)
    6c96:	f06f 030f 	mvn.w	r3, #15
    6c9a:	220e      	movs	r2, #14
    6c9c:	f002 fb03 	bl	92a6 <assert_print>
    6ca0:	f44f 7106 	mov.w	r1, #536	; 0x218
    6ca4:	4803      	ldr	r0, [pc, #12]	; (6cb4 <z_setup_new_thread+0x98>)
    6ca6:	f002 faf7 	bl	9298 <assert_post_action>
    6caa:	bf00      	nop
    6cac:	00006e15 	.word	0x00006e15
    6cb0:	20000ea0 	.word	0x20000ea0
    6cb4:	0000b8ef 	.word	0x0000b8ef
    6cb8:	0000b912 	.word	0x0000b912
    6cbc:	0000a2e8 	.word	0x0000a2e8
    6cc0:	0000b992 	.word	0x0000b992

00006cc4 <z_init_static_threads>:
{
    6cc4:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    6cc8:	4c39      	ldr	r4, [pc, #228]	; (6db0 <z_init_static_threads+0xec>)
	_FOREACH_STATIC_THREAD(thread_data) {
    6cca:	4d3a      	ldr	r5, [pc, #232]	; (6db4 <z_init_static_threads+0xf0>)
{
    6ccc:	b087      	sub	sp, #28
	_FOREACH_STATIC_THREAD(thread_data) {
    6cce:	42ac      	cmp	r4, r5
    6cd0:	4626      	mov	r6, r4
    6cd2:	d92a      	bls.n	6d2a <z_init_static_threads+0x66>
    6cd4:	4938      	ldr	r1, [pc, #224]	; (6db8 <z_init_static_threads+0xf4>)
    6cd6:	f240 23ee 	movw	r3, #750	; 0x2ee
    6cda:	4a38      	ldr	r2, [pc, #224]	; (6dbc <z_init_static_threads+0xf8>)
    6cdc:	4838      	ldr	r0, [pc, #224]	; (6dc0 <z_init_static_threads+0xfc>)
    6cde:	f002 fae2 	bl	92a6 <assert_print>
    6ce2:	4838      	ldr	r0, [pc, #224]	; (6dc4 <z_init_static_threads+0x100>)
    6ce4:	f002 fadf 	bl	92a6 <assert_print>
    6ce8:	f240 21ee 	movw	r1, #750	; 0x2ee
	_FOREACH_STATIC_THREAD(thread_data) {
    6cec:	4833      	ldr	r0, [pc, #204]	; (6dbc <z_init_static_threads+0xf8>)
    6cee:	f002 fad3 	bl	9298 <assert_post_action>
		z_setup_new_thread(
    6cf2:	f854 3c04 	ldr.w	r3, [r4, #-4]
    6cf6:	9305      	str	r3, [sp, #20]
    6cf8:	f854 3c10 	ldr.w	r3, [r4, #-16]
    6cfc:	9304      	str	r3, [sp, #16]
    6cfe:	f854 3c14 	ldr.w	r3, [r4, #-20]
    6d02:	9303      	str	r3, [sp, #12]
    6d04:	f854 3c18 	ldr.w	r3, [r4, #-24]
    6d08:	9302      	str	r3, [sp, #8]
    6d0a:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    6d0e:	9301      	str	r3, [sp, #4]
    6d10:	f854 3c20 	ldr.w	r3, [r4, #-32]
    6d14:	9300      	str	r3, [sp, #0]
    6d16:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    6d1a:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    6d1e:	f7ff ff7d 	bl	6c1c <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    6d22:	f854 3c30 	ldr.w	r3, [r4, #-48]
    6d26:	655e      	str	r6, [r3, #84]	; 0x54
	_FOREACH_STATIC_THREAD(thread_data) {
    6d28:	e7d1      	b.n	6cce <z_init_static_threads+0xa>
    6d2a:	42ae      	cmp	r6, r5
    6d2c:	f104 0430 	add.w	r4, r4, #48	; 0x30
    6d30:	d3df      	bcc.n	6cf2 <z_init_static_threads+0x2e>
	k_sched_lock();
    6d32:	f000 fccd 	bl	76d0 <k_sched_lock>
			return ((t * to_hz + off) / from_hz);
    6d36:	f44f 4600 	mov.w	r6, #32768	; 0x8000
    6d3a:	f240 37e7 	movw	r7, #999	; 0x3e7
	_FOREACH_STATIC_THREAD(thread_data) {
    6d3e:	4c1c      	ldr	r4, [pc, #112]	; (6db0 <z_init_static_threads+0xec>)

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    6d40:	f8df 9084 	ldr.w	r9, [pc, #132]	; 6dc8 <z_init_static_threads+0x104>
    6d44:	42ac      	cmp	r4, r5
    6d46:	d92c      	bls.n	6da2 <z_init_static_threads+0xde>
    6d48:	491b      	ldr	r1, [pc, #108]	; (6db8 <z_init_static_threads+0xf4>)
    6d4a:	f240 330d 	movw	r3, #781	; 0x30d
    6d4e:	4a1b      	ldr	r2, [pc, #108]	; (6dbc <z_init_static_threads+0xf8>)
    6d50:	481b      	ldr	r0, [pc, #108]	; (6dc0 <z_init_static_threads+0xfc>)
    6d52:	f002 faa8 	bl	92a6 <assert_print>
    6d56:	481b      	ldr	r0, [pc, #108]	; (6dc4 <z_init_static_threads+0x100>)
    6d58:	f002 faa5 	bl	92a6 <assert_print>
    6d5c:	f240 310d 	movw	r1, #781	; 0x30d
    6d60:	e7c4      	b.n	6cec <z_init_static_threads+0x28>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    6d62:	6a63      	ldr	r3, [r4, #36]	; 0x24
    6d64:	1c5a      	adds	r2, r3, #1
    6d66:	d00d      	beq.n	6d84 <z_init_static_threads+0xc0>
    6d68:	2100      	movs	r1, #0
    6d6a:	4638      	mov	r0, r7
					    K_MSEC(thread_data->init_delay));
    6d6c:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    6d70:	fbc3 0106 	smlal	r0, r1, r3, r6
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    6d74:	ea51 33c3 	orrs.w	r3, r1, r3, lsl #15
			schedule_new_thread(thread_data->init_thread,
    6d78:	f8d4 8000 	ldr.w	r8, [r4]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    6d7c:	d104      	bne.n	6d88 <z_init_static_threads+0xc4>
	z_sched_start(thread);
    6d7e:	4640      	mov	r0, r8
    6d80:	f000 fc54 	bl	762c <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    6d84:	3430      	adds	r4, #48	; 0x30
    6d86:	e7dd      	b.n	6d44 <z_init_static_threads+0x80>
    6d88:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    6d8c:	2300      	movs	r3, #0
    6d8e:	f7f9 f9e1 	bl	154 <__aeabi_uldivmod>
    6d92:	4602      	mov	r2, r0
    6d94:	460b      	mov	r3, r1
    6d96:	f108 0018 	add.w	r0, r8, #24
    6d9a:	4649      	mov	r1, r9
    6d9c:	f001 fc06 	bl	85ac <z_add_timeout>
    6da0:	e7f0      	b.n	6d84 <z_init_static_threads+0xc0>
    6da2:	d3de      	bcc.n	6d62 <z_init_static_threads+0x9e>
}
    6da4:	b007      	add	sp, #28
    6da6:	e8bd 43f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, lr}
	k_sched_unlock();
    6daa:	f000 bcfd 	b.w	77a8 <k_sched_unlock>
    6dae:	bf00      	nop
    6db0:	00009f64 	.word	0x00009f64
    6db4:	00009f64 	.word	0x00009f64
    6db8:	0000b9c3 	.word	0x0000b9c3
    6dbc:	0000b8ef 	.word	0x0000b8ef
    6dc0:	0000a2e8 	.word	0x0000a2e8
    6dc4:	0000a7bc 	.word	0x0000a7bc
    6dc8:	00007e65 	.word	0x00007e65

00006dcc <z_spin_lock_valid>:
 * them in spinlock.h is a giant header ordering headache.
 */
#ifdef CONFIG_SPIN_VALIDATE
bool z_spin_lock_valid(struct k_spinlock *l)
{
	uintptr_t thread_cpu = l->thread_cpu;
    6dcc:	6800      	ldr	r0, [r0, #0]

	if (thread_cpu != 0U) {
    6dce:	b138      	cbz	r0, 6de0 <z_spin_lock_valid+0x14>
		if ((thread_cpu & 3U) == _current_cpu->id) {
    6dd0:	4b04      	ldr	r3, [pc, #16]	; (6de4 <z_spin_lock_valid+0x18>)
    6dd2:	f000 0003 	and.w	r0, r0, #3
    6dd6:	7d1b      	ldrb	r3, [r3, #20]
    6dd8:	1ac0      	subs	r0, r0, r3
    6dda:	bf18      	it	ne
    6ddc:	2001      	movne	r0, #1
    6dde:	4770      	bx	lr
			return false;
		}
	}
	return true;
    6de0:	2001      	movs	r0, #1
}
    6de2:	4770      	bx	lr
    6de4:	20000ea0 	.word	0x20000ea0

00006de8 <z_spin_unlock_valid>:

bool z_spin_unlock_valid(struct k_spinlock *l)
{
	if (l->thread_cpu != (_current_cpu->id | (uintptr_t)_current)) {
    6de8:	4a05      	ldr	r2, [pc, #20]	; (6e00 <z_spin_unlock_valid+0x18>)
{
    6dea:	4603      	mov	r3, r0
	if (l->thread_cpu != (_current_cpu->id | (uintptr_t)_current)) {
    6dec:	7d11      	ldrb	r1, [r2, #20]
    6dee:	6892      	ldr	r2, [r2, #8]
    6df0:	430a      	orrs	r2, r1
    6df2:	6801      	ldr	r1, [r0, #0]
    6df4:	2000      	movs	r0, #0
    6df6:	4291      	cmp	r1, r2
		return false;
	}
	l->thread_cpu = 0;
    6df8:	bf04      	itt	eq
    6dfa:	6018      	streq	r0, [r3, #0]
	return true;
    6dfc:	2001      	moveq	r0, #1
}
    6dfe:	4770      	bx	lr
    6e00:	20000ea0 	.word	0x20000ea0

00006e04 <z_spin_lock_set_owner>:

void z_spin_lock_set_owner(struct k_spinlock *l)
{
	l->thread_cpu = _current_cpu->id | (uintptr_t)_current;
    6e04:	4b02      	ldr	r3, [pc, #8]	; (6e10 <z_spin_lock_set_owner+0xc>)
    6e06:	7d1a      	ldrb	r2, [r3, #20]
    6e08:	689b      	ldr	r3, [r3, #8]
    6e0a:	4313      	orrs	r3, r2
    6e0c:	6003      	str	r3, [r0, #0]
}
    6e0e:	4770      	bx	lr
    6e10:	20000ea0 	.word	0x20000ea0

00006e14 <idle>:
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
}

void idle(void *unused1, void *unused2, void *unused3)
{
    6e14:	b508      	push	{r3, lr}
	ARG_UNUSED(unused1);
	ARG_UNUSED(unused2);
	ARG_UNUSED(unused3);

	__ASSERT_NO_MSG(_current->base.prio >= 0);
    6e16:	4c13      	ldr	r4, [pc, #76]	; (6e64 <idle+0x50>)
    6e18:	68a3      	ldr	r3, [r4, #8]
    6e1a:	f993 300e 	ldrsb.w	r3, [r3, #14]
    6e1e:	2b00      	cmp	r3, #0
    6e20:	db10      	blt.n	6e44 <idle+0x30>
	return !z_sys_post_kernel;
    6e22:	4d11      	ldr	r5, [pc, #68]	; (6e68 <idle+0x54>)
	__asm__ volatile(
    6e24:	f04f 0220 	mov.w	r2, #32
    6e28:	f3ef 8311 	mrs	r3, BASEPRI
    6e2c:	f382 8812 	msr	BASEPRI_MAX, r2
    6e30:	f3bf 8f6f 	isb	sy
		 * higher level construct.
		 */
		(void) arch_irq_lock();

#ifdef CONFIG_PM
		_kernel.idle = z_get_next_timeout_expiry();
    6e34:	f001 fccc 	bl	87d0 <z_get_next_timeout_expiry>
		 * processing in those cases i.e. skips k_cpu_idle().
		 * The kernel's idle processing re-enables interrupts
		 * which is essential for the kernel's scheduling
		 * logic.
		 */
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    6e38:	782b      	ldrb	r3, [r5, #0]
		_kernel.idle = z_get_next_timeout_expiry();
    6e3a:	61a0      	str	r0, [r4, #24]
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    6e3c:	b963      	cbnz	r3, 6e58 <idle+0x44>
	arch_cpu_idle();
    6e3e:	f7fc fad3 	bl	33e8 <arch_cpu_idle>
}
    6e42:	e7ef      	b.n	6e24 <idle+0x10>
	__ASSERT_NO_MSG(_current->base.prio >= 0);
    6e44:	4909      	ldr	r1, [pc, #36]	; (6e6c <idle+0x58>)
    6e46:	480a      	ldr	r0, [pc, #40]	; (6e70 <idle+0x5c>)
    6e48:	2327      	movs	r3, #39	; 0x27
    6e4a:	4a0a      	ldr	r2, [pc, #40]	; (6e74 <idle+0x60>)
    6e4c:	f002 fa2b 	bl	92a6 <assert_print>
    6e50:	2127      	movs	r1, #39	; 0x27
    6e52:	4808      	ldr	r0, [pc, #32]	; (6e74 <idle+0x60>)
    6e54:	f002 fa20 	bl	9298 <assert_post_action>
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    6e58:	f7fc f8c6 	bl	2fe8 <pm_system_suspend>
    6e5c:	2800      	cmp	r0, #0
    6e5e:	d1e1      	bne.n	6e24 <idle+0x10>
    6e60:	e7ed      	b.n	6e3e <idle+0x2a>
    6e62:	bf00      	nop
    6e64:	20000ea0 	.word	0x20000ea0
    6e68:	200010ce 	.word	0x200010ce
    6e6c:	0000ba11 	.word	0x0000ba11
    6e70:	0000a2e8 	.word	0x0000a2e8
    6e74:	0000b9f0 	.word	0x0000b9f0

00006e78 <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
    6e78:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    6e7c:	4604      	mov	r4, r0
    6e7e:	4617      	mov	r7, r2
    6e80:	461e      	mov	r6, r3
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    6e82:	f3ef 8505 	mrs	r5, IPSR
	int new_prio;
	k_spinlock_key_t key;
	bool resched = false;

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");
    6e86:	b165      	cbz	r5, 6ea2 <z_impl_k_mutex_lock+0x2a>
    6e88:	4958      	ldr	r1, [pc, #352]	; (6fec <z_impl_k_mutex_lock+0x174>)
    6e8a:	2365      	movs	r3, #101	; 0x65
    6e8c:	4a58      	ldr	r2, [pc, #352]	; (6ff0 <z_impl_k_mutex_lock+0x178>)
    6e8e:	4859      	ldr	r0, [pc, #356]	; (6ff4 <z_impl_k_mutex_lock+0x17c>)
    6e90:	f002 fa09 	bl	92a6 <assert_print>
    6e94:	4858      	ldr	r0, [pc, #352]	; (6ff8 <z_impl_k_mutex_lock+0x180>)
    6e96:	f002 fa06 	bl	92a6 <assert_print>
    6e9a:	2165      	movs	r1, #101	; 0x65
    6e9c:	4854      	ldr	r0, [pc, #336]	; (6ff0 <z_impl_k_mutex_lock+0x178>)
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    6e9e:	f002 f9fb 	bl	9298 <assert_post_action>
    6ea2:	f04f 0320 	mov.w	r3, #32
    6ea6:	f3ef 8811 	mrs	r8, BASEPRI
    6eaa:	f383 8812 	msr	BASEPRI_MAX, r3
    6eae:	f3bf 8f6f 	isb	sy
    6eb2:	4852      	ldr	r0, [pc, #328]	; (6ffc <z_impl_k_mutex_lock+0x184>)
    6eb4:	f7ff ff8a 	bl	6dcc <z_spin_lock_valid>
    6eb8:	b960      	cbnz	r0, 6ed4 <z_impl_k_mutex_lock+0x5c>
    6eba:	2394      	movs	r3, #148	; 0x94
    6ebc:	4a50      	ldr	r2, [pc, #320]	; (7000 <z_impl_k_mutex_lock+0x188>)
    6ebe:	4951      	ldr	r1, [pc, #324]	; (7004 <z_impl_k_mutex_lock+0x18c>)
    6ec0:	484c      	ldr	r0, [pc, #304]	; (6ff4 <z_impl_k_mutex_lock+0x17c>)
    6ec2:	f002 f9f0 	bl	92a6 <assert_print>
    6ec6:	494d      	ldr	r1, [pc, #308]	; (6ffc <z_impl_k_mutex_lock+0x184>)
    6ec8:	484f      	ldr	r0, [pc, #316]	; (7008 <z_impl_k_mutex_lock+0x190>)
    6eca:	f002 f9ec 	bl	92a6 <assert_print>
    6ece:	2194      	movs	r1, #148	; 0x94
    6ed0:	484b      	ldr	r0, [pc, #300]	; (7000 <z_impl_k_mutex_lock+0x188>)
    6ed2:	e7e4      	b.n	6e9e <z_impl_k_mutex_lock+0x26>
	z_spin_lock_set_owner(l);
    6ed4:	4849      	ldr	r0, [pc, #292]	; (6ffc <z_impl_k_mutex_lock+0x184>)
    6ed6:	f7ff ff95 	bl	6e04 <z_spin_lock_set_owner>

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, lock, mutex, timeout);

	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    6eda:	68e3      	ldr	r3, [r4, #12]
    6edc:	4a4b      	ldr	r2, [pc, #300]	; (700c <z_impl_k_mutex_lock+0x194>)
    6ede:	b19b      	cbz	r3, 6f08 <z_impl_k_mutex_lock+0x90>
    6ee0:	68a0      	ldr	r0, [r4, #8]
    6ee2:	6891      	ldr	r1, [r2, #8]
    6ee4:	4288      	cmp	r0, r1
    6ee6:	d027      	beq.n	6f38 <z_impl_k_mutex_lock+0xc0>
		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, 0);

		return 0;
	}

	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
    6ee8:	ea57 0306 	orrs.w	r3, r7, r6
    6eec:	d12c      	bne.n	6f48 <z_impl_k_mutex_lock+0xd0>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    6eee:	4843      	ldr	r0, [pc, #268]	; (6ffc <z_impl_k_mutex_lock+0x184>)
    6ef0:	f7ff ff7a 	bl	6de8 <z_spin_unlock_valid>
    6ef4:	b1a0      	cbz	r0, 6f20 <z_impl_k_mutex_lock+0xa8>
	__asm__ volatile(
    6ef6:	f388 8811 	msr	BASEPRI, r8
    6efa:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);

		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EBUSY);

		return -EBUSY;
    6efe:	f06f 000f 	mvn.w	r0, #15
	}

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EAGAIN);

	return -EAGAIN;
}
    6f02:	b002      	add	sp, #8
    6f04:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
					_current->base.prio :
    6f08:	6891      	ldr	r1, [r2, #8]
    6f0a:	f991 100e 	ldrsb.w	r1, [r1, #14]
		mutex->lock_count++;
    6f0e:	3301      	adds	r3, #1
    6f10:	60e3      	str	r3, [r4, #12]
		mutex->owner = _current;
    6f12:	6893      	ldr	r3, [r2, #8]
    6f14:	4839      	ldr	r0, [pc, #228]	; (6ffc <z_impl_k_mutex_lock+0x184>)
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
    6f16:	6121      	str	r1, [r4, #16]
		mutex->owner = _current;
    6f18:	60a3      	str	r3, [r4, #8]
    6f1a:	f7ff ff65 	bl	6de8 <z_spin_unlock_valid>
    6f1e:	b968      	cbnz	r0, 6f3c <z_impl_k_mutex_lock+0xc4>
    6f20:	23c2      	movs	r3, #194	; 0xc2
    6f22:	4a37      	ldr	r2, [pc, #220]	; (7000 <z_impl_k_mutex_lock+0x188>)
    6f24:	493a      	ldr	r1, [pc, #232]	; (7010 <z_impl_k_mutex_lock+0x198>)
    6f26:	4833      	ldr	r0, [pc, #204]	; (6ff4 <z_impl_k_mutex_lock+0x17c>)
    6f28:	f002 f9bd 	bl	92a6 <assert_print>
    6f2c:	4933      	ldr	r1, [pc, #204]	; (6ffc <z_impl_k_mutex_lock+0x184>)
    6f2e:	4839      	ldr	r0, [pc, #228]	; (7014 <z_impl_k_mutex_lock+0x19c>)
    6f30:	f002 f9b9 	bl	92a6 <assert_print>
    6f34:	21c2      	movs	r1, #194	; 0xc2
    6f36:	e7cb      	b.n	6ed0 <z_impl_k_mutex_lock+0x58>
					_current->base.prio :
    6f38:	6921      	ldr	r1, [r4, #16]
    6f3a:	e7e8      	b.n	6f0e <z_impl_k_mutex_lock+0x96>
    6f3c:	f388 8811 	msr	BASEPRI, r8
    6f40:	f3bf 8f6f 	isb	sy
		return 0;
    6f44:	2000      	movs	r0, #0
    6f46:	e7dc      	b.n	6f02 <z_impl_k_mutex_lock+0x8a>
	new_prio = new_prio_for_inheritance(_current->base.prio,
    6f48:	f991 100e 	ldrsb.w	r1, [r1, #14]
    6f4c:	f990 300e 	ldrsb.w	r3, [r0, #14]
	return prio >= CONFIG_PRIORITY_CEILING;
}

static inline int z_get_new_prio_with_ceiling(int prio)
{
	return z_is_under_prio_ceiling(prio) ? prio : CONFIG_PRIORITY_CEILING;
    6f50:	f06f 027e 	mvn.w	r2, #126	; 0x7e
    6f54:	4299      	cmp	r1, r3
    6f56:	bfa8      	it	ge
    6f58:	4619      	movge	r1, r3
    6f5a:	4291      	cmp	r1, r2
    6f5c:	bfb8      	it	lt
    6f5e:	4611      	movlt	r1, r2
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
    6f60:	428b      	cmp	r3, r1
    6f62:	dd02      	ble.n	6f6a <z_impl_k_mutex_lock+0xf2>
		resched = adjust_owner_prio(mutex, new_prio);
    6f64:	f002 fe1b 	bl	9b9e <adjust_owner_prio.isra.0>
    6f68:	4605      	mov	r5, r0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
    6f6a:	4622      	mov	r2, r4
    6f6c:	4641      	mov	r1, r8
    6f6e:	e9cd 7600 	strd	r7, r6, [sp]
    6f72:	4822      	ldr	r0, [pc, #136]	; (6ffc <z_impl_k_mutex_lock+0x184>)
    6f74:	f000 fde6 	bl	7b44 <z_pend_curr>
	if (got_mutex == 0) {
    6f78:	2800      	cmp	r0, #0
    6f7a:	d0e3      	beq.n	6f44 <z_impl_k_mutex_lock+0xcc>
	__asm__ volatile(
    6f7c:	f04f 0320 	mov.w	r3, #32
    6f80:	f3ef 8611 	mrs	r6, BASEPRI
    6f84:	f383 8812 	msr	BASEPRI_MAX, r3
    6f88:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    6f8c:	481b      	ldr	r0, [pc, #108]	; (6ffc <z_impl_k_mutex_lock+0x184>)
    6f8e:	f7ff ff1d 	bl	6dcc <z_spin_lock_valid>
    6f92:	2800      	cmp	r0, #0
    6f94:	d091      	beq.n	6eba <z_impl_k_mutex_lock+0x42>
	z_spin_lock_set_owner(l);
    6f96:	4819      	ldr	r0, [pc, #100]	; (6ffc <z_impl_k_mutex_lock+0x184>)
    6f98:	f7ff ff34 	bl	6e04 <z_spin_lock_set_owner>
	if (likely(mutex->owner != NULL)) {
    6f9c:	68a0      	ldr	r0, [r4, #8]
    6f9e:	b1c0      	cbz	r0, 6fd2 <z_impl_k_mutex_lock+0x15a>
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    6fa0:	6823      	ldr	r3, [r4, #0]
			new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    6fa2:	6921      	ldr	r1, [r4, #16]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    6fa4:	429c      	cmp	r4, r3
    6fa6:	d00a      	beq.n	6fbe <z_impl_k_mutex_lock+0x146>
    6fa8:	b14b      	cbz	r3, 6fbe <z_impl_k_mutex_lock+0x146>
    6faa:	f993 300e 	ldrsb.w	r3, [r3, #14]
    6fae:	4299      	cmp	r1, r3
    6fb0:	bfa8      	it	ge
    6fb2:	4619      	movge	r1, r3
    6fb4:	f06f 037e 	mvn.w	r3, #126	; 0x7e
    6fb8:	4299      	cmp	r1, r3
    6fba:	bfb8      	it	lt
    6fbc:	4619      	movlt	r1, r3
		resched = adjust_owner_prio(mutex, new_prio) || resched;
    6fbe:	f002 fdee 	bl	9b9e <adjust_owner_prio.isra.0>
    6fc2:	b130      	cbz	r0, 6fd2 <z_impl_k_mutex_lock+0x15a>
		z_reschedule(&lock, key);
    6fc4:	4631      	mov	r1, r6
    6fc6:	480d      	ldr	r0, [pc, #52]	; (6ffc <z_impl_k_mutex_lock+0x184>)
    6fc8:	f000 faee 	bl	75a8 <z_reschedule>
	return -EAGAIN;
    6fcc:	f06f 000a 	mvn.w	r0, #10
    6fd0:	e797      	b.n	6f02 <z_impl_k_mutex_lock+0x8a>
	if (resched) {
    6fd2:	2d00      	cmp	r5, #0
    6fd4:	d1f6      	bne.n	6fc4 <z_impl_k_mutex_lock+0x14c>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    6fd6:	4809      	ldr	r0, [pc, #36]	; (6ffc <z_impl_k_mutex_lock+0x184>)
    6fd8:	f7ff ff06 	bl	6de8 <z_spin_unlock_valid>
    6fdc:	2800      	cmp	r0, #0
    6fde:	d09f      	beq.n	6f20 <z_impl_k_mutex_lock+0xa8>
	__asm__ volatile(
    6fe0:	f386 8811 	msr	BASEPRI, r6
    6fe4:	f3bf 8f6f 	isb	sy
    6fe8:	e7f0      	b.n	6fcc <z_impl_k_mutex_lock+0x154>
    6fea:	bf00      	nop
    6fec:	0000ba5b 	.word	0x0000ba5b
    6ff0:	0000ba39 	.word	0x0000ba39
    6ff4:	0000a2e8 	.word	0x0000a2e8
    6ff8:	0000ba6d 	.word	0x0000ba6d
    6ffc:	20000ec8 	.word	0x20000ec8
    7000:	0000a51d 	.word	0x0000a51d
    7004:	0000a576 	.word	0x0000a576
    7008:	0000a58b 	.word	0x0000a58b
    700c:	20000ea0 	.word	0x20000ea0
    7010:	0000a54a 	.word	0x0000a54a
    7014:	0000a561 	.word	0x0000a561

00007018 <z_impl_k_mutex_unlock>:
}
#include <syscalls/k_mutex_lock_mrsh.c>
#endif

int z_impl_k_mutex_unlock(struct k_mutex *mutex)
{
    7018:	b570      	push	{r4, r5, r6, lr}
    701a:	4604      	mov	r4, r0
    701c:	f3ef 8605 	mrs	r6, IPSR
	struct k_thread *new_owner;

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");
    7020:	b166      	cbz	r6, 703c <z_impl_k_mutex_unlock+0x24>
    7022:	4938      	ldr	r1, [pc, #224]	; (7104 <z_impl_k_mutex_unlock+0xec>)
    7024:	23cd      	movs	r3, #205	; 0xcd
    7026:	4a38      	ldr	r2, [pc, #224]	; (7108 <z_impl_k_mutex_unlock+0xf0>)
    7028:	4838      	ldr	r0, [pc, #224]	; (710c <z_impl_k_mutex_unlock+0xf4>)
    702a:	f002 f93c 	bl	92a6 <assert_print>
    702e:	4838      	ldr	r0, [pc, #224]	; (7110 <z_impl_k_mutex_unlock+0xf8>)
    7030:	f002 f939 	bl	92a6 <assert_print>
    7034:	21cd      	movs	r1, #205	; 0xcd
	 * Attempt to unlock a mutex which is unlocked. mutex->lock_count
	 * cannot be zero if the current thread is equal to mutex->owner,
	 * therefore no underflow check is required. Use assert to catch
	 * undefined behavior.
	 */
	__ASSERT_NO_MSG(mutex->lock_count > 0U);
    7036:	4834      	ldr	r0, [pc, #208]	; (7108 <z_impl_k_mutex_unlock+0xf0>)
    7038:	f002 f92e 	bl	9298 <assert_post_action>
	CHECKIF(mutex->owner == NULL) {
    703c:	6883      	ldr	r3, [r0, #8]
    703e:	2b00      	cmp	r3, #0
    7040:	d059      	beq.n	70f6 <z_impl_k_mutex_unlock+0xde>
	CHECKIF(mutex->owner != _current) {
    7042:	4a34      	ldr	r2, [pc, #208]	; (7114 <z_impl_k_mutex_unlock+0xfc>)
    7044:	6892      	ldr	r2, [r2, #8]
    7046:	4293      	cmp	r3, r2
    7048:	d158      	bne.n	70fc <z_impl_k_mutex_unlock+0xe4>
	__ASSERT_NO_MSG(mutex->lock_count > 0U);
    704a:	68c3      	ldr	r3, [r0, #12]
    704c:	b93b      	cbnz	r3, 705e <z_impl_k_mutex_unlock+0x46>
    704e:	4932      	ldr	r1, [pc, #200]	; (7118 <z_impl_k_mutex_unlock+0x100>)
    7050:	23e5      	movs	r3, #229	; 0xe5
    7052:	4a2d      	ldr	r2, [pc, #180]	; (7108 <z_impl_k_mutex_unlock+0xf0>)
    7054:	482d      	ldr	r0, [pc, #180]	; (710c <z_impl_k_mutex_unlock+0xf4>)
    7056:	f002 f926 	bl	92a6 <assert_print>
    705a:	21e5      	movs	r1, #229	; 0xe5
    705c:	e7eb      	b.n	7036 <z_impl_k_mutex_unlock+0x1e>

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count > 1U) {
    705e:	2b01      	cmp	r3, #1
    7060:	d003      	beq.n	706a <z_impl_k_mutex_unlock+0x52>
		mutex->lock_count--;
    7062:	3b01      	subs	r3, #1
    7064:	60c3      	str	r3, [r0, #12]


k_mutex_unlock_return:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, unlock, mutex, 0);

	return 0;
    7066:	2000      	movs	r0, #0
}
    7068:	bd70      	pop	{r4, r5, r6, pc}
	__asm__ volatile(
    706a:	f04f 0320 	mov.w	r3, #32
    706e:	f3ef 8511 	mrs	r5, BASEPRI
    7072:	f383 8812 	msr	BASEPRI_MAX, r3
    7076:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    707a:	4828      	ldr	r0, [pc, #160]	; (711c <z_impl_k_mutex_unlock+0x104>)
    707c:	f7ff fea6 	bl	6dcc <z_spin_lock_valid>
    7080:	b960      	cbnz	r0, 709c <z_impl_k_mutex_unlock+0x84>
    7082:	2394      	movs	r3, #148	; 0x94
    7084:	4a26      	ldr	r2, [pc, #152]	; (7120 <z_impl_k_mutex_unlock+0x108>)
    7086:	4927      	ldr	r1, [pc, #156]	; (7124 <z_impl_k_mutex_unlock+0x10c>)
    7088:	4820      	ldr	r0, [pc, #128]	; (710c <z_impl_k_mutex_unlock+0xf4>)
    708a:	f002 f90c 	bl	92a6 <assert_print>
    708e:	4923      	ldr	r1, [pc, #140]	; (711c <z_impl_k_mutex_unlock+0x104>)
    7090:	4825      	ldr	r0, [pc, #148]	; (7128 <z_impl_k_mutex_unlock+0x110>)
    7092:	f002 f908 	bl	92a6 <assert_print>
    7096:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7098:	4821      	ldr	r0, [pc, #132]	; (7120 <z_impl_k_mutex_unlock+0x108>)
    709a:	e7cd      	b.n	7038 <z_impl_k_mutex_unlock+0x20>
	z_spin_lock_set_owner(l);
    709c:	481f      	ldr	r0, [pc, #124]	; (711c <z_impl_k_mutex_unlock+0x104>)
    709e:	f7ff feb1 	bl	6e04 <z_spin_lock_set_owner>
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
    70a2:	6921      	ldr	r1, [r4, #16]
    70a4:	68a0      	ldr	r0, [r4, #8]
    70a6:	f002 fd7a 	bl	9b9e <adjust_owner_prio.isra.0>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
    70aa:	4620      	mov	r0, r4
    70ac:	f000 ff7e 	bl	7fac <z_unpend_first_thread>
	mutex->owner = new_owner;
    70b0:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
    70b2:	b150      	cbz	r0, 70ca <z_impl_k_mutex_unlock+0xb2>
		mutex->owner_orig_prio = new_owner->base.prio;
    70b4:	f990 200e 	ldrsb.w	r2, [r0, #14]
    70b8:	6122      	str	r2, [r4, #16]
    70ba:	6786      	str	r6, [r0, #120]	; 0x78
		z_ready_thread(new_owner);
    70bc:	f000 f9e8 	bl	7490 <z_ready_thread>
		z_reschedule(&lock, key);
    70c0:	4629      	mov	r1, r5
    70c2:	4816      	ldr	r0, [pc, #88]	; (711c <z_impl_k_mutex_unlock+0x104>)
    70c4:	f000 fa70 	bl	75a8 <z_reschedule>
    70c8:	e7cd      	b.n	7066 <z_impl_k_mutex_unlock+0x4e>
		mutex->lock_count = 0U;
    70ca:	60e0      	str	r0, [r4, #12]
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    70cc:	4813      	ldr	r0, [pc, #76]	; (711c <z_impl_k_mutex_unlock+0x104>)
    70ce:	f7ff fe8b 	bl	6de8 <z_spin_unlock_valid>
    70d2:	b958      	cbnz	r0, 70ec <z_impl_k_mutex_unlock+0xd4>
    70d4:	23c2      	movs	r3, #194	; 0xc2
    70d6:	4a12      	ldr	r2, [pc, #72]	; (7120 <z_impl_k_mutex_unlock+0x108>)
    70d8:	4914      	ldr	r1, [pc, #80]	; (712c <z_impl_k_mutex_unlock+0x114>)
    70da:	480c      	ldr	r0, [pc, #48]	; (710c <z_impl_k_mutex_unlock+0xf4>)
    70dc:	f002 f8e3 	bl	92a6 <assert_print>
    70e0:	490e      	ldr	r1, [pc, #56]	; (711c <z_impl_k_mutex_unlock+0x104>)
    70e2:	4813      	ldr	r0, [pc, #76]	; (7130 <z_impl_k_mutex_unlock+0x118>)
    70e4:	f002 f8df 	bl	92a6 <assert_print>
    70e8:	21c2      	movs	r1, #194	; 0xc2
    70ea:	e7d5      	b.n	7098 <z_impl_k_mutex_unlock+0x80>
	__asm__ volatile(
    70ec:	f385 8811 	msr	BASEPRI, r5
    70f0:	f3bf 8f6f 	isb	sy
    70f4:	e7b7      	b.n	7066 <z_impl_k_mutex_unlock+0x4e>
		return -EINVAL;
    70f6:	f06f 0015 	mvn.w	r0, #21
    70fa:	e7b5      	b.n	7068 <z_impl_k_mutex_unlock+0x50>
		return -EPERM;
    70fc:	f04f 30ff 	mov.w	r0, #4294967295
    7100:	e7b2      	b.n	7068 <z_impl_k_mutex_unlock+0x50>
    7102:	bf00      	nop
    7104:	0000ba5b 	.word	0x0000ba5b
    7108:	0000ba39 	.word	0x0000ba39
    710c:	0000a2e8 	.word	0x0000a2e8
    7110:	0000ba6d 	.word	0x0000ba6d
    7114:	20000ea0 	.word	0x20000ea0
    7118:	0000ba92 	.word	0x0000ba92
    711c:	20000ec8 	.word	0x20000ec8
    7120:	0000a51d 	.word	0x0000a51d
    7124:	0000a576 	.word	0x0000a576
    7128:	0000a58b 	.word	0x0000a58b
    712c:	0000a54a 	.word	0x0000a54a
    7130:	0000a561 	.word	0x0000a561

00007134 <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    7134:	b538      	push	{r3, r4, r5, lr}
    7136:	4604      	mov	r4, r0
	__asm__ volatile(
    7138:	f04f 0320 	mov.w	r3, #32
    713c:	f3ef 8511 	mrs	r5, BASEPRI
    7140:	f383 8812 	msr	BASEPRI_MAX, r3
    7144:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    7148:	4814      	ldr	r0, [pc, #80]	; (719c <z_impl_k_sem_give+0x68>)
    714a:	f7ff fe3f 	bl	6dcc <z_spin_lock_valid>
    714e:	b968      	cbnz	r0, 716c <z_impl_k_sem_give+0x38>
    7150:	2394      	movs	r3, #148	; 0x94
    7152:	4a13      	ldr	r2, [pc, #76]	; (71a0 <z_impl_k_sem_give+0x6c>)
    7154:	4913      	ldr	r1, [pc, #76]	; (71a4 <z_impl_k_sem_give+0x70>)
    7156:	4814      	ldr	r0, [pc, #80]	; (71a8 <z_impl_k_sem_give+0x74>)
    7158:	f002 f8a5 	bl	92a6 <assert_print>
    715c:	490f      	ldr	r1, [pc, #60]	; (719c <z_impl_k_sem_give+0x68>)
    715e:	4813      	ldr	r0, [pc, #76]	; (71ac <z_impl_k_sem_give+0x78>)
    7160:	f002 f8a1 	bl	92a6 <assert_print>
    7164:	2194      	movs	r1, #148	; 0x94
    7166:	480e      	ldr	r0, [pc, #56]	; (71a0 <z_impl_k_sem_give+0x6c>)
    7168:	f002 f896 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    716c:	480b      	ldr	r0, [pc, #44]	; (719c <z_impl_k_sem_give+0x68>)
    716e:	f7ff fe49 	bl	6e04 <z_spin_lock_set_owner>
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    7172:	4620      	mov	r0, r4
    7174:	f000 ff1a 	bl	7fac <z_unpend_first_thread>

	if (thread != NULL) {
    7178:	b148      	cbz	r0, 718e <z_impl_k_sem_give+0x5a>
    717a:	2200      	movs	r2, #0
    717c:	6782      	str	r2, [r0, #120]	; 0x78
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    717e:	f000 f987 	bl	7490 <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    7182:	4629      	mov	r1, r5

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    7184:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    7188:	4804      	ldr	r0, [pc, #16]	; (719c <z_impl_k_sem_give+0x68>)
    718a:	f000 ba0d 	b.w	75a8 <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    718e:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    7192:	429a      	cmp	r2, r3
    7194:	bf18      	it	ne
    7196:	3301      	addne	r3, #1
    7198:	60a3      	str	r3, [r4, #8]
}
    719a:	e7f2      	b.n	7182 <z_impl_k_sem_give+0x4e>
    719c:	20000ecc 	.word	0x20000ecc
    71a0:	0000a51d 	.word	0x0000a51d
    71a4:	0000a576 	.word	0x0000a576
    71a8:	0000a2e8 	.word	0x0000a2e8
    71ac:	0000a58b 	.word	0x0000a58b

000071b0 <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    71b0:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    71b2:	4604      	mov	r4, r0
    71b4:	4616      	mov	r6, r2
    71b6:	461d      	mov	r5, r3
    71b8:	f3ef 8305 	mrs	r3, IPSR
	int ret = 0;

	__ASSERT(((arch_is_in_isr() == false) ||
    71bc:	b17b      	cbz	r3, 71de <z_impl_k_sem_take+0x2e>
    71be:	ea52 0305 	orrs.w	r3, r2, r5
    71c2:	d00c      	beq.n	71de <z_impl_k_sem_take+0x2e>
    71c4:	492d      	ldr	r1, [pc, #180]	; (727c <z_impl_k_sem_take+0xcc>)
    71c6:	2379      	movs	r3, #121	; 0x79
    71c8:	4a2d      	ldr	r2, [pc, #180]	; (7280 <z_impl_k_sem_take+0xd0>)
    71ca:	482e      	ldr	r0, [pc, #184]	; (7284 <z_impl_k_sem_take+0xd4>)
    71cc:	f002 f86b 	bl	92a6 <assert_print>
    71d0:	482d      	ldr	r0, [pc, #180]	; (7288 <z_impl_k_sem_take+0xd8>)
    71d2:	f002 f868 	bl	92a6 <assert_print>
    71d6:	2179      	movs	r1, #121	; 0x79
    71d8:	4829      	ldr	r0, [pc, #164]	; (7280 <z_impl_k_sem_take+0xd0>)
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    71da:	f002 f85d 	bl	9298 <assert_post_action>
    71de:	f04f 0320 	mov.w	r3, #32
    71e2:	f3ef 8711 	mrs	r7, BASEPRI
    71e6:	f383 8812 	msr	BASEPRI_MAX, r3
    71ea:	f3bf 8f6f 	isb	sy
    71ee:	4827      	ldr	r0, [pc, #156]	; (728c <z_impl_k_sem_take+0xdc>)
    71f0:	f7ff fdec 	bl	6dcc <z_spin_lock_valid>
    71f4:	b960      	cbnz	r0, 7210 <z_impl_k_sem_take+0x60>
    71f6:	2394      	movs	r3, #148	; 0x94
    71f8:	4a25      	ldr	r2, [pc, #148]	; (7290 <z_impl_k_sem_take+0xe0>)
    71fa:	4926      	ldr	r1, [pc, #152]	; (7294 <z_impl_k_sem_take+0xe4>)
    71fc:	4821      	ldr	r0, [pc, #132]	; (7284 <z_impl_k_sem_take+0xd4>)
    71fe:	f002 f852 	bl	92a6 <assert_print>
    7202:	4922      	ldr	r1, [pc, #136]	; (728c <z_impl_k_sem_take+0xdc>)
    7204:	4824      	ldr	r0, [pc, #144]	; (7298 <z_impl_k_sem_take+0xe8>)
    7206:	f002 f84e 	bl	92a6 <assert_print>
    720a:	2194      	movs	r1, #148	; 0x94
    720c:	4820      	ldr	r0, [pc, #128]	; (7290 <z_impl_k_sem_take+0xe0>)
    720e:	e7e4      	b.n	71da <z_impl_k_sem_take+0x2a>
	z_spin_lock_set_owner(l);
    7210:	481e      	ldr	r0, [pc, #120]	; (728c <z_impl_k_sem_take+0xdc>)
    7212:	f7ff fdf7 	bl	6e04 <z_spin_lock_set_owner>

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    7216:	68a3      	ldr	r3, [r4, #8]
    7218:	b1c3      	cbz	r3, 724c <z_impl_k_sem_take+0x9c>
		sem->count--;
    721a:	3b01      	subs	r3, #1
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    721c:	481b      	ldr	r0, [pc, #108]	; (728c <z_impl_k_sem_take+0xdc>)
    721e:	60a3      	str	r3, [r4, #8]
    7220:	f7ff fde2 	bl	6de8 <z_spin_unlock_valid>
    7224:	b958      	cbnz	r0, 723e <z_impl_k_sem_take+0x8e>
    7226:	23c2      	movs	r3, #194	; 0xc2
    7228:	4a19      	ldr	r2, [pc, #100]	; (7290 <z_impl_k_sem_take+0xe0>)
    722a:	491c      	ldr	r1, [pc, #112]	; (729c <z_impl_k_sem_take+0xec>)
    722c:	4815      	ldr	r0, [pc, #84]	; (7284 <z_impl_k_sem_take+0xd4>)
    722e:	f002 f83a 	bl	92a6 <assert_print>
    7232:	4916      	ldr	r1, [pc, #88]	; (728c <z_impl_k_sem_take+0xdc>)
    7234:	481a      	ldr	r0, [pc, #104]	; (72a0 <z_impl_k_sem_take+0xf0>)
    7236:	f002 f836 	bl	92a6 <assert_print>
    723a:	21c2      	movs	r1, #194	; 0xc2
    723c:	e7e6      	b.n	720c <z_impl_k_sem_take+0x5c>
	__asm__ volatile(
    723e:	f387 8811 	msr	BASEPRI, r7
    7242:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    7246:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    7248:	b003      	add	sp, #12
    724a:	bdf0      	pop	{r4, r5, r6, r7, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    724c:	ea56 0305 	orrs.w	r3, r6, r5
    7250:	d10b      	bne.n	726a <z_impl_k_sem_take+0xba>
    7252:	480e      	ldr	r0, [pc, #56]	; (728c <z_impl_k_sem_take+0xdc>)
    7254:	f7ff fdc8 	bl	6de8 <z_spin_unlock_valid>
    7258:	2800      	cmp	r0, #0
    725a:	d0e4      	beq.n	7226 <z_impl_k_sem_take+0x76>
    725c:	f387 8811 	msr	BASEPRI, r7
    7260:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    7264:	f06f 000f 	mvn.w	r0, #15
    7268:	e7ee      	b.n	7248 <z_impl_k_sem_take+0x98>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    726a:	4622      	mov	r2, r4
    726c:	4639      	mov	r1, r7
    726e:	e9cd 6500 	strd	r6, r5, [sp]
    7272:	4806      	ldr	r0, [pc, #24]	; (728c <z_impl_k_sem_take+0xdc>)
    7274:	f000 fc66 	bl	7b44 <z_pend_curr>
	return ret;
    7278:	e7e6      	b.n	7248 <z_impl_k_sem_take+0x98>
    727a:	bf00      	nop
    727c:	0000bac9 	.word	0x0000bac9
    7280:	0000baa9 	.word	0x0000baa9
    7284:	0000a2e8 	.word	0x0000a2e8
    7288:	0000bb17 	.word	0x0000bb17
    728c:	20000ecc 	.word	0x20000ecc
    7290:	0000a51d 	.word	0x0000a51d
    7294:	0000a576 	.word	0x0000a576
    7298:	0000a58b 	.word	0x0000a58b
    729c:	0000a54a 	.word	0x0000a54a
    72a0:	0000a561 	.word	0x0000a561

000072a4 <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(struct k_thread *curr)
{
    72a4:	b538      	push	{r3, r4, r5, lr}
	int ret = slice_ticks;
    72a6:	4d07      	ldr	r5, [pc, #28]	; (72c4 <z_reset_time_slice+0x20>)
    72a8:	682c      	ldr	r4, [r5, #0]
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time(curr) != 0) {
    72aa:	b154      	cbz	r4, 72c2 <z_reset_time_slice+0x1e>
		_current_cpu->slice_ticks = slice_time(curr) + sys_clock_elapsed();
    72ac:	f7fe f8ee 	bl	548c <sys_clock_elapsed>
    72b0:	4b05      	ldr	r3, [pc, #20]	; (72c8 <z_reset_time_slice+0x24>)
    72b2:	4404      	add	r4, r0
    72b4:	611c      	str	r4, [r3, #16]
		z_set_timeout_expiry(slice_time(curr), false);
    72b6:	6828      	ldr	r0, [r5, #0]
    72b8:	2100      	movs	r1, #0
	}
}
    72ba:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
		z_set_timeout_expiry(slice_time(curr), false);
    72be:	f001 bacd 	b.w	885c <z_set_timeout_expiry>
}
    72c2:	bd38      	pop	{r3, r4, r5, pc}
    72c4:	20000ed8 	.word	0x20000ed8
    72c8:	20000ea0 	.word	0x20000ea0

000072cc <update_cache>:
	}
#endif
}

static void update_cache(int preempt_ok)
{
    72cc:	b538      	push	{r3, r4, r5, lr}
	return list->head == list;
    72ce:	4d14      	ldr	r5, [pc, #80]	; (7320 <update_cache+0x54>)
    72d0:	462b      	mov	r3, r5
    72d2:	f853 4f20 	ldr.w	r4, [r3, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    72d6:	429c      	cmp	r4, r3
    72d8:	d000      	beq.n	72dc <update_cache+0x10>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    72da:	b904      	cbnz	r4, 72de <update_cache+0x12>
    72dc:	68ec      	ldr	r4, [r5, #12]
	__ASSERT(_current != NULL, "");
    72de:	68ab      	ldr	r3, [r5, #8]
	if (preempt_ok != 0) {
    72e0:	b9a8      	cbnz	r0, 730e <update_cache+0x42>
	__ASSERT(_current != NULL, "");
    72e2:	b963      	cbnz	r3, 72fe <update_cache+0x32>
    72e4:	490f      	ldr	r1, [pc, #60]	; (7324 <update_cache+0x58>)
    72e6:	2389      	movs	r3, #137	; 0x89
    72e8:	4a0f      	ldr	r2, [pc, #60]	; (7328 <update_cache+0x5c>)
    72ea:	4810      	ldr	r0, [pc, #64]	; (732c <update_cache+0x60>)
    72ec:	f001 ffdb 	bl	92a6 <assert_print>
    72f0:	480f      	ldr	r0, [pc, #60]	; (7330 <update_cache+0x64>)
    72f2:	f001 ffd8 	bl	92a6 <assert_print>
    72f6:	2189      	movs	r1, #137	; 0x89
    72f8:	480b      	ldr	r0, [pc, #44]	; (7328 <update_cache+0x5c>)
    72fa:	f001 ffcd 	bl	9298 <assert_post_action>
	if (z_is_thread_prevented_from_running(_current)) {
    72fe:	7b5a      	ldrb	r2, [r3, #13]
    7300:	06d2      	lsls	r2, r2, #27
    7302:	d104      	bne.n	730e <update_cache+0x42>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    7304:	69a2      	ldr	r2, [r4, #24]
    7306:	b912      	cbnz	r2, 730e <update_cache+0x42>
	if (is_preempt(_current) || is_metairq(thread)) {
    7308:	89da      	ldrh	r2, [r3, #14]
    730a:	2a7f      	cmp	r2, #127	; 0x7f
    730c:	d805      	bhi.n	731a <update_cache+0x4e>
#ifndef CONFIG_SMP
	struct k_thread *thread = next_up();

	if (should_preempt(thread, preempt_ok)) {
#ifdef CONFIG_TIMESLICING
		if (thread != _current) {
    730e:	429c      	cmp	r4, r3
    7310:	d002      	beq.n	7318 <update_cache+0x4c>
			z_reset_time_slice(thread);
    7312:	4620      	mov	r0, r4
    7314:	f7ff ffc6 	bl	72a4 <z_reset_time_slice>
		}
#endif
		update_metairq_preempt(thread);
		_kernel.ready_q.cache = thread;
    7318:	4623      	mov	r3, r4
    731a:	61eb      	str	r3, [r5, #28]
	 * thread because if the thread gets preempted for whatever
	 * reason the scheduler will make the same decision anyway.
	 */
	_current_cpu->swap_ok = preempt_ok;
#endif
}
    731c:	bd38      	pop	{r3, r4, r5, pc}
    731e:	bf00      	nop
    7320:	20000ea0 	.word	0x20000ea0
    7324:	0000bb3c 	.word	0x0000bb3c
    7328:	0000bb1a 	.word	0x0000bb1a
    732c:	0000a2e8 	.word	0x0000a2e8
    7330:	0000bb17 	.word	0x0000bb17

00007334 <ready_thread>:
	}
#endif
}

static void ready_thread(struct k_thread *thread)
{
    7334:	b570      	push	{r4, r5, r6, lr}
#endif

	/* If thread is queued already, do not try and added it to the
	 * run queue again
	 */
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    7336:	f990 300d 	ldrsb.w	r3, [r0, #13]
	return (thread->base.thread_state & state) != 0U;
    733a:	7b42      	ldrb	r2, [r0, #13]
    733c:	2b00      	cmp	r3, #0
    733e:	db38      	blt.n	73b2 <ready_thread+0x7e>
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    7340:	06d3      	lsls	r3, r2, #27
    7342:	d136      	bne.n	73b2 <ready_thread+0x7e>
	return node->next != NULL;
    7344:	6983      	ldr	r3, [r0, #24]
    7346:	2b00      	cmp	r3, #0
    7348:	d133      	bne.n	73b2 <ready_thread+0x7e>
	thread->base.thread_state |= _THREAD_QUEUED;
    734a:	f062 027f 	orn	r2, r2, #127	; 0x7f
    734e:	7342      	strb	r2, [r0, #13]
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));
    7350:	4a18      	ldr	r2, [pc, #96]	; (73b4 <ready_thread+0x80>)
    7352:	4290      	cmp	r0, r2
    7354:	d109      	bne.n	736a <ready_thread+0x36>
    7356:	4918      	ldr	r1, [pc, #96]	; (73b8 <ready_thread+0x84>)
    7358:	4818      	ldr	r0, [pc, #96]	; (73bc <ready_thread+0x88>)
    735a:	23ba      	movs	r3, #186	; 0xba
    735c:	4a18      	ldr	r2, [pc, #96]	; (73c0 <ready_thread+0x8c>)
    735e:	f001 ffa2 	bl	92a6 <assert_print>
    7362:	21ba      	movs	r1, #186	; 0xba
    7364:	4816      	ldr	r0, [pc, #88]	; (73c0 <ready_thread+0x8c>)
    7366:	f001 ff97 	bl	9298 <assert_post_action>
	return list->head == list;
    736a:	4916      	ldr	r1, [pc, #88]	; (73c4 <ready_thread+0x90>)
    736c:	460a      	mov	r2, r1
    736e:	f852 4f20 	ldr.w	r4, [r2, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    7372:	4294      	cmp	r4, r2
    7374:	bf18      	it	ne
    7376:	4623      	movne	r3, r4
 */

static inline sys_dnode_t *sys_dlist_peek_next_no_check(sys_dlist_t *list,
							sys_dnode_t *node)
{
	return (node == list->tail) ? NULL : node->next;
    7378:	6a4c      	ldr	r4, [r1, #36]	; 0x24
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    737a:	b923      	cbnz	r3, 7386 <ready_thread+0x52>
static inline void sys_dlist_append(sys_dlist_t *list, sys_dnode_t *node)
{
	sys_dnode_t *const tail = list->tail;

	node->next = list;
	node->prev = tail;
    737c:	e9c0 2400 	strd	r2, r4, [r0]

	tail->next = node;
    7380:	6020      	str	r0, [r4, #0]
	list->tail = node;
    7382:	6248      	str	r0, [r1, #36]	; 0x24
}
    7384:	e00c      	b.n	73a0 <ready_thread+0x6c>
	int32_t b1 = thread_1->base.prio;
    7386:	f990 500e 	ldrsb.w	r5, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    738a:	f993 600e 	ldrsb.w	r6, [r3, #14]
	if (b1 != b2) {
    738e:	42b5      	cmp	r5, r6
    7390:	d00b      	beq.n	73aa <ready_thread+0x76>
		if (z_sched_prio_cmp(thread, t) > 0) {
    7392:	42ae      	cmp	r6, r5
    7394:	dd09      	ble.n	73aa <ready_thread+0x76>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    7396:	685a      	ldr	r2, [r3, #4]

	node->prev = prev;
	node->next = successor;
    7398:	e9c0 3200 	strd	r3, r2, [r0]
	prev->next = node;
    739c:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    739e:	6058      	str	r0, [r3, #4]
		SYS_PORT_TRACING_OBJ_FUNC(k_thread, sched_ready, thread);

		queue_thread(thread);
		update_cache(0);
    73a0:	2000      	movs	r0, #0
		flag_ipi();
	}
}
    73a2:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		update_cache(0);
    73a6:	f7ff bf91 	b.w	72cc <update_cache>
	return (node == list->tail) ? NULL : node->next;
    73aa:	42a3      	cmp	r3, r4
    73ac:	d0e6      	beq.n	737c <ready_thread+0x48>
    73ae:	681b      	ldr	r3, [r3, #0]
    73b0:	e7e3      	b.n	737a <ready_thread+0x46>
}
    73b2:	bd70      	pop	{r4, r5, r6, pc}
    73b4:	20000660 	.word	0x20000660
    73b8:	0000bb63 	.word	0x0000bb63
    73bc:	0000a2e8 	.word	0x0000a2e8
    73c0:	0000bb1a 	.word	0x0000bb1a
    73c4:	20000ea0 	.word	0x20000ea0

000073c8 <k_sched_time_slice_set>:
{
    73c8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    73ca:	4604      	mov	r4, r0
    73cc:	460d      	mov	r5, r1
	__asm__ volatile(
    73ce:	f04f 0320 	mov.w	r3, #32
    73d2:	f3ef 8711 	mrs	r7, BASEPRI
    73d6:	f383 8812 	msr	BASEPRI_MAX, r3
    73da:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    73de:	4822      	ldr	r0, [pc, #136]	; (7468 <k_sched_time_slice_set+0xa0>)
    73e0:	f7ff fcf4 	bl	6dcc <z_spin_lock_valid>
    73e4:	b968      	cbnz	r0, 7402 <k_sched_time_slice_set+0x3a>
    73e6:	2394      	movs	r3, #148	; 0x94
    73e8:	4a20      	ldr	r2, [pc, #128]	; (746c <k_sched_time_slice_set+0xa4>)
    73ea:	4921      	ldr	r1, [pc, #132]	; (7470 <k_sched_time_slice_set+0xa8>)
    73ec:	4821      	ldr	r0, [pc, #132]	; (7474 <k_sched_time_slice_set+0xac>)
    73ee:	f001 ff5a 	bl	92a6 <assert_print>
    73f2:	491d      	ldr	r1, [pc, #116]	; (7468 <k_sched_time_slice_set+0xa0>)
    73f4:	4820      	ldr	r0, [pc, #128]	; (7478 <k_sched_time_slice_set+0xb0>)
    73f6:	f001 ff56 	bl	92a6 <assert_print>
    73fa:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    73fc:	481b      	ldr	r0, [pc, #108]	; (746c <k_sched_time_slice_set+0xa4>)
    73fe:	f001 ff4b 	bl	9298 <assert_post_action>
			return (uint32_t)((t * to_hz + off) / from_hz);
    7402:	2600      	movs	r6, #0
	z_spin_lock_set_owner(l);
    7404:	4818      	ldr	r0, [pc, #96]	; (7468 <k_sched_time_slice_set+0xa0>)
    7406:	f7ff fcfd 	bl	6e04 <z_spin_lock_set_owner>
    740a:	f44f 4c00 	mov.w	ip, #32768	; 0x8000
    740e:	f240 30e7 	movw	r0, #999	; 0x3e7
    7412:	4631      	mov	r1, r6
    7414:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    7418:	2300      	movs	r3, #0
    741a:	fbe4 010c 	umlal	r0, r1, r4, ip
    741e:	f7f8 fe99 	bl	154 <__aeabi_uldivmod>
		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && slice > 0) {
    7422:	42b4      	cmp	r4, r6
    7424:	dd02      	ble.n	742c <k_sched_time_slice_set+0x64>
			slice_ticks = MAX(2, slice_ticks);
    7426:	2802      	cmp	r0, #2
    7428:	bfb8      	it	lt
    742a:	2002      	movlt	r0, #2
		slice_ticks = k_ms_to_ticks_ceil32(slice);
    742c:	4a13      	ldr	r2, [pc, #76]	; (747c <k_sched_time_slice_set+0xb4>)
		_current_cpu->slice_ticks = 0;
    742e:	4b14      	ldr	r3, [pc, #80]	; (7480 <k_sched_time_slice_set+0xb8>)
		slice_ticks = k_ms_to_ticks_ceil32(slice);
    7430:	6010      	str	r0, [r2, #0]
		slice_max_prio = prio;
    7432:	4a14      	ldr	r2, [pc, #80]	; (7484 <k_sched_time_slice_set+0xbc>)
		z_reset_time_slice(_current);
    7434:	6898      	ldr	r0, [r3, #8]
		_current_cpu->slice_ticks = 0;
    7436:	611e      	str	r6, [r3, #16]
		slice_max_prio = prio;
    7438:	6015      	str	r5, [r2, #0]
		z_reset_time_slice(_current);
    743a:	f7ff ff33 	bl	72a4 <z_reset_time_slice>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    743e:	480a      	ldr	r0, [pc, #40]	; (7468 <k_sched_time_slice_set+0xa0>)
    7440:	f7ff fcd2 	bl	6de8 <z_spin_unlock_valid>
    7444:	b958      	cbnz	r0, 745e <k_sched_time_slice_set+0x96>
    7446:	23c2      	movs	r3, #194	; 0xc2
    7448:	4a08      	ldr	r2, [pc, #32]	; (746c <k_sched_time_slice_set+0xa4>)
    744a:	490f      	ldr	r1, [pc, #60]	; (7488 <k_sched_time_slice_set+0xc0>)
    744c:	4809      	ldr	r0, [pc, #36]	; (7474 <k_sched_time_slice_set+0xac>)
    744e:	f001 ff2a 	bl	92a6 <assert_print>
    7452:	4905      	ldr	r1, [pc, #20]	; (7468 <k_sched_time_slice_set+0xa0>)
    7454:	480d      	ldr	r0, [pc, #52]	; (748c <k_sched_time_slice_set+0xc4>)
    7456:	f001 ff26 	bl	92a6 <assert_print>
    745a:	21c2      	movs	r1, #194	; 0xc2
    745c:	e7ce      	b.n	73fc <k_sched_time_slice_set+0x34>
	__asm__ volatile(
    745e:	f387 8811 	msr	BASEPRI, r7
    7462:	f3bf 8f6f 	isb	sy
}
    7466:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    7468:	20000edc 	.word	0x20000edc
    746c:	0000a51d 	.word	0x0000a51d
    7470:	0000a576 	.word	0x0000a576
    7474:	0000a2e8 	.word	0x0000a2e8
    7478:	0000a58b 	.word	0x0000a58b
    747c:	20000ed8 	.word	0x20000ed8
    7480:	20000ea0 	.word	0x20000ea0
    7484:	20000ed4 	.word	0x20000ed4
    7488:	0000a54a 	.word	0x0000a54a
    748c:	0000a561 	.word	0x0000a561

00007490 <z_ready_thread>:

void z_ready_thread(struct k_thread *thread)
{
    7490:	b538      	push	{r3, r4, r5, lr}
    7492:	4604      	mov	r4, r0
	__asm__ volatile(
    7494:	f04f 0320 	mov.w	r3, #32
    7498:	f3ef 8511 	mrs	r5, BASEPRI
    749c:	f383 8812 	msr	BASEPRI_MAX, r3
    74a0:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    74a4:	4816      	ldr	r0, [pc, #88]	; (7500 <z_ready_thread+0x70>)
    74a6:	f7ff fc91 	bl	6dcc <z_spin_lock_valid>
    74aa:	b968      	cbnz	r0, 74c8 <z_ready_thread+0x38>
    74ac:	2394      	movs	r3, #148	; 0x94
    74ae:	4a15      	ldr	r2, [pc, #84]	; (7504 <z_ready_thread+0x74>)
    74b0:	4915      	ldr	r1, [pc, #84]	; (7508 <z_ready_thread+0x78>)
    74b2:	4816      	ldr	r0, [pc, #88]	; (750c <z_ready_thread+0x7c>)
    74b4:	f001 fef7 	bl	92a6 <assert_print>
    74b8:	4911      	ldr	r1, [pc, #68]	; (7500 <z_ready_thread+0x70>)
    74ba:	4815      	ldr	r0, [pc, #84]	; (7510 <z_ready_thread+0x80>)
    74bc:	f001 fef3 	bl	92a6 <assert_print>
    74c0:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    74c2:	4810      	ldr	r0, [pc, #64]	; (7504 <z_ready_thread+0x74>)
    74c4:	f001 fee8 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    74c8:	480d      	ldr	r0, [pc, #52]	; (7500 <z_ready_thread+0x70>)
    74ca:	f7ff fc9b 	bl	6e04 <z_spin_lock_set_owner>
	LOCKED(&sched_spinlock) {
		if (!thread_active_elsewhere(thread)) {
			ready_thread(thread);
    74ce:	4620      	mov	r0, r4
    74d0:	f7ff ff30 	bl	7334 <ready_thread>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    74d4:	480a      	ldr	r0, [pc, #40]	; (7500 <z_ready_thread+0x70>)
    74d6:	f7ff fc87 	bl	6de8 <z_spin_unlock_valid>
    74da:	b958      	cbnz	r0, 74f4 <z_ready_thread+0x64>
    74dc:	23c2      	movs	r3, #194	; 0xc2
    74de:	4a09      	ldr	r2, [pc, #36]	; (7504 <z_ready_thread+0x74>)
    74e0:	490c      	ldr	r1, [pc, #48]	; (7514 <z_ready_thread+0x84>)
    74e2:	480a      	ldr	r0, [pc, #40]	; (750c <z_ready_thread+0x7c>)
    74e4:	f001 fedf 	bl	92a6 <assert_print>
    74e8:	4905      	ldr	r1, [pc, #20]	; (7500 <z_ready_thread+0x70>)
    74ea:	480b      	ldr	r0, [pc, #44]	; (7518 <z_ready_thread+0x88>)
    74ec:	f001 fedb 	bl	92a6 <assert_print>
    74f0:	21c2      	movs	r1, #194	; 0xc2
    74f2:	e7e6      	b.n	74c2 <z_ready_thread+0x32>
	__asm__ volatile(
    74f4:	f385 8811 	msr	BASEPRI, r5
    74f8:	f3bf 8f6f 	isb	sy
		}
	}
}
    74fc:	bd38      	pop	{r3, r4, r5, pc}
    74fe:	bf00      	nop
    7500:	20000edc 	.word	0x20000edc
    7504:	0000a51d 	.word	0x0000a51d
    7508:	0000a576 	.word	0x0000a576
    750c:	0000a2e8 	.word	0x0000a2e8
    7510:	0000a58b 	.word	0x0000a58b
    7514:	0000a54a 	.word	0x0000a54a
    7518:	0000a561 	.word	0x0000a561

0000751c <z_unpend_thread_no_timeout>:
	z_mark_thread_as_not_pending(thread);
	thread->base.pended_on = NULL;
}

ALWAYS_INLINE void z_unpend_thread_no_timeout(struct k_thread *thread)
{
    751c:	b538      	push	{r3, r4, r5, lr}
    751e:	4604      	mov	r4, r0
	__asm__ volatile(
    7520:	f04f 0320 	mov.w	r3, #32
    7524:	f3ef 8511 	mrs	r5, BASEPRI
    7528:	f383 8812 	msr	BASEPRI_MAX, r3
    752c:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    7530:	4816      	ldr	r0, [pc, #88]	; (758c <z_unpend_thread_no_timeout+0x70>)
    7532:	f7ff fc4b 	bl	6dcc <z_spin_lock_valid>
    7536:	b968      	cbnz	r0, 7554 <z_unpend_thread_no_timeout+0x38>
    7538:	2394      	movs	r3, #148	; 0x94
    753a:	4a15      	ldr	r2, [pc, #84]	; (7590 <z_unpend_thread_no_timeout+0x74>)
    753c:	4915      	ldr	r1, [pc, #84]	; (7594 <z_unpend_thread_no_timeout+0x78>)
    753e:	4816      	ldr	r0, [pc, #88]	; (7598 <z_unpend_thread_no_timeout+0x7c>)
    7540:	f001 feb1 	bl	92a6 <assert_print>
    7544:	4911      	ldr	r1, [pc, #68]	; (758c <z_unpend_thread_no_timeout+0x70>)
    7546:	4815      	ldr	r0, [pc, #84]	; (759c <z_unpend_thread_no_timeout+0x80>)
    7548:	f001 fead 	bl	92a6 <assert_print>
    754c:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    754e:	4810      	ldr	r0, [pc, #64]	; (7590 <z_unpend_thread_no_timeout+0x74>)
    7550:	f001 fea2 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    7554:	480d      	ldr	r0, [pc, #52]	; (758c <z_unpend_thread_no_timeout+0x70>)
    7556:	f7ff fc55 	bl	6e04 <z_spin_lock_set_owner>
	LOCKED(&sched_spinlock) {
		unpend_thread_no_timeout(thread);
    755a:	4620      	mov	r0, r4
    755c:	f000 fc62 	bl	7e24 <unpend_thread_no_timeout>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7560:	480a      	ldr	r0, [pc, #40]	; (758c <z_unpend_thread_no_timeout+0x70>)
    7562:	f7ff fc41 	bl	6de8 <z_spin_unlock_valid>
    7566:	b958      	cbnz	r0, 7580 <z_unpend_thread_no_timeout+0x64>
    7568:	23c2      	movs	r3, #194	; 0xc2
    756a:	4a09      	ldr	r2, [pc, #36]	; (7590 <z_unpend_thread_no_timeout+0x74>)
    756c:	490c      	ldr	r1, [pc, #48]	; (75a0 <z_unpend_thread_no_timeout+0x84>)
    756e:	480a      	ldr	r0, [pc, #40]	; (7598 <z_unpend_thread_no_timeout+0x7c>)
    7570:	f001 fe99 	bl	92a6 <assert_print>
    7574:	4905      	ldr	r1, [pc, #20]	; (758c <z_unpend_thread_no_timeout+0x70>)
    7576:	480b      	ldr	r0, [pc, #44]	; (75a4 <z_unpend_thread_no_timeout+0x88>)
    7578:	f001 fe95 	bl	92a6 <assert_print>
    757c:	21c2      	movs	r1, #194	; 0xc2
    757e:	e7e6      	b.n	754e <z_unpend_thread_no_timeout+0x32>
	__asm__ volatile(
    7580:	f385 8811 	msr	BASEPRI, r5
    7584:	f3bf 8f6f 	isb	sy
	}
}
    7588:	bd38      	pop	{r3, r4, r5, pc}
    758a:	bf00      	nop
    758c:	20000edc 	.word	0x20000edc
    7590:	0000a51d 	.word	0x0000a51d
    7594:	0000a576 	.word	0x0000a576
    7598:	0000a2e8 	.word	0x0000a2e8
    759c:	0000a58b 	.word	0x0000a58b
    75a0:	0000a54a 	.word	0x0000a54a
    75a4:	0000a561 	.word	0x0000a561

000075a8 <z_reschedule>:
	return new_thread != _current;
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
    75a8:	b570      	push	{r4, r5, r6, lr}
    75aa:	4604      	mov	r4, r0
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    75ac:	460d      	mov	r5, r1
    75ae:	b9e9      	cbnz	r1, 75ec <z_reschedule+0x44>
    75b0:	f3ef 8605 	mrs	r6, IPSR
    75b4:	b9d6      	cbnz	r6, 75ec <z_reschedule+0x44>
	new_thread = _kernel.ready_q.cache;
    75b6:	4b18      	ldr	r3, [pc, #96]	; (7618 <z_reschedule+0x70>)
	if (resched(key.key) && need_swap()) {
    75b8:	69da      	ldr	r2, [r3, #28]
    75ba:	689b      	ldr	r3, [r3, #8]
    75bc:	429a      	cmp	r2, r3
    75be:	d015      	beq.n	75ec <z_reschedule+0x44>
 */
static ALWAYS_INLINE void k_spin_release(struct k_spinlock *l)
{
	ARG_UNUSED(l);
#ifdef CONFIG_SPIN_VALIDATE
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    75c0:	f7ff fc12 	bl	6de8 <z_spin_unlock_valid>
    75c4:	b968      	cbnz	r0, 75e2 <z_reschedule+0x3a>
    75c6:	23e1      	movs	r3, #225	; 0xe1
    75c8:	4a14      	ldr	r2, [pc, #80]	; (761c <z_reschedule+0x74>)
    75ca:	4915      	ldr	r1, [pc, #84]	; (7620 <z_reschedule+0x78>)
    75cc:	4815      	ldr	r0, [pc, #84]	; (7624 <z_reschedule+0x7c>)
    75ce:	f001 fe6a 	bl	92a6 <assert_print>
    75d2:	4621      	mov	r1, r4
    75d4:	4814      	ldr	r0, [pc, #80]	; (7628 <z_reschedule+0x80>)
    75d6:	f001 fe66 	bl	92a6 <assert_print>
    75da:	21e1      	movs	r1, #225	; 0xe1
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    75dc:	480f      	ldr	r0, [pc, #60]	; (761c <z_reschedule+0x74>)
    75de:	f001 fe5b 	bl	9298 <assert_post_action>
	ret = arch_swap(key);
    75e2:	4630      	mov	r0, r6
		z_swap(lock, key);
	} else {
		k_spin_unlock(lock, key);
		signal_pending_ipi();
	}
}
    75e4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    75e8:	f7fc b80c 	b.w	3604 <arch_swap>
    75ec:	4620      	mov	r0, r4
    75ee:	f7ff fbfb 	bl	6de8 <z_spin_unlock_valid>
    75f2:	b958      	cbnz	r0, 760c <z_reschedule+0x64>
    75f4:	23c2      	movs	r3, #194	; 0xc2
    75f6:	4a09      	ldr	r2, [pc, #36]	; (761c <z_reschedule+0x74>)
    75f8:	4909      	ldr	r1, [pc, #36]	; (7620 <z_reschedule+0x78>)
    75fa:	480a      	ldr	r0, [pc, #40]	; (7624 <z_reschedule+0x7c>)
    75fc:	f001 fe53 	bl	92a6 <assert_print>
    7600:	4621      	mov	r1, r4
    7602:	4809      	ldr	r0, [pc, #36]	; (7628 <z_reschedule+0x80>)
    7604:	f001 fe4f 	bl	92a6 <assert_print>
    7608:	21c2      	movs	r1, #194	; 0xc2
    760a:	e7e7      	b.n	75dc <z_reschedule+0x34>
    760c:	f385 8811 	msr	BASEPRI, r5
    7610:	f3bf 8f6f 	isb	sy
    7614:	bd70      	pop	{r4, r5, r6, pc}
    7616:	bf00      	nop
    7618:	20000ea0 	.word	0x20000ea0
    761c:	0000a51d 	.word	0x0000a51d
    7620:	0000a54a 	.word	0x0000a54a
    7624:	0000a2e8 	.word	0x0000a2e8
    7628:	0000a561 	.word	0x0000a561

0000762c <z_sched_start>:
{
    762c:	b538      	push	{r3, r4, r5, lr}
    762e:	4604      	mov	r4, r0
	__asm__ volatile(
    7630:	f04f 0320 	mov.w	r3, #32
    7634:	f3ef 8511 	mrs	r5, BASEPRI
    7638:	f383 8812 	msr	BASEPRI_MAX, r3
    763c:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    7640:	481c      	ldr	r0, [pc, #112]	; (76b4 <z_sched_start+0x88>)
    7642:	f7ff fbc3 	bl	6dcc <z_spin_lock_valid>
    7646:	b968      	cbnz	r0, 7664 <z_sched_start+0x38>
    7648:	2394      	movs	r3, #148	; 0x94
    764a:	4a1b      	ldr	r2, [pc, #108]	; (76b8 <z_sched_start+0x8c>)
    764c:	491b      	ldr	r1, [pc, #108]	; (76bc <z_sched_start+0x90>)
    764e:	481c      	ldr	r0, [pc, #112]	; (76c0 <z_sched_start+0x94>)
    7650:	f001 fe29 	bl	92a6 <assert_print>
    7654:	4917      	ldr	r1, [pc, #92]	; (76b4 <z_sched_start+0x88>)
    7656:	481b      	ldr	r0, [pc, #108]	; (76c4 <z_sched_start+0x98>)
    7658:	f001 fe25 	bl	92a6 <assert_print>
    765c:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    765e:	4816      	ldr	r0, [pc, #88]	; (76b8 <z_sched_start+0x8c>)
    7660:	f001 fe1a 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    7664:	4813      	ldr	r0, [pc, #76]	; (76b4 <z_sched_start+0x88>)
    7666:	f7ff fbcd 	bl	6e04 <z_spin_lock_set_owner>
	return (thread->base.thread_state & _THREAD_PRESTART) == 0U;
    766a:	7b63      	ldrb	r3, [r4, #13]
	if (z_has_thread_started(thread)) {
    766c:	075a      	lsls	r2, r3, #29
    766e:	d414      	bmi.n	769a <z_sched_start+0x6e>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7670:	4810      	ldr	r0, [pc, #64]	; (76b4 <z_sched_start+0x88>)
    7672:	f7ff fbb9 	bl	6de8 <z_spin_unlock_valid>
    7676:	b958      	cbnz	r0, 7690 <z_sched_start+0x64>
    7678:	23c2      	movs	r3, #194	; 0xc2
    767a:	4a0f      	ldr	r2, [pc, #60]	; (76b8 <z_sched_start+0x8c>)
    767c:	4912      	ldr	r1, [pc, #72]	; (76c8 <z_sched_start+0x9c>)
    767e:	4810      	ldr	r0, [pc, #64]	; (76c0 <z_sched_start+0x94>)
    7680:	f001 fe11 	bl	92a6 <assert_print>
    7684:	490b      	ldr	r1, [pc, #44]	; (76b4 <z_sched_start+0x88>)
    7686:	4811      	ldr	r0, [pc, #68]	; (76cc <z_sched_start+0xa0>)
    7688:	f001 fe0d 	bl	92a6 <assert_print>
    768c:	21c2      	movs	r1, #194	; 0xc2
    768e:	e7e6      	b.n	765e <z_sched_start+0x32>
	__asm__ volatile(
    7690:	f385 8811 	msr	BASEPRI, r5
    7694:	f3bf 8f6f 	isb	sy
}
    7698:	bd38      	pop	{r3, r4, r5, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    769a:	f023 0304 	bic.w	r3, r3, #4
	ready_thread(thread);
    769e:	4620      	mov	r0, r4
    76a0:	7363      	strb	r3, [r4, #13]
    76a2:	f7ff fe47 	bl	7334 <ready_thread>
	z_reschedule(&sched_spinlock, key);
    76a6:	4629      	mov	r1, r5
}
    76a8:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&sched_spinlock, key);
    76ac:	4801      	ldr	r0, [pc, #4]	; (76b4 <z_sched_start+0x88>)
    76ae:	f7ff bf7b 	b.w	75a8 <z_reschedule>
    76b2:	bf00      	nop
    76b4:	20000edc 	.word	0x20000edc
    76b8:	0000a51d 	.word	0x0000a51d
    76bc:	0000a576 	.word	0x0000a576
    76c0:	0000a2e8 	.word	0x0000a2e8
    76c4:	0000a58b 	.word	0x0000a58b
    76c8:	0000a54a 	.word	0x0000a54a
    76cc:	0000a561 	.word	0x0000a561

000076d0 <k_sched_lock>:
		signal_pending_ipi();
	}
}

void k_sched_lock(void)
{
    76d0:	b510      	push	{r4, lr}
	__asm__ volatile(
    76d2:	f04f 0320 	mov.w	r3, #32
    76d6:	f3ef 8411 	mrs	r4, BASEPRI
    76da:	f383 8812 	msr	BASEPRI_MAX, r3
    76de:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    76e2:	4825      	ldr	r0, [pc, #148]	; (7778 <k_sched_lock+0xa8>)
    76e4:	f7ff fb72 	bl	6dcc <z_spin_lock_valid>
    76e8:	b960      	cbnz	r0, 7704 <k_sched_lock+0x34>
    76ea:	2394      	movs	r3, #148	; 0x94
    76ec:	4a23      	ldr	r2, [pc, #140]	; (777c <k_sched_lock+0xac>)
    76ee:	4924      	ldr	r1, [pc, #144]	; (7780 <k_sched_lock+0xb0>)
    76f0:	4824      	ldr	r0, [pc, #144]	; (7784 <k_sched_lock+0xb4>)
    76f2:	f001 fdd8 	bl	92a6 <assert_print>
    76f6:	4920      	ldr	r1, [pc, #128]	; (7778 <k_sched_lock+0xa8>)
    76f8:	4823      	ldr	r0, [pc, #140]	; (7788 <k_sched_lock+0xb8>)
    76fa:	f001 fdd4 	bl	92a6 <assert_print>
    76fe:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7700:	481e      	ldr	r0, [pc, #120]	; (777c <k_sched_lock+0xac>)
    7702:	e010      	b.n	7726 <k_sched_lock+0x56>
	z_spin_lock_set_owner(l);
    7704:	481c      	ldr	r0, [pc, #112]	; (7778 <k_sched_lock+0xa8>)
    7706:	f7ff fb7d 	bl	6e04 <z_spin_lock_set_owner>
    770a:	f3ef 8305 	mrs	r3, IPSR
	}
}

static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
    770e:	b163      	cbz	r3, 772a <k_sched_lock+0x5a>
    7710:	491e      	ldr	r1, [pc, #120]	; (778c <k_sched_lock+0xbc>)
    7712:	23fd      	movs	r3, #253	; 0xfd
    7714:	4a1e      	ldr	r2, [pc, #120]	; (7790 <k_sched_lock+0xc0>)
    7716:	481b      	ldr	r0, [pc, #108]	; (7784 <k_sched_lock+0xb4>)
    7718:	f001 fdc5 	bl	92a6 <assert_print>
    771c:	481d      	ldr	r0, [pc, #116]	; (7794 <k_sched_lock+0xc4>)
    771e:	f001 fdc2 	bl	92a6 <assert_print>
    7722:	21fd      	movs	r1, #253	; 0xfd
    7724:	481a      	ldr	r0, [pc, #104]	; (7790 <k_sched_lock+0xc0>)
    7726:	f001 fdb7 	bl	9298 <assert_post_action>
	__ASSERT(_current->base.sched_locked != 1U, "");
    772a:	4b1b      	ldr	r3, [pc, #108]	; (7798 <k_sched_lock+0xc8>)
    772c:	689a      	ldr	r2, [r3, #8]
    772e:	7bd3      	ldrb	r3, [r2, #15]
    7730:	2b01      	cmp	r3, #1
    7732:	d10a      	bne.n	774a <k_sched_lock+0x7a>
    7734:	4919      	ldr	r1, [pc, #100]	; (779c <k_sched_lock+0xcc>)
    7736:	23fe      	movs	r3, #254	; 0xfe
    7738:	4a15      	ldr	r2, [pc, #84]	; (7790 <k_sched_lock+0xc0>)
    773a:	4812      	ldr	r0, [pc, #72]	; (7784 <k_sched_lock+0xb4>)
    773c:	f001 fdb3 	bl	92a6 <assert_print>
    7740:	4814      	ldr	r0, [pc, #80]	; (7794 <k_sched_lock+0xc4>)
    7742:	f001 fdb0 	bl	92a6 <assert_print>
    7746:	21fe      	movs	r1, #254	; 0xfe
    7748:	e7ec      	b.n	7724 <k_sched_lock+0x54>

	--_current->base.sched_locked;
    774a:	3b01      	subs	r3, #1
    774c:	73d3      	strb	r3, [r2, #15]
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    774e:	480a      	ldr	r0, [pc, #40]	; (7778 <k_sched_lock+0xa8>)
    7750:	f7ff fb4a 	bl	6de8 <z_spin_unlock_valid>
    7754:	b958      	cbnz	r0, 776e <k_sched_lock+0x9e>
    7756:	23c2      	movs	r3, #194	; 0xc2
    7758:	4a08      	ldr	r2, [pc, #32]	; (777c <k_sched_lock+0xac>)
    775a:	4911      	ldr	r1, [pc, #68]	; (77a0 <k_sched_lock+0xd0>)
    775c:	4809      	ldr	r0, [pc, #36]	; (7784 <k_sched_lock+0xb4>)
    775e:	f001 fda2 	bl	92a6 <assert_print>
    7762:	4905      	ldr	r1, [pc, #20]	; (7778 <k_sched_lock+0xa8>)
    7764:	480f      	ldr	r0, [pc, #60]	; (77a4 <k_sched_lock+0xd4>)
    7766:	f001 fd9e 	bl	92a6 <assert_print>
    776a:	21c2      	movs	r1, #194	; 0xc2
    776c:	e7c8      	b.n	7700 <k_sched_lock+0x30>
	__asm__ volatile(
    776e:	f384 8811 	msr	BASEPRI, r4
    7772:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		SYS_PORT_TRACING_FUNC(k_thread, sched_lock);

		z_sched_lock();
	}
}
    7776:	bd10      	pop	{r4, pc}
    7778:	20000edc 	.word	0x20000edc
    777c:	0000a51d 	.word	0x0000a51d
    7780:	0000a576 	.word	0x0000a576
    7784:	0000a2e8 	.word	0x0000a2e8
    7788:	0000a58b 	.word	0x0000a58b
    778c:	0000ba5b 	.word	0x0000ba5b
    7790:	0000bb84 	.word	0x0000bb84
    7794:	0000bb17 	.word	0x0000bb17
    7798:	20000ea0 	.word	0x20000ea0
    779c:	0000bbaf 	.word	0x0000bbaf
    77a0:	0000a54a 	.word	0x0000a54a
    77a4:	0000a561 	.word	0x0000a561

000077a8 <k_sched_unlock>:

void k_sched_unlock(void)
{
    77a8:	b510      	push	{r4, lr}
	__asm__ volatile(
    77aa:	f04f 0320 	mov.w	r3, #32
    77ae:	f3ef 8411 	mrs	r4, BASEPRI
    77b2:	f383 8812 	msr	BASEPRI_MAX, r3
    77b6:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    77ba:	4829      	ldr	r0, [pc, #164]	; (7860 <k_sched_unlock+0xb8>)
    77bc:	f7ff fb06 	bl	6dcc <z_spin_lock_valid>
    77c0:	b960      	cbnz	r0, 77dc <k_sched_unlock+0x34>
    77c2:	2394      	movs	r3, #148	; 0x94
    77c4:	4a27      	ldr	r2, [pc, #156]	; (7864 <k_sched_unlock+0xbc>)
    77c6:	4928      	ldr	r1, [pc, #160]	; (7868 <k_sched_unlock+0xc0>)
    77c8:	4828      	ldr	r0, [pc, #160]	; (786c <k_sched_unlock+0xc4>)
    77ca:	f001 fd6c 	bl	92a6 <assert_print>
    77ce:	4924      	ldr	r1, [pc, #144]	; (7860 <k_sched_unlock+0xb8>)
    77d0:	4827      	ldr	r0, [pc, #156]	; (7870 <k_sched_unlock+0xc8>)
    77d2:	f001 fd68 	bl	92a6 <assert_print>
    77d6:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    77d8:	4822      	ldr	r0, [pc, #136]	; (7864 <k_sched_unlock+0xbc>)
    77da:	e013      	b.n	7804 <k_sched_unlock+0x5c>
	z_spin_lock_set_owner(l);
    77dc:	4820      	ldr	r0, [pc, #128]	; (7860 <k_sched_unlock+0xb8>)
    77de:	f7ff fb11 	bl	6e04 <z_spin_lock_set_owner>
	LOCKED(&sched_spinlock) {
		__ASSERT(_current->base.sched_locked != 0U, "");
    77e2:	4b24      	ldr	r3, [pc, #144]	; (7874 <k_sched_unlock+0xcc>)
    77e4:	689a      	ldr	r2, [r3, #8]
    77e6:	7bd3      	ldrb	r3, [r2, #15]
    77e8:	b973      	cbnz	r3, 7808 <k_sched_unlock+0x60>
    77ea:	4923      	ldr	r1, [pc, #140]	; (7878 <k_sched_unlock+0xd0>)
    77ec:	f240 33e7 	movw	r3, #999	; 0x3e7
    77f0:	4a22      	ldr	r2, [pc, #136]	; (787c <k_sched_unlock+0xd4>)
    77f2:	481e      	ldr	r0, [pc, #120]	; (786c <k_sched_unlock+0xc4>)
    77f4:	f001 fd57 	bl	92a6 <assert_print>
    77f8:	4821      	ldr	r0, [pc, #132]	; (7880 <k_sched_unlock+0xd8>)
    77fa:	f001 fd54 	bl	92a6 <assert_print>
    77fe:	f240 31e7 	movw	r1, #999	; 0x3e7
    7802:	481e      	ldr	r0, [pc, #120]	; (787c <k_sched_unlock+0xd4>)
    7804:	f001 fd48 	bl	9298 <assert_post_action>
    7808:	f3ef 8005 	mrs	r0, IPSR
		__ASSERT(!arch_is_in_isr(), "");
    780c:	b160      	cbz	r0, 7828 <k_sched_unlock+0x80>
    780e:	491d      	ldr	r1, [pc, #116]	; (7884 <k_sched_unlock+0xdc>)
    7810:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    7814:	4a19      	ldr	r2, [pc, #100]	; (787c <k_sched_unlock+0xd4>)
    7816:	4815      	ldr	r0, [pc, #84]	; (786c <k_sched_unlock+0xc4>)
    7818:	f001 fd45 	bl	92a6 <assert_print>
    781c:	4818      	ldr	r0, [pc, #96]	; (7880 <k_sched_unlock+0xd8>)
    781e:	f001 fd42 	bl	92a6 <assert_print>
    7822:	f44f 717a 	mov.w	r1, #1000	; 0x3e8
    7826:	e7ec      	b.n	7802 <k_sched_unlock+0x5a>

		++_current->base.sched_locked;
    7828:	3301      	adds	r3, #1
    782a:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    782c:	f7ff fd4e 	bl	72cc <update_cache>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7830:	480b      	ldr	r0, [pc, #44]	; (7860 <k_sched_unlock+0xb8>)
    7832:	f7ff fad9 	bl	6de8 <z_spin_unlock_valid>
    7836:	b958      	cbnz	r0, 7850 <k_sched_unlock+0xa8>
    7838:	23c2      	movs	r3, #194	; 0xc2
    783a:	4a0a      	ldr	r2, [pc, #40]	; (7864 <k_sched_unlock+0xbc>)
    783c:	4912      	ldr	r1, [pc, #72]	; (7888 <k_sched_unlock+0xe0>)
    783e:	480b      	ldr	r0, [pc, #44]	; (786c <k_sched_unlock+0xc4>)
    7840:	f001 fd31 	bl	92a6 <assert_print>
    7844:	4906      	ldr	r1, [pc, #24]	; (7860 <k_sched_unlock+0xb8>)
    7846:	4811      	ldr	r0, [pc, #68]	; (788c <k_sched_unlock+0xe4>)
    7848:	f001 fd2d 	bl	92a6 <assert_print>
    784c:	21c2      	movs	r1, #194	; 0xc2
    784e:	e7c3      	b.n	77d8 <k_sched_unlock+0x30>
	__asm__ volatile(
    7850:	f384 8811 	msr	BASEPRI, r4
    7854:	f3bf 8f6f 	isb	sy
		_current, _current->base.sched_locked);

	SYS_PORT_TRACING_FUNC(k_thread, sched_unlock);

	z_reschedule_unlocked();
}
    7858:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    785c:	f002 b9c6 	b.w	9bec <z_reschedule_unlocked>
    7860:	20000edc 	.word	0x20000edc
    7864:	0000a51d 	.word	0x0000a51d
    7868:	0000a576 	.word	0x0000a576
    786c:	0000a2e8 	.word	0x0000a2e8
    7870:	0000a58b 	.word	0x0000a58b
    7874:	20000ea0 	.word	0x20000ea0
    7878:	0000bbe0 	.word	0x0000bbe0
    787c:	0000bb1a 	.word	0x0000bb1a
    7880:	0000bb17 	.word	0x0000bb17
    7884:	0000ba5b 	.word	0x0000ba5b
    7888:	0000a54a 	.word	0x0000a54a
    788c:	0000a561 	.word	0x0000a561

00007890 <z_priq_dumb_remove>:
#endif
}
#endif

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
    7890:	b508      	push	{r3, lr}
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));
    7892:	4b0b      	ldr	r3, [pc, #44]	; (78c0 <z_priq_dumb_remove+0x30>)
    7894:	4299      	cmp	r1, r3
    7896:	d10b      	bne.n	78b0 <z_priq_dumb_remove+0x20>
    7898:	490a      	ldr	r1, [pc, #40]	; (78c4 <z_priq_dumb_remove+0x34>)
    789a:	480b      	ldr	r0, [pc, #44]	; (78c8 <z_priq_dumb_remove+0x38>)
    789c:	f240 4373 	movw	r3, #1139	; 0x473
    78a0:	4a0a      	ldr	r2, [pc, #40]	; (78cc <z_priq_dumb_remove+0x3c>)
    78a2:	f001 fd00 	bl	92a6 <assert_print>
    78a6:	f240 4173 	movw	r1, #1139	; 0x473
    78aa:	4808      	ldr	r0, [pc, #32]	; (78cc <z_priq_dumb_remove+0x3c>)
    78ac:	f001 fcf4 	bl	9298 <assert_post_action>
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
	sys_dnode_t *const next = node->next;
    78b0:	e9d1 3200 	ldrd	r3, r2, [r1]

	prev->next = next;
    78b4:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    78b6:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    78b8:	2300      	movs	r3, #0
	node->prev = NULL;
    78ba:	e9c1 3300 	strd	r3, r3, [r1]

	sys_dlist_remove(&thread->base.qnode_dlist);
}
    78be:	bd08      	pop	{r3, pc}
    78c0:	20000660 	.word	0x20000660
    78c4:	0000bb63 	.word	0x0000bb63
    78c8:	0000a2e8 	.word	0x0000a2e8
    78cc:	0000bb1a 	.word	0x0000bb1a

000078d0 <move_thread_to_end_of_prio_q>:
{
    78d0:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    78d2:	f990 200d 	ldrsb.w	r2, [r0, #13]
{
    78d6:	4604      	mov	r4, r0
	if (z_is_thread_queued(thread)) {
    78d8:	2a00      	cmp	r2, #0
	return (thread->base.thread_state & state) != 0U;
    78da:	7b43      	ldrb	r3, [r0, #13]
    78dc:	da06      	bge.n	78ec <move_thread_to_end_of_prio_q+0x1c>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    78de:	f003 037f 	and.w	r3, r3, #127	; 0x7f
	_priq_run_remove(thread_runq(thread), thread);
    78e2:	4601      	mov	r1, r0
	thread->base.thread_state &= ~_THREAD_QUEUED;
    78e4:	7343      	strb	r3, [r0, #13]
	_priq_run_remove(thread_runq(thread), thread);
    78e6:	481d      	ldr	r0, [pc, #116]	; (795c <move_thread_to_end_of_prio_q+0x8c>)
    78e8:	f7ff ffd2 	bl	7890 <z_priq_dumb_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    78ec:	7b63      	ldrb	r3, [r4, #13]
    78ee:	f063 037f 	orn	r3, r3, #127	; 0x7f
    78f2:	7363      	strb	r3, [r4, #13]
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));
    78f4:	4b1a      	ldr	r3, [pc, #104]	; (7960 <move_thread_to_end_of_prio_q+0x90>)
    78f6:	429c      	cmp	r4, r3
    78f8:	d109      	bne.n	790e <move_thread_to_end_of_prio_q+0x3e>
    78fa:	491a      	ldr	r1, [pc, #104]	; (7964 <move_thread_to_end_of_prio_q+0x94>)
    78fc:	481a      	ldr	r0, [pc, #104]	; (7968 <move_thread_to_end_of_prio_q+0x98>)
    78fe:	23ba      	movs	r3, #186	; 0xba
    7900:	4a1a      	ldr	r2, [pc, #104]	; (796c <move_thread_to_end_of_prio_q+0x9c>)
    7902:	f001 fcd0 	bl	92a6 <assert_print>
    7906:	21ba      	movs	r1, #186	; 0xba
    7908:	4818      	ldr	r0, [pc, #96]	; (796c <move_thread_to_end_of_prio_q+0x9c>)
    790a:	f001 fcc5 	bl	9298 <assert_post_action>
	return list->head == list;
    790e:	4a18      	ldr	r2, [pc, #96]	; (7970 <move_thread_to_end_of_prio_q+0xa0>)
    7910:	4611      	mov	r1, r2
    7912:	f851 3f20 	ldr.w	r3, [r1, #32]!
	return (node == list->tail) ? NULL : node->next;
    7916:	6a50      	ldr	r0, [r2, #36]	; 0x24
	return sys_dlist_is_empty(list) ? NULL : list->head;
    7918:	428b      	cmp	r3, r1
    791a:	bf08      	it	eq
    791c:	2300      	moveq	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    791e:	b923      	cbnz	r3, 792a <move_thread_to_end_of_prio_q+0x5a>
	node->prev = tail;
    7920:	e9c4 1000 	strd	r1, r0, [r4]
	tail->next = node;
    7924:	6004      	str	r4, [r0, #0]
	list->tail = node;
    7926:	6254      	str	r4, [r2, #36]	; 0x24
}
    7928:	e00c      	b.n	7944 <move_thread_to_end_of_prio_q+0x74>
	int32_t b1 = thread_1->base.prio;
    792a:	f994 500e 	ldrsb.w	r5, [r4, #14]
	int32_t b2 = thread_2->base.prio;
    792e:	f993 600e 	ldrsb.w	r6, [r3, #14]
	if (b1 != b2) {
    7932:	42b5      	cmp	r5, r6
    7934:	d00e      	beq.n	7954 <move_thread_to_end_of_prio_q+0x84>
		if (z_sched_prio_cmp(thread, t) > 0) {
    7936:	42ae      	cmp	r6, r5
    7938:	dd0c      	ble.n	7954 <move_thread_to_end_of_prio_q+0x84>
	sys_dnode_t *const prev = successor->prev;
    793a:	6859      	ldr	r1, [r3, #4]
	node->next = successor;
    793c:	e9c4 3100 	strd	r3, r1, [r4]
	prev->next = node;
    7940:	600c      	str	r4, [r1, #0]
	successor->prev = node;
    7942:	605c      	str	r4, [r3, #4]
	update_cache(thread == _current);
    7944:	6890      	ldr	r0, [r2, #8]
    7946:	1b03      	subs	r3, r0, r4
    7948:	4258      	negs	r0, r3
    794a:	4158      	adcs	r0, r3
}
    794c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    7950:	f7ff bcbc 	b.w	72cc <update_cache>
	return (node == list->tail) ? NULL : node->next;
    7954:	4298      	cmp	r0, r3
    7956:	d0e3      	beq.n	7920 <move_thread_to_end_of_prio_q+0x50>
    7958:	681b      	ldr	r3, [r3, #0]
    795a:	e7e0      	b.n	791e <move_thread_to_end_of_prio_q+0x4e>
    795c:	20000ec0 	.word	0x20000ec0
    7960:	20000660 	.word	0x20000660
    7964:	0000bb63 	.word	0x0000bb63
    7968:	0000a2e8 	.word	0x0000a2e8
    796c:	0000bb1a 	.word	0x0000bb1a
    7970:	20000ea0 	.word	0x20000ea0

00007974 <z_time_slice>:
{
    7974:	b570      	push	{r4, r5, r6, lr}
    7976:	4605      	mov	r5, r0
	__asm__ volatile(
    7978:	f04f 0320 	mov.w	r3, #32
    797c:	f3ef 8611 	mrs	r6, BASEPRI
    7980:	f383 8812 	msr	BASEPRI_MAX, r3
    7984:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    7988:	4829      	ldr	r0, [pc, #164]	; (7a30 <z_time_slice+0xbc>)
    798a:	f7ff fa1f 	bl	6dcc <z_spin_lock_valid>
    798e:	b968      	cbnz	r0, 79ac <z_time_slice+0x38>
    7990:	2394      	movs	r3, #148	; 0x94
    7992:	4a28      	ldr	r2, [pc, #160]	; (7a34 <z_time_slice+0xc0>)
    7994:	4928      	ldr	r1, [pc, #160]	; (7a38 <z_time_slice+0xc4>)
    7996:	4829      	ldr	r0, [pc, #164]	; (7a3c <z_time_slice+0xc8>)
    7998:	f001 fc85 	bl	92a6 <assert_print>
    799c:	4924      	ldr	r1, [pc, #144]	; (7a30 <z_time_slice+0xbc>)
    799e:	4828      	ldr	r0, [pc, #160]	; (7a40 <z_time_slice+0xcc>)
    79a0:	f001 fc81 	bl	92a6 <assert_print>
    79a4:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    79a6:	4823      	ldr	r0, [pc, #140]	; (7a34 <z_time_slice+0xc0>)
    79a8:	f001 fc76 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    79ac:	4820      	ldr	r0, [pc, #128]	; (7a30 <z_time_slice+0xbc>)
    79ae:	f7ff fa29 	bl	6e04 <z_spin_lock_set_owner>
	if (pending_current == _current) {
    79b2:	4b24      	ldr	r3, [pc, #144]	; (7a44 <z_time_slice+0xd0>)
    79b4:	4a24      	ldr	r2, [pc, #144]	; (7a48 <z_time_slice+0xd4>)
    79b6:	689c      	ldr	r4, [r3, #8]
    79b8:	6811      	ldr	r1, [r2, #0]
    79ba:	428c      	cmp	r4, r1
    79bc:	d112      	bne.n	79e4 <z_time_slice+0x70>
		z_reset_time_slice(_current);
    79be:	4620      	mov	r0, r4
    79c0:	f7ff fc70 	bl	72a4 <z_reset_time_slice>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    79c4:	481a      	ldr	r0, [pc, #104]	; (7a30 <z_time_slice+0xbc>)
    79c6:	f7ff fa0f 	bl	6de8 <z_spin_unlock_valid>
    79ca:	bb58      	cbnz	r0, 7a24 <z_time_slice+0xb0>
    79cc:	23c2      	movs	r3, #194	; 0xc2
    79ce:	4a19      	ldr	r2, [pc, #100]	; (7a34 <z_time_slice+0xc0>)
    79d0:	491e      	ldr	r1, [pc, #120]	; (7a4c <z_time_slice+0xd8>)
    79d2:	481a      	ldr	r0, [pc, #104]	; (7a3c <z_time_slice+0xc8>)
    79d4:	f001 fc67 	bl	92a6 <assert_print>
    79d8:	4915      	ldr	r1, [pc, #84]	; (7a30 <z_time_slice+0xbc>)
    79da:	481d      	ldr	r0, [pc, #116]	; (7a50 <z_time_slice+0xdc>)
    79dc:	f001 fc63 	bl	92a6 <assert_print>
    79e0:	21c2      	movs	r1, #194	; 0xc2
    79e2:	e7e0      	b.n	79a6 <z_time_slice+0x32>
	pending_current = NULL;
    79e4:	2100      	movs	r1, #0
    79e6:	6011      	str	r1, [r2, #0]
	int ret = slice_ticks;
    79e8:	4a1a      	ldr	r2, [pc, #104]	; (7a54 <z_time_slice+0xe0>)
	if (slice_time(_current) && sliceable(_current)) {
    79ea:	6812      	ldr	r2, [r2, #0]
    79ec:	b1c2      	cbz	r2, 7a20 <z_time_slice+0xac>
		&& !z_is_idle_thread_object(thread);
    79ee:	89e2      	ldrh	r2, [r4, #14]
    79f0:	2a7f      	cmp	r2, #127	; 0x7f
    79f2:	d815      	bhi.n	7a20 <z_time_slice+0xac>
		&& !z_is_thread_prevented_from_running(thread)
    79f4:	7b62      	ldrb	r2, [r4, #13]
    79f6:	06d2      	lsls	r2, r2, #27
    79f8:	d112      	bne.n	7a20 <z_time_slice+0xac>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    79fa:	4a17      	ldr	r2, [pc, #92]	; (7a58 <z_time_slice+0xe4>)
    79fc:	f994 100e 	ldrsb.w	r1, [r4, #14]
    7a00:	6812      	ldr	r2, [r2, #0]
    7a02:	4291      	cmp	r1, r2
    7a04:	db0c      	blt.n	7a20 <z_time_slice+0xac>
		&& !z_is_idle_thread_object(thread);
    7a06:	4a15      	ldr	r2, [pc, #84]	; (7a5c <z_time_slice+0xe8>)
    7a08:	4294      	cmp	r4, r2
    7a0a:	d009      	beq.n	7a20 <z_time_slice+0xac>
		if (ticks >= _current_cpu->slice_ticks) {
    7a0c:	691a      	ldr	r2, [r3, #16]
    7a0e:	42aa      	cmp	r2, r5
    7a10:	dc03      	bgt.n	7a1a <z_time_slice+0xa6>
		move_thread_to_end_of_prio_q(curr);
    7a12:	4620      	mov	r0, r4
    7a14:	f7ff ff5c 	bl	78d0 <move_thread_to_end_of_prio_q>
	z_reset_time_slice(curr);
    7a18:	e7d1      	b.n	79be <z_time_slice+0x4a>
			_current_cpu->slice_ticks -= ticks;
    7a1a:	1b52      	subs	r2, r2, r5
		_current_cpu->slice_ticks = 0;
    7a1c:	611a      	str	r2, [r3, #16]
    7a1e:	e7d1      	b.n	79c4 <z_time_slice+0x50>
    7a20:	2200      	movs	r2, #0
    7a22:	e7fb      	b.n	7a1c <z_time_slice+0xa8>
	__asm__ volatile(
    7a24:	f386 8811 	msr	BASEPRI, r6
    7a28:	f3bf 8f6f 	isb	sy
}
    7a2c:	bd70      	pop	{r4, r5, r6, pc}
    7a2e:	bf00      	nop
    7a30:	20000edc 	.word	0x20000edc
    7a34:	0000a51d 	.word	0x0000a51d
    7a38:	0000a576 	.word	0x0000a576
    7a3c:	0000a2e8 	.word	0x0000a2e8
    7a40:	0000a58b 	.word	0x0000a58b
    7a44:	20000ea0 	.word	0x20000ea0
    7a48:	20000ed0 	.word	0x20000ed0
    7a4c:	0000a54a 	.word	0x0000a54a
    7a50:	0000a561 	.word	0x0000a561
    7a54:	20000ed8 	.word	0x20000ed8
    7a58:	20000ed4 	.word	0x20000ed4
    7a5c:	20000660 	.word	0x20000660

00007a60 <unready_thread>:
{
    7a60:	b510      	push	{r4, lr}
	if (z_is_thread_queued(thread)) {
    7a62:	f990 200d 	ldrsb.w	r2, [r0, #13]
{
    7a66:	4604      	mov	r4, r0
	if (z_is_thread_queued(thread)) {
    7a68:	2a00      	cmp	r2, #0
    7a6a:	7b43      	ldrb	r3, [r0, #13]
    7a6c:	da06      	bge.n	7a7c <unready_thread+0x1c>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    7a6e:	f003 037f 	and.w	r3, r3, #127	; 0x7f
	_priq_run_remove(thread_runq(thread), thread);
    7a72:	4601      	mov	r1, r0
	thread->base.thread_state &= ~_THREAD_QUEUED;
    7a74:	7343      	strb	r3, [r0, #13]
	_priq_run_remove(thread_runq(thread), thread);
    7a76:	4806      	ldr	r0, [pc, #24]	; (7a90 <unready_thread+0x30>)
    7a78:	f7ff ff0a 	bl	7890 <z_priq_dumb_remove>
	update_cache(thread == _current);
    7a7c:	4b05      	ldr	r3, [pc, #20]	; (7a94 <unready_thread+0x34>)
    7a7e:	6898      	ldr	r0, [r3, #8]
    7a80:	1b03      	subs	r3, r0, r4
    7a82:	4258      	negs	r0, r3
    7a84:	4158      	adcs	r0, r3
}
    7a86:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	update_cache(thread == _current);
    7a8a:	f7ff bc1f 	b.w	72cc <update_cache>
    7a8e:	bf00      	nop
    7a90:	20000ec0 	.word	0x20000ec0
    7a94:	20000ea0 	.word	0x20000ea0

00007a98 <add_to_waitq_locked>:
{
    7a98:	b538      	push	{r3, r4, r5, lr}
    7a9a:	4604      	mov	r4, r0
    7a9c:	460d      	mov	r5, r1
	unready_thread(thread);
    7a9e:	f7ff ffdf 	bl	7a60 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    7aa2:	7b63      	ldrb	r3, [r4, #13]
    7aa4:	f043 0302 	orr.w	r3, r3, #2
    7aa8:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    7aaa:	b34d      	cbz	r5, 7b00 <add_to_waitq_locked+0x68>
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));
    7aac:	4b15      	ldr	r3, [pc, #84]	; (7b04 <add_to_waitq_locked+0x6c>)
		thread->base.pended_on = wait_q;
    7aae:	60a5      	str	r5, [r4, #8]
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));
    7ab0:	429c      	cmp	r4, r3
    7ab2:	d109      	bne.n	7ac8 <add_to_waitq_locked+0x30>
    7ab4:	4914      	ldr	r1, [pc, #80]	; (7b08 <add_to_waitq_locked+0x70>)
    7ab6:	4815      	ldr	r0, [pc, #84]	; (7b0c <add_to_waitq_locked+0x74>)
    7ab8:	23ba      	movs	r3, #186	; 0xba
    7aba:	4a15      	ldr	r2, [pc, #84]	; (7b10 <add_to_waitq_locked+0x78>)
    7abc:	f001 fbf3 	bl	92a6 <assert_print>
    7ac0:	21ba      	movs	r1, #186	; 0xba
    7ac2:	4813      	ldr	r0, [pc, #76]	; (7b10 <add_to_waitq_locked+0x78>)
    7ac4:	f001 fbe8 	bl	9298 <assert_post_action>
	return list->head == list;
    7ac8:	682b      	ldr	r3, [r5, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    7aca:	429d      	cmp	r5, r3
    7acc:	d109      	bne.n	7ae2 <add_to_waitq_locked+0x4a>
	sys_dnode_t *const tail = list->tail;
    7ace:	686b      	ldr	r3, [r5, #4]
	node->prev = tail;
    7ad0:	e9c4 5300 	strd	r5, r3, [r4]
	tail->next = node;
    7ad4:	601c      	str	r4, [r3, #0]
	list->tail = node;
    7ad6:	606c      	str	r4, [r5, #4]
}
    7ad8:	e012      	b.n	7b00 <add_to_waitq_locked+0x68>
	return (node == list->tail) ? NULL : node->next;
    7ada:	686a      	ldr	r2, [r5, #4]
    7adc:	4293      	cmp	r3, r2
    7ade:	d0f6      	beq.n	7ace <add_to_waitq_locked+0x36>
    7ae0:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    7ae2:	2b00      	cmp	r3, #0
    7ae4:	d0f3      	beq.n	7ace <add_to_waitq_locked+0x36>
	int32_t b1 = thread_1->base.prio;
    7ae6:	f994 200e 	ldrsb.w	r2, [r4, #14]
	int32_t b2 = thread_2->base.prio;
    7aea:	f993 100e 	ldrsb.w	r1, [r3, #14]
	if (b1 != b2) {
    7aee:	428a      	cmp	r2, r1
    7af0:	d0f3      	beq.n	7ada <add_to_waitq_locked+0x42>
		if (z_sched_prio_cmp(thread, t) > 0) {
    7af2:	4291      	cmp	r1, r2
    7af4:	ddf1      	ble.n	7ada <add_to_waitq_locked+0x42>
	sys_dnode_t *const prev = successor->prev;
    7af6:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    7af8:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    7afc:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    7afe:	605c      	str	r4, [r3, #4]
}
    7b00:	bd38      	pop	{r3, r4, r5, pc}
    7b02:	bf00      	nop
    7b04:	20000660 	.word	0x20000660
    7b08:	0000bb63 	.word	0x0000bb63
    7b0c:	0000a2e8 	.word	0x0000a2e8
    7b10:	0000bb1a 	.word	0x0000bb1a

00007b14 <pend_locked>:
{
    7b14:	b570      	push	{r4, r5, r6, lr}
    7b16:	4615      	mov	r5, r2
    7b18:	461c      	mov	r4, r3
    7b1a:	4606      	mov	r6, r0
	add_to_waitq_locked(thread, wait_q);
    7b1c:	f7ff ffbc 	bl	7a98 <add_to_waitq_locked>
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    7b20:	f1b4 3fff 	cmp.w	r4, #4294967295
    7b24:	bf08      	it	eq
    7b26:	f1b5 3fff 	cmpeq.w	r5, #4294967295
    7b2a:	d008      	beq.n	7b3e <pend_locked+0x2a>
    7b2c:	462a      	mov	r2, r5
    7b2e:	4623      	mov	r3, r4
    7b30:	f106 0018 	add.w	r0, r6, #24
    7b34:	4902      	ldr	r1, [pc, #8]	; (7b40 <pend_locked+0x2c>)
}
    7b36:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    7b3a:	f000 bd37 	b.w	85ac <z_add_timeout>
    7b3e:	bd70      	pop	{r4, r5, r6, pc}
    7b40:	00007e65 	.word	0x00007e65

00007b44 <z_pend_curr>:
{
    7b44:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    7b48:	e9dd 8908 	ldrd	r8, r9, [sp, #32]
	pending_current = _current;
    7b4c:	f8df a0b4 	ldr.w	sl, [pc, #180]	; 7c04 <z_pend_curr+0xc0>
	__ASSERT_NO_MSG(sizeof(sched_spinlock) == 0 || lock != &sched_spinlock);
    7b50:	4c2d      	ldr	r4, [pc, #180]	; (7c08 <z_pend_curr+0xc4>)
{
    7b52:	4617      	mov	r7, r2
	pending_current = _current;
    7b54:	4b2d      	ldr	r3, [pc, #180]	; (7c0c <z_pend_curr+0xc8>)
    7b56:	f8da 2008 	ldr.w	r2, [sl, #8]
	__ASSERT_NO_MSG(sizeof(sched_spinlock) == 0 || lock != &sched_spinlock);
    7b5a:	42a0      	cmp	r0, r4
{
    7b5c:	4605      	mov	r5, r0
    7b5e:	460e      	mov	r6, r1
	pending_current = _current;
    7b60:	601a      	str	r2, [r3, #0]
	__ASSERT_NO_MSG(sizeof(sched_spinlock) == 0 || lock != &sched_spinlock);
    7b62:	d10b      	bne.n	7b7c <z_pend_curr+0x38>
    7b64:	492a      	ldr	r1, [pc, #168]	; (7c10 <z_pend_curr+0xcc>)
    7b66:	482b      	ldr	r0, [pc, #172]	; (7c14 <z_pend_curr+0xd0>)
    7b68:	f240 334e 	movw	r3, #846	; 0x34e
    7b6c:	4a2a      	ldr	r2, [pc, #168]	; (7c18 <z_pend_curr+0xd4>)
    7b6e:	f001 fb9a 	bl	92a6 <assert_print>
    7b72:	f240 314e 	movw	r1, #846	; 0x34e
    7b76:	4828      	ldr	r0, [pc, #160]	; (7c18 <z_pend_curr+0xd4>)
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    7b78:	f001 fb8e 	bl	9298 <assert_post_action>
	__asm__ volatile(
    7b7c:	f04f 0220 	mov.w	r2, #32
    7b80:	f3ef 8311 	mrs	r3, BASEPRI
    7b84:	f382 8812 	msr	BASEPRI_MAX, r2
    7b88:	f3bf 8f6f 	isb	sy
    7b8c:	4620      	mov	r0, r4
    7b8e:	f7ff f91d 	bl	6dcc <z_spin_lock_valid>
    7b92:	b960      	cbnz	r0, 7bae <z_pend_curr+0x6a>
    7b94:	2394      	movs	r3, #148	; 0x94
    7b96:	4a21      	ldr	r2, [pc, #132]	; (7c1c <z_pend_curr+0xd8>)
    7b98:	4921      	ldr	r1, [pc, #132]	; (7c20 <z_pend_curr+0xdc>)
    7b9a:	481e      	ldr	r0, [pc, #120]	; (7c14 <z_pend_curr+0xd0>)
    7b9c:	f001 fb83 	bl	92a6 <assert_print>
    7ba0:	4621      	mov	r1, r4
    7ba2:	4820      	ldr	r0, [pc, #128]	; (7c24 <z_pend_curr+0xe0>)
    7ba4:	f001 fb7f 	bl	92a6 <assert_print>
    7ba8:	2194      	movs	r1, #148	; 0x94
    7baa:	481c      	ldr	r0, [pc, #112]	; (7c1c <z_pend_curr+0xd8>)
    7bac:	e7e4      	b.n	7b78 <z_pend_curr+0x34>
	z_spin_lock_set_owner(l);
    7bae:	4620      	mov	r0, r4
    7bb0:	f7ff f928 	bl	6e04 <z_spin_lock_set_owner>
	pend_locked(_current, wait_q, timeout);
    7bb4:	f8da 0008 	ldr.w	r0, [sl, #8]
    7bb8:	4642      	mov	r2, r8
    7bba:	464b      	mov	r3, r9
    7bbc:	4639      	mov	r1, r7
    7bbe:	f7ff ffa9 	bl	7b14 <pend_locked>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7bc2:	4628      	mov	r0, r5
    7bc4:	f7ff f910 	bl	6de8 <z_spin_unlock_valid>
    7bc8:	b958      	cbnz	r0, 7be2 <z_pend_curr+0x9e>
    7bca:	4917      	ldr	r1, [pc, #92]	; (7c28 <z_pend_curr+0xe4>)
    7bcc:	23e1      	movs	r3, #225	; 0xe1
    7bce:	4a13      	ldr	r2, [pc, #76]	; (7c1c <z_pend_curr+0xd8>)
    7bd0:	4810      	ldr	r0, [pc, #64]	; (7c14 <z_pend_curr+0xd0>)
    7bd2:	f001 fb68 	bl	92a6 <assert_print>
    7bd6:	4629      	mov	r1, r5
    7bd8:	4814      	ldr	r0, [pc, #80]	; (7c2c <z_pend_curr+0xe8>)
    7bda:	f001 fb64 	bl	92a6 <assert_print>
    7bde:	21e1      	movs	r1, #225	; 0xe1
    7be0:	e7e3      	b.n	7baa <z_pend_curr+0x66>
    7be2:	4620      	mov	r0, r4
    7be4:	f7ff f900 	bl	6de8 <z_spin_unlock_valid>
    7be8:	b938      	cbnz	r0, 7bfa <z_pend_curr+0xb6>
    7bea:	490f      	ldr	r1, [pc, #60]	; (7c28 <z_pend_curr+0xe4>)
    7bec:	23e1      	movs	r3, #225	; 0xe1
    7bee:	4a0b      	ldr	r2, [pc, #44]	; (7c1c <z_pend_curr+0xd8>)
    7bf0:	4808      	ldr	r0, [pc, #32]	; (7c14 <z_pend_curr+0xd0>)
    7bf2:	f001 fb58 	bl	92a6 <assert_print>
    7bf6:	4621      	mov	r1, r4
    7bf8:	e7ee      	b.n	7bd8 <z_pend_curr+0x94>
    7bfa:	4630      	mov	r0, r6
}
    7bfc:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    7c00:	f7fb bd00 	b.w	3604 <arch_swap>
    7c04:	20000ea0 	.word	0x20000ea0
    7c08:	20000edc 	.word	0x20000edc
    7c0c:	20000ed0 	.word	0x20000ed0
    7c10:	0000bc11 	.word	0x0000bc11
    7c14:	0000a2e8 	.word	0x0000a2e8
    7c18:	0000bb1a 	.word	0x0000bb1a
    7c1c:	0000a51d 	.word	0x0000a51d
    7c20:	0000a576 	.word	0x0000a576
    7c24:	0000a58b 	.word	0x0000a58b
    7c28:	0000a54a 	.word	0x0000a54a
    7c2c:	0000a561 	.word	0x0000a561

00007c30 <z_set_prio>:
{
    7c30:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    7c34:	4604      	mov	r4, r0
    7c36:	460e      	mov	r6, r1
    7c38:	f04f 0320 	mov.w	r3, #32
    7c3c:	f3ef 8911 	mrs	r9, BASEPRI
    7c40:	f383 8812 	msr	BASEPRI_MAX, r3
    7c44:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    7c48:	4837      	ldr	r0, [pc, #220]	; (7d28 <z_set_prio+0xf8>)
    7c4a:	f7ff f8bf 	bl	6dcc <z_spin_lock_valid>
    7c4e:	4607      	mov	r7, r0
    7c50:	b960      	cbnz	r0, 7c6c <z_set_prio+0x3c>
    7c52:	2394      	movs	r3, #148	; 0x94
    7c54:	4a35      	ldr	r2, [pc, #212]	; (7d2c <z_set_prio+0xfc>)
    7c56:	4936      	ldr	r1, [pc, #216]	; (7d30 <z_set_prio+0x100>)
    7c58:	4836      	ldr	r0, [pc, #216]	; (7d34 <z_set_prio+0x104>)
    7c5a:	f001 fb24 	bl	92a6 <assert_print>
    7c5e:	4932      	ldr	r1, [pc, #200]	; (7d28 <z_set_prio+0xf8>)
    7c60:	4835      	ldr	r0, [pc, #212]	; (7d38 <z_set_prio+0x108>)
    7c62:	f001 fb20 	bl	92a6 <assert_print>
    7c66:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7c68:	4830      	ldr	r0, [pc, #192]	; (7d2c <z_set_prio+0xfc>)
    7c6a:	e021      	b.n	7cb0 <z_set_prio+0x80>
	z_spin_lock_set_owner(l);
    7c6c:	482e      	ldr	r0, [pc, #184]	; (7d28 <z_set_prio+0xf8>)
    7c6e:	f7ff f8c9 	bl	6e04 <z_spin_lock_set_owner>
	uint8_t state = thread->base.thread_state;
    7c72:	7b63      	ldrb	r3, [r4, #13]
				thread->base.prio = prio;
    7c74:	b276      	sxtb	r6, r6
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    7c76:	06da      	lsls	r2, r3, #27
    7c78:	d11c      	bne.n	7cb4 <z_set_prio+0x84>
	return node->next != NULL;
    7c7a:	69a5      	ldr	r5, [r4, #24]
    7c7c:	b9d5      	cbnz	r5, 7cb4 <z_set_prio+0x84>
	_priq_run_remove(thread_runq(thread), thread);
    7c7e:	f8df 80bc 	ldr.w	r8, [pc, #188]	; 7d3c <z_set_prio+0x10c>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    7c82:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    7c86:	7363      	strb	r3, [r4, #13]
	_priq_run_remove(thread_runq(thread), thread);
    7c88:	4621      	mov	r1, r4
    7c8a:	4640      	mov	r0, r8
    7c8c:	f7ff fe00 	bl	7890 <z_priq_dumb_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    7c90:	7b63      	ldrb	r3, [r4, #13]
				thread->base.prio = prio;
    7c92:	73a6      	strb	r6, [r4, #14]
	thread->base.thread_state |= _THREAD_QUEUED;
    7c94:	f063 037f 	orn	r3, r3, #127	; 0x7f
    7c98:	7363      	strb	r3, [r4, #13]
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));
    7c9a:	4b29      	ldr	r3, [pc, #164]	; (7d40 <z_set_prio+0x110>)
    7c9c:	429c      	cmp	r4, r3
    7c9e:	d11b      	bne.n	7cd8 <z_set_prio+0xa8>
    7ca0:	4928      	ldr	r1, [pc, #160]	; (7d44 <z_set_prio+0x114>)
    7ca2:	4824      	ldr	r0, [pc, #144]	; (7d34 <z_set_prio+0x104>)
    7ca4:	23ba      	movs	r3, #186	; 0xba
    7ca6:	4a28      	ldr	r2, [pc, #160]	; (7d48 <z_set_prio+0x118>)
    7ca8:	f001 fafd 	bl	92a6 <assert_print>
    7cac:	21ba      	movs	r1, #186	; 0xba
    7cae:	4826      	ldr	r0, [pc, #152]	; (7d48 <z_set_prio+0x118>)
    7cb0:	f001 faf2 	bl	9298 <assert_post_action>
    7cb4:	2700      	movs	r7, #0
			thread->base.prio = prio;
    7cb6:	73a6      	strb	r6, [r4, #14]
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7cb8:	481b      	ldr	r0, [pc, #108]	; (7d28 <z_set_prio+0xf8>)
    7cba:	f7ff f895 	bl	6de8 <z_spin_unlock_valid>
    7cbe:	bb58      	cbnz	r0, 7d18 <z_set_prio+0xe8>
    7cc0:	23c2      	movs	r3, #194	; 0xc2
    7cc2:	4a1a      	ldr	r2, [pc, #104]	; (7d2c <z_set_prio+0xfc>)
    7cc4:	4921      	ldr	r1, [pc, #132]	; (7d4c <z_set_prio+0x11c>)
    7cc6:	481b      	ldr	r0, [pc, #108]	; (7d34 <z_set_prio+0x104>)
    7cc8:	f001 faed 	bl	92a6 <assert_print>
    7ccc:	4916      	ldr	r1, [pc, #88]	; (7d28 <z_set_prio+0xf8>)
    7cce:	4820      	ldr	r0, [pc, #128]	; (7d50 <z_set_prio+0x120>)
    7cd0:	f001 fae9 	bl	92a6 <assert_print>
    7cd4:	21c2      	movs	r1, #194	; 0xc2
    7cd6:	e7c7      	b.n	7c68 <z_set_prio+0x38>
	return list->head == list;
    7cd8:	4643      	mov	r3, r8
    7cda:	f853 2920 	ldr.w	r2, [r3], #-32
	return sys_dlist_is_empty(list) ? NULL : list->head;
    7cde:	4542      	cmp	r2, r8
    7ce0:	bf18      	it	ne
    7ce2:	4615      	movne	r5, r2
	return (node == list->tail) ? NULL : node->next;
    7ce4:	6a5a      	ldr	r2, [r3, #36]	; 0x24
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    7ce6:	b925      	cbnz	r5, 7cf2 <z_set_prio+0xc2>
	node->prev = tail;
    7ce8:	e9c4 8200 	strd	r8, r2, [r4]
	tail->next = node;
    7cec:	6014      	str	r4, [r2, #0]
	list->tail = node;
    7cee:	625c      	str	r4, [r3, #36]	; 0x24
}
    7cf0:	e00a      	b.n	7d08 <z_set_prio+0xd8>
	int32_t b2 = thread_2->base.prio;
    7cf2:	f995 100e 	ldrsb.w	r1, [r5, #14]
	if (b1 != b2) {
    7cf6:	428e      	cmp	r6, r1
    7cf8:	d00a      	beq.n	7d10 <z_set_prio+0xe0>
		if (z_sched_prio_cmp(thread, t) > 0) {
    7cfa:	42b1      	cmp	r1, r6
    7cfc:	dd08      	ble.n	7d10 <z_set_prio+0xe0>
	sys_dnode_t *const prev = successor->prev;
    7cfe:	686b      	ldr	r3, [r5, #4]
	node->next = successor;
    7d00:	e9c4 5300 	strd	r5, r3, [r4]
	prev->next = node;
    7d04:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    7d06:	606c      	str	r4, [r5, #4]
			update_cache(1);
    7d08:	2001      	movs	r0, #1
    7d0a:	f7ff fadf 	bl	72cc <update_cache>
    7d0e:	e7d3      	b.n	7cb8 <z_set_prio+0x88>
	return (node == list->tail) ? NULL : node->next;
    7d10:	42aa      	cmp	r2, r5
    7d12:	d0e9      	beq.n	7ce8 <z_set_prio+0xb8>
    7d14:	682d      	ldr	r5, [r5, #0]
    7d16:	e7e6      	b.n	7ce6 <z_set_prio+0xb6>
	__asm__ volatile(
    7d18:	f389 8811 	msr	BASEPRI, r9
    7d1c:	f3bf 8f6f 	isb	sy
}
    7d20:	4638      	mov	r0, r7
    7d22:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    7d26:	bf00      	nop
    7d28:	20000edc 	.word	0x20000edc
    7d2c:	0000a51d 	.word	0x0000a51d
    7d30:	0000a576 	.word	0x0000a576
    7d34:	0000a2e8 	.word	0x0000a2e8
    7d38:	0000a58b 	.word	0x0000a58b
    7d3c:	20000ec0 	.word	0x20000ec0
    7d40:	20000660 	.word	0x20000660
    7d44:	0000bb63 	.word	0x0000bb63
    7d48:	0000bb1a 	.word	0x0000bb1a
    7d4c:	0000a54a 	.word	0x0000a54a
    7d50:	0000a561 	.word	0x0000a561

00007d54 <z_impl_k_thread_suspend>:
{
    7d54:	b570      	push	{r4, r5, r6, lr}
    7d56:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    7d58:	3018      	adds	r0, #24
    7d5a:	f000 fced 	bl	8738 <z_abort_timeout>
	__asm__ volatile(
    7d5e:	f04f 0320 	mov.w	r3, #32
    7d62:	f3ef 8611 	mrs	r6, BASEPRI
    7d66:	f383 8812 	msr	BASEPRI_MAX, r3
    7d6a:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    7d6e:	4824      	ldr	r0, [pc, #144]	; (7e00 <z_impl_k_thread_suspend+0xac>)
    7d70:	f7ff f82c 	bl	6dcc <z_spin_lock_valid>
    7d74:	b968      	cbnz	r0, 7d92 <z_impl_k_thread_suspend+0x3e>
    7d76:	2394      	movs	r3, #148	; 0x94
    7d78:	4a22      	ldr	r2, [pc, #136]	; (7e04 <z_impl_k_thread_suspend+0xb0>)
    7d7a:	4923      	ldr	r1, [pc, #140]	; (7e08 <z_impl_k_thread_suspend+0xb4>)
    7d7c:	4823      	ldr	r0, [pc, #140]	; (7e0c <z_impl_k_thread_suspend+0xb8>)
    7d7e:	f001 fa92 	bl	92a6 <assert_print>
    7d82:	491f      	ldr	r1, [pc, #124]	; (7e00 <z_impl_k_thread_suspend+0xac>)
    7d84:	4822      	ldr	r0, [pc, #136]	; (7e10 <z_impl_k_thread_suspend+0xbc>)
    7d86:	f001 fa8e 	bl	92a6 <assert_print>
    7d8a:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7d8c:	481d      	ldr	r0, [pc, #116]	; (7e04 <z_impl_k_thread_suspend+0xb0>)
    7d8e:	f001 fa83 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    7d92:	481b      	ldr	r0, [pc, #108]	; (7e00 <z_impl_k_thread_suspend+0xac>)
    7d94:	f7ff f836 	bl	6e04 <z_spin_lock_set_owner>
		if (z_is_thread_queued(thread)) {
    7d98:	f994 200d 	ldrsb.w	r2, [r4, #13]
	return (thread->base.thread_state & state) != 0U;
    7d9c:	7b63      	ldrb	r3, [r4, #13]
    7d9e:	2a00      	cmp	r2, #0
    7da0:	da06      	bge.n	7db0 <z_impl_k_thread_suspend+0x5c>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    7da2:	f003 037f 	and.w	r3, r3, #127	; 0x7f
	_priq_run_remove(thread_runq(thread), thread);
    7da6:	4621      	mov	r1, r4
    7da8:	481a      	ldr	r0, [pc, #104]	; (7e14 <z_impl_k_thread_suspend+0xc0>)
	thread->base.thread_state &= ~_THREAD_QUEUED;
    7daa:	7363      	strb	r3, [r4, #13]
	_priq_run_remove(thread_runq(thread), thread);
    7dac:	f7ff fd70 	bl	7890 <z_priq_dumb_remove>
		update_cache(thread == _current);
    7db0:	4d19      	ldr	r5, [pc, #100]	; (7e18 <z_impl_k_thread_suspend+0xc4>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    7db2:	7b63      	ldrb	r3, [r4, #13]
    7db4:	68a8      	ldr	r0, [r5, #8]
    7db6:	f043 0310 	orr.w	r3, r3, #16
    7dba:	7363      	strb	r3, [r4, #13]
    7dbc:	1b03      	subs	r3, r0, r4
    7dbe:	4258      	negs	r0, r3
    7dc0:	4158      	adcs	r0, r3
    7dc2:	f7ff fa83 	bl	72cc <update_cache>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7dc6:	480e      	ldr	r0, [pc, #56]	; (7e00 <z_impl_k_thread_suspend+0xac>)
    7dc8:	f7ff f80e 	bl	6de8 <z_spin_unlock_valid>
    7dcc:	b958      	cbnz	r0, 7de6 <z_impl_k_thread_suspend+0x92>
    7dce:	23c2      	movs	r3, #194	; 0xc2
    7dd0:	4a0c      	ldr	r2, [pc, #48]	; (7e04 <z_impl_k_thread_suspend+0xb0>)
    7dd2:	4912      	ldr	r1, [pc, #72]	; (7e1c <z_impl_k_thread_suspend+0xc8>)
    7dd4:	480d      	ldr	r0, [pc, #52]	; (7e0c <z_impl_k_thread_suspend+0xb8>)
    7dd6:	f001 fa66 	bl	92a6 <assert_print>
    7dda:	4909      	ldr	r1, [pc, #36]	; (7e00 <z_impl_k_thread_suspend+0xac>)
    7ddc:	4810      	ldr	r0, [pc, #64]	; (7e20 <z_impl_k_thread_suspend+0xcc>)
    7dde:	f001 fa62 	bl	92a6 <assert_print>
    7de2:	21c2      	movs	r1, #194	; 0xc2
    7de4:	e7d2      	b.n	7d8c <z_impl_k_thread_suspend+0x38>
	__asm__ volatile(
    7de6:	f386 8811 	msr	BASEPRI, r6
    7dea:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    7dee:	68ab      	ldr	r3, [r5, #8]
    7df0:	42a3      	cmp	r3, r4
    7df2:	d103      	bne.n	7dfc <z_impl_k_thread_suspend+0xa8>
}
    7df4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    7df8:	f001 bef8 	b.w	9bec <z_reschedule_unlocked>
}
    7dfc:	bd70      	pop	{r4, r5, r6, pc}
    7dfe:	bf00      	nop
    7e00:	20000edc 	.word	0x20000edc
    7e04:	0000a51d 	.word	0x0000a51d
    7e08:	0000a576 	.word	0x0000a576
    7e0c:	0000a2e8 	.word	0x0000a2e8
    7e10:	0000a58b 	.word	0x0000a58b
    7e14:	20000ec0 	.word	0x20000ec0
    7e18:	20000ea0 	.word	0x20000ea0
    7e1c:	0000a54a 	.word	0x0000a54a
    7e20:	0000a561 	.word	0x0000a561

00007e24 <unpend_thread_no_timeout>:
{
    7e24:	b510      	push	{r4, lr}
    7e26:	4604      	mov	r4, r0
    7e28:	6880      	ldr	r0, [r0, #8]
	__ASSERT_NO_MSG(thread->base.pended_on);
    7e2a:	b958      	cbnz	r0, 7e44 <unpend_thread_no_timeout+0x20>
    7e2c:	490a      	ldr	r1, [pc, #40]	; (7e58 <unpend_thread_no_timeout+0x34>)
    7e2e:	480b      	ldr	r0, [pc, #44]	; (7e5c <unpend_thread_no_timeout+0x38>)
    7e30:	f240 23d6 	movw	r3, #726	; 0x2d6
    7e34:	4a0a      	ldr	r2, [pc, #40]	; (7e60 <unpend_thread_no_timeout+0x3c>)
    7e36:	f001 fa36 	bl	92a6 <assert_print>
    7e3a:	f240 21d6 	movw	r1, #726	; 0x2d6
    7e3e:	4808      	ldr	r0, [pc, #32]	; (7e60 <unpend_thread_no_timeout+0x3c>)
    7e40:	f001 fa2a 	bl	9298 <assert_post_action>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    7e44:	4621      	mov	r1, r4
    7e46:	f7ff fd23 	bl	7890 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    7e4a:	7b63      	ldrb	r3, [r4, #13]
    7e4c:	f023 0302 	bic.w	r3, r3, #2
    7e50:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    7e52:	2300      	movs	r3, #0
    7e54:	60a3      	str	r3, [r4, #8]
}
    7e56:	bd10      	pop	{r4, pc}
    7e58:	0000bc48 	.word	0x0000bc48
    7e5c:	0000a2e8 	.word	0x0000a2e8
    7e60:	0000bb1a 	.word	0x0000bb1a

00007e64 <z_thread_timeout>:
{
    7e64:	b570      	push	{r4, r5, r6, lr}
    7e66:	4604      	mov	r4, r0
	__asm__ volatile(
    7e68:	f04f 0320 	mov.w	r3, #32
    7e6c:	f3ef 8611 	mrs	r6, BASEPRI
    7e70:	f383 8812 	msr	BASEPRI_MAX, r3
    7e74:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    7e78:	481f      	ldr	r0, [pc, #124]	; (7ef8 <z_thread_timeout+0x94>)
    7e7a:	f7fe ffa7 	bl	6dcc <z_spin_lock_valid>
    7e7e:	b968      	cbnz	r0, 7e9c <z_thread_timeout+0x38>
    7e80:	2394      	movs	r3, #148	; 0x94
    7e82:	4a1e      	ldr	r2, [pc, #120]	; (7efc <z_thread_timeout+0x98>)
    7e84:	491e      	ldr	r1, [pc, #120]	; (7f00 <z_thread_timeout+0x9c>)
    7e86:	481f      	ldr	r0, [pc, #124]	; (7f04 <z_thread_timeout+0xa0>)
    7e88:	f001 fa0d 	bl	92a6 <assert_print>
    7e8c:	491a      	ldr	r1, [pc, #104]	; (7ef8 <z_thread_timeout+0x94>)
    7e8e:	481e      	ldr	r0, [pc, #120]	; (7f08 <z_thread_timeout+0xa4>)
    7e90:	f001 fa09 	bl	92a6 <assert_print>
    7e94:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7e96:	4819      	ldr	r0, [pc, #100]	; (7efc <z_thread_timeout+0x98>)
    7e98:	f001 f9fe 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    7e9c:	4816      	ldr	r0, [pc, #88]	; (7ef8 <z_thread_timeout+0x94>)
    7e9e:	f7fe ffb1 	bl	6e04 <z_spin_lock_set_owner>
		if (!killed) {
    7ea2:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
    7ea6:	f013 0f28 	tst.w	r3, #40	; 0x28
    7eaa:	d110      	bne.n	7ece <z_thread_timeout+0x6a>
			if (thread->base.pended_on != NULL) {
    7eac:	f854 3c10 	ldr.w	r3, [r4, #-16]
	struct k_thread *thread = CONTAINER_OF(timeout,
    7eb0:	f1a4 0518 	sub.w	r5, r4, #24
			if (thread->base.pended_on != NULL) {
    7eb4:	b113      	cbz	r3, 7ebc <z_thread_timeout+0x58>
				unpend_thread_no_timeout(thread);
    7eb6:	4628      	mov	r0, r5
    7eb8:	f7ff ffb4 	bl	7e24 <unpend_thread_no_timeout>
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    7ebc:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
			ready_thread(thread);
    7ec0:	4628      	mov	r0, r5
    7ec2:	f023 0314 	bic.w	r3, r3, #20
    7ec6:	f804 3c0b 	strb.w	r3, [r4, #-11]
    7eca:	f7ff fa33 	bl	7334 <ready_thread>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7ece:	480a      	ldr	r0, [pc, #40]	; (7ef8 <z_thread_timeout+0x94>)
    7ed0:	f7fe ff8a 	bl	6de8 <z_spin_unlock_valid>
    7ed4:	b958      	cbnz	r0, 7eee <z_thread_timeout+0x8a>
    7ed6:	23c2      	movs	r3, #194	; 0xc2
    7ed8:	4a08      	ldr	r2, [pc, #32]	; (7efc <z_thread_timeout+0x98>)
    7eda:	490c      	ldr	r1, [pc, #48]	; (7f0c <z_thread_timeout+0xa8>)
    7edc:	4809      	ldr	r0, [pc, #36]	; (7f04 <z_thread_timeout+0xa0>)
    7ede:	f001 f9e2 	bl	92a6 <assert_print>
    7ee2:	4905      	ldr	r1, [pc, #20]	; (7ef8 <z_thread_timeout+0x94>)
    7ee4:	480a      	ldr	r0, [pc, #40]	; (7f10 <z_thread_timeout+0xac>)
    7ee6:	f001 f9de 	bl	92a6 <assert_print>
    7eea:	21c2      	movs	r1, #194	; 0xc2
    7eec:	e7d3      	b.n	7e96 <z_thread_timeout+0x32>
	__asm__ volatile(
    7eee:	f386 8811 	msr	BASEPRI, r6
    7ef2:	f3bf 8f6f 	isb	sy
}
    7ef6:	bd70      	pop	{r4, r5, r6, pc}
    7ef8:	20000edc 	.word	0x20000edc
    7efc:	0000a51d 	.word	0x0000a51d
    7f00:	0000a576 	.word	0x0000a576
    7f04:	0000a2e8 	.word	0x0000a2e8
    7f08:	0000a58b 	.word	0x0000a58b
    7f0c:	0000a54a 	.word	0x0000a54a
    7f10:	0000a561 	.word	0x0000a561

00007f14 <z_unpend1_no_timeout>:
{
    7f14:	b570      	push	{r4, r5, r6, lr}
    7f16:	4605      	mov	r5, r0
	__asm__ volatile(
    7f18:	f04f 0320 	mov.w	r3, #32
    7f1c:	f3ef 8611 	mrs	r6, BASEPRI
    7f20:	f383 8812 	msr	BASEPRI_MAX, r3
    7f24:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    7f28:	4819      	ldr	r0, [pc, #100]	; (7f90 <z_unpend1_no_timeout+0x7c>)
    7f2a:	f7fe ff4f 	bl	6dcc <z_spin_lock_valid>
    7f2e:	b968      	cbnz	r0, 7f4c <z_unpend1_no_timeout+0x38>
    7f30:	2394      	movs	r3, #148	; 0x94
    7f32:	4a18      	ldr	r2, [pc, #96]	; (7f94 <z_unpend1_no_timeout+0x80>)
    7f34:	4918      	ldr	r1, [pc, #96]	; (7f98 <z_unpend1_no_timeout+0x84>)
    7f36:	4819      	ldr	r0, [pc, #100]	; (7f9c <z_unpend1_no_timeout+0x88>)
    7f38:	f001 f9b5 	bl	92a6 <assert_print>
    7f3c:	4914      	ldr	r1, [pc, #80]	; (7f90 <z_unpend1_no_timeout+0x7c>)
    7f3e:	4818      	ldr	r0, [pc, #96]	; (7fa0 <z_unpend1_no_timeout+0x8c>)
    7f40:	f001 f9b1 	bl	92a6 <assert_print>
    7f44:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7f46:	4813      	ldr	r0, [pc, #76]	; (7f94 <z_unpend1_no_timeout+0x80>)
    7f48:	f001 f9a6 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    7f4c:	4810      	ldr	r0, [pc, #64]	; (7f90 <z_unpend1_no_timeout+0x7c>)
    7f4e:	f7fe ff59 	bl	6e04 <z_spin_lock_set_owner>
	return list->head == list;
    7f52:	682c      	ldr	r4, [r5, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    7f54:	42a5      	cmp	r5, r4
    7f56:	d013      	beq.n	7f80 <z_unpend1_no_timeout+0x6c>
		if (thread != NULL) {
    7f58:	b114      	cbz	r4, 7f60 <z_unpend1_no_timeout+0x4c>
			unpend_thread_no_timeout(thread);
    7f5a:	4620      	mov	r0, r4
    7f5c:	f7ff ff62 	bl	7e24 <unpend_thread_no_timeout>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7f60:	480b      	ldr	r0, [pc, #44]	; (7f90 <z_unpend1_no_timeout+0x7c>)
    7f62:	f7fe ff41 	bl	6de8 <z_spin_unlock_valid>
    7f66:	b968      	cbnz	r0, 7f84 <z_unpend1_no_timeout+0x70>
    7f68:	23c2      	movs	r3, #194	; 0xc2
    7f6a:	4a0a      	ldr	r2, [pc, #40]	; (7f94 <z_unpend1_no_timeout+0x80>)
    7f6c:	490d      	ldr	r1, [pc, #52]	; (7fa4 <z_unpend1_no_timeout+0x90>)
    7f6e:	480b      	ldr	r0, [pc, #44]	; (7f9c <z_unpend1_no_timeout+0x88>)
    7f70:	f001 f999 	bl	92a6 <assert_print>
    7f74:	4906      	ldr	r1, [pc, #24]	; (7f90 <z_unpend1_no_timeout+0x7c>)
    7f76:	480c      	ldr	r0, [pc, #48]	; (7fa8 <z_unpend1_no_timeout+0x94>)
    7f78:	f001 f995 	bl	92a6 <assert_print>
    7f7c:	21c2      	movs	r1, #194	; 0xc2
    7f7e:	e7e2      	b.n	7f46 <z_unpend1_no_timeout+0x32>
    7f80:	2400      	movs	r4, #0
    7f82:	e7ed      	b.n	7f60 <z_unpend1_no_timeout+0x4c>
	__asm__ volatile(
    7f84:	f386 8811 	msr	BASEPRI, r6
    7f88:	f3bf 8f6f 	isb	sy
}
    7f8c:	4620      	mov	r0, r4
    7f8e:	bd70      	pop	{r4, r5, r6, pc}
    7f90:	20000edc 	.word	0x20000edc
    7f94:	0000a51d 	.word	0x0000a51d
    7f98:	0000a576 	.word	0x0000a576
    7f9c:	0000a2e8 	.word	0x0000a2e8
    7fa0:	0000a58b 	.word	0x0000a58b
    7fa4:	0000a54a 	.word	0x0000a54a
    7fa8:	0000a561 	.word	0x0000a561

00007fac <z_unpend_first_thread>:
{
    7fac:	b570      	push	{r4, r5, r6, lr}
    7fae:	4605      	mov	r5, r0
	__asm__ volatile(
    7fb0:	f04f 0320 	mov.w	r3, #32
    7fb4:	f3ef 8611 	mrs	r6, BASEPRI
    7fb8:	f383 8812 	msr	BASEPRI_MAX, r3
    7fbc:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    7fc0:	481b      	ldr	r0, [pc, #108]	; (8030 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x30>)
    7fc2:	f7fe ff03 	bl	6dcc <z_spin_lock_valid>
    7fc6:	b968      	cbnz	r0, 7fe4 <z_unpend_first_thread+0x38>
    7fc8:	2394      	movs	r3, #148	; 0x94
    7fca:	4a1a      	ldr	r2, [pc, #104]	; (8034 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x34>)
    7fcc:	491a      	ldr	r1, [pc, #104]	; (8038 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x38>)
    7fce:	481b      	ldr	r0, [pc, #108]	; (803c <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x3c>)
    7fd0:	f001 f969 	bl	92a6 <assert_print>
    7fd4:	4916      	ldr	r1, [pc, #88]	; (8030 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x30>)
    7fd6:	481a      	ldr	r0, [pc, #104]	; (8040 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x40>)
    7fd8:	f001 f965 	bl	92a6 <assert_print>
    7fdc:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    7fde:	4815      	ldr	r0, [pc, #84]	; (8034 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x34>)
    7fe0:	f001 f95a 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    7fe4:	4812      	ldr	r0, [pc, #72]	; (8030 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x30>)
    7fe6:	f7fe ff0d 	bl	6e04 <z_spin_lock_set_owner>
	return list->head == list;
    7fea:	682c      	ldr	r4, [r5, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    7fec:	42a5      	cmp	r5, r4
    7fee:	d017      	beq.n	8020 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x20>
		if (thread != NULL) {
    7ff0:	b134      	cbz	r4, 8000 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE>
			unpend_thread_no_timeout(thread);
    7ff2:	4620      	mov	r0, r4
    7ff4:	f7ff ff16 	bl	7e24 <unpend_thread_no_timeout>
    7ff8:	f104 0018 	add.w	r0, r4, #24
    7ffc:	f000 fb9c 	bl	8738 <z_abort_timeout>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8000:	480b      	ldr	r0, [pc, #44]	; (8030 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x30>)
    8002:	f7fe fef1 	bl	6de8 <z_spin_unlock_valid>
    8006:	b968      	cbnz	r0, 8024 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x24>
    8008:	23c2      	movs	r3, #194	; 0xc2
    800a:	4a0a      	ldr	r2, [pc, #40]	; (8034 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x34>)
    800c:	490d      	ldr	r1, [pc, #52]	; (8044 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x44>)
    800e:	480b      	ldr	r0, [pc, #44]	; (803c <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x3c>)
    8010:	f001 f949 	bl	92a6 <assert_print>
    8014:	4906      	ldr	r1, [pc, #24]	; (8030 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x30>)
    8016:	480c      	ldr	r0, [pc, #48]	; (8048 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x48>)
    8018:	f001 f945 	bl	92a6 <assert_print>
    801c:	21c2      	movs	r1, #194	; 0xc2
    801e:	e7de      	b.n	7fde <z_unpend_first_thread+0x32>
    8020:	2400      	movs	r4, #0
    8022:	e7ed      	b.n	8000 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE>
	__asm__ volatile(
    8024:	f386 8811 	msr	BASEPRI, r6
    8028:	f3bf 8f6f 	isb	sy
}
    802c:	4620      	mov	r0, r4
    802e:	bd70      	pop	{r4, r5, r6, pc}
    8030:	20000edc 	.word	0x20000edc
    8034:	0000a51d 	.word	0x0000a51d
    8038:	0000a576 	.word	0x0000a576
    803c:	0000a2e8 	.word	0x0000a2e8
    8040:	0000a58b 	.word	0x0000a58b
    8044:	0000a54a 	.word	0x0000a54a
    8048:	0000a561 	.word	0x0000a561

0000804c <z_sched_init>:
#else
	init_ready_q(&_kernel.ready_q);
#endif

#ifdef CONFIG_TIMESLICING
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    804c:	2100      	movs	r1, #0
	list->head = (sys_dnode_t *)list;
    804e:	4b04      	ldr	r3, [pc, #16]	; (8060 <z_sched_init+0x14>)
    8050:	4608      	mov	r0, r1
    8052:	f103 0220 	add.w	r2, r3, #32
	list->tail = (sys_dnode_t *)list;
    8056:	e9c3 2208 	strd	r2, r2, [r3, #32]
    805a:	f7ff b9b5 	b.w	73c8 <k_sched_time_slice_set>
    805e:	bf00      	nop
    8060:	20000ea0 	.word	0x20000ea0

00008064 <z_impl_k_yield>:
	return !(k_is_pre_kernel() || k_is_in_isr() ||
		 z_is_idle_thread_object(_current));
}

void z_impl_k_yield(void)
{
    8064:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    8066:	f3ef 8305 	mrs	r3, IPSR
	__ASSERT(!arch_is_in_isr(), "");
    806a:	b16b      	cbz	r3, 8088 <z_impl_k_yield+0x24>
    806c:	493c      	ldr	r1, [pc, #240]	; (8160 <z_impl_k_yield+0xfc>)
    806e:	f44f 63ae 	mov.w	r3, #1392	; 0x570
    8072:	4a3c      	ldr	r2, [pc, #240]	; (8164 <z_impl_k_yield+0x100>)
    8074:	483c      	ldr	r0, [pc, #240]	; (8168 <z_impl_k_yield+0x104>)
    8076:	f001 f916 	bl	92a6 <assert_print>
    807a:	483c      	ldr	r0, [pc, #240]	; (816c <z_impl_k_yield+0x108>)
    807c:	f001 f913 	bl	92a6 <assert_print>
    8080:	f44f 61ae 	mov.w	r1, #1392	; 0x570
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));
    8084:	4837      	ldr	r0, [pc, #220]	; (8164 <z_impl_k_yield+0x100>)
    8086:	e017      	b.n	80b8 <z_impl_k_yield+0x54>
	__asm__ volatile(
    8088:	f04f 0320 	mov.w	r3, #32
    808c:	f3ef 8611 	mrs	r6, BASEPRI
    8090:	f383 8812 	msr	BASEPRI_MAX, r3
    8094:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    8098:	4835      	ldr	r0, [pc, #212]	; (8170 <z_impl_k_yield+0x10c>)
    809a:	f7fe fe97 	bl	6dcc <z_spin_lock_valid>
    809e:	b968      	cbnz	r0, 80bc <z_impl_k_yield+0x58>
    80a0:	2394      	movs	r3, #148	; 0x94
    80a2:	4a34      	ldr	r2, [pc, #208]	; (8174 <z_impl_k_yield+0x110>)
    80a4:	4934      	ldr	r1, [pc, #208]	; (8178 <z_impl_k_yield+0x114>)
    80a6:	4830      	ldr	r0, [pc, #192]	; (8168 <z_impl_k_yield+0x104>)
    80a8:	f001 f8fd 	bl	92a6 <assert_print>
    80ac:	4930      	ldr	r1, [pc, #192]	; (8170 <z_impl_k_yield+0x10c>)
    80ae:	4833      	ldr	r0, [pc, #204]	; (817c <z_impl_k_yield+0x118>)
    80b0:	f001 f8f9 	bl	92a6 <assert_print>
    80b4:	2194      	movs	r1, #148	; 0x94
    80b6:	482f      	ldr	r0, [pc, #188]	; (8174 <z_impl_k_yield+0x110>)
    80b8:	f001 f8ee 	bl	9298 <assert_post_action>

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if (!IS_ENABLED(CONFIG_SMP) ||
	    z_is_thread_queued(_current)) {
		dequeue_thread(_current);
    80bc:	4c30      	ldr	r4, [pc, #192]	; (8180 <z_impl_k_yield+0x11c>)
	z_spin_lock_set_owner(l);
    80be:	482c      	ldr	r0, [pc, #176]	; (8170 <z_impl_k_yield+0x10c>)
    80c0:	f7fe fea0 	bl	6e04 <z_spin_lock_set_owner>
    80c4:	68a1      	ldr	r1, [r4, #8]
	_priq_run_remove(thread_runq(thread), thread);
    80c6:	f104 0520 	add.w	r5, r4, #32
	thread->base.thread_state &= ~_THREAD_QUEUED;
    80ca:	7b4b      	ldrb	r3, [r1, #13]
	_priq_run_remove(thread_runq(thread), thread);
    80cc:	4628      	mov	r0, r5
	thread->base.thread_state &= ~_THREAD_QUEUED;
    80ce:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    80d2:	734b      	strb	r3, [r1, #13]
	_priq_run_remove(thread_runq(thread), thread);
    80d4:	f7ff fbdc 	bl	7890 <z_priq_dumb_remove>
	}
	queue_thread(_current);
    80d8:	68a3      	ldr	r3, [r4, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    80da:	7b5a      	ldrb	r2, [r3, #13]
    80dc:	f062 027f 	orn	r2, r2, #127	; 0x7f
    80e0:	735a      	strb	r2, [r3, #13]
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));
    80e2:	4a28      	ldr	r2, [pc, #160]	; (8184 <z_impl_k_yield+0x120>)
    80e4:	4293      	cmp	r3, r2
    80e6:	d107      	bne.n	80f8 <z_impl_k_yield+0x94>
    80e8:	4927      	ldr	r1, [pc, #156]	; (8188 <z_impl_k_yield+0x124>)
    80ea:	23ba      	movs	r3, #186	; 0xba
    80ec:	4a1d      	ldr	r2, [pc, #116]	; (8164 <z_impl_k_yield+0x100>)
    80ee:	481e      	ldr	r0, [pc, #120]	; (8168 <z_impl_k_yield+0x104>)
    80f0:	f001 f8d9 	bl	92a6 <assert_print>
    80f4:	21ba      	movs	r1, #186	; 0xba
    80f6:	e7c5      	b.n	8084 <z_impl_k_yield+0x20>
	return list->head == list;
    80f8:	6a22      	ldr	r2, [r4, #32]
	return (node == list->tail) ? NULL : node->next;
    80fa:	6a61      	ldr	r1, [r4, #36]	; 0x24
	return sys_dlist_is_empty(list) ? NULL : list->head;
    80fc:	42aa      	cmp	r2, r5
    80fe:	bf08      	it	eq
    8100:	2200      	moveq	r2, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    8102:	b922      	cbnz	r2, 810e <z_impl_k_yield+0xaa>
	node->prev = tail;
    8104:	e9c3 5100 	strd	r5, r1, [r3]
	tail->next = node;
    8108:	600b      	str	r3, [r1, #0]
	list->tail = node;
    810a:	6263      	str	r3, [r4, #36]	; 0x24
}
    810c:	e00c      	b.n	8128 <z_impl_k_yield+0xc4>
	int32_t b1 = thread_1->base.prio;
    810e:	f993 000e 	ldrsb.w	r0, [r3, #14]
	int32_t b2 = thread_2->base.prio;
    8112:	f992 700e 	ldrsb.w	r7, [r2, #14]
	if (b1 != b2) {
    8116:	42b8      	cmp	r0, r7
    8118:	d019      	beq.n	814e <z_impl_k_yield+0xea>
		if (z_sched_prio_cmp(thread, t) > 0) {
    811a:	4287      	cmp	r7, r0
    811c:	dd17      	ble.n	814e <z_impl_k_yield+0xea>
	sys_dnode_t *const prev = successor->prev;
    811e:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
    8120:	e9c3 2100 	strd	r2, r1, [r3]
	prev->next = node;
    8124:	600b      	str	r3, [r1, #0]
	successor->prev = node;
    8126:	6053      	str	r3, [r2, #4]
	update_cache(1);
    8128:	2001      	movs	r0, #1
    812a:	f7ff f8cf 	bl	72cc <update_cache>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    812e:	4810      	ldr	r0, [pc, #64]	; (8170 <z_impl_k_yield+0x10c>)
    8130:	f7fe fe5a 	bl	6de8 <z_spin_unlock_valid>
    8134:	b978      	cbnz	r0, 8156 <z_impl_k_yield+0xf2>
    8136:	23e1      	movs	r3, #225	; 0xe1
    8138:	4a0e      	ldr	r2, [pc, #56]	; (8174 <z_impl_k_yield+0x110>)
    813a:	4914      	ldr	r1, [pc, #80]	; (818c <z_impl_k_yield+0x128>)
    813c:	480a      	ldr	r0, [pc, #40]	; (8168 <z_impl_k_yield+0x104>)
    813e:	f001 f8b2 	bl	92a6 <assert_print>
    8142:	490b      	ldr	r1, [pc, #44]	; (8170 <z_impl_k_yield+0x10c>)
    8144:	4812      	ldr	r0, [pc, #72]	; (8190 <z_impl_k_yield+0x12c>)
    8146:	f001 f8ae 	bl	92a6 <assert_print>
    814a:	21e1      	movs	r1, #225	; 0xe1
    814c:	e7b3      	b.n	80b6 <z_impl_k_yield+0x52>
	return (node == list->tail) ? NULL : node->next;
    814e:	428a      	cmp	r2, r1
    8150:	d0d8      	beq.n	8104 <z_impl_k_yield+0xa0>
    8152:	6812      	ldr	r2, [r2, #0]
    8154:	e7d5      	b.n	8102 <z_impl_k_yield+0x9e>
    8156:	4630      	mov	r0, r6
	z_swap(&sched_spinlock, key);
}
    8158:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    815c:	f7fb ba52 	b.w	3604 <arch_swap>
    8160:	0000ba5b 	.word	0x0000ba5b
    8164:	0000bb1a 	.word	0x0000bb1a
    8168:	0000a2e8 	.word	0x0000a2e8
    816c:	0000bb17 	.word	0x0000bb17
    8170:	20000edc 	.word	0x20000edc
    8174:	0000a51d 	.word	0x0000a51d
    8178:	0000a576 	.word	0x0000a576
    817c:	0000a58b 	.word	0x0000a58b
    8180:	20000ea0 	.word	0x20000ea0
    8184:	20000660 	.word	0x20000660
    8188:	0000bb63 	.word	0x0000bb63
    818c:	0000a54a 	.word	0x0000a54a
    8190:	0000a561 	.word	0x0000a561

00008194 <z_tick_sleep>:
}
#include <syscalls/k_yield_mrsh.c>
#endif

static int32_t z_tick_sleep(k_ticks_t ticks)
{
    8194:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    8198:	4605      	mov	r5, r0
    819a:	460e      	mov	r6, r1
    819c:	f3ef 8305 	mrs	r3, IPSR
#ifdef CONFIG_MULTITHREADING
	uint32_t expected_wakeup_ticks;

	__ASSERT(!arch_is_in_isr(), "");
    81a0:	b16b      	cbz	r3, 81be <z_tick_sleep+0x2a>
    81a2:	493f      	ldr	r1, [pc, #252]	; (82a0 <z_tick_sleep+0x10c>)
    81a4:	f240 538c 	movw	r3, #1420	; 0x58c
    81a8:	4a3e      	ldr	r2, [pc, #248]	; (82a4 <z_tick_sleep+0x110>)
    81aa:	483f      	ldr	r0, [pc, #252]	; (82a8 <z_tick_sleep+0x114>)
    81ac:	f001 f87b 	bl	92a6 <assert_print>
    81b0:	483e      	ldr	r0, [pc, #248]	; (82ac <z_tick_sleep+0x118>)
    81b2:	f001 f878 	bl	92a6 <assert_print>
    81b6:	f240 518c 	movw	r1, #1420	; 0x58c
	z_add_thread_timeout(_current, timeout);
	z_mark_thread_as_suspended(_current);

	(void)z_swap(&sched_spinlock, key);

	__ASSERT(!z_is_thread_state_set(_current, _THREAD_SUSPENDED), "");
    81ba:	483a      	ldr	r0, [pc, #232]	; (82a4 <z_tick_sleep+0x110>)
    81bc:	e025      	b.n	820a <z_tick_sleep+0x76>
	if (ticks == 0) {
    81be:	ea50 0301 	orrs.w	r3, r0, r1
    81c2:	d103      	bne.n	81cc <z_tick_sleep+0x38>
	z_impl_k_yield();
    81c4:	f7ff ff4e 	bl	8064 <z_impl_k_yield>
		return 0;
    81c8:	2000      	movs	r0, #0
    81ca:	e066      	b.n	829a <z_tick_sleep+0x106>
	if (Z_TICK_ABS(ticks) <= 0) {
    81cc:	1c82      	adds	r2, r0, #2
    81ce:	f171 33ff 	sbcs.w	r3, r1, #4294967295
    81d2:	db1c      	blt.n	820e <z_tick_sleep+0x7a>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    81d4:	f001 fd14 	bl	9c00 <sys_clock_tick_get_32>
    81d8:	182c      	adds	r4, r5, r0
    81da:	f04f 0320 	mov.w	r3, #32
    81de:	f3ef 8811 	mrs	r8, BASEPRI
    81e2:	f383 8812 	msr	BASEPRI_MAX, r3
    81e6:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    81ea:	4831      	ldr	r0, [pc, #196]	; (82b0 <z_tick_sleep+0x11c>)
    81ec:	f7fe fdee 	bl	6dcc <z_spin_lock_valid>
    81f0:	b988      	cbnz	r0, 8216 <z_tick_sleep+0x82>
    81f2:	2394      	movs	r3, #148	; 0x94
    81f4:	4a2f      	ldr	r2, [pc, #188]	; (82b4 <z_tick_sleep+0x120>)
    81f6:	4930      	ldr	r1, [pc, #192]	; (82b8 <z_tick_sleep+0x124>)
    81f8:	482b      	ldr	r0, [pc, #172]	; (82a8 <z_tick_sleep+0x114>)
    81fa:	f001 f854 	bl	92a6 <assert_print>
    81fe:	492c      	ldr	r1, [pc, #176]	; (82b0 <z_tick_sleep+0x11c>)
    8200:	482e      	ldr	r0, [pc, #184]	; (82bc <z_tick_sleep+0x128>)
    8202:	f001 f850 	bl	92a6 <assert_print>
    8206:	2194      	movs	r1, #148	; 0x94
    8208:	482a      	ldr	r0, [pc, #168]	; (82b4 <z_tick_sleep+0x120>)
    820a:	f001 f845 	bl	9298 <assert_post_action>
		expected_wakeup_ticks = Z_TICK_ABS(ticks);
    820e:	f06f 0401 	mvn.w	r4, #1
    8212:	1a24      	subs	r4, r4, r0
    8214:	e7e1      	b.n	81da <z_tick_sleep+0x46>
	pending_current = _current;
    8216:	4f2a      	ldr	r7, [pc, #168]	; (82c0 <z_tick_sleep+0x12c>)
	z_spin_lock_set_owner(l);
    8218:	4825      	ldr	r0, [pc, #148]	; (82b0 <z_tick_sleep+0x11c>)
    821a:	f7fe fdf3 	bl	6e04 <z_spin_lock_set_owner>
    821e:	68b8      	ldr	r0, [r7, #8]
    8220:	4b28      	ldr	r3, [pc, #160]	; (82c4 <z_tick_sleep+0x130>)
    8222:	6018      	str	r0, [r3, #0]
	unready_thread(_current);
    8224:	f7ff fc1c 	bl	7a60 <unready_thread>
	z_add_thread_timeout(_current, timeout);
    8228:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    822a:	462a      	mov	r2, r5
    822c:	4633      	mov	r3, r6
    822e:	3018      	adds	r0, #24
    8230:	4925      	ldr	r1, [pc, #148]	; (82c8 <z_tick_sleep+0x134>)
    8232:	f000 f9bb 	bl	85ac <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    8236:	68ba      	ldr	r2, [r7, #8]
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8238:	481d      	ldr	r0, [pc, #116]	; (82b0 <z_tick_sleep+0x11c>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    823a:	7b53      	ldrb	r3, [r2, #13]
    823c:	f043 0310 	orr.w	r3, r3, #16
    8240:	7353      	strb	r3, [r2, #13]
    8242:	f7fe fdd1 	bl	6de8 <z_spin_unlock_valid>
    8246:	b958      	cbnz	r0, 8260 <z_tick_sleep+0xcc>
    8248:	23e1      	movs	r3, #225	; 0xe1
    824a:	4a1a      	ldr	r2, [pc, #104]	; (82b4 <z_tick_sleep+0x120>)
    824c:	491f      	ldr	r1, [pc, #124]	; (82cc <z_tick_sleep+0x138>)
    824e:	4816      	ldr	r0, [pc, #88]	; (82a8 <z_tick_sleep+0x114>)
    8250:	f001 f829 	bl	92a6 <assert_print>
    8254:	4916      	ldr	r1, [pc, #88]	; (82b0 <z_tick_sleep+0x11c>)
    8256:	481e      	ldr	r0, [pc, #120]	; (82d0 <z_tick_sleep+0x13c>)
    8258:	f001 f825 	bl	92a6 <assert_print>
    825c:	21e1      	movs	r1, #225	; 0xe1
    825e:	e7d3      	b.n	8208 <z_tick_sleep+0x74>
    8260:	4640      	mov	r0, r8
    8262:	f7fb f9cf 	bl	3604 <arch_swap>
	return (thread->base.thread_state & state) != 0U;
    8266:	68bb      	ldr	r3, [r7, #8]
	__ASSERT(!z_is_thread_state_set(_current, _THREAD_SUSPENDED), "");
    8268:	7b5b      	ldrb	r3, [r3, #13]
    826a:	06db      	lsls	r3, r3, #27
    826c:	d50c      	bpl.n	8288 <z_tick_sleep+0xf4>
    826e:	4919      	ldr	r1, [pc, #100]	; (82d4 <z_tick_sleep+0x140>)
    8270:	f44f 63b5 	mov.w	r3, #1448	; 0x5a8
    8274:	4a0b      	ldr	r2, [pc, #44]	; (82a4 <z_tick_sleep+0x110>)
    8276:	480c      	ldr	r0, [pc, #48]	; (82a8 <z_tick_sleep+0x114>)
    8278:	f001 f815 	bl	92a6 <assert_print>
    827c:	480b      	ldr	r0, [pc, #44]	; (82ac <z_tick_sleep+0x118>)
    827e:	f001 f812 	bl	92a6 <assert_print>
    8282:	f44f 61b5 	mov.w	r1, #1448	; 0x5a8
    8286:	e798      	b.n	81ba <z_tick_sleep+0x26>

	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    8288:	f001 fcba 	bl	9c00 <sys_clock_tick_get_32>
    828c:	1a20      	subs	r0, r4, r0
    828e:	eb63 0303 	sbc.w	r3, r3, r3
	if (ticks > 0) {
    8292:	2801      	cmp	r0, #1
    8294:	f173 0300 	sbcs.w	r3, r3, #0
    8298:	db96      	blt.n	81c8 <z_tick_sleep+0x34>
		return ticks;
	}
#endif

	return 0;
}
    829a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    829e:	bf00      	nop
    82a0:	0000ba5b 	.word	0x0000ba5b
    82a4:	0000bb1a 	.word	0x0000bb1a
    82a8:	0000a2e8 	.word	0x0000a2e8
    82ac:	0000bb17 	.word	0x0000bb17
    82b0:	20000edc 	.word	0x20000edc
    82b4:	0000a51d 	.word	0x0000a51d
    82b8:	0000a576 	.word	0x0000a576
    82bc:	0000a58b 	.word	0x0000a58b
    82c0:	20000ea0 	.word	0x20000ea0
    82c4:	20000ed0 	.word	0x20000ed0
    82c8:	00007e65 	.word	0x00007e65
    82cc:	0000a54a 	.word	0x0000a54a
    82d0:	0000a561 	.word	0x0000a561
    82d4:	0000bc5f 	.word	0x0000bc5f

000082d8 <z_impl_k_sleep>:

int32_t z_impl_k_sleep(k_timeout_t timeout)
{
    82d8:	b508      	push	{r3, lr}
    82da:	f3ef 8305 	mrs	r3, IPSR
	k_ticks_t ticks;

	__ASSERT(!arch_is_in_isr(), "");
    82de:	b173      	cbz	r3, 82fe <z_impl_k_sleep+0x26>
    82e0:	4912      	ldr	r1, [pc, #72]	; (832c <z_impl_k_sleep+0x54>)
    82e2:	f240 53b7 	movw	r3, #1463	; 0x5b7
    82e6:	4a12      	ldr	r2, [pc, #72]	; (8330 <z_impl_k_sleep+0x58>)
    82e8:	4812      	ldr	r0, [pc, #72]	; (8334 <z_impl_k_sleep+0x5c>)
    82ea:	f000 ffdc 	bl	92a6 <assert_print>
    82ee:	4812      	ldr	r0, [pc, #72]	; (8338 <z_impl_k_sleep+0x60>)
    82f0:	f000 ffd9 	bl	92a6 <assert_print>
    82f4:	f240 51b7 	movw	r1, #1463	; 0x5b7
    82f8:	480d      	ldr	r0, [pc, #52]	; (8330 <z_impl_k_sleep+0x58>)
    82fa:	f000 ffcd 	bl	9298 <assert_post_action>

	SYS_PORT_TRACING_FUNC_ENTER(k_thread, sleep, timeout);

	/* in case of K_FOREVER, we suspend */
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    82fe:	f1b1 3fff 	cmp.w	r1, #4294967295
    8302:	bf08      	it	eq
    8304:	f1b0 3fff 	cmpeq.w	r0, #4294967295
    8308:	d106      	bne.n	8318 <z_impl_k_sleep+0x40>
		k_thread_suspend(_current);
    830a:	4b0c      	ldr	r3, [pc, #48]	; (833c <z_impl_k_sleep+0x64>)
    830c:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    830e:	f7ff fd21 	bl	7d54 <z_impl_k_thread_suspend>

		SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER);

		return (int32_t) K_TICKS_FOREVER;
    8312:	f04f 30ff 	mov.w	r0, #4294967295
	int32_t ret = k_ticks_to_ms_floor64(ticks);

	SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ret);

	return ret;
}
    8316:	bd08      	pop	{r3, pc}
	ticks = z_tick_sleep(ticks);
    8318:	f7ff ff3c 	bl	8194 <z_tick_sleep>
			return ((t * to_hz + off) / from_hz);
    831c:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    8320:	fb80 0303 	smull	r0, r3, r0, r3
    8324:	0bc0      	lsrs	r0, r0, #15
    8326:	ea40 4043 	orr.w	r0, r0, r3, lsl #17
	return ret;
    832a:	e7f4      	b.n	8316 <z_impl_k_sleep+0x3e>
    832c:	0000ba5b 	.word	0x0000ba5b
    8330:	0000bb1a 	.word	0x0000bb1a
    8334:	0000a2e8 	.word	0x0000a2e8
    8338:	0000bb17 	.word	0x0000bb17
    833c:	20000ea0 	.word	0x20000ea0

00008340 <z_impl_z_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    8340:	4b01      	ldr	r3, [pc, #4]	; (8348 <z_impl_z_current_get+0x8>)
    8342:	6898      	ldr	r0, [r3, #8]
    8344:	4770      	bx	lr
    8346:	bf00      	nop
    8348:	20000ea0 	.word	0x20000ea0

0000834c <z_thread_abort>:
#endif
	}
}

void z_thread_abort(struct k_thread *thread)
{
    834c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    8350:	4604      	mov	r4, r0
    8352:	f04f 0320 	mov.w	r3, #32
    8356:	f3ef 8611 	mrs	r6, BASEPRI
    835a:	f383 8812 	msr	BASEPRI_MAX, r3
    835e:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    8362:	4851      	ldr	r0, [pc, #324]	; (84a8 <z_thread_abort+0x15c>)
    8364:	f7fe fd32 	bl	6dcc <z_spin_lock_valid>
    8368:	b968      	cbnz	r0, 8386 <z_thread_abort+0x3a>
    836a:	2394      	movs	r3, #148	; 0x94
    836c:	4a4f      	ldr	r2, [pc, #316]	; (84ac <z_thread_abort+0x160>)
    836e:	4950      	ldr	r1, [pc, #320]	; (84b0 <z_thread_abort+0x164>)
    8370:	4850      	ldr	r0, [pc, #320]	; (84b4 <z_thread_abort+0x168>)
    8372:	f000 ff98 	bl	92a6 <assert_print>
    8376:	494c      	ldr	r1, [pc, #304]	; (84a8 <z_thread_abort+0x15c>)
    8378:	484f      	ldr	r0, [pc, #316]	; (84b8 <z_thread_abort+0x16c>)
    837a:	f000 ff94 	bl	92a6 <assert_print>
    837e:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8380:	484a      	ldr	r0, [pc, #296]	; (84ac <z_thread_abort+0x160>)
    8382:	f000 ff89 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    8386:	4848      	ldr	r0, [pc, #288]	; (84a8 <z_thread_abort+0x15c>)
    8388:	f7fe fd3c 	bl	6e04 <z_spin_lock_set_owner>
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.user_options & K_ESSENTIAL) != 0) {
    838c:	7b23      	ldrb	r3, [r4, #12]
    838e:	07d9      	lsls	r1, r3, #31
    8390:	d522      	bpl.n	83d8 <z_thread_abort+0x8c>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8392:	4845      	ldr	r0, [pc, #276]	; (84a8 <z_thread_abort+0x15c>)
    8394:	f7fe fd28 	bl	6de8 <z_spin_unlock_valid>
    8398:	b958      	cbnz	r0, 83b2 <z_thread_abort+0x66>
    839a:	23c2      	movs	r3, #194	; 0xc2
    839c:	4a43      	ldr	r2, [pc, #268]	; (84ac <z_thread_abort+0x160>)
    839e:	4947      	ldr	r1, [pc, #284]	; (84bc <z_thread_abort+0x170>)
    83a0:	4844      	ldr	r0, [pc, #272]	; (84b4 <z_thread_abort+0x168>)
    83a2:	f000 ff80 	bl	92a6 <assert_print>
    83a6:	4940      	ldr	r1, [pc, #256]	; (84a8 <z_thread_abort+0x15c>)
    83a8:	4845      	ldr	r0, [pc, #276]	; (84c0 <z_thread_abort+0x174>)
    83aa:	f000 ff7c 	bl	92a6 <assert_print>
    83ae:	21c2      	movs	r1, #194	; 0xc2
    83b0:	e7e6      	b.n	8380 <z_thread_abort+0x34>
	__asm__ volatile(
    83b2:	f386 8811 	msr	BASEPRI, r6
    83b6:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&sched_spinlock, key);
		__ASSERT(false, "aborting essential thread %p", thread);
    83ba:	f240 63c3 	movw	r3, #1731	; 0x6c3
    83be:	4a41      	ldr	r2, [pc, #260]	; (84c4 <z_thread_abort+0x178>)
    83c0:	4941      	ldr	r1, [pc, #260]	; (84c8 <z_thread_abort+0x17c>)
    83c2:	483c      	ldr	r0, [pc, #240]	; (84b4 <z_thread_abort+0x168>)
    83c4:	f000 ff6f 	bl	92a6 <assert_print>
    83c8:	4621      	mov	r1, r4
    83ca:	4840      	ldr	r0, [pc, #256]	; (84cc <z_thread_abort+0x180>)
    83cc:	f000 ff6b 	bl	92a6 <assert_print>
    83d0:	f240 61c3 	movw	r1, #1731	; 0x6c3
	}
#endif
	end_thread(thread);
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
    83d4:	483b      	ldr	r0, [pc, #236]	; (84c4 <z_thread_abort+0x178>)
    83d6:	e7d4      	b.n	8382 <z_thread_abort+0x36>
	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    83d8:	7b63      	ldrb	r3, [r4, #13]
    83da:	071a      	lsls	r2, r3, #28
    83dc:	d50a      	bpl.n	83f4 <z_thread_abort+0xa8>
    83de:	4832      	ldr	r0, [pc, #200]	; (84a8 <z_thread_abort+0x15c>)
    83e0:	f7fe fd02 	bl	6de8 <z_spin_unlock_valid>
    83e4:	2800      	cmp	r0, #0
    83e6:	d0d8      	beq.n	839a <z_thread_abort+0x4e>
    83e8:	f386 8811 	msr	BASEPRI, r6
    83ec:	f3bf 8f6f 	isb	sy
	}
	k_spin_unlock(&sched_spinlock, key);
}
    83f0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		thread->base.thread_state &= ~_THREAD_ABORTING;
    83f4:	f023 0220 	bic.w	r2, r3, #32
    83f8:	f042 0108 	orr.w	r1, r2, #8
		if (z_is_thread_queued(thread)) {
    83fc:	09d2      	lsrs	r2, r2, #7
    83fe:	d12c      	bne.n	845a <z_thread_abort+0x10e>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    8400:	7361      	strb	r1, [r4, #13]
		if (thread->base.pended_on != NULL) {
    8402:	68a3      	ldr	r3, [r4, #8]
    8404:	b113      	cbz	r3, 840c <z_thread_abort+0xc0>
			unpend_thread_no_timeout(thread);
    8406:	4620      	mov	r0, r4
    8408:	f7ff fd0c 	bl	7e24 <unpend_thread_no_timeout>
	return z_abort_timeout(&thread->base.timeout);
    840c:	f104 0018 	add.w	r0, r4, #24
    8410:	f000 f992 	bl	8738 <z_abort_timeout>
    8414:	f04f 0800 	mov.w	r8, #0
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    8418:	f104 0758 	add.w	r7, r4, #88	; 0x58
	return list->head == list;
    841c:	6da5      	ldr	r5, [r4, #88]	; 0x58
	return sys_dlist_is_empty(list) ? NULL : list->head;
    841e:	42bd      	cmp	r5, r7
    8420:	d000      	beq.n	8424 <z_thread_abort+0xd8>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    8422:	bb25      	cbnz	r5, 846e <z_thread_abort+0x122>
		update_cache(1);
    8424:	2001      	movs	r0, #1
    8426:	f7fe ff51 	bl	72cc <update_cache>
	if (thread == _current && !arch_is_in_isr()) {
    842a:	4b29      	ldr	r3, [pc, #164]	; (84d0 <z_thread_abort+0x184>)
    842c:	689b      	ldr	r3, [r3, #8]
    842e:	42a3      	cmp	r3, r4
    8430:	d1d5      	bne.n	83de <z_thread_abort+0x92>
    8432:	f3ef 8305 	mrs	r3, IPSR
    8436:	2b00      	cmp	r3, #0
    8438:	d1d1      	bne.n	83de <z_thread_abort+0x92>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    843a:	481b      	ldr	r0, [pc, #108]	; (84a8 <z_thread_abort+0x15c>)
    843c:	f7fe fcd4 	bl	6de8 <z_spin_unlock_valid>
    8440:	bb10      	cbnz	r0, 8488 <z_thread_abort+0x13c>
    8442:	23e1      	movs	r3, #225	; 0xe1
    8444:	4a19      	ldr	r2, [pc, #100]	; (84ac <z_thread_abort+0x160>)
    8446:	491d      	ldr	r1, [pc, #116]	; (84bc <z_thread_abort+0x170>)
    8448:	481a      	ldr	r0, [pc, #104]	; (84b4 <z_thread_abort+0x168>)
    844a:	f000 ff2c 	bl	92a6 <assert_print>
    844e:	4916      	ldr	r1, [pc, #88]	; (84a8 <z_thread_abort+0x15c>)
    8450:	481b      	ldr	r0, [pc, #108]	; (84c0 <z_thread_abort+0x174>)
    8452:	f000 ff28 	bl	92a6 <assert_print>
    8456:	21e1      	movs	r1, #225	; 0xe1
    8458:	e792      	b.n	8380 <z_thread_abort+0x34>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    845a:	f003 035f 	and.w	r3, r3, #95	; 0x5f
    845e:	f043 0308 	orr.w	r3, r3, #8
	_priq_run_remove(thread_runq(thread), thread);
    8462:	4621      	mov	r1, r4
    8464:	481b      	ldr	r0, [pc, #108]	; (84d4 <z_thread_abort+0x188>)
	thread->base.thread_state &= ~_THREAD_QUEUED;
    8466:	7363      	strb	r3, [r4, #13]
	_priq_run_remove(thread_runq(thread), thread);
    8468:	f7ff fa12 	bl	7890 <z_priq_dumb_remove>
}
    846c:	e7c9      	b.n	8402 <z_thread_abort+0xb6>
		unpend_thread_no_timeout(thread);
    846e:	4628      	mov	r0, r5
    8470:	f7ff fcd8 	bl	7e24 <unpend_thread_no_timeout>
    8474:	f105 0018 	add.w	r0, r5, #24
    8478:	f000 f95e 	bl	8738 <z_abort_timeout>
		ready_thread(thread);
    847c:	4628      	mov	r0, r5
    847e:	f8c5 8078 	str.w	r8, [r5, #120]	; 0x78
    8482:	f7fe ff57 	bl	7334 <ready_thread>
    8486:	e7c9      	b.n	841c <z_thread_abort+0xd0>
    8488:	4630      	mov	r0, r6
    848a:	f7fb f8bb 	bl	3604 <arch_swap>
		__ASSERT(false, "aborted _current back from dead");
    848e:	490e      	ldr	r1, [pc, #56]	; (84c8 <z_thread_abort+0x17c>)
    8490:	f240 63f2 	movw	r3, #1778	; 0x6f2
    8494:	4a0b      	ldr	r2, [pc, #44]	; (84c4 <z_thread_abort+0x178>)
    8496:	4807      	ldr	r0, [pc, #28]	; (84b4 <z_thread_abort+0x168>)
    8498:	f000 ff05 	bl	92a6 <assert_print>
    849c:	480e      	ldr	r0, [pc, #56]	; (84d8 <z_thread_abort+0x18c>)
    849e:	f000 ff02 	bl	92a6 <assert_print>
    84a2:	f240 61f2 	movw	r1, #1778	; 0x6f2
    84a6:	e795      	b.n	83d4 <z_thread_abort+0x88>
    84a8:	20000edc 	.word	0x20000edc
    84ac:	0000a51d 	.word	0x0000a51d
    84b0:	0000a576 	.word	0x0000a576
    84b4:	0000a2e8 	.word	0x0000a2e8
    84b8:	0000a58b 	.word	0x0000a58b
    84bc:	0000a54a 	.word	0x0000a54a
    84c0:	0000a561 	.word	0x0000a561
    84c4:	0000bb1a 	.word	0x0000bb1a
    84c8:	0000a5f9 	.word	0x0000a5f9
    84cc:	0000bc9f 	.word	0x0000bc9f
    84d0:	20000ea0 	.word	0x20000ea0
    84d4:	20000ec0 	.word	0x20000ec0
    84d8:	0000bcbe 	.word	0x0000bcbe

000084dc <z_data_copy>:
 * @brief Copy the data section from ROM to RAM
 *
 * This routine copies the data section from ROM to RAM.
 */
void z_data_copy(void)
{
    84dc:	b508      	push	{r3, lr}
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
		       __data_region_end - __data_region_start);
    84de:	4806      	ldr	r0, [pc, #24]	; (84f8 <z_data_copy+0x1c>)
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
    84e0:	4a06      	ldr	r2, [pc, #24]	; (84fc <z_data_copy+0x20>)
    84e2:	4907      	ldr	r1, [pc, #28]	; (8500 <z_data_copy+0x24>)
    84e4:	1a12      	subs	r2, r2, r0
    84e6:	f001 fb24 	bl	9b32 <z_early_memcpy>
#else
	z_early_memcpy(&_app_smem_start, &_app_smem_rom_start,
		       _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    84ea:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_early_memcpy(&__ramfunc_start, &__ramfunc_load_start,
    84ee:	4a05      	ldr	r2, [pc, #20]	; (8504 <z_data_copy+0x28>)
    84f0:	4905      	ldr	r1, [pc, #20]	; (8508 <z_data_copy+0x2c>)
    84f2:	4806      	ldr	r0, [pc, #24]	; (850c <z_data_copy+0x30>)
    84f4:	f001 bb1d 	b.w	9b32 <z_early_memcpy>
    84f8:	20000000 	.word	0x20000000
    84fc:	200001ec 	.word	0x200001ec
    8500:	0000bd24 	.word	0x0000bd24
    8504:	00000000 	.word	0x00000000
    8508:	0000bd24 	.word	0x0000bd24
    850c:	20000000 	.word	0x20000000

00008510 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    8510:	4b03      	ldr	r3, [pc, #12]	; (8520 <elapsed+0x10>)
    8512:	681b      	ldr	r3, [r3, #0]
    8514:	b90b      	cbnz	r3, 851a <elapsed+0xa>
    8516:	f7fc bfb9 	b.w	548c <sys_clock_elapsed>
}
    851a:	2000      	movs	r0, #0
    851c:	4770      	bx	lr
    851e:	bf00      	nop
    8520:	20000ee0 	.word	0x20000ee0

00008524 <next_timeout>:

static int32_t next_timeout(void)
{
    8524:	b510      	push	{r4, lr}
	return list->head == list;
    8526:	4b11      	ldr	r3, [pc, #68]	; (856c <next_timeout+0x48>)
    8528:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    852a:	429c      	cmp	r4, r3
    852c:	d10a      	bne.n	8544 <next_timeout+0x20>
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    852e:	f7ff ffef 	bl	8510 <elapsed>
	int32_t ret;

	if ((to == NULL) ||
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
		ret = MAX_WAIT;
    8532:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
	} else {
		ret = MAX(0, to->dticks - ticks_elapsed);
	}

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    8536:	4b0e      	ldr	r3, [pc, #56]	; (8570 <next_timeout+0x4c>)
    8538:	691b      	ldr	r3, [r3, #16]
    853a:	b113      	cbz	r3, 8542 <next_timeout+0x1e>
    853c:	4298      	cmp	r0, r3
    853e:	bfa8      	it	ge
    8540:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    8542:	bd10      	pop	{r4, pc}
	int32_t ticks_elapsed = elapsed();
    8544:	f7ff ffe4 	bl	8510 <elapsed>
	if ((to == NULL) ||
    8548:	2c00      	cmp	r4, #0
    854a:	d0f2      	beq.n	8532 <next_timeout+0xe>
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
    854c:	e9d4 3204 	ldrd	r3, r2, [r4, #16]
    8550:	1a1b      	subs	r3, r3, r0
    8552:	eb62 72e0 	sbc.w	r2, r2, r0, asr #31
	if ((to == NULL) ||
    8556:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    855a:	f172 0100 	sbcs.w	r1, r2, #0
    855e:	dae8      	bge.n	8532 <next_timeout+0xe>
		ret = MAX(0, to->dticks - ticks_elapsed);
    8560:	2a00      	cmp	r2, #0
    8562:	bfac      	ite	ge
    8564:	4618      	movge	r0, r3
    8566:	2000      	movlt	r0, #0
    8568:	e7e5      	b.n	8536 <next_timeout+0x12>
    856a:	bf00      	nop
    856c:	200000d8 	.word	0x200000d8
    8570:	20000ea0 	.word	0x20000ea0

00008574 <remove_timeout>:
{
    8574:	b530      	push	{r4, r5, lr}
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    8576:	b170      	cbz	r0, 8596 <remove_timeout+0x22>
	return (node == list->tail) ? NULL : node->next;
    8578:	4b0b      	ldr	r3, [pc, #44]	; (85a8 <remove_timeout+0x34>)
    857a:	685b      	ldr	r3, [r3, #4]
    857c:	4298      	cmp	r0, r3
    857e:	d00a      	beq.n	8596 <remove_timeout+0x22>
    8580:	6803      	ldr	r3, [r0, #0]
	if (next(t) != NULL) {
    8582:	b143      	cbz	r3, 8596 <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    8584:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    8588:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    858c:	1912      	adds	r2, r2, r4
    858e:	eb41 0105 	adc.w	r1, r1, r5
    8592:	e9c3 2104 	strd	r2, r1, [r3, #16]
	sys_dnode_t *const next = node->next;
    8596:	e9d0 3200 	ldrd	r3, r2, [r0]
	prev->next = next;
    859a:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    859c:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    859e:	2300      	movs	r3, #0
	node->prev = NULL;
    85a0:	e9c0 3300 	strd	r3, r3, [r0]
}
    85a4:	bd30      	pop	{r4, r5, pc}
    85a6:	bf00      	nop
    85a8:	200000d8 	.word	0x200000d8

000085ac <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    85ac:	f1b3 3fff 	cmp.w	r3, #4294967295
    85b0:	bf08      	it	eq
    85b2:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    85b6:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    85ba:	4604      	mov	r4, r0
    85bc:	4692      	mov	sl, r2
    85be:	461d      	mov	r5, r3
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    85c0:	f000 809e 	beq.w	8700 <z_add_timeout+0x154>
	return node->next != NULL;
    85c4:	6806      	ldr	r6, [r0, #0]

#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
    85c6:	b166      	cbz	r6, 85e2 <z_add_timeout+0x36>
    85c8:	494e      	ldr	r1, [pc, #312]	; (8704 <z_add_timeout+0x158>)
    85ca:	2363      	movs	r3, #99	; 0x63
    85cc:	4a4e      	ldr	r2, [pc, #312]	; (8708 <z_add_timeout+0x15c>)
    85ce:	484f      	ldr	r0, [pc, #316]	; (870c <z_add_timeout+0x160>)
    85d0:	f000 fe69 	bl	92a6 <assert_print>
    85d4:	484e      	ldr	r0, [pc, #312]	; (8710 <z_add_timeout+0x164>)
    85d6:	f000 fe66 	bl	92a6 <assert_print>
    85da:	2163      	movs	r1, #99	; 0x63
    85dc:	484a      	ldr	r0, [pc, #296]	; (8708 <z_add_timeout+0x15c>)
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    85de:	f000 fe5b 	bl	9298 <assert_post_action>
	to->fn = fn;
    85e2:	6081      	str	r1, [r0, #8]
	__asm__ volatile(
    85e4:	f04f 0320 	mov.w	r3, #32
    85e8:	f3ef 8711 	mrs	r7, BASEPRI
    85ec:	f383 8812 	msr	BASEPRI_MAX, r3
    85f0:	f3bf 8f6f 	isb	sy
    85f4:	4847      	ldr	r0, [pc, #284]	; (8714 <z_add_timeout+0x168>)
    85f6:	f7fe fbe9 	bl	6dcc <z_spin_lock_valid>
    85fa:	b960      	cbnz	r0, 8616 <z_add_timeout+0x6a>
    85fc:	2394      	movs	r3, #148	; 0x94
    85fe:	4a46      	ldr	r2, [pc, #280]	; (8718 <z_add_timeout+0x16c>)
    8600:	4946      	ldr	r1, [pc, #280]	; (871c <z_add_timeout+0x170>)
    8602:	4842      	ldr	r0, [pc, #264]	; (870c <z_add_timeout+0x160>)
    8604:	f000 fe4f 	bl	92a6 <assert_print>
    8608:	4942      	ldr	r1, [pc, #264]	; (8714 <z_add_timeout+0x168>)
    860a:	4845      	ldr	r0, [pc, #276]	; (8720 <z_add_timeout+0x174>)
    860c:	f000 fe4b 	bl	92a6 <assert_print>
    8610:	2194      	movs	r1, #148	; 0x94
    8612:	4841      	ldr	r0, [pc, #260]	; (8718 <z_add_timeout+0x16c>)
    8614:	e7e3      	b.n	85de <z_add_timeout+0x32>
	z_spin_lock_set_owner(l);
    8616:	483f      	ldr	r0, [pc, #252]	; (8714 <z_add_timeout+0x168>)
    8618:	f7fe fbf4 	bl	6e04 <z_spin_lock_set_owner>

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    861c:	f1ba 3fff 	cmp.w	sl, #4294967295
    8620:	f175 33ff 	sbcs.w	r3, r5, #4294967295
    8624:	da23      	bge.n	866e <z_add_timeout+0xc2>
		    Z_TICK_ABS(timeout.ticks) >= 0) {
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    8626:	f06f 0301 	mvn.w	r3, #1
    862a:	493e      	ldr	r1, [pc, #248]	; (8724 <z_add_timeout+0x178>)
    862c:	e9d1 2000 	ldrd	r2, r0, [r1]
    8630:	1a9b      	subs	r3, r3, r2
    8632:	f04f 32ff 	mov.w	r2, #4294967295
    8636:	eb62 0000 	sbc.w	r0, r2, r0
    863a:	ebb3 030a 	subs.w	r3, r3, sl
    863e:	eb60 0005 	sbc.w	r0, r0, r5

			to->dticks = MAX(1, ticks);
    8642:	2b01      	cmp	r3, #1
    8644:	f170 0200 	sbcs.w	r2, r0, #0
    8648:	da01      	bge.n	864e <z_add_timeout+0xa2>
    864a:	2301      	movs	r3, #1
    864c:	4630      	mov	r0, r6
    864e:	e9c4 3004 	strd	r3, r0, [r4, #16]
	return list->head == list;
    8652:	4b35      	ldr	r3, [pc, #212]	; (8728 <z_add_timeout+0x17c>)
    8654:	681a      	ldr	r2, [r3, #0]
	return (node == list->tail) ? NULL : node->next;
    8656:	f8d3 c004 	ldr.w	ip, [r3, #4]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    865a:	429a      	cmp	r2, r3
    865c:	bf18      	it	ne
    865e:	4616      	movne	r6, r2
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
		}

		for (t = first(); t != NULL; t = next(t)) {
    8660:	b986      	cbnz	r6, 8684 <z_add_timeout+0xd8>
	node->prev = tail;
    8662:	e9c4 3c00 	strd	r3, ip, [r4]
	tail->next = node;
    8666:	f8cc 4000 	str.w	r4, [ip]
	list->tail = node;
    866a:	605c      	str	r4, [r3, #4]
}
    866c:	e01c      	b.n	86a8 <z_add_timeout+0xfc>
			to->dticks = timeout.ticks + 1 + elapsed();
    866e:	f7ff ff4f 	bl	8510 <elapsed>
    8672:	f11a 0801 	adds.w	r8, sl, #1
    8676:	f145 0500 	adc.w	r5, r5, #0
    867a:	eb18 0300 	adds.w	r3, r8, r0
    867e:	eb45 70e0 	adc.w	r0, r5, r0, asr #31
    8682:	e7e4      	b.n	864e <z_add_timeout+0xa2>
			if (t->dticks > to->dticks) {
    8684:	e9d6 1504 	ldrd	r1, r5, [r6, #16]
    8688:	e9d4 2004 	ldrd	r2, r0, [r4, #16]
    868c:	428a      	cmp	r2, r1
    868e:	eb70 0e05 	sbcs.w	lr, r0, r5
    8692:	da28      	bge.n	86e6 <z_add_timeout+0x13a>
				t->dticks -= to->dticks;
    8694:	1a89      	subs	r1, r1, r2
	sys_dnode_t *const prev = successor->prev;
    8696:	6872      	ldr	r2, [r6, #4]
    8698:	eb65 0500 	sbc.w	r5, r5, r0
    869c:	e9c6 1504 	strd	r1, r5, [r6, #16]
	node->next = successor;
    86a0:	e9c4 6200 	strd	r6, r2, [r4]
	prev->next = node;
    86a4:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    86a6:	6074      	str	r4, [r6, #4]
	return list->head == list;
    86a8:	681a      	ldr	r2, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    86aa:	429a      	cmp	r2, r3
    86ac:	d00b      	beq.n	86c6 <z_add_timeout+0x11a>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    86ae:	4294      	cmp	r4, r2
    86b0:	d109      	bne.n	86c6 <z_add_timeout+0x11a>
			 * last announcement, and slice_ticks is based
			 * on that. It means that the time remaining for
			 * the next announcement can be less than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    86b2:	f7ff ff37 	bl	8524 <next_timeout>

			if (next_time == 0 ||
    86b6:	b118      	cbz	r0, 86c0 <z_add_timeout+0x114>
			    _current_cpu->slice_ticks != next_time) {
    86b8:	4b1c      	ldr	r3, [pc, #112]	; (872c <z_add_timeout+0x180>)
			if (next_time == 0 ||
    86ba:	691b      	ldr	r3, [r3, #16]
    86bc:	4283      	cmp	r3, r0
    86be:	d002      	beq.n	86c6 <z_add_timeout+0x11a>
				sys_clock_set_timeout(next_time, false);
    86c0:	2100      	movs	r1, #0
    86c2:	f7fc feb1 	bl	5428 <sys_clock_set_timeout>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    86c6:	4813      	ldr	r0, [pc, #76]	; (8714 <z_add_timeout+0x168>)
    86c8:	f7fe fb8e 	bl	6de8 <z_spin_unlock_valid>
    86cc:	b9a0      	cbnz	r0, 86f8 <z_add_timeout+0x14c>
    86ce:	23c2      	movs	r3, #194	; 0xc2
    86d0:	4a11      	ldr	r2, [pc, #68]	; (8718 <z_add_timeout+0x16c>)
    86d2:	4917      	ldr	r1, [pc, #92]	; (8730 <z_add_timeout+0x184>)
    86d4:	480d      	ldr	r0, [pc, #52]	; (870c <z_add_timeout+0x160>)
    86d6:	f000 fde6 	bl	92a6 <assert_print>
    86da:	490e      	ldr	r1, [pc, #56]	; (8714 <z_add_timeout+0x168>)
    86dc:	4815      	ldr	r0, [pc, #84]	; (8734 <z_add_timeout+0x188>)
    86de:	f000 fde2 	bl	92a6 <assert_print>
    86e2:	21c2      	movs	r1, #194	; 0xc2
    86e4:	e795      	b.n	8612 <z_add_timeout+0x66>
			to->dticks -= t->dticks;
    86e6:	1a52      	subs	r2, r2, r1
    86e8:	eb60 0005 	sbc.w	r0, r0, r5
	return (node == list->tail) ? NULL : node->next;
    86ec:	4566      	cmp	r6, ip
    86ee:	e9c4 2004 	strd	r2, r0, [r4, #16]
    86f2:	d0b6      	beq.n	8662 <z_add_timeout+0xb6>
    86f4:	6836      	ldr	r6, [r6, #0]
    86f6:	e7b3      	b.n	8660 <z_add_timeout+0xb4>
	__asm__ volatile(
    86f8:	f387 8811 	msr	BASEPRI, r7
    86fc:	f3bf 8f6f 	isb	sy
#else
			sys_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    8700:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    8704:	0000bd04 	.word	0x0000bd04
    8708:	0000bce0 	.word	0x0000bce0
    870c:	0000a2e8 	.word	0x0000a2e8
    8710:	0000bb17 	.word	0x0000bb17
    8714:	20000ee4 	.word	0x20000ee4
    8718:	0000a51d 	.word	0x0000a51d
    871c:	0000a576 	.word	0x0000a576
    8720:	0000a58b 	.word	0x0000a58b
    8724:	20000760 	.word	0x20000760
    8728:	200000d8 	.word	0x200000d8
    872c:	20000ea0 	.word	0x20000ea0
    8730:	0000a54a 	.word	0x0000a54a
    8734:	0000a561 	.word	0x0000a561

00008738 <z_abort_timeout>:

int z_abort_timeout(struct _timeout *to)
{
    8738:	b538      	push	{r3, r4, r5, lr}
    873a:	4604      	mov	r4, r0
	__asm__ volatile(
    873c:	f04f 0320 	mov.w	r3, #32
    8740:	f3ef 8511 	mrs	r5, BASEPRI
    8744:	f383 8812 	msr	BASEPRI_MAX, r3
    8748:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    874c:	4819      	ldr	r0, [pc, #100]	; (87b4 <z_abort_timeout+0x7c>)
    874e:	f7fe fb3d 	bl	6dcc <z_spin_lock_valid>
    8752:	b968      	cbnz	r0, 8770 <z_abort_timeout+0x38>
    8754:	2394      	movs	r3, #148	; 0x94
    8756:	4a18      	ldr	r2, [pc, #96]	; (87b8 <z_abort_timeout+0x80>)
    8758:	4918      	ldr	r1, [pc, #96]	; (87bc <z_abort_timeout+0x84>)
    875a:	4819      	ldr	r0, [pc, #100]	; (87c0 <z_abort_timeout+0x88>)
    875c:	f000 fda3 	bl	92a6 <assert_print>
    8760:	4914      	ldr	r1, [pc, #80]	; (87b4 <z_abort_timeout+0x7c>)
    8762:	4818      	ldr	r0, [pc, #96]	; (87c4 <z_abort_timeout+0x8c>)
    8764:	f000 fd9f 	bl	92a6 <assert_print>
    8768:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    876a:	4813      	ldr	r0, [pc, #76]	; (87b8 <z_abort_timeout+0x80>)
    876c:	f000 fd94 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    8770:	4810      	ldr	r0, [pc, #64]	; (87b4 <z_abort_timeout+0x7c>)
    8772:	f7fe fb47 	bl	6e04 <z_spin_lock_set_owner>
	int ret = -EINVAL;

	LOCKED(&timeout_lock) {
		if (sys_dnode_is_linked(&to->node)) {
    8776:	6823      	ldr	r3, [r4, #0]
    8778:	b19b      	cbz	r3, 87a2 <z_abort_timeout+0x6a>
			remove_timeout(to);
    877a:	4620      	mov	r0, r4
    877c:	f7ff fefa 	bl	8574 <remove_timeout>
			ret = 0;
    8780:	2400      	movs	r4, #0
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8782:	480c      	ldr	r0, [pc, #48]	; (87b4 <z_abort_timeout+0x7c>)
    8784:	f7fe fb30 	bl	6de8 <z_spin_unlock_valid>
    8788:	b970      	cbnz	r0, 87a8 <z_abort_timeout+0x70>
    878a:	23c2      	movs	r3, #194	; 0xc2
    878c:	4a0a      	ldr	r2, [pc, #40]	; (87b8 <z_abort_timeout+0x80>)
    878e:	490e      	ldr	r1, [pc, #56]	; (87c8 <z_abort_timeout+0x90>)
    8790:	480b      	ldr	r0, [pc, #44]	; (87c0 <z_abort_timeout+0x88>)
    8792:	f000 fd88 	bl	92a6 <assert_print>
    8796:	4907      	ldr	r1, [pc, #28]	; (87b4 <z_abort_timeout+0x7c>)
    8798:	480c      	ldr	r0, [pc, #48]	; (87cc <z_abort_timeout+0x94>)
    879a:	f000 fd84 	bl	92a6 <assert_print>
    879e:	21c2      	movs	r1, #194	; 0xc2
    87a0:	e7e3      	b.n	876a <z_abort_timeout+0x32>
	int ret = -EINVAL;
    87a2:	f06f 0415 	mvn.w	r4, #21
    87a6:	e7ec      	b.n	8782 <z_abort_timeout+0x4a>
	__asm__ volatile(
    87a8:	f385 8811 	msr	BASEPRI, r5
    87ac:	f3bf 8f6f 	isb	sy
		}
	}

	return ret;
}
    87b0:	4620      	mov	r0, r4
    87b2:	bd38      	pop	{r3, r4, r5, pc}
    87b4:	20000ee4 	.word	0x20000ee4
    87b8:	0000a51d 	.word	0x0000a51d
    87bc:	0000a576 	.word	0x0000a576
    87c0:	0000a2e8 	.word	0x0000a2e8
    87c4:	0000a58b 	.word	0x0000a58b
    87c8:	0000a54a 	.word	0x0000a54a
    87cc:	0000a561 	.word	0x0000a561

000087d0 <z_get_next_timeout_expiry>:

	return ticks;
}

int32_t z_get_next_timeout_expiry(void)
{
    87d0:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    87d2:	f04f 0320 	mov.w	r3, #32
    87d6:	f3ef 8511 	mrs	r5, BASEPRI
    87da:	f383 8812 	msr	BASEPRI_MAX, r3
    87de:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    87e2:	4817      	ldr	r0, [pc, #92]	; (8840 <z_get_next_timeout_expiry+0x70>)
    87e4:	f7fe faf2 	bl	6dcc <z_spin_lock_valid>
    87e8:	b968      	cbnz	r0, 8806 <z_get_next_timeout_expiry+0x36>
    87ea:	2394      	movs	r3, #148	; 0x94
    87ec:	4a15      	ldr	r2, [pc, #84]	; (8844 <z_get_next_timeout_expiry+0x74>)
    87ee:	4916      	ldr	r1, [pc, #88]	; (8848 <z_get_next_timeout_expiry+0x78>)
    87f0:	4816      	ldr	r0, [pc, #88]	; (884c <z_get_next_timeout_expiry+0x7c>)
    87f2:	f000 fd58 	bl	92a6 <assert_print>
    87f6:	4912      	ldr	r1, [pc, #72]	; (8840 <z_get_next_timeout_expiry+0x70>)
    87f8:	4815      	ldr	r0, [pc, #84]	; (8850 <z_get_next_timeout_expiry+0x80>)
    87fa:	f000 fd54 	bl	92a6 <assert_print>
    87fe:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8800:	4810      	ldr	r0, [pc, #64]	; (8844 <z_get_next_timeout_expiry+0x74>)
    8802:	f000 fd49 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    8806:	480e      	ldr	r0, [pc, #56]	; (8840 <z_get_next_timeout_expiry+0x70>)
    8808:	f7fe fafc 	bl	6e04 <z_spin_lock_set_owner>
	int32_t ret = (int32_t) K_TICKS_FOREVER;

	LOCKED(&timeout_lock) {
		ret = next_timeout();
    880c:	f7ff fe8a 	bl	8524 <next_timeout>
    8810:	4604      	mov	r4, r0
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8812:	480b      	ldr	r0, [pc, #44]	; (8840 <z_get_next_timeout_expiry+0x70>)
    8814:	f7fe fae8 	bl	6de8 <z_spin_unlock_valid>
    8818:	b958      	cbnz	r0, 8832 <z_get_next_timeout_expiry+0x62>
    881a:	23c2      	movs	r3, #194	; 0xc2
    881c:	4a09      	ldr	r2, [pc, #36]	; (8844 <z_get_next_timeout_expiry+0x74>)
    881e:	490d      	ldr	r1, [pc, #52]	; (8854 <z_get_next_timeout_expiry+0x84>)
    8820:	480a      	ldr	r0, [pc, #40]	; (884c <z_get_next_timeout_expiry+0x7c>)
    8822:	f000 fd40 	bl	92a6 <assert_print>
    8826:	4906      	ldr	r1, [pc, #24]	; (8840 <z_get_next_timeout_expiry+0x70>)
    8828:	480b      	ldr	r0, [pc, #44]	; (8858 <z_get_next_timeout_expiry+0x88>)
    882a:	f000 fd3c 	bl	92a6 <assert_print>
    882e:	21c2      	movs	r1, #194	; 0xc2
    8830:	e7e6      	b.n	8800 <z_get_next_timeout_expiry+0x30>
	__asm__ volatile(
    8832:	f385 8811 	msr	BASEPRI, r5
    8836:	f3bf 8f6f 	isb	sy
	}
	return ret;
}
    883a:	4620      	mov	r0, r4
    883c:	bd38      	pop	{r3, r4, r5, pc}
    883e:	bf00      	nop
    8840:	20000ee4 	.word	0x20000ee4
    8844:	0000a51d 	.word	0x0000a51d
    8848:	0000a576 	.word	0x0000a576
    884c:	0000a2e8 	.word	0x0000a2e8
    8850:	0000a58b 	.word	0x0000a58b
    8854:	0000a54a 	.word	0x0000a54a
    8858:	0000a561 	.word	0x0000a561

0000885c <z_set_timeout_expiry>:

void z_set_timeout_expiry(int32_t ticks, bool is_idle)
{
    885c:	b570      	push	{r4, r5, r6, lr}
    885e:	4604      	mov	r4, r0
    8860:	460d      	mov	r5, r1
	__asm__ volatile(
    8862:	f04f 0320 	mov.w	r3, #32
    8866:	f3ef 8611 	mrs	r6, BASEPRI
    886a:	f383 8812 	msr	BASEPRI_MAX, r3
    886e:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    8872:	481b      	ldr	r0, [pc, #108]	; (88e0 <z_set_timeout_expiry+0x84>)
    8874:	f7fe faaa 	bl	6dcc <z_spin_lock_valid>
    8878:	b968      	cbnz	r0, 8896 <z_set_timeout_expiry+0x3a>
    887a:	2394      	movs	r3, #148	; 0x94
    887c:	4a19      	ldr	r2, [pc, #100]	; (88e4 <z_set_timeout_expiry+0x88>)
    887e:	491a      	ldr	r1, [pc, #104]	; (88e8 <z_set_timeout_expiry+0x8c>)
    8880:	481a      	ldr	r0, [pc, #104]	; (88ec <z_set_timeout_expiry+0x90>)
    8882:	f000 fd10 	bl	92a6 <assert_print>
    8886:	4916      	ldr	r1, [pc, #88]	; (88e0 <z_set_timeout_expiry+0x84>)
    8888:	4819      	ldr	r0, [pc, #100]	; (88f0 <z_set_timeout_expiry+0x94>)
    888a:	f000 fd0c 	bl	92a6 <assert_print>
    888e:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8890:	4814      	ldr	r0, [pc, #80]	; (88e4 <z_set_timeout_expiry+0x88>)
    8892:	f000 fd01 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    8896:	4812      	ldr	r0, [pc, #72]	; (88e0 <z_set_timeout_expiry+0x84>)
    8898:	f7fe fab4 	bl	6e04 <z_spin_lock_set_owner>
	LOCKED(&timeout_lock) {
		int next_to = next_timeout();
    889c:	f7ff fe42 	bl	8524 <next_timeout>
		bool sooner = (next_to == K_TICKS_FOREVER)
			      || (ticks <= next_to);
    88a0:	2801      	cmp	r0, #1
    88a2:	dd07      	ble.n	88b4 <z_set_timeout_expiry+0x58>
    88a4:	42a0      	cmp	r0, r4
    88a6:	db05      	blt.n	88b4 <z_set_timeout_expiry+0x58>
		 * know when context switches happen until interrupt
		 * exit and so can't get the timeslicing clamp folded
		 * in.
		 */
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
			sys_clock_set_timeout(MIN(ticks, next_to), is_idle);
    88a8:	42a0      	cmp	r0, r4
    88aa:	4629      	mov	r1, r5
    88ac:	bfa8      	it	ge
    88ae:	4620      	movge	r0, r4
    88b0:	f7fc fdba 	bl	5428 <sys_clock_set_timeout>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    88b4:	480a      	ldr	r0, [pc, #40]	; (88e0 <z_set_timeout_expiry+0x84>)
    88b6:	f7fe fa97 	bl	6de8 <z_spin_unlock_valid>
    88ba:	b958      	cbnz	r0, 88d4 <z_set_timeout_expiry+0x78>
    88bc:	23c2      	movs	r3, #194	; 0xc2
    88be:	4a09      	ldr	r2, [pc, #36]	; (88e4 <z_set_timeout_expiry+0x88>)
    88c0:	490c      	ldr	r1, [pc, #48]	; (88f4 <z_set_timeout_expiry+0x98>)
    88c2:	480a      	ldr	r0, [pc, #40]	; (88ec <z_set_timeout_expiry+0x90>)
    88c4:	f000 fcef 	bl	92a6 <assert_print>
    88c8:	4905      	ldr	r1, [pc, #20]	; (88e0 <z_set_timeout_expiry+0x84>)
    88ca:	480b      	ldr	r0, [pc, #44]	; (88f8 <z_set_timeout_expiry+0x9c>)
    88cc:	f000 fceb 	bl	92a6 <assert_print>
    88d0:	21c2      	movs	r1, #194	; 0xc2
    88d2:	e7dd      	b.n	8890 <z_set_timeout_expiry+0x34>
	__asm__ volatile(
    88d4:	f386 8811 	msr	BASEPRI, r6
    88d8:	f3bf 8f6f 	isb	sy
		}
	}
}
    88dc:	bd70      	pop	{r4, r5, r6, pc}
    88de:	bf00      	nop
    88e0:	20000ee4 	.word	0x20000ee4
    88e4:	0000a51d 	.word	0x0000a51d
    88e8:	0000a576 	.word	0x0000a576
    88ec:	0000a2e8 	.word	0x0000a2e8
    88f0:	0000a58b 	.word	0x0000a58b
    88f4:	0000a54a 	.word	0x0000a54a
    88f8:	0000a561 	.word	0x0000a561

000088fc <sys_clock_announce>:

void sys_clock_announce(int32_t ticks)
{
    88fc:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    8900:	4604      	mov	r4, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    8902:	f7ff f837 	bl	7974 <z_time_slice>
	__asm__ volatile(
    8906:	f04f 0320 	mov.w	r3, #32
    890a:	f3ef 8711 	mrs	r7, BASEPRI
    890e:	f383 8812 	msr	BASEPRI_MAX, r3
    8912:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    8916:	483f      	ldr	r0, [pc, #252]	; (8a14 <sys_clock_announce+0x118>)
    8918:	f7fe fa58 	bl	6dcc <z_spin_lock_valid>
    891c:	b968      	cbnz	r0, 893a <sys_clock_announce+0x3e>
    891e:	2394      	movs	r3, #148	; 0x94
    8920:	4a3d      	ldr	r2, [pc, #244]	; (8a18 <sys_clock_announce+0x11c>)
    8922:	493e      	ldr	r1, [pc, #248]	; (8a1c <sys_clock_announce+0x120>)
    8924:	483e      	ldr	r0, [pc, #248]	; (8a20 <sys_clock_announce+0x124>)
    8926:	f000 fcbe 	bl	92a6 <assert_print>
    892a:	493a      	ldr	r1, [pc, #232]	; (8a14 <sys_clock_announce+0x118>)
    892c:	483d      	ldr	r0, [pc, #244]	; (8a24 <sys_clock_announce+0x128>)
    892e:	f000 fcba 	bl	92a6 <assert_print>
    8932:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8934:	4838      	ldr	r0, [pc, #224]	; (8a18 <sys_clock_announce+0x11c>)
    8936:	f000 fcaf 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    893a:	4836      	ldr	r0, [pc, #216]	; (8a14 <sys_clock_announce+0x118>)
    893c:	f7fe fa62 	bl	6e04 <z_spin_lock_set_owner>
		announce_remaining += ticks;
		k_spin_unlock(&timeout_lock, key);
		return;
	}

	announce_remaining = ticks;
    8940:	f8df 80e4 	ldr.w	r8, [pc, #228]	; 8a28 <sys_clock_announce+0x12c>
	return list->head == list;
    8944:	f8df 90e4 	ldr.w	r9, [pc, #228]	; 8a2c <sys_clock_announce+0x130>
    8948:	f8d9 5000 	ldr.w	r5, [r9]

	while (first() != NULL && first()->dticks <= announce_remaining) {
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    894c:	4a38      	ldr	r2, [pc, #224]	; (8a30 <sys_clock_announce+0x134>)
	return sys_dlist_is_empty(list) ? NULL : list->head;
    894e:	454d      	cmp	r5, r9
	announce_remaining = ticks;
    8950:	f8c8 4000 	str.w	r4, [r8]
	return list->head == list;
    8954:	ea4f 71e4 	mov.w	r1, r4, asr #31
		curr_tick += dt;
    8958:	e9d2 3c00 	ldrd	r3, ip, [r2]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    895c:	d00b      	beq.n	8976 <sys_clock_announce+0x7a>
	while (first() != NULL && first()->dticks <= announce_remaining) {
    895e:	b155      	cbz	r5, 8976 <sys_clock_announce+0x7a>
    8960:	e9d5 6004 	ldrd	r6, r0, [r5, #16]
    8964:	42b4      	cmp	r4, r6
    8966:	eb71 0e00 	sbcs.w	lr, r1, r0
    896a:	da1c      	bge.n	89a6 <sys_clock_announce+0xaa>
		key = k_spin_lock(&timeout_lock);
		announce_remaining -= dt;
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    896c:	1b36      	subs	r6, r6, r4
    896e:	eb60 0001 	sbc.w	r0, r0, r1
    8972:	e9c5 6004 	strd	r6, r0, [r5, #16]
	}

	curr_tick += announce_remaining;
    8976:	18e3      	adds	r3, r4, r3
	announce_remaining = 0;
    8978:	f04f 0400 	mov.w	r4, #0
	curr_tick += announce_remaining;
    897c:	eb4c 0101 	adc.w	r1, ip, r1
    8980:	e9c2 3100 	strd	r3, r1, [r2]
	announce_remaining = 0;
    8984:	f8c8 4000 	str.w	r4, [r8]

	sys_clock_set_timeout(next_timeout(), false);
    8988:	f7ff fdcc 	bl	8524 <next_timeout>
    898c:	4621      	mov	r1, r4
    898e:	f7fc fd4b 	bl	5428 <sys_clock_set_timeout>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8992:	4820      	ldr	r0, [pc, #128]	; (8a14 <sys_clock_announce+0x118>)
    8994:	f7fe fa28 	bl	6de8 <z_spin_unlock_valid>
    8998:	b1a8      	cbz	r0, 89c6 <sys_clock_announce+0xca>
	__asm__ volatile(
    899a:	f387 8811 	msr	BASEPRI, r7
    899e:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    89a2:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		curr_tick += dt;
    89a6:	18f3      	adds	r3, r6, r3
    89a8:	eb4c 71e6 	adc.w	r1, ip, r6, asr #31
    89ac:	e9c2 3100 	strd	r3, r1, [r2]
		t->dticks = 0;
    89b0:	2200      	movs	r2, #0
    89b2:	2300      	movs	r3, #0
		remove_timeout(t);
    89b4:	4628      	mov	r0, r5
		t->dticks = 0;
    89b6:	e9c5 2304 	strd	r2, r3, [r5, #16]
		remove_timeout(t);
    89ba:	f7ff fddb 	bl	8574 <remove_timeout>
    89be:	4815      	ldr	r0, [pc, #84]	; (8a14 <sys_clock_announce+0x118>)
    89c0:	f7fe fa12 	bl	6de8 <z_spin_unlock_valid>
    89c4:	b958      	cbnz	r0, 89de <sys_clock_announce+0xe2>
    89c6:	23c2      	movs	r3, #194	; 0xc2
    89c8:	4a13      	ldr	r2, [pc, #76]	; (8a18 <sys_clock_announce+0x11c>)
    89ca:	491a      	ldr	r1, [pc, #104]	; (8a34 <sys_clock_announce+0x138>)
    89cc:	4814      	ldr	r0, [pc, #80]	; (8a20 <sys_clock_announce+0x124>)
    89ce:	f000 fc6a 	bl	92a6 <assert_print>
    89d2:	4910      	ldr	r1, [pc, #64]	; (8a14 <sys_clock_announce+0x118>)
    89d4:	4818      	ldr	r0, [pc, #96]	; (8a38 <sys_clock_announce+0x13c>)
    89d6:	f000 fc66 	bl	92a6 <assert_print>
    89da:	21c2      	movs	r1, #194	; 0xc2
    89dc:	e7aa      	b.n	8934 <sys_clock_announce+0x38>
    89de:	f387 8811 	msr	BASEPRI, r7
    89e2:	f3bf 8f6f 	isb	sy
		t->fn(t);
    89e6:	4628      	mov	r0, r5
    89e8:	68ab      	ldr	r3, [r5, #8]
    89ea:	4798      	blx	r3
	__asm__ volatile(
    89ec:	f04f 0320 	mov.w	r3, #32
    89f0:	f3ef 8711 	mrs	r7, BASEPRI
    89f4:	f383 8812 	msr	BASEPRI_MAX, r3
    89f8:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    89fc:	4805      	ldr	r0, [pc, #20]	; (8a14 <sys_clock_announce+0x118>)
    89fe:	f7fe f9e5 	bl	6dcc <z_spin_lock_valid>
    8a02:	2800      	cmp	r0, #0
    8a04:	d08b      	beq.n	891e <sys_clock_announce+0x22>
	z_spin_lock_set_owner(l);
    8a06:	4803      	ldr	r0, [pc, #12]	; (8a14 <sys_clock_announce+0x118>)
    8a08:	f7fe f9fc 	bl	6e04 <z_spin_lock_set_owner>
		announce_remaining -= dt;
    8a0c:	f8d8 4000 	ldr.w	r4, [r8]
    8a10:	1ba4      	subs	r4, r4, r6
    8a12:	e799      	b.n	8948 <sys_clock_announce+0x4c>
    8a14:	20000ee4 	.word	0x20000ee4
    8a18:	0000a51d 	.word	0x0000a51d
    8a1c:	0000a576 	.word	0x0000a576
    8a20:	0000a2e8 	.word	0x0000a2e8
    8a24:	0000a58b 	.word	0x0000a58b
    8a28:	20000ee0 	.word	0x20000ee0
    8a2c:	200000d8 	.word	0x200000d8
    8a30:	20000760 	.word	0x20000760
    8a34:	0000a54a 	.word	0x0000a54a
    8a38:	0000a561 	.word	0x0000a561

00008a3c <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    8a3c:	b570      	push	{r4, r5, r6, lr}
    8a3e:	f04f 0320 	mov.w	r3, #32
    8a42:	f3ef 8611 	mrs	r6, BASEPRI
    8a46:	f383 8812 	msr	BASEPRI_MAX, r3
    8a4a:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    8a4e:	481a      	ldr	r0, [pc, #104]	; (8ab8 <sys_clock_tick_get+0x7c>)
    8a50:	f7fe f9bc 	bl	6dcc <z_spin_lock_valid>
    8a54:	b968      	cbnz	r0, 8a72 <sys_clock_tick_get+0x36>
    8a56:	2394      	movs	r3, #148	; 0x94
    8a58:	4a18      	ldr	r2, [pc, #96]	; (8abc <sys_clock_tick_get+0x80>)
    8a5a:	4919      	ldr	r1, [pc, #100]	; (8ac0 <sys_clock_tick_get+0x84>)
    8a5c:	4819      	ldr	r0, [pc, #100]	; (8ac4 <sys_clock_tick_get+0x88>)
    8a5e:	f000 fc22 	bl	92a6 <assert_print>
    8a62:	4915      	ldr	r1, [pc, #84]	; (8ab8 <sys_clock_tick_get+0x7c>)
    8a64:	4818      	ldr	r0, [pc, #96]	; (8ac8 <sys_clock_tick_get+0x8c>)
    8a66:	f000 fc1e 	bl	92a6 <assert_print>
    8a6a:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8a6c:	4813      	ldr	r0, [pc, #76]	; (8abc <sys_clock_tick_get+0x80>)
    8a6e:	f000 fc13 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    8a72:	4811      	ldr	r0, [pc, #68]	; (8ab8 <sys_clock_tick_get+0x7c>)
    8a74:	f7fe f9c6 	bl	6e04 <z_spin_lock_set_owner>
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + elapsed();
    8a78:	f7ff fd4a 	bl	8510 <elapsed>
    8a7c:	4a13      	ldr	r2, [pc, #76]	; (8acc <sys_clock_tick_get+0x90>)
    8a7e:	e9d2 4500 	ldrd	r4, r5, [r2]
    8a82:	1904      	adds	r4, r0, r4
    8a84:	eb45 75e0 	adc.w	r5, r5, r0, asr #31
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8a88:	480b      	ldr	r0, [pc, #44]	; (8ab8 <sys_clock_tick_get+0x7c>)
    8a8a:	f7fe f9ad 	bl	6de8 <z_spin_unlock_valid>
    8a8e:	b958      	cbnz	r0, 8aa8 <sys_clock_tick_get+0x6c>
    8a90:	23c2      	movs	r3, #194	; 0xc2
    8a92:	4a0a      	ldr	r2, [pc, #40]	; (8abc <sys_clock_tick_get+0x80>)
    8a94:	490e      	ldr	r1, [pc, #56]	; (8ad0 <sys_clock_tick_get+0x94>)
    8a96:	480b      	ldr	r0, [pc, #44]	; (8ac4 <sys_clock_tick_get+0x88>)
    8a98:	f000 fc05 	bl	92a6 <assert_print>
    8a9c:	4906      	ldr	r1, [pc, #24]	; (8ab8 <sys_clock_tick_get+0x7c>)
    8a9e:	480d      	ldr	r0, [pc, #52]	; (8ad4 <sys_clock_tick_get+0x98>)
    8aa0:	f000 fc01 	bl	92a6 <assert_print>
    8aa4:	21c2      	movs	r1, #194	; 0xc2
    8aa6:	e7e1      	b.n	8a6c <sys_clock_tick_get+0x30>
	__asm__ volatile(
    8aa8:	f386 8811 	msr	BASEPRI, r6
    8aac:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    8ab0:	4620      	mov	r0, r4
    8ab2:	4629      	mov	r1, r5
    8ab4:	bd70      	pop	{r4, r5, r6, pc}
    8ab6:	bf00      	nop
    8ab8:	20000ee4 	.word	0x20000ee4
    8abc:	0000a51d 	.word	0x0000a51d
    8ac0:	0000a576 	.word	0x0000a576
    8ac4:	0000a2e8 	.word	0x0000a2e8
    8ac8:	0000a58b 	.word	0x0000a58b
    8acc:	20000760 	.word	0x20000760
    8ad0:	0000a54a 	.word	0x0000a54a
    8ad4:	0000a561 	.word	0x0000a561

00008ad8 <z_timer_expiration_handler>:
 * @brief Handle expiration of a kernel timer object.
 *
 * @param t  Timeout used by the timer.
 */
void z_timer_expiration_handler(struct _timeout *t)
{
    8ad8:	b570      	push	{r4, r5, r6, lr}
    8ada:	4604      	mov	r4, r0
	__asm__ volatile(
    8adc:	f04f 0320 	mov.w	r3, #32
    8ae0:	f3ef 8511 	mrs	r5, BASEPRI
    8ae4:	f383 8812 	msr	BASEPRI_MAX, r3
    8ae8:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    8aec:	4849      	ldr	r0, [pc, #292]	; (8c14 <z_timer_expiration_handler+0x13c>)
    8aee:	f7fe f96d 	bl	6dcc <z_spin_lock_valid>
    8af2:	b968      	cbnz	r0, 8b10 <z_timer_expiration_handler+0x38>
    8af4:	2394      	movs	r3, #148	; 0x94
    8af6:	4a48      	ldr	r2, [pc, #288]	; (8c18 <z_timer_expiration_handler+0x140>)
    8af8:	4948      	ldr	r1, [pc, #288]	; (8c1c <z_timer_expiration_handler+0x144>)
    8afa:	4849      	ldr	r0, [pc, #292]	; (8c20 <z_timer_expiration_handler+0x148>)
    8afc:	f000 fbd3 	bl	92a6 <assert_print>
    8b00:	4944      	ldr	r1, [pc, #272]	; (8c14 <z_timer_expiration_handler+0x13c>)
    8b02:	4848      	ldr	r0, [pc, #288]	; (8c24 <z_timer_expiration_handler+0x14c>)
    8b04:	f000 fbcf 	bl	92a6 <assert_print>
    8b08:	2194      	movs	r1, #148	; 0x94
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8b0a:	4843      	ldr	r0, [pc, #268]	; (8c18 <z_timer_expiration_handler+0x140>)
    8b0c:	f000 fbc4 	bl	9298 <assert_post_action>
	z_spin_lock_set_owner(l);
    8b10:	4840      	ldr	r0, [pc, #256]	; (8c14 <z_timer_expiration_handler+0x13c>)
    8b12:	f7fe f977 	bl	6e04 <z_spin_lock_set_owner>

	/*
	 * if the timer is periodic, start it again; don't add _TICK_ALIGN
	 * since we're already aligned to a tick boundary
	 */
	if (!K_TIMEOUT_EQ(timer->period, K_NO_WAIT) &&
    8b16:	e9d4 320a 	ldrd	r3, r2, [r4, #40]	; 0x28
    8b1a:	3301      	adds	r3, #1
    8b1c:	f142 0200 	adc.w	r2, r2, #0
    8b20:	2b02      	cmp	r3, #2
    8b22:	f172 0200 	sbcs.w	r2, r2, #0
    8b26:	d322      	bcc.n	8b6e <z_timer_expiration_handler+0x96>
	return z_impl_k_uptime_ticks();
    8b28:	f001 f86e 	bl	9c08 <z_impl_k_uptime_ticks>
		 * we "should" have run.  Requires absolute timeouts.
		 * (Note offset by one: we're nominally at the
		 * beginning of a tick, so need to defeat the "round
		 * down" behavior on timeout addition).
		 */
		next = K_TIMEOUT_ABS_TICKS(k_uptime_ticks() + 1
    8b2c:	e9d4 320a 	ldrd	r3, r2, [r4, #40]	; 0x28
    8b30:	3001      	adds	r0, #1
    8b32:	f141 0100 	adc.w	r1, r1, #0
    8b36:	18c0      	adds	r0, r0, r3
    8b38:	eb41 0102 	adc.w	r1, r1, r2
    8b3c:	2801      	cmp	r0, #1
    8b3e:	f171 0100 	sbcs.w	r1, r1, #0
    8b42:	db29      	blt.n	8b98 <z_timer_expiration_handler+0xc0>
    8b44:	f001 f860 	bl	9c08 <z_impl_k_uptime_ticks>
    8b48:	3001      	adds	r0, #1
    8b4a:	f141 0300 	adc.w	r3, r1, #0
    8b4e:	e9d4 210a 	ldrd	r2, r1, [r4, #40]	; 0x28
    8b52:	1880      	adds	r0, r0, r2
    8b54:	f06f 0201 	mvn.w	r2, #1
    8b58:	eb43 0301 	adc.w	r3, r3, r1
    8b5c:	f04f 31ff 	mov.w	r1, #4294967295
    8b60:	1a12      	subs	r2, r2, r0
    8b62:	eb61 0303 	sbc.w	r3, r1, r3
					   + timer->period.ticks);
#endif
		z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    8b66:	4620      	mov	r0, r4
    8b68:	492f      	ldr	r1, [pc, #188]	; (8c28 <z_timer_expiration_handler+0x150>)
    8b6a:	f7ff fd1f 	bl	85ac <z_add_timeout>
			      next);
	}

	/* update timer's status */
	timer->status += 1U;
    8b6e:	6b23      	ldr	r3, [r4, #48]	; 0x30
    8b70:	3301      	adds	r3, #1
    8b72:	6323      	str	r3, [r4, #48]	; 0x30

	/* invoke timer expiry function */
	if (timer->expiry_fn != NULL) {
    8b74:	6a23      	ldr	r3, [r4, #32]
    8b76:	b35b      	cbz	r3, 8bd0 <z_timer_expiration_handler+0xf8>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8b78:	4826      	ldr	r0, [pc, #152]	; (8c14 <z_timer_expiration_handler+0x13c>)
    8b7a:	f7fe f935 	bl	6de8 <z_spin_unlock_valid>
    8b7e:	b980      	cbnz	r0, 8ba2 <z_timer_expiration_handler+0xca>
    8b80:	23c2      	movs	r3, #194	; 0xc2
    8b82:	4a25      	ldr	r2, [pc, #148]	; (8c18 <z_timer_expiration_handler+0x140>)
    8b84:	4929      	ldr	r1, [pc, #164]	; (8c2c <z_timer_expiration_handler+0x154>)
    8b86:	4826      	ldr	r0, [pc, #152]	; (8c20 <z_timer_expiration_handler+0x148>)
    8b88:	f000 fb8d 	bl	92a6 <assert_print>
    8b8c:	4921      	ldr	r1, [pc, #132]	; (8c14 <z_timer_expiration_handler+0x13c>)
    8b8e:	4828      	ldr	r0, [pc, #160]	; (8c30 <z_timer_expiration_handler+0x158>)
    8b90:	f000 fb89 	bl	92a6 <assert_print>
    8b94:	21c2      	movs	r1, #194	; 0xc2
    8b96:	e7b8      	b.n	8b0a <z_timer_expiration_handler+0x32>
		next = K_TIMEOUT_ABS_TICKS(k_uptime_ticks() + 1
    8b98:	f06f 0201 	mvn.w	r2, #1
    8b9c:	f04f 33ff 	mov.w	r3, #4294967295
    8ba0:	e7e1      	b.n	8b66 <z_timer_expiration_handler+0x8e>
	__asm__ volatile(
    8ba2:	f385 8811 	msr	BASEPRI, r5
    8ba6:	f3bf 8f6f 	isb	sy
		/* Unlock for user handler. */
		k_spin_unlock(&lock, key);
		timer->expiry_fn(timer);
    8baa:	4620      	mov	r0, r4
    8bac:	6a23      	ldr	r3, [r4, #32]
    8bae:	4798      	blx	r3
	__asm__ volatile(
    8bb0:	f04f 0320 	mov.w	r3, #32
    8bb4:	f3ef 8511 	mrs	r5, BASEPRI
    8bb8:	f383 8812 	msr	BASEPRI_MAX, r3
    8bbc:	f3bf 8f6f 	isb	sy
	__ASSERT(z_spin_lock_valid(l), "Recursive spinlock %p", l);
    8bc0:	4814      	ldr	r0, [pc, #80]	; (8c14 <z_timer_expiration_handler+0x13c>)
    8bc2:	f7fe f903 	bl	6dcc <z_spin_lock_valid>
    8bc6:	2800      	cmp	r0, #0
    8bc8:	d094      	beq.n	8af4 <z_timer_expiration_handler+0x1c>
	z_spin_lock_set_owner(l);
    8bca:	4812      	ldr	r0, [pc, #72]	; (8c14 <z_timer_expiration_handler+0x13c>)
    8bcc:	f7fe f91a 	bl	6e04 <z_spin_lock_set_owner>
	return list->head == list;
    8bd0:	f854 6f18 	ldr.w	r6, [r4, #24]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    8bd4:	42a6      	cmp	r6, r4
    8bd6:	d000      	beq.n	8bda <z_timer_expiration_handler+0x102>
		return;
	}

	thread = z_waitq_head(&timer->wait_q);

	if (thread == NULL) {
    8bd8:	b94e      	cbnz	r6, 8bee <z_timer_expiration_handler+0x116>
	__ASSERT(z_spin_unlock_valid(l), "Not my spinlock %p", l);
    8bda:	480e      	ldr	r0, [pc, #56]	; (8c14 <z_timer_expiration_handler+0x13c>)
    8bdc:	f7fe f904 	bl	6de8 <z_spin_unlock_valid>
    8be0:	2800      	cmp	r0, #0
    8be2:	d0cd      	beq.n	8b80 <z_timer_expiration_handler+0xa8>
	__asm__ volatile(
    8be4:	f385 8811 	msr	BASEPRI, r5
    8be8:	f3bf 8f6f 	isb	sy
	arch_thread_return_value_set(thread, 0);

	k_spin_unlock(&lock, key);

	z_ready_thread(thread);
}
    8bec:	bd70      	pop	{r4, r5, r6, pc}
	z_unpend_thread_no_timeout(thread);
    8bee:	4630      	mov	r0, r6
    8bf0:	f7fe fc94 	bl	751c <z_unpend_thread_no_timeout>
    8bf4:	2300      	movs	r3, #0
    8bf6:	4807      	ldr	r0, [pc, #28]	; (8c14 <z_timer_expiration_handler+0x13c>)
    8bf8:	67b3      	str	r3, [r6, #120]	; 0x78
    8bfa:	f7fe f8f5 	bl	6de8 <z_spin_unlock_valid>
    8bfe:	2800      	cmp	r0, #0
    8c00:	d0be      	beq.n	8b80 <z_timer_expiration_handler+0xa8>
    8c02:	f385 8811 	msr	BASEPRI, r5
    8c06:	f3bf 8f6f 	isb	sy
	z_ready_thread(thread);
    8c0a:	4630      	mov	r0, r6
}
    8c0c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	z_ready_thread(thread);
    8c10:	f7fe bc3e 	b.w	7490 <z_ready_thread>
    8c14:	20000ee8 	.word	0x20000ee8
    8c18:	0000a51d 	.word	0x0000a51d
    8c1c:	0000a576 	.word	0x0000a576
    8c20:	0000a2e8 	.word	0x0000a2e8
    8c24:	0000a58b 	.word	0x0000a58b
    8c28:	00008ad9 	.word	0x00008ad9
    8c2c:	0000a54a 	.word	0x0000a54a
    8c30:	0000a561 	.word	0x0000a561

00008c34 <z_impl_k_timer_start>:
void z_impl_k_timer_start(struct k_timer *timer, k_timeout_t duration,
			  k_timeout_t period)
{
	SYS_PORT_TRACING_OBJ_FUNC(k_timer, start, timer, duration, period);

	if (K_TIMEOUT_EQ(duration, K_FOREVER)) {
    8c34:	f1b3 3fff 	cmp.w	r3, #4294967295
    8c38:	bf08      	it	eq
    8c3a:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    8c3e:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    8c42:	4619      	mov	r1, r3
    8c44:	4605      	mov	r5, r0
    8c46:	e9dd 6008 	ldrd	r6, r0, [sp, #32]
    8c4a:	4614      	mov	r4, r2
    8c4c:	4691      	mov	r9, r2
    8c4e:	4698      	mov	r8, r3
	if (K_TIMEOUT_EQ(duration, K_FOREVER)) {
    8c50:	d037      	beq.n	8cc2 <z_impl_k_timer_start+0x8e>
	 * for backwards compatibility.  This is unfortunate
	 * (i.e. k_timer_start() doesn't treat its initial sleep
	 * argument the same way k_sleep() does), but historical.  The
	 * timer_api test relies on this behavior.
	 */
	if (!K_TIMEOUT_EQ(period, K_FOREVER) && period.ticks != 0 &&
    8c52:	f1b0 3fff 	cmp.w	r0, #4294967295
    8c56:	bf08      	it	eq
    8c58:	f1b6 3fff 	cmpeq.w	r6, #4294967295
    8c5c:	4637      	mov	r7, r6
    8c5e:	4682      	mov	sl, r0
    8c60:	d011      	beq.n	8c86 <z_impl_k_timer_start+0x52>
    8c62:	ea50 0306 	orrs.w	r3, r0, r6
    8c66:	d00e      	beq.n	8c86 <z_impl_k_timer_start+0x52>
    8c68:	1c72      	adds	r2, r6, #1
    8c6a:	f170 33ff 	sbcs.w	r3, r0, #4294967295
    8c6e:	db0a      	blt.n	8c86 <z_impl_k_timer_start+0x52>
	    Z_TICK_ABS(period.ticks) < 0) {
		period.ticks = MAX(period.ticks - 1, 1);
    8c70:	2e02      	cmp	r6, #2
    8c72:	4684      	mov	ip, r0
    8c74:	f170 0000 	sbcs.w	r0, r0, #0
    8c78:	bfbc      	itt	lt
    8c7a:	2702      	movlt	r7, #2
    8c7c:	f04f 0c00 	movlt.w	ip, #0
    8c80:	3f01      	subs	r7, #1
    8c82:	f14c 3aff 	adc.w	sl, ip, #4294967295
	}
	if (Z_TICK_ABS(duration.ticks) < 0) {
    8c86:	1c63      	adds	r3, r4, #1
    8c88:	f171 33ff 	sbcs.w	r3, r1, #4294967295
    8c8c:	db0a      	blt.n	8ca4 <z_impl_k_timer_start+0x70>
		duration.ticks = MAX(duration.ticks - 1, 0);
    8c8e:	2c01      	cmp	r4, #1
    8c90:	f171 0300 	sbcs.w	r3, r1, #0
    8c94:	4622      	mov	r2, r4
    8c96:	bfbc      	itt	lt
    8c98:	2201      	movlt	r2, #1
    8c9a:	2100      	movlt	r1, #0
    8c9c:	f112 39ff 	adds.w	r9, r2, #4294967295
    8ca0:	f141 38ff 	adc.w	r8, r1, #4294967295
	}

	(void)z_abort_timeout(&timer->timeout);
    8ca4:	4628      	mov	r0, r5
    8ca6:	f7ff fd47 	bl	8738 <z_abort_timeout>
	timer->period = period;
	timer->status = 0U;
    8caa:	2300      	movs	r3, #0
	timer->period = period;
    8cac:	e9c5 7a0a 	strd	r7, sl, [r5, #40]	; 0x28
	timer->status = 0U;
    8cb0:	632b      	str	r3, [r5, #48]	; 0x30

	z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    8cb2:	464a      	mov	r2, r9
    8cb4:	4643      	mov	r3, r8
    8cb6:	4628      	mov	r0, r5
		     duration);
}
    8cb8:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    8cbc:	4902      	ldr	r1, [pc, #8]	; (8cc8 <z_impl_k_timer_start+0x94>)
    8cbe:	f7ff bc75 	b.w	85ac <z_add_timeout>
}
    8cc2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    8cc6:	bf00      	nop
    8cc8:	00008ad9 	.word	0x00008ad9

00008ccc <nrf_cc3xx_platform_init_no_rng>:
    8ccc:	b510      	push	{r4, lr}
    8cce:	4c0a      	ldr	r4, [pc, #40]	; (8cf8 <nrf_cc3xx_platform_init_no_rng+0x2c>)
    8cd0:	6823      	ldr	r3, [r4, #0]
    8cd2:	b11b      	cbz	r3, 8cdc <nrf_cc3xx_platform_init_no_rng+0x10>
    8cd4:	2301      	movs	r3, #1
    8cd6:	2000      	movs	r0, #0
    8cd8:	6023      	str	r3, [r4, #0]
    8cda:	bd10      	pop	{r4, pc}
    8cdc:	f000 f8f4 	bl	8ec8 <CC_LibInitNoRng>
    8ce0:	2800      	cmp	r0, #0
    8ce2:	d0f7      	beq.n	8cd4 <nrf_cc3xx_platform_init_no_rng+0x8>
    8ce4:	3801      	subs	r0, #1
    8ce6:	2807      	cmp	r0, #7
    8ce8:	d803      	bhi.n	8cf2 <nrf_cc3xx_platform_init_no_rng+0x26>
    8cea:	4b04      	ldr	r3, [pc, #16]	; (8cfc <nrf_cc3xx_platform_init_no_rng+0x30>)
    8cec:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    8cf0:	bd10      	pop	{r4, pc}
    8cf2:	4803      	ldr	r0, [pc, #12]	; (8d00 <nrf_cc3xx_platform_init_no_rng+0x34>)
    8cf4:	bd10      	pop	{r4, pc}
    8cf6:	bf00      	nop
    8cf8:	20000eec 	.word	0x20000eec
    8cfc:	0000a228 	.word	0x0000a228
    8d00:	ffff8ffe 	.word	0xffff8ffe

00008d04 <nrf_cc3xx_platform_abort>:
    8d04:	f3bf 8f4f 	dsb	sy
    8d08:	4905      	ldr	r1, [pc, #20]	; (8d20 <nrf_cc3xx_platform_abort+0x1c>)
    8d0a:	4b06      	ldr	r3, [pc, #24]	; (8d24 <nrf_cc3xx_platform_abort+0x20>)
    8d0c:	68ca      	ldr	r2, [r1, #12]
    8d0e:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    8d12:	4313      	orrs	r3, r2
    8d14:	60cb      	str	r3, [r1, #12]
    8d16:	f3bf 8f4f 	dsb	sy
    8d1a:	bf00      	nop
    8d1c:	e7fd      	b.n	8d1a <nrf_cc3xx_platform_abort+0x16>
    8d1e:	bf00      	nop
    8d20:	e000ed00 	.word	0xe000ed00
    8d24:	05fa0004 	.word	0x05fa0004

00008d28 <CC_PalAbort>:
    8d28:	b430      	push	{r4, r5}
    8d2a:	f04f 32fe 	mov.w	r2, #4278124286	; 0xfefefefe
    8d2e:	2500      	movs	r5, #0
    8d30:	4b0b      	ldr	r3, [pc, #44]	; (8d60 <CC_PalAbort+0x38>)
    8d32:	4c0c      	ldr	r4, [pc, #48]	; (8d64 <CC_PalAbort+0x3c>)
    8d34:	490c      	ldr	r1, [pc, #48]	; (8d68 <CC_PalAbort+0x40>)
    8d36:	6849      	ldr	r1, [r1, #4]
    8d38:	f8c3 2400 	str.w	r2, [r3, #1024]	; 0x400
    8d3c:	f8c3 2404 	str.w	r2, [r3, #1028]	; 0x404
    8d40:	f8c3 2408 	str.w	r2, [r3, #1032]	; 0x408
    8d44:	f8c3 240c 	str.w	r2, [r3, #1036]	; 0x40c
    8d48:	f8c3 2410 	str.w	r2, [r3, #1040]	; 0x410
    8d4c:	f8c3 2414 	str.w	r2, [r3, #1044]	; 0x414
    8d50:	f8c3 2418 	str.w	r2, [r3, #1048]	; 0x418
    8d54:	f8c3 241c 	str.w	r2, [r3, #1052]	; 0x41c
    8d58:	f8c4 5500 	str.w	r5, [r4, #1280]	; 0x500
    8d5c:	bc30      	pop	{r4, r5}
    8d5e:	4708      	bx	r1
    8d60:	50845000 	.word	0x50845000
    8d64:	50844000 	.word	0x50844000
    8d68:	200000e0 	.word	0x200000e0

00008d6c <nrf_cc3xx_platform_set_abort>:
    8d6c:	4b02      	ldr	r3, [pc, #8]	; (8d78 <nrf_cc3xx_platform_set_abort+0xc>)
    8d6e:	e9d0 1200 	ldrd	r1, r2, [r0]
    8d72:	e9c3 1200 	strd	r1, r2, [r3]
    8d76:	4770      	bx	lr
    8d78:	200000e0 	.word	0x200000e0

00008d7c <mutex_free>:
    8d7c:	b510      	push	{r4, lr}
    8d7e:	4604      	mov	r4, r0
    8d80:	b150      	cbz	r0, 8d98 <mutex_free+0x1c>
    8d82:	6863      	ldr	r3, [r4, #4]
    8d84:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    8d88:	d005      	beq.n	8d96 <mutex_free+0x1a>
    8d8a:	4a06      	ldr	r2, [pc, #24]	; (8da4 <mutex_free+0x28>)
    8d8c:	4293      	cmp	r3, r2
    8d8e:	d002      	beq.n	8d96 <mutex_free+0x1a>
    8d90:	2300      	movs	r3, #0
    8d92:	6062      	str	r2, [r4, #4]
    8d94:	6023      	str	r3, [r4, #0]
    8d96:	bd10      	pop	{r4, pc}
    8d98:	4b03      	ldr	r3, [pc, #12]	; (8da8 <mutex_free+0x2c>)
    8d9a:	4804      	ldr	r0, [pc, #16]	; (8dac <mutex_free+0x30>)
    8d9c:	685b      	ldr	r3, [r3, #4]
    8d9e:	4798      	blx	r3
    8da0:	e7ef      	b.n	8d82 <mutex_free+0x6>
    8da2:	bf00      	nop
    8da4:	a95c5f2c 	.word	0xa95c5f2c
    8da8:	200000e0 	.word	0x200000e0
    8dac:	0000a248 	.word	0x0000a248

00008db0 <mutex_lock>:
    8db0:	b1c8      	cbz	r0, 8de6 <mutex_lock+0x36>
    8db2:	6843      	ldr	r3, [r0, #4]
    8db4:	4a0d      	ldr	r2, [pc, #52]	; (8dec <mutex_lock+0x3c>)
    8db6:	4293      	cmp	r3, r2
    8db8:	d013      	beq.n	8de2 <mutex_lock+0x32>
    8dba:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    8dbe:	d00e      	beq.n	8dde <mutex_lock+0x2e>
    8dc0:	2301      	movs	r3, #1
    8dc2:	e850 2f00 	ldrex	r2, [r0]
    8dc6:	4619      	mov	r1, r3
    8dc8:	e840 1c00 	strex	ip, r1, [r0]
    8dcc:	f09c 0f00 	teq	ip, #0
    8dd0:	d1f7      	bne.n	8dc2 <mutex_lock+0x12>
    8dd2:	2a01      	cmp	r2, #1
    8dd4:	d0f5      	beq.n	8dc2 <mutex_lock+0x12>
    8dd6:	f3bf 8f5f 	dmb	sy
    8dda:	2000      	movs	r0, #0
    8ddc:	4770      	bx	lr
    8dde:	4804      	ldr	r0, [pc, #16]	; (8df0 <mutex_lock+0x40>)
    8de0:	4770      	bx	lr
    8de2:	4804      	ldr	r0, [pc, #16]	; (8df4 <mutex_lock+0x44>)
    8de4:	4770      	bx	lr
    8de6:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    8dea:	4770      	bx	lr
    8dec:	a95c5f2c 	.word	0xa95c5f2c
    8df0:	ffff8fe9 	.word	0xffff8fe9
    8df4:	ffff8fea 	.word	0xffff8fea

00008df8 <mutex_unlock>:
    8df8:	4603      	mov	r3, r0
    8dfa:	b180      	cbz	r0, 8e1e <mutex_unlock+0x26>
    8dfc:	6842      	ldr	r2, [r0, #4]
    8dfe:	4909      	ldr	r1, [pc, #36]	; (8e24 <mutex_unlock+0x2c>)
    8e00:	428a      	cmp	r2, r1
    8e02:	d00a      	beq.n	8e1a <mutex_unlock+0x22>
    8e04:	f012 5f68 	tst.w	r2, #973078528	; 0x3a000000
    8e08:	d005      	beq.n	8e16 <mutex_unlock+0x1e>
    8e0a:	f3bf 8f5f 	dmb	sy
    8e0e:	2200      	movs	r2, #0
    8e10:	4610      	mov	r0, r2
    8e12:	601a      	str	r2, [r3, #0]
    8e14:	4770      	bx	lr
    8e16:	4804      	ldr	r0, [pc, #16]	; (8e28 <mutex_unlock+0x30>)
    8e18:	4770      	bx	lr
    8e1a:	4804      	ldr	r0, [pc, #16]	; (8e2c <mutex_unlock+0x34>)
    8e1c:	4770      	bx	lr
    8e1e:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    8e22:	4770      	bx	lr
    8e24:	a95c5f2c 	.word	0xa95c5f2c
    8e28:	ffff8fe9 	.word	0xffff8fe9
    8e2c:	ffff8fea 	.word	0xffff8fea

00008e30 <mutex_init>:
    8e30:	b510      	push	{r4, lr}
    8e32:	4604      	mov	r4, r0
    8e34:	b120      	cbz	r0, 8e40 <mutex_init+0x10>
    8e36:	2300      	movs	r3, #0
    8e38:	4a03      	ldr	r2, [pc, #12]	; (8e48 <mutex_init+0x18>)
    8e3a:	6023      	str	r3, [r4, #0]
    8e3c:	6062      	str	r2, [r4, #4]
    8e3e:	bd10      	pop	{r4, pc}
    8e40:	4802      	ldr	r0, [pc, #8]	; (8e4c <mutex_init+0x1c>)
    8e42:	f7ff ff71 	bl	8d28 <CC_PalAbort>
    8e46:	e7f6      	b.n	8e36 <mutex_init+0x6>
    8e48:	3a00003a 	.word	0x3a00003a
    8e4c:	0000a270 	.word	0x0000a270

00008e50 <nrf_cc3xx_platform_set_mutexes>:
    8e50:	b570      	push	{r4, r5, r6, lr}
    8e52:	4c19      	ldr	r4, [pc, #100]	; (8eb8 <nrf_cc3xx_platform_set_mutexes+0x68>)
    8e54:	f8d0 c004 	ldr.w	ip, [r0, #4]
    8e58:	6806      	ldr	r6, [r0, #0]
    8e5a:	f8c4 c004 	str.w	ip, [r4, #4]
    8e5e:	f8d0 c008 	ldr.w	ip, [r0, #8]
    8e62:	68c0      	ldr	r0, [r0, #12]
    8e64:	f8c4 c008 	str.w	ip, [r4, #8]
    8e68:	60e0      	str	r0, [r4, #12]
    8e6a:	6026      	str	r6, [r4, #0]
    8e6c:	6808      	ldr	r0, [r1, #0]
    8e6e:	4b13      	ldr	r3, [pc, #76]	; (8ebc <nrf_cc3xx_platform_set_mutexes+0x6c>)
    8e70:	4d13      	ldr	r5, [pc, #76]	; (8ec0 <nrf_cc3xx_platform_set_mutexes+0x70>)
    8e72:	6018      	str	r0, [r3, #0]
    8e74:	6848      	ldr	r0, [r1, #4]
    8e76:	f8d5 2118 	ldr.w	r2, [r5, #280]	; 0x118
    8e7a:	6058      	str	r0, [r3, #4]
    8e7c:	6888      	ldr	r0, [r1, #8]
    8e7e:	f012 5f68 	tst.w	r2, #973078528	; 0x3a000000
    8e82:	6098      	str	r0, [r3, #8]
    8e84:	68c8      	ldr	r0, [r1, #12]
    8e86:	6909      	ldr	r1, [r1, #16]
    8e88:	60d8      	str	r0, [r3, #12]
    8e8a:	6119      	str	r1, [r3, #16]
    8e8c:	d012      	beq.n	8eb4 <nrf_cc3xx_platform_set_mutexes+0x64>
    8e8e:	2300      	movs	r3, #0
    8e90:	4a0c      	ldr	r2, [pc, #48]	; (8ec4 <nrf_cc3xx_platform_set_mutexes+0x74>)
    8e92:	f505 708a 	add.w	r0, r5, #276	; 0x114
    8e96:	f8c5 3114 	str.w	r3, [r5, #276]	; 0x114
    8e9a:	f8c5 31b8 	str.w	r3, [r5, #440]	; 0x1b8
    8e9e:	f8c5 2118 	str.w	r2, [r5, #280]	; 0x118
    8ea2:	f8c5 21bc 	str.w	r2, [r5, #444]	; 0x1bc
    8ea6:	47b0      	blx	r6
    8ea8:	6823      	ldr	r3, [r4, #0]
    8eaa:	f505 70dc 	add.w	r0, r5, #440	; 0x1b8
    8eae:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    8eb2:	4718      	bx	r3
    8eb4:	bd70      	pop	{r4, r5, r6, pc}
    8eb6:	bf00      	nop
    8eb8:	200000f0 	.word	0x200000f0
    8ebc:	20000100 	.word	0x20000100
    8ec0:	20000f04 	.word	0x20000f04
    8ec4:	a95c5f2c 	.word	0xa95c5f2c

00008ec8 <CC_LibInitNoRng>:
    8ec8:	b508      	push	{r3, lr}
    8eca:	f000 f811 	bl	8ef0 <CC_HalInit>
    8ece:	b930      	cbnz	r0, 8ede <CC_LibInitNoRng+0x16>
    8ed0:	f000 f810 	bl	8ef4 <CC_PalInit>
    8ed4:	b938      	cbnz	r0, 8ee6 <CC_LibInitNoRng+0x1e>
    8ed6:	4a05      	ldr	r2, [pc, #20]	; (8eec <CC_LibInitNoRng+0x24>)
    8ed8:	f8c2 0a0c 	str.w	r0, [r2, #2572]	; 0xa0c
    8edc:	bd08      	pop	{r3, pc}
    8ede:	f000 f837 	bl	8f50 <CC_PalTerminate>
    8ee2:	2003      	movs	r0, #3
    8ee4:	bd08      	pop	{r3, pc}
    8ee6:	2004      	movs	r0, #4
    8ee8:	bd08      	pop	{r3, pc}
    8eea:	bf00      	nop
    8eec:	50845000 	.word	0x50845000

00008ef0 <CC_HalInit>:
    8ef0:	2000      	movs	r0, #0
    8ef2:	4770      	bx	lr

00008ef4 <CC_PalInit>:
    8ef4:	b510      	push	{r4, lr}
    8ef6:	4811      	ldr	r0, [pc, #68]	; (8f3c <CC_PalInit+0x48>)
    8ef8:	f000 f848 	bl	8f8c <CC_PalMutexCreate>
    8efc:	b100      	cbz	r0, 8f00 <CC_PalInit+0xc>
    8efe:	bd10      	pop	{r4, pc}
    8f00:	480f      	ldr	r0, [pc, #60]	; (8f40 <CC_PalInit+0x4c>)
    8f02:	f000 f843 	bl	8f8c <CC_PalMutexCreate>
    8f06:	2800      	cmp	r0, #0
    8f08:	d1f9      	bne.n	8efe <CC_PalInit+0xa>
    8f0a:	4c0e      	ldr	r4, [pc, #56]	; (8f44 <CC_PalInit+0x50>)
    8f0c:	4620      	mov	r0, r4
    8f0e:	f000 f83d 	bl	8f8c <CC_PalMutexCreate>
    8f12:	2800      	cmp	r0, #0
    8f14:	d1f3      	bne.n	8efe <CC_PalInit+0xa>
    8f16:	4b0c      	ldr	r3, [pc, #48]	; (8f48 <CC_PalInit+0x54>)
    8f18:	480c      	ldr	r0, [pc, #48]	; (8f4c <CC_PalInit+0x58>)
    8f1a:	601c      	str	r4, [r3, #0]
    8f1c:	f000 f836 	bl	8f8c <CC_PalMutexCreate>
    8f20:	4601      	mov	r1, r0
    8f22:	2800      	cmp	r0, #0
    8f24:	d1eb      	bne.n	8efe <CC_PalInit+0xa>
    8f26:	f000 f82d 	bl	8f84 <CC_PalDmaInit>
    8f2a:	4604      	mov	r4, r0
    8f2c:	b108      	cbz	r0, 8f32 <CC_PalInit+0x3e>
    8f2e:	4620      	mov	r0, r4
    8f30:	bd10      	pop	{r4, pc}
    8f32:	f000 f83f 	bl	8fb4 <CC_PalPowerSaveModeInit>
    8f36:	4620      	mov	r0, r4
    8f38:	e7fa      	b.n	8f30 <CC_PalInit+0x3c>
    8f3a:	bf00      	nop
    8f3c:	20000138 	.word	0x20000138
    8f40:	2000012c 	.word	0x2000012c
    8f44:	20000134 	.word	0x20000134
    8f48:	2000013c 	.word	0x2000013c
    8f4c:	20000130 	.word	0x20000130

00008f50 <CC_PalTerminate>:
    8f50:	b508      	push	{r3, lr}
    8f52:	4808      	ldr	r0, [pc, #32]	; (8f74 <CC_PalTerminate+0x24>)
    8f54:	f000 f824 	bl	8fa0 <CC_PalMutexDestroy>
    8f58:	4807      	ldr	r0, [pc, #28]	; (8f78 <CC_PalTerminate+0x28>)
    8f5a:	f000 f821 	bl	8fa0 <CC_PalMutexDestroy>
    8f5e:	4807      	ldr	r0, [pc, #28]	; (8f7c <CC_PalTerminate+0x2c>)
    8f60:	f000 f81e 	bl	8fa0 <CC_PalMutexDestroy>
    8f64:	4806      	ldr	r0, [pc, #24]	; (8f80 <CC_PalTerminate+0x30>)
    8f66:	f000 f81b 	bl	8fa0 <CC_PalMutexDestroy>
    8f6a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    8f6e:	f000 b80b 	b.w	8f88 <CC_PalDmaTerminate>
    8f72:	bf00      	nop
    8f74:	20000138 	.word	0x20000138
    8f78:	2000012c 	.word	0x2000012c
    8f7c:	20000134 	.word	0x20000134
    8f80:	20000130 	.word	0x20000130

00008f84 <CC_PalDmaInit>:
    8f84:	2000      	movs	r0, #0
    8f86:	4770      	bx	lr

00008f88 <CC_PalDmaTerminate>:
    8f88:	4770      	bx	lr
    8f8a:	bf00      	nop

00008f8c <CC_PalMutexCreate>:
    8f8c:	b508      	push	{r3, lr}
    8f8e:	4b03      	ldr	r3, [pc, #12]	; (8f9c <CC_PalMutexCreate+0x10>)
    8f90:	6802      	ldr	r2, [r0, #0]
    8f92:	681b      	ldr	r3, [r3, #0]
    8f94:	6810      	ldr	r0, [r2, #0]
    8f96:	4798      	blx	r3
    8f98:	2000      	movs	r0, #0
    8f9a:	bd08      	pop	{r3, pc}
    8f9c:	200000f0 	.word	0x200000f0

00008fa0 <CC_PalMutexDestroy>:
    8fa0:	b508      	push	{r3, lr}
    8fa2:	4b03      	ldr	r3, [pc, #12]	; (8fb0 <CC_PalMutexDestroy+0x10>)
    8fa4:	6802      	ldr	r2, [r0, #0]
    8fa6:	685b      	ldr	r3, [r3, #4]
    8fa8:	6810      	ldr	r0, [r2, #0]
    8faa:	4798      	blx	r3
    8fac:	2000      	movs	r0, #0
    8fae:	bd08      	pop	{r3, pc}
    8fb0:	200000f0 	.word	0x200000f0

00008fb4 <CC_PalPowerSaveModeInit>:
    8fb4:	b570      	push	{r4, r5, r6, lr}
    8fb6:	4c09      	ldr	r4, [pc, #36]	; (8fdc <CC_PalPowerSaveModeInit+0x28>)
    8fb8:	4d09      	ldr	r5, [pc, #36]	; (8fe0 <CC_PalPowerSaveModeInit+0x2c>)
    8fba:	6920      	ldr	r0, [r4, #16]
    8fbc:	68ab      	ldr	r3, [r5, #8]
    8fbe:	4798      	blx	r3
    8fc0:	b118      	cbz	r0, 8fca <CC_PalPowerSaveModeInit+0x16>
    8fc2:	4b08      	ldr	r3, [pc, #32]	; (8fe4 <CC_PalPowerSaveModeInit+0x30>)
    8fc4:	4808      	ldr	r0, [pc, #32]	; (8fe8 <CC_PalPowerSaveModeInit+0x34>)
    8fc6:	685b      	ldr	r3, [r3, #4]
    8fc8:	4798      	blx	r3
    8fca:	2100      	movs	r1, #0
    8fcc:	4a07      	ldr	r2, [pc, #28]	; (8fec <CC_PalPowerSaveModeInit+0x38>)
    8fce:	68eb      	ldr	r3, [r5, #12]
    8fd0:	6011      	str	r1, [r2, #0]
    8fd2:	6920      	ldr	r0, [r4, #16]
    8fd4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    8fd8:	4718      	bx	r3
    8fda:	bf00      	nop
    8fdc:	20000100 	.word	0x20000100
    8fe0:	200000f0 	.word	0x200000f0
    8fe4:	200000e0 	.word	0x200000e0
    8fe8:	0000a294 	.word	0x0000a294
    8fec:	20000f00 	.word	0x20000f00

00008ff0 <cbpprintf_external>:
{
    8ff0:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    8ff4:	4606      	mov	r6, r0
    8ff6:	460d      	mov	r5, r1
    8ff8:	4617      	mov	r7, r2
	if (buf == NULL) {
    8ffa:	4698      	mov	r8, r3
    8ffc:	b32b      	cbz	r3, 904a <cbpprintf_external+0x5a>
	for (i = 0; i < s_nbr; i++) {
    8ffe:	f04f 0a00 	mov.w	sl, #0
	args_size = hdr->hdr.desc.len * sizeof(int);
    9002:	f898 4000 	ldrb.w	r4, [r8]
	s_nbr     = hdr->hdr.desc.str_cnt;
    9006:	f893 9001 	ldrb.w	r9, [r3, #1]
	s = (char *)(buf + args_size + ros_nbr + 2 * rws_nbr);
    900a:	78db      	ldrb	r3, [r3, #3]
	args_size = hdr->hdr.desc.len * sizeof(int);
    900c:	00a4      	lsls	r4, r4, #2
	s = (char *)(buf + args_size + ros_nbr + 2 * rws_nbr);
    900e:	eb04 0443 	add.w	r4, r4, r3, lsl #1
	ros_nbr   = hdr->hdr.desc.ro_str_cnt;
    9012:	f898 3002 	ldrb.w	r3, [r8, #2]
	s = (char *)(buf + args_size + ros_nbr + 2 * rws_nbr);
    9016:	441c      	add	r4, r3
    9018:	4444      	add	r4, r8
	for (i = 0; i < s_nbr; i++) {
    901a:	45ca      	cmp	sl, r9
    901c:	d309      	bcc.n	9032 <cbpprintf_external+0x42>
	return formatter(out, ctx, fmt, u.ap);
    901e:	4639      	mov	r1, r7
    9020:	4630      	mov	r0, r6
    9022:	46ac      	mov	ip, r5
    9024:	f8d8 2004 	ldr.w	r2, [r8, #4]
    9028:	f108 0308 	add.w	r3, r8, #8
}
    902c:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	return formatter(out, ctx, fmt, u.ap);
    9030:	4760      	bx	ip
		ps = (char **)(buf + s_idx * sizeof(int));
    9032:	f814 3b01 	ldrb.w	r3, [r4], #1
	for (i = 0; i < s_nbr; i++) {
    9036:	f10a 0a01 	add.w	sl, sl, #1
		s += strlen(s) + 1;
    903a:	4620      	mov	r0, r4
		*ps = s;
    903c:	f848 4023 	str.w	r4, [r8, r3, lsl #2]
		s += strlen(s) + 1;
    9040:	f000 fad6 	bl	95f0 <strlen>
    9044:	3001      	adds	r0, #1
    9046:	4404      	add	r4, r0
	for (i = 0; i < s_nbr; i++) {
    9048:	e7e7      	b.n	901a <cbpprintf_external+0x2a>
}
    904a:	f06f 0015 	mvn.w	r0, #21
    904e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}

00009052 <is_ptr>:
{
    9052:	b570      	push	{r4, r5, r6, lr}
	int cnt = 0;
    9054:	2500      	movs	r5, #0
{
    9056:	4602      	mov	r2, r0
	bool mod = false;
    9058:	4628      	mov	r0, r5
	while ((c = *fmt++) != '\0') {
    905a:	4614      	mov	r4, r2
    905c:	f814 3b01 	ldrb.w	r3, [r4], #1
    9060:	b90b      	cbnz	r3, 9066 <is_ptr+0x14>
					return false;
    9062:	4618      	mov	r0, r3
    9064:	e009      	b.n	907a <is_ptr+0x28>
		if (mod) {
    9066:	b198      	cbz	r0, 9090 <is_ptr+0x3e>
			if (cnt == n) {
    9068:	428d      	cmp	r5, r1
    906a:	d107      	bne.n	907c <is_ptr+0x2a>
				if (c == 'p') {
    906c:	2b70      	cmp	r3, #112	; 0x70
    906e:	d004      	beq.n	907a <is_ptr+0x28>
				} else if (is_fmt_spec(c)) {
    9070:	f1a3 0240 	sub.w	r2, r3, #64	; 0x40
    9074:	2a3a      	cmp	r2, #58	; 0x3a
    9076:	d80b      	bhi.n	9090 <is_ptr+0x3e>
					return false;
    9078:	2000      	movs	r0, #0
}
    907a:	bd70      	pop	{r4, r5, r6, pc}
			} else if (is_fmt_spec(c)) {
    907c:	f1a3 0640 	sub.w	r6, r3, #64	; 0x40
    9080:	2e3a      	cmp	r6, #58	; 0x3a
    9082:	d805      	bhi.n	9090 <is_ptr+0x3e>
	while ((c = *fmt++) != '\0') {
    9084:	7853      	ldrb	r3, [r2, #1]
				cnt++;
    9086:	3501      	adds	r5, #1
	while ((c = *fmt++) != '\0') {
    9088:	1c94      	adds	r4, r2, #2
    908a:	2b00      	cmp	r3, #0
    908c:	d0e9      	beq.n	9062 <is_ptr+0x10>
    908e:	2000      	movs	r0, #0
		if (c == '%') {
    9090:	2b25      	cmp	r3, #37	; 0x25
	while ((c = *fmt++) != '\0') {
    9092:	4622      	mov	r2, r4
			mod = !mod;
    9094:	bf08      	it	eq
    9096:	f080 0001 	eoreq.w	r0, r0, #1
    909a:	e7de      	b.n	905a <is_ptr+0x8>

0000909c <arch_printk_char_out>:
}
    909c:	2000      	movs	r0, #0
    909e:	4770      	bx	lr

000090a0 <str_out>:
{
    90a0:	b530      	push	{r4, r5, lr}
	if (ctx->str == NULL || ctx->count >= ctx->max) {
    90a2:	688a      	ldr	r2, [r1, #8]
    90a4:	680c      	ldr	r4, [r1, #0]
		ctx->str[ctx->count++] = '\0';
    90a6:	1c55      	adds	r5, r2, #1
	if (ctx->str == NULL || ctx->count >= ctx->max) {
    90a8:	b114      	cbz	r4, 90b0 <str_out+0x10>
    90aa:	684b      	ldr	r3, [r1, #4]
    90ac:	4293      	cmp	r3, r2
    90ae:	dc01      	bgt.n	90b4 <str_out+0x14>
		ctx->count++;
    90b0:	608d      	str	r5, [r1, #8]
}
    90b2:	bd30      	pop	{r4, r5, pc}
	if (ctx->count == ctx->max - 1) {
    90b4:	3b01      	subs	r3, #1
    90b6:	4293      	cmp	r3, r2
		ctx->str[ctx->count++] = '\0';
    90b8:	bf08      	it	eq
    90ba:	2200      	moveq	r2, #0
    90bc:	608d      	str	r5, [r1, #8]
    90be:	bf0c      	ite	eq
    90c0:	54e2      	strbeq	r2, [r4, r3]
		ctx->str[ctx->count++] = c;
    90c2:	54a0      	strbne	r0, [r4, r2]
    90c4:	e7f5      	b.n	90b2 <str_out+0x12>

000090c6 <vprintk>:
		z_log_vprintk(fmt, ap);
    90c6:	f000 b9de 	b.w	9486 <z_log_vprintk>

000090ca <printk>:
{
    90ca:	b40f      	push	{r0, r1, r2, r3}
    90cc:	b507      	push	{r0, r1, r2, lr}
    90ce:	a904      	add	r1, sp, #16
    90d0:	f851 0b04 	ldr.w	r0, [r1], #4
	va_start(ap, fmt);
    90d4:	9101      	str	r1, [sp, #4]
		z_log_vprintk(fmt, ap);
    90d6:	f000 f9d6 	bl	9486 <z_log_vprintk>
}
    90da:	b003      	add	sp, #12
    90dc:	f85d eb04 	ldr.w	lr, [sp], #4
    90e0:	b004      	add	sp, #16
    90e2:	4770      	bx	lr

000090e4 <snprintk>:
{
    90e4:	b40c      	push	{r2, r3}
    90e6:	b507      	push	{r0, r1, r2, lr}
    90e8:	ab04      	add	r3, sp, #16
    90ea:	f853 2b04 	ldr.w	r2, [r3], #4
	va_start(ap, fmt);
    90ee:	9301      	str	r3, [sp, #4]
	ret = vsnprintk(str, size, fmt, ap);
    90f0:	f7f7 fe00 	bl	cf4 <vsnprintk>
}
    90f4:	b003      	add	sp, #12
    90f6:	f85d eb04 	ldr.w	lr, [sp], #4
    90fa:	b002      	add	sp, #8
    90fc:	4770      	bx	lr

000090fe <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    90fe:	4604      	mov	r4, r0
    9100:	b508      	push	{r3, lr}
    9102:	4608      	mov	r0, r1
    9104:	4611      	mov	r1, r2
#ifdef CONFIG_THREAD_LOCAL_STORAGE
	z_tls_current = z_current_get();
#endif
	entry(p1, p2, p3);
    9106:	461a      	mov	r2, r3
    9108:	47a0      	blx	r4
	return z_impl_z_current_get();
    910a:	f7ff f919 	bl	8340 <z_impl_z_current_get>
	z_impl_k_thread_abort(thread);
    910e:	f7fa fee5 	bl	3edc <z_impl_k_thread_abort>

00009112 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    9112:	8b83      	ldrh	r3, [r0, #28]
	if ((state == ONOFF_STATE_OFF)
    9114:	f013 0307 	ands.w	r3, r3, #7
    9118:	d105      	bne.n	9126 <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    911a:	6803      	ldr	r3, [r0, #0]
		evt = EVT_START;
    911c:	2b00      	cmp	r3, #0
    911e:	bf0c      	ite	eq
    9120:	2000      	moveq	r0, #0
    9122:	2003      	movne	r0, #3
    9124:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    9126:	2b02      	cmp	r3, #2
    9128:	d105      	bne.n	9136 <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    912a:	8bc0      	ldrh	r0, [r0, #30]
    912c:	fab0 f080 	clz	r0, r0
    9130:	0940      	lsrs	r0, r0, #5
    9132:	0080      	lsls	r0, r0, #2
    9134:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    9136:	2b01      	cmp	r3, #1
    9138:	d105      	bne.n	9146 <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    913a:	6803      	ldr	r3, [r0, #0]
		evt = EVT_RESET;
    913c:	2b00      	cmp	r3, #0
    913e:	bf0c      	ite	eq
    9140:	2000      	moveq	r0, #0
    9142:	2005      	movne	r0, #5
    9144:	4770      	bx	lr
	int evt = EVT_NOP;
    9146:	2000      	movs	r0, #0
}
    9148:	4770      	bx	lr

0000914a <validate_args>:
{
    914a:	b510      	push	{r4, lr}
    914c:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    914e:	b100      	cbz	r0, 9152 <validate_args+0x8>
    9150:	b911      	cbnz	r1, 9158 <validate_args+0xe>
		return -EINVAL;
    9152:	f06f 0015 	mvn.w	r0, #21
}
    9156:	bd10      	pop	{r4, pc}
	int rv = sys_notify_validate(&cli->notify);
    9158:	1d08      	adds	r0, r1, #4
    915a:	f000 f82f 	bl	91bc <sys_notify_validate>
	if ((rv == 0)
    915e:	2800      	cmp	r0, #0
    9160:	d1f9      	bne.n	9156 <validate_args+0xc>
	    && ((cli->notify.flags
    9162:	68a3      	ldr	r3, [r4, #8]
    9164:	2b03      	cmp	r3, #3
    9166:	d9f6      	bls.n	9156 <validate_args+0xc>
    9168:	e7f3      	b.n	9152 <validate_args+0x8>

0000916a <notify_one>:
{
    916a:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    916e:	460d      	mov	r5, r1
    9170:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    9172:	4619      	mov	r1, r3
    9174:	1d28      	adds	r0, r5, #4
{
    9176:	4690      	mov	r8, r2
    9178:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    917a:	f7f8 f86f 	bl	125c <sys_notify_finalize>
	if (cb) {
    917e:	4604      	mov	r4, r0
    9180:	b138      	cbz	r0, 9192 <notify_one+0x28>
		cb(mgr, cli, state, res);
    9182:	4633      	mov	r3, r6
    9184:	4642      	mov	r2, r8
    9186:	4629      	mov	r1, r5
    9188:	4638      	mov	r0, r7
    918a:	46a4      	mov	ip, r4
}
    918c:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    9190:	4760      	bx	ip
}
    9192:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00009196 <onoff_manager_init>:
{
    9196:	b538      	push	{r3, r4, r5, lr}
    9198:	460c      	mov	r4, r1
	if ((mgr == NULL)
    919a:	4605      	mov	r5, r0
    919c:	b158      	cbz	r0, 91b6 <onoff_manager_init+0x20>
	    || (transitions == NULL)
    919e:	b151      	cbz	r1, 91b6 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    91a0:	680b      	ldr	r3, [r1, #0]
    91a2:	b143      	cbz	r3, 91b6 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    91a4:	684b      	ldr	r3, [r1, #4]
    91a6:	b133      	cbz	r3, 91b6 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    91a8:	2220      	movs	r2, #32
    91aa:	2100      	movs	r1, #0
    91ac:	f000 fa3b 	bl	9626 <memset>
	return 0;
    91b0:	2000      	movs	r0, #0
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    91b2:	612c      	str	r4, [r5, #16]
}
    91b4:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    91b6:	f06f 0015 	mvn.w	r0, #21
    91ba:	e7fb      	b.n	91b4 <onoff_manager_init+0x1e>

000091bc <sys_notify_validate>:
	if (notify == NULL) {
    91bc:	4603      	mov	r3, r0
    91be:	b158      	cbz	r0, 91d8 <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    91c0:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    91c2:	f002 0203 	and.w	r2, r2, #3
	switch (sys_notify_get_method(notify)) {
    91c6:	2a01      	cmp	r2, #1
    91c8:	d003      	beq.n	91d2 <sys_notify_validate+0x16>
    91ca:	2a03      	cmp	r2, #3
    91cc:	d104      	bne.n	91d8 <sys_notify_validate+0x1c>
		if (notify->method.callback == NULL) {
    91ce:	6802      	ldr	r2, [r0, #0]
    91d0:	b112      	cbz	r2, 91d8 <sys_notify_validate+0x1c>
		notify->result = 0;
    91d2:	2000      	movs	r0, #0
    91d4:	6098      	str	r0, [r3, #8]
    91d6:	4770      	bx	lr
    91d8:	f06f 0015 	mvn.w	r0, #21
}
    91dc:	4770      	bx	lr

000091de <encode_uint>:
{
    91de:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    91e2:	469a      	mov	sl, r3
	bool upcase = isupper((int)conv->specifier);
    91e4:	78d3      	ldrb	r3, [r2, #3]
{
    91e6:	4680      	mov	r8, r0
	switch (specifier) {
    91e8:	2b6f      	cmp	r3, #111	; 0x6f
{
    91ea:	460f      	mov	r7, r1
    91ec:	4615      	mov	r5, r2
	return (int)(((unsigned)(a)-(unsigned)'A') < 26U);
    91ee:	f1a3 0b41 	sub.w	fp, r3, #65	; 0x41
	switch (specifier) {
    91f2:	d029      	beq.n	9248 <encode_uint+0x6a>
    91f4:	d824      	bhi.n	9240 <encode_uint+0x62>
		return 10;
    91f6:	2b58      	cmp	r3, #88	; 0x58
    91f8:	bf0c      	ite	eq
    91fa:	2610      	moveq	r6, #16
    91fc:	260a      	movne	r6, #10
	char *bp = bps + (bpe - bps);
    91fe:	f8dd 9028 	ldr.w	r9, [sp, #40]	; 0x28
		unsigned int lsv = (unsigned int)(value % radix);
    9202:	4632      	mov	r2, r6
    9204:	2300      	movs	r3, #0
    9206:	4640      	mov	r0, r8
    9208:	4639      	mov	r1, r7
    920a:	f7f6 ffa3 	bl	154 <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    920e:	2a09      	cmp	r2, #9
    9210:	b2d4      	uxtb	r4, r2
    9212:	d81e      	bhi.n	9252 <encode_uint+0x74>
    9214:	3430      	adds	r4, #48	; 0x30
	} while ((value != 0) && (bps < bp));
    9216:	45b0      	cmp	r8, r6
		*--bp = (lsv <= 9) ? ('0' + lsv)
    9218:	b2e4      	uxtb	r4, r4
	} while ((value != 0) && (bps < bp));
    921a:	f177 0700 	sbcs.w	r7, r7, #0
		*--bp = (lsv <= 9) ? ('0' + lsv)
    921e:	f809 4d01 	strb.w	r4, [r9, #-1]!
	} while ((value != 0) && (bps < bp));
    9222:	d301      	bcc.n	9228 <encode_uint+0x4a>
    9224:	45d1      	cmp	r9, sl
    9226:	d811      	bhi.n	924c <encode_uint+0x6e>
	if (conv->flag_hash) {
    9228:	782b      	ldrb	r3, [r5, #0]
    922a:	069b      	lsls	r3, r3, #26
    922c:	d505      	bpl.n	923a <encode_uint+0x5c>
		if (radix == 8) {
    922e:	2e08      	cmp	r6, #8
    9230:	d115      	bne.n	925e <encode_uint+0x80>
			conv->altform_0 = true;
    9232:	78ab      	ldrb	r3, [r5, #2]
    9234:	f043 0308 	orr.w	r3, r3, #8
			conv->altform_0c = true;
    9238:	70ab      	strb	r3, [r5, #2]
}
    923a:	4648      	mov	r0, r9
    923c:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	switch (specifier) {
    9240:	f003 03f7 	and.w	r3, r3, #247	; 0xf7
		return 10;
    9244:	2b70      	cmp	r3, #112	; 0x70
    9246:	e7d7      	b.n	91f8 <encode_uint+0x1a>
	switch (specifier) {
    9248:	2608      	movs	r6, #8
    924a:	e7d8      	b.n	91fe <encode_uint+0x20>
		value /= radix;
    924c:	4680      	mov	r8, r0
    924e:	460f      	mov	r7, r1
    9250:	e7d7      	b.n	9202 <encode_uint+0x24>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    9252:	f1bb 0f19 	cmp.w	fp, #25
    9256:	bf94      	ite	ls
    9258:	3437      	addls	r4, #55	; 0x37
    925a:	3457      	addhi	r4, #87	; 0x57
    925c:	e7db      	b.n	9216 <encode_uint+0x38>
		} else if (radix == 16) {
    925e:	2e10      	cmp	r6, #16
    9260:	d1eb      	bne.n	923a <encode_uint+0x5c>
			conv->altform_0c = true;
    9262:	78ab      	ldrb	r3, [r5, #2]
    9264:	f043 0310 	orr.w	r3, r3, #16
    9268:	e7e6      	b.n	9238 <encode_uint+0x5a>

0000926a <outs>:
{
    926a:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    926e:	4607      	mov	r7, r0
    9270:	4688      	mov	r8, r1
    9272:	4615      	mov	r5, r2
    9274:	461e      	mov	r6, r3
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    9276:	4614      	mov	r4, r2
    9278:	42b4      	cmp	r4, r6
    927a:	d305      	bcc.n	9288 <outs+0x1e>
    927c:	b10e      	cbz	r6, 9282 <outs+0x18>
	return (int)count;
    927e:	1b60      	subs	r0, r4, r5
    9280:	e008      	b.n	9294 <outs+0x2a>
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    9282:	7823      	ldrb	r3, [r4, #0]
    9284:	2b00      	cmp	r3, #0
    9286:	d0fa      	beq.n	927e <outs+0x14>
		int rc = out((int)*sp++, ctx);
    9288:	4641      	mov	r1, r8
    928a:	f814 0b01 	ldrb.w	r0, [r4], #1
    928e:	47b8      	blx	r7
		if (rc < 0) {
    9290:	2800      	cmp	r0, #0
    9292:	daf1      	bge.n	9278 <outs+0xe>
}
    9294:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00009298 <assert_post_action>:
	if (k_is_user_context()) {
		k_oops();
	}
#endif

	k_panic();
    9298:	4040      	eors	r0, r0
    929a:	f380 8811 	msr	BASEPRI, r0
    929e:	f04f 0004 	mov.w	r0, #4
    92a2:	df02      	svc	2
}
    92a4:	4770      	bx	lr

000092a6 <assert_print>:

void assert_print(const char *fmt, ...)
{
    92a6:	b40f      	push	{r0, r1, r2, r3}
    92a8:	b507      	push	{r0, r1, r2, lr}
    92aa:	a904      	add	r1, sp, #16
    92ac:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    92b0:	9101      	str	r1, [sp, #4]

	vprintk(fmt, ap);
    92b2:	f7ff ff08 	bl	90c6 <vprintk>

	va_end(ap);
}
    92b6:	b003      	add	sp, #12
    92b8:	f85d eb04 	ldr.w	lr, [sp], #4
    92bc:	b004      	add	sp, #16
    92be:	4770      	bx	lr

000092c0 <free_space>:
	if (buffer->rd_idx > buffer->tmp_wr_idx) {
    92c0:	68c3      	ldr	r3, [r0, #12]
    92c2:	6802      	ldr	r2, [r0, #0]
    92c4:	4293      	cmp	r3, r2
    92c6:	d904      	bls.n	92d2 <free_space+0x12>
		*res =  buffer->rd_idx - buffer->tmp_wr_idx - 1;
    92c8:	3b01      	subs	r3, #1
    92ca:	1a9a      	subs	r2, r3, r2
		return false;
    92cc:	2000      	movs	r0, #0
		*res = buffer->size - buffer->tmp_wr_idx - 1;
    92ce:	600a      	str	r2, [r1, #0]
}
    92d0:	4770      	bx	lr
		*res = buffer->size - buffer->tmp_wr_idx - 1;
    92d2:	6a40      	ldr	r0, [r0, #36]	; 0x24
	} else if (!buffer->rd_idx) {
    92d4:	b913      	cbnz	r3, 92dc <free_space+0x1c>
		*res = buffer->size - buffer->tmp_wr_idx - 1;
    92d6:	3801      	subs	r0, #1
    92d8:	1a82      	subs	r2, r0, r2
		return false;
    92da:	e7f7      	b.n	92cc <free_space+0xc>
	*res = buffer->size - buffer->tmp_wr_idx;
    92dc:	1a82      	subs	r2, r0, r2
	return true;
    92de:	2001      	movs	r0, #1
    92e0:	e7f5      	b.n	92ce <free_space+0xe>

000092e2 <get_usage>:
{
    92e2:	b513      	push	{r0, r1, r4, lr}
	if (free_space(buffer, &f)) {
    92e4:	a901      	add	r1, sp, #4
{
    92e6:	4604      	mov	r4, r0
	if (free_space(buffer, &f)) {
    92e8:	f7ff ffea 	bl	92c0 <free_space>
    92ec:	b120      	cbz	r0, 92f8 <get_usage+0x16>
		f += (buffer->rd_idx - 1);
    92ee:	9b01      	ldr	r3, [sp, #4]
    92f0:	68e2      	ldr	r2, [r4, #12]
    92f2:	3b01      	subs	r3, #1
    92f4:	4413      	add	r3, r2
    92f6:	9301      	str	r3, [sp, #4]
	return buffer->size - 1 - f;
    92f8:	6a60      	ldr	r0, [r4, #36]	; 0x24
    92fa:	9b01      	ldr	r3, [sp, #4]
    92fc:	1ac0      	subs	r0, r0, r3
}
    92fe:	3801      	subs	r0, #1
    9300:	b002      	add	sp, #8
    9302:	bd10      	pop	{r4, pc}

00009304 <idx_inc>:
{
    9304:	b510      	push	{r4, lr}
    9306:	4604      	mov	r4, r0
	uint32_t i = idx + val;
    9308:	1888      	adds	r0, r1, r2
	if (buffer->flags & MPSC_PBUF_SIZE_POW2) {
    930a:	6922      	ldr	r2, [r4, #16]
		return i & (buffer->size - 1);
    930c:	6a63      	ldr	r3, [r4, #36]	; 0x24
	if (buffer->flags & MPSC_PBUF_SIZE_POW2) {
    930e:	07d2      	lsls	r2, r2, #31
    9310:	d502      	bpl.n	9318 <idx_inc+0x14>
		return i & (buffer->size - 1);
    9312:	3b01      	subs	r3, #1
    9314:	4018      	ands	r0, r3
}
    9316:	bd10      	pop	{r4, pc}
	return (i >= buffer->size) ? i - buffer->size : i;
    9318:	4298      	cmp	r0, r3
    931a:	bf28      	it	cs
    931c:	1ac0      	subcs	r0, r0, r3
    931e:	e7fa      	b.n	9316 <idx_inc+0x12>

00009320 <add_skip_item>:
{
    9320:	b538      	push	{r3, r4, r5, lr}
    9322:	460d      	mov	r5, r1
	buffer->buf[buffer->tmp_wr_idx] = skip.raw;
    9324:	6a02      	ldr	r2, [r0, #32]
	union mpsc_pbuf_generic skip = {
    9326:	008b      	lsls	r3, r1, #2
	buffer->buf[buffer->tmp_wr_idx] = skip.raw;
    9328:	6801      	ldr	r1, [r0, #0]
	union mpsc_pbuf_generic skip = {
    932a:	f043 0302 	orr.w	r3, r3, #2
	buffer->buf[buffer->tmp_wr_idx] = skip.raw;
    932e:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
	buffer->tmp_wr_idx = idx_inc(buffer, buffer->tmp_wr_idx, wlen);
    9332:	6801      	ldr	r1, [r0, #0]
    9334:	462a      	mov	r2, r5
{
    9336:	4604      	mov	r4, r0
	buffer->tmp_wr_idx = idx_inc(buffer, buffer->tmp_wr_idx, wlen);
    9338:	f7ff ffe4 	bl	9304 <idx_inc>
	buffer->wr_idx = idx_inc(buffer, buffer->wr_idx, wlen);
    933c:	6861      	ldr	r1, [r4, #4]
	buffer->tmp_wr_idx = idx_inc(buffer, buffer->tmp_wr_idx, wlen);
    933e:	6020      	str	r0, [r4, #0]
	buffer->wr_idx = idx_inc(buffer, buffer->wr_idx, wlen);
    9340:	462a      	mov	r2, r5
    9342:	4620      	mov	r0, r4
    9344:	f7ff ffde 	bl	9304 <idx_inc>
    9348:	6060      	str	r0, [r4, #4]
}
    934a:	bd38      	pop	{r3, r4, r5, pc}

0000934c <max_utilization_update>:
{
    934c:	b538      	push	{r3, r4, r5, lr}
	if (!(buffer->flags & MPSC_PBUF_MAX_UTILIZATION)) {
    934e:	6903      	ldr	r3, [r0, #16]
{
    9350:	4604      	mov	r4, r0
	if (!(buffer->flags & MPSC_PBUF_MAX_UTILIZATION)) {
    9352:	075b      	lsls	r3, r3, #29
    9354:	d506      	bpl.n	9364 <max_utilization_update+0x18>
	buffer->max_usage = MAX(buffer->max_usage, get_usage(buffer));
    9356:	6a85      	ldr	r5, [r0, #40]	; 0x28
    9358:	f7ff ffc3 	bl	92e2 <get_usage>
    935c:	4285      	cmp	r5, r0
    935e:	bf2c      	ite	cs
    9360:	62a5      	strcs	r5, [r4, #40]	; 0x28
    9362:	62a0      	strcc	r0, [r4, #40]	; 0x28
}
    9364:	bd38      	pop	{r3, r4, r5, pc}

00009366 <drop_item_locked>:
{
    9366:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    936a:	461f      	mov	r7, r3
	*user_packet = false;
    936c:	2300      	movs	r3, #0
    936e:	703b      	strb	r3, [r7, #0]
	item = (union mpsc_pbuf_generic *)&buffer->buf[buffer->rd_idx];
    9370:	f8d0 a00c 	ldr.w	sl, [r0, #12]
    9374:	f8d0 9020 	ldr.w	r9, [r0, #32]
{
    9378:	4604      	mov	r4, r0
	if (item->hdr.busy && !item->hdr.valid) {
    937a:	f819 302a 	ldrb.w	r3, [r9, sl, lsl #2]
{
    937e:	468b      	mov	fp, r1
	if (item->hdr.busy && !item->hdr.valid) {
    9380:	f003 0303 	and.w	r3, r3, #3
    9384:	2b02      	cmp	r3, #2
{
    9386:	4690      	mov	r8, r2
	item = (union mpsc_pbuf_generic *)&buffer->buf[buffer->rd_idx];
    9388:	eb09 068a 	add.w	r6, r9, sl, lsl #2
	if (item->hdr.busy && !item->hdr.valid) {
    938c:	d103      	bne.n	9396 <drop_item_locked+0x30>
		return item->skip.len;
    938e:	f859 502a 	ldr.w	r5, [r9, sl, lsl #2]
	rd_wlen = skip_wlen ? skip_wlen : buffer->get_wlen(item);
    9392:	08ad      	lsrs	r5, r5, #2
    9394:	d12e      	bne.n	93f4 <drop_item_locked+0x8e>
    9396:	4630      	mov	r0, r6
    9398:	69e3      	ldr	r3, [r4, #28]
    939a:	4798      	blx	r3
    939c:	4605      	mov	r5, r0
	} else if (allow_drop) {
    939e:	f1b8 0f00 	cmp.w	r8, #0
    93a2:	d038      	beq.n	9416 <drop_item_locked+0xb0>
		if (item->hdr.busy) {
    93a4:	f819 302a 	ldrb.w	r3, [r9, sl, lsl #2]
    93a8:	079b      	lsls	r3, r3, #30
    93aa:	d531      	bpl.n	9410 <drop_item_locked+0xaa>
			add_skip_item(buffer, free_wlen + 1);
    93ac:	4620      	mov	r0, r4
    93ae:	f10b 0101 	add.w	r1, fp, #1
    93b2:	f7ff ffb5 	bl	9320 <add_skip_item>
			buffer->wr_idx = idx_inc(buffer, buffer->wr_idx, rd_wlen);
    93b6:	6861      	ldr	r1, [r4, #4]
    93b8:	462a      	mov	r2, r5
    93ba:	4620      	mov	r0, r4
    93bc:	f7ff ffa2 	bl	9304 <idx_inc>
			buffer->tmp_wr_idx = idx_inc(buffer, buffer->tmp_wr_idx, rd_wlen);
    93c0:	6821      	ldr	r1, [r4, #0]
    93c2:	462a      	mov	r2, r5
			buffer->wr_idx = idx_inc(buffer, buffer->wr_idx, rd_wlen);
    93c4:	6060      	str	r0, [r4, #4]
			buffer->tmp_wr_idx = idx_inc(buffer, buffer->tmp_wr_idx, rd_wlen);
    93c6:	4620      	mov	r0, r4
    93c8:	f7ff ff9c 	bl	9304 <idx_inc>
			uint32_t next_rd_idx = idx_inc(buffer, buffer->rd_idx, rd_wlen);
    93cc:	462a      	mov	r2, r5
			buffer->tmp_wr_idx = idx_inc(buffer, buffer->tmp_wr_idx, rd_wlen);
    93ce:	6020      	str	r0, [r4, #0]
			uint32_t next_rd_idx = idx_inc(buffer, buffer->rd_idx, rd_wlen);
    93d0:	68e1      	ldr	r1, [r4, #12]
    93d2:	4620      	mov	r0, r4
    93d4:	f7ff ff96 	bl	9304 <idx_inc>
			item = (union mpsc_pbuf_generic *)&buffer->buf[next_rd_idx];
    93d8:	6a23      	ldr	r3, [r4, #32]
	if (item->hdr.busy && !item->hdr.valid) {
    93da:	f813 2020 	ldrb.w	r2, [r3, r0, lsl #2]
			item = (union mpsc_pbuf_generic *)&buffer->buf[next_rd_idx];
    93de:	eb03 0680 	add.w	r6, r3, r0, lsl #2
	if (item->hdr.busy && !item->hdr.valid) {
    93e2:	f002 0203 	and.w	r2, r2, #3
    93e6:	2a02      	cmp	r2, #2
    93e8:	d10e      	bne.n	9408 <drop_item_locked+0xa2>
		return item->skip.len;
    93ea:	f853 3020 	ldr.w	r3, [r3, r0, lsl #2]
			if (skip_wlen) {
    93ee:	089b      	lsrs	r3, r3, #2
    93f0:	d00a      	beq.n	9408 <drop_item_locked+0xa2>
				rd_wlen += skip_wlen;
    93f2:	441d      	add	r5, r3
		buffer->rd_idx = idx_inc(buffer, buffer->rd_idx, rd_wlen);
    93f4:	68e1      	ldr	r1, [r4, #12]
    93f6:	462a      	mov	r2, r5
    93f8:	4620      	mov	r0, r4
    93fa:	f7ff ff83 	bl	9304 <idx_inc>
		buffer->tmp_rd_idx = buffer->rd_idx;
    93fe:	e9c4 0002 	strd	r0, r0, [r4, #8]
}
    9402:	4630      	mov	r0, r6
    9404:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
				rd_wlen += buffer->get_wlen(item);
    9408:	4630      	mov	r0, r6
    940a:	69e3      	ldr	r3, [r4, #28]
    940c:	4798      	blx	r3
    940e:	4405      	add	r5, r0
			*user_packet = true;
    9410:	2301      	movs	r3, #1
    9412:	703b      	strb	r3, [r7, #0]
	if (allow_drop) {
    9414:	e7ee      	b.n	93f4 <drop_item_locked+0x8e>
		item = NULL;
    9416:	4646      	mov	r6, r8
	return item;
    9418:	e7f3      	b.n	9402 <drop_item_locked+0x9c>

0000941a <mpsc_pbuf_is_pending>:
	if (buffer->tmp_rd_idx <= buffer->wr_idx) {
    941a:	e9d0 2301 	ldrd	r2, r3, [r0, #4]
    941e:	4293      	cmp	r3, r2
	*res = buffer->size - buffer->tmp_rd_idx;
    9420:	bf88      	it	hi
    9422:	6a42      	ldrhi	r2, [r0, #36]	; 0x24
    9424:	1ad3      	subs	r3, r2, r3
	uint32_t a;

	(void)available(buffer, &a);

	return a ? true : false;
}
    9426:	1e18      	subs	r0, r3, #0
    9428:	bf18      	it	ne
    942a:	2001      	movne	r0, #1
    942c:	4770      	bx	lr

0000942e <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_WARN_DEPRECATED, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_ENFORCE_ZEPHYR_STDINT, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    942e:	4770      	bx	lr

00009430 <pm_state_exit_post_ops>:
    9430:	2300      	movs	r3, #0
    9432:	f383 8811 	msr	BASEPRI, r3
    9436:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
    943a:	4770      	bx	lr

0000943c <log_msg_generic_get_wlen>:
	return msg->generic.type == Z_LOG_MSG2_LOG;
    943c:	7803      	ldrb	r3, [r0, #0]
	if (z_log_item_is_msg(generic_msg)) {
    943e:	075b      	lsls	r3, r3, #29
    9440:	d40b      	bmi.n	945a <log_msg_generic_get_wlen+0x1e>
	return Z_LOG_MSG2_ALIGNED_WLEN(desc.package_len, desc.data_len);
    9442:	6803      	ldr	r3, [r0, #0]
    9444:	8842      	ldrh	r2, [r0, #2]
    9446:	f3c3 2349 	ubfx	r3, r3, #9, #10
    944a:	f3c2 02cb 	ubfx	r2, r2, #3, #12
    944e:	1898      	adds	r0, r3, r2
    9450:	3017      	adds	r0, #23
    9452:	f020 0007 	bic.w	r0, r0, #7
    9456:	0880      	lsrs	r0, r0, #2
		return log_msg_get_total_wlen(msg->hdr.desc);
    9458:	4770      	bx	lr
	return 0;
    945a:	2000      	movs	r0, #0
}
    945c:	4770      	bx	lr

0000945e <dummy_timestamp>:
}
    945e:	2000      	movs	r0, #0
    9460:	4770      	bx	lr

00009462 <default_get_timestamp>:
    9462:	f000 b9f1 	b.w	9848 <sys_clock_cycle_get_32>

00009466 <atomic_inc>:
{
    9466:	4603      	mov	r3, r0
}
    9468:	e8d3 0fef 	ldaex	r0, [r3]
    946c:	1c42      	adds	r2, r0, #1
    946e:	e8c3 2fe1 	stlex	r1, r2, [r3]
    9472:	2900      	cmp	r1, #0
    9474:	d1f8      	bne.n	9468 <atomic_inc+0x2>
    9476:	4770      	bx	lr

00009478 <enable_logger>:
				COND_CODE_1(CONFIG_LOG_PROCESS_THREAD,
					K_MSEC(CONFIG_LOG_PROCESS_THREAD_STARTUP_DELAY_MS),
					K_NO_WAIT));
		k_thread_name_set(&logging_thread, "logging");
	} else {
		(void)z_log_init(false, false);
    9478:	2100      	movs	r1, #0
{
    947a:	b508      	push	{r3, lr}
		(void)z_log_init(false, false);
    947c:	4608      	mov	r0, r1
    947e:	f7f8 ff33 	bl	22e8 <z_log_init.isra.0>
	}

	return 0;
}
    9482:	2000      	movs	r0, #0
    9484:	bd08      	pop	{r3, pc}

00009486 <z_log_vprintk>:
{
    9486:	b51f      	push	{r0, r1, r2, r3, r4, lr}
		va_end(parm7.val);
		return;
	}
#endif
	compiler_barrier();
	z_impl_z_log_msg_runtime_vcreate(domain_id, source, level, data, dlen, package_flags, fmt, ap);
    9488:	2300      	movs	r3, #0
    948a:	e9cd 0102 	strd	r0, r1, [sp, #8]
    948e:	461a      	mov	r2, r3
    9490:	4619      	mov	r1, r3
    9492:	4618      	mov	r0, r3
    9494:	e9cd 3300 	strd	r3, r3, [sp]
    9498:	f7f9 fa2c 	bl	28f4 <z_impl_z_log_msg_runtime_vcreate>
}
    949c:	b005      	add	sp, #20
    949e:	f85d fb04 	ldr.w	pc, [sp], #4

000094a2 <z_log_notify_drop>:
				     const union mpsc_pbuf_generic *item)
{
	ARG_UNUSED(buffer);
	ARG_UNUSED(item);

	z_log_dropped(true);
    94a2:	2001      	movs	r0, #1
    94a4:	f7f8 bfce 	b.w	2444 <z_log_dropped>

000094a8 <z_log_get_tag>:
}
    94a8:	2000      	movs	r0, #0
    94aa:	4770      	bx	lr

000094ac <z_cbprintf_cpy>:
{
    94ac:	b570      	push	{r4, r5, r6, lr}
	if ((desc->size - desc->off) < len) {
    94ae:	e9d2 3601 	ldrd	r3, r6, [r2, #4]
    94b2:	1b9b      	subs	r3, r3, r6
    94b4:	428b      	cmp	r3, r1
{
    94b6:	460c      	mov	r4, r1
    94b8:	4615      	mov	r5, r2
	if ((desc->size - desc->off) < len) {
    94ba:	d30a      	bcc.n	94d2 <z_cbprintf_cpy+0x26>
	memcpy(&((uint8_t *)desc->buf)[desc->off], buf, len);
    94bc:	6813      	ldr	r3, [r2, #0]
    94be:	460a      	mov	r2, r1
    94c0:	4601      	mov	r1, r0
    94c2:	1998      	adds	r0, r3, r6
    94c4:	f000 f8a4 	bl	9610 <memcpy>
	return len;
    94c8:	4620      	mov	r0, r4
	desc->off += len;
    94ca:	68ab      	ldr	r3, [r5, #8]
    94cc:	4423      	add	r3, r4
    94ce:	60ab      	str	r3, [r5, #8]
}
    94d0:	bd70      	pop	{r4, r5, r6, pc}
		return -ENOSPC;
    94d2:	f06f 001b 	mvn.w	r0, #27
    94d6:	e7fb      	b.n	94d0 <z_cbprintf_cpy+0x24>

000094d8 <z_log_msg_finalize>:
{
    94d8:	b570      	push	{r4, r5, r6, lr}
    94da:	460e      	mov	r6, r1
    94dc:	4615      	mov	r5, r2
    94de:	4619      	mov	r1, r3
	if (!msg) {
    94e0:	4604      	mov	r4, r0
    94e2:	b918      	cbnz	r0, 94ec <z_log_msg_finalize+0x14>
}
    94e4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_log_dropped(false);
    94e8:	f7f8 bfac 	b.w	2444 <z_log_dropped>
	if (data) {
    94ec:	b13b      	cbz	r3, 94fe <z_log_msg_finalize+0x26>
		uint8_t *d = msg->data + desc.package_len;
    94ee:	f3c2 2349 	ubfx	r3, r2, #9, #10
    94f2:	3010      	adds	r0, #16
		memcpy(d, data, desc.data_len);
    94f4:	f3c2 42cb 	ubfx	r2, r2, #19, #12
    94f8:	4418      	add	r0, r3
    94fa:	f000 f889 	bl	9610 <memcpy>
	msg->hdr.source = source;
    94fe:	e9c4 5600 	strd	r5, r6, [r4]
	z_log_msg_commit(msg);
    9502:	4620      	mov	r0, r4
}
    9504:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	z_log_msg_commit(msg);
    9508:	f7f9 b90e 	b.w	2728 <z_log_msg_commit>

0000950c <buffer_write>:
{
    950c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    950e:	4606      	mov	r6, r0
    9510:	460d      	mov	r5, r1
    9512:	4614      	mov	r4, r2
    9514:	461f      	mov	r7, r3
		processed = outf(buf, len, ctx);
    9516:	4621      	mov	r1, r4
    9518:	4628      	mov	r0, r5
    951a:	463a      	mov	r2, r7
    951c:	47b0      	blx	r6
	} while (len != 0);
    951e:	1a24      	subs	r4, r4, r0
		buf += processed;
    9520:	4405      	add	r5, r0
	} while (len != 0);
    9522:	d1f8      	bne.n	9516 <buffer_write+0xa>
}
    9524:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00009526 <cbvprintf>:
{
    9526:	b513      	push	{r0, r1, r4, lr}
	return z_cbvprintf_impl(out, ctx, format, ap, 0);
    9528:	2400      	movs	r4, #0
    952a:	9400      	str	r4, [sp, #0]
    952c:	f7f7 feb6 	bl	129c <z_cbvprintf_impl>
}
    9530:	b002      	add	sp, #8
    9532:	bd10      	pop	{r4, pc}

00009534 <log_output_flush>:
{
    9534:	b510      	push	{r4, lr}
		     output->control_block->offset,
    9536:	6842      	ldr	r2, [r0, #4]
{
    9538:	4604      	mov	r4, r0
	buffer_write(output->func, output->buf,
    953a:	e9d2 2300 	ldrd	r2, r3, [r2]
    953e:	6881      	ldr	r1, [r0, #8]
    9540:	6800      	ldr	r0, [r0, #0]
    9542:	f7ff ffe3 	bl	950c <buffer_write>
	output->control_block->offset = 0;
    9546:	2200      	movs	r2, #0
    9548:	6863      	ldr	r3, [r4, #4]
    954a:	601a      	str	r2, [r3, #0]
}
    954c:	bd10      	pop	{r4, pc}

0000954e <cr_out_func>:
	if (c == '\n') {
    954e:	280a      	cmp	r0, #10
{
    9550:	b538      	push	{r3, r4, r5, lr}
    9552:	4604      	mov	r4, r0
    9554:	460d      	mov	r5, r1
	if (c == '\n') {
    9556:	d102      	bne.n	955e <cr_out_func+0x10>
		out_func((int)'\r', ctx);
    9558:	200d      	movs	r0, #13
    955a:	f7f9 fa4f 	bl	29fc <out_func>
	out_func(c, ctx);
    955e:	4629      	mov	r1, r5
    9560:	4620      	mov	r0, r4
    9562:	f7f9 fa4b 	bl	29fc <out_func>
}
    9566:	2000      	movs	r0, #0
    9568:	bd38      	pop	{r3, r4, r5, pc}

0000956a <abort_function>:
	sys_reboot(SYS_REBOOT_WARM);
    956a:	2000      	movs	r0, #0
{
    956c:	b508      	push	{r3, lr}
	sys_reboot(SYS_REBOOT_WARM);
    956e:	f7f8 fc7d 	bl	1e6c <sys_reboot>

00009572 <z_do_kernel_oops>:
 *
 * @param esf exception frame
 * @param callee_regs Callee-saved registers (R4-R11)
 */
void z_do_kernel_oops(const z_arch_esf_t *esf, _callee_saved_t *callee_regs)
{
    9572:	4601      	mov	r1, r0
	}

#endif /* CONFIG_USERSPACE */

#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	z_arm_fatal_error(reason, esf);
    9574:	6800      	ldr	r0, [r0, #0]
    9576:	f7f9 bf5d 	b.w	3434 <z_arm_fatal_error>

0000957a <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    957a:	2100      	movs	r1, #0
    957c:	2001      	movs	r0, #1
    957e:	f7f9 bf59 	b.w	3434 <z_arm_fatal_error>

00009582 <z_arm_nmi>:
 * Simply call what is installed in 'static void(*handler)(void)'.
 *
 */

void z_arm_nmi(void)
{
    9582:	b508      	push	{r3, lr}
	handler();
    9584:	f7fa f81e 	bl	35c4 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    9588:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    958c:	f7fa b8e0 	b.w	3750 <z_arm_exc_exit>

00009590 <configure_builtin_stack_guard>:
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    9590:	6e43      	ldr	r3, [r0, #100]	; 0x64
    9592:	f383 880b 	msr	PSPLIM, r3
}
    9596:	4770      	bx	lr

00009598 <z_log_msg_static_create.constprop.0>:
	z_impl_z_log_msg_static_create(source, desc, package, data);
    9598:	2300      	movs	r3, #0
    959a:	f7f9 b945 	b.w	2828 <z_impl_z_log_msg_static_create>

0000959e <arm_cmse_mpu_region_get>:
__CMSE_TT_ASM ()

__extension__ static __inline __attribute__ ((__always_inline__))
cmse_address_info_t
cmse_TT (void *__p)
__CMSE_TT_ASM ()
    959e:	e840 f300 	tt	r3, r0
int arm_cmse_mpu_region_get(uint32_t addr)
{
	cmse_address_info_t addr_info =	cmse_TT((void *)addr);

	if (addr_info.flags.mpu_region_valid) {
		return addr_info.flags.mpu_region;
    95a2:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    95a6:	b2d8      	uxtb	r0, r3
	}

	return -EINVAL;
}
    95a8:	bf08      	it	eq
    95aa:	f06f 0015 	mvneq.w	r0, #21
    95ae:	4770      	bx	lr

000095b0 <mpu_configure_region>:
{
    95b0:	b530      	push	{r4, r5, lr}
	p_attr->rbar = attr->rbar &
    95b2:	890a      	ldrh	r2, [r1, #8]
    95b4:	894d      	ldrh	r5, [r1, #10]
	region_conf.base = new_region->start;
    95b6:	680b      	ldr	r3, [r1, #0]
		&new_region->attr, new_region->start, new_region->size);
    95b8:	684c      	ldr	r4, [r1, #4]
    95ba:	f002 021f 	and.w	r2, r2, #31
{
    95be:	b085      	sub	sp, #20
    95c0:	ea42 1245 	orr.w	r2, r2, r5, lsl #5
	region_conf.base = new_region->start;
    95c4:	9300      	str	r3, [sp, #0]
    95c6:	f88d 2008 	strb.w	r2, [sp, #8]
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
    95ca:	f023 031f 	bic.w	r3, r3, #31
    95ce:	1e62      	subs	r2, r4, #1
    95d0:	4413      	add	r3, r2
    95d2:	f023 031f 	bic.w	r3, r3, #31
	if (index > (get_num_regions() - 1U)) {
    95d6:	2807      	cmp	r0, #7
    95d8:	9303      	str	r3, [sp, #12]
    95da:	d904      	bls.n	95e6 <mpu_configure_region+0x36>
}
    95dc:	b005      	add	sp, #20
    95de:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
    95e2:	f7fa bcc7 	b.w	3f74 <region_allocate_and_init.part.0>
	region_init(index, region_conf);
    95e6:	4669      	mov	r1, sp
    95e8:	f7fa fcaa 	bl	3f40 <region_init>
}
    95ec:	b005      	add	sp, #20
    95ee:	bd30      	pop	{r4, r5, pc}

000095f0 <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    95f0:	4603      	mov	r3, r0
	size_t n = 0;
    95f2:	2000      	movs	r0, #0

	while (*s != '\0') {
    95f4:	5c1a      	ldrb	r2, [r3, r0]
    95f6:	b902      	cbnz	r2, 95fa <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    95f8:	4770      	bx	lr
		n++;
    95fa:	3001      	adds	r0, #1
    95fc:	e7fa      	b.n	95f4 <strlen+0x4>

000095fe <strnlen>:
 *
 * @return number of bytes in fixed-size string <s>
 */

size_t strnlen(const char *s, size_t maxlen)
{
    95fe:	4603      	mov	r3, r0
	size_t n = 0;
    9600:	2000      	movs	r0, #0

	while (*s != '\0' && n < maxlen) {
    9602:	5c1a      	ldrb	r2, [r3, r0]
    9604:	b10a      	cbz	r2, 960a <strnlen+0xc>
    9606:	4288      	cmp	r0, r1
    9608:	d100      	bne.n	960c <strnlen+0xe>
		s++;
		n++;
	}

	return n;
}
    960a:	4770      	bx	lr
		n++;
    960c:	3001      	adds	r0, #1
    960e:	e7f8      	b.n	9602 <strnlen+0x4>

00009610 <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n)
{
    9610:	b510      	push	{r4, lr}
    9612:	1e43      	subs	r3, r0, #1
    9614:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
    9616:	4291      	cmp	r1, r2
    9618:	d100      	bne.n	961c <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    961a:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
    961c:	f811 4b01 	ldrb.w	r4, [r1], #1
    9620:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    9624:	e7f7      	b.n	9616 <memcpy+0x6>

00009626 <memset>:

void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
    9626:	4603      	mov	r3, r0
	unsigned char c_byte = (unsigned char)c;
    9628:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
    962a:	4402      	add	r2, r0
    962c:	4293      	cmp	r3, r2
    962e:	d100      	bne.n	9632 <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    9630:	4770      	bx	lr
		*(d_byte++) = c_byte;
    9632:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    9636:	e7f9      	b.n	962c <memset+0x6>

00009638 <_stdout_hook_default>:
}
    9638:	f04f 30ff 	mov.w	r0, #4294967295
    963c:	4770      	bx	lr

0000963e <set_on_state>:
	__asm__ volatile(
    963e:	f04f 0320 	mov.w	r3, #32
    9642:	f3ef 8211 	mrs	r2, BASEPRI
    9646:	f383 8812 	msr	BASEPRI_MAX, r3
    964a:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    964e:	6803      	ldr	r3, [r0, #0]
    9650:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    9654:	f043 0302 	orr.w	r3, r3, #2
    9658:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    965a:	f382 8811 	msr	BASEPRI, r2
    965e:	f3bf 8f6f 	isb	sy
}
    9662:	4770      	bx	lr

00009664 <async_start>:
{
    9664:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    9666:	9f06      	ldr	r7, [sp, #24]
	struct nrf_clock_control_data *data = dev->data;
    9668:	6904      	ldr	r4, [r0, #16]
	return &data->subsys[type];
    966a:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    966c:	f04f 0520 	mov.w	r5, #32
    9670:	f3ef 8611 	mrs	r6, BASEPRI
    9674:	f385 8812 	msr	BASEPRI_MAX, r5
    9678:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    967c:	250c      	movs	r5, #12
    967e:	4369      	muls	r1, r5
    9680:	440c      	add	r4, r1
    9682:	f8d4 5088 	ldr.w	r5, [r4, #136]	; 0x88
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    9686:	f005 0c07 	and.w	ip, r5, #7
    968a:	f1bc 0f01 	cmp.w	ip, #1
    968e:	d10c      	bne.n	96aa <async_start+0x46>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    9690:	f8c4 7088 	str.w	r7, [r4, #136]	; 0x88
	__asm__ volatile(
    9694:	f386 8811 	msr	BASEPRI, r6
    9698:	f3bf 8f6f 	isb	sy
	subdata->user_data = user_data;
    969c:	e9c4 2320 	strd	r2, r3, [r4, #128]	; 0x80
	 get_sub_config(dev, type)->start();
    96a0:	6843      	ldr	r3, [r0, #4]
    96a2:	585b      	ldr	r3, [r3, r1]
    96a4:	4798      	blx	r3
	return 0;
    96a6:	2000      	movs	r0, #0
}
    96a8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    96aa:	f005 05c0 	and.w	r5, r5, #192	; 0xc0
	} else if (current_ctx != ctx) {
    96ae:	42af      	cmp	r7, r5
    96b0:	f386 8811 	msr	BASEPRI, r6
    96b4:	f3bf 8f6f 	isb	sy
		err = -EALREADY;
    96b8:	bf0c      	ite	eq
    96ba:	f06f 0077 	mvneq.w	r0, #119	; 0x77
		err = -EPERM;
    96be:	f04f 30ff 	movne.w	r0, #4294967295
    96c2:	e7f1      	b.n	96a8 <async_start+0x44>

000096c4 <api_start>:
{
    96c4:	b513      	push	{r0, r1, r4, lr}
	return async_start(dev, subsys, cb, user_data, CTX_API);
    96c6:	2480      	movs	r4, #128	; 0x80
    96c8:	9400      	str	r4, [sp, #0]
    96ca:	f7ff ffcb 	bl	9664 <async_start>
}
    96ce:	b002      	add	sp, #8
    96d0:	bd10      	pop	{r4, pc}

000096d2 <onoff_started_callback>:
	return &data->mgr[type];
    96d2:	6900      	ldr	r0, [r0, #16]
    96d4:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    96d6:	eb00 1043 	add.w	r0, r0, r3, lsl #5
    96da:	2100      	movs	r1, #0
    96dc:	4710      	bx	r2

000096de <hfclkaudio_start>:
	nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLKAUDIO);
    96de:	2003      	movs	r0, #3
    96e0:	f7fc ba64 	b.w	5bac <nrfx_clock_start>

000096e4 <hfclk192m_start>:
	nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK192M);
    96e4:	2002      	movs	r0, #2
    96e6:	f7fc ba61 	b.w	5bac <nrfx_clock_start>

000096ea <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    96ea:	2000      	movs	r0, #0
    96ec:	f7fc ba5e 	b.w	5bac <nrfx_clock_start>

000096f0 <hfclkaudio_stop>:
	nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLKAUDIO);
    96f0:	2003      	movs	r0, #3
    96f2:	f7fc bad9 	b.w	5ca8 <nrfx_clock_stop>

000096f6 <hfclk192m_stop>:
	nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK192M);
    96f6:	2002      	movs	r0, #2
    96f8:	f7fc bad6 	b.w	5ca8 <nrfx_clock_stop>

000096fc <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    96fc:	2000      	movs	r0, #0
    96fe:	f7fc bad3 	b.w	5ca8 <nrfx_clock_stop>

00009702 <blocking_start_callback>:
{
    9702:	4610      	mov	r0, r2
	z_impl_k_sem_give(sem);
    9704:	f7fd bd16 	b.w	7134 <z_impl_k_sem_give>

00009708 <api_stop>:
	return stop(dev, subsys, CTX_API);
    9708:	2280      	movs	r2, #128	; 0x80
    970a:	f7fa be5d 	b.w	43c8 <stop>

0000970e <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    970e:	6843      	ldr	r3, [r0, #4]
}
    9710:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    9712:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    9714:	691b      	ldr	r3, [r3, #16]
	*value = nrf_gpio_port_in_read(reg);
    9716:	600b      	str	r3, [r1, #0]
}
    9718:	4770      	bx	lr

0000971a <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    971a:	6843      	ldr	r3, [r0, #4]
	const uint32_t set_mask = value & mask;
    971c:	ea02 0001 	and.w	r0, r2, r1
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    9720:	685b      	ldr	r3, [r3, #4]
	const uint32_t clear_mask = (~set_mask) & mask;
    9722:	ea21 0102 	bic.w	r1, r1, r2
    p_reg->OUTSET = set_mask;
    9726:	6098      	str	r0, [r3, #8]
}
    9728:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    972a:	60d9      	str	r1, [r3, #12]
    972c:	4770      	bx	lr

0000972e <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    972e:	6843      	ldr	r3, [r0, #4]
}
    9730:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    9732:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTSET = set_mask;
    9734:	6099      	str	r1, [r3, #8]
}
    9736:	4770      	bx	lr

00009738 <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    9738:	6843      	ldr	r3, [r0, #4]
}
    973a:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    973c:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTCLR = clr_mask;
    973e:	60d9      	str	r1, [r3, #12]
}
    9740:	4770      	bx	lr

00009742 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    9742:	6843      	ldr	r3, [r0, #4]
    9744:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    9746:	6853      	ldr	r3, [r2, #4]
	const uint32_t set_mask = value & mask;
    9748:	ea21 0003 	bic.w	r0, r1, r3
	const uint32_t clear_mask = (~value) & mask;
    974c:	400b      	ands	r3, r1
    p_reg->OUTSET = set_mask;
    974e:	6090      	str	r0, [r2, #8]
}
    9750:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    9752:	60d3      	str	r3, [r2, #12]
    9754:	4770      	bx	lr

00009756 <uarte_nrfx_config_get>:
{
    9756:	460b      	mov	r3, r1
	struct uarte_nrfx_data *data = dev->data;
    9758:	6902      	ldr	r2, [r0, #16]
	*cfg = data->uart_config;
    975a:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    975e:	e883 0003 	stmia.w	r3, {r0, r1}
}
    9762:	2000      	movs	r0, #0
    9764:	4770      	bx	lr

00009766 <uarte_nrfx_err_check>:
	return config->uarte_regs;
    9766:	6843      	ldr	r3, [r0, #4]
    9768:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    976a:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    976e:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    9772:	4770      	bx	lr

00009774 <uarte_nrfx_poll_in>:
	return config->uarte_regs;
    9774:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = dev->data;
    9776:	6902      	ldr	r2, [r0, #16]
	return config->uarte_regs;
    9778:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    977a:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    977e:	b150      	cbz	r0, 9796 <uarte_nrfx_poll_in+0x22>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    9780:	2000      	movs	r0, #0
	*c = *data->rx_data;
    9782:	6952      	ldr	r2, [r2, #20]
    9784:	7812      	ldrb	r2, [r2, #0]
    9786:	700a      	strb	r2, [r1, #0]
    9788:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    978c:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    9790:	2201      	movs	r2, #1
    9792:	601a      	str	r2, [r3, #0]
	return 0;
    9794:	4770      	bx	lr
		return -1;
    9796:	f04f 30ff 	mov.w	r0, #4294967295
}
    979a:	4770      	bx	lr

0000979c <is_tx_ready.isra.0>:
	return config->uarte_regs;
    979c:	6802      	ldr	r2, [r0, #0]
static bool is_tx_ready(const struct device *dev)
    979e:	4603      	mov	r3, r0
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    97a0:	f8d2 0158 	ldr.w	r0, [r2, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    97a4:	b940      	cbnz	r0, 97b8 <is_tx_ready.isra.0+0x1c>
	bool ppi_endtx = config->flags & UARTE_CFG_FLAG_PPI_ENDTX;
    97a6:	685b      	ldr	r3, [r3, #4]
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    97a8:	079b      	lsls	r3, r3, #30
    97aa:	d406      	bmi.n	97ba <is_tx_ready.isra.0+0x1e>
    97ac:	f8d2 0120 	ldr.w	r0, [r2, #288]	; 0x120
    97b0:	3800      	subs	r0, #0
    97b2:	bf18      	it	ne
    97b4:	2001      	movne	r0, #1
    97b6:	4770      	bx	lr
    97b8:	2001      	movs	r0, #1
}
    97ba:	4770      	bx	lr

000097bc <uarte_nrfx_isr_int>:
	const struct uarte_nrfx_config *config = dev->config;
    97bc:	6842      	ldr	r2, [r0, #4]
	return config->uarte_regs;
    97be:	6813      	ldr	r3, [r2, #0]
    return p_reg->INTENSET & mask;
    97c0:	f8d3 1304 	ldr.w	r1, [r3, #772]	; 0x304
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
    97c4:	05c9      	lsls	r1, r1, #23
    97c6:	d518      	bpl.n	97fa <uarte_nrfx_isr_int+0x3e>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    97c8:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    97cc:	b1a9      	cbz	r1, 97fa <uarte_nrfx_isr_int+0x3e>
	__asm__ volatile(
    97ce:	f04f 0020 	mov.w	r0, #32
    97d2:	f3ef 8111 	mrs	r1, BASEPRI
    97d6:	f380 8812 	msr	BASEPRI_MAX, r0
    97da:	f3bf 8f6f 	isb	sy
    97de:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
    97e2:	b130      	cbz	r0, 97f2 <uarte_nrfx_isr_int+0x36>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    97e4:	2000      	movs	r0, #0
    97e6:	f8c3 0120 	str.w	r0, [r3, #288]	; 0x120
    97ea:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    97ee:	2001      	movs	r0, #1
    97f0:	60d8      	str	r0, [r3, #12]
	__asm__ volatile(
    97f2:	f381 8811 	msr	BASEPRI, r1
    97f6:	f3bf 8f6f 	isb	sy
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    97fa:	6852      	ldr	r2, [r2, #4]
    97fc:	06d2      	lsls	r2, r2, #27
    97fe:	d515      	bpl.n	982c <uarte_nrfx_isr_int+0x70>
	__asm__ volatile(
    9800:	f04f 0120 	mov.w	r1, #32
    9804:	f3ef 8211 	mrs	r2, BASEPRI
    9808:	f381 8812 	msr	BASEPRI_MAX, r1
    980c:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    9810:	f8d3 1158 	ldr.w	r1, [r3, #344]	; 0x158
		if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
    9814:	b111      	cbz	r1, 981c <uarte_nrfx_isr_int+0x60>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    9816:	2100      	movs	r1, #0
    9818:	f8c3 1500 	str.w	r1, [r3, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    981c:	f44f 0180 	mov.w	r1, #4194304	; 0x400000
    9820:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
	__asm__ volatile(
    9824:	f382 8811 	msr	BASEPRI, r2
    9828:	f3bf 8f6f 	isb	sy
}
    982c:	4770      	bx	lr

0000982e <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
    982e:	4770      	bx	lr

00009830 <event_clear>:
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    9830:	2200      	movs	r2, #0
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    9832:	f100 0350 	add.w	r3, r0, #80	; 0x50
    9836:	009b      	lsls	r3, r3, #2
    9838:	b29b      	uxth	r3, r3
    983a:	f103 2350 	add.w	r3, r3, #1342197760	; 0x50005000
    983e:	f503 3380 	add.w	r3, r3, #65536	; 0x10000
    9842:	601a      	str	r2, [r3, #0]
    9844:	681b      	ldr	r3, [r3, #0]
}
    9846:	4770      	bx	lr

00009848 <sys_clock_cycle_get_32>:
{
    9848:	b508      	push	{r3, lr}
	return (uint32_t)z_nrf_rtc_timer_read();
    984a:	f7fb fc1d 	bl	5088 <z_nrf_rtc_timer_read>
}
    984e:	bd08      	pop	{r3, pc}

00009850 <pinctrl_lookup_state>:

#include <zephyr/drivers/pinctrl.h>

int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
			 const struct pinctrl_state **state)
{
    9850:	b530      	push	{r4, r5, lr}
	*state = &config->states[0];
    9852:	6843      	ldr	r3, [r0, #4]
    9854:	6013      	str	r3, [r2, #0]
	while (*state < &config->states[config->state_cnt]) {
    9856:	7a05      	ldrb	r5, [r0, #8]
    9858:	6844      	ldr	r4, [r0, #4]
    985a:	eb04 04c5 	add.w	r4, r4, r5, lsl #3
    985e:	42a3      	cmp	r3, r4
    9860:	d302      	bcc.n	9868 <pinctrl_lookup_state+0x18>
		}

		(*state)++;
	}

	return -ENOENT;
    9862:	f06f 0001 	mvn.w	r0, #1
}
    9866:	bd30      	pop	{r4, r5, pc}
		if (id == (*state)->id) {
    9868:	795c      	ldrb	r4, [r3, #5]
    986a:	428c      	cmp	r4, r1
    986c:	d001      	beq.n	9872 <pinctrl_lookup_state+0x22>
		(*state)++;
    986e:	3308      	adds	r3, #8
    9870:	e7f0      	b.n	9854 <pinctrl_lookup_state+0x4>
			return 0;
    9872:	2000      	movs	r0, #0
    9874:	e7f7      	b.n	9866 <pinctrl_lookup_state+0x16>

00009876 <pinctrl_configure_pins>:
#define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
#endif

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
			   uintptr_t reg)
{
    9876:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    987a:	4615      	mov	r5, r2
    987c:	4682      	mov	sl, r0
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    987e:	f04f 0901 	mov.w	r9, #1
    9882:	b085      	sub	sp, #20
    9884:	eb00 0881 	add.w	r8, r0, r1, lsl #2
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    9888:	45d0      	cmp	r8, sl
    988a:	d103      	bne.n	9894 <pinctrl_configure_pins+0x1e>
			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
				     drive, NRF_GPIO_PIN_NOSENSE);
		}
	}

	return 0;
    988c:	2000      	movs	r0, #0
}
    988e:	b005      	add	sp, #20
    9890:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    9894:	f8da 3000 	ldr.w	r3, [sl]
		uint32_t pin = NRF_GET_PIN(pins[i]);
    9898:	f003 047f 	and.w	r4, r3, #127	; 0x7f
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    989c:	f3c3 2743 	ubfx	r7, r3, #9, #4
			pin = 0xFFFFFFFFU;
    98a0:	2c7f      	cmp	r4, #127	; 0x7f
		switch (NRF_GET_FUN(pins[i])) {
    98a2:	ea4f 4313 	mov.w	r3, r3, lsr #16
			pin = 0xFFFFFFFFU;
    98a6:	bf08      	it	eq
    98a8:	f04f 34ff 	moveq.w	r4, #4294967295
		switch (NRF_GET_FUN(pins[i])) {
    98ac:	2b22      	cmp	r3, #34	; 0x22
    98ae:	f200 8097 	bhi.w	99e0 <pinctrl_configure_pins+0x16a>
    98b2:	e8df f003 	tbb	[pc, r3]
    98b6:	4112      	.short	0x4112
    98b8:	3426211e 	.word	0x3426211e
    98bc:	3b213821 	.word	0x3b213821
    98c0:	956e4441 	.word	0x956e4441
    98c4:	95959595 	.word	0x95959595
    98c8:	95959595 	.word	0x95959595
    98cc:	807d7a71 	.word	0x807d7a71
    98d0:	83959595 	.word	0x83959595
    98d4:	8f8c8986 	.word	0x8f8c8986
    98d8:	92          	.byte	0x92
    98d9:	00          	.byte	0x00
			NRF_PSEL_UART(reg, TXD) = pin;
    98da:	f8c5 450c 	str.w	r4, [r5, #1292]	; 0x50c
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    98de:	a803      	add	r0, sp, #12
    98e0:	9403      	str	r4, [sp, #12]
    98e2:	f7fb fddd 	bl	54a0 <nrf_gpio_pin_port_decode>
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    98e6:	9b03      	ldr	r3, [sp, #12]
        nrf_gpio_pin_set(pin_number);
    98e8:	2601      	movs	r6, #1
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    98ea:	fa09 f303 	lsl.w	r3, r9, r3
    p_reg->OUTSET = set_mask;
    98ee:	6083      	str	r3, [r0, #8]
    98f0:	e012      	b.n	9918 <pinctrl_configure_pins+0xa2>
			NRF_PSEL_UART(reg, RTS) = pin;
    98f2:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
			if (write != NO_WRITE) {
    98f6:	e7f2      	b.n	98de <pinctrl_configure_pins+0x68>
			NRF_PSEL_UART(reg, CTS) = pin;
    98f8:	f8c5 4510 	str.w	r4, [r5, #1296]	; 0x510
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    98fc:	2600      	movs	r6, #0
			dir = NRF_GPIO_PIN_DIR_INPUT;
    98fe:	46b3      	mov	fp, r6
    9900:	e024      	b.n	994c <pinctrl_configure_pins+0xd6>
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    9902:	2600      	movs	r6, #0
			NRF_PSEL_SPIM(reg, SCK) = pin;
    9904:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    9908:	a803      	add	r0, sp, #12
    990a:	9403      	str	r4, [sp, #12]
    990c:	f7fb fdc8 	bl	54a0 <nrf_gpio_pin_port_decode>
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    9910:	9b03      	ldr	r3, [sp, #12]
    9912:	fa09 f303 	lsl.w	r3, r9, r3
    p_reg->OUTCLR = clr_mask;
    9916:	60c3      	str	r3, [r0, #12]
    9918:	f04f 0b01 	mov.w	fp, #1
    991c:	e016      	b.n	994c <pinctrl_configure_pins+0xd6>
			NRF_PSEL_SPIM(reg, MOSI) = pin;
    991e:	f8c5 450c 	str.w	r4, [r5, #1292]	; 0x50c
			pin = 0xFFFFFFFFU;
    9922:	2601      	movs	r6, #1
    9924:	e7f0      	b.n	9908 <pinctrl_configure_pins+0x92>
			NRF_PSEL_SPIS(reg, SCK) = pin;
    9926:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
			if (write != NO_WRITE) {
    992a:	e7e7      	b.n	98fc <pinctrl_configure_pins+0x86>
			NRF_PSEL_SPIS(reg, MISO) = pin;
    992c:	f8c5 450c 	str.w	r4, [r5, #1292]	; 0x50c
			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    9930:	2601      	movs	r6, #1
			dir = NRF_GPIO_PIN_DIR_INPUT;
    9932:	f04f 0b00 	mov.w	fp, #0
    9936:	e009      	b.n	994c <pinctrl_configure_pins+0xd6>
			NRF_PSEL_SPIS(reg, CSN) = pin;
    9938:	f8c5 4514 	str.w	r4, [r5, #1300]	; 0x514
			if (write != NO_WRITE) {
    993c:	e7de      	b.n	98fc <pinctrl_configure_pins+0x86>
			NRF_PSEL_TWIM(reg, SCL) = pin;
    993e:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
			if (drive == NRF_DRIVE_S0S1) {
    9942:	2f00      	cmp	r7, #0
    9944:	d1da      	bne.n	98fc <pinctrl_configure_pins+0x86>
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    9946:	2600      	movs	r6, #0
				drive = NRF_DRIVE_S0D1;
    9948:	2706      	movs	r7, #6
			dir = NRF_GPIO_PIN_DIR_INPUT;
    994a:	46b3      	mov	fp, r6
			if (NRF_GET_LP(pins[i]) == NRF_LP_ENABLE) {
    994c:	f85a 3b04 	ldr.w	r3, [sl], #4
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    9950:	a803      	add	r0, sp, #12
    9952:	f403 5200 	and.w	r2, r3, #8192	; 0x2000
				input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    9956:	2a00      	cmp	r2, #0
    9958:	bf1c      	itt	ne
    995a:	2601      	movne	r6, #1
    995c:	f04f 0b00 	movne.w	fp, #0
			if (NRF_GET_LP(pins[i]) == NRF_LP_ENABLE) {
    9960:	9301      	str	r3, [sp, #4]
    9962:	9403      	str	r4, [sp, #12]
    9964:	f7fb fd9c 	bl	54a0 <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    9968:	9a03      	ldr	r2, [sp, #12]
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    996a:	9b01      	ldr	r3, [sp, #4]
    996c:	eb00 0082 	add.w	r0, r0, r2, lsl #2
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    9970:	f8d0 1200 	ldr.w	r1, [r0, #512]	; 0x200
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    9974:	f3c3 12c1 	ubfx	r2, r3, #7, #2
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    9978:	023b      	lsls	r3, r7, #8
    997a:	ea43 0382 	orr.w	r3, r3, r2, lsl #2
    997e:	ea43 030b 	orr.w	r3, r3, fp
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    9982:	f001 42e0 	and.w	r2, r1, #1879048192	; 0x70000000
    9986:	4313      	orrs	r3, r2
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    9988:	ea43 0346 	orr.w	r3, r3, r6, lsl #1
    reg->PIN_CNF[pin_number] = cnf;
    998c:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    9990:	e77a      	b.n	9888 <pinctrl_configure_pins+0x12>
			NRF_PSEL_TWIM(reg, SDA) = pin;
    9992:	f8c5 450c 	str.w	r4, [r5, #1292]	; 0x50c
			if (drive == NRF_DRIVE_S0S1) {
    9996:	e7d4      	b.n	9942 <pinctrl_configure_pins+0xcc>
			NRF_PSEL_PWM(reg, OUT[0]) = pin;
    9998:	f8c5 4560 	str.w	r4, [r5, #1376]	; 0x560
			write = NRF_GET_INVERT(pins[i]);
    999c:	f8da 3000 	ldr.w	r3, [sl]
    99a0:	f3c3 3380 	ubfx	r3, r3, #14, #1
    if (value == 0)
    99a4:	2b00      	cmp	r3, #0
    99a6:	d0bc      	beq.n	9922 <pinctrl_configure_pins+0xac>
    99a8:	e799      	b.n	98de <pinctrl_configure_pins+0x68>
			NRF_PSEL_PWM(reg, OUT[1]) = pin;
    99aa:	f8c5 4564 	str.w	r4, [r5, #1380]	; 0x564
			write = NRF_GET_INVERT(pins[i]);
    99ae:	e7f5      	b.n	999c <pinctrl_configure_pins+0x126>
			NRF_PSEL_PWM(reg, OUT[2]) = pin;
    99b0:	f8c5 4568 	str.w	r4, [r5, #1384]	; 0x568
    99b4:	e7f2      	b.n	999c <pinctrl_configure_pins+0x126>
			NRF_PSEL_PWM(reg, OUT[3]) = pin;
    99b6:	f8c5 456c 	str.w	r4, [r5, #1388]	; 0x56c
			write = NRF_GET_INVERT(pins[i]);
    99ba:	e7ef      	b.n	999c <pinctrl_configure_pins+0x126>
			NRF_PSEL_QSPI(reg, SCK) = pin;
    99bc:	f8c5 4524 	str.w	r4, [r5, #1316]	; 0x524
			if (write != NO_WRITE) {
    99c0:	e7b6      	b.n	9930 <pinctrl_configure_pins+0xba>
			NRF_PSEL_QSPI(reg, CSN) = pin;
    99c2:	f8c5 4528 	str.w	r4, [r5, #1320]	; 0x528
    99c6:	e78a      	b.n	98de <pinctrl_configure_pins+0x68>
			NRF_PSEL_QSPI(reg, IO0) = pin;
    99c8:	f8c5 4530 	str.w	r4, [r5, #1328]	; 0x530
			if (write != NO_WRITE) {
    99cc:	e7b0      	b.n	9930 <pinctrl_configure_pins+0xba>
			NRF_PSEL_QSPI(reg, IO1) = pin;
    99ce:	f8c5 4534 	str.w	r4, [r5, #1332]	; 0x534
    99d2:	e7ad      	b.n	9930 <pinctrl_configure_pins+0xba>
			NRF_PSEL_QSPI(reg, IO2) = pin;
    99d4:	f8c5 4538 	str.w	r4, [r5, #1336]	; 0x538
			if (write != NO_WRITE) {
    99d8:	e7aa      	b.n	9930 <pinctrl_configure_pins+0xba>
			NRF_PSEL_QSPI(reg, IO3) = pin;
    99da:	f8c5 453c 	str.w	r4, [r5, #1340]	; 0x53c
			if (write != NO_WRITE) {
    99de:	e7a7      	b.n	9930 <pinctrl_configure_pins+0xba>
		switch (NRF_GET_FUN(pins[i])) {
    99e0:	f06f 0085 	mvn.w	r0, #133	; 0x85
    99e4:	e753      	b.n	988e <pinctrl_configure_pins+0x18>

000099e6 <mbox_nrf_register_callback>:
{
    99e6:	b510      	push	{r4, lr}
	struct mbox_nrf_data *data = dev->data;
    99e8:	6900      	ldr	r0, [r0, #16]
	if (channel >= IPC_CONF_NUM) {
    99ea:	290f      	cmp	r1, #15
	data->cb[channel] = cb;
    99ec:	bf9f      	itttt	ls
    99ee:	eb00 0481 	addls.w	r4, r0, r1, lsl #2
    99f2:	f840 2021 	strls.w	r2, [r0, r1, lsl #2]
	data->user_data[channel] = user_data;
    99f6:	6423      	strls	r3, [r4, #64]	; 0x40
	return 0;
    99f8:	2000      	movls	r0, #0
		return -EINVAL;
    99fa:	bf88      	it	hi
    99fc:	f06f 0015 	mvnhi.w	r0, #21
}
    9a00:	bd10      	pop	{r4, pc}

00009a02 <mbox_nrf_mtu_get>:
}
    9a02:	2000      	movs	r0, #0
    9a04:	4770      	bx	lr

00009a06 <mbox_nrf_max_channels_get>:
}
    9a06:	2010      	movs	r0, #16
    9a08:	4770      	bx	lr

00009a0a <hw_cc3xx_init_internal>:

	/* Initialize the cc3xx HW with or without RNG support */
#if CONFIG_ENTROPY_CC3XX
	res = nrf_cc3xx_platform_init();
#else
	res = nrf_cc3xx_platform_init_no_rng();
    9a0a:	f7ff b95f 	b.w	8ccc <nrf_cc3xx_platform_init_no_rng>

00009a0e <hw_cc3xx_init>:

	return res;
}

static int hw_cc3xx_init(const struct device *dev)
{
    9a0e:	b508      	push	{r3, lr}
	int res;

	/* Set the RTOS abort APIs */
	nrf_cc3xx_platform_abort_init();
    9a10:	f7f9 fbe6 	bl	31e0 <nrf_cc3xx_platform_abort_init>

	/* Set the RTOS mutex APIs */
	nrf_cc3xx_platform_mutex_init();
    9a14:	f7f9 fccc 	bl	33b0 <nrf_cc3xx_platform_mutex_init>

	/* Enable the hardware */
	res = hw_cc3xx_init_internal(dev);
	return res;
}
    9a18:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	res = nrf_cc3xx_platform_init_no_rng();
    9a1c:	f7ff b956 	b.w	8ccc <nrf_cc3xx_platform_init_no_rng>

00009a20 <nrfx_isr>:
#include <zephyr/kernel.h>
#include <soc/nrfx_coredep.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    9a20:	4700      	bx	r0

00009a22 <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    9a22:	f000 b8f3 	b.w	9c0c <z_impl_k_busy_wait>

00009a26 <nrf_gpio_pin_present_check>:
    switch (port)
    9a26:	0943      	lsrs	r3, r0, #5
    9a28:	d00b      	beq.n	9a42 <nrf_gpio_pin_present_check+0x1c>
    uint32_t mask = 0;
    9a2a:	2b01      	cmp	r3, #1
    9a2c:	f64f 73ff 	movw	r3, #65535	; 0xffff
    9a30:	bf18      	it	ne
    9a32:	2300      	movne	r3, #0
    pin_number &= 0x1F;
    9a34:	f000 001f 	and.w	r0, r0, #31
    return (mask & (1UL << pin_number)) ? true : false;
    9a38:	fa23 f000 	lsr.w	r0, r3, r0
}
    9a3c:	f000 0001 	and.w	r0, r0, #1
    9a40:	4770      	bx	lr
    switch (port)
    9a42:	f04f 33ff 	mov.w	r3, #4294967295
    9a46:	e7f5      	b.n	9a34 <nrf_gpio_pin_present_check+0xe>

00009a48 <pin_is_task_output>:
{
    9a48:	b508      	push	{r3, lr}
    9a4a:	4602      	mov	r2, r0
    return pin_is_output(pin) && pin_in_use_by_te(pin);
    9a4c:	f7fc f9ca 	bl	5de4 <pin_is_output>
    9a50:	b110      	cbz	r0, 9a58 <pin_is_task_output+0x10>
    9a52:	4610      	mov	r0, r2
    9a54:	f7fc f9b0 	bl	5db8 <pin_in_use_by_te>
}
    9a58:	f000 0001 	and.w	r0, r0, #1
    9a5c:	bd08      	pop	{r3, pc}

00009a5e <nrf_gpio_reconfigure>:
{
    9a5e:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    9a62:	4617      	mov	r7, r2
    9a64:	e9dd 5808 	ldrd	r5, r8, [sp, #32]
    9a68:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    9a6a:	a801      	add	r0, sp, #4
{
    9a6c:	460c      	mov	r4, r1
    9a6e:	461e      	mov	r6, r3
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    9a70:	f7fc fa3c 	bl	5eec <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number];
    9a74:	9b01      	ldr	r3, [sp, #4]
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    9a76:	1e39      	subs	r1, r7, #0
    9a78:	bf18      	it	ne
    9a7a:	2101      	movne	r1, #1
    9a7c:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    9a80:	1e23      	subs	r3, r4, #0
    9a82:	bf18      	it	ne
    9a84:	2301      	movne	r3, #1
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    9a86:	2e00      	cmp	r6, #0
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    9a88:	ea43 0341 	orr.w	r3, r3, r1, lsl #1
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    9a8c:	bf14      	ite	ne
    9a8e:	210c      	movne	r1, #12
    9a90:	2100      	moveq	r1, #0
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    9a92:	2d00      	cmp	r5, #0
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    9a94:	ea43 0301 	orr.w	r3, r3, r1
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    9a98:	bf14      	ite	ne
    9a9a:	f44f 6170 	movne.w	r1, #3840	; 0xf00
    9a9e:	2100      	moveq	r1, #0
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    9aa0:	f1b8 0f00 	cmp.w	r8, #0
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    9aa4:	ea43 0301 	orr.w	r3, r3, r1
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    9aa8:	bf14      	ite	ne
    9aaa:	f44f 3140 	movne.w	r1, #196608	; 0x30000
    9aae:	2100      	moveq	r1, #0
    uint32_t cnf = reg->PIN_CNF[pin_number];
    9ab0:	f8d0 2200 	ldr.w	r2, [r0, #512]	; 0x200
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    9ab4:	430b      	orrs	r3, r1
    cnf &= ~to_update;
    9ab6:	ea22 0303 	bic.w	r3, r2, r3
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    9aba:	b104      	cbz	r4, 9abe <nrf_gpio_reconfigure+0x60>
    9abc:	7824      	ldrb	r4, [r4, #0]
           ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
    9abe:	b10f      	cbz	r7, 9ac4 <nrf_gpio_reconfigure+0x66>
    9ac0:	783f      	ldrb	r7, [r7, #0]
    9ac2:	007f      	lsls	r7, r7, #1
    9ac4:	431c      	orrs	r4, r3
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    9ac6:	b10e      	cbz	r6, 9acc <nrf_gpio_reconfigure+0x6e>
    9ac8:	7836      	ldrb	r6, [r6, #0]
    9aca:	00b6      	lsls	r6, r6, #2
    9acc:	433c      	orrs	r4, r7
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    9ace:	b18d      	cbz	r5, 9af4 <nrf_gpio_reconfigure+0x96>
    9ad0:	7829      	ldrb	r1, [r5, #0]
    9ad2:	0209      	lsls	r1, r1, #8
    9ad4:	4334      	orrs	r4, r6
           ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos);
    9ad6:	f1b8 0f00 	cmp.w	r8, #0
    9ada:	d003      	beq.n	9ae4 <nrf_gpio_reconfigure+0x86>
    9adc:	f898 8000 	ldrb.w	r8, [r8]
    9ae0:	ea4f 4808 	mov.w	r8, r8, lsl #16
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    9ae4:	4321      	orrs	r1, r4
    9ae6:	ea41 0108 	orr.w	r1, r1, r8
    reg->PIN_CNF[pin_number] = cnf;
    9aea:	f8c0 1200 	str.w	r1, [r0, #512]	; 0x200
}
    9aee:	b002      	add	sp, #8
    9af0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    9af4:	4629      	mov	r1, r5
    9af6:	e7ed      	b.n	9ad4 <nrf_gpio_reconfigure+0x76>

00009af8 <nrf_gpio_cfg_sense_set>:
{
    9af8:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    9afa:	f10d 030f 	add.w	r3, sp, #15
    9afe:	9301      	str	r3, [sp, #4]
    9b00:	2300      	movs	r3, #0
{
    9b02:	f88d 100f 	strb.w	r1, [sp, #15]
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    9b06:	461a      	mov	r2, r3
    9b08:	4619      	mov	r1, r3
    9b0a:	9300      	str	r3, [sp, #0]
    9b0c:	f7ff ffa7 	bl	9a5e <nrf_gpio_reconfigure>
}
    9b10:	b005      	add	sp, #20
    9b12:	f85d fb04 	ldr.w	pc, [sp], #4

00009b16 <z_device_state_init>:

	while (dev < __device_end) {
		z_object_init(dev);
		++dev;
	}
}
    9b16:	4770      	bx	lr

00009b18 <z_device_is_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    9b18:	b140      	cbz	r0, 9b2c <z_device_is_ready+0x14>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    9b1a:	68c3      	ldr	r3, [r0, #12]
    9b1c:	7858      	ldrb	r0, [r3, #1]
    9b1e:	f010 0001 	ands.w	r0, r0, #1
    9b22:	bf1e      	ittt	ne
    9b24:	7818      	ldrbne	r0, [r3, #0]
    9b26:	fab0 f080 	clzne	r0, r0
    9b2a:	0940      	lsrne	r0, r0, #5
}
    9b2c:	4770      	bx	lr

00009b2e <z_early_memset>:
	(void) memset(dst, c, n);
    9b2e:	f7ff bd7a 	b.w	9626 <memset>

00009b32 <z_early_memcpy>:
	(void) memcpy(dst, src, n);
    9b32:	f7ff bd6d 	b.w	9610 <memcpy>

00009b36 <create_free_list>:
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    9b36:	e9d0 3204 	ldrd	r3, r2, [r0, #16]
    9b3a:	4313      	orrs	r3, r2
    9b3c:	f013 0303 	ands.w	r3, r3, #3
    9b40:	d10c      	bne.n	9b5c <create_free_list+0x26>
	slab->free_list = NULL;
    9b42:	6183      	str	r3, [r0, #24]
	for (j = 0U; j < slab->num_blocks; j++) {
    9b44:	68c1      	ldr	r1, [r0, #12]
    9b46:	4299      	cmp	r1, r3
    9b48:	d801      	bhi.n	9b4e <create_free_list+0x18>
	return 0;
    9b4a:	2000      	movs	r0, #0
    9b4c:	4770      	bx	lr
		*(char **)p = slab->free_list;
    9b4e:	6981      	ldr	r1, [r0, #24]
	for (j = 0U; j < slab->num_blocks; j++) {
    9b50:	3301      	adds	r3, #1
		*(char **)p = slab->free_list;
    9b52:	6011      	str	r1, [r2, #0]
		p += slab->block_size;
    9b54:	6901      	ldr	r1, [r0, #16]
		slab->free_list = p;
    9b56:	6182      	str	r2, [r0, #24]
		p += slab->block_size;
    9b58:	440a      	add	r2, r1
	for (j = 0U; j < slab->num_blocks; j++) {
    9b5a:	e7f3      	b.n	9b44 <create_free_list+0xe>
		return -EINVAL;
    9b5c:	f06f 0015 	mvn.w	r0, #21
}
    9b60:	4770      	bx	lr

00009b62 <k_mem_slab_init>:
{
    9b62:	b510      	push	{r4, lr}
	slab->block_size = block_size;
    9b64:	e9c0 3203 	strd	r3, r2, [r0, #12]
	slab->num_used = 0U;
    9b68:	2300      	movs	r3, #0
	slab->buffer = buffer;
    9b6a:	6141      	str	r1, [r0, #20]
	slab->num_used = 0U;
    9b6c:	61c3      	str	r3, [r0, #28]
	slab->lock = (struct k_spinlock) {};
    9b6e:	6083      	str	r3, [r0, #8]
{
    9b70:	4604      	mov	r4, r0
	rc = create_free_list(slab);
    9b72:	f7ff ffe0 	bl	9b36 <create_free_list>
	if (rc < 0) {
    9b76:	2800      	cmp	r0, #0
	list->tail = (sys_dnode_t *)list;
    9b78:	bfa8      	it	ge
    9b7a:	e9c4 4400 	strdge	r4, r4, [r4]
}
    9b7e:	bd10      	pop	{r4, pc}

00009b80 <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    9b80:	f3ef 8005 	mrs	r0, IPSR
}
    9b84:	3800      	subs	r0, #0
    9b86:	bf18      	it	ne
    9b88:	2001      	movne	r0, #1
    9b8a:	4770      	bx	lr

00009b8c <k_thread_name_get>:
}
    9b8c:	2000      	movs	r0, #0
    9b8e:	4770      	bx	lr

00009b90 <z_pm_save_idle_exit>:
{
    9b90:	b508      	push	{r3, lr}
	pm_system_resume();
    9b92:	f7f9 f9f1 	bl	2f78 <pm_system_resume>
}
    9b96:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	sys_clock_idle_exit();
    9b9a:	f7ff be48 	b.w	982e <sys_clock_idle_exit>

00009b9e <adjust_owner_prio.isra.0>:
	if (mutex->owner->base.prio != new_prio) {
    9b9e:	f990 300e 	ldrsb.w	r3, [r0, #14]
    9ba2:	428b      	cmp	r3, r1
    9ba4:	d001      	beq.n	9baa <adjust_owner_prio.isra.0+0xc>
		return z_set_prio(mutex->owner, new_prio);
    9ba6:	f7fe b843 	b.w	7c30 <z_set_prio>
}
    9baa:	2000      	movs	r0, #0
    9bac:	4770      	bx	lr

00009bae <z_impl_k_mutex_init>:
{
    9bae:	4603      	mov	r3, r0
	mutex->owner = NULL;
    9bb0:	2000      	movs	r0, #0
    9bb2:	e9c3 3300 	strd	r3, r3, [r3]
	mutex->lock_count = 0U;
    9bb6:	e9c3 0002 	strd	r0, r0, [r3, #8]
}
    9bba:	4770      	bx	lr

00009bbc <z_impl_k_sem_init>:
	CHECKIF(limit == 0U || limit > K_SEM_MAX_LIMIT || initial_count > limit) {
    9bbc:	b13a      	cbz	r2, 9bce <z_impl_k_sem_init+0x12>
    9bbe:	428a      	cmp	r2, r1
    9bc0:	d305      	bcc.n	9bce <z_impl_k_sem_init+0x12>
	sem->limit = limit;
    9bc2:	e9c0 1202 	strd	r1, r2, [r0, #8]
    9bc6:	e9c0 0000 	strd	r0, r0, [r0]
	return 0;
    9bca:	2000      	movs	r0, #0
    9bcc:	4770      	bx	lr
		return -EINVAL;
    9bce:	f06f 0015 	mvn.w	r0, #21
}
    9bd2:	4770      	bx	lr

00009bd4 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    9bd4:	4603      	mov	r3, r0
    9bd6:	b920      	cbnz	r0, 9be2 <z_reschedule_irqlock+0xe>
    9bd8:	f3ef 8205 	mrs	r2, IPSR
    9bdc:	b90a      	cbnz	r2, 9be2 <z_reschedule_irqlock+0xe>
    9bde:	f7f9 bd11 	b.w	3604 <arch_swap>
    9be2:	f383 8811 	msr	BASEPRI, r3
    9be6:	f3bf 8f6f 	isb	sy
}
    9bea:	4770      	bx	lr

00009bec <z_reschedule_unlocked>:
	__asm__ volatile(
    9bec:	f04f 0320 	mov.w	r3, #32
    9bf0:	f3ef 8011 	mrs	r0, BASEPRI
    9bf4:	f383 8812 	msr	BASEPRI_MAX, r3
    9bf8:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    9bfc:	f7ff bfea 	b.w	9bd4 <z_reschedule_irqlock>

00009c00 <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
    9c00:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
    9c02:	f7fe ff1b 	bl	8a3c <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    9c06:	bd08      	pop	{r3, pc}

00009c08 <z_impl_k_uptime_ticks>:

int64_t z_impl_k_uptime_ticks(void)
{
	return sys_clock_tick_get();
    9c08:	f7fe bf18 	b.w	8a3c <sys_clock_tick_get>

00009c0c <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    9c0c:	b108      	cbz	r0, 9c12 <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    9c0e:	f7f8 b9e1 	b.w	1fd4 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    9c12:	4770      	bx	lr

00009c14 <z_impl_k_timer_stop>:
}
#include <syscalls/k_timer_start_mrsh.c>
#endif

void z_impl_k_timer_stop(struct k_timer *timer)
{
    9c14:	b510      	push	{r4, lr}
    9c16:	4604      	mov	r4, r0
	SYS_PORT_TRACING_OBJ_FUNC(k_timer, stop, timer);

	bool inactive = (z_abort_timeout(&timer->timeout) != 0);
    9c18:	f7fe fd8e 	bl	8738 <z_abort_timeout>

	if (inactive) {
    9c1c:	b9b0      	cbnz	r0, 9c4c <z_impl_k_timer_stop+0x38>
		return;
	}

	if (timer->stop_fn != NULL) {
    9c1e:	6a63      	ldr	r3, [r4, #36]	; 0x24
    9c20:	b10b      	cbz	r3, 9c26 <z_impl_k_timer_stop+0x12>
		timer->stop_fn(timer);
    9c22:	4620      	mov	r0, r4
    9c24:	4798      	blx	r3
	}

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		struct k_thread *pending_thread = z_unpend1_no_timeout(&timer->wait_q);
    9c26:	f104 0018 	add.w	r0, r4, #24
    9c2a:	f7fe f973 	bl	7f14 <z_unpend1_no_timeout>

		if (pending_thread != NULL) {
    9c2e:	b168      	cbz	r0, 9c4c <z_impl_k_timer_stop+0x38>
			z_ready_thread(pending_thread);
    9c30:	f7fd fc2e 	bl	7490 <z_ready_thread>
    9c34:	f04f 0320 	mov.w	r3, #32
    9c38:	f3ef 8011 	mrs	r0, BASEPRI
    9c3c:	f383 8812 	msr	BASEPRI_MAX, r3
    9c40:	f3bf 8f6f 	isb	sy
			z_reschedule_unlocked();
		}
	}
}
    9c44:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    9c48:	f7ff bfc4 	b.w	9bd4 <z_reschedule_irqlock>
    9c4c:	bd10      	pop	{r4, pc}

00009c4e <boot_banner>:
#endif /* defined(CONFIG_BOOT_DELAY) && (CONFIG_BOOT_DELAY > 0) */

#if CONFIG_BOOT_BANNER
	printk("*** Booting Zephyr OS build " BANNER_VERSION BANNER_POSTFIX " ***\n");
#endif /* CONFIG_BOOT_BANNER */
}
    9c4e:	4770      	bx	lr

00009c50 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    9c50:	4770      	bx	lr
	...
