
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_start>:
#include <syscalls/z_errno_mrsh.c>

#else
int *z_impl_z_errno(void)
{
	return &_current->errno_var;
   0:	200011d8 	.word	0x200011d8
}
   4:	00002605 	.word	0x00002605
   8:	00006515 	.word	0x00006515
   c:	00002659 	.word	0x00002659
  10:	00002659 	.word	0x00002659
  14:	00002659 	.word	0x00002659
  18:	00002659 	.word	0x00002659
	...
  2c:	00002561 	.word	0x00002561
  30:	00002659 	.word	0x00002659
  34:	00000000 	.word	0x00000000
  38:	00002519 	.word	0x00002519
  3c:	00006501 	.word	0x00006501

00000040 <_irq_vector_table>:
  40:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..
  50:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..
  60:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..
  70:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..
  80:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..
  90:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..
  a0:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..
  b0:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..
  c0:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..
  d0:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..
  e0:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..
  f0:	000025c5 000025c5 000025c5 000025c5     .%...%...%...%..

Disassembly of section text:

00000100 <memchr>:
     100:	f001 01ff 	and.w	r1, r1, #255	; 0xff
     104:	2a10      	cmp	r2, #16
     106:	db2b      	blt.n	160 <CONFIG_IDLE_STACK_SIZE+0x20>
     108:	f010 0f07 	tst.w	r0, #7
     10c:	d008      	beq.n	120 <memchr+0x20>
     10e:	f810 3b01 	ldrb.w	r3, [r0], #1
     112:	3a01      	subs	r2, #1
     114:	428b      	cmp	r3, r1
     116:	d02d      	beq.n	174 <CONFIG_IDLE_STACK_SIZE+0x34>
     118:	f010 0f07 	tst.w	r0, #7
     11c:	b342      	cbz	r2, 170 <CONFIG_IDLE_STACK_SIZE+0x30>
     11e:	d1f6      	bne.n	10e <memchr+0xe>
     120:	b4f0      	push	{r4, r5, r6, r7}
     122:	ea41 2101 	orr.w	r1, r1, r1, lsl #8
     126:	ea41 4101 	orr.w	r1, r1, r1, lsl #16
     12a:	f022 0407 	bic.w	r4, r2, #7
     12e:	f07f 0700 	mvns.w	r7, #0
     132:	2300      	movs	r3, #0
     134:	e8f0 5602 	ldrd	r5, r6, [r0], #8
     138:	3c08      	subs	r4, #8
     13a:	ea85 0501 	eor.w	r5, r5, r1
     13e:	ea86 0601 	eor.w	r6, r6, r1
     142:	fa85 f547 	uadd8	r5, r5, r7
     146:	faa3 f587 	sel	r5, r3, r7
     14a:	fa86 f647 	uadd8	r6, r6, r7
     14e:	faa5 f687 	sel	r6, r5, r7
     152:	b98e      	cbnz	r6, 178 <CONFIG_IDLE_STACK_SIZE+0x38>
     154:	d1ee      	bne.n	134 <memchr+0x34>
     156:	bcf0      	pop	{r4, r5, r6, r7}
     158:	f001 01ff 	and.w	r1, r1, #255	; 0xff
     15c:	f002 0207 	and.w	r2, r2, #7
     160:	b132      	cbz	r2, 170 <CONFIG_IDLE_STACK_SIZE+0x30>
     162:	f810 3b01 	ldrb.w	r3, [r0], #1
     166:	3a01      	subs	r2, #1
     168:	ea83 0301 	eor.w	r3, r3, r1
     16c:	b113      	cbz	r3, 174 <CONFIG_IDLE_STACK_SIZE+0x34>
     16e:	d1f8      	bne.n	162 <CONFIG_IDLE_STACK_SIZE+0x22>
     170:	2000      	movs	r0, #0
     172:	4770      	bx	lr
     174:	3801      	subs	r0, #1
     176:	4770      	bx	lr
     178:	2d00      	cmp	r5, #0
     17a:	bf06      	itte	eq
     17c:	4635      	moveq	r5, r6
     17e:	3803      	subeq	r0, #3
     180:	3807      	subne	r0, #7
     182:	f015 0f01 	tst.w	r5, #1
     186:	d107      	bne.n	198 <CONFIG_IDLE_STACK_SIZE+0x58>
     188:	3001      	adds	r0, #1
     18a:	f415 7f80 	tst.w	r5, #256	; 0x100
     18e:	bf02      	ittt	eq
     190:	3001      	addeq	r0, #1
     192:	f415 3fc0 	tsteq.w	r5, #98304	; 0x18000
     196:	3001      	addeq	r0, #1
     198:	bcf0      	pop	{r4, r5, r6, r7}
     19a:	3801      	subs	r0, #1
     19c:	4770      	bx	lr
     19e:	bf00      	nop

000001a0 <__aeabi_uldivmod>:
     1a0:	b953      	cbnz	r3, 1b8 <__aeabi_uldivmod+0x18>
     1a2:	b94a      	cbnz	r2, 1b8 <__aeabi_uldivmod+0x18>
     1a4:	2900      	cmp	r1, #0
     1a6:	bf08      	it	eq
     1a8:	2800      	cmpeq	r0, #0
     1aa:	bf1c      	itt	ne
     1ac:	f04f 31ff 	movne.w	r1, #4294967295
     1b0:	f04f 30ff 	movne.w	r0, #4294967295
     1b4:	f000 b96c 	b.w	490 <__aeabi_idiv0>
     1b8:	f1ad 0c08 	sub.w	ip, sp, #8
     1bc:	e96d ce04 	strd	ip, lr, [sp, #-16]!
     1c0:	f000 f806 	bl	1d0 <__udivmoddi4>
     1c4:	f8dd e004 	ldr.w	lr, [sp, #4]
     1c8:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     1cc:	b004      	add	sp, #16
     1ce:	4770      	bx	lr

000001d0 <__udivmoddi4>:
     1d0:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     1d4:	9e08      	ldr	r6, [sp, #32]
     1d6:	460d      	mov	r5, r1
     1d8:	4604      	mov	r4, r0
     1da:	468e      	mov	lr, r1
     1dc:	2b00      	cmp	r3, #0
     1de:	f040 8082 	bne.w	2e6 <CONFIG_FLASH_SIZE+0xe6>
     1e2:	428a      	cmp	r2, r1
     1e4:	4617      	mov	r7, r2
     1e6:	d946      	bls.n	276 <CONFIG_FLASH_SIZE+0x76>
     1e8:	fab2 f282 	clz	r2, r2
     1ec:	b14a      	cbz	r2, 202 <CONFIG_FLASH_SIZE+0x2>
     1ee:	f1c2 0120 	rsb	r1, r2, #32
     1f2:	fa05 f302 	lsl.w	r3, r5, r2
     1f6:	fa20 f101 	lsr.w	r1, r0, r1
     1fa:	4097      	lsls	r7, r2
     1fc:	ea41 0e03 	orr.w	lr, r1, r3
     200:	4094      	lsls	r4, r2
     202:	ea4f 4817 	mov.w	r8, r7, lsr #16
     206:	0c23      	lsrs	r3, r4, #16
     208:	fbbe fcf8 	udiv	ip, lr, r8
     20c:	b2b9      	uxth	r1, r7
     20e:	fb08 ee1c 	mls	lr, r8, ip, lr
     212:	ea43 430e 	orr.w	r3, r3, lr, lsl #16
     216:	fb0c f001 	mul.w	r0, ip, r1
     21a:	4298      	cmp	r0, r3
     21c:	d90a      	bls.n	234 <CONFIG_FLASH_SIZE+0x34>
     21e:	18fb      	adds	r3, r7, r3
     220:	f10c 35ff 	add.w	r5, ip, #4294967295
     224:	f080 8116 	bcs.w	454 <CONFIG_LOG_BUFFER_SIZE+0x54>
     228:	4298      	cmp	r0, r3
     22a:	f240 8113 	bls.w	454 <CONFIG_LOG_BUFFER_SIZE+0x54>
     22e:	f1ac 0c02 	sub.w	ip, ip, #2
     232:	443b      	add	r3, r7
     234:	1a1b      	subs	r3, r3, r0
     236:	b2a4      	uxth	r4, r4
     238:	fbb3 f0f8 	udiv	r0, r3, r8
     23c:	fb08 3310 	mls	r3, r8, r0, r3
     240:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     244:	fb00 f101 	mul.w	r1, r0, r1
     248:	42a1      	cmp	r1, r4
     24a:	d909      	bls.n	260 <CONFIG_FLASH_SIZE+0x60>
     24c:	193c      	adds	r4, r7, r4
     24e:	f100 33ff 	add.w	r3, r0, #4294967295
     252:	f080 8101 	bcs.w	458 <CONFIG_LOG_BUFFER_SIZE+0x58>
     256:	42a1      	cmp	r1, r4
     258:	f240 80fe 	bls.w	458 <CONFIG_LOG_BUFFER_SIZE+0x58>
     25c:	3802      	subs	r0, #2
     25e:	443c      	add	r4, r7
     260:	1a64      	subs	r4, r4, r1
     262:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     266:	2100      	movs	r1, #0
     268:	b11e      	cbz	r6, 272 <CONFIG_FLASH_SIZE+0x72>
     26a:	40d4      	lsrs	r4, r2
     26c:	2300      	movs	r3, #0
     26e:	e9c6 4300 	strd	r4, r3, [r6]
     272:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     276:	b902      	cbnz	r2, 27a <CONFIG_FLASH_SIZE+0x7a>
     278:	deff      	udf	#255	; 0xff
     27a:	fab2 f282 	clz	r2, r2
     27e:	2a00      	cmp	r2, #0
     280:	d14f      	bne.n	322 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x22>
     282:	1bcb      	subs	r3, r1, r7
     284:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     288:	fa1f f887 	uxth.w	r8, r7
     28c:	2101      	movs	r1, #1
     28e:	fbb3 fcfe 	udiv	ip, r3, lr
     292:	0c25      	lsrs	r5, r4, #16
     294:	fb0e 331c 	mls	r3, lr, ip, r3
     298:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     29c:	fb08 f30c 	mul.w	r3, r8, ip
     2a0:	42ab      	cmp	r3, r5
     2a2:	d907      	bls.n	2b4 <CONFIG_FLASH_SIZE+0xb4>
     2a4:	197d      	adds	r5, r7, r5
     2a6:	f10c 30ff 	add.w	r0, ip, #4294967295
     2aa:	d202      	bcs.n	2b2 <CONFIG_FLASH_SIZE+0xb2>
     2ac:	42ab      	cmp	r3, r5
     2ae:	f200 80e7 	bhi.w	480 <CONFIG_LOG_BUFFER_SIZE+0x80>
     2b2:	4684      	mov	ip, r0
     2b4:	1aed      	subs	r5, r5, r3
     2b6:	b2a3      	uxth	r3, r4
     2b8:	fbb5 f0fe 	udiv	r0, r5, lr
     2bc:	fb0e 5510 	mls	r5, lr, r0, r5
     2c0:	ea43 4405 	orr.w	r4, r3, r5, lsl #16
     2c4:	fb08 f800 	mul.w	r8, r8, r0
     2c8:	45a0      	cmp	r8, r4
     2ca:	d907      	bls.n	2dc <CONFIG_FLASH_SIZE+0xdc>
     2cc:	193c      	adds	r4, r7, r4
     2ce:	f100 33ff 	add.w	r3, r0, #4294967295
     2d2:	d202      	bcs.n	2da <CONFIG_FLASH_SIZE+0xda>
     2d4:	45a0      	cmp	r8, r4
     2d6:	f200 80d7 	bhi.w	488 <CONFIG_LOG_BUFFER_SIZE+0x88>
     2da:	4618      	mov	r0, r3
     2dc:	eba4 0408 	sub.w	r4, r4, r8
     2e0:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     2e4:	e7c0      	b.n	268 <CONFIG_FLASH_SIZE+0x68>
     2e6:	428b      	cmp	r3, r1
     2e8:	d908      	bls.n	2fc <CONFIG_FLASH_SIZE+0xfc>
     2ea:	2e00      	cmp	r6, #0
     2ec:	f000 80af 	beq.w	44e <CONFIG_LOG_BUFFER_SIZE+0x4e>
     2f0:	2100      	movs	r1, #0
     2f2:	e9c6 0500 	strd	r0, r5, [r6]
     2f6:	4608      	mov	r0, r1
     2f8:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     2fc:	fab3 f183 	clz	r1, r3
     300:	2900      	cmp	r1, #0
     302:	d14b      	bne.n	39c <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x9c>
     304:	42ab      	cmp	r3, r5
     306:	d302      	bcc.n	30e <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xe>
     308:	4282      	cmp	r2, r0
     30a:	f200 80b7 	bhi.w	47c <CONFIG_LOG_BUFFER_SIZE+0x7c>
     30e:	1a84      	subs	r4, r0, r2
     310:	eb65 0303 	sbc.w	r3, r5, r3
     314:	2001      	movs	r0, #1
     316:	469e      	mov	lr, r3
     318:	2e00      	cmp	r6, #0
     31a:	d0aa      	beq.n	272 <CONFIG_FLASH_SIZE+0x72>
     31c:	e9c6 4e00 	strd	r4, lr, [r6]
     320:	e7a7      	b.n	272 <CONFIG_FLASH_SIZE+0x72>
     322:	f1c2 0c20 	rsb	ip, r2, #32
     326:	fa01 f302 	lsl.w	r3, r1, r2
     32a:	4097      	lsls	r7, r2
     32c:	fa20 f00c 	lsr.w	r0, r0, ip
     330:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     334:	fa21 fc0c 	lsr.w	ip, r1, ip
     338:	4318      	orrs	r0, r3
     33a:	fbbc f1fe 	udiv	r1, ip, lr
     33e:	0c05      	lsrs	r5, r0, #16
     340:	fb0e cc11 	mls	ip, lr, r1, ip
     344:	fa1f f887 	uxth.w	r8, r7
     348:	ea45 450c 	orr.w	r5, r5, ip, lsl #16
     34c:	fb01 f308 	mul.w	r3, r1, r8
     350:	42ab      	cmp	r3, r5
     352:	fa04 f402 	lsl.w	r4, r4, r2
     356:	d909      	bls.n	36c <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x6c>
     358:	197d      	adds	r5, r7, r5
     35a:	f101 3cff 	add.w	ip, r1, #4294967295
     35e:	f080 808b 	bcs.w	478 <CONFIG_LOG_BUFFER_SIZE+0x78>
     362:	42ab      	cmp	r3, r5
     364:	f240 8088 	bls.w	478 <CONFIG_LOG_BUFFER_SIZE+0x78>
     368:	3902      	subs	r1, #2
     36a:	443d      	add	r5, r7
     36c:	1aeb      	subs	r3, r5, r3
     36e:	b285      	uxth	r5, r0
     370:	fbb3 f0fe 	udiv	r0, r3, lr
     374:	fb0e 3310 	mls	r3, lr, r0, r3
     378:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     37c:	fb00 f308 	mul.w	r3, r0, r8
     380:	42ab      	cmp	r3, r5
     382:	d907      	bls.n	394 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x94>
     384:	197d      	adds	r5, r7, r5
     386:	f100 3cff 	add.w	ip, r0, #4294967295
     38a:	d271      	bcs.n	470 <CONFIG_LOG_BUFFER_SIZE+0x70>
     38c:	42ab      	cmp	r3, r5
     38e:	d96f      	bls.n	470 <CONFIG_LOG_BUFFER_SIZE+0x70>
     390:	3802      	subs	r0, #2
     392:	443d      	add	r5, r7
     394:	1aeb      	subs	r3, r5, r3
     396:	ea40 4101 	orr.w	r1, r0, r1, lsl #16
     39a:	e778      	b.n	28e <CONFIG_FLASH_SIZE+0x8e>
     39c:	f1c1 0c20 	rsb	ip, r1, #32
     3a0:	408b      	lsls	r3, r1
     3a2:	fa22 f70c 	lsr.w	r7, r2, ip
     3a6:	431f      	orrs	r7, r3
     3a8:	fa20 f40c 	lsr.w	r4, r0, ip
     3ac:	fa05 f301 	lsl.w	r3, r5, r1
     3b0:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     3b4:	fa25 f50c 	lsr.w	r5, r5, ip
     3b8:	431c      	orrs	r4, r3
     3ba:	0c23      	lsrs	r3, r4, #16
     3bc:	fbb5 f9fe 	udiv	r9, r5, lr
     3c0:	fa1f f887 	uxth.w	r8, r7
     3c4:	fb0e 5519 	mls	r5, lr, r9, r5
     3c8:	ea43 4505 	orr.w	r5, r3, r5, lsl #16
     3cc:	fb09 fa08 	mul.w	sl, r9, r8
     3d0:	45aa      	cmp	sl, r5
     3d2:	fa02 f201 	lsl.w	r2, r2, r1
     3d6:	fa00 f301 	lsl.w	r3, r0, r1
     3da:	d908      	bls.n	3ee <CONFIG_LOG_PROCESS_THREAD_SLEEP_MS+0x6>
     3dc:	197d      	adds	r5, r7, r5
     3de:	f109 30ff 	add.w	r0, r9, #4294967295
     3e2:	d247      	bcs.n	474 <CONFIG_LOG_BUFFER_SIZE+0x74>
     3e4:	45aa      	cmp	sl, r5
     3e6:	d945      	bls.n	474 <CONFIG_LOG_BUFFER_SIZE+0x74>
     3e8:	f1a9 0902 	sub.w	r9, r9, #2
     3ec:	443d      	add	r5, r7
     3ee:	eba5 050a 	sub.w	r5, r5, sl
     3f2:	b2a4      	uxth	r4, r4
     3f4:	fbb5 f0fe 	udiv	r0, r5, lr
     3f8:	fb0e 5510 	mls	r5, lr, r0, r5
     3fc:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
     400:	fb00 f808 	mul.w	r8, r0, r8
     404:	45a0      	cmp	r8, r4
     406:	d907      	bls.n	418 <CONFIG_LOG_BUFFER_SIZE+0x18>
     408:	193c      	adds	r4, r7, r4
     40a:	f100 35ff 	add.w	r5, r0, #4294967295
     40e:	d22d      	bcs.n	46c <CONFIG_LOG_BUFFER_SIZE+0x6c>
     410:	45a0      	cmp	r8, r4
     412:	d92b      	bls.n	46c <CONFIG_LOG_BUFFER_SIZE+0x6c>
     414:	3802      	subs	r0, #2
     416:	443c      	add	r4, r7
     418:	ea40 4009 	orr.w	r0, r0, r9, lsl #16
     41c:	eba4 0408 	sub.w	r4, r4, r8
     420:	fba0 8902 	umull	r8, r9, r0, r2
     424:	454c      	cmp	r4, r9
     426:	46c6      	mov	lr, r8
     428:	464d      	mov	r5, r9
     42a:	d319      	bcc.n	460 <CONFIG_LOG_BUFFER_SIZE+0x60>
     42c:	d016      	beq.n	45c <CONFIG_LOG_BUFFER_SIZE+0x5c>
     42e:	b15e      	cbz	r6, 448 <CONFIG_LOG_BUFFER_SIZE+0x48>
     430:	ebb3 020e 	subs.w	r2, r3, lr
     434:	eb64 0405 	sbc.w	r4, r4, r5
     438:	fa04 fc0c 	lsl.w	ip, r4, ip
     43c:	40ca      	lsrs	r2, r1
     43e:	ea4c 0202 	orr.w	r2, ip, r2
     442:	40cc      	lsrs	r4, r1
     444:	e9c6 2400 	strd	r2, r4, [r6]
     448:	2100      	movs	r1, #0
     44a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     44e:	4631      	mov	r1, r6
     450:	4630      	mov	r0, r6
     452:	e70e      	b.n	272 <CONFIG_FLASH_SIZE+0x72>
     454:	46ac      	mov	ip, r5
     456:	e6ed      	b.n	234 <CONFIG_FLASH_SIZE+0x34>
     458:	4618      	mov	r0, r3
     45a:	e701      	b.n	260 <CONFIG_FLASH_SIZE+0x60>
     45c:	4543      	cmp	r3, r8
     45e:	d2e6      	bcs.n	42e <CONFIG_LOG_BUFFER_SIZE+0x2e>
     460:	ebb8 0e02 	subs.w	lr, r8, r2
     464:	eb69 0507 	sbc.w	r5, r9, r7
     468:	3801      	subs	r0, #1
     46a:	e7e0      	b.n	42e <CONFIG_LOG_BUFFER_SIZE+0x2e>
     46c:	4628      	mov	r0, r5
     46e:	e7d3      	b.n	418 <CONFIG_LOG_BUFFER_SIZE+0x18>
     470:	4660      	mov	r0, ip
     472:	e78f      	b.n	394 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x94>
     474:	4681      	mov	r9, r0
     476:	e7ba      	b.n	3ee <CONFIG_LOG_PROCESS_THREAD_SLEEP_MS+0x6>
     478:	4661      	mov	r1, ip
     47a:	e777      	b.n	36c <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x6c>
     47c:	4608      	mov	r0, r1
     47e:	e74b      	b.n	318 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x18>
     480:	f1ac 0c02 	sub.w	ip, ip, #2
     484:	443d      	add	r5, r7
     486:	e715      	b.n	2b4 <CONFIG_FLASH_SIZE+0xb4>
     488:	3802      	subs	r0, #2
     48a:	443c      	add	r4, r7
     48c:	e726      	b.n	2dc <CONFIG_FLASH_SIZE+0xdc>
     48e:	bf00      	nop

00000490 <__aeabi_idiv0>:
     490:	4770      	bx	lr
     492:	bf00      	nop

00000494 <strcmp>:
     494:	f810 2b01 	ldrb.w	r2, [r0], #1
     498:	f811 3b01 	ldrb.w	r3, [r1], #1
     49c:	2a01      	cmp	r2, #1
     49e:	bf28      	it	cs
     4a0:	429a      	cmpcs	r2, r3
     4a2:	d0f7      	beq.n	494 <strcmp>
     4a4:	1ad0      	subs	r0, r2, r3
     4a6:	4770      	bx	lr

000004a8 <strlen>:
     4a8:	4603      	mov	r3, r0
     4aa:	f813 2b01 	ldrb.w	r2, [r3], #1
     4ae:	2a00      	cmp	r2, #0
     4b0:	d1fb      	bne.n	4aa <strlen+0x2>
     4b2:	1a18      	subs	r0, r3, r0
     4b4:	3801      	subs	r0, #1
     4b6:	4770      	bx	lr

000004b8 <main>:
#include <zephyr.h>
#include <sys/printk.h>
#include <stdio.h>

void main(void)
{
     4b8:	b508      	push	{r3, lr}
        printf("Hello... \n");
     4ba:	4804      	ldr	r0, [pc, #16]	; (4cc <main+0x14>)
     4bc:	f004 fd8c 	bl	4fd8 <iprintf>
	printk("Hello World! %s\n", CONFIG_BOARD);
}
     4c0:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	printk("Hello World! %s\n", CONFIG_BOARD);
     4c4:	4902      	ldr	r1, [pc, #8]	; (4d0 <main+0x18>)
     4c6:	4803      	ldr	r0, [pc, #12]	; (4d4 <main+0x1c>)
     4c8:	f005 bbc9 	b.w	5c5e <printk>
     4cc:	000072f0 	.word	0x000072f0
     4d0:	000072fb 	.word	0x000072fb
     4d4:	00007305 	.word	0x00007305

000004d8 <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
     4d8:	680b      	ldr	r3, [r1, #0]
     4da:	3301      	adds	r3, #1
     4dc:	600b      	str	r3, [r1, #0]
	return _char_out(c);
     4de:	4b01      	ldr	r3, [pc, #4]	; (4e4 <char_out+0xc>)
     4e0:	681b      	ldr	r3, [r3, #0]
     4e2:	4718      	bx	r3
     4e4:	20000000 	.word	0x20000000

000004e8 <__printk_hook_install>:
	_char_out = fn;
     4e8:	4b01      	ldr	r3, [pc, #4]	; (4f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x8>)
     4ea:	6018      	str	r0, [r3, #0]
}
     4ec:	4770      	bx	lr
     4ee:	bf00      	nop
     4f0:	20000000 	.word	0x20000000

000004f4 <vprintk>:
#endif
	}
}
#else
void vprintk(const char *fmt, va_list ap)
{
     4f4:	b507      	push	{r0, r1, r2, lr}
     4f6:	460b      	mov	r3, r1
	struct out_context ctx = { 0 };
     4f8:	2100      	movs	r1, #0
{
     4fa:	4602      	mov	r2, r0
	struct out_context ctx = { 0 };
     4fc:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
	k_spinlock_key_t key = k_spin_lock(&lock);
#endif

	cbvprintf(char_out, &ctx, fmt, ap);
     4fe:	4803      	ldr	r0, [pc, #12]	; (50c <vprintk+0x18>)
     500:	a901      	add	r1, sp, #4
     502:	f000 f965 	bl	7d0 <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
	k_spin_unlock(&lock, key);
#endif
}
     506:	b003      	add	sp, #12
     508:	f85d fb04 	ldr.w	pc, [sp], #4
     50c:	000004d9 	.word	0x000004d9

00000510 <vsnprintk>:

	return ret;
}

int vsnprintk(char *str, size_t size, const char *fmt, va_list ap)
{
     510:	b530      	push	{r4, r5, lr}
     512:	b085      	sub	sp, #20
	struct str_context ctx = { str, size, 0 };
     514:	e9cd 0101 	strd	r0, r1, [sp, #4]
{
     518:	4604      	mov	r4, r0
	struct str_context ctx = { str, size, 0 };
     51a:	2500      	movs	r5, #0

	cbvprintf(str_out, &ctx, fmt, ap);
     51c:	a901      	add	r1, sp, #4
     51e:	4805      	ldr	r0, [pc, #20]	; (534 <vsnprintk+0x24>)
	struct str_context ctx = { str, size, 0 };
     520:	9503      	str	r5, [sp, #12]
	cbvprintf(str_out, &ctx, fmt, ap);
     522:	f000 f955 	bl	7d0 <cbvprintf>

	if (ctx.count < ctx.max) {
     526:	e9dd 3002 	ldrd	r3, r0, [sp, #8]
     52a:	4298      	cmp	r0, r3
		str[ctx.count] = '\0';
     52c:	bfb8      	it	lt
     52e:	5425      	strblt	r5, [r4, r0]
	}

	return ctx.count;
}
     530:	b005      	add	sp, #20
     532:	bd30      	pop	{r4, r5, pc}
     534:	00005c39 	.word	0x00005c39

00000538 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     538:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     53c:	f8b0 901c 	ldrh.w	r9, [r0, #28]
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     540:	f019 0808 	ands.w	r8, r9, #8
{
     544:	4604      	mov	r4, r0
     546:	4693      	mov	fp, r2
	if (processing) {
     548:	d00d      	beq.n	566 <process_event+0x2e>
		if (evt == EVT_COMPLETE) {
     54a:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     54c:	bf0c      	ite	eq
     54e:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
     552:	f049 0920 	orrne.w	r9, r9, #32
     556:	f8a0 901c 	strh.w	r9, [r0, #28]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     55a:	f38b 8811 	msr	BASEPRI, fp
     55e:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     562:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     566:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
     56a:	2902      	cmp	r1, #2
     56c:	d107      	bne.n	57e <process_event+0x46>
			evt = process_recheck(mgr);
     56e:	4620      	mov	r0, r4
     570:	f005 fb8f 	bl	5c92 <process_recheck>
		if (evt == EVT_NOP) {
     574:	2800      	cmp	r0, #0
     576:	d0f0      	beq.n	55a <process_event+0x22>
		if (evt == EVT_COMPLETE) {
     578:	2801      	cmp	r0, #1
     57a:	8ba3      	ldrh	r3, [r4, #28]
     57c:	d150      	bne.n	620 <process_event+0xe8>
			res = mgr->last_res;
     57e:	69a7      	ldr	r7, [r4, #24]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     580:	8ba1      	ldrh	r1, [r4, #28]
	if (res < 0) {
     582:	2f00      	cmp	r7, #0
     584:	da15      	bge.n	5b2 <process_event+0x7a>
		*clients = mgr->clients;
     586:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     588:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
     58c:	e9c4 8800 	strd	r8, r8, [r4]
     590:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
     594:	83a1      	strh	r1, [r4, #28]
		onoff_transition_fn transit = NULL;
     596:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     598:	8ba1      	ldrh	r1, [r4, #28]
     59a:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     59e:	45ca      	cmp	sl, r9
     5a0:	d002      	beq.n	5a8 <process_event+0x70>
		if (do_monitors
     5a2:	68a3      	ldr	r3, [r4, #8]
     5a4:	2b00      	cmp	r3, #0
     5a6:	d15c      	bne.n	662 <process_event+0x12a>
		    || !sys_slist_is_empty(&clients)
     5a8:	b90d      	cbnz	r5, 5ae <process_event+0x76>
		    || (transit != NULL)) {
     5aa:	2e00      	cmp	r6, #0
     5ac:	d074      	beq.n	698 <process_event+0x160>
     5ae:	2300      	movs	r3, #0
     5b0:	e058      	b.n	664 <process_event+0x12c>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     5b2:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
     5b6:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
     5b8:	2a01      	cmp	r2, #1
     5ba:	d820      	bhi.n	5fe <process_event+0xc6>
		*clients = mgr->clients;
     5bc:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
     5c0:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
     5c2:	6825      	ldr	r5, [r4, #0]
	list->head = NULL;
     5c4:	b289      	uxth	r1, r1
	list->tail = NULL;
     5c6:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
     5ca:	d10c      	bne.n	5e6 <process_event+0xae>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     5cc:	2d00      	cmp	r5, #0
     5ce:	462b      	mov	r3, r5
     5d0:	bf38      	it	cc
     5d2:	2300      	movcc	r3, #0
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     5d4:	b12b      	cbz	r3, 5e2 <process_event+0xaa>
				mgr->refs += 1U;
     5d6:	8be2      	ldrh	r2, [r4, #30]
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next_no_check(sys_snode_t *node);

Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     5d8:	681b      	ldr	r3, [r3, #0]
     5da:	3201      	adds	r2, #1
     5dc:	83e2      	strh	r2, [r4, #30]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     5de:	2b00      	cmp	r3, #0
     5e0:	d1f8      	bne.n	5d4 <process_event+0x9c>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     5e2:	f041 0102 	orr.w	r1, r1, #2
	mgr->flags = (state & ONOFF_STATE_MASK)
     5e6:	83a1      	strh	r1, [r4, #28]
		if (process_recheck(mgr) != EVT_NOP) {
     5e8:	4620      	mov	r0, r4
     5ea:	f005 fb52 	bl	5c92 <process_recheck>
     5ee:	4606      	mov	r6, r0
     5f0:	2800      	cmp	r0, #0
     5f2:	d0d1      	beq.n	598 <process_event+0x60>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     5f4:	8ba3      	ldrh	r3, [r4, #28]
     5f6:	f043 0320 	orr.w	r3, r3, #32
     5fa:	83a3      	strh	r3, [r4, #28]
     5fc:	e7cb      	b.n	596 <process_event+0x5e>
	} else if (state == ONOFF_STATE_TO_OFF) {
     5fe:	2b04      	cmp	r3, #4
     600:	d10c      	bne.n	61c <process_event+0xe4>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     602:	f021 0107 	bic.w	r1, r1, #7
     606:	b289      	uxth	r1, r1
	mgr->flags = (state & ONOFF_STATE_MASK)
     608:	83a1      	strh	r1, [r4, #28]
		if (process_recheck(mgr) != EVT_NOP) {
     60a:	4620      	mov	r0, r4
     60c:	f005 fb41 	bl	5c92 <process_recheck>
     610:	4605      	mov	r5, r0
     612:	2800      	cmp	r0, #0
     614:	d0bf      	beq.n	596 <process_event+0x5e>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     616:	f041 0120 	orr.w	r1, r1, #32
     61a:	83a1      	strh	r1, [r4, #28]
     61c:	2500      	movs	r5, #0
     61e:	e7ba      	b.n	596 <process_event+0x5e>
		} else if (evt == EVT_START) {
     620:	2803      	cmp	r0, #3
     622:	d109      	bne.n	638 <process_event+0x100>
			transit = mgr->transitions->start;
     624:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     626:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
     62a:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     62c:	f043 0306 	orr.w	r3, r3, #6
	mgr->flags = (state & ONOFF_STATE_MASK)
     630:	83a3      	strh	r3, [r4, #28]
}
     632:	2500      	movs	r5, #0
		res = 0;
     634:	462f      	mov	r7, r5
     636:	e7af      	b.n	598 <process_event+0x60>
		} else if (evt == EVT_STOP) {
     638:	2804      	cmp	r0, #4
     63a:	d106      	bne.n	64a <process_event+0x112>
			transit = mgr->transitions->stop;
     63c:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     63e:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
     642:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     644:	f043 0304 	orr.w	r3, r3, #4
     648:	e7f2      	b.n	630 <process_event+0xf8>
		} else if (evt == EVT_RESET) {
     64a:	2805      	cmp	r0, #5
     64c:	d106      	bne.n	65c <process_event+0x124>
			transit = mgr->transitions->reset;
     64e:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     650:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
     654:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     656:	f043 0305 	orr.w	r3, r3, #5
     65a:	e7e9      	b.n	630 <process_event+0xf8>
     65c:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
     65e:	462e      	mov	r6, r5
     660:	e7e8      	b.n	634 <process_event+0xfc>
				   && !sys_slist_is_empty(&mgr->monitors);
     662:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     664:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     668:	83a1      	strh	r1, [r4, #28]
     66a:	f38b 8811 	msr	BASEPRI, fp
     66e:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
     672:	bb03      	cbnz	r3, 6b6 <process_event+0x17e>
	while (!sys_slist_is_empty(list)) {
     674:	2d00      	cmp	r5, #0
     676:	d133      	bne.n	6e0 <process_event+0x1a8>
			if (transit != NULL) {
     678:	b116      	cbz	r6, 680 <process_event+0x148>
				transit(mgr, transition_complete);
     67a:	4921      	ldr	r1, [pc, #132]	; (700 <process_event+0x1c8>)
     67c:	4620      	mov	r0, r4
     67e:	47b0      	blx	r6
	__asm__ volatile(
     680:	f04f 0320 	mov.w	r3, #32
     684:	f3ef 8b11 	mrs	fp, BASEPRI
     688:	f383 8811 	msr	BASEPRI, r3
     68c:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     690:	8ba3      	ldrh	r3, [r4, #28]
     692:	f023 0308 	bic.w	r3, r3, #8
     696:	83a3      	strh	r3, [r4, #28]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     698:	8ba3      	ldrh	r3, [r4, #28]
     69a:	06da      	lsls	r2, r3, #27
     69c:	d528      	bpl.n	6f0 <process_event+0x1b8>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     69e:	f023 0310 	bic.w	r3, r3, #16
     6a2:	83a3      	strh	r3, [r4, #28]
			evt = EVT_COMPLETE;
     6a4:	2101      	movs	r1, #1
		state = mgr->flags & ONOFF_STATE_MASK;
     6a6:	f8b4 901c 	ldrh.w	r9, [r4, #28]
     6aa:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
     6ae:	2900      	cmp	r1, #0
     6b0:	f47f af5b 	bne.w	56a <process_event+0x32>
out:
     6b4:	e751      	b.n	55a <process_event+0x22>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     6b6:	68a1      	ldr	r1, [r4, #8]
     6b8:	2900      	cmp	r1, #0
     6ba:	d0db      	beq.n	674 <process_event+0x13c>
	return node->next;
     6bc:	680b      	ldr	r3, [r1, #0]
		mon->callback(mgr, mon, state, res);
     6be:	f8d1 b004 	ldr.w	fp, [r1, #4]
     6c2:	2b00      	cmp	r3, #0
     6c4:	bf38      	it	cc
     6c6:	2300      	movcc	r3, #0
     6c8:	4699      	mov	r9, r3
     6ca:	4652      	mov	r2, sl
     6cc:	463b      	mov	r3, r7
     6ce:	4620      	mov	r0, r4
     6d0:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     6d2:	f1b9 0f00 	cmp.w	r9, #0
     6d6:	d0cd      	beq.n	674 <process_event+0x13c>
     6d8:	f8d9 3000 	ldr.w	r3, [r9]
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     6dc:	4649      	mov	r1, r9
     6de:	e7ee      	b.n	6be <process_event+0x186>
 *
 * @return A pointer to the first node of the list
 */
static inline sys_snode_t *sys_slist_get_not_empty(sys_slist_t *list);

Z_GENLIST_GET_NOT_EMPTY(slist, snode)
     6e0:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
     6e2:	463b      	mov	r3, r7
     6e4:	4652      	mov	r2, sl
     6e6:	4620      	mov	r0, r4
     6e8:	682d      	ldr	r5, [r5, #0]
     6ea:	f005 faee 	bl	5cca <notify_one>
     6ee:	e7c1      	b.n	674 <process_event+0x13c>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     6f0:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     6f4:	bf1e      	ittt	ne
     6f6:	f023 0320 	bicne.w	r3, r3, #32
     6fa:	83a3      	strhne	r3, [r4, #28]
			evt = EVT_RECHECK;
     6fc:	2102      	movne	r1, #2
     6fe:	e7d2      	b.n	6a6 <process_event+0x16e>
     700:	00005cf7 	.word	0x00005cf7

00000704 <extract_decimal>:
 * the referenced text.
 *
 * @return the decoded integer value.
 */
static size_t extract_decimal(const char **str)
{
     704:	b5f0      	push	{r4, r5, r6, r7, lr}
	const char *sp = *str;
	size_t val = 0;

	while (isdigit((int)(unsigned char)*sp)) {
     706:	4e09      	ldr	r6, [pc, #36]	; (72c <extract_decimal+0x28>)
     708:	6801      	ldr	r1, [r0, #0]
{
     70a:	4602      	mov	r2, r0
		val = 10U * val + *sp++ - '0';
     70c:	270a      	movs	r7, #10
	size_t val = 0;
     70e:	2000      	movs	r0, #0
     710:	460c      	mov	r4, r1
	while (isdigit((int)(unsigned char)*sp)) {
     712:	3101      	adds	r1, #1
     714:	7823      	ldrb	r3, [r4, #0]
     716:	5d9d      	ldrb	r5, [r3, r6]
     718:	076d      	lsls	r5, r5, #29
     71a:	d401      	bmi.n	720 <extract_decimal+0x1c>
	}
	*str = sp;
     71c:	6014      	str	r4, [r2, #0]
	return val;
}
     71e:	bdf0      	pop	{r4, r5, r6, r7, pc}
		val = 10U * val + *sp++ - '0';
     720:	fb07 3300 	mla	r3, r7, r0, r3
     724:	f1a3 0030 	sub.w	r0, r3, #48	; 0x30
     728:	e7f2      	b.n	710 <extract_decimal+0xc>
     72a:	bf00      	nop
     72c:	000079da 	.word	0x000079da

00000730 <encode_uint>:
 */
static char *encode_uint(uint_value_type value,
			 struct conversion *conv,
			 char *bps,
			 const char *bpe)
{
     730:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
     734:	4614      	mov	r4, r2
     736:	4699      	mov	r9, r3
	bool upcase = isupper((int)conv->specifier);
     738:	78d3      	ldrb	r3, [r2, #3]
     73a:	4a24      	ldr	r2, [pc, #144]	; (7cc <encode_uint+0x9c>)
     73c:	f813 a002 	ldrb.w	sl, [r3, r2]
	switch (specifier) {
     740:	2b6f      	cmp	r3, #111	; 0x6f
     742:	f00a 0203 	and.w	r2, sl, #3
{
     746:	4606      	mov	r6, r0
     748:	460f      	mov	r7, r1
     74a:	9201      	str	r2, [sp, #4]
	switch (specifier) {
     74c:	d02d      	beq.n	7aa <encode_uint+0x7a>
     74e:	d828      	bhi.n	7a2 <encode_uint+0x72>
		return 16;
     750:	2b58      	cmp	r3, #88	; 0x58
     752:	bf14      	ite	ne
     754:	250a      	movne	r5, #10
     756:	2510      	moveq	r5, #16
	const unsigned int radix = conversion_radix(conv->specifier);
	char *bp = bps + (bpe - bps);
     758:	f8dd 8030 	ldr.w	r8, [sp, #48]	; 0x30

	do {
		unsigned int lsv = (unsigned int)(value % radix);
     75c:	46aa      	mov	sl, r5
     75e:	f04f 0b00 	mov.w	fp, #0
     762:	4652      	mov	r2, sl
     764:	465b      	mov	r3, fp
     766:	4630      	mov	r0, r6
     768:	4639      	mov	r1, r7
     76a:	f7ff fd19 	bl	1a0 <__aeabi_uldivmod>

		*--bp = (lsv <= 9) ? ('0' + lsv)
     76e:	2a09      	cmp	r2, #9
     770:	b2d3      	uxtb	r3, r2
     772:	d81f      	bhi.n	7b4 <encode_uint+0x84>
     774:	3330      	adds	r3, #48	; 0x30
			: upcase ? ('A' + lsv - 10) : ('a' + lsv - 10);
		value /= radix;
	} while ((value != 0) && (bps < bp));
     776:	455f      	cmp	r7, fp
		*--bp = (lsv <= 9) ? ('0' + lsv)
     778:	b2db      	uxtb	r3, r3
	} while ((value != 0) && (bps < bp));
     77a:	bf08      	it	eq
     77c:	4556      	cmpeq	r6, sl
		*--bp = (lsv <= 9) ? ('0' + lsv)
     77e:	f808 3d01 	strb.w	r3, [r8, #-1]!
	} while ((value != 0) && (bps < bp));
     782:	d301      	bcc.n	788 <encode_uint+0x58>
     784:	45c8      	cmp	r8, r9
     786:	d812      	bhi.n	7ae <encode_uint+0x7e>

	/* Record required alternate forms.  This can be determined
	 * from the radix without re-checking specifier.
	 */
	if (conv->flag_hash) {
     788:	7823      	ldrb	r3, [r4, #0]
     78a:	069b      	lsls	r3, r3, #26
     78c:	d505      	bpl.n	79a <encode_uint+0x6a>
		if (radix == 8) {
     78e:	2d08      	cmp	r5, #8
     790:	d116      	bne.n	7c0 <encode_uint+0x90>
			conv->altform_0 = true;
     792:	78a3      	ldrb	r3, [r4, #2]
     794:	f043 0308 	orr.w	r3, r3, #8
		} else if (radix == 16) {
			conv->altform_0c = true;
     798:	70a3      	strb	r3, [r4, #2]
			;
		}
	}

	return bp;
}
     79a:	4640      	mov	r0, r8
     79c:	b003      	add	sp, #12
     79e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	switch (specifier) {
     7a2:	f003 03f7 	and.w	r3, r3, #247	; 0xf7
		return 16;
     7a6:	2b70      	cmp	r3, #112	; 0x70
     7a8:	e7d3      	b.n	752 <encode_uint+0x22>
	switch (specifier) {
     7aa:	2508      	movs	r5, #8
     7ac:	e7d4      	b.n	758 <encode_uint+0x28>
		value /= radix;
     7ae:	4606      	mov	r6, r0
     7b0:	460f      	mov	r7, r1
     7b2:	e7d6      	b.n	762 <encode_uint+0x32>
		*--bp = (lsv <= 9) ? ('0' + lsv)
     7b4:	9a01      	ldr	r2, [sp, #4]
     7b6:	2a01      	cmp	r2, #1
     7b8:	bf0c      	ite	eq
     7ba:	3337      	addeq	r3, #55	; 0x37
     7bc:	3357      	addne	r3, #87	; 0x57
     7be:	e7da      	b.n	776 <encode_uint+0x46>
		} else if (radix == 16) {
     7c0:	2d10      	cmp	r5, #16
     7c2:	d1ea      	bne.n	79a <encode_uint+0x6a>
			conv->altform_0c = true;
     7c4:	78a3      	ldrb	r3, [r4, #2]
     7c6:	f043 0310 	orr.w	r3, r3, #16
     7ca:	e7e5      	b.n	798 <encode_uint+0x68>
     7cc:	000079da 	.word	0x000079da

000007d0 <cbvprintf>:

	return (int)count;
}

int cbvprintf(cbprintf_cb out, void *ctx, const char *fp, va_list ap)
{
     7d0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     7d4:	4682      	mov	sl, r0
     7d6:	b093      	sub	sp, #76	; 0x4c
     7d8:	468b      	mov	fp, r1
     7da:	4691      	mov	r9, r2
     7dc:	461c      	mov	r4, r3
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
     7de:	2500      	movs	r5, #0
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
     7e0:	f899 0000 	ldrb.w	r0, [r9]
     7e4:	b908      	cbnz	r0, 7ea <cbvprintf+0x1a>
			OUTC(' ');
			--width;
		}
	}

	return count;
     7e6:	4628      	mov	r0, r5
     7e8:	e33a      	b.n	e60 <CONFIG_ISR_STACK_SIZE+0x660>
		if (*fp != '%') {
     7ea:	f109 0301 	add.w	r3, r9, #1
     7ee:	2825      	cmp	r0, #37	; 0x25
     7f0:	9302      	str	r3, [sp, #8]
     7f2:	d006      	beq.n	802 <CONFIG_ISR_STACK_SIZE+0x2>
			OUTC('%');
     7f4:	4659      	mov	r1, fp
     7f6:	47d0      	blx	sl
     7f8:	2800      	cmp	r0, #0
     7fa:	f2c0 8331 	blt.w	e60 <CONFIG_ISR_STACK_SIZE+0x660>
     7fe:	3501      	adds	r5, #1
			break;
     800:	e1f1      	b.n	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
		} state = {
     802:	2218      	movs	r2, #24
     804:	2100      	movs	r1, #0
     806:	a80c      	add	r0, sp, #48	; 0x30
     808:	f006 f988 	bl	6b1c <memset>
	if (*sp == '%') {
     80c:	f899 3001 	ldrb.w	r3, [r9, #1]
     810:	2b25      	cmp	r3, #37	; 0x25
     812:	d059      	beq.n	8c8 <CONFIG_ISR_STACK_SIZE+0xc8>
     814:	9a02      	ldr	r2, [sp, #8]
     816:	4616      	mov	r6, r2
		switch (*sp) {
     818:	f812 3b01 	ldrb.w	r3, [r2], #1
     81c:	2b2b      	cmp	r3, #43	; 0x2b
     81e:	f000 808b 	beq.w	938 <CONFIG_ISR_STACK_SIZE+0x138>
     822:	d879      	bhi.n	918 <CONFIG_ISR_STACK_SIZE+0x118>
     824:	2b20      	cmp	r3, #32
     826:	f000 808c 	beq.w	942 <CONFIG_ISR_STACK_SIZE+0x142>
     82a:	2b23      	cmp	r3, #35	; 0x23
     82c:	f000 808e 	beq.w	94c <CONFIG_ISR_STACK_SIZE+0x14c>
	if (conv->flag_zero && conv->flag_dash) {
     830:	f89d 3038 	ldrb.w	r3, [sp, #56]	; 0x38
     834:	f003 0244 	and.w	r2, r3, #68	; 0x44
     838:	2a44      	cmp	r2, #68	; 0x44
     83a:	d103      	bne.n	844 <CONFIG_ISR_STACK_SIZE+0x44>
		conv->flag_zero = false;
     83c:	f36f 1386 	bfc	r3, #6, #1
     840:	f88d 3038 	strb.w	r3, [sp, #56]	; 0x38
	conv->width_present = true;
     844:	f89d 3038 	ldrb.w	r3, [sp, #56]	; 0x38
     848:	9605      	str	r6, [sp, #20]
     84a:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     84e:	f88d 3038 	strb.w	r3, [sp, #56]	; 0x38
	if (*sp == '*') {
     852:	7833      	ldrb	r3, [r6, #0]
     854:	2b2a      	cmp	r3, #42	; 0x2a
     856:	d17e      	bne.n	956 <CONFIG_ISR_STACK_SIZE+0x156>
		conv->width_star = true;
     858:	f89d 3039 	ldrb.w	r3, [sp, #57]	; 0x39
     85c:	f043 0301 	orr.w	r3, r3, #1
     860:	f88d 3039 	strb.w	r3, [sp, #57]	; 0x39
		return ++sp;
     864:	1c73      	adds	r3, r6, #1
	sp = extract_prec(conv, sp);
     866:	9305      	str	r3, [sp, #20]
	conv->prec_present = (*sp == '.');
     868:	781a      	ldrb	r2, [r3, #0]
     86a:	2a2e      	cmp	r2, #46	; 0x2e
     86c:	f89d 2039 	ldrb.w	r2, [sp, #57]	; 0x39
     870:	bf0c      	ite	eq
     872:	2101      	moveq	r1, #1
     874:	2100      	movne	r1, #0
     876:	f361 0241 	bfi	r2, r1, #1, #1
     87a:	f88d 2039 	strb.w	r2, [sp, #57]	; 0x39
	if (!conv->prec_present) {
     87e:	d10b      	bne.n	898 <CONFIG_ISR_STACK_SIZE+0x98>
	++sp;
     880:	1c5a      	adds	r2, r3, #1
     882:	9205      	str	r2, [sp, #20]
	if (*sp == '*') {
     884:	785a      	ldrb	r2, [r3, #1]
     886:	2a2a      	cmp	r2, #42	; 0x2a
     888:	d17b      	bne.n	982 <CONFIG_ISR_STACK_SIZE+0x182>
		conv->prec_star = true;
     88a:	f89d 2039 	ldrb.w	r2, [sp, #57]	; 0x39
     88e:	f042 0204 	orr.w	r2, r2, #4
     892:	f88d 2039 	strb.w	r2, [sp, #57]	; 0x39
		return ++sp;
     896:	3302      	adds	r3, #2
	switch (*sp) {
     898:	4619      	mov	r1, r3
     89a:	f811 0b01 	ldrb.w	r0, [r1], #1
     89e:	286c      	cmp	r0, #108	; 0x6c
     8a0:	f000 80b6 	beq.w	a10 <CONFIG_ISR_STACK_SIZE+0x210>
     8a4:	d87d      	bhi.n	9a2 <CONFIG_ISR_STACK_SIZE+0x1a2>
     8a6:	2868      	cmp	r0, #104	; 0x68
     8a8:	f000 8084 	beq.w	9b4 <CONFIG_ISR_STACK_SIZE+0x1b4>
     8ac:	286a      	cmp	r0, #106	; 0x6a
     8ae:	f000 80b9 	beq.w	a24 <CONFIG_ISR_STACK_SIZE+0x224>
     8b2:	284c      	cmp	r0, #76	; 0x4c
     8b4:	f000 80bd 	beq.w	a32 <CONFIG_ISR_STACK_SIZE+0x232>
		conv->length_mod = LENGTH_NONE;
     8b8:	f89d 2039 	ldrb.w	r2, [sp, #57]	; 0x39
     8bc:	f36f 02c6 	bfc	r2, #3, #4
     8c0:	f88d 2039 	strb.w	r2, [sp, #57]	; 0x39
		break;
     8c4:	4619      	mov	r1, r3
     8c6:	e080      	b.n	9ca <CONFIG_ISR_STACK_SIZE+0x1ca>
		conv->specifier = *sp++;
     8c8:	f109 0202 	add.w	r2, r9, #2
     8cc:	9202      	str	r2, [sp, #8]
     8ce:	f88d 303b 	strb.w	r3, [sp, #59]	; 0x3b
		if (conv->width_star) {
     8d2:	f89d 3039 	ldrb.w	r3, [sp, #57]	; 0x39
     8d6:	07d9      	lsls	r1, r3, #31
     8d8:	f140 8149 	bpl.w	b6e <CONFIG_ISR_STACK_SIZE+0x36e>
			width = va_arg(ap, int);
     8dc:	f854 8b04 	ldr.w	r8, [r4], #4
			if (width < 0) {
     8e0:	f1b8 0f00 	cmp.w	r8, #0
     8e4:	da07      	bge.n	8f6 <CONFIG_ISR_STACK_SIZE+0xf6>
				conv->flag_dash = true;
     8e6:	f89d 2038 	ldrb.w	r2, [sp, #56]	; 0x38
     8ea:	f042 0204 	orr.w	r2, r2, #4
     8ee:	f88d 2038 	strb.w	r2, [sp, #56]	; 0x38
				width = -width;
     8f2:	f1c8 0800 	rsb	r8, r8, #0
		if (conv->prec_star) {
     8f6:	075a      	lsls	r2, r3, #29
     8f8:	f140 8142 	bpl.w	b80 <CONFIG_ISR_STACK_SIZE+0x380>
			int arg = va_arg(ap, int);
     8fc:	f854 7b04 	ldr.w	r7, [r4], #4
			if (arg < 0) {
     900:	2f00      	cmp	r7, #0
     902:	f280 8141 	bge.w	b88 <CONFIG_ISR_STACK_SIZE+0x388>
				conv->prec_present = false;
     906:	f89d 3039 	ldrb.w	r3, [sp, #57]	; 0x39
     90a:	f36f 0341 	bfc	r3, #1, #1
     90e:	f88d 3039 	strb.w	r3, [sp, #57]	; 0x39
		int precision = -1;
     912:	f04f 37ff 	mov.w	r7, #4294967295
     916:	e137      	b.n	b88 <CONFIG_ISR_STACK_SIZE+0x388>
		switch (*sp) {
     918:	2b2d      	cmp	r3, #45	; 0x2d
     91a:	d006      	beq.n	92a <CONFIG_ISR_STACK_SIZE+0x12a>
     91c:	2b30      	cmp	r3, #48	; 0x30
     91e:	d187      	bne.n	830 <CONFIG_ISR_STACK_SIZE+0x30>
			conv->flag_zero = true;
     920:	f89d 3038 	ldrb.w	r3, [sp, #56]	; 0x38
     924:	f043 0340 	orr.w	r3, r3, #64	; 0x40
     928:	e003      	b.n	932 <CONFIG_ISR_STACK_SIZE+0x132>
			conv->flag_dash = true;
     92a:	f89d 3038 	ldrb.w	r3, [sp, #56]	; 0x38
     92e:	f043 0304 	orr.w	r3, r3, #4
			conv->flag_zero = true;
     932:	f88d 3038 	strb.w	r3, [sp, #56]	; 0x38
			break;
     936:	e76e      	b.n	816 <CONFIG_ISR_STACK_SIZE+0x16>
			conv->flag_plus = true;
     938:	f89d 3038 	ldrb.w	r3, [sp, #56]	; 0x38
     93c:	f043 0308 	orr.w	r3, r3, #8
     940:	e7f7      	b.n	932 <CONFIG_ISR_STACK_SIZE+0x132>
			conv->flag_space = true;
     942:	f89d 3038 	ldrb.w	r3, [sp, #56]	; 0x38
     946:	f043 0310 	orr.w	r3, r3, #16
     94a:	e7f2      	b.n	932 <CONFIG_ISR_STACK_SIZE+0x132>
			conv->flag_hash = true;
     94c:	f89d 3038 	ldrb.w	r3, [sp, #56]	; 0x38
     950:	f043 0320 	orr.w	r3, r3, #32
     954:	e7ed      	b.n	932 <CONFIG_ISR_STACK_SIZE+0x132>
	size_t width = extract_decimal(&sp);
     956:	a805      	add	r0, sp, #20
     958:	f7ff fed4 	bl	704 <extract_decimal>
	if (sp != wp) {
     95c:	9b05      	ldr	r3, [sp, #20]
     95e:	42b3      	cmp	r3, r6
     960:	d081      	beq.n	866 <CONFIG_ISR_STACK_SIZE+0x66>
		conv->unsupported |= ((conv->width_value < 0)
     962:	f89d 1038 	ldrb.w	r1, [sp, #56]	; 0x38
		conv->width_value = width;
     966:	900f      	str	r0, [sp, #60]	; 0x3c
		conv->unsupported |= ((conv->width_value < 0)
     968:	f3c1 0240 	ubfx	r2, r1, #1, #1
     96c:	ea42 72d0 	orr.w	r2, r2, r0, lsr #31
     970:	0052      	lsls	r2, r2, #1
     972:	f062 027f 	orn	r2, r2, #127	; 0x7f
     976:	f001 017d 	and.w	r1, r1, #125	; 0x7d
     97a:	430a      	orrs	r2, r1
     97c:	f88d 2038 	strb.w	r2, [sp, #56]	; 0x38
     980:	e771      	b.n	866 <CONFIG_ISR_STACK_SIZE+0x66>
	size_t prec = extract_decimal(&sp);
     982:	a805      	add	r0, sp, #20
     984:	f7ff febe 	bl	704 <extract_decimal>
	conv->unsupported |= ((conv->prec_value < 0)
     988:	f89d 3038 	ldrb.w	r3, [sp, #56]	; 0x38
	conv->prec_value = prec;
     98c:	9010      	str	r0, [sp, #64]	; 0x40
	conv->unsupported |= ((conv->prec_value < 0)
     98e:	f3c3 0240 	ubfx	r2, r3, #1, #1
     992:	ea42 70d0 	orr.w	r0, r2, r0, lsr #31
     996:	f360 0341 	bfi	r3, r0, #1, #1
     99a:	f88d 3038 	strb.w	r3, [sp, #56]	; 0x38
	return sp;
     99e:	9b05      	ldr	r3, [sp, #20]
     9a0:	e77a      	b.n	898 <CONFIG_ISR_STACK_SIZE+0x98>
	switch (*sp) {
     9a2:	2874      	cmp	r0, #116	; 0x74
     9a4:	f89d 2039 	ldrb.w	r2, [sp, #57]	; 0x39
     9a8:	d040      	beq.n	a2c <CONFIG_ISR_STACK_SIZE+0x22c>
     9aa:	287a      	cmp	r0, #122	; 0x7a
     9ac:	d184      	bne.n	8b8 <CONFIG_ISR_STACK_SIZE+0xb8>
		conv->length_mod = LENGTH_Z;
     9ae:	4613      	mov	r3, r2
     9b0:	2206      	movs	r2, #6
     9b2:	e028      	b.n	a06 <CONFIG_ISR_STACK_SIZE+0x206>
		if (*++sp == 'h') {
     9b4:	785a      	ldrb	r2, [r3, #1]
     9b6:	2a68      	cmp	r2, #104	; 0x68
     9b8:	f89d 2039 	ldrb.w	r2, [sp, #57]	; 0x39
     9bc:	d121      	bne.n	a02 <CONFIG_ISR_STACK_SIZE+0x202>
			conv->length_mod = LENGTH_HH;
     9be:	2101      	movs	r1, #1
			conv->length_mod = LENGTH_LL;
     9c0:	f361 02c6 	bfi	r2, r1, #3, #4
     9c4:	f88d 2039 	strb.w	r2, [sp, #57]	; 0x39
			++sp;
     9c8:	1c99      	adds	r1, r3, #2
	conv->specifier = *sp++;
     9ca:	460b      	mov	r3, r1
     9cc:	f813 2b01 	ldrb.w	r2, [r3], #1
     9d0:	9302      	str	r3, [sp, #8]
	switch (conv->specifier) {
     9d2:	2a78      	cmp	r2, #120	; 0x78
     9d4:	f89d 3039 	ldrb.w	r3, [sp, #57]	; 0x39
	conv->specifier = *sp++;
     9d8:	f88d 203b 	strb.w	r2, [sp, #59]	; 0x3b
	switch (conv->specifier) {
     9dc:	f200 80bf 	bhi.w	b5e <CONFIG_ISR_STACK_SIZE+0x35e>
     9e0:	2a57      	cmp	r2, #87	; 0x57
     9e2:	d833      	bhi.n	a4c <CONFIG_ISR_STACK_SIZE+0x24c>
     9e4:	2a41      	cmp	r2, #65	; 0x41
     9e6:	d003      	beq.n	9f0 <CONFIG_ISR_STACK_SIZE+0x1f0>
     9e8:	3a45      	subs	r2, #69	; 0x45
     9ea:	2a02      	cmp	r2, #2
     9ec:	f200 80b7 	bhi.w	b5e <CONFIG_ISR_STACK_SIZE+0x35e>
		conv->specifier_cat = SPECIFIER_FP;
     9f0:	f89d 303a 	ldrb.w	r3, [sp, #58]	; 0x3a
     9f4:	2204      	movs	r2, #4
     9f6:	f362 0302 	bfi	r3, r2, #0, #3
     9fa:	f88d 303a 	strb.w	r3, [sp, #58]	; 0x3a
			unsupported = true;
     9fe:	2301      	movs	r3, #1
			break;
     a00:	e084      	b.n	b0c <CONFIG_ISR_STACK_SIZE+0x30c>
			conv->length_mod = LENGTH_H;
     a02:	4613      	mov	r3, r2
     a04:	2202      	movs	r2, #2
			conv->length_mod = LENGTH_L;
     a06:	f362 03c6 	bfi	r3, r2, #3, #4
     a0a:	f88d 3039 	strb.w	r3, [sp, #57]	; 0x39
     a0e:	e7dc      	b.n	9ca <CONFIG_ISR_STACK_SIZE+0x1ca>
		if (*++sp == 'l') {
     a10:	785a      	ldrb	r2, [r3, #1]
     a12:	2a6c      	cmp	r2, #108	; 0x6c
     a14:	f89d 2039 	ldrb.w	r2, [sp, #57]	; 0x39
     a18:	d101      	bne.n	a1e <CONFIG_ISR_STACK_SIZE+0x21e>
			conv->length_mod = LENGTH_LL;
     a1a:	2104      	movs	r1, #4
     a1c:	e7d0      	b.n	9c0 <CONFIG_ISR_STACK_SIZE+0x1c0>
			conv->length_mod = LENGTH_L;
     a1e:	4613      	mov	r3, r2
     a20:	2203      	movs	r2, #3
     a22:	e7f0      	b.n	a06 <CONFIG_ISR_STACK_SIZE+0x206>
		conv->length_mod = LENGTH_J;
     a24:	f89d 3039 	ldrb.w	r3, [sp, #57]	; 0x39
     a28:	2205      	movs	r2, #5
     a2a:	e7ec      	b.n	a06 <CONFIG_ISR_STACK_SIZE+0x206>
		conv->length_mod = LENGTH_T;
     a2c:	4613      	mov	r3, r2
     a2e:	2207      	movs	r2, #7
     a30:	e7e9      	b.n	a06 <CONFIG_ISR_STACK_SIZE+0x206>
		conv->unsupported = true;
     a32:	f8bd 3038 	ldrh.w	r3, [sp, #56]	; 0x38
     a36:	f423 43f0 	bic.w	r3, r3, #30720	; 0x7800
     a3a:	f023 0302 	bic.w	r3, r3, #2
     a3e:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
     a42:	f043 0302 	orr.w	r3, r3, #2
     a46:	f8ad 3038 	strh.w	r3, [sp, #56]	; 0x38
		break;
     a4a:	e7be      	b.n	9ca <CONFIG_ISR_STACK_SIZE+0x1ca>
     a4c:	f1a2 0158 	sub.w	r1, r2, #88	; 0x58
     a50:	2920      	cmp	r1, #32
     a52:	f200 8084 	bhi.w	b5e <CONFIG_ISR_STACK_SIZE+0x35e>
     a56:	a001      	add	r0, pc, #4	; (adr r0, a5c <CONFIG_ISR_STACK_SIZE+0x25c>)
     a58:	f850 f021 	ldr.w	pc, [r0, r1, lsl #2]
     a5c:	00000b21 	.word	0x00000b21
     a60:	00000b5f 	.word	0x00000b5f
     a64:	00000b5f 	.word	0x00000b5f
     a68:	00000b5f 	.word	0x00000b5f
     a6c:	00000b5f 	.word	0x00000b5f
     a70:	00000b5f 	.word	0x00000b5f
     a74:	00000b5f 	.word	0x00000b5f
     a78:	00000b5f 	.word	0x00000b5f
     a7c:	00000b5f 	.word	0x00000b5f
     a80:	000009f1 	.word	0x000009f1
     a84:	00000b5f 	.word	0x00000b5f
     a88:	00000b21 	.word	0x00000b21
     a8c:	00000ae1 	.word	0x00000ae1
     a90:	000009f1 	.word	0x000009f1
     a94:	000009f1 	.word	0x000009f1
     a98:	000009f1 	.word	0x000009f1
     a9c:	00000b5f 	.word	0x00000b5f
     aa0:	00000ae1 	.word	0x00000ae1
     aa4:	00000b5f 	.word	0x00000b5f
     aa8:	00000b5f 	.word	0x00000b5f
     aac:	00000b5f 	.word	0x00000b5f
     ab0:	00000b5f 	.word	0x00000b5f
     ab4:	00000b29 	.word	0x00000b29
     ab8:	00000b21 	.word	0x00000b21
     abc:	00000b45 	.word	0x00000b45
     ac0:	00000b5f 	.word	0x00000b5f
     ac4:	00000b5f 	.word	0x00000b5f
     ac8:	00000b45 	.word	0x00000b45
     acc:	00000b5f 	.word	0x00000b5f
     ad0:	00000b21 	.word	0x00000b21
     ad4:	00000b5f 	.word	0x00000b5f
     ad8:	00000b5f 	.word	0x00000b5f
     adc:	00000b21 	.word	0x00000b21
		conv->specifier_cat = SPECIFIER_SINT;
     ae0:	f89d 103a 	ldrb.w	r1, [sp, #58]	; 0x3a
     ae4:	2001      	movs	r0, #1
		if (conv->length_mod == LENGTH_UPPER_L) {
     ae6:	f003 0378 	and.w	r3, r3, #120	; 0x78
		conv->specifier_cat = SPECIFIER_UINT;
     aea:	f360 0102 	bfi	r1, r0, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     aee:	2b40      	cmp	r3, #64	; 0x40
		conv->specifier_cat = SPECIFIER_UINT;
     af0:	f88d 103a 	strb.w	r1, [sp, #58]	; 0x3a
			conv->invalid = true;
     af4:	bf02      	ittt	eq
     af6:	f89d 1038 	ldrbeq.w	r1, [sp, #56]	; 0x38
     afa:	f041 0101 	orreq.w	r1, r1, #1
     afe:	f88d 1038 	strbeq.w	r1, [sp, #56]	; 0x38
		if (conv->specifier == 'c') {
     b02:	2a63      	cmp	r2, #99	; 0x63
     b04:	d131      	bne.n	b6a <CONFIG_ISR_STACK_SIZE+0x36a>
			unsupported = (conv->length_mod != LENGTH_NONE);
     b06:	3b00      	subs	r3, #0
     b08:	bf18      	it	ne
     b0a:	2301      	movne	r3, #1
	conv->unsupported |= unsupported;
     b0c:	f89d 2038 	ldrb.w	r2, [sp, #56]	; 0x38
     b10:	f3c2 0140 	ubfx	r1, r2, #1, #1
     b14:	430b      	orrs	r3, r1
     b16:	f363 0241 	bfi	r2, r3, #1, #1
     b1a:	f88d 2038 	strb.w	r2, [sp, #56]	; 0x38
	return sp;
     b1e:	e6d8      	b.n	8d2 <CONFIG_ISR_STACK_SIZE+0xd2>
		conv->specifier_cat = SPECIFIER_UINT;
     b20:	f89d 103a 	ldrb.w	r1, [sp, #58]	; 0x3a
     b24:	2002      	movs	r0, #2
     b26:	e7de      	b.n	ae6 <CONFIG_ISR_STACK_SIZE+0x2e6>
		conv->specifier_cat = SPECIFIER_PTR;
     b28:	f89d 203a 	ldrb.w	r2, [sp, #58]	; 0x3a
		if (conv->length_mod == LENGTH_UPPER_L) {
     b2c:	f003 0378 	and.w	r3, r3, #120	; 0x78
     b30:	f1a3 0040 	sub.w	r0, r3, #64	; 0x40
		conv->specifier_cat = SPECIFIER_PTR;
     b34:	2103      	movs	r1, #3
     b36:	f361 0202 	bfi	r2, r1, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     b3a:	4243      	negs	r3, r0
		conv->specifier_cat = SPECIFIER_PTR;
     b3c:	f88d 203a 	strb.w	r2, [sp, #58]	; 0x3a
		if (conv->length_mod == LENGTH_UPPER_L) {
     b40:	4143      	adcs	r3, r0
     b42:	e7e3      	b.n	b0c <CONFIG_ISR_STACK_SIZE+0x30c>
		conv->specifier_cat = SPECIFIER_PTR;
     b44:	f89d 203a 	ldrb.w	r2, [sp, #58]	; 0x3a
     b48:	2103      	movs	r1, #3
		if (conv->length_mod != LENGTH_NONE) {
     b4a:	f013 0f78 	tst.w	r3, #120	; 0x78
		conv->specifier_cat = SPECIFIER_PTR;
     b4e:	f361 0202 	bfi	r2, r1, #0, #3
     b52:	f88d 203a 	strb.w	r2, [sp, #58]	; 0x3a
		if (conv->length_mod != LENGTH_NONE) {
     b56:	bf14      	ite	ne
     b58:	2301      	movne	r3, #1
     b5a:	2300      	moveq	r3, #0
     b5c:	e7d6      	b.n	b0c <CONFIG_ISR_STACK_SIZE+0x30c>
		conv->invalid = true;
     b5e:	f89d 3038 	ldrb.w	r3, [sp, #56]	; 0x38
     b62:	f043 0301 	orr.w	r3, r3, #1
     b66:	f88d 3038 	strb.w	r3, [sp, #56]	; 0x38
	bool unsupported = false;
     b6a:	2300      	movs	r3, #0
     b6c:	e7ce      	b.n	b0c <CONFIG_ISR_STACK_SIZE+0x30c>
		} else if (conv->width_present) {
     b6e:	f99d 2038 	ldrsb.w	r2, [sp, #56]	; 0x38
     b72:	2a00      	cmp	r2, #0
			width = conv->width_value;
     b74:	bfb4      	ite	lt
     b76:	f8dd 803c 	ldrlt.w	r8, [sp, #60]	; 0x3c
		int width = -1;
     b7a:	f04f 38ff 	movge.w	r8, #4294967295
     b7e:	e6ba      	b.n	8f6 <CONFIG_ISR_STACK_SIZE+0xf6>
		} else if (conv->prec_present) {
     b80:	079f      	lsls	r7, r3, #30
     b82:	f57f aec6 	bpl.w	912 <CONFIG_ISR_STACK_SIZE+0x112>
			precision = conv->prec_value;
     b86:	9f10      	ldr	r7, [sp, #64]	; 0x40
			= (enum length_mod_enum)conv->length_mod;
     b88:	f89d 1039 	ldrb.w	r1, [sp, #57]	; 0x39
		conv->pad0_value = 0;
     b8c:	2300      	movs	r3, #0
		conv->pad0_pre_exp = 0;
     b8e:	e9cd 330f 	strd	r3, r3, [sp, #60]	; 0x3c
			= (enum specifier_cat_enum)conv->specifier_cat;
     b92:	f89d 303a 	ldrb.w	r3, [sp, #58]	; 0x3a
		enum specifier_cat_enum specifier_cat
     b96:	f003 0307 	and.w	r3, r3, #7
		if (specifier_cat == SPECIFIER_SINT) {
     b9a:	2b01      	cmp	r3, #1
			= (enum length_mod_enum)conv->length_mod;
     b9c:	f3c1 01c3 	ubfx	r1, r1, #3, #4
		if (specifier_cat == SPECIFIER_SINT) {
     ba0:	d137      	bne.n	c12 <CONFIG_ISR_STACK_SIZE+0x412>
			switch (length_mod) {
     ba2:	1ecb      	subs	r3, r1, #3
     ba4:	2b04      	cmp	r3, #4
     ba6:	d821      	bhi.n	bec <CONFIG_ISR_STACK_SIZE+0x3ec>
     ba8:	e8df f003 	tbb	[pc, r3]
     bac:	20070703 	.word	0x20070703
     bb0:	20          	.byte	0x20
     bb1:	00          	.byte	0x00
					value->sint = va_arg(ap, long);
     bb2:	f854 2b04 	ldr.w	r2, [r4], #4
				value->sint = (short)value->sint;
     bb6:	17d3      	asrs	r3, r2, #31
     bb8:	e004      	b.n	bc4 <CONFIG_ISR_STACK_SIZE+0x3c4>
					(sint_value_type)va_arg(ap, intmax_t);
     bba:	3407      	adds	r4, #7
     bbc:	f024 0407 	bic.w	r4, r4, #7
				value->sint =
     bc0:	e8f4 2302 	ldrd	r2, r3, [r4], #8
				value->sint = (short)value->sint;
     bc4:	e9cd 230c 	strd	r2, r3, [sp, #48]	; 0x30
		if (conv->invalid || conv->unsupported) {
     bc8:	f89d 3038 	ldrb.w	r3, [sp, #56]	; 0x38
     bcc:	f013 0603 	ands.w	r6, r3, #3
     bd0:	d055      	beq.n	c7e <CONFIG_ISR_STACK_SIZE+0x47e>
			OUTS(sp, fp);
     bd2:	9b02      	ldr	r3, [sp, #8]
     bd4:	464a      	mov	r2, r9
     bd6:	4659      	mov	r1, fp
     bd8:	4650      	mov	r0, sl
     bda:	f005 f934 	bl	5e46 <outs>
     bde:	2800      	cmp	r0, #0
     be0:	f2c0 813e 	blt.w	e60 <CONFIG_ISR_STACK_SIZE+0x660>
     be4:	4405      	add	r5, r0
			OUTS(bps, bpe);
     be6:	f8dd 9008 	ldr.w	r9, [sp, #8]
     bea:	e5f9      	b.n	7e0 <cbvprintf+0x10>
					(sint_value_type)va_arg(ap, ptrdiff_t);
     bec:	f854 2b04 	ldr.w	r2, [r4], #4
			if (length_mod == LENGTH_HH) {
     bf0:	2901      	cmp	r1, #1
					(sint_value_type)va_arg(ap, ptrdiff_t);
     bf2:	ea4f 73e2 	mov.w	r3, r2, asr #31
     bf6:	e9cd 230c 	strd	r2, r3, [sp, #48]	; 0x30
			if (length_mod == LENGTH_HH) {
     bfa:	d105      	bne.n	c08 <CONFIG_ISR_STACK_SIZE+0x408>
				value->uint = (unsigned char)value->uint;
     bfc:	f89d 3030 	ldrb.w	r3, [sp, #48]	; 0x30
				value->uint = (unsigned short)value->uint;
     c00:	930c      	str	r3, [sp, #48]	; 0x30
     c02:	2300      	movs	r3, #0
     c04:	930d      	str	r3, [sp, #52]	; 0x34
     c06:	e7df      	b.n	bc8 <CONFIG_ISR_STACK_SIZE+0x3c8>
			} else if (length_mod == LENGTH_H) {
     c08:	2902      	cmp	r1, #2
     c0a:	d1dd      	bne.n	bc8 <CONFIG_ISR_STACK_SIZE+0x3c8>
				value->sint = (short)value->sint;
     c0c:	f9bd 2030 	ldrsh.w	r2, [sp, #48]	; 0x30
     c10:	e7d1      	b.n	bb6 <CONFIG_ISR_STACK_SIZE+0x3b6>
		} else if (specifier_cat == SPECIFIER_UINT) {
     c12:	2b02      	cmp	r3, #2
     c14:	d123      	bne.n	c5e <CONFIG_ISR_STACK_SIZE+0x45e>
			switch (length_mod) {
     c16:	1ecb      	subs	r3, r1, #3
     c18:	2b04      	cmp	r3, #4
     c1a:	d813      	bhi.n	c44 <CONFIG_ISR_STACK_SIZE+0x444>
     c1c:	e8df f003 	tbb	[pc, r3]
     c20:	120a0a03 	.word	0x120a0a03
     c24:	12          	.byte	0x12
     c25:	00          	.byte	0x00
					value->uint = (wchar_t)va_arg(ap,
     c26:	6822      	ldr	r2, [r4, #0]
     c28:	920c      	str	r2, [sp, #48]	; 0x30
     c2a:	2300      	movs	r3, #0
     c2c:	1d20      	adds	r0, r4, #4
     c2e:	930d      	str	r3, [sp, #52]	; 0x34
					(uint_value_type)va_arg(ap, size_t);
     c30:	4604      	mov	r4, r0
     c32:	e7c9      	b.n	bc8 <CONFIG_ISR_STACK_SIZE+0x3c8>
					(uint_value_type)va_arg(ap,
     c34:	3407      	adds	r4, #7
     c36:	f024 0007 	bic.w	r0, r4, #7
				value->uint =
     c3a:	e8f0 2302 	ldrd	r2, r3, [r0], #8
     c3e:	e9cd 230c 	strd	r2, r3, [sp, #48]	; 0x30
				break;
     c42:	e7f5      	b.n	c30 <CONFIG_ISR_STACK_SIZE+0x430>
					(uint_value_type)va_arg(ap, size_t);
     c44:	f854 3b04 	ldr.w	r3, [r4], #4
     c48:	930c      	str	r3, [sp, #48]	; 0x30
			if (length_mod == LENGTH_HH) {
     c4a:	2901      	cmp	r1, #1
					(uint_value_type)va_arg(ap, size_t);
     c4c:	f04f 0300 	mov.w	r3, #0
     c50:	930d      	str	r3, [sp, #52]	; 0x34
			if (length_mod == LENGTH_HH) {
     c52:	d0d3      	beq.n	bfc <CONFIG_ISR_STACK_SIZE+0x3fc>
			} else if (length_mod == LENGTH_H) {
     c54:	2902      	cmp	r1, #2
     c56:	d1b7      	bne.n	bc8 <CONFIG_ISR_STACK_SIZE+0x3c8>
				value->uint = (unsigned short)value->uint;
     c58:	f8bd 3030 	ldrh.w	r3, [sp, #48]	; 0x30
     c5c:	e7d0      	b.n	c00 <CONFIG_ISR_STACK_SIZE+0x400>
		} else if (specifier_cat == SPECIFIER_FP) {
     c5e:	2b04      	cmp	r3, #4
     c60:	d107      	bne.n	c72 <CONFIG_ISR_STACK_SIZE+0x472>
			if (length_mod == LENGTH_UPPER_L) {
     c62:	3407      	adds	r4, #7
     c64:	f024 0407 	bic.w	r4, r4, #7
     c68:	e8f4 2302 	ldrd	r2, r3, [r4], #8
				value->ldbl = va_arg(ap, long double);
     c6c:	e9cd 230c 	strd	r2, r3, [sp, #48]	; 0x30
     c70:	e7aa      	b.n	bc8 <CONFIG_ISR_STACK_SIZE+0x3c8>
		} else if (specifier_cat == SPECIFIER_PTR) {
     c72:	2b03      	cmp	r3, #3
			value->ptr = va_arg(ap, void *);
     c74:	bf04      	itt	eq
     c76:	f854 3b04 	ldreq.w	r3, [r4], #4
     c7a:	930c      	streq	r3, [sp, #48]	; 0x30
     c7c:	e7a4      	b.n	bc8 <CONFIG_ISR_STACK_SIZE+0x3c8>
		switch (conv->specifier) {
     c7e:	f89d 003b 	ldrb.w	r0, [sp, #59]	; 0x3b
     c82:	2878      	cmp	r0, #120	; 0x78
     c84:	d8af      	bhi.n	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
     c86:	2862      	cmp	r0, #98	; 0x62
     c88:	d820      	bhi.n	ccc <CONFIG_ISR_STACK_SIZE+0x4cc>
     c8a:	2825      	cmp	r0, #37	; 0x25
     c8c:	f43f adb2 	beq.w	7f4 <cbvprintf+0x24>
     c90:	2858      	cmp	r0, #88	; 0x58
     c92:	d1a8      	bne.n	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
			bps = encode_uint(value->uint, conv, buf, bpe);
     c94:	f10d 032e 	add.w	r3, sp, #46	; 0x2e
     c98:	9300      	str	r3, [sp, #0]
     c9a:	e9dd 010c 	ldrd	r0, r1, [sp, #48]	; 0x30
     c9e:	ab06      	add	r3, sp, #24
     ca0:	aa0e      	add	r2, sp, #56	; 0x38
     ca2:	f7ff fd45 	bl	730 <encode_uint>
     ca6:	4681      	mov	r9, r0
			if (precision >= 0) {
     ca8:	2f00      	cmp	r7, #0
     caa:	f10d 002e 	add.w	r0, sp, #46	; 0x2e
     cae:	db0b      	blt.n	cc8 <CONFIG_ISR_STACK_SIZE+0x4c8>
				conv->flag_zero = false;
     cb0:	f89d 2038 	ldrb.w	r2, [sp, #56]	; 0x38
				size_t len = bpe - bps;
     cb4:	eba0 0309 	sub.w	r3, r0, r9
				conv->flag_zero = false;
     cb8:	f36f 1286 	bfc	r2, #6, #1
				if (len < (size_t)precision) {
     cbc:	429f      	cmp	r7, r3
				conv->flag_zero = false;
     cbe:	f88d 2038 	strb.w	r2, [sp, #56]	; 0x38
				if (len < (size_t)precision) {
     cc2:	d901      	bls.n	cc8 <CONFIG_ISR_STACK_SIZE+0x4c8>
					conv->pad0_value = precision - (int)len;
     cc4:	1aff      	subs	r7, r7, r3
     cc6:	970f      	str	r7, [sp, #60]	; 0x3c
		const char *bpe = buf + sizeof(buf);
     cc8:	4607      	mov	r7, r0
     cca:	e03c      	b.n	d46 <CONFIG_ISR_STACK_SIZE+0x546>
     ccc:	3863      	subs	r0, #99	; 0x63
     cce:	2815      	cmp	r0, #21
     cd0:	d889      	bhi.n	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
     cd2:	a201      	add	r2, pc, #4	; (adr r2, cd8 <CONFIG_ISR_STACK_SIZE+0x4d8>)
     cd4:	f852 f020 	ldr.w	pc, [r2, r0, lsl #2]
     cd8:	00000d57 	.word	0x00000d57
     cdc:	00000db9 	.word	0x00000db9
     ce0:	00000be7 	.word	0x00000be7
     ce4:	00000be7 	.word	0x00000be7
     ce8:	00000be7 	.word	0x00000be7
     cec:	00000be7 	.word	0x00000be7
     cf0:	00000db9 	.word	0x00000db9
     cf4:	00000be7 	.word	0x00000be7
     cf8:	00000be7 	.word	0x00000be7
     cfc:	00000be7 	.word	0x00000be7
     d00:	00000be7 	.word	0x00000be7
     d04:	00000e17 	.word	0x00000e17
     d08:	00000de5 	.word	0x00000de5
     d0c:	00000de9 	.word	0x00000de9
     d10:	00000be7 	.word	0x00000be7
     d14:	00000be7 	.word	0x00000be7
     d18:	00000d31 	.word	0x00000d31
     d1c:	00000be7 	.word	0x00000be7
     d20:	00000de5 	.word	0x00000de5
     d24:	00000be7 	.word	0x00000be7
     d28:	00000be7 	.word	0x00000be7
     d2c:	00000de5 	.word	0x00000de5
			if (precision >= 0) {
     d30:	2f00      	cmp	r7, #0
			bps = (const char *)value->ptr;
     d32:	f8dd 9030 	ldr.w	r9, [sp, #48]	; 0x30
			if (precision >= 0) {
     d36:	db0a      	blt.n	d4e <CONFIG_ISR_STACK_SIZE+0x54e>
				len = strnlen(bps, precision);
     d38:	4639      	mov	r1, r7
     d3a:	4648      	mov	r0, r9
     d3c:	f005 ff11 	bl	6b62 <strnlen>
			bpe = bps + len;
     d40:	eb09 0700 	add.w	r7, r9, r0
		char sign = 0;
     d44:	2600      	movs	r6, #0
		if (bps == NULL) {
     d46:	f1b9 0f00 	cmp.w	r9, #0
     d4a:	d10c      	bne.n	d66 <CONFIG_ISR_STACK_SIZE+0x566>
     d4c:	e74b      	b.n	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
				len = strlen(bps);
     d4e:	4648      	mov	r0, r9
     d50:	f7ff fbaa 	bl	4a8 <strlen>
     d54:	e7f4      	b.n	d40 <CONFIG_ISR_STACK_SIZE+0x540>
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     d56:	9b0c      	ldr	r3, [sp, #48]	; 0x30
     d58:	f88d 3018 	strb.w	r3, [sp, #24]
			break;
     d5c:	2600      	movs	r6, #0
			bpe = buf + 1;
     d5e:	f10d 0719 	add.w	r7, sp, #25
			bps = buf;
     d62:	f10d 0918 	add.w	r9, sp, #24
		size_t nj_len = (bpe - bps);
     d66:	eba7 0309 	sub.w	r3, r7, r9
		if (sign != 0) {
     d6a:	b106      	cbz	r6, d6e <CONFIG_ISR_STACK_SIZE+0x56e>
			nj_len += 1U;
     d6c:	3301      	adds	r3, #1
		if (conv->altform_0c) {
     d6e:	f89d 203a 	ldrb.w	r2, [sp, #58]	; 0x3a
     d72:	06d0      	lsls	r0, r2, #27
     d74:	d569      	bpl.n	e4a <CONFIG_ISR_STACK_SIZE+0x64a>
			nj_len += 2U;
     d76:	3302      	adds	r3, #2
		if (conv->pad_fp) {
     d78:	0652      	lsls	r2, r2, #25
		nj_len += conv->pad0_value;
     d7a:	990f      	ldr	r1, [sp, #60]	; 0x3c
			nj_len += conv->pad0_pre_exp;
     d7c:	bf48      	it	mi
     d7e:	9a10      	ldrmi	r2, [sp, #64]	; 0x40
		nj_len += conv->pad0_value;
     d80:	440b      	add	r3, r1
			nj_len += conv->pad0_pre_exp;
     d82:	bf48      	it	mi
     d84:	189b      	addmi	r3, r3, r2
		if (width > 0) {
     d86:	f1b8 0f00 	cmp.w	r8, #0
     d8a:	dd76      	ble.n	e7a <CONFIG_ISR_STACK_SIZE+0x67a>
			if (!conv->flag_dash) {
     d8c:	f89d 2038 	ldrb.w	r2, [sp, #56]	; 0x38
			width -= (int)nj_len;
     d90:	eba8 0803 	sub.w	r8, r8, r3
			if (!conv->flag_dash) {
     d94:	f3c2 0380 	ubfx	r3, r2, #2, #1
     d98:	9303      	str	r3, [sp, #12]
     d9a:	0753      	lsls	r3, r2, #29
     d9c:	d46d      	bmi.n	e7a <CONFIG_ISR_STACK_SIZE+0x67a>
				if (conv->flag_zero) {
     d9e:	0650      	lsls	r0, r2, #25
     da0:	d561      	bpl.n	e66 <CONFIG_ISR_STACK_SIZE+0x666>
					if (sign != 0) {
     da2:	b13e      	cbz	r6, db4 <CONFIG_ISR_STACK_SIZE+0x5b4>
						OUTC(sign);
     da4:	4659      	mov	r1, fp
     da6:	4630      	mov	r0, r6
     da8:	47d0      	blx	sl
     daa:	2800      	cmp	r0, #0
     dac:	db58      	blt.n	e60 <CONFIG_ISR_STACK_SIZE+0x660>
						sign = 0;
     dae:	9b03      	ldr	r3, [sp, #12]
						OUTC(sign);
     db0:	3501      	adds	r5, #1
						sign = 0;
     db2:	461e      	mov	r6, r3
					pad = '0';
     db4:	2330      	movs	r3, #48	; 0x30
     db6:	e057      	b.n	e68 <CONFIG_ISR_STACK_SIZE+0x668>
			if (conv->flag_plus) {
     db8:	071e      	lsls	r6, r3, #28
     dba:	d411      	bmi.n	de0 <CONFIG_ISR_STACK_SIZE+0x5e0>
				sign = ' ';
     dbc:	f013 0610 	ands.w	r6, r3, #16
     dc0:	bf18      	it	ne
     dc2:	2620      	movne	r6, #32
			sint = value->sint;
     dc4:	e9dd 230c 	ldrd	r2, r3, [sp, #48]	; 0x30
			if (sint < 0) {
     dc8:	2a00      	cmp	r2, #0
     dca:	f173 0100 	sbcs.w	r1, r3, #0
     dce:	f6bf af61 	bge.w	c94 <CONFIG_ISR_STACK_SIZE+0x494>
				value->uint = (uint_value_type)-sint;
     dd2:	4252      	negs	r2, r2
     dd4:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
     dd8:	e9cd 230c 	strd	r2, r3, [sp, #48]	; 0x30
				sign = '-';
     ddc:	262d      	movs	r6, #45	; 0x2d
     dde:	e759      	b.n	c94 <CONFIG_ISR_STACK_SIZE+0x494>
				sign = '+';
     de0:	262b      	movs	r6, #43	; 0x2b
     de2:	e7ef      	b.n	dc4 <CONFIG_ISR_STACK_SIZE+0x5c4>
		switch (conv->specifier) {
     de4:	2600      	movs	r6, #0
     de6:	e755      	b.n	c94 <CONFIG_ISR_STACK_SIZE+0x494>
			if (value->ptr != NULL) {
     de8:	980c      	ldr	r0, [sp, #48]	; 0x30
     dea:	b348      	cbz	r0, e40 <CONFIG_ISR_STACK_SIZE+0x640>
				bps = encode_uint((uintptr_t)value->ptr, conv,
     dec:	f10d 032e 	add.w	r3, sp, #46	; 0x2e
     df0:	9300      	str	r3, [sp, #0]
     df2:	aa0e      	add	r2, sp, #56	; 0x38
     df4:	ab06      	add	r3, sp, #24
     df6:	2100      	movs	r1, #0
     df8:	f7ff fc9a 	bl	730 <encode_uint>
				conv->altform_0c = true;
     dfc:	f8bd 303a 	ldrh.w	r3, [sp, #58]	; 0x3a
     e00:	f003 03ef 	and.w	r3, r3, #239	; 0xef
     e04:	f443 43f0 	orr.w	r3, r3, #30720	; 0x7800
     e08:	f043 0310 	orr.w	r3, r3, #16
				bps = encode_uint((uintptr_t)value->ptr, conv,
     e0c:	4681      	mov	r9, r0
				conv->altform_0c = true;
     e0e:	f8ad 303a 	strh.w	r3, [sp, #58]	; 0x3a
		char sign = 0;
     e12:	2600      	movs	r6, #0
				goto prec_int_pad0;
     e14:	e748      	b.n	ca8 <CONFIG_ISR_STACK_SIZE+0x4a8>
				store_count(conv, value->ptr, count);
     e16:	9b0c      	ldr	r3, [sp, #48]	; 0x30
	switch ((enum length_mod_enum)conv->length_mod) {
     e18:	2907      	cmp	r1, #7
     e1a:	f63f aee4 	bhi.w	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
     e1e:	e8df f001 	tbb	[pc, r1]
     e22:	040d      	.short	0x040d
     e24:	08080d06 	.word	0x08080d06
     e28:	0d0d      	.short	0x0d0d
		*(signed char *)dp = (signed char)count;
     e2a:	701d      	strb	r5, [r3, #0]
		break;
     e2c:	e6db      	b.n	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
		*(short *)dp = (short)count;
     e2e:	801d      	strh	r5, [r3, #0]
		break;
     e30:	e6d9      	b.n	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
		*(intmax_t *)dp = (intmax_t)count;
     e32:	4628      	mov	r0, r5
     e34:	17e9      	asrs	r1, r5, #31
     e36:	e9c3 0100 	strd	r0, r1, [r3]
		break;
     e3a:	e6d4      	b.n	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
     e3c:	601d      	str	r5, [r3, #0]
		break;
     e3e:	e6d2      	b.n	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
			bpe = bps + 5;
     e40:	4f2e      	ldr	r7, [pc, #184]	; (efc <CONFIG_ISR_STACK_SIZE+0x6fc>)
     e42:	4606      	mov	r6, r0
			bps = "(nil)";
     e44:	f1a7 0905 	sub.w	r9, r7, #5
     e48:	e78d      	b.n	d66 <CONFIG_ISR_STACK_SIZE+0x566>
		} else if (conv->altform_0) {
     e4a:	0711      	lsls	r1, r2, #28
			nj_len += 1U;
     e4c:	bf48      	it	mi
     e4e:	3301      	addmi	r3, #1
     e50:	e792      	b.n	d78 <CONFIG_ISR_STACK_SIZE+0x578>
					OUTC(pad);
     e52:	4618      	mov	r0, r3
     e54:	4659      	mov	r1, fp
     e56:	9303      	str	r3, [sp, #12]
     e58:	47d0      	blx	sl
     e5a:	2800      	cmp	r0, #0
     e5c:	9b03      	ldr	r3, [sp, #12]
     e5e:	da04      	bge.n	e6a <CONFIG_ISR_STACK_SIZE+0x66a>
#undef OUTS
#undef OUTC
}
     e60:	b013      	add	sp, #76	; 0x4c
     e62:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				char pad = ' ';
     e66:	2320      	movs	r3, #32
     e68:	4445      	add	r5, r8
     e6a:	4642      	mov	r2, r8
				while (width-- > 0) {
     e6c:	2a00      	cmp	r2, #0
     e6e:	eba5 0108 	sub.w	r1, r5, r8
     e72:	f108 38ff 	add.w	r8, r8, #4294967295
     e76:	dcec      	bgt.n	e52 <CONFIG_ISR_STACK_SIZE+0x652>
     e78:	460d      	mov	r5, r1
		if (sign != 0) {
     e7a:	b12e      	cbz	r6, e88 <CONFIG_ISR_STACK_SIZE+0x688>
			OUTC(sign);
     e7c:	4659      	mov	r1, fp
     e7e:	4630      	mov	r0, r6
     e80:	47d0      	blx	sl
     e82:	2800      	cmp	r0, #0
     e84:	dbec      	blt.n	e60 <CONFIG_ISR_STACK_SIZE+0x660>
     e86:	3501      	adds	r5, #1
			if (conv->altform_0c | conv->altform_0) {
     e88:	f89d 303a 	ldrb.w	r3, [sp, #58]	; 0x3a
     e8c:	06d9      	lsls	r1, r3, #27
     e8e:	d401      	bmi.n	e94 <CONFIG_ISR_STACK_SIZE+0x694>
     e90:	071a      	lsls	r2, r3, #28
     e92:	d505      	bpl.n	ea0 <CONFIG_ISR_STACK_SIZE+0x6a0>
				OUTC('0');
     e94:	4659      	mov	r1, fp
     e96:	2030      	movs	r0, #48	; 0x30
     e98:	47d0      	blx	sl
     e9a:	2800      	cmp	r0, #0
     e9c:	dbe0      	blt.n	e60 <CONFIG_ISR_STACK_SIZE+0x660>
     e9e:	3501      	adds	r5, #1
			if (conv->altform_0c) {
     ea0:	f89d 303a 	ldrb.w	r3, [sp, #58]	; 0x3a
     ea4:	06db      	lsls	r3, r3, #27
     ea6:	d506      	bpl.n	eb6 <CONFIG_ISR_STACK_SIZE+0x6b6>
				OUTC(conv->specifier);
     ea8:	f89d 003b 	ldrb.w	r0, [sp, #59]	; 0x3b
     eac:	4659      	mov	r1, fp
     eae:	47d0      	blx	sl
     eb0:	2800      	cmp	r0, #0
     eb2:	dbd5      	blt.n	e60 <CONFIG_ISR_STACK_SIZE+0x660>
     eb4:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
     eb6:	9e0f      	ldr	r6, [sp, #60]	; 0x3c
     eb8:	442e      	add	r6, r5
     eba:	1b73      	subs	r3, r6, r5
     ebc:	2b00      	cmp	r3, #0
     ebe:	dc15      	bgt.n	eec <CONFIG_ISR_STACK_SIZE+0x6ec>
			OUTS(bps, bpe);
     ec0:	463b      	mov	r3, r7
     ec2:	464a      	mov	r2, r9
     ec4:	4659      	mov	r1, fp
     ec6:	4650      	mov	r0, sl
     ec8:	f004 ffbd 	bl	5e46 <outs>
     ecc:	2800      	cmp	r0, #0
     ece:	dbc7      	blt.n	e60 <CONFIG_ISR_STACK_SIZE+0x660>
     ed0:	4405      	add	r5, r0
		while (width > 0) {
     ed2:	44a8      	add	r8, r5
     ed4:	eba8 0305 	sub.w	r3, r8, r5
     ed8:	2b00      	cmp	r3, #0
     eda:	f77f ae84 	ble.w	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
			OUTC(' ');
     ede:	4659      	mov	r1, fp
     ee0:	2020      	movs	r0, #32
     ee2:	47d0      	blx	sl
     ee4:	2800      	cmp	r0, #0
     ee6:	dbbb      	blt.n	e60 <CONFIG_ISR_STACK_SIZE+0x660>
     ee8:	3501      	adds	r5, #1
			--width;
     eea:	e7f3      	b.n	ed4 <CONFIG_ISR_STACK_SIZE+0x6d4>
				OUTC('0');
     eec:	4659      	mov	r1, fp
     eee:	2030      	movs	r0, #48	; 0x30
     ef0:	47d0      	blx	sl
     ef2:	2800      	cmp	r0, #0
     ef4:	dbb4      	blt.n	e60 <CONFIG_ISR_STACK_SIZE+0x660>
     ef6:	3501      	adds	r5, #1
     ef8:	e7df      	b.n	eba <CONFIG_ISR_STACK_SIZE+0x6ba>
     efa:	bf00      	nop
     efc:	0000731b 	.word	0x0000731b

00000f00 <enable_logger>:

K_KERNEL_STACK_DEFINE(logging_stack, CONFIG_LOG_PROCESS_THREAD_STACK_SIZE);
struct k_thread logging_thread;

static int enable_logger(const struct device *arg)
{
     f00:	b530      	push	{r4, r5, lr}
	ARG_UNUSED(arg);

	if (IS_ENABLED(CONFIG_LOG_PROCESS_THREAD)) {
		k_timer_init(&log_process_thread_timer,
     f02:	4910      	ldr	r1, [pc, #64]	; (f44 <enable_logger+0x44>)
     f04:	4810      	ldr	r0, [pc, #64]	; (f48 <enable_logger+0x48>)
{
     f06:	b089      	sub	sp, #36	; 0x24
		k_timer_init(&log_process_thread_timer,
     f08:	2200      	movs	r2, #0
     f0a:	f005 fdcb 	bl	6aa4 <k_timer_init>
		/* coverity[OVERRUN] */
		return (k_tid_t) arch_syscall_invoke6(*(uintptr_t *)&new_thread, *(uintptr_t *)&stack, *(uintptr_t *)&stack_size, *(uintptr_t *)&entry, *(uintptr_t *)&p1, (uintptr_t) &more, K_SYSCALL_K_THREAD_CREATE);
	}
#endif
	compiler_barrier();
	return z_impl_k_thread_create(new_thread, stack, stack_size, entry, p1, p2, p3, prio, options, delay);
     f0e:	4d0f      	ldr	r5, [pc, #60]	; (f4c <enable_logger+0x4c>)
     f10:	490f      	ldr	r1, [pc, #60]	; (f50 <enable_logger+0x50>)
     f12:	2200      	movs	r2, #0
     f14:	2300      	movs	r3, #0
     f16:	e9cd 2306 	strd	r2, r3, [sp, #24]
     f1a:	2400      	movs	r4, #0
     f1c:	230e      	movs	r3, #14
     f1e:	e9cd 3403 	strd	r3, r4, [sp, #12]
     f22:	e9cd 4401 	strd	r4, r4, [sp, #4]
     f26:	4b0b      	ldr	r3, [pc, #44]	; (f54 <enable_logger+0x54>)
     f28:	9400      	str	r4, [sp, #0]
     f2a:	f44f 7240 	mov.w	r2, #768	; 0x300
     f2e:	4628      	mov	r0, r5
     f30:	f002 ffd4 	bl	3edc <z_impl_k_thread_create>
		/* coverity[OVERRUN] */
		return (int) arch_syscall_invoke2(*(uintptr_t *)&thread, *(uintptr_t *)&str, K_SYSCALL_K_THREAD_NAME_SET);
	}
#endif
	compiler_barrier();
	return z_impl_k_thread_name_set(thread, str);
     f34:	4908      	ldr	r1, [pc, #32]	; (f58 <enable_logger+0x58>)
     f36:	4628      	mov	r0, r5
     f38:	f005 fc3c 	bl	67b4 <z_impl_k_thread_name_set>
	} else {
		log_init();
	}

	return 0;
}
     f3c:	4620      	mov	r0, r4
     f3e:	b009      	add	sp, #36	; 0x24
     f40:	bd30      	pop	{r4, r5, pc}
     f42:	bf00      	nop
     f44:	00000f5d 	.word	0x00000f5d
     f48:	20000110 	.word	0x20000110
     f4c:	20000148 	.word	0x20000148
     f50:	20000ad8 	.word	0x20000ad8
     f54:	000013e9 	.word	0x000013e9
     f58:	0000731c 	.word	0x0000731c

00000f5c <log_process_thread_timer_expiry_fn>:
		arch_syscall_invoke1(*(uintptr_t *)&sem, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
     f5c:	4801      	ldr	r0, [pc, #4]	; (f64 <log_process_thread_timer_expiry_fn+0x8>)
     f5e:	f003 b921 	b.w	41a4 <z_impl_k_sem_give>
     f62:	bf00      	nop
     f64:	200000fc 	.word	0x200000fc

00000f68 <z_log_get_s_mask>:
{
     f68:	b5f0      	push	{r4, r5, r6, r7, lr}
     f6a:	4605      	mov	r5, r0
		} else if (arm && isalpha((int)curr)) {
     f6c:	4e0f      	ldr	r6, [pc, #60]	; (fac <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0xc>)
	uint32_t mask = 0U;
     f6e:	2000      	movs	r0, #0
	uint32_t arg = 0U;
     f70:	4603      	mov	r3, r0
	bool arm = false;
     f72:	4602      	mov	r2, r0
				mask |= BIT(arg);
     f74:	2701      	movs	r7, #1
	while ((curr = *str++) && arg < nargs) {
     f76:	f815 4b01 	ldrb.w	r4, [r5], #1
     f7a:	b10c      	cbz	r4, f80 <z_log_get_s_mask+0x18>
     f7c:	428b      	cmp	r3, r1
     f7e:	d300      	bcc.n	f82 <z_log_get_s_mask+0x1a>
}
     f80:	bdf0      	pop	{r4, r5, r6, r7, pc}
		if (curr == '%') {
     f82:	2c25      	cmp	r4, #37	; 0x25
     f84:	d102      	bne.n	f8c <z_log_get_s_mask+0x24>
			arm = !arm;
     f86:	f082 0201 	eor.w	r2, r2, #1
     f8a:	e7f4      	b.n	f76 <z_log_get_s_mask+0xe>
		} else if (arm && isalpha((int)curr)) {
     f8c:	2a00      	cmp	r2, #0
     f8e:	d0f2      	beq.n	f76 <z_log_get_s_mask+0xe>
     f90:	f814 c006 	ldrb.w	ip, [r4, r6]
     f94:	f01c 0f03 	tst.w	ip, #3
     f98:	d0ed      	beq.n	f76 <z_log_get_s_mask+0xe>
			if (curr == 's') {
     f9a:	2c73      	cmp	r4, #115	; 0x73
				mask |= BIT(arg);
     f9c:	bf04      	itt	eq
     f9e:	fa07 f203 	lsleq.w	r2, r7, r3
     fa2:	4310      	orreq	r0, r2
			arg++;
     fa4:	3301      	adds	r3, #1
			arm = false;
     fa6:	2200      	movs	r2, #0
     fa8:	e7e5      	b.n	f76 <z_log_get_s_mask+0xe>
     faa:	bf00      	nop
     fac:	000079da 	.word	0x000079da

00000fb0 <log_core_init>:
{
     fb0:	b510      	push	{r4, lr}
	panic_mode = false;
     fb2:	4b0b      	ldr	r3, [pc, #44]	; (fe0 <log_core_init+0x30>)
     fb4:	2200      	movs	r2, #0
     fb6:	701a      	strb	r2, [r3, #0]
		timestamp_func = default_get_timestamp;
     fb8:	4b0a      	ldr	r3, [pc, #40]	; (fe4 <log_core_init+0x34>)
     fba:	4a0b      	ldr	r2, [pc, #44]	; (fe8 <log_core_init+0x38>)
     fbc:	601a      	str	r2, [r3, #0]
	log_output_timestamp_freq_set(freq);
     fbe:	f44f 4000 	mov.w	r0, #32768	; 0x8000
     fc2:	f000 fcc1 	bl	1948 <log_output_timestamp_freq_set>
		log_msg_pool_init();
     fc6:	f000 fa71 	bl	14ac <log_msg_pool_init>
		log_list_init(&list);
     fca:	4808      	ldr	r0, [pc, #32]	; (fec <log_core_init+0x3c>)
     fcc:	f004 ff52 	bl	5e74 <log_list_init>
}
     fd0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		k_mem_slab_init(&log_strdup_pool, log_strdup_pool_buf,
     fd4:	4906      	ldr	r1, [pc, #24]	; (ff0 <log_core_init+0x40>)
     fd6:	4807      	ldr	r0, [pc, #28]	; (ff4 <log_core_init+0x44>)
     fd8:	2304      	movs	r3, #4
     fda:	2228      	movs	r2, #40	; 0x28
     fdc:	f005 bb9f 	b.w	671e <k_mem_slab_init>
     fe0:	2000069b 	.word	0x2000069b
     fe4:	20000004 	.word	0x20000004
     fe8:	00005eb3 	.word	0x00005eb3
     fec:	2000037c 	.word	0x2000037c
     ff0:	20001f18 	.word	0x20001f18
     ff4:	20000384 	.word	0x20000384

00000ff8 <get_msg>:
{
     ff8:	b510      	push	{r4, lr}
     ffa:	f04f 0320 	mov.w	r3, #32
     ffe:	f3ef 8411 	mrs	r4, BASEPRI
    1002:	f383 8811 	msr	BASEPRI, r3
    1006:	f3bf 8f6f 	isb	sy
	msg.msg = log_list_head_get(&list);
    100a:	4804      	ldr	r0, [pc, #16]	; (101c <CONFIG_FPROTECT_BLOCK_SIZE+0x1c>)
    100c:	f004 ff42 	bl	5e94 <log_list_head_get>
	__asm__ volatile(
    1010:	f384 8811 	msr	BASEPRI, r4
    1014:	f3bf 8f6f 	isb	sy
}
    1018:	bd10      	pop	{r4, pc}
    101a:	bf00      	nop
    101c:	2000037c 	.word	0x2000037c

00001020 <z_log_dropped>:
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_add(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST);
    1020:	4b06      	ldr	r3, [pc, #24]	; (103c <z_log_dropped+0x1c>)
    1022:	f3bf 8f5b 	dmb	ish
    1026:	e853 2f00 	ldrex	r2, [r3]
    102a:	3201      	adds	r2, #1
    102c:	e843 2100 	strex	r1, r2, [r3]
    1030:	2900      	cmp	r1, #0
    1032:	d1f8      	bne.n	1026 <z_log_dropped+0x6>
    1034:	f3bf 8f5b 	dmb	ish
}
    1038:	4770      	bx	lr
    103a:	bf00      	nop
    103c:	20000374 	.word	0x20000374

00001040 <z_log_dropped_read_and_clear>:
}
    1040:	2000      	movs	r0, #0
{
	/* This builtin, as described by Intel, is not a traditional
	 * test-and-set operation, but rather an atomic exchange operation. It
	 * writes value into *ptr, and returns the previous contents of *ptr.
	 */
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    1042:	4b06      	ldr	r3, [pc, #24]	; (105c <z_log_dropped_read_and_clear+0x1c>)
    1044:	f3bf 8f5b 	dmb	ish
    1048:	4602      	mov	r2, r0
    104a:	e853 0f00 	ldrex	r0, [r3]
    104e:	e843 2100 	strex	r1, r2, [r3]
    1052:	2900      	cmp	r1, #0
    1054:	d1f9      	bne.n	104a <z_log_dropped_read_and_clear+0xa>
    1056:	f3bf 8f5b 	dmb	ish
    105a:	4770      	bx	lr
    105c:	20000374 	.word	0x20000374

00001060 <dropped_notify>:
{
    1060:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	uint32_t dropped = z_log_dropped_read_and_clear();
    1062:	f7ff ffed 	bl	1040 <z_log_dropped_read_and_clear>
 *
 * @return Number of backends.
 */
static inline int log_backend_count_get(void)
{
	return __log_backends_end - __log_backends_start;
    1066:	4c0a      	ldr	r4, [pc, #40]	; (1090 <dropped_notify+0x30>)
    1068:	4d0a      	ldr	r5, [pc, #40]	; (1094 <dropped_notify+0x34>)
    106a:	1b2d      	subs	r5, r5, r4
    106c:	4607      	mov	r7, r0
    106e:	112d      	asrs	r5, r5, #4
	for (int i = 0; i < log_backend_count_get(); i++) {
    1070:	2600      	movs	r6, #0
    1072:	42ae      	cmp	r6, r5
    1074:	db00      	blt.n	1078 <dropped_notify+0x18>
}
    1076:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 */
static inline bool log_backend_is_active(
				const struct log_backend *const backend)
{
	__ASSERT_NO_MSG(backend != NULL);
	return backend->cb->active;
    1078:	6863      	ldr	r3, [r4, #4]
		if (log_backend_is_active(backend)) {
    107a:	795b      	ldrb	r3, [r3, #5]
    107c:	b12b      	cbz	r3, 108a <dropped_notify+0x2a>
	if (backend->api->dropped != NULL) {
    107e:	6823      	ldr	r3, [r4, #0]
    1080:	691b      	ldr	r3, [r3, #16]
    1082:	b113      	cbz	r3, 108a <dropped_notify+0x2a>
		backend->api->dropped(backend, cnt);
    1084:	4639      	mov	r1, r7
    1086:	4620      	mov	r0, r4
    1088:	4798      	blx	r3
	for (int i = 0; i < log_backend_count_get(); i++) {
    108a:	3601      	adds	r6, #1
    108c:	3410      	adds	r4, #16
    108e:	e7f0      	b.n	1072 <dropped_notify+0x12>
    1090:	000070b8 	.word	0x000070b8
    1094:	000070d8 	.word	0x000070d8

00001098 <log_source_name_get>:
 * @return Source ID.
 */
static inline uint32_t log_const_source_id(
				const struct log_source_const_data *data)
{
	return ((uint8_t *)data - (uint8_t *)__log_const_start)/
    1098:	4a04      	ldr	r2, [pc, #16]	; (10ac <log_source_name_get+0x14>)
    109a:	4b05      	ldr	r3, [pc, #20]	; (10b0 <log_source_name_get+0x18>)
    109c:	1a9b      	subs	r3, r3, r2
	return src_id < log_sources_count() ? log_name_get(src_id) : NULL;
    109e:	ebb1 0fd3 	cmp.w	r1, r3, lsr #3
	return __log_const_start[source_id].name;
    10a2:	bf34      	ite	cc
    10a4:	f852 0031 	ldrcc.w	r0, [r2, r1, lsl #3]
    10a8:	2000      	movcs	r0, #0
}
    10aa:	4770      	bx	lr
    10ac:	00007078 	.word	0x00007078
    10b0:	000070b8 	.word	0x000070b8

000010b4 <log_backend_enable>:
	id += backend - log_backend_get(0);
    10b4:	4b09      	ldr	r3, [pc, #36]	; (10dc <log_backend_enable+0x28>)
	log_backend_id_set(backend, id);
    10b6:	6842      	ldr	r2, [r0, #4]
	id += backend - log_backend_get(0);
    10b8:	1ac3      	subs	r3, r0, r3
    10ba:	111b      	asrs	r3, r3, #4
    10bc:	3301      	adds	r3, #1
{
    10be:	b510      	push	{r4, lr}
	log_backend_id_set(backend, id);
    10c0:	7113      	strb	r3, [r2, #4]
	log_backend_activate(backend, ctx);
    10c2:	6843      	ldr	r3, [r0, #4]
	if (IS_ENABLED(CONFIG_LOG_PROCESS_THREAD) && !backend_attached) {
    10c4:	4c06      	ldr	r4, [pc, #24]	; (10e0 <log_backend_enable+0x2c>)
	backend->cb->ctx = ctx;
    10c6:	6019      	str	r1, [r3, #0]
	backend->cb->active = true;
    10c8:	2201      	movs	r2, #1
    10ca:	715a      	strb	r2, [r3, #5]
    10cc:	7822      	ldrb	r2, [r4, #0]
    10ce:	b912      	cbnz	r2, 10d6 <log_backend_enable+0x22>
    10d0:	4804      	ldr	r0, [pc, #16]	; (10e4 <log_backend_enable+0x30>)
    10d2:	f003 f867 	bl	41a4 <z_impl_k_sem_give>
	backend_attached = true;
    10d6:	2301      	movs	r3, #1
    10d8:	7023      	strb	r3, [r4, #0]
}
    10da:	bd10      	pop	{r4, pc}
    10dc:	000070b8 	.word	0x000070b8
    10e0:	2000069a 	.word	0x2000069a
    10e4:	200000fc 	.word	0x200000fc

000010e8 <log_init>:
{
    10e8:	b570      	push	{r4, r5, r6, lr}
	return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST);
    10ea:	4b12      	ldr	r3, [pc, #72]	; (1134 <log_init+0x4c>)
    10ec:	f3bf 8f5b 	dmb	ish
    10f0:	e853 5f00 	ldrex	r5, [r3]
    10f4:	1c6a      	adds	r2, r5, #1
    10f6:	e843 2100 	strex	r1, r2, [r3]
    10fa:	2900      	cmp	r1, #0
    10fc:	d1f8      	bne.n	10f0 <log_init+0x8>
    10fe:	f3bf 8f5b 	dmb	ish
	if (atomic_inc(&initialized) != 0) {
    1102:	b92d      	cbnz	r5, 1110 <log_init+0x28>
	return __log_backends_end - __log_backends_start;
    1104:	4c0c      	ldr	r4, [pc, #48]	; (1138 <log_init+0x50>)
    1106:	4e0d      	ldr	r6, [pc, #52]	; (113c <log_init+0x54>)
    1108:	1b36      	subs	r6, r6, r4
    110a:	1136      	asrs	r6, r6, #4
	for (i = 0; i < log_backend_count_get(); i++) {
    110c:	42b5      	cmp	r5, r6
    110e:	db00      	blt.n	1112 <log_init+0x2a>
}
    1110:	bd70      	pop	{r4, r5, r6, pc}
		if (backend->autostart) {
    1112:	7b23      	ldrb	r3, [r4, #12]
    1114:	b153      	cbz	r3, 112c <log_init+0x44>
			if (backend->api->init != NULL) {
    1116:	6823      	ldr	r3, [r4, #0]
    1118:	699b      	ldr	r3, [r3, #24]
    111a:	b10b      	cbz	r3, 1120 <log_init+0x38>
				backend->api->init(backend);
    111c:	4620      	mov	r0, r4
    111e:	4798      	blx	r3
			log_backend_enable(backend,
    1120:	6863      	ldr	r3, [r4, #4]
    1122:	2204      	movs	r2, #4
    1124:	6819      	ldr	r1, [r3, #0]
    1126:	4620      	mov	r0, r4
    1128:	f7ff ffc4 	bl	10b4 <log_backend_enable>
	for (i = 0; i < log_backend_count_get(); i++) {
    112c:	3501      	adds	r5, #1
    112e:	3410      	adds	r4, #16
    1130:	e7ec      	b.n	110c <log_init+0x24>
    1132:	bf00      	nop
    1134:	20000378 	.word	0x20000378
    1138:	000070b8 	.word	0x000070b8
    113c:	000070d8 	.word	0x000070d8

00001140 <z_log_strdup>:
	return (((const char *)addr >= (const char *)RO_START) &&
    1140:	4b17      	ldr	r3, [pc, #92]	; (11a0 <z_log_strdup+0x60>)
    1142:	4298      	cmp	r0, r3
{
    1144:	b573      	push	{r0, r1, r4, r5, r6, lr}
    1146:	4604      	mov	r4, r0
	return (((const char *)addr >= (const char *)RO_START) &&
    1148:	d302      	bcc.n	1150 <z_log_strdup+0x10>
	if (IS_ENABLED(CONFIG_LOG_IMMEDIATE) ||
    114a:	4b16      	ldr	r3, [pc, #88]	; (11a4 <z_log_strdup+0x64>)
    114c:	4298      	cmp	r0, r3
    114e:	d321      	bcc.n	1194 <z_log_strdup+0x54>
	err = k_mem_slab_alloc(&log_strdup_pool, (void **)&dup, K_NO_WAIT);
    1150:	4815      	ldr	r0, [pc, #84]	; (11a8 <z_log_strdup+0x68>)
    1152:	2200      	movs	r2, #0
    1154:	2300      	movs	r3, #0
    1156:	a901      	add	r1, sp, #4
    1158:	f002 fe60 	bl	3e1c <k_mem_slab_alloc>
	if (err != 0) {
    115c:	4605      	mov	r5, r0
    115e:	b9e0      	cbnz	r0, 119a <z_log_strdup+0x5a>
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    1160:	2201      	movs	r2, #1
    1162:	9b01      	ldr	r3, [sp, #4]
    1164:	f3bf 8f5b 	dmb	ish
    1168:	e853 1f00 	ldrex	r1, [r3]
    116c:	e843 2000 	strex	r0, r2, [r3]
    1170:	2800      	cmp	r0, #0
    1172:	d1f9      	bne.n	1168 <z_log_strdup+0x28>
    1174:	f3bf 8f5b 	dmb	ish
	strncpy(dup->buf, str, sizeof(dup->buf) - 2);
    1178:	9e01      	ldr	r6, [sp, #4]
    117a:	1d33      	adds	r3, r6, #4
#if __GNUC_PREREQ__(4,8) || defined(__clang__)
__ssp_bos_icheck3_restrict(stpncpy, char *, const char *)
#endif
__ssp_bos_icheck2_restrict(strcpy, char *, const char *)
__ssp_bos_icheck2_restrict(strcat, char *, const char *)
__ssp_bos_icheck3_restrict(strncpy, char *, const char *)
    117c:	221f      	movs	r2, #31
    117e:	4618      	mov	r0, r3
    1180:	4621      	mov	r1, r4
    1182:	f005 fcdb 	bl	6b3c <strncpy>
	dup->buf[sizeof(dup->buf) - 2] = '~';
    1186:	227e      	movs	r2, #126	; 0x7e
    1188:	4603      	mov	r3, r0
    118a:	f886 2023 	strb.w	r2, [r6, #35]	; 0x23
	dup->buf[sizeof(dup->buf) - 1] = '\0';
    118e:	f886 5024 	strb.w	r5, [r6, #36]	; 0x24
	return dup->buf;
    1192:	461c      	mov	r4, r3
}
    1194:	4620      	mov	r0, r4
    1196:	b002      	add	sp, #8
    1198:	bd70      	pop	{r4, r5, r6, pc}
		return (char *)log_strdup_fail_msg;
    119a:	4b04      	ldr	r3, [pc, #16]	; (11ac <z_log_strdup+0x6c>)
    119c:	e7f9      	b.n	1192 <z_log_strdup+0x52>
    119e:	bf00      	nop
    11a0:	00006df0 	.word	0x00006df0
    11a4:	00007b10 	.word	0x00007b10
    11a8:	20000384 	.word	0x20000384
    11ac:	00007324 	.word	0x00007324

000011b0 <log_is_strdup>:
	return PART_OF_ARRAY(log_strdup_pool_buf, (uint8_t *)buf);
    11b0:	b148      	cbz	r0, 11c6 <log_is_strdup+0x16>
    11b2:	4b05      	ldr	r3, [pc, #20]	; (11c8 <log_is_strdup+0x18>)
    11b4:	4298      	cmp	r0, r3
    11b6:	d305      	bcc.n	11c4 <log_is_strdup+0x14>
    11b8:	33a0      	adds	r3, #160	; 0xa0
    11ba:	4298      	cmp	r0, r3
    11bc:	bf2c      	ite	cs
    11be:	2000      	movcs	r0, #0
    11c0:	2001      	movcc	r0, #1
    11c2:	4770      	bx	lr
    11c4:	2000      	movs	r0, #0
}
    11c6:	4770      	bx	lr
    11c8:	20001f18 	.word	0x20001f18

000011cc <z_impl_log_process>:
{
    11cc:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
	if (!backend_attached && !bypass) {
    11d0:	4b46      	ldr	r3, [pc, #280]	; (12ec <z_impl_log_process+0x120>)
    11d2:	781b      	ldrb	r3, [r3, #0]
{
    11d4:	b085      	sub	sp, #20
    11d6:	4604      	mov	r4, r0
	if (!backend_attached && !bypass) {
    11d8:	b903      	cbnz	r3, 11dc <z_impl_log_process+0x10>
    11da:	b300      	cbz	r0, 121e <z_impl_log_process+0x52>
	msg = get_msg();
    11dc:	f7ff ff0c 	bl	ff8 <get_msg>
	if (msg.msg) {
    11e0:	4605      	mov	r5, r0
    11e2:	b178      	cbz	r0, 1204 <z_impl_log_process+0x38>
	return __atomic_fetch_sub(target, value, __ATOMIC_SEQ_CST);
    11e4:	f3bf 8f5b 	dmb	ish
    11e8:	4b41      	ldr	r3, [pc, #260]	; (12f0 <z_impl_log_process+0x124>)
    11ea:	e853 2f00 	ldrex	r2, [r3]
    11ee:	3a01      	subs	r2, #1
    11f0:	e843 2100 	strex	r1, r2, [r3]
    11f4:	2900      	cmp	r1, #0
    11f6:	d1f8      	bne.n	11ea <z_impl_log_process+0x1e>
    11f8:	f3bf 8f5b 	dmb	ish
	if (!bypass) {
    11fc:	b19c      	cbz	r4, 1226 <z_impl_log_process+0x5a>
			log_msg_put(msg.msg);
    11fe:	4628      	mov	r0, r5
    1200:	f004 ff36 	bl	6070 <log_msg_put>
	if (!bypass && z_log_dropped_pending()) {
    1204:	b92c      	cbnz	r4, 1212 <z_impl_log_process+0x46>
	return dropped_cnt > 0;
    1206:	4b3b      	ldr	r3, [pc, #236]	; (12f4 <z_impl_log_process+0x128>)
	if (!bypass && z_log_dropped_pending()) {
    1208:	681b      	ldr	r3, [r3, #0]
    120a:	2b00      	cmp	r3, #0
    120c:	dd01      	ble.n	1212 <z_impl_log_process+0x46>
		dropped_notify();
    120e:	f7ff ff27 	bl	1060 <dropped_notify>
	return (log_list_head_peek(&list) != NULL);
    1212:	4839      	ldr	r0, [pc, #228]	; (12f8 <z_impl_log_process+0x12c>)
    1214:	f004 fe3c 	bl	5e90 <log_list_head_peek>
    1218:	1e04      	subs	r4, r0, #0
    121a:	bf18      	it	ne
    121c:	2401      	movne	r4, #1
}
    121e:	4620      	mov	r0, r4
    1220:	b005      	add	sp, #20
    1222:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		    !panic_mode) {
    1226:	4b35      	ldr	r3, [pc, #212]	; (12fc <z_impl_log_process+0x130>)
		if (!IS_ENABLED(CONFIG_LOG2) &&
    1228:	781b      	ldrb	r3, [r3, #0]
    122a:	b9cb      	cbnz	r3, 1260 <z_impl_log_process+0x94>
 * @retval true  Standard message.
 * @retval false Hexdump message.
 */
static inline bool log_msg_is_std(struct log_msg *msg)
{
	return  (msg->hdr.params.generic.type == LOG_MSG_TYPE_STD);
    122c:	7a2b      	ldrb	r3, [r5, #8]
	if (!log_msg_is_std(msg)) {
    122e:	07db      	lsls	r3, r3, #31
    1230:	d416      	bmi.n	1260 <z_impl_log_process+0x94>
	msg_str = log_msg_str_get(msg);
    1232:	f004 ff30 	bl	6096 <log_msg_str_get>
    1236:	4680      	mov	r8, r0
	mask = z_log_get_s_mask(msg_str, log_msg_nargs_get(msg));
    1238:	4628      	mov	r0, r5
    123a:	f004 fef7 	bl	602c <log_msg_nargs_get>
    123e:	4601      	mov	r1, r0
    1240:	4640      	mov	r0, r8
    1242:	f7ff fe91 	bl	f68 <z_log_get_s_mask>
	return ((uint8_t *)data - (uint8_t *)__log_const_start)/
    1246:	4f2e      	ldr	r7, [pc, #184]	; (1300 <z_impl_log_process+0x134>)
    1248:	4b2e      	ldr	r3, [pc, #184]	; (1304 <z_impl_log_process+0x138>)
				LOG_ERR(ERR_MSG, idx, src_name, msg_str);
    124a:	f8df b0d4 	ldr.w	fp, [pc, #212]	; 1320 <z_impl_log_process+0x154>
    124e:	1bdb      	subs	r3, r3, r7
    1250:	08db      	lsrs	r3, r3, #3
    1252:	9303      	str	r3, [sp, #12]
    1254:	4b2c      	ldr	r3, [pc, #176]	; (1308 <z_impl_log_process+0x13c>)
    1256:	1bdb      	subs	r3, r3, r7
	mask = z_log_get_s_mask(msg_str, log_msg_nargs_get(msg));
    1258:	4606      	mov	r6, r0
    125a:	ea4f 0ad3 	mov.w	sl, r3, lsr #3
	while (mask) {
    125e:	b936      	cbnz	r6, 126e <z_impl_log_process+0xa2>
    1260:	4e2a      	ldr	r6, [pc, #168]	; (130c <z_impl_log_process+0x140>)
    1262:	4f2b      	ldr	r7, [pc, #172]	; (1310 <z_impl_log_process+0x144>)
    1264:	1bbf      	subs	r7, r7, r6
    1266:	113f      	asrs	r7, r7, #4
    1268:	f04f 0800 	mov.w	r8, #0
    126c:	e03a      	b.n	12e4 <z_impl_log_process+0x118>
		idx = 31 - __builtin_clz(mask);
    126e:	fab6 f186 	clz	r1, r6
    1272:	f1c1 091f 	rsb	r9, r1, #31
		str = (const char *)log_msg_arg_get(msg, idx);
    1276:	4649      	mov	r1, r9
    1278:	4628      	mov	r0, r5
    127a:	f004 feda 	bl	6032 <log_msg_arg_get>
	return (((const char *)addr >= (const char *)RO_START) &&
    127e:	4b25      	ldr	r3, [pc, #148]	; (1314 <z_impl_log_process+0x148>)
    1280:	4298      	cmp	r0, r3
		str = (const char *)log_msg_arg_get(msg, idx);
    1282:	4601      	mov	r1, r0
	return (((const char *)addr >= (const char *)RO_START) &&
    1284:	d302      	bcc.n	128c <z_impl_log_process+0xc0>
		if (!is_rodata(str) && !log_is_strdup(str) &&
    1286:	4b24      	ldr	r3, [pc, #144]	; (1318 <z_impl_log_process+0x14c>)
    1288:	4298      	cmp	r0, r3
    128a:	d31a      	bcc.n	12c2 <z_impl_log_process+0xf6>
    128c:	4608      	mov	r0, r1
    128e:	f7ff ff8f 	bl	11b0 <log_is_strdup>
    1292:	4602      	mov	r2, r0
    1294:	b9a8      	cbnz	r0, 12c2 <z_impl_log_process+0xf6>
    1296:	4b21      	ldr	r3, [pc, #132]	; (131c <z_impl_log_process+0x150>)
    1298:	4299      	cmp	r1, r3
    129a:	d012      	beq.n	12c2 <z_impl_log_process+0xf6>
	return msg->hdr.ids.source_id;
    129c:	896b      	ldrh	r3, [r5, #10]
	return src_id < log_sources_count() ? log_name_get(src_id) : NULL;
    129e:	9903      	ldr	r1, [sp, #12]
    12a0:	f3c3 1389 	ubfx	r3, r3, #6, #10
    12a4:	428b      	cmp	r3, r1
	return __log_const_start[source_id].name;
    12a6:	bf38      	it	cc
    12a8:	f857 2033 	ldrcc.w	r2, [r7, r3, lsl #3]
				LOG_ERR(ERR_MSG, idx, src_name, msg_str);
    12ac:	ea4f 138a 	mov.w	r3, sl, lsl #6
    12b0:	f043 0301 	orr.w	r3, r3, #1
    12b4:	f8ad 3000 	strh.w	r3, [sp]
    12b8:	4649      	mov	r1, r9
    12ba:	4643      	mov	r3, r8
    12bc:	4658      	mov	r0, fp
    12be:	f004 fe36 	bl	5f2e <log_3>
		mask &= ~BIT(idx);
    12c2:	2101      	movs	r1, #1
    12c4:	fa01 f109 	lsl.w	r1, r1, r9
    12c8:	ea26 0601 	bic.w	r6, r6, r1
    12cc:	e7c7      	b.n	125e <z_impl_log_process+0x92>
	return backend->cb->active;
    12ce:	6873      	ldr	r3, [r6, #4]
			if (log_backend_is_active(backend) &&
    12d0:	795b      	ldrb	r3, [r3, #5]
    12d2:	b123      	cbz	r3, 12de <z_impl_log_process+0x112>
	backend->api->put(backend, msg);
    12d4:	6833      	ldr	r3, [r6, #0]
    12d6:	4629      	mov	r1, r5
    12d8:	685b      	ldr	r3, [r3, #4]
    12da:	4630      	mov	r0, r6
    12dc:	4798      	blx	r3
		for (int i = 0; i < log_backend_count_get(); i++) {
    12de:	f108 0801 	add.w	r8, r8, #1
    12e2:	3610      	adds	r6, #16
    12e4:	45b8      	cmp	r8, r7
    12e6:	dbf2      	blt.n	12ce <z_impl_log_process+0x102>
    12e8:	e789      	b.n	11fe <z_impl_log_process+0x32>
    12ea:	bf00      	nop
    12ec:	2000069a 	.word	0x2000069a
    12f0:	20000370 	.word	0x20000370
    12f4:	20000374 	.word	0x20000374
    12f8:	2000037c 	.word	0x2000037c
    12fc:	2000069b 	.word	0x2000069b
    1300:	00007078 	.word	0x00007078
    1304:	000070b8 	.word	0x000070b8
    1308:	00007088 	.word	0x00007088
    130c:	000070b8 	.word	0x000070b8
    1310:	000070d8 	.word	0x000070d8
    1314:	00006df0 	.word	0x00006df0
    1318:	00007b10 	.word	0x00007b10
    131c:	00007324 	.word	0x00007324
    1320:	0000733e 	.word	0x0000733e

00001324 <msg_finalize>:
	msg->hdr.timestamp = timestamp_func();
    1324:	4b29      	ldr	r3, [pc, #164]	; (13cc <msg_finalize+0xa8>)
{
    1326:	b537      	push	{r0, r1, r2, r4, r5, lr}
	msg->hdr.timestamp = timestamp_func();
    1328:	681b      	ldr	r3, [r3, #0]
	msg->hdr.ids = src_level;
    132a:	8141      	strh	r1, [r0, #10]
{
    132c:	4604      	mov	r4, r0
	msg->hdr.timestamp = timestamp_func();
    132e:	4798      	blx	r3
    1330:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    1332:	f04f 0320 	mov.w	r3, #32
    1336:	f3ef 8511 	mrs	r5, BASEPRI
    133a:	f383 8811 	msr	BASEPRI, r3
    133e:	f3bf 8f6f 	isb	sy
	log_list_add_tail(&list, msg);
    1342:	4823      	ldr	r0, [pc, #140]	; (13d0 <msg_finalize+0xac>)
    1344:	4621      	mov	r1, r4
    1346:	f004 fd99 	bl	5e7c <log_list_add_tail>
	__asm__ volatile(
    134a:	f385 8811 	msr	BASEPRI, r5
    134e:	f3bf 8f6f 	isb	sy
	return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST);
    1352:	f3bf 8f5b 	dmb	ish
    1356:	4b1f      	ldr	r3, [pc, #124]	; (13d4 <msg_finalize+0xb0>)
    1358:	e853 2f00 	ldrex	r2, [r3]
    135c:	3201      	adds	r2, #1
    135e:	e843 2100 	strex	r1, r2, [r3]
    1362:	2900      	cmp	r1, #0
    1364:	d1f8      	bne.n	1358 <msg_finalize+0x34>
    1366:	f3bf 8f5b 	dmb	ish
	if (panic_mode) {
    136a:	4a1b      	ldr	r2, [pc, #108]	; (13d8 <msg_finalize+0xb4>)
    136c:	7812      	ldrb	r2, [r2, #0]
    136e:	b182      	cbz	r2, 1392 <msg_finalize+0x6e>
	__asm__ volatile(
    1370:	f04f 0320 	mov.w	r3, #32
    1374:	f3ef 8411 	mrs	r4, BASEPRI
    1378:	f383 8811 	msr	BASEPRI, r3
    137c:	f3bf 8f6f 	isb	sy
		/* coverity[OVERRUN] */
		return (bool) arch_syscall_invoke1(*(uintptr_t *)&bypass, K_SYSCALL_LOG_PROCESS);
	}
#endif
	compiler_barrier();
	return z_impl_log_process(bypass);
    1380:	2000      	movs	r0, #0
    1382:	f7ff ff23 	bl	11cc <z_impl_log_process>
	__asm__ volatile(
    1386:	f384 8811 	msr	BASEPRI, r4
    138a:	f3bf 8f6f 	isb	sy
}
    138e:	b003      	add	sp, #12
    1390:	bd30      	pop	{r4, r5, pc}
	} else if (proc_tid != NULL && buffered_cnt == 1) {
    1392:	4a12      	ldr	r2, [pc, #72]	; (13dc <msg_finalize+0xb8>)
    1394:	681b      	ldr	r3, [r3, #0]
    1396:	6812      	ldr	r2, [r2, #0]
    1398:	2a00      	cmp	r2, #0
    139a:	d0f8      	beq.n	138e <msg_finalize+0x6a>
    139c:	2b01      	cmp	r3, #1
    139e:	d10a      	bne.n	13b6 <msg_finalize+0x92>
	z_impl_k_timer_start(timer, duration, period);
    13a0:	2200      	movs	r2, #0
    13a2:	2300      	movs	r3, #0
    13a4:	e9cd 2300 	strd	r2, r3, [sp]
    13a8:	480d      	ldr	r0, [pc, #52]	; (13e0 <msg_finalize+0xbc>)
    13aa:	f44f 4200 	mov.w	r2, #32768	; 0x8000
    13ae:	2300      	movs	r3, #0
    13b0:	f003 fd8c 	bl	4ecc <z_impl_k_timer_start>
    13b4:	e7eb      	b.n	138e <msg_finalize+0x6a>
		if ((buffered_cnt == CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD) &&
    13b6:	2b0a      	cmp	r3, #10
    13b8:	d1e9      	bne.n	138e <msg_finalize+0x6a>
	z_impl_k_timer_stop(timer);
    13ba:	4809      	ldr	r0, [pc, #36]	; (13e0 <msg_finalize+0xbc>)
    13bc:	f005 fb7e 	bl	6abc <z_impl_k_timer_stop>
	z_impl_k_sem_give(sem);
    13c0:	4808      	ldr	r0, [pc, #32]	; (13e4 <msg_finalize+0xc0>)
}
    13c2:	b003      	add	sp, #12
    13c4:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
    13c8:	f002 beec 	b.w	41a4 <z_impl_k_sem_give>
    13cc:	20000004 	.word	0x20000004
    13d0:	2000037c 	.word	0x2000037c
    13d4:	20000370 	.word	0x20000370
    13d8:	2000069b 	.word	0x2000069b
    13dc:	200003a4 	.word	0x200003a4
    13e0:	20000110 	.word	0x20000110
    13e4:	200000fc 	.word	0x200000fc

000013e8 <log_process_thread_func>:
{
    13e8:	b510      	push	{r4, lr}
	log_init();
    13ea:	f7ff fe7d 	bl	10e8 <log_init>
	return z_impl_k_current_get();
    13ee:	f003 fb53 	bl	4a98 <z_impl_k_current_get>
	proc_tid = process_tid;
    13f2:	4b0c      	ldr	r3, [pc, #48]	; (1424 <log_process_thread_func+0x3c>)
    13f4:	6018      	str	r0, [r3, #0]
	if (CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD &&
    13f6:	b130      	cbz	r0, 1406 <log_process_thread_func+0x1e>
	    buffered_cnt >= CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD) {
    13f8:	4b0b      	ldr	r3, [pc, #44]	; (1428 <log_process_thread_func+0x40>)
	    process_tid &&
    13fa:	681b      	ldr	r3, [r3, #0]
    13fc:	2b09      	cmp	r3, #9
    13fe:	dd02      	ble.n	1406 <log_process_thread_func+0x1e>
	z_impl_k_sem_give(sem);
    1400:	480a      	ldr	r0, [pc, #40]	; (142c <log_process_thread_func+0x44>)
    1402:	f002 fecf 	bl	41a4 <z_impl_k_sem_give>
	return z_impl_k_sem_take(sem, timeout);
    1406:	4c09      	ldr	r4, [pc, #36]	; (142c <log_process_thread_func+0x44>)
    1408:	2000      	movs	r0, #0
    140a:	f7ff fedf 	bl	11cc <z_impl_log_process>
		if (log_process(false) == false) {
    140e:	2800      	cmp	r0, #0
    1410:	d1fa      	bne.n	1408 <log_process_thread_func+0x20>
    1412:	f04f 32ff 	mov.w	r2, #4294967295
    1416:	f04f 33ff 	mov.w	r3, #4294967295
    141a:	4620      	mov	r0, r4
    141c:	f002 fee2 	bl	41e4 <z_impl_k_sem_take>
    1420:	e7f2      	b.n	1408 <log_process_thread_func+0x20>
    1422:	bf00      	nop
    1424:	200003a4 	.word	0x200003a4
    1428:	20000370 	.word	0x20000370
    142c:	200000fc 	.word	0x200000fc

00001430 <z_impl_log_panic>:
{
    1430:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	if (panic_mode) {
    1432:	4f0e      	ldr	r7, [pc, #56]	; (146c <z_impl_log_panic+0x3c>)
    1434:	783d      	ldrb	r5, [r7, #0]
    1436:	b975      	cbnz	r5, 1456 <z_impl_log_panic+0x26>
	return __log_backends_end - __log_backends_start;
    1438:	4c0d      	ldr	r4, [pc, #52]	; (1470 <z_impl_log_panic+0x40>)
    143a:	4e0e      	ldr	r6, [pc, #56]	; (1474 <z_impl_log_panic+0x44>)
	log_init();
    143c:	f7ff fe54 	bl	10e8 <log_init>
    1440:	1b36      	subs	r6, r6, r4
    1442:	1136      	asrs	r6, r6, #4
	for (int i = 0; i < log_backend_count_get(); i++) {
    1444:	42b5      	cmp	r5, r6
    1446:	db07      	blt.n	1458 <z_impl_log_panic+0x28>
    1448:	2000      	movs	r0, #0
    144a:	f7ff febf 	bl	11cc <z_impl_log_process>
		while (log_process(false) == true) {
    144e:	2800      	cmp	r0, #0
    1450:	d1fa      	bne.n	1448 <z_impl_log_panic+0x18>
	panic_mode = true;
    1452:	2301      	movs	r3, #1
    1454:	703b      	strb	r3, [r7, #0]
}
    1456:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return backend->cb->active;
    1458:	6863      	ldr	r3, [r4, #4]
		if (log_backend_is_active(backend)) {
    145a:	795b      	ldrb	r3, [r3, #5]
    145c:	b11b      	cbz	r3, 1466 <z_impl_log_panic+0x36>
	backend->api->panic(backend);
    145e:	6823      	ldr	r3, [r4, #0]
    1460:	4620      	mov	r0, r4
    1462:	695b      	ldr	r3, [r3, #20]
    1464:	4798      	blx	r3
	for (int i = 0; i < log_backend_count_get(); i++) {
    1466:	3501      	adds	r5, #1
    1468:	3410      	adds	r4, #16
    146a:	e7eb      	b.n	1444 <z_impl_log_panic+0x14>
    146c:	2000069b 	.word	0x2000069b
    1470:	000070b8 	.word	0x000070b8
    1474:	000070d8 	.word	0x000070d8

00001478 <log_free>:
{
    1478:	b507      	push	{r0, r1, r2, lr}
	struct log_strdup_buf *dup = CONTAINER_OF(str, struct log_strdup_buf,
    147a:	3804      	subs	r0, #4
    147c:	9001      	str	r0, [sp, #4]
	return __atomic_fetch_sub(target, value, __ATOMIC_SEQ_CST);
    147e:	f3bf 8f5b 	dmb	ish
    1482:	e850 3f00 	ldrex	r3, [r0]
    1486:	1e5a      	subs	r2, r3, #1
    1488:	e840 2100 	strex	r1, r2, [r0]
    148c:	2900      	cmp	r1, #0
    148e:	d1f8      	bne.n	1482 <log_free+0xa>
    1490:	f3bf 8f5b 	dmb	ish
	if (atomic_dec(&dup->refcount) == 1) {
    1494:	2b01      	cmp	r3, #1
    1496:	d103      	bne.n	14a0 <log_free+0x28>
		k_mem_slab_free(&log_strdup_pool, (void **)&dup);
    1498:	4803      	ldr	r0, [pc, #12]	; (14a8 <log_free+0x30>)
    149a:	a901      	add	r1, sp, #4
    149c:	f005 f95b 	bl	6756 <k_mem_slab_free>
}
    14a0:	b003      	add	sp, #12
    14a2:	f85d fb04 	ldr.w	pc, [sp], #4
    14a6:	bf00      	nop
    14a8:	20000384 	.word	0x20000384

000014ac <log_msg_pool_init>:
static uint8_t __noinit __aligned(sizeof(void *))
		log_msg_pool_buf[CONFIG_LOG_BUFFER_SIZE];

void log_msg_pool_init(void)
{
	k_mem_slab_init(&log_msg_pool, log_msg_pool_buf, MSG_SIZE, NUM_OF_MSGS);
    14ac:	2320      	movs	r3, #32
    14ae:	4902      	ldr	r1, [pc, #8]	; (14b8 <log_msg_pool_init+0xc>)
    14b0:	4802      	ldr	r0, [pc, #8]	; (14bc <log_msg_pool_init+0x10>)
    14b2:	461a      	mov	r2, r3
    14b4:	f005 b933 	b.w	671e <k_mem_slab_init>
    14b8:	20001fb8 	.word	0x20001fb8
    14bc:	200003a8 	.word	0x200003a8

000014c0 <log_msg_no_space_handle>:

	k_mem_slab_free(&log_msg_pool, (void **)&msg);
}

union log_msg_chunk *log_msg_no_space_handle(void)
{
    14c0:	b537      	push	{r0, r1, r2, r4, r5, lr}
	union log_msg_chunk *msg = NULL;
    14c2:	2300      	movs	r3, #0

	if (IS_ENABLED(CONFIG_LOG_MODE_OVERFLOW)) {
		do {
			more = log_process(true);
			z_log_dropped();
			err = k_mem_slab_alloc(&log_msg_pool,
    14c4:	4d09      	ldr	r5, [pc, #36]	; (14ec <log_msg_no_space_handle+0x2c>)
	union log_msg_chunk *msg = NULL;
    14c6:	9301      	str	r3, [sp, #4]
    14c8:	2001      	movs	r0, #1
    14ca:	f7ff fe7f 	bl	11cc <z_impl_log_process>
    14ce:	4604      	mov	r4, r0
			z_log_dropped();
    14d0:	f7ff fda6 	bl	1020 <z_log_dropped>
			err = k_mem_slab_alloc(&log_msg_pool,
    14d4:	2200      	movs	r2, #0
    14d6:	2300      	movs	r3, #0
    14d8:	a901      	add	r1, sp, #4
    14da:	4628      	mov	r0, r5
    14dc:	f002 fc9e 	bl	3e1c <k_mem_slab_alloc>
					       (void **)&msg,
					       K_NO_WAIT);
		} while ((err != 0) && more);
    14e0:	b108      	cbz	r0, 14e6 <log_msg_no_space_handle+0x26>
    14e2:	2c00      	cmp	r4, #0
    14e4:	d1f0      	bne.n	14c8 <log_msg_no_space_handle+0x8>
	} else {
		z_log_dropped();
	}
	return msg;

}
    14e6:	9801      	ldr	r0, [sp, #4]
    14e8:	b003      	add	sp, #12
    14ea:	bd30      	pop	{r4, r5, pc}
    14ec:	200003a8 	.word	0x200003a8

000014f0 <log_msg_chunk_alloc>:
{
    14f0:	b507      	push	{r0, r1, r2, lr}
	union log_msg_chunk *msg = NULL;
    14f2:	2300      	movs	r3, #0
    14f4:	9301      	str	r3, [sp, #4]
	int err = k_mem_slab_alloc(&log_msg_pool, (void **)&msg,
    14f6:	4807      	ldr	r0, [pc, #28]	; (1514 <log_msg_chunk_alloc+0x24>)
    14f8:	2200      	movs	r2, #0
    14fa:	2300      	movs	r3, #0
    14fc:	a901      	add	r1, sp, #4
    14fe:	f002 fc8d 	bl	3e1c <k_mem_slab_alloc>
	if (err != 0) {
    1502:	b110      	cbz	r0, 150a <log_msg_chunk_alloc+0x1a>
		msg = log_msg_no_space_handle();
    1504:	f7ff ffdc 	bl	14c0 <log_msg_no_space_handle>
    1508:	9001      	str	r0, [sp, #4]
}
    150a:	9801      	ldr	r0, [sp, #4]
    150c:	b003      	add	sp, #12
    150e:	f85d fb04 	ldr.w	pc, [sp], #4
    1512:	bf00      	nop
    1514:	200003a8 	.word	0x200003a8

00001518 <msg_free>:
{
    1518:	b5f0      	push	{r4, r5, r6, r7, lr}
	return  (msg->hdr.params.generic.type == LOG_MSG_TYPE_STD);
    151a:	7a03      	ldrb	r3, [r0, #8]
	}
}

uint32_t log_msg_nargs_get(struct log_msg *msg)
{
	return msg->hdr.params.std.nargs;
    151c:	7a45      	ldrb	r5, [r0, #9]
{
    151e:	b085      	sub	sp, #20
	return msg->hdr.params.std.nargs;
    1520:	092d      	lsrs	r5, r5, #4
{
    1522:	9001      	str	r0, [sp, #4]
	if (log_msg_is_std(msg) && nargs) {
    1524:	07d8      	lsls	r0, r3, #31
    1526:	d41c      	bmi.n	1562 <msg_free+0x4a>
    1528:	b1dd      	cbz	r5, 1562 <msg_free+0x4a>
		uint32_t smask = 0U;
    152a:	2400      	movs	r4, #0
		for (i = 0U; i < nargs; i++) {
    152c:	4626      	mov	r6, r4
			void *buf = (void *)log_msg_arg_get(msg, i);
    152e:	9801      	ldr	r0, [sp, #4]
    1530:	4631      	mov	r1, r6
    1532:	f004 fd7e 	bl	6032 <log_msg_arg_get>
    1536:	4607      	mov	r7, r0
			if (log_is_strdup(buf)) {
    1538:	f7ff fe3a 	bl	11b0 <log_is_strdup>
    153c:	b170      	cbz	r0, 155c <msg_free+0x44>
				if (smask == 0U) {
    153e:	b934      	cbnz	r4, 154e <msg_free+0x36>
					smask = z_log_get_s_mask(
    1540:	9b01      	ldr	r3, [sp, #4]
    1542:	4629      	mov	r1, r5
    1544:	6918      	ldr	r0, [r3, #16]
    1546:	f7ff fd0f 	bl	f68 <z_log_get_s_mask>
					if (smask == 0U) {
    154a:	4604      	mov	r4, r0
    154c:	b148      	cbz	r0, 1562 <msg_free+0x4a>
				if (smask & BIT(i)) {
    154e:	fa24 f306 	lsr.w	r3, r4, r6
    1552:	07d9      	lsls	r1, r3, #31
    1554:	d502      	bpl.n	155c <msg_free+0x44>
					log_free(buf);
    1556:	4638      	mov	r0, r7
    1558:	f7ff ff8e 	bl	1478 <log_free>
		for (i = 0U; i < nargs; i++) {
    155c:	3601      	adds	r6, #1
    155e:	42ae      	cmp	r6, r5
    1560:	d3e5      	bcc.n	152e <msg_free+0x16>
	if (msg->hdr.params.generic.ext == 1) {
    1562:	9b01      	ldr	r3, [sp, #4]
    1564:	7a1a      	ldrb	r2, [r3, #8]
    1566:	0792      	lsls	r2, r2, #30
    1568:	d504      	bpl.n	1574 <msg_free+0x5c>
		cont_free(msg->payload.ext.next);
    156a:	695b      	ldr	r3, [r3, #20]
		k_mem_slab_free(&log_msg_pool, (void **)&cont);
    156c:	4c08      	ldr	r4, [pc, #32]	; (1590 <msg_free+0x78>)
    156e:	9303      	str	r3, [sp, #12]
	while (cont != NULL) {
    1570:	9b03      	ldr	r3, [sp, #12]
    1572:	b92b      	cbnz	r3, 1580 <msg_free+0x68>
	k_mem_slab_free(&log_msg_pool, (void **)&msg);
    1574:	4806      	ldr	r0, [pc, #24]	; (1590 <msg_free+0x78>)
    1576:	a901      	add	r1, sp, #4
    1578:	f005 f8ed 	bl	6756 <k_mem_slab_free>
}
    157c:	b005      	add	sp, #20
    157e:	bdf0      	pop	{r4, r5, r6, r7, pc}
		next = cont->next;
    1580:	681d      	ldr	r5, [r3, #0]
		k_mem_slab_free(&log_msg_pool, (void **)&cont);
    1582:	a903      	add	r1, sp, #12
    1584:	4620      	mov	r0, r4
    1586:	f005 f8e6 	bl	6756 <k_mem_slab_free>
		cont = next;
    158a:	9503      	str	r5, [sp, #12]
    158c:	e7f0      	b.n	1570 <msg_free+0x58>
    158e:	bf00      	nop
    1590:	200003a8 	.word	0x200003a8

00001594 <print_formatted>:
	return 0;
}

static int print_formatted(const struct log_output *output,
			   const char *fmt, ...)
{
    1594:	b40e      	push	{r1, r2, r3}
    1596:	b503      	push	{r0, r1, lr}
    1598:	ab03      	add	r3, sp, #12
    159a:	4601      	mov	r1, r0
    159c:	f853 2b04 	ldr.w	r2, [r3], #4
	va_list args;
	int length = 0;

	va_start(args, fmt);
	length = cbvprintf(out_func, (void *)output, fmt, args);
    15a0:	4804      	ldr	r0, [pc, #16]	; (15b4 <print_formatted+0x20>)
	va_start(args, fmt);
    15a2:	9301      	str	r3, [sp, #4]
	length = cbvprintf(out_func, (void *)output, fmt, args);
    15a4:	f7ff f914 	bl	7d0 <cbvprintf>
	va_end(args);

	return length;
}
    15a8:	b002      	add	sp, #8
    15aa:	f85d eb04 	ldr.w	lr, [sp], #4
    15ae:	b003      	add	sp, #12
    15b0:	4770      	bx	lr
    15b2:	bf00      	nop
    15b4:	00006397 	.word	0x00006397

000015b8 <prefix_print>:
}

static uint32_t prefix_print(const struct log_output *output,
			 uint32_t flags, bool func_on, uint32_t timestamp, uint8_t level,
			 uint8_t domain_id, int16_t source_id)
{
    15b8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    15bc:	b087      	sub	sp, #28
			"<%d>1 ",
			facility * 8 +
			level_to_rfc5424_severity(level));
	}

	if (stamp) {
    15be:	f011 0602 	ands.w	r6, r1, #2
{
    15c2:	9205      	str	r2, [sp, #20]
    15c4:	f89d 8040 	ldrb.w	r8, [sp, #64]	; 0x40
    15c8:	f9bd 9048 	ldrsh.w	r9, [sp, #72]	; 0x48
    15cc:	4607      	mov	r7, r0
    15ce:	461a      	mov	r2, r3
	bool colors_on = flags & LOG_OUTPUT_FLAG_COLORS;
    15d0:	f001 0a01 	and.w	sl, r1, #1
	bool level_on = flags & LOG_OUTPUT_FLAG_LEVEL;
    15d4:	f001 0508 	and.w	r5, r1, #8
	if (stamp) {
    15d8:	d006      	beq.n	15e8 <prefix_print+0x30>
	if (!format) {
    15da:	f011 0f44 	tst.w	r1, #68	; 0x44
    15de:	d138      	bne.n	1652 <prefix_print+0x9a>
		length = print_formatted(output, "[%08lu] ", timestamp);
    15e0:	4932      	ldr	r1, [pc, #200]	; (16ac <prefix_print+0xf4>)
    15e2:	f7ff ffd7 	bl	1594 <print_formatted>
		length += timestamp_print(output, flags, timestamp);
    15e6:	4606      	mov	r6, r0
	if (color) {
    15e8:	f1ba 0f00 	cmp.w	sl, #0
    15ec:	d00a      	beq.n	1604 <prefix_print+0x4c>
		const char *log_color = start && (colors[level] != NULL) ?
    15ee:	4b30      	ldr	r3, [pc, #192]	; (16b0 <prefix_print+0xf8>)
		print_formatted(output, "%s", log_color);
    15f0:	4930      	ldr	r1, [pc, #192]	; (16b4 <prefix_print+0xfc>)
		const char *log_color = start && (colors[level] != NULL) ?
    15f2:	f853 2028 	ldr.w	r2, [r3, r8, lsl #2]
		print_formatted(output, "%s", log_color);
    15f6:	4b30      	ldr	r3, [pc, #192]	; (16b8 <prefix_print+0x100>)
    15f8:	4638      	mov	r0, r7
    15fa:	2a00      	cmp	r2, #0
    15fc:	bf08      	it	eq
    15fe:	461a      	moveq	r2, r3
    1600:	f7ff ffc8 	bl	1594 <print_formatted>
	if (level_on) {
    1604:	b13d      	cbz	r5, 1616 <prefix_print+0x5e>
		total += print_formatted(output, "<%s> ", severity[level]);
    1606:	4b2d      	ldr	r3, [pc, #180]	; (16bc <prefix_print+0x104>)
    1608:	492d      	ldr	r1, [pc, #180]	; (16c0 <prefix_print+0x108>)
    160a:	f853 2028 	ldr.w	r2, [r3, r8, lsl #2]
    160e:	4638      	mov	r0, r7
    1610:	f7ff ffc0 	bl	1594 <print_formatted>
    1614:	4605      	mov	r5, r0
	if (source_id >= 0) {
    1616:	f1b9 0f00 	cmp.w	r9, #0
    161a:	db16      	blt.n	164a <prefix_print+0x92>
		total += print_formatted(output,
    161c:	9b05      	ldr	r3, [sp, #20]
    161e:	2b00      	cmp	r3, #0
    1620:	d041      	beq.n	16a6 <prefix_print+0xee>
				((1 << level) & LOG_FUNCTION_PREFIX_MASK)) ?
    1622:	2301      	movs	r3, #1
    1624:	fa03 f808 	lsl.w	r8, r3, r8
		total += print_formatted(output,
    1628:	4b26      	ldr	r3, [pc, #152]	; (16c4 <prefix_print+0x10c>)
    162a:	4c27      	ldr	r4, [pc, #156]	; (16c8 <prefix_print+0x110>)
    162c:	f018 0f10 	tst.w	r8, #16
    1630:	bf18      	it	ne
    1632:	461c      	movne	r4, r3
    1634:	4649      	mov	r1, r9
    1636:	f89d 0044 	ldrb.w	r0, [sp, #68]	; 0x44
    163a:	f7ff fd2d 	bl	1098 <log_source_name_get>
    163e:	4621      	mov	r1, r4
    1640:	4602      	mov	r2, r0
    1642:	4638      	mov	r0, r7
    1644:	f7ff ffa6 	bl	1594 <print_formatted>
    1648:	4405      	add	r5, r0
	length += ids_print(output, level_on, func_on,
			domain_id, source_id, level);


	return length;
}
    164a:	19a8      	adds	r0, r5, r6
    164c:	b007      	add	sp, #28
    164e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	} else if (freq != 0U) {
    1652:	4b1e      	ldr	r3, [pc, #120]	; (16cc <prefix_print+0x114>)
    1654:	6819      	ldr	r1, [r3, #0]
    1656:	b321      	cbz	r1, 16a2 <prefix_print+0xea>
		timestamp /= timestamp_div;
    1658:	4b1d      	ldr	r3, [pc, #116]	; (16d0 <prefix_print+0x118>)
    165a:	f44f 6c61 	mov.w	ip, #3600	; 0xe10
    165e:	681b      	ldr	r3, [r3, #0]
    1660:	fbb2 f3f3 	udiv	r3, r2, r3
		ms = (remainder * 1000U) / freq;
    1664:	f44f 767a 	mov.w	r6, #1000	; 0x3e8
		total_seconds = timestamp / freq;
    1668:	fbb3 f4f1 	udiv	r4, r3, r1
		seconds -= hours * 3600U;
    166c:	fbb4 f2fc 	udiv	r2, r4, ip
    1670:	fb0c 4c12 	mls	ip, ip, r2, r4
		remainder = timestamp % freq;
    1674:	fb01 3414 	mls	r4, r1, r4, r3
		ms = (remainder * 1000U) / freq;
    1678:	4374      	muls	r4, r6
		mins = seconds / 60U;
    167a:	f04f 0e3c 	mov.w	lr, #60	; 0x3c
		us = (1000 * (remainder * 1000U - (ms * freq))) / freq;
    167e:	fbb4 fbf1 	udiv	fp, r4, r1
    1682:	fb01 441b 	mls	r4, r1, fp, r4
    1686:	4374      	muls	r4, r6
		mins = seconds / 60U;
    1688:	fbbc f3fe 	udiv	r3, ip, lr
		us = (1000 * (remainder * 1000U - (ms * freq))) / freq;
    168c:	fbb4 f1f1 	udiv	r1, r4, r1
			length = print_formatted(output,
    1690:	e9cd b101 	strd	fp, r1, [sp, #4]
    1694:	fb0e c113 	mls	r1, lr, r3, ip
    1698:	9100      	str	r1, [sp, #0]
    169a:	490e      	ldr	r1, [pc, #56]	; (16d4 <prefix_print+0x11c>)
    169c:	f7ff ff7a 	bl	1594 <print_formatted>
    16a0:	e7a1      	b.n	15e6 <prefix_print+0x2e>
		length = 0;
    16a2:	4608      	mov	r0, r1
    16a4:	e79f      	b.n	15e6 <prefix_print+0x2e>
		total += print_formatted(output,
    16a6:	4c08      	ldr	r4, [pc, #32]	; (16c8 <prefix_print+0x110>)
    16a8:	e7c4      	b.n	1634 <prefix_print+0x7c>
    16aa:	bf00      	nop
    16ac:	0000738f 	.word	0x0000738f
    16b0:	00007118 	.word	0x00007118
    16b4:	000073b4 	.word	0x000073b4
    16b8:	00007381 	.word	0x00007381
    16bc:	0000712c 	.word	0x0000712c
    16c0:	000073b7 	.word	0x000073b7
    16c4:	0000738b 	.word	0x0000738b
    16c8:	00007386 	.word	0x00007386
    16cc:	200003c8 	.word	0x200003c8
    16d0:	200003cc 	.word	0x200003cc
    16d4:	00007398 	.word	0x00007398

000016d8 <postfix_print>:

static void postfix_print(const struct log_output *output,
			  uint32_t flags, uint8_t level)
{
    16d8:	b538      	push	{r3, r4, r5, lr}
    16da:	460c      	mov	r4, r1
	if (color) {
    16dc:	07e1      	lsls	r1, r4, #31
{
    16de:	4605      	mov	r5, r0
	if (color) {
    16e0:	d503      	bpl.n	16ea <postfix_print+0x12>
		print_formatted(output, "%s", log_color);
    16e2:	4a08      	ldr	r2, [pc, #32]	; (1704 <postfix_print+0x2c>)
    16e4:	4908      	ldr	r1, [pc, #32]	; (1708 <postfix_print+0x30>)
    16e6:	f7ff ff55 	bl	1594 <print_formatted>
	if ((flags & LOG_OUTPUT_FLAG_CRLF_NONE) != 0U) {
    16ea:	06e2      	lsls	r2, r4, #27
    16ec:	d408      	bmi.n	1700 <postfix_print+0x28>
	if ((flags & LOG_OUTPUT_FLAG_CRLF_LFONLY) != 0U) {
    16ee:	06a3      	lsls	r3, r4, #26
		print_formatted(ctx, "\r\n");
    16f0:	4628      	mov	r0, r5
		print_formatted(ctx, "\n");
    16f2:	bf4c      	ite	mi
    16f4:	4905      	ldrmi	r1, [pc, #20]	; (170c <postfix_print+0x34>)
		print_formatted(ctx, "\r\n");
    16f6:	4906      	ldrpl	r1, [pc, #24]	; (1710 <postfix_print+0x38>)
	color_postfix(output, (flags & LOG_OUTPUT_FLAG_COLORS),
			      level);
	newline_print(output, flags);
}
    16f8:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
		print_formatted(ctx, "\r\n");
    16fc:	f7ff bf4a 	b.w	1594 <print_formatted>
}
    1700:	bd38      	pop	{r3, r4, r5, pc}
    1702:	bf00      	nop
    1704:	00007381 	.word	0x00007381
    1708:	000073b4 	.word	0x000073b4
    170c:	000073be 	.word	0x000073be
    1710:	000073bd 	.word	0x000073bd

00001714 <hexdump_line_print>:
{
    1714:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    1718:	461d      	mov	r5, r3
    171a:	9b08      	ldr	r3, [sp, #32]
    171c:	4617      	mov	r7, r2
	if ((flags & LOG_OUTPUT_FLAG_CRLF_NONE) != 0U) {
    171e:	06da      	lsls	r2, r3, #27
{
    1720:	4604      	mov	r4, r0
    1722:	460e      	mov	r6, r1
	if ((flags & LOG_OUTPUT_FLAG_CRLF_NONE) != 0U) {
    1724:	d405      	bmi.n	1732 <hexdump_line_print+0x1e>
	if ((flags & LOG_OUTPUT_FLAG_CRLF_LFONLY) != 0U) {
    1726:	0699      	lsls	r1, r3, #26
		print_formatted(ctx, "\n");
    1728:	bf4c      	ite	mi
    172a:	492b      	ldrmi	r1, [pc, #172]	; (17d8 <hexdump_line_print+0xc4>)
		print_formatted(ctx, "\r\n");
    172c:	492b      	ldrpl	r1, [pc, #172]	; (17dc <hexdump_line_print+0xc8>)
    172e:	f7ff ff31 	bl	1594 <print_formatted>
		print_formatted(output, " ");
    1732:	f8df 90b0 	ldr.w	r9, [pc, #176]	; 17e4 <hexdump_line_print+0xd0>
{
    1736:	f04f 0800 	mov.w	r8, #0
	for (int i = 0; i < prefix_offset; i++) {
    173a:	45a8      	cmp	r8, r5
    173c:	db2d      	blt.n	179a <hexdump_line_print+0x86>
			print_formatted(output, "   ");
    173e:	f8df 80a8 	ldr.w	r8, [pc, #168]	; 17e8 <hexdump_line_print+0xd4>
			print_formatted(output, "%02x ", data[i]);
    1742:	f8df 90a8 	ldr.w	r9, [pc, #168]	; 17ec <hexdump_line_print+0xd8>
			print_formatted(output, " ");
    1746:	f8df a09c 	ldr.w	sl, [pc, #156]	; 17e4 <hexdump_line_print+0xd0>
	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    174a:	2500      	movs	r5, #0
		if (i < length) {
    174c:	42bd      	cmp	r5, r7
    174e:	d232      	bcs.n	17b6 <hexdump_line_print+0xa2>
			print_formatted(output, "%02x ", data[i]);
    1750:	5d72      	ldrb	r2, [r6, r5]
    1752:	4649      	mov	r1, r9
    1754:	4620      	mov	r0, r4
    1756:	f7ff ff1d 	bl	1594 <print_formatted>
	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    175a:	3501      	adds	r5, #1
    175c:	2d10      	cmp	r5, #16
    175e:	d123      	bne.n	17a8 <hexdump_line_print+0x94>
	print_formatted(output, "|");
    1760:	491f      	ldr	r1, [pc, #124]	; (17e0 <hexdump_line_print+0xcc>)
			print_formatted(output, " ");
    1762:	f8df 8080 	ldr.w	r8, [pc, #128]	; 17e4 <hexdump_line_print+0xd0>
			      isprint((int)c) ? c : '.');
    1766:	f8df 9088 	ldr.w	r9, [pc, #136]	; 17f0 <hexdump_line_print+0xdc>
			print_formatted(output, "%c",
    176a:	f8df a088 	ldr.w	sl, [pc, #136]	; 17f4 <hexdump_line_print+0xe0>
	print_formatted(output, "|");
    176e:	4620      	mov	r0, r4
    1770:	f7ff ff10 	bl	1594 <print_formatted>
	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    1774:	2500      	movs	r5, #0
		if (i < length) {
    1776:	42af      	cmp	r7, r5
    1778:	d929      	bls.n	17ce <hexdump_line_print+0xba>
			char c = (char)data[i];
    177a:	5d72      	ldrb	r2, [r6, r5]
			print_formatted(output, "%c",
    177c:	f812 3009 	ldrb.w	r3, [r2, r9]
    1780:	f013 0f97 	tst.w	r3, #151	; 0x97
    1784:	bf08      	it	eq
    1786:	222e      	moveq	r2, #46	; 0x2e
    1788:	4651      	mov	r1, sl
    178a:	4620      	mov	r0, r4
    178c:	f7ff ff02 	bl	1594 <print_formatted>
	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    1790:	3501      	adds	r5, #1
    1792:	2d10      	cmp	r5, #16
    1794:	d114      	bne.n	17c0 <hexdump_line_print+0xac>
}
    1796:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		print_formatted(output, " ");
    179a:	4649      	mov	r1, r9
    179c:	4620      	mov	r0, r4
    179e:	f7ff fef9 	bl	1594 <print_formatted>
	for (int i = 0; i < prefix_offset; i++) {
    17a2:	f108 0801 	add.w	r8, r8, #1
    17a6:	e7c8      	b.n	173a <hexdump_line_print+0x26>
		if (i > 0 && !(i % 8)) {
    17a8:	076a      	lsls	r2, r5, #29
    17aa:	d1cf      	bne.n	174c <hexdump_line_print+0x38>
			print_formatted(output, " ");
    17ac:	4651      	mov	r1, sl
    17ae:	4620      	mov	r0, r4
    17b0:	f7ff fef0 	bl	1594 <print_formatted>
    17b4:	e7ca      	b.n	174c <hexdump_line_print+0x38>
			print_formatted(output, "   ");
    17b6:	4641      	mov	r1, r8
    17b8:	4620      	mov	r0, r4
    17ba:	f7ff feeb 	bl	1594 <print_formatted>
    17be:	e7cc      	b.n	175a <hexdump_line_print+0x46>
		if (i > 0 && !(i % 8)) {
    17c0:	076b      	lsls	r3, r5, #29
    17c2:	d1d8      	bne.n	1776 <hexdump_line_print+0x62>
			print_formatted(output, " ");
    17c4:	4641      	mov	r1, r8
    17c6:	4620      	mov	r0, r4
    17c8:	f7ff fee4 	bl	1594 <print_formatted>
    17cc:	e7d3      	b.n	1776 <hexdump_line_print+0x62>
			print_formatted(output, " ");
    17ce:	4641      	mov	r1, r8
    17d0:	4620      	mov	r0, r4
    17d2:	f7ff fedf 	bl	1594 <print_formatted>
    17d6:	e7db      	b.n	1790 <hexdump_line_print+0x7c>
    17d8:	000073be 	.word	0x000073be
    17dc:	000073bd 	.word	0x000073bd
    17e0:	000073ca 	.word	0x000073ca
    17e4:	000073c8 	.word	0x000073c8
    17e8:	000073c6 	.word	0x000073c6
    17ec:	000073c0 	.word	0x000073c0
    17f0:	000079da 	.word	0x000079da
    17f4:	000073cc 	.word	0x000073cc

000017f8 <log_output_msg_process>:

void log_output_msg_process(const struct log_output *output,
			    struct log_msg *msg,
			    uint32_t flags)
{
    17f8:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	return msg->hdr.ids.level;
    17fc:	7a8b      	ldrb	r3, [r1, #10]
		log_output_msg_syst_process(output, msg, flags);
		return;
	}

	prefix_offset = raw_string ?
			0 : prefix_print(output, flags, std_msg, timestamp,
    17fe:	f013 0807 	ands.w	r8, r3, #7
{
    1802:	4617      	mov	r7, r2
    1804:	b08a      	sub	sp, #40	; 0x28
	return  (msg->hdr.params.generic.type == LOG_MSG_TYPE_STD);
    1806:	7a0a      	ldrb	r2, [r1, #8]
    1808:	4605      	mov	r5, r0
    180a:	460e      	mov	r6, r1
			0 : prefix_print(output, flags, std_msg, timestamp,
    180c:	d021      	beq.n	1852 <log_output_msg_process+0x5a>
	return msg->hdr.ids.source_id;
    180e:	8949      	ldrh	r1, [r1, #10]
    1810:	f3c3 03c2 	ubfx	r3, r3, #3, #3
    1814:	f3c1 1189 	ubfx	r1, r1, #6, #10
	return  (msg->hdr.params.generic.type == LOG_MSG_TYPE_STD);
    1818:	43d2      	mvns	r2, r2
    181a:	e9cd 8300 	strd	r8, r3, [sp]
    181e:	9102      	str	r1, [sp, #8]
    1820:	68f3      	ldr	r3, [r6, #12]
    1822:	f002 0201 	and.w	r2, r2, #1
    1826:	4639      	mov	r1, r7
    1828:	f7ff fec6 	bl	15b8 <prefix_print>
    182c:	4681      	mov	r9, r0
    182e:	7a34      	ldrb	r4, [r6, #8]
    1830:	43e4      	mvns	r4, r4
					 level, domain_id, source_id);

	if (log_msg_is_std(msg)) {
    1832:	f014 0401 	ands.w	r4, r4, #1
    1836:	d00e      	beq.n	1856 <log_output_msg_process+0x5e>
		std_print(msg, output);
    1838:	4629      	mov	r1, r5
    183a:	4630      	mov	r0, r6
    183c:	f004 fc41 	bl	60c2 <std_print>
		raw_string_print(msg, output);
	} else {
		hexdump_print(msg, output, prefix_offset, flags);
	}

	if (!raw_string) {
    1840:	f1b8 0f00 	cmp.w	r8, #0
    1844:	d02b      	beq.n	189e <log_output_msg_process+0xa6>
		postfix_print(output, flags, level);
    1846:	4642      	mov	r2, r8
    1848:	4639      	mov	r1, r7
    184a:	4628      	mov	r0, r5
    184c:	f7ff ff44 	bl	16d8 <postfix_print>
    1850:	e025      	b.n	189e <log_output_msg_process+0xa6>
			0 : prefix_print(output, flags, std_msg, timestamp,
    1852:	46c1      	mov	r9, r8
    1854:	e7eb      	b.n	182e <log_output_msg_process+0x36>
	} else if (raw_string) {
    1856:	f1b8 0f00 	cmp.w	r8, #0
    185a:	d126      	bne.n	18aa <log_output_msg_process+0xb2>
	size_t offset = 0;
    185c:	4627      	mov	r7, r4
		length = output->size;
    185e:	68eb      	ldr	r3, [r5, #12]
    1860:	9306      	str	r3, [sp, #24]
		log_msg_hexdump_data_get(msg, output->buf, &length, offset);
    1862:	aa06      	add	r2, sp, #24
    1864:	463b      	mov	r3, r7
    1866:	68a9      	ldr	r1, [r5, #8]
    1868:	4630      	mov	r0, r6
    186a:	f004 fc16 	bl	609a <log_msg_hexdump_data_get>
		output->control_block->offset = length;
    186e:	9a06      	ldr	r2, [sp, #24]
    1870:	686b      	ldr	r3, [r5, #4]
    1872:	601a      	str	r2, [r3, #0]
		if (length != 0) {
    1874:	b13a      	cbz	r2, 1886 <log_output_msg_process+0x8e>
			eol = (output->buf[length - 1] == '\n');
    1876:	68ab      	ldr	r3, [r5, #8]
    1878:	4413      	add	r3, r2
    187a:	f813 4c01 	ldrb.w	r4, [r3, #-1]
    187e:	f1a4 030a 	sub.w	r3, r4, #10
    1882:	425c      	negs	r4, r3
    1884:	415c      	adcs	r4, r3
		log_output_flush(output);
    1886:	4628      	mov	r0, r5
    1888:	f004 fd78 	bl	637c <log_output_flush>
		offset += length;
    188c:	9b06      	ldr	r3, [sp, #24]
    188e:	441f      	add	r7, r3
	} while (length > 0);
    1890:	2b00      	cmp	r3, #0
    1892:	d1e4      	bne.n	185e <log_output_msg_process+0x66>
	if (eol) {
    1894:	b11c      	cbz	r4, 189e <log_output_msg_process+0xa6>
		print_formatted(output, "\r");
    1896:	4914      	ldr	r1, [pc, #80]	; (18e8 <log_output_msg_process+0xf0>)
    1898:	4628      	mov	r0, r5
    189a:	f7ff fe7b 	bl	1594 <print_formatted>
	}

	log_output_flush(output);
    189e:	4628      	mov	r0, r5
    18a0:	f004 fd6c 	bl	637c <log_output_flush>
}
    18a4:	b00a      	add	sp, #40	; 0x28
    18a6:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
	print_formatted(output, "%s", log_msg_str_get(msg));
    18aa:	4630      	mov	r0, r6
    18ac:	f004 fbf3 	bl	6096 <log_msg_str_get>
    18b0:	490e      	ldr	r1, [pc, #56]	; (18ec <log_output_msg_process+0xf4>)
    18b2:	4602      	mov	r2, r0
    18b4:	4628      	mov	r0, r5
    18b6:	f7ff fe6d 	bl	1594 <print_formatted>
		length = sizeof(buf);
    18ba:	f04f 0a10 	mov.w	sl, #16
		log_msg_hexdump_data_get(msg, buf, &length, offset);
    18be:	aa05      	add	r2, sp, #20
    18c0:	4623      	mov	r3, r4
    18c2:	a906      	add	r1, sp, #24
    18c4:	4630      	mov	r0, r6
		length = sizeof(buf);
    18c6:	f8cd a014 	str.w	sl, [sp, #20]
		log_msg_hexdump_data_get(msg, buf, &length, offset);
    18ca:	f004 fbe6 	bl	609a <log_msg_hexdump_data_get>
		if (length) {
    18ce:	9a05      	ldr	r2, [sp, #20]
    18d0:	2a00      	cmp	r2, #0
    18d2:	d0b8      	beq.n	1846 <log_output_msg_process+0x4e>
			hexdump_line_print(output, buf, length,
    18d4:	464b      	mov	r3, r9
    18d6:	9700      	str	r7, [sp, #0]
    18d8:	a906      	add	r1, sp, #24
    18da:	4628      	mov	r0, r5
    18dc:	f7ff ff1a 	bl	1714 <hexdump_line_print>
			offset += length;
    18e0:	9b05      	ldr	r3, [sp, #20]
    18e2:	441c      	add	r4, r3
		length = sizeof(buf);
    18e4:	e7eb      	b.n	18be <log_output_msg_process+0xc6>
    18e6:	bf00      	nop
    18e8:	000073cf 	.word	0x000073cf
    18ec:	000073b4 	.word	0x000073b4

000018f0 <log_output_dropped_process>:
	postfix_print(output, flags, level);
	log_output_flush(output);
}

void log_output_dropped_process(const struct log_output *output, uint32_t cnt)
{
    18f0:	b573      	push	{r0, r1, r4, r5, r6, lr}
	static const char postfix[] =
			" messages dropped ---\r\n" DROPPED_COLOR_POSTFIX;
	log_output_func_t outf = output->func;

	cnt = MIN(cnt, 9999);
	len = snprintk(buf, sizeof(buf), "%d", cnt);
    18f2:	f242 730f 	movw	r3, #9999	; 0x270f
    18f6:	428b      	cmp	r3, r1
    18f8:	bf28      	it	cs
    18fa:	460b      	movcs	r3, r1
	log_output_func_t outf = output->func;
    18fc:	6805      	ldr	r5, [r0, #0]
	len = snprintk(buf, sizeof(buf), "%d", cnt);
    18fe:	4a0f      	ldr	r2, [pc, #60]	; (193c <log_output_dropped_process+0x4c>)
{
    1900:	4604      	mov	r4, r0
	len = snprintk(buf, sizeof(buf), "%d", cnt);
    1902:	2105      	movs	r1, #5
    1904:	4668      	mov	r0, sp
    1906:	f004 f9b7 	bl	5c78 <snprintk>

	buffer_write(outf, (uint8_t *)prefix, sizeof(prefix) - 1,
    190a:	6863      	ldr	r3, [r4, #4]
    190c:	490c      	ldr	r1, [pc, #48]	; (1940 <log_output_dropped_process+0x50>)
    190e:	685b      	ldr	r3, [r3, #4]
	len = snprintk(buf, sizeof(buf), "%d", cnt);
    1910:	4606      	mov	r6, r0
	buffer_write(outf, (uint8_t *)prefix, sizeof(prefix) - 1,
    1912:	220b      	movs	r2, #11
    1914:	4628      	mov	r0, r5
    1916:	f004 fbc7 	bl	60a8 <buffer_write>
		     output->control_block->ctx);
	buffer_write(outf, buf, len, output->control_block->ctx);
    191a:	6863      	ldr	r3, [r4, #4]
    191c:	4632      	mov	r2, r6
    191e:	4669      	mov	r1, sp
    1920:	4628      	mov	r0, r5
    1922:	685b      	ldr	r3, [r3, #4]
    1924:	f004 fbc0 	bl	60a8 <buffer_write>
	buffer_write(outf, (uint8_t *)postfix, sizeof(postfix) - 1,
    1928:	6863      	ldr	r3, [r4, #4]
    192a:	4906      	ldr	r1, [pc, #24]	; (1944 <log_output_dropped_process+0x54>)
    192c:	685b      	ldr	r3, [r3, #4]
    192e:	221b      	movs	r2, #27
    1930:	4628      	mov	r0, r5
    1932:	f004 fbb9 	bl	60a8 <buffer_write>
		     output->control_block->ctx);
}
    1936:	b002      	add	sp, #8
    1938:	bd70      	pop	{r4, r5, r6, pc}
    193a:	bf00      	nop
    193c:	0000790e 	.word	0x0000790e
    1940:	0000740d 	.word	0x0000740d
    1944:	000073f1 	.word	0x000073f1

00001948 <log_output_timestamp_freq_set>:

void log_output_timestamp_freq_set(uint32_t frequency)
{
	timestamp_div = 1U;
    1948:	4a08      	ldr	r2, [pc, #32]	; (196c <log_output_timestamp_freq_set+0x24>)
{
    194a:	b510      	push	{r4, lr}
	timestamp_div = 1U;
    194c:	2301      	movs	r3, #1
	/* There is no point to have frequency higher than 1MHz (ns are not
	 * printed) and too high frequency leads to overflows in calculations.
	 */
	while (frequency > 1000000) {
    194e:	4c08      	ldr	r4, [pc, #32]	; (1970 <log_output_timestamp_freq_set+0x28>)
	timestamp_div = 1U;
    1950:	6013      	str	r3, [r2, #0]
	while (frequency > 1000000) {
    1952:	2100      	movs	r1, #0
    1954:	42a0      	cmp	r0, r4
    1956:	d804      	bhi.n	1962 <log_output_timestamp_freq_set+0x1a>
    1958:	b101      	cbz	r1, 195c <log_output_timestamp_freq_set+0x14>
    195a:	6013      	str	r3, [r2, #0]
		frequency /= 2U;
		timestamp_div *= 2U;
	}

	freq = frequency;
    195c:	4b05      	ldr	r3, [pc, #20]	; (1974 <log_output_timestamp_freq_set+0x2c>)
    195e:	6018      	str	r0, [r3, #0]
}
    1960:	bd10      	pop	{r4, pc}
		frequency /= 2U;
    1962:	0840      	lsrs	r0, r0, #1
		timestamp_div *= 2U;
    1964:	005b      	lsls	r3, r3, #1
    1966:	2101      	movs	r1, #1
    1968:	e7f4      	b.n	1954 <log_output_timestamp_freq_set+0xc>
    196a:	bf00      	nop
    196c:	200003cc 	.word	0x200003cc
    1970:	000f4240 	.word	0x000f4240
    1974:	200003c8 	.word	0x200003c8

00001978 <char_out>:
static const char LOG_HEX_SEP[10] = "##ZLOGV1##";

static const struct device *uart_dev;

static int char_out(uint8_t *data, size_t length, void *ctx)
{
    1978:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
		/* lower 8-bit */
		x = data[i] & 0x0FU;
		(void)hex2char(x, &c);
		uart_poll_out(uart_dev, c);
#else
		uart_poll_out(uart_dev, data[i]);
    197a:	4f07      	ldr	r7, [pc, #28]	; (1998 <char_out+0x20>)
{
    197c:	460d      	mov	r5, r1
    197e:	4604      	mov	r4, r0
    1980:	1846      	adds	r6, r0, r1
	for (size_t i = 0; i < length; i++) {
    1982:	42b4      	cmp	r4, r6
    1984:	d101      	bne.n	198a <char_out+0x12>
#endif
	}

	return length;
}
    1986:	4628      	mov	r0, r5
    1988:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		uart_poll_out(uart_dev, data[i]);
    198a:	6838      	ldr	r0, [r7, #0]
    198c:	f814 1b01 	ldrb.w	r1, [r4], #1
						unsigned char out_char)
{
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    1990:	6883      	ldr	r3, [r0, #8]
    1992:	685b      	ldr	r3, [r3, #4]
    1994:	4798      	blx	r3
	for (size_t i = 0; i < length; i++) {
    1996:	e7f4      	b.n	1982 <char_out+0xa>
    1998:	200003e4 	.word	0x200003e4

0000199c <panic>:
 * @param output	Log output instance.
 */
static inline void
log_backend_std_panic(const struct log_output *const output)
{
	log_output_flush(output);
    199c:	4801      	ldr	r0, [pc, #4]	; (19a4 <panic+0x8>)
    199e:	f004 bced 	b.w	637c <log_output_flush>
    19a2:	bf00      	nop
    19a4:	0000715c 	.word	0x0000715c

000019a8 <dropped>:
 * @param cnt		Number of dropped messages.
 */
static inline void
log_backend_std_dropped(const struct log_output *const output, uint32_t cnt)
{
	log_output_dropped_process(output, cnt);
    19a8:	4801      	ldr	r0, [pc, #4]	; (19b0 <dropped+0x8>)
    19aa:	f7ff bfa1 	b.w	18f0 <log_output_dropped_process>
    19ae:	bf00      	nop
    19b0:	0000715c 	.word	0x0000715c

000019b4 <log_backend_uart_init>:
		log_output_msg2_process(&log_output_uart, &msg->log, flags);
	}
}

static void log_backend_uart_init(struct log_backend const *const backend)
{
    19b4:	b508      	push	{r3, lr}
		/* coverity[OVERRUN] */
		return (const struct device *) arch_syscall_invoke1(*(uintptr_t *)&name, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
    19b6:	4803      	ldr	r0, [pc, #12]	; (19c4 <log_backend_uart_init+0x10>)
    19b8:	f002 f8d2 	bl	3b60 <z_impl_device_get_binding>
	uart_dev = device_get_binding(CONFIG_UART_CONSOLE_ON_DEV_NAME);
    19bc:	4b02      	ldr	r3, [pc, #8]	; (19c8 <log_backend_uart_init+0x14>)
    19be:	6018      	str	r0, [r3, #0]
		 */
		for (int i = 0; i < sizeof(LOG_HEX_SEP); i++) {
			uart_poll_out(uart_dev, LOG_HEX_SEP[i]);
		}
	}
}
    19c0:	bd08      	pop	{r3, pc}
    19c2:	bf00      	nop
    19c4:	00007419 	.word	0x00007419
    19c8:	200003e4 	.word	0x200003e4

000019cc <put>:
{
    19cc:	b510      	push	{r4, lr}
	log_msg_get(msg);
    19ce:	4608      	mov	r0, r1
    19d0:	460c      	mov	r4, r1
    19d2:	f004 fb1e 	bl	6012 <log_msg_get>
	log_output_msg_process(output, msg, flags);
    19d6:	4805      	ldr	r0, [pc, #20]	; (19ec <put+0x20>)
    19d8:	4621      	mov	r1, r4
    19da:	220f      	movs	r2, #15
    19dc:	f7ff ff0c 	bl	17f8 <log_output_msg_process>
	log_msg_put(msg);
    19e0:	4620      	mov	r0, r4
}
    19e2:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    19e6:	f004 bb43 	b.w	6070 <log_msg_put>
    19ea:	bf00      	nop
    19ec:	0000715c 	.word	0x0000715c

000019f0 <log_backend_rtt_init>:
{
	if (CONFIG_LOG_BACKEND_RTT_BUFFER > 0) {
		log_backend_rtt_cfg();
	}

	host_present = true;
    19f0:	4b01      	ldr	r3, [pc, #4]	; (19f8 <log_backend_rtt_init+0x8>)
    19f2:	2201      	movs	r2, #1
    19f4:	701a      	strb	r2, [r3, #0]
	line_pos = line_buf;
}
    19f6:	4770      	bx	lr
    19f8:	200006ad 	.word	0x200006ad

000019fc <panic>:

static void panic(struct log_backend const *const backend)
{
	panic_mode = true;
    19fc:	4b02      	ldr	r3, [pc, #8]	; (1a08 <panic+0xc>)
	log_output_flush(output);
    19fe:	4803      	ldr	r0, [pc, #12]	; (1a0c <panic+0x10>)
    1a00:	2201      	movs	r2, #1
    1a02:	701a      	strb	r2, [r3, #0]
    1a04:	f004 bcba 	b.w	637c <log_output_flush>
    1a08:	200006ae 	.word	0x200006ae
    1a0c:	00007188 	.word	0x00007188

00001a10 <dropped>:
	log_output_dropped_process(output, cnt);
    1a10:	4801      	ldr	r0, [pc, #4]	; (1a18 <dropped+0x8>)
    1a12:	f7ff bf6d 	b.w	18f0 <log_output_dropped_process>
    1a16:	bf00      	nop
    1a18:	00007188 	.word	0x00007188

00001a1c <put>:
{
    1a1c:	b510      	push	{r4, lr}
	log_msg_get(msg);
    1a1e:	4608      	mov	r0, r1
    1a20:	460c      	mov	r4, r1
    1a22:	f004 faf6 	bl	6012 <log_msg_get>
	log_output_msg_process(output, msg, flags);
    1a26:	4805      	ldr	r0, [pc, #20]	; (1a3c <put+0x20>)
    1a28:	4621      	mov	r1, r4
    1a2a:	220f      	movs	r2, #15
    1a2c:	f7ff fee4 	bl	17f8 <log_output_msg_process>
	log_msg_put(msg);
    1a30:	4620      	mov	r0, r4
}
    1a32:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    1a36:	f004 bb1b 	b.w	6070 <log_msg_put>
    1a3a:	bf00      	nop
    1a3c:	00007188 	.word	0x00007188

00001a40 <on_failed_write.part.0>:
	return IS_ENABLED(CONFIG_LOG_IMMEDIATE) || panic_mode;
    1a40:	4b05      	ldr	r3, [pc, #20]	; (1a58 <on_failed_write.part.0+0x18>)
	} else if (is_sync_mode()) {
    1a42:	781b      	ldrb	r3, [r3, #0]
    1a44:	b11b      	cbz	r3, 1a4e <on_failed_write.part.0+0xe>
	z_impl_k_busy_wait(usec_to_wait);
    1a46:	f241 3088 	movw	r0, #5000	; 0x1388
    1a4a:	f005 b827 	b.w	6a9c <z_impl_k_busy_wait>
	return z_impl_k_sleep(timeout);
    1a4e:	20a4      	movs	r0, #164	; 0xa4
    1a50:	2100      	movs	r1, #0
    1a52:	f003 b807 	b.w	4a64 <z_impl_k_sleep>
    1a56:	bf00      	nop
    1a58:	200006ae 	.word	0x200006ae

00001a5c <data_out_block_mode>:
{
    1a5c:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	return IS_ENABLED(CONFIG_LOG_IMMEDIATE) || panic_mode;
    1a60:	f8df 9094 	ldr.w	r9, [pc, #148]	; 1af8 <data_out_block_mode+0x9c>
	return z_impl_k_mutex_lock(mutex, timeout);
    1a64:	f8df a094 	ldr.w	sl, [pc, #148]	; 1afc <data_out_block_mode+0xa0>
{
    1a68:	4680      	mov	r8, r0
    1a6a:	460f      	mov	r7, r1
	int retry_cnt = IS_ENABLED(CONFIG_LOG_BACKEND_RTT_MODE_BLOCK) ?
    1a6c:	2404      	movs	r4, #4
    1a6e:	46cb      	mov	fp, r9
		if (!is_sync_mode()) {
    1a70:	f899 5000 	ldrb.w	r5, [r9]
    1a74:	b9cd      	cbnz	r5, 1aaa <data_out_block_mode+0x4e>
    1a76:	f04f 33ff 	mov.w	r3, #4294967295
    1a7a:	f04f 32ff 	mov.w	r2, #4294967295
    1a7e:	4650      	mov	r0, sl
    1a80:	f002 facc 	bl	401c <z_impl_k_mutex_lock>
			ret = SEGGER_RTT_WriteSkipNoLock(CONFIG_LOG_BACKEND_RTT_BUFFER,
    1a84:	463a      	mov	r2, r7
    1a86:	4641      	mov	r1, r8
    1a88:	4628      	mov	r0, r5
    1a8a:	f001 fff3 	bl	3a74 <SEGGER_RTT_WriteSkipNoLock>
    1a8e:	4606      	mov	r6, r0
	return z_impl_k_mutex_unlock(mutex);
    1a90:	4650      	mov	r0, sl
    1a92:	f002 fb41 	bl	4118 <z_impl_k_mutex_unlock>
		if (ret) {
    1a96:	4d17      	ldr	r5, [pc, #92]	; (1af4 <data_out_block_mode+0x98>)
    1a98:	b1fe      	cbz	r6, 1ada <data_out_block_mode+0x7e>
	host_present = true;
    1a9a:	2301      	movs	r3, #1
    1a9c:	702b      	strb	r3, [r5, #0]
	if (is_panic_mode()) {
    1a9e:	f89b 3000 	ldrb.w	r3, [fp]
    1aa2:	b96b      	cbnz	r3, 1ac0 <data_out_block_mode+0x64>
}
    1aa4:	4638      	mov	r0, r7
    1aa6:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
			ret = SEGGER_RTT_WriteSkipNoLock(CONFIG_LOG_BACKEND_RTT_BUFFER,
    1aaa:	463a      	mov	r2, r7
    1aac:	4641      	mov	r1, r8
    1aae:	2000      	movs	r0, #0
    1ab0:	f001 ffe0 	bl	3a74 <SEGGER_RTT_WriteSkipNoLock>
    1ab4:	4606      	mov	r6, r0
    1ab6:	e7ee      	b.n	1a96 <data_out_block_mode+0x3a>
	if (retry_cnt == 0) {
    1ab8:	b95c      	cbnz	r4, 1ad2 <data_out_block_mode+0x76>
		host_present = false;
    1aba:	702c      	strb	r4, [r5, #0]
    1abc:	f04f 34ff 	mov.w	r4, #4294967295
		while (SEGGER_RTT_HasDataUp(CONFIG_LOG_BACKEND_RTT_BUFFER) &&
    1ac0:	2000      	movs	r0, #0
    1ac2:	f002 f823 	bl	3b0c <SEGGER_RTT_HasDataUp>
    1ac6:	2800      	cmp	r0, #0
    1ac8:	d0ec      	beq.n	1aa4 <data_out_block_mode+0x48>
    1aca:	782b      	ldrb	r3, [r5, #0]
    1acc:	2b00      	cmp	r3, #0
    1ace:	d1f3      	bne.n	1ab8 <data_out_block_mode+0x5c>
    1ad0:	e7e8      	b.n	1aa4 <data_out_block_mode+0x48>
			on_failed_write(retry_cnt--);
    1ad2:	3c01      	subs	r4, #1
    1ad4:	f7ff ffb4 	bl	1a40 <on_failed_write.part.0>
    1ad8:	e7f2      	b.n	1ac0 <data_out_block_mode+0x64>
		} else if (host_present) {
    1ada:	782b      	ldrb	r3, [r5, #0]
    1adc:	b113      	cbz	r3, 1ae4 <data_out_block_mode+0x88>
	if (retry_cnt == 0) {
    1ade:	3c01      	subs	r4, #1
    1ae0:	d104      	bne.n	1aec <data_out_block_mode+0x90>
		host_present = false;
    1ae2:	702c      	strb	r4, [r5, #0]
	} while ((ret == 0) && host_present);
    1ae4:	782b      	ldrb	r3, [r5, #0]
    1ae6:	2b00      	cmp	r3, #0
    1ae8:	d1c2      	bne.n	1a70 <data_out_block_mode+0x14>
    1aea:	e7db      	b.n	1aa4 <data_out_block_mode+0x48>
    1aec:	f7ff ffa8 	bl	1a40 <on_failed_write.part.0>
    1af0:	e7f8      	b.n	1ae4 <data_out_block_mode+0x88>
    1af2:	bf00      	nop
    1af4:	200006ad 	.word	0x200006ad
    1af8:	200006ae 	.word	0x200006ae
    1afc:	200000e8 	.word	0x200000e8

00001b00 <__do_init_array_aux>:
 * @brief Execute initialization routines referenced in .init_array section
 *
 * @return N/A
 */
void __do_init_array_aux(void)
{
    1b00:	b538      	push	{r3, r4, r5, lr}
	for (func_ptr *func = __init_array_start;
    1b02:	4c04      	ldr	r4, [pc, #16]	; (1b14 <__do_init_array_aux+0x14>)
    1b04:	4d04      	ldr	r5, [pc, #16]	; (1b18 <__do_init_array_aux+0x18>)
    1b06:	42ac      	cmp	r4, r5
    1b08:	d300      	bcc.n	1b0c <__do_init_array_aux+0xc>
		func < __init_array_end;
		func++) {
		(*func)();
	}
}
    1b0a:	bd38      	pop	{r3, r4, r5, pc}
		(*func)();
    1b0c:	f854 3b04 	ldr.w	r3, [r4], #4
    1b10:	4798      	blx	r3
		func++) {
    1b12:	e7f8      	b.n	1b06 <__do_init_array_aux+0x6>
    1b14:	00007078 	.word	0x00007078
    1b18:	00007078 	.word	0x00007078

00001b1c <__do_global_ctors_aux>:
 *
 * This routine is invoked by the kernel prior to the execution of the
 * application's main().
 */
void __do_global_ctors_aux(void)
{
    1b1c:	b538      	push	{r3, r4, r5, lr}
	unsigned int nCtors;

	nCtors = (unsigned long)__CTOR_LIST__[0];
    1b1e:	4c05      	ldr	r4, [pc, #20]	; (1b34 <__do_global_ctors_aux+0x18>)
    1b20:	6825      	ldr	r5, [r4, #0]

	while (nCtors >= 1U) {
    1b22:	eb04 0485 	add.w	r4, r4, r5, lsl #2
    1b26:	b905      	cbnz	r5, 1b2a <__do_global_ctors_aux+0xe>
		__CTOR_LIST__[nCtors--]();
	}
}
    1b28:	bd38      	pop	{r3, r4, r5, pc}
		__CTOR_LIST__[nCtors--]();
    1b2a:	f854 3904 	ldr.w	r3, [r4], #-4
    1b2e:	3d01      	subs	r5, #1
    1b30:	4798      	blx	r3
    1b32:	e7f8      	b.n	1b26 <__do_global_ctors_aux+0xa>
    1b34:	00007070 	.word	0x00007070

00001b38 <pm_state_notify>:
/*
 * Function called to notify when the system is entering / exiting a
 * power state
 */
static inline void pm_state_notify(bool entering_state)
{
    1b38:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    1b3a:	4605      	mov	r5, r0
	__asm__ volatile(
    1b3c:	f04f 0320 	mov.w	r3, #32
    1b40:	f3ef 8611 	mrs	r6, BASEPRI
    1b44:	f383 8811 	msr	BASEPRI, r3
    1b48:	f3bf 8f6f 	isb	sy
	struct pm_notifier *notifier;
	k_spinlock_key_t pm_notifier_key;
	void (*callback)(enum pm_state state);

	pm_notifier_key = k_spin_lock(&pm_notifier_lock);
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    1b4c:	4b0b      	ldr	r3, [pc, #44]	; (1b7c <pm_state_notify+0x44>)
    1b4e:	681c      	ldr	r4, [r3, #0]
    1b50:	2c00      	cmp	r4, #0
    1b52:	bf38      	it	cc
    1b54:	2400      	movcc	r4, #0
    1b56:	b15c      	cbz	r4, 1b70 <pm_state_notify+0x38>
		} else {
			callback = notifier->state_exit;
		}

		if (callback) {
			callback(z_power_state.state);
    1b58:	4f09      	ldr	r7, [pc, #36]	; (1b80 <pm_state_notify+0x48>)
			callback = notifier->state_exit;
    1b5a:	e9d4 3201 	ldrd	r3, r2, [r4, #4]
    1b5e:	2d00      	cmp	r5, #0
    1b60:	bf08      	it	eq
    1b62:	4613      	moveq	r3, r2
		if (callback) {
    1b64:	b10b      	cbz	r3, 1b6a <pm_state_notify+0x32>
			callback(z_power_state.state);
    1b66:	7838      	ldrb	r0, [r7, #0]
    1b68:	4798      	blx	r3
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    1b6a:	6824      	ldr	r4, [r4, #0]
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    1b6c:	2c00      	cmp	r4, #0
    1b6e:	d1f4      	bne.n	1b5a <pm_state_notify+0x22>
	__asm__ volatile(
    1b70:	f386 8811 	msr	BASEPRI, r6
    1b74:	f3bf 8f6f 	isb	sy
		}
	}
	k_spin_unlock(&pm_notifier_lock, pm_notifier_key);
}
    1b78:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    1b7a:	bf00      	nop
    1b7c:	200003fc 	.word	0x200003fc
    1b80:	20000404 	.word	0x20000404

00001b84 <pm_system_resume>:

void pm_system_resume(void)
{
    1b84:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	 * and it may schedule another thread.
	 *
	 * Call pm_idle_exit_notification_disable() if this
	 * notification is not required.
	 */
	if (!post_ops_done) {
    1b86:	4b0f      	ldr	r3, [pc, #60]	; (1bc4 <pm_system_resume+0x40>)
    1b88:	681a      	ldr	r2, [r3, #0]
    1b8a:	b9ba      	cbnz	r2, 1bbc <pm_system_resume+0x38>
		post_ops_done = 1;
    1b8c:	2201      	movs	r2, #1
    1b8e:	601a      	str	r2, [r3, #0]
		exit_pos_ops(z_power_state);
    1b90:	4a0d      	ldr	r2, [pc, #52]	; (1bc8 <pm_system_resume+0x44>)
    1b92:	ca07      	ldmia	r2, {r0, r1, r2}
    1b94:	ab01      	add	r3, sp, #4
    1b96:	e883 0007 	stmia.w	r3, {r0, r1, r2}
	if (pm_power_state_exit_post_ops != NULL) {
    1b9a:	4a0c      	ldr	r2, [pc, #48]	; (1bcc <pm_system_resume+0x48>)
    1b9c:	b14a      	cbz	r2, 1bb2 <pm_system_resume+0x2e>
		pm_power_state_exit_post_ops(info);
    1b9e:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
    1ba2:	f004 fcef 	bl	6584 <pm_power_state_exit_post_ops>
		pm_state_notify(false);
    1ba6:	2000      	movs	r0, #0
	}
}
    1ba8:	b005      	add	sp, #20
    1baa:	f85d eb04 	ldr.w	lr, [sp], #4
		pm_state_notify(false);
    1bae:	f7ff bfc3 	b.w	1b38 <pm_state_notify>
    1bb2:	f382 8811 	msr	BASEPRI, r2
    1bb6:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    1bba:	e7f4      	b.n	1ba6 <pm_system_resume+0x22>
}
    1bbc:	b005      	add	sp, #20
    1bbe:	f85d fb04 	ldr.w	pc, [sp], #4
    1bc2:	bf00      	nop
    1bc4:	20000008 	.word	0x20000008
    1bc8:	20000404 	.word	0x20000404
    1bcc:	00006585 	.word	0x00006585

00001bd0 <pm_system_suspend>:
	return PM_STATE_ACTIVE;
}
#endif

enum pm_state pm_system_suspend(int32_t ticks)
{
    1bd0:	b5f0      	push	{r4, r5, r6, r7, lr}
    1bd2:	b089      	sub	sp, #36	; 0x24
	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);
	z_power_state = pm_policy_next_state(ticks);
    1bd4:	466e      	mov	r6, sp
    1bd6:	4601      	mov	r1, r0
{
    1bd8:	4605      	mov	r5, r0
	z_power_state = pm_policy_next_state(ticks);
    1bda:	4630      	mov	r0, r6
    1bdc:	f004 fbf6 	bl	63cc <pm_policy_next_state>
    1be0:	e896 0007 	ldmia.w	r6, {r0, r1, r2}
    1be4:	4c17      	ldr	r4, [pc, #92]	; (1c44 <pm_system_suspend+0x74>)
    1be6:	e884 0007 	stmia.w	r4, {r0, r1, r2}
	if (z_power_state.state == PM_STATE_ACTIVE) {
    1bea:	7820      	ldrb	r0, [r4, #0]
    1bec:	b340      	cbz	r0, 1c40 <pm_system_suspend+0x70>
		LOG_DBG("No PM operations done.");
		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks, z_power_state.state);
		return z_power_state.state;
	}
	post_ops_done = 0;
    1bee:	4b16      	ldr	r3, [pc, #88]	; (1c48 <pm_system_suspend+0x78>)
    1bf0:	2100      	movs	r1, #0
    1bf2:	6019      	str	r1, [r3, #0]

	if (ticks != K_TICKS_FOREVER) {
    1bf4:	1c6b      	adds	r3, r5, #1
    1bf6:	d00e      	beq.n	1c16 <pm_system_suspend+0x46>
		} else {
			return t * ((uint64_t)to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    1bf8:	4814      	ldr	r0, [pc, #80]	; (1c4c <pm_system_suspend+0x7c>)
    1bfa:	4617      	mov	r7, r2
    1bfc:	f44f 4600 	mov.w	r6, #32768	; 0x8000
    1c00:	2100      	movs	r1, #0
    1c02:	4a13      	ldr	r2, [pc, #76]	; (1c50 <pm_system_suspend+0x80>)
    1c04:	2300      	movs	r3, #0
    1c06:	fbe6 0107 	umlal	r0, r1, r6, r7
    1c0a:	f7fe fac9 	bl	1a0 <__aeabi_uldivmod>

		/*
		 * We need to set the timer to interrupt a little bit early to
		 * accommodate the time required by the CPU to fully wake up.
		 */
		z_set_timeout_expiry(ticks -
    1c0e:	2101      	movs	r1, #1
    1c10:	1a28      	subs	r0, r5, r0
    1c12:	f004 ff25 	bl	6a60 <z_set_timeout_expiry>
	 * state. We don't want to be scheduled out yet, first we need
	 * to send a notification about leaving the idle state. So,
	 * we lock the scheduler here and unlock just after we have
	 * sent the notification in pm_system_resume().
	 */
	k_sched_lock();
    1c16:	f002 fc95 	bl	4544 <k_sched_lock>
	pm_debug_start_timer();
	/* Enter power state */
	pm_state_notify(true);
    1c1a:	2001      	movs	r0, #1
    1c1c:	f7ff ff8c 	bl	1b38 <pm_state_notify>
	pm_state_set(z_power_state);
    1c20:	e894 0007 	ldmia.w	r4, {r0, r1, r2}
    1c24:	ab05      	add	r3, sp, #20
    1c26:	e883 0007 	stmia.w	r3, {r0, r1, r2}
	if (pm_power_state_set != NULL) {
    1c2a:	4a0a      	ldr	r2, [pc, #40]	; (1c54 <pm_system_suspend+0x84>)
    1c2c:	b11a      	cbz	r2, 1c36 <pm_system_suspend+0x66>
		pm_power_state_set(info);
    1c2e:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
    1c32:	f004 fc94 	bl	655e <pm_power_state_set>
		/* Turn on peripherals and restore device states as necessary */
		pm_resume_devices();
	}
#endif
	pm_log_debug_info(z_power_state.state);
	pm_system_resume();
    1c36:	f7ff ffa5 	bl	1b84 <pm_system_resume>
	k_sched_unlock();
    1c3a:	f002 fd3b 	bl	46b4 <k_sched_unlock>
	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks, z_power_state.state);
	return z_power_state.state;
    1c3e:	7820      	ldrb	r0, [r4, #0]
}
    1c40:	b009      	add	sp, #36	; 0x24
    1c42:	bdf0      	pop	{r4, r5, r6, r7, pc}
    1c44:	20000404 	.word	0x20000404
    1c48:	20000008 	.word	0x20000008
    1c4c:	000f423f 	.word	0x000f423f
    1c50:	000f4240 	.word	0x000f4240
    1c54:	0000655f 	.word	0x0000655f

00001c58 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    1c58:	b510      	push	{r4, lr}
    1c5a:	4807      	ldr	r0, [pc, #28]	; (1c78 <uart_console_init+0x20>)
	__stdout_hook_install(console_out);
    1c5c:	4c07      	ldr	r4, [pc, #28]	; (1c7c <uart_console_init+0x24>)
    1c5e:	f001 ff7f 	bl	3b60 <z_impl_device_get_binding>

	ARG_UNUSED(arg);

	/* Claim console device */
	uart_console_dev = device_get_binding(CONFIG_UART_CONSOLE_ON_DEV_NAME);
    1c62:	4b07      	ldr	r3, [pc, #28]	; (1c80 <uart_console_init+0x28>)
    1c64:	6018      	str	r0, [r3, #0]
	__stdout_hook_install(console_out);
    1c66:	4620      	mov	r0, r4
    1c68:	f001 f82e 	bl	2cc8 <__stdout_hook_install>
	__printk_hook_install(console_out);
    1c6c:	4620      	mov	r0, r4
    1c6e:	f7fe fc3b 	bl	4e8 <__printk_hook_install>

	uart_console_hook_install();

	return 0;
}
    1c72:	2000      	movs	r0, #0
    1c74:	bd10      	pop	{r4, pc}
    1c76:	bf00      	nop
    1c78:	00007419 	.word	0x00007419
    1c7c:	00001c85 	.word	0x00001c85
    1c80:	20000410 	.word	0x20000410

00001c84 <console_out>:
	if ('\n' == c) {
    1c84:	280a      	cmp	r0, #10
{
    1c86:	b538      	push	{r3, r4, r5, lr}
    1c88:	4d07      	ldr	r5, [pc, #28]	; (1ca8 <console_out+0x24>)
    1c8a:	4604      	mov	r4, r0
	if ('\n' == c) {
    1c8c:	d104      	bne.n	1c98 <console_out+0x14>
    1c8e:	6828      	ldr	r0, [r5, #0]
    1c90:	6883      	ldr	r3, [r0, #8]
    1c92:	210d      	movs	r1, #13
    1c94:	685b      	ldr	r3, [r3, #4]
    1c96:	4798      	blx	r3
	uart_poll_out(uart_console_dev, c);
    1c98:	6828      	ldr	r0, [r5, #0]
    1c9a:	6883      	ldr	r3, [r0, #8]
    1c9c:	b2e1      	uxtb	r1, r4
    1c9e:	685b      	ldr	r3, [r3, #4]
    1ca0:	4798      	blx	r3
}
    1ca2:	4620      	mov	r0, r4
    1ca4:	bd38      	pop	{r3, r4, r5, pc}
    1ca6:	bf00      	nop
    1ca8:	20000410 	.word	0x20000410

00001cac <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    1cac:	4a0d      	ldr	r2, [pc, #52]	; (1ce4 <onoff_stop+0x38>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    1cae:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1cb0:	1a85      	subs	r5, r0, r2
    1cb2:	f3c5 1347 	ubfx	r3, r5, #5, #8
	err = set_off_state(&subdata->flags, ctx);
    1cb6:	250c      	movs	r5, #12
    1cb8:	435d      	muls	r5, r3
{
    1cba:	4604      	mov	r4, r0
	err = set_off_state(&subdata->flags, ctx);
    1cbc:	f105 0048 	add.w	r0, r5, #72	; 0x48
{
    1cc0:	460e      	mov	r6, r1
	err = set_off_state(&subdata->flags, ctx);
    1cc2:	4410      	add	r0, r2
    1cc4:	2140      	movs	r1, #64	; 0x40
    1cc6:	f004 fb8f 	bl	63e8 <set_off_state>
	if (err < 0) {
    1cca:	1e01      	subs	r1, r0, #0
    1ccc:	db04      	blt.n	1cd8 <onoff_stop+0x2c>
	get_sub_config(dev, type)->stop();
    1cce:	4b06      	ldr	r3, [pc, #24]	; (1ce8 <onoff_stop+0x3c>)
    1cd0:	441d      	add	r5, r3
    1cd2:	686b      	ldr	r3, [r5, #4]
    1cd4:	4798      	blx	r3
	return 0;
    1cd6:	2100      	movs	r1, #0
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
	notify(mgr, res);
    1cd8:	4620      	mov	r0, r4
    1cda:	4633      	mov	r3, r6
}
    1cdc:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    1ce0:	4718      	bx	r3
    1ce2:	bf00      	nop
    1ce4:	20000428 	.word	0x20000428
    1ce8:	000071ac 	.word	0x000071ac

00001cec <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    1cec:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1cf0:	4c0e      	ldr	r4, [pc, #56]	; (1d2c <onoff_start+0x40>)
    1cf2:	1b05      	subs	r5, r0, r4
    1cf4:	f3c5 1347 	ubfx	r3, r5, #5, #8
	err = set_starting_state(&subdata->flags, ctx);
    1cf8:	250c      	movs	r5, #12
    1cfa:	435d      	muls	r5, r3
{
    1cfc:	4607      	mov	r7, r0
	err = set_starting_state(&subdata->flags, ctx);
    1cfe:	f105 0048 	add.w	r0, r5, #72	; 0x48
{
    1d02:	460e      	mov	r6, r1
	err = set_starting_state(&subdata->flags, ctx);
    1d04:	4420      	add	r0, r4
    1d06:	2140      	movs	r1, #64	; 0x40
    1d08:	f004 fb87 	bl	641a <set_starting_state>
	if (err < 0) {
    1d0c:	1e01      	subs	r1, r0, #0
    1d0e:	db08      	blt.n	1d22 <onoff_start+0x36>
	subdata->cb = cb;
    1d10:	4b07      	ldr	r3, [pc, #28]	; (1d30 <onoff_start+0x44>)
    1d12:	442c      	add	r4, r5
	subdata->user_data = user_data;
    1d14:	e9c4 3610 	strd	r3, r6, [r4, #64]	; 0x40
	 get_sub_config(dev, type)->start();
    1d18:	4b06      	ldr	r3, [pc, #24]	; (1d34 <onoff_start+0x48>)
    1d1a:	595b      	ldr	r3, [r3, r5]
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
		notify(mgr, err);
	}
}
    1d1c:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
	 get_sub_config(dev, type)->start();
    1d20:	4718      	bx	r3
		notify(mgr, err);
    1d22:	4638      	mov	r0, r7
    1d24:	4633      	mov	r3, r6
}
    1d26:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		notify(mgr, err);
    1d2a:	4718      	bx	r3
    1d2c:	20000428 	.word	0x20000428
    1d30:	0000647d 	.word	0x0000647d
    1d34:	000071ac 	.word	0x000071ac

00001d38 <clk_init>:
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1d38:	2200      	movs	r2, #0
{
    1d3a:	b570      	push	{r4, r5, r6, lr}
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1d3c:	2101      	movs	r1, #1
{
    1d3e:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1d40:	4610      	mov	r0, r2
    1d42:	f000 fb4f 	bl	23e4 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);
	irq_enable(DT_INST_IRQN(0));
    1d46:	2000      	movs	r0, #0
    1d48:	f000 fb2e 	bl	23a8 <arch_irq_enable>

	nrfx_err = nrfx_clock_init(clock_event_handler);
    1d4c:	4810      	ldr	r0, [pc, #64]	; (1d90 <clk_init+0x58>)
    1d4e:	f001 fd1b 	bl	3788 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    1d52:	4b10      	ldr	r3, [pc, #64]	; (1d94 <clk_init+0x5c>)
    1d54:	4298      	cmp	r0, r3
    1d56:	d118      	bne.n	1d8a <clk_init+0x52>

	if (IS_ENABLED(CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION) &&
	    !IS_ENABLED(CONFIG_CLOCK_CONTROL_NRF_FORCE_ALT)) {
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
    1d58:	6920      	ldr	r0, [r4, #16]
    1d5a:	f000 f9c7 	bl	20ec <z_nrf_clock_calibration_init>
	}

	nrfx_clock_enable();
    1d5e:	f004 fcbf 	bl	66e0 <nrfx_clock_enable>

	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);
    1d62:	6926      	ldr	r6, [r4, #16]

		err = onoff_manager_init(get_onoff_manager(dev, i),
    1d64:	490c      	ldr	r1, [pc, #48]	; (1d98 <clk_init+0x60>)
    1d66:	4630      	mov	r0, r6
    1d68:	f003 ffe2 	bl	5d30 <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    1d6c:	2800      	cmp	r0, #0
    1d6e:	db0b      	blt.n	1d88 <clk_init+0x50>
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1d70:	2501      	movs	r5, #1
    1d72:	64b5      	str	r5, [r6, #72]	; 0x48
						get_sub_data(dev, i);
    1d74:	6924      	ldr	r4, [r4, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    1d76:	4908      	ldr	r1, [pc, #32]	; (1d98 <clk_init+0x60>)
    1d78:	f104 0020 	add.w	r0, r4, #32
    1d7c:	f003 ffd8 	bl	5d30 <onoff_manager_init>
		if (err < 0) {
    1d80:	2800      	cmp	r0, #0
    1d82:	db01      	blt.n	1d88 <clk_init+0x50>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1d84:	6565      	str	r5, [r4, #84]	; 0x54
	}

	return 0;
    1d86:	2000      	movs	r0, #0
}
    1d88:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    1d8a:	f06f 0004 	mvn.w	r0, #4
    1d8e:	e7fb      	b.n	1d88 <clk_init+0x50>
    1d90:	00001dd1 	.word	0x00001dd1
    1d94:	0bad0000 	.word	0x0bad0000
    1d98:	000071c4 	.word	0x000071c4

00001d9c <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    1d9c:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    1d9e:	230c      	movs	r3, #12
    1da0:	4809      	ldr	r0, [pc, #36]	; (1dc8 <clkstarted_handle.constprop.0+0x2c>)
    1da2:	434b      	muls	r3, r1
static void clkstarted_handle(const struct device *dev,
    1da4:	b570      	push	{r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    1da6:	18c4      	adds	r4, r0, r3
	void *user_data = sub_data->user_data;
    1da8:	e9d4 5610 	ldrd	r5, r6, [r4, #64]	; 0x40
	sub_data->cb = NULL;
    1dac:	2200      	movs	r2, #0
	set_on_state(&sub_data->flags);
    1dae:	3348      	adds	r3, #72	; 0x48
	sub_data->cb = NULL;
    1db0:	6422      	str	r2, [r4, #64]	; 0x40
	set_on_state(&sub_data->flags);
    1db2:	4418      	add	r0, r3
    1db4:	f004 fb4f 	bl	6456 <set_on_state>
	if (callback) {
    1db8:	b12d      	cbz	r5, 1dc6 <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    1dba:	4632      	mov	r2, r6
    1dbc:	462b      	mov	r3, r5
    1dbe:	4803      	ldr	r0, [pc, #12]	; (1dcc <clkstarted_handle.constprop.0+0x30>)
}
    1dc0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    1dc4:	4718      	bx	r3
}
    1dc6:	bd70      	pop	{r4, r5, r6, pc}
    1dc8:	20000428 	.word	0x20000428
    1dcc:	00006e60 	.word	0x00006e60

00001dd0 <clock_event_handler>:
	switch (event) {
    1dd0:	2801      	cmp	r0, #1
{
    1dd2:	b510      	push	{r4, lr}
    1dd4:	4604      	mov	r4, r0
	switch (event) {
    1dd6:	d00a      	beq.n	1dee <clock_event_handler+0x1e>
    1dd8:	2803      	cmp	r0, #3
    1dda:	d00c      	beq.n	1df6 <clock_event_handler+0x26>
    1ddc:	b978      	cbnz	r0, 1dfe <clock_event_handler+0x2e>
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    1dde:	4b08      	ldr	r3, [pc, #32]	; (1e00 <clock_event_handler+0x30>)
    1de0:	6c9b      	ldr	r3, [r3, #72]	; 0x48
    1de2:	075b      	lsls	r3, r3, #29
    1de4:	d10b      	bne.n	1dfe <clock_event_handler+0x2e>
}
    1de6:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    1dea:	f7ff bfd7 	b.w	1d9c <clkstarted_handle.constprop.0>
			z_nrf_clock_calibration_lfclk_started();
    1dee:	f000 f98b 	bl	2108 <z_nrf_clock_calibration_lfclk_started>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    1df2:	4620      	mov	r0, r4
    1df4:	e7f7      	b.n	1de6 <clock_event_handler+0x16>
}
    1df6:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
			z_nrf_clock_calibration_done_handler();
    1dfa:	f000 b9a5 	b.w	2148 <z_nrf_clock_calibration_done_handler>
}
    1dfe:	bd10      	pop	{r4, pc}
    1e00:	20000428 	.word	0x20000428

00001e04 <generic_hfclk_start>:
{
    1e04:	b508      	push	{r3, lr}
	__asm__ volatile(
    1e06:	f04f 0320 	mov.w	r3, #32
    1e0a:	f3ef 8111 	mrs	r1, BASEPRI
    1e0e:	f383 8811 	msr	BASEPRI, r3
    1e12:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    1e16:	4a12      	ldr	r2, [pc, #72]	; (1e60 <generic_hfclk_start+0x5c>)
    1e18:	6813      	ldr	r3, [r2, #0]
    1e1a:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
    1e1e:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
    1e22:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    1e24:	d00c      	beq.n	1e40 <generic_hfclk_start+0x3c>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    1e26:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    1e2a:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    1e2e:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    1e32:	f013 0301 	ands.w	r3, r3, #1
    1e36:	d003      	beq.n	1e40 <generic_hfclk_start+0x3c>
			set_on_state(get_hf_flags());
    1e38:	480a      	ldr	r0, [pc, #40]	; (1e64 <generic_hfclk_start+0x60>)
    1e3a:	f004 fb0c 	bl	6456 <set_on_state>
			already_started = true;
    1e3e:	2301      	movs	r3, #1
	__asm__ volatile(
    1e40:	f381 8811 	msr	BASEPRI, r1
    1e44:	f3bf 8f6f 	isb	sy
	if (already_started) {
    1e48:	b123      	cbz	r3, 1e54 <generic_hfclk_start+0x50>
}
    1e4a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    1e4e:	2000      	movs	r0, #0
    1e50:	f7ff bfa4 	b.w	1d9c <clkstarted_handle.constprop.0>
}
    1e54:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    1e58:	2001      	movs	r0, #1
    1e5a:	f001 bca7 	b.w	37ac <nrfx_clock_start>
    1e5e:	bf00      	nop
    1e60:	20000480 	.word	0x20000480
    1e64:	20000470 	.word	0x20000470

00001e68 <generic_hfclk_stop>:
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    1e68:	4b09      	ldr	r3, [pc, #36]	; (1e90 <generic_hfclk_stop+0x28>)
    1e6a:	f3bf 8f5b 	dmb	ish
    1e6e:	e853 2f00 	ldrex	r2, [r3]
    1e72:	f022 0102 	bic.w	r1, r2, #2
    1e76:	e843 1000 	strex	r0, r1, [r3]
    1e7a:	2800      	cmp	r0, #0
    1e7c:	d1f7      	bne.n	1e6e <generic_hfclk_stop+0x6>
    1e7e:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    1e82:	07d3      	lsls	r3, r2, #31
    1e84:	d402      	bmi.n	1e8c <generic_hfclk_stop+0x24>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    1e86:	2001      	movs	r0, #1
    1e88:	f001 bcae 	b.w	37e8 <nrfx_clock_stop>
}
    1e8c:	4770      	bx	lr
    1e8e:	bf00      	nop
    1e90:	20000480 	.word	0x20000480

00001e94 <api_blocking_start>:
{
    1e94:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1e96:	2200      	movs	r2, #0
    1e98:	2301      	movs	r3, #1
    1e9a:	e9cd 2302 	strd	r2, r3, [sp, #8]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1e9e:	4a09      	ldr	r2, [pc, #36]	; (1ec4 <api_blocking_start+0x30>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1ea0:	f8cd d000 	str.w	sp, [sp]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1ea4:	466b      	mov	r3, sp
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1ea6:	f8cd d004 	str.w	sp, [sp, #4]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1eaa:	f004 fb0f 	bl	64cc <api_start>
	if (err < 0) {
    1eae:	2800      	cmp	r0, #0
    1eb0:	db05      	blt.n	1ebe <api_blocking_start+0x2a>
	return z_impl_k_sem_take(sem, timeout);
    1eb2:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    1eb6:	2300      	movs	r3, #0
    1eb8:	4668      	mov	r0, sp
    1eba:	f002 f993 	bl	41e4 <z_impl_k_sem_take>
}
    1ebe:	b005      	add	sp, #20
    1ec0:	f85d fb04 	ldr.w	pc, [sp], #4
    1ec4:	0000648f 	.word	0x0000648f

00001ec8 <z_nrf_clock_control_get_onoff>:
}
    1ec8:	4b02      	ldr	r3, [pc, #8]	; (1ed4 <z_nrf_clock_control_get_onoff+0xc>)
	return &data->mgr[type];
    1eca:	b2c0      	uxtb	r0, r0
}
    1ecc:	eb03 1040 	add.w	r0, r3, r0, lsl #5
    1ed0:	4770      	bx	lr
    1ed2:	bf00      	nop
    1ed4:	20000428 	.word	0x20000428

00001ed8 <z_nrf_clock_control_lf_on>:
{
    1ed8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    1eda:	4928      	ldr	r1, [pc, #160]	; (1f7c <z_nrf_clock_control_lf_on+0xa4>)
    1edc:	f3bf 8f5b 	dmb	ish
    1ee0:	4606      	mov	r6, r0
    1ee2:	2201      	movs	r2, #1
    1ee4:	e851 3f00 	ldrex	r3, [r1]
    1ee8:	e841 2000 	strex	r0, r2, [r1]
    1eec:	2800      	cmp	r0, #0
    1eee:	d1f9      	bne.n	1ee4 <z_nrf_clock_control_lf_on+0xc>
    1ef0:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    1ef4:	b933      	cbnz	r3, 1f04 <z_nrf_clock_control_lf_on+0x2c>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    1ef6:	4922      	ldr	r1, [pc, #136]	; (1f80 <z_nrf_clock_control_lf_on+0xa8>)
		err = onoff_request(mgr, &cli);
    1ef8:	4822      	ldr	r0, [pc, #136]	; (1f84 <z_nrf_clock_control_lf_on+0xac>)
    1efa:	604b      	str	r3, [r1, #4]
    1efc:	60cb      	str	r3, [r1, #12]
    1efe:	608a      	str	r2, [r1, #8]
    1f00:	f003 ff29 	bl	5d56 <onoff_request>
	switch (start_mode) {
    1f04:	1e73      	subs	r3, r6, #1
    1f06:	2b01      	cmp	r3, #1
    1f08:	d820      	bhi.n	1f4c <z_nrf_clock_control_lf_on+0x74>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    1f0a:	f004 fc4d 	bl	67a8 <k_is_in_isr>
    1f0e:	4604      	mov	r4, r0
    1f10:	b910      	cbnz	r0, 1f18 <z_nrf_clock_control_lf_on+0x40>
 */
static inline bool k_is_pre_kernel(void)
{
	extern bool z_sys_post_kernel; /* in init.c */

	return !z_sys_post_kernel;
    1f12:	4b1d      	ldr	r3, [pc, #116]	; (1f88 <z_nrf_clock_control_lf_on+0xb0>)
	int key = isr_mode ? irq_lock() : 0;
    1f14:	781b      	ldrb	r3, [r3, #0]
    1f16:	bb53      	cbnz	r3, 1f6e <z_nrf_clock_control_lf_on+0x96>
	__asm__ volatile(
    1f18:	f04f 0320 	mov.w	r3, #32
    1f1c:	f3ef 8511 	mrs	r5, BASEPRI
    1f20:	f383 8811 	msr	BASEPRI, r3
    1f24:	f3bf 8f6f 	isb	sy
    1f28:	2401      	movs	r4, #1
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    1f2a:	f04f 4780 	mov.w	r7, #1073741824	; 0x40000000
    1f2e:	f8d7 3418 	ldr.w	r3, [r7, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    1f32:	f8d7 2418 	ldr.w	r2, [r7, #1048]	; 0x418
    1f36:	03d2      	lsls	r2, r2, #15
    1f38:	d509      	bpl.n	1f4e <z_nrf_clock_control_lf_on+0x76>
	while (!(nrfx_clock_is_running(d, (void *)&type)
    1f3a:	079b      	lsls	r3, r3, #30
    1f3c:	d001      	beq.n	1f42 <z_nrf_clock_control_lf_on+0x6a>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    1f3e:	2e01      	cmp	r6, #1
    1f40:	d105      	bne.n	1f4e <z_nrf_clock_control_lf_on+0x76>
	if (isr_mode) {
    1f42:	b174      	cbz	r4, 1f62 <z_nrf_clock_control_lf_on+0x8a>
	__asm__ volatile(
    1f44:	f385 8811 	msr	BASEPRI, r5
    1f48:	f3bf 8f6f 	isb	sy
}
    1f4c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    1f4e:	b11c      	cbz	r4, 1f58 <z_nrf_clock_control_lf_on+0x80>
 *
 * @return N/A
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    1f50:	4628      	mov	r0, r5
    1f52:	f000 fb29 	bl	25a8 <arch_cpu_atomic_idle>
}
    1f56:	e7ea      	b.n	1f2e <z_nrf_clock_control_lf_on+0x56>
	return z_impl_k_sleep(timeout);
    1f58:	2100      	movs	r1, #0
    1f5a:	2021      	movs	r0, #33	; 0x21
    1f5c:	f002 fd82 	bl	4a64 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    1f60:	e7e5      	b.n	1f2e <z_nrf_clock_control_lf_on+0x56>
    p_reg->INTENSET = mask;
    1f62:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1f66:	2202      	movs	r2, #2
    1f68:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    1f6c:	e7ee      	b.n	1f4c <z_nrf_clock_control_lf_on+0x74>
    p_reg->INTENCLR = mask;
    1f6e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1f72:	2202      	movs	r2, #2
    1f74:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
	int key = isr_mode ? irq_lock() : 0;
    1f78:	4605      	mov	r5, r0
}
    1f7a:	e7d6      	b.n	1f2a <z_nrf_clock_control_lf_on+0x52>
    1f7c:	20000484 	.word	0x20000484
    1f80:	20000418 	.word	0x20000418
    1f84:	20000448 	.word	0x20000448
    1f88:	20000ac2 	.word	0x20000ac2

00001f8c <hf_request>:
					      sys_notify_generic_callback handler)
{
	__ASSERT_NO_MSG(notify != NULL);
	__ASSERT_NO_MSG(handler != NULL);

	*notify = (struct sys_notify){
    1f8c:	4905      	ldr	r1, [pc, #20]	; (1fa4 <hf_request+0x18>)
    1f8e:	2300      	movs	r3, #0
    1f90:	60cb      	str	r3, [r1, #12]
    1f92:	4b05      	ldr	r3, [pc, #20]	; (1fa8 <hf_request+0x1c>)
    1f94:	604b      	str	r3, [r1, #4]
    1f96:	2303      	movs	r3, #3
    1f98:	608b      	str	r3, [r1, #8]
			onoff_client_callback callback)
{
	int err;

	sys_notify_init_callback(&cli->notify, callback);
	err = onoff_request(mgr, cli);
    1f9a:	4b04      	ldr	r3, [pc, #16]	; (1fac <hf_request+0x20>)
    1f9c:	6818      	ldr	r0, [r3, #0]
    1f9e:	f003 beda 	b.w	5d56 <onoff_request>
    1fa2:	bf00      	nop
    1fa4:	2000048c 	.word	0x2000048c
    1fa8:	000020b9 	.word	0x000020b9
    1fac:	2000049c 	.word	0x2000049c

00001fb0 <temp_sensor_init>:
	total_skips_cnt = 0;
}

#if CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP
static int temp_sensor_init(const struct device *arg)
{
    1fb0:	b508      	push	{r3, lr}
    1fb2:	4803      	ldr	r0, [pc, #12]	; (1fc0 <temp_sensor_init+0x10>)
    1fb4:	f001 fdd4 	bl	3b60 <z_impl_device_get_binding>
	temp_sensor = temp_device();
    1fb8:	4b02      	ldr	r3, [pc, #8]	; (1fc4 <temp_sensor_init+0x14>)
    1fba:	6018      	str	r0, [r3, #0]

	return 0;
}
    1fbc:	2000      	movs	r0, #0
    1fbe:	bd08      	pop	{r3, pc}
    1fc0:	00007467 	.word	0x00007467
    1fc4:	200004a0 	.word	0x200004a0

00001fc8 <start_cycle>:
{
    1fc8:	b507      	push	{r0, r1, r2, lr}
	z_impl_k_timer_start(timer, duration, period);
    1fca:	2200      	movs	r2, #0
    1fcc:	2300      	movs	r3, #0
    1fce:	e9cd 2300 	strd	r2, r3, [sp]
    1fd2:	4808      	ldr	r0, [pc, #32]	; (1ff4 <start_cycle+0x2c>)
    1fd4:	f44f 3200 	mov.w	r2, #131072	; 0x20000
    1fd8:	2300      	movs	r3, #0
    1fda:	f002 ff77 	bl	4ecc <z_impl_k_timer_start>
	clk_release(&mgrs[CLOCK_CONTROL_NRF_TYPE_HFCLK]);
    1fde:	4b06      	ldr	r3, [pc, #24]	; (1ff8 <start_cycle+0x30>)
	err = onoff_release(mgr);
    1fe0:	6818      	ldr	r0, [r3, #0]
    1fe2:	f003 ff01 	bl	5de8 <onoff_release>
	cal_process_in_progress = 0;
    1fe6:	4b05      	ldr	r3, [pc, #20]	; (1ffc <start_cycle+0x34>)
    1fe8:	2200      	movs	r2, #0
    1fea:	601a      	str	r2, [r3, #0]
}
    1fec:	b003      	add	sp, #12
    1fee:	f85d fb04 	ldr.w	pc, [sp], #4
    1ff2:	bf00      	nop
    1ff4:	200000b0 	.word	0x200000b0
    1ff8:	2000049c 	.word	0x2000049c
    1ffc:	20000488 	.word	0x20000488

00002000 <measure_temperature>:
{
    2000:	b537      	push	{r0, r1, r2, r4, r5, lr}
	int rc = sensor_sample_fetch(temp_sensor);
    2002:	4c1d      	ldr	r4, [pc, #116]	; (2078 <measure_temperature+0x78>)
    2004:	6820      	ldr	r0, [r4, #0]
static inline int z_impl_sensor_sample_fetch(const struct device *dev)
{
	const struct sensor_driver_api *api =
		(const struct sensor_driver_api *)dev->api;

	return api->sample_fetch(dev, SENSOR_CHAN_ALL);
    2006:	6883      	ldr	r3, [r0, #8]
    2008:	4d1c      	ldr	r5, [pc, #112]	; (207c <measure_temperature+0x7c>)
    200a:	68db      	ldr	r3, [r3, #12]
    200c:	2138      	movs	r1, #56	; 0x38
    200e:	4798      	blx	r3
	if (rc == 0) {
    2010:	b188      	cbz	r0, 2036 <measure_temperature+0x36>
		calib_skip_cnt = 0;
    2012:	2400      	movs	r4, #0
    2014:	702c      	strb	r4, [r5, #0]
	int16_t diff = 0;
    2016:	4620      	mov	r0, r4
	if ((calib_skip_cnt == 0) ||
    2018:	782b      	ldrb	r3, [r5, #0]
    201a:	b10b      	cbz	r3, 2020 <measure_temperature+0x20>
    201c:	2801      	cmp	r0, #1
    201e:	dd22      	ble.n	2066 <measure_temperature+0x66>
		prev_temperature = temperature;
    2020:	4b17      	ldr	r3, [pc, #92]	; (2080 <measure_temperature+0x80>)
    2022:	801c      	strh	r4, [r3, #0]
		*(volatile uint32_t *)0x40000C34 = 0x00000002;
    2024:	4b17      	ldr	r3, [pc, #92]	; (2084 <measure_temperature+0x84>)
    2026:	2202      	movs	r2, #2
    2028:	601a      	str	r2, [r3, #0]
	nrfx_clock_calibration_start();
    202a:	f001 fc1f 	bl	386c <nrfx_clock_calibration_start>
	calib_skip_cnt = CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP;
    202e:	2301      	movs	r3, #1
    2030:	702b      	strb	r3, [r5, #0]
}
    2032:	b003      	add	sp, #12
    2034:	bd30      	pop	{r4, r5, pc}
		rc = sensor_channel_get(temp_sensor, SENSOR_CHAN_DIE_TEMP,
    2036:	6820      	ldr	r0, [r4, #0]
					    struct sensor_value *val)
{
	const struct sensor_driver_api *api =
		(const struct sensor_driver_api *)dev->api;

	return api->channel_get(dev, chan, val);
    2038:	6883      	ldr	r3, [r0, #8]
    203a:	466a      	mov	r2, sp
    203c:	691b      	ldr	r3, [r3, #16]
    203e:	210c      	movs	r1, #12
    2040:	4798      	blx	r3
	if (rc == 0) {
    2042:	2800      	cmp	r0, #0
    2044:	d1e5      	bne.n	2012 <measure_temperature+0x12>
	return (int16_t)(4 * val->val1 + val->val2 / 250000);
    2046:	9c01      	ldr	r4, [sp, #4]
    2048:	4b0f      	ldr	r3, [pc, #60]	; (2088 <measure_temperature+0x88>)
    204a:	fb94 f4f3 	sdiv	r4, r4, r3
    204e:	9b00      	ldr	r3, [sp, #0]
    2050:	eb04 0483 	add.w	r4, r4, r3, lsl #2
		diff = abs(temperature - prev_temperature);
    2054:	4b0a      	ldr	r3, [pc, #40]	; (2080 <measure_temperature+0x80>)
    2056:	f9b3 0000 	ldrsh.w	r0, [r3]
	return (int16_t)(4 * val->val1 + val->val2 / 250000);
    205a:	b224      	sxth	r4, r4
		diff = abs(temperature - prev_temperature);
    205c:	1a20      	subs	r0, r4, r0
    205e:	f004 fd4b 	bl	6af8 <abs>
    2062:	b200      	sxth	r0, r0
    2064:	e7d8      	b.n	2018 <measure_temperature+0x18>
		total_skips_cnt++;
    2066:	4a09      	ldr	r2, [pc, #36]	; (208c <measure_temperature+0x8c>)
		calib_skip_cnt--;
    2068:	3b01      	subs	r3, #1
    206a:	702b      	strb	r3, [r5, #0]
		total_skips_cnt++;
    206c:	6813      	ldr	r3, [r2, #0]
    206e:	3301      	adds	r3, #1
    2070:	6013      	str	r3, [r2, #0]
		start_cycle();
    2072:	f7ff ffa9 	bl	1fc8 <start_cycle>
}
    2076:	e7dc      	b.n	2032 <measure_temperature+0x32>
    2078:	200004a0 	.word	0x200004a0
    207c:	200006af 	.word	0x200006af
    2080:	20000698 	.word	0x20000698
    2084:	40000c34 	.word	0x40000c34
    2088:	0003d090 	.word	0x0003d090
    208c:	200004a8 	.word	0x200004a8

00002090 <timeout_handler>:
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    2090:	4b08      	ldr	r3, [pc, #32]	; (20b4 <timeout_handler+0x24>)
    2092:	f3bf 8f5b 	dmb	ish
    2096:	2201      	movs	r2, #1
    2098:	e853 1f00 	ldrex	r1, [r3]
    209c:	2900      	cmp	r1, #0
    209e:	d103      	bne.n	20a8 <timeout_handler+0x18>
    20a0:	e843 2000 	strex	r0, r2, [r3]
    20a4:	2800      	cmp	r0, #0
    20a6:	d1f7      	bne.n	2098 <timeout_handler+0x8>
    20a8:	f3bf 8f5b 	dmb	ish
	if (atomic_cas(&cal_process_in_progress, 0, 1) == false) {
    20ac:	d101      	bne.n	20b2 <timeout_handler+0x22>
		hf_request();
    20ae:	f7ff bf6d 	b.w	1f8c <hf_request>
}
    20b2:	4770      	bx	lr
    20b4:	20000488 	.word	0x20000488

000020b8 <cal_hf_callback>:
{
    20b8:	b508      	push	{r3, lr}
	if ((temp_sensor == NULL) || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    20ba:	4b08      	ldr	r3, [pc, #32]	; (20dc <cal_hf_callback+0x24>)
    20bc:	681b      	ldr	r3, [r3, #0]
    20be:	b943      	cbnz	r3, 20d2 <cal_hf_callback+0x1a>
		*(volatile uint32_t *)0x40000C34 = 0x00000002;
    20c0:	4b07      	ldr	r3, [pc, #28]	; (20e0 <cal_hf_callback+0x28>)
    20c2:	2202      	movs	r2, #2
    20c4:	601a      	str	r2, [r3, #0]
	nrfx_clock_calibration_start();
    20c6:	f001 fbd1 	bl	386c <nrfx_clock_calibration_start>
	calib_skip_cnt = CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP;
    20ca:	4b06      	ldr	r3, [pc, #24]	; (20e4 <cal_hf_callback+0x2c>)
    20cc:	2201      	movs	r2, #1
    20ce:	701a      	strb	r2, [r3, #0]
}
    20d0:	bd08      	pop	{r3, pc}
    20d2:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		k_work_submit(&temp_measure_work);
    20d6:	4804      	ldr	r0, [pc, #16]	; (20e8 <cal_hf_callback+0x30>)
    20d8:	f002 b99c 	b.w	4414 <k_work_submit>
    20dc:	200004a0 	.word	0x200004a0
    20e0:	40000c34 	.word	0x40000c34
    20e4:	200006af 	.word	0x200006af
    20e8:	2000000c 	.word	0x2000000c

000020ec <z_nrf_clock_calibration_init>:
	mgrs = onoff_mgrs;
    20ec:	4b03      	ldr	r3, [pc, #12]	; (20fc <z_nrf_clock_calibration_init+0x10>)
	total_cnt = 0;
    20ee:	4a04      	ldr	r2, [pc, #16]	; (2100 <z_nrf_clock_calibration_init+0x14>)
	mgrs = onoff_mgrs;
    20f0:	6018      	str	r0, [r3, #0]
	total_cnt = 0;
    20f2:	2300      	movs	r3, #0
    20f4:	6013      	str	r3, [r2, #0]
	total_skips_cnt = 0;
    20f6:	4a03      	ldr	r2, [pc, #12]	; (2104 <z_nrf_clock_calibration_init+0x18>)
    20f8:	6013      	str	r3, [r2, #0]
}
    20fa:	4770      	bx	lr
    20fc:	2000049c 	.word	0x2000049c
    2100:	200004a4 	.word	0x200004a4
    2104:	200004a8 	.word	0x200004a8

00002108 <z_nrf_clock_calibration_lfclk_started>:
SYS_INIT(temp_sensor_init, APPLICATION, 0);
#endif /* CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP */

static void start_unconditional_cal_process(void)
{
	calib_skip_cnt = 0;
    2108:	4b0a      	ldr	r3, [pc, #40]	; (2134 <z_nrf_clock_calibration_lfclk_started+0x2c>)
    210a:	2200      	movs	r2, #0
    210c:	701a      	strb	r2, [r3, #0]
    210e:	4b0a      	ldr	r3, [pc, #40]	; (2138 <z_nrf_clock_calibration_lfclk_started+0x30>)
    2110:	f3bf 8f5b 	dmb	ish
    2114:	2201      	movs	r2, #1
    2116:	e853 1f00 	ldrex	r1, [r3]
    211a:	2900      	cmp	r1, #0
    211c:	d103      	bne.n	2126 <z_nrf_clock_calibration_lfclk_started+0x1e>
    211e:	e843 2000 	strex	r0, r2, [r3]
    2122:	2800      	cmp	r0, #0
    2124:	d1f7      	bne.n	2116 <z_nrf_clock_calibration_lfclk_started+0xe>
    2126:	f3bf 8f5b 	dmb	ish
	if (atomic_cas(&cal_process_in_progress, 0, 1) == false) {
    212a:	d101      	bne.n	2130 <z_nrf_clock_calibration_lfclk_started+0x28>
		hf_request();
    212c:	f7ff bf2e 	b.w	1f8c <hf_request>
}

void z_nrf_clock_calibration_lfclk_started(void)
{
	start_unconditional_cal_process();
}
    2130:	4770      	bx	lr
    2132:	bf00      	nop
    2134:	200006af 	.word	0x200006af
    2138:	20000488 	.word	0x20000488

0000213c <z_nrf_clock_calibration_lfclk_stopped>:
	z_impl_k_timer_stop(timer);
    213c:	4801      	ldr	r0, [pc, #4]	; (2144 <z_nrf_clock_calibration_lfclk_stopped+0x8>)
    213e:	f004 bcbd 	b.w	6abc <z_impl_k_timer_stop>
    2142:	bf00      	nop
    2144:	200000b0 	.word	0x200000b0

00002148 <z_nrf_clock_calibration_done_handler>:
	LOG_DBG("Calibration stopped");
}

void z_nrf_clock_calibration_done_handler(void)
{
	total_cnt++;
    2148:	4a02      	ldr	r2, [pc, #8]	; (2154 <z_nrf_clock_calibration_done_handler+0xc>)
    214a:	6813      	ldr	r3, [r2, #0]
    214c:	3301      	adds	r3, #1
    214e:	6013      	str	r3, [r2, #0]
	LOG_DBG("Calibration done.");

	start_cycle();
    2150:	f7ff bf3a 	b.w	1fc8 <start_cycle>
    2154:	200004a4 	.word	0x200004a4

00002158 <sys_clock_timeout_handler>:

static void sys_clock_timeout_handler(int32_t chan,
				      uint32_t cc_value,
				      void *user_data)
{
	uint32_t dticks = counter_sub(cc_value, last_count) / CYC_PER_TICK;
    2158:	4a04      	ldr	r2, [pc, #16]	; (216c <sys_clock_timeout_handler+0x14>)
    215a:	6813      	ldr	r3, [r2, #0]
	return (a - b) & COUNTER_MAX;
    215c:	1ac8      	subs	r0, r1, r3
    215e:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000

	last_count += dticks * CYC_PER_TICK;
    2162:	4403      	add	r3, r0
    2164:	6013      	str	r3, [r2, #0]
		 */
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    2166:	f002 be03 	b.w	4d70 <sys_clock_announce>
    216a:	bf00      	nop
    216c:	200004bc 	.word	0x200004bc

00002170 <set_absolute_alarm>:
{
    2170:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    2174:	0086      	lsls	r6, r0, #2
    2176:	f106 4680 	add.w	r6, r6, #1073741824	; 0x40000000
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    217a:	f100 0450 	add.w	r4, r0, #80	; 0x50
    217e:	f506 3688 	add.w	r6, r6, #69632	; 0x11000
    2182:	00a4      	lsls	r4, r4, #2
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type const * p_reg)
{
     return p_reg->COUNTER;
    2184:	f8df 807c 	ldr.w	r8, [pc, #124]	; 2204 <set_absolute_alarm+0x94>
    return p_reg->CC[ch];
    2188:	f8d6 3540 	ldr.w	r3, [r6, #1344]	; 0x540
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    218c:	b2a4      	uxth	r4, r4
    218e:	f104 4480 	add.w	r4, r4, #1073741824	; 0x40000000
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2192:	f44f 3780 	mov.w	r7, #65536	; 0x10000
	uint32_t cc_val = abs_val & COUNTER_MAX;
    2196:	f021 457f 	bic.w	r5, r1, #4278190080	; 0xff000000
    219a:	f504 3488 	add.w	r4, r4, #69632	; 0x11000
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    219e:	4087      	lsls	r7, r0
    21a0:	46c1      	mov	r9, r8
     return p_reg->COUNTER;
    21a2:	f8d8 a504 	ldr.w	sl, [r8, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    21a6:	eba3 030a 	sub.w	r3, r3, sl
    21aa:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    21ae:	f02a 427f 	bic.w	r2, sl, #4278190080	; 0xff000000
		if (counter_sub(prev_cc, now) == 1) {
    21b2:	2b01      	cmp	r3, #1
    p_reg->CC[ch] = cc_val;
    21b4:	f8c6 2540 	str.w	r2, [r6, #1344]	; 0x540
    21b8:	d102      	bne.n	21c0 <set_absolute_alarm+0x50>
	z_impl_k_busy_wait(usec_to_wait);
    21ba:	2013      	movs	r0, #19
    21bc:	f004 fc6e 	bl	6a9c <z_impl_k_busy_wait>
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    21c0:	f10a 0202 	add.w	r2, sl, #2
	return (a - b) & COUNTER_MAX;
    21c4:	1aab      	subs	r3, r5, r2
    21c6:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
			cc_val = now + 2;
    21ca:	f5b3 0f00 	cmp.w	r3, #8388608	; 0x800000
    21ce:	bf88      	it	hi
    21d0:	4615      	movhi	r5, r2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    21d2:	2300      	movs	r3, #0
    21d4:	6023      	str	r3, [r4, #0]
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    21d6:	6823      	ldr	r3, [r4, #0]
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
    21d8:	f8c9 7344 	str.w	r7, [r9, #836]	; 0x344
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    21dc:	f025 437f 	bic.w	r3, r5, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    21e0:	f8c6 3540 	str.w	r3, [r6, #1344]	; 0x540
     return p_reg->COUNTER;
    21e4:	f8d9 3504 	ldr.w	r3, [r9, #1284]	; 0x504
		 (counter_sub(cc_val, now2 + 2) > COUNTER_HALF_SPAN));
    21e8:	459a      	cmp	sl, r3
    21ea:	d006      	beq.n	21fa <set_absolute_alarm+0x8a>
	return (a - b) & COUNTER_MAX;
    21ec:	1aeb      	subs	r3, r5, r3
    21ee:	3b02      	subs	r3, #2
    21f0:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
	} while ((now2 != now) &&
    21f4:	f5b3 0f00 	cmp.w	r3, #8388608	; 0x800000
    21f8:	d801      	bhi.n	21fe <set_absolute_alarm+0x8e>
}
    21fa:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		prev_cc = cc_val;
    21fe:	462b      	mov	r3, r5
    2200:	e7cf      	b.n	21a2 <set_absolute_alarm+0x32>
    2202:	bf00      	nop
    2204:	40011000 	.word	0x40011000

00002208 <rtc_nrf_isr>:
 * probably better abstract that at some point (e.g. query and reset
 * it by pointer at runtime, maybe?) so we don't have this leaky
 * symbol.
 */
void rtc_nrf_isr(const void *arg)
{
    2208:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    return p_reg->INTENSET & mask;
    220a:	4c15      	ldr	r4, [pc, #84]	; (2260 <rtc_nrf_isr+0x58>)
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    220c:	4f15      	ldr	r7, [pc, #84]	; (2264 <rtc_nrf_isr+0x5c>)
	ARG_UNUSED(arg);

	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    220e:	2600      	movs	r6, #0
    2210:	4b15      	ldr	r3, [pc, #84]	; (2268 <rtc_nrf_isr+0x60>)
    2212:	2000      	movs	r0, #0
    2214:	681d      	ldr	r5, [r3, #0]
    2216:	469c      	mov	ip, r3
    2218:	b106      	cbz	r6, 221c <rtc_nrf_isr+0x14>
				handler(chan, cc_val,
					cc_data[chan].user_context);
			}
		}
	}
}
    221a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    return p_reg->INTENSET & mask;
    221c:	f8d4 2304 	ldr.w	r2, [r4, #772]	; 0x304
		if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan)) &&
    2220:	03d2      	lsls	r2, r2, #15
    2222:	d5fa      	bpl.n	221a <rtc_nrf_isr+0x12>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2224:	683a      	ldr	r2, [r7, #0]
    2226:	2a00      	cmp	r2, #0
    2228:	d0f7      	beq.n	221a <rtc_nrf_isr+0x12>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    222a:	603e      	str	r6, [r7, #0]
    222c:	683a      	ldr	r2, [r7, #0]
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    222e:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    2232:	f8c4 2348 	str.w	r2, [r4, #840]	; 0x348
    return p_reg->CC[ch];
    2236:	f8d4 1540 	ldr.w	r1, [r4, #1344]	; 0x540
     return p_reg->COUNTER;
    223a:	f8d4 6504 	ldr.w	r6, [r4, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    223e:	1a72      	subs	r2, r6, r1
    2240:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
				cc_val = now;
    2244:	f5b2 0f00 	cmp.w	r2, #8388608	; 0x800000
    2248:	bf88      	it	hi
    224a:	4631      	movhi	r1, r6
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    224c:	2601      	movs	r6, #1
			if (handler) {
    224e:	b11d      	cbz	r5, 2258 <rtc_nrf_isr+0x50>
				handler(chan, cc_val,
    2250:	685a      	ldr	r2, [r3, #4]
    2252:	6018      	str	r0, [r3, #0]
    2254:	47a8      	blx	r5
    2256:	e7db      	b.n	2210 <rtc_nrf_isr+0x8>
    2258:	f8cc 5000 	str.w	r5, [ip]
}
    225c:	e7dd      	b.n	221a <rtc_nrf_isr+0x12>
    225e:	bf00      	nop
    2260:	40011000 	.word	0x40011000
    2264:	40011140 	.word	0x40011140
    2268:	200004b0 	.word	0x200004b0

0000226c <sys_clock_driver_init>:

	atomic_or(&alloc_mask, BIT(chan));
}

int sys_clock_driver_init(const struct device *dev)
{
    226c:	b538      	push	{r3, r4, r5, lr}
    p_reg->PRESCALER = val;
    226e:	4d10      	ldr	r5, [pc, #64]	; (22b0 <sys_clock_driver_init+0x44>)
    2270:	2400      	movs	r4, #0
    p_reg->INTENSET = mask;
    2272:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    p_reg->PRESCALER = val;
    2276:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    p_reg->INTENSET = mask;
    227a:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
 */
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    227e:	4b0d      	ldr	r3, [pc, #52]	; (22b4 <sys_clock_driver_init+0x48>)
    2280:	f44f 3200 	mov.w	r2, #131072	; 0x20000
    2284:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
	}

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    2288:	2101      	movs	r1, #1
    228a:	4622      	mov	r2, r4
    228c:	2011      	movs	r0, #17
    228e:	f000 f8a9 	bl	23e4 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    2292:	2011      	movs	r0, #17
    2294:	f000 f888 	bl	23a8 <arch_irq_enable>
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    2298:	4a07      	ldr	r2, [pc, #28]	; (22b8 <sys_clock_driver_init+0x4c>)
    229a:	2301      	movs	r3, #1
    229c:	6013      	str	r3, [r2, #0]

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    229e:	4a07      	ldr	r2, [pc, #28]	; (22bc <sys_clock_driver_init+0x50>)
    22a0:	602b      	str	r3, [r5, #0]
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		compare_set(0, counter() + CYC_PER_TICK,
			    sys_clock_timeout_handler, NULL);
	}

	z_nrf_clock_control_lf_on(mode);
    22a2:	2002      	movs	r0, #2
	int_mask = BIT_MASK(CHAN_COUNT);
    22a4:	6013      	str	r3, [r2, #0]
	z_nrf_clock_control_lf_on(mode);
    22a6:	f7ff fe17 	bl	1ed8 <z_nrf_clock_control_lf_on>

	return 0;
}
    22aa:	4620      	mov	r0, r4
    22ac:	bd38      	pop	{r3, r4, r5, pc}
    22ae:	bf00      	nop
    22b0:	40011000 	.word	0x40011000
    22b4:	e000e100 	.word	0xe000e100
    22b8:	40011008 	.word	0x40011008
    22bc:	200004b8 	.word	0x200004b8

000022c0 <sys_clock_set_timeout>:

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return;
	}

	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    22c0:	4b13      	ldr	r3, [pc, #76]	; (2310 <sys_clock_set_timeout+0x50>)
    22c2:	f1b0 3fff 	cmp.w	r0, #4294967295
    22c6:	bf08      	it	eq
    22c8:	4618      	moveq	r0, r3
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    22ca:	3801      	subs	r0, #1
    22cc:	2800      	cmp	r0, #0
    22ce:	dd1c      	ble.n	230a <sys_clock_set_timeout+0x4a>
    22d0:	4298      	cmp	r0, r3
    22d2:	bfa8      	it	ge
    22d4:	4618      	movge	r0, r3
     return p_reg->COUNTER;
    22d6:	4b0f      	ldr	r3, [pc, #60]	; (2314 <sys_clock_set_timeout+0x54>)
    22d8:	f8d3 2504 	ldr.w	r2, [r3, #1284]	; 0x504

	uint32_t unannounced = counter_sub(counter(), last_count);
    22dc:	4b0e      	ldr	r3, [pc, #56]	; (2318 <sys_clock_set_timeout+0x58>)
    22de:	6819      	ldr	r1, [r3, #0]
	return (a - b) & COUNTER_MAX;
    22e0:	1a52      	subs	r2, r2, r1
	 * duration, then force an announce to avoid loss of a wrap
	 * event.  This can happen if new timeouts keep being set
	 * before the existing one triggers the interrupt.
	 */
	if (unannounced >= COUNTER_HALF_SPAN) {
		ticks = 0;
    22e2:	f412 0f00 	tst.w	r2, #8388608	; 0x800000
	return (a - b) & COUNTER_MAX;
    22e6:	f022 437f 	bic.w	r3, r2, #4278190080	; 0xff000000
		ticks = 0;
    22ea:	bf18      	it	ne
    22ec:	2000      	movne	r0, #0
	cc_data[chan].callback = handler;
    22ee:	4a0b      	ldr	r2, [pc, #44]	; (231c <sys_clock_set_timeout+0x5c>)
	}

	/* Get the cycles from last_count to the tick boundary after
	 * the requested ticks have passed starting now.
	 */
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    22f0:	3301      	adds	r3, #1
    22f2:	4403      	add	r3, r0
	cc_data[chan].callback = handler;
    22f4:	480a      	ldr	r0, [pc, #40]	; (2320 <sys_clock_set_timeout+0x60>)
    22f6:	6010      	str	r0, [r2, #0]
	cc_data[chan].user_context = user_data;
    22f8:	2000      	movs	r0, #0
    22fa:	6050      	str	r0, [r2, #4]
	set_absolute_alarm(chan, cc_value);
    22fc:	4a04      	ldr	r2, [pc, #16]	; (2310 <sys_clock_set_timeout+0x50>)
    22fe:	4293      	cmp	r3, r2
    2300:	bf94      	ite	ls
    2302:	18c9      	addls	r1, r1, r3
    2304:	1889      	addhi	r1, r1, r2
    2306:	f7ff bf33 	b.w	2170 <set_absolute_alarm>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    230a:	2000      	movs	r0, #0
    230c:	e7e3      	b.n	22d6 <sys_clock_set_timeout+0x16>
    230e:	bf00      	nop
    2310:	007fffff 	.word	0x007fffff
    2314:	40011000 	.word	0x40011000
    2318:	200004bc 	.word	0x200004bc
    231c:	200004b0 	.word	0x200004b0
    2320:	00002159 	.word	0x00002159

00002324 <sys_clock_elapsed>:
    2324:	4b04      	ldr	r3, [pc, #16]	; (2338 <sys_clock_elapsed+0x14>)
    2326:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
{
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return 0;
	}

	return counter_sub(counter(), last_count) / CYC_PER_TICK;
    232a:	4b04      	ldr	r3, [pc, #16]	; (233c <sys_clock_elapsed+0x18>)
	return (a - b) & COUNTER_MAX;
    232c:	681b      	ldr	r3, [r3, #0]
    232e:	1ac0      	subs	r0, r0, r3
}
    2330:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
    2334:	4770      	bx	lr
    2336:	bf00      	nop
    2338:	40011000 	.word	0x40011000
    233c:	200004bc 	.word	0x200004bc

00002340 <sys_clock_cycle_get_32>:
	__asm__ volatile(
    2340:	f04f 0320 	mov.w	r3, #32
    2344:	f3ef 8211 	mrs	r2, BASEPRI
    2348:	f383 8811 	msr	BASEPRI, r3
    234c:	f3bf 8f6f 	isb	sy

uint32_t sys_clock_cycle_get_32(void)
{
	k_spinlock_key_t key = k_spin_lock(&lock);
	uint32_t ret = counter_sub(counter(), last_count) + last_count;
    2350:	4906      	ldr	r1, [pc, #24]	; (236c <sys_clock_cycle_get_32+0x2c>)
    2352:	4b07      	ldr	r3, [pc, #28]	; (2370 <sys_clock_cycle_get_32+0x30>)
    2354:	6808      	ldr	r0, [r1, #0]
    2356:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	__asm__ volatile(
    235a:	f382 8811 	msr	BASEPRI, r2
    235e:	f3bf 8f6f 	isb	sy
	return (a - b) & COUNTER_MAX;
    2362:	1a1b      	subs	r3, r3, r0
    2364:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000

	k_spin_unlock(&lock, key);
	return ret;
}
    2368:	4418      	add	r0, r3
    236a:	4770      	bx	lr
    236c:	200004bc 	.word	0x200004bc
    2370:	40011000 	.word	0x40011000

00002374 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    2374:	4a09      	ldr	r2, [pc, #36]	; (239c <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    2376:	490a      	ldr	r1, [pc, #40]	; (23a0 <arch_swap+0x2c>)
	_current->arch.basepri = key;
    2378:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    237a:	6809      	ldr	r1, [r1, #0]
    237c:	6799      	str	r1, [r3, #120]	; 0x78

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    237e:	4909      	ldr	r1, [pc, #36]	; (23a4 <arch_swap+0x30>)
	_current->arch.basepri = key;
    2380:	6758      	str	r0, [r3, #116]	; 0x74
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    2382:	684b      	ldr	r3, [r1, #4]
    2384:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    2388:	604b      	str	r3, [r1, #4]
    238a:	2300      	movs	r3, #0
    238c:	f383 8811 	msr	BASEPRI, r3
    2390:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    2394:	6893      	ldr	r3, [r2, #8]
}
    2396:	6f98      	ldr	r0, [r3, #120]	; 0x78
    2398:	4770      	bx	lr
    239a:	bf00      	nop
    239c:	20000648 	.word	0x20000648
    23a0:	00007274 	.word	0x00007274
    23a4:	e000ed00 	.word	0xe000ed00

000023a8 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    23a8:	b243      	sxtb	r3, r0
  if ((int32_t)(IRQn) >= 0)
    23aa:	2b00      	cmp	r3, #0
    23ac:	db08      	blt.n	23c0 <arch_irq_enable+0x18>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    23ae:	2201      	movs	r2, #1
    23b0:	f000 001f 	and.w	r0, r0, #31
    23b4:	fa02 f000 	lsl.w	r0, r2, r0
    23b8:	095b      	lsrs	r3, r3, #5
    23ba:	4a02      	ldr	r2, [pc, #8]	; (23c4 <arch_irq_enable+0x1c>)
    23bc:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    23c0:	4770      	bx	lr
    23c2:	bf00      	nop
    23c4:	e000e100 	.word	0xe000e100

000023c8 <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    23c8:	4b05      	ldr	r3, [pc, #20]	; (23e0 <arch_irq_is_enabled+0x18>)
    23ca:	0942      	lsrs	r2, r0, #5
    23cc:	f000 001f 	and.w	r0, r0, #31
    23d0:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    23d4:	2301      	movs	r3, #1
    23d6:	fa03 f000 	lsl.w	r0, r3, r0
}
    23da:	4010      	ands	r0, r2
    23dc:	4770      	bx	lr
    23de:	bf00      	nop
    23e0:	e000e100 	.word	0xe000e100

000023e4 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    23e4:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    23e6:	2b00      	cmp	r3, #0
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    23e8:	bfa8      	it	ge
    23ea:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
		prio += _IRQ_PRIO_OFFSET;
    23ee:	f101 0101 	add.w	r1, r1, #1
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    23f2:	bfb8      	it	lt
    23f4:	4b06      	ldrlt	r3, [pc, #24]	; (2410 <z_arm_irq_priority_set+0x2c>)
    23f6:	ea4f 1141 	mov.w	r1, r1, lsl #5
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    23fa:	bfac      	ite	ge
    23fc:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2400:	f000 000f 	andlt.w	r0, r0, #15
    2404:	b2c9      	uxtb	r1, r1
    2406:	bfb4      	ite	lt
    2408:	5419      	strblt	r1, [r3, r0]
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    240a:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
}
    240e:	4770      	bx	lr
    2410:	e000ed14 	.word	0xe000ed14

00002414 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    2414:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    2418:	9b00      	ldr	r3, [sp, #0]
    241a:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->pc &= 0xfffffffe;
    241e:	490a      	ldr	r1, [pc, #40]	; (2448 <arch_new_thread+0x34>)
	iframe->a3 = (uint32_t)p2;
    2420:	9b01      	ldr	r3, [sp, #4]
    2422:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    2426:	9b02      	ldr	r3, [sp, #8]
    2428:	f842 3c14 	str.w	r3, [r2, #-20]
	iframe->pc &= 0xfffffffe;
    242c:	f021 0101 	bic.w	r1, r1, #1

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    2430:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    2434:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->pc &= 0xfffffffe;
    2438:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    243c:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    243e:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    2440:	6502      	str	r2, [r0, #80]	; 0x50
	thread->arch.basepri = 0;
    2442:	6743      	str	r3, [r0, #116]	; 0x74
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    2444:	4770      	bx	lr
    2446:	bf00      	nop
    2448:	00005e33 	.word	0x00005e33

0000244c <arch_switch_to_main_thread>:
void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    244c:	4b07      	ldr	r3, [pc, #28]	; (246c <arch_switch_to_main_thread+0x20>)
    244e:	6098      	str	r0, [r3, #8]

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    2450:	4610      	mov	r0, r2
    2452:	f381 8809 	msr	PSP, r1
    2456:	2100      	movs	r1, #0
    2458:	b663      	cpsie	if
    245a:	f381 8811 	msr	BASEPRI, r1
    245e:	f3bf 8f6f 	isb	sy
    2462:	2200      	movs	r2, #0
    2464:	2300      	movs	r3, #0
    2466:	f003 fce4 	bl	5e32 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    246a:	bf00      	nop
    246c:	20000648 	.word	0x20000648

00002470 <z_arm_fatal_error>:
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
		esf->basic.pc);
}

void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    2470:	b573      	push	{r0, r1, r4, r5, r6, lr}
    2472:	4606      	mov	r6, r0

	if (esf != NULL) {
    2474:	460c      	mov	r4, r1
    2476:	b301      	cbz	r1, 24ba <z_arm_fatal_error+0x4a>
	return ((uint8_t *)data - (uint8_t *)__log_const_start)/
    2478:	4b13      	ldr	r3, [pc, #76]	; (24c8 <z_arm_fatal_error+0x58>)
    247a:	4d14      	ldr	r5, [pc, #80]	; (24cc <z_arm_fatal_error+0x5c>)
	LOG_ERR("r0/a1:  0x%08x  r1/a2:  0x%08x  r2/a3:  0x%08x",
    247c:	4814      	ldr	r0, [pc, #80]	; (24d0 <z_arm_fatal_error+0x60>)
    247e:	1aed      	subs	r5, r5, r3
    2480:	08ed      	lsrs	r5, r5, #3
    2482:	01ad      	lsls	r5, r5, #6
    2484:	f045 0501 	orr.w	r5, r5, #1
    2488:	f8ad 5000 	strh.w	r5, [sp]
    248c:	e9d1 2301 	ldrd	r2, r3, [r1, #4]
    2490:	6809      	ldr	r1, [r1, #0]
    2492:	f003 fd4c 	bl	5f2e <log_3>
	LOG_ERR("r3/a4:  0x%08x r12/ip:  0x%08x r14/lr:  0x%08x",
    2496:	f8ad 5000 	strh.w	r5, [sp]
    249a:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    249e:	68e1      	ldr	r1, [r4, #12]
    24a0:	480c      	ldr	r0, [pc, #48]	; (24d4 <z_arm_fatal_error+0x64>)
    24a2:	f003 fd44 	bl	5f2e <log_3>
	LOG_ERR(" xpsr:  0x%08x", esf->basic.xpsr);
    24a6:	69e1      	ldr	r1, [r4, #28]
    24a8:	480b      	ldr	r0, [pc, #44]	; (24d8 <z_arm_fatal_error+0x68>)
    24aa:	462a      	mov	r2, r5
    24ac:	f003 fd12 	bl	5ed4 <log_1>
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
    24b0:	69a1      	ldr	r1, [r4, #24]
    24b2:	480a      	ldr	r0, [pc, #40]	; (24dc <z_arm_fatal_error+0x6c>)
    24b4:	462a      	mov	r2, r5
    24b6:	f003 fd0d 	bl	5ed4 <log_1>
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    24ba:	4621      	mov	r1, r4
    24bc:	4630      	mov	r0, r6
}
    24be:	b002      	add	sp, #8
    24c0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	z_fatal_error(reason, esf);
    24c4:	f001 bb78 	b.w	3bb8 <z_fatal_error>
    24c8:	00007078 	.word	0x00007078
    24cc:	00007098 	.word	0x00007098
    24d0:	00007478 	.word	0x00007478
    24d4:	000074a7 	.word	0x000074a7
    24d8:	000074d6 	.word	0x000074d6
    24dc:	000074e5 	.word	0x000074e5

000024e0 <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    24e0:	4a0b      	ldr	r2, [pc, #44]	; (2510 <z_arm_prep_c+0x30>)
 * This routine prepares for the execution of and runs C code.
 *
 * @return N/A
 */
void z_arm_prep_c(void)
{
    24e2:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    24e4:	4b0b      	ldr	r3, [pc, #44]	; (2514 <z_arm_prep_c+0x34>)
    24e6:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    24ea:	609a      	str	r2, [r3, #8]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    24ec:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    24f0:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    24f4:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    24f8:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    24fc:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    2500:	f001 fbb8 	bl	3c74 <z_bss_zero>
	z_data_copy();
    2504:	f002 fb42 	bl	4b8c <z_data_copy>
#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    2508:	f000 fb0e 	bl	2b28 <z_arm_interrupt_init>
	z_cstart();
    250c:	f001 fbda 	bl	3cc4 <z_cstart>
    2510:	00000000 	.word	0x00000000
    2514:	e000ed00 	.word	0xe000ed00

00002518 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    2518:	490f      	ldr	r1, [pc, #60]	; (2558 <z_arm_pendsv+0x40>)
    ldr r2, [r1, #_kernel_offset_to_current]
    251a:	688a      	ldr	r2, [r1, #8]
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    251c:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    2520:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    2522:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    2526:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    252a:	2020      	movs	r0, #32
    msr BASEPRI, r0
    252c:	f380 8811 	msr	BASEPRI, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    2530:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    2534:	4f09      	ldr	r7, [pc, #36]	; (255c <z_arm_pendsv+0x44>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    2536:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    253a:	6a4a      	ldr	r2, [r1, #36]	; 0x24

    str r2, [r1, #_kernel_offset_to_current]
    253c:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    253e:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    2540:	6f50      	ldr	r0, [r2, #116]	; 0x74
    movs r3, #0
    2542:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    2544:	6753      	str	r3, [r2, #116]	; 0x74
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    2546:	f380 8811 	msr	BASEPRI, r0
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    254a:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    254e:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    2552:	f38c 8809 	msr	PSP, ip

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    2556:	4770      	bx	lr
    ldr r1, =_kernel
    2558:	20000648 	.word	0x20000648
    ldr v4, =_SCS_ICSR
    255c:	e000ed04 	.word	0xe000ed04

00002560 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #0x4    /* did we come from thread mode ? */
    2560:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    2564:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    2566:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    256a:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    256e:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    2570:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    2574:	2902      	cmp	r1, #2
    beq _oops
    2576:	d0ff      	beq.n	2578 <_oops>

00002578 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    2578:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    257a:	f003 ffc7 	bl	650c <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    257e:	bd01      	pop	{r0, pc}

00002580 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    2580:	4901      	ldr	r1, [pc, #4]	; (2588 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    2582:	2210      	movs	r2, #16
	str	r2, [r1]
    2584:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    2586:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    2588:	e000ed10 	.word	0xe000ed10

0000258c <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    258c:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    258e:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    2590:	f380 8811 	msr	BASEPRI, r0
	isb
    2594:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    2598:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    259c:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    259e:	b662      	cpsie	i
	isb
    25a0:	f3bf 8f6f 	isb	sy

	bx	lr
    25a4:	4770      	bx	lr
    25a6:	bf00      	nop

000025a8 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    25a8:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    25aa:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    25ac:	f381 8811 	msr	BASEPRI, r1

	wfe
    25b0:	bf20      	wfe

	msr	BASEPRI, r0
    25b2:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    25b6:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    25b8:	4770      	bx	lr
    25ba:	bf00      	nop

000025bc <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    25bc:	bf30      	wfi
    b z_SysNmiOnReset
    25be:	f7ff bffd 	b.w	25bc <z_SysNmiOnReset>
    25c2:	bf00      	nop

000025c4 <_isr_wrapper>:
 * @return N/A
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    25c4:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    25c6:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    25c8:	4a0b      	ldr	r2, [pc, #44]	; (25f8 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    25ca:	6a10      	ldr	r0, [r2, #32]
	cmp r0, #0
    25cc:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    25ce:	bf1e      	ittt	ne
	movne	r1, #0
    25d0:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    25d2:	6211      	strne	r1, [r2, #32]
		blne	z_pm_save_idle_exit
    25d4:	f004 f8f5 	blne	67c2 <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    25d8:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    25da:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    25de:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    25e2:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    25e6:	4905      	ldr	r1, [pc, #20]	; (25fc <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    25e8:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    25ea:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    25ec:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    25ee:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    25f2:	4903      	ldr	r1, [pc, #12]	; (2600 <_isr_wrapper+0x3c>)
	bx r1
    25f4:	4708      	bx	r1
    25f6:	0000      	.short	0x0000
	ldr r2, =_kernel
    25f8:	20000648 	.word	0x20000648
	ldr r1, =_sw_isr_table
    25fc:	00006ef0 	.word	0x00006ef0
	ldr r1, =z_arm_int_exit
    2600:	0000266d 	.word	0x0000266d

00002604 <__start>:
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    2604:	2000      	movs	r0, #0
    msr CONTROL, r0
    2606:	f380 8814 	msr	CONTROL, r0
    isb
    260a:	f3bf 8f6f 	isb	sy
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_platform_init
    260e:	f004 fbe9 	bl	6de4 <z_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    2612:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    2614:	490d      	ldr	r1, [pc, #52]	; (264c <__start+0x48>)
    str r0, [r1]
    2616:	6008      	str	r0, [r1, #0]
    dsb
    2618:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    261c:	480c      	ldr	r0, [pc, #48]	; (2650 <__start+0x4c>)
    msr msp, r0
    261e:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    2622:	f000 fa4f 	bl	2ac4 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    2626:	2020      	movs	r0, #32
    msr BASEPRI, r0
    2628:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    262c:	4809      	ldr	r0, [pc, #36]	; (2654 <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    262e:	f44f 6100 	mov.w	r1, #2048	; 0x800
    adds r0, r0, r1
    2632:	1840      	adds	r0, r0, r1
    msr PSP, r0
    2634:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    2638:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    263c:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    263e:	4308      	orrs	r0, r1
    msr CONTROL, r0
    2640:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    2644:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    2648:	f7ff ff4a 	bl	24e0 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    264c:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    2650:	200011d8 	.word	0x200011d8
    ldr r0, =z_interrupt_stacks
    2654:	20001318 	.word	0x20001318

00002658 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    2658:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    265c:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    2660:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    2662:	4672      	mov	r2, lr
	bl z_arm_fault
    2664:	f000 f942 	bl	28ec <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    2668:	bd01      	pop	{r0, pc}
    266a:	bf00      	nop

0000266c <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    266c:	4b04      	ldr	r3, [pc, #16]	; (2680 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    266e:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    2670:	6a58      	ldr	r0, [r3, #36]	; 0x24
	cmp r0, r1
    2672:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    2674:	d003      	beq.n	267e <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    2676:	4903      	ldr	r1, [pc, #12]	; (2684 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    2678:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    267c:	600a      	str	r2, [r1, #0]

0000267e <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    267e:	4770      	bx	lr
	ldr r3, =_kernel
    2680:	20000648 	.word	0x20000648
	ldr r1, =_SCS_ICSR
    2684:	e000ed04 	.word	0xe000ed04

00002688 <usage_fault.isra.0>:
 *
 * See z_arm_fault_dump() for example.
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t usage_fault(const z_arch_esf_t *esf)
    2688:	b570      	push	{r4, r5, r6, lr}
    268a:	4b23      	ldr	r3, [pc, #140]	; (2718 <usage_fault.isra.0+0x90>)
    268c:	4c23      	ldr	r4, [pc, #140]	; (271c <usage_fault.isra.0+0x94>)
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    268e:	4d24      	ldr	r5, [pc, #144]	; (2720 <usage_fault.isra.0+0x98>)
	PR_FAULT_INFO("***** USAGE FAULT *****");
    2690:	4824      	ldr	r0, [pc, #144]	; (2724 <usage_fault.isra.0+0x9c>)
    2692:	1ae4      	subs	r4, r4, r3
    2694:	08e4      	lsrs	r4, r4, #3
    2696:	01a4      	lsls	r4, r4, #6
    2698:	f044 0601 	orr.w	r6, r4, #1
    269c:	4631      	mov	r1, r6
    269e:	f003 fc0c 	bl	5eba <log_0>
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    26a2:	6aaa      	ldr	r2, [r5, #40]	; 0x28
    26a4:	0193      	lsls	r3, r2, #6
    26a6:	d503      	bpl.n	26b0 <usage_fault.isra.0+0x28>
		PR_FAULT_INFO("  Division by zero");
    26a8:	481f      	ldr	r0, [pc, #124]	; (2728 <usage_fault.isra.0+0xa0>)
    26aa:	4631      	mov	r1, r6
    26ac:	f003 fc05 	bl	5eba <log_0>
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    26b0:	6aab      	ldr	r3, [r5, #40]	; 0x28
    26b2:	01dd      	lsls	r5, r3, #7
    26b4:	d504      	bpl.n	26c0 <usage_fault.isra.0+0x38>
		PR_FAULT_INFO("  Unaligned memory access");
    26b6:	481d      	ldr	r0, [pc, #116]	; (272c <usage_fault.isra.0+0xa4>)
    26b8:	f044 0101 	orr.w	r1, r4, #1
    26bc:	f003 fbfd 	bl	5eba <log_0>
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    26c0:	4d17      	ldr	r5, [pc, #92]	; (2720 <usage_fault.isra.0+0x98>)
    26c2:	6aaa      	ldr	r2, [r5, #40]	; 0x28
    26c4:	0310      	lsls	r0, r2, #12
    26c6:	d504      	bpl.n	26d2 <usage_fault.isra.0+0x4a>
		PR_FAULT_INFO("  No coprocessor instructions");
    26c8:	4819      	ldr	r0, [pc, #100]	; (2730 <usage_fault.isra.0+0xa8>)
    26ca:	f044 0101 	orr.w	r1, r4, #1
    26ce:	f003 fbf4 	bl	5eba <log_0>
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    26d2:	6aab      	ldr	r3, [r5, #40]	; 0x28
    26d4:	0359      	lsls	r1, r3, #13
    26d6:	d504      	bpl.n	26e2 <usage_fault.isra.0+0x5a>
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
    26d8:	4816      	ldr	r0, [pc, #88]	; (2734 <usage_fault.isra.0+0xac>)
    26da:	f044 0101 	orr.w	r1, r4, #1
    26de:	f003 fbec 	bl	5eba <log_0>
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    26e2:	4d0f      	ldr	r5, [pc, #60]	; (2720 <usage_fault.isra.0+0x98>)
    26e4:	6aaa      	ldr	r2, [r5, #40]	; 0x28
    26e6:	0392      	lsls	r2, r2, #14
    26e8:	d504      	bpl.n	26f4 <usage_fault.isra.0+0x6c>
		PR_FAULT_INFO("  Illegal use of the EPSR");
    26ea:	4813      	ldr	r0, [pc, #76]	; (2738 <usage_fault.isra.0+0xb0>)
    26ec:	f044 0101 	orr.w	r1, r4, #1
    26f0:	f003 fbe3 	bl	5eba <log_0>
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    26f4:	6aab      	ldr	r3, [r5, #40]	; 0x28
    26f6:	03db      	lsls	r3, r3, #15
    26f8:	d504      	bpl.n	2704 <usage_fault.isra.0+0x7c>
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
    26fa:	4810      	ldr	r0, [pc, #64]	; (273c <usage_fault.isra.0+0xb4>)
    26fc:	f044 0101 	orr.w	r1, r4, #1
    2700:	f003 fbdb 	bl	5eba <log_0>
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    2704:	4a06      	ldr	r2, [pc, #24]	; (2720 <usage_fault.isra.0+0x98>)
    2706:	6a93      	ldr	r3, [r2, #40]	; 0x28
    2708:	ea6f 4303 	mvn.w	r3, r3, lsl #16
    270c:	ea6f 4313 	mvn.w	r3, r3, lsr #16
    2710:	6293      	str	r3, [r2, #40]	; 0x28

	return reason;
}
    2712:	2000      	movs	r0, #0
    2714:	bd70      	pop	{r4, r5, r6, pc}
    2716:	bf00      	nop
    2718:	00007078 	.word	0x00007078
    271c:	00007098 	.word	0x00007098
    2720:	e000ed00 	.word	0xe000ed00
    2724:	00007513 	.word	0x00007513
    2728:	0000752b 	.word	0x0000752b
    272c:	0000753e 	.word	0x0000753e
    2730:	00007558 	.word	0x00007558
    2734:	00007576 	.word	0x00007576
    2738:	0000759b 	.word	0x0000759b
    273c:	000075b5 	.word	0x000075b5

00002740 <mem_manage_fault.isra.0>:
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
    2740:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    2744:	4b28      	ldr	r3, [pc, #160]	; (27e8 <mem_manage_fault.isra.0+0xa8>)
    2746:	4c29      	ldr	r4, [pc, #164]	; (27ec <mem_manage_fault.isra.0+0xac>)
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    2748:	4d29      	ldr	r5, [pc, #164]	; (27f0 <mem_manage_fault.isra.0+0xb0>)
    274a:	1ae4      	subs	r4, r4, r3
    274c:	08e4      	lsrs	r4, r4, #3
	PR_FAULT_INFO("***** MPU FAULT *****");
    274e:	01a4      	lsls	r4, r4, #6
    2750:	f044 0801 	orr.w	r8, r4, #1
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
    2754:	4607      	mov	r7, r0
    2756:	460e      	mov	r6, r1
	PR_FAULT_INFO("***** MPU FAULT *****");
    2758:	4826      	ldr	r0, [pc, #152]	; (27f4 <mem_manage_fault.isra.0+0xb4>)
    275a:	4641      	mov	r1, r8
    275c:	f003 fbad 	bl	5eba <log_0>
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    2760:	6aaa      	ldr	r2, [r5, #40]	; 0x28
    2762:	06d0      	lsls	r0, r2, #27
    2764:	d503      	bpl.n	276e <mem_manage_fault.isra.0+0x2e>
		PR_FAULT_INFO("  Stacking error (context area might be"
    2766:	4824      	ldr	r0, [pc, #144]	; (27f8 <mem_manage_fault.isra.0+0xb8>)
    2768:	4641      	mov	r1, r8
    276a:	f003 fba6 	bl	5eba <log_0>
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    276e:	6aab      	ldr	r3, [r5, #40]	; 0x28
    2770:	0719      	lsls	r1, r3, #28
    2772:	d504      	bpl.n	277e <mem_manage_fault.isra.0+0x3e>
		PR_FAULT_INFO("  Unstacking error");
    2774:	4821      	ldr	r0, [pc, #132]	; (27fc <mem_manage_fault.isra.0+0xbc>)
    2776:	f044 0101 	orr.w	r1, r4, #1
    277a:	f003 fb9e 	bl	5eba <log_0>
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    277e:	4d1c      	ldr	r5, [pc, #112]	; (27f0 <mem_manage_fault.isra.0+0xb0>)
    2780:	6aab      	ldr	r3, [r5, #40]	; 0x28
    2782:	079a      	lsls	r2, r3, #30
    2784:	d512      	bpl.n	27ac <mem_manage_fault.isra.0+0x6c>
		PR_FAULT_INFO("  Data Access Violation");
    2786:	f044 0801 	orr.w	r8, r4, #1
    278a:	4641      	mov	r1, r8
    278c:	481c      	ldr	r0, [pc, #112]	; (2800 <mem_manage_fault.isra.0+0xc0>)
    278e:	f003 fb94 	bl	5eba <log_0>
		uint32_t temp = SCB->MMFAR;
    2792:	6b69      	ldr	r1, [r5, #52]	; 0x34
		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    2794:	6aab      	ldr	r3, [r5, #40]	; 0x28
    2796:	061b      	lsls	r3, r3, #24
    2798:	d508      	bpl.n	27ac <mem_manage_fault.isra.0+0x6c>
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
    279a:	481a      	ldr	r0, [pc, #104]	; (2804 <mem_manage_fault.isra.0+0xc4>)
    279c:	4642      	mov	r2, r8
    279e:	f003 fb99 	bl	5ed4 <log_1>
			if (from_hard_fault != 0) {
    27a2:	b11f      	cbz	r7, 27ac <mem_manage_fault.isra.0+0x6c>
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    27a4:	6aab      	ldr	r3, [r5, #40]	; 0x28
    27a6:	f023 0380 	bic.w	r3, r3, #128	; 0x80
    27aa:	62ab      	str	r3, [r5, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    27ac:	4d10      	ldr	r5, [pc, #64]	; (27f0 <mem_manage_fault.isra.0+0xb0>)
    27ae:	6aaa      	ldr	r2, [r5, #40]	; 0x28
    27b0:	07d0      	lsls	r0, r2, #31
    27b2:	d504      	bpl.n	27be <mem_manage_fault.isra.0+0x7e>
		PR_FAULT_INFO("  Instruction Access Violation");
    27b4:	4814      	ldr	r0, [pc, #80]	; (2808 <mem_manage_fault.isra.0+0xc8>)
    27b6:	f044 0101 	orr.w	r1, r4, #1
    27ba:	f003 fb7e 	bl	5eba <log_0>
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    27be:	6aab      	ldr	r3, [r5, #40]	; 0x28
    27c0:	0699      	lsls	r1, r3, #26
    27c2:	d504      	bpl.n	27ce <mem_manage_fault.isra.0+0x8e>
		PR_FAULT_INFO(
    27c4:	4811      	ldr	r0, [pc, #68]	; (280c <mem_manage_fault.isra.0+0xcc>)
    27c6:	f044 0101 	orr.w	r1, r4, #1
    27ca:	f003 fb76 	bl	5eba <log_0>
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    27ce:	4b08      	ldr	r3, [pc, #32]	; (27f0 <mem_manage_fault.isra.0+0xb0>)
    27d0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    27d2:	06d2      	lsls	r2, r2, #27
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    27d4:	bf58      	it	pl
    27d6:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    27d8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    27da:	2000      	movs	r0, #0
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    27dc:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    27e0:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    27e2:	7030      	strb	r0, [r6, #0]
}
    27e4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    27e8:	00007078 	.word	0x00007078
    27ec:	00007098 	.word	0x00007098
    27f0:	e000ed00 	.word	0xe000ed00
    27f4:	000075e0 	.word	0x000075e0
    27f8:	000075f6 	.word	0x000075f6
    27fc:	00007629 	.word	0x00007629
    2800:	0000763c 	.word	0x0000763c
    2804:	00007654 	.word	0x00007654
    2808:	0000766a 	.word	0x0000766a
    280c:	00007689 	.word	0x00007689

00002810 <bus_fault.isra.0>:
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    2810:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    2814:	4b2a      	ldr	r3, [pc, #168]	; (28c0 <bus_fault.isra.0+0xb0>)
    2816:	4c2b      	ldr	r4, [pc, #172]	; (28c4 <bus_fault.isra.0+0xb4>)
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    2818:	4d2b      	ldr	r5, [pc, #172]	; (28c8 <bus_fault.isra.0+0xb8>)
    281a:	1ae4      	subs	r4, r4, r3
    281c:	08e4      	lsrs	r4, r4, #3
	PR_FAULT_INFO("***** BUS FAULT *****");
    281e:	01a4      	lsls	r4, r4, #6
    2820:	f044 0801 	orr.w	r8, r4, #1
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    2824:	4607      	mov	r7, r0
    2826:	460e      	mov	r6, r1
	PR_FAULT_INFO("***** BUS FAULT *****");
    2828:	4828      	ldr	r0, [pc, #160]	; (28cc <bus_fault.isra.0+0xbc>)
    282a:	4641      	mov	r1, r8
    282c:	f003 fb45 	bl	5eba <log_0>
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    2830:	6aaa      	ldr	r2, [r5, #40]	; 0x28
    2832:	04d1      	lsls	r1, r2, #19
    2834:	d503      	bpl.n	283e <bus_fault.isra.0+0x2e>
		PR_FAULT_INFO("  Stacking error");
    2836:	4826      	ldr	r0, [pc, #152]	; (28d0 <bus_fault.isra.0+0xc0>)
    2838:	4641      	mov	r1, r8
    283a:	f003 fb3e 	bl	5eba <log_0>
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    283e:	6aab      	ldr	r3, [r5, #40]	; 0x28
    2840:	051a      	lsls	r2, r3, #20
    2842:	d504      	bpl.n	284e <bus_fault.isra.0+0x3e>
		PR_FAULT_INFO("  Unstacking error");
    2844:	4823      	ldr	r0, [pc, #140]	; (28d4 <bus_fault.isra.0+0xc4>)
    2846:	f044 0101 	orr.w	r1, r4, #1
    284a:	f003 fb36 	bl	5eba <log_0>
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    284e:	4d1e      	ldr	r5, [pc, #120]	; (28c8 <bus_fault.isra.0+0xb8>)
    2850:	6aab      	ldr	r3, [r5, #40]	; 0x28
    2852:	059b      	lsls	r3, r3, #22
    2854:	d512      	bpl.n	287c <bus_fault.isra.0+0x6c>
		PR_FAULT_INFO("  Precise data bus error");
    2856:	f044 0801 	orr.w	r8, r4, #1
    285a:	481f      	ldr	r0, [pc, #124]	; (28d8 <bus_fault.isra.0+0xc8>)
    285c:	4641      	mov	r1, r8
    285e:	f003 fb2c 	bl	5eba <log_0>
		STORE_xFAR(bfar, SCB->BFAR);
    2862:	6ba9      	ldr	r1, [r5, #56]	; 0x38
		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    2864:	6aab      	ldr	r3, [r5, #40]	; 0x28
    2866:	0418      	lsls	r0, r3, #16
    2868:	d508      	bpl.n	287c <bus_fault.isra.0+0x6c>
			PR_EXC("  BFAR Address: 0x%x", bfar);
    286a:	481c      	ldr	r0, [pc, #112]	; (28dc <bus_fault.isra.0+0xcc>)
    286c:	4642      	mov	r2, r8
    286e:	f003 fb31 	bl	5ed4 <log_1>
			if (from_hard_fault != 0) {
    2872:	b11f      	cbz	r7, 287c <bus_fault.isra.0+0x6c>
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    2874:	6aab      	ldr	r3, [r5, #40]	; 0x28
    2876:	f423 4300 	bic.w	r3, r3, #32768	; 0x8000
    287a:	62ab      	str	r3, [r5, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    287c:	4d12      	ldr	r5, [pc, #72]	; (28c8 <bus_fault.isra.0+0xb8>)
    287e:	6aab      	ldr	r3, [r5, #40]	; 0x28
    2880:	0559      	lsls	r1, r3, #21
    2882:	d504      	bpl.n	288e <bus_fault.isra.0+0x7e>
		PR_FAULT_INFO("  Imprecise data bus error");
    2884:	4816      	ldr	r0, [pc, #88]	; (28e0 <bus_fault.isra.0+0xd0>)
    2886:	f044 0101 	orr.w	r1, r4, #1
    288a:	f003 fb16 	bl	5eba <log_0>
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    288e:	6aab      	ldr	r3, [r5, #40]	; 0x28
    2890:	05da      	lsls	r2, r3, #23
    2892:	d50d      	bpl.n	28b0 <bus_fault.isra.0+0xa0>
		PR_FAULT_INFO("  Instruction bus error");
    2894:	4813      	ldr	r0, [pc, #76]	; (28e4 <bus_fault.isra.0+0xd4>)
    2896:	f044 0101 	orr.w	r1, r4, #1
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    289a:	f003 fb0e 	bl	5eba <log_0>
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    289e:	4a0a      	ldr	r2, [pc, #40]	; (28c8 <bus_fault.isra.0+0xb8>)
    28a0:	6a93      	ldr	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    28a2:	2000      	movs	r0, #0
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    28a4:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    28a8:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    28aa:	7030      	strb	r0, [r6, #0]
}
    28ac:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    28b0:	6aab      	ldr	r3, [r5, #40]	; 0x28
    28b2:	049b      	lsls	r3, r3, #18
    28b4:	d5f3      	bpl.n	289e <bus_fault.isra.0+0x8e>
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    28b6:	480c      	ldr	r0, [pc, #48]	; (28e8 <bus_fault.isra.0+0xd8>)
    28b8:	f044 0101 	orr.w	r1, r4, #1
    28bc:	e7ed      	b.n	289a <bus_fault.isra.0+0x8a>
    28be:	bf00      	nop
    28c0:	00007078 	.word	0x00007078
    28c4:	00007098 	.word	0x00007098
    28c8:	e000ed00 	.word	0xe000ed00
    28cc:	000076b8 	.word	0x000076b8
    28d0:	000076ce 	.word	0x000076ce
    28d4:	00007629 	.word	0x00007629
    28d8:	000076df 	.word	0x000076df
    28dc:	000076f8 	.word	0x000076f8
    28e0:	0000770d 	.word	0x0000770d
    28e4:	00007728 	.word	0x00007728
    28e8:	00007689 	.word	0x00007689

000028ec <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    28ec:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    28f0:	460d      	mov	r5, r1
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    28f2:	495a      	ldr	r1, [pc, #360]	; (2a5c <z_arm_fault+0x170>)
    28f4:	684f      	ldr	r7, [r1, #4]
{
    28f6:	b08a      	sub	sp, #40	; 0x28
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    28f8:	f3c7 0408 	ubfx	r4, r7, #0, #9
    28fc:	2600      	movs	r6, #0
    28fe:	f386 8811 	msr	BASEPRI, r6
    2902:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    2906:	f002 417f 	and.w	r1, r2, #4278190080	; 0xff000000
    290a:	f1b1 4f7f 	cmp.w	r1, #4278190080	; 0xff000000
    290e:	d10d      	bne.n	292c <z_arm_fault+0x40>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    2910:	f002 010c 	and.w	r1, r2, #12
    2914:	2908      	cmp	r1, #8
    2916:	d10b      	bne.n	2930 <z_arm_fault+0x44>
    2918:	4951      	ldr	r1, [pc, #324]	; (2a60 <z_arm_fault+0x174>)
    291a:	4b52      	ldr	r3, [pc, #328]	; (2a64 <z_arm_fault+0x178>)
		PR_EXC("SPSEL in thread mode does not indicate PSP");
    291c:	4852      	ldr	r0, [pc, #328]	; (2a68 <z_arm_fault+0x17c>)
    291e:	1ac9      	subs	r1, r1, r3
    2920:	08c9      	lsrs	r1, r1, #3
    2922:	0189      	lsls	r1, r1, #6
    2924:	f041 0101 	orr.w	r1, r1, #1
    2928:	f003 fac7 	bl	5eba <log_0>
		return NULL;
    292c:	4635      	mov	r5, r6
    292e:	e003      	b.n	2938 <z_arm_fault+0x4c>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    2930:	0712      	lsls	r2, r2, #28
    2932:	d401      	bmi.n	2938 <z_arm_fault+0x4c>
			ptr_esf = (z_arch_esf_t *)msp;
    2934:	4605      	mov	r5, r0
			*nested_exc = true;
    2936:	2601      	movs	r6, #1
	*recoverable = false;
    2938:	2300      	movs	r3, #0
    293a:	f88d 3007 	strb.w	r3, [sp, #7]
	switch (fault) {
    293e:	1ee3      	subs	r3, r4, #3
    2940:	2b09      	cmp	r3, #9
    2942:	d871      	bhi.n	2a28 <z_arm_fault+0x13c>
    2944:	e8df f003 	tbb	[pc, r3]
    2948:	3c635f05 	.word	0x3c635f05
    294c:	70707070 	.word	0x70707070
    2950:	6770      	.short	0x6770
    2952:	4b44      	ldr	r3, [pc, #272]	; (2a64 <z_arm_fault+0x178>)
    2954:	4f42      	ldr	r7, [pc, #264]	; (2a60 <z_arm_fault+0x174>)
	PR_FAULT_INFO("***** HARD FAULT *****");
    2956:	4845      	ldr	r0, [pc, #276]	; (2a6c <z_arm_fault+0x180>)
    2958:	1aff      	subs	r7, r7, r3
    295a:	08ff      	lsrs	r7, r7, #3
    295c:	01bf      	lsls	r7, r7, #6
    295e:	f047 0701 	orr.w	r7, r7, #1
    2962:	4639      	mov	r1, r7
    2964:	f003 faa9 	bl	5eba <log_0>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    2968:	4b3c      	ldr	r3, [pc, #240]	; (2a5c <z_arm_fault+0x170>)
    296a:	6adc      	ldr	r4, [r3, #44]	; 0x2c
	*recoverable = false;
    296c:	f04f 0800 	mov.w	r8, #0
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    2970:	f014 0402 	ands.w	r4, r4, #2
	*recoverable = false;
    2974:	f88d 8007 	strb.w	r8, [sp, #7]
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    2978:	d005      	beq.n	2986 <z_arm_fault+0x9a>
		PR_EXC("  Bus fault on vector table read");
    297a:	483d      	ldr	r0, [pc, #244]	; (2a70 <z_arm_fault+0x184>)
    297c:	4639      	mov	r1, r7
	PR_FAULT_INFO(
    297e:	f003 fa9c 	bl	5eba <log_0>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    2982:	2400      	movs	r4, #0
}
    2984:	e01f      	b.n	29c6 <z_arm_fault+0xda>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    2986:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    2988:	005b      	lsls	r3, r3, #1
    298a:	d51c      	bpl.n	29c6 <z_arm_fault+0xda>
		PR_EXC("  Fault escalation (see below)");
    298c:	4839      	ldr	r0, [pc, #228]	; (2a74 <z_arm_fault+0x188>)
    298e:	4639      	mov	r1, r7
    2990:	f003 fa93 	bl	5eba <log_0>
		if (SCB_MMFSR != 0) {
    2994:	4b38      	ldr	r3, [pc, #224]	; (2a78 <z_arm_fault+0x18c>)
    2996:	781b      	ldrb	r3, [r3, #0]
    2998:	b12b      	cbz	r3, 29a6 <z_arm_fault+0xba>
			reason = mem_manage_fault(esf, 1, recoverable);
    299a:	f10d 0107 	add.w	r1, sp, #7
    299e:	2001      	movs	r0, #1
		reason = mem_manage_fault(esf, 0, recoverable);
    29a0:	f7ff fece 	bl	2740 <mem_manage_fault.isra.0>
    29a4:	e00e      	b.n	29c4 <z_arm_fault+0xd8>
		} else if (SCB_BFSR != 0) {
    29a6:	4b35      	ldr	r3, [pc, #212]	; (2a7c <z_arm_fault+0x190>)
    29a8:	781b      	ldrb	r3, [r3, #0]
    29aa:	b12b      	cbz	r3, 29b8 <z_arm_fault+0xcc>
			reason = bus_fault(esf, 1, recoverable);
    29ac:	f10d 0107 	add.w	r1, sp, #7
    29b0:	2001      	movs	r0, #1
		reason = bus_fault(esf, 0, recoverable);
    29b2:	f7ff ff2d 	bl	2810 <bus_fault.isra.0>
    29b6:	e005      	b.n	29c4 <z_arm_fault+0xd8>
		} else if (SCB_UFSR != 0) {
    29b8:	4b31      	ldr	r3, [pc, #196]	; (2a80 <z_arm_fault+0x194>)
    29ba:	881b      	ldrh	r3, [r3, #0]
    29bc:	b29b      	uxth	r3, r3
    29be:	b113      	cbz	r3, 29c6 <z_arm_fault+0xda>
			reason = usage_fault(esf);
    29c0:	f7ff fe62 	bl	2688 <usage_fault.isra.0>
    29c4:	4604      	mov	r4, r0
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    29c6:	f89d 3007 	ldrb.w	r3, [sp, #7]
    29ca:	b9cb      	cbnz	r3, 2a00 <z_arm_fault+0x114>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    29cc:	462b      	mov	r3, r5
    29ce:	f103 0720 	add.w	r7, r3, #32
    29d2:	ad02      	add	r5, sp, #8
    29d4:	6818      	ldr	r0, [r3, #0]
    29d6:	6859      	ldr	r1, [r3, #4]
    29d8:	462a      	mov	r2, r5
    29da:	c203      	stmia	r2!, {r0, r1}
    29dc:	3308      	adds	r3, #8
    29de:	42bb      	cmp	r3, r7
    29e0:	4615      	mov	r5, r2
    29e2:	d1f7      	bne.n	29d4 <z_arm_fault+0xe8>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    29e4:	9b09      	ldr	r3, [sp, #36]	; 0x24
    29e6:	b39e      	cbz	r6, 2a50 <z_arm_fault+0x164>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    29e8:	f3c3 0208 	ubfx	r2, r3, #0, #9
    29ec:	b922      	cbnz	r2, 29f8 <z_arm_fault+0x10c>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    29ee:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    29f2:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    29f6:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    29f8:	a902      	add	r1, sp, #8
    29fa:	4620      	mov	r0, r4
    29fc:	f7ff fd38 	bl	2470 <z_arm_fatal_error>
}
    2a00:	b00a      	add	sp, #40	; 0x28
    2a02:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		reason = mem_manage_fault(esf, 0, recoverable);
    2a06:	f10d 0107 	add.w	r1, sp, #7
    2a0a:	2000      	movs	r0, #0
    2a0c:	e7c8      	b.n	29a0 <z_arm_fault+0xb4>
		reason = bus_fault(esf, 0, recoverable);
    2a0e:	f10d 0107 	add.w	r1, sp, #7
    2a12:	2000      	movs	r0, #0
    2a14:	e7cd      	b.n	29b2 <z_arm_fault+0xc6>
    2a16:	4912      	ldr	r1, [pc, #72]	; (2a60 <z_arm_fault+0x174>)
    2a18:	4b12      	ldr	r3, [pc, #72]	; (2a64 <z_arm_fault+0x178>)
	PR_FAULT_INFO(
    2a1a:	481a      	ldr	r0, [pc, #104]	; (2a84 <z_arm_fault+0x198>)
    2a1c:	1ac9      	subs	r1, r1, r3
    2a1e:	08c9      	lsrs	r1, r1, #3
    2a20:	0189      	lsls	r1, r1, #6
    2a22:	f041 0101 	orr.w	r1, r1, #1
    2a26:	e7aa      	b.n	297e <z_arm_fault+0x92>
    2a28:	4a0e      	ldr	r2, [pc, #56]	; (2a64 <z_arm_fault+0x178>)
    2a2a:	4b0d      	ldr	r3, [pc, #52]	; (2a60 <z_arm_fault+0x174>)
	PR_FAULT_INFO("***** %s %d) *****",
    2a2c:	4816      	ldr	r0, [pc, #88]	; (2a88 <z_arm_fault+0x19c>)
    2a2e:	4917      	ldr	r1, [pc, #92]	; (2a8c <z_arm_fault+0x1a0>)
    2a30:	1a9b      	subs	r3, r3, r2
    2a32:	08db      	lsrs	r3, r3, #3
    2a34:	f417 7ff8 	tst.w	r7, #496	; 0x1f0
    2a38:	ea4f 1383 	mov.w	r3, r3, lsl #6
    2a3c:	bf18      	it	ne
    2a3e:	4601      	movne	r1, r0
    2a40:	f043 0301 	orr.w	r3, r3, #1
    2a44:	4812      	ldr	r0, [pc, #72]	; (2a90 <z_arm_fault+0x1a4>)
    2a46:	f1a4 0210 	sub.w	r2, r4, #16
    2a4a:	f003 fa57 	bl	5efc <log_2>
    2a4e:	e798      	b.n	2982 <z_arm_fault+0x96>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    2a50:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    2a54:	f023 0301 	bic.w	r3, r3, #1
    2a58:	e7cd      	b.n	29f6 <z_arm_fault+0x10a>
    2a5a:	bf00      	nop
    2a5c:	e000ed00 	.word	0xe000ed00
    2a60:	00007098 	.word	0x00007098
    2a64:	00007078 	.word	0x00007078
    2a68:	00007740 	.word	0x00007740
    2a6c:	0000776b 	.word	0x0000776b
    2a70:	00007782 	.word	0x00007782
    2a74:	000077a3 	.word	0x000077a3
    2a78:	e000ed28 	.word	0xe000ed28
    2a7c:	e000ed29 	.word	0xe000ed29
    2a80:	e000ed2a 	.word	0xe000ed2a
    2a84:	000077c2 	.word	0x000077c2
    2a88:	000077fb 	.word	0x000077fb
    2a8c:	000077e6 	.word	0x000077e6
    2a90:	00007814 	.word	0x00007814

00002a94 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    2a94:	4a02      	ldr	r2, [pc, #8]	; (2aa0 <z_arm_fault_init+0xc>)
    2a96:	6953      	ldr	r3, [r2, #20]
    2a98:	f043 0310 	orr.w	r3, r3, #16
    2a9c:	6153      	str	r3, [r2, #20]
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
}
    2a9e:	4770      	bx	lr
    2aa0:	e000ed00 	.word	0xe000ed00

00002aa4 <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    2aa4:	4a06      	ldr	r2, [pc, #24]	; (2ac0 <z_arm_clear_arm_mpu_config+0x1c>)
    2aa6:	6811      	ldr	r1, [r2, #0]

	for (i = 0; i < num_regions; i++) {
    2aa8:	2300      	movs	r3, #0
	int num_regions =
    2aaa:	f3c1 2107 	ubfx	r1, r1, #8, #8
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
  MPU->RASR = 0U;
    2aae:	4618      	mov	r0, r3
	for (i = 0; i < num_regions; i++) {
    2ab0:	428b      	cmp	r3, r1
    2ab2:	d100      	bne.n	2ab6 <z_arm_clear_arm_mpu_config+0x12>
		ARM_MPU_ClrRegion(i);
	}
}
    2ab4:	4770      	bx	lr
  MPU->RNR = rnr;
    2ab6:	6093      	str	r3, [r2, #8]
  MPU->RASR = 0U;
    2ab8:	6110      	str	r0, [r2, #16]
	for (i = 0; i < num_regions; i++) {
    2aba:	3301      	adds	r3, #1
    2abc:	e7f8      	b.n	2ab0 <z_arm_clear_arm_mpu_config+0xc>
    2abe:	bf00      	nop
    2ac0:	e000ed90 	.word	0xe000ed90

00002ac4 <z_arm_init_arch_hw_at_boot>:
 * components and core registers.
 *
 * @return N/A
 */
void z_arm_init_arch_hw_at_boot(void)
{
    2ac4:	b508      	push	{r3, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    2ac6:	b672      	cpsid	i
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    2ac8:	2300      	movs	r3, #0
    2aca:	f383 8813 	msr	FAULTMASK, r3

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    2ace:	f7ff ffe9 	bl	2aa4 <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    2ad2:	4b14      	ldr	r3, [pc, #80]	; (2b24 <z_arm_init_arch_hw_at_boot+0x60>)
    2ad4:	f04f 32ff 	mov.w	r2, #4294967295
    2ad8:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
    2adc:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
    2ae0:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    2ae4:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
    2ae8:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
    2aec:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
    2af0:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    2af4:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    2af8:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    2afc:	f8c3 2184 	str.w	r2, [r3, #388]	; 0x184
    2b00:	f8c3 2188 	str.w	r2, [r3, #392]	; 0x188
    2b04:	f8c3 218c 	str.w	r2, [r3, #396]	; 0x18c
    2b08:	f8c3 2190 	str.w	r2, [r3, #400]	; 0x190
    2b0c:	f8c3 2194 	str.w	r2, [r3, #404]	; 0x194
    2b10:	f8c3 2198 	str.w	r2, [r3, #408]	; 0x198
    2b14:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c
  __ASM volatile ("cpsie i" : : : "memory");
    2b18:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    2b1a:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2b1e:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    2b22:	bd08      	pop	{r3, pc}
    2b24:	e000e100 	.word	0xe000e100

00002b28 <z_arm_interrupt_init>:
    2b28:	4804      	ldr	r0, [pc, #16]	; (2b3c <z_arm_interrupt_init+0x14>)
 * @return N/A
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    2b2a:	2300      	movs	r3, #0
    2b2c:	2120      	movs	r1, #32
    2b2e:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    2b30:	3301      	adds	r3, #1
    2b32:	2b30      	cmp	r3, #48	; 0x30
    2b34:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    2b38:	d1f9      	bne.n	2b2e <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    2b3a:	4770      	bx	lr
    2b3c:	e000e100 	.word	0xe000e100

00002b40 <z_impl_k_thread_abort>:
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
	if (_current == thread) {
    2b40:	4b06      	ldr	r3, [pc, #24]	; (2b5c <z_impl_k_thread_abort+0x1c>)
    2b42:	689b      	ldr	r3, [r3, #8]
    2b44:	4283      	cmp	r3, r0
    2b46:	d107      	bne.n	2b58 <z_impl_k_thread_abort+0x18>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    2b48:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    2b4c:	b123      	cbz	r3, 2b58 <z_impl_k_thread_abort+0x18>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    2b4e:	4a04      	ldr	r2, [pc, #16]	; (2b60 <z_impl_k_thread_abort+0x20>)
    2b50:	6853      	ldr	r3, [r2, #4]
    2b52:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    2b56:	6053      	str	r3, [r2, #4]
		}
	}

	z_thread_abort(thread);
    2b58:	f001 bfb4 	b.w	4ac4 <z_thread_abort>
    2b5c:	20000648 	.word	0x20000648
    2b60:	e000ed00 	.word	0xe000ed00

00002b64 <z_arm_configure_static_mpu_regions>:
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    2b64:	4b02      	ldr	r3, [pc, #8]	; (2b70 <z_arm_configure_static_mpu_regions+0xc>)
    2b66:	4a03      	ldr	r2, [pc, #12]	; (2b74 <z_arm_configure_static_mpu_regions+0x10>)
    2b68:	4803      	ldr	r0, [pc, #12]	; (2b78 <z_arm_configure_static_mpu_regions+0x14>)
    2b6a:	2101      	movs	r1, #1
    2b6c:	f000 b874 	b.w	2c58 <arm_core_mpu_configure_static_mpu_regions>
    2b70:	20020000 	.word	0x20020000
    2b74:	20000000 	.word	0x20000000
    2b78:	000071d0 	.word	0x000071d0

00002b7c <mpu_configure_regions>:
 * sanity check of the memory regions to be programmed.
 */
static int mpu_configure_regions(const struct z_arm_mpu_partition
	regions[], uint8_t regions_num, uint8_t start_reg_index,
	bool do_sanity_check)
{
    2b7c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 */
static void region_init(const uint32_t index,
	const struct arm_mpu_region *region_conf)
{
	/* Select the region you want to access */
	MPU->RNR = index;
    2b7e:	4f28      	ldr	r7, [pc, #160]	; (2c20 <mpu_configure_regions+0xa4>)
    2b80:	460e      	mov	r6, r1
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    2b82:	2100      	movs	r1, #0
    2b84:	42b1      	cmp	r1, r6
    2b86:	da14      	bge.n	2bb2 <mpu_configure_regions+0x36>
		if (regions[i].size == 0U) {
    2b88:	6844      	ldr	r4, [r0, #4]
    2b8a:	2c00      	cmp	r4, #0
    2b8c:	d045      	beq.n	2c1a <mpu_configure_regions+0x9e>
			continue;
		}
		/* Non-empty region. */

		if (do_sanity_check &&
    2b8e:	b1c3      	cbz	r3, 2bc2 <mpu_configure_regions+0x46>
	 * and greater or equal to the minimum
	 * MPU region size. Start address of the
	 * partition must align with size.
	 */
	int partition_is_valid =
		((part->size & (part->size - 1U)) == 0U)
    2b90:	f104 3cff 	add.w	ip, r4, #4294967295
		&&
		(part->size >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
		&&
    2b94:	ea14 0f0c 	tst.w	r4, ip
    2b98:	d00d      	beq.n	2bb6 <mpu_configure_regions+0x3a>
    2b9a:	4a22      	ldr	r2, [pc, #136]	; (2c24 <mpu_configure_regions+0xa8>)
    2b9c:	4b22      	ldr	r3, [pc, #136]	; (2c28 <mpu_configure_regions+0xac>)
				(!mpu_partition_is_valid(&regions[i]))) {
			LOG_ERR("Partition %u: sanity check failed.", i);
    2b9e:	4823      	ldr	r0, [pc, #140]	; (2c2c <mpu_configure_regions+0xb0>)
    2ba0:	1ad2      	subs	r2, r2, r3
    2ba2:	08d2      	lsrs	r2, r2, #3
    2ba4:	0192      	lsls	r2, r2, #6
    2ba6:	f042 0201 	orr.w	r2, r2, #1
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    2baa:	f003 f993 	bl	5ed4 <log_1>
			return -EINVAL;
		}

		reg_index = mpu_configure_region(reg_index, &regions[i]);
    2bae:	f06f 0215 	mvn.w	r2, #21
		/* Increment number of programmed MPU indices. */
		reg_index++;
	}

	return reg_index;
}
    2bb2:	4610      	mov	r0, r2
    2bb4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		&&
    2bb6:	2c1f      	cmp	r4, #31
    2bb8:	d9ef      	bls.n	2b9a <mpu_configure_regions+0x1e>
		((part->start & (part->size - 1U)) == 0U);
    2bba:	6805      	ldr	r5, [r0, #0]
		&&
    2bbc:	ea1c 0f05 	tst.w	ip, r5
    2bc0:	d1eb      	bne.n	2b9a <mpu_configure_regions+0x1e>
 * to that power-of-two value.
 */
static inline uint32_t size_to_mpu_rasr_size(uint32_t size)
{
	/* The minimal supported region size is 32 bytes */
	if (size <= 32U) {
    2bc2:	2c20      	cmp	r4, #32
		reg_index = mpu_configure_region(reg_index, &regions[i]);
    2bc4:	b2d5      	uxtb	r5, r2
	get_region_attr_from_mpu_partition_info(&region_conf.attr,
    2bc6:	f8d0 c008 	ldr.w	ip, [r0, #8]
	region_conf.base = new_region->start;
    2bca:	6802      	ldr	r2, [r0, #0]
    2bcc:	d916      	bls.n	2bfc <mpu_configure_regions+0x80>
	/*
	 * A size value greater than 2^31 could not be handled by
	 * round_up_to_next_power_of_two() properly. We handle
	 * it separately here.
	 */
	if (size > (1UL << 31)) {
    2bce:	f1b4 4f00 	cmp.w	r4, #2147483648	; 0x80000000
    2bd2:	d815      	bhi.n	2c00 <mpu_configure_regions+0x84>
		return REGION_4G;
	}

	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    2bd4:	3c01      	subs	r4, #1
    2bd6:	fab4 f484 	clz	r4, r4
    2bda:	f1c4 041f 	rsb	r4, r4, #31
    2bde:	0064      	lsls	r4, r4, #1
	if (index > (get_num_regions() - 1U)) {
    2be0:	2d07      	cmp	r5, #7
	/* in ARMv7-M MPU the base address is not required
	 * to determine region attributes
	 */
	(void) base;

	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    2be2:	ea4c 0404 	orr.w	r4, ip, r4
    2be6:	d90d      	bls.n	2c04 <mpu_configure_regions+0x88>
    2be8:	4a0e      	ldr	r2, [pc, #56]	; (2c24 <mpu_configure_regions+0xa8>)
    2bea:	4b0f      	ldr	r3, [pc, #60]	; (2c28 <mpu_configure_regions+0xac>)
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    2bec:	4810      	ldr	r0, [pc, #64]	; (2c30 <mpu_configure_regions+0xb4>)
    2bee:	1ad2      	subs	r2, r2, r3
    2bf0:	08d2      	lsrs	r2, r2, #3
    2bf2:	0192      	lsls	r2, r2, #6
    2bf4:	f042 0201 	orr.w	r2, r2, #1
    2bf8:	4629      	mov	r1, r5
    2bfa:	e7d6      	b.n	2baa <mpu_configure_regions+0x2e>
		return REGION_32B;
    2bfc:	2408      	movs	r4, #8
    2bfe:	e7ef      	b.n	2be0 <mpu_configure_regions+0x64>
		return REGION_4G;
    2c00:	243e      	movs	r4, #62	; 0x3e
    2c02:	e7ed      	b.n	2be0 <mpu_configure_regions+0x64>
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2c04:	f022 021f 	bic.w	r2, r2, #31
				| MPU_RBAR_VALID_Msk | index;
    2c08:	432a      	orrs	r2, r5
    2c0a:	f042 0210 	orr.w	r2, r2, #16
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2c0e:	f044 0401 	orr.w	r4, r4, #1
	MPU->RNR = index;
    2c12:	60bd      	str	r5, [r7, #8]
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2c14:	60fa      	str	r2, [r7, #12]
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2c16:	613c      	str	r4, [r7, #16]
		reg_index++;
    2c18:	1c6a      	adds	r2, r5, #1
	for (i = 0; i < regions_num; i++) {
    2c1a:	3101      	adds	r1, #1
    2c1c:	300c      	adds	r0, #12
    2c1e:	e7b1      	b.n	2b84 <mpu_configure_regions+0x8>
    2c20:	e000ed90 	.word	0xe000ed90
    2c24:	00007090 	.word	0x00007090
    2c28:	00007078 	.word	0x00007078
    2c2c:	0000782b 	.word	0x0000782b
    2c30:	0000784e 	.word	0x0000784e

00002c34 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    2c34:	4b03      	ldr	r3, [pc, #12]	; (2c44 <arm_core_mpu_enable+0x10>)
    2c36:	2205      	movs	r2, #5
    2c38:	605a      	str	r2, [r3, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    2c3a:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2c3e:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    2c42:	4770      	bx	lr
    2c44:	e000ed90 	.word	0xe000ed90

00002c48 <arm_core_mpu_disable>:
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
__STATIC_FORCEINLINE void __DMB(void)
{
  __ASM volatile ("dmb 0xF":::"memory");
    2c48:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    2c4c:	4b01      	ldr	r3, [pc, #4]	; (2c54 <arm_core_mpu_disable+0xc>)
    2c4e:	2200      	movs	r2, #0
    2c50:	605a      	str	r2, [r3, #4]
}
    2c52:	4770      	bx	lr
    2c54:	e000ed90 	.word	0xe000ed90

00002c58 <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    2c58:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    2c5a:	4c03      	ldr	r4, [pc, #12]	; (2c68 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    2c5c:	2301      	movs	r3, #1
    2c5e:	7822      	ldrb	r2, [r4, #0]
    2c60:	f7ff ff8c 	bl	2b7c <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    2c64:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    2c66:	bd10      	pop	{r4, pc}
    2c68:	200006b0 	.word	0x200006b0

00002c6c <z_arm_mpu_init>:
 */
int z_arm_mpu_init(void)
{
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    2c6c:	4913      	ldr	r1, [pc, #76]	; (2cbc <z_arm_mpu_init+0x50>)
    2c6e:	6808      	ldr	r0, [r1, #0]
    2c70:	2808      	cmp	r0, #8
{
    2c72:	b510      	push	{r4, lr}
	if (mpu_config.num_regions > get_num_regions()) {
    2c74:	d81e      	bhi.n	2cb4 <z_arm_mpu_init+0x48>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    2c76:	f7ff ffe7 	bl	2c48 <arm_core_mpu_disable>
	MPU->RNR = index;
    2c7a:	4c11      	ldr	r4, [pc, #68]	; (2cc0 <z_arm_mpu_init+0x54>)
    2c7c:	6849      	ldr	r1, [r1, #4]

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2c7e:	2200      	movs	r2, #0
    2c80:	4290      	cmp	r0, r2
    2c82:	f101 010c 	add.w	r1, r1, #12
    2c86:	d105      	bne.n	2c94 <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    2c88:	4b0e      	ldr	r3, [pc, #56]	; (2cc4 <z_arm_mpu_init+0x58>)
    2c8a:	7018      	strb	r0, [r3, #0]


	arm_core_mpu_enable();
    2c8c:	f7ff ffd2 	bl	2c34 <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    2c90:	2000      	movs	r0, #0
}
    2c92:	bd10      	pop	{r4, pc}
    2c94:	60a2      	str	r2, [r4, #8]
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2c96:	f851 3c0c 	ldr.w	r3, [r1, #-12]
    2c9a:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    2c9e:	4313      	orrs	r3, r2
    2ca0:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2ca4:	60e3      	str	r3, [r4, #12]
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2ca6:	f851 3c04 	ldr.w	r3, [r1, #-4]
    2caa:	f043 0301 	orr.w	r3, r3, #1
    2cae:	6123      	str	r3, [r4, #16]
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2cb0:	3201      	adds	r2, #1
    2cb2:	e7e5      	b.n	2c80 <z_arm_mpu_init+0x14>
		return -1;
    2cb4:	f04f 30ff 	mov.w	r0, #4294967295
    2cb8:	e7eb      	b.n	2c92 <z_arm_mpu_init+0x26>
    2cba:	bf00      	nop
    2cbc:	000071dc 	.word	0x000071dc
    2cc0:	e000ed90 	.word	0xe000ed90
    2cc4:	200006b0 	.word	0x200006b0

00002cc8 <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
    2cc8:	4b01      	ldr	r3, [pc, #4]	; (2cd0 <__stdout_hook_install+0x8>)
    2cca:	6018      	str	r0, [r3, #0]
}
    2ccc:	4770      	bx	lr
    2cce:	bf00      	nop
    2cd0:	20000020 	.word	0x20000020

00002cd4 <z_impl_zephyr_read_stdin>:
{
	_stdin_hook = hook;
}

int z_impl_zephyr_read_stdin(char *buf, int nbytes)
{
    2cd4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	int i = 0;

	for (i = 0; i < nbytes; i++) {
		*(buf + i) = _stdin_hook();
    2cd6:	4f08      	ldr	r7, [pc, #32]	; (2cf8 <z_impl_zephyr_read_stdin+0x24>)
{
    2cd8:	4606      	mov	r6, r0
    2cda:	460d      	mov	r5, r1
	for (i = 0; i < nbytes; i++) {
    2cdc:	2400      	movs	r4, #0
    2cde:	42ac      	cmp	r4, r5
    2ce0:	da08      	bge.n	2cf4 <z_impl_zephyr_read_stdin+0x20>
		*(buf + i) = _stdin_hook();
    2ce2:	683b      	ldr	r3, [r7, #0]
    2ce4:	4798      	blx	r3
		if ((*(buf + i) == '\n') || (*(buf + i) == '\r')) {
    2ce6:	280a      	cmp	r0, #10
		*(buf + i) = _stdin_hook();
    2ce8:	5530      	strb	r0, [r6, r4]
		if ((*(buf + i) == '\n') || (*(buf + i) == '\r')) {
    2cea:	f104 0401 	add.w	r4, r4, #1
    2cee:	d001      	beq.n	2cf4 <z_impl_zephyr_read_stdin+0x20>
    2cf0:	280d      	cmp	r0, #13
    2cf2:	d1f4      	bne.n	2cde <z_impl_zephyr_read_stdin+0xa>
			i++;
			break;
		}
	}
	return i;
}
    2cf4:	4620      	mov	r0, r4
    2cf6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    2cf8:	2000001c 	.word	0x2000001c

00002cfc <z_impl_zephyr_write_stdout>:
}
#include <syscalls/z_zephyr_read_stdin_mrsh.c>
#endif

int z_impl_zephyr_write_stdout(const void *buffer, int nbytes)
{
    2cfc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2cfe:	4f0a      	ldr	r7, [pc, #40]	; (2d28 <z_impl_zephyr_write_stdout+0x2c>)
    2d00:	460d      	mov	r5, r1
    2d02:	1e46      	subs	r6, r0, #1
	const char *buf = buffer;
	int i;

	for (i = 0; i < nbytes; i++) {
    2d04:	f1c0 0401 	rsb	r4, r0, #1
    2d08:	19a3      	adds	r3, r4, r6
    2d0a:	429d      	cmp	r5, r3
    2d0c:	dc01      	bgt.n	2d12 <z_impl_zephyr_write_stdout+0x16>
			_stdout_hook('\r');
		}
		_stdout_hook(*(buf + i));
	}
	return nbytes;
}
    2d0e:	4628      	mov	r0, r5
    2d10:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		if (*(buf + i) == '\n') {
    2d12:	7873      	ldrb	r3, [r6, #1]
    2d14:	2b0a      	cmp	r3, #10
    2d16:	d102      	bne.n	2d1e <z_impl_zephyr_write_stdout+0x22>
			_stdout_hook('\r');
    2d18:	683b      	ldr	r3, [r7, #0]
    2d1a:	200d      	movs	r0, #13
    2d1c:	4798      	blx	r3
		_stdout_hook(*(buf + i));
    2d1e:	683b      	ldr	r3, [r7, #0]
    2d20:	f816 0f01 	ldrb.w	r0, [r6, #1]!
    2d24:	4798      	blx	r3
	for (i = 0; i < nbytes; i++) {
    2d26:	e7ef      	b.n	2d08 <z_impl_zephyr_write_stdout+0xc>
    2d28:	20000020 	.word	0x20000020

00002d2c <_sbrk>:
		;
	}
}

void *_sbrk(intptr_t count)
{
    2d2c:	b510      	push	{r4, lr}
	void *ret, *ptr;

	ptr = ((char *)HEAP_BASE) + heap_sz;
    2d2e:	4c07      	ldr	r4, [pc, #28]	; (2d4c <_sbrk+0x20>)
    2d30:	6823      	ldr	r3, [r4, #0]

	if ((heap_sz + count) < MAX_HEAP_SIZE) {
    2d32:	18c2      	adds	r2, r0, r3
    2d34:	4806      	ldr	r0, [pc, #24]	; (2d50 <_sbrk+0x24>)
    2d36:	f1c0 5100 	rsb	r1, r0, #536870912	; 0x20000000
    2d3a:	f501 3100 	add.w	r1, r1, #131072	; 0x20000
    2d3e:	428a      	cmp	r2, r1
	ptr = ((char *)HEAP_BASE) + heap_sz;
    2d40:	bf3a      	itte	cc
    2d42:	18c0      	addcc	r0, r0, r3
		heap_sz += count;
    2d44:	6022      	strcc	r2, [r4, #0]
		ret = ptr;
	} else {
		ret = (void *)-1;
    2d46:	f04f 30ff 	movcs.w	r0, #4294967295
	}

	return ret;
}
    2d4a:	bd10      	pop	{r4, pc}
    2d4c:	200004c0 	.word	0x200004c0
    2d50:	200023b8 	.word	0x200023b8

00002d54 <__malloc_lock>:
	return z_impl_k_mutex_lock(mutex, timeout);
    2d54:	4803      	ldr	r0, [pc, #12]	; (2d64 <__malloc_lock+0x10>)
    2d56:	f04f 32ff 	mov.w	r2, #4294967295
    2d5a:	f04f 33ff 	mov.w	r3, #4294967295
    2d5e:	f001 b95d 	b.w	401c <z_impl_k_mutex_lock>
    2d62:	bf00      	nop
    2d64:	20000024 	.word	0x20000024

00002d68 <__malloc_unlock>:
	return z_impl_k_mutex_unlock(mutex);
    2d68:	4801      	ldr	r0, [pc, #4]	; (2d70 <__malloc_unlock+0x8>)
    2d6a:	f001 b9d5 	b.w	4118 <z_impl_k_mutex_unlock>
    2d6e:	bf00      	nop
    2d70:	20000024 	.word	0x20000024

00002d74 <nordicsemi_nrf52_init>:
	__asm__ volatile(
    2d74:	f04f 0320 	mov.w	r3, #32
    2d78:	f3ef 8211 	mrs	r2, BASEPRI
    2d7c:	f383 8811 	msr	BASEPRI, r3
    2d80:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    2d84:	4906      	ldr	r1, [pc, #24]	; (2da0 <nordicsemi_nrf52_init+0x2c>)
    2d86:	2301      	movs	r3, #1
    2d88:	f8c1 3540 	str.w	r3, [r1, #1344]	; 0x540
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    2d8c:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    2d90:	f8c1 3578 	str.w	r3, [r1, #1400]	; 0x578
	__asm__ volatile(
    2d94:	f382 8811 	msr	BASEPRI, r2
    2d98:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    2d9c:	2000      	movs	r0, #0
    2d9e:	4770      	bx	lr
    2da0:	4001e000 	.word	0x4001e000

00002da4 <sys_arch_reboot>:
    *p_gpregret = val;
    2da4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2da8:	b2c0      	uxtb	r0, r0
    2daa:	f8c3 051c 	str.w	r0, [r3, #1308]	; 0x51c
  __ASM volatile ("dsb 0xF":::"memory");
    2dae:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2db2:	4905      	ldr	r1, [pc, #20]	; (2dc8 <sys_arch_reboot+0x24>)
    2db4:	4b05      	ldr	r3, [pc, #20]	; (2dcc <sys_arch_reboot+0x28>)
    2db6:	68ca      	ldr	r2, [r1, #12]
    2db8:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2dbc:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    2dbe:	60cb      	str	r3, [r1, #12]
    2dc0:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    2dc4:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    2dc6:	e7fd      	b.n	2dc4 <sys_arch_reboot+0x20>
    2dc8:	e000ed00 	.word	0xe000ed00
    2dcc:	05fa0004 	.word	0x05fa0004

00002dd0 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    2dd0:	b120      	cbz	r0, 2ddc <arch_busy_wait+0xc>
    };

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    2dd2:	4b03      	ldr	r3, [pc, #12]	; (2de0 <arch_busy_wait+0x10>)
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    2dd4:	0180      	lsls	r0, r0, #6
    2dd6:	f043 0301 	orr.w	r3, r3, #1
    2dda:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    2ddc:	4770      	bx	lr
    2dde:	bf00      	nop
    2de0:	00007110 	.word	0x00007110

00002de4 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    2de4:	b508      	push	{r3, lr}
	static bool gpio_initialized;

	if (!gpio_initialized) {
    2de6:	4b09      	ldr	r3, [pc, #36]	; (2e0c <gpio_nrfx_init+0x28>)
    2de8:	781a      	ldrb	r2, [r3, #0]
    2dea:	b96a      	cbnz	r2, 2e08 <gpio_nrfx_init+0x24>
		gpio_initialized = true;
    2dec:	2101      	movs	r1, #1
    2dee:	7019      	strb	r1, [r3, #0]
		IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    2df0:	2006      	movs	r0, #6
    2df2:	2105      	movs	r1, #5
    2df4:	f7ff faf6 	bl	23e4 <z_arm_irq_priority_set>
			    gpiote_event_handler, NULL, 0);

		irq_enable(DT_IRQN(GPIOTE_NODE));
    2df8:	2006      	movs	r0, #6
    2dfa:	f7ff fad5 	bl	23a8 <arch_irq_enable>
    return ((uint32_t)p_reg + event);
}

NRF_STATIC_INLINE void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask)
{
    p_reg->INTENSET = mask;
    2dfe:	4b04      	ldr	r3, [pc, #16]	; (2e10 <gpio_nrfx_init+0x2c>)
    2e00:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    2e04:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
		nrf_gpiote_int_enable(NRF_GPIOTE, NRF_GPIOTE_INT_PORT_MASK);
	}

	return 0;
}
    2e08:	2000      	movs	r0, #0
    2e0a:	bd08      	pop	{r3, pc}
    2e0c:	200006b1 	.word	0x200006b1
    2e10:	40006000 	.word	0x40006000

00002e14 <gpio_nrfx_config>:
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    2e14:	4b2b      	ldr	r3, [pc, #172]	; (2ec4 <gpio_nrfx_config+0xb0>)
{
    2e16:	b5f0      	push	{r4, r5, r6, r7, lr}
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    2e18:	6844      	ldr	r4, [r0, #4]
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    2e1a:	482b      	ldr	r0, [pc, #172]	; (2ec8 <gpio_nrfx_config+0xb4>)
    2e1c:	4013      	ands	r3, r2
    2e1e:	4283      	cmp	r3, r0
    2e20:	d041      	beq.n	2ea6 <gpio_nrfx_config+0x92>
    2e22:	d80d      	bhi.n	2e40 <gpio_nrfx_config+0x2c>
    2e24:	2b06      	cmp	r3, #6
    2e26:	d015      	beq.n	2e54 <gpio_nrfx_config+0x40>
    2e28:	d805      	bhi.n	2e36 <gpio_nrfx_config+0x22>
    2e2a:	b19b      	cbz	r3, 2e54 <gpio_nrfx_config+0x40>
    2e2c:	2b02      	cmp	r3, #2
    2e2e:	d03c      	beq.n	2eaa <gpio_nrfx_config+0x96>
    2e30:	f06f 0015 	mvn.w	r0, #21
    2e34:	e036      	b.n	2ea4 <gpio_nrfx_config+0x90>
    2e36:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    2e3a:	d1f9      	bne.n	2e30 <gpio_nrfx_config+0x1c>
		drive = NRF_GPIO_PIN_H0S1;
    2e3c:	2301      	movs	r3, #1
    2e3e:	e009      	b.n	2e54 <gpio_nrfx_config+0x40>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    2e40:	4822      	ldr	r0, [pc, #136]	; (2ecc <gpio_nrfx_config+0xb8>)
    2e42:	4283      	cmp	r3, r0
    2e44:	d033      	beq.n	2eae <gpio_nrfx_config+0x9a>
    2e46:	f5b3 0fa0 	cmp.w	r3, #5242880	; 0x500000
    2e4a:	d032      	beq.n	2eb2 <gpio_nrfx_config+0x9e>
    2e4c:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
    2e50:	d1ee      	bne.n	2e30 <gpio_nrfx_config+0x1c>
		drive = NRF_GPIO_PIN_S0H1;
    2e52:	2302      	movs	r3, #2
	if ((flags & GPIO_PULL_UP) != 0) {
    2e54:	06d0      	lsls	r0, r2, #27
		pull = NRF_GPIO_PIN_NOPULL;
    2e56:	bf54      	ite	pl
    2e58:	f3c2 1640 	ubfxpl	r6, r2, #5, #1
		pull = NRF_GPIO_PIN_PULLUP;
    2e5c:	2603      	movmi	r6, #3
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
    2e5e:	f482 7580 	eor.w	r5, r2, #256	; 0x100
	if ((flags & GPIO_OUTPUT) != 0) {
    2e62:	0597      	lsls	r7, r2, #22
	dir = ((flags & GPIO_OUTPUT) != 0)
    2e64:	f3c2 2040 	ubfx	r0, r2, #9, #1
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
    2e68:	f3c5 2500 	ubfx	r5, r5, #8, #1
	if ((flags & GPIO_OUTPUT) != 0) {
    2e6c:	d507      	bpl.n	2e7e <gpio_nrfx_config+0x6a>
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
    2e6e:	f412 6f00 	tst.w	r2, #2048	; 0x800
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    2e72:	6867      	ldr	r7, [r4, #4]
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
    2e74:	d01f      	beq.n	2eb6 <gpio_nrfx_config+0xa2>
			nrf_gpio_port_out_set(reg, BIT(pin));
    2e76:	2201      	movs	r2, #1
    2e78:	408a      	lsls	r2, r1
}


NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
{
    p_reg->OUTSET = set_mask;
    2e7a:	f8c7 2508 	str.w	r2, [r7, #1288]	; 0x508
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;

    return pin_number >> 5;
    2e7e:	7a22      	ldrb	r2, [r4, #8]
        case 1: return NRF_P1;
    2e80:	4c13      	ldr	r4, [pc, #76]	; (2ed0 <gpio_nrfx_config+0xbc>)
    2e82:	2a01      	cmp	r2, #1
    *p_pin = pin_number & 0x1F;
    2e84:	f001 011f 	and.w	r1, r1, #31
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    2e88:	ea40 0245 	orr.w	r2, r0, r5, lsl #1
        case 1: return NRF_P1;
    2e8c:	bf18      	it	ne
    2e8e:	f04f 44a0 	movne.w	r4, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    2e92:	ea42 2303 	orr.w	r3, r2, r3, lsl #8
    reg->PIN_CNF[pin_number] = cnf;
    2e96:	f501 71e0 	add.w	r1, r1, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    2e9a:	ea43 0386 	orr.w	r3, r3, r6, lsl #2
    reg->PIN_CNF[pin_number] = cnf;
    2e9e:	f844 3021 	str.w	r3, [r4, r1, lsl #2]
	return 0;
    2ea2:	2000      	movs	r0, #0
}
    2ea4:	bdf0      	pop	{r4, r5, r6, r7, pc}
		drive = NRF_GPIO_PIN_H0D1;
    2ea6:	2307      	movs	r3, #7
    2ea8:	e7d4      	b.n	2e54 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_D0S1;
    2eaa:	2304      	movs	r3, #4
    2eac:	e7d2      	b.n	2e54 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_D0H1;
    2eae:	2305      	movs	r3, #5
    2eb0:	e7d0      	b.n	2e54 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_H0H1;
    2eb2:	2303      	movs	r3, #3
    2eb4:	e7ce      	b.n	2e54 <gpio_nrfx_config+0x40>
		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
    2eb6:	0552      	lsls	r2, r2, #21
			nrf_gpio_port_out_clear(reg, BIT(pin));
    2eb8:	bf42      	ittt	mi
    2eba:	2201      	movmi	r2, #1
    2ebc:	408a      	lslmi	r2, r1
    p_reg->OUTCLR = clr_mask;
    2ebe:	f8c7 250c 	strmi.w	r2, [r7, #1292]	; 0x50c
}
    2ec2:	e7dc      	b.n	2e7e <gpio_nrfx_config+0x6a>
    2ec4:	00f00006 	.word	0x00f00006
    2ec8:	00100006 	.word	0x00100006
    2ecc:	00400002 	.word	0x00400002
    2ed0:	50000300 	.word	0x50000300

00002ed4 <nrf_gpio_cfg_sense_set>:
    *p_pin = pin_number & 0x1F;
    2ed4:	f000 021f 	and.w	r2, r0, #31
    return pin_number >> 5;
    2ed8:	0940      	lsrs	r0, r0, #5
        case 1: return NRF_P1;
    2eda:	4b08      	ldr	r3, [pc, #32]	; (2efc <nrf_gpio_cfg_sense_set+0x28>)
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    2edc:	2801      	cmp	r0, #1
        case 1: return NRF_P1;
    2ede:	bf18      	it	ne
    2ee0:	f04f 43a0 	movne.w	r3, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    2ee4:	eb03 0382 	add.w	r3, r3, r2, lsl #2
    2ee8:	f8d3 2700 	ldr.w	r2, [r3, #1792]	; 0x700
    2eec:	f422 3240 	bic.w	r2, r2, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    2ef0:	ea42 4201 	orr.w	r2, r2, r1, lsl #16
    2ef4:	f8c3 2700 	str.w	r2, [r3, #1792]	; 0x700
}
    2ef8:	4770      	bx	lr
    2efa:	bf00      	nop
    2efc:	50000300 	.word	0x50000300

00002f00 <check_level_trigger_pins>:
{
    2f00:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	struct gpio_nrfx_data *data = get_port_data(port);
    2f04:	6903      	ldr	r3, [r0, #16]
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
    2f06:	f8d0 a004 	ldr.w	sl, [r0, #4]
	uint32_t out = data->pin_int_en;
    2f0a:	68de      	ldr	r6, [r3, #12]
        case 1: return NRF_P1;
    2f0c:	f8df b07c 	ldr.w	fp, [pc, #124]	; 2f8c <check_level_trigger_pins+0x8c>
{
    2f10:	4688      	mov	r8, r1
	out &= ~data->trig_edge & ~data->double_edge;
    2f12:	e9d3 2105 	ldrd	r2, r1, [r3, #20]
    2f16:	430a      	orrs	r2, r1
    2f18:	ea26 0602 	bic.w	r6, r6, r2
	uint32_t port_in = nrf_gpio_port_in_read(cfg->port);
    2f1c:	f8da 2004 	ldr.w	r2, [sl, #4]
	uint32_t pin_states = ~(port_in ^ data->int_active_level);
    2f20:	691b      	ldr	r3, [r3, #16]
    return p_reg->IN;
    2f22:	f8d2 5510 	ldr.w	r5, [r2, #1296]	; 0x510
    2f26:	405d      	eors	r5, r3
	uint32_t out = pin_states & level_pins;
    2f28:	ea26 0505 	bic.w	r5, r6, r5
	uint32_t check_pins = level_pins;
    2f2c:	4637      	mov	r7, r6
	uint32_t bit = 1U << pin;
    2f2e:	2401      	movs	r4, #1
	uint32_t pin = 0U;
    2f30:	f04f 0900 	mov.w	r9, #0
	while (check_pins) {
    2f34:	b917      	cbnz	r7, 2f3c <check_level_trigger_pins+0x3c>
}
    2f36:	4628      	mov	r0, r5
    2f38:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
		if (check_pins & bit) {
    2f3c:	423c      	tst	r4, r7
    2f3e:	d021      	beq.n	2f84 <check_level_trigger_pins+0x84>
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    2f40:	f89a 3008 	ldrb.w	r3, [sl, #8]
    2f44:	f009 001f 	and.w	r0, r9, #31
			if (!(level_pins & bit)) {
    2f48:	4234      	tst	r4, r6
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    2f4a:	ea40 1043 	orr.w	r0, r0, r3, lsl #5
			if (!(level_pins & bit)) {
    2f4e:	d114      	bne.n	2f7a <check_level_trigger_pins+0x7a>
    return pin_number >> 5;
    2f50:	0942      	lsrs	r2, r0, #5
        case 1: return NRF_P1;
    2f52:	2a01      	cmp	r2, #1
    *p_pin = pin_number & 0x1F;
    2f54:	f000 031f 	and.w	r3, r0, #31
        case 1: return NRF_P1;
    2f58:	bf14      	ite	ne
    2f5a:	f04f 42a0 	movne.w	r2, #1342177280	; 0x50000000
    2f5e:	465a      	moveq	r2, fp
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    2f60:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    2f64:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    2f68:	f3c3 4301 	ubfx	r3, r3, #16, #2
				if (high) {
    2f6c:	2b02      	cmp	r3, #2
					*sense_levels |= bit;
    2f6e:	bf02      	ittt	eq
    2f70:	f8d8 3000 	ldreq.w	r3, [r8]
    2f74:	4323      	orreq	r3, r4
    2f76:	f8c8 3000 	streq.w	r3, [r8]
			nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
    2f7a:	2100      	movs	r1, #0
    2f7c:	f7ff ffaa 	bl	2ed4 <nrf_gpio_cfg_sense_set>
			check_pins &= ~bit;
    2f80:	ea27 0704 	bic.w	r7, r7, r4
		++pin;
    2f84:	f109 0901 	add.w	r9, r9, #1
		bit <<= 1;
    2f88:	0064      	lsls	r4, r4, #1
    2f8a:	e7d3      	b.n	2f34 <check_level_trigger_pins+0x34>
    2f8c:	50000300 	.word	0x50000300

00002f90 <gpio_nrfx_pin_interrupt_configure>:
{
    2f90:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    2f92:	460e      	mov	r6, r1
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    2f94:	6841      	ldr	r1, [r0, #4]
	struct gpio_nrfx_data *data = get_port_data(port);
    2f96:	6907      	ldr	r7, [r0, #16]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    2f98:	7a09      	ldrb	r1, [r1, #8]
    2f9a:	f006 051f 	and.w	r5, r6, #31
	if (!IS_ENABLED(CONFIG_GPIO_NRF_INT_EDGE_USING_SENSE) &&
    2f9e:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    2fa2:	ea45 1541 	orr.w	r5, r5, r1, lsl #5
    2fa6:	d110      	bne.n	2fca <gpio_nrfx_pin_interrupt_configure+0x3a>
    return pin_number >> 5;
    2fa8:	0968      	lsrs	r0, r5, #5
        case 1: return NRF_P1;
    2faa:	2801      	cmp	r0, #1
    *p_pin = pin_number & 0x1F;
    2fac:	f005 011f 	and.w	r1, r5, #31
        case 1: return NRF_P1;
    2fb0:	485d      	ldr	r0, [pc, #372]	; (3128 <gpio_nrfx_pin_interrupt_configure+0x198>)
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    2fb2:	f501 71e0 	add.w	r1, r1, #448	; 0x1c0
        case 1: return NRF_P1;
    2fb6:	bf18      	it	ne
    2fb8:	f04f 40a0 	movne.w	r0, #1342177280	; 0x50000000
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    2fbc:	f850 1021 	ldr.w	r1, [r0, r1, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    2fc0:	07c8      	lsls	r0, r1, #31
    2fc2:	d507      	bpl.n	2fd4 <gpio_nrfx_pin_interrupt_configure+0x44>
		return -ENOTSUP;
    2fc4:	f06f 0085 	mvn.w	r0, #133	; 0x85
    2fc8:	e093      	b.n	30f2 <gpio_nrfx_pin_interrupt_configure+0x162>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    2fca:	f5b2 5f00 	cmp.w	r2, #8192	; 0x2000
    2fce:	68f9      	ldr	r1, [r7, #12]
    2fd0:	f000 8091 	beq.w	30f6 <gpio_nrfx_pin_interrupt_configure+0x166>
    2fd4:	68f8      	ldr	r0, [r7, #12]
    2fd6:	2101      	movs	r1, #1
    2fd8:	40b1      	lsls	r1, r6
    2fda:	4301      	orrs	r1, r0
    2fdc:	6978      	ldr	r0, [r7, #20]
    2fde:	60f9      	str	r1, [r7, #12]
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    2fe0:	2101      	movs	r1, #1
    2fe2:	40b1      	lsls	r1, r6
    2fe4:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    2fe8:	69ba      	ldr	r2, [r7, #24]
    2fea:	bf0c      	ite	eq
    2fec:	4308      	orreq	r0, r1
    2fee:	4388      	bicne	r0, r1
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
    2ff0:	f5b3 2fc0 	cmp.w	r3, #393216	; 0x60000
    2ff4:	bf0c      	ite	eq
    2ff6:	430a      	orreq	r2, r1
    2ff8:	438a      	bicne	r2, r1
    2ffa:	61ba      	str	r2, [r7, #24]
    2ffc:	693a      	ldr	r2, [r7, #16]
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    2ffe:	6178      	str	r0, [r7, #20]
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    3000:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
    3004:	bf0c      	ite	eq
    3006:	4311      	orreq	r1, r2
    3008:	ea22 0101 	bicne.w	r1, r2, r1
    p_reg->INTENCLR = mask;
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask)
{
    return p_reg->INTENSET & mask;
    300c:	4a47      	ldr	r2, [pc, #284]	; (312c <gpio_nrfx_pin_interrupt_configure+0x19c>)
    300e:	6139      	str	r1, [r7, #16]
    3010:	f8d2 3304 	ldr.w	r3, [r2, #772]	; 0x304
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    3014:	2000      	movs	r0, #0
    3016:	b2db      	uxtb	r3, r3
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
{
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    3018:	f500 71a2 	add.w	r1, r0, #324	; 0x144
    301c:	f852 1021 	ldr.w	r1, [r2, r1, lsl #2]
    3020:	f3c1 2105 	ubfx	r1, r1, #8, #6
		if ((nrf_gpiote_event_pin_get(NRF_GPIOTE, i) == abs_pin)
    3024:	428d      	cmp	r5, r1
    3026:	d16b      	bne.n	3100 <gpio_nrfx_pin_interrupt_configure+0x170>
		    && (intenset & BIT(i))) {
    3028:	fa23 f100 	lsr.w	r1, r3, r0
    302c:	07c9      	lsls	r1, r1, #31
    302e:	d567      	bpl.n	3100 <gpio_nrfx_pin_interrupt_configure+0x170>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
    3030:	0083      	lsls	r3, r0, #2
    3032:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    3036:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    303a:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
    303e:	f021 0101 	bic.w	r1, r1, #1
    3042:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
			nrf_gpiote_int_disable(NRF_GPIOTE, BIT(i));
    3046:	2301      	movs	r3, #1
    3048:	4083      	lsls	r3, r0
    p_reg->INTENCLR = mask;
    304a:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
			nrfx_gpiote_channel_free(i);
    304e:	b2c0      	uxtb	r0, r0
    3050:	f000 fc86 	bl	3960 <nrfx_gpiote_channel_free>
	nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
    3054:	4628      	mov	r0, r5
    3056:	2100      	movs	r1, #0
    3058:	f7ff ff3c 	bl	2ed4 <nrf_gpio_cfg_sense_set>
	if (data->pin_int_en & BIT(pin)) {
    305c:	68f8      	ldr	r0, [r7, #12]
    305e:	40f0      	lsrs	r0, r6
    3060:	f010 0001 	ands.w	r0, r0, #1
    3064:	d045      	beq.n	30f2 <gpio_nrfx_pin_interrupt_configure+0x162>
		if (data->trig_edge & BIT(pin)) {
    3066:	6978      	ldr	r0, [r7, #20]
    3068:	40f0      	lsrs	r0, r6
    306a:	f010 0401 	ands.w	r4, r0, #1
    306e:	d04e      	beq.n	310e <gpio_nrfx_pin_interrupt_configure+0x17e>
				if (data->double_edge & BIT(pin)) {
    3070:	69bb      	ldr	r3, [r7, #24]
    3072:	40f3      	lsrs	r3, r6
    3074:	07db      	lsls	r3, r3, #31
				} else if ((data->int_active_level & BIT(pin)) != 0U) {
    3076:	bf5f      	itttt	pl
    3078:	6939      	ldrpl	r1, [r7, #16]
    307a:	fa21 f606 	lsrpl.w	r6, r1, r6
    307e:	f006 0601 	andpl.w	r6, r6, #1
    3082:	f1c6 0602 	rsbpl	r6, r6, #2
	if (nrfx_gpiote_channel_alloc(&channel) != NRFX_SUCCESS) {
    3086:	f10d 0007 	add.w	r0, sp, #7
				} else if ((data->int_active_level & BIT(pin)) != 0U) {
    308a:	bf54      	ite	pl
    308c:	b2f6      	uxtbpl	r6, r6
					pol = NRF_GPIOTE_POLARITY_TOGGLE;
    308e:	2603      	movmi	r6, #3
	if (nrfx_gpiote_channel_alloc(&channel) != NRFX_SUCCESS) {
    3090:	f000 fc88 	bl	39a4 <nrfx_gpiote_channel_alloc>
    3094:	4b26      	ldr	r3, [pc, #152]	; (3130 <gpio_nrfx_pin_interrupt_configure+0x1a0>)
    3096:	4298      	cmp	r0, r3
    3098:	d136      	bne.n	3108 <gpio_nrfx_pin_interrupt_configure+0x178>
	nrf_gpiote_event_t evt = offsetof(NRF_GPIOTE_Type, EVENTS_IN[channel]);
    309a:	f89d 1007 	ldrb.w	r1, [sp, #7]
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    309e:	008b      	lsls	r3, r1, #2
    30a0:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    30a4:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    30a8:	022d      	lsls	r5, r5, #8
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    30aa:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    30ae:	f422 324f 	bic.w	r2, r2, #211968	; 0x33c00
    30b2:	f422 7240 	bic.w	r2, r2, #768	; 0x300
    30b6:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    30ba:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    30be:	f405 557c 	and.w	r5, r5, #16128	; 0x3f00
    30c2:	4315      	orrs	r5, r2
    return ((uint32_t)p_reg + event);
    30c4:	008a      	lsls	r2, r1, #2
    30c6:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    30ca:	f502 42c2 	add.w	r2, r2, #24832	; 0x6100
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    30ce:	ea45 4606 	orr.w	r6, r5, r6, lsl #16
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    30d2:	2000      	movs	r0, #0
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    30d4:	f8c3 6510 	str.w	r6, [r3, #1296]	; 0x510
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    30d8:	6010      	str	r0, [r2, #0]
    30da:	6812      	ldr	r2, [r2, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    30dc:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    30e0:	f042 0201 	orr.w	r2, r2, #1
    30e4:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
    p_reg->INTENSET = mask;
    30e8:	4a10      	ldr	r2, [pc, #64]	; (312c <gpio_nrfx_pin_interrupt_configure+0x19c>)
	nrf_gpiote_int_enable(NRF_GPIOTE, BIT(channel));
    30ea:	2301      	movs	r3, #1
    30ec:	408b      	lsls	r3, r1
    30ee:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    30f2:	b003      	add	sp, #12
    30f4:	bdf0      	pop	{r4, r5, r6, r7, pc}
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    30f6:	2001      	movs	r0, #1
    30f8:	40b0      	lsls	r0, r6
    30fa:	ea21 0100 	bic.w	r1, r1, r0
    30fe:	e76d      	b.n	2fdc <gpio_nrfx_pin_interrupt_configure+0x4c>
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    3100:	3001      	adds	r0, #1
    3102:	2808      	cmp	r0, #8
    3104:	d188      	bne.n	3018 <gpio_nrfx_pin_interrupt_configure+0x88>
    3106:	e7a5      	b.n	3054 <gpio_nrfx_pin_interrupt_configure+0xc4>
		return -ENODEV;
    3108:	f06f 0012 	mvn.w	r0, #18
    310c:	e7f1      	b.n	30f2 <gpio_nrfx_pin_interrupt_configure+0x162>
	if ((BIT(pin) & data->int_active_level) != 0U) {
    310e:	6939      	ldr	r1, [r7, #16]
    3110:	40f1      	lsrs	r1, r6
    3112:	f001 0101 	and.w	r1, r1, #1
    3116:	f1c1 0103 	rsb	r1, r1, #3
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    311a:	4628      	mov	r0, r5
    311c:	b2c9      	uxtb	r1, r1
    311e:	f7ff fed9 	bl	2ed4 <nrf_gpio_cfg_sense_set>
	int res = 0;
    3122:	4620      	mov	r0, r4
    3124:	e7e5      	b.n	30f2 <gpio_nrfx_pin_interrupt_configure+0x162>
    3126:	bf00      	nop
    3128:	50000300 	.word	0x50000300
    312c:	40006000 	.word	0x40006000
    3130:	0bad0000 	.word	0x0bad0000

00003134 <gpiote_event_handler>:
{
    3134:	b5f0      	push	{r4, r5, r6, r7, lr}
	uint32_t fired_triggers[GPIO_COUNT] = {0};
    3136:	2400      	movs	r4, #0
{
    3138:	b085      	sub	sp, #20
	uint32_t fired_triggers[GPIO_COUNT] = {0};
    313a:	e9cd 4400 	strd	r4, r4, [sp]
	uint32_t sense_levels[GPIO_COUNT] = {0};
    313e:	e9cd 4402 	strd	r4, r4, [sp, #8]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3142:	4e26      	ldr	r6, [pc, #152]	; (31dc <gpiote_event_handler+0xa8>)
    3144:	6835      	ldr	r5, [r6, #0]
	if (port_event) {
    3146:	b15d      	cbz	r5, 3160 <gpiote_event_handler+0x2c>
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(0)),
    3148:	a902      	add	r1, sp, #8
    314a:	4825      	ldr	r0, [pc, #148]	; (31e0 <gpiote_event_handler+0xac>)
    314c:	f7ff fed8 	bl	2f00 <check_level_trigger_pins>
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(1)),
    3150:	a903      	add	r1, sp, #12
		fired_triggers[0] =
    3152:	9000      	str	r0, [sp, #0]
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(1)),
    3154:	4823      	ldr	r0, [pc, #140]	; (31e4 <gpiote_event_handler+0xb0>)
    3156:	f7ff fed3 	bl	2f00 <check_level_trigger_pins>
		fired_triggers[1] =
    315a:	9001      	str	r0, [sp, #4]
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    315c:	6034      	str	r4, [r6, #0]
    315e:	6833      	ldr	r3, [r6, #0]
    return p_reg->INTENSET & mask;
    3160:	4c21      	ldr	r4, [pc, #132]	; (31e8 <gpiote_event_handler+0xb4>)
{
    3162:	2200      	movs	r2, #0
		if (nrf_gpiote_int_enable_check(NRF_GPIOTE, BIT(i)) &&
    3164:	2601      	movs	r6, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3166:	4694      	mov	ip, r2
    return p_reg->INTENSET & mask;
    3168:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
    316c:	fa06 f102 	lsl.w	r1, r6, r2
    3170:	4219      	tst	r1, r3
    3172:	d01b      	beq.n	31ac <gpiote_event_handler+0x78>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3174:	0091      	lsls	r1, r2, #2
    3176:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    317a:	f501 41c2 	add.w	r1, r1, #24832	; 0x6100
    317e:	680b      	ldr	r3, [r1, #0]
    3180:	b1a3      	cbz	r3, 31ac <gpiote_event_handler+0x78>
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    3182:	f502 73a2 	add.w	r3, r2, #324	; 0x144
			fired_triggers[abs_pin / 32U] |= BIT(abs_pin % 32);
    3186:	af04      	add	r7, sp, #16
    3188:	f854 3023 	ldr.w	r3, [r4, r3, lsl #2]
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    318c:	f8c1 c000 	str.w	ip, [r1]
    3190:	f3c3 3040 	ubfx	r0, r3, #13, #1
    3194:	eb07 0080 	add.w	r0, r7, r0, lsl #2
    3198:	f3c3 2304 	ubfx	r3, r3, #8, #5
    319c:	f850 7c10 	ldr.w	r7, [r0, #-16]
    31a0:	fa06 f303 	lsl.w	r3, r6, r3
    31a4:	433b      	orrs	r3, r7
    31a6:	f840 3c10 	str.w	r3, [r0, #-16]
    31aa:	680b      	ldr	r3, [r1, #0]
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    31ac:	3201      	adds	r2, #1
    31ae:	2a08      	cmp	r2, #8
    31b0:	d1da      	bne.n	3168 <gpiote_event_handler+0x34>
	if (fired_triggers[0]) {
    31b2:	9a00      	ldr	r2, [sp, #0]
    31b4:	b11a      	cbz	r2, 31be <gpiote_event_handler+0x8a>
	gpio_fire_callbacks(list, port, pins);
    31b6:	490a      	ldr	r1, [pc, #40]	; (31e0 <gpiote_event_handler+0xac>)
    31b8:	480c      	ldr	r0, [pc, #48]	; (31ec <gpiote_event_handler+0xb8>)
    31ba:	f003 f9ee 	bl	659a <gpio_fire_callbacks>
	if (fired_triggers[1]) {
    31be:	9a01      	ldr	r2, [sp, #4]
    31c0:	b11a      	cbz	r2, 31ca <gpiote_event_handler+0x96>
	gpio_fire_callbacks(list, port, pins);
    31c2:	4908      	ldr	r1, [pc, #32]	; (31e4 <gpiote_event_handler+0xb0>)
    31c4:	480a      	ldr	r0, [pc, #40]	; (31f0 <gpiote_event_handler+0xbc>)
    31c6:	f003 f9e8 	bl	659a <gpio_fire_callbacks>
	if (port_event) {
    31ca:	b12d      	cbz	r5, 31d8 <gpiote_event_handler+0xa4>
		cfg_level_pins(DEVICE_DT_GET(GPIO(0)));
    31cc:	4804      	ldr	r0, [pc, #16]	; (31e0 <gpiote_event_handler+0xac>)
    31ce:	f003 fa4e 	bl	666e <cfg_level_pins>
		cfg_level_pins(DEVICE_DT_GET(GPIO(1)));
    31d2:	4804      	ldr	r0, [pc, #16]	; (31e4 <gpiote_event_handler+0xb0>)
    31d4:	f003 fa4b 	bl	666e <cfg_level_pins>
}
    31d8:	b005      	add	sp, #20
    31da:	bdf0      	pop	{r4, r5, r6, r7, pc}
    31dc:	4000617c 	.word	0x4000617c
    31e0:	00006ea8 	.word	0x00006ea8
    31e4:	00006ec0 	.word	0x00006ec0
    31e8:	40006000 	.word	0x40006000
    31ec:	200004d0 	.word	0x200004d0
    31f0:	200004ec 	.word	0x200004ec

000031f4 <hfclk_on_callback>:
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)task);
}

NRF_STATIC_INLINE void nrf_temp_task_trigger(NRF_TEMP_Type * p_reg, nrf_temp_task_t task)
{
    *(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task) = 1;
    31f4:	4b01      	ldr	r3, [pc, #4]	; (31fc <hfclk_on_callback+0x8>)
    31f6:	2201      	movs	r2, #1
    31f8:	601a      	str	r2, [r3, #0]
			      struct onoff_client *cli,
			      uint32_t state,
			      int res)
{
	nrf_temp_task_trigger(NRF_TEMP, NRF_TEMP_TASK_START);
}
    31fa:	4770      	bx	lr
    31fc:	4000c000 	.word	0x4000c000

00003200 <temp_nrf5_channel_get>:
{
	struct temp_nrf5_data *data = dev->data;
	int32_t uval;


	if (chan != SENSOR_CHAN_DIE_TEMP) {
    3200:	290c      	cmp	r1, #12
	struct temp_nrf5_data *data = dev->data;
    3202:	6903      	ldr	r3, [r0, #16]
	if (chan != SENSOR_CHAN_DIE_TEMP) {
    3204:	d10b      	bne.n	321e <temp_nrf5_channel_get+0x1e>
		return -ENOTSUP;
	}

	uval = data->sample * TEMP_NRF5_TEMP_SCALE;
    3206:	6a59      	ldr	r1, [r3, #36]	; 0x24
    3208:	4b06      	ldr	r3, [pc, #24]	; (3224 <temp_nrf5_channel_get+0x24>)
	val->val1 = uval / 1000000;
    320a:	4807      	ldr	r0, [pc, #28]	; (3228 <temp_nrf5_channel_get+0x28>)
	uval = data->sample * TEMP_NRF5_TEMP_SCALE;
    320c:	4359      	muls	r1, r3
	val->val1 = uval / 1000000;
    320e:	fb91 f3f0 	sdiv	r3, r1, r0
    3212:	6013      	str	r3, [r2, #0]
	val->val2 = uval % 1000000;
    3214:	fb00 1313 	mls	r3, r0, r3, r1
    3218:	6053      	str	r3, [r2, #4]

	LOG_DBG("Temperature:%d,%d", val->val1, val->val2);

	return 0;
    321a:	2000      	movs	r0, #0
    321c:	4770      	bx	lr
		return -ENOTSUP;
    321e:	f06f 0085 	mvn.w	r0, #133	; 0x85
}
    3222:	4770      	bx	lr
    3224:	0003d090 	.word	0x0003d090
    3228:	000f4240 	.word	0x000f4240

0000322c <temp_nrf5_isr>:
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE void nrf_temp_event_clear(NRF_TEMP_Type * p_reg, nrf_temp_event_t event)
{
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    322c:	4b03      	ldr	r3, [pc, #12]	; (323c <temp_nrf5_isr+0x10>)

static void temp_nrf5_isr(void *arg)
{
	const struct device *dev = (const struct device *)arg;
	struct temp_nrf5_data *data = dev->data;
    322e:	6900      	ldr	r0, [r0, #16]
    3230:	2200      	movs	r2, #0
    3232:	601a      	str	r2, [r3, #0]
    3234:	681b      	ldr	r3, [r3, #0]
	z_impl_k_sem_give(sem);
    3236:	f000 bfb5 	b.w	41a4 <z_impl_k_sem_give>
    323a:	bf00      	nop
    323c:	4000c100 	.word	0x4000c100

00003240 <temp_nrf5_init>:
	.sample_fetch = temp_nrf5_sample_fetch,
	.channel_get = temp_nrf5_channel_get,
};

static int temp_nrf5_init(const struct device *dev)
{
    3240:	b510      	push	{r4, lr}
	struct temp_nrf5_data *data = dev->data;
    3242:	6904      	ldr	r4, [r0, #16]

	LOG_DBG("");

	/* A null clk_mgr indicates sensor has not been initialized */
	data->clk_mgr =
		z_nrf_clock_control_get_onoff(CLOCK_CONTROL_NRF_SUBSYS_HF);
    3244:	2000      	movs	r0, #0
    3246:	f7fe fe3f 	bl	1ec8 <z_nrf_clock_control_get_onoff>
	data->clk_mgr =
    324a:	62a0      	str	r0, [r4, #40]	; 0x28
	return z_impl_k_sem_init(sem, initial_count, limit);
    324c:	f04f 32ff 	mov.w	r2, #4294967295
    3250:	2100      	movs	r1, #0
    3252:	4620      	mov	r0, r4
    3254:	f003 fac3 	bl	67de <z_impl_k_sem_init>
	return z_impl_k_mutex_init(mutex);
    3258:	f104 0010 	add.w	r0, r4, #16
    325c:	f003 fab8 	bl	67d0 <z_impl_k_mutex_init>
	__ASSERT_NO_MSG(data->clk_mgr);

	k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
	k_mutex_init(&data->mutex);

	IRQ_CONNECT(
    3260:	2200      	movs	r2, #0
    3262:	2101      	movs	r1, #1
    3264:	200c      	movs	r0, #12
    3266:	f7ff f8bd 	bl	23e4 <z_arm_irq_priority_set>
		DT_INST_IRQN(0),
		DT_INST_IRQ(0, priority),
		temp_nrf5_isr,
		DEVICE_DT_INST_GET(0),
		0);
	irq_enable(DT_INST_IRQN(0));
    326a:	200c      	movs	r0, #12
    326c:	f7ff f89c 	bl	23a8 <arch_irq_enable>
    p_reg->INTENSET = mask;
    3270:	4b02      	ldr	r3, [pc, #8]	; (327c <temp_nrf5_init+0x3c>)
    3272:	2201      	movs	r2, #1
    3274:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304

	nrf_temp_int_enable(NRF_TEMP, NRF_TEMP_INT_DATARDY_MASK);

	return 0;
}
    3278:	2000      	movs	r0, #0
    327a:	bd10      	pop	{r4, pc}
    327c:	4000c000 	.word	0x4000c000

00003280 <temp_nrf5_sample_fetch>:
{
    3280:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
	struct temp_nrf5_data *data = dev->data;
    3282:	6905      	ldr	r5, [r0, #16]
	if (data->clk_mgr == NULL) {
    3284:	6aab      	ldr	r3, [r5, #40]	; 0x28
    3286:	b36b      	cbz	r3, 32e4 <temp_nrf5_sample_fetch+0x64>
	if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_DIE_TEMP) {
    3288:	2938      	cmp	r1, #56	; 0x38
    328a:	d001      	beq.n	3290 <temp_nrf5_sample_fetch+0x10>
    328c:	290c      	cmp	r1, #12
    328e:	d12c      	bne.n	32ea <temp_nrf5_sample_fetch+0x6a>
	k_mutex_lock(&data->mutex, K_FOREVER);
    3290:	f105 0610 	add.w	r6, r5, #16
	return z_impl_k_mutex_lock(mutex, timeout);
    3294:	f04f 32ff 	mov.w	r2, #4294967295
    3298:	f04f 33ff 	mov.w	r3, #4294967295
    329c:	4630      	mov	r0, r6
    329e:	f000 febd 	bl	401c <z_impl_k_mutex_lock>
    32a2:	4b13      	ldr	r3, [pc, #76]	; (32f0 <temp_nrf5_sample_fetch+0x70>)
    32a4:	9301      	str	r3, [sp, #4]
	r = onoff_request(data->clk_mgr, &cli);
    32a6:	6aa8      	ldr	r0, [r5, #40]	; 0x28
    32a8:	2303      	movs	r3, #3
    32aa:	2400      	movs	r4, #0
    32ac:	4669      	mov	r1, sp
    32ae:	9403      	str	r4, [sp, #12]
    32b0:	9302      	str	r3, [sp, #8]
    32b2:	f002 fd50 	bl	5d56 <onoff_request>
	return z_impl_k_sem_take(sem, timeout);
    32b6:	f04f 32ff 	mov.w	r2, #4294967295
    32ba:	f04f 33ff 	mov.w	r3, #4294967295
    32be:	4628      	mov	r0, r5
    32c0:	f000 ff90 	bl	41e4 <z_impl_k_sem_take>
	r = onoff_release(data->clk_mgr);
    32c4:	6aa8      	ldr	r0, [r5, #40]	; 0x28
    32c6:	f002 fd8f 	bl	5de8 <onoff_release>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
}

NRF_STATIC_INLINE int32_t nrf_temp_result_get(NRF_TEMP_Type const * p_reg)
{
    int32_t raw_measurement = p_reg->TEMP;
    32ca:	4b0a      	ldr	r3, [pc, #40]	; (32f4 <temp_nrf5_sample_fetch+0x74>)
    32cc:	f8d3 3508 	ldr.w	r3, [r3, #1288]	; 0x508
	data->sample = nrf_temp_result_get(NRF_TEMP);
    32d0:	626b      	str	r3, [r5, #36]	; 0x24
    *(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task) = 1;
    32d2:	4b09      	ldr	r3, [pc, #36]	; (32f8 <temp_nrf5_sample_fetch+0x78>)
    32d4:	2201      	movs	r2, #1
    32d6:	601a      	str	r2, [r3, #0]
	return z_impl_k_mutex_unlock(mutex);
    32d8:	4630      	mov	r0, r6
    32da:	f000 ff1d 	bl	4118 <z_impl_k_mutex_unlock>
	return 0;
    32de:	4620      	mov	r0, r4
}
    32e0:	b004      	add	sp, #16
    32e2:	bd70      	pop	{r4, r5, r6, pc}
		return -EAGAIN;
    32e4:	f06f 000a 	mvn.w	r0, #10
    32e8:	e7fa      	b.n	32e0 <temp_nrf5_sample_fetch+0x60>
		return -ENOTSUP;
    32ea:	f06f 0085 	mvn.w	r0, #133	; 0x85
    32ee:	e7f7      	b.n	32e0 <temp_nrf5_sample_fetch+0x60>
    32f0:	000031f5 	.word	0x000031f5
    32f4:	4000c000 	.word	0x4000c000
    32f8:	4000c004 	.word	0x4000c004

000032fc <uart_nrfx_poll_in>:
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type const * p_reg, nrf_uart_event_t event)
{
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    32fc:	4b06      	ldr	r3, [pc, #24]	; (3318 <uart_nrfx_poll_in+0x1c>)
    32fe:	681a      	ldr	r2, [r3, #0]
 * @return 0 if a character arrived, -1 if the input buffer if empty.
 */

static int uart_nrfx_poll_in(const struct device *dev, unsigned char *c)
{
	if (!nrf_uart_event_check(uart0_addr, NRF_UART_EVENT_RXDRDY)) {
    3300:	b13a      	cbz	r2, 3312 <uart_nrfx_poll_in+0x16>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3302:	2000      	movs	r0, #0
    3304:	6018      	str	r0, [r3, #0]
    3306:	681b      	ldr	r3, [r3, #0]
    nrf_uart_hwfc_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED);
}

NRF_STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type const * p_reg)
{
    return p_reg->RXD;
    3308:	4b04      	ldr	r3, [pc, #16]	; (331c <uart_nrfx_poll_in+0x20>)
    330a:	f8d3 3518 	ldr.w	r3, [r3, #1304]	; 0x518
    330e:	700b      	strb	r3, [r1, #0]
	nrf_uart_event_clear(uart0_addr, NRF_UART_EVENT_RXDRDY);

	/* got a character */
	*c = nrf_uart_rxd_get(uart0_addr);

	return 0;
    3310:	4770      	bx	lr
		return -1;
    3312:	f04f 30ff 	mov.w	r0, #4294967295
}
    3316:	4770      	bx	lr
    3318:	40002108 	.word	0x40002108
    331c:	40002000 	.word	0x40002000

00003320 <uart_nrfx_err_check>:
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    3320:	4b02      	ldr	r3, [pc, #8]	; (332c <uart_nrfx_err_check+0xc>)
    3322:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    3326:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
/** Console I/O function */
static int uart_nrfx_err_check(const struct device *dev)
{
	/* register bitfields maps to the defines in uart.h */
	return nrf_uart_errorsrc_get_and_clear(uart0_addr);
}
    332a:	4770      	bx	lr
    332c:	40002000 	.word	0x40002000

00003330 <uart_nrfx_configure>:

static int uart_nrfx_configure(const struct device *dev,
			       const struct uart_config *cfg)
{
    3330:	b5f0      	push	{r4, r5, r6, r7, lr}
	nrf_uart_config_t uart_cfg;

#if defined(UART_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
    3332:	794b      	ldrb	r3, [r1, #5]
    3334:	2b01      	cmp	r3, #1
    3336:	d026      	beq.n	3386 <uart_nrfx_configure+0x56>
    3338:	2b03      	cmp	r3, #3
    333a:	d121      	bne.n	3380 <uart_nrfx_configure+0x50>
	case UART_CFG_STOP_BITS_1:
		uart_cfg.stop = NRF_UART_STOP_ONE;
		break;
	case UART_CFG_STOP_BITS_2:
		uart_cfg.stop = NRF_UART_STOP_TWO;
    333c:	2710      	movs	r7, #16
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    333e:	798b      	ldrb	r3, [r1, #6]
    3340:	2b03      	cmp	r3, #3
    3342:	d11d      	bne.n	3380 <uart_nrfx_configure+0x50>
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
    3344:	79cd      	ldrb	r5, [r1, #7]
    3346:	b10d      	cbz	r5, 334c <uart_nrfx_configure+0x1c>
    3348:	2d01      	cmp	r5, #1
    334a:	d119      	bne.n	3380 <uart_nrfx_configure+0x50>
	}

#if defined(UART_CONFIG_PARITYTYPE_Msk)
	uart_cfg.paritytype = NRF_UART_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
    334c:	790a      	ldrb	r2, [r1, #4]
    334e:	2a01      	cmp	r2, #1
    3350:	d01b      	beq.n	338a <uart_nrfx_configure+0x5a>
    3352:	2a02      	cmp	r2, #2
    3354:	d01d      	beq.n	3392 <uart_nrfx_configure+0x62>
    3356:	b99a      	cbnz	r2, 3380 <uart_nrfx_configure+0x50>
    3358:	4614      	mov	r4, r2
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
    335a:	680b      	ldr	r3, [r1, #0]
	switch (baudrate) {
    335c:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
    3360:	d069      	beq.n	3436 <uart_nrfx_configure+0x106>
    3362:	d833      	bhi.n	33cc <uart_nrfx_configure+0x9c>
    3364:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    3368:	d067      	beq.n	343a <uart_nrfx_configure+0x10a>
    336a:	d81c      	bhi.n	33a6 <uart_nrfx_configure+0x76>
    336c:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    3370:	d065      	beq.n	343e <uart_nrfx_configure+0x10e>
    3372:	d810      	bhi.n	3396 <uart_nrfx_configure+0x66>
    3374:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    3378:	d064      	beq.n	3444 <uart_nrfx_configure+0x114>
    337a:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    337e:	d064      	beq.n	344a <uart_nrfx_configure+0x11a>
    3380:	f06f 0085 	mvn.w	r0, #133	; 0x85
    3384:	e056      	b.n	3434 <uart_nrfx_configure+0x104>
	switch (cfg->stop_bits) {
    3386:	2700      	movs	r7, #0
    3388:	e7d9      	b.n	333e <uart_nrfx_configure+0xe>
		uart_cfg.paritytype = NRF_UART_PARITYTYPE_ODD;
    338a:	f44f 7480 	mov.w	r4, #256	; 0x100
		uart_cfg.parity = NRF_UART_PARITY_INCLUDED;
    338e:	220e      	movs	r2, #14
    3390:	e7e3      	b.n	335a <uart_nrfx_configure+0x2a>
	uart_cfg.paritytype = NRF_UART_PARITYTYPE_EVEN;
    3392:	2400      	movs	r4, #0
    3394:	e7fb      	b.n	338e <uart_nrfx_configure+0x5e>
	switch (baudrate) {
    3396:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    339a:	d059      	beq.n	3450 <uart_nrfx_configure+0x120>
    339c:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    33a0:	d1ee      	bne.n	3380 <uart_nrfx_configure+0x50>
		nrf_baudrate = NRF_UART_BAUDRATE_4800;
    33a2:	4b35      	ldr	r3, [pc, #212]	; (3478 <uart_nrfx_configure+0x148>)
    33a4:	e039      	b.n	341a <uart_nrfx_configure+0xea>
	switch (baudrate) {
    33a6:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    33aa:	d054      	beq.n	3456 <uart_nrfx_configure+0x126>
    33ac:	d807      	bhi.n	33be <uart_nrfx_configure+0x8e>
    33ae:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    33b2:	d052      	beq.n	345a <uart_nrfx_configure+0x12a>
    33b4:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    33b8:	d1e2      	bne.n	3380 <uart_nrfx_configure+0x50>
		nrf_baudrate = NRF_UART_BAUDRATE_19200;
    33ba:	4b30      	ldr	r3, [pc, #192]	; (347c <uart_nrfx_configure+0x14c>)
    33bc:	e02d      	b.n	341a <uart_nrfx_configure+0xea>
	switch (baudrate) {
    33be:	f647 2612 	movw	r6, #31250	; 0x7a12
    33c2:	42b3      	cmp	r3, r6
    33c4:	d1dc      	bne.n	3380 <uart_nrfx_configure+0x50>
		nrf_baudrate = NRF_UART_BAUDRATE_31250;
    33c6:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    33ca:	e026      	b.n	341a <uart_nrfx_configure+0xea>
	switch (baudrate) {
    33cc:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    33d0:	d046      	beq.n	3460 <uart_nrfx_configure+0x130>
    33d2:	d811      	bhi.n	33f8 <uart_nrfx_configure+0xc8>
    33d4:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    33d8:	d044      	beq.n	3464 <uart_nrfx_configure+0x134>
    33da:	d808      	bhi.n	33ee <uart_nrfx_configure+0xbe>
    33dc:	f64d 26c0 	movw	r6, #56000	; 0xdac0
    33e0:	42b3      	cmp	r3, r6
    33e2:	d041      	beq.n	3468 <uart_nrfx_configure+0x138>
    33e4:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    33e8:	d1ca      	bne.n	3380 <uart_nrfx_configure+0x50>
		nrf_baudrate = NRF_UART_BAUDRATE_57600;
    33ea:	4b25      	ldr	r3, [pc, #148]	; (3480 <uart_nrfx_configure+0x150>)
    33ec:	e015      	b.n	341a <uart_nrfx_configure+0xea>
	switch (baudrate) {
    33ee:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    33f2:	d1c5      	bne.n	3380 <uart_nrfx_configure+0x50>
		nrf_baudrate = NRF_UART_BAUDRATE_115200;
    33f4:	4b23      	ldr	r3, [pc, #140]	; (3484 <uart_nrfx_configure+0x154>)
    33f6:	e010      	b.n	341a <uart_nrfx_configure+0xea>
	switch (baudrate) {
    33f8:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    33fc:	d037      	beq.n	346e <uart_nrfx_configure+0x13e>
    33fe:	d807      	bhi.n	3410 <uart_nrfx_configure+0xe0>
    3400:	4e21      	ldr	r6, [pc, #132]	; (3488 <uart_nrfx_configure+0x158>)
    3402:	42b3      	cmp	r3, r6
    3404:	d035      	beq.n	3472 <uart_nrfx_configure+0x142>
    3406:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    340a:	d1b9      	bne.n	3380 <uart_nrfx_configure+0x50>
		nrf_baudrate = NRF_UART_BAUDRATE_460800;
    340c:	4b1f      	ldr	r3, [pc, #124]	; (348c <uart_nrfx_configure+0x15c>)
    340e:	e004      	b.n	341a <uart_nrfx_configure+0xea>
	switch (baudrate) {
    3410:	4e1f      	ldr	r6, [pc, #124]	; (3490 <uart_nrfx_configure+0x160>)
    3412:	42b3      	cmp	r3, r6
    3414:	d1b4      	bne.n	3380 <uart_nrfx_configure+0x50>
		nrf_baudrate = NRF_UART_BAUDRATE_1000000;
    3416:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    341a:	4e1e      	ldr	r6, [pc, #120]	; (3494 <uart_nrfx_configure+0x164>)
                    | (uint32_t)p_cfg->stop
    341c:	433a      	orrs	r2, r7
                    | (uint32_t)p_cfg->hwfc;
    341e:	432c      	orrs	r4, r5
    3420:	4322      	orrs	r2, r4
    p_reg->BAUDRATE = baudrate;
    3422:	f8c6 3524 	str.w	r3, [r6, #1316]	; 0x524
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    3426:	f8c6 256c 	str.w	r2, [r6, #1388]	; 0x56c
		return -ENOTSUP;
	}

	nrf_uart_configure(uart0_addr, &uart_cfg);

	get_dev_data(dev)->uart_config = *cfg;
    342a:	6903      	ldr	r3, [r0, #16]
    342c:	c903      	ldmia	r1, {r0, r1}
    342e:	e883 0003 	stmia.w	r3, {r0, r1}

	return 0;
    3432:	2000      	movs	r0, #0
}
    3434:	bdf0      	pop	{r4, r5, r6, r7, pc}
		nrf_baudrate = NRF_UART_BAUDRATE_38400;
    3436:	4b18      	ldr	r3, [pc, #96]	; (3498 <uart_nrfx_configure+0x168>)
    3438:	e7ef      	b.n	341a <uart_nrfx_configure+0xea>
		nrf_baudrate = NRF_UART_BAUDRATE_9600;
    343a:	4b18      	ldr	r3, [pc, #96]	; (349c <uart_nrfx_configure+0x16c>)
    343c:	e7ed      	b.n	341a <uart_nrfx_configure+0xea>
		nrf_baudrate = NRF_UART_BAUDRATE_1200;
    343e:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    3442:	e7ea      	b.n	341a <uart_nrfx_configure+0xea>
		nrf_baudrate = 0x00014000;
    3444:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    3448:	e7e7      	b.n	341a <uart_nrfx_configure+0xea>
	switch (baudrate) {
    344a:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    344e:	e7e4      	b.n	341a <uart_nrfx_configure+0xea>
		nrf_baudrate = NRF_UART_BAUDRATE_2400;
    3450:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    3454:	e7e1      	b.n	341a <uart_nrfx_configure+0xea>
		nrf_baudrate = NRF_UART_BAUDRATE_28800;
    3456:	4b12      	ldr	r3, [pc, #72]	; (34a0 <uart_nrfx_configure+0x170>)
    3458:	e7df      	b.n	341a <uart_nrfx_configure+0xea>
		nrf_baudrate = NRF_UART_BAUDRATE_14400;
    345a:	f44f 136c 	mov.w	r3, #3866624	; 0x3b0000
    345e:	e7dc      	b.n	341a <uart_nrfx_configure+0xea>
		nrf_baudrate = NRF_UART_BAUDRATE_230400;
    3460:	4b10      	ldr	r3, [pc, #64]	; (34a4 <uart_nrfx_configure+0x174>)
    3462:	e7da      	b.n	341a <uart_nrfx_configure+0xea>
		nrf_baudrate = NRF_UART_BAUDRATE_76800;
    3464:	4b10      	ldr	r3, [pc, #64]	; (34a8 <uart_nrfx_configure+0x178>)
    3466:	e7d8      	b.n	341a <uart_nrfx_configure+0xea>
		nrf_baudrate = NRF_UART_BAUDRATE_56000;
    3468:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    346c:	e7d5      	b.n	341a <uart_nrfx_configure+0xea>
		nrf_baudrate = NRF_UART_BAUDRATE_921600;
    346e:	4b0f      	ldr	r3, [pc, #60]	; (34ac <uart_nrfx_configure+0x17c>)
    3470:	e7d3      	b.n	341a <uart_nrfx_configure+0xea>
		nrf_baudrate = NRF_UART_BAUDRATE_250000;
    3472:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    3476:	e7d0      	b.n	341a <uart_nrfx_configure+0xea>
    3478:	0013b000 	.word	0x0013b000
    347c:	004ea000 	.word	0x004ea000
    3480:	00ebf000 	.word	0x00ebf000
    3484:	01d7e000 	.word	0x01d7e000
    3488:	0003d090 	.word	0x0003d090
    348c:	075f7000 	.word	0x075f7000
    3490:	000f4240 	.word	0x000f4240
    3494:	40002000 	.word	0x40002000
    3498:	009d5000 	.word	0x009d5000
    349c:	00275000 	.word	0x00275000
    34a0:	0075f000 	.word	0x0075f000
    34a4:	03afb000 	.word	0x03afb000
    34a8:	013a9000 	.word	0x013a9000
    34ac:	0ebed000 	.word	0x0ebed000

000034b0 <uart_nrfx_poll_out>:
{
    34b0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    34b2:	460e      	mov	r6, r1
	if (!k_is_in_isr()) {
    34b4:	f003 f978 	bl	67a8 <k_is_in_isr>
    34b8:	4d19      	ldr	r5, [pc, #100]	; (3520 <uart_nrfx_poll_out+0x70>)
    34ba:	bb70      	cbnz	r0, 351a <uart_nrfx_poll_out+0x6a>
    34bc:	2464      	movs	r4, #100	; 0x64
    34be:	2701      	movs	r7, #1
    34c0:	f3bf 8f5b 	dmb	ish
    34c4:	e855 3f00 	ldrex	r3, [r5]
    34c8:	2b00      	cmp	r3, #0
    34ca:	d103      	bne.n	34d4 <uart_nrfx_poll_out+0x24>
    34cc:	e845 7200 	strex	r2, r7, [r5]
    34d0:	2a00      	cmp	r2, #0
    34d2:	d1f7      	bne.n	34c4 <uart_nrfx_poll_out+0x14>
    34d4:	f3bf 8f5b 	dmb	ish
		while (atomic_cas((atomic_t *) lock,
    34d8:	d007      	beq.n	34ea <uart_nrfx_poll_out+0x3a>
	return z_impl_k_sleep(timeout);
    34da:	2021      	movs	r0, #33	; 0x21
    34dc:	2100      	movs	r1, #0
    34de:	3c01      	subs	r4, #1
    34e0:	f001 fac0 	bl	4a64 <z_impl_k_sleep>
			if (--safety_cnt == 0) {
    34e4:	f014 04ff 	ands.w	r4, r4, #255	; 0xff
    34e8:	d1ea      	bne.n	34c0 <uart_nrfx_poll_out+0x10>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    34ea:	4c0e      	ldr	r4, [pc, #56]	; (3524 <uart_nrfx_poll_out+0x74>)
    34ec:	2200      	movs	r2, #0
    34ee:	6022      	str	r2, [r4, #0]
    34f0:	6822      	ldr	r2, [r4, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    34f2:	4a0d      	ldr	r2, [pc, #52]	; (3528 <uart_nrfx_poll_out+0x78>)
    34f4:	2101      	movs	r1, #1
    34f6:	6011      	str	r1, [r2, #0]
    p_reg->TXD = txd;
    34f8:	f8c2 6514 	str.w	r6, [r2, #1300]	; 0x514
    34fc:	f44f 767a 	mov.w	r6, #1000	; 0x3e8
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3500:	6823      	ldr	r3, [r4, #0]
	NRFX_WAIT_FOR(event_txdrdy_check(), 1000, 1, res);
    3502:	b923      	cbnz	r3, 350e <uart_nrfx_poll_out+0x5e>
    3504:	2001      	movs	r0, #1
    3506:	f003 f8e9 	bl	66dc <nrfx_busy_wait>
    350a:	3e01      	subs	r6, #1
    350c:	d1f8      	bne.n	3500 <uart_nrfx_poll_out+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    350e:	4b07      	ldr	r3, [pc, #28]	; (352c <uart_nrfx_poll_out+0x7c>)
    3510:	2201      	movs	r2, #1
    3512:	601a      	str	r2, [r3, #0]
	*lock = 0;
    3514:	2300      	movs	r3, #0
    3516:	602b      	str	r3, [r5, #0]
}
    3518:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		*lock = 1;
    351a:	2301      	movs	r3, #1
    351c:	602b      	str	r3, [r5, #0]
    351e:	e7e4      	b.n	34ea <uart_nrfx_poll_out+0x3a>
    3520:	20000538 	.word	0x20000538
    3524:	4000211c 	.word	0x4000211c
    3528:	40002008 	.word	0x40002008
    352c:	4000200c 	.word	0x4000200c

00003530 <nrf_gpio_pin_set>:
    *p_pin = pin_number & 0x1F;
    3530:	f000 011f 	and.w	r1, r0, #31
    return pin_number >> 5;
    3534:	0940      	lsrs	r0, r0, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3536:	2801      	cmp	r0, #1
        case 1: return NRF_P1;
    3538:	4b04      	ldr	r3, [pc, #16]	; (354c <nrf_gpio_pin_set+0x1c>)
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    353a:	f04f 0201 	mov.w	r2, #1
        case 1: return NRF_P1;
    353e:	bf18      	it	ne
    3540:	f04f 43a0 	movne.w	r3, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    3544:	408a      	lsls	r2, r1
    p_reg->OUTSET = set_mask;
    3546:	f8c3 2508 	str.w	r2, [r3, #1288]	; 0x508
}
    354a:	4770      	bx	lr
    354c:	50000300 	.word	0x50000300

00003550 <uart_nrfx_init>:
 * @param dev UART device struct
 *
 * @return 0 on success
 */
static int uart_nrfx_init(const struct device *dev)
{
    3550:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    p_reg->ENABLE = UART_ENABLE_ENABLE_Disabled;
    3552:	4c19      	ldr	r4, [pc, #100]	; (35b8 <uart_nrfx_init+0x68>)
    3554:	2300      	movs	r3, #0
    3556:	4605      	mov	r5, r0
    3558:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
        nrf_gpio_pin_set(pin_number);
    355c:	2006      	movs	r0, #6
    355e:	f7ff ffe7 	bl	3530 <nrf_gpio_pin_set>
    reg->PIN_CNF[pin_number] = cnf;
    3562:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000

	/* Setting default height state of the TX PIN to avoid glitches
	 * on the line during peripheral activation/deactivation.
	 */
	nrf_gpio_pin_write(TX_PIN, 1);
	nrf_gpio_cfg_output(TX_PIN);
    3566:	2006      	movs	r0, #6
    3568:	f003 f8af 	bl	66ca <nrf_gpio_cfg_output>
    356c:	270c      	movs	r7, #12
    p_reg->PSEL.RXD = pselrxd;
    356e:	2308      	movs	r3, #8
    3570:	f8c6 7720 	str.w	r7, [r6, #1824]	; 0x720
    3574:	f8c4 3514 	str.w	r3, [r4, #1300]	; 0x514
    p_reg->PSEL.TXD = pseltxd;
    3578:	2306      	movs	r3, #6
    357a:	f8c4 350c 	str.w	r3, [r4, #1292]	; 0x50c
        nrf_gpio_pin_set(pin_number);
    357e:	2005      	movs	r0, #5
    3580:	f7ff ffd6 	bl	3530 <nrf_gpio_pin_set>
	if (HAS_PROP(rts_pin)) {
		/* Setting default height state of the RTS PIN to avoid glitches
		 * on the line during peripheral activation/deactivation.
		 */
		nrf_gpio_pin_write(RTS_PIN, 1);
		nrf_gpio_cfg_output(RTS_PIN);
    3584:	2005      	movs	r0, #5
    3586:	f003 f8a0 	bl	66ca <nrf_gpio_cfg_output>
    p_reg->PSEL.RTS = pselrts;
    358a:	2305      	movs	r3, #5
    reg->PIN_CNF[pin_number] = cnf;
    358c:	f8c6 771c 	str.w	r7, [r6, #1820]	; 0x71c
    3590:	f8c4 3508 	str.w	r3, [r4, #1288]	; 0x508
    p_reg->PSEL.CTS = pselcts;
    3594:	2307      	movs	r3, #7
	}

	nrf_uart_hwfc_pins_set(uart0_addr, RTS_PIN, CTS_PIN);

	/* Set initial configuration */
	err = uart_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
    3596:	6929      	ldr	r1, [r5, #16]
    3598:	f8c4 3510 	str.w	r3, [r4, #1296]	; 0x510
    359c:	4628      	mov	r0, r5
    359e:	f7ff fec7 	bl	3330 <uart_nrfx_configure>
	if (err) {
    35a2:	b938      	cbnz	r0, 35b4 <uart_nrfx_init+0x64>
    p_reg->ENABLE = UART_ENABLE_ENABLE_Enabled;
    35a4:	2304      	movs	r3, #4
    35a6:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    35aa:	4b04      	ldr	r3, [pc, #16]	; (35bc <uart_nrfx_init+0x6c>)
    35ac:	6018      	str	r0, [r3, #0]
    35ae:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    35b0:	2301      	movs	r3, #1
    35b2:	6023      	str	r3, [r4, #0]
#if HW_FLOW_CONTROL_AVAILABLE
	k_timer_init(&uart0_cb.tx_timeout_timer, tx_timeout, NULL);
#endif
#endif
	return 0;
}
    35b4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    35b6:	bf00      	nop
    35b8:	40002000 	.word	0x40002000
    35bc:	40002108 	.word	0x40002108

000035c0 <k_sys_fatal_error_handler>:

extern void sys_arch_reboot(int type);

void k_sys_fatal_error_handler(unsigned int reason,
			       const z_arch_esf_t *esf)
{
    35c0:	b508      	push	{r3, lr}
	z_impl_log_panic();
    35c2:	f7fd ff35 	bl	1430 <z_impl_log_panic>
    35c6:	4b06      	ldr	r3, [pc, #24]	; (35e0 <k_sys_fatal_error_handler+0x20>)
    35c8:	4906      	ldr	r1, [pc, #24]	; (35e4 <k_sys_fatal_error_handler+0x24>)
	defined(CONFIG_SPM_SERVICE_NS_HANDLER_FROM_SPM_FAULT)
	z_spm_ns_fatal_error_handler();
#endif

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
    35ca:	4807      	ldr	r0, [pc, #28]	; (35e8 <k_sys_fatal_error_handler+0x28>)
    35cc:	1ac9      	subs	r1, r1, r3
    35ce:	08c9      	lsrs	r1, r1, #3
    35d0:	0189      	lsls	r1, r1, #6
    35d2:	f041 0101 	orr.w	r1, r1, #1
    35d6:	f002 fc70 	bl	5eba <log_0>
		sys_arch_reboot(0);
    35da:	2000      	movs	r0, #0
    35dc:	f7ff fbe2 	bl	2da4 <sys_arch_reboot>
		for (;;) {
			/* Spin endlessly */
		}
	}

	CODE_UNREACHABLE;
    35e0:	00007078 	.word	0x00007078
    35e4:	00007080 	.word	0x00007080
    35e8:	0000789f 	.word	0x0000789f

000035ec <nrf52_errata_136>:
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    35ec:	4b03      	ldr	r3, [pc, #12]	; (35fc <nrf52_errata_136+0x10>)
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    35ee:	6818      	ldr	r0, [r3, #0]
                }
            }
        #endif
        return false;
    #endif
}
    35f0:	f1a0 030d 	sub.w	r3, r0, #13
    35f4:	4258      	negs	r0, r3
    35f6:	4158      	adcs	r0, r3
    35f8:	4770      	bx	lr
    35fa:	bf00      	nop
    35fc:	10000130 	.word	0x10000130

00003600 <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    3600:	4a02      	ldr	r2, [pc, #8]	; (360c <nvmc_wait+0xc>)
    3602:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    3606:	2b00      	cmp	r3, #0
    3608:	d0fb      	beq.n	3602 <nvmc_wait+0x2>
}
    360a:	4770      	bx	lr
    360c:	4001e000 	.word	0x4001e000

00003610 <SystemInit>:
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
}

void SystemInit(void)
{
    3610:	b510      	push	{r4, lr}
    #endif

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
    3612:	f7ff ffeb 	bl	35ec <nrf52_errata_136>
    3616:	b140      	cbz	r0, 362a <SystemInit+0x1a>
            NRF_CLOCK->EVENTS_DONE = 0;
    3618:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    361c:	2200      	movs	r2, #0
    361e:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    3622:	f8c3 2110 	str.w	r2, [r3, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    3626:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    #endif

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
    362a:	f7ff ffdf 	bl	35ec <nrf52_errata_136>
    362e:	2800      	cmp	r0, #0
    3630:	d046      	beq.n	36c0 <SystemInit+0xb0>
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    3632:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
    3636:	4b4b      	ldr	r3, [pc, #300]	; (3764 <SystemInit+0x154>)
    3638:	f8d2 1404 	ldr.w	r1, [r2, #1028]	; 0x404
    363c:	f8c3 1520 	str.w	r1, [r3, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    3640:	f8d2 1408 	ldr.w	r1, [r2, #1032]	; 0x408
    3644:	f8c3 1524 	str.w	r1, [r3, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    3648:	f8d2 140c 	ldr.w	r1, [r2, #1036]	; 0x40c
    364c:	f8c3 1528 	str.w	r1, [r3, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    3650:	f8d2 1410 	ldr.w	r1, [r2, #1040]	; 0x410
    3654:	f8c3 152c 	str.w	r1, [r3, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    3658:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
    365c:	f8c3 1530 	str.w	r1, [r3, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    3660:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    3664:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    3668:	f8d2 141c 	ldr.w	r1, [r2, #1052]	; 0x41c
    366c:	f8c3 1540 	str.w	r1, [r3, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    3670:	f8d2 1420 	ldr.w	r1, [r2, #1056]	; 0x420
    3674:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    3678:	f8d2 1424 	ldr.w	r1, [r2, #1060]	; 0x424
    367c:	f8c3 1548 	str.w	r1, [r3, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    3680:	f8d2 1428 	ldr.w	r1, [r2, #1064]	; 0x428
    3684:	f8c3 154c 	str.w	r1, [r3, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    3688:	f8d2 142c 	ldr.w	r1, [r2, #1068]	; 0x42c
    368c:	f8c3 1550 	str.w	r1, [r3, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    3690:	f8d2 1430 	ldr.w	r1, [r2, #1072]	; 0x430
    3694:	f8c3 1554 	str.w	r1, [r3, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    3698:	f8d2 1434 	ldr.w	r1, [r2, #1076]	; 0x434
    369c:	f8c3 1560 	str.w	r1, [r3, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    36a0:	f8d2 1438 	ldr.w	r1, [r2, #1080]	; 0x438
    36a4:	f8c3 1564 	str.w	r1, [r3, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    36a8:	f8d2 143c 	ldr.w	r1, [r2, #1084]	; 0x43c
    36ac:	f8c3 1568 	str.w	r1, [r3, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    36b0:	f8d2 1440 	ldr.w	r1, [r2, #1088]	; 0x440
    36b4:	f8c3 156c 	str.w	r1, [r3, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    36b8:	f8d2 2444 	ldr.w	r2, [r2, #1092]	; 0x444
    36bc:	f8c3 2570 	str.w	r2, [r3, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
    36c0:	f7ff ff94 	bl	35ec <nrf52_errata_136>
    36c4:	b148      	cbz	r0, 36da <SystemInit+0xca>
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    36c6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    36ca:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    36ce:	07d2      	lsls	r2, r2, #31
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    36d0:	bf44      	itt	mi
    36d2:	f06f 0201 	mvnmi.w	r2, #1
    36d6:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400
        #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    36da:	4b23      	ldr	r3, [pc, #140]	; (3768 <SystemInit+0x158>)
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    36dc:	681b      	ldr	r3, [r3, #0]
    36de:	2b0d      	cmp	r3, #13
    36e0:	d10e      	bne.n	3700 <SystemInit+0xf0>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    36e2:	4b22      	ldr	r3, [pc, #136]	; (376c <SystemInit+0x15c>)
    36e4:	681b      	ldr	r3, [r3, #0]
            {
                switch(var2)
    36e6:	2b02      	cmp	r3, #2
    36e8:	d802      	bhi.n	36f0 <SystemInit+0xe0>
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_errata_249())
    36ea:	4a21      	ldr	r2, [pc, #132]	; (3770 <SystemInit+0x160>)
    36ec:	5cd3      	ldrb	r3, [r2, r3]
    36ee:	b13b      	cbz	r3, 3700 <SystemInit+0xf0>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    36f0:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    36f4:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    36f8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    36fc:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    3700:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    3704:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    3708:	2a00      	cmp	r2, #0
    370a:	db03      	blt.n	3714 <SystemInit+0x104>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    370c:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    3710:	2b00      	cmp	r3, #0
    3712:	da22      	bge.n	375a <SystemInit+0x14a>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    3714:	4917      	ldr	r1, [pc, #92]	; (3774 <SystemInit+0x164>)
    3716:	2301      	movs	r3, #1
    3718:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    371c:	f7ff ff70 	bl	3600 <nvmc_wait>
            nvmc_config(NVMC_CONFIG_WEN_Wen);
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    3720:	f04f 2010 	mov.w	r0, #268439552	; 0x10001000
    3724:	2412      	movs	r4, #18
    3726:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
            nvmc_wait();
    372a:	f7ff ff69 	bl	3600 <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    372e:	f8c0 4204 	str.w	r4, [r0, #516]	; 0x204
            nvmc_wait();
    3732:	f7ff ff65 	bl	3600 <nvmc_wait>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    3736:	2300      	movs	r3, #0
    3738:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    373c:	f7ff ff60 	bl	3600 <nvmc_wait>
    3740:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    3744:	490c      	ldr	r1, [pc, #48]	; (3778 <SystemInit+0x168>)
    3746:	4b0d      	ldr	r3, [pc, #52]	; (377c <SystemInit+0x16c>)
    3748:	68ca      	ldr	r2, [r1, #12]
    374a:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    374e:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    3750:	60cb      	str	r3, [r1, #12]
    3752:	f3bf 8f4f 	dsb	sy
    __NOP();
    3756:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    3758:	e7fd      	b.n	3756 <SystemInit+0x146>
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    375a:	4b09      	ldr	r3, [pc, #36]	; (3780 <SystemInit+0x170>)
    375c:	4a09      	ldr	r2, [pc, #36]	; (3784 <SystemInit+0x174>)
    375e:	601a      	str	r2, [r3, #0]
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
}
    3760:	bd10      	pop	{r4, pc}
    3762:	bf00      	nop
    3764:	4000c000 	.word	0x4000c000
    3768:	10000130 	.word	0x10000130
    376c:	10000134 	.word	0x10000134
    3770:	000078bc 	.word	0x000078bc
    3774:	4001e000 	.word	0x4001e000
    3778:	e000ed00 	.word	0xe000ed00
    377c:	05fa0004 	.word	0x05fa0004
    3780:	20000040 	.word	0x20000040
    3784:	03d09000 	.word	0x03d09000

00003788 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    3788:	4b05      	ldr	r3, [pc, #20]	; (37a0 <nrfx_clock_init+0x18>)
    378a:	791a      	ldrb	r2, [r3, #4]
    378c:	b92a      	cbnz	r2, 379a <nrfx_clock_init+0x12>
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    }
    else
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
    378e:	715a      	strb	r2, [r3, #5]
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    3790:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    3792:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    3794:	711a      	strb	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    3796:	4803      	ldr	r0, [pc, #12]	; (37a4 <nrfx_clock_init+0x1c>)
    3798:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    379a:	4803      	ldr	r0, [pc, #12]	; (37a8 <nrfx_clock_init+0x20>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    379c:	4770      	bx	lr
    379e:	bf00      	nop
    37a0:	2000053c 	.word	0x2000053c
    37a4:	0bad0000 	.word	0x0bad0000
    37a8:	0bad000c 	.word	0x0bad000c

000037ac <nrfx_clock_start>:
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    37ac:	b110      	cbz	r0, 37b4 <nrfx_clock_start+0x8>
    37ae:	2801      	cmp	r0, #1
    37b0:	d00b      	beq.n	37ca <nrfx_clock_start+0x1e>
    37b2:	4770      	bx	lr
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    37b4:	4b0a      	ldr	r3, [pc, #40]	; (37e0 <nrfx_clock_start+0x34>)
    37b6:	6018      	str	r0, [r3, #0]
    37b8:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    37ba:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    37be:	2202      	movs	r2, #2
    37c0:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    37c4:	2201      	movs	r2, #1
    37c6:	609a      	str	r2, [r3, #8]
}
    37c8:	4770      	bx	lr
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    37ca:	4b06      	ldr	r3, [pc, #24]	; (37e4 <nrfx_clock_start+0x38>)
    37cc:	2200      	movs	r2, #0
    37ce:	601a      	str	r2, [r3, #0]
    37d0:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    37d2:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    37d6:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    37da:	6018      	str	r0, [r3, #0]
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    37dc:	4770      	bx	lr
    37de:	bf00      	nop
    37e0:	40000104 	.word	0x40000104
    37e4:	40000100 	.word	0x40000100

000037e8 <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
    37e8:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    37ea:	b110      	cbz	r0, 37f2 <nrfx_clock_stop+0xa>
    37ec:	2801      	cmp	r0, #1
    37ee:	d018      	beq.n	3822 <nrfx_clock_stop+0x3a>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    37f0:	bd38      	pop	{r3, r4, r5, pc}
    p_reg->INTENCLR = mask;
    37f2:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    37f6:	2202      	movs	r2, #2
    37f8:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    37fc:	4a17      	ldr	r2, [pc, #92]	; (385c <nrfx_clock_stop+0x74>)
    37fe:	6010      	str	r0, [r2, #0]
    3800:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3802:	4a17      	ldr	r2, [pc, #92]	; (3860 <nrfx_clock_stop+0x78>)
    3804:	2101      	movs	r1, #1
    3806:	6011      	str	r1, [r2, #0]
    3808:	f242 7510 	movw	r5, #10000	; 0x2710
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    380c:	461c      	mov	r4, r3
    380e:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
    3812:	03db      	lsls	r3, r3, #15
    3814:	d5ec      	bpl.n	37f0 <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    3816:	2001      	movs	r0, #1
    3818:	f002 ff60 	bl	66dc <nrfx_busy_wait>
    381c:	3d01      	subs	r5, #1
    381e:	d1f6      	bne.n	380e <nrfx_clock_stop+0x26>
    3820:	e7e6      	b.n	37f0 <nrfx_clock_stop+0x8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3822:	4b10      	ldr	r3, [pc, #64]	; (3864 <nrfx_clock_stop+0x7c>)
    p_reg->INTENCLR = mask;
    3824:	f04f 4480 	mov.w	r4, #1073741824	; 0x40000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3828:	2200      	movs	r2, #0
    p_reg->INTENCLR = mask;
    382a:	f8c4 0308 	str.w	r0, [r4, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    382e:	601a      	str	r2, [r3, #0]
    3830:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3832:	4b0d      	ldr	r3, [pc, #52]	; (3868 <nrfx_clock_stop+0x80>)
    3834:	f242 7510 	movw	r5, #10000	; 0x2710
    3838:	6018      	str	r0, [r3, #0]
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    383a:	f8d4 340c 	ldr.w	r3, [r4, #1036]	; 0x40c
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    383e:	f8d4 240c 	ldr.w	r2, [r4, #1036]	; 0x40c
    3842:	03d2      	lsls	r2, r2, #15
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    3844:	f003 0301 	and.w	r3, r3, #1
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    3848:	d5d2      	bpl.n	37f0 <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
    384a:	2b00      	cmp	r3, #0
    384c:	d0d0      	beq.n	37f0 <nrfx_clock_stop+0x8>
    384e:	2001      	movs	r0, #1
    3850:	f002 ff44 	bl	66dc <nrfx_busy_wait>
    3854:	3d01      	subs	r5, #1
    3856:	d1f0      	bne.n	383a <nrfx_clock_stop+0x52>
    3858:	e7ca      	b.n	37f0 <nrfx_clock_stop+0x8>
    385a:	bf00      	nop
    385c:	40000104 	.word	0x40000104
    3860:	4000000c 	.word	0x4000000c
    3864:	40000100 	.word	0x40000100
    3868:	40000004 	.word	0x40000004

0000386c <nrfx_clock_calibration_start>:
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    386c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3870:	f8d3 240c 	ldr.w	r2, [r3, #1036]	; 0x40c
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    3874:	f8d3 140c 	ldr.w	r1, [r3, #1036]	; 0x40c
    3878:	03c8      	lsls	r0, r1, #15
    387a:	d516      	bpl.n	38aa <nrfx_clock_calibration_start+0x3e>
    if (!nrfx_clock_is_running(NRF_CLOCK_DOMAIN_HFCLK, &clk_src))
    {
        return NRFX_ERROR_INVALID_STATE;
    }

    if (clk_src != NRF_CLOCK_HFCLK_HIGH_ACCURACY)
    387c:	07d1      	lsls	r1, r2, #31
    387e:	d514      	bpl.n	38aa <nrfx_clock_calibration_start+0x3e>
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    3880:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
    3884:	03d2      	lsls	r2, r2, #15
    3886:	d510      	bpl.n	38aa <nrfx_clock_calibration_start+0x3e>
    if (!nrfx_clock_is_running(NRF_CLOCK_DOMAIN_LFCLK, NULL))
    {
        return NRFX_ERROR_INVALID_STATE;
    }

    if (m_clock_cb.cal_state == CAL_STATE_IDLE)
    3888:	4a0a      	ldr	r2, [pc, #40]	; (38b4 <nrfx_clock_calibration_start+0x48>)
    388a:	7951      	ldrb	r1, [r2, #5]
    388c:	f001 00ff 	and.w	r0, r1, #255	; 0xff
    3890:	b969      	cbnz	r1, 38ae <nrfx_clock_calibration_start+0x42>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3892:	4909      	ldr	r1, [pc, #36]	; (38b8 <nrfx_clock_calibration_start+0x4c>)
    3894:	6008      	str	r0, [r1, #0]
    3896:	6809      	ldr	r1, [r1, #0]
    nrfx_err_t err_code = NRFX_SUCCESS;
    3898:	4808      	ldr	r0, [pc, #32]	; (38bc <nrfx_clock_calibration_start+0x50>)
    p_reg->INTENSET = mask;
    389a:	2108      	movs	r1, #8
    389c:	f8c3 1304 	str.w	r1, [r3, #772]	; 0x304
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_DONE);
        nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_DONE_MASK);
        m_clock_cb.cal_state = CAL_STATE_CAL;
    38a0:	2301      	movs	r3, #1
    38a2:	7153      	strb	r3, [r2, #5]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    38a4:	4a06      	ldr	r2, [pc, #24]	; (38c0 <nrfx_clock_calibration_start+0x54>)
    38a6:	6013      	str	r3, [r2, #0]
}
    38a8:	4770      	bx	lr
        return NRFX_ERROR_INVALID_STATE;
    38aa:	4806      	ldr	r0, [pc, #24]	; (38c4 <nrfx_clock_calibration_start+0x58>)
    38ac:	4770      	bx	lr
#endif
        nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_CAL);
    }
    else
    {
        err_code = NRFX_ERROR_BUSY;
    38ae:	4806      	ldr	r0, [pc, #24]	; (38c8 <nrfx_clock_calibration_start+0x5c>)

    NRFX_LOG_WARNING("Function: %s, error code: %s.",
                     __func__,
                     NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    38b0:	4770      	bx	lr
    38b2:	bf00      	nop
    38b4:	2000053c 	.word	0x2000053c
    38b8:	4000010c 	.word	0x4000010c
    38bc:	0bad0000 	.word	0x0bad0000
    38c0:	40000010 	.word	0x40000010
    38c4:	0bad0005 	.word	0x0bad0005
    38c8:	0bad000b 	.word	0x0bad000b

000038cc <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    38cc:	4b1f      	ldr	r3, [pc, #124]	; (394c <nrfx_power_clock_irq_handler+0x80>)
    38ce:	681a      	ldr	r2, [r3, #0]
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    38d0:	b510      	push	{r4, lr}
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    38d2:	b152      	cbz	r2, 38ea <nrfx_power_clock_irq_handler+0x1e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    38d4:	2000      	movs	r0, #0
    38d6:	6018      	str	r0, [r3, #0]
    38d8:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    38da:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    38de:	2201      	movs	r2, #1
    38e0:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    38e4:	4b1a      	ldr	r3, [pc, #104]	; (3950 <nrfx_power_clock_irq_handler+0x84>)
    38e6:	681b      	ldr	r3, [r3, #0]
    38e8:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    38ea:	4b1a      	ldr	r3, [pc, #104]	; (3954 <nrfx_power_clock_irq_handler+0x88>)
    38ec:	681a      	ldr	r2, [r3, #0]
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    38ee:	b15a      	cbz	r2, 3908 <nrfx_power_clock_irq_handler+0x3c>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    38f0:	2200      	movs	r2, #0
    38f2:	601a      	str	r2, [r3, #0]
    38f4:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    38f6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    38fa:	2202      	movs	r2, #2
    38fc:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        else
#endif
        {
            // After the LF clock external source start invoke user callback.
            nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK);
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    3900:	4b13      	ldr	r3, [pc, #76]	; (3950 <nrfx_power_clock_irq_handler+0x84>)
    3902:	2001      	movs	r0, #1
    3904:	681b      	ldr	r3, [r3, #0]
    3906:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    3908:	4b13      	ldr	r3, [pc, #76]	; (3958 <nrfx_power_clock_irq_handler+0x8c>)
    390a:	681a      	ldr	r2, [r3, #0]
        }
    }

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
#if NRF_CLOCK_HAS_CALIBRATION_TIMER
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO))
    390c:	b15a      	cbz	r2, 3926 <nrfx_power_clock_irq_handler+0x5a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    390e:	2200      	movs	r2, #0
    3910:	601a      	str	r2, [r3, #0]
    3912:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    3914:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3918:	2210      	movs	r2, #16
    391a:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_CTTO");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_CTTO);
    391e:	4b0c      	ldr	r3, [pc, #48]	; (3950 <nrfx_power_clock_irq_handler+0x84>)
    3920:	2002      	movs	r0, #2
    3922:	681b      	ldr	r3, [r3, #0]
    3924:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    3926:	4b0d      	ldr	r3, [pc, #52]	; (395c <nrfx_power_clock_irq_handler+0x90>)
    3928:	681a      	ldr	r2, [r3, #0]
    }
#endif // NRF_CLOCK_HAS_CALIBRATION_TIMER

    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_DONE))
    392a:	b172      	cbz	r2, 394a <nrfx_power_clock_irq_handler+0x7e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    392c:	2200      	movs	r2, #0
    392e:	601a      	str	r2, [r3, #0]
    3930:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    3932:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3936:	2108      	movs	r1, #8
    3938:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
        *(volatile uint32_t *)0x40000C34 = 0x00000000;
#endif
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_DONE);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_DONE");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_DONE_MASK);
        m_clock_cb.cal_state = CAL_STATE_IDLE;
    393c:	4b04      	ldr	r3, [pc, #16]	; (3950 <nrfx_power_clock_irq_handler+0x84>)
    393e:	715a      	strb	r2, [r3, #5]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    3940:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_CAL_DONE);
    3944:	681b      	ldr	r3, [r3, #0]
    3946:	2003      	movs	r0, #3
    3948:	4718      	bx	r3
}
    394a:	bd10      	pop	{r4, pc}
    394c:	40000100 	.word	0x40000100
    3950:	2000053c 	.word	0x2000053c
    3954:	40000104 	.word	0x40000104
    3958:	40000110 	.word	0x40000110
    395c:	4000010c 	.word	0x4000010c

00003960 <nrfx_gpiote_channel_free>:
    return m_cb.allocated_channels_mask & (1UL << index);
}

static bool is_app_channel(uint8_t index)
{
    return NRFX_GPIOTE_APP_CHANNELS_MASK & (1UL << index);
    3960:	2301      	movs	r3, #1
    3962:	fa03 f000 	lsl.w	r0, r3, r0

nrfx_err_t nrfx_gpiote_channel_free(uint8_t channel)
{
    nrfx_err_t err_code = NRFX_SUCCESS;

    if (!is_app_channel(channel))
    3966:	f010 0fff 	tst.w	r0, #255	; 0xff
    396a:	d012      	beq.n	3992 <nrfx_gpiote_channel_free+0x32>
	__asm__ volatile(
    396c:	f04f 0320 	mov.w	r3, #32
    3970:	f3ef 8111 	mrs	r1, BASEPRI
    3974:	f383 8811 	msr	BASEPRI, r3
    3978:	f3bf 8f6f 	isb	sy
    m_cb.allocated_channels_mask &= ~(1UL << index);
    397c:	4a06      	ldr	r2, [pc, #24]	; (3998 <nrfx_gpiote_channel_free+0x38>)
    397e:	6d93      	ldr	r3, [r2, #88]	; 0x58
    3980:	ea23 0000 	bic.w	r0, r3, r0
    3984:	6590      	str	r0, [r2, #88]	; 0x58
	__asm__ volatile(
    3986:	f381 8811 	msr	BASEPRI, r1
    398a:	f3bf 8f6f 	isb	sy
    398e:	4803      	ldr	r0, [pc, #12]	; (399c <nrfx_gpiote_channel_free+0x3c>)
    3990:	4770      	bx	lr
    {
        err_code = NRFX_ERROR_INVALID_PARAM;
    3992:	4803      	ldr	r0, [pc, #12]	; (39a0 <nrfx_gpiote_channel_free+0x40>)
        NRFX_CRITICAL_SECTION_EXIT();
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    3994:	4770      	bx	lr
    3996:	bf00      	nop
    3998:	20000544 	.word	0x20000544
    399c:	0bad0000 	.word	0x0bad0000
    39a0:	0bad0004 	.word	0x0bad0004

000039a4 <nrfx_gpiote_channel_alloc>:

nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel)
{
    39a4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    39a8:	4605      	mov	r5, r0
    return m_cb.allocated_channels_mask & (1UL << index);
    39aa:	f8df e060 	ldr.w	lr, [pc, #96]	; 3a0c <nrfx_gpiote_channel_alloc+0x68>
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    39ae:	4816      	ldr	r0, [pc, #88]	; (3a08 <nrfx_gpiote_channel_alloc+0x64>)
        NRFX_CRITICAL_SECTION_ENTER();
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
        {
            channel_allocated_set(ch_idx);
            *p_channel = ch_idx;
            err_code = NRFX_SUCCESS;
    39b0:	f8df 805c 	ldr.w	r8, [pc, #92]	; 3a10 <nrfx_gpiote_channel_alloc+0x6c>
{
    39b4:	2400      	movs	r4, #0
    uint32_t mask = NRFX_GPIOTE_APP_CHANNELS_MASK;
    39b6:	22ff      	movs	r2, #255	; 0xff
    return m_cb.allocated_channels_mask & (1UL << index);
    39b8:	2601      	movs	r6, #1
    39ba:	b2e3      	uxtb	r3, r4
	__asm__ volatile(
    39bc:	f04f 0120 	mov.w	r1, #32
    39c0:	f3ef 8c11 	mrs	ip, BASEPRI
    39c4:	f381 8811 	msr	BASEPRI, r1
    39c8:	f3bf 8f6f 	isb	sy
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
    39cc:	fa22 f103 	lsr.w	r1, r2, r3
    39d0:	07c9      	lsls	r1, r1, #31
    39d2:	d50a      	bpl.n	39ea <nrfx_gpiote_channel_alloc+0x46>
    return m_cb.allocated_channels_mask & (1UL << index);
    39d4:	f8de 1058 	ldr.w	r1, [lr, #88]	; 0x58
    39d8:	fa06 f703 	lsl.w	r7, r6, r3
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
    39dc:	4239      	tst	r1, r7
    m_cb.allocated_channels_mask |= (1UL << index);
    39de:	bf01      	itttt	eq
    39e0:	4339      	orreq	r1, r7
    39e2:	f8ce 1058 	streq.w	r1, [lr, #88]	; 0x58
            err_code = NRFX_SUCCESS;
    39e6:	4640      	moveq	r0, r8
            *p_channel = ch_idx;
    39e8:	702b      	strbeq	r3, [r5, #0]
	__asm__ volatile(
    39ea:	f38c 8811 	msr	BASEPRI, ip
    39ee:	f3bf 8f6f 	isb	sy
        }
        NRFX_CRITICAL_SECTION_EXIT();

        if (err_code == NRFX_SUCCESS)
    39f2:	4540      	cmp	r0, r8
    39f4:	d005      	beq.n	3a02 <nrfx_gpiote_channel_alloc+0x5e>
        {
            NRFX_LOG_INFO("Allocated channel: %d.", ch_idx);
            break;
        }

        mask &= ~(1UL << ch_idx);
    39f6:	fa06 f303 	lsl.w	r3, r6, r3
    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    39fa:	439a      	bics	r2, r3
    39fc:	f104 0401 	add.w	r4, r4, #1
    3a00:	d1db      	bne.n	39ba <nrfx_gpiote_channel_alloc+0x16>
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    3a02:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    3a06:	bf00      	nop
    3a08:	0bad0002 	.word	0x0bad0002
    3a0c:	20000544 	.word	0x20000544
    3a10:	0bad0000 	.word	0x0bad0000

00003a14 <_DoInit>:
                      _DoInit();                                                                     \
                    }                                                                                \
                  } while (0);                                                                       \
                }

static void _DoInit(void) {
    3a14:	b510      	push	{r4, lr}
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    3a16:	4c11      	ldr	r4, [pc, #68]	; (3a5c <_DoInit+0x48>)
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    3a18:	4a11      	ldr	r2, [pc, #68]	; (3a60 <_DoInit+0x4c>)
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    3a1a:	4912      	ldr	r1, [pc, #72]	; (3a64 <_DoInit+0x50>)
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    3a1c:	2303      	movs	r3, #3
    3a1e:	6123      	str	r3, [r4, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    3a20:	6163      	str	r3, [r4, #20]
  p->aUp[0].pBuffer       = _acUpBuffer;
    3a22:	4b11      	ldr	r3, [pc, #68]	; (3a68 <_DoInit+0x54>)
  p->aUp[0].sName         = "Terminal";
    3a24:	61a2      	str	r2, [r4, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    3a26:	61e3      	str	r3, [r4, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    3a28:	f44f 6380 	mov.w	r3, #1024	; 0x400
    3a2c:	6223      	str	r3, [r4, #32]
  p->aUp[0].RdOff         = 0u;
    3a2e:	2300      	movs	r3, #0
    3a30:	62a3      	str	r3, [r4, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    3a32:	6263      	str	r3, [r4, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    3a34:	62e3      	str	r3, [r4, #44]	; 0x2c
  p->aDown[0].sName         = "Terminal";
    3a36:	6622      	str	r2, [r4, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    3a38:	4a0c      	ldr	r2, [pc, #48]	; (3a6c <_DoInit+0x58>)
    3a3a:	6662      	str	r2, [r4, #100]	; 0x64
  STRCPY((char*)&p->acID[7], "RTT");
    3a3c:	1de0      	adds	r0, r4, #7
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    3a3e:	2210      	movs	r2, #16
    3a40:	66a2      	str	r2, [r4, #104]	; 0x68
  p->aDown[0].RdOff         = 0u;
    3a42:	6723      	str	r3, [r4, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    3a44:	66e3      	str	r3, [r4, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    3a46:	6763      	str	r3, [r4, #116]	; 0x74
  STRCPY((char*)&p->acID[7], "RTT");
    3a48:	f003 f870 	bl	6b2c <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
  STRCPY((char*)&p->acID[0], "SEGGER");
    3a4c:	4908      	ldr	r1, [pc, #32]	; (3a70 <_DoInit+0x5c>)
    3a4e:	4620      	mov	r0, r4
    3a50:	f003 f86c 	bl	6b2c <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
  p->acID[6] = ' ';
    3a54:	2320      	movs	r3, #32
    3a56:	71a3      	strb	r3, [r4, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
}
    3a58:	bd10      	pop	{r4, pc}
    3a5a:	bf00      	nop
    3a5c:	200005a0 	.word	0x200005a0
    3a60:	000078bf 	.word	0x000078bf
    3a64:	000078c8 	.word	0x000078c8
    3a68:	200006c2 	.word	0x200006c2
    3a6c:	200006b2 	.word	0x200006b2
    3a70:	000078cc 	.word	0x000078cc

00003a74 <SEGGER_RTT_WriteSkipNoLock>:
*    (2) For performance reasons this function does not call Init()
*        and may only be called after RTT has been initialized.
*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
*/
#if (RTT_USE_ASM == 0)
unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
    3a74:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  //
  // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough
  //
  pData = (const char *)pBuffer;
  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
  RdOff = pRing->RdOff;
    3a78:	4f23      	ldr	r7, [pc, #140]	; (3b08 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x70>)
    3a7a:	f04f 0b18 	mov.w	fp, #24
unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
    3a7e:	4614      	mov	r4, r2
  RdOff = pRing->RdOff;
    3a80:	fb0b 7200 	mla	r2, fp, r0, r7
unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
    3a84:	4606      	mov	r6, r0
  RdOff = pRing->RdOff;
    3a86:	6a93      	ldr	r3, [r2, #40]	; 0x28
  WrOff = pRing->WrOff;
    3a88:	6a55      	ldr	r5, [r2, #36]	; 0x24
  if (RdOff <= WrOff) {                                 // Case 1), 2) or 3)
    3a8a:	42ab      	cmp	r3, r5
unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
    3a8c:	4688      	mov	r8, r1
  if (RdOff <= WrOff) {                                 // Case 1), 2) or 3)
    3a8e:	d834      	bhi.n	3afa <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x62>
    Avail = pRing->SizeOfBuffer - WrOff - 1u;           // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0)
    3a90:	f8d2 a020 	ldr.w	sl, [r2, #32]
    3a94:	ebaa 0905 	sub.w	r9, sl, r5
    3a98:	f109 32ff 	add.w	r2, r9, #4294967295
    if (Avail >= NumBytes) {                            // Case 1)?
    3a9c:	4294      	cmp	r4, r2
    3a9e:	d811      	bhi.n	3ac4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x2c>
CopyStraight:
      pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
    3aa0:	f04f 0918 	mov.w	r9, #24
    3aa4:	fb06 9309 	mla	r3, r6, r9, r9
    3aa8:	443b      	add	r3, r7
__ssp_bos_icheck3_restrict(memcpy, void *, const void *)
    3aaa:	4622      	mov	r2, r4
    3aac:	6858      	ldr	r0, [r3, #4]
    3aae:	4641      	mov	r1, r8
    3ab0:	4428      	add	r0, r5
    3ab2:	f003 f825 	bl	6b00 <memcpy>
      memcpy((void*)pDst, pData, NumBytes);
      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
      pRing->WrOff = WrOff + NumBytes;
    3ab6:	fb09 7606 	mla	r6, r9, r6, r7
    3aba:	442c      	add	r4, r5
      if (NumBytes) {
        pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF;
        memcpy((void*)pDst, pData + Rem, NumBytes);
      }
      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
      pRing->WrOff = NumBytes;
    3abc:	6274      	str	r4, [r6, #36]	; 0x24
      return 1;
    3abe:	2001      	movs	r0, #1
    if (Avail >= NumBytes) {                           // Case 4)? => If not, we have case 5) (does not fit)
      goto CopyStraight;
    }
  }
  return 0;     // No space in buffer
}
    3ac0:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
    Avail += RdOff;                                     // Space incl. wrap-around
    3ac4:	4413      	add	r3, r2
    if (Avail >= NumBytes) {                            // Case 2? => If not, we have case 3) (does not fit)
    3ac6:	429c      	cmp	r4, r3
    3ac8:	d81b      	bhi.n	3b02 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x6a>
      pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
    3aca:	fb00 bb0b 	mla	fp, r0, fp, fp
    3ace:	44bb      	add	fp, r7
    3ad0:	464a      	mov	r2, r9
    3ad2:	f8db 0004 	ldr.w	r0, [fp, #4]
    3ad6:	442c      	add	r4, r5
    3ad8:	4428      	add	r0, r5
    3ada:	f003 f811 	bl	6b00 <memcpy>
      if (NumBytes) {
    3ade:	ebb4 040a 	subs.w	r4, r4, sl
    3ae2:	d006      	beq.n	3af2 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x5a>
    3ae4:	f8db 0004 	ldr.w	r0, [fp, #4]
    3ae8:	4622      	mov	r2, r4
    3aea:	eb08 0109 	add.w	r1, r8, r9
    3aee:	f003 f807 	bl	6b00 <memcpy>
      pRing->WrOff = NumBytes;
    3af2:	2018      	movs	r0, #24
    3af4:	fb00 7606 	mla	r6, r0, r6, r7
    3af8:	e7e0      	b.n	3abc <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x24>
    Avail = RdOff - WrOff - 1u;
    3afa:	3b01      	subs	r3, #1
    3afc:	1b5b      	subs	r3, r3, r5
    if (Avail >= NumBytes) {                           // Case 4)? => If not, we have case 5) (does not fit)
    3afe:	42a3      	cmp	r3, r4
    3b00:	d2ce      	bcs.n	3aa0 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x8>
  return 0;     // No space in buffer
    3b02:	2000      	movs	r0, #0
    3b04:	e7dc      	b.n	3ac0 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x28>
    3b06:	bf00      	nop
    3b08:	200005a0 	.word	0x200005a0

00003b0c <SEGGER_RTT_HasDataUp>:
unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) {
  SEGGER_RTT_BUFFER_UP* pRing;
  unsigned                v;

  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
  v = pRing->RdOff;
    3b0c:	4b03      	ldr	r3, [pc, #12]	; (3b1c <SEGGER_RTT_HasDataUp+0x10>)
    3b0e:	2218      	movs	r2, #24
    3b10:	fb02 3300 	mla	r3, r2, r0, r3
    3b14:	6a9a      	ldr	r2, [r3, #40]	; 0x28
  return pRing->WrOff - v;
    3b16:	6a58      	ldr	r0, [r3, #36]	; 0x24
}
    3b18:	1a80      	subs	r0, r0, r2
    3b1a:	4770      	bx	lr
    3b1c:	200005a0 	.word	0x200005a0

00003b20 <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3b20:	4b0e      	ldr	r3, [pc, #56]	; (3b5c <z_sys_init_run_level+0x3c>)
{
    3b22:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3b24:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    3b28:	3001      	adds	r0, #1
    3b2a:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    3b2e:	42a6      	cmp	r6, r4
    3b30:	d800      	bhi.n	3b34 <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    3b32:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    3b34:	e9d4 3500 	ldrd	r3, r5, [r4]
    3b38:	4628      	mov	r0, r5
    3b3a:	4798      	blx	r3
		if (dev != NULL) {
    3b3c:	b165      	cbz	r5, 3b58 <z_sys_init_run_level+0x38>
			if (rc != 0) {
    3b3e:	68eb      	ldr	r3, [r5, #12]
    3b40:	b130      	cbz	r0, 3b50 <z_sys_init_run_level+0x30>
				if (rc < 0) {
    3b42:	2800      	cmp	r0, #0
    3b44:	bfb8      	it	lt
    3b46:	4240      	neglt	r0, r0
				dev->state->init_res = rc;
    3b48:	28ff      	cmp	r0, #255	; 0xff
    3b4a:	bfa8      	it	ge
    3b4c:	20ff      	movge	r0, #255	; 0xff
    3b4e:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    3b50:	785a      	ldrb	r2, [r3, #1]
    3b52:	f042 0201 	orr.w	r2, r2, #1
    3b56:	705a      	strb	r2, [r3, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3b58:	3408      	adds	r4, #8
    3b5a:	e7e8      	b.n	3b2e <z_sys_init_run_level+0xe>
    3b5c:	00007260 	.word	0x00007260

00003b60 <z_impl_device_get_binding>:

const struct device *z_impl_device_get_binding(const char *name)
{
    3b60:	b570      	push	{r4, r5, r6, lr}
	const struct device *dev;

	/* A null string identifies no device.  So does an empty
	 * string.
	 */
	if ((name == NULL) || (name[0] == '\0')) {
    3b62:	4605      	mov	r5, r0
    3b64:	b910      	cbnz	r0, 3b6c <z_impl_device_get_binding+0xc>
		return NULL;
    3b66:	2400      	movs	r4, #0
			return dev;
		}
	}

	return NULL;
}
    3b68:	4620      	mov	r0, r4
    3b6a:	bd70      	pop	{r4, r5, r6, pc}
	if ((name == NULL) || (name[0] == '\0')) {
    3b6c:	7803      	ldrb	r3, [r0, #0]
    3b6e:	2b00      	cmp	r3, #0
    3b70:	d0f9      	beq.n	3b66 <z_impl_device_get_binding+0x6>
	for (dev = __device_start; dev != __device_end; dev++) {
    3b72:	4a0f      	ldr	r2, [pc, #60]	; (3bb0 <z_impl_device_get_binding+0x50>)
    3b74:	4c0f      	ldr	r4, [pc, #60]	; (3bb4 <z_impl_device_get_binding+0x54>)
    3b76:	4616      	mov	r6, r2
    3b78:	4294      	cmp	r4, r2
    3b7a:	d108      	bne.n	3b8e <z_impl_device_get_binding+0x2e>
	for (dev = __device_start; dev != __device_end; dev++) {
    3b7c:	4c0d      	ldr	r4, [pc, #52]	; (3bb4 <z_impl_device_get_binding+0x54>)
    3b7e:	42b4      	cmp	r4, r6
    3b80:	d0f1      	beq.n	3b66 <z_impl_device_get_binding+0x6>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    3b82:	4620      	mov	r0, r4
    3b84:	f002 fdc1 	bl	670a <z_device_ready>
    3b88:	b950      	cbnz	r0, 3ba0 <z_impl_device_get_binding+0x40>
	for (dev = __device_start; dev != __device_end; dev++) {
    3b8a:	3418      	adds	r4, #24
    3b8c:	e7f7      	b.n	3b7e <z_impl_device_get_binding+0x1e>
		if (z_device_ready(dev) && (dev->name == name)) {
    3b8e:	4620      	mov	r0, r4
    3b90:	f002 fdbb 	bl	670a <z_device_ready>
    3b94:	b110      	cbz	r0, 3b9c <z_impl_device_get_binding+0x3c>
    3b96:	6823      	ldr	r3, [r4, #0]
    3b98:	42ab      	cmp	r3, r5
    3b9a:	d0e5      	beq.n	3b68 <z_impl_device_get_binding+0x8>
	for (dev = __device_start; dev != __device_end; dev++) {
    3b9c:	3418      	adds	r4, #24
    3b9e:	e7eb      	b.n	3b78 <z_impl_device_get_binding+0x18>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    3ba0:	6821      	ldr	r1, [r4, #0]
    3ba2:	4628      	mov	r0, r5
    3ba4:	f7fc fc76 	bl	494 <strcmp>
    3ba8:	2800      	cmp	r0, #0
    3baa:	d1ee      	bne.n	3b8a <z_impl_device_get_binding+0x2a>
    3bac:	e7dc      	b.n	3b68 <z_impl_device_get_binding+0x8>
    3bae:	bf00      	nop
    3bb0:	00006ef0 	.word	0x00006ef0
    3bb4:	00006e60 	.word	0x00006e60

00003bb8 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    3bb8:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    3bbc:	4606      	mov	r6, r0
    3bbe:	460f      	mov	r7, r1
	__asm__ volatile(
    3bc0:	f04f 0320 	mov.w	r3, #32
    3bc4:	f3ef 8811 	mrs	r8, BASEPRI
    3bc8:	f383 8811 	msr	BASEPRI, r3
    3bcc:	f3bf 8f6f 	isb	sy
	return z_impl_k_current_get();
    3bd0:	f000 ff62 	bl	4a98 <z_impl_k_current_get>
    3bd4:	4c1f      	ldr	r4, [pc, #124]	; (3c54 <z_fatal_error+0x9c>)
    3bd6:	4b20      	ldr	r3, [pc, #128]	; (3c58 <z_fatal_error+0xa0>)
    3bd8:	1ae4      	subs	r4, r4, r3
    3bda:	2e04      	cmp	r6, #4
    3bdc:	ea4f 04d4 	mov.w	r4, r4, lsr #3
    3be0:	bf96      	itet	ls
    3be2:	4a1e      	ldrls	r2, [pc, #120]	; (3c5c <z_fatal_error+0xa4>)
			k_current_get() : NULL;

	/* twister looks for the "ZEPHYR FATAL ERROR" string, don't
	 * change it without also updating twister
	 */
	LOG_ERR(">>> ZEPHYR FATAL ERROR %d: %s on CPU %d", reason,
    3be4:	4a1e      	ldrhi	r2, [pc, #120]	; (3c60 <z_fatal_error+0xa8>)
    3be6:	f852 2026 	ldrls.w	r2, [r2, r6, lsl #2]
    3bea:	01a4      	lsls	r4, r4, #6
    3bec:	f044 0301 	orr.w	r3, r4, #1
    3bf0:	4605      	mov	r5, r0
    3bf2:	f8ad 3000 	strh.w	r3, [sp]
    3bf6:	481b      	ldr	r0, [pc, #108]	; (3c64 <z_fatal_error+0xac>)
    3bf8:	2300      	movs	r3, #0
    3bfa:	4631      	mov	r1, r6
    3bfc:	f002 f997 	bl	5f2e <log_3>
	 * an IRQ or exception was being handled, or thread context.
	 *
	 * See #17656
	 */
#if defined(CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION)
	if ((esf != NULL) && arch_is_in_nested_exception(esf)) {
    3c00:	b147      	cbz	r7, 3c14 <z_fatal_error+0x5c>
 * @return true if execution state was in handler mode, before
 *              the current exception occurred, otherwise false.
 */
static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf)
{
	return (esf->basic.xpsr & IPSR_ISR_Msk) ? (true) : (false);
    3c02:	69fb      	ldr	r3, [r7, #28]
    3c04:	f3c3 0308 	ubfx	r3, r3, #0, #9
    3c08:	b123      	cbz	r3, 3c14 <z_fatal_error+0x5c>
		LOG_ERR("Fault during interrupt handling\n");
    3c0a:	4817      	ldr	r0, [pc, #92]	; (3c68 <z_fatal_error+0xb0>)
    3c0c:	f044 0101 	orr.w	r1, r4, #1
    3c10:	f002 f953 	bl	5eba <log_0>
	}
#endif

	LOG_ERR("Current thread: %p (%s)", thread,
    3c14:	f044 0401 	orr.w	r4, r4, #1
	const char *thread_name = (thread != NULL) ? k_thread_name_get(thread) : NULL;
    3c18:	b12d      	cbz	r5, 3c26 <z_fatal_error+0x6e>
    3c1a:	4628      	mov	r0, r5
    3c1c:	f002 fdcd 	bl	67ba <k_thread_name_get>
	if ((thread_name == NULL) || (thread_name[0] == '\0')) {
    3c20:	b108      	cbz	r0, 3c26 <z_fatal_error+0x6e>
    3c22:	7803      	ldrb	r3, [r0, #0]
    3c24:	b903      	cbnz	r3, 3c28 <z_fatal_error+0x70>
		thread_name = "unknown";
    3c26:	4811      	ldr	r0, [pc, #68]	; (3c6c <z_fatal_error+0xb4>)
{
	if (IS_ENABLED(CONFIG_LOG_MINIMAL) || IS_ENABLED(CONFIG_LOG2)) {
		return (char *)str;
	}

	return z_log_strdup(str);
    3c28:	f7fd fa8a 	bl	1140 <z_log_strdup>
	LOG_ERR("Current thread: %p (%s)", thread,
    3c2c:	4623      	mov	r3, r4
    3c2e:	4602      	mov	r2, r0
    3c30:	4629      	mov	r1, r5
    3c32:	480f      	ldr	r0, [pc, #60]	; (3c70 <z_fatal_error+0xb8>)
    3c34:	f002 f962 	bl	5efc <log_2>
		log_strdup(thread_name_get(thread)));

	coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    3c38:	4639      	mov	r1, r7
    3c3a:	4630      	mov	r0, r6
    3c3c:	f7ff fcc0 	bl	35c0 <k_sys_fatal_error_handler>
	__asm__ volatile(
    3c40:	f388 8811 	msr	BASEPRI, r8
    3c44:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    3c48:	4628      	mov	r0, r5
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    3c4a:	b002      	add	sp, #8
    3c4c:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    3c50:	f7fe bf76 	b.w	2b40 <z_impl_k_thread_abort>
    3c54:	00007098 	.word	0x00007098
    3c58:	00007078 	.word	0x00007078
    3c5c:	00007278 	.word	0x00007278
    3c60:	000078d3 	.word	0x000078d3
    3c64:	000078e9 	.word	0x000078e9
    3c68:	00007911 	.word	0x00007911
    3c6c:	000078e1 	.word	0x000078e1
    3c70:	00007932 	.word	0x00007932

00003c74 <z_bss_zero>:
 * @return N/A
 */
__boot_func
void z_bss_zero(void)
{
	(void)memset(__bss_start, 0, __bss_end - __bss_start);
    3c74:	4802      	ldr	r0, [pc, #8]	; (3c80 <z_bss_zero+0xc>)
__ssp_bos_icheck3(memset, void *, int)
    3c76:	4a03      	ldr	r2, [pc, #12]	; (3c84 <z_bss_zero+0x10>)
    3c78:	2100      	movs	r1, #0
    3c7a:	1a12      	subs	r2, r2, r0
    3c7c:	f002 bf4e 	b.w	6b1c <memset>
    3c80:	20000110 	.word	0x20000110
    3c84:	20000ad8 	.word	0x20000ad8

00003c88 <bg_thread_main>:
 *
 * @return N/A
 */
__boot_func
static void bg_thread_main(void *unused1, void *unused2, void *unused3)
{
    3c88:	b508      	push	{r3, lr}
	 * may perform memory management tasks (except for z_phys_map() which
	 * is allowed at any time)
	 */
	z_mem_manage_init();
#endif /* CONFIG_MMU */
	z_sys_post_kernel = true;
    3c8a:	4b0c      	ldr	r3, [pc, #48]	; (3cbc <bg_thread_main+0x34>)
    3c8c:	2201      	movs	r2, #1

	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    3c8e:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
    3c90:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    3c92:	f7ff ff45 	bl	3b20 <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    3c96:	f001 f979 	bl	4f8c <boot_banner>

#if defined(CONFIG_CPLUSPLUS) && !defined(CONFIG_ARCH_POSIX)
	/* Process the .ctors and .init_array sections */
	extern void __do_global_ctors_aux(void);
	extern void __do_init_array_aux(void);
	__do_global_ctors_aux();
    3c9a:	f7fd ff3f 	bl	1b1c <__do_global_ctors_aux>
	__do_init_array_aux();
    3c9e:	f7fd ff2f 	bl	1b00 <__do_init_array_aux>
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    3ca2:	2003      	movs	r0, #3
    3ca4:	f7ff ff3c 	bl	3b20 <z_sys_init_run_level>

	z_init_static_threads();
    3ca8:	f000 f944 	bl	3f34 <z_init_static_threads>
	z_sys_init_run_level(_SYS_INIT_LEVEL_SMP);
#endif

	extern void main(void);

	main();
    3cac:	f7fc fc04 	bl	4b8 <main>

	/* Mark nonessenrial since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    3cb0:	4a03      	ldr	r2, [pc, #12]	; (3cc0 <bg_thread_main+0x38>)
    3cb2:	7b13      	ldrb	r3, [r2, #12]
    3cb4:	f023 0301 	bic.w	r3, r3, #1
    3cb8:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    3cba:	bd08      	pop	{r3, pc}
    3cbc:	20000ac2 	.word	0x20000ac2
    3cc0:	20000248 	.word	0x20000248

00003cc4 <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    3cc4:	e92d 4880 	stmdb	sp!, {r7, fp, lr}
    3cc8:	b0a7      	sub	sp, #156	; 0x9c
	/* gcov hook needed to get the coverage report.*/
	gcov_static_init();

	LOG_CORE_INIT();
    3cca:	f7fd f971 	bl	fb0 <log_core_init>
 *
 * @return N/A
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    3cce:	f8df 9100 	ldr.w	r9, [pc, #256]	; 3dd0 <z_cstart+0x10c>
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    3cd2:	f389 8808 	msr	MSP, r9
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    3cd6:	4d36      	ldr	r5, [pc, #216]	; (3db0 <z_cstart+0xec>)
	_kernel.ready_q.cache = &z_main_thread;
    3cd8:	4e36      	ldr	r6, [pc, #216]	; (3db4 <z_cstart+0xf0>)
    3cda:	696b      	ldr	r3, [r5, #20]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3cdc:	f8df a0f4 	ldr.w	sl, [pc, #244]	; 3dd4 <z_cstart+0x110>
	z_setup_new_thread(thread, stack,
    3ce0:	4f35      	ldr	r7, [pc, #212]	; (3db8 <z_cstart+0xf4>)
    3ce2:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    3ce6:	2400      	movs	r4, #0
    3ce8:	616b      	str	r3, [r5, #20]
    3cea:	23e0      	movs	r3, #224	; 0xe0
    3cec:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    3cf0:	77ec      	strb	r4, [r5, #31]
    3cf2:	762c      	strb	r4, [r5, #24]
    3cf4:	766c      	strb	r4, [r5, #25]
    3cf6:	76ac      	strb	r4, [r5, #26]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    3cf8:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    3cfa:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    3cfe:	626b      	str	r3, [r5, #36]	; 0x24

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    3d00:	f7fe fec8 	bl	2a94 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    3d04:	f7fe fc3c 	bl	2580 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    3d08:	f04f 33ff 	mov.w	r3, #4294967295
    3d0c:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    3d0e:	62eb      	str	r3, [r5, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    3d10:	f7fe ffac 	bl	2c6c <z_arm_mpu_init>
#endif
#ifdef CONFIG_USERSPACE
	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
#endif

	_current_cpu->current = dummy_thread;
    3d14:	4d29      	ldr	r5, [pc, #164]	; (3dbc <z_cstart+0xf8>)
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    3d16:	f7fe ff25 	bl	2b64 <z_arm_configure_static_mpu_regions>
	dummy_thread->base.user_options = K_ESSENTIAL;
    3d1a:	f240 1301 	movw	r3, #257	; 0x101
    3d1e:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    3d22:	ab06      	add	r3, sp, #24
    3d24:	60ab      	str	r3, [r5, #8]
	dummy_thread->stack_info.size = 0U;
    3d26:	e9cd 441f 	strd	r4, r4, [sp, #124]	; 0x7c
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    3d2a:	f002 fced 	bl	6708 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    3d2e:	4620      	mov	r0, r4
    3d30:	f7ff fef6 	bl	3b20 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    3d34:	2001      	movs	r0, #1
    3d36:	f7ff fef3 	bl	3b20 <z_sys_init_run_level>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3d3a:	f04f 0b01 	mov.w	fp, #1
	z_sched_init();
    3d3e:	f000 fdf7 	bl	4930 <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3d42:	4b1f      	ldr	r3, [pc, #124]	; (3dc0 <z_cstart+0xfc>)
	_kernel.ready_q.cache = &z_main_thread;
    3d44:	626e      	str	r6, [r5, #36]	; 0x24
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3d46:	491f      	ldr	r1, [pc, #124]	; (3dc4 <z_cstart+0x100>)
    3d48:	9305      	str	r3, [sp, #20]
    3d4a:	f44f 6280 	mov.w	r2, #1024	; 0x400
    3d4e:	4653      	mov	r3, sl
    3d50:	e9cd 4b03 	strd	r4, fp, [sp, #12]
    3d54:	e9cd 4401 	strd	r4, r4, [sp, #4]
    3d58:	9400      	str	r4, [sp, #0]
    3d5a:	4630      	mov	r0, r6
    3d5c:	f000 f88e 	bl	3e7c <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    3d60:	7b73      	ldrb	r3, [r6, #13]
    3d62:	4680      	mov	r8, r0
    3d64:	f023 0304 	bic.w	r3, r3, #4
	z_ready_thread(&z_main_thread);
    3d68:	4630      	mov	r0, r6
    3d6a:	7373      	strb	r3, [r6, #13]
    3d6c:	f002 fdd6 	bl	691c <z_ready_thread>
	z_setup_new_thread(thread, stack,
    3d70:	230f      	movs	r3, #15
    3d72:	e9cd 4302 	strd	r4, r3, [sp, #8]
    3d76:	4914      	ldr	r1, [pc, #80]	; (3dc8 <z_cstart+0x104>)
    3d78:	4b14      	ldr	r3, [pc, #80]	; (3dcc <z_cstart+0x108>)
    3d7a:	f44f 72a0 	mov.w	r2, #320	; 0x140
    3d7e:	e9cd b404 	strd	fp, r4, [sp, #16]
    3d82:	e9cd 5400 	strd	r5, r4, [sp]
    3d86:	4638      	mov	r0, r7
    3d88:	f000 f878 	bl	3e7c <z_setup_new_thread>
    3d8c:	7b7b      	ldrb	r3, [r7, #13]
		_kernel.cpus[i].idle_thread = &z_idle_threads[i];
    3d8e:	60ef      	str	r7, [r5, #12]
    3d90:	f023 0304 	bic.w	r3, r3, #4
    3d94:	737b      	strb	r3, [r7, #13]
 * @return N/A
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
    3d96:	f105 0318 	add.w	r3, r5, #24
	list->tail = (sys_dnode_t *)list;
    3d9a:	e9c5 3306 	strd	r3, r3, [r5, #24]
		_kernel.cpus[i].id = i;
    3d9e:	752c      	strb	r4, [r5, #20]
		_kernel.cpus[i].irq_stack =
    3da0:	f8c5 9004 	str.w	r9, [r5, #4]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    3da4:	4652      	mov	r2, sl
    3da6:	4641      	mov	r1, r8
    3da8:	4630      	mov	r0, r6
    3daa:	f7fe fb4f 	bl	244c <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    3dae:	bf00      	nop
    3db0:	e000ed00 	.word	0xe000ed00
    3db4:	20000248 	.word	0x20000248
    3db8:	200001c8 	.word	0x200001c8
    3dbc:	20000648 	.word	0x20000648
    3dc0:	00007994 	.word	0x00007994
    3dc4:	20000dd8 	.word	0x20000dd8
    3dc8:	200011d8 	.word	0x200011d8
    3dcc:	00003ff1 	.word	0x00003ff1
    3dd0:	20001b18 	.word	0x20001b18
    3dd4:	00003c89 	.word	0x00003c89

00003dd8 <init_mem_slab_module>:
 * Perform any initialization that wasn't done at build time.
 *
 * @return N/A
 */
static int init_mem_slab_module(const struct device *dev)
{
    3dd8:	b570      	push	{r4, r5, r6, lr}
	int rc = 0;
	ARG_UNUSED(dev);

	Z_STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    3dda:	4b0e      	ldr	r3, [pc, #56]	; (3e14 <init_mem_slab_module+0x3c>)
    3ddc:	4c0e      	ldr	r4, [pc, #56]	; (3e18 <init_mem_slab_module+0x40>)
    3dde:	42a3      	cmp	r3, r4
    3de0:	d301      	bcc.n	3de6 <init_mem_slab_module+0xe>
			goto out;
		}
		z_object_init(slab);
	}

out:
    3de2:	2000      	movs	r0, #0
	return rc;
}
    3de4:	bd70      	pop	{r4, r5, r6, pc}
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    3de6:	e9d3 0104 	ldrd	r0, r1, [r3, #16]
    3dea:	ea41 0200 	orr.w	r2, r1, r0
    3dee:	f012 0203 	ands.w	r2, r2, #3
    3df2:	d10b      	bne.n	3e0c <init_mem_slab_module+0x34>
	for (j = 0U; j < slab->num_blocks; j++) {
    3df4:	68dd      	ldr	r5, [r3, #12]
	slab->free_list = NULL;
    3df6:	619a      	str	r2, [r3, #24]
	for (j = 0U; j < slab->num_blocks; j++) {
    3df8:	42aa      	cmp	r2, r5
    3dfa:	d101      	bne.n	3e00 <init_mem_slab_module+0x28>
	Z_STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    3dfc:	3320      	adds	r3, #32
    3dfe:	e7ee      	b.n	3dde <init_mem_slab_module+0x6>
		*(char **)p = slab->free_list;
    3e00:	699e      	ldr	r6, [r3, #24]
    3e02:	600e      	str	r6, [r1, #0]
	for (j = 0U; j < slab->num_blocks; j++) {
    3e04:	3201      	adds	r2, #1
		slab->free_list = p;
    3e06:	6199      	str	r1, [r3, #24]
		p += slab->block_size;
    3e08:	4401      	add	r1, r0
	for (j = 0U; j < slab->num_blocks; j++) {
    3e0a:	e7f5      	b.n	3df8 <init_mem_slab_module+0x20>
		return -EINVAL;
    3e0c:	f06f 0015 	mvn.w	r0, #21
	return rc;
    3e10:	e7e8      	b.n	3de4 <init_mem_slab_module+0xc>
    3e12:	bf00      	nop
    3e14:	200000e8 	.word	0x200000e8
    3e18:	200000e8 	.word	0x200000e8

00003e1c <k_mem_slab_alloc>:

	return rc;
}

int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
{
    3e1c:	b5d3      	push	{r0, r1, r4, r6, r7, lr}
    3e1e:	460c      	mov	r4, r1
    3e20:	4616      	mov	r6, r2
    3e22:	461f      	mov	r7, r3
	__asm__ volatile(
    3e24:	f04f 0320 	mov.w	r3, #32
    3e28:	f3ef 8111 	mrs	r1, BASEPRI
    3e2c:	f383 8811 	msr	BASEPRI, r3
    3e30:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);
	int result;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, alloc, slab, timeout);

	if (slab->free_list != NULL) {
    3e34:	6983      	ldr	r3, [r0, #24]
    3e36:	b15b      	cbz	r3, 3e50 <k_mem_slab_alloc+0x34>
		/* take a free block */
		*mem = slab->free_list;
    3e38:	6023      	str	r3, [r4, #0]
		slab->free_list = *(char **)(slab->free_list);
    3e3a:	681b      	ldr	r3, [r3, #0]
    3e3c:	6183      	str	r3, [r0, #24]
		slab->num_used++;
    3e3e:	69c3      	ldr	r3, [r0, #28]
    3e40:	3301      	adds	r3, #1
    3e42:	61c3      	str	r3, [r0, #28]

#ifdef CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION
		slab->max_used = MAX(slab->num_used, slab->max_used);
#endif

		result = 0;
    3e44:	2000      	movs	r0, #0
	__asm__ volatile(
    3e46:	f381 8811 	msr	BASEPRI, r1
    3e4a:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, alloc, slab, timeout, result);

	k_spin_unlock(&slab->lock, key);

	return result;
    3e4e:	e011      	b.n	3e74 <k_mem_slab_alloc+0x58>
	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT) ||
    3e50:	ea56 0207 	orrs.w	r2, r6, r7
    3e54:	d103      	bne.n	3e5e <k_mem_slab_alloc+0x42>
		*mem = NULL;
    3e56:	6023      	str	r3, [r4, #0]
		result = -ENOMEM;
    3e58:	f06f 000b 	mvn.w	r0, #11
    3e5c:	e7f3      	b.n	3e46 <k_mem_slab_alloc+0x2a>
		result = z_pend_curr(&slab->lock, key, &slab->wait_q, timeout);
    3e5e:	4602      	mov	r2, r0
    3e60:	e9cd 6700 	strd	r6, r7, [sp]
    3e64:	3008      	adds	r0, #8
    3e66:	f000 fbdf 	bl	4628 <z_pend_curr>
		if (result == 0) {
    3e6a:	b918      	cbnz	r0, 3e74 <k_mem_slab_alloc+0x58>
			*mem = _current->base.swap_data;
    3e6c:	4b02      	ldr	r3, [pc, #8]	; (3e78 <k_mem_slab_alloc+0x5c>)
    3e6e:	689b      	ldr	r3, [r3, #8]
    3e70:	695b      	ldr	r3, [r3, #20]
    3e72:	6023      	str	r3, [r4, #0]
}
    3e74:	b002      	add	sp, #8
    3e76:	bdd0      	pop	{r4, r6, r7, pc}
    3e78:	20000648 	.word	0x20000648

00003e7c <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    3e7c:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
	thread_base->user_options = (uint8_t)options;
    3e80:	9e0e      	ldr	r6, [sp, #56]	; 0x38
    3e82:	7306      	strb	r6, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    3e84:	2604      	movs	r6, #4
    3e86:	7346      	strb	r6, [r0, #13]

	thread_base->prio = priority;
    3e88:	9e0d      	ldr	r6, [sp, #52]	; 0x34
    3e8a:	7386      	strb	r6, [r0, #14]
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    3e8c:	f100 0558 	add.w	r5, r0, #88	; 0x58
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    3e90:	1dd6      	adds	r6, r2, #7
    3e92:	e9c0 5516 	strd	r5, r5, [r0, #88]	; 0x58
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3e96:	9a0c      	ldr	r2, [sp, #48]	; 0x30
	thread_base->pended_on = NULL;
    3e98:	2500      	movs	r5, #0
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    3e9a:	f026 0607 	bic.w	r6, r6, #7
 */

static inline void sys_dnode_init(sys_dnode_t *node)
{
	node->next = NULL;
	node->prev = NULL;
    3e9e:	e9c0 5506 	strd	r5, r5, [r0, #24]
	new_thread->stack_info.size = stack_buf_size;
    3ea2:	e9c0 1619 	strd	r1, r6, [r0, #100]	; 0x64
	thread_base->pended_on = NULL;
    3ea6:	6085      	str	r5, [r0, #8]

	thread_base->sched_locked = 0U;
    3ea8:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    3eaa:	66c5      	str	r5, [r0, #108]	; 0x6c
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3eac:	9202      	str	r2, [sp, #8]
    3eae:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    3eb0:	9201      	str	r2, [sp, #4]
	stack_ptr = (char *)stack + stack_obj_size;
    3eb2:	eb01 0806 	add.w	r8, r1, r6
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3eb6:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    3eb8:	9200      	str	r2, [sp, #0]
    3eba:	4642      	mov	r2, r8
{
    3ebc:	4604      	mov	r4, r0
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3ebe:	f7fe faa9 	bl	2414 <arch_new_thread>
	if (!_current) {
    3ec2:	4b05      	ldr	r3, [pc, #20]	; (3ed8 <z_setup_new_thread+0x5c>)
	new_thread->init_data = NULL;
    3ec4:	6565      	str	r5, [r4, #84]	; 0x54
	if (!_current) {
    3ec6:	689b      	ldr	r3, [r3, #8]
    3ec8:	b103      	cbz	r3, 3ecc <z_setup_new_thread+0x50>
	new_thread->resource_pool = _current->resource_pool;
    3eca:	6f1b      	ldr	r3, [r3, #112]	; 0x70
	return stack_ptr;
    3ecc:	6723      	str	r3, [r4, #112]	; 0x70
}
    3ece:	4640      	mov	r0, r8
    3ed0:	b004      	add	sp, #16
    3ed2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    3ed6:	bf00      	nop
    3ed8:	20000648 	.word	0x20000648

00003edc <z_impl_k_thread_create>:
{
    3edc:	b5f0      	push	{r4, r5, r6, r7, lr}
    3ede:	b087      	sub	sp, #28
	z_setup_new_thread(new_thread, stack, stack_size, entry, p1, p2, p3,
    3ee0:	2500      	movs	r5, #0
    3ee2:	9505      	str	r5, [sp, #20]
    3ee4:	9d10      	ldr	r5, [sp, #64]	; 0x40
    3ee6:	9504      	str	r5, [sp, #16]
    3ee8:	9d0f      	ldr	r5, [sp, #60]	; 0x3c
    3eea:	9503      	str	r5, [sp, #12]
    3eec:	9d0e      	ldr	r5, [sp, #56]	; 0x38
    3eee:	9502      	str	r5, [sp, #8]
{
    3ef0:	e9dd 6712 	ldrd	r6, r7, [sp, #72]	; 0x48
	z_setup_new_thread(new_thread, stack, stack_size, entry, p1, p2, p3,
    3ef4:	9d0d      	ldr	r5, [sp, #52]	; 0x34
    3ef6:	9501      	str	r5, [sp, #4]
    3ef8:	9d0c      	ldr	r5, [sp, #48]	; 0x30
    3efa:	9500      	str	r5, [sp, #0]
{
    3efc:	4604      	mov	r4, r0
	z_setup_new_thread(new_thread, stack, stack_size, entry, p1, p2, p3,
    3efe:	f7ff ffbd 	bl	3e7c <z_setup_new_thread>
	if (!K_TIMEOUT_EQ(delay, K_FOREVER)) {
    3f02:	1c7b      	adds	r3, r7, #1
    3f04:	bf08      	it	eq
    3f06:	f1b6 3fff 	cmpeq.w	r6, #4294967295
    3f0a:	d005      	beq.n	3f18 <z_impl_k_thread_create+0x3c>
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3f0c:	ea56 0307 	orrs.w	r3, r6, r7
    3f10:	d105      	bne.n	3f1e <z_impl_k_thread_create+0x42>
	z_sched_start(thread);
    3f12:	4620      	mov	r0, r4
    3f14:	f000 fca2 	bl	485c <z_sched_start>
}
    3f18:	4620      	mov	r0, r4
    3f1a:	b007      	add	sp, #28
    3f1c:	bdf0      	pop	{r4, r5, r6, r7, pc}

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    3f1e:	4904      	ldr	r1, [pc, #16]	; (3f30 <z_impl_k_thread_create+0x54>)
    3f20:	4632      	mov	r2, r6
    3f22:	463b      	mov	r3, r7
    3f24:	f104 0018 	add.w	r0, r4, #24
    3f28:	f000 fe9a 	bl	4c60 <z_add_timeout>
    3f2c:	e7f4      	b.n	3f18 <z_impl_k_thread_create+0x3c>
    3f2e:	bf00      	nop
    3f30:	0000693d 	.word	0x0000693d

00003f34 <z_init_static_threads>:
{
    3f34:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	_FOREACH_STATIC_THREAD(thread_data) {
    3f38:	4e2a      	ldr	r6, [pc, #168]	; (3fe4 <z_init_static_threads+0xb0>)
    3f3a:	4d2b      	ldr	r5, [pc, #172]	; (3fe8 <z_init_static_threads+0xb4>)
{
    3f3c:	b086      	sub	sp, #24
    3f3e:	46b0      	mov	r8, r6
	_FOREACH_STATIC_THREAD(thread_data) {
    3f40:	42b5      	cmp	r5, r6
    3f42:	f105 0430 	add.w	r4, r5, #48	; 0x30
    3f46:	d310      	bcc.n	3f6a <z_init_static_threads+0x36>
	k_sched_lock();
    3f48:	f000 fafc 	bl	4544 <k_sched_lock>
	_FOREACH_STATIC_THREAD(thread_data) {
    3f4c:	4c26      	ldr	r4, [pc, #152]	; (3fe8 <z_init_static_threads+0xb4>)
    3f4e:	f8df a09c 	ldr.w	sl, [pc, #156]	; 3fec <z_init_static_threads+0xb8>
		} else {
			return (t * to_hz + off) / from_hz;
    3f52:	f44f 4900 	mov.w	r9, #32768	; 0x8000
    3f56:	f240 36e7 	movw	r6, #999	; 0x3e7
    3f5a:	2700      	movs	r7, #0
    3f5c:	4544      	cmp	r4, r8
    3f5e:	d321      	bcc.n	3fa4 <z_init_static_threads+0x70>
}
    3f60:	b006      	add	sp, #24
    3f62:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	k_sched_unlock();
    3f66:	f000 bba5 	b.w	46b4 <k_sched_unlock>
		z_setup_new_thread(
    3f6a:	f854 3c04 	ldr.w	r3, [r4, #-4]
    3f6e:	9305      	str	r3, [sp, #20]
    3f70:	f854 3c10 	ldr.w	r3, [r4, #-16]
    3f74:	9304      	str	r3, [sp, #16]
    3f76:	f854 3c14 	ldr.w	r3, [r4, #-20]
    3f7a:	9303      	str	r3, [sp, #12]
    3f7c:	f854 3c18 	ldr.w	r3, [r4, #-24]
    3f80:	9302      	str	r3, [sp, #8]
    3f82:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    3f86:	9301      	str	r3, [sp, #4]
    3f88:	f854 3c20 	ldr.w	r3, [r4, #-32]
    3f8c:	9300      	str	r3, [sp, #0]
    3f8e:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    3f92:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    3f96:	f7ff ff71 	bl	3e7c <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    3f9a:	f854 3c30 	ldr.w	r3, [r4, #-48]
    3f9e:	655d      	str	r5, [r3, #84]	; 0x54
    3fa0:	4625      	mov	r5, r4
    3fa2:	e7cd      	b.n	3f40 <z_init_static_threads+0xc>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    3fa4:	6a63      	ldr	r3, [r4, #36]	; 0x24
    3fa6:	1c5a      	adds	r2, r3, #1
    3fa8:	d00d      	beq.n	3fc6 <z_init_static_threads+0x92>
					    K_MSEC(thread_data->init_delay));
    3faa:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    3fae:	4630      	mov	r0, r6
    3fb0:	4639      	mov	r1, r7
    3fb2:	fbc9 0103 	smlal	r0, r1, r9, r3
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3fb6:	42b9      	cmp	r1, r7
    3fb8:	bf08      	it	eq
    3fba:	42b0      	cmpeq	r0, r6
			schedule_new_thread(thread_data->init_thread,
    3fbc:	6825      	ldr	r5, [r4, #0]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3fbe:	d104      	bne.n	3fca <z_init_static_threads+0x96>
	z_sched_start(thread);
    3fc0:	4628      	mov	r0, r5
    3fc2:	f000 fc4b 	bl	485c <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    3fc6:	3430      	adds	r4, #48	; 0x30
    3fc8:	e7c8      	b.n	3f5c <z_init_static_threads+0x28>
    3fca:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    3fce:	2300      	movs	r3, #0
    3fd0:	f7fc f8e6 	bl	1a0 <__aeabi_uldivmod>
    3fd4:	4602      	mov	r2, r0
    3fd6:	460b      	mov	r3, r1
    3fd8:	f105 0018 	add.w	r0, r5, #24
    3fdc:	4651      	mov	r1, sl
    3fde:	f000 fe3f 	bl	4c60 <z_add_timeout>
    3fe2:	e7f0      	b.n	3fc6 <z_init_static_threads+0x92>
    3fe4:	200000b0 	.word	0x200000b0
    3fe8:	200000b0 	.word	0x200000b0
    3fec:	0000693d 	.word	0x0000693d

00003ff0 <idle>:
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
}

void idle(void *unused1, void *unused2, void *unused3)
{
    3ff0:	b508      	push	{r3, lr}
	_kernel.idle = ticks;
    3ff2:	4c09      	ldr	r4, [pc, #36]	; (4018 <idle+0x28>)
	__asm__ volatile(
    3ff4:	f04f 0220 	mov.w	r2, #32
    3ff8:	f3ef 8311 	mrs	r3, BASEPRI
    3ffc:	f382 8811 	msr	BASEPRI, r2
    4000:	f3bf 8f6f 	isb	sy
	int32_t ticks = z_get_next_timeout_expiry();
    4004:	f002 fd1c 	bl	6a40 <z_get_next_timeout_expiry>
	_kernel.idle = ticks;
    4008:	6220      	str	r0, [r4, #32]
	if (pm_system_suspend(ticks) == PM_STATE_ACTIVE) {
    400a:	f7fd fde1 	bl	1bd0 <pm_system_suspend>
    400e:	2800      	cmp	r0, #0
    4010:	d1f0      	bne.n	3ff4 <idle+0x4>
	arch_cpu_idle();
    4012:	f7fe fabb 	bl	258c <arch_cpu_idle>
}
    4016:	e7ed      	b.n	3ff4 <idle+0x4>
    4018:	20000648 	.word	0x20000648

0000401c <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
    401c:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    4020:	4604      	mov	r4, r0
    4022:	4616      	mov	r6, r2
    4024:	461f      	mov	r7, r3
    4026:	f04f 0320 	mov.w	r3, #32
    402a:	f3ef 8811 	mrs	r8, BASEPRI
    402e:	f383 8811 	msr	BASEPRI, r3
    4032:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, lock, mutex, timeout);

	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    4036:	68c3      	ldr	r3, [r0, #12]
    4038:	4a35      	ldr	r2, [pc, #212]	; (4110 <z_impl_k_mutex_lock+0xf4>)
    403a:	b16b      	cbz	r3, 4058 <z_impl_k_mutex_lock+0x3c>
    403c:	6880      	ldr	r0, [r0, #8]
    403e:	6891      	ldr	r1, [r2, #8]
    4040:	4288      	cmp	r0, r1
    4042:	d019      	beq.n	4078 <z_impl_k_mutex_lock+0x5c>
		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, 0);

		return 0;
	}

	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
    4044:	ea56 0307 	orrs.w	r3, r6, r7
    4048:	d118      	bne.n	407c <z_impl_k_mutex_lock+0x60>
	__asm__ volatile(
    404a:	f388 8811 	msr	BASEPRI, r8
    404e:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);

		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EBUSY);

		return -EBUSY;
    4052:	f06f 000f 	mvn.w	r0, #15
    4056:	e00c      	b.n	4072 <z_impl_k_mutex_lock+0x56>
					_current->base.prio :
    4058:	6891      	ldr	r1, [r2, #8]
    405a:	f991 100e 	ldrsb.w	r1, [r1, #14]
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
    405e:	6121      	str	r1, [r4, #16]
		mutex->lock_count++;
    4060:	3301      	adds	r3, #1
    4062:	60e3      	str	r3, [r4, #12]
		mutex->owner = _current;
    4064:	6893      	ldr	r3, [r2, #8]
    4066:	60a3      	str	r3, [r4, #8]
    4068:	f388 8811 	msr	BASEPRI, r8
    406c:	f3bf 8f6f 	isb	sy
		return 0;
    4070:	2000      	movs	r0, #0
	}

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EAGAIN);

	return -EAGAIN;
}
    4072:	b002      	add	sp, #8
    4074:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
					_current->base.prio :
    4078:	6921      	ldr	r1, [r4, #16]
    407a:	e7f0      	b.n	405e <z_impl_k_mutex_lock+0x42>
	new_prio = new_prio_for_inheritance(_current->base.prio,
    407c:	f991 100e 	ldrsb.w	r1, [r1, #14]
    4080:	f990 300e 	ldrsb.w	r3, [r0, #14]
	thread->base.thread_state &= ~states;
}

static inline bool z_is_under_prio_ceiling(int prio)
{
	return prio >= CONFIG_PRIORITY_CEILING;
    4084:	4299      	cmp	r1, r3
    4086:	bfa8      	it	ge
    4088:	4619      	movge	r1, r3
    408a:	f06f 027e 	mvn.w	r2, #126	; 0x7e
    408e:	4291      	cmp	r1, r2
    4090:	bfb8      	it	lt
    4092:	4611      	movlt	r1, r2
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
    4094:	428b      	cmp	r3, r1
    4096:	dd2f      	ble.n	40f8 <z_impl_k_mutex_lock+0xdc>
		return z_set_prio(mutex->owner, new_prio);
    4098:	f000 fbfe 	bl	4898 <z_set_prio>
    409c:	4605      	mov	r5, r0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
    409e:	e9cd 6700 	strd	r6, r7, [sp]
    40a2:	481c      	ldr	r0, [pc, #112]	; (4114 <z_impl_k_mutex_lock+0xf8>)
    40a4:	4622      	mov	r2, r4
    40a6:	4641      	mov	r1, r8
    40a8:	f000 fabe 	bl	4628 <z_pend_curr>
	if (got_mutex == 0) {
    40ac:	2800      	cmp	r0, #0
    40ae:	d0e0      	beq.n	4072 <z_impl_k_mutex_lock+0x56>
	__asm__ volatile(
    40b0:	f04f 0320 	mov.w	r3, #32
    40b4:	f3ef 8611 	mrs	r6, BASEPRI
    40b8:	f383 8811 	msr	BASEPRI, r3
    40bc:	f3bf 8f6f 	isb	sy
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    40c0:	6823      	ldr	r3, [r4, #0]
    40c2:	6921      	ldr	r1, [r4, #16]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    40c4:	429c      	cmp	r4, r3
    40c6:	d00a      	beq.n	40de <z_impl_k_mutex_lock+0xc2>
		new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    40c8:	b14b      	cbz	r3, 40de <z_impl_k_mutex_lock+0xc2>
    40ca:	f993 300e 	ldrsb.w	r3, [r3, #14]
    40ce:	4299      	cmp	r1, r3
    40d0:	bfa8      	it	ge
    40d2:	4619      	movge	r1, r3
    40d4:	f06f 037e 	mvn.w	r3, #126	; 0x7e
    40d8:	4299      	cmp	r1, r3
    40da:	bfb8      	it	lt
    40dc:	4619      	movlt	r1, r3
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    40de:	68a0      	ldr	r0, [r4, #8]
	if (mutex->owner->base.prio != new_prio) {
    40e0:	f990 300e 	ldrsb.w	r3, [r0, #14]
    40e4:	4299      	cmp	r1, r3
    40e6:	d109      	bne.n	40fc <z_impl_k_mutex_lock+0xe0>
	if (resched) {
    40e8:	b16d      	cbz	r5, 4106 <z_impl_k_mutex_lock+0xea>
		z_reschedule(&lock, key);
    40ea:	480a      	ldr	r0, [pc, #40]	; (4114 <z_impl_k_mutex_lock+0xf8>)
    40ec:	4631      	mov	r1, r6
    40ee:	f000 fa17 	bl	4520 <z_reschedule>
	return -EAGAIN;
    40f2:	f06f 000a 	mvn.w	r0, #10
    40f6:	e7bc      	b.n	4072 <z_impl_k_mutex_lock+0x56>
	bool resched = false;
    40f8:	2500      	movs	r5, #0
    40fa:	e7d0      	b.n	409e <z_impl_k_mutex_lock+0x82>
		return z_set_prio(mutex->owner, new_prio);
    40fc:	f000 fbcc 	bl	4898 <z_set_prio>
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    4100:	2800      	cmp	r0, #0
    4102:	d1f2      	bne.n	40ea <z_impl_k_mutex_lock+0xce>
    4104:	e7f0      	b.n	40e8 <z_impl_k_mutex_lock+0xcc>
	__asm__ volatile(
    4106:	f386 8811 	msr	BASEPRI, r6
    410a:	f3bf 8f6f 	isb	sy
    410e:	e7f0      	b.n	40f2 <z_impl_k_mutex_lock+0xd6>
    4110:	20000648 	.word	0x20000648
    4114:	20000ac3 	.word	0x20000ac3

00004118 <z_impl_k_mutex_unlock>:
}
#include <syscalls/k_mutex_lock_mrsh.c>
#endif

int z_impl_k_mutex_unlock(struct k_mutex *mutex)
{
    4118:	b538      	push	{r3, r4, r5, lr}

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, unlock, mutex);

	CHECKIF(mutex->owner == NULL) {
    411a:	6883      	ldr	r3, [r0, #8]
{
    411c:	4604      	mov	r4, r0
	CHECKIF(mutex->owner == NULL) {
    411e:	2b00      	cmp	r3, #0
    4120:	d036      	beq.n	4190 <z_impl_k_mutex_unlock+0x78>
		return -EINVAL;
	}
	/*
	 * The current thread does not own the mutex.
	 */
	CHECKIF(mutex->owner != _current) {
    4122:	4a1e      	ldr	r2, [pc, #120]	; (419c <z_impl_k_mutex_unlock+0x84>)
    4124:	6892      	ldr	r2, [r2, #8]
    4126:	4293      	cmp	r3, r2
    4128:	d135      	bne.n	4196 <z_impl_k_mutex_unlock+0x7e>
static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1U, "");

	--_current->base.sched_locked;
    412a:	7bda      	ldrb	r2, [r3, #15]
    412c:	3a01      	subs	r2, #1
    412e:	73da      	strb	r2, [r3, #15]

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count > 1U) {
    4130:	68c3      	ldr	r3, [r0, #12]
    4132:	2b01      	cmp	r3, #1
    4134:	d905      	bls.n	4142 <z_impl_k_mutex_unlock+0x2a>
		mutex->lock_count--;
    4136:	3b01      	subs	r3, #1
    4138:	60c3      	str	r3, [r0, #12]


k_mutex_unlock_return:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, unlock, mutex, 0);

	k_sched_unlock();
    413a:	f000 fabb 	bl	46b4 <k_sched_unlock>

	return 0;
    413e:	2000      	movs	r0, #0
}
    4140:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    4142:	f04f 0320 	mov.w	r3, #32
    4146:	f3ef 8511 	mrs	r5, BASEPRI
    414a:	f383 8811 	msr	BASEPRI, r3
    414e:	f3bf 8f6f 	isb	sy
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
    4152:	6901      	ldr	r1, [r0, #16]
    4154:	6880      	ldr	r0, [r0, #8]
	if (mutex->owner->base.prio != new_prio) {
    4156:	f990 300e 	ldrsb.w	r3, [r0, #14]
    415a:	4299      	cmp	r1, r3
    415c:	d001      	beq.n	4162 <z_impl_k_mutex_unlock+0x4a>
		return z_set_prio(mutex->owner, new_prio);
    415e:	f000 fb9b 	bl	4898 <z_set_prio>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
    4162:	4620      	mov	r0, r4
    4164:	f002 fc21 	bl	69aa <z_unpend_first_thread>
	mutex->owner = new_owner;
    4168:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
    416a:	b158      	cbz	r0, 4184 <z_impl_k_mutex_unlock+0x6c>
		mutex->owner_orig_prio = new_owner->base.prio;
    416c:	f990 200e 	ldrsb.w	r2, [r0, #14]
    4170:	6122      	str	r2, [r4, #16]
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    4172:	2200      	movs	r2, #0
    4174:	6782      	str	r2, [r0, #120]	; 0x78
		z_ready_thread(new_owner);
    4176:	f002 fbd1 	bl	691c <z_ready_thread>
		z_reschedule(&lock, key);
    417a:	4809      	ldr	r0, [pc, #36]	; (41a0 <z_impl_k_mutex_unlock+0x88>)
    417c:	4629      	mov	r1, r5
    417e:	f000 f9cf 	bl	4520 <z_reschedule>
    4182:	e7da      	b.n	413a <z_impl_k_mutex_unlock+0x22>
		mutex->lock_count = 0U;
    4184:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    4186:	f385 8811 	msr	BASEPRI, r5
    418a:	f3bf 8f6f 	isb	sy
    418e:	e7d4      	b.n	413a <z_impl_k_mutex_unlock+0x22>
		return -EINVAL;
    4190:	f06f 0015 	mvn.w	r0, #21
    4194:	e7d4      	b.n	4140 <z_impl_k_mutex_unlock+0x28>
		return -EPERM;
    4196:	f04f 30ff 	mov.w	r0, #4294967295
    419a:	e7d1      	b.n	4140 <z_impl_k_mutex_unlock+0x28>
    419c:	20000648 	.word	0x20000648
    41a0:	20000ac3 	.word	0x20000ac3

000041a4 <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    41a4:	b538      	push	{r3, r4, r5, lr}
    41a6:	4604      	mov	r4, r0
	__asm__ volatile(
    41a8:	f04f 0320 	mov.w	r3, #32
    41ac:	f3ef 8511 	mrs	r5, BASEPRI
    41b0:	f383 8811 	msr	BASEPRI, r3
    41b4:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    41b8:	f002 fbf7 	bl	69aa <z_unpend_first_thread>

	if (thread != NULL) {
    41bc:	b148      	cbz	r0, 41d2 <z_impl_k_sem_give+0x2e>
    41be:	2200      	movs	r2, #0
    41c0:	6782      	str	r2, [r0, #120]	; 0x78
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    41c2:	f002 fbab 	bl	691c <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    41c6:	4629      	mov	r1, r5
    41c8:	4805      	ldr	r0, [pc, #20]	; (41e0 <z_impl_k_sem_give+0x3c>)

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    41ca:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    41ce:	f000 b9a7 	b.w	4520 <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    41d2:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    41d6:	429a      	cmp	r2, r3
    41d8:	bf18      	it	ne
    41da:	3301      	addne	r3, #1
    41dc:	60a3      	str	r3, [r4, #8]
		handle_poll_events(sem);
    41de:	e7f2      	b.n	41c6 <z_impl_k_sem_give+0x22>
    41e0:	20000ac4 	.word	0x20000ac4

000041e4 <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    41e4:	b537      	push	{r0, r1, r2, r4, r5, lr}
    41e6:	4614      	mov	r4, r2
    41e8:	461d      	mov	r5, r3
    41ea:	f04f 0320 	mov.w	r3, #32
    41ee:	f3ef 8111 	mrs	r1, BASEPRI
    41f2:	f383 8811 	msr	BASEPRI, r3
    41f6:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    41fa:	6883      	ldr	r3, [r0, #8]
    41fc:	b143      	cbz	r3, 4210 <z_impl_k_sem_take+0x2c>
		sem->count--;
    41fe:	3b01      	subs	r3, #1
    4200:	6083      	str	r3, [r0, #8]
	__asm__ volatile(
    4202:	f381 8811 	msr	BASEPRI, r1
    4206:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    420a:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    420c:	b003      	add	sp, #12
    420e:	bd30      	pop	{r4, r5, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    4210:	ea54 0305 	orrs.w	r3, r4, r5
    4214:	d106      	bne.n	4224 <z_impl_k_sem_take+0x40>
    4216:	f381 8811 	msr	BASEPRI, r1
    421a:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    421e:	f06f 000f 	mvn.w	r0, #15
    4222:	e7f3      	b.n	420c <z_impl_k_sem_take+0x28>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    4224:	4602      	mov	r2, r0
    4226:	e9cd 4500 	strd	r4, r5, [sp]
    422a:	4802      	ldr	r0, [pc, #8]	; (4234 <z_impl_k_sem_take+0x50>)
    422c:	f000 f9fc 	bl	4628 <z_pend_curr>
	return ret;
    4230:	e7ec      	b.n	420c <z_impl_k_sem_take+0x28>
    4232:	bf00      	nop
    4234:	20000ac4 	.word	0x20000ac4

00004238 <work_queue_main>:
/* Loop executed by a work queue thread.
 *
 * @param workq_ptr pointer to the work queue structure
 */
static void work_queue_main(void *workq_ptr, void *p2, void *p3)
{
    4238:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&pending_cancels, wc, tmp, node) {
    423c:	4e4b      	ldr	r6, [pc, #300]	; (436c <work_queue_main+0x134>)
{
    423e:	b085      	sub	sp, #20
    4240:	4604      	mov	r4, r0
			 * stop.  Just go to sleep: when something happens the
			 * work thread will be woken and we can check again.
			 */

			(void)z_sched_wait(&lock, key, &queue->notifyq,
					   K_FOREVER, NULL);
    4242:	f04f 38ff 	mov.w	r8, #4294967295
    4246:	f04f 39ff 	mov.w	r9, #4294967295
	__asm__ volatile(
    424a:	f04f 0320 	mov.w	r3, #32
    424e:	f3ef 8711 	mrs	r7, BASEPRI
    4252:	f383 8811 	msr	BASEPRI, r3
    4256:	f3bf 8f6f 	isb	sy
Z_GENLIST_IS_EMPTY(slist)
    425a:	f8d4 5080 	ldr.w	r5, [r4, #128]	; 0x80
	return list->head;
    425e:	f8d4 3098 	ldr.w	r3, [r4, #152]	; 0x98
 *
 * @return A pointer to the first node of the list (or NULL if empty)
 */
static inline sys_snode_t *sys_slist_get(sys_slist_t *list);

Z_GENLIST_GET(slist, snode)
    4262:	b985      	cbnz	r5, 4286 <work_queue_main+0x4e>
	*flagp &= ~BIT(bit);
    4264:	f023 0204 	bic.w	r2, r3, #4
		} else if (flag_test_and_clear(&queue->flags,
    4268:	075d      	lsls	r5, r3, #29
	*flagp &= ~BIT(bit);
    426a:	f8c4 2098 	str.w	r2, [r4, #152]	; 0x98
		} else if (flag_test_and_clear(&queue->flags,
    426e:	d433      	bmi.n	42d8 <work_queue_main+0xa0>
			(void)z_sched_wait(&lock, key, &queue->notifyq,
    4270:	2300      	movs	r3, #0
    4272:	e9cd 8900 	strd	r8, r9, [sp]
    4276:	9302      	str	r3, [sp, #8]
    4278:	f104 0288 	add.w	r2, r4, #136	; 0x88
    427c:	4639      	mov	r1, r7
    427e:	483c      	ldr	r0, [pc, #240]	; (4370 <work_queue_main+0x138>)
    4280:	f000 fc72 	bl	4b68 <z_sched_wait>
			continue;
    4284:	e7e1      	b.n	424a <work_queue_main+0x12>
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    4286:	f8d4 2084 	ldr.w	r2, [r4, #132]	; 0x84
    428a:	6829      	ldr	r1, [r5, #0]
	list->head = node;
    428c:	f8c4 1080 	str.w	r1, [r4, #128]	; 0x80
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    4290:	4295      	cmp	r5, r2
    4292:	d101      	bne.n	4298 <work_queue_main+0x60>
	list->tail = node;
    4294:	f8c4 1084 	str.w	r1, [r4, #132]	; 0x84
	*flagp |= BIT(bit);
    4298:	f043 0302 	orr.w	r3, r3, #2
    429c:	f8c4 3098 	str.w	r3, [r4, #152]	; 0x98
	*flagp &= ~BIT(bit);
    42a0:	68eb      	ldr	r3, [r5, #12]
    42a2:	f023 0304 	bic.w	r3, r3, #4
    42a6:	f043 0301 	orr.w	r3, r3, #1
    42aa:	60eb      	str	r3, [r5, #12]
			handler = work->handler;
    42ac:	686b      	ldr	r3, [r5, #4]
	__asm__ volatile(
    42ae:	f387 8811 	msr	BASEPRI, r7
    42b2:	f3bf 8f6f 	isb	sy

		if (work != NULL) {
			bool yield;

			__ASSERT_NO_MSG(handler != NULL);
			handler(work);
    42b6:	4628      	mov	r0, r5
    42b8:	4798      	blx	r3
	__asm__ volatile(
    42ba:	f04f 0320 	mov.w	r3, #32
    42be:	f3ef 8b11 	mrs	fp, BASEPRI
    42c2:	f383 8811 	msr	BASEPRI, r3
    42c6:	f3bf 8f6f 	isb	sy
	*flagp &= ~BIT(bit);
    42ca:	68eb      	ldr	r3, [r5, #12]
			 * starving other threads.
			 */
			key = k_spin_lock(&lock);

			flag_clear(&work->flags, K_WORK_RUNNING_BIT);
			if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
    42cc:	0799      	lsls	r1, r3, #30
	*flagp &= ~BIT(bit);
    42ce:	f023 0201 	bic.w	r2, r3, #1
			if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
    42d2:	d40b      	bmi.n	42ec <work_queue_main+0xb4>
	*flagp &= ~BIT(bit);
    42d4:	60ea      	str	r2, [r5, #12]
    42d6:	e00e      	b.n	42f6 <work_queue_main+0xbe>
			(void)z_sched_wake_all(&queue->drainq, 1, NULL);
    42d8:	f104 0590 	add.w	r5, r4, #144	; 0x90
static inline bool z_sched_wake_all(_wait_q_t *wait_q, int swap_retval,
				    void *swap_data)
{
	bool woken = false;

	while (z_sched_wake(wait_q, swap_retval, swap_data)) {
    42dc:	2200      	movs	r2, #0
    42de:	2101      	movs	r1, #1
    42e0:	4628      	mov	r0, r5
    42e2:	f002 fb7a 	bl	69da <z_sched_wake>
    42e6:	2800      	cmp	r0, #0
    42e8:	d1f8      	bne.n	42dc <work_queue_main+0xa4>
    42ea:	e7c1      	b.n	4270 <work_queue_main+0x38>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&pending_cancels, wc, tmp, node) {
    42ec:	6830      	ldr	r0, [r6, #0]
	*flagp &= ~BIT(bit);
    42ee:	f023 0303 	bic.w	r3, r3, #3
    42f2:	60eb      	str	r3, [r5, #12]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&pending_cancels, wc, tmp, node) {
    42f4:	b970      	cbnz	r0, 4314 <work_queue_main+0xdc>
	*flagp &= ~BIT(bit);
    42f6:	f8d4 3098 	ldr.w	r3, [r4, #152]	; 0x98
    42fa:	f023 0302 	bic.w	r3, r3, #2
    42fe:	f8c4 3098 	str.w	r3, [r4, #152]	; 0x98
	__asm__ volatile(
    4302:	f38b 8811 	msr	BASEPRI, fp
    4306:	f3bf 8f6f 	isb	sy
			k_spin_unlock(&lock, key);

			/* Optionally yield to prevent the work queue from
			 * starving other threads.
			 */
			if (yield) {
    430a:	05d8      	lsls	r0, r3, #23
    430c:	d49d      	bmi.n	424a <work_queue_main+0x12>
	z_impl_k_yield();
    430e:	f000 fb1b 	bl	4948 <z_impl_k_yield>
}
    4312:	e79a      	b.n	424a <work_queue_main+0x12>
	return node->next;
    4314:	6807      	ldr	r7, [r0, #0]
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    4316:	f04f 0a00 	mov.w	sl, #0
    431a:	2f00      	cmp	r7, #0
    431c:	bf38      	it	cc
    431e:	2700      	movcc	r7, #0
	parent->next = child;
    4320:	4653      	mov	r3, sl
		if (wc->work == work) {
    4322:	6842      	ldr	r2, [r0, #4]
    4324:	4295      	cmp	r5, r2
    4326:	4601      	mov	r1, r0
    4328:	d10e      	bne.n	4348 <work_queue_main+0x110>
 */
static inline void sys_slist_remove(sys_slist_t *list,
				    sys_snode_t *prev_node,
				    sys_snode_t *node);

Z_GENLIST_REMOVE(slist, snode)
    432a:	6801      	ldr	r1, [r0, #0]
    432c:	f1ba 0f00 	cmp.w	sl, #0
    4330:	d114      	bne.n	435c <work_queue_main+0x124>
    4332:	6872      	ldr	r2, [r6, #4]
	list->head = node;
    4334:	6031      	str	r1, [r6, #0]
Z_GENLIST_REMOVE(slist, snode)
    4336:	4290      	cmp	r0, r2
    4338:	d100      	bne.n	433c <work_queue_main+0x104>
	list->tail = node;
    433a:	6071      	str	r1, [r6, #4]
	parent->next = child;
    433c:	f840 3b08 	str.w	r3, [r0], #8
	z_impl_k_sem_give(sem);
    4340:	f7ff ff30 	bl	41a4 <z_impl_k_sem_give>
}
    4344:	4651      	mov	r1, sl
    4346:	2300      	movs	r3, #0
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&pending_cancels, wc, tmp, node) {
    4348:	2f00      	cmp	r7, #0
    434a:	d0d4      	beq.n	42f6 <work_queue_main+0xbe>
	return node->next;
    434c:	683a      	ldr	r2, [r7, #0]
    434e:	2a00      	cmp	r2, #0
    4350:	bf38      	it	cc
    4352:	2200      	movcc	r2, #0
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    4354:	4638      	mov	r0, r7
    4356:	468a      	mov	sl, r1
    4358:	4617      	mov	r7, r2
    435a:	e7e2      	b.n	4322 <work_queue_main+0xea>
	parent->next = child;
    435c:	f8ca 1000 	str.w	r1, [sl]
Z_GENLIST_REMOVE(slist, snode)
    4360:	6872      	ldr	r2, [r6, #4]
    4362:	4290      	cmp	r0, r2
	list->tail = node;
    4364:	bf08      	it	eq
    4366:	f8c6 a004 	streq.w	sl, [r6, #4]
}
    436a:	e7e7      	b.n	433c <work_queue_main+0x104>
    436c:	20000678 	.word	0x20000678
    4370:	20000ac5 	.word	0x20000ac5

00004374 <submit_to_queue_locked>:
{
    4374:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
    4376:	68c3      	ldr	r3, [r0, #12]
    4378:	079a      	lsls	r2, r3, #30
{
    437a:	4604      	mov	r4, r0
    437c:	460e      	mov	r6, r1
	if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
    437e:	f3c3 0540 	ubfx	r5, r3, #1, #1
    4382:	d41f      	bmi.n	43c4 <submit_to_queue_locked+0x50>
	} else if (!flag_test(&work->flags, K_WORK_QUEUED_BIT)) {
    4384:	075f      	lsls	r7, r3, #29
    4386:	d41f      	bmi.n	43c8 <submit_to_queue_locked+0x54>
		if (*queuep == NULL) {
    4388:	680a      	ldr	r2, [r1, #0]
    438a:	b90a      	cbnz	r2, 4390 <submit_to_queue_locked+0x1c>
			*queuep = work->queue;
    438c:	6882      	ldr	r2, [r0, #8]
    438e:	600a      	str	r2, [r1, #0]
		if (flag_test(&work->flags, K_WORK_RUNNING_BIT)) {
    4390:	07d8      	lsls	r0, r3, #31
			*queuep = work->queue;
    4392:	bf44      	itt	mi
    4394:	68a3      	ldrmi	r3, [r4, #8]
    4396:	6033      	strmi	r3, [r6, #0]
		int rc = queue_submit_locked(*queuep, work);
    4398:	6837      	ldr	r7, [r6, #0]
			ret = 2;
    439a:	bf4c      	ite	mi
    439c:	2502      	movmi	r5, #2
		ret = 1;
    439e:	2501      	movpl	r5, #1
	if (queue == NULL) {
    43a0:	b37f      	cbz	r7, 4402 <submit_to_queue_locked+0x8e>
	bool chained = (_current == &queue->thread) && !k_is_in_isr();
    43a2:	4b1b      	ldr	r3, [pc, #108]	; (4410 <submit_to_queue_locked+0x9c>)
    43a4:	689b      	ldr	r3, [r3, #8]
    43a6:	42bb      	cmp	r3, r7
    43a8:	d111      	bne.n	43ce <submit_to_queue_locked+0x5a>
    43aa:	f002 f9fd 	bl	67a8 <k_is_in_isr>
    43ae:	f080 0001 	eor.w	r0, r0, #1
    43b2:	b2c0      	uxtb	r0, r0
	bool draining = flag_test(&queue->flags, K_WORK_QUEUE_DRAIN_BIT);
    43b4:	f8d7 3098 	ldr.w	r3, [r7, #152]	; 0x98
	if (!flag_test(&queue->flags, K_WORK_QUEUE_STARTED_BIT)) {
    43b8:	07d9      	lsls	r1, r3, #31
	return (*flagp & BIT(bit)) != 0U;
    43ba:	f3c3 0280 	ubfx	r2, r3, #2, #1
	if (!flag_test(&queue->flags, K_WORK_QUEUE_STARTED_BIT)) {
    43be:	d523      	bpl.n	4408 <submit_to_queue_locked+0x94>
	} else if (draining && !chained) {
    43c0:	b13a      	cbz	r2, 43d2 <submit_to_queue_locked+0x5e>
    43c2:	b940      	cbnz	r0, 43d6 <submit_to_queue_locked+0x62>
		ret = -EBUSY;
    43c4:	f06f 050f 	mvn.w	r5, #15
		*queuep = NULL;
    43c8:	2300      	movs	r3, #0
    43ca:	6033      	str	r3, [r6, #0]
	return ret;
    43cc:	e013      	b.n	43f6 <submit_to_queue_locked+0x82>
	bool chained = (_current == &queue->thread) && !k_is_in_isr();
    43ce:	2000      	movs	r0, #0
    43d0:	e7f0      	b.n	43b4 <submit_to_queue_locked+0x40>
	} else if (plugged && !draining) {
    43d2:	071b      	lsls	r3, r3, #28
    43d4:	d4f6      	bmi.n	43c4 <submit_to_queue_locked+0x50>
	parent->next = child;
    43d6:	2300      	movs	r3, #0
    43d8:	6023      	str	r3, [r4, #0]
Z_GENLIST_APPEND(slist, snode)
    43da:	f8d7 3084 	ldr.w	r3, [r7, #132]	; 0x84
    43de:	b963      	cbnz	r3, 43fa <submit_to_queue_locked+0x86>
	list->head = node;
    43e0:	e9c7 4420 	strd	r4, r4, [r7, #128]	; 0x80
		(void)notify_queue_locked(queue);
    43e4:	4638      	mov	r0, r7
    43e6:	f002 fa06 	bl	67f6 <notify_queue_locked>
	*flagp |= BIT(bit);
    43ea:	68e3      	ldr	r3, [r4, #12]
    43ec:	f043 0304 	orr.w	r3, r3, #4
    43f0:	60e3      	str	r3, [r4, #12]
			work->queue = *queuep;
    43f2:	6833      	ldr	r3, [r6, #0]
    43f4:	60a3      	str	r3, [r4, #8]
}
    43f6:	4628      	mov	r0, r5
    43f8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	parent->next = child;
    43fa:	601c      	str	r4, [r3, #0]
	list->tail = node;
    43fc:	f8c7 4084 	str.w	r4, [r7, #132]	; 0x84
}
    4400:	e7f0      	b.n	43e4 <submit_to_queue_locked+0x70>
		return -EINVAL;
    4402:	f06f 0515 	mvn.w	r5, #21
    4406:	e7df      	b.n	43c8 <submit_to_queue_locked+0x54>
		ret = -ENODEV;
    4408:	f06f 0512 	mvn.w	r5, #18
    440c:	e7dc      	b.n	43c8 <submit_to_queue_locked+0x54>
    440e:	bf00      	nop
    4410:	20000648 	.word	0x20000648

00004414 <k_work_submit>:
{
    4414:	4601      	mov	r1, r0
	int ret = k_work_submit_to_queue(&k_sys_work_q, work);
    4416:	4801      	ldr	r0, [pc, #4]	; (441c <k_work_submit+0x8>)
    4418:	f002 b9f4 	b.w	6804 <k_work_submit_to_queue>
    441c:	200002d0 	.word	0x200002d0

00004420 <k_work_queue_start>:
void k_work_queue_start(struct k_work_q *queue,
			k_thread_stack_t *stack,
			size_t stack_size,
			int prio,
			const struct k_work_queue_config *cfg)
{
    4420:	b5f0      	push	{r4, r5, r6, r7, lr}
    4422:	b089      	sub	sp, #36	; 0x24
    4424:	4604      	mov	r4, r0
	list->head = NULL;
    4426:	2000      	movs	r0, #0
	list->tail = NULL;
    4428:	e9c4 0020 	strd	r0, r0, [r4, #128]	; 0x80
    442c:	9d0e      	ldr	r5, [sp, #56]	; 0x38
    442e:	f104 0088 	add.w	r0, r4, #136	; 0x88
	list->tail = (sys_dnode_t *)list;
    4432:	e9c4 0022 	strd	r0, r0, [r4, #136]	; 0x88
    4436:	f104 0090 	add.w	r0, r4, #144	; 0x90
    443a:	e9c4 0024 	strd	r0, r0, [r4, #144]	; 0x90

	sys_slist_init(&queue->pending);
	z_waitq_init(&queue->notifyq);
	z_waitq_init(&queue->drainq);

	if ((cfg != NULL) && cfg->no_yield) {
    443e:	b31d      	cbz	r5, 4488 <k_work_queue_start+0x68>
    4440:	7928      	ldrb	r0, [r5, #4]
		flags |= K_WORK_QUEUE_NO_YIELD;
    4442:	2800      	cmp	r0, #0
    4444:	f240 1001 	movw	r0, #257	; 0x101
    4448:	bf08      	it	eq
    444a:	2001      	moveq	r0, #1
	*flagp = flags;
    444c:	f8c4 0098 	str.w	r0, [r4, #152]	; 0x98
	return z_impl_k_thread_create(new_thread, stack, stack_size, entry, p1, p2, p3, prio, options, delay);
    4450:	2000      	movs	r0, #0
    4452:	f04f 36ff 	mov.w	r6, #4294967295
    4456:	f04f 37ff 	mov.w	r7, #4294967295
    445a:	e9cd 3003 	strd	r3, r0, [sp, #12]
    445e:	e9cd 0001 	strd	r0, r0, [sp, #4]
    4462:	e9cd 6706 	strd	r6, r7, [sp, #24]
    4466:	4b09      	ldr	r3, [pc, #36]	; (448c <k_work_queue_start+0x6c>)
    4468:	9400      	str	r4, [sp, #0]
    446a:	4620      	mov	r0, r4
    446c:	f7ff fd36 	bl	3edc <z_impl_k_thread_create>

	(void)k_thread_create(&queue->thread, stack, stack_size,
			      work_queue_main, queue, NULL, NULL,
			      prio, 0, K_FOREVER);

	if ((cfg != NULL) && (cfg->name != NULL)) {
    4470:	b125      	cbz	r5, 447c <k_work_queue_start+0x5c>
    4472:	6829      	ldr	r1, [r5, #0]
    4474:	b111      	cbz	r1, 447c <k_work_queue_start+0x5c>
	return z_impl_k_thread_name_set(thread, str);
    4476:	4620      	mov	r0, r4
    4478:	f002 f99c 	bl	67b4 <z_impl_k_thread_name_set>
	z_impl_k_thread_start(thread);
    447c:	4620      	mov	r0, r4
	}

	k_thread_start(&queue->thread);

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_work_queue, start, queue);
}
    447e:	b009      	add	sp, #36	; 0x24
    4480:	e8bd 40f0 	ldmia.w	sp!, {r4, r5, r6, r7, lr}
    4484:	f002 b99b 	b.w	67be <z_impl_k_thread_start>
	uint32_t flags = K_WORK_QUEUE_STARTED;
    4488:	2001      	movs	r0, #1
    448a:	e7df      	b.n	444c <k_work_queue_start+0x2c>
    448c:	00004239 	.word	0x00004239

00004490 <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(void)
{
    4490:	b510      	push	{r4, lr}
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time != 0) {
    4492:	4c08      	ldr	r4, [pc, #32]	; (44b4 <z_reset_time_slice+0x24>)
    4494:	6823      	ldr	r3, [r4, #0]
    4496:	b15b      	cbz	r3, 44b0 <z_reset_time_slice+0x20>
		_current_cpu->slice_ticks = slice_time + sys_clock_elapsed();
    4498:	f7fd ff44 	bl	2324 <sys_clock_elapsed>
    449c:	4603      	mov	r3, r0
    449e:	6820      	ldr	r0, [r4, #0]
    44a0:	4a05      	ldr	r2, [pc, #20]	; (44b8 <z_reset_time_slice+0x28>)
    44a2:	4403      	add	r3, r0
		z_set_timeout_expiry(slice_time, false);
	}
}
    44a4:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		_current_cpu->slice_ticks = slice_time + sys_clock_elapsed();
    44a8:	6113      	str	r3, [r2, #16]
		z_set_timeout_expiry(slice_time, false);
    44aa:	2100      	movs	r1, #0
    44ac:	f002 bad8 	b.w	6a60 <z_set_timeout_expiry>
}
    44b0:	bd10      	pop	{r4, pc}
    44b2:	bf00      	nop
    44b4:	20000688 	.word	0x20000688
    44b8:	20000648 	.word	0x20000648

000044bc <k_sched_time_slice_set>:

void k_sched_time_slice_set(int32_t slice, int prio)
{
    44bc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    44be:	4604      	mov	r4, r0
    44c0:	460d      	mov	r5, r1
	__asm__ volatile(
    44c2:	f04f 0320 	mov.w	r3, #32
    44c6:	f3ef 8611 	mrs	r6, BASEPRI
    44ca:	f383 8811 	msr	BASEPRI, r3
    44ce:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		_current_cpu->slice_ticks = 0;
    44d2:	4b10      	ldr	r3, [pc, #64]	; (4514 <k_sched_time_slice_set+0x58>)
    44d4:	2200      	movs	r2, #0
			return (uint32_t)((t * to_hz + off) / from_hz);
    44d6:	f44f 4700 	mov.w	r7, #32768	; 0x8000
    44da:	f240 30e7 	movw	r0, #999	; 0x3e7
    44de:	2100      	movs	r1, #0
    44e0:	611a      	str	r2, [r3, #16]
    44e2:	fbe7 0104 	umlal	r0, r1, r7, r4
    44e6:	2300      	movs	r3, #0
    44e8:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    44ec:	f7fb fe58 	bl	1a0 <__aeabi_uldivmod>
		slice_time = k_ms_to_ticks_ceil32(slice);
		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && slice > 0) {
    44f0:	2c00      	cmp	r4, #0
    44f2:	4b09      	ldr	r3, [pc, #36]	; (4518 <k_sched_time_slice_set+0x5c>)
    44f4:	dc09      	bgt.n	450a <k_sched_time_slice_set+0x4e>
			/* It's not possible to reliably set a 1-tick
			 * timeout if ticks aren't regular.
			 */
			slice_time = MAX(2, slice_time);
    44f6:	6018      	str	r0, [r3, #0]
		}
		slice_max_prio = prio;
    44f8:	4b08      	ldr	r3, [pc, #32]	; (451c <k_sched_time_slice_set+0x60>)
    44fa:	601d      	str	r5, [r3, #0]
		z_reset_time_slice();
    44fc:	f7ff ffc8 	bl	4490 <z_reset_time_slice>
	__asm__ volatile(
    4500:	f386 8811 	msr	BASEPRI, r6
    4504:	f3bf 8f6f 	isb	sy
	}
}
    4508:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
			slice_time = MAX(2, slice_time);
    450a:	2802      	cmp	r0, #2
    450c:	bfb8      	it	lt
    450e:	2002      	movlt	r0, #2
    4510:	e7f1      	b.n	44f6 <k_sched_time_slice_set+0x3a>
    4512:	bf00      	nop
    4514:	20000648 	.word	0x20000648
    4518:	20000688 	.word	0x20000688
    451c:	20000684 	.word	0x20000684

00004520 <z_reschedule>:
{
#ifdef CONFIG_SMP
	_current_cpu->swap_ok = 0;
#endif

	return arch_irq_unlocked(key) && !arch_is_in_isr();
    4520:	b949      	cbnz	r1, 4536 <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    4522:	f3ef 8005 	mrs	r0, IPSR
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
	if (resched(key.key) && need_swap()) {
    4526:	b930      	cbnz	r0, 4536 <z_reschedule+0x16>
	new_thread = _kernel.ready_q.cache;
    4528:	4b05      	ldr	r3, [pc, #20]	; (4540 <z_reschedule+0x20>)
	if (resched(key.key) && need_swap()) {
    452a:	6a5a      	ldr	r2, [r3, #36]	; 0x24
    452c:	689b      	ldr	r3, [r3, #8]
    452e:	429a      	cmp	r2, r3
    4530:	d001      	beq.n	4536 <z_reschedule+0x16>
	ret = arch_swap(key);
    4532:	f7fd bf1f 	b.w	2374 <arch_swap>
    4536:	f381 8811 	msr	BASEPRI, r1
    453a:	f3bf 8f6f 	isb	sy
		z_swap(lock, key);
	} else {
		k_spin_unlock(lock, key);
	}
}
    453e:	4770      	bx	lr
    4540:	20000648 	.word	0x20000648

00004544 <k_sched_lock>:
	__asm__ volatile(
    4544:	f04f 0320 	mov.w	r3, #32
    4548:	f3ef 8111 	mrs	r1, BASEPRI
    454c:	f383 8811 	msr	BASEPRI, r3
    4550:	f3bf 8f6f 	isb	sy
	--_current->base.sched_locked;
    4554:	4b04      	ldr	r3, [pc, #16]	; (4568 <k_sched_lock+0x24>)
    4556:	689a      	ldr	r2, [r3, #8]
    4558:	7bd3      	ldrb	r3, [r2, #15]
    455a:	3b01      	subs	r3, #1
    455c:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    455e:	f381 8811 	msr	BASEPRI, r1
    4562:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		SYS_PORT_TRACING_FUNC(k_thread, sched_lock);

		z_sched_lock();
	}
}
    4566:	4770      	bx	lr
    4568:	20000648 	.word	0x20000648

0000456c <update_cache>:
{
    456c:	b538      	push	{r3, r4, r5, lr}
    456e:	4602      	mov	r2, r0
	thread = _priq_run_best(&_kernel.ready_q.runq);
    4570:	480c      	ldr	r0, [pc, #48]	; (45a4 <update_cache+0x38>)
    4572:	4d0d      	ldr	r5, [pc, #52]	; (45a8 <update_cache+0x3c>)
    4574:	f002 f99b 	bl	68ae <z_priq_dumb_best>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    4578:	4604      	mov	r4, r0
    457a:	b900      	cbnz	r0, 457e <update_cache+0x12>
    457c:	68ec      	ldr	r4, [r5, #12]
	if (preempt_ok != 0) {
    457e:	68ab      	ldr	r3, [r5, #8]
    4580:	b94a      	cbnz	r2, 4596 <update_cache+0x2a>
	if (z_is_thread_prevented_from_running(_current)) {
    4582:	7b5a      	ldrb	r2, [r3, #13]
    4584:	06d2      	lsls	r2, r2, #27
    4586:	d106      	bne.n	4596 <update_cache+0x2a>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    4588:	69a2      	ldr	r2, [r4, #24]
    458a:	b922      	cbnz	r2, 4596 <update_cache+0x2a>
	if (is_preempt(_current) || is_metairq(thread)) {
    458c:	89da      	ldrh	r2, [r3, #14]
    458e:	2a7f      	cmp	r2, #127	; 0x7f
    4590:	d901      	bls.n	4596 <update_cache+0x2a>
		_kernel.ready_q.cache = _current;
    4592:	626b      	str	r3, [r5, #36]	; 0x24
}
    4594:	bd38      	pop	{r3, r4, r5, pc}
		if (thread != _current) {
    4596:	429c      	cmp	r4, r3
    4598:	d001      	beq.n	459e <update_cache+0x32>
			z_reset_time_slice();
    459a:	f7ff ff79 	bl	4490 <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    459e:	626c      	str	r4, [r5, #36]	; 0x24
}
    45a0:	e7f8      	b.n	4594 <update_cache+0x28>
    45a2:	bf00      	nop
    45a4:	20000670 	.word	0x20000670
    45a8:	20000648 	.word	0x20000648

000045ac <unready_thread>:
{
    45ac:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    45ae:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return z_is_thread_state_set(thread, _THREAD_QUEUED);
    45b2:	7b43      	ldrb	r3, [r0, #13]
    45b4:	2a00      	cmp	r2, #0
{
    45b6:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    45b8:	da04      	bge.n	45c4 <unready_thread+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    45ba:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    45be:	7343      	strb	r3, [r0, #13]

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
    45c0:	f002 f93d 	bl	683e <sys_dlist_remove>
	update_cache(thread == _current);
    45c4:	4b04      	ldr	r3, [pc, #16]	; (45d8 <unready_thread+0x2c>)
    45c6:	6898      	ldr	r0, [r3, #8]
    45c8:	1a43      	subs	r3, r0, r1
    45ca:	4258      	negs	r0, r3
    45cc:	4158      	adcs	r0, r3
}
    45ce:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    45d2:	f7ff bfcb 	b.w	456c <update_cache>
    45d6:	bf00      	nop
    45d8:	20000648 	.word	0x20000648

000045dc <pend>:
{
    45dc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    45e0:	4606      	mov	r6, r0
    45e2:	4614      	mov	r4, r2
    45e4:	461d      	mov	r5, r3
	__asm__ volatile(
    45e6:	f04f 0320 	mov.w	r3, #32
    45ea:	f3ef 8711 	mrs	r7, BASEPRI
    45ee:	f383 8811 	msr	BASEPRI, r3
    45f2:	f3bf 8f6f 	isb	sy
		add_to_waitq_locked(thread, wait_q);
    45f6:	f002 f964 	bl	68c2 <add_to_waitq_locked>
	__asm__ volatile(
    45fa:	f387 8811 	msr	BASEPRI, r7
    45fe:	f3bf 8f6f 	isb	sy
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    4602:	1c6b      	adds	r3, r5, #1
    4604:	bf08      	it	eq
    4606:	f1b4 3fff 	cmpeq.w	r4, #4294967295
    460a:	d008      	beq.n	461e <pend+0x42>
    460c:	4622      	mov	r2, r4
    460e:	462b      	mov	r3, r5
    4610:	f106 0018 	add.w	r0, r6, #24
    4614:	4903      	ldr	r1, [pc, #12]	; (4624 <pend+0x48>)
}
    4616:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    461a:	f000 bb21 	b.w	4c60 <z_add_timeout>
    461e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4622:	bf00      	nop
    4624:	0000693d 	.word	0x0000693d

00004628 <z_pend_curr>:
{
    4628:	b510      	push	{r4, lr}
	pending_current = _current;
    462a:	4b07      	ldr	r3, [pc, #28]	; (4648 <z_pend_curr+0x20>)
    462c:	6898      	ldr	r0, [r3, #8]
    462e:	4b07      	ldr	r3, [pc, #28]	; (464c <z_pend_curr+0x24>)
{
    4630:	460c      	mov	r4, r1
	pending_current = _current;
    4632:	6018      	str	r0, [r3, #0]
{
    4634:	4611      	mov	r1, r2
	pend(_current, wait_q, timeout);
    4636:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    463a:	f7ff ffcf 	bl	45dc <pend>
    463e:	4620      	mov	r0, r4
}
    4640:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    4644:	f7fd be96 	b.w	2374 <arch_swap>
    4648:	20000648 	.word	0x20000648
    464c:	20000680 	.word	0x20000680

00004650 <z_impl_k_thread_suspend>:
{
    4650:	b570      	push	{r4, r5, r6, lr}
    4652:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    4654:	3018      	adds	r0, #24
    4656:	f002 f9dd 	bl	6a14 <z_abort_timeout>
	__asm__ volatile(
    465a:	f04f 0320 	mov.w	r3, #32
    465e:	f3ef 8611 	mrs	r6, BASEPRI
    4662:	f383 8811 	msr	BASEPRI, r3
    4666:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    466a:	f994 200d 	ldrsb.w	r2, [r4, #13]
    466e:	7b63      	ldrb	r3, [r4, #13]
    4670:	2a00      	cmp	r2, #0
    4672:	da05      	bge.n	4680 <z_impl_k_thread_suspend+0x30>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    4674:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    4678:	7363      	strb	r3, [r4, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    467a:	4620      	mov	r0, r4
    467c:	f002 f8df 	bl	683e <sys_dlist_remove>
		update_cache(thread == _current);
    4680:	4d0b      	ldr	r5, [pc, #44]	; (46b0 <z_impl_k_thread_suspend+0x60>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    4682:	7b63      	ldrb	r3, [r4, #13]
    4684:	68a8      	ldr	r0, [r5, #8]
    4686:	f043 0310 	orr.w	r3, r3, #16
    468a:	7363      	strb	r3, [r4, #13]
    468c:	1b03      	subs	r3, r0, r4
    468e:	4258      	negs	r0, r3
    4690:	4158      	adcs	r0, r3
    4692:	f7ff ff6b 	bl	456c <update_cache>
	__asm__ volatile(
    4696:	f386 8811 	msr	BASEPRI, r6
    469a:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    469e:	68ab      	ldr	r3, [r5, #8]
    46a0:	42a3      	cmp	r3, r4
    46a2:	d103      	bne.n	46ac <z_impl_k_thread_suspend+0x5c>
}
    46a4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    46a8:	f002 b8f7 	b.w	689a <z_reschedule_unlocked>
}
    46ac:	bd70      	pop	{r4, r5, r6, pc}
    46ae:	bf00      	nop
    46b0:	20000648 	.word	0x20000648

000046b4 <k_sched_unlock>:
{
    46b4:	b510      	push	{r4, lr}
	__asm__ volatile(
    46b6:	f04f 0320 	mov.w	r3, #32
    46ba:	f3ef 8411 	mrs	r4, BASEPRI
    46be:	f383 8811 	msr	BASEPRI, r3
    46c2:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    46c6:	4b08      	ldr	r3, [pc, #32]	; (46e8 <k_sched_unlock+0x34>)
    46c8:	689a      	ldr	r2, [r3, #8]
    46ca:	7bd3      	ldrb	r3, [r2, #15]
    46cc:	3301      	adds	r3, #1
    46ce:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    46d0:	2000      	movs	r0, #0
    46d2:	f7ff ff4b 	bl	456c <update_cache>
	__asm__ volatile(
    46d6:	f384 8811 	msr	BASEPRI, r4
    46da:	f3bf 8f6f 	isb	sy
}
    46de:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    46e2:	f002 b8da 	b.w	689a <z_reschedule_unlocked>
    46e6:	bf00      	nop
    46e8:	20000648 	.word	0x20000648

000046ec <move_thread_to_end_of_prio_q>:
{
    46ec:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    46ee:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return z_is_thread_state_set(thread, _THREAD_QUEUED);
    46f2:	7b43      	ldrb	r3, [r0, #13]
    46f4:	2a00      	cmp	r2, #0
{
    46f6:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    46f8:	da04      	bge.n	4704 <move_thread_to_end_of_prio_q+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    46fa:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    46fe:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    4700:	f002 f89d 	bl	683e <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    4704:	7b4b      	ldrb	r3, [r1, #13]
	return list->head == list;
    4706:	4a17      	ldr	r2, [pc, #92]	; (4764 <move_thread_to_end_of_prio_q+0x78>)
    4708:	f063 037f 	orn	r3, r3, #127	; 0x7f
    470c:	4610      	mov	r0, r2
    470e:	734b      	strb	r3, [r1, #13]
    4710:	f850 3f28 	ldr.w	r3, [r0, #40]!
 */

static inline sys_dnode_t *sys_dlist_peek_next(sys_dlist_t *list,
					       sys_dnode_t *node)
{
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    4714:	6ad5      	ldr	r5, [r2, #44]	; 0x2c
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4716:	4283      	cmp	r3, r0
    4718:	bf08      	it	eq
    471a:	2300      	moveq	r3, #0
    471c:	2b00      	cmp	r3, #0
    471e:	bf38      	it	cc
    4720:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4722:	b1cb      	cbz	r3, 4758 <move_thread_to_end_of_prio_q+0x6c>
	int32_t b1 = thread_1->base.prio;
    4724:	f991 600e 	ldrsb.w	r6, [r1, #14]
	int32_t b2 = thread_2->base.prio;
    4728:	f993 400e 	ldrsb.w	r4, [r3, #14]
	if (b1 != b2) {
    472c:	42a6      	cmp	r6, r4
    472e:	d00f      	beq.n	4750 <move_thread_to_end_of_prio_q+0x64>
		return b2 - b1;
    4730:	1ba4      	subs	r4, r4, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    4732:	2c00      	cmp	r4, #0
    4734:	dd0c      	ble.n	4750 <move_thread_to_end_of_prio_q+0x64>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    4736:	6858      	ldr	r0, [r3, #4]

	node->prev = prev;
	node->next = successor;
    4738:	e9c1 3000 	strd	r3, r0, [r1]
	prev->next = node;
    473c:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    473e:	6059      	str	r1, [r3, #4]
	update_cache(thread == _current);
    4740:	6890      	ldr	r0, [r2, #8]
    4742:	1a43      	subs	r3, r0, r1
    4744:	4258      	negs	r0, r3
}
    4746:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    474a:	4158      	adcs	r0, r3
    474c:	f7ff bf0e 	b.w	456c <update_cache>
	return (node == list->tail) ? NULL : node->next;
    4750:	42ab      	cmp	r3, r5
    4752:	d001      	beq.n	4758 <move_thread_to_end_of_prio_q+0x6c>
    4754:	681b      	ldr	r3, [r3, #0]
    4756:	e7e4      	b.n	4722 <move_thread_to_end_of_prio_q+0x36>
	node->prev = tail;
    4758:	e9c1 0500 	strd	r0, r5, [r1]
	tail->next = node;
    475c:	6029      	str	r1, [r5, #0]
	list->tail = node;
    475e:	62d1      	str	r1, [r2, #44]	; 0x2c
}
    4760:	e7ee      	b.n	4740 <move_thread_to_end_of_prio_q+0x54>
    4762:	bf00      	nop
    4764:	20000648 	.word	0x20000648

00004768 <z_time_slice>:
{
    4768:	b570      	push	{r4, r5, r6, lr}
    476a:	4601      	mov	r1, r0
	__asm__ volatile(
    476c:	f04f 0320 	mov.w	r3, #32
    4770:	f3ef 8411 	mrs	r4, BASEPRI
    4774:	f383 8811 	msr	BASEPRI, r3
    4778:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    477c:	4b16      	ldr	r3, [pc, #88]	; (47d8 <z_time_slice+0x70>)
    477e:	4a17      	ldr	r2, [pc, #92]	; (47dc <z_time_slice+0x74>)
    4780:	6898      	ldr	r0, [r3, #8]
    4782:	6815      	ldr	r5, [r2, #0]
    4784:	42a8      	cmp	r0, r5
    4786:	461d      	mov	r5, r3
    4788:	d106      	bne.n	4798 <z_time_slice+0x30>
			z_reset_time_slice();
    478a:	f7ff fe81 	bl	4490 <z_reset_time_slice>
	__asm__ volatile(
    478e:	f384 8811 	msr	BASEPRI, r4
    4792:	f3bf 8f6f 	isb	sy
}
    4796:	bd70      	pop	{r4, r5, r6, pc}
	pending_current = NULL;
    4798:	2600      	movs	r6, #0
    479a:	6016      	str	r6, [r2, #0]
	if (slice_time && sliceable(_current)) {
    479c:	4a10      	ldr	r2, [pc, #64]	; (47e0 <z_time_slice+0x78>)
    479e:	6812      	ldr	r2, [r2, #0]
    47a0:	b1ba      	cbz	r2, 47d2 <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    47a2:	89c2      	ldrh	r2, [r0, #14]
    47a4:	2a7f      	cmp	r2, #127	; 0x7f
    47a6:	d814      	bhi.n	47d2 <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
    47a8:	7b42      	ldrb	r2, [r0, #13]
    47aa:	06d2      	lsls	r2, r2, #27
    47ac:	d111      	bne.n	47d2 <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    47ae:	4a0d      	ldr	r2, [pc, #52]	; (47e4 <z_time_slice+0x7c>)
    47b0:	f990 600e 	ldrsb.w	r6, [r0, #14]
    47b4:	6812      	ldr	r2, [r2, #0]
    47b6:	4296      	cmp	r6, r2
    47b8:	db0b      	blt.n	47d2 <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    47ba:	4a0b      	ldr	r2, [pc, #44]	; (47e8 <z_time_slice+0x80>)
    47bc:	4290      	cmp	r0, r2
    47be:	d008      	beq.n	47d2 <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
    47c0:	691a      	ldr	r2, [r3, #16]
    47c2:	428a      	cmp	r2, r1
    47c4:	dc02      	bgt.n	47cc <z_time_slice+0x64>
			move_thread_to_end_of_prio_q(_current);
    47c6:	f7ff ff91 	bl	46ec <move_thread_to_end_of_prio_q>
    47ca:	e7de      	b.n	478a <z_time_slice+0x22>
			_current_cpu->slice_ticks -= ticks;
    47cc:	1a52      	subs	r2, r2, r1
    47ce:	611a      	str	r2, [r3, #16]
    47d0:	e7dd      	b.n	478e <z_time_slice+0x26>
		_current_cpu->slice_ticks = 0;
    47d2:	2300      	movs	r3, #0
    47d4:	612b      	str	r3, [r5, #16]
    47d6:	e7da      	b.n	478e <z_time_slice+0x26>
    47d8:	20000648 	.word	0x20000648
    47dc:	20000680 	.word	0x20000680
    47e0:	20000688 	.word	0x20000688
    47e4:	20000684 	.word	0x20000684
    47e8:	200001c8 	.word	0x200001c8

000047ec <ready_thread>:
{
    47ec:	b470      	push	{r4, r5, r6}
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    47ee:	f990 300d 	ldrsb.w	r3, [r0, #13]
    47f2:	7b42      	ldrb	r2, [r0, #13]
    47f4:	2b00      	cmp	r3, #0
    47f6:	db2d      	blt.n	4854 <ready_thread+0x68>
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    47f8:	06d3      	lsls	r3, r2, #27
    47fa:	d12b      	bne.n	4854 <ready_thread+0x68>
	return !sys_dnode_is_linked(&to->node);
    47fc:	6983      	ldr	r3, [r0, #24]
    47fe:	bb4b      	cbnz	r3, 4854 <ready_thread+0x68>
	return list->head == list;
    4800:	4915      	ldr	r1, [pc, #84]	; (4858 <ready_thread+0x6c>)
	thread->base.thread_state |= _THREAD_QUEUED;
    4802:	f062 027f 	orn	r2, r2, #127	; 0x7f
    4806:	7342      	strb	r2, [r0, #13]
    4808:	460a      	mov	r2, r1
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    480a:	6acd      	ldr	r5, [r1, #44]	; 0x2c
	return list->head == list;
    480c:	f852 4f28 	ldr.w	r4, [r2, #40]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4810:	4294      	cmp	r4, r2
    4812:	bf18      	it	ne
    4814:	4623      	movne	r3, r4
    4816:	2b00      	cmp	r3, #0
    4818:	bf38      	it	cc
    481a:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    481c:	b1ab      	cbz	r3, 484a <ready_thread+0x5e>
	int32_t b1 = thread_1->base.prio;
    481e:	f990 600e 	ldrsb.w	r6, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    4822:	f993 400e 	ldrsb.w	r4, [r3, #14]
	if (b1 != b2) {
    4826:	42a6      	cmp	r6, r4
    4828:	d00b      	beq.n	4842 <ready_thread+0x56>
		return b2 - b1;
    482a:	1ba4      	subs	r4, r4, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    482c:	2c00      	cmp	r4, #0
    482e:	dd08      	ble.n	4842 <ready_thread+0x56>
	sys_dnode_t *const prev = successor->prev;
    4830:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    4832:	e9c0 3200 	strd	r3, r2, [r0]
	prev->next = node;
    4836:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    4838:	6058      	str	r0, [r3, #4]
}
    483a:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    483c:	2000      	movs	r0, #0
    483e:	f7ff be95 	b.w	456c <update_cache>
	return (node == list->tail) ? NULL : node->next;
    4842:	42ab      	cmp	r3, r5
    4844:	d001      	beq.n	484a <ready_thread+0x5e>
    4846:	681b      	ldr	r3, [r3, #0]
    4848:	e7e8      	b.n	481c <ready_thread+0x30>
	node->prev = tail;
    484a:	e9c0 2500 	strd	r2, r5, [r0]
	tail->next = node;
    484e:	6028      	str	r0, [r5, #0]
	list->tail = node;
    4850:	62c8      	str	r0, [r1, #44]	; 0x2c
}
    4852:	e7f2      	b.n	483a <ready_thread+0x4e>
}
    4854:	bc70      	pop	{r4, r5, r6}
    4856:	4770      	bx	lr
    4858:	20000648 	.word	0x20000648

0000485c <z_sched_start>:
{
    485c:	b510      	push	{r4, lr}
	__asm__ volatile(
    485e:	f04f 0220 	mov.w	r2, #32
    4862:	f3ef 8411 	mrs	r4, BASEPRI
    4866:	f382 8811 	msr	BASEPRI, r2
    486a:	f3bf 8f6f 	isb	sy
	if (z_has_thread_started(thread)) {
    486e:	7b42      	ldrb	r2, [r0, #13]
    4870:	0751      	lsls	r1, r2, #29
    4872:	d404      	bmi.n	487e <z_sched_start+0x22>
	__asm__ volatile(
    4874:	f384 8811 	msr	BASEPRI, r4
    4878:	f3bf 8f6f 	isb	sy
}
    487c:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    487e:	f022 0204 	bic.w	r2, r2, #4
    4882:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    4884:	f7ff ffb2 	bl	47ec <ready_thread>
	z_reschedule(&sched_spinlock, key);
    4888:	4621      	mov	r1, r4
    488a:	4802      	ldr	r0, [pc, #8]	; (4894 <z_sched_start+0x38>)
}
    488c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    4890:	f7ff be46 	b.w	4520 <z_reschedule>
    4894:	20000ac6 	.word	0x20000ac6

00004898 <z_set_prio>:
{
    4898:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    489a:	4604      	mov	r4, r0
	__asm__ volatile(
    489c:	f04f 0320 	mov.w	r3, #32
    48a0:	f3ef 8611 	mrs	r6, BASEPRI
    48a4:	f383 8811 	msr	BASEPRI, r3
    48a8:	f3bf 8f6f 	isb	sy
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    48ac:	7b43      	ldrb	r3, [r0, #13]
    48ae:	06da      	lsls	r2, r3, #27
    48b0:	b249      	sxtb	r1, r1
    48b2:	d138      	bne.n	4926 <z_set_prio+0x8e>
    48b4:	6985      	ldr	r5, [r0, #24]
		if (need_sched) {
    48b6:	2d00      	cmp	r5, #0
    48b8:	d135      	bne.n	4926 <z_set_prio+0x8e>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    48ba:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    48be:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    48c0:	f001 ffbd 	bl	683e <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    48c4:	7b43      	ldrb	r3, [r0, #13]
				thread->base.prio = prio;
    48c6:	7381      	strb	r1, [r0, #14]
	thread->base.thread_state |= _THREAD_QUEUED;
    48c8:	f063 037f 	orn	r3, r3, #127	; 0x7f
    48cc:	7343      	strb	r3, [r0, #13]
	return list->head == list;
    48ce:	4817      	ldr	r0, [pc, #92]	; (492c <z_set_prio+0x94>)
    48d0:	4603      	mov	r3, r0
    48d2:	f853 7f28 	ldr.w	r7, [r3, #40]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    48d6:	429f      	cmp	r7, r3
    48d8:	bf18      	it	ne
    48da:	463d      	movne	r5, r7
    48dc:	2d00      	cmp	r5, #0
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    48de:	6ac7      	ldr	r7, [r0, #44]	; 0x2c
    48e0:	461a      	mov	r2, r3
    48e2:	462b      	mov	r3, r5
    48e4:	bf38      	it	cc
    48e6:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    48e8:	b1c3      	cbz	r3, 491c <z_set_prio+0x84>
	int32_t b2 = thread_2->base.prio;
    48ea:	f993 500e 	ldrsb.w	r5, [r3, #14]
	if (b1 != b2) {
    48ee:	42a9      	cmp	r1, r5
    48f0:	d010      	beq.n	4914 <z_set_prio+0x7c>
		return b2 - b1;
    48f2:	1a6d      	subs	r5, r5, r1
		if (z_sched_prio_cmp(thread, t) > 0) {
    48f4:	2d00      	cmp	r5, #0
    48f6:	dd0d      	ble.n	4914 <z_set_prio+0x7c>
	sys_dnode_t *const prev = successor->prev;
    48f8:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    48fa:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    48fe:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    4900:	605c      	str	r4, [r3, #4]
			update_cache(1);
    4902:	2001      	movs	r0, #1
    4904:	f7ff fe32 	bl	456c <update_cache>
    4908:	2001      	movs	r0, #1
	__asm__ volatile(
    490a:	f386 8811 	msr	BASEPRI, r6
    490e:	f3bf 8f6f 	isb	sy
}
    4912:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return (node == list->tail) ? NULL : node->next;
    4914:	42bb      	cmp	r3, r7
    4916:	d001      	beq.n	491c <z_set_prio+0x84>
    4918:	681b      	ldr	r3, [r3, #0]
    491a:	e7e5      	b.n	48e8 <z_set_prio+0x50>
	node->prev = tail;
    491c:	e9c4 2700 	strd	r2, r7, [r4]
	tail->next = node;
    4920:	603c      	str	r4, [r7, #0]
	list->tail = node;
    4922:	62c4      	str	r4, [r0, #44]	; 0x2c
}
    4924:	e7ed      	b.n	4902 <z_set_prio+0x6a>
			thread->base.prio = prio;
    4926:	73a1      	strb	r1, [r4, #14]
    4928:	2000      	movs	r0, #0
    492a:	e7ee      	b.n	490a <z_set_prio+0x72>
    492c:	20000648 	.word	0x20000648

00004930 <z_sched_init>:
	list->head = (sys_dnode_t *)list;
    4930:	4b04      	ldr	r3, [pc, #16]	; (4944 <z_sched_init+0x14>)
		sys_dlist_init(&_kernel.ready_q.runq.queues[i]);
	}
#endif

#ifdef CONFIG_TIMESLICING
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    4932:	2100      	movs	r1, #0
    4934:	f103 0228 	add.w	r2, r3, #40	; 0x28
	list->tail = (sys_dnode_t *)list;
    4938:	e9c3 220a 	strd	r2, r2, [r3, #40]	; 0x28
    493c:	4608      	mov	r0, r1
    493e:	f7ff bdbd 	b.w	44bc <k_sched_time_slice_set>
    4942:	bf00      	nop
    4944:	20000648 	.word	0x20000648

00004948 <z_impl_k_yield>:
#include <syscalls/k_thread_deadline_set_mrsh.c>
#endif
#endif

void z_impl_k_yield(void)
{
    4948:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	__asm__ volatile(
    494a:	f04f 0320 	mov.w	r3, #32
    494e:	f3ef 8411 	mrs	r4, BASEPRI
    4952:	f383 8811 	msr	BASEPRI, r3
    4956:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if (!IS_ENABLED(CONFIG_SMP) ||
	    z_is_thread_queued(_current)) {
		dequeue_thread(&_kernel.ready_q.runq,
    495a:	491b      	ldr	r1, [pc, #108]	; (49c8 <z_impl_k_yield+0x80>)
    495c:	6888      	ldr	r0, [r1, #8]
	thread->base.thread_state &= ~_THREAD_QUEUED;
    495e:	7b43      	ldrb	r3, [r0, #13]
    4960:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    4964:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    4966:	f001 ff6a 	bl	683e <sys_dlist_remove>
			       _current);
	}
	queue_thread(&_kernel.ready_q.runq, _current);
    496a:	688a      	ldr	r2, [r1, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    496c:	7b53      	ldrb	r3, [r2, #13]
	return list->head == list;
    496e:	4608      	mov	r0, r1
    4970:	f063 037f 	orn	r3, r3, #127	; 0x7f
    4974:	7353      	strb	r3, [r2, #13]
    4976:	f850 3f28 	ldr.w	r3, [r0, #40]!
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    497a:	6ace      	ldr	r6, [r1, #44]	; 0x2c
	return sys_dlist_is_empty(list) ? NULL : list->head;
    497c:	4283      	cmp	r3, r0
    497e:	bf08      	it	eq
    4980:	2300      	moveq	r3, #0
    4982:	2b00      	cmp	r3, #0
    4984:	bf38      	it	cc
    4986:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4988:	b1cb      	cbz	r3, 49be <z_impl_k_yield+0x76>
	int32_t b1 = thread_1->base.prio;
    498a:	f992 700e 	ldrsb.w	r7, [r2, #14]
	int32_t b2 = thread_2->base.prio;
    498e:	f993 500e 	ldrsb.w	r5, [r3, #14]
	if (b1 != b2) {
    4992:	42af      	cmp	r7, r5
    4994:	d00f      	beq.n	49b6 <z_impl_k_yield+0x6e>
		return b2 - b1;
    4996:	1bed      	subs	r5, r5, r7
		if (z_sched_prio_cmp(thread, t) > 0) {
    4998:	2d00      	cmp	r5, #0
    499a:	dd0c      	ble.n	49b6 <z_impl_k_yield+0x6e>
	sys_dnode_t *const prev = successor->prev;
    499c:	6859      	ldr	r1, [r3, #4]
	node->next = successor;
    499e:	e9c2 3100 	strd	r3, r1, [r2]
	prev->next = node;
    49a2:	600a      	str	r2, [r1, #0]
	successor->prev = node;
    49a4:	605a      	str	r2, [r3, #4]
	update_cache(1);
    49a6:	2001      	movs	r0, #1
    49a8:	f7ff fde0 	bl	456c <update_cache>
    49ac:	4620      	mov	r0, r4
	z_swap(&sched_spinlock, key);
}
    49ae:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    49b2:	f7fd bcdf 	b.w	2374 <arch_swap>
	return (node == list->tail) ? NULL : node->next;
    49b6:	42b3      	cmp	r3, r6
    49b8:	d001      	beq.n	49be <z_impl_k_yield+0x76>
    49ba:	681b      	ldr	r3, [r3, #0]
    49bc:	e7e4      	b.n	4988 <z_impl_k_yield+0x40>
	node->prev = tail;
    49be:	e9c2 0600 	strd	r0, r6, [r2]
	tail->next = node;
    49c2:	6032      	str	r2, [r6, #0]
	list->tail = node;
    49c4:	62ca      	str	r2, [r1, #44]	; 0x2c
}
    49c6:	e7ee      	b.n	49a6 <z_impl_k_yield+0x5e>
    49c8:	20000648 	.word	0x20000648

000049cc <z_tick_sleep>:
}
#include <syscalls/k_yield_mrsh.c>
#endif

static int32_t z_tick_sleep(k_ticks_t ticks)
{
    49cc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    49d0:	4604      	mov	r4, r0
    49d2:	460d      	mov	r5, r1
	 */
	LOG_DBG("thread %p for %u ticks", _current, ticks);
#endif

	/* wait of 0 ms is treated as a 'yield' */
	if (ticks == 0) {
    49d4:	ea54 0105 	orrs.w	r1, r4, r5
    49d8:	d104      	bne.n	49e4 <z_tick_sleep+0x18>
	z_impl_k_yield();
    49da:	f7ff ffb5 	bl	4948 <z_impl_k_yield>
		k_yield();
		return 0;
    49de:	2000      	movs	r0, #0
		return ticks;
	}
#endif

	return 0;
}
    49e0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if (Z_TICK_ABS(ticks) <= 0) {
    49e4:	f06f 0101 	mvn.w	r1, #1
    49e8:	1a0a      	subs	r2, r1, r0
    49ea:	f04f 31ff 	mov.w	r1, #4294967295
    49ee:	eb61 0305 	sbc.w	r3, r1, r5
    49f2:	2a01      	cmp	r2, #1
    49f4:	f173 0300 	sbcs.w	r3, r3, #0
    49f8:	da2a      	bge.n	4a50 <z_tick_sleep+0x84>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    49fa:	f002 f84b 	bl	6a94 <sys_clock_tick_get_32>
    49fe:	1906      	adds	r6, r0, r4
    4a00:	f04f 0320 	mov.w	r3, #32
    4a04:	f3ef 8811 	mrs	r8, BASEPRI
    4a08:	f383 8811 	msr	BASEPRI, r3
    4a0c:	f3bf 8f6f 	isb	sy
	pending_current = _current;
    4a10:	4f11      	ldr	r7, [pc, #68]	; (4a58 <z_tick_sleep+0x8c>)
    4a12:	4b12      	ldr	r3, [pc, #72]	; (4a5c <z_tick_sleep+0x90>)
    4a14:	68b8      	ldr	r0, [r7, #8]
    4a16:	6018      	str	r0, [r3, #0]
	unready_thread(_current);
    4a18:	f7ff fdc8 	bl	45ac <unready_thread>
	z_add_thread_timeout(_current, timeout);
    4a1c:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    4a1e:	4910      	ldr	r1, [pc, #64]	; (4a60 <z_tick_sleep+0x94>)
    4a20:	4622      	mov	r2, r4
    4a22:	462b      	mov	r3, r5
    4a24:	3018      	adds	r0, #24
    4a26:	f000 f91b 	bl	4c60 <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    4a2a:	68ba      	ldr	r2, [r7, #8]
	thread->base.thread_state |= _THREAD_SUSPENDED;
    4a2c:	7b53      	ldrb	r3, [r2, #13]
    4a2e:	f043 0310 	orr.w	r3, r3, #16
    4a32:	7353      	strb	r3, [r2, #13]
    4a34:	4640      	mov	r0, r8
    4a36:	f7fd fc9d 	bl	2374 <arch_swap>
	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    4a3a:	f002 f82b 	bl	6a94 <sys_clock_tick_get_32>
    4a3e:	1a30      	subs	r0, r6, r0
    4a40:	eb66 0106 	sbc.w	r1, r6, r6
	if (ticks > 0) {
    4a44:	2801      	cmp	r0, #1
    4a46:	f171 0300 	sbcs.w	r3, r1, #0
		return ticks;
    4a4a:	bfb8      	it	lt
    4a4c:	2000      	movlt	r0, #0
    4a4e:	e7c7      	b.n	49e0 <z_tick_sleep+0x14>
		expected_wakeup_ticks = Z_TICK_ABS(ticks);
    4a50:	f06f 0601 	mvn.w	r6, #1
    4a54:	1a36      	subs	r6, r6, r0
    4a56:	e7d3      	b.n	4a00 <z_tick_sleep+0x34>
    4a58:	20000648 	.word	0x20000648
    4a5c:	20000680 	.word	0x20000680
    4a60:	0000693d 	.word	0x0000693d

00004a64 <z_impl_k_sleep>:

int32_t z_impl_k_sleep(k_timeout_t timeout)
{
    4a64:	b508      	push	{r3, lr}
    4a66:	460b      	mov	r3, r1
	__ASSERT(!arch_is_in_isr(), "");

	SYS_PORT_TRACING_FUNC_ENTER(k_thread, sleep, timeout);

	/* in case of K_FOREVER, we suspend */
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    4a68:	3301      	adds	r3, #1
    4a6a:	bf08      	it	eq
    4a6c:	f1b0 3fff 	cmpeq.w	r0, #4294967295
    4a70:	d106      	bne.n	4a80 <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
    4a72:	4b08      	ldr	r3, [pc, #32]	; (4a94 <z_impl_k_sleep+0x30>)
    4a74:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    4a76:	f7ff fdeb 	bl	4650 <z_impl_k_thread_suspend>

		SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER);

		return (int32_t) K_TICKS_FOREVER;
    4a7a:	f04f 30ff 	mov.w	r0, #4294967295
	int32_t ret = k_ticks_to_ms_floor64(ticks);

	SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ret);

	return ret;
}
    4a7e:	bd08      	pop	{r3, pc}
	ticks = z_tick_sleep(ticks);
    4a80:	f7ff ffa4 	bl	49cc <z_tick_sleep>
			return (t * to_hz + off) / from_hz;
    4a84:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    4a88:	fb80 2303 	smull	r2, r3, r0, r3
    4a8c:	0bd0      	lsrs	r0, r2, #15
    4a8e:	ea40 4043 	orr.w	r0, r0, r3, lsl #17
	return ret;
    4a92:	e7f4      	b.n	4a7e <z_impl_k_sleep+0x1a>
    4a94:	20000648 	.word	0x20000648

00004a98 <z_impl_k_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    4a98:	4b01      	ldr	r3, [pc, #4]	; (4aa0 <z_impl_k_current_get+0x8>)
    4a9a:	6898      	ldr	r0, [r3, #8]
    4a9c:	4770      	bx	lr
    4a9e:	bf00      	nop
    4aa0:	20000648 	.word	0x20000648

00004aa4 <z_impl_k_is_preempt_thread>:
    4aa4:	f3ef 8305 	mrs	r3, IPSR
#include <syscalls/k_current_get_mrsh.c>
#endif

int z_impl_k_is_preempt_thread(void)
{
	return !arch_is_in_isr() && is_preempt(_current);
    4aa8:	b93b      	cbnz	r3, 4aba <z_impl_k_is_preempt_thread+0x16>
    4aaa:	4b05      	ldr	r3, [pc, #20]	; (4ac0 <z_impl_k_is_preempt_thread+0x1c>)
    4aac:	689b      	ldr	r3, [r3, #8]
    4aae:	89d8      	ldrh	r0, [r3, #14]
    4ab0:	287f      	cmp	r0, #127	; 0x7f
    4ab2:	bf8c      	ite	hi
    4ab4:	2000      	movhi	r0, #0
    4ab6:	2001      	movls	r0, #1
    4ab8:	4770      	bx	lr
    4aba:	2000      	movs	r0, #0
}
    4abc:	4770      	bx	lr
    4abe:	bf00      	nop
    4ac0:	20000648 	.word	0x20000648

00004ac4 <z_thread_abort>:
#endif
	}
}

void z_thread_abort(struct k_thread *thread)
{
    4ac4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4ac8:	4604      	mov	r4, r0
    4aca:	f04f 0320 	mov.w	r3, #32
    4ace:	f3ef 8611 	mrs	r6, BASEPRI
    4ad2:	f383 8811 	msr	BASEPRI, r3
    4ad6:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    4ada:	7b43      	ldrb	r3, [r0, #13]
    4adc:	071a      	lsls	r2, r3, #28
    4ade:	d505      	bpl.n	4aec <z_thread_abort+0x28>
	__asm__ volatile(
    4ae0:	f386 8811 	msr	BASEPRI, r6
    4ae4:	f3bf 8f6f 	isb	sy
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
	}
	k_spin_unlock(&sched_spinlock, key);
}
    4ae8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		thread->base.thread_state &= ~_THREAD_ABORTING;
    4aec:	f023 0220 	bic.w	r2, r3, #32
    4af0:	f042 0108 	orr.w	r1, r2, #8
		if (z_is_thread_queued(thread)) {
    4af4:	09d2      	lsrs	r2, r2, #7
    4af6:	d120      	bne.n	4b3a <z_thread_abort+0x76>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    4af8:	7341      	strb	r1, [r0, #13]
		if (thread->base.pended_on != NULL) {
    4afa:	68a3      	ldr	r3, [r4, #8]
    4afc:	b113      	cbz	r3, 4b04 <z_thread_abort+0x40>
			unpend_thread_no_timeout(thread);
    4afe:	4620      	mov	r0, r4
    4b00:	f001 fea5 	bl	684e <unpend_thread_no_timeout>
	return z_abort_timeout(&thread->base.timeout);
    4b04:	f104 0018 	add.w	r0, r4, #24
    4b08:	f001 ff84 	bl	6a14 <z_abort_timeout>
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    4b0c:	f104 0758 	add.w	r7, r4, #88	; 0x58
    4b10:	f04f 0800 	mov.w	r8, #0
	return list->head == list;
    4b14:	6da5      	ldr	r5, [r4, #88]	; 0x58
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4b16:	42bd      	cmp	r5, r7
    4b18:	d000      	beq.n	4b1c <z_thread_abort+0x58>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    4b1a:	b9b5      	cbnz	r5, 4b4a <z_thread_abort+0x86>
		update_cache(1);
    4b1c:	2001      	movs	r0, #1
    4b1e:	f7ff fd25 	bl	456c <update_cache>
	if (thread == _current && !arch_is_in_isr()) {
    4b22:	4b10      	ldr	r3, [pc, #64]	; (4b64 <z_thread_abort+0xa0>)
    4b24:	689b      	ldr	r3, [r3, #8]
    4b26:	42a3      	cmp	r3, r4
    4b28:	d1da      	bne.n	4ae0 <z_thread_abort+0x1c>
    4b2a:	f3ef 8305 	mrs	r3, IPSR
    4b2e:	2b00      	cmp	r3, #0
    4b30:	d1d6      	bne.n	4ae0 <z_thread_abort+0x1c>
    4b32:	4630      	mov	r0, r6
    4b34:	f7fd fc1e 	bl	2374 <arch_swap>
	return ret;
    4b38:	e7d2      	b.n	4ae0 <z_thread_abort+0x1c>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    4b3a:	f003 035f 	and.w	r3, r3, #95	; 0x5f
    4b3e:	f043 0308 	orr.w	r3, r3, #8
    4b42:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    4b44:	f001 fe7b 	bl	683e <sys_dlist_remove>
}
    4b48:	e7d7      	b.n	4afa <z_thread_abort+0x36>
		unpend_thread_no_timeout(thread);
    4b4a:	4628      	mov	r0, r5
    4b4c:	f001 fe7f 	bl	684e <unpend_thread_no_timeout>
    4b50:	f105 0018 	add.w	r0, r5, #24
    4b54:	f001 ff5e 	bl	6a14 <z_abort_timeout>
    4b58:	f8c5 8078 	str.w	r8, [r5, #120]	; 0x78
		ready_thread(thread);
    4b5c:	4628      	mov	r0, r5
    4b5e:	f7ff fe45 	bl	47ec <ready_thread>
    4b62:	e7d7      	b.n	4b14 <z_thread_abort+0x50>
    4b64:	20000648 	.word	0x20000648

00004b68 <z_sched_wait>:
	return ret;
}

int z_sched_wait(struct k_spinlock *lock, k_spinlock_key_t key,
		 _wait_q_t *wait_q, k_timeout_t timeout, void **data)
{
    4b68:	b5d3      	push	{r0, r1, r4, r6, r7, lr}
	int ret = z_pend_curr(lock, key, wait_q, timeout);
    4b6a:	e9dd 6706 	ldrd	r6, r7, [sp, #24]
{
    4b6e:	9c08      	ldr	r4, [sp, #32]
	int ret = z_pend_curr(lock, key, wait_q, timeout);
    4b70:	e9cd 6700 	strd	r6, r7, [sp]
    4b74:	f7ff fd58 	bl	4628 <z_pend_curr>

	if (data != NULL) {
    4b78:	b11c      	cbz	r4, 4b82 <z_sched_wait+0x1a>
		*data = _current->base.swap_data;
    4b7a:	4b03      	ldr	r3, [pc, #12]	; (4b88 <z_sched_wait+0x20>)
    4b7c:	689b      	ldr	r3, [r3, #8]
    4b7e:	695b      	ldr	r3, [r3, #20]
    4b80:	6023      	str	r3, [r4, #0]
	}
	return ret;
}
    4b82:	b002      	add	sp, #8
    4b84:	bdd0      	pop	{r4, r6, r7, pc}
    4b86:	bf00      	nop
    4b88:	20000648 	.word	0x20000648

00004b8c <z_data_copy>:
 * This routine copies the data section from ROM to RAM.
 *
 * @return N/A
 */
void z_data_copy(void)
{
    4b8c:	b508      	push	{r3, lr}
__ssp_bos_icheck3_restrict(memcpy, void *, const void *)
    4b8e:	4806      	ldr	r0, [pc, #24]	; (4ba8 <z_data_copy+0x1c>)
    4b90:	4a06      	ldr	r2, [pc, #24]	; (4bac <z_data_copy+0x20>)
    4b92:	4907      	ldr	r1, [pc, #28]	; (4bb0 <z_data_copy+0x24>)
    4b94:	1a12      	subs	r2, r2, r0
    4b96:	f001 ffb3 	bl	6b00 <memcpy>
#else
	(void)memcpy(&_app_smem_start, &_app_smem_rom_start,
		 _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    4b9a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    4b9e:	4a05      	ldr	r2, [pc, #20]	; (4bb4 <z_data_copy+0x28>)
    4ba0:	4905      	ldr	r1, [pc, #20]	; (4bb8 <z_data_copy+0x2c>)
    4ba2:	4806      	ldr	r0, [pc, #24]	; (4bbc <z_data_copy+0x30>)
    4ba4:	f001 bfac 	b.w	6b00 <memcpy>
    4ba8:	20000000 	.word	0x20000000
    4bac:	2000010c 	.word	0x2000010c
    4bb0:	00007b10 	.word	0x00007b10
    4bb4:	00000000 	.word	0x00000000
    4bb8:	00007b10 	.word	0x00007b10
    4bbc:	20000000 	.word	0x20000000

00004bc0 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    4bc0:	4b03      	ldr	r3, [pc, #12]	; (4bd0 <elapsed+0x10>)
    4bc2:	681b      	ldr	r3, [r3, #0]
    4bc4:	b90b      	cbnz	r3, 4bca <elapsed+0xa>
    4bc6:	f7fd bbad 	b.w	2324 <sys_clock_elapsed>
}
    4bca:	2000      	movs	r0, #0
    4bcc:	4770      	bx	lr
    4bce:	bf00      	nop
    4bd0:	2000068c 	.word	0x2000068c

00004bd4 <remove_timeout>:
{
    4bd4:	b530      	push	{r4, r5, lr}
    4bd6:	6803      	ldr	r3, [r0, #0]
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    4bd8:	b168      	cbz	r0, 4bf6 <remove_timeout+0x22>
    4bda:	4a0a      	ldr	r2, [pc, #40]	; (4c04 <remove_timeout+0x30>)
	return (node == list->tail) ? NULL : node->next;
    4bdc:	6852      	ldr	r2, [r2, #4]
    4bde:	4290      	cmp	r0, r2
    4be0:	d009      	beq.n	4bf6 <remove_timeout+0x22>
	if (next(t) != NULL) {
    4be2:	b143      	cbz	r3, 4bf6 <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    4be4:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    4be8:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    4bec:	1912      	adds	r2, r2, r4
    4bee:	eb45 0101 	adc.w	r1, r5, r1
    4bf2:	e9c3 2104 	strd	r2, r1, [r3, #16]
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
    4bf6:	6842      	ldr	r2, [r0, #4]
	sys_dnode_t *const next = node->next;

	prev->next = next;
    4bf8:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    4bfa:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    4bfc:	2300      	movs	r3, #0
	node->prev = NULL;
    4bfe:	e9c0 3300 	strd	r3, r3, [r0]
}
    4c02:	bd30      	pop	{r4, r5, pc}
    4c04:	20000044 	.word	0x20000044

00004c08 <next_timeout>:

static int32_t next_timeout(void)
{
    4c08:	b538      	push	{r3, r4, r5, lr}
	return list->head == list;
    4c0a:	4b13      	ldr	r3, [pc, #76]	; (4c58 <next_timeout+0x50>)
    4c0c:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4c0e:	429c      	cmp	r4, r3
    4c10:	bf08      	it	eq
    4c12:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    4c14:	f7ff ffd4 	bl	4bc0 <elapsed>
    4c18:	4605      	mov	r5, r0
	int32_t ret = to == NULL ? MAX_WAIT
    4c1a:	b1bc      	cbz	r4, 4c4c <next_timeout+0x44>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    4c1c:	e9d4 0104 	ldrd	r0, r1, [r4, #16]
    4c20:	1b40      	subs	r0, r0, r5
    4c22:	eb61 71e5 	sbc.w	r1, r1, r5, asr #31
	int32_t ret = to == NULL ? MAX_WAIT
    4c26:	2801      	cmp	r0, #1
    4c28:	f171 0300 	sbcs.w	r3, r1, #0
    4c2c:	db11      	blt.n	4c52 <next_timeout+0x4a>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    4c2e:	f06f 4200 	mvn.w	r2, #2147483648	; 0x80000000
    4c32:	2300      	movs	r3, #0
    4c34:	4282      	cmp	r2, r0
    4c36:	eb73 0401 	sbcs.w	r4, r3, r1
    4c3a:	da00      	bge.n	4c3e <next_timeout+0x36>
    4c3c:	4610      	mov	r0, r2

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    4c3e:	4b07      	ldr	r3, [pc, #28]	; (4c5c <next_timeout+0x54>)
    4c40:	691b      	ldr	r3, [r3, #16]
    4c42:	b113      	cbz	r3, 4c4a <next_timeout+0x42>
    4c44:	4298      	cmp	r0, r3
    4c46:	bfa8      	it	ge
    4c48:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    4c4a:	bd38      	pop	{r3, r4, r5, pc}
	int32_t ret = to == NULL ? MAX_WAIT
    4c4c:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    4c50:	e7f5      	b.n	4c3e <next_timeout+0x36>
    4c52:	2000      	movs	r0, #0
    4c54:	e7f3      	b.n	4c3e <next_timeout+0x36>
    4c56:	bf00      	nop
    4c58:	20000044 	.word	0x20000044
    4c5c:	20000648 	.word	0x20000648

00004c60 <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    4c60:	f1b3 3fff 	cmp.w	r3, #4294967295
    4c64:	bf08      	it	eq
    4c66:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    4c6a:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4c6e:	4604      	mov	r4, r0
    4c70:	4692      	mov	sl, r2
    4c72:	469b      	mov	fp, r3
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    4c74:	d073      	beq.n	4d5e <z_add_timeout+0xfe>
#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    4c76:	6081      	str	r1, [r0, #8]
	__asm__ volatile(
    4c78:	f04f 0320 	mov.w	r3, #32
    4c7c:	f3ef 8511 	mrs	r5, BASEPRI
    4c80:	f383 8811 	msr	BASEPRI, r3
    4c84:	f3bf 8f6f 	isb	sy

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
		    Z_TICK_ABS(timeout.ticks) >= 0) {
    4c88:	f06f 0301 	mvn.w	r3, #1
    4c8c:	ebb3 080a 	subs.w	r8, r3, sl
    4c90:	f04f 32ff 	mov.w	r2, #4294967295
    4c94:	eb62 090b 	sbc.w	r9, r2, fp
		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    4c98:	f1b8 0f00 	cmp.w	r8, #0
    4c9c:	f179 0100 	sbcs.w	r1, r9, #0
    4ca0:	db1c      	blt.n	4cdc <z_add_timeout+0x7c>
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    4ca2:	4830      	ldr	r0, [pc, #192]	; (4d64 <z_add_timeout+0x104>)
    4ca4:	e9d0 1000 	ldrd	r1, r0, [r0]
    4ca8:	1a5b      	subs	r3, r3, r1
    4caa:	eb62 0200 	sbc.w	r2, r2, r0

			to->dticks = MAX(1, ticks);
    4cae:	ebb3 060a 	subs.w	r6, r3, sl
    4cb2:	eb62 070b 	sbc.w	r7, r2, fp
    4cb6:	2e01      	cmp	r6, #1
    4cb8:	f177 0300 	sbcs.w	r3, r7, #0
    4cbc:	bfbc      	itt	lt
    4cbe:	2601      	movlt	r6, #1
    4cc0:	2700      	movlt	r7, #0
    4cc2:	e9c4 6704 	strd	r6, r7, [r4, #16]
	return list->head == list;
    4cc6:	4a28      	ldr	r2, [pc, #160]	; (4d68 <z_add_timeout+0x108>)
    4cc8:	e9d2 3c00 	ldrd	r3, ip, [r2]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4ccc:	4293      	cmp	r3, r2
    4cce:	d11e      	bne.n	4d0e <z_add_timeout+0xae>
	node->prev = tail;
    4cd0:	e9c4 2c00 	strd	r2, ip, [r4]
	tail->next = node;
    4cd4:	f8cc 4000 	str.w	r4, [ip]
	list->tail = node;
    4cd8:	6054      	str	r4, [r2, #4]
}
    4cda:	e02d      	b.n	4d38 <z_add_timeout+0xd8>
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
    4cdc:	f7ff ff70 	bl	4bc0 <elapsed>
    4ce0:	f11a 0301 	adds.w	r3, sl, #1
    4ce4:	9300      	str	r3, [sp, #0]
    4ce6:	f14b 0300 	adc.w	r3, fp, #0
    4cea:	9301      	str	r3, [sp, #4]
    4cec:	e9dd 2300 	ldrd	r2, r3, [sp]
    4cf0:	1812      	adds	r2, r2, r0
    4cf2:	eb43 73e0 	adc.w	r3, r3, r0, asr #31
    4cf6:	e9c4 2304 	strd	r2, r3, [r4, #16]
    4cfa:	e7e4      	b.n	4cc6 <z_add_timeout+0x66>
			if (t->dticks > to->dticks) {
				t->dticks -= to->dticks;
				sys_dlist_insert(&t->node, &to->node);
				break;
			}
			to->dticks -= t->dticks;
    4cfc:	ebb6 0008 	subs.w	r0, r6, r8
    4d00:	eb67 0109 	sbc.w	r1, r7, r9
	return (node == list->tail) ? NULL : node->next;
    4d04:	4563      	cmp	r3, ip
    4d06:	e9c4 0104 	strd	r0, r1, [r4, #16]
    4d0a:	d0e1      	beq.n	4cd0 <z_add_timeout+0x70>
    4d0c:	681b      	ldr	r3, [r3, #0]
		for (t = first(); t != NULL; t = next(t)) {
    4d0e:	2b00      	cmp	r3, #0
    4d10:	d0de      	beq.n	4cd0 <z_add_timeout+0x70>
			if (t->dticks > to->dticks) {
    4d12:	e9d3 8904 	ldrd	r8, r9, [r3, #16]
    4d16:	e9d4 6704 	ldrd	r6, r7, [r4, #16]
    4d1a:	4546      	cmp	r6, r8
    4d1c:	eb77 0109 	sbcs.w	r1, r7, r9
    4d20:	daec      	bge.n	4cfc <z_add_timeout+0x9c>
				t->dticks -= to->dticks;
    4d22:	ebb8 0006 	subs.w	r0, r8, r6
    4d26:	eb69 0107 	sbc.w	r1, r9, r7
    4d2a:	e9c3 0104 	strd	r0, r1, [r3, #16]
	sys_dnode_t *const prev = successor->prev;
    4d2e:	6859      	ldr	r1, [r3, #4]
	node->next = successor;
    4d30:	e9c4 3100 	strd	r3, r1, [r4]
	prev->next = node;
    4d34:	600c      	str	r4, [r1, #0]
	successor->prev = node;
    4d36:	605c      	str	r4, [r3, #4]
	return list->head == list;
    4d38:	6813      	ldr	r3, [r2, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4d3a:	4293      	cmp	r3, r2
    4d3c:	d00b      	beq.n	4d56 <z_add_timeout+0xf6>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    4d3e:	429c      	cmp	r4, r3
    4d40:	d109      	bne.n	4d56 <z_add_timeout+0xf6>
			 * last announcement, and slice_ticks is based
			 * on that. It means that the time remaining for
			 * the next announcement can be less than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    4d42:	f7ff ff61 	bl	4c08 <next_timeout>

			if (next_time == 0 ||
    4d46:	b118      	cbz	r0, 4d50 <z_add_timeout+0xf0>
			    _current_cpu->slice_ticks != next_time) {
    4d48:	4b08      	ldr	r3, [pc, #32]	; (4d6c <z_add_timeout+0x10c>)
			if (next_time == 0 ||
    4d4a:	691b      	ldr	r3, [r3, #16]
    4d4c:	4283      	cmp	r3, r0
    4d4e:	d002      	beq.n	4d56 <z_add_timeout+0xf6>
				sys_clock_set_timeout(next_time, false);
    4d50:	2100      	movs	r1, #0
    4d52:	f7fd fab5 	bl	22c0 <sys_clock_set_timeout>
	__asm__ volatile(
    4d56:	f385 8811 	msr	BASEPRI, r5
    4d5a:	f3bf 8f6f 	isb	sy
#else
			sys_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    4d5e:	b003      	add	sp, #12
    4d60:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    4d64:	200002c8 	.word	0x200002c8
    4d68:	20000044 	.word	0x20000044
    4d6c:	20000648 	.word	0x20000648

00004d70 <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    4d70:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4d74:	4606      	mov	r6, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    4d76:	f7ff fcf7 	bl	4768 <z_time_slice>
	__asm__ volatile(
    4d7a:	f04f 0320 	mov.w	r3, #32
    4d7e:	f3ef 8411 	mrs	r4, BASEPRI
    4d82:	f383 8811 	msr	BASEPRI, r3
    4d86:	f3bf 8f6f 	isb	sy
#endif

	k_spinlock_key_t key = k_spin_lock(&timeout_lock);

	announce_remaining = ticks;
    4d8a:	4d2c      	ldr	r5, [pc, #176]	; (4e3c <sys_clock_announce+0xcc>)
    4d8c:	f8df a0b0 	ldr.w	sl, [pc, #176]	; 4e40 <sys_clock_announce+0xd0>
	return list->head == list;
    4d90:	f8df b0b0 	ldr.w	fp, [pc, #176]	; 4e44 <sys_clock_announce+0xd4>
    4d94:	602e      	str	r6, [r5, #0]

	while (first() != NULL && first()->dticks <= announce_remaining) {
    4d96:	4651      	mov	r1, sl
    4d98:	f8d5 c000 	ldr.w	ip, [r5]
    4d9c:	f8db 0000 	ldr.w	r0, [fp]
    4da0:	4662      	mov	r2, ip
    4da2:	17d3      	asrs	r3, r2, #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4da4:	4558      	cmp	r0, fp
    4da6:	e9da 8900 	ldrd	r8, r9, [sl]
    4daa:	e9cd 2300 	strd	r2, r3, [sp]
    4dae:	d00d      	beq.n	4dcc <sys_clock_announce+0x5c>
    4db0:	b160      	cbz	r0, 4dcc <sys_clock_announce+0x5c>
    4db2:	e9d0 6704 	ldrd	r6, r7, [r0, #16]
    4db6:	45b4      	cmp	ip, r6
    4db8:	41bb      	sbcs	r3, r7
    4dba:	da1e      	bge.n	4dfa <sys_clock_announce+0x8a>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    4dbc:	9b00      	ldr	r3, [sp, #0]
    4dbe:	ebb6 0c03 	subs.w	ip, r6, r3
    4dc2:	9b01      	ldr	r3, [sp, #4]
    4dc4:	eb67 0603 	sbc.w	r6, r7, r3
    4dc8:	e9c0 c604 	strd	ip, r6, [r0, #16]
	}

	curr_tick += announce_remaining;
    4dcc:	9b00      	ldr	r3, [sp, #0]
    4dce:	eb13 0208 	adds.w	r2, r3, r8
    4dd2:	9b01      	ldr	r3, [sp, #4]
	announce_remaining = 0;
    4dd4:	f04f 0600 	mov.w	r6, #0
	curr_tick += announce_remaining;
    4dd8:	eb43 0309 	adc.w	r3, r3, r9
    4ddc:	e9c1 2300 	strd	r2, r3, [r1]
	announce_remaining = 0;
    4de0:	602e      	str	r6, [r5, #0]

	sys_clock_set_timeout(next_timeout(), false);
    4de2:	f7ff ff11 	bl	4c08 <next_timeout>
    4de6:	4631      	mov	r1, r6
    4de8:	f7fd fa6a 	bl	22c0 <sys_clock_set_timeout>
	__asm__ volatile(
    4dec:	f384 8811 	msr	BASEPRI, r4
    4df0:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    4df4:	b003      	add	sp, #12
    4df6:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		curr_tick += dt;
    4dfa:	eb18 0806 	adds.w	r8, r8, r6
		t->dticks = 0;
    4dfe:	f04f 0200 	mov.w	r2, #0
    4e02:	f04f 0300 	mov.w	r3, #0
		curr_tick += dt;
    4e06:	eb49 79e6 	adc.w	r9, r9, r6, asr #31
		t->dticks = 0;
    4e0a:	e9c0 2304 	strd	r2, r3, [r0, #16]
		announce_remaining -= dt;
    4e0e:	ebac 0606 	sub.w	r6, ip, r6
		curr_tick += dt;
    4e12:	e9ca 8900 	strd	r8, r9, [sl]
		announce_remaining -= dt;
    4e16:	602e      	str	r6, [r5, #0]
		remove_timeout(t);
    4e18:	f7ff fedc 	bl	4bd4 <remove_timeout>
    4e1c:	f384 8811 	msr	BASEPRI, r4
    4e20:	f3bf 8f6f 	isb	sy
		t->fn(t);
    4e24:	6883      	ldr	r3, [r0, #8]
    4e26:	4798      	blx	r3
	__asm__ volatile(
    4e28:	f04f 0320 	mov.w	r3, #32
    4e2c:	f3ef 8411 	mrs	r4, BASEPRI
    4e30:	f383 8811 	msr	BASEPRI, r3
    4e34:	f3bf 8f6f 	isb	sy

	/* Note that we need to use the underlying arch-specific lock
	 * implementation.  The "irq_lock()" API in SMP context is
	 * actually a wrapper for a global spinlock!
	 */
	k.key = arch_irq_lock();
    4e38:	4901      	ldr	r1, [pc, #4]	; (4e40 <sys_clock_announce+0xd0>)
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    4e3a:	e7ad      	b.n	4d98 <sys_clock_announce+0x28>
    4e3c:	2000068c 	.word	0x2000068c
    4e40:	200002c8 	.word	0x200002c8
    4e44:	20000044 	.word	0x20000044

00004e48 <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    4e48:	b510      	push	{r4, lr}
    4e4a:	f04f 0320 	mov.w	r3, #32
    4e4e:	f3ef 8411 	mrs	r4, BASEPRI
    4e52:	f383 8811 	msr	BASEPRI, r3
    4e56:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + sys_clock_elapsed();
    4e5a:	f7fd fa63 	bl	2324 <sys_clock_elapsed>
    4e5e:	4b06      	ldr	r3, [pc, #24]	; (4e78 <sys_clock_tick_get+0x30>)
    4e60:	e9d3 2300 	ldrd	r2, r3, [r3]
    4e64:	1812      	adds	r2, r2, r0
    4e66:	f143 0300 	adc.w	r3, r3, #0
	__asm__ volatile(
    4e6a:	f384 8811 	msr	BASEPRI, r4
    4e6e:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    4e72:	4610      	mov	r0, r2
    4e74:	4619      	mov	r1, r3
    4e76:	bd10      	pop	{r4, pc}
    4e78:	200002c8 	.word	0x200002c8

00004e7c <z_timer_expiration_handler>:
 * @param t  Timeout used by the timer.
 *
 * @return N/A
 */
void z_timer_expiration_handler(struct _timeout *t)
{
    4e7c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}

	/*
	 * if the timer is periodic, start it again; don't add _TICK_ALIGN
	 * since we're already aligned to a tick boundary
	 */
	if (!K_TIMEOUT_EQ(timer->period, K_NO_WAIT) &&
    4e7e:	e9d0 230a 	ldrd	r2, r3, [r0, #40]	; 0x28
    4e82:	1c56      	adds	r6, r2, #1
    4e84:	f143 0700 	adc.w	r7, r3, #0
    4e88:	2f00      	cmp	r7, #0
    4e8a:	bf08      	it	eq
    4e8c:	2e02      	cmpeq	r6, #2
{
    4e8e:	4604      	mov	r4, r0
	if (!K_TIMEOUT_EQ(timer->period, K_NO_WAIT) &&
    4e90:	d302      	bcc.n	4e98 <z_timer_expiration_handler+0x1c>
	    !K_TIMEOUT_EQ(timer->period, K_FOREVER)) {
		z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    4e92:	490d      	ldr	r1, [pc, #52]	; (4ec8 <z_timer_expiration_handler+0x4c>)
    4e94:	f7ff fee4 	bl	4c60 <z_add_timeout>
			     timer->period);
	}

	/* update timer's status */
	timer->status += 1U;
    4e98:	6b23      	ldr	r3, [r4, #48]	; 0x30
    4e9a:	3301      	adds	r3, #1
    4e9c:	6323      	str	r3, [r4, #48]	; 0x30

	/* invoke timer expiry function */
	if (timer->expiry_fn != NULL) {
    4e9e:	6a23      	ldr	r3, [r4, #32]
    4ea0:	b10b      	cbz	r3, 4ea6 <z_timer_expiration_handler+0x2a>
		timer->expiry_fn(timer);
    4ea2:	4620      	mov	r0, r4
    4ea4:	4798      	blx	r3
	return list->head == list;
    4ea6:	f854 5f18 	ldr.w	r5, [r4, #24]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4eaa:	42a5      	cmp	r5, r4
    4eac:	d00a      	beq.n	4ec4 <z_timer_expiration_handler+0x48>
		return;
	}

	thread = z_waitq_head(&timer->wait_q);

	if (thread == NULL) {
    4eae:	b14d      	cbz	r5, 4ec4 <z_timer_expiration_handler+0x48>
	 * place a thread can be taken off this pend queue, and b) the
	 * only place a thread can be put on the pend queue is at
	 * thread level, which of course cannot interrupt the current
	 * context.
	 */
	z_unpend_thread_no_timeout(thread);
    4eb0:	4628      	mov	r0, r5
    4eb2:	f001 fcd6 	bl	6862 <z_unpend_thread_no_timeout>
    4eb6:	2300      	movs	r3, #0
    4eb8:	67ab      	str	r3, [r5, #120]	; 0x78

	arch_thread_return_value_set(thread, 0);

	z_ready_thread(thread);
    4eba:	4628      	mov	r0, r5
}
    4ebc:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
	z_ready_thread(thread);
    4ec0:	f001 bd2c 	b.w	691c <z_ready_thread>
}
    4ec4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    4ec6:	bf00      	nop
    4ec8:	00004e7d 	.word	0x00004e7d

00004ecc <z_impl_k_timer_start>:
}


void z_impl_k_timer_start(struct k_timer *timer, k_timeout_t duration,
			  k_timeout_t period)
{
    4ecc:	e92d 4f73 	stmdb	sp!, {r0, r1, r4, r5, r6, r8, r9, sl, fp, lr}
    4ed0:	4619      	mov	r1, r3
    4ed2:	4606      	mov	r6, r0
	SYS_PORT_TRACING_OBJ_FUNC(k_timer, start, timer);

	if (K_TIMEOUT_EQ(duration, K_FOREVER)) {
    4ed4:	1c4c      	adds	r4, r1, #1
{
    4ed6:	4610      	mov	r0, r2
	if (K_TIMEOUT_EQ(duration, K_FOREVER)) {
    4ed8:	bf08      	it	eq
    4eda:	f1b0 3fff 	cmpeq.w	r0, #4294967295
{
    4ede:	e9dd 230a 	ldrd	r2, r3, [sp, #40]	; 0x28
    4ee2:	4680      	mov	r8, r0
    4ee4:	4689      	mov	r9, r1
	if (K_TIMEOUT_EQ(duration, K_FOREVER)) {
    4ee6:	d04c      	beq.n	4f82 <z_impl_k_timer_start+0xb6>
    4ee8:	461d      	mov	r5, r3
	 * for backwards compatibility.  This is unfortunate
	 * (i.e. k_timer_start() doesn't treat its initial sleep
	 * argument the same way k_sleep() does), but historical.  The
	 * timer_api test relies on this behavior.
	 */
	if (!K_TIMEOUT_EQ(period, K_FOREVER) && period.ticks != 0 &&
    4eea:	1c6b      	adds	r3, r5, #1
    4eec:	bf08      	it	eq
    4eee:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    4ef2:	4614      	mov	r4, r2
    4ef4:	d019      	beq.n	4f2a <z_impl_k_timer_start+0x5e>
    4ef6:	ea54 0305 	orrs.w	r3, r4, r5
    4efa:	d016      	beq.n	4f2a <z_impl_k_timer_start+0x5e>
	    Z_TICK_ABS(period.ticks) < 0) {
    4efc:	f06f 0301 	mvn.w	r3, #1
    4f00:	ebb3 0a02 	subs.w	sl, r3, r2
    4f04:	f04f 33ff 	mov.w	r3, #4294967295
    4f08:	eb63 0b05 	sbc.w	fp, r3, r5
	if (!K_TIMEOUT_EQ(period, K_FOREVER) && period.ticks != 0 &&
    4f0c:	f1ba 0f00 	cmp.w	sl, #0
    4f10:	f17b 0300 	sbcs.w	r3, fp, #0
    4f14:	da09      	bge.n	4f2a <z_impl_k_timer_start+0x5e>
		period.ticks = MAX(period.ticks - 1, 1);
    4f16:	f112 34ff 	adds.w	r4, r2, #4294967295
    4f1a:	f145 35ff 	adc.w	r5, r5, #4294967295
    4f1e:	2c01      	cmp	r4, #1
    4f20:	f175 0300 	sbcs.w	r3, r5, #0
    4f24:	bfbc      	itt	lt
    4f26:	2401      	movlt	r4, #1
    4f28:	2500      	movlt	r5, #0
	}
	if (Z_TICK_ABS(duration.ticks) < 0) {
    4f2a:	f06f 0301 	mvn.w	r3, #1
    4f2e:	1a1b      	subs	r3, r3, r0
    4f30:	9300      	str	r3, [sp, #0]
    4f32:	f04f 33ff 	mov.w	r3, #4294967295
    4f36:	eb63 0301 	sbc.w	r3, r3, r1
    4f3a:	9301      	str	r3, [sp, #4]
    4f3c:	e9dd 2300 	ldrd	r2, r3, [sp]
    4f40:	2a00      	cmp	r2, #0
    4f42:	f173 0300 	sbcs.w	r3, r3, #0
    4f46:	da0c      	bge.n	4f62 <z_impl_k_timer_start+0x96>
		duration.ticks = MAX(duration.ticks - 1, 0);
    4f48:	f110 38ff 	adds.w	r8, r0, #4294967295
    4f4c:	f141 39ff 	adc.w	r9, r1, #4294967295
    4f50:	f1b8 0f00 	cmp.w	r8, #0
    4f54:	f179 0300 	sbcs.w	r3, r9, #0
    4f58:	bfbc      	itt	lt
    4f5a:	f04f 0800 	movlt.w	r8, #0
    4f5e:	f04f 0900 	movlt.w	r9, #0
	}

	(void)z_abort_timeout(&timer->timeout);
    4f62:	4630      	mov	r0, r6
    4f64:	f001 fd56 	bl	6a14 <z_abort_timeout>
	timer->period = period;
	timer->status = 0U;
    4f68:	2300      	movs	r3, #0

	z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    4f6a:	4907      	ldr	r1, [pc, #28]	; (4f88 <z_impl_k_timer_start+0xbc>)
	timer->status = 0U;
    4f6c:	6333      	str	r3, [r6, #48]	; 0x30
	z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    4f6e:	4642      	mov	r2, r8
    4f70:	464b      	mov	r3, r9
    4f72:	4630      	mov	r0, r6
	timer->period = period;
    4f74:	e9c6 450a 	strd	r4, r5, [r6, #40]	; 0x28
		     duration);
}
    4f78:	b002      	add	sp, #8
    4f7a:	e8bd 4f70 	ldmia.w	sp!, {r4, r5, r6, r8, r9, sl, fp, lr}
	z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    4f7e:	f7ff be6f 	b.w	4c60 <z_add_timeout>
}
    4f82:	b002      	add	sp, #8
    4f84:	e8bd 8f70 	ldmia.w	sp!, {r4, r5, r6, r8, r9, sl, fp, pc}
    4f88:	00004e7d 	.word	0x00004e7d

00004f8c <boot_banner>:
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
    4f8c:	4a02      	ldr	r2, [pc, #8]	; (4f98 <boot_banner+0xc>)
    4f8e:	4903      	ldr	r1, [pc, #12]	; (4f9c <boot_banner+0x10>)
    4f90:	4803      	ldr	r0, [pc, #12]	; (4fa0 <boot_banner+0x14>)
    4f92:	f000 be64 	b.w	5c5e <printk>
    4f96:	bf00      	nop
    4f98:	000073bf 	.word	0x000073bf
    4f9c:	0000799c 	.word	0x0000799c
    4fa0:	000079a9 	.word	0x000079a9

00004fa4 <k_sys_work_q_init>:
			     CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE);

struct k_work_q k_sys_work_q;

static int k_sys_work_q_init(const struct device *dev)
{
    4fa4:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	ARG_UNUSED(dev);
	struct k_work_queue_config cfg = {
    4fa6:	4b09      	ldr	r3, [pc, #36]	; (4fcc <k_sys_work_q_init+0x28>)
    4fa8:	9302      	str	r3, [sp, #8]
		.name = "sysworkq",
		.no_yield = IS_ENABLED(CONFIG_SYSTEM_WORKQUEUE_NO_YIELD),
	};

	k_work_queue_start(&k_sys_work_q,
    4faa:	ab02      	add	r3, sp, #8
	struct k_work_queue_config cfg = {
    4fac:	2400      	movs	r4, #0
	k_work_queue_start(&k_sys_work_q,
    4fae:	9300      	str	r3, [sp, #0]
    4fb0:	4907      	ldr	r1, [pc, #28]	; (4fd0 <k_sys_work_q_init+0x2c>)
    4fb2:	4808      	ldr	r0, [pc, #32]	; (4fd4 <k_sys_work_q_init+0x30>)
	struct k_work_queue_config cfg = {
    4fb4:	f88d 400c 	strb.w	r4, [sp, #12]
	k_work_queue_start(&k_sys_work_q,
    4fb8:	f04f 33ff 	mov.w	r3, #4294967295
    4fbc:	f44f 6280 	mov.w	r2, #1024	; 0x400
    4fc0:	f7ff fa2e 	bl	4420 <k_work_queue_start>
			    sys_work_q_stack,
			    K_KERNEL_STACK_SIZEOF(sys_work_q_stack),
			    CONFIG_SYSTEM_WORKQUEUE_PRIORITY, &cfg);
	return 0;
}
    4fc4:	4620      	mov	r0, r4
    4fc6:	b004      	add	sp, #16
    4fc8:	bd10      	pop	{r4, pc}
    4fca:	bf00      	nop
    4fcc:	000079d0 	.word	0x000079d0
    4fd0:	20001b18 	.word	0x20001b18
    4fd4:	200002d0 	.word	0x200002d0

00004fd8 <iprintf>:
    4fd8:	b40f      	push	{r0, r1, r2, r3}
    4fda:	4b0a      	ldr	r3, [pc, #40]	; (5004 <iprintf+0x2c>)
    4fdc:	b513      	push	{r0, r1, r4, lr}
    4fde:	681c      	ldr	r4, [r3, #0]
    4fe0:	b124      	cbz	r4, 4fec <iprintf+0x14>
    4fe2:	69a3      	ldr	r3, [r4, #24]
    4fe4:	b913      	cbnz	r3, 4fec <iprintf+0x14>
    4fe6:	4620      	mov	r0, r4
    4fe8:	f000 f850 	bl	508c <__sinit>
    4fec:	ab05      	add	r3, sp, #20
    4fee:	9a04      	ldr	r2, [sp, #16]
    4ff0:	68a1      	ldr	r1, [r4, #8]
    4ff2:	9301      	str	r3, [sp, #4]
    4ff4:	4620      	mov	r0, r4
    4ff6:	f000 f921 	bl	523c <_vfiprintf_r>
    4ffa:	b002      	add	sp, #8
    4ffc:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    5000:	b004      	add	sp, #16
    5002:	4770      	bx	lr
    5004:	2000004c 	.word	0x2000004c

00005008 <std>:
    5008:	2300      	movs	r3, #0
    500a:	b510      	push	{r4, lr}
    500c:	4604      	mov	r4, r0
    500e:	e9c0 3300 	strd	r3, r3, [r0]
    5012:	e9c0 3304 	strd	r3, r3, [r0, #16]
    5016:	6083      	str	r3, [r0, #8]
    5018:	8181      	strh	r1, [r0, #12]
    501a:	6643      	str	r3, [r0, #100]	; 0x64
    501c:	81c2      	strh	r2, [r0, #14]
    501e:	6183      	str	r3, [r0, #24]
    5020:	4619      	mov	r1, r3
    5022:	2208      	movs	r2, #8
    5024:	305c      	adds	r0, #92	; 0x5c
    5026:	f001 fd79 	bl	6b1c <memset>
    502a:	4b05      	ldr	r3, [pc, #20]	; (5040 <std+0x38>)
    502c:	6263      	str	r3, [r4, #36]	; 0x24
    502e:	4b05      	ldr	r3, [pc, #20]	; (5044 <std+0x3c>)
    5030:	62a3      	str	r3, [r4, #40]	; 0x28
    5032:	4b05      	ldr	r3, [pc, #20]	; (5048 <std+0x40>)
    5034:	62e3      	str	r3, [r4, #44]	; 0x2c
    5036:	4b05      	ldr	r3, [pc, #20]	; (504c <std+0x44>)
    5038:	6224      	str	r4, [r4, #32]
    503a:	6323      	str	r3, [r4, #48]	; 0x30
    503c:	bd10      	pop	{r4, pc}
    503e:	bf00      	nop
    5040:	00006d15 	.word	0x00006d15
    5044:	00006d37 	.word	0x00006d37
    5048:	00006d6f 	.word	0x00006d6f
    504c:	00006d93 	.word	0x00006d93

00005050 <_cleanup_r>:
    5050:	4901      	ldr	r1, [pc, #4]	; (5058 <_cleanup_r+0x8>)
    5052:	f001 bda9 	b.w	6ba8 <_fwalk_reent>
    5056:	bf00      	nop
    5058:	000059d9 	.word	0x000059d9

0000505c <__sfp_lock_acquire>:
    505c:	4801      	ldr	r0, [pc, #4]	; (5064 <__sfp_lock_acquire+0x8>)
    505e:	f001 bdc3 	b.w	6be8 <__retarget_lock_acquire_recursive>
    5062:	bf00      	nop
    5064:	20000ad4 	.word	0x20000ad4

00005068 <__sfp_lock_release>:
    5068:	4801      	ldr	r0, [pc, #4]	; (5070 <__sfp_lock_release+0x8>)
    506a:	f001 bdbe 	b.w	6bea <__retarget_lock_release_recursive>
    506e:	bf00      	nop
    5070:	20000ad4 	.word	0x20000ad4

00005074 <__sinit_lock_acquire>:
    5074:	4801      	ldr	r0, [pc, #4]	; (507c <__sinit_lock_acquire+0x8>)
    5076:	f001 bdb7 	b.w	6be8 <__retarget_lock_acquire_recursive>
    507a:	bf00      	nop
    507c:	20000acf 	.word	0x20000acf

00005080 <__sinit_lock_release>:
    5080:	4801      	ldr	r0, [pc, #4]	; (5088 <__sinit_lock_release+0x8>)
    5082:	f001 bdb2 	b.w	6bea <__retarget_lock_release_recursive>
    5086:	bf00      	nop
    5088:	20000acf 	.word	0x20000acf

0000508c <__sinit>:
    508c:	b510      	push	{r4, lr}
    508e:	4604      	mov	r4, r0
    5090:	f7ff fff0 	bl	5074 <__sinit_lock_acquire>
    5094:	69a3      	ldr	r3, [r4, #24]
    5096:	b11b      	cbz	r3, 50a0 <__sinit+0x14>
    5098:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    509c:	f7ff bff0 	b.w	5080 <__sinit_lock_release>
    50a0:	e9c4 3312 	strd	r3, r3, [r4, #72]	; 0x48
    50a4:	6523      	str	r3, [r4, #80]	; 0x50
    50a6:	4b13      	ldr	r3, [pc, #76]	; (50f4 <__sinit+0x68>)
    50a8:	4a13      	ldr	r2, [pc, #76]	; (50f8 <__sinit+0x6c>)
    50aa:	681b      	ldr	r3, [r3, #0]
    50ac:	62a2      	str	r2, [r4, #40]	; 0x28
    50ae:	42a3      	cmp	r3, r4
    50b0:	bf04      	itt	eq
    50b2:	2301      	moveq	r3, #1
    50b4:	61a3      	streq	r3, [r4, #24]
    50b6:	4620      	mov	r0, r4
    50b8:	f000 f820 	bl	50fc <__sfp>
    50bc:	6060      	str	r0, [r4, #4]
    50be:	4620      	mov	r0, r4
    50c0:	f000 f81c 	bl	50fc <__sfp>
    50c4:	60a0      	str	r0, [r4, #8]
    50c6:	4620      	mov	r0, r4
    50c8:	f000 f818 	bl	50fc <__sfp>
    50cc:	2200      	movs	r2, #0
    50ce:	60e0      	str	r0, [r4, #12]
    50d0:	2104      	movs	r1, #4
    50d2:	6860      	ldr	r0, [r4, #4]
    50d4:	f7ff ff98 	bl	5008 <std>
    50d8:	68a0      	ldr	r0, [r4, #8]
    50da:	2201      	movs	r2, #1
    50dc:	2109      	movs	r1, #9
    50de:	f7ff ff93 	bl	5008 <std>
    50e2:	68e0      	ldr	r0, [r4, #12]
    50e4:	2202      	movs	r2, #2
    50e6:	2112      	movs	r1, #18
    50e8:	f7ff ff8e 	bl	5008 <std>
    50ec:	2301      	movs	r3, #1
    50ee:	61a3      	str	r3, [r4, #24]
    50f0:	e7d2      	b.n	5098 <__sinit+0xc>
    50f2:	bf00      	nop
    50f4:	000072ec 	.word	0x000072ec
    50f8:	00005051 	.word	0x00005051

000050fc <__sfp>:
    50fc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    50fe:	4607      	mov	r7, r0
    5100:	f7ff ffac 	bl	505c <__sfp_lock_acquire>
    5104:	4b1e      	ldr	r3, [pc, #120]	; (5180 <__sfp+0x84>)
    5106:	681e      	ldr	r6, [r3, #0]
    5108:	69b3      	ldr	r3, [r6, #24]
    510a:	b913      	cbnz	r3, 5112 <__sfp+0x16>
    510c:	4630      	mov	r0, r6
    510e:	f7ff ffbd 	bl	508c <__sinit>
    5112:	3648      	adds	r6, #72	; 0x48
    5114:	e9d6 3401 	ldrd	r3, r4, [r6, #4]
    5118:	3b01      	subs	r3, #1
    511a:	d503      	bpl.n	5124 <__sfp+0x28>
    511c:	6833      	ldr	r3, [r6, #0]
    511e:	b30b      	cbz	r3, 5164 <__sfp+0x68>
    5120:	6836      	ldr	r6, [r6, #0]
    5122:	e7f7      	b.n	5114 <__sfp+0x18>
    5124:	f9b4 500c 	ldrsh.w	r5, [r4, #12]
    5128:	b9d5      	cbnz	r5, 5160 <__sfp+0x64>
    512a:	4b16      	ldr	r3, [pc, #88]	; (5184 <__sfp+0x88>)
    512c:	60e3      	str	r3, [r4, #12]
    512e:	f104 0058 	add.w	r0, r4, #88	; 0x58
    5132:	6665      	str	r5, [r4, #100]	; 0x64
    5134:	f001 fd57 	bl	6be6 <__retarget_lock_init_recursive>
    5138:	f7ff ff96 	bl	5068 <__sfp_lock_release>
    513c:	e9c4 5501 	strd	r5, r5, [r4, #4]
    5140:	e9c4 5504 	strd	r5, r5, [r4, #16]
    5144:	6025      	str	r5, [r4, #0]
    5146:	61a5      	str	r5, [r4, #24]
    5148:	2208      	movs	r2, #8
    514a:	4629      	mov	r1, r5
    514c:	f104 005c 	add.w	r0, r4, #92	; 0x5c
    5150:	f001 fce4 	bl	6b1c <memset>
    5154:	e9c4 550d 	strd	r5, r5, [r4, #52]	; 0x34
    5158:	e9c4 5512 	strd	r5, r5, [r4, #72]	; 0x48
    515c:	4620      	mov	r0, r4
    515e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    5160:	3468      	adds	r4, #104	; 0x68
    5162:	e7d9      	b.n	5118 <__sfp+0x1c>
    5164:	2104      	movs	r1, #4
    5166:	4638      	mov	r0, r7
    5168:	f001 fd08 	bl	6b7c <__sfmoreglue>
    516c:	4604      	mov	r4, r0
    516e:	6030      	str	r0, [r6, #0]
    5170:	2800      	cmp	r0, #0
    5172:	d1d5      	bne.n	5120 <__sfp+0x24>
    5174:	f7ff ff78 	bl	5068 <__sfp_lock_release>
    5178:	230c      	movs	r3, #12
    517a:	603b      	str	r3, [r7, #0]
    517c:	e7ee      	b.n	515c <__sfp+0x60>
    517e:	bf00      	nop
    5180:	000072ec 	.word	0x000072ec
    5184:	ffff0001 	.word	0xffff0001

00005188 <_malloc_r>:
    5188:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    518a:	1ccd      	adds	r5, r1, #3
    518c:	f025 0503 	bic.w	r5, r5, #3
    5190:	3508      	adds	r5, #8
    5192:	2d0c      	cmp	r5, #12
    5194:	bf38      	it	cc
    5196:	250c      	movcc	r5, #12
    5198:	2d00      	cmp	r5, #0
    519a:	4606      	mov	r6, r0
    519c:	db01      	blt.n	51a2 <_malloc_r+0x1a>
    519e:	42a9      	cmp	r1, r5
    51a0:	d903      	bls.n	51aa <_malloc_r+0x22>
    51a2:	230c      	movs	r3, #12
    51a4:	6033      	str	r3, [r6, #0]
    51a6:	2000      	movs	r0, #0
    51a8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    51aa:	f7fd fdd3 	bl	2d54 <__malloc_lock>
    51ae:	4921      	ldr	r1, [pc, #132]	; (5234 <_malloc_r+0xac>)
    51b0:	680a      	ldr	r2, [r1, #0]
    51b2:	4614      	mov	r4, r2
    51b4:	b99c      	cbnz	r4, 51de <_malloc_r+0x56>
    51b6:	4f20      	ldr	r7, [pc, #128]	; (5238 <_malloc_r+0xb0>)
    51b8:	683b      	ldr	r3, [r7, #0]
    51ba:	b923      	cbnz	r3, 51c6 <_malloc_r+0x3e>
    51bc:	4621      	mov	r1, r4
    51be:	4630      	mov	r0, r6
    51c0:	f000 fa92 	bl	56e8 <_sbrk_r>
    51c4:	6038      	str	r0, [r7, #0]
    51c6:	4629      	mov	r1, r5
    51c8:	4630      	mov	r0, r6
    51ca:	f000 fa8d 	bl	56e8 <_sbrk_r>
    51ce:	1c43      	adds	r3, r0, #1
    51d0:	d123      	bne.n	521a <_malloc_r+0x92>
    51d2:	230c      	movs	r3, #12
    51d4:	6033      	str	r3, [r6, #0]
    51d6:	4630      	mov	r0, r6
    51d8:	f7fd fdc6 	bl	2d68 <__malloc_unlock>
    51dc:	e7e3      	b.n	51a6 <_malloc_r+0x1e>
    51de:	6823      	ldr	r3, [r4, #0]
    51e0:	1b5b      	subs	r3, r3, r5
    51e2:	d417      	bmi.n	5214 <_malloc_r+0x8c>
    51e4:	2b0b      	cmp	r3, #11
    51e6:	d903      	bls.n	51f0 <_malloc_r+0x68>
    51e8:	6023      	str	r3, [r4, #0]
    51ea:	441c      	add	r4, r3
    51ec:	6025      	str	r5, [r4, #0]
    51ee:	e004      	b.n	51fa <_malloc_r+0x72>
    51f0:	6863      	ldr	r3, [r4, #4]
    51f2:	42a2      	cmp	r2, r4
    51f4:	bf0c      	ite	eq
    51f6:	600b      	streq	r3, [r1, #0]
    51f8:	6053      	strne	r3, [r2, #4]
    51fa:	4630      	mov	r0, r6
    51fc:	f7fd fdb4 	bl	2d68 <__malloc_unlock>
    5200:	f104 000b 	add.w	r0, r4, #11
    5204:	1d23      	adds	r3, r4, #4
    5206:	f020 0007 	bic.w	r0, r0, #7
    520a:	1ac2      	subs	r2, r0, r3
    520c:	d0cc      	beq.n	51a8 <_malloc_r+0x20>
    520e:	1a1b      	subs	r3, r3, r0
    5210:	50a3      	str	r3, [r4, r2]
    5212:	e7c9      	b.n	51a8 <_malloc_r+0x20>
    5214:	4622      	mov	r2, r4
    5216:	6864      	ldr	r4, [r4, #4]
    5218:	e7cc      	b.n	51b4 <_malloc_r+0x2c>
    521a:	1cc4      	adds	r4, r0, #3
    521c:	f024 0403 	bic.w	r4, r4, #3
    5220:	42a0      	cmp	r0, r4
    5222:	d0e3      	beq.n	51ec <_malloc_r+0x64>
    5224:	1a21      	subs	r1, r4, r0
    5226:	4630      	mov	r0, r6
    5228:	f000 fa5e 	bl	56e8 <_sbrk_r>
    522c:	3001      	adds	r0, #1
    522e:	d1dd      	bne.n	51ec <_malloc_r+0x64>
    5230:	e7cf      	b.n	51d2 <_malloc_r+0x4a>
    5232:	bf00      	nop
    5234:	20000690 	.word	0x20000690
    5238:	20000694 	.word	0x20000694

0000523c <_vfiprintf_r>:
    523c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    5240:	460d      	mov	r5, r1
    5242:	b09d      	sub	sp, #116	; 0x74
    5244:	4614      	mov	r4, r2
    5246:	4698      	mov	r8, r3
    5248:	4606      	mov	r6, r0
    524a:	b118      	cbz	r0, 5254 <_vfiprintf_r+0x18>
    524c:	6983      	ldr	r3, [r0, #24]
    524e:	b90b      	cbnz	r3, 5254 <_vfiprintf_r+0x18>
    5250:	f7ff ff1c 	bl	508c <__sinit>
    5254:	4b89      	ldr	r3, [pc, #548]	; (547c <_vfiprintf_r+0x240>)
    5256:	429d      	cmp	r5, r3
    5258:	d11b      	bne.n	5292 <_vfiprintf_r+0x56>
    525a:	6875      	ldr	r5, [r6, #4]
    525c:	6e6b      	ldr	r3, [r5, #100]	; 0x64
    525e:	07d9      	lsls	r1, r3, #31
    5260:	d405      	bmi.n	526e <_vfiprintf_r+0x32>
    5262:	89ab      	ldrh	r3, [r5, #12]
    5264:	059a      	lsls	r2, r3, #22
    5266:	d402      	bmi.n	526e <_vfiprintf_r+0x32>
    5268:	6da8      	ldr	r0, [r5, #88]	; 0x58
    526a:	f001 fcbd 	bl	6be8 <__retarget_lock_acquire_recursive>
    526e:	89ab      	ldrh	r3, [r5, #12]
    5270:	071b      	lsls	r3, r3, #28
    5272:	d501      	bpl.n	5278 <_vfiprintf_r+0x3c>
    5274:	692b      	ldr	r3, [r5, #16]
    5276:	b9eb      	cbnz	r3, 52b4 <_vfiprintf_r+0x78>
    5278:	4629      	mov	r1, r5
    527a:	4630      	mov	r0, r6
    527c:	f000 faa8 	bl	57d0 <__swsetup_r>
    5280:	b1c0      	cbz	r0, 52b4 <_vfiprintf_r+0x78>
    5282:	6e6b      	ldr	r3, [r5, #100]	; 0x64
    5284:	07dc      	lsls	r4, r3, #31
    5286:	d50e      	bpl.n	52a6 <_vfiprintf_r+0x6a>
    5288:	f04f 30ff 	mov.w	r0, #4294967295
    528c:	b01d      	add	sp, #116	; 0x74
    528e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    5292:	4b7b      	ldr	r3, [pc, #492]	; (5480 <_vfiprintf_r+0x244>)
    5294:	429d      	cmp	r5, r3
    5296:	d101      	bne.n	529c <_vfiprintf_r+0x60>
    5298:	68b5      	ldr	r5, [r6, #8]
    529a:	e7df      	b.n	525c <_vfiprintf_r+0x20>
    529c:	4b79      	ldr	r3, [pc, #484]	; (5484 <_vfiprintf_r+0x248>)
    529e:	429d      	cmp	r5, r3
    52a0:	bf08      	it	eq
    52a2:	68f5      	ldreq	r5, [r6, #12]
    52a4:	e7da      	b.n	525c <_vfiprintf_r+0x20>
    52a6:	89ab      	ldrh	r3, [r5, #12]
    52a8:	0598      	lsls	r0, r3, #22
    52aa:	d4ed      	bmi.n	5288 <_vfiprintf_r+0x4c>
    52ac:	6da8      	ldr	r0, [r5, #88]	; 0x58
    52ae:	f001 fc9c 	bl	6bea <__retarget_lock_release_recursive>
    52b2:	e7e9      	b.n	5288 <_vfiprintf_r+0x4c>
    52b4:	2300      	movs	r3, #0
    52b6:	9309      	str	r3, [sp, #36]	; 0x24
    52b8:	2320      	movs	r3, #32
    52ba:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
    52be:	f8cd 800c 	str.w	r8, [sp, #12]
    52c2:	2330      	movs	r3, #48	; 0x30
    52c4:	f8df 81c0 	ldr.w	r8, [pc, #448]	; 5488 <_vfiprintf_r+0x24c>
    52c8:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
    52cc:	f04f 0901 	mov.w	r9, #1
    52d0:	4623      	mov	r3, r4
    52d2:	469a      	mov	sl, r3
    52d4:	f813 2b01 	ldrb.w	r2, [r3], #1
    52d8:	b10a      	cbz	r2, 52de <_vfiprintf_r+0xa2>
    52da:	2a25      	cmp	r2, #37	; 0x25
    52dc:	d1f9      	bne.n	52d2 <_vfiprintf_r+0x96>
    52de:	ebba 0b04 	subs.w	fp, sl, r4
    52e2:	d00b      	beq.n	52fc <_vfiprintf_r+0xc0>
    52e4:	465b      	mov	r3, fp
    52e6:	4622      	mov	r2, r4
    52e8:	4629      	mov	r1, r5
    52ea:	4630      	mov	r0, r6
    52ec:	f001 fc93 	bl	6c16 <__sfputs_r>
    52f0:	3001      	adds	r0, #1
    52f2:	f000 80aa 	beq.w	544a <_vfiprintf_r+0x20e>
    52f6:	9a09      	ldr	r2, [sp, #36]	; 0x24
    52f8:	445a      	add	r2, fp
    52fa:	9209      	str	r2, [sp, #36]	; 0x24
    52fc:	f89a 3000 	ldrb.w	r3, [sl]
    5300:	2b00      	cmp	r3, #0
    5302:	f000 80a2 	beq.w	544a <_vfiprintf_r+0x20e>
    5306:	2300      	movs	r3, #0
    5308:	f04f 32ff 	mov.w	r2, #4294967295
    530c:	e9cd 2305 	strd	r2, r3, [sp, #20]
    5310:	f10a 0a01 	add.w	sl, sl, #1
    5314:	9304      	str	r3, [sp, #16]
    5316:	9307      	str	r3, [sp, #28]
    5318:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
    531c:	931a      	str	r3, [sp, #104]	; 0x68
    531e:	4654      	mov	r4, sl
    5320:	2205      	movs	r2, #5
    5322:	f814 1b01 	ldrb.w	r1, [r4], #1
    5326:	4858      	ldr	r0, [pc, #352]	; (5488 <_vfiprintf_r+0x24c>)
    5328:	f7fa feea 	bl	100 <memchr>
    532c:	9a04      	ldr	r2, [sp, #16]
    532e:	b9d8      	cbnz	r0, 5368 <_vfiprintf_r+0x12c>
    5330:	06d1      	lsls	r1, r2, #27
    5332:	bf44      	itt	mi
    5334:	2320      	movmi	r3, #32
    5336:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
    533a:	0713      	lsls	r3, r2, #28
    533c:	bf44      	itt	mi
    533e:	232b      	movmi	r3, #43	; 0x2b
    5340:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
    5344:	f89a 3000 	ldrb.w	r3, [sl]
    5348:	2b2a      	cmp	r3, #42	; 0x2a
    534a:	d015      	beq.n	5378 <_vfiprintf_r+0x13c>
    534c:	9a07      	ldr	r2, [sp, #28]
    534e:	4654      	mov	r4, sl
    5350:	2000      	movs	r0, #0
    5352:	f04f 0c0a 	mov.w	ip, #10
    5356:	4621      	mov	r1, r4
    5358:	f811 3b01 	ldrb.w	r3, [r1], #1
    535c:	3b30      	subs	r3, #48	; 0x30
    535e:	2b09      	cmp	r3, #9
    5360:	d94e      	bls.n	5400 <_vfiprintf_r+0x1c4>
    5362:	b1b0      	cbz	r0, 5392 <_vfiprintf_r+0x156>
    5364:	9207      	str	r2, [sp, #28]
    5366:	e014      	b.n	5392 <_vfiprintf_r+0x156>
    5368:	eba0 0308 	sub.w	r3, r0, r8
    536c:	fa09 f303 	lsl.w	r3, r9, r3
    5370:	4313      	orrs	r3, r2
    5372:	9304      	str	r3, [sp, #16]
    5374:	46a2      	mov	sl, r4
    5376:	e7d2      	b.n	531e <_vfiprintf_r+0xe2>
    5378:	9b03      	ldr	r3, [sp, #12]
    537a:	1d19      	adds	r1, r3, #4
    537c:	681b      	ldr	r3, [r3, #0]
    537e:	9103      	str	r1, [sp, #12]
    5380:	2b00      	cmp	r3, #0
    5382:	bfbb      	ittet	lt
    5384:	425b      	neglt	r3, r3
    5386:	f042 0202 	orrlt.w	r2, r2, #2
    538a:	9307      	strge	r3, [sp, #28]
    538c:	9307      	strlt	r3, [sp, #28]
    538e:	bfb8      	it	lt
    5390:	9204      	strlt	r2, [sp, #16]
    5392:	7823      	ldrb	r3, [r4, #0]
    5394:	2b2e      	cmp	r3, #46	; 0x2e
    5396:	d10c      	bne.n	53b2 <_vfiprintf_r+0x176>
    5398:	7863      	ldrb	r3, [r4, #1]
    539a:	2b2a      	cmp	r3, #42	; 0x2a
    539c:	d135      	bne.n	540a <_vfiprintf_r+0x1ce>
    539e:	9b03      	ldr	r3, [sp, #12]
    53a0:	1d1a      	adds	r2, r3, #4
    53a2:	681b      	ldr	r3, [r3, #0]
    53a4:	9203      	str	r2, [sp, #12]
    53a6:	2b00      	cmp	r3, #0
    53a8:	bfb8      	it	lt
    53aa:	f04f 33ff 	movlt.w	r3, #4294967295
    53ae:	3402      	adds	r4, #2
    53b0:	9305      	str	r3, [sp, #20]
    53b2:	f8df a0e4 	ldr.w	sl, [pc, #228]	; 5498 <_vfiprintf_r+0x25c>
    53b6:	7821      	ldrb	r1, [r4, #0]
    53b8:	2203      	movs	r2, #3
    53ba:	4650      	mov	r0, sl
    53bc:	f7fa fea0 	bl	100 <memchr>
    53c0:	b140      	cbz	r0, 53d4 <_vfiprintf_r+0x198>
    53c2:	2340      	movs	r3, #64	; 0x40
    53c4:	eba0 000a 	sub.w	r0, r0, sl
    53c8:	fa03 f000 	lsl.w	r0, r3, r0
    53cc:	9b04      	ldr	r3, [sp, #16]
    53ce:	4303      	orrs	r3, r0
    53d0:	3401      	adds	r4, #1
    53d2:	9304      	str	r3, [sp, #16]
    53d4:	f814 1b01 	ldrb.w	r1, [r4], #1
    53d8:	482c      	ldr	r0, [pc, #176]	; (548c <_vfiprintf_r+0x250>)
    53da:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
    53de:	2206      	movs	r2, #6
    53e0:	f7fa fe8e 	bl	100 <memchr>
    53e4:	2800      	cmp	r0, #0
    53e6:	d03f      	beq.n	5468 <_vfiprintf_r+0x22c>
    53e8:	4b29      	ldr	r3, [pc, #164]	; (5490 <_vfiprintf_r+0x254>)
    53ea:	bb1b      	cbnz	r3, 5434 <_vfiprintf_r+0x1f8>
    53ec:	9b03      	ldr	r3, [sp, #12]
    53ee:	3307      	adds	r3, #7
    53f0:	f023 0307 	bic.w	r3, r3, #7
    53f4:	3308      	adds	r3, #8
    53f6:	9303      	str	r3, [sp, #12]
    53f8:	9b09      	ldr	r3, [sp, #36]	; 0x24
    53fa:	443b      	add	r3, r7
    53fc:	9309      	str	r3, [sp, #36]	; 0x24
    53fe:	e767      	b.n	52d0 <_vfiprintf_r+0x94>
    5400:	fb0c 3202 	mla	r2, ip, r2, r3
    5404:	460c      	mov	r4, r1
    5406:	2001      	movs	r0, #1
    5408:	e7a5      	b.n	5356 <_vfiprintf_r+0x11a>
    540a:	2300      	movs	r3, #0
    540c:	3401      	adds	r4, #1
    540e:	9305      	str	r3, [sp, #20]
    5410:	4619      	mov	r1, r3
    5412:	f04f 0c0a 	mov.w	ip, #10
    5416:	4620      	mov	r0, r4
    5418:	f810 2b01 	ldrb.w	r2, [r0], #1
    541c:	3a30      	subs	r2, #48	; 0x30
    541e:	2a09      	cmp	r2, #9
    5420:	d903      	bls.n	542a <_vfiprintf_r+0x1ee>
    5422:	2b00      	cmp	r3, #0
    5424:	d0c5      	beq.n	53b2 <_vfiprintf_r+0x176>
    5426:	9105      	str	r1, [sp, #20]
    5428:	e7c3      	b.n	53b2 <_vfiprintf_r+0x176>
    542a:	fb0c 2101 	mla	r1, ip, r1, r2
    542e:	4604      	mov	r4, r0
    5430:	2301      	movs	r3, #1
    5432:	e7f0      	b.n	5416 <_vfiprintf_r+0x1da>
    5434:	ab03      	add	r3, sp, #12
    5436:	9300      	str	r3, [sp, #0]
    5438:	462a      	mov	r2, r5
    543a:	4b16      	ldr	r3, [pc, #88]	; (5494 <_vfiprintf_r+0x258>)
    543c:	a904      	add	r1, sp, #16
    543e:	4630      	mov	r0, r6
    5440:	f3af 8000 	nop.w
    5444:	4607      	mov	r7, r0
    5446:	1c78      	adds	r0, r7, #1
    5448:	d1d6      	bne.n	53f8 <_vfiprintf_r+0x1bc>
    544a:	6e6b      	ldr	r3, [r5, #100]	; 0x64
    544c:	07d9      	lsls	r1, r3, #31
    544e:	d405      	bmi.n	545c <_vfiprintf_r+0x220>
    5450:	89ab      	ldrh	r3, [r5, #12]
    5452:	059a      	lsls	r2, r3, #22
    5454:	d402      	bmi.n	545c <_vfiprintf_r+0x220>
    5456:	6da8      	ldr	r0, [r5, #88]	; 0x58
    5458:	f001 fbc7 	bl	6bea <__retarget_lock_release_recursive>
    545c:	89ab      	ldrh	r3, [r5, #12]
    545e:	065b      	lsls	r3, r3, #25
    5460:	f53f af12 	bmi.w	5288 <_vfiprintf_r+0x4c>
    5464:	9809      	ldr	r0, [sp, #36]	; 0x24
    5466:	e711      	b.n	528c <_vfiprintf_r+0x50>
    5468:	ab03      	add	r3, sp, #12
    546a:	9300      	str	r3, [sp, #0]
    546c:	462a      	mov	r2, r5
    546e:	4b09      	ldr	r3, [pc, #36]	; (5494 <_vfiprintf_r+0x258>)
    5470:	a904      	add	r1, sp, #16
    5472:	4630      	mov	r0, r6
    5474:	f000 f812 	bl	549c <_printf_i>
    5478:	e7e4      	b.n	5444 <_vfiprintf_r+0x208>
    547a:	bf00      	nop
    547c:	000072ac 	.word	0x000072ac
    5480:	000072cc 	.word	0x000072cc
    5484:	0000728c 	.word	0x0000728c
    5488:	00007ada 	.word	0x00007ada
    548c:	00007ae4 	.word	0x00007ae4
    5490:	00000000 	.word	0x00000000
    5494:	00006c17 	.word	0x00006c17
    5498:	00007ae0 	.word	0x00007ae0

0000549c <_printf_i>:
    549c:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
    54a0:	460c      	mov	r4, r1
    54a2:	4691      	mov	r9, r2
    54a4:	7e27      	ldrb	r7, [r4, #24]
    54a6:	990c      	ldr	r1, [sp, #48]	; 0x30
    54a8:	2f78      	cmp	r7, #120	; 0x78
    54aa:	4680      	mov	r8, r0
    54ac:	469a      	mov	sl, r3
    54ae:	f104 0243 	add.w	r2, r4, #67	; 0x43
    54b2:	d807      	bhi.n	54c4 <_printf_i+0x28>
    54b4:	2f62      	cmp	r7, #98	; 0x62
    54b6:	d80a      	bhi.n	54ce <_printf_i+0x32>
    54b8:	2f00      	cmp	r7, #0
    54ba:	f000 80d8 	beq.w	566e <_printf_i+0x1d2>
    54be:	2f58      	cmp	r7, #88	; 0x58
    54c0:	f000 80a3 	beq.w	560a <_printf_i+0x16e>
    54c4:	f104 0642 	add.w	r6, r4, #66	; 0x42
    54c8:	f884 7042 	strb.w	r7, [r4, #66]	; 0x42
    54cc:	e03a      	b.n	5544 <_printf_i+0xa8>
    54ce:	f1a7 0363 	sub.w	r3, r7, #99	; 0x63
    54d2:	2b15      	cmp	r3, #21
    54d4:	d8f6      	bhi.n	54c4 <_printf_i+0x28>
    54d6:	a001      	add	r0, pc, #4	; (adr r0, 54dc <_printf_i+0x40>)
    54d8:	f850 f023 	ldr.w	pc, [r0, r3, lsl #2]
    54dc:	00005535 	.word	0x00005535
    54e0:	00005549 	.word	0x00005549
    54e4:	000054c5 	.word	0x000054c5
    54e8:	000054c5 	.word	0x000054c5
    54ec:	000054c5 	.word	0x000054c5
    54f0:	000054c5 	.word	0x000054c5
    54f4:	00005549 	.word	0x00005549
    54f8:	000054c5 	.word	0x000054c5
    54fc:	000054c5 	.word	0x000054c5
    5500:	000054c5 	.word	0x000054c5
    5504:	000054c5 	.word	0x000054c5
    5508:	00005655 	.word	0x00005655
    550c:	00005579 	.word	0x00005579
    5510:	00005637 	.word	0x00005637
    5514:	000054c5 	.word	0x000054c5
    5518:	000054c5 	.word	0x000054c5
    551c:	00005677 	.word	0x00005677
    5520:	000054c5 	.word	0x000054c5
    5524:	00005579 	.word	0x00005579
    5528:	000054c5 	.word	0x000054c5
    552c:	000054c5 	.word	0x000054c5
    5530:	0000563f 	.word	0x0000563f
    5534:	680b      	ldr	r3, [r1, #0]
    5536:	1d1a      	adds	r2, r3, #4
    5538:	681b      	ldr	r3, [r3, #0]
    553a:	600a      	str	r2, [r1, #0]
    553c:	f104 0642 	add.w	r6, r4, #66	; 0x42
    5540:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
    5544:	2301      	movs	r3, #1
    5546:	e0a3      	b.n	5690 <_printf_i+0x1f4>
    5548:	6825      	ldr	r5, [r4, #0]
    554a:	6808      	ldr	r0, [r1, #0]
    554c:	062e      	lsls	r6, r5, #24
    554e:	f100 0304 	add.w	r3, r0, #4
    5552:	d50a      	bpl.n	556a <_printf_i+0xce>
    5554:	6805      	ldr	r5, [r0, #0]
    5556:	600b      	str	r3, [r1, #0]
    5558:	2d00      	cmp	r5, #0
    555a:	da03      	bge.n	5564 <_printf_i+0xc8>
    555c:	232d      	movs	r3, #45	; 0x2d
    555e:	426d      	negs	r5, r5
    5560:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
    5564:	485e      	ldr	r0, [pc, #376]	; (56e0 <_printf_i+0x244>)
    5566:	230a      	movs	r3, #10
    5568:	e019      	b.n	559e <_printf_i+0x102>
    556a:	f015 0f40 	tst.w	r5, #64	; 0x40
    556e:	6805      	ldr	r5, [r0, #0]
    5570:	600b      	str	r3, [r1, #0]
    5572:	bf18      	it	ne
    5574:	b22d      	sxthne	r5, r5
    5576:	e7ef      	b.n	5558 <_printf_i+0xbc>
    5578:	680b      	ldr	r3, [r1, #0]
    557a:	6825      	ldr	r5, [r4, #0]
    557c:	1d18      	adds	r0, r3, #4
    557e:	6008      	str	r0, [r1, #0]
    5580:	0628      	lsls	r0, r5, #24
    5582:	d501      	bpl.n	5588 <_printf_i+0xec>
    5584:	681d      	ldr	r5, [r3, #0]
    5586:	e002      	b.n	558e <_printf_i+0xf2>
    5588:	0669      	lsls	r1, r5, #25
    558a:	d5fb      	bpl.n	5584 <_printf_i+0xe8>
    558c:	881d      	ldrh	r5, [r3, #0]
    558e:	4854      	ldr	r0, [pc, #336]	; (56e0 <_printf_i+0x244>)
    5590:	2f6f      	cmp	r7, #111	; 0x6f
    5592:	bf0c      	ite	eq
    5594:	2308      	moveq	r3, #8
    5596:	230a      	movne	r3, #10
    5598:	2100      	movs	r1, #0
    559a:	f884 1043 	strb.w	r1, [r4, #67]	; 0x43
    559e:	6866      	ldr	r6, [r4, #4]
    55a0:	60a6      	str	r6, [r4, #8]
    55a2:	2e00      	cmp	r6, #0
    55a4:	bfa2      	ittt	ge
    55a6:	6821      	ldrge	r1, [r4, #0]
    55a8:	f021 0104 	bicge.w	r1, r1, #4
    55ac:	6021      	strge	r1, [r4, #0]
    55ae:	b90d      	cbnz	r5, 55b4 <_printf_i+0x118>
    55b0:	2e00      	cmp	r6, #0
    55b2:	d04d      	beq.n	5650 <_printf_i+0x1b4>
    55b4:	4616      	mov	r6, r2
    55b6:	fbb5 f1f3 	udiv	r1, r5, r3
    55ba:	fb03 5711 	mls	r7, r3, r1, r5
    55be:	5dc7      	ldrb	r7, [r0, r7]
    55c0:	f806 7d01 	strb.w	r7, [r6, #-1]!
    55c4:	462f      	mov	r7, r5
    55c6:	42bb      	cmp	r3, r7
    55c8:	460d      	mov	r5, r1
    55ca:	d9f4      	bls.n	55b6 <_printf_i+0x11a>
    55cc:	2b08      	cmp	r3, #8
    55ce:	d10b      	bne.n	55e8 <_printf_i+0x14c>
    55d0:	6823      	ldr	r3, [r4, #0]
    55d2:	07df      	lsls	r7, r3, #31
    55d4:	d508      	bpl.n	55e8 <_printf_i+0x14c>
    55d6:	6923      	ldr	r3, [r4, #16]
    55d8:	6861      	ldr	r1, [r4, #4]
    55da:	4299      	cmp	r1, r3
    55dc:	bfde      	ittt	le
    55de:	2330      	movle	r3, #48	; 0x30
    55e0:	f806 3c01 	strble.w	r3, [r6, #-1]
    55e4:	f106 36ff 	addle.w	r6, r6, #4294967295
    55e8:	1b92      	subs	r2, r2, r6
    55ea:	6122      	str	r2, [r4, #16]
    55ec:	f8cd a000 	str.w	sl, [sp]
    55f0:	464b      	mov	r3, r9
    55f2:	aa03      	add	r2, sp, #12
    55f4:	4621      	mov	r1, r4
    55f6:	4640      	mov	r0, r8
    55f8:	f001 fb1f 	bl	6c3a <_printf_common>
    55fc:	3001      	adds	r0, #1
    55fe:	d14c      	bne.n	569a <_printf_i+0x1fe>
    5600:	f04f 30ff 	mov.w	r0, #4294967295
    5604:	b004      	add	sp, #16
    5606:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    560a:	4835      	ldr	r0, [pc, #212]	; (56e0 <_printf_i+0x244>)
    560c:	f884 7045 	strb.w	r7, [r4, #69]	; 0x45
    5610:	6823      	ldr	r3, [r4, #0]
    5612:	680e      	ldr	r6, [r1, #0]
    5614:	061f      	lsls	r7, r3, #24
    5616:	f856 5b04 	ldr.w	r5, [r6], #4
    561a:	600e      	str	r6, [r1, #0]
    561c:	d514      	bpl.n	5648 <_printf_i+0x1ac>
    561e:	07d9      	lsls	r1, r3, #31
    5620:	bf44      	itt	mi
    5622:	f043 0320 	orrmi.w	r3, r3, #32
    5626:	6023      	strmi	r3, [r4, #0]
    5628:	b91d      	cbnz	r5, 5632 <_printf_i+0x196>
    562a:	6823      	ldr	r3, [r4, #0]
    562c:	f023 0320 	bic.w	r3, r3, #32
    5630:	6023      	str	r3, [r4, #0]
    5632:	2310      	movs	r3, #16
    5634:	e7b0      	b.n	5598 <_printf_i+0xfc>
    5636:	6823      	ldr	r3, [r4, #0]
    5638:	f043 0320 	orr.w	r3, r3, #32
    563c:	6023      	str	r3, [r4, #0]
    563e:	2378      	movs	r3, #120	; 0x78
    5640:	4828      	ldr	r0, [pc, #160]	; (56e4 <_printf_i+0x248>)
    5642:	f884 3045 	strb.w	r3, [r4, #69]	; 0x45
    5646:	e7e3      	b.n	5610 <_printf_i+0x174>
    5648:	065e      	lsls	r6, r3, #25
    564a:	bf48      	it	mi
    564c:	b2ad      	uxthmi	r5, r5
    564e:	e7e6      	b.n	561e <_printf_i+0x182>
    5650:	4616      	mov	r6, r2
    5652:	e7bb      	b.n	55cc <_printf_i+0x130>
    5654:	680b      	ldr	r3, [r1, #0]
    5656:	6826      	ldr	r6, [r4, #0]
    5658:	6960      	ldr	r0, [r4, #20]
    565a:	1d1d      	adds	r5, r3, #4
    565c:	600d      	str	r5, [r1, #0]
    565e:	0635      	lsls	r5, r6, #24
    5660:	681b      	ldr	r3, [r3, #0]
    5662:	d501      	bpl.n	5668 <_printf_i+0x1cc>
    5664:	6018      	str	r0, [r3, #0]
    5666:	e002      	b.n	566e <_printf_i+0x1d2>
    5668:	0671      	lsls	r1, r6, #25
    566a:	d5fb      	bpl.n	5664 <_printf_i+0x1c8>
    566c:	8018      	strh	r0, [r3, #0]
    566e:	2300      	movs	r3, #0
    5670:	6123      	str	r3, [r4, #16]
    5672:	4616      	mov	r6, r2
    5674:	e7ba      	b.n	55ec <_printf_i+0x150>
    5676:	680b      	ldr	r3, [r1, #0]
    5678:	1d1a      	adds	r2, r3, #4
    567a:	600a      	str	r2, [r1, #0]
    567c:	681e      	ldr	r6, [r3, #0]
    567e:	6862      	ldr	r2, [r4, #4]
    5680:	2100      	movs	r1, #0
    5682:	4630      	mov	r0, r6
    5684:	f7fa fd3c 	bl	100 <memchr>
    5688:	b108      	cbz	r0, 568e <_printf_i+0x1f2>
    568a:	1b80      	subs	r0, r0, r6
    568c:	6060      	str	r0, [r4, #4]
    568e:	6863      	ldr	r3, [r4, #4]
    5690:	6123      	str	r3, [r4, #16]
    5692:	2300      	movs	r3, #0
    5694:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
    5698:	e7a8      	b.n	55ec <_printf_i+0x150>
    569a:	6923      	ldr	r3, [r4, #16]
    569c:	4632      	mov	r2, r6
    569e:	4649      	mov	r1, r9
    56a0:	4640      	mov	r0, r8
    56a2:	47d0      	blx	sl
    56a4:	3001      	adds	r0, #1
    56a6:	d0ab      	beq.n	5600 <_printf_i+0x164>
    56a8:	6823      	ldr	r3, [r4, #0]
    56aa:	079b      	lsls	r3, r3, #30
    56ac:	d413      	bmi.n	56d6 <_printf_i+0x23a>
    56ae:	68e0      	ldr	r0, [r4, #12]
    56b0:	9b03      	ldr	r3, [sp, #12]
    56b2:	4298      	cmp	r0, r3
    56b4:	bfb8      	it	lt
    56b6:	4618      	movlt	r0, r3
    56b8:	e7a4      	b.n	5604 <_printf_i+0x168>
    56ba:	2301      	movs	r3, #1
    56bc:	4632      	mov	r2, r6
    56be:	4649      	mov	r1, r9
    56c0:	4640      	mov	r0, r8
    56c2:	47d0      	blx	sl
    56c4:	3001      	adds	r0, #1
    56c6:	d09b      	beq.n	5600 <_printf_i+0x164>
    56c8:	3501      	adds	r5, #1
    56ca:	68e3      	ldr	r3, [r4, #12]
    56cc:	9903      	ldr	r1, [sp, #12]
    56ce:	1a5b      	subs	r3, r3, r1
    56d0:	42ab      	cmp	r3, r5
    56d2:	dcf2      	bgt.n	56ba <_printf_i+0x21e>
    56d4:	e7eb      	b.n	56ae <_printf_i+0x212>
    56d6:	2500      	movs	r5, #0
    56d8:	f104 0619 	add.w	r6, r4, #25
    56dc:	e7f5      	b.n	56ca <_printf_i+0x22e>
    56de:	bf00      	nop
    56e0:	00007aeb 	.word	0x00007aeb
    56e4:	00007afc 	.word	0x00007afc

000056e8 <_sbrk_r>:
    56e8:	b538      	push	{r3, r4, r5, lr}
    56ea:	4d06      	ldr	r5, [pc, #24]	; (5704 <_sbrk_r+0x1c>)
    56ec:	2300      	movs	r3, #0
    56ee:	4604      	mov	r4, r0
    56f0:	4608      	mov	r0, r1
    56f2:	602b      	str	r3, [r5, #0]
    56f4:	f7fd fb1a 	bl	2d2c <_sbrk>
    56f8:	1c43      	adds	r3, r0, #1
    56fa:	d102      	bne.n	5702 <_sbrk_r+0x1a>
    56fc:	682b      	ldr	r3, [r5, #0]
    56fe:	b103      	cbz	r3, 5702 <_sbrk_r+0x1a>
    5700:	6023      	str	r3, [r4, #0]
    5702:	bd38      	pop	{r3, r4, r5, pc}
    5704:	20000ac8 	.word	0x20000ac8

00005708 <__swbuf_r>:
    5708:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    570a:	460e      	mov	r6, r1
    570c:	4614      	mov	r4, r2
    570e:	4605      	mov	r5, r0
    5710:	b118      	cbz	r0, 571a <__swbuf_r+0x12>
    5712:	6983      	ldr	r3, [r0, #24]
    5714:	b90b      	cbnz	r3, 571a <__swbuf_r+0x12>
    5716:	f7ff fcb9 	bl	508c <__sinit>
    571a:	4b21      	ldr	r3, [pc, #132]	; (57a0 <__swbuf_r+0x98>)
    571c:	429c      	cmp	r4, r3
    571e:	d12b      	bne.n	5778 <__swbuf_r+0x70>
    5720:	686c      	ldr	r4, [r5, #4]
    5722:	69a3      	ldr	r3, [r4, #24]
    5724:	60a3      	str	r3, [r4, #8]
    5726:	89a3      	ldrh	r3, [r4, #12]
    5728:	071a      	lsls	r2, r3, #28
    572a:	d52f      	bpl.n	578c <__swbuf_r+0x84>
    572c:	6923      	ldr	r3, [r4, #16]
    572e:	b36b      	cbz	r3, 578c <__swbuf_r+0x84>
    5730:	6923      	ldr	r3, [r4, #16]
    5732:	6820      	ldr	r0, [r4, #0]
    5734:	1ac0      	subs	r0, r0, r3
    5736:	6963      	ldr	r3, [r4, #20]
    5738:	b2f6      	uxtb	r6, r6
    573a:	4283      	cmp	r3, r0
    573c:	4637      	mov	r7, r6
    573e:	dc04      	bgt.n	574a <__swbuf_r+0x42>
    5740:	4621      	mov	r1, r4
    5742:	4628      	mov	r0, r5
    5744:	f000 f948 	bl	59d8 <_fflush_r>
    5748:	bb30      	cbnz	r0, 5798 <__swbuf_r+0x90>
    574a:	68a3      	ldr	r3, [r4, #8]
    574c:	3b01      	subs	r3, #1
    574e:	60a3      	str	r3, [r4, #8]
    5750:	6823      	ldr	r3, [r4, #0]
    5752:	1c5a      	adds	r2, r3, #1
    5754:	6022      	str	r2, [r4, #0]
    5756:	701e      	strb	r6, [r3, #0]
    5758:	6963      	ldr	r3, [r4, #20]
    575a:	3001      	adds	r0, #1
    575c:	4283      	cmp	r3, r0
    575e:	d004      	beq.n	576a <__swbuf_r+0x62>
    5760:	89a3      	ldrh	r3, [r4, #12]
    5762:	07db      	lsls	r3, r3, #31
    5764:	d506      	bpl.n	5774 <__swbuf_r+0x6c>
    5766:	2e0a      	cmp	r6, #10
    5768:	d104      	bne.n	5774 <__swbuf_r+0x6c>
    576a:	4621      	mov	r1, r4
    576c:	4628      	mov	r0, r5
    576e:	f000 f933 	bl	59d8 <_fflush_r>
    5772:	b988      	cbnz	r0, 5798 <__swbuf_r+0x90>
    5774:	4638      	mov	r0, r7
    5776:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    5778:	4b0a      	ldr	r3, [pc, #40]	; (57a4 <__swbuf_r+0x9c>)
    577a:	429c      	cmp	r4, r3
    577c:	d101      	bne.n	5782 <__swbuf_r+0x7a>
    577e:	68ac      	ldr	r4, [r5, #8]
    5780:	e7cf      	b.n	5722 <__swbuf_r+0x1a>
    5782:	4b09      	ldr	r3, [pc, #36]	; (57a8 <__swbuf_r+0xa0>)
    5784:	429c      	cmp	r4, r3
    5786:	bf08      	it	eq
    5788:	68ec      	ldreq	r4, [r5, #12]
    578a:	e7ca      	b.n	5722 <__swbuf_r+0x1a>
    578c:	4621      	mov	r1, r4
    578e:	4628      	mov	r0, r5
    5790:	f000 f81e 	bl	57d0 <__swsetup_r>
    5794:	2800      	cmp	r0, #0
    5796:	d0cb      	beq.n	5730 <__swbuf_r+0x28>
    5798:	f04f 37ff 	mov.w	r7, #4294967295
    579c:	e7ea      	b.n	5774 <__swbuf_r+0x6c>
    579e:	bf00      	nop
    57a0:	000072ac 	.word	0x000072ac
    57a4:	000072cc 	.word	0x000072cc
    57a8:	0000728c 	.word	0x0000728c

000057ac <_write_r>:
    57ac:	b538      	push	{r3, r4, r5, lr}
    57ae:	4d07      	ldr	r5, [pc, #28]	; (57cc <_write_r+0x20>)
    57b0:	4604      	mov	r4, r0
    57b2:	4608      	mov	r0, r1
    57b4:	4611      	mov	r1, r2
    57b6:	2200      	movs	r2, #0
    57b8:	602a      	str	r2, [r5, #0]
    57ba:	461a      	mov	r2, r3
    57bc:	f000 febc 	bl	6538 <_write>
    57c0:	1c43      	adds	r3, r0, #1
    57c2:	d102      	bne.n	57ca <_write_r+0x1e>
    57c4:	682b      	ldr	r3, [r5, #0]
    57c6:	b103      	cbz	r3, 57ca <_write_r+0x1e>
    57c8:	6023      	str	r3, [r4, #0]
    57ca:	bd38      	pop	{r3, r4, r5, pc}
    57cc:	20000ac8 	.word	0x20000ac8

000057d0 <__swsetup_r>:
    57d0:	4b32      	ldr	r3, [pc, #200]	; (589c <__swsetup_r+0xcc>)
    57d2:	b570      	push	{r4, r5, r6, lr}
    57d4:	681d      	ldr	r5, [r3, #0]
    57d6:	4606      	mov	r6, r0
    57d8:	460c      	mov	r4, r1
    57da:	b125      	cbz	r5, 57e6 <__swsetup_r+0x16>
    57dc:	69ab      	ldr	r3, [r5, #24]
    57de:	b913      	cbnz	r3, 57e6 <__swsetup_r+0x16>
    57e0:	4628      	mov	r0, r5
    57e2:	f7ff fc53 	bl	508c <__sinit>
    57e6:	4b2e      	ldr	r3, [pc, #184]	; (58a0 <__swsetup_r+0xd0>)
    57e8:	429c      	cmp	r4, r3
    57ea:	d10f      	bne.n	580c <__swsetup_r+0x3c>
    57ec:	686c      	ldr	r4, [r5, #4]
    57ee:	89a3      	ldrh	r3, [r4, #12]
    57f0:	f9b4 200c 	ldrsh.w	r2, [r4, #12]
    57f4:	0719      	lsls	r1, r3, #28
    57f6:	d42c      	bmi.n	5852 <__swsetup_r+0x82>
    57f8:	06dd      	lsls	r5, r3, #27
    57fa:	d411      	bmi.n	5820 <__swsetup_r+0x50>
    57fc:	2309      	movs	r3, #9
    57fe:	6033      	str	r3, [r6, #0]
    5800:	f042 0340 	orr.w	r3, r2, #64	; 0x40
    5804:	81a3      	strh	r3, [r4, #12]
    5806:	f04f 30ff 	mov.w	r0, #4294967295
    580a:	e03e      	b.n	588a <__swsetup_r+0xba>
    580c:	4b25      	ldr	r3, [pc, #148]	; (58a4 <__swsetup_r+0xd4>)
    580e:	429c      	cmp	r4, r3
    5810:	d101      	bne.n	5816 <__swsetup_r+0x46>
    5812:	68ac      	ldr	r4, [r5, #8]
    5814:	e7eb      	b.n	57ee <__swsetup_r+0x1e>
    5816:	4b24      	ldr	r3, [pc, #144]	; (58a8 <__swsetup_r+0xd8>)
    5818:	429c      	cmp	r4, r3
    581a:	bf08      	it	eq
    581c:	68ec      	ldreq	r4, [r5, #12]
    581e:	e7e6      	b.n	57ee <__swsetup_r+0x1e>
    5820:	0758      	lsls	r0, r3, #29
    5822:	d512      	bpl.n	584a <__swsetup_r+0x7a>
    5824:	6b61      	ldr	r1, [r4, #52]	; 0x34
    5826:	b141      	cbz	r1, 583a <__swsetup_r+0x6a>
    5828:	f104 0344 	add.w	r3, r4, #68	; 0x44
    582c:	4299      	cmp	r1, r3
    582e:	d002      	beq.n	5836 <__swsetup_r+0x66>
    5830:	4630      	mov	r0, r6
    5832:	f000 f95f 	bl	5af4 <_free_r>
    5836:	2300      	movs	r3, #0
    5838:	6363      	str	r3, [r4, #52]	; 0x34
    583a:	89a3      	ldrh	r3, [r4, #12]
    583c:	f023 0324 	bic.w	r3, r3, #36	; 0x24
    5840:	81a3      	strh	r3, [r4, #12]
    5842:	2300      	movs	r3, #0
    5844:	6063      	str	r3, [r4, #4]
    5846:	6923      	ldr	r3, [r4, #16]
    5848:	6023      	str	r3, [r4, #0]
    584a:	89a3      	ldrh	r3, [r4, #12]
    584c:	f043 0308 	orr.w	r3, r3, #8
    5850:	81a3      	strh	r3, [r4, #12]
    5852:	6923      	ldr	r3, [r4, #16]
    5854:	b94b      	cbnz	r3, 586a <__swsetup_r+0x9a>
    5856:	89a3      	ldrh	r3, [r4, #12]
    5858:	f403 7320 	and.w	r3, r3, #640	; 0x280
    585c:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    5860:	d003      	beq.n	586a <__swsetup_r+0x9a>
    5862:	4621      	mov	r1, r4
    5864:	4630      	mov	r0, r6
    5866:	f000 f905 	bl	5a74 <__smakebuf_r>
    586a:	89a0      	ldrh	r0, [r4, #12]
    586c:	f9b4 200c 	ldrsh.w	r2, [r4, #12]
    5870:	f010 0301 	ands.w	r3, r0, #1
    5874:	d00a      	beq.n	588c <__swsetup_r+0xbc>
    5876:	2300      	movs	r3, #0
    5878:	60a3      	str	r3, [r4, #8]
    587a:	6963      	ldr	r3, [r4, #20]
    587c:	425b      	negs	r3, r3
    587e:	61a3      	str	r3, [r4, #24]
    5880:	6923      	ldr	r3, [r4, #16]
    5882:	b943      	cbnz	r3, 5896 <__swsetup_r+0xc6>
    5884:	f010 0080 	ands.w	r0, r0, #128	; 0x80
    5888:	d1ba      	bne.n	5800 <__swsetup_r+0x30>
    588a:	bd70      	pop	{r4, r5, r6, pc}
    588c:	0781      	lsls	r1, r0, #30
    588e:	bf58      	it	pl
    5890:	6963      	ldrpl	r3, [r4, #20]
    5892:	60a3      	str	r3, [r4, #8]
    5894:	e7f4      	b.n	5880 <__swsetup_r+0xb0>
    5896:	2000      	movs	r0, #0
    5898:	e7f7      	b.n	588a <__swsetup_r+0xba>
    589a:	bf00      	nop
    589c:	2000004c 	.word	0x2000004c
    58a0:	000072ac 	.word	0x000072ac
    58a4:	000072cc 	.word	0x000072cc
    58a8:	0000728c 	.word	0x0000728c

000058ac <_close_r>:
    58ac:	b538      	push	{r3, r4, r5, lr}
    58ae:	4d06      	ldr	r5, [pc, #24]	; (58c8 <_close_r+0x1c>)
    58b0:	2300      	movs	r3, #0
    58b2:	4604      	mov	r4, r0
    58b4:	4608      	mov	r0, r1
    58b6:	602b      	str	r3, [r5, #0]
    58b8:	f000 fe42 	bl	6540 <_close>
    58bc:	1c43      	adds	r3, r0, #1
    58be:	d102      	bne.n	58c6 <_close_r+0x1a>
    58c0:	682b      	ldr	r3, [r5, #0]
    58c2:	b103      	cbz	r3, 58c6 <_close_r+0x1a>
    58c4:	6023      	str	r3, [r4, #0]
    58c6:	bd38      	pop	{r3, r4, r5, pc}
    58c8:	20000ac8 	.word	0x20000ac8

000058cc <__sflush_r>:
    58cc:	898a      	ldrh	r2, [r1, #12]
    58ce:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    58d2:	4605      	mov	r5, r0
    58d4:	0710      	lsls	r0, r2, #28
    58d6:	460c      	mov	r4, r1
    58d8:	d458      	bmi.n	598c <__sflush_r+0xc0>
    58da:	684b      	ldr	r3, [r1, #4]
    58dc:	2b00      	cmp	r3, #0
    58de:	dc05      	bgt.n	58ec <__sflush_r+0x20>
    58e0:	6c0b      	ldr	r3, [r1, #64]	; 0x40
    58e2:	2b00      	cmp	r3, #0
    58e4:	dc02      	bgt.n	58ec <__sflush_r+0x20>
    58e6:	2000      	movs	r0, #0
    58e8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    58ec:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
    58ee:	2e00      	cmp	r6, #0
    58f0:	d0f9      	beq.n	58e6 <__sflush_r+0x1a>
    58f2:	2300      	movs	r3, #0
    58f4:	f412 5280 	ands.w	r2, r2, #4096	; 0x1000
    58f8:	682f      	ldr	r7, [r5, #0]
    58fa:	602b      	str	r3, [r5, #0]
    58fc:	d032      	beq.n	5964 <__sflush_r+0x98>
    58fe:	6d60      	ldr	r0, [r4, #84]	; 0x54
    5900:	89a3      	ldrh	r3, [r4, #12]
    5902:	075a      	lsls	r2, r3, #29
    5904:	d505      	bpl.n	5912 <__sflush_r+0x46>
    5906:	6863      	ldr	r3, [r4, #4]
    5908:	1ac0      	subs	r0, r0, r3
    590a:	6b63      	ldr	r3, [r4, #52]	; 0x34
    590c:	b10b      	cbz	r3, 5912 <__sflush_r+0x46>
    590e:	6c23      	ldr	r3, [r4, #64]	; 0x40
    5910:	1ac0      	subs	r0, r0, r3
    5912:	2300      	movs	r3, #0
    5914:	4602      	mov	r2, r0
    5916:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
    5918:	6a21      	ldr	r1, [r4, #32]
    591a:	4628      	mov	r0, r5
    591c:	47b0      	blx	r6
    591e:	1c43      	adds	r3, r0, #1
    5920:	89a3      	ldrh	r3, [r4, #12]
    5922:	d106      	bne.n	5932 <__sflush_r+0x66>
    5924:	6829      	ldr	r1, [r5, #0]
    5926:	291d      	cmp	r1, #29
    5928:	d82c      	bhi.n	5984 <__sflush_r+0xb8>
    592a:	4a2a      	ldr	r2, [pc, #168]	; (59d4 <__sflush_r+0x108>)
    592c:	40ca      	lsrs	r2, r1
    592e:	07d6      	lsls	r6, r2, #31
    5930:	d528      	bpl.n	5984 <__sflush_r+0xb8>
    5932:	2200      	movs	r2, #0
    5934:	6062      	str	r2, [r4, #4]
    5936:	04d9      	lsls	r1, r3, #19
    5938:	6922      	ldr	r2, [r4, #16]
    593a:	6022      	str	r2, [r4, #0]
    593c:	d504      	bpl.n	5948 <__sflush_r+0x7c>
    593e:	1c42      	adds	r2, r0, #1
    5940:	d101      	bne.n	5946 <__sflush_r+0x7a>
    5942:	682b      	ldr	r3, [r5, #0]
    5944:	b903      	cbnz	r3, 5948 <__sflush_r+0x7c>
    5946:	6560      	str	r0, [r4, #84]	; 0x54
    5948:	6b61      	ldr	r1, [r4, #52]	; 0x34
    594a:	602f      	str	r7, [r5, #0]
    594c:	2900      	cmp	r1, #0
    594e:	d0ca      	beq.n	58e6 <__sflush_r+0x1a>
    5950:	f104 0344 	add.w	r3, r4, #68	; 0x44
    5954:	4299      	cmp	r1, r3
    5956:	d002      	beq.n	595e <__sflush_r+0x92>
    5958:	4628      	mov	r0, r5
    595a:	f000 f8cb 	bl	5af4 <_free_r>
    595e:	2000      	movs	r0, #0
    5960:	6360      	str	r0, [r4, #52]	; 0x34
    5962:	e7c1      	b.n	58e8 <__sflush_r+0x1c>
    5964:	6a21      	ldr	r1, [r4, #32]
    5966:	2301      	movs	r3, #1
    5968:	4628      	mov	r0, r5
    596a:	47b0      	blx	r6
    596c:	1c41      	adds	r1, r0, #1
    596e:	d1c7      	bne.n	5900 <__sflush_r+0x34>
    5970:	682b      	ldr	r3, [r5, #0]
    5972:	2b00      	cmp	r3, #0
    5974:	d0c4      	beq.n	5900 <__sflush_r+0x34>
    5976:	2b1d      	cmp	r3, #29
    5978:	d001      	beq.n	597e <__sflush_r+0xb2>
    597a:	2b16      	cmp	r3, #22
    597c:	d101      	bne.n	5982 <__sflush_r+0xb6>
    597e:	602f      	str	r7, [r5, #0]
    5980:	e7b1      	b.n	58e6 <__sflush_r+0x1a>
    5982:	89a3      	ldrh	r3, [r4, #12]
    5984:	f043 0340 	orr.w	r3, r3, #64	; 0x40
    5988:	81a3      	strh	r3, [r4, #12]
    598a:	e7ad      	b.n	58e8 <__sflush_r+0x1c>
    598c:	690f      	ldr	r7, [r1, #16]
    598e:	2f00      	cmp	r7, #0
    5990:	d0a9      	beq.n	58e6 <__sflush_r+0x1a>
    5992:	0793      	lsls	r3, r2, #30
    5994:	680e      	ldr	r6, [r1, #0]
    5996:	bf08      	it	eq
    5998:	694b      	ldreq	r3, [r1, #20]
    599a:	600f      	str	r7, [r1, #0]
    599c:	bf18      	it	ne
    599e:	2300      	movne	r3, #0
    59a0:	eba6 0807 	sub.w	r8, r6, r7
    59a4:	608b      	str	r3, [r1, #8]
    59a6:	f1b8 0f00 	cmp.w	r8, #0
    59aa:	dd9c      	ble.n	58e6 <__sflush_r+0x1a>
    59ac:	6a21      	ldr	r1, [r4, #32]
    59ae:	6aa6      	ldr	r6, [r4, #40]	; 0x28
    59b0:	4643      	mov	r3, r8
    59b2:	463a      	mov	r2, r7
    59b4:	4628      	mov	r0, r5
    59b6:	47b0      	blx	r6
    59b8:	2800      	cmp	r0, #0
    59ba:	dc06      	bgt.n	59ca <__sflush_r+0xfe>
    59bc:	89a3      	ldrh	r3, [r4, #12]
    59be:	f043 0340 	orr.w	r3, r3, #64	; 0x40
    59c2:	81a3      	strh	r3, [r4, #12]
    59c4:	f04f 30ff 	mov.w	r0, #4294967295
    59c8:	e78e      	b.n	58e8 <__sflush_r+0x1c>
    59ca:	4407      	add	r7, r0
    59cc:	eba8 0800 	sub.w	r8, r8, r0
    59d0:	e7e9      	b.n	59a6 <__sflush_r+0xda>
    59d2:	bf00      	nop
    59d4:	20400001 	.word	0x20400001

000059d8 <_fflush_r>:
    59d8:	b538      	push	{r3, r4, r5, lr}
    59da:	690b      	ldr	r3, [r1, #16]
    59dc:	4605      	mov	r5, r0
    59de:	460c      	mov	r4, r1
    59e0:	b913      	cbnz	r3, 59e8 <_fflush_r+0x10>
    59e2:	2500      	movs	r5, #0
    59e4:	4628      	mov	r0, r5
    59e6:	bd38      	pop	{r3, r4, r5, pc}
    59e8:	b118      	cbz	r0, 59f2 <_fflush_r+0x1a>
    59ea:	6983      	ldr	r3, [r0, #24]
    59ec:	b90b      	cbnz	r3, 59f2 <_fflush_r+0x1a>
    59ee:	f7ff fb4d 	bl	508c <__sinit>
    59f2:	4b14      	ldr	r3, [pc, #80]	; (5a44 <_fflush_r+0x6c>)
    59f4:	429c      	cmp	r4, r3
    59f6:	d11b      	bne.n	5a30 <_fflush_r+0x58>
    59f8:	686c      	ldr	r4, [r5, #4]
    59fa:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
    59fe:	2b00      	cmp	r3, #0
    5a00:	d0ef      	beq.n	59e2 <_fflush_r+0xa>
    5a02:	6e62      	ldr	r2, [r4, #100]	; 0x64
    5a04:	07d0      	lsls	r0, r2, #31
    5a06:	d404      	bmi.n	5a12 <_fflush_r+0x3a>
    5a08:	0599      	lsls	r1, r3, #22
    5a0a:	d402      	bmi.n	5a12 <_fflush_r+0x3a>
    5a0c:	6da0      	ldr	r0, [r4, #88]	; 0x58
    5a0e:	f001 f8eb 	bl	6be8 <__retarget_lock_acquire_recursive>
    5a12:	4628      	mov	r0, r5
    5a14:	4621      	mov	r1, r4
    5a16:	f7ff ff59 	bl	58cc <__sflush_r>
    5a1a:	6e63      	ldr	r3, [r4, #100]	; 0x64
    5a1c:	07da      	lsls	r2, r3, #31
    5a1e:	4605      	mov	r5, r0
    5a20:	d4e0      	bmi.n	59e4 <_fflush_r+0xc>
    5a22:	89a3      	ldrh	r3, [r4, #12]
    5a24:	059b      	lsls	r3, r3, #22
    5a26:	d4dd      	bmi.n	59e4 <_fflush_r+0xc>
    5a28:	6da0      	ldr	r0, [r4, #88]	; 0x58
    5a2a:	f001 f8de 	bl	6bea <__retarget_lock_release_recursive>
    5a2e:	e7d9      	b.n	59e4 <_fflush_r+0xc>
    5a30:	4b05      	ldr	r3, [pc, #20]	; (5a48 <_fflush_r+0x70>)
    5a32:	429c      	cmp	r4, r3
    5a34:	d101      	bne.n	5a3a <_fflush_r+0x62>
    5a36:	68ac      	ldr	r4, [r5, #8]
    5a38:	e7df      	b.n	59fa <_fflush_r+0x22>
    5a3a:	4b04      	ldr	r3, [pc, #16]	; (5a4c <_fflush_r+0x74>)
    5a3c:	429c      	cmp	r4, r3
    5a3e:	bf08      	it	eq
    5a40:	68ec      	ldreq	r4, [r5, #12]
    5a42:	e7da      	b.n	59fa <_fflush_r+0x22>
    5a44:	000072ac 	.word	0x000072ac
    5a48:	000072cc 	.word	0x000072cc
    5a4c:	0000728c 	.word	0x0000728c

00005a50 <_lseek_r>:
    5a50:	b538      	push	{r3, r4, r5, lr}
    5a52:	4d07      	ldr	r5, [pc, #28]	; (5a70 <_lseek_r+0x20>)
    5a54:	4604      	mov	r4, r0
    5a56:	4608      	mov	r0, r1
    5a58:	4611      	mov	r1, r2
    5a5a:	2200      	movs	r2, #0
    5a5c:	602a      	str	r2, [r5, #0]
    5a5e:	461a      	mov	r2, r3
    5a60:	f000 fd71 	bl	6546 <_lseek>
    5a64:	1c43      	adds	r3, r0, #1
    5a66:	d102      	bne.n	5a6e <_lseek_r+0x1e>
    5a68:	682b      	ldr	r3, [r5, #0]
    5a6a:	b103      	cbz	r3, 5a6e <_lseek_r+0x1e>
    5a6c:	6023      	str	r3, [r4, #0]
    5a6e:	bd38      	pop	{r3, r4, r5, pc}
    5a70:	20000ac8 	.word	0x20000ac8

00005a74 <__smakebuf_r>:
    5a74:	898b      	ldrh	r3, [r1, #12]
    5a76:	b573      	push	{r0, r1, r4, r5, r6, lr}
    5a78:	079d      	lsls	r5, r3, #30
    5a7a:	4606      	mov	r6, r0
    5a7c:	460c      	mov	r4, r1
    5a7e:	d507      	bpl.n	5a90 <__smakebuf_r+0x1c>
    5a80:	f104 0347 	add.w	r3, r4, #71	; 0x47
    5a84:	6023      	str	r3, [r4, #0]
    5a86:	6123      	str	r3, [r4, #16]
    5a88:	2301      	movs	r3, #1
    5a8a:	6163      	str	r3, [r4, #20]
    5a8c:	b002      	add	sp, #8
    5a8e:	bd70      	pop	{r4, r5, r6, pc}
    5a90:	ab01      	add	r3, sp, #4
    5a92:	466a      	mov	r2, sp
    5a94:	f001 f981 	bl	6d9a <__swhatbuf_r>
    5a98:	9900      	ldr	r1, [sp, #0]
    5a9a:	4605      	mov	r5, r0
    5a9c:	4630      	mov	r0, r6
    5a9e:	f7ff fb73 	bl	5188 <_malloc_r>
    5aa2:	b948      	cbnz	r0, 5ab8 <__smakebuf_r+0x44>
    5aa4:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
    5aa8:	059a      	lsls	r2, r3, #22
    5aaa:	d4ef      	bmi.n	5a8c <__smakebuf_r+0x18>
    5aac:	f023 0303 	bic.w	r3, r3, #3
    5ab0:	f043 0302 	orr.w	r3, r3, #2
    5ab4:	81a3      	strh	r3, [r4, #12]
    5ab6:	e7e3      	b.n	5a80 <__smakebuf_r+0xc>
    5ab8:	4b0d      	ldr	r3, [pc, #52]	; (5af0 <__smakebuf_r+0x7c>)
    5aba:	62b3      	str	r3, [r6, #40]	; 0x28
    5abc:	89a3      	ldrh	r3, [r4, #12]
    5abe:	6020      	str	r0, [r4, #0]
    5ac0:	f043 0380 	orr.w	r3, r3, #128	; 0x80
    5ac4:	81a3      	strh	r3, [r4, #12]
    5ac6:	9b00      	ldr	r3, [sp, #0]
    5ac8:	6163      	str	r3, [r4, #20]
    5aca:	9b01      	ldr	r3, [sp, #4]
    5acc:	6120      	str	r0, [r4, #16]
    5ace:	b15b      	cbz	r3, 5ae8 <__smakebuf_r+0x74>
    5ad0:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
    5ad4:	4630      	mov	r0, r6
    5ad6:	f000 f87f 	bl	5bd8 <_isatty_r>
    5ada:	b128      	cbz	r0, 5ae8 <__smakebuf_r+0x74>
    5adc:	89a3      	ldrh	r3, [r4, #12]
    5ade:	f023 0303 	bic.w	r3, r3, #3
    5ae2:	f043 0301 	orr.w	r3, r3, #1
    5ae6:	81a3      	strh	r3, [r4, #12]
    5ae8:	89a0      	ldrh	r0, [r4, #12]
    5aea:	4305      	orrs	r5, r0
    5aec:	81a5      	strh	r5, [r4, #12]
    5aee:	e7cd      	b.n	5a8c <__smakebuf_r+0x18>
    5af0:	00005051 	.word	0x00005051

00005af4 <_free_r>:
    5af4:	b538      	push	{r3, r4, r5, lr}
    5af6:	4605      	mov	r5, r0
    5af8:	2900      	cmp	r1, #0
    5afa:	d045      	beq.n	5b88 <_free_r+0x94>
    5afc:	f851 3c04 	ldr.w	r3, [r1, #-4]
    5b00:	1f0c      	subs	r4, r1, #4
    5b02:	2b00      	cmp	r3, #0
    5b04:	bfb8      	it	lt
    5b06:	18e4      	addlt	r4, r4, r3
    5b08:	f7fd f924 	bl	2d54 <__malloc_lock>
    5b0c:	4a1f      	ldr	r2, [pc, #124]	; (5b8c <_free_r+0x98>)
    5b0e:	6813      	ldr	r3, [r2, #0]
    5b10:	4610      	mov	r0, r2
    5b12:	b933      	cbnz	r3, 5b22 <_free_r+0x2e>
    5b14:	6063      	str	r3, [r4, #4]
    5b16:	6014      	str	r4, [r2, #0]
    5b18:	4628      	mov	r0, r5
    5b1a:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
    5b1e:	f7fd b923 	b.w	2d68 <__malloc_unlock>
    5b22:	42a3      	cmp	r3, r4
    5b24:	d90b      	bls.n	5b3e <_free_r+0x4a>
    5b26:	6821      	ldr	r1, [r4, #0]
    5b28:	1862      	adds	r2, r4, r1
    5b2a:	4293      	cmp	r3, r2
    5b2c:	bf04      	itt	eq
    5b2e:	681a      	ldreq	r2, [r3, #0]
    5b30:	685b      	ldreq	r3, [r3, #4]
    5b32:	6063      	str	r3, [r4, #4]
    5b34:	bf04      	itt	eq
    5b36:	1852      	addeq	r2, r2, r1
    5b38:	6022      	streq	r2, [r4, #0]
    5b3a:	6004      	str	r4, [r0, #0]
    5b3c:	e7ec      	b.n	5b18 <_free_r+0x24>
    5b3e:	461a      	mov	r2, r3
    5b40:	685b      	ldr	r3, [r3, #4]
    5b42:	b10b      	cbz	r3, 5b48 <_free_r+0x54>
    5b44:	42a3      	cmp	r3, r4
    5b46:	d9fa      	bls.n	5b3e <_free_r+0x4a>
    5b48:	6811      	ldr	r1, [r2, #0]
    5b4a:	1850      	adds	r0, r2, r1
    5b4c:	42a0      	cmp	r0, r4
    5b4e:	d10b      	bne.n	5b68 <_free_r+0x74>
    5b50:	6820      	ldr	r0, [r4, #0]
    5b52:	4401      	add	r1, r0
    5b54:	1850      	adds	r0, r2, r1
    5b56:	4283      	cmp	r3, r0
    5b58:	6011      	str	r1, [r2, #0]
    5b5a:	d1dd      	bne.n	5b18 <_free_r+0x24>
    5b5c:	6818      	ldr	r0, [r3, #0]
    5b5e:	685b      	ldr	r3, [r3, #4]
    5b60:	6053      	str	r3, [r2, #4]
    5b62:	4401      	add	r1, r0
    5b64:	6011      	str	r1, [r2, #0]
    5b66:	e7d7      	b.n	5b18 <_free_r+0x24>
    5b68:	d902      	bls.n	5b70 <_free_r+0x7c>
    5b6a:	230c      	movs	r3, #12
    5b6c:	602b      	str	r3, [r5, #0]
    5b6e:	e7d3      	b.n	5b18 <_free_r+0x24>
    5b70:	6820      	ldr	r0, [r4, #0]
    5b72:	1821      	adds	r1, r4, r0
    5b74:	428b      	cmp	r3, r1
    5b76:	bf04      	itt	eq
    5b78:	6819      	ldreq	r1, [r3, #0]
    5b7a:	685b      	ldreq	r3, [r3, #4]
    5b7c:	6063      	str	r3, [r4, #4]
    5b7e:	bf04      	itt	eq
    5b80:	1809      	addeq	r1, r1, r0
    5b82:	6021      	streq	r1, [r4, #0]
    5b84:	6054      	str	r4, [r2, #4]
    5b86:	e7c7      	b.n	5b18 <_free_r+0x24>
    5b88:	bd38      	pop	{r3, r4, r5, pc}
    5b8a:	bf00      	nop
    5b8c:	20000690 	.word	0x20000690

00005b90 <_read_r>:
    5b90:	b538      	push	{r3, r4, r5, lr}
    5b92:	4d07      	ldr	r5, [pc, #28]	; (5bb0 <_read_r+0x20>)
    5b94:	4604      	mov	r4, r0
    5b96:	4608      	mov	r0, r1
    5b98:	4611      	mov	r1, r2
    5b9a:	2200      	movs	r2, #0
    5b9c:	602a      	str	r2, [r5, #0]
    5b9e:	461a      	mov	r2, r3
    5ba0:	f000 fcc6 	bl	6530 <_read>
    5ba4:	1c43      	adds	r3, r0, #1
    5ba6:	d102      	bne.n	5bae <_read_r+0x1e>
    5ba8:	682b      	ldr	r3, [r5, #0]
    5baa:	b103      	cbz	r3, 5bae <_read_r+0x1e>
    5bac:	6023      	str	r3, [r4, #0]
    5bae:	bd38      	pop	{r3, r4, r5, pc}
    5bb0:	20000ac8 	.word	0x20000ac8

00005bb4 <_fstat_r>:
    5bb4:	b538      	push	{r3, r4, r5, lr}
    5bb6:	4d07      	ldr	r5, [pc, #28]	; (5bd4 <_fstat_r+0x20>)
    5bb8:	2300      	movs	r3, #0
    5bba:	4604      	mov	r4, r0
    5bbc:	4608      	mov	r0, r1
    5bbe:	4611      	mov	r1, r2
    5bc0:	602b      	str	r3, [r5, #0]
    5bc2:	f000 fcc7 	bl	6554 <_fstat>
    5bc6:	1c43      	adds	r3, r0, #1
    5bc8:	d102      	bne.n	5bd0 <_fstat_r+0x1c>
    5bca:	682b      	ldr	r3, [r5, #0]
    5bcc:	b103      	cbz	r3, 5bd0 <_fstat_r+0x1c>
    5bce:	6023      	str	r3, [r4, #0]
    5bd0:	bd38      	pop	{r3, r4, r5, pc}
    5bd2:	bf00      	nop
    5bd4:	20000ac8 	.word	0x20000ac8

00005bd8 <_isatty_r>:
    5bd8:	b538      	push	{r3, r4, r5, lr}
    5bda:	4d06      	ldr	r5, [pc, #24]	; (5bf4 <_isatty_r+0x1c>)
    5bdc:	2300      	movs	r3, #0
    5bde:	4604      	mov	r4, r0
    5be0:	4608      	mov	r0, r1
    5be2:	602b      	str	r3, [r5, #0]
    5be4:	f000 fcb1 	bl	654a <_isatty>
    5be8:	1c43      	adds	r3, r0, #1
    5bea:	d102      	bne.n	5bf2 <_isatty_r+0x1a>
    5bec:	682b      	ldr	r3, [r5, #0]
    5bee:	b103      	cbz	r3, 5bf2 <_isatty_r+0x1a>
    5bf0:	6023      	str	r3, [r4, #0]
    5bf2:	bd38      	pop	{r3, r4, r5, pc}
    5bf4:	20000ac8 	.word	0x20000ac8

00005bf8 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    5bf8:	4603      	mov	r3, r0
    5bfa:	b158      	cbz	r0, 5c14 <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    5bfc:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    5bfe:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    5c02:	2a01      	cmp	r2, #1
    5c04:	d003      	beq.n	5c0e <sys_notify_validate+0x16>
    5c06:	2a03      	cmp	r2, #3
    5c08:	d104      	bne.n	5c14 <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    5c0a:	6802      	ldr	r2, [r0, #0]
    5c0c:	b112      	cbz	r2, 5c14 <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    5c0e:	2000      	movs	r0, #0
    5c10:	6098      	str	r0, [r3, #8]
    5c12:	4770      	bx	lr
		return -EINVAL;
    5c14:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    5c18:	4770      	bx	lr

00005c1a <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    5c1a:	6842      	ldr	r2, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    5c1c:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    5c1e:	f002 0203 	and.w	r2, r2, #3
	switch (method) {
    5c22:	2a03      	cmp	r2, #3
    5c24:	f04f 0200 	mov.w	r2, #0
{
    5c28:	4603      	mov	r3, r0
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    5c2a:	bf0c      	ite	eq
    5c2c:	6800      	ldreq	r0, [r0, #0]
	sys_notify_generic_callback rv = NULL;
    5c2e:	4610      	movne	r0, r2
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    5c30:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    5c32:	4770      	bx	lr

00005c34 <arch_printk_char_out>:
}
    5c34:	2000      	movs	r0, #0
    5c36:	4770      	bx	lr

00005c38 <str_out>:
{
    5c38:	b530      	push	{r4, r5, lr}
    5c3a:	688a      	ldr	r2, [r1, #8]
	if (ctx->str == NULL || ctx->count >= ctx->max) {
    5c3c:	680c      	ldr	r4, [r1, #0]
    5c3e:	1c55      	adds	r5, r2, #1
    5c40:	b114      	cbz	r4, 5c48 <str_out+0x10>
    5c42:	684b      	ldr	r3, [r1, #4]
    5c44:	4293      	cmp	r3, r2
    5c46:	dc01      	bgt.n	5c4c <str_out+0x14>
		ctx->count++;
    5c48:	608d      	str	r5, [r1, #8]
}
    5c4a:	bd30      	pop	{r4, r5, pc}
	if (ctx->count == ctx->max - 1) {
    5c4c:	3b01      	subs	r3, #1
    5c4e:	4293      	cmp	r3, r2
		ctx->str[ctx->count++] = '\0';
    5c50:	bf08      	it	eq
    5c52:	2200      	moveq	r2, #0
    5c54:	608d      	str	r5, [r1, #8]
    5c56:	bf0c      	ite	eq
    5c58:	54e2      	strbeq	r2, [r4, r3]
		ctx->str[ctx->count++] = c;
    5c5a:	54a0      	strbne	r0, [r4, r2]
    5c5c:	e7f5      	b.n	5c4a <str_out+0x12>

00005c5e <printk>:
{
    5c5e:	b40f      	push	{r0, r1, r2, r3}
    5c60:	b507      	push	{r0, r1, r2, lr}
    5c62:	a904      	add	r1, sp, #16
    5c64:	f851 0b04 	ldr.w	r0, [r1], #4
	va_start(ap, fmt);
    5c68:	9101      	str	r1, [sp, #4]
		vprintk(fmt, ap);
    5c6a:	f7fa fc43 	bl	4f4 <vprintk>
}
    5c6e:	b003      	add	sp, #12
    5c70:	f85d eb04 	ldr.w	lr, [sp], #4
    5c74:	b004      	add	sp, #16
    5c76:	4770      	bx	lr

00005c78 <snprintk>:
{
    5c78:	b40c      	push	{r2, r3}
    5c7a:	b507      	push	{r0, r1, r2, lr}
    5c7c:	ab04      	add	r3, sp, #16
    5c7e:	f853 2b04 	ldr.w	r2, [r3], #4
	va_start(ap, fmt);
    5c82:	9301      	str	r3, [sp, #4]
	ret = vsnprintk(str, size, fmt, ap);
    5c84:	f7fa fc44 	bl	510 <vsnprintk>
}
    5c88:	b003      	add	sp, #12
    5c8a:	f85d eb04 	ldr.w	lr, [sp], #4
    5c8e:	b002      	add	sp, #8
    5c90:	4770      	bx	lr

00005c92 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5c92:	8b83      	ldrh	r3, [r0, #28]
	if ((state == ONOFF_STATE_OFF)
    5c94:	f013 0307 	ands.w	r3, r3, #7
    5c98:	d105      	bne.n	5ca6 <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    5c9a:	6803      	ldr	r3, [r0, #0]
    5c9c:	2b00      	cmp	r3, #0
		evt = EVT_START;
    5c9e:	bf0c      	ite	eq
    5ca0:	2000      	moveq	r0, #0
    5ca2:	2003      	movne	r0, #3
    5ca4:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    5ca6:	2b02      	cmp	r3, #2
    5ca8:	d105      	bne.n	5cb6 <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    5caa:	8bc3      	ldrh	r3, [r0, #30]
    5cac:	2b00      	cmp	r3, #0
		evt = EVT_STOP;
    5cae:	bf14      	ite	ne
    5cb0:	2000      	movne	r0, #0
    5cb2:	2004      	moveq	r0, #4
    5cb4:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    5cb6:	2b01      	cmp	r3, #1
    5cb8:	d105      	bne.n	5cc6 <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    5cba:	6803      	ldr	r3, [r0, #0]
    5cbc:	2b00      	cmp	r3, #0
		evt = EVT_RESET;
    5cbe:	bf0c      	ite	eq
    5cc0:	2000      	moveq	r0, #0
    5cc2:	2005      	movne	r0, #5
    5cc4:	4770      	bx	lr
	int evt = EVT_NOP;
    5cc6:	2000      	movs	r0, #0
}
    5cc8:	4770      	bx	lr

00005cca <notify_one>:
{
    5cca:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5cce:	460d      	mov	r5, r1
    5cd0:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5cd2:	4619      	mov	r1, r3
    5cd4:	1d28      	adds	r0, r5, #4
{
    5cd6:	4690      	mov	r8, r2
    5cd8:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5cda:	f7ff ff9e 	bl	5c1a <sys_notify_finalize>
	if (cb) {
    5cde:	4604      	mov	r4, r0
    5ce0:	b138      	cbz	r0, 5cf2 <notify_one+0x28>
		cb(mgr, cli, state, res);
    5ce2:	4633      	mov	r3, r6
    5ce4:	4642      	mov	r2, r8
    5ce6:	4629      	mov	r1, r5
    5ce8:	4638      	mov	r0, r7
    5cea:	46a4      	mov	ip, r4
}
    5cec:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    5cf0:	4760      	bx	ip
}
    5cf2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005cf6 <transition_complete>:
{
    5cf6:	b410      	push	{r4}
	__asm__ volatile(
    5cf8:	f04f 0420 	mov.w	r4, #32
    5cfc:	f3ef 8211 	mrs	r2, BASEPRI
    5d00:	f384 8811 	msr	BASEPRI, r4
    5d04:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    5d08:	6181      	str	r1, [r0, #24]
}
    5d0a:	bc10      	pop	{r4}
	process_event(mgr, EVT_COMPLETE, key);
    5d0c:	2101      	movs	r1, #1
    5d0e:	f7fa bc13 	b.w	538 <process_event>

00005d12 <validate_args>:
{
    5d12:	b510      	push	{r4, lr}
    5d14:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    5d16:	b140      	cbz	r0, 5d2a <validate_args+0x18>
    5d18:	b139      	cbz	r1, 5d2a <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
    5d1a:	1d08      	adds	r0, r1, #4
    5d1c:	f7ff ff6c 	bl	5bf8 <sys_notify_validate>
	if ((rv == 0)
    5d20:	b928      	cbnz	r0, 5d2e <validate_args+0x1c>
	    && ((cli->notify.flags
    5d22:	68a3      	ldr	r3, [r4, #8]
    5d24:	f033 0303 	bics.w	r3, r3, #3
    5d28:	d001      	beq.n	5d2e <validate_args+0x1c>
		rv = -EINVAL;
    5d2a:	f06f 0015 	mvn.w	r0, #21
}
    5d2e:	bd10      	pop	{r4, pc}

00005d30 <onoff_manager_init>:
{
    5d30:	b538      	push	{r3, r4, r5, lr}
    5d32:	460c      	mov	r4, r1
	if ((mgr == NULL)
    5d34:	4605      	mov	r5, r0
    5d36:	b158      	cbz	r0, 5d50 <onoff_manager_init+0x20>
	    || (transitions == NULL)
    5d38:	b151      	cbz	r1, 5d50 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    5d3a:	680b      	ldr	r3, [r1, #0]
    5d3c:	b143      	cbz	r3, 5d50 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    5d3e:	684b      	ldr	r3, [r1, #4]
    5d40:	b133      	cbz	r3, 5d50 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    5d42:	2220      	movs	r2, #32
    5d44:	2100      	movs	r1, #0
    5d46:	f000 fee9 	bl	6b1c <memset>
    5d4a:	612c      	str	r4, [r5, #16]
	return 0;
    5d4c:	2000      	movs	r0, #0
}
    5d4e:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    5d50:	f06f 0015 	mvn.w	r0, #21
    5d54:	e7fb      	b.n	5d4e <onoff_manager_init+0x1e>

00005d56 <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    5d56:	b570      	push	{r4, r5, r6, lr}
    5d58:	4604      	mov	r4, r0
    5d5a:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    5d5c:	f7ff ffd9 	bl	5d12 <validate_args>

	if (rv < 0) {
    5d60:	1e05      	subs	r5, r0, #0
    5d62:	db31      	blt.n	5dc8 <onoff_request+0x72>
    5d64:	f04f 0320 	mov.w	r3, #32
    5d68:	f3ef 8111 	mrs	r1, BASEPRI
    5d6c:	f383 8811 	msr	BASEPRI, r3
    5d70:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    5d74:	8be3      	ldrh	r3, [r4, #30]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5d76:	8ba0      	ldrh	r0, [r4, #28]
	if (mgr->refs == SERVICE_REFS_MAX) {
    5d78:	f64f 75ff 	movw	r5, #65535	; 0xffff
    5d7c:	42ab      	cmp	r3, r5
    5d7e:	f000 0207 	and.w	r2, r0, #7
    5d82:	d02e      	beq.n	5de2 <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
    5d84:	2a02      	cmp	r2, #2
    5d86:	d10e      	bne.n	5da6 <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
    5d88:	3301      	adds	r3, #1
    5d8a:	83e3      	strh	r3, [r4, #30]
	rv = state;
    5d8c:	4615      	mov	r5, r2
		notify = true;
    5d8e:	2301      	movs	r3, #1
	__asm__ volatile(
    5d90:	f381 8811 	msr	BASEPRI, r1
    5d94:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    5d98:	b1b3      	cbz	r3, 5dc8 <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
    5d9a:	2300      	movs	r3, #0
    5d9c:	4631      	mov	r1, r6
    5d9e:	4620      	mov	r0, r4
    5da0:	f7ff ff93 	bl	5cca <notify_one>
    5da4:	e010      	b.n	5dc8 <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
    5da6:	0783      	lsls	r3, r0, #30
    5da8:	d001      	beq.n	5dae <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
    5daa:	2a06      	cmp	r2, #6
    5dac:	d10e      	bne.n	5dcc <onoff_request+0x76>
	parent->next = child;
    5dae:	2300      	movs	r3, #0
    5db0:	6033      	str	r3, [r6, #0]
Z_GENLIST_APPEND(slist, snode)
    5db2:	6863      	ldr	r3, [r4, #4]
    5db4:	b993      	cbnz	r3, 5ddc <onoff_request+0x86>
	list->head = node;
    5db6:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
    5dba:	4615      	mov	r5, r2
    5dbc:	b962      	cbnz	r2, 5dd8 <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
    5dbe:	460a      	mov	r2, r1
    5dc0:	4620      	mov	r0, r4
    5dc2:	2102      	movs	r1, #2
    5dc4:	f7fa fbb8 	bl	538 <process_event>
		}
	}

	return rv;
}
    5dc8:	4628      	mov	r0, r5
    5dca:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
    5dcc:	2a05      	cmp	r2, #5
    5dce:	bf0c      	ite	eq
    5dd0:	f06f 0585 	mvneq.w	r5, #133	; 0x85
    5dd4:	f06f 0504 	mvnne.w	r5, #4
    5dd8:	2300      	movs	r3, #0
    5dda:	e7d9      	b.n	5d90 <onoff_request+0x3a>
	parent->next = child;
    5ddc:	601e      	str	r6, [r3, #0]
	list->tail = node;
    5dde:	6066      	str	r6, [r4, #4]
}
    5de0:	e7eb      	b.n	5dba <onoff_request+0x64>
		rv = -EAGAIN;
    5de2:	f06f 050a 	mvn.w	r5, #10
    5de6:	e7f7      	b.n	5dd8 <onoff_request+0x82>

00005de8 <onoff_release>:

int onoff_release(struct onoff_manager *mgr)
{
    5de8:	b510      	push	{r4, lr}
	__asm__ volatile(
    5dea:	f04f 0320 	mov.w	r3, #32
    5dee:	f3ef 8211 	mrs	r2, BASEPRI
    5df2:	f383 8811 	msr	BASEPRI, r3
    5df6:	f3bf 8f6f 	isb	sy
	bool stop = false;      /* trigger a stop transition */

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5dfa:	8b84      	ldrh	r4, [r0, #28]
    5dfc:	f004 0407 	and.w	r4, r4, #7
	int rv = state;

	if (state != ONOFF_STATE_ON) {
    5e00:	2c02      	cmp	r4, #2
    5e02:	d00a      	beq.n	5e1a <onoff_release+0x32>
		if (state == ONOFF_STATE_ERROR) {
    5e04:	2c01      	cmp	r4, #1
			rv = -EIO;
		} else {
			rv = -ENOTSUP;
    5e06:	bf0c      	ite	eq
    5e08:	f06f 0004 	mvneq.w	r0, #4
    5e0c:	f06f 0085 	mvnne.w	r0, #133	; 0x85
	__asm__ volatile(
    5e10:	f382 8811 	msr	BASEPRI, r2
    5e14:	f3bf 8f6f 	isb	sy
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);
	}

	return rv;
    5e18:	e008      	b.n	5e2c <onoff_release+0x44>
	mgr->refs -= 1U;
    5e1a:	8bc3      	ldrh	r3, [r0, #30]
    5e1c:	3b01      	subs	r3, #1
    5e1e:	b29b      	uxth	r3, r3
    5e20:	83c3      	strh	r3, [r0, #30]
	if (stop) {
    5e22:	b923      	cbnz	r3, 5e2e <onoff_release+0x46>
		process_event(mgr, EVT_RECHECK, key);
    5e24:	4621      	mov	r1, r4
    5e26:	f7fa fb87 	bl	538 <process_event>
	int rv = state;
    5e2a:	4620      	mov	r0, r4
}
    5e2c:	bd10      	pop	{r4, pc}
	int rv = state;
    5e2e:	4620      	mov	r0, r4
    5e30:	e7ee      	b.n	5e10 <onoff_release+0x28>

00005e32 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    5e32:	4604      	mov	r4, r0
    5e34:	b508      	push	{r3, lr}
    5e36:	4608      	mov	r0, r1
    5e38:	4611      	mov	r1, r2
	entry(p1, p2, p3);
    5e3a:	461a      	mov	r2, r3
    5e3c:	47a0      	blx	r4
	return z_impl_k_current_get();
    5e3e:	f7fe fe2b 	bl	4a98 <z_impl_k_current_get>
	z_impl_k_thread_abort(thread);
    5e42:	f7fc fe7d 	bl	2b40 <z_impl_k_thread_abort>

00005e46 <outs>:
{
    5e46:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5e4a:	4607      	mov	r7, r0
    5e4c:	4688      	mov	r8, r1
    5e4e:	4615      	mov	r5, r2
    5e50:	461e      	mov	r6, r3
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    5e52:	4614      	mov	r4, r2
    5e54:	42b4      	cmp	r4, r6
    5e56:	eba4 0005 	sub.w	r0, r4, r5
    5e5a:	d302      	bcc.n	5e62 <outs+0x1c>
    5e5c:	b93e      	cbnz	r6, 5e6e <outs+0x28>
    5e5e:	7823      	ldrb	r3, [r4, #0]
    5e60:	b12b      	cbz	r3, 5e6e <outs+0x28>
		int rc = out((int)*sp++, ctx);
    5e62:	f814 0b01 	ldrb.w	r0, [r4], #1
    5e66:	4641      	mov	r1, r8
    5e68:	47b8      	blx	r7
		if (rc < 0) {
    5e6a:	2800      	cmp	r0, #0
    5e6c:	daf2      	bge.n	5e54 <outs+0xe>
}
    5e6e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005e72 <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_DISASSEMBLY, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_PRINT_MEMORY_USAGE, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    5e72:	4770      	bx	lr

00005e74 <log_list_init>:

#include "log_list.h"

void log_list_init(struct log_list_t *list)
{
	list->tail = NULL;
    5e74:	2300      	movs	r3, #0
	list->head = NULL;
    5e76:	e9c0 3300 	strd	r3, r3, [r0]
}
    5e7a:	4770      	bx	lr

00005e7c <log_list_add_tail>:

void log_list_add_tail(struct log_list_t *list, struct log_msg *msg)
{
	if (list->head == NULL) {
    5e7c:	6803      	ldr	r3, [r0, #0]
    5e7e:	b923      	cbnz	r3, 5e8a <log_list_add_tail+0xe>
		list->head = msg;
    5e80:	6001      	str	r1, [r0, #0]
	} else {
		list->tail->next = msg;
	}

	list->tail = msg;
	msg->next = NULL;
    5e82:	2300      	movs	r3, #0
	list->tail = msg;
    5e84:	6041      	str	r1, [r0, #4]
	msg->next = NULL;
    5e86:	600b      	str	r3, [r1, #0]
}
    5e88:	4770      	bx	lr
		list->tail->next = msg;
    5e8a:	6843      	ldr	r3, [r0, #4]
    5e8c:	6019      	str	r1, [r3, #0]
    5e8e:	e7f8      	b.n	5e82 <log_list_add_tail+0x6>

00005e90 <log_list_head_peek>:

struct log_msg *log_list_head_peek(struct log_list_t *list)
{
	return list->head;
}
    5e90:	6800      	ldr	r0, [r0, #0]
    5e92:	4770      	bx	lr

00005e94 <log_list_head_get>:

struct log_msg *log_list_head_get(struct log_list_t *list)
{
    5e94:	4603      	mov	r3, r0
	struct log_msg *msg = list->head;
    5e96:	6800      	ldr	r0, [r0, #0]

	if (list->head != NULL) {
    5e98:	b108      	cbz	r0, 5e9e <log_list_head_get+0xa>
		list->head = list->head->next;
    5e9a:	6802      	ldr	r2, [r0, #0]
    5e9c:	601a      	str	r2, [r3, #0]
	}

	return msg;
}
    5e9e:	4770      	bx	lr

00005ea0 <z_log_msg_std_alloc>:
/** @brief Allocate chunk for standard log message.
 *
 *  @return Allocated chunk of NULL.
 */
static inline struct log_msg *z_log_msg_std_alloc(void)
{
    5ea0:	b508      	push	{r3, lr}
	struct  log_msg *msg = (struct  log_msg *)log_msg_chunk_alloc();
    5ea2:	f7fb fb25 	bl	14f0 <log_msg_chunk_alloc>

	if (msg != NULL) {
    5ea6:	b118      	cbz	r0, 5eb0 <z_log_msg_std_alloc+0x10>
		/* all fields reset to 0, reference counter to 1 */
		msg->hdr.ref_cnt = 1;
    5ea8:	2301      	movs	r3, #1
    5eaa:	6043      	str	r3, [r0, #4]
		msg->hdr.params.raw = 0U;
    5eac:	2300      	movs	r3, #0
    5eae:	8103      	strh	r3, [r0, #8]
			msg->hdr.ids.source_id = 0;
		}
	}

	return msg;
}
    5eb0:	bd08      	pop	{r3, pc}

00005eb2 <default_get_timestamp>:
#ifndef _ASMLANGUAGE
extern uint32_t sys_clock_cycle_get_32(void);

static inline uint32_t arch_k_cycle_get_32(void)
{
	return sys_clock_cycle_get_32();
    5eb2:	f7fc ba45 	b.w	2340 <sys_clock_cycle_get_32>

00005eb6 <dummy_timestamp>:
    5eb6:	2000      	movs	r0, #0
    5eb8:	4770      	bx	lr

00005eba <log_0>:
{
    5eba:	b538      	push	{r3, r4, r5, lr}
    5ebc:	4605      	mov	r5, r0
    5ebe:	460c      	mov	r4, r1
 *
 *  @return Pointer to allocated head of the message or NULL.
 */
static inline struct log_msg *log_msg_create_0(const char *str)
{
	struct log_msg *msg = z_log_msg_std_alloc();
    5ec0:	f7ff ffee 	bl	5ea0 <z_log_msg_std_alloc>

	if (msg != NULL) {
    5ec4:	b128      	cbz	r0, 5ed2 <log_0+0x18>
		msg->str = str;
    5ec6:	6105      	str	r5, [r0, #16]
		msg_finalize(msg, src_level);
    5ec8:	4621      	mov	r1, r4
}
    5eca:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
		msg_finalize(msg, src_level);
    5ece:	f7fb ba29 	b.w	1324 <msg_finalize>
}
    5ed2:	bd38      	pop	{r3, r4, r5, pc}

00005ed4 <log_1>:
{
    5ed4:	b570      	push	{r4, r5, r6, lr}
    5ed6:	4606      	mov	r6, r0
    5ed8:	460d      	mov	r5, r1
    5eda:	4614      	mov	r4, r2
 *  @return Pointer to allocated head of the message or NULL.
 */
static inline struct log_msg *log_msg_create_1(const char *str,
					       log_arg_t arg1)
{
	struct  log_msg *msg = z_log_msg_std_alloc();
    5edc:	f7ff ffe0 	bl	5ea0 <z_log_msg_std_alloc>

	if (msg != NULL) {
    5ee0:	b158      	cbz	r0, 5efa <log_1+0x26>
		msg->str = str;
		msg->hdr.params.std.nargs = 1U;
    5ee2:	7a42      	ldrb	r2, [r0, #9]
		msg->str = str;
    5ee4:	6106      	str	r6, [r0, #16]
		msg->hdr.params.std.nargs = 1U;
    5ee6:	2101      	movs	r1, #1
    5ee8:	f361 1207 	bfi	r2, r1, #4, #4
    5eec:	7242      	strb	r2, [r0, #9]
		msg->payload.single.args[0] = arg1;
    5eee:	6145      	str	r5, [r0, #20]
		msg_finalize(msg, src_level);
    5ef0:	4621      	mov	r1, r4
}
    5ef2:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		msg_finalize(msg, src_level);
    5ef6:	f7fb ba15 	b.w	1324 <msg_finalize>
}
    5efa:	bd70      	pop	{r4, r5, r6, pc}

00005efc <log_2>:
{
    5efc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5f00:	4680      	mov	r8, r0
    5f02:	460f      	mov	r7, r1
    5f04:	4616      	mov	r6, r2
    5f06:	461d      	mov	r5, r3
 */
static inline struct log_msg *log_msg_create_2(const char *str,
					       log_arg_t arg1,
					       log_arg_t arg2)
{
	struct  log_msg *msg = z_log_msg_std_alloc();
    5f08:	f7ff ffca 	bl	5ea0 <z_log_msg_std_alloc>

	if (msg != NULL) {
    5f0c:	b168      	cbz	r0, 5f2a <log_2+0x2e>
		msg->str = str;
		msg->hdr.params.std.nargs = 2U;
    5f0e:	7a43      	ldrb	r3, [r0, #9]
		msg->str = str;
    5f10:	f8c0 8010 	str.w	r8, [r0, #16]
		msg->hdr.params.std.nargs = 2U;
    5f14:	2202      	movs	r2, #2
    5f16:	f362 1307 	bfi	r3, r2, #4, #4
    5f1a:	7243      	strb	r3, [r0, #9]
		msg->payload.single.args[0] = arg1;
		msg->payload.single.args[1] = arg2;
    5f1c:	e9c0 7605 	strd	r7, r6, [r0, #20]
		msg_finalize(msg, src_level);
    5f20:	4629      	mov	r1, r5
}
    5f22:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		msg_finalize(msg, src_level);
    5f26:	f7fb b9fd 	b.w	1324 <msg_finalize>
}
    5f2a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005f2e <log_3>:
{
    5f2e:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    5f32:	4680      	mov	r8, r0
    5f34:	f8bd 9020 	ldrh.w	r9, [sp, #32]
    5f38:	460f      	mov	r7, r1
    5f3a:	4616      	mov	r6, r2
    5f3c:	461d      	mov	r5, r3
static inline struct log_msg *log_msg_create_3(const char *str,
					       log_arg_t arg1,
					       log_arg_t arg2,
					       log_arg_t arg3)
{
	struct  log_msg *msg = z_log_msg_std_alloc();
    5f3e:	f7ff ffaf 	bl	5ea0 <z_log_msg_std_alloc>

	if (msg != NULL) {
    5f42:	b170      	cbz	r0, 5f62 <log_3+0x34>
		msg->str = str;
		msg->hdr.params.std.nargs = 3U;
    5f44:	7a43      	ldrb	r3, [r0, #9]
		msg->str = str;
    5f46:	f8c0 8010 	str.w	r8, [r0, #16]
		msg->hdr.params.std.nargs = 3U;
    5f4a:	2203      	movs	r2, #3
    5f4c:	f362 1307 	bfi	r3, r2, #4, #4
    5f50:	7243      	strb	r3, [r0, #9]
		msg->payload.single.args[0] = arg1;
		msg->payload.single.args[1] = arg2;
    5f52:	e9c0 7605 	strd	r7, r6, [r0, #20]
		msg->payload.single.args[2] = arg3;
    5f56:	61c5      	str	r5, [r0, #28]
		msg_finalize(msg, src_level);
    5f58:	4649      	mov	r1, r9
}
    5f5a:	e8bd 43f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
		msg_finalize(msg, src_level);
    5f5e:	f7fb b9e1 	b.w	1324 <msg_finalize>
}
    5f62:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

00005f66 <log_msg_hexdump_data_op>:
static void log_msg_hexdump_data_op(struct log_msg *msg,
				    uint8_t *data,
				    size_t *length,
				    size_t offset,
				    bool put_op)
{
    5f66:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    5f6a:	461c      	mov	r4, r3
	uint32_t available_len = msg->hdr.params.hexdump.length;
    5f6c:	8903      	ldrh	r3, [r0, #8]
{
    5f6e:	f89d 7020 	ldrb.w	r7, [sp, #32]
    5f72:	460e      	mov	r6, r1
    5f74:	4611      	mov	r1, r2
	uint32_t available_len = msg->hdr.params.hexdump.length;
    5f76:	f3c3 028d 	ubfx	r2, r3, #2, #14
	uint8_t *head_data;
	uint32_t chunk_len;
	uint32_t req_len;
	uint32_t cpy_len;

	if (offset >= available_len) {
    5f7a:	42a2      	cmp	r2, r4
    5f7c:	d803      	bhi.n	5f86 <log_msg_hexdump_data_op+0x20>
		*length = 0;
    5f7e:	2300      	movs	r3, #0
    5f80:	600b      	str	r3, [r1, #0]
		offset = 0;
		cont = cont->next;
		req_len -= cpy_len;
		data += cpy_len;
	}
}
    5f82:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
	if ((offset + *length) > available_len) {
    5f86:	680b      	ldr	r3, [r1, #0]
    5f88:	4423      	add	r3, r4
    5f8a:	4293      	cmp	r3, r2
		*length = available_len - offset;
    5f8c:	bf84      	itt	hi
    5f8e:	1b13      	subhi	r3, r2, r4
    5f90:	600b      	strhi	r3, [r1, #0]
	if (available_len > LOG_MSG_HEXDUMP_BYTES_SINGLE_CHUNK) {
    5f92:	2a0c      	cmp	r2, #12
	req_len = *length;
    5f94:	f8d1 9000 	ldr.w	r9, [r1]
	if (available_len > LOG_MSG_HEXDUMP_BYTES_SINGLE_CHUNK) {
    5f98:	d92a      	bls.n	5ff0 <log_msg_hexdump_data_op+0x8a>
	if (offset < chunk_len) {
    5f9a:	2c07      	cmp	r4, #7
		cont = msg->payload.ext.next;
    5f9c:	f8d0 8014 	ldr.w	r8, [r0, #20]
	if (offset < chunk_len) {
    5fa0:	d82d      	bhi.n	5ffe <log_msg_hexdump_data_op+0x98>
		head_data = msg->payload.ext.data.bytes;
    5fa2:	3018      	adds	r0, #24
		chunk_len = LOG_MSG_HEXDUMP_BYTES_HEAD_CHUNK;
    5fa4:	2208      	movs	r2, #8
		cpy_len = req_len > chunk_len ? chunk_len : req_len;
    5fa6:	454a      	cmp	r2, r9
    5fa8:	bf28      	it	cs
    5faa:	464a      	movcs	r2, r9
    5fac:	4615      	mov	r5, r2
		if (put_op) {
    5fae:	4420      	add	r0, r4
    5fb0:	b317      	cbz	r7, 5ff8 <log_msg_hexdump_data_op+0x92>
    5fb2:	4631      	mov	r1, r6
    5fb4:	f000 fda4 	bl	6b00 <memcpy>
		req_len -= cpy_len;
    5fb8:	eba9 0905 	sub.w	r9, r9, r5
		data += cpy_len;
    5fbc:	442e      	add	r6, r5
	while ((req_len > 0) && (cont != NULL)) {
    5fbe:	f1b9 0f00 	cmp.w	r9, #0
    5fc2:	d0de      	beq.n	5f82 <log_msg_hexdump_data_op+0x1c>
    5fc4:	f1b8 0f00 	cmp.w	r8, #0
    5fc8:	d0db      	beq.n	5f82 <log_msg_hexdump_data_op+0x1c>
		chunk_len = HEXDUMP_BYTES_CONT_MSG - offset;
    5fca:	f1c4 051c 	rsb	r5, r4, #28
		cpy_len = req_len > chunk_len ? chunk_len : req_len;
    5fce:	454d      	cmp	r5, r9
    5fd0:	bf28      	it	cs
    5fd2:	464d      	movcs	r5, r9
		if (put_op) {
    5fd4:	1d20      	adds	r0, r4, #4
    5fd6:	4440      	add	r0, r8
    5fd8:	462a      	mov	r2, r5
    5fda:	b1bf      	cbz	r7, 600c <log_msg_hexdump_data_op+0xa6>
    5fdc:	4631      	mov	r1, r6
    5fde:	f000 fd8f 	bl	6b00 <memcpy>
		req_len -= cpy_len;
    5fe2:	eba9 0905 	sub.w	r9, r9, r5
		cont = cont->next;
    5fe6:	f8d8 8000 	ldr.w	r8, [r8]
		data += cpy_len;
    5fea:	442e      	add	r6, r5
		offset = 0;
    5fec:	2400      	movs	r4, #0
    5fee:	e7e6      	b.n	5fbe <log_msg_hexdump_data_op+0x58>
		head_data = msg->payload.single.bytes;
    5ff0:	3014      	adds	r0, #20
	struct log_msg_cont *cont = NULL;
    5ff2:	f04f 0800 	mov.w	r8, #0
    5ff6:	e7d6      	b.n	5fa6 <log_msg_hexdump_data_op+0x40>
    5ff8:	4601      	mov	r1, r0
    5ffa:	4630      	mov	r0, r6
    5ffc:	e7da      	b.n	5fb4 <log_msg_hexdump_data_op+0x4e>
		offset -= chunk_len;
    5ffe:	3c08      	subs	r4, #8
		while (offset >= chunk_len) {
    6000:	2c1b      	cmp	r4, #27
    6002:	d9dc      	bls.n	5fbe <log_msg_hexdump_data_op+0x58>
			cont = cont->next;
    6004:	f8d8 8000 	ldr.w	r8, [r8]
			offset -= chunk_len;
    6008:	3c1c      	subs	r4, #28
    600a:	e7f9      	b.n	6000 <log_msg_hexdump_data_op+0x9a>
    600c:	4601      	mov	r1, r0
    600e:	4630      	mov	r0, r6
    6010:	e7e5      	b.n	5fde <log_msg_hexdump_data_op+0x78>

00006012 <log_msg_get>:
	return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST);
    6012:	3004      	adds	r0, #4
    6014:	f3bf 8f5b 	dmb	ish
    6018:	e850 3f00 	ldrex	r3, [r0]
    601c:	3301      	adds	r3, #1
    601e:	e840 3200 	strex	r2, r3, [r0]
    6022:	2a00      	cmp	r2, #0
    6024:	d1f8      	bne.n	6018 <log_msg_get+0x6>
    6026:	f3bf 8f5b 	dmb	ish
}
    602a:	4770      	bx	lr

0000602c <log_msg_nargs_get>:
	return msg->hdr.params.std.nargs;
    602c:	7a40      	ldrb	r0, [r0, #9]
}
    602e:	0900      	lsrs	r0, r0, #4
    6030:	4770      	bx	lr

00006032 <log_msg_arg_get>:
	if (arg_idx >= msg->hdr.params.std.nargs) {
    6032:	7a43      	ldrb	r3, [r0, #9]
    6034:	ebb1 1f13 	cmp.w	r1, r3, lsr #4
    6038:	ea4f 1213 	mov.w	r2, r3, lsr #4
    603c:	d216      	bcs.n	606c <log_msg_arg_get+0x3a>
	if (msg->hdr.params.std.nargs <= LOG_MSG_NARGS_SINGLE_CHUNK) {
    603e:	2a03      	cmp	r2, #3
    6040:	d803      	bhi.n	604a <log_msg_arg_get+0x18>
		arg = msg->payload.single.args[arg_idx];
    6042:	eb00 0181 	add.w	r1, r0, r1, lsl #2
    6046:	6948      	ldr	r0, [r1, #20]
    6048:	4770      	bx	lr
	if (arg_idx < LOG_MSG_NARGS_HEAD_CHUNK) {
    604a:	2901      	cmp	r1, #1
    604c:	d803      	bhi.n	6056 <log_msg_arg_get+0x24>
		return msg->payload.ext.data.args[arg_idx];
    604e:	eb00 0181 	add.w	r1, r0, r1, lsl #2
    6052:	6988      	ldr	r0, [r1, #24]
    6054:	4770      	bx	lr
	cont = msg->payload.ext.next;
    6056:	6943      	ldr	r3, [r0, #20]
	arg_idx -= LOG_MSG_NARGS_HEAD_CHUNK;
    6058:	3902      	subs	r1, #2
	while (arg_idx >= ARGS_CONT_MSG) {
    605a:	2906      	cmp	r1, #6
    605c:	d803      	bhi.n	6066 <log_msg_arg_get+0x34>
	return cont->payload.args[arg_idx];
    605e:	eb03 0181 	add.w	r1, r3, r1, lsl #2
    6062:	6848      	ldr	r0, [r1, #4]
    6064:	4770      	bx	lr
		cont = cont->next;
    6066:	681b      	ldr	r3, [r3, #0]
		arg_idx -= ARGS_CONT_MSG;
    6068:	3907      	subs	r1, #7
		cont = cont->next;
    606a:	e7f6      	b.n	605a <log_msg_arg_get+0x28>
		return 0;
    606c:	2000      	movs	r0, #0
}
    606e:	4770      	bx	lr

00006070 <log_msg_put>:
{
    6070:	4603      	mov	r3, r0
	return __atomic_fetch_sub(target, value, __ATOMIC_SEQ_CST);
    6072:	1d02      	adds	r2, r0, #4
    6074:	f3bf 8f5b 	dmb	ish
    6078:	e852 1f00 	ldrex	r1, [r2]
    607c:	3901      	subs	r1, #1
    607e:	e842 1c00 	strex	ip, r1, [r2]
    6082:	f1bc 0f00 	cmp.w	ip, #0
    6086:	d1f7      	bne.n	6078 <log_msg_put+0x8>
    6088:	f3bf 8f5b 	dmb	ish
	if (msg->hdr.ref_cnt == 0) {
    608c:	685b      	ldr	r3, [r3, #4]
    608e:	b90b      	cbnz	r3, 6094 <log_msg_put+0x24>
		msg_free(msg);
    6090:	f7fb ba42 	b.w	1518 <msg_free>
}
    6094:	4770      	bx	lr

00006096 <log_msg_str_get>:
}
    6096:	6900      	ldr	r0, [r0, #16]
    6098:	4770      	bx	lr

0000609a <log_msg_hexdump_data_get>:

void log_msg_hexdump_data_get(struct log_msg *msg,
			      uint8_t *data,
			      size_t *length,
			      size_t offset)
{
    609a:	b513      	push	{r0, r1, r4, lr}
	log_msg_hexdump_data_op(msg, data, length, offset, false);
    609c:	2400      	movs	r4, #0
    609e:	9400      	str	r4, [sp, #0]
    60a0:	f7ff ff61 	bl	5f66 <log_msg_hexdump_data_op>
}
    60a4:	b002      	add	sp, #8
    60a6:	bd10      	pop	{r4, pc}

000060a8 <buffer_write>:
{
    60a8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    60aa:	4606      	mov	r6, r0
    60ac:	460d      	mov	r5, r1
    60ae:	4614      	mov	r4, r2
    60b0:	461f      	mov	r7, r3
		processed = outf(buf, len, ctx);
    60b2:	4621      	mov	r1, r4
    60b4:	4628      	mov	r0, r5
    60b6:	463a      	mov	r2, r7
    60b8:	47b0      	blx	r6
	} while (len != 0);
    60ba:	1a24      	subs	r4, r4, r0
		buf += processed;
    60bc:	4405      	add	r5, r0
	} while (len != 0);
    60be:	d1f8      	bne.n	60b2 <buffer_write+0xa>
}
    60c0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

000060c2 <std_print>:
{
    60c2:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    60c6:	b08e      	sub	sp, #56	; 0x38
    60c8:	af0e      	add	r7, sp, #56	; 0x38
    60ca:	4680      	mov	r8, r0
    60cc:	460d      	mov	r5, r1
	const char *str = log_msg_str_get(msg);
    60ce:	f7ff ffe2 	bl	6096 <log_msg_str_get>
    60d2:	4606      	mov	r6, r0
	uint32_t nargs = log_msg_nargs_get(msg);
    60d4:	4640      	mov	r0, r8
    60d6:	f7ff ffa9 	bl	602c <log_msg_nargs_get>
	log_arg_t *args = alloca(sizeof(log_arg_t)*nargs);
    60da:	0083      	lsls	r3, r0, #2
    60dc:	3307      	adds	r3, #7
    60de:	f023 0307 	bic.w	r3, r3, #7
    60e2:	ebad 0d03 	sub.w	sp, sp, r3
	uint32_t nargs = log_msg_nargs_get(msg);
    60e6:	4682      	mov	sl, r0
	log_arg_t *args = alloca(sizeof(log_arg_t)*nargs);
    60e8:	ac0e      	add	r4, sp, #56	; 0x38
	for (i = 0; i < nargs; i++) {
    60ea:	f04f 0900 	mov.w	r9, #0
    60ee:	45d1      	cmp	r9, sl
    60f0:	d116      	bne.n	6120 <std_print+0x5e>
	switch (log_msg_nargs_get(msg)) {
    60f2:	4640      	mov	r0, r8
    60f4:	f7ff ff9a 	bl	602c <log_msg_nargs_get>
    60f8:	280f      	cmp	r0, #15
    60fa:	d81e      	bhi.n	613a <std_print+0x78>
    60fc:	e8df f010 	tbh	[pc, r0, lsl #1]
    6100:	00200019 	.word	0x00200019
    6104:	002d0026 	.word	0x002d0026
    6108:	00410036 	.word	0x00410036
    610c:	005d004e 	.word	0x005d004e
    6110:	0081006e 	.word	0x0081006e
    6114:	00ad0096 	.word	0x00ad0096
    6118:	00e100c6 	.word	0x00e100c6
    611c:	011d00fe 	.word	0x011d00fe
		args[i] = log_msg_arg_get(msg, i);
    6120:	4649      	mov	r1, r9
    6122:	4640      	mov	r0, r8
    6124:	f7ff ff85 	bl	6032 <log_msg_arg_get>
    6128:	f844 0029 	str.w	r0, [r4, r9, lsl #2]
	for (i = 0; i < nargs; i++) {
    612c:	f109 0901 	add.w	r9, r9, #1
    6130:	e7dd      	b.n	60ee <std_print+0x2c>
		print_formatted(output, str);
    6132:	4631      	mov	r1, r6
    6134:	4628      	mov	r0, r5
    6136:	f7fb fa2d 	bl	1594 <print_formatted>
}
    613a:	46bd      	mov	sp, r7
    613c:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		print_formatted(output, str, args[0]);
    6140:	6822      	ldr	r2, [r4, #0]
    6142:	4631      	mov	r1, r6
    6144:	4628      	mov	r0, r5
    6146:	f7fb fa25 	bl	1594 <print_formatted>
		break;
    614a:	e7f6      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1]);
    614c:	e9d4 2300 	ldrd	r2, r3, [r4]
    6150:	4631      	mov	r1, r6
    6152:	4628      	mov	r0, r5
    6154:	f7fb fa1e 	bl	1594 <print_formatted>
		break;
    6158:	e7ef      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2]);
    615a:	68a3      	ldr	r3, [r4, #8]
    615c:	9300      	str	r3, [sp, #0]
    615e:	e9d4 2300 	ldrd	r2, r3, [r4]
    6162:	4631      	mov	r1, r6
    6164:	4628      	mov	r0, r5
    6166:	f7fb fa15 	bl	1594 <print_formatted>
		break;
    616a:	e7e6      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    616c:	68e3      	ldr	r3, [r4, #12]
    616e:	9301      	str	r3, [sp, #4]
    6170:	68a3      	ldr	r3, [r4, #8]
    6172:	9300      	str	r3, [sp, #0]
    6174:	e9d4 2300 	ldrd	r2, r3, [r4]
    6178:	4631      	mov	r1, r6
    617a:	4628      	mov	r0, r5
    617c:	f7fb fa0a 	bl	1594 <print_formatted>
		break;
    6180:	e7db      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    6182:	6923      	ldr	r3, [r4, #16]
    6184:	9302      	str	r3, [sp, #8]
    6186:	68e3      	ldr	r3, [r4, #12]
    6188:	9301      	str	r3, [sp, #4]
    618a:	68a3      	ldr	r3, [r4, #8]
    618c:	9300      	str	r3, [sp, #0]
    618e:	e9d4 2300 	ldrd	r2, r3, [r4]
    6192:	4631      	mov	r1, r6
    6194:	4628      	mov	r0, r5
    6196:	f7fb f9fd 	bl	1594 <print_formatted>
		break;
    619a:	e7ce      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    619c:	6963      	ldr	r3, [r4, #20]
    619e:	9303      	str	r3, [sp, #12]
    61a0:	6923      	ldr	r3, [r4, #16]
    61a2:	9302      	str	r3, [sp, #8]
    61a4:	68e3      	ldr	r3, [r4, #12]
    61a6:	9301      	str	r3, [sp, #4]
    61a8:	68a3      	ldr	r3, [r4, #8]
    61aa:	9300      	str	r3, [sp, #0]
    61ac:	e9d4 2300 	ldrd	r2, r3, [r4]
    61b0:	4631      	mov	r1, r6
    61b2:	4628      	mov	r0, r5
    61b4:	f7fb f9ee 	bl	1594 <print_formatted>
		break;
    61b8:	e7bf      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    61ba:	69a3      	ldr	r3, [r4, #24]
    61bc:	9304      	str	r3, [sp, #16]
    61be:	6963      	ldr	r3, [r4, #20]
    61c0:	9303      	str	r3, [sp, #12]
    61c2:	6923      	ldr	r3, [r4, #16]
    61c4:	9302      	str	r3, [sp, #8]
    61c6:	68e3      	ldr	r3, [r4, #12]
    61c8:	9301      	str	r3, [sp, #4]
    61ca:	68a3      	ldr	r3, [r4, #8]
    61cc:	9300      	str	r3, [sp, #0]
    61ce:	e9d4 2300 	ldrd	r2, r3, [r4]
    61d2:	4631      	mov	r1, r6
    61d4:	4628      	mov	r0, r5
    61d6:	f7fb f9dd 	bl	1594 <print_formatted>
		break;
    61da:	e7ae      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    61dc:	69e3      	ldr	r3, [r4, #28]
    61de:	9305      	str	r3, [sp, #20]
    61e0:	69a3      	ldr	r3, [r4, #24]
    61e2:	9304      	str	r3, [sp, #16]
    61e4:	6963      	ldr	r3, [r4, #20]
    61e6:	9303      	str	r3, [sp, #12]
    61e8:	6923      	ldr	r3, [r4, #16]
    61ea:	9302      	str	r3, [sp, #8]
    61ec:	68e3      	ldr	r3, [r4, #12]
    61ee:	9301      	str	r3, [sp, #4]
    61f0:	68a3      	ldr	r3, [r4, #8]
    61f2:	9300      	str	r3, [sp, #0]
    61f4:	e9d4 2300 	ldrd	r2, r3, [r4]
    61f8:	4631      	mov	r1, r6
    61fa:	4628      	mov	r0, r5
    61fc:	f7fb f9ca 	bl	1594 <print_formatted>
		break;
    6200:	e79b      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    6202:	6a23      	ldr	r3, [r4, #32]
    6204:	9306      	str	r3, [sp, #24]
    6206:	69e3      	ldr	r3, [r4, #28]
    6208:	9305      	str	r3, [sp, #20]
    620a:	69a3      	ldr	r3, [r4, #24]
    620c:	9304      	str	r3, [sp, #16]
    620e:	6963      	ldr	r3, [r4, #20]
    6210:	9303      	str	r3, [sp, #12]
    6212:	6923      	ldr	r3, [r4, #16]
    6214:	9302      	str	r3, [sp, #8]
    6216:	68e3      	ldr	r3, [r4, #12]
    6218:	9301      	str	r3, [sp, #4]
    621a:	68a3      	ldr	r3, [r4, #8]
    621c:	9300      	str	r3, [sp, #0]
    621e:	e9d4 2300 	ldrd	r2, r3, [r4]
    6222:	4631      	mov	r1, r6
    6224:	4628      	mov	r0, r5
    6226:	f7fb f9b5 	bl	1594 <print_formatted>
		break;
    622a:	e786      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    622c:	6a63      	ldr	r3, [r4, #36]	; 0x24
    622e:	9307      	str	r3, [sp, #28]
    6230:	6a23      	ldr	r3, [r4, #32]
    6232:	9306      	str	r3, [sp, #24]
    6234:	69e3      	ldr	r3, [r4, #28]
    6236:	9305      	str	r3, [sp, #20]
    6238:	69a3      	ldr	r3, [r4, #24]
    623a:	9304      	str	r3, [sp, #16]
    623c:	6963      	ldr	r3, [r4, #20]
    623e:	9303      	str	r3, [sp, #12]
    6240:	6923      	ldr	r3, [r4, #16]
    6242:	9302      	str	r3, [sp, #8]
    6244:	68e3      	ldr	r3, [r4, #12]
    6246:	9301      	str	r3, [sp, #4]
    6248:	68a3      	ldr	r3, [r4, #8]
    624a:	9300      	str	r3, [sp, #0]
    624c:	e9d4 2300 	ldrd	r2, r3, [r4]
    6250:	4631      	mov	r1, r6
    6252:	4628      	mov	r0, r5
    6254:	f7fb f99e 	bl	1594 <print_formatted>
		break;
    6258:	e76f      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    625a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    625c:	9308      	str	r3, [sp, #32]
    625e:	6a63      	ldr	r3, [r4, #36]	; 0x24
    6260:	9307      	str	r3, [sp, #28]
    6262:	6a23      	ldr	r3, [r4, #32]
    6264:	9306      	str	r3, [sp, #24]
    6266:	69e3      	ldr	r3, [r4, #28]
    6268:	9305      	str	r3, [sp, #20]
    626a:	69a3      	ldr	r3, [r4, #24]
    626c:	9304      	str	r3, [sp, #16]
    626e:	6963      	ldr	r3, [r4, #20]
    6270:	9303      	str	r3, [sp, #12]
    6272:	6923      	ldr	r3, [r4, #16]
    6274:	9302      	str	r3, [sp, #8]
    6276:	68e3      	ldr	r3, [r4, #12]
    6278:	9301      	str	r3, [sp, #4]
    627a:	68a3      	ldr	r3, [r4, #8]
    627c:	9300      	str	r3, [sp, #0]
    627e:	e9d4 2300 	ldrd	r2, r3, [r4]
    6282:	4631      	mov	r1, r6
    6284:	4628      	mov	r0, r5
    6286:	f7fb f985 	bl	1594 <print_formatted>
		break;
    628a:	e756      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    628c:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    628e:	9309      	str	r3, [sp, #36]	; 0x24
    6290:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    6292:	9308      	str	r3, [sp, #32]
    6294:	6a63      	ldr	r3, [r4, #36]	; 0x24
    6296:	9307      	str	r3, [sp, #28]
    6298:	6a23      	ldr	r3, [r4, #32]
    629a:	9306      	str	r3, [sp, #24]
    629c:	69e3      	ldr	r3, [r4, #28]
    629e:	9305      	str	r3, [sp, #20]
    62a0:	69a3      	ldr	r3, [r4, #24]
    62a2:	9304      	str	r3, [sp, #16]
    62a4:	6963      	ldr	r3, [r4, #20]
    62a6:	9303      	str	r3, [sp, #12]
    62a8:	6923      	ldr	r3, [r4, #16]
    62aa:	9302      	str	r3, [sp, #8]
    62ac:	68e3      	ldr	r3, [r4, #12]
    62ae:	9301      	str	r3, [sp, #4]
    62b0:	68a3      	ldr	r3, [r4, #8]
    62b2:	9300      	str	r3, [sp, #0]
    62b4:	e9d4 2300 	ldrd	r2, r3, [r4]
    62b8:	4631      	mov	r1, r6
    62ba:	4628      	mov	r0, r5
    62bc:	f7fb f96a 	bl	1594 <print_formatted>
		break;
    62c0:	e73b      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    62c2:	6b23      	ldr	r3, [r4, #48]	; 0x30
    62c4:	930a      	str	r3, [sp, #40]	; 0x28
    62c6:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    62c8:	9309      	str	r3, [sp, #36]	; 0x24
    62ca:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    62cc:	9308      	str	r3, [sp, #32]
    62ce:	6a63      	ldr	r3, [r4, #36]	; 0x24
    62d0:	9307      	str	r3, [sp, #28]
    62d2:	6a23      	ldr	r3, [r4, #32]
    62d4:	9306      	str	r3, [sp, #24]
    62d6:	69e3      	ldr	r3, [r4, #28]
    62d8:	9305      	str	r3, [sp, #20]
    62da:	69a3      	ldr	r3, [r4, #24]
    62dc:	9304      	str	r3, [sp, #16]
    62de:	6963      	ldr	r3, [r4, #20]
    62e0:	9303      	str	r3, [sp, #12]
    62e2:	6923      	ldr	r3, [r4, #16]
    62e4:	9302      	str	r3, [sp, #8]
    62e6:	68e3      	ldr	r3, [r4, #12]
    62e8:	9301      	str	r3, [sp, #4]
    62ea:	68a3      	ldr	r3, [r4, #8]
    62ec:	9300      	str	r3, [sp, #0]
    62ee:	e9d4 2300 	ldrd	r2, r3, [r4]
    62f2:	4631      	mov	r1, r6
    62f4:	4628      	mov	r0, r5
    62f6:	f7fb f94d 	bl	1594 <print_formatted>
		break;
    62fa:	e71e      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    62fc:	6b63      	ldr	r3, [r4, #52]	; 0x34
    62fe:	930b      	str	r3, [sp, #44]	; 0x2c
    6300:	6b23      	ldr	r3, [r4, #48]	; 0x30
    6302:	930a      	str	r3, [sp, #40]	; 0x28
    6304:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    6306:	9309      	str	r3, [sp, #36]	; 0x24
    6308:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    630a:	9308      	str	r3, [sp, #32]
    630c:	6a63      	ldr	r3, [r4, #36]	; 0x24
    630e:	9307      	str	r3, [sp, #28]
    6310:	6a23      	ldr	r3, [r4, #32]
    6312:	9306      	str	r3, [sp, #24]
    6314:	69e3      	ldr	r3, [r4, #28]
    6316:	9305      	str	r3, [sp, #20]
    6318:	69a3      	ldr	r3, [r4, #24]
    631a:	9304      	str	r3, [sp, #16]
    631c:	6963      	ldr	r3, [r4, #20]
    631e:	9303      	str	r3, [sp, #12]
    6320:	6923      	ldr	r3, [r4, #16]
    6322:	9302      	str	r3, [sp, #8]
    6324:	68e3      	ldr	r3, [r4, #12]
    6326:	9301      	str	r3, [sp, #4]
    6328:	68a3      	ldr	r3, [r4, #8]
    632a:	9300      	str	r3, [sp, #0]
    632c:	e9d4 2300 	ldrd	r2, r3, [r4]
    6330:	4631      	mov	r1, r6
    6332:	4628      	mov	r0, r5
    6334:	f7fb f92e 	bl	1594 <print_formatted>
		break;
    6338:	e6ff      	b.n	613a <std_print+0x78>
		print_formatted(output, str, args[0], args[1], args[2],
    633a:	6ba3      	ldr	r3, [r4, #56]	; 0x38
    633c:	930c      	str	r3, [sp, #48]	; 0x30
    633e:	6b63      	ldr	r3, [r4, #52]	; 0x34
    6340:	930b      	str	r3, [sp, #44]	; 0x2c
    6342:	6b23      	ldr	r3, [r4, #48]	; 0x30
    6344:	930a      	str	r3, [sp, #40]	; 0x28
    6346:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    6348:	9309      	str	r3, [sp, #36]	; 0x24
    634a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    634c:	9308      	str	r3, [sp, #32]
    634e:	6a63      	ldr	r3, [r4, #36]	; 0x24
    6350:	9307      	str	r3, [sp, #28]
    6352:	6a23      	ldr	r3, [r4, #32]
    6354:	9306      	str	r3, [sp, #24]
    6356:	69e3      	ldr	r3, [r4, #28]
    6358:	9305      	str	r3, [sp, #20]
    635a:	69a3      	ldr	r3, [r4, #24]
    635c:	9304      	str	r3, [sp, #16]
    635e:	6963      	ldr	r3, [r4, #20]
    6360:	9303      	str	r3, [sp, #12]
    6362:	6923      	ldr	r3, [r4, #16]
    6364:	9302      	str	r3, [sp, #8]
    6366:	68e3      	ldr	r3, [r4, #12]
    6368:	9301      	str	r3, [sp, #4]
    636a:	68a3      	ldr	r3, [r4, #8]
    636c:	9300      	str	r3, [sp, #0]
    636e:	e9d4 2300 	ldrd	r2, r3, [r4]
    6372:	4631      	mov	r1, r6
    6374:	4628      	mov	r0, r5
    6376:	f7fb f90d 	bl	1594 <print_formatted>
}
    637a:	e6de      	b.n	613a <std_print+0x78>

0000637c <log_output_flush>:
		     output->control_block->offset,
    637c:	6842      	ldr	r2, [r0, #4]
	buffer_write(output->func, output->buf,
    637e:	6881      	ldr	r1, [r0, #8]
{
    6380:	b510      	push	{r4, lr}
    6382:	4604      	mov	r4, r0
	buffer_write(output->func, output->buf,
    6384:	e9d2 2300 	ldrd	r2, r3, [r2]
    6388:	6800      	ldr	r0, [r0, #0]
    638a:	f7ff fe8d 	bl	60a8 <buffer_write>
	output->control_block->offset = 0;
    638e:	6863      	ldr	r3, [r4, #4]
    6390:	2200      	movs	r2, #0
    6392:	601a      	str	r2, [r3, #0]
}
    6394:	bd10      	pop	{r4, pc}

00006396 <out_func>:
{
    6396:	b538      	push	{r3, r4, r5, lr}
	if (out_ctx->control_block->offset == out_ctx->size) {
    6398:	684b      	ldr	r3, [r1, #4]
    639a:	681a      	ldr	r2, [r3, #0]
    639c:	68cb      	ldr	r3, [r1, #12]
    639e:	429a      	cmp	r2, r3
{
    63a0:	4605      	mov	r5, r0
    63a2:	460c      	mov	r4, r1
	if (out_ctx->control_block->offset == out_ctx->size) {
    63a4:	d102      	bne.n	63ac <out_func+0x16>
		log_output_flush(out_ctx);
    63a6:	4608      	mov	r0, r1
    63a8:	f7ff ffe8 	bl	637c <log_output_flush>
	return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST);
    63ac:	6863      	ldr	r3, [r4, #4]
    63ae:	f3bf 8f5b 	dmb	ish
    63b2:	e853 2f00 	ldrex	r2, [r3]
    63b6:	1c51      	adds	r1, r2, #1
    63b8:	e843 1000 	strex	r0, r1, [r3]
    63bc:	2800      	cmp	r0, #0
    63be:	d1f8      	bne.n	63b2 <out_func+0x1c>
    63c0:	f3bf 8f5b 	dmb	ish
	out_ctx->buf[idx] = (uint8_t)c;
    63c4:	68a3      	ldr	r3, [r4, #8]
    63c6:	549d      	strb	r5, [r3, r2]
}
    63c8:	2000      	movs	r0, #0
    63ca:	bd38      	pop	{r3, r4, r5, pc}

000063cc <pm_policy_next_state>:
			return pm_min_residency[i];
		}
	}

	LOG_DBG("No suitable power state found!");
	return (struct pm_state_info){PM_STATE_ACTIVE, 0, 0};
    63cc:	2200      	movs	r2, #0
    63ce:	e9c0 2200 	strd	r2, r2, [r0]
    63d2:	6082      	str	r2, [r0, #8]
}
    63d4:	4770      	bx	lr

000063d6 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    63d6:	6902      	ldr	r2, [r0, #16]
    63d8:	b2cb      	uxtb	r3, r1
    63da:	210c      	movs	r1, #12
    63dc:	fb03 2101 	mla	r1, r3, r1, r2
    63e0:	6c88      	ldr	r0, [r1, #72]	; 0x48
}
    63e2:	f000 0007 	and.w	r0, r0, #7
    63e6:	4770      	bx	lr

000063e8 <set_off_state>:
	__asm__ volatile(
    63e8:	f04f 0320 	mov.w	r3, #32
    63ec:	f3ef 8211 	mrs	r2, BASEPRI
    63f0:	f383 8811 	msr	BASEPRI, r3
    63f4:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    63f8:	6803      	ldr	r3, [r0, #0]
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    63fa:	f013 03c0 	ands.w	r3, r3, #192	; 0xc0
    63fe:	d001      	beq.n	6404 <set_off_state+0x1c>
    6400:	428b      	cmp	r3, r1
    6402:	d107      	bne.n	6414 <set_off_state+0x2c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    6404:	2301      	movs	r3, #1
    6406:	6003      	str	r3, [r0, #0]
	int err = 0;
    6408:	2000      	movs	r0, #0
	__asm__ volatile(
    640a:	f382 8811 	msr	BASEPRI, r2
    640e:	f3bf 8f6f 	isb	sy
}
    6412:	4770      	bx	lr
		err = -EPERM;
    6414:	f04f 30ff 	mov.w	r0, #4294967295
    6418:	e7f7      	b.n	640a <set_off_state+0x22>

0000641a <set_starting_state>:
{
    641a:	b510      	push	{r4, lr}
	__asm__ volatile(
    641c:	f04f 0320 	mov.w	r3, #32
    6420:	f3ef 8211 	mrs	r2, BASEPRI
    6424:	f383 8811 	msr	BASEPRI, r3
    6428:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    642c:	6803      	ldr	r3, [r0, #0]
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    642e:	f003 0407 	and.w	r4, r3, #7
    6432:	2c01      	cmp	r4, #1
    6434:	d106      	bne.n	6444 <set_starting_state+0x2a>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    6436:	6001      	str	r1, [r0, #0]
	int err = 0;
    6438:	2000      	movs	r0, #0
	__asm__ volatile(
    643a:	f382 8811 	msr	BASEPRI, r2
    643e:	f3bf 8f6f 	isb	sy
}
    6442:	bd10      	pop	{r4, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    6444:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
	} else if (current_ctx != ctx) {
    6448:	428b      	cmp	r3, r1
		err = -EALREADY;
    644a:	bf14      	ite	ne
    644c:	f04f 30ff 	movne.w	r0, #4294967295
    6450:	f06f 0077 	mvneq.w	r0, #119	; 0x77
    6454:	e7f1      	b.n	643a <set_starting_state+0x20>

00006456 <set_on_state>:
	__asm__ volatile(
    6456:	f04f 0320 	mov.w	r3, #32
    645a:	f3ef 8211 	mrs	r2, BASEPRI
    645e:	f383 8811 	msr	BASEPRI, r3
    6462:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    6466:	6803      	ldr	r3, [r0, #0]
    6468:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    646c:	f043 0302 	orr.w	r3, r3, #2
    6470:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    6472:	f382 8811 	msr	BASEPRI, r2
    6476:	f3bf 8f6f 	isb	sy
}
    647a:	4770      	bx	lr

0000647c <onoff_started_callback>:
	return &data->mgr[type];
    647c:	6900      	ldr	r0, [r0, #16]
    647e:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    6480:	eb00 1043 	add.w	r0, r0, r3, lsl #5
    6484:	2100      	movs	r1, #0
    6486:	4710      	bx	r2

00006488 <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    6488:	2000      	movs	r0, #0
    648a:	f7fd b98f 	b.w	37ac <nrfx_clock_start>

0000648e <blocking_start_callback>:
{
    648e:	4610      	mov	r0, r2
	z_impl_k_sem_give(sem);
    6490:	f7fd be88 	b.w	41a4 <z_impl_k_sem_give>

00006494 <lfclk_stop>:
{
    6494:	b508      	push	{r3, lr}
		z_nrf_clock_calibration_lfclk_stopped();
    6496:	f7fb fe51 	bl	213c <z_nrf_clock_calibration_lfclk_stopped>
}
    649a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    649e:	2000      	movs	r0, #0
    64a0:	f7fd b9a2 	b.w	37e8 <nrfx_clock_stop>

000064a4 <api_stop>:
{
    64a4:	b538      	push	{r3, r4, r5, lr}
    64a6:	b2c9      	uxtb	r1, r1
	err = set_off_state(&subdata->flags, ctx);
    64a8:	240c      	movs	r4, #12
    64aa:	434c      	muls	r4, r1
{
    64ac:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
    64ae:	6900      	ldr	r0, [r0, #16]
    64b0:	f104 0348 	add.w	r3, r4, #72	; 0x48
    64b4:	2180      	movs	r1, #128	; 0x80
    64b6:	4418      	add	r0, r3
    64b8:	f7ff ff96 	bl	63e8 <set_off_state>
	if (err < 0) {
    64bc:	2800      	cmp	r0, #0
    64be:	db04      	blt.n	64ca <api_stop+0x26>
	get_sub_config(dev, type)->stop();
    64c0:	6869      	ldr	r1, [r5, #4]
    64c2:	440c      	add	r4, r1
    64c4:	6863      	ldr	r3, [r4, #4]
    64c6:	4798      	blx	r3
	return 0;
    64c8:	2000      	movs	r0, #0
}
    64ca:	bd38      	pop	{r3, r4, r5, pc}

000064cc <api_start>:
{
    64cc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    64d0:	b2c9      	uxtb	r1, r1
	err = set_starting_state(&subdata->flags, ctx);
    64d2:	240c      	movs	r4, #12
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    64d4:	6905      	ldr	r5, [r0, #16]
	err = set_starting_state(&subdata->flags, ctx);
    64d6:	434c      	muls	r4, r1
{
    64d8:	4606      	mov	r6, r0
	err = set_starting_state(&subdata->flags, ctx);
    64da:	f104 0048 	add.w	r0, r4, #72	; 0x48
    64de:	2180      	movs	r1, #128	; 0x80
    64e0:	4428      	add	r0, r5
{
    64e2:	4690      	mov	r8, r2
    64e4:	461f      	mov	r7, r3
	err = set_starting_state(&subdata->flags, ctx);
    64e6:	f7ff ff98 	bl	641a <set_starting_state>
	if (err < 0) {
    64ea:	2800      	cmp	r0, #0
    64ec:	db06      	blt.n	64fc <api_start+0x30>
	subdata->cb = cb;
    64ee:	4425      	add	r5, r4
	subdata->user_data = user_data;
    64f0:	e9c5 8710 	strd	r8, r7, [r5, #64]	; 0x40
	 get_sub_config(dev, type)->start();
    64f4:	6873      	ldr	r3, [r6, #4]
    64f6:	591b      	ldr	r3, [r3, r4]
    64f8:	4798      	blx	r3
	return 0;
    64fa:	2000      	movs	r0, #0
}
    64fc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00006500 <sys_clock_isr>:
/* Weak-linked noop defaults for optional driver interfaces*/

void __weak sys_clock_isr(void *arg)
{
	__ASSERT_NO_MSG(false);
}
    6500:	4770      	bx	lr

00006502 <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
    6502:	4770      	bx	lr

00006504 <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    6504:	2100      	movs	r1, #0
    6506:	2001      	movs	r0, #1
    6508:	f7fb bfb2 	b.w	2470 <z_arm_fatal_error>

0000650c <z_do_kernel_oops>:
 *   fault handler will executed insted of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    650c:	4601      	mov	r1, r0
	}

#endif /* CONFIG_USERSPACE */

#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	z_arm_fatal_error(reason, esf);
    650e:	6800      	ldr	r0, [r0, #0]
    6510:	f7fb bfae 	b.w	2470 <z_arm_fatal_error>

00006514 <z_arm_nmi>:
 *
 * @return N/A
 */

void z_arm_nmi(void)
{
    6514:	b508      	push	{r3, lr}
	handler();
    6516:	f7fc f851 	bl	25bc <z_SysNmiOnReset>
	z_arm_int_exit();
}
    651a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    651e:	f7fc b8a5 	b.w	266c <z_arm_exc_exit>

00006522 <malloc_prepare>:
}
    6522:	2000      	movs	r0, #0
    6524:	4770      	bx	lr

00006526 <_stdout_hook_default>:
}
    6526:	f04f 30ff 	mov.w	r0, #4294967295
    652a:	4770      	bx	lr

0000652c <_stdin_hook_default>:
}
    652c:	2000      	movs	r0, #0
    652e:	4770      	bx	lr

00006530 <_read>:
{
    6530:	4608      	mov	r0, r1
	return z_impl_zephyr_read_stdin(buf, nbytes);
    6532:	4611      	mov	r1, r2
    6534:	f7fc bbce 	b.w	2cd4 <z_impl_zephyr_read_stdin>

00006538 <_write>:
{
    6538:	4608      	mov	r0, r1
	return z_impl_zephyr_write_stdout(buf, nbytes);
    653a:	4611      	mov	r1, r2
    653c:	f7fc bbde 	b.w	2cfc <z_impl_zephyr_write_stdout>

00006540 <_close>:
    6540:	f04f 30ff 	mov.w	r0, #4294967295
    6544:	4770      	bx	lr

00006546 <_lseek>:
}
    6546:	2000      	movs	r0, #0
    6548:	4770      	bx	lr

0000654a <_isatty>:
}
    654a:	2802      	cmp	r0, #2
    654c:	bfcc      	ite	gt
    654e:	2000      	movgt	r0, #0
    6550:	2001      	movle	r0, #1
    6552:	4770      	bx	lr

00006554 <_fstat>:
	st->st_mode = S_IFCHR;
    6554:	f44f 5300 	mov.w	r3, #8192	; 0x2000
    6558:	604b      	str	r3, [r1, #4]
}
    655a:	2000      	movs	r0, #0
    655c:	4770      	bx	lr

0000655e <pm_power_state_set>:
#include <logging/log.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);

/* Invoke Low Power/System Off specific Tasks */
__weak void pm_power_state_set(struct pm_state_info info)
{
    655e:	b084      	sub	sp, #16
    6560:	ab04      	add	r3, sp, #16
    6562:	e903 0007 	stmdb	r3, {r0, r1, r2}
	switch (info.state) {
    6566:	f89d 3004 	ldrb.w	r3, [sp, #4]
    656a:	2b06      	cmp	r3, #6
    656c:	d108      	bne.n	6580 <pm_power_state_set+0x22>
    p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
    656e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    6572:	2201      	movs	r2, #1
    6574:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  __ASM volatile ("dsb 0xF":::"memory");
    6578:	f3bf 8f4f 	dsb	sy
        __WFE();
    657c:	bf20      	wfe
    while (true)
    657e:	e7fd      	b.n	657c <pm_power_state_set+0x1e>
		break;
	default:
		LOG_DBG("Unsupported power state %u", info.state);
		break;
	}
}
    6580:	b004      	add	sp, #16
    6582:	4770      	bx	lr

00006584 <pm_power_state_exit_post_ops>:

/* Handle SOC specific activity after Low Power Mode Exit */
__weak void pm_power_state_exit_post_ops(struct pm_state_info info)
{
    6584:	b084      	sub	sp, #16
    6586:	ab04      	add	r3, sp, #16
    6588:	e903 0007 	stmdb	r3, {r0, r1, r2}
    658c:	2300      	movs	r3, #0
    658e:	f383 8811 	msr	BASEPRI, r3
    6592:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
    6596:	b004      	add	sp, #16
    6598:	4770      	bx	lr

0000659a <gpio_fire_callbacks>:
 * @param pins The actual pin mask that triggered the interrupt
 */
static inline void gpio_fire_callbacks(sys_slist_t *list,
					const struct device *port,
					uint32_t pins)
{
    659a:	b570      	push	{r4, r5, r6, lr}
    659c:	460e      	mov	r6, r1
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    659e:	6801      	ldr	r1, [r0, #0]
{
    65a0:	4615      	mov	r5, r2
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    65a2:	b189      	cbz	r1, 65c8 <gpio_fire_callbacks+0x2e>
	return node->next;
    65a4:	680c      	ldr	r4, [r1, #0]
    65a6:	2c00      	cmp	r4, #0
    65a8:	bf38      	it	cc
    65aa:	2400      	movcc	r4, #0
		if (cb->pin_mask & pins) {
    65ac:	688a      	ldr	r2, [r1, #8]
    65ae:	402a      	ands	r2, r5
    65b0:	d002      	beq.n	65b8 <gpio_fire_callbacks+0x1e>
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    65b2:	684b      	ldr	r3, [r1, #4]
    65b4:	4630      	mov	r0, r6
    65b6:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    65b8:	b134      	cbz	r4, 65c8 <gpio_fire_callbacks+0x2e>
    65ba:	6823      	ldr	r3, [r4, #0]
    65bc:	2b00      	cmp	r3, #0
    65be:	bf38      	it	cc
    65c0:	2300      	movcc	r3, #0
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    65c2:	4621      	mov	r1, r4
    65c4:	461c      	mov	r4, r3
    65c6:	e7f1      	b.n	65ac <gpio_fire_callbacks+0x12>
		}
	}
}
    65c8:	bd70      	pop	{r4, r5, r6, pc}

000065ca <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    65ca:	6843      	ldr	r3, [r0, #4]
    65cc:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    65ce:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    65d2:	600b      	str	r3, [r1, #0]
}
    65d4:	2000      	movs	r0, #0
    65d6:	4770      	bx	lr

000065d8 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    65d8:	6843      	ldr	r3, [r0, #4]
    65da:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
    65dc:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
    65e0:	4042      	eors	r2, r0
    65e2:	400a      	ands	r2, r1
    65e4:	4042      	eors	r2, r0
    p_reg->OUT = value;
    65e6:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
}
    65ea:	2000      	movs	r0, #0
    65ec:	4770      	bx	lr

000065ee <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    65ee:	6843      	ldr	r3, [r0, #4]
    65f0:	685b      	ldr	r3, [r3, #4]
}
    65f2:	2000      	movs	r0, #0
    p_reg->OUTSET = set_mask;
    65f4:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
    65f8:	4770      	bx	lr

000065fa <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    65fa:	6843      	ldr	r3, [r0, #4]
    65fc:	685b      	ldr	r3, [r3, #4]
}
    65fe:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    6600:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
    6604:	4770      	bx	lr

00006606 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6606:	6843      	ldr	r3, [r0, #4]
    6608:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    660a:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value ^ mask);
    660e:	404b      	eors	r3, r1
    p_reg->OUT = value;
    6610:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
}
    6614:	2000      	movs	r0, #0
    6616:	4770      	bx	lr

00006618 <gpio_nrfx_manage_callback>:
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    6618:	6903      	ldr	r3, [r0, #16]
Z_GENLIST_IS_EMPTY(slist)
    661a:	6858      	ldr	r0, [r3, #4]
{
    661c:	b530      	push	{r4, r5, lr}
	if (!sys_slist_is_empty(callbacks)) {
    661e:	b158      	cbz	r0, 6638 <gpio_nrfx_manage_callback+0x20>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    6620:	2400      	movs	r4, #0
    6622:	4281      	cmp	r1, r0
    6624:	d113      	bne.n	664e <gpio_nrfx_manage_callback+0x36>
Z_GENLIST_REMOVE(slist, snode)
    6626:	6808      	ldr	r0, [r1, #0]
    6628:	b95c      	cbnz	r4, 6642 <gpio_nrfx_manage_callback+0x2a>
    662a:	689c      	ldr	r4, [r3, #8]
	list->head = node;
    662c:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    662e:	42a1      	cmp	r1, r4
    6630:	d100      	bne.n	6634 <gpio_nrfx_manage_callback+0x1c>
	list->tail = node;
    6632:	6098      	str	r0, [r3, #8]
	parent->next = child;
    6634:	2000      	movs	r0, #0
    6636:	6008      	str	r0, [r1, #0]
	if (set) {
    6638:	b972      	cbnz	r2, 6658 <gpio_nrfx_manage_callback+0x40>
	return 0;
    663a:	2000      	movs	r0, #0
}
    663c:	bd30      	pop	{r4, r5, pc}
    663e:	4628      	mov	r0, r5
    6640:	e7ef      	b.n	6622 <gpio_nrfx_manage_callback+0xa>
    6642:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
    6644:	6898      	ldr	r0, [r3, #8]
    6646:	4281      	cmp	r1, r0
	list->tail = node;
    6648:	bf08      	it	eq
    664a:	609c      	streq	r4, [r3, #8]
}
    664c:	e7f2      	b.n	6634 <gpio_nrfx_manage_callback+0x1c>
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    664e:	6805      	ldr	r5, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    6650:	4604      	mov	r4, r0
    6652:	2d00      	cmp	r5, #0
    6654:	d1f3      	bne.n	663e <gpio_nrfx_manage_callback+0x26>
			if (!set) {
    6656:	b13a      	cbz	r2, 6668 <gpio_nrfx_manage_callback+0x50>
Z_GENLIST_PREPEND(slist, snode)
    6658:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
    665a:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
    665c:	6898      	ldr	r0, [r3, #8]
	list->head = node;
    665e:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    6660:	2800      	cmp	r0, #0
    6662:	d1ea      	bne.n	663a <gpio_nrfx_manage_callback+0x22>
	list->tail = node;
    6664:	6099      	str	r1, [r3, #8]
}
    6666:	e7e9      	b.n	663c <gpio_nrfx_manage_callback+0x24>
				return -EINVAL;
    6668:	f06f 0015 	mvn.w	r0, #21
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    666c:	e7e6      	b.n	663c <gpio_nrfx_manage_callback+0x24>

0000666e <cfg_level_pins>:
{
    666e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	const struct gpio_nrfx_data *data = get_port_data(port);
    6672:	6907      	ldr	r7, [r0, #16]
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
    6674:	f8d0 8004 	ldr.w	r8, [r0, #4]
	uint32_t out = data->pin_int_en;
    6678:	68fc      	ldr	r4, [r7, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    667a:	e9d7 3205 	ldrd	r3, r2, [r7, #20]
    667e:	4313      	orrs	r3, r2
    6680:	ea24 0403 	bic.w	r4, r4, r3
	uint32_t bit = 1U << pin;
    6684:	2601      	movs	r6, #1
	uint32_t pin = 0U;
    6686:	2500      	movs	r5, #0
	while (level_pins) {
    6688:	b90c      	cbnz	r4, 668e <cfg_level_pins+0x20>
}
    668a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		if (level_pins & bit) {
    668e:	4226      	tst	r6, r4
    6690:	d010      	beq.n	66b4 <cfg_level_pins+0x46>
	if ((BIT(pin) & data->int_active_level) != 0U) {
    6692:	6939      	ldr	r1, [r7, #16]
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    6694:	f898 3008 	ldrb.w	r3, [r8, #8]
	if ((BIT(pin) & data->int_active_level) != 0U) {
    6698:	40e9      	lsrs	r1, r5
    669a:	f001 0101 	and.w	r1, r1, #1
    669e:	f1c1 0103 	rsb	r1, r1, #3
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    66a2:	f005 001f 	and.w	r0, r5, #31
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    66a6:	b2c9      	uxtb	r1, r1
    66a8:	ea40 1043 	orr.w	r0, r0, r3, lsl #5
    66ac:	f7fc fc12 	bl	2ed4 <nrf_gpio_cfg_sense_set>
			level_pins &= ~bit;
    66b0:	ea24 0406 	bic.w	r4, r4, r6
		++pin;
    66b4:	3501      	adds	r5, #1
		bit <<= 1;
    66b6:	0076      	lsls	r6, r6, #1
    66b8:	e7e6      	b.n	6688 <cfg_level_pins+0x1a>

000066ba <uart_nrfx_config_get>:
	*cfg = get_dev_data(dev)->uart_config;
    66ba:	6902      	ldr	r2, [r0, #16]
{
    66bc:	460b      	mov	r3, r1
	*cfg = get_dev_data(dev)->uart_config;
    66be:	e892 0003 	ldmia.w	r2, {r0, r1}
    66c2:	e883 0003 	stmia.w	r3, {r0, r1}
}
    66c6:	2000      	movs	r0, #0
    66c8:	4770      	bx	lr

000066ca <nrf_gpio_cfg_output>:
    reg->PIN_CNF[pin_number] = cnf;
    66ca:	f500 70e0 	add.w	r0, r0, #448	; 0x1c0
    66ce:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    66d2:	2203      	movs	r2, #3
    66d4:	f843 2020 	str.w	r2, [r3, r0, lsl #2]
}
    66d8:	4770      	bx	lr

000066da <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    66da:	4700      	bx	r0

000066dc <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    66dc:	f000 b9de 	b.w	6a9c <z_impl_k_busy_wait>

000066e0 <nrfx_clock_enable>:
{
    66e0:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    66e2:	2000      	movs	r0, #0
    66e4:	f7fb fe70 	bl	23c8 <arch_irq_is_enabled>
    66e8:	b908      	cbnz	r0, 66ee <nrfx_clock_enable+0xe>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    66ea:	f7fb fe5d 	bl	23a8 <arch_irq_enable>
    return false;
}

NRF_STATIC_INLINE void nrf_clock_lf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_lfclk_t source)
{
    p_reg->LFCLKSRC = (uint32_t)(source);
    66ee:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    66f2:	2200      	movs	r2, #0
    66f4:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    66f8:	bd08      	pop	{r3, pc}

000066fa <SEGGER_RTT_Init>:
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
  _DoInit();
    66fa:	f7fd b98b 	b.w	3a14 <_DoInit>

000066fe <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(const struct device *unused)
{
    66fe:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	SEGGER_RTT_Init();
    6700:	f7ff fffb 	bl	66fa <SEGGER_RTT_Init>

	return 0;
}
    6704:	2000      	movs	r0, #0
    6706:	bd08      	pop	{r3, pc}

00006708 <z_device_state_init>:
}
    6708:	4770      	bx	lr

0000670a <z_device_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    670a:	b138      	cbz	r0, 671c <z_device_ready+0x12>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    670c:	68c3      	ldr	r3, [r0, #12]
    670e:	8818      	ldrh	r0, [r3, #0]
    6710:	f3c0 0008 	ubfx	r0, r0, #0, #9
    6714:	f5a0 7380 	sub.w	r3, r0, #256	; 0x100
    6718:	4258      	negs	r0, r3
    671a:	4158      	adcs	r0, r3
}
    671c:	4770      	bx	lr

0000671e <k_mem_slab_init>:
{
    671e:	b530      	push	{r4, r5, lr}
	slab->num_used = 0U;
    6720:	2400      	movs	r4, #0
    6722:	61c4      	str	r4, [r0, #28]
	slab->lock = (struct k_spinlock) {};
    6724:	7204      	strb	r4, [r0, #8]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    6726:	ea41 0402 	orr.w	r4, r1, r2
    672a:	f014 0403 	ands.w	r4, r4, #3
	slab->block_size = block_size;
    672e:	e9c0 3203 	strd	r3, r2, [r0, #12]
	slab->buffer = buffer;
    6732:	6141      	str	r1, [r0, #20]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    6734:	d10c      	bne.n	6750 <k_mem_slab_init+0x32>
	slab->free_list = NULL;
    6736:	6184      	str	r4, [r0, #24]
	for (j = 0U; j < slab->num_blocks; j++) {
    6738:	42a3      	cmp	r3, r4
    673a:	d103      	bne.n	6744 <k_mem_slab_init+0x26>
	list->tail = (sys_dnode_t *)list;
    673c:	e9c0 0000 	strd	r0, r0, [r0]
}
    6740:	2000      	movs	r0, #0
}
    6742:	bd30      	pop	{r4, r5, pc}
		*(char **)p = slab->free_list;
    6744:	6985      	ldr	r5, [r0, #24]
    6746:	600d      	str	r5, [r1, #0]
	for (j = 0U; j < slab->num_blocks; j++) {
    6748:	3401      	adds	r4, #1
		slab->free_list = p;
    674a:	6181      	str	r1, [r0, #24]
		p += slab->block_size;
    674c:	4411      	add	r1, r2
	for (j = 0U; j < slab->num_blocks; j++) {
    674e:	e7f3      	b.n	6738 <k_mem_slab_init+0x1a>
		return -EINVAL;
    6750:	f06f 0015 	mvn.w	r0, #21
	return rc;
    6754:	e7f5      	b.n	6742 <k_mem_slab_init+0x24>

00006756 <k_mem_slab_free>:

void k_mem_slab_free(struct k_mem_slab *slab, void **mem)
{
    6756:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6758:	4604      	mov	r4, r0
    675a:	460d      	mov	r5, r1
	__asm__ volatile(
    675c:	f04f 0320 	mov.w	r3, #32
    6760:	f3ef 8611 	mrs	r6, BASEPRI
    6764:	f383 8811 	msr	BASEPRI, r3
    6768:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, free, slab);
	if (slab->free_list == NULL && IS_ENABLED(CONFIG_MULTITHREADING)) {
    676c:	6987      	ldr	r7, [r0, #24]
    676e:	b977      	cbnz	r7, 678e <k_mem_slab_free+0x38>
		struct k_thread *pending_thread = z_unpend_first_thread(&slab->wait_q);
    6770:	f000 f91b 	bl	69aa <z_unpend_first_thread>

		if (pending_thread != NULL) {
    6774:	b158      	cbz	r0, 678e <k_mem_slab_free+0x38>
			SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

			z_thread_return_value_set_with_data(pending_thread, 0, *mem);
    6776:	682a      	ldr	r2, [r5, #0]
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    6778:	6142      	str	r2, [r0, #20]
    677a:	6787      	str	r7, [r0, #120]	; 0x78
			z_ready_thread(pending_thread);
    677c:	f000 f8ce 	bl	691c <z_ready_thread>
			z_reschedule(&slab->lock, key);
    6780:	4631      	mov	r1, r6
    6782:	f104 0008 	add.w	r0, r4, #8
	slab->num_used--;

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

	k_spin_unlock(&slab->lock, key);
}
    6786:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
			z_reschedule(&slab->lock, key);
    678a:	f7fd bec9 	b.w	4520 <z_reschedule>
	**(char ***) mem = slab->free_list;
    678e:	682b      	ldr	r3, [r5, #0]
    6790:	69a2      	ldr	r2, [r4, #24]
    6792:	601a      	str	r2, [r3, #0]
	slab->free_list = *(char **) mem;
    6794:	682b      	ldr	r3, [r5, #0]
    6796:	61a3      	str	r3, [r4, #24]
	slab->num_used--;
    6798:	69e3      	ldr	r3, [r4, #28]
    679a:	3b01      	subs	r3, #1
    679c:	61e3      	str	r3, [r4, #28]
	__asm__ volatile(
    679e:	f386 8811 	msr	BASEPRI, r6
    67a2:	f3bf 8f6f 	isb	sy
}
    67a6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

000067a8 <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    67a8:	f3ef 8005 	mrs	r0, IPSR
}
    67ac:	3800      	subs	r0, #0
    67ae:	bf18      	it	ne
    67b0:	2001      	movne	r0, #1
    67b2:	4770      	bx	lr

000067b4 <z_impl_k_thread_name_set>:
}
    67b4:	f06f 0057 	mvn.w	r0, #87	; 0x57
    67b8:	4770      	bx	lr

000067ba <k_thread_name_get>:
}
    67ba:	2000      	movs	r0, #0
    67bc:	4770      	bx	lr

000067be <z_impl_k_thread_start>:
	z_sched_start(thread);
    67be:	f7fe b84d 	b.w	485c <z_sched_start>

000067c2 <z_pm_save_idle_exit>:
{
    67c2:	b508      	push	{r3, lr}
	pm_system_resume();
    67c4:	f7fb f9de 	bl	1b84 <pm_system_resume>
}
    67c8:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	sys_clock_idle_exit();
    67cc:	f7ff be99 	b.w	6502 <sys_clock_idle_exit>

000067d0 <z_impl_k_mutex_init>:
{
    67d0:	4603      	mov	r3, r0
	mutex->owner = NULL;
    67d2:	2000      	movs	r0, #0
	mutex->lock_count = 0U;
    67d4:	e9c3 0002 	strd	r0, r0, [r3, #8]
    67d8:	e9c3 3300 	strd	r3, r3, [r3]
}
    67dc:	4770      	bx	lr

000067de <z_impl_k_sem_init>:
	CHECKIF(limit == 0U || limit > K_SEM_MAX_LIMIT || initial_count > limit) {
    67de:	b13a      	cbz	r2, 67f0 <z_impl_k_sem_init+0x12>
    67e0:	428a      	cmp	r2, r1
    67e2:	d305      	bcc.n	67f0 <z_impl_k_sem_init+0x12>
	sem->limit = limit;
    67e4:	e9c0 1202 	strd	r1, r2, [r0, #8]
    67e8:	e9c0 0000 	strd	r0, r0, [r0]
	return 0;
    67ec:	2000      	movs	r0, #0
    67ee:	4770      	bx	lr
		return -EINVAL;
    67f0:	f06f 0015 	mvn.w	r0, #21
}
    67f4:	4770      	bx	lr

000067f6 <notify_queue_locked>:
	if (queue != NULL) {
    67f6:	b120      	cbz	r0, 6802 <notify_queue_locked+0xc>
		rv = z_sched_wake(&queue->notifyq, 0, NULL);
    67f8:	2200      	movs	r2, #0
    67fa:	4611      	mov	r1, r2
    67fc:	3088      	adds	r0, #136	; 0x88
    67fe:	f000 b8ec 	b.w	69da <z_sched_wake>
}
    6802:	4770      	bx	lr

00006804 <k_work_submit_to_queue>:
{
    6804:	b537      	push	{r0, r1, r2, r4, r5, lr}
    6806:	9001      	str	r0, [sp, #4]
    6808:	4608      	mov	r0, r1
	__asm__ volatile(
    680a:	f04f 0320 	mov.w	r3, #32
    680e:	f3ef 8511 	mrs	r5, BASEPRI
    6812:	f383 8811 	msr	BASEPRI, r3
    6816:	f3bf 8f6f 	isb	sy
	int ret = submit_to_queue_locked(work, &queue);
    681a:	a901      	add	r1, sp, #4
    681c:	f7fd fdaa 	bl	4374 <submit_to_queue_locked>
    6820:	4604      	mov	r4, r0
	__asm__ volatile(
    6822:	f385 8811 	msr	BASEPRI, r5
    6826:	f3bf 8f6f 	isb	sy
	if ((ret > 0) && (k_is_preempt_thread() != 0)) {
    682a:	2800      	cmp	r0, #0
    682c:	dd04      	ble.n	6838 <k_work_submit_to_queue+0x34>
	return z_impl_k_is_preempt_thread();
    682e:	f7fe f939 	bl	4aa4 <z_impl_k_is_preempt_thread>
    6832:	b108      	cbz	r0, 6838 <k_work_submit_to_queue+0x34>
	z_impl_k_yield();
    6834:	f7fe f888 	bl	4948 <z_impl_k_yield>
}
    6838:	4620      	mov	r0, r4
    683a:	b003      	add	sp, #12
    683c:	bd30      	pop	{r4, r5, pc}

0000683e <sys_dlist_remove>:
	sys_dnode_t *const next = node->next;
    683e:	e9d0 3200 	ldrd	r3, r2, [r0]
	prev->next = next;
    6842:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    6844:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    6846:	2300      	movs	r3, #0
	node->prev = NULL;
    6848:	e9c0 3300 	strd	r3, r3, [r0]
	sys_dnode_init(node);
}
    684c:	4770      	bx	lr

0000684e <unpend_thread_no_timeout>:
{
    684e:	b508      	push	{r3, lr}
	sys_dlist_remove(&thread->base.qnode_dlist);
    6850:	f7ff fff5 	bl	683e <sys_dlist_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    6854:	7b43      	ldrb	r3, [r0, #13]
    6856:	f023 0302 	bic.w	r3, r3, #2
    685a:	7343      	strb	r3, [r0, #13]
	thread->base.pended_on = NULL;
    685c:	2300      	movs	r3, #0
    685e:	6083      	str	r3, [r0, #8]
}
    6860:	bd08      	pop	{r3, pc}

00006862 <z_unpend_thread_no_timeout>:
{
    6862:	b508      	push	{r3, lr}
	__asm__ volatile(
    6864:	f04f 0320 	mov.w	r3, #32
    6868:	f3ef 8111 	mrs	r1, BASEPRI
    686c:	f383 8811 	msr	BASEPRI, r3
    6870:	f3bf 8f6f 	isb	sy
		unpend_thread_no_timeout(thread);
    6874:	f7ff ffeb 	bl	684e <unpend_thread_no_timeout>
	__asm__ volatile(
    6878:	f381 8811 	msr	BASEPRI, r1
    687c:	f3bf 8f6f 	isb	sy
}
    6880:	bd08      	pop	{r3, pc}

00006882 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    6882:	4603      	mov	r3, r0
    6884:	b920      	cbnz	r0, 6890 <z_reschedule_irqlock+0xe>
    6886:	f3ef 8205 	mrs	r2, IPSR
	if (resched(key)) {
    688a:	b90a      	cbnz	r2, 6890 <z_reschedule_irqlock+0xe>
	ret = arch_swap(key);
    688c:	f7fb bd72 	b.w	2374 <arch_swap>
    6890:	f383 8811 	msr	BASEPRI, r3
    6894:	f3bf 8f6f 	isb	sy
}
    6898:	4770      	bx	lr

0000689a <z_reschedule_unlocked>:
	__asm__ volatile(
    689a:	f04f 0320 	mov.w	r3, #32
    689e:	f3ef 8011 	mrs	r0, BASEPRI
    68a2:	f383 8811 	msr	BASEPRI, r3
    68a6:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    68aa:	f7ff bfea 	b.w	6882 <z_reschedule_irqlock>

000068ae <z_priq_dumb_best>:
{
    68ae:	4603      	mov	r3, r0
	return list->head == list;
    68b0:	6800      	ldr	r0, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    68b2:	4283      	cmp	r3, r0
    68b4:	d003      	beq.n	68be <z_priq_dumb_best+0x10>
	if (n != NULL) {
    68b6:	2800      	cmp	r0, #0
    68b8:	bf38      	it	cc
    68ba:	2000      	movcc	r0, #0
    68bc:	4770      	bx	lr
	struct k_thread *thread = NULL;
    68be:	2000      	movs	r0, #0
}
    68c0:	4770      	bx	lr

000068c2 <add_to_waitq_locked>:
{
    68c2:	b538      	push	{r3, r4, r5, lr}
    68c4:	4604      	mov	r4, r0
    68c6:	460d      	mov	r5, r1
	unready_thread(thread);
    68c8:	f7fd fe70 	bl	45ac <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    68cc:	7b63      	ldrb	r3, [r4, #13]
    68ce:	f043 0302 	orr.w	r3, r3, #2
    68d2:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    68d4:	b1b5      	cbz	r5, 6904 <add_to_waitq_locked+0x42>
	return list->head == list;
    68d6:	682b      	ldr	r3, [r5, #0]
		thread->base.pended_on = wait_q;
    68d8:	60a5      	str	r5, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    68da:	429d      	cmp	r5, r3
    68dc:	bf08      	it	eq
    68de:	2300      	moveq	r3, #0
    68e0:	2b00      	cmp	r3, #0
    68e2:	bf38      	it	cc
    68e4:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    68e6:	b19b      	cbz	r3, 6910 <add_to_waitq_locked+0x4e>
	int32_t b1 = thread_1->base.prio;
    68e8:	f994 100e 	ldrsb.w	r1, [r4, #14]
	int32_t b2 = thread_2->base.prio;
    68ec:	f993 200e 	ldrsb.w	r2, [r3, #14]
	if (b1 != b2) {
    68f0:	4291      	cmp	r1, r2
    68f2:	d008      	beq.n	6906 <add_to_waitq_locked+0x44>
		return b2 - b1;
    68f4:	1a52      	subs	r2, r2, r1
		if (z_sched_prio_cmp(thread, t) > 0) {
    68f6:	2a00      	cmp	r2, #0
    68f8:	dd05      	ble.n	6906 <add_to_waitq_locked+0x44>
	sys_dnode_t *const prev = successor->prev;
    68fa:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    68fc:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    6900:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    6902:	605c      	str	r4, [r3, #4]
}
    6904:	bd38      	pop	{r3, r4, r5, pc}
	return (node == list->tail) ? NULL : node->next;
    6906:	686a      	ldr	r2, [r5, #4]
    6908:	4293      	cmp	r3, r2
    690a:	d001      	beq.n	6910 <add_to_waitq_locked+0x4e>
    690c:	681b      	ldr	r3, [r3, #0]
    690e:	e7ea      	b.n	68e6 <add_to_waitq_locked+0x24>
	sys_dnode_t *const tail = list->tail;
    6910:	686b      	ldr	r3, [r5, #4]
	node->prev = tail;
    6912:	e9c4 5300 	strd	r5, r3, [r4]
	tail->next = node;
    6916:	601c      	str	r4, [r3, #0]
	list->tail = node;
    6918:	606c      	str	r4, [r5, #4]
    691a:	e7f3      	b.n	6904 <add_to_waitq_locked+0x42>

0000691c <z_ready_thread>:
{
    691c:	b510      	push	{r4, lr}
    691e:	f04f 0320 	mov.w	r3, #32
    6922:	f3ef 8411 	mrs	r4, BASEPRI
    6926:	f383 8811 	msr	BASEPRI, r3
    692a:	f3bf 8f6f 	isb	sy
			ready_thread(thread);
    692e:	f7fd ff5d 	bl	47ec <ready_thread>
	__asm__ volatile(
    6932:	f384 8811 	msr	BASEPRI, r4
    6936:	f3bf 8f6f 	isb	sy
}
    693a:	bd10      	pop	{r4, pc}

0000693c <z_thread_timeout>:
{
    693c:	b510      	push	{r4, lr}
    693e:	4601      	mov	r1, r0
	__asm__ volatile(
    6940:	f04f 0320 	mov.w	r3, #32
    6944:	f3ef 8411 	mrs	r4, BASEPRI
    6948:	f383 8811 	msr	BASEPRI, r3
    694c:	f3bf 8f6f 	isb	sy
		if (!killed) {
    6950:	f810 3c0b 	ldrb.w	r3, [r0, #-11]
    6954:	f013 0f28 	tst.w	r3, #40	; 0x28
    6958:	d10d      	bne.n	6976 <z_thread_timeout+0x3a>
			if (thread->base.pended_on != NULL) {
    695a:	f851 3c10 	ldr.w	r3, [r1, #-16]
	struct k_thread *thread = CONTAINER_OF(timeout,
    695e:	3818      	subs	r0, #24
			if (thread->base.pended_on != NULL) {
    6960:	b10b      	cbz	r3, 6966 <z_thread_timeout+0x2a>
				unpend_thread_no_timeout(thread);
    6962:	f7ff ff74 	bl	684e <unpend_thread_no_timeout>
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    6966:	f811 3c0b 	ldrb.w	r3, [r1, #-11]
    696a:	f023 0314 	bic.w	r3, r3, #20
    696e:	f801 3c0b 	strb.w	r3, [r1, #-11]
			ready_thread(thread);
    6972:	f7fd ff3b 	bl	47ec <ready_thread>
	__asm__ volatile(
    6976:	f384 8811 	msr	BASEPRI, r4
    697a:	f3bf 8f6f 	isb	sy
}
    697e:	bd10      	pop	{r4, pc}

00006980 <z_unpend1_no_timeout>:
{
    6980:	b510      	push	{r4, lr}
	__asm__ volatile(
    6982:	f04f 0320 	mov.w	r3, #32
    6986:	f3ef 8411 	mrs	r4, BASEPRI
    698a:	f383 8811 	msr	BASEPRI, r3
    698e:	f3bf 8f6f 	isb	sy
		thread = _priq_wait_best(&wait_q->waitq);
    6992:	f7ff ff8c 	bl	68ae <z_priq_dumb_best>
		if (thread != NULL) {
    6996:	4601      	mov	r1, r0
    6998:	b108      	cbz	r0, 699e <z_unpend1_no_timeout+0x1e>
			unpend_thread_no_timeout(thread);
    699a:	f7ff ff58 	bl	684e <unpend_thread_no_timeout>
	__asm__ volatile(
    699e:	f384 8811 	msr	BASEPRI, r4
    69a2:	f3bf 8f6f 	isb	sy
}
    69a6:	4608      	mov	r0, r1
    69a8:	bd10      	pop	{r4, pc}

000069aa <z_unpend_first_thread>:
{
    69aa:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    69ac:	f04f 0320 	mov.w	r3, #32
    69b0:	f3ef 8511 	mrs	r5, BASEPRI
    69b4:	f383 8811 	msr	BASEPRI, r3
    69b8:	f3bf 8f6f 	isb	sy
		thread = _priq_wait_best(&wait_q->waitq);
    69bc:	f7ff ff77 	bl	68ae <z_priq_dumb_best>
		if (thread != NULL) {
    69c0:	4604      	mov	r4, r0
    69c2:	b120      	cbz	r0, 69ce <z_unpend_first_thread+0x24>
			unpend_thread_no_timeout(thread);
    69c4:	f7ff ff43 	bl	684e <unpend_thread_no_timeout>
    69c8:	3018      	adds	r0, #24
    69ca:	f000 f823 	bl	6a14 <z_abort_timeout>
	__asm__ volatile(
    69ce:	f385 8811 	msr	BASEPRI, r5
    69d2:	f3bf 8f6f 	isb	sy
}
    69d6:	4620      	mov	r0, r4
    69d8:	bd38      	pop	{r3, r4, r5, pc}

000069da <z_sched_wake>:
{
    69da:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    69dc:	f04f 0320 	mov.w	r3, #32
    69e0:	f3ef 8511 	mrs	r5, BASEPRI
    69e4:	f383 8811 	msr	BASEPRI, r3
    69e8:	f3bf 8f6f 	isb	sy
		thread = _priq_wait_best(&wait_q->waitq);
    69ec:	f7ff ff5f 	bl	68ae <z_priq_dumb_best>
		if (thread != NULL) {
    69f0:	4604      	mov	r4, r0
    69f2:	b150      	cbz	r0, 6a0a <z_sched_wake+0x30>
    69f4:	6781      	str	r1, [r0, #120]	; 0x78
    69f6:	6142      	str	r2, [r0, #20]
			unpend_thread_no_timeout(thread);
    69f8:	f7ff ff29 	bl	684e <unpend_thread_no_timeout>
    69fc:	3018      	adds	r0, #24
    69fe:	f000 f809 	bl	6a14 <z_abort_timeout>
			ready_thread(thread);
    6a02:	4620      	mov	r0, r4
    6a04:	f7fd fef2 	bl	47ec <ready_thread>
			ret = true;
    6a08:	2001      	movs	r0, #1
	__asm__ volatile(
    6a0a:	f385 8811 	msr	BASEPRI, r5
    6a0e:	f3bf 8f6f 	isb	sy
}
    6a12:	bd38      	pop	{r3, r4, r5, pc}

00006a14 <z_abort_timeout>:
{
    6a14:	b510      	push	{r4, lr}
	__asm__ volatile(
    6a16:	f04f 0220 	mov.w	r2, #32
    6a1a:	f3ef 8411 	mrs	r4, BASEPRI
    6a1e:	f382 8811 	msr	BASEPRI, r2
    6a22:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
    6a26:	6803      	ldr	r3, [r0, #0]
    6a28:	b13b      	cbz	r3, 6a3a <z_abort_timeout+0x26>
			remove_timeout(to);
    6a2a:	f7fe f8d3 	bl	4bd4 <remove_timeout>
			ret = 0;
    6a2e:	2000      	movs	r0, #0
	__asm__ volatile(
    6a30:	f384 8811 	msr	BASEPRI, r4
    6a34:	f3bf 8f6f 	isb	sy
}
    6a38:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
    6a3a:	f06f 0015 	mvn.w	r0, #21
    6a3e:	e7f7      	b.n	6a30 <z_abort_timeout+0x1c>

00006a40 <z_get_next_timeout_expiry>:
{
    6a40:	b510      	push	{r4, lr}
	__asm__ volatile(
    6a42:	f04f 0320 	mov.w	r3, #32
    6a46:	f3ef 8411 	mrs	r4, BASEPRI
    6a4a:	f383 8811 	msr	BASEPRI, r3
    6a4e:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
    6a52:	f7fe f8d9 	bl	4c08 <next_timeout>
	__asm__ volatile(
    6a56:	f384 8811 	msr	BASEPRI, r4
    6a5a:	f3bf 8f6f 	isb	sy
}
    6a5e:	bd10      	pop	{r4, pc}

00006a60 <z_set_timeout_expiry>:
{
    6a60:	b570      	push	{r4, r5, r6, lr}
    6a62:	4604      	mov	r4, r0
    6a64:	460d      	mov	r5, r1
	__asm__ volatile(
    6a66:	f04f 0320 	mov.w	r3, #32
    6a6a:	f3ef 8611 	mrs	r6, BASEPRI
    6a6e:	f383 8811 	msr	BASEPRI, r3
    6a72:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
    6a76:	f7fe f8c7 	bl	4c08 <next_timeout>
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
    6a7a:	2801      	cmp	r0, #1
    6a7c:	dd05      	ble.n	6a8a <z_set_timeout_expiry+0x2a>
    6a7e:	42a0      	cmp	r0, r4
    6a80:	db03      	blt.n	6a8a <z_set_timeout_expiry+0x2a>
			sys_clock_set_timeout(MIN(ticks, next_to), is_idle);
    6a82:	4629      	mov	r1, r5
    6a84:	4620      	mov	r0, r4
    6a86:	f7fb fc1b 	bl	22c0 <sys_clock_set_timeout>
	__asm__ volatile(
    6a8a:	f386 8811 	msr	BASEPRI, r6
    6a8e:	f3bf 8f6f 	isb	sy
}
    6a92:	bd70      	pop	{r4, r5, r6, pc}

00006a94 <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
    6a94:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
    6a96:	f7fe f9d7 	bl	4e48 <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    6a9a:	bd08      	pop	{r3, pc}

00006a9c <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    6a9c:	b108      	cbz	r0, 6aa2 <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    6a9e:	f7fc b997 	b.w	2dd0 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    6aa2:	4770      	bx	lr

00006aa4 <k_timer_init>:
	timer->status = 0U;
    6aa4:	2300      	movs	r3, #0
	timer->stop_fn = stop_fn;
    6aa6:	e9c0 1208 	strd	r1, r2, [r0, #32]
	sys_dlist_init(&w->waitq);
    6aaa:	f100 0218 	add.w	r2, r0, #24
	list->tail = (sys_dnode_t *)list;
    6aae:	e9c0 2206 	strd	r2, r2, [r0, #24]
	node->prev = NULL;
    6ab2:	e9c0 3300 	strd	r3, r3, [r0]
	timer->status = 0U;
    6ab6:	6303      	str	r3, [r0, #48]	; 0x30
	timer->user_data = NULL;
    6ab8:	6343      	str	r3, [r0, #52]	; 0x34
}
    6aba:	4770      	bx	lr

00006abc <z_impl_k_timer_stop>:
}
#include <syscalls/k_timer_start_mrsh.c>
#endif

void z_impl_k_timer_stop(struct k_timer *timer)
{
    6abc:	b510      	push	{r4, lr}
    6abe:	4604      	mov	r4, r0
	SYS_PORT_TRACING_OBJ_FUNC(k_timer, stop, timer);

	int inactive = z_abort_timeout(&timer->timeout) != 0;
    6ac0:	f7ff ffa8 	bl	6a14 <z_abort_timeout>

	if (inactive) {
    6ac4:	b9b0      	cbnz	r0, 6af4 <z_impl_k_timer_stop+0x38>
		return;
	}

	if (timer->stop_fn != NULL) {
    6ac6:	6a63      	ldr	r3, [r4, #36]	; 0x24
    6ac8:	b10b      	cbz	r3, 6ace <z_impl_k_timer_stop+0x12>
		timer->stop_fn(timer);
    6aca:	4620      	mov	r0, r4
    6acc:	4798      	blx	r3
	}

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		struct k_thread *pending_thread = z_unpend1_no_timeout(&timer->wait_q);
    6ace:	f104 0018 	add.w	r0, r4, #24
    6ad2:	f7ff ff55 	bl	6980 <z_unpend1_no_timeout>

		if (pending_thread != NULL) {
    6ad6:	b168      	cbz	r0, 6af4 <z_impl_k_timer_stop+0x38>
			z_ready_thread(pending_thread);
    6ad8:	f7ff ff20 	bl	691c <z_ready_thread>
	__asm__ volatile(
    6adc:	f04f 0320 	mov.w	r3, #32
    6ae0:	f3ef 8011 	mrs	r0, BASEPRI
    6ae4:	f383 8811 	msr	BASEPRI, r3
    6ae8:	f3bf 8f6f 	isb	sy
			z_reschedule_unlocked();
		}
	}
}
    6aec:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	(void) z_reschedule_irqlock(arch_irq_lock());
    6af0:	f7ff bec7 	b.w	6882 <z_reschedule_irqlock>
    6af4:	bd10      	pop	{r4, pc}

00006af6 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    6af6:	4770      	bx	lr

00006af8 <abs>:
    6af8:	2800      	cmp	r0, #0
    6afa:	bfb8      	it	lt
    6afc:	4240      	neglt	r0, r0
    6afe:	4770      	bx	lr

00006b00 <memcpy>:
    6b00:	440a      	add	r2, r1
    6b02:	4291      	cmp	r1, r2
    6b04:	f100 33ff 	add.w	r3, r0, #4294967295
    6b08:	d100      	bne.n	6b0c <memcpy+0xc>
    6b0a:	4770      	bx	lr
    6b0c:	b510      	push	{r4, lr}
    6b0e:	f811 4b01 	ldrb.w	r4, [r1], #1
    6b12:	f803 4f01 	strb.w	r4, [r3, #1]!
    6b16:	4291      	cmp	r1, r2
    6b18:	d1f9      	bne.n	6b0e <memcpy+0xe>
    6b1a:	bd10      	pop	{r4, pc}

00006b1c <memset>:
    6b1c:	4402      	add	r2, r0
    6b1e:	4603      	mov	r3, r0
    6b20:	4293      	cmp	r3, r2
    6b22:	d100      	bne.n	6b26 <memset+0xa>
    6b24:	4770      	bx	lr
    6b26:	f803 1b01 	strb.w	r1, [r3], #1
    6b2a:	e7f9      	b.n	6b20 <memset+0x4>

00006b2c <strcpy>:
    6b2c:	4603      	mov	r3, r0
    6b2e:	f811 2b01 	ldrb.w	r2, [r1], #1
    6b32:	f803 2b01 	strb.w	r2, [r3], #1
    6b36:	2a00      	cmp	r2, #0
    6b38:	d1f9      	bne.n	6b2e <strcpy+0x2>
    6b3a:	4770      	bx	lr

00006b3c <strncpy>:
    6b3c:	b510      	push	{r4, lr}
    6b3e:	3901      	subs	r1, #1
    6b40:	4603      	mov	r3, r0
    6b42:	b132      	cbz	r2, 6b52 <strncpy+0x16>
    6b44:	f811 4f01 	ldrb.w	r4, [r1, #1]!
    6b48:	f803 4b01 	strb.w	r4, [r3], #1
    6b4c:	3a01      	subs	r2, #1
    6b4e:	2c00      	cmp	r4, #0
    6b50:	d1f7      	bne.n	6b42 <strncpy+0x6>
    6b52:	441a      	add	r2, r3
    6b54:	2100      	movs	r1, #0
    6b56:	4293      	cmp	r3, r2
    6b58:	d100      	bne.n	6b5c <strncpy+0x20>
    6b5a:	bd10      	pop	{r4, pc}
    6b5c:	f803 1b01 	strb.w	r1, [r3], #1
    6b60:	e7f9      	b.n	6b56 <strncpy+0x1a>

00006b62 <strnlen>:
    6b62:	b510      	push	{r4, lr}
    6b64:	4602      	mov	r2, r0
    6b66:	4401      	add	r1, r0
    6b68:	428a      	cmp	r2, r1
    6b6a:	4613      	mov	r3, r2
    6b6c:	d101      	bne.n	6b72 <strnlen+0x10>
    6b6e:	1a18      	subs	r0, r3, r0
    6b70:	bd10      	pop	{r4, pc}
    6b72:	781c      	ldrb	r4, [r3, #0]
    6b74:	3201      	adds	r2, #1
    6b76:	2c00      	cmp	r4, #0
    6b78:	d1f6      	bne.n	6b68 <strnlen+0x6>
    6b7a:	e7f8      	b.n	6b6e <strnlen+0xc>

00006b7c <__sfmoreglue>:
    6b7c:	b570      	push	{r4, r5, r6, lr}
    6b7e:	1e4a      	subs	r2, r1, #1
    6b80:	2568      	movs	r5, #104	; 0x68
    6b82:	4355      	muls	r5, r2
    6b84:	460e      	mov	r6, r1
    6b86:	f105 0174 	add.w	r1, r5, #116	; 0x74
    6b8a:	f7fe fafd 	bl	5188 <_malloc_r>
    6b8e:	4604      	mov	r4, r0
    6b90:	b140      	cbz	r0, 6ba4 <__sfmoreglue+0x28>
    6b92:	2100      	movs	r1, #0
    6b94:	e9c0 1600 	strd	r1, r6, [r0]
    6b98:	300c      	adds	r0, #12
    6b9a:	60a0      	str	r0, [r4, #8]
    6b9c:	f105 0268 	add.w	r2, r5, #104	; 0x68
    6ba0:	f7ff ffbc 	bl	6b1c <memset>
    6ba4:	4620      	mov	r0, r4
    6ba6:	bd70      	pop	{r4, r5, r6, pc}

00006ba8 <_fwalk_reent>:
    6ba8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    6bac:	4606      	mov	r6, r0
    6bae:	4688      	mov	r8, r1
    6bb0:	f100 0448 	add.w	r4, r0, #72	; 0x48
    6bb4:	2700      	movs	r7, #0
    6bb6:	e9d4 9501 	ldrd	r9, r5, [r4, #4]
    6bba:	f1b9 0901 	subs.w	r9, r9, #1
    6bbe:	d505      	bpl.n	6bcc <_fwalk_reent+0x24>
    6bc0:	6824      	ldr	r4, [r4, #0]
    6bc2:	2c00      	cmp	r4, #0
    6bc4:	d1f7      	bne.n	6bb6 <_fwalk_reent+0xe>
    6bc6:	4638      	mov	r0, r7
    6bc8:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    6bcc:	89ab      	ldrh	r3, [r5, #12]
    6bce:	2b01      	cmp	r3, #1
    6bd0:	d907      	bls.n	6be2 <_fwalk_reent+0x3a>
    6bd2:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
    6bd6:	3301      	adds	r3, #1
    6bd8:	d003      	beq.n	6be2 <_fwalk_reent+0x3a>
    6bda:	4629      	mov	r1, r5
    6bdc:	4630      	mov	r0, r6
    6bde:	47c0      	blx	r8
    6be0:	4307      	orrs	r7, r0
    6be2:	3568      	adds	r5, #104	; 0x68
    6be4:	e7e9      	b.n	6bba <_fwalk_reent+0x12>

00006be6 <__retarget_lock_init_recursive>:
    6be6:	4770      	bx	lr

00006be8 <__retarget_lock_acquire_recursive>:
    6be8:	4770      	bx	lr

00006bea <__retarget_lock_release_recursive>:
    6bea:	4770      	bx	lr

00006bec <__sfputc_r>:
    6bec:	6893      	ldr	r3, [r2, #8]
    6bee:	3b01      	subs	r3, #1
    6bf0:	2b00      	cmp	r3, #0
    6bf2:	b410      	push	{r4}
    6bf4:	6093      	str	r3, [r2, #8]
    6bf6:	da07      	bge.n	6c08 <__sfputc_r+0x1c>
    6bf8:	6994      	ldr	r4, [r2, #24]
    6bfa:	42a3      	cmp	r3, r4
    6bfc:	db01      	blt.n	6c02 <__sfputc_r+0x16>
    6bfe:	290a      	cmp	r1, #10
    6c00:	d102      	bne.n	6c08 <__sfputc_r+0x1c>
    6c02:	bc10      	pop	{r4}
    6c04:	f7fe bd80 	b.w	5708 <__swbuf_r>
    6c08:	6813      	ldr	r3, [r2, #0]
    6c0a:	1c58      	adds	r0, r3, #1
    6c0c:	6010      	str	r0, [r2, #0]
    6c0e:	7019      	strb	r1, [r3, #0]
    6c10:	4608      	mov	r0, r1
    6c12:	bc10      	pop	{r4}
    6c14:	4770      	bx	lr

00006c16 <__sfputs_r>:
    6c16:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6c18:	4606      	mov	r6, r0
    6c1a:	460f      	mov	r7, r1
    6c1c:	4614      	mov	r4, r2
    6c1e:	18d5      	adds	r5, r2, r3
    6c20:	42ac      	cmp	r4, r5
    6c22:	d101      	bne.n	6c28 <__sfputs_r+0x12>
    6c24:	2000      	movs	r0, #0
    6c26:	e007      	b.n	6c38 <__sfputs_r+0x22>
    6c28:	f814 1b01 	ldrb.w	r1, [r4], #1
    6c2c:	463a      	mov	r2, r7
    6c2e:	4630      	mov	r0, r6
    6c30:	f7ff ffdc 	bl	6bec <__sfputc_r>
    6c34:	1c43      	adds	r3, r0, #1
    6c36:	d1f3      	bne.n	6c20 <__sfputs_r+0xa>
    6c38:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00006c3a <_printf_common>:
    6c3a:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    6c3e:	4616      	mov	r6, r2
    6c40:	4699      	mov	r9, r3
    6c42:	688a      	ldr	r2, [r1, #8]
    6c44:	690b      	ldr	r3, [r1, #16]
    6c46:	f8dd 8020 	ldr.w	r8, [sp, #32]
    6c4a:	4293      	cmp	r3, r2
    6c4c:	bfb8      	it	lt
    6c4e:	4613      	movlt	r3, r2
    6c50:	6033      	str	r3, [r6, #0]
    6c52:	f891 2043 	ldrb.w	r2, [r1, #67]	; 0x43
    6c56:	4607      	mov	r7, r0
    6c58:	460c      	mov	r4, r1
    6c5a:	b10a      	cbz	r2, 6c60 <_printf_common+0x26>
    6c5c:	3301      	adds	r3, #1
    6c5e:	6033      	str	r3, [r6, #0]
    6c60:	6823      	ldr	r3, [r4, #0]
    6c62:	0699      	lsls	r1, r3, #26
    6c64:	bf42      	ittt	mi
    6c66:	6833      	ldrmi	r3, [r6, #0]
    6c68:	3302      	addmi	r3, #2
    6c6a:	6033      	strmi	r3, [r6, #0]
    6c6c:	6825      	ldr	r5, [r4, #0]
    6c6e:	f015 0506 	ands.w	r5, r5, #6
    6c72:	d106      	bne.n	6c82 <_printf_common+0x48>
    6c74:	f104 0a19 	add.w	sl, r4, #25
    6c78:	68e3      	ldr	r3, [r4, #12]
    6c7a:	6832      	ldr	r2, [r6, #0]
    6c7c:	1a9b      	subs	r3, r3, r2
    6c7e:	42ab      	cmp	r3, r5
    6c80:	dc26      	bgt.n	6cd0 <_printf_common+0x96>
    6c82:	f894 2043 	ldrb.w	r2, [r4, #67]	; 0x43
    6c86:	1e13      	subs	r3, r2, #0
    6c88:	6822      	ldr	r2, [r4, #0]
    6c8a:	bf18      	it	ne
    6c8c:	2301      	movne	r3, #1
    6c8e:	0692      	lsls	r2, r2, #26
    6c90:	d42b      	bmi.n	6cea <_printf_common+0xb0>
    6c92:	f104 0243 	add.w	r2, r4, #67	; 0x43
    6c96:	4649      	mov	r1, r9
    6c98:	4638      	mov	r0, r7
    6c9a:	47c0      	blx	r8
    6c9c:	3001      	adds	r0, #1
    6c9e:	d01e      	beq.n	6cde <_printf_common+0xa4>
    6ca0:	6823      	ldr	r3, [r4, #0]
    6ca2:	68e5      	ldr	r5, [r4, #12]
    6ca4:	6832      	ldr	r2, [r6, #0]
    6ca6:	f003 0306 	and.w	r3, r3, #6
    6caa:	2b04      	cmp	r3, #4
    6cac:	bf08      	it	eq
    6cae:	1aad      	subeq	r5, r5, r2
    6cb0:	68a3      	ldr	r3, [r4, #8]
    6cb2:	6922      	ldr	r2, [r4, #16]
    6cb4:	bf0c      	ite	eq
    6cb6:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
    6cba:	2500      	movne	r5, #0
    6cbc:	4293      	cmp	r3, r2
    6cbe:	bfc4      	itt	gt
    6cc0:	1a9b      	subgt	r3, r3, r2
    6cc2:	18ed      	addgt	r5, r5, r3
    6cc4:	2600      	movs	r6, #0
    6cc6:	341a      	adds	r4, #26
    6cc8:	42b5      	cmp	r5, r6
    6cca:	d11a      	bne.n	6d02 <_printf_common+0xc8>
    6ccc:	2000      	movs	r0, #0
    6cce:	e008      	b.n	6ce2 <_printf_common+0xa8>
    6cd0:	2301      	movs	r3, #1
    6cd2:	4652      	mov	r2, sl
    6cd4:	4649      	mov	r1, r9
    6cd6:	4638      	mov	r0, r7
    6cd8:	47c0      	blx	r8
    6cda:	3001      	adds	r0, #1
    6cdc:	d103      	bne.n	6ce6 <_printf_common+0xac>
    6cde:	f04f 30ff 	mov.w	r0, #4294967295
    6ce2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    6ce6:	3501      	adds	r5, #1
    6ce8:	e7c6      	b.n	6c78 <_printf_common+0x3e>
    6cea:	18e1      	adds	r1, r4, r3
    6cec:	1c5a      	adds	r2, r3, #1
    6cee:	2030      	movs	r0, #48	; 0x30
    6cf0:	f881 0043 	strb.w	r0, [r1, #67]	; 0x43
    6cf4:	4422      	add	r2, r4
    6cf6:	f894 1045 	ldrb.w	r1, [r4, #69]	; 0x45
    6cfa:	f882 1043 	strb.w	r1, [r2, #67]	; 0x43
    6cfe:	3302      	adds	r3, #2
    6d00:	e7c7      	b.n	6c92 <_printf_common+0x58>
    6d02:	2301      	movs	r3, #1
    6d04:	4622      	mov	r2, r4
    6d06:	4649      	mov	r1, r9
    6d08:	4638      	mov	r0, r7
    6d0a:	47c0      	blx	r8
    6d0c:	3001      	adds	r0, #1
    6d0e:	d0e6      	beq.n	6cde <_printf_common+0xa4>
    6d10:	3601      	adds	r6, #1
    6d12:	e7d9      	b.n	6cc8 <_printf_common+0x8e>

00006d14 <__sread>:
    6d14:	b510      	push	{r4, lr}
    6d16:	460c      	mov	r4, r1
    6d18:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
    6d1c:	f7fe ff38 	bl	5b90 <_read_r>
    6d20:	2800      	cmp	r0, #0
    6d22:	bfab      	itete	ge
    6d24:	6d63      	ldrge	r3, [r4, #84]	; 0x54
    6d26:	89a3      	ldrhlt	r3, [r4, #12]
    6d28:	181b      	addge	r3, r3, r0
    6d2a:	f423 5380 	biclt.w	r3, r3, #4096	; 0x1000
    6d2e:	bfac      	ite	ge
    6d30:	6563      	strge	r3, [r4, #84]	; 0x54
    6d32:	81a3      	strhlt	r3, [r4, #12]
    6d34:	bd10      	pop	{r4, pc}

00006d36 <__swrite>:
    6d36:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6d3a:	461f      	mov	r7, r3
    6d3c:	898b      	ldrh	r3, [r1, #12]
    6d3e:	05db      	lsls	r3, r3, #23
    6d40:	4605      	mov	r5, r0
    6d42:	460c      	mov	r4, r1
    6d44:	4616      	mov	r6, r2
    6d46:	d505      	bpl.n	6d54 <__swrite+0x1e>
    6d48:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
    6d4c:	2302      	movs	r3, #2
    6d4e:	2200      	movs	r2, #0
    6d50:	f7fe fe7e 	bl	5a50 <_lseek_r>
    6d54:	89a3      	ldrh	r3, [r4, #12]
    6d56:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
    6d5a:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
    6d5e:	81a3      	strh	r3, [r4, #12]
    6d60:	4632      	mov	r2, r6
    6d62:	463b      	mov	r3, r7
    6d64:	4628      	mov	r0, r5
    6d66:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    6d6a:	f7fe bd1f 	b.w	57ac <_write_r>

00006d6e <__sseek>:
    6d6e:	b510      	push	{r4, lr}
    6d70:	460c      	mov	r4, r1
    6d72:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
    6d76:	f7fe fe6b 	bl	5a50 <_lseek_r>
    6d7a:	1c43      	adds	r3, r0, #1
    6d7c:	89a3      	ldrh	r3, [r4, #12]
    6d7e:	bf15      	itete	ne
    6d80:	6560      	strne	r0, [r4, #84]	; 0x54
    6d82:	f423 5380 	biceq.w	r3, r3, #4096	; 0x1000
    6d86:	f443 5380 	orrne.w	r3, r3, #4096	; 0x1000
    6d8a:	81a3      	strheq	r3, [r4, #12]
    6d8c:	bf18      	it	ne
    6d8e:	81a3      	strhne	r3, [r4, #12]
    6d90:	bd10      	pop	{r4, pc}

00006d92 <__sclose>:
    6d92:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
    6d96:	f7fe bd89 	b.w	58ac <_close_r>

00006d9a <__swhatbuf_r>:
    6d9a:	b570      	push	{r4, r5, r6, lr}
    6d9c:	460e      	mov	r6, r1
    6d9e:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
    6da2:	2900      	cmp	r1, #0
    6da4:	b096      	sub	sp, #88	; 0x58
    6da6:	4614      	mov	r4, r2
    6da8:	461d      	mov	r5, r3
    6daa:	da07      	bge.n	6dbc <__swhatbuf_r+0x22>
    6dac:	2300      	movs	r3, #0
    6dae:	602b      	str	r3, [r5, #0]
    6db0:	89b3      	ldrh	r3, [r6, #12]
    6db2:	061a      	lsls	r2, r3, #24
    6db4:	d410      	bmi.n	6dd8 <__swhatbuf_r+0x3e>
    6db6:	f44f 6380 	mov.w	r3, #1024	; 0x400
    6dba:	e00e      	b.n	6dda <__swhatbuf_r+0x40>
    6dbc:	466a      	mov	r2, sp
    6dbe:	f7fe fef9 	bl	5bb4 <_fstat_r>
    6dc2:	2800      	cmp	r0, #0
    6dc4:	dbf2      	blt.n	6dac <__swhatbuf_r+0x12>
    6dc6:	9a01      	ldr	r2, [sp, #4]
    6dc8:	f402 4270 	and.w	r2, r2, #61440	; 0xf000
    6dcc:	f5a2 5300 	sub.w	r3, r2, #8192	; 0x2000
    6dd0:	425a      	negs	r2, r3
    6dd2:	415a      	adcs	r2, r3
    6dd4:	602a      	str	r2, [r5, #0]
    6dd6:	e7ee      	b.n	6db6 <__swhatbuf_r+0x1c>
    6dd8:	2340      	movs	r3, #64	; 0x40
    6dda:	2000      	movs	r0, #0
    6ddc:	6023      	str	r3, [r4, #0]
    6dde:	b016      	add	sp, #88	; 0x58
    6de0:	bd70      	pop	{r4, r5, r6, pc}
	...

00006de4 <z_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    6de4:	f7fc bc14 	b.w	3610 <SystemInit>
