/* * Generated by gen_defines.py * * DTS input file: * /home/santos/Documents/FirmwareLifeFinder/life_finder_nrfconn_3x/build/life_finder_nrfconn_3x/zephyr/zephyr.dts.pre * * Directories with bindings: * /home/santos/ncs/v3.0.2/nrf/dts/bindings, $ZEPHYR_BASE/dts/bindings * * Node dependency ordering (ordinal and path): * 0 / * 1 /aliases * 2 /analog-connector * 3 /chosen * 4 /connector * 5 /entropy_bt_hci * 6 /gpio_fwd * 7 /nrf-gpio-forwarder * 8 /soc * 9 /soc/interrupt-controller@e000e100 * 10 /soc/peripheral@50000000 * 11 /soc/peripheral@50000000/timer@10000 * 12 /sw-pwm * 13 /soc/peripheral@50000000/adc@e000 * 14 /soc/gpiote@5000d000 * 15 /soc/peripheral@50000000/gpio@842500 * 16 /soc/peripheral@50000000/gpio@842800 * 17 /zephyr,user * 18 /buttons * 19 /buttons/button_0 * 20 /buttons/button_1 * 21 /buttons/button_2 * 22 /buttons/button_3 * 23 /cpus * 24 /cpus/cpu@0 * 25 /cpus/cpu@0/itm@e0000000 * 26 /cpus/cpu@0/mpu@e000ed90 * 27 /ipc * 28 /reserved-memory * 29 /reserved-memory/memory@20078000 * 30 /soc/peripheral@50000000/mbox@2a000 * 31 /ipc/ipc1 * 32 /reserved-memory/memory@20070000 * 33 /ipc/ipc0 * 34 /ipc/ipc0/bt_hci_ipc0 * 35 /leds * 36 /leds/led_0 * 37 /leds/led_1 * 38 /leds/led_2 * 39 /leds/led_3 * 40 /pin-controller * 41 /pin-controller/spi3_st7789v_default * 42 /pin-controller/spi3_st7789v_sleep * 43 /soc/peripheral@50000000/spi@c000 * 44 /mipi_dbi_st7789v * 45 /mipi_dbi_st7789v/st7789v@0 * 46 /pin-controller/i2c1_default * 47 /pin-controller/i2c1_default/group1 * 48 /pin-controller/i2c1_sleep * 49 /pin-controller/i2c1_sleep/group1 * 50 /pin-controller/pwm0_backlight_default * 51 /pin-controller/pwm0_backlight_default/group1 * 52 /pin-controller/pwm0_backlight_sleep * 53 /pin-controller/pwm0_backlight_sleep/group1 * 54 /pin-controller/pwm0_sleep * 55 /pin-controller/pwm0_sleep/group1 * 56 /pin-controller/pwm2_motor_default * 57 /pin-controller/pwm2_motor_default/group1 * 58 /pin-controller/pwm2_motor_sleep * 59 /pin-controller/pwm2_motor_sleep/group1 * 60 /pin-controller/pwm3_buzzer_default * 61 /pin-controller/pwm3_buzzer_default/group1 * 62 /pin-controller/pwm3_buzzer_sleep * 63 /pin-controller/pwm3_buzzer_sleep/group1 * 64 /pin-controller/qspi_default * 65 /pin-controller/qspi_default/group1 * 66 /pin-controller/qspi_sleep * 67 /pin-controller/qspi_sleep/group1 * 68 /pin-controller/qspi_sleep/group2 * 69 /pin-controller/spi0_sx128x_default * 70 /pin-controller/spi0_sx128x_default/group1 * 71 /pin-controller/spi0_sx128x_sleep * 72 /pin-controller/spi0_sx128x_sleep/group1 * 73 /pin-controller/spi3_st7789v_default/group1 * 74 /pin-controller/spi3_st7789v_sleep/group1 * 75 /pin-controller/spi4_default * 76 /pin-controller/spi4_default/group1 * 77 /pin-controller/spi4_sleep * 78 /pin-controller/spi4_sleep/group1 * 79 /pin-controller/uart0_default * 80 /pin-controller/uart0_default/group1 * 81 /pin-controller/uart0_default/group2 * 82 /pin-controller/uart0_sleep * 83 /pin-controller/uart0_sleep/group1 * 84 /pin-controller/uart1_default * 85 /pin-controller/uart1_default/group1 * 86 /pin-controller/uart1_default/group2 * 87 /pin-controller/uart1_sleep * 88 /pin-controller/uart1_sleep/group1 * 89 /pin-controller/uart2_default * 90 /pin-controller/uart2_default/group1 * 91 /pin-controller/uart2_default/group2 * 92 /pin-controller/uart2_sleep * 93 /pin-controller/uart2_sleep/group1 * 94 /pins_io * 95 /pins_io/en_motor * 96 /pins_io/key1 * 97 /soc/peripheral@50000000/pwm@21000 * 98 /soc/peripheral@50000000/pwm@23000 * 99 /soc/peripheral@50000000/pwm@24000 * 100 /pwmleds * 101 /pwmleds/backlight * 102 /pwmleds/buzzer * 103 /pwmleds/motor * 104 /pwmleds/pwm_led_0 * 105 /reserved-memory/image@20000000 * 106 /reserved-memory/image_ns@20040000 * 107 /reserved-memory/image_ns_app@20040000 * 108 /reserved-memory/image_s@20000000 * 109 /soc/crypto@50844000 * 110 /soc/ficr@ff0000 * 111 /soc/gpiote@4002f000 * 112 /soc/memory@20000000 * 113 /soc/spu@50003000 * 114 /soc/timer@e000e010 * 115 /soc/uicr@ff8000 * 116 /soc/peripheral@50000000/clock@5000 * 117 /soc/peripheral@50000000/comparator@1a000 * 118 /soc/peripheral@50000000/ctrlap@6000 * 119 /soc/peripheral@50000000/dcnf@0 * 120 /soc/peripheral@50000000/dppic@17000 * 121 /soc/peripheral@50000000/egu@1b000 * 122 /soc/peripheral@50000000/egu@1c000 * 123 /soc/peripheral@50000000/egu@1d000 * 124 /soc/peripheral@50000000/egu@1e000 * 125 /soc/peripheral@50000000/egu@1f000 * 126 /soc/peripheral@50000000/egu@20000 * 127 /soc/peripheral@50000000/i2c@8000 * 128 /soc/peripheral@50000000/i2c@b000 * 129 /soc/peripheral@50000000/i2c@c000 * 130 /soc/peripheral@50000000/i2s@28000 * 131 /soc/peripheral@50000000/ieee802154 * 132 /soc/peripheral@50000000/kmu@39000 * 133 /soc/peripheral@50000000/mutex@30000 * 134 /soc/peripheral@50000000/nfct@2d000 * 135 /soc/peripheral@50000000/pdm@26000 * 136 /soc/peripheral@50000000/pwm@22000 * 137 /soc/peripheral@50000000/qdec@33000 * 138 /soc/peripheral@50000000/qdec@34000 * 139 /soc/peripheral@50000000/regulator@37000 * 140 /soc/peripheral@50000000/reset-controller@5000 * 141 /soc/peripheral@50000000/rtc@14000 * 142 /soc/peripheral@50000000/rtc@15000 * 143 /soc/peripheral@50000000/spi@9000 * 144 /soc/peripheral@50000000/spi@a000 * 145 /soc/peripheral@50000000/spi@b000 * 146 /soc/peripheral@50000000/timer@f000 * 147 /soc/peripheral@50000000/timer@11000 * 148 /soc/peripheral@50000000/uart@8000 * 149 /soc/peripheral@50000000/uart@9000 * 150 /soc/peripheral@50000000/uart@b000 * 151 /soc/peripheral@50000000/uart@c000 * 152 /soc/peripheral@50000000/usbd@36000 * 153 /soc/peripheral@50000000/vmc@81000 * 154 /soc/peripheral@50000000/watchdog@18000 * 155 /soc/peripheral@50000000/watchdog@19000 * 156 /soc/peripheral@50000000/adc@e000/channel@5 * 157 /soc/peripheral@50000000/clock-controller@4000 * 158 /soc/peripheral@50000000/clock-controller@4000/hfxo * 159 /soc/peripheral@50000000/clock-controller@4000/lfxo * 160 /soc/peripheral@50000000/flash-controller@39000 * 161 /soc/peripheral@50000000/flash-controller@39000/flash@0 * 162 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions * 163 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0 * 164 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000 * 165 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000 * 166 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000 * 167 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000 * 168 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f0000 * 169 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f4000 * 170 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f6000 * 171 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f8000 * 172 /soc/peripheral@50000000/i2c@9000 * 173 /soc/peripheral@50000000/i2c@9000/bmi270@68 * 174 /soc/peripheral@50000000/i2c@9000/rv-8263-c8@51 * 175 /soc/peripheral@50000000/power@5000 * 176 /soc/peripheral@50000000/power@5000/gpregret1@51c * 177 /soc/peripheral@50000000/power@5000/gpregret2@520 * 178 /soc/peripheral@50000000/qspi@2b000 * 179 /soc/peripheral@50000000/qspi@2b000/mx25r6435f@0 * 180 /soc/peripheral@50000000/qspi@2b000/mx25r8035f@0 * 181 /soc/peripheral@50000000/regulator@4000 * 182 /soc/peripheral@50000000/regulator@4000/regulator@4704 * 183 /soc/peripheral@50000000/regulator@4000/regulator@4904 * 184 /soc/peripheral@50000000/regulator@4000/regulator@4b00 * 185 /soc/peripheral@50000000/spi@8000 * 186 /soc/peripheral@50000000/spi@8000/sx1280@0 * * Definitions derived from these nodes in dependency order are next, * followed by /chosen nodes. */ /* Used to remove brackets from around a single argument */ #define DT_DEBRACKET_INTERNAL(...) __VA_ARGS__ /* * Devicetree node: / * * Node identifier: DT_N */ /* Node's full path: */ #define DT_N_PATH "/" /* Node's name with unit-address: */ #define DT_N_FULL_NAME "/" #define DT_N_FULL_NAME_UNQUOTED / #define DT_N_FULL_NAME_TOKEN _ #define DT_N_FULL_NAME_UPPER_TOKEN _ /* Helpers for dealing with node labels: */ #define DT_N_NODELABEL_NUM 0 #define DT_N_FOREACH_NODELABEL(fn) #define DT_N_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_FOREACH_ANCESTOR(fn) /* Helper macros for child nodes of this node. */ #define DT_N_CHILD_NUM 19 #define DT_N_CHILD_NUM_STATUS_OKAY 14 #define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_sw_pwm) fn(DT_N_S_cpus) fn(DT_N_S_ipc) fn(DT_N_S_leds) fn(DT_N_S_buttons) fn(DT_N_S_connector) fn(DT_N_S_pwmleds) fn(DT_N_S_analog_connector) fn(DT_N_S_nrf_gpio_forwarder) fn(DT_N_S_reserved_memory) fn(DT_N_S_gpio_fwd) fn(DT_N_S_mipi_dbi_st7789v) fn(DT_N_S_pins_io) fn(DT_N_S_zephyr_user) #define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sw_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_nrf_gpio_forwarder) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_fwd) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mipi_dbi_st7789v) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pins_io) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user) #define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_sw_pwm, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_ipc, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__) fn(DT_N_S_nrf_gpio_forwarder, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_gpio_fwd, __VA_ARGS__) fn(DT_N_S_mipi_dbi_st7789v, __VA_ARGS__) fn(DT_N_S_pins_io, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) #define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sw_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_nrf_gpio_forwarder, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_fwd, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mipi_dbi_st7789v, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pins_io, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user, __VA_ARGS__) #define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_ipc) fn(DT_N_S_leds) fn(DT_N_S_buttons) fn(DT_N_S_pwmleds) fn(DT_N_S_reserved_memory) fn(DT_N_S_mipi_dbi_st7789v) fn(DT_N_S_pins_io) fn(DT_N_S_zephyr_user) #define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mipi_dbi_st7789v) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pins_io) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user) #define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_ipc, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_mipi_dbi_st7789v, __VA_ARGS__) fn(DT_N_S_pins_io, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) #define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mipi_dbi_st7789v, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pins_io, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_ORD 0 #define DT_N_ORD_STR_SORTABLE 00000 /* Ordinals for what this node depends on directly: */ #define DT_N_REQUIRES_ORDS /* nothing */ /* Ordinals for what depends directly on this node: */ #define DT_N_SUPPORTS_ORDS \ 1, /* /aliases */ \ 2, /* /analog-connector */ \ 3, /* /chosen */ \ 4, /* /connector */ \ 5, /* /entropy_bt_hci */ \ 6, /* /gpio_fwd */ \ 7, /* /nrf-gpio-forwarder */ \ 8, /* /soc */ \ 12, /* /sw-pwm */ \ 17, /* /zephyr,user */ \ 18, /* /buttons */ \ 23, /* /cpus */ \ 27, /* /ipc */ \ 28, /* /reserved-memory */ \ 35, /* /leds */ \ 40, /* /pin-controller */ \ 44, /* /mipi_dbi_st7789v */ \ 94, /* /pins_io */ \ 100, /* /pwmleds */ /* Existence and alternate IDs: */ #define DT_N_EXISTS 1 #define DT_N_INST_0_nordic_nrf5340_dk_nrf5340_cpuapp DT_N /* Macros for properties that are special in the specification: */ #define DT_N_REG_NUM 0 #define DT_N_RANGES_NUM 0 #define DT_N_FOREACH_RANGE(fn) #define DT_N_IRQ_NUM 0 #define DT_N_IRQ_LEVEL 0 #define DT_N_COMPAT_MATCHES_nordic_nrf5340_dk_nrf5340_cpuapp 1 #define DT_N_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_COMPAT_MODEL_IDX_0 "nrf5340-dk-nrf5340-cpuapp" #define DT_N_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_P_compatible {"nordic,nrf5340-dk-nrf5340-cpuapp"} #define DT_N_P_compatible_IDX_0_EXISTS 1 #define DT_N_P_compatible_IDX_0 "nordic,nrf5340-dk-nrf5340-cpuapp" #define DT_N_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf5340-dk-nrf5340-cpuapp #define DT_N_P_compatible_IDX_0_STRING_TOKEN nordic_nrf5340_dk_nrf5340_cpuapp #define DT_N_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF5340_DK_NRF5340_CPUAPP #define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0) #define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N, compatible, 0) #define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__) #define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N, compatible, 0, __VA_ARGS__) #define DT_N_P_compatible_LEN 1 #define DT_N_P_compatible_EXISTS 1 /* * Devicetree node: /aliases * * Node identifier: DT_N_S_aliases */ /* Node's full path: */ #define DT_N_S_aliases_PATH "/aliases" /* Node's name with unit-address: */ #define DT_N_S_aliases_FULL_NAME "aliases" #define DT_N_S_aliases_FULL_NAME_UNQUOTED aliases #define DT_N_S_aliases_FULL_NAME_TOKEN aliases #define DT_N_S_aliases_FULL_NAME_UPPER_TOKEN ALIASES /* Node parent (/) identifier: */ #define DT_N_S_aliases_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_aliases_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_aliases_NODELABEL_NUM 0 #define DT_N_S_aliases_FOREACH_NODELABEL(fn) #define DT_N_S_aliases_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_aliases_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_aliases_CHILD_NUM 0 #define DT_N_S_aliases_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_aliases_FOREACH_CHILD(fn) #define DT_N_S_aliases_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_aliases_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_aliases_ORD 1 #define DT_N_S_aliases_ORD_STR_SORTABLE 00001 /* Ordinals for what this node depends on directly: */ #define DT_N_S_aliases_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_aliases_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_aliases_REG_NUM 0 #define DT_N_S_aliases_RANGES_NUM 0 #define DT_N_S_aliases_FOREACH_RANGE(fn) #define DT_N_S_aliases_IRQ_NUM 0 #define DT_N_S_aliases_IRQ_LEVEL 0 #define DT_N_S_aliases_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_aliases_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /analog-connector * * Node identifier: DT_N_S_analog_connector * * Binding (compatible = arduino,uno-adc): * $ZEPHYR_BASE/dts/bindings/adc/arduino,uno-adc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_analog_connector_PATH "/analog-connector" /* Node's name with unit-address: */ #define DT_N_S_analog_connector_FULL_NAME "analog-connector" #define DT_N_S_analog_connector_FULL_NAME_UNQUOTED analog-connector #define DT_N_S_analog_connector_FULL_NAME_TOKEN analog_connector #define DT_N_S_analog_connector_FULL_NAME_UPPER_TOKEN ANALOG_CONNECTOR /* Node parent (/) identifier: */ #define DT_N_S_analog_connector_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_analog_connector_CHILD_IDX 12 /* Helpers for dealing with node labels: */ #define DT_N_S_analog_connector_NODELABEL_NUM 1 #define DT_N_S_analog_connector_FOREACH_NODELABEL(fn) fn(arduino_adc) #define DT_N_S_analog_connector_FOREACH_NODELABEL_VARGS(fn, ...) fn(arduino_adc, __VA_ARGS__) #define DT_N_S_analog_connector_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_analog_connector_CHILD_NUM 0 #define DT_N_S_analog_connector_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_analog_connector_FOREACH_CHILD(fn) #define DT_N_S_analog_connector_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_analog_connector_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_analog_connector_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_analog_connector_ORD 2 #define DT_N_S_analog_connector_ORD_STR_SORTABLE 00002 /* Ordinals for what this node depends on directly: */ #define DT_N_S_analog_connector_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_analog_connector_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_analog_connector_EXISTS 1 #define DT_N_INST_0_arduino_uno_adc DT_N_S_analog_connector #define DT_N_NODELABEL_arduino_adc DT_N_S_analog_connector /* Macros for properties that are special in the specification: */ #define DT_N_S_analog_connector_REG_NUM 0 #define DT_N_S_analog_connector_RANGES_NUM 0 #define DT_N_S_analog_connector_FOREACH_RANGE(fn) #define DT_N_S_analog_connector_IRQ_NUM 0 #define DT_N_S_analog_connector_IRQ_LEVEL 0 #define DT_N_S_analog_connector_COMPAT_MATCHES_arduino_uno_adc 1 #define DT_N_S_analog_connector_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_analog_connector_COMPAT_VENDOR_IDX_0 "Arduino" #define DT_N_S_analog_connector_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_analog_connector_COMPAT_MODEL_IDX_0 "uno-adc" #define DT_N_S_analog_connector_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_analog_connector_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_analog_connector_P_status "disabled" #define DT_N_S_analog_connector_P_status_STRING_UNQUOTED disabled #define DT_N_S_analog_connector_P_status_STRING_TOKEN disabled #define DT_N_S_analog_connector_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_analog_connector_P_status_IDX_0 "disabled" #define DT_N_S_analog_connector_P_status_IDX_0_EXISTS 1 #define DT_N_S_analog_connector_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_analog_connector_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_analog_connector_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_analog_connector, status, 0) #define DT_N_S_analog_connector_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_analog_connector, status, 0) #define DT_N_S_analog_connector_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_analog_connector, status, 0, __VA_ARGS__) #define DT_N_S_analog_connector_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_analog_connector, status, 0, __VA_ARGS__) #define DT_N_S_analog_connector_P_status_LEN 1 #define DT_N_S_analog_connector_P_status_EXISTS 1 #define DT_N_S_analog_connector_P_compatible {"arduino,uno-adc"} #define DT_N_S_analog_connector_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_analog_connector_P_compatible_IDX_0 "arduino,uno-adc" #define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_UNQUOTED arduino,uno-adc #define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_TOKEN arduino_uno_adc #define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_UNO_ADC #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_analog_connector, compatible, 0) #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_analog_connector, compatible, 0) #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_analog_connector, compatible, 0, __VA_ARGS__) #define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_analog_connector, compatible, 0, __VA_ARGS__) #define DT_N_S_analog_connector_P_compatible_LEN 1 #define DT_N_S_analog_connector_P_compatible_EXISTS 1 #define DT_N_S_analog_connector_P_zephyr_deferred_init 0 #define DT_N_S_analog_connector_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_analog_connector_P_wakeup_source 0 #define DT_N_S_analog_connector_P_wakeup_source_EXISTS 1 #define DT_N_S_analog_connector_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_analog_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /chosen * * Node identifier: DT_N_S_chosen */ /* Node's full path: */ #define DT_N_S_chosen_PATH "/chosen" /* Node's name with unit-address: */ #define DT_N_S_chosen_FULL_NAME "chosen" #define DT_N_S_chosen_FULL_NAME_UNQUOTED chosen #define DT_N_S_chosen_FULL_NAME_TOKEN chosen #define DT_N_S_chosen_FULL_NAME_UPPER_TOKEN CHOSEN /* Node parent (/) identifier: */ #define DT_N_S_chosen_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_chosen_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_chosen_NODELABEL_NUM 0 #define DT_N_S_chosen_FOREACH_NODELABEL(fn) #define DT_N_S_chosen_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_chosen_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_chosen_CHILD_NUM 0 #define DT_N_S_chosen_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_chosen_FOREACH_CHILD(fn) #define DT_N_S_chosen_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_chosen_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_chosen_ORD 3 #define DT_N_S_chosen_ORD_STR_SORTABLE 00003 /* Ordinals for what this node depends on directly: */ #define DT_N_S_chosen_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_chosen_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_chosen_REG_NUM 0 #define DT_N_S_chosen_RANGES_NUM 0 #define DT_N_S_chosen_FOREACH_RANGE(fn) #define DT_N_S_chosen_IRQ_NUM 0 #define DT_N_S_chosen_IRQ_LEVEL 0 #define DT_N_S_chosen_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_chosen_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /connector * * Node identifier: DT_N_S_connector * * Binding (compatible = arduino-header-r3): * $ZEPHYR_BASE/dts/bindings/gpio/arduino-header-r3.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_connector_PATH "/connector" /* Node's name with unit-address: */ #define DT_N_S_connector_FULL_NAME "connector" #define DT_N_S_connector_FULL_NAME_UNQUOTED connector #define DT_N_S_connector_FULL_NAME_TOKEN connector #define DT_N_S_connector_FULL_NAME_UPPER_TOKEN CONNECTOR /* Node parent (/) identifier: */ #define DT_N_S_connector_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_connector_CHILD_IDX 10 /* Helpers for dealing with node labels: */ #define DT_N_S_connector_NODELABEL_NUM 1 #define DT_N_S_connector_FOREACH_NODELABEL(fn) fn(arduino_header) #define DT_N_S_connector_FOREACH_NODELABEL_VARGS(fn, ...) fn(arduino_header, __VA_ARGS__) #define DT_N_S_connector_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_connector_CHILD_NUM 0 #define DT_N_S_connector_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_connector_FOREACH_CHILD(fn) #define DT_N_S_connector_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_connector_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_connector_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_connector_ORD 4 #define DT_N_S_connector_ORD_STR_SORTABLE 00004 /* Ordinals for what this node depends on directly: */ #define DT_N_S_connector_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_connector_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_connector_EXISTS 1 #define DT_N_INST_0_arduino_header_r3 DT_N_S_connector #define DT_N_NODELABEL_arduino_header DT_N_S_connector /* Macros for properties that are special in the specification: */ #define DT_N_S_connector_REG_NUM 0 #define DT_N_S_connector_RANGES_NUM 0 #define DT_N_S_connector_FOREACH_RANGE(fn) #define DT_N_S_connector_IRQ_NUM 0 #define DT_N_S_connector_IRQ_LEVEL 0 #define DT_N_S_connector_COMPAT_MATCHES_arduino_header_r3 1 #define DT_N_S_connector_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_connector_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_connector_P_status "disabled" #define DT_N_S_connector_P_status_STRING_UNQUOTED disabled #define DT_N_S_connector_P_status_STRING_TOKEN disabled #define DT_N_S_connector_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_connector_P_status_IDX_0 "disabled" #define DT_N_S_connector_P_status_IDX_0_EXISTS 1 #define DT_N_S_connector_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_connector_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_connector_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, status, 0) #define DT_N_S_connector_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, status, 0) #define DT_N_S_connector_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, status, 0, __VA_ARGS__) #define DT_N_S_connector_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, status, 0, __VA_ARGS__) #define DT_N_S_connector_P_status_LEN 1 #define DT_N_S_connector_P_status_EXISTS 1 #define DT_N_S_connector_P_compatible {"arduino-header-r3"} #define DT_N_S_connector_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_connector_P_compatible_IDX_0 "arduino-header-r3" #define DT_N_S_connector_P_compatible_IDX_0_STRING_UNQUOTED arduino-header-r3 #define DT_N_S_connector_P_compatible_IDX_0_STRING_TOKEN arduino_header_r3 #define DT_N_S_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_HEADER_R3 #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, compatible, 0) #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, compatible, 0) #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__) #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__) #define DT_N_S_connector_P_compatible_LEN 1 #define DT_N_S_connector_P_compatible_EXISTS 1 #define DT_N_S_connector_P_zephyr_deferred_init 0 #define DT_N_S_connector_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_connector_P_wakeup_source 0 #define DT_N_S_connector_P_wakeup_source_EXISTS 1 #define DT_N_S_connector_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /entropy_bt_hci * * Node identifier: DT_N_S_entropy_bt_hci * * Binding (compatible = zephyr,bt-hci-entropy): * $ZEPHYR_BASE/dts/bindings/bluetooth/zephyr,bt-hci-entropy.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_entropy_bt_hci_PATH "/entropy_bt_hci" /* Node's name with unit-address: */ #define DT_N_S_entropy_bt_hci_FULL_NAME "entropy_bt_hci" #define DT_N_S_entropy_bt_hci_FULL_NAME_UNQUOTED entropy_bt_hci #define DT_N_S_entropy_bt_hci_FULL_NAME_TOKEN entropy_bt_hci #define DT_N_S_entropy_bt_hci_FULL_NAME_UPPER_TOKEN ENTROPY_BT_HCI /* Node parent (/) identifier: */ #define DT_N_S_entropy_bt_hci_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_entropy_bt_hci_CHILD_IDX 4 /* Helpers for dealing with node labels: */ #define DT_N_S_entropy_bt_hci_NODELABEL_NUM 1 #define DT_N_S_entropy_bt_hci_FOREACH_NODELABEL(fn) fn(rng_hci) #define DT_N_S_entropy_bt_hci_FOREACH_NODELABEL_VARGS(fn, ...) fn(rng_hci, __VA_ARGS__) #define DT_N_S_entropy_bt_hci_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_entropy_bt_hci_CHILD_NUM 0 #define DT_N_S_entropy_bt_hci_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_entropy_bt_hci_FOREACH_CHILD(fn) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_entropy_bt_hci_ORD 5 #define DT_N_S_entropy_bt_hci_ORD_STR_SORTABLE 00005 /* Ordinals for what this node depends on directly: */ #define DT_N_S_entropy_bt_hci_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_entropy_bt_hci_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_entropy_bt_hci_EXISTS 1 #define DT_N_INST_0_zephyr_bt_hci_entropy DT_N_S_entropy_bt_hci #define DT_N_NODELABEL_rng_hci DT_N_S_entropy_bt_hci /* Macros for properties that are special in the specification: */ #define DT_N_S_entropy_bt_hci_REG_NUM 0 #define DT_N_S_entropy_bt_hci_RANGES_NUM 0 #define DT_N_S_entropy_bt_hci_FOREACH_RANGE(fn) #define DT_N_S_entropy_bt_hci_IRQ_NUM 0 #define DT_N_S_entropy_bt_hci_IRQ_LEVEL 0 #define DT_N_S_entropy_bt_hci_COMPAT_MATCHES_zephyr_bt_hci_entropy 1 #define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding" #define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0 "bt-hci-entropy" #define DT_N_S_entropy_bt_hci_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_entropy_bt_hci_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_entropy_bt_hci_P_status "okay" #define DT_N_S_entropy_bt_hci_P_status_STRING_UNQUOTED okay #define DT_N_S_entropy_bt_hci_P_status_STRING_TOKEN okay #define DT_N_S_entropy_bt_hci_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_entropy_bt_hci_P_status_IDX_0 "okay" #define DT_N_S_entropy_bt_hci_P_status_IDX_0_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_entropy_bt_hci_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, status, 0) #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, status, 0) #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__) #define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__) #define DT_N_S_entropy_bt_hci_P_status_LEN 1 #define DT_N_S_entropy_bt_hci_P_status_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_compatible {"zephyr,bt-hci-entropy"} #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0 "zephyr,bt-hci-entropy" #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UNQUOTED zephyr,bt-hci-entropy #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_entropy #define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_ENTROPY #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, compatible, 0) #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, compatible, 0) #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__) #define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__) #define DT_N_S_entropy_bt_hci_P_compatible_LEN 1 #define DT_N_S_entropy_bt_hci_P_compatible_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_zephyr_deferred_init 0 #define DT_N_S_entropy_bt_hci_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_wakeup_source 0 #define DT_N_S_entropy_bt_hci_P_wakeup_source_EXISTS 1 #define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /gpio_fwd * * Node identifier: DT_N_S_gpio_fwd */ /* Node's full path: */ #define DT_N_S_gpio_fwd_PATH "/gpio_fwd" /* Node's name with unit-address: */ #define DT_N_S_gpio_fwd_FULL_NAME "gpio_fwd" #define DT_N_S_gpio_fwd_FULL_NAME_UNQUOTED gpio_fwd #define DT_N_S_gpio_fwd_FULL_NAME_TOKEN gpio_fwd #define DT_N_S_gpio_fwd_FULL_NAME_UPPER_TOKEN GPIO_FWD /* Node parent (/) identifier: */ #define DT_N_S_gpio_fwd_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_gpio_fwd_CHILD_IDX 15 /* Helpers for dealing with node labels: */ #define DT_N_S_gpio_fwd_NODELABEL_NUM 0 #define DT_N_S_gpio_fwd_FOREACH_NODELABEL(fn) #define DT_N_S_gpio_fwd_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_gpio_fwd_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_gpio_fwd_CHILD_NUM 0 #define DT_N_S_gpio_fwd_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_gpio_fwd_FOREACH_CHILD(fn) #define DT_N_S_gpio_fwd_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_gpio_fwd_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_gpio_fwd_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_gpio_fwd_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_gpio_fwd_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_gpio_fwd_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_gpio_fwd_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_gpio_fwd_ORD 6 #define DT_N_S_gpio_fwd_ORD_STR_SORTABLE 00006 /* Ordinals for what this node depends on directly: */ #define DT_N_S_gpio_fwd_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_gpio_fwd_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_gpio_fwd_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_gpio_fwd_REG_NUM 0 #define DT_N_S_gpio_fwd_RANGES_NUM 0 #define DT_N_S_gpio_fwd_FOREACH_RANGE(fn) #define DT_N_S_gpio_fwd_IRQ_NUM 0 #define DT_N_S_gpio_fwd_IRQ_LEVEL 0 #define DT_N_S_gpio_fwd_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_gpio_fwd_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_gpio_fwd_P_status "disabled" #define DT_N_S_gpio_fwd_P_status_STRING_UNQUOTED disabled #define DT_N_S_gpio_fwd_P_status_STRING_TOKEN disabled #define DT_N_S_gpio_fwd_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_gpio_fwd_P_status_IDX_0 "disabled" #define DT_N_S_gpio_fwd_P_status_IDX_0_EXISTS 1 #define DT_N_S_gpio_fwd_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_gpio_fwd_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_gpio_fwd_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_fwd, status, 0) #define DT_N_S_gpio_fwd_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_fwd, status, 0) #define DT_N_S_gpio_fwd_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_fwd, status, 0, __VA_ARGS__) #define DT_N_S_gpio_fwd_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_fwd, status, 0, __VA_ARGS__) #define DT_N_S_gpio_fwd_P_status_LEN 1 #define DT_N_S_gpio_fwd_P_status_EXISTS 1 /* * Devicetree node: /nrf-gpio-forwarder * * Node identifier: DT_N_S_nrf_gpio_forwarder * * Binding (compatible = nordic,nrf-gpio-forwarder): * $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpio-forwarder.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_nrf_gpio_forwarder_PATH "/nrf-gpio-forwarder" /* Node's name with unit-address: */ #define DT_N_S_nrf_gpio_forwarder_FULL_NAME "nrf-gpio-forwarder" #define DT_N_S_nrf_gpio_forwarder_FULL_NAME_UNQUOTED nrf-gpio-forwarder #define DT_N_S_nrf_gpio_forwarder_FULL_NAME_TOKEN nrf_gpio_forwarder #define DT_N_S_nrf_gpio_forwarder_FULL_NAME_UPPER_TOKEN NRF_GPIO_FORWARDER /* Node parent (/) identifier: */ #define DT_N_S_nrf_gpio_forwarder_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_nrf_gpio_forwarder_CHILD_IDX 13 /* Helpers for dealing with node labels: */ #define DT_N_S_nrf_gpio_forwarder_NODELABEL_NUM 1 #define DT_N_S_nrf_gpio_forwarder_FOREACH_NODELABEL(fn) fn(gpio_fwd) #define DT_N_S_nrf_gpio_forwarder_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpio_fwd, __VA_ARGS__) #define DT_N_S_nrf_gpio_forwarder_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_nrf_gpio_forwarder_CHILD_NUM 0 #define DT_N_S_nrf_gpio_forwarder_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD(fn) #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_nrf_gpio_forwarder_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_nrf_gpio_forwarder_ORD 7 #define DT_N_S_nrf_gpio_forwarder_ORD_STR_SORTABLE 00007 /* Ordinals for what this node depends on directly: */ #define DT_N_S_nrf_gpio_forwarder_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_nrf_gpio_forwarder_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_nrf_gpio_forwarder_EXISTS 1 #define DT_N_INST_0_nordic_nrf_gpio_forwarder DT_N_S_nrf_gpio_forwarder #define DT_N_NODELABEL_gpio_fwd DT_N_S_nrf_gpio_forwarder /* Macros for properties that are special in the specification: */ #define DT_N_S_nrf_gpio_forwarder_REG_NUM 0 #define DT_N_S_nrf_gpio_forwarder_RANGES_NUM 0 #define DT_N_S_nrf_gpio_forwarder_FOREACH_RANGE(fn) #define DT_N_S_nrf_gpio_forwarder_IRQ_NUM 0 #define DT_N_S_nrf_gpio_forwarder_IRQ_LEVEL 0 #define DT_N_S_nrf_gpio_forwarder_COMPAT_MATCHES_nordic_nrf_gpio_forwarder 1 #define DT_N_S_nrf_gpio_forwarder_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_nrf_gpio_forwarder_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_nrf_gpio_forwarder_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_nrf_gpio_forwarder_COMPAT_MODEL_IDX_0 "nrf-gpio-forwarder" #define DT_N_S_nrf_gpio_forwarder_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_nrf_gpio_forwarder_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_nrf_gpio_forwarder_P_status "disabled" #define DT_N_S_nrf_gpio_forwarder_P_status_STRING_UNQUOTED disabled #define DT_N_S_nrf_gpio_forwarder_P_status_STRING_TOKEN disabled #define DT_N_S_nrf_gpio_forwarder_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_nrf_gpio_forwarder_P_status_IDX_0 "disabled" #define DT_N_S_nrf_gpio_forwarder_P_status_IDX_0_EXISTS 1 #define DT_N_S_nrf_gpio_forwarder_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_nrf_gpio_forwarder_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_nrf_gpio_forwarder_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_nrf_gpio_forwarder, status, 0) #define DT_N_S_nrf_gpio_forwarder_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_nrf_gpio_forwarder, status, 0) #define DT_N_S_nrf_gpio_forwarder_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_nrf_gpio_forwarder, status, 0, __VA_ARGS__) #define DT_N_S_nrf_gpio_forwarder_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_nrf_gpio_forwarder, status, 0, __VA_ARGS__) #define DT_N_S_nrf_gpio_forwarder_P_status_LEN 1 #define DT_N_S_nrf_gpio_forwarder_P_status_EXISTS 1 #define DT_N_S_nrf_gpio_forwarder_P_compatible {"nordic,nrf-gpio-forwarder"} #define DT_N_S_nrf_gpio_forwarder_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_nrf_gpio_forwarder_P_compatible_IDX_0 "nordic,nrf-gpio-forwarder" #define DT_N_S_nrf_gpio_forwarder_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio-forwarder #define DT_N_S_nrf_gpio_forwarder_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio_forwarder #define DT_N_S_nrf_gpio_forwarder_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO_FORWARDER #define DT_N_S_nrf_gpio_forwarder_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_nrf_gpio_forwarder, compatible, 0) #define DT_N_S_nrf_gpio_forwarder_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_nrf_gpio_forwarder, compatible, 0) #define DT_N_S_nrf_gpio_forwarder_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_nrf_gpio_forwarder, compatible, 0, __VA_ARGS__) #define DT_N_S_nrf_gpio_forwarder_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_nrf_gpio_forwarder, compatible, 0, __VA_ARGS__) #define DT_N_S_nrf_gpio_forwarder_P_compatible_LEN 1 #define DT_N_S_nrf_gpio_forwarder_P_compatible_EXISTS 1 #define DT_N_S_nrf_gpio_forwarder_P_zephyr_deferred_init 0 #define DT_N_S_nrf_gpio_forwarder_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_nrf_gpio_forwarder_P_wakeup_source 0 #define DT_N_S_nrf_gpio_forwarder_P_wakeup_source_EXISTS 1 #define DT_N_S_nrf_gpio_forwarder_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_nrf_gpio_forwarder_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc * * Node identifier: DT_N_S_soc */ /* Node's full path: */ #define DT_N_S_soc_PATH "/soc" /* Node's name with unit-address: */ #define DT_N_S_soc_FULL_NAME "soc" #define DT_N_S_soc_FULL_NAME_UNQUOTED soc #define DT_N_S_soc_FULL_NAME_TOKEN soc #define DT_N_S_soc_FULL_NAME_UPPER_TOKEN SOC /* Node parent (/) identifier: */ #define DT_N_S_soc_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_soc_CHILD_IDX 2 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_NODELABEL_NUM 0 #define DT_N_S_soc_FOREACH_NODELABEL(fn) #define DT_N_S_soc_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_soc_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_CHILD_NUM 10 #define DT_N_S_soc_CHILD_NUM_STATUS_OKAY 8 #define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_gpiote_4002f000) fn(DT_N_S_soc_S_crypto_50844000) #define DT_N_S_soc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_4002f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000) #define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_4002f000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) #define DT_N_S_soc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_4002f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_crypto_50844000) #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000) #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_ORD 8 #define DT_N_S_soc_ORD_STR_SORTABLE 00008 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_SUPPORTS_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 14, /* /soc/gpiote@5000d000 */ \ 109, /* /soc/crypto@50844000 */ \ 110, /* /soc/ficr@ff0000 */ \ 111, /* /soc/gpiote@4002f000 */ \ 112, /* /soc/memory@20000000 */ \ 113, /* /soc/spu@50003000 */ \ 114, /* /soc/timer@e000e010 */ \ 115, /* /soc/uicr@ff8000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_EXISTS 1 #define DT_N_INST_0_nordic_nrf5340_cpuapp_qkaa DT_N_S_soc #define DT_N_INST_0_nordic_nrf5340_cpuapp DT_N_S_soc #define DT_N_INST_0_nordic_nrf53 DT_N_S_soc #define DT_N_INST_0_simple_bus DT_N_S_soc /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_REG_NUM 0 #define DT_N_S_soc_RANGES_NUM 0 #define DT_N_S_soc_FOREACH_RANGE(fn) #define DT_N_S_soc_IRQ_NUM 0 #define DT_N_S_soc_IRQ_LEVEL 0 #define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf5340_cpuapp_qkaa 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_COMPAT_MODEL_IDX_0 "nrf5340-cpuapp-qkaa" #define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf5340_cpuapp 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_1_EXISTS 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor" #define DT_N_S_soc_COMPAT_MODEL_IDX_1_EXISTS 1 #define DT_N_S_soc_COMPAT_MODEL_IDX_1 "nrf5340-cpuapp" #define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf53 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_2_EXISTS 1 #define DT_N_S_soc_COMPAT_VENDOR_IDX_2 "Nordic Semiconductor" #define DT_N_S_soc_COMPAT_MODEL_IDX_2_EXISTS 1 #define DT_N_S_soc_COMPAT_MODEL_IDX_2 "nrf53" #define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1 #define DT_N_S_soc_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_P_compatible {"nordic,nrf5340-cpuapp-qkaa", "nordic,nrf5340-cpuapp", "nordic,nrf53", "simple-bus"} #define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_P_compatible_IDX_0 "nordic,nrf5340-cpuapp-qkaa" #define DT_N_S_soc_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf5340-cpuapp-qkaa #define DT_N_S_soc_P_compatible_IDX_0_STRING_TOKEN nordic_nrf5340_cpuapp_qkaa #define DT_N_S_soc_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF5340_CPUAPP_QKAA #define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_P_compatible_IDX_1 "nordic,nrf5340-cpuapp" #define DT_N_S_soc_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf5340-cpuapp #define DT_N_S_soc_P_compatible_IDX_1_STRING_TOKEN nordic_nrf5340_cpuapp #define DT_N_S_soc_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF5340_CPUAPP #define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_P_compatible_IDX_2 "nordic,nrf53" #define DT_N_S_soc_P_compatible_IDX_2_STRING_UNQUOTED nordic,nrf53 #define DT_N_S_soc_P_compatible_IDX_2_STRING_TOKEN nordic_nrf53 #define DT_N_S_soc_P_compatible_IDX_2_STRING_UPPER_TOKEN NORDIC_NRF53 #define DT_N_S_soc_P_compatible_IDX_3_EXISTS 1 #define DT_N_S_soc_P_compatible_IDX_3 "simple-bus" #define DT_N_S_soc_P_compatible_IDX_3_STRING_UNQUOTED simple-bus #define DT_N_S_soc_P_compatible_IDX_3_STRING_TOKEN simple_bus #define DT_N_S_soc_P_compatible_IDX_3_STRING_UPPER_TOKEN SIMPLE_BUS #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0) \ fn(DT_N_S_soc, compatible, 1) \ fn(DT_N_S_soc, compatible, 2) \ fn(DT_N_S_soc, compatible, 3) #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc, compatible, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 3) #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) \ fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) \ fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) \ fn(DT_N_S_soc, compatible, 3, __VA_ARGS__) #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc, compatible, 3, __VA_ARGS__) #define DT_N_S_soc_P_compatible_LEN 4 #define DT_N_S_soc_P_compatible_EXISTS 1 #define DT_N_S_soc_P_ranges_EXISTS 1 /* * Devicetree node: /soc/interrupt-controller@e000e100 * * Node identifier: DT_N_S_soc_S_interrupt_controller_e000e100 * * Binding (compatible = arm,v8m-nvic): * $ZEPHYR_BASE/dts/bindings/interrupt-controller/arm,v8m-nvic.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_PATH "/soc/interrupt-controller@e000e100" /* Node's name with unit-address: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME "interrupt-controller@e000e100" #define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_UNQUOTED interrupt-controller@e000e100 #define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_TOKEN interrupt_controller_e000e100 #define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_UPPER_TOKEN INTERRUPT_CONTROLLER_E000E100 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_NODELABEL_NUM 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_NODELABEL(fn) fn(nvic) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_NODELABEL_VARGS(fn, ...) fn(nvic, __VA_ARGS__) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_ORD 9 #define DT_N_S_soc_S_interrupt_controller_e000e100_ORD_STR_SORTABLE 00009 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS \ 8, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \ 11, /* /soc/peripheral@50000000/timer@10000 */ \ 13, /* /soc/peripheral@50000000/adc@e000 */ \ 14, /* /soc/gpiote@5000d000 */ \ 30, /* /soc/peripheral@50000000/mbox@2a000 */ \ 43, /* /soc/peripheral@50000000/spi@c000 */ \ 97, /* /soc/peripheral@50000000/pwm@21000 */ \ 98, /* /soc/peripheral@50000000/pwm@23000 */ \ 99, /* /soc/peripheral@50000000/pwm@24000 */ \ 109, /* /soc/crypto@50844000 */ \ 111, /* /soc/gpiote@4002f000 */ \ 113, /* /soc/spu@50003000 */ \ 116, /* /soc/peripheral@50000000/clock@5000 */ \ 117, /* /soc/peripheral@50000000/comparator@1a000 */ \ 121, /* /soc/peripheral@50000000/egu@1b000 */ \ 122, /* /soc/peripheral@50000000/egu@1c000 */ \ 123, /* /soc/peripheral@50000000/egu@1d000 */ \ 124, /* /soc/peripheral@50000000/egu@1e000 */ \ 125, /* /soc/peripheral@50000000/egu@1f000 */ \ 126, /* /soc/peripheral@50000000/egu@20000 */ \ 127, /* /soc/peripheral@50000000/i2c@8000 */ \ 128, /* /soc/peripheral@50000000/i2c@b000 */ \ 129, /* /soc/peripheral@50000000/i2c@c000 */ \ 130, /* /soc/peripheral@50000000/i2s@28000 */ \ 132, /* /soc/peripheral@50000000/kmu@39000 */ \ 134, /* /soc/peripheral@50000000/nfct@2d000 */ \ 135, /* /soc/peripheral@50000000/pdm@26000 */ \ 136, /* /soc/peripheral@50000000/pwm@22000 */ \ 137, /* /soc/peripheral@50000000/qdec@33000 */ \ 138, /* /soc/peripheral@50000000/qdec@34000 */ \ 139, /* /soc/peripheral@50000000/regulator@37000 */ \ 141, /* /soc/peripheral@50000000/rtc@14000 */ \ 142, /* /soc/peripheral@50000000/rtc@15000 */ \ 143, /* /soc/peripheral@50000000/spi@9000 */ \ 144, /* /soc/peripheral@50000000/spi@a000 */ \ 145, /* /soc/peripheral@50000000/spi@b000 */ \ 146, /* /soc/peripheral@50000000/timer@f000 */ \ 147, /* /soc/peripheral@50000000/timer@11000 */ \ 148, /* /soc/peripheral@50000000/uart@8000 */ \ 149, /* /soc/peripheral@50000000/uart@9000 */ \ 150, /* /soc/peripheral@50000000/uart@b000 */ \ 151, /* /soc/peripheral@50000000/uart@c000 */ \ 152, /* /soc/peripheral@50000000/usbd@36000 */ \ 154, /* /soc/peripheral@50000000/watchdog@18000 */ \ 155, /* /soc/peripheral@50000000/watchdog@19000 */ \ 172, /* /soc/peripheral@50000000/i2c@9000 */ \ 175, /* /soc/peripheral@50000000/power@5000 */ \ 178, /* /soc/peripheral@50000000/qspi@2b000 */ \ 185, /* /soc/peripheral@50000000/spi@8000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1 #define DT_N_INST_0_arm_v8m_nvic DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_NODELABEL_nvic DT_N_S_soc_S_interrupt_controller_e000e100 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */ #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */ #define DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE(fn) #define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_LEVEL 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0 "ARM Ltd." #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0 "v8m-nvic" #define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */} #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 3 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v8m-nvic"} #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v8m-nvic" #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UNQUOTED arm,v8m-nvic #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_TOKEN arm_v8m_nvic #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_V8M_NVIC #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000 */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_PATH "/soc/peripheral@50000000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_FULL_NAME "peripheral@50000000" #define DT_N_S_soc_S_peripheral_50000000_FULL_NAME_UNQUOTED peripheral@50000000 #define DT_N_S_soc_S_peripheral_50000000_FULL_NAME_TOKEN peripheral_50000000 #define DT_N_S_soc_S_peripheral_50000000_FULL_NAME_UPPER_TOKEN PERIPHERAL_50000000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_CHILD_IDX 5 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_NODELABEL_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_FOREACH_NODELABEL(fn) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_CHILD_NUM 56 #define DT_N_S_soc_S_peripheral_50000000_CHILD_NUM_STATUS_OKAY 34 #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_ORD 10 #define DT_N_S_soc_S_peripheral_50000000_ORD_STR_SORTABLE 00010 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_REQUIRES_ORDS \ 8, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_SUPPORTS_ORDS \ 11, /* /soc/peripheral@50000000/timer@10000 */ \ 13, /* /soc/peripheral@50000000/adc@e000 */ \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 16, /* /soc/peripheral@50000000/gpio@842800 */ \ 30, /* /soc/peripheral@50000000/mbox@2a000 */ \ 43, /* /soc/peripheral@50000000/spi@c000 */ \ 97, /* /soc/peripheral@50000000/pwm@21000 */ \ 98, /* /soc/peripheral@50000000/pwm@23000 */ \ 99, /* /soc/peripheral@50000000/pwm@24000 */ \ 116, /* /soc/peripheral@50000000/clock@5000 */ \ 117, /* /soc/peripheral@50000000/comparator@1a000 */ \ 118, /* /soc/peripheral@50000000/ctrlap@6000 */ \ 119, /* /soc/peripheral@50000000/dcnf@0 */ \ 120, /* /soc/peripheral@50000000/dppic@17000 */ \ 121, /* /soc/peripheral@50000000/egu@1b000 */ \ 122, /* /soc/peripheral@50000000/egu@1c000 */ \ 123, /* /soc/peripheral@50000000/egu@1d000 */ \ 124, /* /soc/peripheral@50000000/egu@1e000 */ \ 125, /* /soc/peripheral@50000000/egu@1f000 */ \ 126, /* /soc/peripheral@50000000/egu@20000 */ \ 127, /* /soc/peripheral@50000000/i2c@8000 */ \ 128, /* /soc/peripheral@50000000/i2c@b000 */ \ 129, /* /soc/peripheral@50000000/i2c@c000 */ \ 130, /* /soc/peripheral@50000000/i2s@28000 */ \ 131, /* /soc/peripheral@50000000/ieee802154 */ \ 132, /* /soc/peripheral@50000000/kmu@39000 */ \ 133, /* /soc/peripheral@50000000/mutex@30000 */ \ 134, /* /soc/peripheral@50000000/nfct@2d000 */ \ 135, /* /soc/peripheral@50000000/pdm@26000 */ \ 136, /* /soc/peripheral@50000000/pwm@22000 */ \ 137, /* /soc/peripheral@50000000/qdec@33000 */ \ 138, /* /soc/peripheral@50000000/qdec@34000 */ \ 139, /* /soc/peripheral@50000000/regulator@37000 */ \ 140, /* /soc/peripheral@50000000/reset-controller@5000 */ \ 141, /* /soc/peripheral@50000000/rtc@14000 */ \ 142, /* /soc/peripheral@50000000/rtc@15000 */ \ 143, /* /soc/peripheral@50000000/spi@9000 */ \ 144, /* /soc/peripheral@50000000/spi@a000 */ \ 145, /* /soc/peripheral@50000000/spi@b000 */ \ 146, /* /soc/peripheral@50000000/timer@f000 */ \ 147, /* /soc/peripheral@50000000/timer@11000 */ \ 148, /* /soc/peripheral@50000000/uart@8000 */ \ 149, /* /soc/peripheral@50000000/uart@9000 */ \ 150, /* /soc/peripheral@50000000/uart@b000 */ \ 151, /* /soc/peripheral@50000000/uart@c000 */ \ 152, /* /soc/peripheral@50000000/usbd@36000 */ \ 153, /* /soc/peripheral@50000000/vmc@81000 */ \ 154, /* /soc/peripheral@50000000/watchdog@18000 */ \ 155, /* /soc/peripheral@50000000/watchdog@19000 */ \ 157, /* /soc/peripheral@50000000/clock-controller@4000 */ \ 160, /* /soc/peripheral@50000000/flash-controller@39000 */ \ 172, /* /soc/peripheral@50000000/i2c@9000 */ \ 175, /* /soc/peripheral@50000000/power@5000 */ \ 178, /* /soc/peripheral@50000000/qspi@2b000 */ \ 181, /* /soc/peripheral@50000000/regulator@4000 */ \ 185, /* /soc/peripheral@50000000/spi@8000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_REG_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_RANGES_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */ #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 1342177280 /* 0x50000000 */ #define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_LENGTH 268435456 /* 0x10000000 */ #define DT_N_S_soc_S_peripheral_50000000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_peripheral_50000000, 0) #define DT_N_S_soc_S_peripheral_50000000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_P_ranges_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/timer@10000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_10000 * * Binding (compatible = nordic,nrf-timer): * $ZEPHYR_BASE/dts/bindings/counter/nordic,nrf-timer.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PATH "/soc/peripheral@50000000/timer@10000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FULL_NAME "timer@10000" #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FULL_NAME_UNQUOTED timer@10000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FULL_NAME_TOKEN timer_10000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FULL_NAME_UPPER_TOKEN TIMER_10000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_CHILD_IDX 22 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_NODELABEL(fn) fn(timer1) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_ORD 11 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_ORD_STR_SORTABLE 00011 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_SUPPORTS_ORDS \ 12, /* /sw-pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_10000 #define DT_N_NODELABEL_timer1 DT_N_S_soc_S_peripheral_50000000_S_timer_10000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_ADDRESS 1342242816 /* 0x50010000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq 16 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MATCHES_nordic_nrf_timer 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MODEL_IDX_0 "nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg {65536 /* 0x10000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_0 65536 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_cc_num 6 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_cc_num_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_bit_width 32 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_bit_width_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts {16 /* 0x10 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_0 16 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_frequency 16000000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zli 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zli_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible {"nordic,nrf-timer"} #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0 "nordic,nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /sw-pwm * * Node identifier: DT_N_S_sw_pwm * * Binding (compatible = nordic,nrf-sw-pwm): * $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-sw-pwm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_sw_pwm_PATH "/sw-pwm" /* Node's name with unit-address: */ #define DT_N_S_sw_pwm_FULL_NAME "sw-pwm" #define DT_N_S_sw_pwm_FULL_NAME_UNQUOTED sw-pwm #define DT_N_S_sw_pwm_FULL_NAME_TOKEN sw_pwm #define DT_N_S_sw_pwm_FULL_NAME_UPPER_TOKEN SW_PWM /* Node parent (/) identifier: */ #define DT_N_S_sw_pwm_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_sw_pwm_CHILD_IDX 5 /* Helpers for dealing with node labels: */ #define DT_N_S_sw_pwm_NODELABEL_NUM 1 #define DT_N_S_sw_pwm_FOREACH_NODELABEL(fn) fn(sw_pwm) #define DT_N_S_sw_pwm_FOREACH_NODELABEL_VARGS(fn, ...) fn(sw_pwm, __VA_ARGS__) #define DT_N_S_sw_pwm_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_sw_pwm_CHILD_NUM 0 #define DT_N_S_sw_pwm_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_sw_pwm_FOREACH_CHILD(fn) #define DT_N_S_sw_pwm_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_sw_pwm_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_sw_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_sw_pwm_ORD 12 #define DT_N_S_sw_pwm_ORD_STR_SORTABLE 00012 /* Ordinals for what this node depends on directly: */ #define DT_N_S_sw_pwm_REQUIRES_ORDS \ 0, /* / */ \ 11, /* /soc/peripheral@50000000/timer@10000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_sw_pwm_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_sw_pwm_EXISTS 1 #define DT_N_INST_0_nordic_nrf_sw_pwm DT_N_S_sw_pwm #define DT_N_NODELABEL_sw_pwm DT_N_S_sw_pwm /* Macros for properties that are special in the specification: */ #define DT_N_S_sw_pwm_REG_NUM 0 #define DT_N_S_sw_pwm_RANGES_NUM 0 #define DT_N_S_sw_pwm_FOREACH_RANGE(fn) #define DT_N_S_sw_pwm_IRQ_NUM 0 #define DT_N_S_sw_pwm_IRQ_LEVEL 0 #define DT_N_S_sw_pwm_COMPAT_MATCHES_nordic_nrf_sw_pwm 1 #define DT_N_S_sw_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_sw_pwm_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_sw_pwm_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_sw_pwm_COMPAT_MODEL_IDX_0 "nrf-sw-pwm" #define DT_N_S_sw_pwm_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_sw_pwm_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_sw_pwm_P_generator DT_N_S_soc_S_peripheral_50000000_S_timer_10000 #define DT_N_S_sw_pwm_P_generator_IDX_0 DT_N_S_soc_S_peripheral_50000000_S_timer_10000 #define DT_N_S_sw_pwm_P_generator_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_timer_10000 #define DT_N_S_sw_pwm_P_generator_IDX_0_EXISTS 1 #define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, generator, 0) #define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, generator, 0) #define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, generator, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, generator, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_generator_LEN 1 #define DT_N_S_sw_pwm_P_generator_EXISTS 1 #define DT_N_S_sw_pwm_P_clock_prescaler 0 #define DT_N_S_sw_pwm_P_clock_prescaler_EXISTS 1 #define DT_N_S_sw_pwm_P_status "disabled" #define DT_N_S_sw_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_sw_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_sw_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_sw_pwm_P_status_IDX_0 "disabled" #define DT_N_S_sw_pwm_P_status_IDX_0_EXISTS 1 #define DT_N_S_sw_pwm_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_sw_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, status, 0) #define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, status, 0) #define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, status, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, status, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_status_LEN 1 #define DT_N_S_sw_pwm_P_status_EXISTS 1 #define DT_N_S_sw_pwm_P_compatible {"nordic,nrf-sw-pwm"} #define DT_N_S_sw_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_sw_pwm_P_compatible_IDX_0 "nordic,nrf-sw-pwm" #define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-sw-pwm #define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_sw_pwm #define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SW_PWM #define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, compatible, 0) #define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, compatible, 0) #define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, compatible, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, compatible, 0, __VA_ARGS__) #define DT_N_S_sw_pwm_P_compatible_LEN 1 #define DT_N_S_sw_pwm_P_compatible_EXISTS 1 #define DT_N_S_sw_pwm_P_zephyr_deferred_init 0 #define DT_N_S_sw_pwm_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_sw_pwm_P_wakeup_source 0 #define DT_N_S_sw_pwm_P_wakeup_source_EXISTS 1 #define DT_N_S_sw_pwm_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_sw_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/adc@e000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_adc_e000 * * Binding (compatible = nordic,nrf-saadc): * $ZEPHYR_BASE/dts/bindings/adc/nordic,nrf-saadc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PATH "/soc/peripheral@50000000/adc@e000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FULL_NAME "adc@e000" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FULL_NAME_UNQUOTED adc@e000 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FULL_NAME_TOKEN adc_e000 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FULL_NAME_UPPER_TOKEN ADC_E000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_CHILD_IDX 20 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_NODELABEL(fn) fn(adc) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_CHILD_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_ORD 13 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_ORD_STR_SORTABLE 00013 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_SUPPORTS_ORDS \ 17, /* /zephyr,user */ \ 156, /* /soc/peripheral@50000000/adc@e000/channel@5 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_saadc DT_N_S_soc_S_peripheral_50000000_S_adc_e000 #define DT_N_NODELABEL_adc DT_N_S_soc_S_peripheral_50000000_S_adc_e000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_ADDRESS 1342234624 /* 0x5000e000 */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq 14 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MATCHES_nordic_nrf_saadc 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MODEL_IDX_0 "nrf-saadc" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg {57344 /* 0xe000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_0 57344 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts {14 /* 0xe */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_0 14 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible {"nordic,nrf-saadc"} #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0 "nordic,nrf-saadc" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-saadc #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_saadc #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SAADC #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_pm_device_runtime_auto 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/gpiote@5000d000 * * Node identifier: DT_N_S_soc_S_gpiote_5000d000 * * Binding (compatible = nordic,nrf-gpiote): * $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpiote.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_gpiote_5000d000_PATH "/soc/gpiote@5000d000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_gpiote_5000d000_FULL_NAME "gpiote@5000d000" #define DT_N_S_soc_S_gpiote_5000d000_FULL_NAME_UNQUOTED gpiote@5000d000 #define DT_N_S_soc_S_gpiote_5000d000_FULL_NAME_TOKEN gpiote_5000d000 #define DT_N_S_soc_S_gpiote_5000d000_FULL_NAME_UPPER_TOKEN GPIOTE_5000D000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_gpiote_5000d000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_gpiote_5000d000_CHILD_IDX 7 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_gpiote_5000d000_NODELABEL_NUM 2 #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_NODELABEL(fn) fn(gpiote) fn(gpiote0) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiote, __VA_ARGS__) fn(gpiote0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_gpiote_5000d000_CHILD_NUM 0 #define DT_N_S_soc_S_gpiote_5000d000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_gpiote_5000d000_ORD 14 #define DT_N_S_soc_S_gpiote_5000d000_ORD_STR_SORTABLE 00014 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_gpiote_5000d000_REQUIRES_ORDS \ 8, /* /soc */ \ 9, /* /soc/interrupt-controller@e000e100 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_gpiote_5000d000_SUPPORTS_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 16, /* /soc/peripheral@50000000/gpio@842800 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_gpiote_5000d000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_5000d000 #define DT_N_NODELABEL_gpiote DT_N_S_soc_S_gpiote_5000d000 #define DT_N_NODELABEL_gpiote0 DT_N_S_soc_S_gpiote_5000d000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_gpiote_5000d000_REG_NUM 1 #define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_ADDRESS 1342230528 /* 0x5000d000 */ #define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_gpiote_5000d000_RANGES_NUM 0 #define DT_N_S_soc_S_gpiote_5000d000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_gpiote_5000d000_IRQ_NUM 1 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq 13 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority 5 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_gpiote_5000d000_IRQ_LEVEL 1 #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MATCHES_nordic_nrf_gpiote 1 #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MODEL_IDX_0 "nrf-gpiote" #define DT_N_S_soc_S_gpiote_5000d000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_gpiote_5000d000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_gpiote_5000d000_P_reg {1342230528 /* 0x5000d000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_0 1342230528 #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_gpiote_5000d000_P_reg_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts {13 /* 0xd */, 5 /* 0x5 */} #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_0 13 #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_1 5 #define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_instance 0 #define DT_N_S_soc_S_gpiote_5000d000_P_instance_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_status "okay" #define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_gpiote_5000d000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_gpiote_5000d000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_gpiote_5000d000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0) #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0) #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_5000d000_P_status_LEN 1 #define DT_N_S_soc_S_gpiote_5000d000_P_status_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_compatible {"nordic,nrf-gpiote"} #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0 "nordic,nrf-gpiote" #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpiote #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0) #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0) #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_LEN 1 #define DT_N_S_soc_S_gpiote_5000d000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_wakeup_source 0 #define DT_N_S_soc_S_gpiote_5000d000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/gpio@842500 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 * * Binding (compatible = nordic,nrf-gpio): * $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpio.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PATH "/soc/peripheral@50000000/gpio@842500" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FULL_NAME "gpio@842500" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FULL_NAME_UNQUOTED gpio@842500 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FULL_NAME_TOKEN gpio_842500 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FULL_NAME_UPPER_TOKEN GPIO_842500 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_CHILD_IDX 53 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_NODELABEL(fn) fn(gpio0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpio0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_ORD 15 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_ORD_STR_SORTABLE 00015 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ \ 14, /* /soc/gpiote@5000d000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_SUPPORTS_ORDS \ 17, /* /zephyr,user */ \ 18, /* /buttons */ \ 19, /* /buttons/button_0 */ \ 20, /* /buttons/button_1 */ \ 21, /* /buttons/button_2 */ \ 22, /* /buttons/button_3 */ \ 35, /* /leds */ \ 36, /* /leds/led_0 */ \ 37, /* /leds/led_1 */ \ 38, /* /leds/led_2 */ \ 39, /* /leds/led_3 */ \ 43, /* /soc/peripheral@50000000/spi@c000 */ \ 44, /* /mipi_dbi_st7789v */ \ 94, /* /pins_io */ \ 95, /* /pins_io/en_motor */ \ 96, /* /pins_io/key1 */ \ 185, /* /soc/peripheral@50000000/spi@8000 */ \ 186, /* /soc/peripheral@50000000/spi@8000/sx1280@0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_EXISTS 1 #define DT_N_INST_0_nordic_nrf_gpio DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_NODELABEL_gpio0 DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_ADDRESS 1350837504 /* 0x50842500 */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_SIZE 768 /* 0x300 */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MATCHES_nordic_nrf_gpio 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MODEL_IDX_0 "nrf-gpio" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg {8660224 /* 0x842500 */, 768 /* 0x300 */} #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_0 8660224 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_1 768 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance DT_N_S_soc_S_gpiote_5000d000 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_IDX_0 DT_N_S_soc_S_gpiote_5000d000 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_IDX_0_PH DT_N_S_soc_S_gpiote_5000d000 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_port 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_port_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios 32 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible {"nordic,nrf-gpio"} #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0 "nordic,nrf-gpio" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/gpio@842800 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_gpio_842800 * * Binding (compatible = nordic,nrf-gpio): * $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpio.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_PATH "/soc/peripheral@50000000/gpio@842800" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FULL_NAME "gpio@842800" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FULL_NAME_UNQUOTED gpio@842800 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FULL_NAME_TOKEN gpio_842800 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FULL_NAME_UPPER_TOKEN GPIO_842800 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_CHILD_IDX 54 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_NODELABEL(fn) fn(gpio1) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpio1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_ORD 16 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_ORD_STR_SORTABLE 00016 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ \ 14, /* /soc/gpiote@5000d000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_SUPPORTS_ORDS \ 17, /* /zephyr,user */ \ 44, /* /mipi_dbi_st7789v */ \ 144, /* /soc/peripheral@50000000/spi@a000 */ \ 186, /* /soc/peripheral@50000000/spi@8000/sx1280@0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_EXISTS 1 #define DT_N_INST_1_nordic_nrf_gpio DT_N_S_soc_S_peripheral_50000000_S_gpio_842800 #define DT_N_NODELABEL_gpio1 DT_N_S_soc_S_peripheral_50000000_S_gpio_842800 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_VAL_ADDRESS 1350838272 /* 0x50842800 */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_VAL_SIZE 768 /* 0x300 */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_MATCHES_nordic_nrf_gpio 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_MODEL_IDX_0 "nrf-gpio" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg {8660992 /* 0x842800 */, 768 /* 0x300 */} #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_0 8660992 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_1 768 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance DT_N_S_soc_S_gpiote_5000d000 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_IDX_0 DT_N_S_soc_S_gpiote_5000d000 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_IDX_0_PH DT_N_S_soc_S_gpiote_5000d000 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, gpiote_instance, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, gpiote_instance, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, gpiote_instance, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, gpiote_instance, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_port 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_port_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpio_controller 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpio_controller_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_ngpios 16 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_ngpios_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible {"nordic,nrf-gpio"} #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0 "nordic,nrf-gpio" #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /zephyr,user * * Node identifier: DT_N_S_zephyr_user * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_zephyr_user_PATH "/zephyr,user" /* Node's name with unit-address: */ #define DT_N_S_zephyr_user_FULL_NAME "zephyr,user" #define DT_N_S_zephyr_user_FULL_NAME_UNQUOTED zephyr,user #define DT_N_S_zephyr_user_FULL_NAME_TOKEN zephyr_user #define DT_N_S_zephyr_user_FULL_NAME_UPPER_TOKEN ZEPHYR_USER /* Node parent (/) identifier: */ #define DT_N_S_zephyr_user_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_zephyr_user_CHILD_IDX 18 /* Helpers for dealing with node labels: */ #define DT_N_S_zephyr_user_NODELABEL_NUM 0 #define DT_N_S_zephyr_user_FOREACH_NODELABEL(fn) #define DT_N_S_zephyr_user_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_zephyr_user_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_zephyr_user_CHILD_NUM 0 #define DT_N_S_zephyr_user_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_zephyr_user_FOREACH_CHILD(fn) #define DT_N_S_zephyr_user_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_zephyr_user_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_zephyr_user_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_zephyr_user_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_zephyr_user_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_zephyr_user_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_zephyr_user_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_zephyr_user_ORD 17 #define DT_N_S_zephyr_user_ORD_STR_SORTABLE 00017 /* Ordinals for what this node depends on directly: */ #define DT_N_S_zephyr_user_REQUIRES_ORDS \ 0, /* / */ \ 13, /* /soc/peripheral@50000000/adc@e000 */ \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 16, /* /soc/peripheral@50000000/gpio@842800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_zephyr_user_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_zephyr_user_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_zephyr_user_REG_NUM 0 #define DT_N_S_zephyr_user_RANGES_NUM 0 #define DT_N_S_zephyr_user_FOREACH_RANGE(fn) #define DT_N_S_zephyr_user_IRQ_NUM 0 #define DT_N_S_zephyr_user_IRQ_LEVEL 0 #define DT_N_S_zephyr_user_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_zephyr_user_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_zephyr_user_P_io_channels_IDX_0_EXISTS 1 #define DT_N_S_zephyr_user_P_io_channels_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_adc_e000 #define DT_N_S_zephyr_user_P_io_channels_IDX_0_VAL_input 5 #define DT_N_S_zephyr_user_P_io_channels_IDX_0_VAL_input_EXISTS 1 #define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_zephyr_user, io_channels, 0) #define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_zephyr_user, io_channels, 0) #define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_zephyr_user, io_channels, 0, __VA_ARGS__) #define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_zephyr_user, io_channels, 0, __VA_ARGS__) #define DT_N_S_zephyr_user_P_io_channels_LEN 1 #define DT_N_S_zephyr_user_P_io_channels_EXISTS 1 #define DT_N_S_zephyr_user_P_bq24040_gpios_IDX_0_EXISTS 1 #define DT_N_S_zephyr_user_P_bq24040_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_zephyr_user_P_bq24040_gpios_IDX_0_VAL_pin 24 #define DT_N_S_zephyr_user_P_bq24040_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_bq24040_gpios_IDX_0_VAL_flags 0 #define DT_N_S_zephyr_user_P_bq24040_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_bq24040_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_zephyr_user, bq24040_gpios, 0) #define DT_N_S_zephyr_user_P_bq24040_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_zephyr_user, bq24040_gpios, 0) #define DT_N_S_zephyr_user_P_bq24040_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_zephyr_user, bq24040_gpios, 0, __VA_ARGS__) #define DT_N_S_zephyr_user_P_bq24040_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_zephyr_user, bq24040_gpios, 0, __VA_ARGS__) #define DT_N_S_zephyr_user_P_bq24040_gpios_LEN 1 #define DT_N_S_zephyr_user_P_bq24040_gpios_EXISTS 1 #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_IDX_0_EXISTS 1 #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842800 #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_IDX_0_VAL_pin 0 #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_IDX_0_VAL_flags 17 #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_zephyr_user, bmi270_int1_gpios, 0) #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_zephyr_user, bmi270_int1_gpios, 0) #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_zephyr_user, bmi270_int1_gpios, 0, __VA_ARGS__) #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_zephyr_user, bmi270_int1_gpios, 0, __VA_ARGS__) #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_LEN 1 #define DT_N_S_zephyr_user_P_bmi270_int1_gpios_EXISTS 1 #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_IDX_0_EXISTS 1 #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_IDX_0_VAL_pin 11 #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_IDX_0_VAL_flags 17 #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_zephyr_user, bmi270_int2_gpios, 0) #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_zephyr_user, bmi270_int2_gpios, 0) #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_zephyr_user, bmi270_int2_gpios, 0, __VA_ARGS__) #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_zephyr_user, bmi270_int2_gpios, 0, __VA_ARGS__) #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_LEN 1 #define DT_N_S_zephyr_user_P_bmi270_int2_gpios_EXISTS 1 /* * Devicetree node: /buttons * * Node identifier: DT_N_S_buttons * * Binding (compatible = gpio-keys): * $ZEPHYR_BASE/dts/bindings/input/gpio-keys.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_buttons_PATH "/buttons" /* Node's name with unit-address: */ #define DT_N_S_buttons_FULL_NAME "buttons" #define DT_N_S_buttons_FULL_NAME_UNQUOTED buttons #define DT_N_S_buttons_FULL_NAME_TOKEN buttons #define DT_N_S_buttons_FULL_NAME_UPPER_TOKEN BUTTONS /* Node parent (/) identifier: */ #define DT_N_S_buttons_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_buttons_CHILD_IDX 9 /* Helpers for dealing with node labels: */ #define DT_N_S_buttons_NODELABEL_NUM 0 #define DT_N_S_buttons_FOREACH_NODELABEL(fn) #define DT_N_S_buttons_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_buttons_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_buttons_CHILD_NUM 4 #define DT_N_S_buttons_CHILD_NUM_STATUS_OKAY 4 #define DT_N_S_buttons_FOREACH_CHILD(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) #define DT_N_S_buttons_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3) #define DT_N_S_buttons_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) #define DT_N_S_buttons_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3) #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) #define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_buttons_ORD 18 #define DT_N_S_buttons_ORD_STR_SORTABLE 00018 /* Ordinals for what this node depends on directly: */ #define DT_N_S_buttons_REQUIRES_ORDS \ 0, /* / */ \ 15, /* /soc/peripheral@50000000/gpio@842500 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_buttons_SUPPORTS_ORDS \ 19, /* /buttons/button_0 */ \ 20, /* /buttons/button_1 */ \ 21, /* /buttons/button_2 */ \ 22, /* /buttons/button_3 */ /* Existence and alternate IDs: */ #define DT_N_S_buttons_EXISTS 1 #define DT_N_INST_0_gpio_keys DT_N_S_buttons /* Macros for properties that are special in the specification: */ #define DT_N_S_buttons_REG_NUM 0 #define DT_N_S_buttons_RANGES_NUM 0 #define DT_N_S_buttons_FOREACH_RANGE(fn) #define DT_N_S_buttons_IRQ_NUM 0 #define DT_N_S_buttons_IRQ_LEVEL 0 #define DT_N_S_buttons_COMPAT_MATCHES_gpio_keys 1 #define DT_N_S_buttons_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_buttons_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_buttons_P_debounce_interval_ms 30 #define DT_N_S_buttons_P_debounce_interval_ms_EXISTS 1 #define DT_N_S_buttons_P_polling_mode 0 #define DT_N_S_buttons_P_polling_mode_EXISTS 1 #define DT_N_S_buttons_P_no_disconnect 0 #define DT_N_S_buttons_P_no_disconnect_EXISTS 1 #define DT_N_S_buttons_P_compatible {"gpio-keys"} #define DT_N_S_buttons_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_buttons_P_compatible_IDX_0 "gpio-keys" #define DT_N_S_buttons_P_compatible_IDX_0_STRING_UNQUOTED gpio-keys #define DT_N_S_buttons_P_compatible_IDX_0_STRING_TOKEN gpio_keys #define DT_N_S_buttons_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_KEYS #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons, compatible, 0) #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons, compatible, 0) #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__) #define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__) #define DT_N_S_buttons_P_compatible_LEN 1 #define DT_N_S_buttons_P_compatible_EXISTS 1 #define DT_N_S_buttons_P_zephyr_deferred_init 0 #define DT_N_S_buttons_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_buttons_P_wakeup_source 0 #define DT_N_S_buttons_P_wakeup_source_EXISTS 1 #define DT_N_S_buttons_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_buttons_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /buttons/button_0 * * Node identifier: DT_N_S_buttons_S_button_0 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_buttons_S_button_0_PATH "/buttons/button_0" /* Node's name with unit-address: */ #define DT_N_S_buttons_S_button_0_FULL_NAME "button_0" #define DT_N_S_buttons_S_button_0_FULL_NAME_UNQUOTED button_0 #define DT_N_S_buttons_S_button_0_FULL_NAME_TOKEN button_0 #define DT_N_S_buttons_S_button_0_FULL_NAME_UPPER_TOKEN BUTTON_0 /* Node parent (/buttons) identifier: */ #define DT_N_S_buttons_S_button_0_PARENT DT_N_S_buttons /* Node's index in its parent's list of children: */ #define DT_N_S_buttons_S_button_0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_buttons_S_button_0_NODELABEL_NUM 1 #define DT_N_S_buttons_S_button_0_FOREACH_NODELABEL(fn) fn(button0) #define DT_N_S_buttons_S_button_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(button0, __VA_ARGS__) #define DT_N_S_buttons_S_button_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_buttons) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_buttons_S_button_0_CHILD_NUM 0 #define DT_N_S_buttons_S_button_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_buttons_S_button_0_FOREACH_CHILD(fn) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_buttons_S_button_0_ORD 19 #define DT_N_S_buttons_S_button_0_ORD_STR_SORTABLE 00019 /* Ordinals for what this node depends on directly: */ #define DT_N_S_buttons_S_button_0_REQUIRES_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 18, /* /buttons */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_buttons_S_button_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_buttons_S_button_0_EXISTS 1 #define DT_N_ALIAS_sw0 DT_N_S_buttons_S_button_0 #define DT_N_NODELABEL_button0 DT_N_S_buttons_S_button_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_buttons_S_button_0_REG_NUM 0 #define DT_N_S_buttons_S_button_0_RANGES_NUM 0 #define DT_N_S_buttons_S_button_0_FOREACH_RANGE(fn) #define DT_N_S_buttons_S_button_0_IRQ_NUM 0 #define DT_N_S_buttons_S_button_0_IRQ_LEVEL 0 #define DT_N_S_buttons_S_button_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_buttons_S_button_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin 23 #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags 17 #define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_0, gpios, 0) #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0, gpios, 0) #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_0_P_gpios_LEN 1 #define DT_N_S_buttons_S_button_0_P_gpios_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_label "Push button 1" #define DT_N_S_buttons_S_button_0_P_label_STRING_UNQUOTED Push button 1 #define DT_N_S_buttons_S_button_0_P_label_STRING_TOKEN Push_button_1 #define DT_N_S_buttons_S_button_0_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_1 #define DT_N_S_buttons_S_button_0_P_label_IDX_0 "Push button 1" #define DT_N_S_buttons_S_button_0_P_label_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_0, label, 0) #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0, label, 0) #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_0_P_label_LEN 1 #define DT_N_S_buttons_S_button_0_P_label_EXISTS 1 #define DT_N_S_buttons_S_button_0_P_zephyr_code 11 #define DT_N_S_buttons_S_button_0_P_zephyr_code_EXISTS 1 /* * Devicetree node: /buttons/button_1 * * Node identifier: DT_N_S_buttons_S_button_1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_buttons_S_button_1_PATH "/buttons/button_1" /* Node's name with unit-address: */ #define DT_N_S_buttons_S_button_1_FULL_NAME "button_1" #define DT_N_S_buttons_S_button_1_FULL_NAME_UNQUOTED button_1 #define DT_N_S_buttons_S_button_1_FULL_NAME_TOKEN button_1 #define DT_N_S_buttons_S_button_1_FULL_NAME_UPPER_TOKEN BUTTON_1 /* Node parent (/buttons) identifier: */ #define DT_N_S_buttons_S_button_1_PARENT DT_N_S_buttons /* Node's index in its parent's list of children: */ #define DT_N_S_buttons_S_button_1_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_buttons_S_button_1_NODELABEL_NUM 1 #define DT_N_S_buttons_S_button_1_FOREACH_NODELABEL(fn) fn(button1) #define DT_N_S_buttons_S_button_1_FOREACH_NODELABEL_VARGS(fn, ...) fn(button1, __VA_ARGS__) #define DT_N_S_buttons_S_button_1_FOREACH_ANCESTOR(fn) fn(DT_N_S_buttons) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_buttons_S_button_1_CHILD_NUM 0 #define DT_N_S_buttons_S_button_1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_buttons_S_button_1_FOREACH_CHILD(fn) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_buttons_S_button_1_ORD 20 #define DT_N_S_buttons_S_button_1_ORD_STR_SORTABLE 00020 /* Ordinals for what this node depends on directly: */ #define DT_N_S_buttons_S_button_1_REQUIRES_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 18, /* /buttons */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_buttons_S_button_1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_buttons_S_button_1_EXISTS 1 #define DT_N_NODELABEL_button1 DT_N_S_buttons_S_button_1 /* Macros for properties that are special in the specification: */ #define DT_N_S_buttons_S_button_1_REG_NUM 0 #define DT_N_S_buttons_S_button_1_RANGES_NUM 0 #define DT_N_S_buttons_S_button_1_FOREACH_RANGE(fn) #define DT_N_S_buttons_S_button_1_IRQ_NUM 0 #define DT_N_S_buttons_S_button_1_IRQ_LEVEL 0 #define DT_N_S_buttons_S_button_1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_buttons_S_button_1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin 24 #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags 17 #define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_1, gpios, 0) #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_1, gpios, 0) #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_1_P_gpios_LEN 1 #define DT_N_S_buttons_S_button_1_P_gpios_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_label "Push button 2" #define DT_N_S_buttons_S_button_1_P_label_STRING_UNQUOTED Push button 2 #define DT_N_S_buttons_S_button_1_P_label_STRING_TOKEN Push_button_2 #define DT_N_S_buttons_S_button_1_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_2 #define DT_N_S_buttons_S_button_1_P_label_IDX_0 "Push button 2" #define DT_N_S_buttons_S_button_1_P_label_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_1, label, 0) #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_1, label, 0) #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_1, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_1, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_1_P_label_LEN 1 #define DT_N_S_buttons_S_button_1_P_label_EXISTS 1 #define DT_N_S_buttons_S_button_1_P_zephyr_code 2 #define DT_N_S_buttons_S_button_1_P_zephyr_code_EXISTS 1 /* * Devicetree node: /buttons/button_2 * * Node identifier: DT_N_S_buttons_S_button_2 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_buttons_S_button_2_PATH "/buttons/button_2" /* Node's name with unit-address: */ #define DT_N_S_buttons_S_button_2_FULL_NAME "button_2" #define DT_N_S_buttons_S_button_2_FULL_NAME_UNQUOTED button_2 #define DT_N_S_buttons_S_button_2_FULL_NAME_TOKEN button_2 #define DT_N_S_buttons_S_button_2_FULL_NAME_UPPER_TOKEN BUTTON_2 /* Node parent (/buttons) identifier: */ #define DT_N_S_buttons_S_button_2_PARENT DT_N_S_buttons /* Node's index in its parent's list of children: */ #define DT_N_S_buttons_S_button_2_CHILD_IDX 2 /* Helpers for dealing with node labels: */ #define DT_N_S_buttons_S_button_2_NODELABEL_NUM 1 #define DT_N_S_buttons_S_button_2_FOREACH_NODELABEL(fn) fn(button2) #define DT_N_S_buttons_S_button_2_FOREACH_NODELABEL_VARGS(fn, ...) fn(button2, __VA_ARGS__) #define DT_N_S_buttons_S_button_2_FOREACH_ANCESTOR(fn) fn(DT_N_S_buttons) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_buttons_S_button_2_CHILD_NUM 0 #define DT_N_S_buttons_S_button_2_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_buttons_S_button_2_FOREACH_CHILD(fn) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_buttons_S_button_2_ORD 21 #define DT_N_S_buttons_S_button_2_ORD_STR_SORTABLE 00021 /* Ordinals for what this node depends on directly: */ #define DT_N_S_buttons_S_button_2_REQUIRES_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 18, /* /buttons */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_buttons_S_button_2_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_buttons_S_button_2_EXISTS 1 #define DT_N_NODELABEL_button2 DT_N_S_buttons_S_button_2 /* Macros for properties that are special in the specification: */ #define DT_N_S_buttons_S_button_2_REG_NUM 0 #define DT_N_S_buttons_S_button_2_RANGES_NUM 0 #define DT_N_S_buttons_S_button_2_FOREACH_RANGE(fn) #define DT_N_S_buttons_S_button_2_IRQ_NUM 0 #define DT_N_S_buttons_S_button_2_IRQ_LEVEL 0 #define DT_N_S_buttons_S_button_2_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_buttons_S_button_2_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin 8 #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags 17 #define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_2, gpios, 0) #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_2, gpios, 0) #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_2_P_gpios_LEN 1 #define DT_N_S_buttons_S_button_2_P_gpios_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_label "Push button 3" #define DT_N_S_buttons_S_button_2_P_label_STRING_UNQUOTED Push button 3 #define DT_N_S_buttons_S_button_2_P_label_STRING_TOKEN Push_button_3 #define DT_N_S_buttons_S_button_2_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_3 #define DT_N_S_buttons_S_button_2_P_label_IDX_0 "Push button 3" #define DT_N_S_buttons_S_button_2_P_label_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_2, label, 0) #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_2, label, 0) #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_2, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_2, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_2_P_label_LEN 1 #define DT_N_S_buttons_S_button_2_P_label_EXISTS 1 #define DT_N_S_buttons_S_button_2_P_zephyr_code 3 #define DT_N_S_buttons_S_button_2_P_zephyr_code_EXISTS 1 /* * Devicetree node: /buttons/button_3 * * Node identifier: DT_N_S_buttons_S_button_3 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_buttons_S_button_3_PATH "/buttons/button_3" /* Node's name with unit-address: */ #define DT_N_S_buttons_S_button_3_FULL_NAME "button_3" #define DT_N_S_buttons_S_button_3_FULL_NAME_UNQUOTED button_3 #define DT_N_S_buttons_S_button_3_FULL_NAME_TOKEN button_3 #define DT_N_S_buttons_S_button_3_FULL_NAME_UPPER_TOKEN BUTTON_3 /* Node parent (/buttons) identifier: */ #define DT_N_S_buttons_S_button_3_PARENT DT_N_S_buttons /* Node's index in its parent's list of children: */ #define DT_N_S_buttons_S_button_3_CHILD_IDX 3 /* Helpers for dealing with node labels: */ #define DT_N_S_buttons_S_button_3_NODELABEL_NUM 1 #define DT_N_S_buttons_S_button_3_FOREACH_NODELABEL(fn) fn(button3) #define DT_N_S_buttons_S_button_3_FOREACH_NODELABEL_VARGS(fn, ...) fn(button3, __VA_ARGS__) #define DT_N_S_buttons_S_button_3_FOREACH_ANCESTOR(fn) fn(DT_N_S_buttons) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_buttons_S_button_3_CHILD_NUM 0 #define DT_N_S_buttons_S_button_3_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_buttons_S_button_3_FOREACH_CHILD(fn) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_buttons_S_button_3_ORD 22 #define DT_N_S_buttons_S_button_3_ORD_STR_SORTABLE 00022 /* Ordinals for what this node depends on directly: */ #define DT_N_S_buttons_S_button_3_REQUIRES_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 18, /* /buttons */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_buttons_S_button_3_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_buttons_S_button_3_EXISTS 1 #define DT_N_NODELABEL_button3 DT_N_S_buttons_S_button_3 /* Macros for properties that are special in the specification: */ #define DT_N_S_buttons_S_button_3_REG_NUM 0 #define DT_N_S_buttons_S_button_3_RANGES_NUM 0 #define DT_N_S_buttons_S_button_3_FOREACH_RANGE(fn) #define DT_N_S_buttons_S_button_3_IRQ_NUM 0 #define DT_N_S_buttons_S_button_3_IRQ_LEVEL 0 #define DT_N_S_buttons_S_button_3_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_buttons_S_button_3_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin 9 #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags 17 #define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_3, gpios, 0) #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_3, gpios, 0) #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_3, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_3, gpios, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_3_P_gpios_LEN 1 #define DT_N_S_buttons_S_button_3_P_gpios_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_label "Push button 4" #define DT_N_S_buttons_S_button_3_P_label_STRING_UNQUOTED Push button 4 #define DT_N_S_buttons_S_button_3_P_label_STRING_TOKEN Push_button_4 #define DT_N_S_buttons_S_button_3_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_4 #define DT_N_S_buttons_S_button_3_P_label_IDX_0 "Push button 4" #define DT_N_S_buttons_S_button_3_P_label_IDX_0_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_3, label, 0) #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_3, label, 0) #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_3, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_3, label, 0, __VA_ARGS__) #define DT_N_S_buttons_S_button_3_P_label_LEN 1 #define DT_N_S_buttons_S_button_3_P_label_EXISTS 1 #define DT_N_S_buttons_S_button_3_P_zephyr_code 4 #define DT_N_S_buttons_S_button_3_P_zephyr_code_EXISTS 1 /* * Devicetree node: /cpus * * Node identifier: DT_N_S_cpus */ /* Node's full path: */ #define DT_N_S_cpus_PATH "/cpus" /* Node's name with unit-address: */ #define DT_N_S_cpus_FULL_NAME "cpus" #define DT_N_S_cpus_FULL_NAME_UNQUOTED cpus #define DT_N_S_cpus_FULL_NAME_TOKEN cpus #define DT_N_S_cpus_FULL_NAME_UPPER_TOKEN CPUS /* Node parent (/) identifier: */ #define DT_N_S_cpus_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_cpus_CHILD_IDX 6 /* Helpers for dealing with node labels: */ #define DT_N_S_cpus_NODELABEL_NUM 0 #define DT_N_S_cpus_FOREACH_NODELABEL(fn) #define DT_N_S_cpus_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_cpus_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_cpus_CHILD_NUM 1 #define DT_N_S_cpus_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0) #define DT_N_S_cpus_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0) #define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) #define DT_N_S_cpus_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0) #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0) #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_cpus_ORD 23 #define DT_N_S_cpus_ORD_STR_SORTABLE 00023 /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_SUPPORTS_ORDS \ 24, /* /cpus/cpu@0 */ /* Existence and alternate IDs: */ #define DT_N_S_cpus_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_cpus_REG_NUM 0 #define DT_N_S_cpus_RANGES_NUM 0 #define DT_N_S_cpus_FOREACH_RANGE(fn) #define DT_N_S_cpus_IRQ_NUM 0 #define DT_N_S_cpus_IRQ_LEVEL 0 #define DT_N_S_cpus_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_cpus_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /cpus/cpu@0 * * Node identifier: DT_N_S_cpus_S_cpu_0 * * Binding (compatible = arm,cortex-m33f): * $ZEPHYR_BASE/dts/bindings/cpu/arm,cortex-m33f.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0" /* Node's name with unit-address: */ #define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0" #define DT_N_S_cpus_S_cpu_0_FULL_NAME_UNQUOTED cpu@0 #define DT_N_S_cpus_S_cpu_0_FULL_NAME_TOKEN cpu_0 #define DT_N_S_cpus_S_cpu_0_FULL_NAME_UPPER_TOKEN CPU_0 /* Node parent (/cpus) identifier: */ #define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus /* Node's index in its parent's list of children: */ #define DT_N_S_cpus_S_cpu_0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_cpus_S_cpu_0_NODELABEL_NUM 1 #define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL(fn) fn(cpu0) #define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpu0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_cpus_S_cpu_0_CHILD_NUM 2 #define DT_N_S_cpus_S_cpu_0_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_cpus_S_cpu_0_ORD 24 #define DT_N_S_cpus_S_cpu_0_ORD_STR_SORTABLE 00024 /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \ 23, /* /cpus */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS \ 25, /* /cpus/cpu@0/itm@e0000000 */ \ 26, /* /cpus/cpu@0/mpu@e000ed90 */ /* Existence and alternate IDs: */ #define DT_N_S_cpus_S_cpu_0_EXISTS 1 #define DT_N_INST_0_arm_cortex_m33f DT_N_S_cpus_S_cpu_0 #define DT_N_NODELABEL_cpu0 DT_N_S_cpus_S_cpu_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_cpus_S_cpu_0_REG_NUM 1 #define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ #define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0 #define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) #define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0 #define DT_N_S_cpus_S_cpu_0_IRQ_LEVEL 0 #define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m33f 1 #define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0 "ARM Ltd." #define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0 "cortex-m33f" #define DT_N_S_cpus_S_cpu_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m33f"} #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m33f" #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UNQUOTED arm,cortex-m33f #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_TOKEN arm_cortex_m33f #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CORTEX_M33F #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0) #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, compatible, 0) #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1 #define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */} #define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0 #define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init 0 #define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0 #define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /cpus/cpu@0/itm@e0000000 * * Node identifier: DT_N_S_cpus_S_cpu_0_S_itm_e0000000 * * Binding (compatible = arm,armv8m-itm): * $ZEPHYR_BASE/dts/bindings/debug/arm,armv8m-itm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PATH "/cpus/cpu@0/itm@e0000000" /* Node's name with unit-address: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FULL_NAME "itm@e0000000" #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FULL_NAME_UNQUOTED itm@e0000000 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FULL_NAME_TOKEN itm_e0000000 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FULL_NAME_UPPER_TOKEN ITM_E0000000 /* Node parent (/cpus/cpu@0) identifier: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PARENT DT_N_S_cpus_S_cpu_0 /* Node's index in its parent's list of children: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_NODELABEL_NUM 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_NODELABEL(fn) fn(itm) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(itm, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_NUM 0 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD(fn) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_ORD 25 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_ORD_STR_SORTABLE 00025 /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REQUIRES_ORDS \ 24, /* /cpus/cpu@0 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_EXISTS 1 #define DT_N_INST_0_arm_armv8m_itm DT_N_S_cpus_S_cpu_0_S_itm_e0000000 #define DT_N_NODELABEL_itm DT_N_S_cpus_S_cpu_0_S_itm_e0000000 /* Macros for properties that are special in the specification: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_NUM 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_VAL_ADDRESS 3758096384 /* 0xe0000000 */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_RANGES_NUM 0 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_RANGE(fn) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_IRQ_NUM 0 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_IRQ_LEVEL 0 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MATCHES_arm_armv8m_itm 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_VENDOR_IDX_0 "ARM Ltd." #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MODEL_IDX_0 "armv8m-itm" #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_swo_ref_frequency 64000000 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_swo_ref_frequency_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible {"arm,armv8m-itm"} #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0 "arm,armv8m-itm" #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-itm #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_itm #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_ITM #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_LEN 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg {3758096384 /* 0xe0000000 */, 4096 /* 0x1000 */} #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_0 3758096384 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_1 4096 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_deferred_init 0 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_wakeup_source 0 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_wakeup_source_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /cpus/cpu@0/mpu@e000ed90 * * Node identifier: DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90 * * Binding (compatible = arm,armv8m-mpu): * $ZEPHYR_BASE/dts/bindings/mmu_mpu/arm,armv8m-mpu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PATH "/cpus/cpu@0/mpu@e000ed90" /* Node's name with unit-address: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME "mpu@e000ed90" #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME_UNQUOTED mpu@e000ed90 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME_TOKEN mpu_e000ed90 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME_UPPER_TOKEN MPU_E000ED90 /* Node parent (/cpus/cpu@0) identifier: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PARENT DT_N_S_cpus_S_cpu_0 /* Node's index in its parent's list of children: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_NODELABEL_NUM 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_NODELABEL(fn) fn(mpu) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_NODELABEL_VARGS(fn, ...) fn(mpu, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_NUM 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD(fn) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD 26 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD_STR_SORTABLE 00026 /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REQUIRES_ORDS \ 24, /* /cpus/cpu@0 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_EXISTS 1 #define DT_N_INST_0_arm_armv8m_mpu DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90 #define DT_N_NODELABEL_mpu DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90 /* Macros for properties that are special in the specification: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_NUM 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS 3758157200 /* 0xe000ed90 */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE 64 /* 0x40 */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_RANGES_NUM 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_RANGE(fn) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_NUM 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_LEVEL 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MATCHES_arm_armv8m_mpu 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_VENDOR_IDX_0 "ARM Ltd." #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MODEL_IDX_0 "armv8m-mpu" #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg {3758157200 /* 0xe000ed90 */, 64 /* 0x40 */} #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0 3758157200 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1 64 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible {"arm,armv8m-mpu"} #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0 "arm,armv8m-mpu" #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-mpu #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_mpu #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_MPU #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_LEN 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_deferred_init 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /ipc * * Node identifier: DT_N_S_ipc */ /* Node's full path: */ #define DT_N_S_ipc_PATH "/ipc" /* Node's name with unit-address: */ #define DT_N_S_ipc_FULL_NAME "ipc" #define DT_N_S_ipc_FULL_NAME_UNQUOTED ipc #define DT_N_S_ipc_FULL_NAME_TOKEN ipc #define DT_N_S_ipc_FULL_NAME_UPPER_TOKEN IPC /* Node parent (/) identifier: */ #define DT_N_S_ipc_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_ipc_CHILD_IDX 7 /* Helpers for dealing with node labels: */ #define DT_N_S_ipc_NODELABEL_NUM 0 #define DT_N_S_ipc_FOREACH_NODELABEL(fn) #define DT_N_S_ipc_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_ipc_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_ipc_CHILD_NUM 2 #define DT_N_S_ipc_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_ipc_FOREACH_CHILD(fn) fn(DT_N_S_ipc_S_ipc0) fn(DT_N_S_ipc_S_ipc1) #define DT_N_S_ipc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc_S_ipc1) #define DT_N_S_ipc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc1, __VA_ARGS__) #define DT_N_S_ipc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc_S_ipc1, __VA_ARGS__) #define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_ipc_S_ipc0) fn(DT_N_S_ipc_S_ipc1) #define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc_S_ipc1) #define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc1, __VA_ARGS__) #define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc_S_ipc1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_ipc_ORD 27 #define DT_N_S_ipc_ORD_STR_SORTABLE 00027 /* Ordinals for what this node depends on directly: */ #define DT_N_S_ipc_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_ipc_SUPPORTS_ORDS \ 31, /* /ipc/ipc1 */ \ 33, /* /ipc/ipc0 */ /* Existence and alternate IDs: */ #define DT_N_S_ipc_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_ipc_REG_NUM 0 #define DT_N_S_ipc_RANGES_NUM 0 #define DT_N_S_ipc_FOREACH_RANGE(fn) #define DT_N_S_ipc_IRQ_NUM 0 #define DT_N_S_ipc_IRQ_LEVEL 0 #define DT_N_S_ipc_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_ipc_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /reserved-memory * * Node identifier: DT_N_S_reserved_memory */ /* Node's full path: */ #define DT_N_S_reserved_memory_PATH "/reserved-memory" /* Node's name with unit-address: */ #define DT_N_S_reserved_memory_FULL_NAME "reserved-memory" #define DT_N_S_reserved_memory_FULL_NAME_UNQUOTED reserved-memory #define DT_N_S_reserved_memory_FULL_NAME_TOKEN reserved_memory #define DT_N_S_reserved_memory_FULL_NAME_UPPER_TOKEN RESERVED_MEMORY /* Node parent (/) identifier: */ #define DT_N_S_reserved_memory_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_reserved_memory_CHILD_IDX 14 /* Helpers for dealing with node labels: */ #define DT_N_S_reserved_memory_NODELABEL_NUM 0 #define DT_N_S_reserved_memory_FOREACH_NODELABEL(fn) #define DT_N_S_reserved_memory_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_reserved_memory_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_reserved_memory_CHILD_NUM 6 #define DT_N_S_reserved_memory_CHILD_NUM_STATUS_OKAY 6 #define DT_N_S_reserved_memory_FOREACH_CHILD(fn) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_image_ns_app_20040000) fn(DT_N_S_reserved_memory_S_memory_20070000) fn(DT_N_S_reserved_memory_S_memory_20078000) #define DT_N_S_reserved_memory_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_app_20040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20070000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20078000) #define DT_N_S_reserved_memory_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_app_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20070000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__) #define DT_N_S_reserved_memory_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_app_20040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20070000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__) #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_image_ns_app_20040000) fn(DT_N_S_reserved_memory_S_memory_20070000) fn(DT_N_S_reserved_memory_S_memory_20078000) #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_app_20040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20070000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20078000) #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_app_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20070000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__) #define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_app_20040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20070000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_reserved_memory_ORD 28 #define DT_N_S_reserved_memory_ORD_STR_SORTABLE 00028 /* Ordinals for what this node depends on directly: */ #define DT_N_S_reserved_memory_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_reserved_memory_SUPPORTS_ORDS \ 29, /* /reserved-memory/memory@20078000 */ \ 32, /* /reserved-memory/memory@20070000 */ \ 105, /* /reserved-memory/image@20000000 */ \ 106, /* /reserved-memory/image_ns@20040000 */ \ 107, /* /reserved-memory/image_ns_app@20040000 */ \ 108, /* /reserved-memory/image_s@20000000 */ /* Existence and alternate IDs: */ #define DT_N_S_reserved_memory_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_reserved_memory_REG_NUM 0 #define DT_N_S_reserved_memory_RANGES_NUM 0 #define DT_N_S_reserved_memory_FOREACH_RANGE(fn) #define DT_N_S_reserved_memory_IRQ_NUM 0 #define DT_N_S_reserved_memory_IRQ_LEVEL 0 #define DT_N_S_reserved_memory_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_reserved_memory_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_reserved_memory_P_ranges_EXISTS 1 /* * Devicetree node: /reserved-memory/memory@20078000 * * Node identifier: DT_N_S_reserved_memory_S_memory_20078000 */ /* Node's full path: */ #define DT_N_S_reserved_memory_S_memory_20078000_PATH "/reserved-memory/memory@20078000" /* Node's name with unit-address: */ #define DT_N_S_reserved_memory_S_memory_20078000_FULL_NAME "memory@20078000" #define DT_N_S_reserved_memory_S_memory_20078000_FULL_NAME_UNQUOTED memory@20078000 #define DT_N_S_reserved_memory_S_memory_20078000_FULL_NAME_TOKEN memory_20078000 #define DT_N_S_reserved_memory_S_memory_20078000_FULL_NAME_UPPER_TOKEN MEMORY_20078000 /* Node parent (/reserved-memory) identifier: */ #define DT_N_S_reserved_memory_S_memory_20078000_PARENT DT_N_S_reserved_memory /* Node's index in its parent's list of children: */ #define DT_N_S_reserved_memory_S_memory_20078000_CHILD_IDX 5 /* Helpers for dealing with node labels: */ #define DT_N_S_reserved_memory_S_memory_20078000_NODELABEL_NUM 1 #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_NODELABEL(fn) fn(sram_ipc1) #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram_ipc1, __VA_ARGS__) #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_ANCESTOR(fn) fn(DT_N_S_reserved_memory) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_reserved_memory_S_memory_20078000_CHILD_NUM 0 #define DT_N_S_reserved_memory_S_memory_20078000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD(fn) #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_reserved_memory_S_memory_20078000_ORD 29 #define DT_N_S_reserved_memory_S_memory_20078000_ORD_STR_SORTABLE 00029 /* Ordinals for what this node depends on directly: */ #define DT_N_S_reserved_memory_S_memory_20078000_REQUIRES_ORDS \ 28, /* /reserved-memory */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_reserved_memory_S_memory_20078000_SUPPORTS_ORDS \ 31, /* /ipc/ipc1 */ /* Existence and alternate IDs: */ #define DT_N_S_reserved_memory_S_memory_20078000_EXISTS 1 #define DT_N_NODELABEL_sram_ipc1 DT_N_S_reserved_memory_S_memory_20078000 /* Macros for properties that are special in the specification: */ #define DT_N_S_reserved_memory_S_memory_20078000_REG_NUM 1 #define DT_N_S_reserved_memory_S_memory_20078000_REG_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_memory_20078000_REG_IDX_0_VAL_ADDRESS 537362432 /* 0x20078000 */ #define DT_N_S_reserved_memory_S_memory_20078000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */ #define DT_N_S_reserved_memory_S_memory_20078000_RANGES_NUM 0 #define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_RANGE(fn) #define DT_N_S_reserved_memory_S_memory_20078000_IRQ_NUM 0 #define DT_N_S_reserved_memory_S_memory_20078000_IRQ_LEVEL 0 #define DT_N_S_reserved_memory_S_memory_20078000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_reserved_memory_S_memory_20078000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_reserved_memory_S_memory_20078000_P_reg {537362432 /* 0x20078000 */, 32768 /* 0x8000 */} #define DT_N_S_reserved_memory_S_memory_20078000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_memory_20078000_P_reg_IDX_0 537362432 #define DT_N_S_reserved_memory_S_memory_20078000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_reserved_memory_S_memory_20078000_P_reg_IDX_1 32768 #define DT_N_S_reserved_memory_S_memory_20078000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/mbox@2a000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 * * Binding (compatible = nordic,mbox-nrf-ipc): * $ZEPHYR_BASE/dts/bindings/mbox/nordic,mbox-nrf-ipc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_PATH "/soc/peripheral@50000000/mbox@2a000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FULL_NAME "mbox@2a000" #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FULL_NAME_UNQUOTED mbox@2a000 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FULL_NAME_TOKEN mbox_2a000 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FULL_NAME_UPPER_TOKEN MBOX_2A000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_CHILD_IDX 42 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_NODELABEL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_NODELABEL(fn) fn(mbox) fn(ipc) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(mbox, __VA_ARGS__) fn(ipc, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_ORD 30 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_ORD_STR_SORTABLE 00030 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_SUPPORTS_ORDS \ 31, /* /ipc/ipc1 */ \ 33, /* /ipc/ipc0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_EXISTS 1 #define DT_N_INST_0_nordic_mbox_nrf_ipc DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 #define DT_N_INST_0_nordic_nrf_ipc DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 #define DT_N_NODELABEL_mbox DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 #define DT_N_NODELABEL_ipc DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_IDX_0_VAL_ADDRESS 1342349312 /* 0x5002a000 */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_irq 42 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MATCHES_nordic_mbox_nrf_ipc 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_0 "mbox-nrf-ipc" #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MATCHES_nordic_nrf_ipc 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_1 "nrf-ipc" #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_tx_mask 65535 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_tx_mask_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_rx_mask 65535 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_rx_mask_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts {42 /* 0x2a */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_0 42 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible {"nordic,mbox-nrf-ipc", "nordic,nrf-ipc"} #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0 "nordic,mbox-nrf-ipc" #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,mbox-nrf-ipc #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_STRING_TOKEN nordic_mbox_nrf_ipc #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_MBOX_NRF_IPC #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1 "nordic,nrf-ipc" #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf-ipc #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_STRING_TOKEN nordic_nrf_ipc #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF_IPC #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg {172032 /* 0x2a000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_0 172032 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /ipc/ipc1 * * Node identifier: DT_N_S_ipc_S_ipc1 * * Binding (compatible = zephyr,ipc-openamp-static-vrings): * $ZEPHYR_BASE/dts/bindings/ipc/zephyr,ipc-openamp-static-vrings.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_ipc_S_ipc1_PATH "/ipc/ipc1" /* Node's name with unit-address: */ #define DT_N_S_ipc_S_ipc1_FULL_NAME "ipc1" #define DT_N_S_ipc_S_ipc1_FULL_NAME_UNQUOTED ipc1 #define DT_N_S_ipc_S_ipc1_FULL_NAME_TOKEN ipc1 #define DT_N_S_ipc_S_ipc1_FULL_NAME_UPPER_TOKEN IPC1 /* Node parent (/ipc) identifier: */ #define DT_N_S_ipc_S_ipc1_PARENT DT_N_S_ipc /* Node's index in its parent's list of children: */ #define DT_N_S_ipc_S_ipc1_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_ipc_S_ipc1_NODELABEL_NUM 1 #define DT_N_S_ipc_S_ipc1_FOREACH_NODELABEL(fn) fn(ipc1) #define DT_N_S_ipc_S_ipc1_FOREACH_NODELABEL_VARGS(fn, ...) fn(ipc1, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_FOREACH_ANCESTOR(fn) fn(DT_N_S_ipc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_ipc_S_ipc1_CHILD_NUM 0 #define DT_N_S_ipc_S_ipc1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_ipc_S_ipc1_FOREACH_CHILD(fn) #define DT_N_S_ipc_S_ipc1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_ipc_S_ipc1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_ipc_S_ipc1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_ipc_S_ipc1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_ipc_S_ipc1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_ipc_S_ipc1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_ipc_S_ipc1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_ipc_S_ipc1_ORD 31 #define DT_N_S_ipc_S_ipc1_ORD_STR_SORTABLE 00031 /* Ordinals for what this node depends on directly: */ #define DT_N_S_ipc_S_ipc1_REQUIRES_ORDS \ 27, /* /ipc */ \ 29, /* /reserved-memory/memory@20078000 */ \ 30, /* /soc/peripheral@50000000/mbox@2a000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_ipc_S_ipc1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_ipc_S_ipc1_EXISTS 1 #define DT_N_INST_1_zephyr_ipc_openamp_static_vrings DT_N_S_ipc_S_ipc1 #define DT_N_NODELABEL_ipc1 DT_N_S_ipc_S_ipc1 /* Macros for properties that are special in the specification: */ #define DT_N_S_ipc_S_ipc1_REG_NUM 0 #define DT_N_S_ipc_S_ipc1_RANGES_NUM 0 #define DT_N_S_ipc_S_ipc1_FOREACH_RANGE(fn) #define DT_N_S_ipc_S_ipc1_IRQ_NUM 0 #define DT_N_S_ipc_S_ipc1_IRQ_LEVEL 0 #define DT_N_S_ipc_S_ipc1_COMPAT_MATCHES_zephyr_ipc_openamp_static_vrings 1 #define DT_N_S_ipc_S_ipc1_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc1_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding" #define DT_N_S_ipc_S_ipc1_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc1_COMPAT_MODEL_IDX_0 "ipc-openamp-static-vrings" #define DT_N_S_ipc_S_ipc1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_ipc_S_ipc1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_ipc_S_ipc1_P_role "host" #define DT_N_S_ipc_S_ipc1_P_role_STRING_UNQUOTED host #define DT_N_S_ipc_S_ipc1_P_role_STRING_TOKEN host #define DT_N_S_ipc_S_ipc1_P_role_STRING_UPPER_TOKEN HOST #define DT_N_S_ipc_S_ipc1_P_role_IDX_0 "host" #define DT_N_S_ipc_S_ipc1_P_role_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_role_IDX_0_ENUM_IDX 0 #define DT_N_S_ipc_S_ipc1_P_role_IDX_0_ENUM_VAL_host_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_role_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc1, role, 0) #define DT_N_S_ipc_S_ipc1_P_role_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc1, role, 0) #define DT_N_S_ipc_S_ipc1_P_role_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc1, role, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_role_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc1, role, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_role_LEN 1 #define DT_N_S_ipc_S_ipc1_P_role_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_memory_region DT_N_S_reserved_memory_S_memory_20078000 #define DT_N_S_ipc_S_ipc1_P_memory_region_IDX_0 DT_N_S_reserved_memory_S_memory_20078000 #define DT_N_S_ipc_S_ipc1_P_memory_region_IDX_0_PH DT_N_S_reserved_memory_S_memory_20078000 #define DT_N_S_ipc_S_ipc1_P_memory_region_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc1, memory_region, 0) #define DT_N_S_ipc_S_ipc1_P_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc1, memory_region, 0) #define DT_N_S_ipc_S_ipc1_P_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc1, memory_region, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc1, memory_region, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_memory_region_LEN 1 #define DT_N_S_ipc_S_ipc1_P_memory_region_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mboxes_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mboxes_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 #define DT_N_S_ipc_S_ipc1_P_mboxes_IDX_0_VAL_channel 2 #define DT_N_S_ipc_S_ipc1_P_mboxes_IDX_0_VAL_channel_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mboxes_IDX_0_NAME "tx" #define DT_N_S_ipc_S_ipc1_P_mboxes_NAME_tx_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 #define DT_N_S_ipc_S_ipc1_P_mboxes_NAME_tx_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mboxes_NAME_tx_VAL_channel DT_N_S_ipc_S_ipc1_P_mboxes_IDX_0_VAL_channel #define DT_N_S_ipc_S_ipc1_P_mboxes_NAME_tx_VAL_channel_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mboxes_IDX_1_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mboxes_IDX_1_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 #define DT_N_S_ipc_S_ipc1_P_mboxes_IDX_1_VAL_channel 3 #define DT_N_S_ipc_S_ipc1_P_mboxes_IDX_1_VAL_channel_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mboxes_IDX_1_NAME "rx" #define DT_N_S_ipc_S_ipc1_P_mboxes_NAME_rx_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 #define DT_N_S_ipc_S_ipc1_P_mboxes_NAME_rx_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mboxes_NAME_rx_VAL_channel DT_N_S_ipc_S_ipc1_P_mboxes_IDX_1_VAL_channel #define DT_N_S_ipc_S_ipc1_P_mboxes_NAME_rx_VAL_channel_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mboxes_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc1, mboxes, 0) \ fn(DT_N_S_ipc_S_ipc1, mboxes, 1) #define DT_N_S_ipc_S_ipc1_P_mboxes_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc1, mboxes, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_ipc_S_ipc1, mboxes, 1) #define DT_N_S_ipc_S_ipc1_P_mboxes_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc1, mboxes, 0, __VA_ARGS__) \ fn(DT_N_S_ipc_S_ipc1, mboxes, 1, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_mboxes_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc1, mboxes, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_ipc_S_ipc1, mboxes, 1, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_mboxes_LEN 2 #define DT_N_S_ipc_S_ipc1_P_mboxes_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mbox_names {"tx", "rx"} #define DT_N_S_ipc_S_ipc1_P_mbox_names_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mbox_names_IDX_0 "tx" #define DT_N_S_ipc_S_ipc1_P_mbox_names_IDX_0_STRING_UNQUOTED tx #define DT_N_S_ipc_S_ipc1_P_mbox_names_IDX_0_STRING_TOKEN tx #define DT_N_S_ipc_S_ipc1_P_mbox_names_IDX_0_STRING_UPPER_TOKEN TX #define DT_N_S_ipc_S_ipc1_P_mbox_names_IDX_1_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_mbox_names_IDX_1 "rx" #define DT_N_S_ipc_S_ipc1_P_mbox_names_IDX_1_STRING_UNQUOTED rx #define DT_N_S_ipc_S_ipc1_P_mbox_names_IDX_1_STRING_TOKEN rx #define DT_N_S_ipc_S_ipc1_P_mbox_names_IDX_1_STRING_UPPER_TOKEN RX #define DT_N_S_ipc_S_ipc1_P_mbox_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc1, mbox_names, 0) \ fn(DT_N_S_ipc_S_ipc1, mbox_names, 1) #define DT_N_S_ipc_S_ipc1_P_mbox_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc1, mbox_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_ipc_S_ipc1, mbox_names, 1) #define DT_N_S_ipc_S_ipc1_P_mbox_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc1, mbox_names, 0, __VA_ARGS__) \ fn(DT_N_S_ipc_S_ipc1, mbox_names, 1, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_mbox_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc1, mbox_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_ipc_S_ipc1, mbox_names, 1, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_mbox_names_LEN 2 #define DT_N_S_ipc_S_ipc1_P_mbox_names_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_zephyr_buffer_size 2048 #define DT_N_S_ipc_S_ipc1_P_zephyr_buffer_size_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_status "okay" #define DT_N_S_ipc_S_ipc1_P_status_STRING_UNQUOTED okay #define DT_N_S_ipc_S_ipc1_P_status_STRING_TOKEN okay #define DT_N_S_ipc_S_ipc1_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_ipc_S_ipc1_P_status_IDX_0 "okay" #define DT_N_S_ipc_S_ipc1_P_status_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_ipc_S_ipc1_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc1, status, 0) #define DT_N_S_ipc_S_ipc1_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc1, status, 0) #define DT_N_S_ipc_S_ipc1_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc1, status, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc1, status, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_status_LEN 1 #define DT_N_S_ipc_S_ipc1_P_status_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_compatible {"zephyr,ipc-openamp-static-vrings"} #define DT_N_S_ipc_S_ipc1_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_compatible_IDX_0 "zephyr,ipc-openamp-static-vrings" #define DT_N_S_ipc_S_ipc1_P_compatible_IDX_0_STRING_UNQUOTED zephyr,ipc-openamp-static-vrings #define DT_N_S_ipc_S_ipc1_P_compatible_IDX_0_STRING_TOKEN zephyr_ipc_openamp_static_vrings #define DT_N_S_ipc_S_ipc1_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_IPC_OPENAMP_STATIC_VRINGS #define DT_N_S_ipc_S_ipc1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc1, compatible, 0) #define DT_N_S_ipc_S_ipc1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc1, compatible, 0) #define DT_N_S_ipc_S_ipc1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc1, compatible, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc1, compatible, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc1_P_compatible_LEN 1 #define DT_N_S_ipc_S_ipc1_P_compatible_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_zephyr_deferred_init 0 #define DT_N_S_ipc_S_ipc1_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_wakeup_source 0 #define DT_N_S_ipc_S_ipc1_P_wakeup_source_EXISTS 1 #define DT_N_S_ipc_S_ipc1_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_ipc_S_ipc1_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /reserved-memory/memory@20070000 * * Node identifier: DT_N_S_reserved_memory_S_memory_20070000 */ /* Node's full path: */ #define DT_N_S_reserved_memory_S_memory_20070000_PATH "/reserved-memory/memory@20070000" /* Node's name with unit-address: */ #define DT_N_S_reserved_memory_S_memory_20070000_FULL_NAME "memory@20070000" #define DT_N_S_reserved_memory_S_memory_20070000_FULL_NAME_UNQUOTED memory@20070000 #define DT_N_S_reserved_memory_S_memory_20070000_FULL_NAME_TOKEN memory_20070000 #define DT_N_S_reserved_memory_S_memory_20070000_FULL_NAME_UPPER_TOKEN MEMORY_20070000 /* Node parent (/reserved-memory) identifier: */ #define DT_N_S_reserved_memory_S_memory_20070000_PARENT DT_N_S_reserved_memory /* Node's index in its parent's list of children: */ #define DT_N_S_reserved_memory_S_memory_20070000_CHILD_IDX 4 /* Helpers for dealing with node labels: */ #define DT_N_S_reserved_memory_S_memory_20070000_NODELABEL_NUM 1 #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_NODELABEL(fn) fn(sram_ipc0) #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram_ipc0, __VA_ARGS__) #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_ANCESTOR(fn) fn(DT_N_S_reserved_memory) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_reserved_memory_S_memory_20070000_CHILD_NUM 0 #define DT_N_S_reserved_memory_S_memory_20070000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD(fn) #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_reserved_memory_S_memory_20070000_ORD 32 #define DT_N_S_reserved_memory_S_memory_20070000_ORD_STR_SORTABLE 00032 /* Ordinals for what this node depends on directly: */ #define DT_N_S_reserved_memory_S_memory_20070000_REQUIRES_ORDS \ 28, /* /reserved-memory */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_reserved_memory_S_memory_20070000_SUPPORTS_ORDS \ 33, /* /ipc/ipc0 */ /* Existence and alternate IDs: */ #define DT_N_S_reserved_memory_S_memory_20070000_EXISTS 1 #define DT_N_NODELABEL_sram_ipc0 DT_N_S_reserved_memory_S_memory_20070000 /* Macros for properties that are special in the specification: */ #define DT_N_S_reserved_memory_S_memory_20070000_REG_NUM 1 #define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_VAL_ADDRESS 537329664 /* 0x20070000 */ #define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */ #define DT_N_S_reserved_memory_S_memory_20070000_RANGES_NUM 0 #define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_RANGE(fn) #define DT_N_S_reserved_memory_S_memory_20070000_IRQ_NUM 0 #define DT_N_S_reserved_memory_S_memory_20070000_IRQ_LEVEL 0 #define DT_N_S_reserved_memory_S_memory_20070000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_reserved_memory_S_memory_20070000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_reserved_memory_S_memory_20070000_P_reg {537329664 /* 0x20070000 */, 32768 /* 0x8000 */} #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_0 537329664 #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_1 32768 #define DT_N_S_reserved_memory_S_memory_20070000_P_reg_EXISTS 1 /* * Devicetree node: /ipc/ipc0 * * Node identifier: DT_N_S_ipc_S_ipc0 * * Binding (compatible = zephyr,ipc-openamp-static-vrings): * $ZEPHYR_BASE/dts/bindings/ipc/zephyr,ipc-openamp-static-vrings.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_ipc_S_ipc0_PATH "/ipc/ipc0" /* Node's name with unit-address: */ #define DT_N_S_ipc_S_ipc0_FULL_NAME "ipc0" #define DT_N_S_ipc_S_ipc0_FULL_NAME_UNQUOTED ipc0 #define DT_N_S_ipc_S_ipc0_FULL_NAME_TOKEN ipc0 #define DT_N_S_ipc_S_ipc0_FULL_NAME_UPPER_TOKEN IPC0 /* Node parent (/ipc) identifier: */ #define DT_N_S_ipc_S_ipc0_PARENT DT_N_S_ipc /* Node's index in its parent's list of children: */ #define DT_N_S_ipc_S_ipc0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_ipc_S_ipc0_NODELABEL_NUM 1 #define DT_N_S_ipc_S_ipc0_FOREACH_NODELABEL(fn) fn(ipc0) #define DT_N_S_ipc_S_ipc0_FOREACH_NODELABEL_VARGS(fn, ...) fn(ipc0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_FOREACH_ANCESTOR(fn) fn(DT_N_S_ipc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_ipc_S_ipc0_CHILD_NUM 1 #define DT_N_S_ipc_S_ipc0_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0) #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0) #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0) #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0) #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_ipc_S_ipc0_ORD 33 #define DT_N_S_ipc_S_ipc0_ORD_STR_SORTABLE 00033 /* Ordinals for what this node depends on directly: */ #define DT_N_S_ipc_S_ipc0_REQUIRES_ORDS \ 27, /* /ipc */ \ 30, /* /soc/peripheral@50000000/mbox@2a000 */ \ 32, /* /reserved-memory/memory@20070000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_ipc_S_ipc0_SUPPORTS_ORDS \ 34, /* /ipc/ipc0/bt_hci_ipc0 */ /* Existence and alternate IDs: */ #define DT_N_S_ipc_S_ipc0_EXISTS 1 #define DT_N_ALIAS_ipc0 DT_N_S_ipc_S_ipc0 #define DT_N_INST_0_zephyr_ipc_openamp_static_vrings DT_N_S_ipc_S_ipc0 #define DT_N_NODELABEL_ipc0 DT_N_S_ipc_S_ipc0 /* Macros for properties that are special in the specification: */ #define DT_N_S_ipc_S_ipc0_REG_NUM 0 #define DT_N_S_ipc_S_ipc0_RANGES_NUM 0 #define DT_N_S_ipc_S_ipc0_FOREACH_RANGE(fn) #define DT_N_S_ipc_S_ipc0_IRQ_NUM 0 #define DT_N_S_ipc_S_ipc0_IRQ_LEVEL 0 #define DT_N_S_ipc_S_ipc0_COMPAT_MATCHES_zephyr_ipc_openamp_static_vrings 1 #define DT_N_S_ipc_S_ipc0_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding" #define DT_N_S_ipc_S_ipc0_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_COMPAT_MODEL_IDX_0 "ipc-openamp-static-vrings" #define DT_N_S_ipc_S_ipc0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_ipc_S_ipc0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_ipc_S_ipc0_P_role "host" #define DT_N_S_ipc_S_ipc0_P_role_STRING_UNQUOTED host #define DT_N_S_ipc_S_ipc0_P_role_STRING_TOKEN host #define DT_N_S_ipc_S_ipc0_P_role_STRING_UPPER_TOKEN HOST #define DT_N_S_ipc_S_ipc0_P_role_IDX_0 "host" #define DT_N_S_ipc_S_ipc0_P_role_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_role_IDX_0_ENUM_IDX 0 #define DT_N_S_ipc_S_ipc0_P_role_IDX_0_ENUM_VAL_host_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, role, 0) #define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, role, 0) #define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, role, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, role, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_role_LEN 1 #define DT_N_S_ipc_S_ipc0_P_role_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_memory_region DT_N_S_reserved_memory_S_memory_20070000 #define DT_N_S_ipc_S_ipc0_P_memory_region_IDX_0 DT_N_S_reserved_memory_S_memory_20070000 #define DT_N_S_ipc_S_ipc0_P_memory_region_IDX_0_PH DT_N_S_reserved_memory_S_memory_20070000 #define DT_N_S_ipc_S_ipc0_P_memory_region_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, memory_region, 0) #define DT_N_S_ipc_S_ipc0_P_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, memory_region, 0) #define DT_N_S_ipc_S_ipc0_P_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, memory_region, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, memory_region, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_memory_region_LEN 1 #define DT_N_S_ipc_S_ipc0_P_memory_region_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_VAL_channel 0 #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_VAL_channel_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_NAME "tx" #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_VAL_channel DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_VAL_channel #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_VAL_channel_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_VAL_channel 1 #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_VAL_channel_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_NAME "rx" #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000 #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_VAL_channel DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_VAL_channel #define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_VAL_channel_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, mboxes, 0) \ fn(DT_N_S_ipc_S_ipc0, mboxes, 1) #define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, mboxes, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_ipc_S_ipc0, mboxes, 1) #define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, mboxes, 0, __VA_ARGS__) \ fn(DT_N_S_ipc_S_ipc0, mboxes, 1, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, mboxes, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_ipc_S_ipc0, mboxes, 1, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_mboxes_LEN 2 #define DT_N_S_ipc_S_ipc0_P_mboxes_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mbox_names {"tx", "rx"} #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0 "tx" #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_STRING_UNQUOTED tx #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_STRING_TOKEN tx #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_STRING_UPPER_TOKEN TX #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1 "rx" #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_STRING_UNQUOTED rx #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_STRING_TOKEN rx #define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_STRING_UPPER_TOKEN RX #define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0) \ fn(DT_N_S_ipc_S_ipc0, mbox_names, 1) #define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_ipc_S_ipc0, mbox_names, 1) #define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0, __VA_ARGS__) \ fn(DT_N_S_ipc_S_ipc0, mbox_names, 1, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_ipc_S_ipc0, mbox_names, 1, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_mbox_names_LEN 2 #define DT_N_S_ipc_S_ipc0_P_mbox_names_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_status "okay" #define DT_N_S_ipc_S_ipc0_P_status_STRING_UNQUOTED okay #define DT_N_S_ipc_S_ipc0_P_status_STRING_TOKEN okay #define DT_N_S_ipc_S_ipc0_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_ipc_S_ipc0_P_status_IDX_0 "okay" #define DT_N_S_ipc_S_ipc0_P_status_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_ipc_S_ipc0_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, status, 0) #define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, status, 0) #define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, status, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, status, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_status_LEN 1 #define DT_N_S_ipc_S_ipc0_P_status_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_compatible {"zephyr,ipc-openamp-static-vrings"} #define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0 "zephyr,ipc-openamp-static-vrings" #define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_STRING_UNQUOTED zephyr,ipc-openamp-static-vrings #define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_STRING_TOKEN zephyr_ipc_openamp_static_vrings #define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_IPC_OPENAMP_STATIC_VRINGS #define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, compatible, 0) #define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, compatible, 0) #define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, compatible, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, compatible, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_P_compatible_LEN 1 #define DT_N_S_ipc_S_ipc0_P_compatible_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_zephyr_deferred_init 0 #define DT_N_S_ipc_S_ipc0_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_wakeup_source 0 #define DT_N_S_ipc_S_ipc0_P_wakeup_source_EXISTS 1 #define DT_N_S_ipc_S_ipc0_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_ipc_S_ipc0_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /ipc/ipc0/bt_hci_ipc0 * * Node identifier: DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0 * * Binding (compatible = zephyr,bt-hci-ipc): * $ZEPHYR_BASE/dts/bindings/bluetooth/zephyr,bt-hci-ipc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_PATH "/ipc/ipc0/bt_hci_ipc0" /* Node's name with unit-address: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FULL_NAME "bt_hci_ipc0" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FULL_NAME_UNQUOTED bt_hci_ipc0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FULL_NAME_TOKEN bt_hci_ipc0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FULL_NAME_UPPER_TOKEN BT_HCI_IPC0 /* Node parent (/ipc/ipc0) identifier: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_PARENT DT_N_S_ipc_S_ipc0 /* Node's index in its parent's list of children: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_NODELABEL_NUM 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_NODELABEL(fn) fn(bt_hci_ipc0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_NODELABEL_VARGS(fn, ...) fn(bt_hci_ipc0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_ANCESTOR(fn) fn(DT_N_S_ipc_S_ipc0) fn(DT_N_S_ipc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_CHILD_NUM 0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD(fn) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_ORD 34 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_ORD_STR_SORTABLE 00034 /* Ordinals for what this node depends on directly: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_REQUIRES_ORDS \ 33, /* /ipc/ipc0 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_EXISTS 1 #define DT_N_INST_0_zephyr_bt_hci_ipc DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0 #define DT_N_NODELABEL_bt_hci_ipc0 DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0 /* Macros for properties that are special in the specification: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_REG_NUM 0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_RANGES_NUM 0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_RANGE(fn) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_IRQ_NUM 0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_IRQ_LEVEL 0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_COMPAT_MATCHES_zephyr_bt_hci_ipc 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_COMPAT_MODEL_IDX_0 "bt-hci-ipc" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name "IPC" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_STRING_UNQUOTED IPC #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_STRING_TOKEN IPC #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_STRING_UPPER_TOKEN IPC #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_IDX_0 "IPC" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_name, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_name, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_name, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_name, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_LEN 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus "ipc" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_STRING_UNQUOTED ipc #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_STRING_TOKEN ipc #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_STRING_UPPER_TOKEN IPC #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_IDX_0 "ipc" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_IDX_0_ENUM_IDX 12 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_IDX_0_ENUM_VAL_ipc_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_bus, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_bus, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_bus, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_bus, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_LEN 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks {"no-auto-dle"} #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0_ENUM_IDX 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0_ENUM_VAL_no_auto_dle_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0 "no-auto-dle" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0_STRING_UNQUOTED no-auto-dle #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0_STRING_TOKEN no_auto_dle #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0_STRING_UPPER_TOKEN NO_AUTO_DLE #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_quirks, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_quirks, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_quirks, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_quirks, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_LEN 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name "nrf_bt_hci" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_STRING_UNQUOTED nrf_bt_hci #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_STRING_TOKEN nrf_bt_hci #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_STRING_UPPER_TOKEN NRF_BT_HCI #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_IDX_0 "nrf_bt_hci" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_ipc_name, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_ipc_name, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_ipc_name, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_ipc_name, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_LEN 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_vs_ext 0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_vs_ext_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status "okay" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_STRING_UNQUOTED okay #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_STRING_TOKEN okay #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_IDX_0 "okay" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, status, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, status, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, status, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, status, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_LEN 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible {"zephyr,bt-hci-ipc"} #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_IDX_0 "zephyr,bt-hci-ipc" #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_IDX_0_STRING_UNQUOTED zephyr,bt-hci-ipc #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_ipc #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_IPC #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, compatible, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, compatible, 0) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, compatible, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, compatible, 0, __VA_ARGS__) #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_LEN 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_zephyr_deferred_init 0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_wakeup_source 0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_wakeup_source_EXISTS 1 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /leds * * Node identifier: DT_N_S_leds * * Binding (compatible = gpio-leds): * $ZEPHYR_BASE/dts/bindings/led/gpio-leds.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_leds_PATH "/leds" /* Node's name with unit-address: */ #define DT_N_S_leds_FULL_NAME "leds" #define DT_N_S_leds_FULL_NAME_UNQUOTED leds #define DT_N_S_leds_FULL_NAME_TOKEN leds #define DT_N_S_leds_FULL_NAME_UPPER_TOKEN LEDS /* Node parent (/) identifier: */ #define DT_N_S_leds_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_leds_CHILD_IDX 8 /* Helpers for dealing with node labels: */ #define DT_N_S_leds_NODELABEL_NUM 0 #define DT_N_S_leds_FOREACH_NODELABEL(fn) #define DT_N_S_leds_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_leds_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_leds_CHILD_NUM 4 #define DT_N_S_leds_CHILD_NUM_STATUS_OKAY 4 #define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) #define DT_N_S_leds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_leds_S_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3) #define DT_N_S_leds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) #define DT_N_S_leds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__) #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_leds_S_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3) #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_leds_ORD 35 #define DT_N_S_leds_ORD_STR_SORTABLE 00035 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_REQUIRES_ORDS \ 0, /* / */ \ 15, /* /soc/peripheral@50000000/gpio@842500 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_SUPPORTS_ORDS \ 36, /* /leds/led_0 */ \ 37, /* /leds/led_1 */ \ 38, /* /leds/led_2 */ \ 39, /* /leds/led_3 */ /* Existence and alternate IDs: */ #define DT_N_S_leds_EXISTS 1 #define DT_N_INST_0_gpio_leds DT_N_S_leds /* Macros for properties that are special in the specification: */ #define DT_N_S_leds_REG_NUM 0 #define DT_N_S_leds_RANGES_NUM 0 #define DT_N_S_leds_FOREACH_RANGE(fn) #define DT_N_S_leds_IRQ_NUM 0 #define DT_N_S_leds_IRQ_LEVEL 0 #define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1 #define DT_N_S_leds_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_leds_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_leds_P_compatible {"gpio-leds"} #define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds" #define DT_N_S_leds_P_compatible_IDX_0_STRING_UNQUOTED gpio-leds #define DT_N_S_leds_P_compatible_IDX_0_STRING_TOKEN gpio_leds #define DT_N_S_leds_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_LEDS #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds, compatible, 0) #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds, compatible, 0) #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__) #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__) #define DT_N_S_leds_P_compatible_LEN 1 #define DT_N_S_leds_P_compatible_EXISTS 1 /* * Devicetree node: /leds/led_0 * * Node identifier: DT_N_S_leds_S_led_0 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_leds_S_led_0_PATH "/leds/led_0" /* Node's name with unit-address: */ #define DT_N_S_leds_S_led_0_FULL_NAME "led_0" #define DT_N_S_leds_S_led_0_FULL_NAME_UNQUOTED led_0 #define DT_N_S_leds_S_led_0_FULL_NAME_TOKEN led_0 #define DT_N_S_leds_S_led_0_FULL_NAME_UPPER_TOKEN LED_0 /* Node parent (/leds) identifier: */ #define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds /* Node's index in its parent's list of children: */ #define DT_N_S_leds_S_led_0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_leds_S_led_0_NODELABEL_NUM 1 #define DT_N_S_leds_S_led_0_FOREACH_NODELABEL(fn) fn(led0) #define DT_N_S_leds_S_led_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(led0, __VA_ARGS__) #define DT_N_S_leds_S_led_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_leds) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_leds_S_led_0_CHILD_NUM 0 #define DT_N_S_leds_S_led_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_leds_S_led_0_ORD 36 #define DT_N_S_leds_S_led_0_ORD_STR_SORTABLE 00036 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_0_REQUIRES_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 35, /* /leds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_leds_S_led_0_EXISTS 1 #define DT_N_NODELABEL_led0 DT_N_S_leds_S_led_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_leds_S_led_0_REG_NUM 0 #define DT_N_S_leds_S_led_0_RANGES_NUM 0 #define DT_N_S_leds_S_led_0_FOREACH_RANGE(fn) #define DT_N_S_leds_S_led_0_IRQ_NUM 0 #define DT_N_S_leds_S_led_0_IRQ_LEVEL 0 #define DT_N_S_leds_S_led_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_leds_S_led_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin 28 #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags 1 #define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, gpios, 0) #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, gpios, 0) #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_0_P_gpios_LEN 1 #define DT_N_S_leds_S_led_0_P_gpios_EXISTS 1 #define DT_N_S_leds_S_led_0_P_label "Green LED 0" #define DT_N_S_leds_S_led_0_P_label_STRING_UNQUOTED Green LED 0 #define DT_N_S_leds_S_led_0_P_label_STRING_TOKEN Green_LED_0 #define DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN GREEN_LED_0 #define DT_N_S_leds_S_led_0_P_label_IDX_0 "Green LED 0" #define DT_N_S_leds_S_led_0_P_label_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, label, 0) #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, label, 0) #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_0_P_label_LEN 1 #define DT_N_S_leds_S_led_0_P_label_EXISTS 1 /* * Devicetree node: /leds/led_1 * * Node identifier: DT_N_S_leds_S_led_1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_leds_S_led_1_PATH "/leds/led_1" /* Node's name with unit-address: */ #define DT_N_S_leds_S_led_1_FULL_NAME "led_1" #define DT_N_S_leds_S_led_1_FULL_NAME_UNQUOTED led_1 #define DT_N_S_leds_S_led_1_FULL_NAME_TOKEN led_1 #define DT_N_S_leds_S_led_1_FULL_NAME_UPPER_TOKEN LED_1 /* Node parent (/leds) identifier: */ #define DT_N_S_leds_S_led_1_PARENT DT_N_S_leds /* Node's index in its parent's list of children: */ #define DT_N_S_leds_S_led_1_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_leds_S_led_1_NODELABEL_NUM 1 #define DT_N_S_leds_S_led_1_FOREACH_NODELABEL(fn) fn(led1) #define DT_N_S_leds_S_led_1_FOREACH_NODELABEL_VARGS(fn, ...) fn(led1, __VA_ARGS__) #define DT_N_S_leds_S_led_1_FOREACH_ANCESTOR(fn) fn(DT_N_S_leds) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_leds_S_led_1_CHILD_NUM 0 #define DT_N_S_leds_S_led_1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_leds_S_led_1_FOREACH_CHILD(fn) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_leds_S_led_1_ORD 37 #define DT_N_S_leds_S_led_1_ORD_STR_SORTABLE 00037 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_1_REQUIRES_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 35, /* /leds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_leds_S_led_1_EXISTS 1 #define DT_N_NODELABEL_led1 DT_N_S_leds_S_led_1 /* Macros for properties that are special in the specification: */ #define DT_N_S_leds_S_led_1_REG_NUM 0 #define DT_N_S_leds_S_led_1_RANGES_NUM 0 #define DT_N_S_leds_S_led_1_FOREACH_RANGE(fn) #define DT_N_S_leds_S_led_1_IRQ_NUM 0 #define DT_N_S_leds_S_led_1_IRQ_LEVEL 0 #define DT_N_S_leds_S_led_1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_leds_S_led_1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin 29 #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags 1 #define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, gpios, 0) #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, gpios, 0) #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_1_P_gpios_LEN 1 #define DT_N_S_leds_S_led_1_P_gpios_EXISTS 1 #define DT_N_S_leds_S_led_1_P_label "Green LED 1" #define DT_N_S_leds_S_led_1_P_label_STRING_UNQUOTED Green LED 1 #define DT_N_S_leds_S_led_1_P_label_STRING_TOKEN Green_LED_1 #define DT_N_S_leds_S_led_1_P_label_STRING_UPPER_TOKEN GREEN_LED_1 #define DT_N_S_leds_S_led_1_P_label_IDX_0 "Green LED 1" #define DT_N_S_leds_S_led_1_P_label_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, label, 0) #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, label, 0) #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_1_P_label_LEN 1 #define DT_N_S_leds_S_led_1_P_label_EXISTS 1 /* * Devicetree node: /leds/led_2 * * Node identifier: DT_N_S_leds_S_led_2 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_leds_S_led_2_PATH "/leds/led_2" /* Node's name with unit-address: */ #define DT_N_S_leds_S_led_2_FULL_NAME "led_2" #define DT_N_S_leds_S_led_2_FULL_NAME_UNQUOTED led_2 #define DT_N_S_leds_S_led_2_FULL_NAME_TOKEN led_2 #define DT_N_S_leds_S_led_2_FULL_NAME_UPPER_TOKEN LED_2 /* Node parent (/leds) identifier: */ #define DT_N_S_leds_S_led_2_PARENT DT_N_S_leds /* Node's index in its parent's list of children: */ #define DT_N_S_leds_S_led_2_CHILD_IDX 2 /* Helpers for dealing with node labels: */ #define DT_N_S_leds_S_led_2_NODELABEL_NUM 1 #define DT_N_S_leds_S_led_2_FOREACH_NODELABEL(fn) fn(led2) #define DT_N_S_leds_S_led_2_FOREACH_NODELABEL_VARGS(fn, ...) fn(led2, __VA_ARGS__) #define DT_N_S_leds_S_led_2_FOREACH_ANCESTOR(fn) fn(DT_N_S_leds) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_leds_S_led_2_CHILD_NUM 0 #define DT_N_S_leds_S_led_2_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_leds_S_led_2_FOREACH_CHILD(fn) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_leds_S_led_2_ORD 38 #define DT_N_S_leds_S_led_2_ORD_STR_SORTABLE 00038 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_2_REQUIRES_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 35, /* /leds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_2_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_leds_S_led_2_EXISTS 1 #define DT_N_NODELABEL_led2 DT_N_S_leds_S_led_2 /* Macros for properties that are special in the specification: */ #define DT_N_S_leds_S_led_2_REG_NUM 0 #define DT_N_S_leds_S_led_2_RANGES_NUM 0 #define DT_N_S_leds_S_led_2_FOREACH_RANGE(fn) #define DT_N_S_leds_S_led_2_IRQ_NUM 0 #define DT_N_S_leds_S_led_2_IRQ_LEVEL 0 #define DT_N_S_leds_S_led_2_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_leds_S_led_2_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin 30 #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags 1 #define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, gpios, 0) #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, gpios, 0) #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_2_P_gpios_LEN 1 #define DT_N_S_leds_S_led_2_P_gpios_EXISTS 1 #define DT_N_S_leds_S_led_2_P_label "Green LED 2" #define DT_N_S_leds_S_led_2_P_label_STRING_UNQUOTED Green LED 2 #define DT_N_S_leds_S_led_2_P_label_STRING_TOKEN Green_LED_2 #define DT_N_S_leds_S_led_2_P_label_STRING_UPPER_TOKEN GREEN_LED_2 #define DT_N_S_leds_S_led_2_P_label_IDX_0 "Green LED 2" #define DT_N_S_leds_S_led_2_P_label_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, label, 0) #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, label, 0) #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_2_P_label_LEN 1 #define DT_N_S_leds_S_led_2_P_label_EXISTS 1 /* * Devicetree node: /leds/led_3 * * Node identifier: DT_N_S_leds_S_led_3 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_leds_S_led_3_PATH "/leds/led_3" /* Node's name with unit-address: */ #define DT_N_S_leds_S_led_3_FULL_NAME "led_3" #define DT_N_S_leds_S_led_3_FULL_NAME_UNQUOTED led_3 #define DT_N_S_leds_S_led_3_FULL_NAME_TOKEN led_3 #define DT_N_S_leds_S_led_3_FULL_NAME_UPPER_TOKEN LED_3 /* Node parent (/leds) identifier: */ #define DT_N_S_leds_S_led_3_PARENT DT_N_S_leds /* Node's index in its parent's list of children: */ #define DT_N_S_leds_S_led_3_CHILD_IDX 3 /* Helpers for dealing with node labels: */ #define DT_N_S_leds_S_led_3_NODELABEL_NUM 1 #define DT_N_S_leds_S_led_3_FOREACH_NODELABEL(fn) fn(led3) #define DT_N_S_leds_S_led_3_FOREACH_NODELABEL_VARGS(fn, ...) fn(led3, __VA_ARGS__) #define DT_N_S_leds_S_led_3_FOREACH_ANCESTOR(fn) fn(DT_N_S_leds) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_leds_S_led_3_CHILD_NUM 0 #define DT_N_S_leds_S_led_3_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_leds_S_led_3_FOREACH_CHILD(fn) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_leds_S_led_3_ORD 39 #define DT_N_S_leds_S_led_3_ORD_STR_SORTABLE 00039 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_3_REQUIRES_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 35, /* /leds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_3_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_leds_S_led_3_EXISTS 1 #define DT_N_NODELABEL_led3 DT_N_S_leds_S_led_3 /* Macros for properties that are special in the specification: */ #define DT_N_S_leds_S_led_3_REG_NUM 0 #define DT_N_S_leds_S_led_3_RANGES_NUM 0 #define DT_N_S_leds_S_led_3_FOREACH_RANGE(fn) #define DT_N_S_leds_S_led_3_IRQ_NUM 0 #define DT_N_S_leds_S_led_3_IRQ_LEVEL 0 #define DT_N_S_leds_S_led_3_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_leds_S_led_3_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin 31 #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags 1 #define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, gpios, 0) #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, gpios, 0) #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_3_P_gpios_LEN 1 #define DT_N_S_leds_S_led_3_P_gpios_EXISTS 1 #define DT_N_S_leds_S_led_3_P_label "Green LED 3" #define DT_N_S_leds_S_led_3_P_label_STRING_UNQUOTED Green LED 3 #define DT_N_S_leds_S_led_3_P_label_STRING_TOKEN Green_LED_3 #define DT_N_S_leds_S_led_3_P_label_STRING_UPPER_TOKEN GREEN_LED_3 #define DT_N_S_leds_S_led_3_P_label_IDX_0 "Green LED 3" #define DT_N_S_leds_S_led_3_P_label_IDX_0_EXISTS 1 #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, label, 0) #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, label, 0) #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__) #define DT_N_S_leds_S_led_3_P_label_LEN 1 #define DT_N_S_leds_S_led_3_P_label_EXISTS 1 /* * Devicetree node: /pin-controller * * Node identifier: DT_N_S_pin_controller * * Binding (compatible = nordic,nrf-pinctrl): * $ZEPHYR_BASE/dts/bindings/pinctrl/nordic,nrf-pinctrl.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_PATH "/pin-controller" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_FULL_NAME "pin-controller" #define DT_N_S_pin_controller_FULL_NAME_UNQUOTED pin-controller #define DT_N_S_pin_controller_FULL_NAME_TOKEN pin_controller #define DT_N_S_pin_controller_FULL_NAME_UPPER_TOKEN PIN_CONTROLLER /* Node parent (/) identifier: */ #define DT_N_S_pin_controller_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_CHILD_IDX 3 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_NODELABEL_NUM 1 #define DT_N_S_pin_controller_FOREACH_NODELABEL(fn) fn(pinctrl) #define DT_N_S_pin_controller_FOREACH_NODELABEL_VARGS(fn, ...) fn(pinctrl, __VA_ARGS__) #define DT_N_S_pin_controller_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_CHILD_NUM 23 #define DT_N_S_pin_controller_CHILD_NUM_STATUS_OKAY 23 #define DT_N_S_pin_controller_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_pwm0_backlight_default) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep) fn(DT_N_S_pin_controller_S_pwm2_motor_default) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep) fn(DT_N_S_pin_controller_S_spi0_sx128x_default) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep) fn(DT_N_S_pin_controller_S_uart2_default) fn(DT_N_S_pin_controller_S_uart2_sleep) fn(DT_N_S_pin_controller_S_spi3_st7789v_default) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep) #define DT_N_S_pin_controller_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_backlight_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm2_motor_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm2_motor_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm3_buzzer_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sx128x_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_st7789v_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep) #define DT_N_S_pin_controller_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_backlight_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm2_motor_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm2_motor_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm3_buzzer_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sx128x_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_st7789v_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_pwm0_backlight_default) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep) fn(DT_N_S_pin_controller_S_pwm2_motor_default) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep) fn(DT_N_S_pin_controller_S_spi0_sx128x_default) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep) fn(DT_N_S_pin_controller_S_uart2_default) fn(DT_N_S_pin_controller_S_uart2_sleep) fn(DT_N_S_pin_controller_S_spi3_st7789v_default) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep) #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_backlight_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm2_motor_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm2_motor_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm3_buzzer_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sx128x_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_st7789v_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep) #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_backlight_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm2_motor_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm2_motor_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm3_buzzer_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sx128x_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_st7789v_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_ORD 40 #define DT_N_S_pin_controller_ORD_STR_SORTABLE 00040 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_REQUIRES_ORDS \ 0, /* / */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_SUPPORTS_ORDS \ 41, /* /pin-controller/spi3_st7789v_default */ \ 42, /* /pin-controller/spi3_st7789v_sleep */ \ 46, /* /pin-controller/i2c1_default */ \ 48, /* /pin-controller/i2c1_sleep */ \ 50, /* /pin-controller/pwm0_backlight_default */ \ 52, /* /pin-controller/pwm0_backlight_sleep */ \ 54, /* /pin-controller/pwm0_sleep */ \ 56, /* /pin-controller/pwm2_motor_default */ \ 58, /* /pin-controller/pwm2_motor_sleep */ \ 60, /* /pin-controller/pwm3_buzzer_default */ \ 62, /* /pin-controller/pwm3_buzzer_sleep */ \ 64, /* /pin-controller/qspi_default */ \ 66, /* /pin-controller/qspi_sleep */ \ 69, /* /pin-controller/spi0_sx128x_default */ \ 71, /* /pin-controller/spi0_sx128x_sleep */ \ 75, /* /pin-controller/spi4_default */ \ 77, /* /pin-controller/spi4_sleep */ \ 79, /* /pin-controller/uart0_default */ \ 82, /* /pin-controller/uart0_sleep */ \ 84, /* /pin-controller/uart1_default */ \ 87, /* /pin-controller/uart1_sleep */ \ 89, /* /pin-controller/uart2_default */ \ 92, /* /pin-controller/uart2_sleep */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_EXISTS 1 #define DT_N_INST_0_nordic_nrf_pinctrl DT_N_S_pin_controller #define DT_N_NODELABEL_pinctrl DT_N_S_pin_controller /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_REG_NUM 0 #define DT_N_S_pin_controller_RANGES_NUM 0 #define DT_N_S_pin_controller_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_IRQ_NUM 0 #define DT_N_S_pin_controller_IRQ_LEVEL 0 #define DT_N_S_pin_controller_COMPAT_MATCHES_nordic_nrf_pinctrl 1 #define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0 "nrf-pinctrl" #define DT_N_S_pin_controller_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_P_compatible {"nordic,nrf-pinctrl"} #define DT_N_S_pin_controller_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_P_compatible_IDX_0 "nordic,nrf-pinctrl" #define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pinctrl #define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pinctrl #define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PINCTRL #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller, compatible, 0) #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller, compatible, 0) #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__) #define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__) #define DT_N_S_pin_controller_P_compatible_LEN 1 #define DT_N_S_pin_controller_P_compatible_EXISTS 1 #define DT_N_S_pin_controller_P_zephyr_deferred_init 0 #define DT_N_S_pin_controller_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_pin_controller_P_wakeup_source 0 #define DT_N_S_pin_controller_P_wakeup_source_EXISTS 1 #define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /pin-controller/spi3_st7789v_default * * Node identifier: DT_N_S_pin_controller_S_spi3_st7789v_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_PATH "/pin-controller/spi3_st7789v_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_FULL_NAME "spi3_st7789v_default" #define DT_N_S_pin_controller_S_spi3_st7789v_default_FULL_NAME_UNQUOTED spi3_st7789v_default #define DT_N_S_pin_controller_S_spi3_st7789v_default_FULL_NAME_TOKEN spi3_st7789v_default #define DT_N_S_pin_controller_S_spi3_st7789v_default_FULL_NAME_UPPER_TOKEN SPI3_ST7789V_DEFAULT /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_CHILD_IDX 21 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_NODELABEL(fn) fn(spi3_st7789v_default) #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3_st7789v_default, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_CHILD_NUM 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1) #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1) #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1) #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1) #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_ORD 41 #define DT_N_S_pin_controller_S_spi3_st7789v_default_ORD_STR_SORTABLE 00041 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_SUPPORTS_ORDS \ 43, /* /soc/peripheral@50000000/spi@c000 */ \ 73, /* /pin-controller/spi3_st7789v_default/group1 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_EXISTS 1 #define DT_N_NODELABEL_spi3_st7789v_default DT_N_S_pin_controller_S_spi3_st7789v_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_REG_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi3_st7789v_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/spi3_st7789v_sleep * * Node identifier: DT_N_S_pin_controller_S_spi3_st7789v_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_PATH "/pin-controller/spi3_st7789v_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FULL_NAME "spi3_st7789v_sleep" #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FULL_NAME_UNQUOTED spi3_st7789v_sleep #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FULL_NAME_TOKEN spi3_st7789v_sleep #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FULL_NAME_UPPER_TOKEN SPI3_ST7789V_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_CHILD_IDX 22 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_NODELABEL(fn) fn(spi3_st7789v_sleep) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3_st7789v_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_ORD 42 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_ORD_STR_SORTABLE 00042 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_SUPPORTS_ORDS \ 43, /* /soc/peripheral@50000000/spi@c000 */ \ 74, /* /pin-controller/spi3_st7789v_sleep/group1 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_EXISTS 1 #define DT_N_NODELABEL_spi3_st7789v_sleep DT_N_S_pin_controller_S_spi3_st7789v_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /soc/peripheral@50000000/spi@c000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_c000 * * Binding (compatible = nordic,nrf-spim): * $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PATH "/soc/peripheral@50000000/spi@c000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FULL_NAME "spi@c000" #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FULL_NAME_UNQUOTED spi@c000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FULL_NAME_TOKEN spi_c000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FULL_NAME_UPPER_TOKEN SPI_C000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_CHILD_IDX 18 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_NODELABEL(fn) fn(spi3) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_ORD 43 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_ORD_STR_SORTABLE 00043 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 41, /* /pin-controller/spi3_st7789v_default */ \ 42, /* /pin-controller/spi3_st7789v_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_SUPPORTS_ORDS \ 44, /* /mipi_dbi_st7789v */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_c000 #define DT_N_NODELABEL_spi3 DT_N_S_soc_S_peripheral_50000000_S_spi_c000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_irq 12 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_MATCHES_nordic_nrf_spim 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_MODEL_IDX_0 "nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi3_st7789v_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi3_st7789v_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_anomaly_58_workaround 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_anomaly_58_workaround_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_rx_delay_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_rx_delay_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_0 49152 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_0 12 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi3_st7789v_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi3_st7789v_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_max_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_overrun_character 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_overrun_character_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_easydma_maxcnt_bits 16 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_IDX_0_VAL_pin 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_IDX_0_VAL_flags 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, cs_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, cs_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, cs_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, cs_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_cs_gpios_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible {"nordic,nrf-spim"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0 "nordic,nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi3_st7789v_sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi3_st7789v_sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_pinctrl_1_EXISTS 1 /* * Devicetree node: /mipi_dbi_st7789v * * Node identifier: DT_N_S_mipi_dbi_st7789v * * Binding (compatible = zephyr,mipi-dbi-spi): * $ZEPHYR_BASE/dts/bindings/mipi-dbi/zephyr,mipi-dbi-spi.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_mipi_dbi_st7789v_PATH "/mipi_dbi_st7789v" /* Node's name with unit-address: */ #define DT_N_S_mipi_dbi_st7789v_FULL_NAME "mipi_dbi_st7789v" #define DT_N_S_mipi_dbi_st7789v_FULL_NAME_UNQUOTED mipi_dbi_st7789v #define DT_N_S_mipi_dbi_st7789v_FULL_NAME_TOKEN mipi_dbi_st7789v #define DT_N_S_mipi_dbi_st7789v_FULL_NAME_UPPER_TOKEN MIPI_DBI_ST7789V /* Node parent (/) identifier: */ #define DT_N_S_mipi_dbi_st7789v_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_mipi_dbi_st7789v_CHILD_IDX 16 /* Helpers for dealing with node labels: */ #define DT_N_S_mipi_dbi_st7789v_NODELABEL_NUM 0 #define DT_N_S_mipi_dbi_st7789v_FOREACH_NODELABEL(fn) #define DT_N_S_mipi_dbi_st7789v_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_mipi_dbi_st7789v_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_mipi_dbi_st7789v_CHILD_NUM 1 #define DT_N_S_mipi_dbi_st7789v_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_mipi_dbi_st7789v_FOREACH_CHILD(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0) #define DT_N_S_mipi_dbi_st7789v_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0) #define DT_N_S_mipi_dbi_st7789v_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0) #define DT_N_S_mipi_dbi_st7789v_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0) #define DT_N_S_mipi_dbi_st7789v_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_mipi_dbi_st7789v_ORD 44 #define DT_N_S_mipi_dbi_st7789v_ORD_STR_SORTABLE 00044 /* Ordinals for what this node depends on directly: */ #define DT_N_S_mipi_dbi_st7789v_REQUIRES_ORDS \ 0, /* / */ \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 16, /* /soc/peripheral@50000000/gpio@842800 */ \ 43, /* /soc/peripheral@50000000/spi@c000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_mipi_dbi_st7789v_SUPPORTS_ORDS \ 45, /* /mipi_dbi_st7789v/st7789v@0 */ /* Existence and alternate IDs: */ #define DT_N_S_mipi_dbi_st7789v_EXISTS 1 #define DT_N_INST_0_zephyr_mipi_dbi_spi DT_N_S_mipi_dbi_st7789v /* Macros for properties that are special in the specification: */ #define DT_N_S_mipi_dbi_st7789v_REG_NUM 0 #define DT_N_S_mipi_dbi_st7789v_RANGES_NUM 0 #define DT_N_S_mipi_dbi_st7789v_FOREACH_RANGE(fn) #define DT_N_S_mipi_dbi_st7789v_IRQ_NUM 0 #define DT_N_S_mipi_dbi_st7789v_IRQ_LEVEL 0 #define DT_N_S_mipi_dbi_st7789v_COMPAT_MATCHES_zephyr_mipi_dbi_spi 1 #define DT_N_S_mipi_dbi_st7789v_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding" #define DT_N_S_mipi_dbi_st7789v_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_COMPAT_MODEL_IDX_0 "mipi-dbi-spi" #define DT_N_S_mipi_dbi_st7789v_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_mipi_dbi_st7789v_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_mipi_dbi_st7789v_P_spi_dev DT_N_S_soc_S_peripheral_50000000_S_spi_c000 #define DT_N_S_mipi_dbi_st7789v_P_spi_dev_IDX_0 DT_N_S_soc_S_peripheral_50000000_S_spi_c000 #define DT_N_S_mipi_dbi_st7789v_P_spi_dev_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_spi_c000 #define DT_N_S_mipi_dbi_st7789v_P_spi_dev_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_spi_dev_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v, spi_dev, 0) #define DT_N_S_mipi_dbi_st7789v_P_spi_dev_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v, spi_dev, 0) #define DT_N_S_mipi_dbi_st7789v_P_spi_dev_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v, spi_dev, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_P_spi_dev_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v, spi_dev, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_P_spi_dev_LEN 1 #define DT_N_S_mipi_dbi_st7789v_P_spi_dev_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842800 #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_IDX_0_VAL_pin 11 #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_IDX_0_VAL_flags 0 #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v, dc_gpios, 0) #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v, dc_gpios, 0) #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v, dc_gpios, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v, dc_gpios, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_LEN 1 #define DT_N_S_mipi_dbi_st7789v_P_dc_gpios_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_IDX_0_VAL_pin 3 #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_IDX_0_VAL_flags 1 #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v, reset_gpios, 0) #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v, reset_gpios, 0) #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v, reset_gpios, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v, reset_gpios, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_LEN 1 #define DT_N_S_mipi_dbi_st7789v_P_reset_gpios_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_xfr_min_bits 8 #define DT_N_S_mipi_dbi_st7789v_P_xfr_min_bits_IDX_0_ENUM_IDX 0 #define DT_N_S_mipi_dbi_st7789v_P_xfr_min_bits_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_xfr_min_bits_IDX_0_ENUM_VAL_8_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_xfr_min_bits_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_write_only 1 #define DT_N_S_mipi_dbi_st7789v_P_write_only_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_compatible {"zephyr,mipi-dbi-spi"} #define DT_N_S_mipi_dbi_st7789v_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_compatible_IDX_0 "zephyr,mipi-dbi-spi" #define DT_N_S_mipi_dbi_st7789v_P_compatible_IDX_0_STRING_UNQUOTED zephyr,mipi-dbi-spi #define DT_N_S_mipi_dbi_st7789v_P_compatible_IDX_0_STRING_TOKEN zephyr_mipi_dbi_spi #define DT_N_S_mipi_dbi_st7789v_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MIPI_DBI_SPI #define DT_N_S_mipi_dbi_st7789v_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v, compatible, 0) #define DT_N_S_mipi_dbi_st7789v_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v, compatible, 0) #define DT_N_S_mipi_dbi_st7789v_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v, compatible, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v, compatible, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_P_compatible_LEN 1 #define DT_N_S_mipi_dbi_st7789v_P_compatible_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_zephyr_deferred_init 0 #define DT_N_S_mipi_dbi_st7789v_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_wakeup_source 0 #define DT_N_S_mipi_dbi_st7789v_P_wakeup_source_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_mipi_dbi_st7789v_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /mipi_dbi_st7789v/st7789v@0 * * Node identifier: DT_N_S_mipi_dbi_st7789v_S_st7789v_0 * * Binding (compatible = sitronix,st7789v): * $ZEPHYR_BASE/dts/bindings/display/sitronix,st7789v.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_PATH "/mipi_dbi_st7789v/st7789v@0" /* Node's name with unit-address: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FULL_NAME "st7789v@0" #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FULL_NAME_UNQUOTED st7789v@0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FULL_NAME_TOKEN st7789v_0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FULL_NAME_UPPER_TOKEN ST7789V_0 /* Node parent (/mipi_dbi_st7789v) identifier: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_PARENT DT_N_S_mipi_dbi_st7789v /* Node's index in its parent's list of children: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_NODELABEL_NUM 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_NODELABEL(fn) fn(st7789v) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(st7789v, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_mipi_dbi_st7789v) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_CHILD_NUM 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_CHILD(fn) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_ORD 45 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_ORD_STR_SORTABLE 00045 /* Ordinals for what this node depends on directly: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_REQUIRES_ORDS \ 44, /* /mipi_dbi_st7789v */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_EXISTS 1 #define DT_N_INST_0_sitronix_st7789v DT_N_S_mipi_dbi_st7789v_S_st7789v_0 #define DT_N_NODELABEL_st7789v DT_N_S_mipi_dbi_st7789v_S_st7789v_0 /* Bus info (controller: '/mipi_dbi_st7789v', type: '['mipi-dbi']') */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_BUS_mipi_dbi 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_BUS DT_N_S_mipi_dbi_st7789v /* Macros for properties that are special in the specification: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_REG_NUM 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_REG_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_RANGES_NUM 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_FOREACH_RANGE(fn) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_IRQ_NUM 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_IRQ_LEVEL 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_COMPAT_MATCHES_sitronix_st7789v 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_COMPAT_VENDOR_IDX_0 "Sitronix Technology Corporation" #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_COMPAT_MODEL_IDX_0 "st7789v" #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_x_offset 80 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_x_offset_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_y_offset 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_y_offset_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_vcom 25 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_vcom_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_gctrl 53 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_gctrl_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_vrhs 18 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_vrhs_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_vdvs 32 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_vdvs_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mdac 160 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mdac_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_lcm 44 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_lcm_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_colmod 5 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_colmod_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_gamma 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_gamma_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_inversion_off 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_inversion_off_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param {12 /* 0xc */, 12 /* 0xc */, 0 /* 0x0 */, 51 /* 0x33 */, 51 /* 0x33 */} #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_IDX_0 12 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_IDX_1_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_IDX_1 12 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_IDX_2_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_IDX_2 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_IDX_3_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_IDX_3 51 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_IDX_4_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_IDX_4 51 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 0) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 1) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 2) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 3) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 4) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 3) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 4) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 0, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 1, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 2, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 3, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 4, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, porch_param, 4, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_LEN 5 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_porch_param_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param {90 /* 0x5a */, 105 /* 0x69 */, 2 /* 0x2 */, 1 /* 0x1 */} #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_IDX_0 90 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_IDX_1_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_IDX_1 105 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_IDX_2_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_IDX_2 2 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_IDX_3_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_IDX_3 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 0) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 1) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 2) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 3) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 3) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 0, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 1, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 2, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 3, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, cmd2en_param, 3, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_LEN 4 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_cmd2en_param_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pwctrl1_param {164 /* 0xa4 */, 161 /* 0xa1 */} #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pwctrl1_param_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pwctrl1_param_IDX_0 164 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pwctrl1_param_IDX_1_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pwctrl1_param_IDX_1 161 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pwctrl1_param_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pwctrl1_param, 0) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pwctrl1_param, 1) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pwctrl1_param_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pwctrl1_param, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pwctrl1_param, 1) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pwctrl1_param_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pwctrl1_param, 0, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pwctrl1_param, 1, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pwctrl1_param_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pwctrl1_param, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pwctrl1_param, 1, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pwctrl1_param_LEN 2 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pwctrl1_param_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param {208 /* 0xd0 */, 4 /* 0x4 */, 13 /* 0xd */, 17 /* 0x11 */, 19 /* 0x13 */, 43 /* 0x2b */, 63 /* 0x3f */, 84 /* 0x54 */, 76 /* 0x4c */, 24 /* 0x18 */, 13 /* 0xd */, 11 /* 0xb */, 31 /* 0x1f */, 35 /* 0x23 */} #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_0 208 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_1_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_1 4 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_2_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_2 13 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_3_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_3 17 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_4_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_4 19 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_5_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_5 43 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_6_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_6 63 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_7_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_7 84 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_8_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_8 76 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_9_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_9 24 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_10_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_10 13 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_11_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_11 11 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_12_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_12 31 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_13_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_IDX_13 35 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 0) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 1) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 2) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 3) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 4) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 5) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 6) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 7) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 8) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 9) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 10) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 11) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 12) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 13) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 3) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 4) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 5) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 6) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 7) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 8) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 9) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 10) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 11) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 12) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 13) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 0, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 1, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 2, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 3, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 4, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 5, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 6, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 7, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 8, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 9, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 10, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 11, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 12, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 13, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, pvgam_param, 13, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_LEN 14 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_pvgam_param_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param {208 /* 0xd0 */, 4 /* 0x4 */, 12 /* 0xc */, 17 /* 0x11 */, 19 /* 0x13 */, 44 /* 0x2c */, 63 /* 0x3f */, 68 /* 0x44 */, 81 /* 0x51 */, 47 /* 0x2f */, 31 /* 0x1f */, 31 /* 0x1f */, 32 /* 0x20 */, 35 /* 0x23 */} #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_0 208 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_1_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_1 4 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_2_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_2 12 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_3_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_3 17 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_4_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_4 19 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_5_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_5 44 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_6_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_6 63 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_7_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_7 68 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_8_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_8 81 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_9_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_9 47 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_10_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_10 31 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_11_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_11 31 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_12_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_12 32 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_13_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_IDX_13 35 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 0) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 1) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 2) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 3) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 4) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 5) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 6) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 7) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 8) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 9) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 10) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 11) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 12) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 13) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 3) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 4) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 5) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 6) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 7) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 8) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 9) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 10) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 11) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 12) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 13) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 0, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 1, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 2, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 3, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 4, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 5, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 6, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 7, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 8, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 9, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 10, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 11, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 12, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 13, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, nvgam_param, 13, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_LEN 14 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_nvgam_param_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_ram_param {0 /* 0x0 */, 240 /* 0xf0 */} #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_ram_param_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_ram_param_IDX_0 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_ram_param_IDX_1_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_ram_param_IDX_1 240 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_ram_param_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, ram_param, 0) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, ram_param, 1) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_ram_param_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, ram_param, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, ram_param, 1) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_ram_param_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, ram_param, 0, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, ram_param, 1, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_ram_param_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, ram_param, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, ram_param, 1, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_ram_param_LEN 2 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_ram_param_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param {205 /* 0xcd */, 8 /* 0x8 */, 20 /* 0x14 */} #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_IDX_0 205 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_IDX_1_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_IDX_1 8 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_IDX_2_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_IDX_2 20 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 0) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 1) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 2) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 2) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 0, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 1, __VA_ARGS__) \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 2, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, rgb_param, 2, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_LEN 3 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_rgb_param_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode "MIPI_DBI_MODE_SPI_4WIRE" #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_STRING_UNQUOTED MIPI_DBI_MODE_SPI_4WIRE #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_STRING_TOKEN MIPI_DBI_MODE_SPI_4WIRE #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_STRING_UPPER_TOKEN MIPI_DBI_MODE_SPI_4WIRE #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_IDX_0 "MIPI_DBI_MODE_SPI_4WIRE" #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_IDX_0_ENUM_IDX 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_IDX_0_ENUM_VAL_MIPI_DBI_MODE_SPI_4WIRE_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, mipi_mode, 0) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, mipi_mode, 0) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, mipi_mode, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, mipi_mode, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_LEN 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_mode_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_duplex 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_duplex_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_cpol 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_cpol_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_cpha 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_cpha_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_hold_cs 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_hold_cs_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_max_frequency 8000000 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_mipi_max_frequency_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode "MIPI_DBI_TE_NO_EDGE" #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_STRING_UNQUOTED MIPI_DBI_TE_NO_EDGE #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_STRING_TOKEN MIPI_DBI_TE_NO_EDGE #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_STRING_UPPER_TOKEN MIPI_DBI_TE_NO_EDGE #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_IDX_0 "MIPI_DBI_TE_NO_EDGE" #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_IDX_0_ENUM_IDX 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_IDX_0_ENUM_VAL_MIPI_DBI_TE_NO_EDGE_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, te_mode, 0) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, te_mode, 0) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, te_mode, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, te_mode, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_LEN 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_mode_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_delay 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_te_delay_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible {"sitronix,st7789v"} #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible_IDX_0 "sitronix,st7789v" #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible_IDX_0_STRING_UNQUOTED sitronix,st7789v #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible_IDX_0_STRING_TOKEN sitronix_st7789v #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SITRONIX_ST7789V #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, compatible, 0) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, compatible, 0) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, compatible, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, compatible, 0, __VA_ARGS__) #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible_LEN 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_compatible_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_reg {0 /* 0x0 */} #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_reg_IDX_0_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_reg_IDX_0 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_reg_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_zephyr_deferred_init 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_wakeup_source 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_wakeup_source_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_height 240 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_height_EXISTS 1 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_width 240 #define DT_N_S_mipi_dbi_st7789v_S_st7789v_0_P_width_EXISTS 1 /* * Devicetree node: /pin-controller/i2c1_default * * Node identifier: DT_N_S_pin_controller_S_i2c1_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_i2c1_default_PATH "/pin-controller/i2c1_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME "i2c1_default" #define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME_UNQUOTED i2c1_default #define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME_TOKEN i2c1_default #define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME_UPPER_TOKEN I2C1_DEFAULT /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_i2c1_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_i2c1_default_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_i2c1_default_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_NODELABEL(fn) fn(i2c1_default) #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1_default, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_i2c1_default_CHILD_NUM 1 #define DT_N_S_pin_controller_S_i2c1_default_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_i2c1_default_ORD 46 #define DT_N_S_pin_controller_S_i2c1_default_ORD_STR_SORTABLE 00046 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_i2c1_default_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_i2c1_default_SUPPORTS_ORDS \ 47, /* /pin-controller/i2c1_default/group1 */ \ 172, /* /soc/peripheral@50000000/i2c@9000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_i2c1_default_EXISTS 1 #define DT_N_NODELABEL_i2c1_default DT_N_S_pin_controller_S_i2c1_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_i2c1_default_REG_NUM 0 #define DT_N_S_pin_controller_S_i2c1_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_i2c1_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_i2c1_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_i2c1_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_i2c1_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_i2c1_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/i2c1_default/group1 * * Node identifier: DT_N_S_pin_controller_S_i2c1_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_PATH "/pin-controller/i2c1_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/i2c1_default) identifier: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_PARENT DT_N_S_pin_controller_S_i2c1_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_ORD 47 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_ORD_STR_SORTABLE 00047 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_REQUIRES_ORDS \ 46, /* /pin-controller/i2c1_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels {201326626 /* 0xc000022 */, 184549411 /* 0xb000023 */} #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0 201326626 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1 184549411 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_LEN 2 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode 8 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up 1 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/i2c1_sleep * * Node identifier: DT_N_S_pin_controller_S_i2c1_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_i2c1_sleep_PATH "/pin-controller/i2c1_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_i2c1_sleep_FULL_NAME "i2c1_sleep" #define DT_N_S_pin_controller_S_i2c1_sleep_FULL_NAME_UNQUOTED i2c1_sleep #define DT_N_S_pin_controller_S_i2c1_sleep_FULL_NAME_TOKEN i2c1_sleep #define DT_N_S_pin_controller_S_i2c1_sleep_FULL_NAME_UPPER_TOKEN I2C1_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_i2c1_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_i2c1_sleep_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_i2c1_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_NODELABEL(fn) fn(i2c1_sleep) #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_i2c1_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_i2c1_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1) #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1) #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1) #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1) #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_i2c1_sleep_ORD 48 #define DT_N_S_pin_controller_S_i2c1_sleep_ORD_STR_SORTABLE 00048 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_i2c1_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_i2c1_sleep_SUPPORTS_ORDS \ 49, /* /pin-controller/i2c1_sleep/group1 */ \ 172, /* /soc/peripheral@50000000/i2c@9000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_i2c1_sleep_EXISTS 1 #define DT_N_NODELABEL_i2c1_sleep DT_N_S_pin_controller_S_i2c1_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_i2c1_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_i2c1_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_i2c1_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_i2c1_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_i2c1_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_i2c1_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/i2c1_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_i2c1_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PATH "/pin-controller/i2c1_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/i2c1_sleep) identifier: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PARENT DT_N_S_pin_controller_S_i2c1_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_ORD 49 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_ORD_STR_SORTABLE 00049 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REQUIRES_ORDS \ 48, /* /pin-controller/i2c1_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels {201326626 /* 0xc000022 */, 184549411 /* 0xb000023 */} #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0 201326626 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1 184549411 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_LEN 2 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/pwm0_backlight_default * * Node identifier: DT_N_S_pin_controller_S_pwm0_backlight_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_PATH "/pin-controller/pwm0_backlight_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_FULL_NAME "pwm0_backlight_default" #define DT_N_S_pin_controller_S_pwm0_backlight_default_FULL_NAME_UNQUOTED pwm0_backlight_default #define DT_N_S_pin_controller_S_pwm0_backlight_default_FULL_NAME_TOKEN pwm0_backlight_default #define DT_N_S_pin_controller_S_pwm0_backlight_default_FULL_NAME_UPPER_TOKEN PWM0_BACKLIGHT_DEFAULT /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_CHILD_IDX 11 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_NODELABEL(fn) fn(pwm0_backlight_default) #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm0_backlight_default, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_CHILD_NUM 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1) #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1) #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1) #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1) #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_ORD 50 #define DT_N_S_pin_controller_S_pwm0_backlight_default_ORD_STR_SORTABLE 00050 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_SUPPORTS_ORDS \ 51, /* /pin-controller/pwm0_backlight_default/group1 */ \ 97, /* /soc/peripheral@50000000/pwm@21000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_EXISTS 1 #define DT_N_NODELABEL_pwm0_backlight_default DT_N_S_pin_controller_S_pwm0_backlight_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm0_backlight_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/pwm0_backlight_default/group1 * * Node identifier: DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_PATH "/pin-controller/pwm0_backlight_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/pwm0_backlight_default) identifier: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_PARENT DT_N_S_pin_controller_S_pwm0_backlight_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_pwm0_backlight_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_ORD 51 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_ORD_STR_SORTABLE 00051 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_REQUIRES_ORDS \ 50, /* /pin-controller/pwm0_backlight_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_psels {369098780 /* 0x1600001c */} #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_psels_IDX_0 369098780 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_psels_LEN 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_nordic_invert 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_bias_pull_down 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/pwm0_backlight_sleep * * Node identifier: DT_N_S_pin_controller_S_pwm0_backlight_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_PATH "/pin-controller/pwm0_backlight_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FULL_NAME "pwm0_backlight_sleep" #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FULL_NAME_UNQUOTED pwm0_backlight_sleep #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FULL_NAME_TOKEN pwm0_backlight_sleep #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FULL_NAME_UPPER_TOKEN PWM0_BACKLIGHT_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_CHILD_IDX 12 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_NODELABEL(fn) fn(pwm0_backlight_sleep) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm0_backlight_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_ORD 52 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_ORD_STR_SORTABLE 00052 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_SUPPORTS_ORDS \ 53, /* /pin-controller/pwm0_backlight_sleep/group1 */ \ 97, /* /soc/peripheral@50000000/pwm@21000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_EXISTS 1 #define DT_N_NODELABEL_pwm0_backlight_sleep DT_N_S_pin_controller_S_pwm0_backlight_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/pwm0_backlight_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_PATH "/pin-controller/pwm0_backlight_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/pwm0_backlight_sleep) identifier: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_PARENT DT_N_S_pin_controller_S_pwm0_backlight_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_ORD 53 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_ORD_STR_SORTABLE 00053 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_REQUIRES_ORDS \ 52, /* /pin-controller/pwm0_backlight_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_psels {369098780 /* 0x1600001c */} #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_psels_IDX_0 369098780 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_psels_LEN 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/pwm0_sleep * * Node identifier: DT_N_S_pin_controller_S_pwm0_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm0_sleep_PATH "/pin-controller/pwm0_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm0_sleep_FULL_NAME "pwm0_sleep" #define DT_N_S_pin_controller_S_pwm0_sleep_FULL_NAME_UNQUOTED pwm0_sleep #define DT_N_S_pin_controller_S_pwm0_sleep_FULL_NAME_TOKEN pwm0_sleep #define DT_N_S_pin_controller_S_pwm0_sleep_FULL_NAME_UPPER_TOKEN PWM0_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_pwm0_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm0_sleep_CHILD_IDX 4 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm0_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_NODELABEL(fn) fn(pwm0_sleep) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm0_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm0_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_pwm0_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm0_sleep_ORD 54 #define DT_N_S_pin_controller_S_pwm0_sleep_ORD_STR_SORTABLE 00054 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm0_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm0_sleep_SUPPORTS_ORDS \ 55, /* /pin-controller/pwm0_sleep/group1 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm0_sleep_EXISTS 1 #define DT_N_NODELABEL_pwm0_sleep DT_N_S_pin_controller_S_pwm0_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm0_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm0_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm0_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm0_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/pwm0_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_pwm0_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PATH "/pin-controller/pwm0_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/pwm0_sleep) identifier: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_pwm0_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_ORD 55 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_ORD_STR_SORTABLE 00055 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_REQUIRES_ORDS \ 54, /* /pin-controller/pwm0_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels {369098780 /* 0x1600001c */} #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_IDX_0 369098780 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_LEN 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/pwm2_motor_default * * Node identifier: DT_N_S_pin_controller_S_pwm2_motor_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_PATH "/pin-controller/pwm2_motor_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_FULL_NAME "pwm2_motor_default" #define DT_N_S_pin_controller_S_pwm2_motor_default_FULL_NAME_UNQUOTED pwm2_motor_default #define DT_N_S_pin_controller_S_pwm2_motor_default_FULL_NAME_TOKEN pwm2_motor_default #define DT_N_S_pin_controller_S_pwm2_motor_default_FULL_NAME_UPPER_TOKEN PWM2_MOTOR_DEFAULT /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_CHILD_IDX 13 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_NODELABEL(fn) fn(pwm2_motor_default) #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm2_motor_default, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm2_motor_default_CHILD_NUM 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1) #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1) #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1) #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1) #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_ORD 56 #define DT_N_S_pin_controller_S_pwm2_motor_default_ORD_STR_SORTABLE 00056 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_SUPPORTS_ORDS \ 57, /* /pin-controller/pwm2_motor_default/group1 */ \ 98, /* /soc/peripheral@50000000/pwm@23000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_EXISTS 1 #define DT_N_NODELABEL_pwm2_motor_default DT_N_S_pin_controller_S_pwm2_motor_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm2_motor_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/pwm2_motor_default/group1 * * Node identifier: DT_N_S_pin_controller_S_pwm2_motor_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_PATH "/pin-controller/pwm2_motor_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/pwm2_motor_default) identifier: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_PARENT DT_N_S_pin_controller_S_pwm2_motor_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_pwm2_motor_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_ORD 57 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_ORD_STR_SORTABLE 00057 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_REQUIRES_ORDS \ 56, /* /pin-controller/pwm2_motor_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_psels {369098764 /* 0x1600000c */} #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_psels_IDX_0 369098764 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_psels_LEN 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_nordic_invert 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_bias_pull_down 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_pwm2_motor_default_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/pwm2_motor_sleep * * Node identifier: DT_N_S_pin_controller_S_pwm2_motor_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_PATH "/pin-controller/pwm2_motor_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FULL_NAME "pwm2_motor_sleep" #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FULL_NAME_UNQUOTED pwm2_motor_sleep #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FULL_NAME_TOKEN pwm2_motor_sleep #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FULL_NAME_UPPER_TOKEN PWM2_MOTOR_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_CHILD_IDX 14 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_NODELABEL(fn) fn(pwm2_motor_sleep) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm2_motor_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_ORD 58 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_ORD_STR_SORTABLE 00058 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_SUPPORTS_ORDS \ 59, /* /pin-controller/pwm2_motor_sleep/group1 */ \ 98, /* /soc/peripheral@50000000/pwm@23000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_EXISTS 1 #define DT_N_NODELABEL_pwm2_motor_sleep DT_N_S_pin_controller_S_pwm2_motor_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/pwm2_motor_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_PATH "/pin-controller/pwm2_motor_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/pwm2_motor_sleep) identifier: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_PARENT DT_N_S_pin_controller_S_pwm2_motor_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_ORD 59 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_ORD_STR_SORTABLE 00059 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_REQUIRES_ORDS \ 58, /* /pin-controller/pwm2_motor_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_psels {369098764 /* 0x1600000c */} #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_psels_IDX_0 369098764 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_psels_LEN 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/pwm3_buzzer_default * * Node identifier: DT_N_S_pin_controller_S_pwm3_buzzer_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_PATH "/pin-controller/pwm3_buzzer_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FULL_NAME "pwm3_buzzer_default" #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FULL_NAME_UNQUOTED pwm3_buzzer_default #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FULL_NAME_TOKEN pwm3_buzzer_default #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FULL_NAME_UPPER_TOKEN PWM3_BUZZER_DEFAULT /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_CHILD_IDX 15 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_NODELABEL(fn) fn(pwm3_buzzer_default) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm3_buzzer_default, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_CHILD_NUM 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_ORD 60 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_ORD_STR_SORTABLE 00060 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_SUPPORTS_ORDS \ 61, /* /pin-controller/pwm3_buzzer_default/group1 */ \ 99, /* /soc/peripheral@50000000/pwm@24000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_EXISTS 1 #define DT_N_NODELABEL_pwm3_buzzer_default DT_N_S_pin_controller_S_pwm3_buzzer_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/pwm3_buzzer_default/group1 * * Node identifier: DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_PATH "/pin-controller/pwm3_buzzer_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/pwm3_buzzer_default) identifier: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_PARENT DT_N_S_pin_controller_S_pwm3_buzzer_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_ORD 61 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_ORD_STR_SORTABLE 00061 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_REQUIRES_ORDS \ 60, /* /pin-controller/pwm3_buzzer_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_psels {369098772 /* 0x16000014 */} #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_psels_IDX_0 369098772 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_psels_LEN 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_nordic_drive_mode 3 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_nordic_invert 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_bias_pull_down 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/pwm3_buzzer_sleep * * Node identifier: DT_N_S_pin_controller_S_pwm3_buzzer_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_PATH "/pin-controller/pwm3_buzzer_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FULL_NAME "pwm3_buzzer_sleep" #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FULL_NAME_UNQUOTED pwm3_buzzer_sleep #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FULL_NAME_TOKEN pwm3_buzzer_sleep #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FULL_NAME_UPPER_TOKEN PWM3_BUZZER_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_CHILD_IDX 16 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_NODELABEL(fn) fn(pwm3_buzzer_sleep) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm3_buzzer_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_ORD 62 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_ORD_STR_SORTABLE 00062 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_SUPPORTS_ORDS \ 63, /* /pin-controller/pwm3_buzzer_sleep/group1 */ \ 99, /* /soc/peripheral@50000000/pwm@24000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_EXISTS 1 #define DT_N_NODELABEL_pwm3_buzzer_sleep DT_N_S_pin_controller_S_pwm3_buzzer_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/pwm3_buzzer_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_PATH "/pin-controller/pwm3_buzzer_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/pwm3_buzzer_sleep) identifier: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_PARENT DT_N_S_pin_controller_S_pwm3_buzzer_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_ORD 63 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_ORD_STR_SORTABLE 00063 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_REQUIRES_ORDS \ 62, /* /pin-controller/pwm3_buzzer_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_psels {369098772 /* 0x16000014 */} #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_psels_IDX_0 369098772 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1, psels, 0) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_psels_LEN 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/qspi_default * * Node identifier: DT_N_S_pin_controller_S_qspi_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_qspi_default_PATH "/pin-controller/qspi_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_qspi_default_FULL_NAME "qspi_default" #define DT_N_S_pin_controller_S_qspi_default_FULL_NAME_UNQUOTED qspi_default #define DT_N_S_pin_controller_S_qspi_default_FULL_NAME_TOKEN qspi_default #define DT_N_S_pin_controller_S_qspi_default_FULL_NAME_UPPER_TOKEN QSPI_DEFAULT /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_qspi_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_qspi_default_CHILD_IDX 5 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_qspi_default_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_qspi_default_FOREACH_NODELABEL(fn) fn(qspi_default) #define DT_N_S_pin_controller_S_qspi_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(qspi_default, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_qspi_default_CHILD_NUM 1 #define DT_N_S_pin_controller_S_qspi_default_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_qspi_default_S_group1) #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_default_S_group1) #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_qspi_default_S_group1) #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_default_S_group1) #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_qspi_default_ORD 64 #define DT_N_S_pin_controller_S_qspi_default_ORD_STR_SORTABLE 00064 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_qspi_default_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_qspi_default_SUPPORTS_ORDS \ 65, /* /pin-controller/qspi_default/group1 */ \ 178, /* /soc/peripheral@50000000/qspi@2b000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_qspi_default_EXISTS 1 #define DT_N_NODELABEL_qspi_default DT_N_S_pin_controller_S_qspi_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_qspi_default_REG_NUM 0 #define DT_N_S_pin_controller_S_qspi_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_qspi_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_qspi_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_qspi_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_qspi_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_qspi_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/qspi_default/group1 * * Node identifier: DT_N_S_pin_controller_S_qspi_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_PATH "/pin-controller/qspi_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_qspi_default_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/qspi_default) identifier: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_PARENT DT_N_S_pin_controller_S_qspi_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_ORD 65 #define DT_N_S_pin_controller_S_qspi_default_S_group1_ORD_STR_SORTABLE 00065 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_REQUIRES_ORDS \ 64, /* /pin-controller/qspi_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_qspi_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels {486539281 /* 0x1d000011 */, 520093709 /* 0x1f00000d */, 536870926 /* 0x2000000e */, 553648143 /* 0x2100000f */, 570425360 /* 0x22000010 */, 503316498 /* 0x1e000012 */} #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_0 486539281 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_1 520093709 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_2 536870926 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_3_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_3 553648143 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_4_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_4 570425360 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_5_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_5 503316498 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2) \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3) \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4) \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5) #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5) #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_LEN 6 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_drive_mode 3 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_qspi_default_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/qspi_sleep * * Node identifier: DT_N_S_pin_controller_S_qspi_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_qspi_sleep_PATH "/pin-controller/qspi_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_qspi_sleep_FULL_NAME "qspi_sleep" #define DT_N_S_pin_controller_S_qspi_sleep_FULL_NAME_UNQUOTED qspi_sleep #define DT_N_S_pin_controller_S_qspi_sleep_FULL_NAME_TOKEN qspi_sleep #define DT_N_S_pin_controller_S_qspi_sleep_FULL_NAME_UPPER_TOKEN QSPI_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_qspi_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_qspi_sleep_CHILD_IDX 6 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_qspi_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_NODELABEL(fn) fn(qspi_sleep) #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(qspi_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_qspi_sleep_CHILD_NUM 2 #define DT_N_S_pin_controller_S_qspi_sleep_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2) #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2) #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2) #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2) #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_qspi_sleep_ORD 66 #define DT_N_S_pin_controller_S_qspi_sleep_ORD_STR_SORTABLE 00066 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_qspi_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_qspi_sleep_SUPPORTS_ORDS \ 67, /* /pin-controller/qspi_sleep/group1 */ \ 68, /* /pin-controller/qspi_sleep/group2 */ \ 178, /* /soc/peripheral@50000000/qspi@2b000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_qspi_sleep_EXISTS 1 #define DT_N_NODELABEL_qspi_sleep DT_N_S_pin_controller_S_qspi_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_qspi_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_qspi_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_qspi_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_qspi_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/qspi_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_qspi_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_PATH "/pin-controller/qspi_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/qspi_sleep) identifier: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_PARENT DT_N_S_pin_controller_S_qspi_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_ORD 67 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_ORD_STR_SORTABLE 00067 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_REQUIRES_ORDS \ 66, /* /pin-controller/qspi_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels {486539281 /* 0x1d000011 */, 520093709 /* 0x1f00000d */, 536870926 /* 0x2000000e */, 553648143 /* 0x2100000f */, 570425360 /* 0x22000010 */} #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_0 486539281 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_1 520093709 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_2 536870926 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_3_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_3 553648143 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_4_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_4 570425360 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2) \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3) \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_LEN 5 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/qspi_sleep/group2 * * Node identifier: DT_N_S_pin_controller_S_qspi_sleep_S_group2 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_PATH "/pin-controller/qspi_sleep/group2" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FULL_NAME "group2" #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FULL_NAME_UNQUOTED group2 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FULL_NAME_TOKEN group2 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FULL_NAME_UPPER_TOKEN GROUP2 /* Node parent (/pin-controller/qspi_sleep) identifier: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_PARENT DT_N_S_pin_controller_S_qspi_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_CHILD_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_ORD 68 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_ORD_STR_SORTABLE 00068 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_REQUIRES_ORDS \ 66, /* /pin-controller/qspi_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_REG_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_RANGES_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_IRQ_NUM 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels {503316498 /* 0x1e000012 */} #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_IDX_0 503316498 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0, __VA_ARGS__) #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_LEN 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_invert 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_disable 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_up 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_low_power_enable 1 #define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/spi0_sx128x_default * * Node identifier: DT_N_S_pin_controller_S_spi0_sx128x_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_PATH "/pin-controller/spi0_sx128x_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_FULL_NAME "spi0_sx128x_default" #define DT_N_S_pin_controller_S_spi0_sx128x_default_FULL_NAME_UNQUOTED spi0_sx128x_default #define DT_N_S_pin_controller_S_spi0_sx128x_default_FULL_NAME_TOKEN spi0_sx128x_default #define DT_N_S_pin_controller_S_spi0_sx128x_default_FULL_NAME_UPPER_TOKEN SPI0_SX128X_DEFAULT /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_CHILD_IDX 17 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_NODELABEL(fn) fn(spi0_sx128x_default) #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi0_sx128x_default, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_CHILD_NUM 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1) #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1) #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1) #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1) #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_ORD 69 #define DT_N_S_pin_controller_S_spi0_sx128x_default_ORD_STR_SORTABLE 00069 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_SUPPORTS_ORDS \ 70, /* /pin-controller/spi0_sx128x_default/group1 */ \ 185, /* /soc/peripheral@50000000/spi@8000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_EXISTS 1 #define DT_N_NODELABEL_spi0_sx128x_default DT_N_S_pin_controller_S_spi0_sx128x_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_REG_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi0_sx128x_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/spi0_sx128x_default/group1 * * Node identifier: DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_PATH "/pin-controller/spi0_sx128x_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/spi0_sx128x_default) identifier: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_PARENT DT_N_S_pin_controller_S_spi0_sx128x_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_spi0_sx128x_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_ORD 70 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_ORD_STR_SORTABLE 00070 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_REQUIRES_ORDS \ 69, /* /pin-controller/spi0_sx128x_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels {67108886 /* 0x4000016 */, 83886080 /* 0x5000000 */, 100663300 /* 0x6000004 */} #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_IDX_0 67108886 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_IDX_1 83886080 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_IDX_2 100663300 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_LEN 3 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_bias_pull_down 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/spi0_sx128x_sleep * * Node identifier: DT_N_S_pin_controller_S_spi0_sx128x_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_PATH "/pin-controller/spi0_sx128x_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FULL_NAME "spi0_sx128x_sleep" #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FULL_NAME_UNQUOTED spi0_sx128x_sleep #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FULL_NAME_TOKEN spi0_sx128x_sleep #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FULL_NAME_UPPER_TOKEN SPI0_SX128X_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_CHILD_IDX 18 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_NODELABEL(fn) fn(spi0_sx128x_sleep) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi0_sx128x_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_ORD 71 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_ORD_STR_SORTABLE 00071 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_SUPPORTS_ORDS \ 72, /* /pin-controller/spi0_sx128x_sleep/group1 */ \ 185, /* /soc/peripheral@50000000/spi@8000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_EXISTS 1 #define DT_N_NODELABEL_spi0_sx128x_sleep DT_N_S_pin_controller_S_spi0_sx128x_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/spi0_sx128x_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_PATH "/pin-controller/spi0_sx128x_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/spi0_sx128x_sleep) identifier: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi0_sx128x_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_ORD 72 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_ORD_STR_SORTABLE 00072 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_REQUIRES_ORDS \ 71, /* /pin-controller/spi0_sx128x_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels {67108886 /* 0x4000016 */, 83886080 /* 0x5000000 */, 100663300 /* 0x6000004 */} #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_IDX_0 67108886 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_IDX_1 83886080 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_IDX_2 100663300 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_LEN 3 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/spi3_st7789v_default/group1 * * Node identifier: DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_PATH "/pin-controller/spi3_st7789v_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/spi3_st7789v_default) identifier: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_PARENT DT_N_S_pin_controller_S_spi3_st7789v_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_spi3_st7789v_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_ORD 73 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_ORD_STR_SORTABLE 00073 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_REQUIRES_ORDS \ 41, /* /pin-controller/spi3_st7789v_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels {67108909 /* 0x400002d */, 83886110 /* 0x500001e */, 100663343 /* 0x600002f */} #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_IDX_0 67108909 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_IDX_1 83886110 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_IDX_2 100663343 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_LEN 3 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_bias_pull_down 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/spi3_st7789v_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_PATH "/pin-controller/spi3_st7789v_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/spi3_st7789v_sleep) identifier: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi3_st7789v_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_ORD 74 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_ORD_STR_SORTABLE 00074 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_REQUIRES_ORDS \ 42, /* /pin-controller/spi3_st7789v_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels {67108909 /* 0x400002d */, 83886110 /* 0x500001e */, 100663343 /* 0x600002f */} #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_IDX_0 67108909 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_IDX_1 83886110 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_IDX_2 100663343 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_LEN 3 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/spi4_default * * Node identifier: DT_N_S_pin_controller_S_spi4_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi4_default_PATH "/pin-controller/spi4_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi4_default_FULL_NAME "spi4_default" #define DT_N_S_pin_controller_S_spi4_default_FULL_NAME_UNQUOTED spi4_default #define DT_N_S_pin_controller_S_spi4_default_FULL_NAME_TOKEN spi4_default #define DT_N_S_pin_controller_S_spi4_default_FULL_NAME_UPPER_TOKEN SPI4_DEFAULT /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_spi4_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi4_default_CHILD_IDX 9 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi4_default_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_spi4_default_FOREACH_NODELABEL(fn) fn(spi4_default) #define DT_N_S_pin_controller_S_spi4_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi4_default, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi4_default_CHILD_NUM 1 #define DT_N_S_pin_controller_S_spi4_default_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi4_default_S_group1) #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_default_S_group1) #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi4_default_S_group1) #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_default_S_group1) #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi4_default_ORD 75 #define DT_N_S_pin_controller_S_spi4_default_ORD_STR_SORTABLE 00075 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi4_default_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi4_default_SUPPORTS_ORDS \ 76, /* /pin-controller/spi4_default/group1 */ \ 144, /* /soc/peripheral@50000000/spi@a000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi4_default_EXISTS 1 #define DT_N_NODELABEL_spi4_default DT_N_S_pin_controller_S_spi4_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi4_default_REG_NUM 0 #define DT_N_S_pin_controller_S_spi4_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi4_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi4_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi4_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi4_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi4_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/spi4_default/group1 * * Node identifier: DT_N_S_pin_controller_S_spi4_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_PATH "/pin-controller/spi4_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_spi4_default_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_spi4_default_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_spi4_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/spi4_default) identifier: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_PARENT DT_N_S_pin_controller_S_spi4_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_ORD 76 #define DT_N_S_pin_controller_S_spi4_default_S_group1_ORD_STR_SORTABLE 00076 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_REQUIRES_ORDS \ 75, /* /pin-controller/spi4_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi4_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels {67108911 /* 0x400002f */, 100663342 /* 0x600002e */, 83886125 /* 0x500002d */} #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_0 67108911 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_1 100663342 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_2 83886125 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_LEN 3 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_spi4_default_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/spi4_sleep * * Node identifier: DT_N_S_pin_controller_S_spi4_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi4_sleep_PATH "/pin-controller/spi4_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi4_sleep_FULL_NAME "spi4_sleep" #define DT_N_S_pin_controller_S_spi4_sleep_FULL_NAME_UNQUOTED spi4_sleep #define DT_N_S_pin_controller_S_spi4_sleep_FULL_NAME_TOKEN spi4_sleep #define DT_N_S_pin_controller_S_spi4_sleep_FULL_NAME_UPPER_TOKEN SPI4_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_spi4_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi4_sleep_CHILD_IDX 10 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi4_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_NODELABEL(fn) fn(spi4_sleep) #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi4_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi4_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_spi4_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1) #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1) #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1) #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1) #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi4_sleep_ORD 77 #define DT_N_S_pin_controller_S_spi4_sleep_ORD_STR_SORTABLE 00077 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi4_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi4_sleep_SUPPORTS_ORDS \ 78, /* /pin-controller/spi4_sleep/group1 */ \ 144, /* /soc/peripheral@50000000/spi@a000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi4_sleep_EXISTS 1 #define DT_N_NODELABEL_spi4_sleep DT_N_S_pin_controller_S_spi4_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi4_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_spi4_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi4_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi4_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi4_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi4_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/spi4_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_spi4_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_PATH "/pin-controller/spi4_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/spi4_sleep) identifier: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi4_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_ORD 78 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_ORD_STR_SORTABLE 00078 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_REQUIRES_ORDS \ 77, /* /pin-controller/spi4_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels {67108911 /* 0x400002f */, 100663342 /* 0x600002e */, 83886125 /* 0x500002d */} #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_0 67108911 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_1 100663342 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_2 83886125 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2, __VA_ARGS__) #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_LEN 3 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/uart0_default * * Node identifier: DT_N_S_pin_controller_S_uart0_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart0_default_PATH "/pin-controller/uart0_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart0_default_FULL_NAME "uart0_default" #define DT_N_S_pin_controller_S_uart0_default_FULL_NAME_UNQUOTED uart0_default #define DT_N_S_pin_controller_S_uart0_default_FULL_NAME_TOKEN uart0_default #define DT_N_S_pin_controller_S_uart0_default_FULL_NAME_UPPER_TOKEN UART0_DEFAULT /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_uart0_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart0_default_CHILD_IDX 2 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart0_default_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_uart0_default_FOREACH_NODELABEL(fn) fn(uart0_default) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart0_default, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart0_default_CHILD_NUM 2 #define DT_N_S_pin_controller_S_uart0_default_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart0_default_ORD 79 #define DT_N_S_pin_controller_S_uart0_default_ORD_STR_SORTABLE 00079 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart0_default_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart0_default_SUPPORTS_ORDS \ 80, /* /pin-controller/uart0_default/group1 */ \ 81, /* /pin-controller/uart0_default/group2 */ \ 148, /* /soc/peripheral@50000000/uart@8000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart0_default_EXISTS 1 #define DT_N_NODELABEL_uart0_default DT_N_S_pin_controller_S_uart0_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart0_default_REG_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart0_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart0_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart0_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/uart0_default/group1 * * Node identifier: DT_N_S_pin_controller_S_uart0_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_PATH "/pin-controller/uart0_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/uart0_default) identifier: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_PARENT DT_N_S_pin_controller_S_uart0_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD 80 #define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD_STR_SORTABLE 00080 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_REQUIRES_ORDS \ 79, /* /pin-controller/uart0_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels {20 /* 0x14 */, 33554451 /* 0x2000013 */} #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0 20 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_1 33554451 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_LEN 2 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/uart0_default/group2 * * Node identifier: DT_N_S_pin_controller_S_uart0_default_S_group2 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_PATH "/pin-controller/uart0_default/group2" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME "group2" #define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME_UNQUOTED group2 #define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME_TOKEN group2 #define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME_UPPER_TOKEN GROUP2 /* Node parent (/pin-controller/uart0_default) identifier: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_PARENT DT_N_S_pin_controller_S_uart0_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_ORD 81 #define DT_N_S_pin_controller_S_uart0_default_S_group2_ORD_STR_SORTABLE 00081 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_REQUIRES_ORDS \ 79, /* /pin-controller/uart0_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_REG_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels {16777238 /* 0x1000016 */, 50331669 /* 0x3000015 */} #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0 16777238 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_1 50331669 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0) \ fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1) #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1) #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_LEN 2 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable 0 #define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/uart0_sleep * * Node identifier: DT_N_S_pin_controller_S_uart0_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart0_sleep_PATH "/pin-controller/uart0_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart0_sleep_FULL_NAME "uart0_sleep" #define DT_N_S_pin_controller_S_uart0_sleep_FULL_NAME_UNQUOTED uart0_sleep #define DT_N_S_pin_controller_S_uart0_sleep_FULL_NAME_TOKEN uart0_sleep #define DT_N_S_pin_controller_S_uart0_sleep_FULL_NAME_UPPER_TOKEN UART0_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_uart0_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart0_sleep_CHILD_IDX 3 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart0_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_NODELABEL(fn) fn(uart0_sleep) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart0_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart0_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_uart0_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart0_sleep_ORD 82 #define DT_N_S_pin_controller_S_uart0_sleep_ORD_STR_SORTABLE 00082 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart0_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart0_sleep_SUPPORTS_ORDS \ 83, /* /pin-controller/uart0_sleep/group1 */ \ 148, /* /soc/peripheral@50000000/uart@8000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart0_sleep_EXISTS 1 #define DT_N_NODELABEL_uart0_sleep DT_N_S_pin_controller_S_uart0_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart0_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart0_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart0_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart0_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/uart0_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_uart0_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PATH "/pin-controller/uart0_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/uart0_sleep) identifier: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart0_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_ORD 83 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_ORD_STR_SORTABLE 00083 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REQUIRES_ORDS \ 82, /* /pin-controller/uart0_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels {20 /* 0x14 */, 16777238 /* 0x1000016 */, 33554451 /* 0x2000013 */, 50331669 /* 0x3000015 */} #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0 20 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1 16777238 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_2 33554451 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_3_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_3 50331669 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_LEN 4 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/uart1_default * * Node identifier: DT_N_S_pin_controller_S_uart1_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart1_default_PATH "/pin-controller/uart1_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart1_default_FULL_NAME "uart1_default" #define DT_N_S_pin_controller_S_uart1_default_FULL_NAME_UNQUOTED uart1_default #define DT_N_S_pin_controller_S_uart1_default_FULL_NAME_TOKEN uart1_default #define DT_N_S_pin_controller_S_uart1_default_FULL_NAME_UPPER_TOKEN UART1_DEFAULT /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_uart1_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart1_default_CHILD_IDX 7 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart1_default_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_uart1_default_FOREACH_NODELABEL(fn) fn(uart1_default) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart1_default, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart1_default_CHILD_NUM 2 #define DT_N_S_pin_controller_S_uart1_default_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart1_default_ORD 84 #define DT_N_S_pin_controller_S_uart1_default_ORD_STR_SORTABLE 00084 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart1_default_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart1_default_SUPPORTS_ORDS \ 85, /* /pin-controller/uart1_default/group1 */ \ 86, /* /pin-controller/uart1_default/group2 */ \ 149, /* /soc/peripheral@50000000/uart@9000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart1_default_EXISTS 1 #define DT_N_NODELABEL_uart1_default DT_N_S_pin_controller_S_uart1_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart1_default_REG_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart1_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart1_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart1_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/uart1_default/group1 * * Node identifier: DT_N_S_pin_controller_S_uart1_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_PATH "/pin-controller/uart1_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_uart1_default_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/uart1_default) identifier: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_PARENT DT_N_S_pin_controller_S_uart1_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_ORD 85 #define DT_N_S_pin_controller_S_uart1_default_S_group1_ORD_STR_SORTABLE 00085 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_REQUIRES_ORDS \ 84, /* /pin-controller/uart1_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels {33 /* 0x21 */, 33554443 /* 0x200000b */} #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_0 33 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_1 33554443 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_LEN 2 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_uart1_default_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/uart1_default/group2 * * Node identifier: DT_N_S_pin_controller_S_uart1_default_S_group2 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_PATH "/pin-controller/uart1_default/group2" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_FULL_NAME "group2" #define DT_N_S_pin_controller_S_uart1_default_S_group2_FULL_NAME_UNQUOTED group2 #define DT_N_S_pin_controller_S_uart1_default_S_group2_FULL_NAME_TOKEN group2 #define DT_N_S_pin_controller_S_uart1_default_S_group2_FULL_NAME_UPPER_TOKEN GROUP2 /* Node parent (/pin-controller/uart1_default) identifier: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_PARENT DT_N_S_pin_controller_S_uart1_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_ORD 86 #define DT_N_S_pin_controller_S_uart1_default_S_group2_ORD_STR_SORTABLE 00086 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_REQUIRES_ORDS \ 84, /* /pin-controller/uart1_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_REG_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart1_default_S_group2_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels {16777248 /* 0x1000020 */, 50331658 /* 0x300000a */} #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_0 16777248 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_1 50331658 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0) \ fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 1) #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 1) #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_LEN 2 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_up 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_low_power_enable 0 #define DT_N_S_pin_controller_S_uart1_default_S_group2_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/uart1_sleep * * Node identifier: DT_N_S_pin_controller_S_uart1_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart1_sleep_PATH "/pin-controller/uart1_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart1_sleep_FULL_NAME "uart1_sleep" #define DT_N_S_pin_controller_S_uart1_sleep_FULL_NAME_UNQUOTED uart1_sleep #define DT_N_S_pin_controller_S_uart1_sleep_FULL_NAME_TOKEN uart1_sleep #define DT_N_S_pin_controller_S_uart1_sleep_FULL_NAME_UPPER_TOKEN UART1_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_uart1_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart1_sleep_CHILD_IDX 8 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart1_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_NODELABEL(fn) fn(uart1_sleep) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart1_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart1_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_uart1_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart1_sleep_ORD 87 #define DT_N_S_pin_controller_S_uart1_sleep_ORD_STR_SORTABLE 00087 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart1_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart1_sleep_SUPPORTS_ORDS \ 88, /* /pin-controller/uart1_sleep/group1 */ \ 149, /* /soc/peripheral@50000000/uart@9000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart1_sleep_EXISTS 1 #define DT_N_NODELABEL_uart1_sleep DT_N_S_pin_controller_S_uart1_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart1_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart1_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart1_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart1_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/uart1_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_uart1_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PATH "/pin-controller/uart1_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/uart1_sleep) identifier: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart1_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_ORD 88 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_ORD_STR_SORTABLE 00088 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_REQUIRES_ORDS \ 87, /* /pin-controller/uart1_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels {33 /* 0x21 */, 16777248 /* 0x1000020 */, 33554443 /* 0x200000b */, 50331658 /* 0x300000a */} #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_0 33 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_1 16777248 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_2 33554443 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_3_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_3 50331658 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 2) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 3) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 3) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 2, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 3, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 3, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_LEN 4 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/uart2_default * * Node identifier: DT_N_S_pin_controller_S_uart2_default * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart2_default_PATH "/pin-controller/uart2_default" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart2_default_FULL_NAME "uart2_default" #define DT_N_S_pin_controller_S_uart2_default_FULL_NAME_UNQUOTED uart2_default #define DT_N_S_pin_controller_S_uart2_default_FULL_NAME_TOKEN uart2_default #define DT_N_S_pin_controller_S_uart2_default_FULL_NAME_UPPER_TOKEN UART2_DEFAULT /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_uart2_default_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart2_default_CHILD_IDX 19 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart2_default_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_uart2_default_FOREACH_NODELABEL(fn) fn(uart2_default) #define DT_N_S_pin_controller_S_uart2_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart2_default, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart2_default_CHILD_NUM 2 #define DT_N_S_pin_controller_S_uart2_default_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart2_default_S_group1) fn(DT_N_S_pin_controller_S_uart2_default_S_group2) #define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart2_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_default_S_group2) #define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart2_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart2_default_S_group1) fn(DT_N_S_pin_controller_S_uart2_default_S_group2) #define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart2_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_default_S_group2) #define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default_S_group2, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart2_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart2_default_S_group2, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart2_default_ORD 89 #define DT_N_S_pin_controller_S_uart2_default_ORD_STR_SORTABLE 00089 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart2_default_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart2_default_SUPPORTS_ORDS \ 90, /* /pin-controller/uart2_default/group1 */ \ 91, /* /pin-controller/uart2_default/group2 */ \ 150, /* /soc/peripheral@50000000/uart@b000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart2_default_EXISTS 1 #define DT_N_NODELABEL_uart2_default DT_N_S_pin_controller_S_uart2_default /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart2_default_REG_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart2_default_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart2_default_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart2_default_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/uart2_default/group1 * * Node identifier: DT_N_S_pin_controller_S_uart2_default_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_PATH "/pin-controller/uart2_default/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_uart2_default_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_uart2_default_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_uart2_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/uart2_default) identifier: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_PARENT DT_N_S_pin_controller_S_uart2_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_uart2_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_ORD 90 #define DT_N_S_pin_controller_S_uart2_default_S_group1_ORD_STR_SORTABLE 00090 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_REQUIRES_ORDS \ 89, /* /pin-controller/uart2_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart2_default_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels {44 /* 0x2c */, 33554478 /* 0x200002e */} #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_0 44 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_1 33554478 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 1) #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_LEN 2 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_low_power_enable 0 #define DT_N_S_pin_controller_S_uart2_default_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/uart2_default/group2 * * Node identifier: DT_N_S_pin_controller_S_uart2_default_S_group2 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_PATH "/pin-controller/uart2_default/group2" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_FULL_NAME "group2" #define DT_N_S_pin_controller_S_uart2_default_S_group2_FULL_NAME_UNQUOTED group2 #define DT_N_S_pin_controller_S_uart2_default_S_group2_FULL_NAME_TOKEN group2 #define DT_N_S_pin_controller_S_uart2_default_S_group2_FULL_NAME_UPPER_TOKEN GROUP2 /* Node parent (/pin-controller/uart2_default) identifier: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_PARENT DT_N_S_pin_controller_S_uart2_default /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_uart2_default) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_ORD 91 #define DT_N_S_pin_controller_S_uart2_default_S_group2_ORD_STR_SORTABLE 00091 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_REQUIRES_ORDS \ 89, /* /pin-controller/uart2_default */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_REG_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart2_default_S_group2_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_psels {16777258 /* 0x100002a */, 50331687 /* 0x3000027 */} #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_psels_IDX_0 16777258 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_psels_IDX_1 50331687 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart2_default_S_group2, psels, 0) \ fn(DT_N_S_pin_controller_S_uart2_default_S_group2, psels, 1) #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart2_default_S_group2, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart2_default_S_group2, psels, 1) #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart2_default_S_group2, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart2_default_S_group2, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart2_default_S_group2, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart2_default_S_group2, psels, 1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_psels_LEN 2 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_bias_pull_up 1 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_low_power_enable 0 #define DT_N_S_pin_controller_S_uart2_default_S_group2_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pin-controller/uart2_sleep * * Node identifier: DT_N_S_pin_controller_S_uart2_sleep * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart2_sleep_PATH "/pin-controller/uart2_sleep" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart2_sleep_FULL_NAME "uart2_sleep" #define DT_N_S_pin_controller_S_uart2_sleep_FULL_NAME_UNQUOTED uart2_sleep #define DT_N_S_pin_controller_S_uart2_sleep_FULL_NAME_TOKEN uart2_sleep #define DT_N_S_pin_controller_S_uart2_sleep_FULL_NAME_UPPER_TOKEN UART2_SLEEP /* Node parent (/pin-controller) identifier: */ #define DT_N_S_pin_controller_S_uart2_sleep_PARENT DT_N_S_pin_controller /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart2_sleep_CHILD_IDX 20 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart2_sleep_NODELABEL_NUM 1 #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_NODELABEL(fn) fn(uart2_sleep) #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart2_sleep, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart2_sleep_CHILD_NUM 1 #define DT_N_S_pin_controller_S_uart2_sleep_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1) #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1) #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1) #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1) #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart2_sleep_ORD 92 #define DT_N_S_pin_controller_S_uart2_sleep_ORD_STR_SORTABLE 00092 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart2_sleep_REQUIRES_ORDS \ 40, /* /pin-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart2_sleep_SUPPORTS_ORDS \ 93, /* /pin-controller/uart2_sleep/group1 */ \ 150, /* /soc/peripheral@50000000/uart@b000 */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart2_sleep_EXISTS 1 #define DT_N_NODELABEL_uart2_sleep DT_N_S_pin_controller_S_uart2_sleep /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart2_sleep_REG_NUM 0 #define DT_N_S_pin_controller_S_uart2_sleep_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart2_sleep_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart2_sleep_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart2_sleep_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart2_sleep_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /pin-controller/uart2_sleep/group1 * * Node identifier: DT_N_S_pin_controller_S_uart2_sleep_S_group1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_PATH "/pin-controller/uart2_sleep/group1" /* Node's name with unit-address: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FULL_NAME "group1" #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FULL_NAME_UNQUOTED group1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FULL_NAME_TOKEN group1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FULL_NAME_UPPER_TOKEN GROUP1 /* Node parent (/pin-controller/uart2_sleep) identifier: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart2_sleep /* Node's index in its parent's list of children: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_NODELABEL_NUM 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_NODELABEL(fn) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_uart2_sleep) fn(DT_N_S_pin_controller) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_CHILD_NUM 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD(fn) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_ORD 93 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_ORD_STR_SORTABLE 00093 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_REQUIRES_ORDS \ 92, /* /pin-controller/uart2_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_REG_NUM 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_RANGES_NUM 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_RANGE(fn) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_IRQ_NUM 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_IRQ_LEVEL 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels {44 /* 0x2c */, 16777258 /* 0x100002a */, 33554478 /* 0x200002e */, 50331687 /* 0x3000027 */} #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_0_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_0 44 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_1_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_1 16777258 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_2_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_2 33554478 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_3_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_3 50331687 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 0) \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 1) \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 2) \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 3) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 3) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 0, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 1, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 2, __VA_ARGS__) \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 3, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 3, __VA_ARGS__) #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_LEN 4 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_drive_mode 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_drive_mode_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_invert 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_invert_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_disable 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_disable_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_up 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_up_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_down 0 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_down_EXISTS 1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_low_power_enable 1 #define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_low_power_enable_EXISTS 1 /* * Devicetree node: /pins_io * * Node identifier: DT_N_S_pins_io * * Binding (compatible = gpio-keys): * $ZEPHYR_BASE/dts/bindings/input/gpio-keys.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pins_io_PATH "/pins_io" /* Node's name with unit-address: */ #define DT_N_S_pins_io_FULL_NAME "pins_io" #define DT_N_S_pins_io_FULL_NAME_UNQUOTED pins_io #define DT_N_S_pins_io_FULL_NAME_TOKEN pins_io #define DT_N_S_pins_io_FULL_NAME_UPPER_TOKEN PINS_IO /* Node parent (/) identifier: */ #define DT_N_S_pins_io_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_pins_io_CHILD_IDX 17 /* Helpers for dealing with node labels: */ #define DT_N_S_pins_io_NODELABEL_NUM 0 #define DT_N_S_pins_io_FOREACH_NODELABEL(fn) #define DT_N_S_pins_io_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pins_io_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pins_io_CHILD_NUM 2 #define DT_N_S_pins_io_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_pins_io_FOREACH_CHILD(fn) fn(DT_N_S_pins_io_S_key1) fn(DT_N_S_pins_io_S_en_motor) #define DT_N_S_pins_io_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pins_io_S_key1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pins_io_S_en_motor) #define DT_N_S_pins_io_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pins_io_S_key1, __VA_ARGS__) fn(DT_N_S_pins_io_S_en_motor, __VA_ARGS__) #define DT_N_S_pins_io_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pins_io_S_key1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pins_io_S_en_motor, __VA_ARGS__) #define DT_N_S_pins_io_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pins_io_S_key1) fn(DT_N_S_pins_io_S_en_motor) #define DT_N_S_pins_io_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pins_io_S_key1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pins_io_S_en_motor) #define DT_N_S_pins_io_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pins_io_S_key1, __VA_ARGS__) fn(DT_N_S_pins_io_S_en_motor, __VA_ARGS__) #define DT_N_S_pins_io_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pins_io_S_key1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pins_io_S_en_motor, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pins_io_ORD 94 #define DT_N_S_pins_io_ORD_STR_SORTABLE 00094 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pins_io_REQUIRES_ORDS \ 0, /* / */ \ 15, /* /soc/peripheral@50000000/gpio@842500 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pins_io_SUPPORTS_ORDS \ 95, /* /pins_io/en_motor */ \ 96, /* /pins_io/key1 */ /* Existence and alternate IDs: */ #define DT_N_S_pins_io_EXISTS 1 #define DT_N_INST_1_gpio_keys DT_N_S_pins_io /* Macros for properties that are special in the specification: */ #define DT_N_S_pins_io_REG_NUM 0 #define DT_N_S_pins_io_RANGES_NUM 0 #define DT_N_S_pins_io_FOREACH_RANGE(fn) #define DT_N_S_pins_io_IRQ_NUM 0 #define DT_N_S_pins_io_IRQ_LEVEL 0 #define DT_N_S_pins_io_COMPAT_MATCHES_gpio_keys 1 #define DT_N_S_pins_io_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pins_io_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pins_io_P_debounce_interval_ms 30 #define DT_N_S_pins_io_P_debounce_interval_ms_EXISTS 1 #define DT_N_S_pins_io_P_polling_mode 0 #define DT_N_S_pins_io_P_polling_mode_EXISTS 1 #define DT_N_S_pins_io_P_no_disconnect 0 #define DT_N_S_pins_io_P_no_disconnect_EXISTS 1 #define DT_N_S_pins_io_P_compatible {"gpio-keys"} #define DT_N_S_pins_io_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_pins_io_P_compatible_IDX_0 "gpio-keys" #define DT_N_S_pins_io_P_compatible_IDX_0_STRING_UNQUOTED gpio-keys #define DT_N_S_pins_io_P_compatible_IDX_0_STRING_TOKEN gpio_keys #define DT_N_S_pins_io_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_KEYS #define DT_N_S_pins_io_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pins_io, compatible, 0) #define DT_N_S_pins_io_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pins_io, compatible, 0) #define DT_N_S_pins_io_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pins_io, compatible, 0, __VA_ARGS__) #define DT_N_S_pins_io_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pins_io, compatible, 0, __VA_ARGS__) #define DT_N_S_pins_io_P_compatible_LEN 1 #define DT_N_S_pins_io_P_compatible_EXISTS 1 #define DT_N_S_pins_io_P_zephyr_deferred_init 0 #define DT_N_S_pins_io_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_pins_io_P_wakeup_source 0 #define DT_N_S_pins_io_P_wakeup_source_EXISTS 1 #define DT_N_S_pins_io_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_pins_io_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /pins_io/en_motor * * Node identifier: DT_N_S_pins_io_S_en_motor * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pins_io_S_en_motor_PATH "/pins_io/en_motor" /* Node's name with unit-address: */ #define DT_N_S_pins_io_S_en_motor_FULL_NAME "en_motor" #define DT_N_S_pins_io_S_en_motor_FULL_NAME_UNQUOTED en_motor #define DT_N_S_pins_io_S_en_motor_FULL_NAME_TOKEN en_motor #define DT_N_S_pins_io_S_en_motor_FULL_NAME_UPPER_TOKEN EN_MOTOR /* Node parent (/pins_io) identifier: */ #define DT_N_S_pins_io_S_en_motor_PARENT DT_N_S_pins_io /* Node's index in its parent's list of children: */ #define DT_N_S_pins_io_S_en_motor_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_pins_io_S_en_motor_NODELABEL_NUM 1 #define DT_N_S_pins_io_S_en_motor_FOREACH_NODELABEL(fn) fn(en_motor) #define DT_N_S_pins_io_S_en_motor_FOREACH_NODELABEL_VARGS(fn, ...) fn(en_motor, __VA_ARGS__) #define DT_N_S_pins_io_S_en_motor_FOREACH_ANCESTOR(fn) fn(DT_N_S_pins_io) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pins_io_S_en_motor_CHILD_NUM 0 #define DT_N_S_pins_io_S_en_motor_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pins_io_S_en_motor_FOREACH_CHILD(fn) #define DT_N_S_pins_io_S_en_motor_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pins_io_S_en_motor_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pins_io_S_en_motor_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pins_io_S_en_motor_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pins_io_S_en_motor_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pins_io_S_en_motor_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pins_io_S_en_motor_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pins_io_S_en_motor_ORD 95 #define DT_N_S_pins_io_S_en_motor_ORD_STR_SORTABLE 00095 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pins_io_S_en_motor_REQUIRES_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 94, /* /pins_io */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pins_io_S_en_motor_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pins_io_S_en_motor_EXISTS 1 #define DT_N_NODELABEL_en_motor DT_N_S_pins_io_S_en_motor /* Macros for properties that are special in the specification: */ #define DT_N_S_pins_io_S_en_motor_REG_NUM 0 #define DT_N_S_pins_io_S_en_motor_RANGES_NUM 0 #define DT_N_S_pins_io_S_en_motor_FOREACH_RANGE(fn) #define DT_N_S_pins_io_S_en_motor_IRQ_NUM 0 #define DT_N_S_pins_io_S_en_motor_IRQ_LEVEL 0 #define DT_N_S_pins_io_S_en_motor_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pins_io_S_en_motor_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pins_io_S_en_motor_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_pins_io_S_en_motor_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_pins_io_S_en_motor_P_gpios_IDX_0_VAL_pin 8 #define DT_N_S_pins_io_S_en_motor_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_pins_io_S_en_motor_P_gpios_IDX_0_VAL_flags 32 #define DT_N_S_pins_io_S_en_motor_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_pins_io_S_en_motor_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pins_io_S_en_motor, gpios, 0) #define DT_N_S_pins_io_S_en_motor_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pins_io_S_en_motor, gpios, 0) #define DT_N_S_pins_io_S_en_motor_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pins_io_S_en_motor, gpios, 0, __VA_ARGS__) #define DT_N_S_pins_io_S_en_motor_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pins_io_S_en_motor, gpios, 0, __VA_ARGS__) #define DT_N_S_pins_io_S_en_motor_P_gpios_LEN 1 #define DT_N_S_pins_io_S_en_motor_P_gpios_EXISTS 1 #define DT_N_S_pins_io_S_en_motor_P_label "en_motor" #define DT_N_S_pins_io_S_en_motor_P_label_STRING_UNQUOTED en_motor #define DT_N_S_pins_io_S_en_motor_P_label_STRING_TOKEN en_motor #define DT_N_S_pins_io_S_en_motor_P_label_STRING_UPPER_TOKEN EN_MOTOR #define DT_N_S_pins_io_S_en_motor_P_label_IDX_0 "en_motor" #define DT_N_S_pins_io_S_en_motor_P_label_IDX_0_EXISTS 1 #define DT_N_S_pins_io_S_en_motor_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pins_io_S_en_motor, label, 0) #define DT_N_S_pins_io_S_en_motor_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pins_io_S_en_motor, label, 0) #define DT_N_S_pins_io_S_en_motor_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pins_io_S_en_motor, label, 0, __VA_ARGS__) #define DT_N_S_pins_io_S_en_motor_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pins_io_S_en_motor, label, 0, __VA_ARGS__) #define DT_N_S_pins_io_S_en_motor_P_label_LEN 1 #define DT_N_S_pins_io_S_en_motor_P_label_EXISTS 1 #define DT_N_S_pins_io_S_en_motor_P_zephyr_code 11 #define DT_N_S_pins_io_S_en_motor_P_zephyr_code_EXISTS 1 /* * Devicetree node: /pins_io/key1 * * Node identifier: DT_N_S_pins_io_S_key1 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pins_io_S_key1_PATH "/pins_io/key1" /* Node's name with unit-address: */ #define DT_N_S_pins_io_S_key1_FULL_NAME "key1" #define DT_N_S_pins_io_S_key1_FULL_NAME_UNQUOTED key1 #define DT_N_S_pins_io_S_key1_FULL_NAME_TOKEN key1 #define DT_N_S_pins_io_S_key1_FULL_NAME_UPPER_TOKEN KEY1 /* Node parent (/pins_io) identifier: */ #define DT_N_S_pins_io_S_key1_PARENT DT_N_S_pins_io /* Node's index in its parent's list of children: */ #define DT_N_S_pins_io_S_key1_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pins_io_S_key1_NODELABEL_NUM 1 #define DT_N_S_pins_io_S_key1_FOREACH_NODELABEL(fn) fn(key1) #define DT_N_S_pins_io_S_key1_FOREACH_NODELABEL_VARGS(fn, ...) fn(key1, __VA_ARGS__) #define DT_N_S_pins_io_S_key1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pins_io) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pins_io_S_key1_CHILD_NUM 0 #define DT_N_S_pins_io_S_key1_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pins_io_S_key1_FOREACH_CHILD(fn) #define DT_N_S_pins_io_S_key1_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pins_io_S_key1_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pins_io_S_key1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pins_io_S_key1_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pins_io_S_key1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pins_io_S_key1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pins_io_S_key1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pins_io_S_key1_ORD 96 #define DT_N_S_pins_io_S_key1_ORD_STR_SORTABLE 00096 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pins_io_S_key1_REQUIRES_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 94, /* /pins_io */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pins_io_S_key1_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pins_io_S_key1_EXISTS 1 #define DT_N_NODELABEL_key1 DT_N_S_pins_io_S_key1 /* Macros for properties that are special in the specification: */ #define DT_N_S_pins_io_S_key1_REG_NUM 0 #define DT_N_S_pins_io_S_key1_RANGES_NUM 0 #define DT_N_S_pins_io_S_key1_FOREACH_RANGE(fn) #define DT_N_S_pins_io_S_key1_IRQ_NUM 0 #define DT_N_S_pins_io_S_key1_IRQ_LEVEL 0 #define DT_N_S_pins_io_S_key1_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pins_io_S_key1_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pins_io_S_key1_P_gpios_IDX_0_EXISTS 1 #define DT_N_S_pins_io_S_key1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_pins_io_S_key1_P_gpios_IDX_0_VAL_pin 31 #define DT_N_S_pins_io_S_key1_P_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_pins_io_S_key1_P_gpios_IDX_0_VAL_flags 17 #define DT_N_S_pins_io_S_key1_P_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_pins_io_S_key1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pins_io_S_key1, gpios, 0) #define DT_N_S_pins_io_S_key1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pins_io_S_key1, gpios, 0) #define DT_N_S_pins_io_S_key1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pins_io_S_key1, gpios, 0, __VA_ARGS__) #define DT_N_S_pins_io_S_key1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pins_io_S_key1, gpios, 0, __VA_ARGS__) #define DT_N_S_pins_io_S_key1_P_gpios_LEN 1 #define DT_N_S_pins_io_S_key1_P_gpios_EXISTS 1 #define DT_N_S_pins_io_S_key1_P_label "key1" #define DT_N_S_pins_io_S_key1_P_label_STRING_UNQUOTED key1 #define DT_N_S_pins_io_S_key1_P_label_STRING_TOKEN key1 #define DT_N_S_pins_io_S_key1_P_label_STRING_UPPER_TOKEN KEY1 #define DT_N_S_pins_io_S_key1_P_label_IDX_0 "key1" #define DT_N_S_pins_io_S_key1_P_label_IDX_0_EXISTS 1 #define DT_N_S_pins_io_S_key1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pins_io_S_key1, label, 0) #define DT_N_S_pins_io_S_key1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pins_io_S_key1, label, 0) #define DT_N_S_pins_io_S_key1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pins_io_S_key1, label, 0, __VA_ARGS__) #define DT_N_S_pins_io_S_key1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pins_io_S_key1, label, 0, __VA_ARGS__) #define DT_N_S_pins_io_S_key1_P_label_LEN 1 #define DT_N_S_pins_io_S_key1_P_label_EXISTS 1 #define DT_N_S_pins_io_S_key1_P_zephyr_code 11 #define DT_N_S_pins_io_S_key1_P_zephyr_code_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/pwm@21000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_21000 * * Binding (compatible = nordic,nrf-pwm): * $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PATH "/soc/peripheral@50000000/pwm@21000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FULL_NAME "pwm@21000" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FULL_NAME_UNQUOTED pwm@21000 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FULL_NAME_TOKEN pwm_21000 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FULL_NAME_UPPER_TOKEN PWM_21000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_CHILD_IDX 36 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_NODELABEL(fn) fn(pwm0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_ORD 97 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_ORD_STR_SORTABLE 00097 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 50, /* /pin-controller/pwm0_backlight_default */ \ 52, /* /pin-controller/pwm0_backlight_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_SUPPORTS_ORDS \ 100, /* /pwmleds */ \ 101, /* /pwmleds/backlight */ \ 104, /* /pwmleds/pwm_led_0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_21000 #define DT_N_NODELABEL_pwm0 DT_N_S_soc_S_peripheral_50000000_S_pwm_21000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_ADDRESS 1342312448 /* 0x50021000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq 33 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MATCHES_nordic_nrf_pwm 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MODEL_IDX_0 "nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_pwm0_backlight_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_pwm0_backlight_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg {135168 /* 0x21000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_0 135168 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_pwm0_backlight_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_pwm0_backlight_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible {"nordic,nrf-pwm"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0 "nordic,nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts {33 /* 0x21 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_0 33 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_pwm0_backlight_sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_pwm0_backlight_sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_pinctrl_1_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/pwm@23000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_23000 * * Binding (compatible = nordic,nrf-pwm): * $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PATH "/soc/peripheral@50000000/pwm@23000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FULL_NAME "pwm@23000" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FULL_NAME_UNQUOTED pwm@23000 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FULL_NAME_TOKEN pwm_23000 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FULL_NAME_UPPER_TOKEN PWM_23000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_CHILD_IDX 38 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_NODELABEL(fn) fn(pwm2) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_ORD 98 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_ORD_STR_SORTABLE 00098 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 56, /* /pin-controller/pwm2_motor_default */ \ 58, /* /pin-controller/pwm2_motor_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_SUPPORTS_ORDS \ 100, /* /pwmleds */ \ 103, /* /pwmleds/motor */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_23000 #define DT_N_NODELABEL_pwm2 DT_N_S_soc_S_peripheral_50000000_S_pwm_23000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_ADDRESS 1342320640 /* 0x50023000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq 35 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MATCHES_nordic_nrf_pwm 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MODEL_IDX_0 "nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_pwm2_motor_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_pwm2_motor_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg {143360 /* 0x23000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_0 143360 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_pwm2_motor_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_pwm2_motor_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible {"nordic,nrf-pwm"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0 "nordic,nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts {35 /* 0x23 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_0 35 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_pwm2_motor_sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_pwm2_motor_sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_pinctrl_1_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/pwm@24000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_24000 * * Binding (compatible = nordic,nrf-pwm): * $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PATH "/soc/peripheral@50000000/pwm@24000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FULL_NAME "pwm@24000" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FULL_NAME_UNQUOTED pwm@24000 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FULL_NAME_TOKEN pwm_24000 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FULL_NAME_UPPER_TOKEN PWM_24000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_CHILD_IDX 39 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_NODELABEL(fn) fn(pwm3) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm3, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_ORD 99 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_ORD_STR_SORTABLE 00099 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 60, /* /pin-controller/pwm3_buzzer_default */ \ 62, /* /pin-controller/pwm3_buzzer_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_SUPPORTS_ORDS \ 100, /* /pwmleds */ \ 102, /* /pwmleds/buzzer */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_24000 #define DT_N_NODELABEL_pwm3 DT_N_S_soc_S_peripheral_50000000_S_pwm_24000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_ADDRESS 1342324736 /* 0x50024000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq 36 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MATCHES_nordic_nrf_pwm 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MODEL_IDX_0 "nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_pwm3_buzzer_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_pwm3_buzzer_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg {147456 /* 0x24000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_0 147456 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_pwm3_buzzer_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_pwm3_buzzer_default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible {"nordic,nrf-pwm"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0 "nordic,nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts {36 /* 0x24 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_0 36 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_pwm3_buzzer_sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_pwm3_buzzer_sleep #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_pinctrl_1_EXISTS 1 /* * Devicetree node: /pwmleds * * Node identifier: DT_N_S_pwmleds * * Binding (compatible = pwm-leds): * $ZEPHYR_BASE/dts/bindings/led/pwm-leds.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pwmleds_PATH "/pwmleds" /* Node's name with unit-address: */ #define DT_N_S_pwmleds_FULL_NAME "pwmleds" #define DT_N_S_pwmleds_FULL_NAME_UNQUOTED pwmleds #define DT_N_S_pwmleds_FULL_NAME_TOKEN pwmleds #define DT_N_S_pwmleds_FULL_NAME_UPPER_TOKEN PWMLEDS /* Node parent (/) identifier: */ #define DT_N_S_pwmleds_PARENT DT_N /* Node's index in its parent's list of children: */ #define DT_N_S_pwmleds_CHILD_IDX 11 /* Helpers for dealing with node labels: */ #define DT_N_S_pwmleds_NODELABEL_NUM 0 #define DT_N_S_pwmleds_FOREACH_NODELABEL(fn) #define DT_N_S_pwmleds_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_pwmleds_FOREACH_ANCESTOR(fn) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pwmleds_CHILD_NUM 4 #define DT_N_S_pwmleds_CHILD_NUM_STATUS_OKAY 4 #define DT_N_S_pwmleds_FOREACH_CHILD(fn) fn(DT_N_S_pwmleds_S_pwm_led_0) fn(DT_N_S_pwmleds_S_backlight) fn(DT_N_S_pwmleds_S_motor) fn(DT_N_S_pwmleds_S_buzzer) #define DT_N_S_pwmleds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_backlight) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_motor) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_buzzer) #define DT_N_S_pwmleds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) fn(DT_N_S_pwmleds_S_backlight, __VA_ARGS__) fn(DT_N_S_pwmleds_S_motor, __VA_ARGS__) fn(DT_N_S_pwmleds_S_buzzer, __VA_ARGS__) #define DT_N_S_pwmleds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_backlight, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_motor, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_buzzer, __VA_ARGS__) #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pwmleds_S_pwm_led_0) fn(DT_N_S_pwmleds_S_backlight) fn(DT_N_S_pwmleds_S_motor) fn(DT_N_S_pwmleds_S_buzzer) #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_backlight) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_motor) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_buzzer) #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) fn(DT_N_S_pwmleds_S_backlight, __VA_ARGS__) fn(DT_N_S_pwmleds_S_motor, __VA_ARGS__) fn(DT_N_S_pwmleds_S_buzzer, __VA_ARGS__) #define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_backlight, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_motor, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds_S_buzzer, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_pwmleds_ORD 100 #define DT_N_S_pwmleds_ORD_STR_SORTABLE 00100 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pwmleds_REQUIRES_ORDS \ 0, /* / */ \ 97, /* /soc/peripheral@50000000/pwm@21000 */ \ 98, /* /soc/peripheral@50000000/pwm@23000 */ \ 99, /* /soc/peripheral@50000000/pwm@24000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pwmleds_SUPPORTS_ORDS \ 101, /* /pwmleds/backlight */ \ 102, /* /pwmleds/buzzer */ \ 103, /* /pwmleds/motor */ \ 104, /* /pwmleds/pwm_led_0 */ /* Existence and alternate IDs: */ #define DT_N_S_pwmleds_EXISTS 1 #define DT_N_INST_0_pwm_leds DT_N_S_pwmleds /* Macros for properties that are special in the specification: */ #define DT_N_S_pwmleds_REG_NUM 0 #define DT_N_S_pwmleds_RANGES_NUM 0 #define DT_N_S_pwmleds_FOREACH_RANGE(fn) #define DT_N_S_pwmleds_IRQ_NUM 0 #define DT_N_S_pwmleds_IRQ_LEVEL 0 #define DT_N_S_pwmleds_COMPAT_MATCHES_pwm_leds 1 #define DT_N_S_pwmleds_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pwmleds_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pwmleds_P_compatible {"pwm-leds"} #define DT_N_S_pwmleds_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_pwmleds_P_compatible_IDX_0 "pwm-leds" #define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UNQUOTED pwm-leds #define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_TOKEN pwm_leds #define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UPPER_TOKEN PWM_LEDS #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds, compatible, 0) #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds, compatible, 0) #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__) #define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__) #define DT_N_S_pwmleds_P_compatible_LEN 1 #define DT_N_S_pwmleds_P_compatible_EXISTS 1 /* * Devicetree node: /pwmleds/backlight * * Node identifier: DT_N_S_pwmleds_S_backlight * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pwmleds_S_backlight_PATH "/pwmleds/backlight" /* Node's name with unit-address: */ #define DT_N_S_pwmleds_S_backlight_FULL_NAME "backlight" #define DT_N_S_pwmleds_S_backlight_FULL_NAME_UNQUOTED backlight #define DT_N_S_pwmleds_S_backlight_FULL_NAME_TOKEN backlight #define DT_N_S_pwmleds_S_backlight_FULL_NAME_UPPER_TOKEN BACKLIGHT /* Node parent (/pwmleds) identifier: */ #define DT_N_S_pwmleds_S_backlight_PARENT DT_N_S_pwmleds /* Node's index in its parent's list of children: */ #define DT_N_S_pwmleds_S_backlight_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_pwmleds_S_backlight_NODELABEL_NUM 1 #define DT_N_S_pwmleds_S_backlight_FOREACH_NODELABEL(fn) fn(backlight) #define DT_N_S_pwmleds_S_backlight_FOREACH_NODELABEL_VARGS(fn, ...) fn(backlight, __VA_ARGS__) #define DT_N_S_pwmleds_S_backlight_FOREACH_ANCESTOR(fn) fn(DT_N_S_pwmleds) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pwmleds_S_backlight_CHILD_NUM 0 #define DT_N_S_pwmleds_S_backlight_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pwmleds_S_backlight_FOREACH_CHILD(fn) #define DT_N_S_pwmleds_S_backlight_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pwmleds_S_backlight_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pwmleds_S_backlight_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pwmleds_S_backlight_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pwmleds_S_backlight_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pwmleds_S_backlight_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pwmleds_S_backlight_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pwmleds_S_backlight_ORD 101 #define DT_N_S_pwmleds_S_backlight_ORD_STR_SORTABLE 00101 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pwmleds_S_backlight_REQUIRES_ORDS \ 97, /* /soc/peripheral@50000000/pwm@21000 */ \ 100, /* /pwmleds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pwmleds_S_backlight_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pwmleds_S_backlight_EXISTS 1 #define DT_N_NODELABEL_backlight DT_N_S_pwmleds_S_backlight /* Macros for properties that are special in the specification: */ #define DT_N_S_pwmleds_S_backlight_REG_NUM 0 #define DT_N_S_pwmleds_S_backlight_RANGES_NUM 0 #define DT_N_S_pwmleds_S_backlight_FOREACH_RANGE(fn) #define DT_N_S_pwmleds_S_backlight_IRQ_NUM 0 #define DT_N_S_pwmleds_S_backlight_IRQ_LEVEL 0 #define DT_N_S_pwmleds_S_backlight_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pwmleds_S_backlight_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pwmleds_S_backlight_P_pwms_IDX_0_EXISTS 1 #define DT_N_S_pwmleds_S_backlight_P_pwms_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_pwm_21000 #define DT_N_S_pwmleds_S_backlight_P_pwms_IDX_0_VAL_channel 0 #define DT_N_S_pwmleds_S_backlight_P_pwms_IDX_0_VAL_channel_EXISTS 1 #define DT_N_S_pwmleds_S_backlight_P_pwms_IDX_0_VAL_period 50000000 #define DT_N_S_pwmleds_S_backlight_P_pwms_IDX_0_VAL_period_EXISTS 1 #define DT_N_S_pwmleds_S_backlight_P_pwms_IDX_0_VAL_flags 0 #define DT_N_S_pwmleds_S_backlight_P_pwms_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_pwmleds_S_backlight_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds_S_backlight, pwms, 0) #define DT_N_S_pwmleds_S_backlight_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds_S_backlight, pwms, 0) #define DT_N_S_pwmleds_S_backlight_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_backlight, pwms, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_backlight_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_backlight, pwms, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_backlight_P_pwms_LEN 1 #define DT_N_S_pwmleds_S_backlight_P_pwms_EXISTS 1 /* * Devicetree node: /pwmleds/buzzer * * Node identifier: DT_N_S_pwmleds_S_buzzer * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pwmleds_S_buzzer_PATH "/pwmleds/buzzer" /* Node's name with unit-address: */ #define DT_N_S_pwmleds_S_buzzer_FULL_NAME "buzzer" #define DT_N_S_pwmleds_S_buzzer_FULL_NAME_UNQUOTED buzzer #define DT_N_S_pwmleds_S_buzzer_FULL_NAME_TOKEN buzzer #define DT_N_S_pwmleds_S_buzzer_FULL_NAME_UPPER_TOKEN BUZZER /* Node parent (/pwmleds) identifier: */ #define DT_N_S_pwmleds_S_buzzer_PARENT DT_N_S_pwmleds /* Node's index in its parent's list of children: */ #define DT_N_S_pwmleds_S_buzzer_CHILD_IDX 3 /* Helpers for dealing with node labels: */ #define DT_N_S_pwmleds_S_buzzer_NODELABEL_NUM 1 #define DT_N_S_pwmleds_S_buzzer_FOREACH_NODELABEL(fn) fn(buzzer) #define DT_N_S_pwmleds_S_buzzer_FOREACH_NODELABEL_VARGS(fn, ...) fn(buzzer, __VA_ARGS__) #define DT_N_S_pwmleds_S_buzzer_FOREACH_ANCESTOR(fn) fn(DT_N_S_pwmleds) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pwmleds_S_buzzer_CHILD_NUM 0 #define DT_N_S_pwmleds_S_buzzer_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pwmleds_S_buzzer_FOREACH_CHILD(fn) #define DT_N_S_pwmleds_S_buzzer_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pwmleds_S_buzzer_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pwmleds_S_buzzer_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pwmleds_S_buzzer_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pwmleds_S_buzzer_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pwmleds_S_buzzer_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pwmleds_S_buzzer_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pwmleds_S_buzzer_ORD 102 #define DT_N_S_pwmleds_S_buzzer_ORD_STR_SORTABLE 00102 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pwmleds_S_buzzer_REQUIRES_ORDS \ 99, /* /soc/peripheral@50000000/pwm@24000 */ \ 100, /* /pwmleds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pwmleds_S_buzzer_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pwmleds_S_buzzer_EXISTS 1 #define DT_N_NODELABEL_buzzer DT_N_S_pwmleds_S_buzzer /* Macros for properties that are special in the specification: */ #define DT_N_S_pwmleds_S_buzzer_REG_NUM 0 #define DT_N_S_pwmleds_S_buzzer_RANGES_NUM 0 #define DT_N_S_pwmleds_S_buzzer_FOREACH_RANGE(fn) #define DT_N_S_pwmleds_S_buzzer_IRQ_NUM 0 #define DT_N_S_pwmleds_S_buzzer_IRQ_LEVEL 0 #define DT_N_S_pwmleds_S_buzzer_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pwmleds_S_buzzer_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pwmleds_S_buzzer_P_pwms_IDX_0_EXISTS 1 #define DT_N_S_pwmleds_S_buzzer_P_pwms_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_pwm_24000 #define DT_N_S_pwmleds_S_buzzer_P_pwms_IDX_0_VAL_channel 0 #define DT_N_S_pwmleds_S_buzzer_P_pwms_IDX_0_VAL_channel_EXISTS 1 #define DT_N_S_pwmleds_S_buzzer_P_pwms_IDX_0_VAL_period 50000000 #define DT_N_S_pwmleds_S_buzzer_P_pwms_IDX_0_VAL_period_EXISTS 1 #define DT_N_S_pwmleds_S_buzzer_P_pwms_IDX_0_VAL_flags 0 #define DT_N_S_pwmleds_S_buzzer_P_pwms_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_pwmleds_S_buzzer_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds_S_buzzer, pwms, 0) #define DT_N_S_pwmleds_S_buzzer_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds_S_buzzer, pwms, 0) #define DT_N_S_pwmleds_S_buzzer_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_buzzer, pwms, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_buzzer_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_buzzer, pwms, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_buzzer_P_pwms_LEN 1 #define DT_N_S_pwmleds_S_buzzer_P_pwms_EXISTS 1 #define DT_N_S_pwmleds_S_buzzer_P_label "buzzer" #define DT_N_S_pwmleds_S_buzzer_P_label_STRING_UNQUOTED buzzer #define DT_N_S_pwmleds_S_buzzer_P_label_STRING_TOKEN buzzer #define DT_N_S_pwmleds_S_buzzer_P_label_STRING_UPPER_TOKEN BUZZER #define DT_N_S_pwmleds_S_buzzer_P_label_IDX_0 "buzzer" #define DT_N_S_pwmleds_S_buzzer_P_label_IDX_0_EXISTS 1 #define DT_N_S_pwmleds_S_buzzer_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds_S_buzzer, label, 0) #define DT_N_S_pwmleds_S_buzzer_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds_S_buzzer, label, 0) #define DT_N_S_pwmleds_S_buzzer_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_buzzer, label, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_buzzer_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_buzzer, label, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_buzzer_P_label_LEN 1 #define DT_N_S_pwmleds_S_buzzer_P_label_EXISTS 1 /* * Devicetree node: /pwmleds/motor * * Node identifier: DT_N_S_pwmleds_S_motor * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pwmleds_S_motor_PATH "/pwmleds/motor" /* Node's name with unit-address: */ #define DT_N_S_pwmleds_S_motor_FULL_NAME "motor" #define DT_N_S_pwmleds_S_motor_FULL_NAME_UNQUOTED motor #define DT_N_S_pwmleds_S_motor_FULL_NAME_TOKEN motor #define DT_N_S_pwmleds_S_motor_FULL_NAME_UPPER_TOKEN MOTOR /* Node parent (/pwmleds) identifier: */ #define DT_N_S_pwmleds_S_motor_PARENT DT_N_S_pwmleds /* Node's index in its parent's list of children: */ #define DT_N_S_pwmleds_S_motor_CHILD_IDX 2 /* Helpers for dealing with node labels: */ #define DT_N_S_pwmleds_S_motor_NODELABEL_NUM 1 #define DT_N_S_pwmleds_S_motor_FOREACH_NODELABEL(fn) fn(motor) #define DT_N_S_pwmleds_S_motor_FOREACH_NODELABEL_VARGS(fn, ...) fn(motor, __VA_ARGS__) #define DT_N_S_pwmleds_S_motor_FOREACH_ANCESTOR(fn) fn(DT_N_S_pwmleds) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pwmleds_S_motor_CHILD_NUM 0 #define DT_N_S_pwmleds_S_motor_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pwmleds_S_motor_FOREACH_CHILD(fn) #define DT_N_S_pwmleds_S_motor_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pwmleds_S_motor_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pwmleds_S_motor_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pwmleds_S_motor_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pwmleds_S_motor_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pwmleds_S_motor_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pwmleds_S_motor_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pwmleds_S_motor_ORD 103 #define DT_N_S_pwmleds_S_motor_ORD_STR_SORTABLE 00103 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pwmleds_S_motor_REQUIRES_ORDS \ 98, /* /soc/peripheral@50000000/pwm@23000 */ \ 100, /* /pwmleds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pwmleds_S_motor_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pwmleds_S_motor_EXISTS 1 #define DT_N_NODELABEL_motor DT_N_S_pwmleds_S_motor /* Macros for properties that are special in the specification: */ #define DT_N_S_pwmleds_S_motor_REG_NUM 0 #define DT_N_S_pwmleds_S_motor_RANGES_NUM 0 #define DT_N_S_pwmleds_S_motor_FOREACH_RANGE(fn) #define DT_N_S_pwmleds_S_motor_IRQ_NUM 0 #define DT_N_S_pwmleds_S_motor_IRQ_LEVEL 0 #define DT_N_S_pwmleds_S_motor_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pwmleds_S_motor_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pwmleds_S_motor_P_pwms_IDX_0_EXISTS 1 #define DT_N_S_pwmleds_S_motor_P_pwms_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_pwm_23000 #define DT_N_S_pwmleds_S_motor_P_pwms_IDX_0_VAL_channel 0 #define DT_N_S_pwmleds_S_motor_P_pwms_IDX_0_VAL_channel_EXISTS 1 #define DT_N_S_pwmleds_S_motor_P_pwms_IDX_0_VAL_period 50000000 #define DT_N_S_pwmleds_S_motor_P_pwms_IDX_0_VAL_period_EXISTS 1 #define DT_N_S_pwmleds_S_motor_P_pwms_IDX_0_VAL_flags 0 #define DT_N_S_pwmleds_S_motor_P_pwms_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_pwmleds_S_motor_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds_S_motor, pwms, 0) #define DT_N_S_pwmleds_S_motor_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds_S_motor, pwms, 0) #define DT_N_S_pwmleds_S_motor_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_motor, pwms, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_motor_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_motor, pwms, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_motor_P_pwms_LEN 1 #define DT_N_S_pwmleds_S_motor_P_pwms_EXISTS 1 #define DT_N_S_pwmleds_S_motor_P_label "motor" #define DT_N_S_pwmleds_S_motor_P_label_STRING_UNQUOTED motor #define DT_N_S_pwmleds_S_motor_P_label_STRING_TOKEN motor #define DT_N_S_pwmleds_S_motor_P_label_STRING_UPPER_TOKEN MOTOR #define DT_N_S_pwmleds_S_motor_P_label_IDX_0 "motor" #define DT_N_S_pwmleds_S_motor_P_label_IDX_0_EXISTS 1 #define DT_N_S_pwmleds_S_motor_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds_S_motor, label, 0) #define DT_N_S_pwmleds_S_motor_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds_S_motor, label, 0) #define DT_N_S_pwmleds_S_motor_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_motor, label, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_motor_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_motor, label, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_motor_P_label_LEN 1 #define DT_N_S_pwmleds_S_motor_P_label_EXISTS 1 /* * Devicetree node: /pwmleds/pwm_led_0 * * Node identifier: DT_N_S_pwmleds_S_pwm_led_0 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_pwmleds_S_pwm_led_0_PATH "/pwmleds/pwm_led_0" /* Node's name with unit-address: */ #define DT_N_S_pwmleds_S_pwm_led_0_FULL_NAME "pwm_led_0" #define DT_N_S_pwmleds_S_pwm_led_0_FULL_NAME_UNQUOTED pwm_led_0 #define DT_N_S_pwmleds_S_pwm_led_0_FULL_NAME_TOKEN pwm_led_0 #define DT_N_S_pwmleds_S_pwm_led_0_FULL_NAME_UPPER_TOKEN PWM_LED_0 /* Node parent (/pwmleds) identifier: */ #define DT_N_S_pwmleds_S_pwm_led_0_PARENT DT_N_S_pwmleds /* Node's index in its parent's list of children: */ #define DT_N_S_pwmleds_S_pwm_led_0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_pwmleds_S_pwm_led_0_NODELABEL_NUM 1 #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_NODELABEL(fn) fn(pwm_led0) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm_led0, __VA_ARGS__) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_pwmleds) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_pwmleds_S_pwm_led_0_CHILD_NUM 0 #define DT_N_S_pwmleds_S_pwm_led_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD(fn) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_pwmleds_S_pwm_led_0_ORD 104 #define DT_N_S_pwmleds_S_pwm_led_0_ORD_STR_SORTABLE 00104 /* Ordinals for what this node depends on directly: */ #define DT_N_S_pwmleds_S_pwm_led_0_REQUIRES_ORDS \ 97, /* /soc/peripheral@50000000/pwm@21000 */ \ 100, /* /pwmleds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_pwmleds_S_pwm_led_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_pwmleds_S_pwm_led_0_EXISTS 1 #define DT_N_NODELABEL_pwm_led0 DT_N_S_pwmleds_S_pwm_led_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_pwmleds_S_pwm_led_0_REG_NUM 0 #define DT_N_S_pwmleds_S_pwm_led_0_RANGES_NUM 0 #define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_RANGE(fn) #define DT_N_S_pwmleds_S_pwm_led_0_IRQ_NUM 0 #define DT_N_S_pwmleds_S_pwm_led_0_IRQ_LEVEL 0 #define DT_N_S_pwmleds_S_pwm_led_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_pwmleds_S_pwm_led_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_EXISTS 1 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_pwm_21000 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_channel 0 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_channel_EXISTS 1 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_period 20000000 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_period_EXISTS 1 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_flags 1 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0) #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0) #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0, __VA_ARGS__) #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_LEN 1 #define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_EXISTS 1 /* * Devicetree node: /reserved-memory/image@20000000 * * Node identifier: DT_N_S_reserved_memory_S_image_20000000 */ /* Node's full path: */ #define DT_N_S_reserved_memory_S_image_20000000_PATH "/reserved-memory/image@20000000" /* Node's name with unit-address: */ #define DT_N_S_reserved_memory_S_image_20000000_FULL_NAME "image@20000000" #define DT_N_S_reserved_memory_S_image_20000000_FULL_NAME_UNQUOTED image@20000000 #define DT_N_S_reserved_memory_S_image_20000000_FULL_NAME_TOKEN image_20000000 #define DT_N_S_reserved_memory_S_image_20000000_FULL_NAME_UPPER_TOKEN IMAGE_20000000 /* Node parent (/reserved-memory) identifier: */ #define DT_N_S_reserved_memory_S_image_20000000_PARENT DT_N_S_reserved_memory /* Node's index in its parent's list of children: */ #define DT_N_S_reserved_memory_S_image_20000000_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_reserved_memory_S_image_20000000_NODELABEL_NUM 1 #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_NODELABEL(fn) fn(sram0_image) #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0_image, __VA_ARGS__) #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_reserved_memory) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_reserved_memory_S_image_20000000_CHILD_NUM 0 #define DT_N_S_reserved_memory_S_image_20000000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD(fn) #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_reserved_memory_S_image_20000000_ORD 105 #define DT_N_S_reserved_memory_S_image_20000000_ORD_STR_SORTABLE 00105 /* Ordinals for what this node depends on directly: */ #define DT_N_S_reserved_memory_S_image_20000000_REQUIRES_ORDS \ 28, /* /reserved-memory */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_reserved_memory_S_image_20000000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_reserved_memory_S_image_20000000_EXISTS 1 #define DT_N_NODELABEL_sram0_image DT_N_S_reserved_memory_S_image_20000000 /* Macros for properties that are special in the specification: */ #define DT_N_S_reserved_memory_S_image_20000000_REG_NUM 1 #define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */ #define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_VAL_SIZE 458752 /* 0x70000 */ #define DT_N_S_reserved_memory_S_image_20000000_RANGES_NUM 0 #define DT_N_S_reserved_memory_S_image_20000000_FOREACH_RANGE(fn) #define DT_N_S_reserved_memory_S_image_20000000_IRQ_NUM 0 #define DT_N_S_reserved_memory_S_image_20000000_IRQ_LEVEL 0 #define DT_N_S_reserved_memory_S_image_20000000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_reserved_memory_S_image_20000000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_reserved_memory_S_image_20000000_P_reg {536870912 /* 0x20000000 */, 458752 /* 0x70000 */} #define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_0 536870912 #define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_1 458752 #define DT_N_S_reserved_memory_S_image_20000000_P_reg_EXISTS 1 /* * Devicetree node: /reserved-memory/image_ns@20040000 * * Node identifier: DT_N_S_reserved_memory_S_image_ns_20040000 */ /* Node's full path: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_PATH "/reserved-memory/image_ns@20040000" /* Node's name with unit-address: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_FULL_NAME "image_ns@20040000" #define DT_N_S_reserved_memory_S_image_ns_20040000_FULL_NAME_UNQUOTED image_ns@20040000 #define DT_N_S_reserved_memory_S_image_ns_20040000_FULL_NAME_TOKEN image_ns_20040000 #define DT_N_S_reserved_memory_S_image_ns_20040000_FULL_NAME_UPPER_TOKEN IMAGE_NS_20040000 /* Node parent (/reserved-memory) identifier: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_PARENT DT_N_S_reserved_memory /* Node's index in its parent's list of children: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_CHILD_IDX 2 /* Helpers for dealing with node labels: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_NODELABEL_NUM 1 #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_NODELABEL(fn) fn(sram0_ns) #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0_ns, __VA_ARGS__) #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_ANCESTOR(fn) fn(DT_N_S_reserved_memory) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_reserved_memory_S_image_ns_20040000_CHILD_NUM 0 #define DT_N_S_reserved_memory_S_image_ns_20040000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD(fn) #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_ORD 106 #define DT_N_S_reserved_memory_S_image_ns_20040000_ORD_STR_SORTABLE 00106 /* Ordinals for what this node depends on directly: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_REQUIRES_ORDS \ 28, /* /reserved-memory */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_EXISTS 1 #define DT_N_NODELABEL_sram0_ns DT_N_S_reserved_memory_S_image_ns_20040000 /* Macros for properties that are special in the specification: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_REG_NUM 1 #define DT_N_S_reserved_memory_S_image_ns_20040000_REG_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_ns_20040000_REG_IDX_0_VAL_ADDRESS 537133056 /* 0x20040000 */ #define DT_N_S_reserved_memory_S_image_ns_20040000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */ #define DT_N_S_reserved_memory_S_image_ns_20040000_RANGES_NUM 0 #define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_RANGE(fn) #define DT_N_S_reserved_memory_S_image_ns_20040000_IRQ_NUM 0 #define DT_N_S_reserved_memory_S_image_ns_20040000_IRQ_LEVEL 0 #define DT_N_S_reserved_memory_S_image_ns_20040000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg {537133056 /* 0x20040000 */, 262144 /* 0x40000 */} #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_0 537133056 #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_1 262144 #define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_EXISTS 1 /* * Devicetree node: /reserved-memory/image_ns_app@20040000 * * Node identifier: DT_N_S_reserved_memory_S_image_ns_app_20040000 */ /* Node's full path: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_PATH "/reserved-memory/image_ns_app@20040000" /* Node's name with unit-address: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FULL_NAME "image_ns_app@20040000" #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FULL_NAME_UNQUOTED image_ns_app@20040000 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FULL_NAME_TOKEN image_ns_app_20040000 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FULL_NAME_UPPER_TOKEN IMAGE_NS_APP_20040000 /* Node parent (/reserved-memory) identifier: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_PARENT DT_N_S_reserved_memory /* Node's index in its parent's list of children: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_CHILD_IDX 3 /* Helpers for dealing with node labels: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_NODELABEL_NUM 1 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_NODELABEL(fn) fn(sram0_ns_app) #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0_ns_app, __VA_ARGS__) #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_ANCESTOR(fn) fn(DT_N_S_reserved_memory) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_CHILD_NUM 0 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_CHILD(fn) #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_ORD 107 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_ORD_STR_SORTABLE 00107 /* Ordinals for what this node depends on directly: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_REQUIRES_ORDS \ 28, /* /reserved-memory */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_EXISTS 1 #define DT_N_NODELABEL_sram0_ns_app DT_N_S_reserved_memory_S_image_ns_app_20040000 /* Macros for properties that are special in the specification: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_REG_NUM 1 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_REG_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_REG_IDX_0_VAL_ADDRESS 537133056 /* 0x20040000 */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_RANGES_NUM 0 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_FOREACH_RANGE(fn) #define DT_N_S_reserved_memory_S_image_ns_app_20040000_IRQ_NUM 0 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_IRQ_LEVEL 0 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_reserved_memory_S_image_ns_app_20040000_P_reg {537133056 /* 0x20040000 */, 196608 /* 0x30000 */} #define DT_N_S_reserved_memory_S_image_ns_app_20040000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_P_reg_IDX_0 537133056 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_P_reg_IDX_1 196608 #define DT_N_S_reserved_memory_S_image_ns_app_20040000_P_reg_EXISTS 1 /* * Devicetree node: /reserved-memory/image_s@20000000 * * Node identifier: DT_N_S_reserved_memory_S_image_s_20000000 */ /* Node's full path: */ #define DT_N_S_reserved_memory_S_image_s_20000000_PATH "/reserved-memory/image_s@20000000" /* Node's name with unit-address: */ #define DT_N_S_reserved_memory_S_image_s_20000000_FULL_NAME "image_s@20000000" #define DT_N_S_reserved_memory_S_image_s_20000000_FULL_NAME_UNQUOTED image_s@20000000 #define DT_N_S_reserved_memory_S_image_s_20000000_FULL_NAME_TOKEN image_s_20000000 #define DT_N_S_reserved_memory_S_image_s_20000000_FULL_NAME_UPPER_TOKEN IMAGE_S_20000000 /* Node parent (/reserved-memory) identifier: */ #define DT_N_S_reserved_memory_S_image_s_20000000_PARENT DT_N_S_reserved_memory /* Node's index in its parent's list of children: */ #define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_reserved_memory_S_image_s_20000000_NODELABEL_NUM 1 #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_NODELABEL(fn) fn(sram0_s) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0_s, __VA_ARGS__) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_reserved_memory) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_NUM 0 #define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD(fn) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_reserved_memory_S_image_s_20000000_ORD 108 #define DT_N_S_reserved_memory_S_image_s_20000000_ORD_STR_SORTABLE 00108 /* Ordinals for what this node depends on directly: */ #define DT_N_S_reserved_memory_S_image_s_20000000_REQUIRES_ORDS \ 28, /* /reserved-memory */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_reserved_memory_S_image_s_20000000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_reserved_memory_S_image_s_20000000_EXISTS 1 #define DT_N_NODELABEL_sram0_s DT_N_S_reserved_memory_S_image_s_20000000 /* Macros for properties that are special in the specification: */ #define DT_N_S_reserved_memory_S_image_s_20000000_REG_NUM 1 #define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */ #define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */ #define DT_N_S_reserved_memory_S_image_s_20000000_RANGES_NUM 0 #define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_RANGE(fn) #define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_NUM 0 #define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_LEVEL 0 #define DT_N_S_reserved_memory_S_image_s_20000000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_reserved_memory_S_image_s_20000000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg {536870912 /* 0x20000000 */, 262144 /* 0x40000 */} #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0 536870912 #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1 262144 #define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_EXISTS 1 /* * Devicetree node: /soc/crypto@50844000 * * Node identifier: DT_N_S_soc_S_crypto_50844000 * * Binding (compatible = arm,cryptocell-312): * $ZEPHYR_BASE/dts/bindings/crypto/arm,cryptocell-312.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_crypto_50844000_PATH "/soc/crypto@50844000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_crypto_50844000_FULL_NAME "crypto@50844000" #define DT_N_S_soc_S_crypto_50844000_FULL_NAME_UNQUOTED crypto@50844000 #define DT_N_S_soc_S_crypto_50844000_FULL_NAME_TOKEN crypto_50844000 #define DT_N_S_soc_S_crypto_50844000_FULL_NAME_UPPER_TOKEN CRYPTO_50844000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_crypto_50844000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_crypto_50844000_CHILD_IDX 9 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_crypto_50844000_NODELABEL_NUM 1 #define DT_N_S_soc_S_crypto_50844000_FOREACH_NODELABEL(fn) fn(cryptocell) #define DT_N_S_soc_S_crypto_50844000_FOREACH_NODELABEL_VARGS(fn, ...) fn(cryptocell, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50844000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_crypto_50844000_CHILD_NUM 0 #define DT_N_S_soc_S_crypto_50844000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_crypto_50844000_ORD 109 #define DT_N_S_soc_S_crypto_50844000_ORD_STR_SORTABLE 00109 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_crypto_50844000_REQUIRES_ORDS \ 8, /* /soc */ \ 9, /* /soc/interrupt-controller@e000e100 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_crypto_50844000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_crypto_50844000_EXISTS 1 #define DT_N_INST_0_nordic_cryptocell DT_N_S_soc_S_crypto_50844000 #define DT_N_INST_0_arm_cryptocell_312 DT_N_S_soc_S_crypto_50844000 #define DT_N_NODELABEL_cryptocell DT_N_S_soc_S_crypto_50844000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_crypto_50844000_REG_NUM 2 #define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_ADDRESS 1350844416 /* 0x50844000 */ #define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_crypto_50844000_REG_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_REG_IDX_1_VAL_ADDRESS 1350848512 /* 0x50845000 */ #define DT_N_S_soc_S_crypto_50844000_REG_IDX_1_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_crypto_50844000_REG_NAME_wrapper_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_REG_NAME_wrapper_VAL_ADDRESS DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_ADDRESS #define DT_N_S_soc_S_crypto_50844000_REG_NAME_wrapper_VAL_SIZE DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_SIZE #define DT_N_S_soc_S_crypto_50844000_REG_NAME_core_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_REG_NAME_core_VAL_ADDRESS DT_N_S_soc_S_crypto_50844000_REG_IDX_1_VAL_ADDRESS #define DT_N_S_soc_S_crypto_50844000_REG_NAME_core_VAL_SIZE DT_N_S_soc_S_crypto_50844000_REG_IDX_1_VAL_SIZE #define DT_N_S_soc_S_crypto_50844000_RANGES_NUM 0 #define DT_N_S_soc_S_crypto_50844000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_crypto_50844000_IRQ_NUM 1 #define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_VAL_irq 68 #define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_crypto_50844000_IRQ_LEVEL 1 #define DT_N_S_soc_S_crypto_50844000_COMPAT_MATCHES_nordic_cryptocell 1 #define DT_N_S_soc_S_crypto_50844000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_crypto_50844000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_COMPAT_MODEL_IDX_0 "cryptocell" #define DT_N_S_soc_S_crypto_50844000_COMPAT_MATCHES_arm_cryptocell_312 1 #define DT_N_S_soc_S_crypto_50844000_COMPAT_VENDOR_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_COMPAT_VENDOR_IDX_1 "ARM Ltd." #define DT_N_S_soc_S_crypto_50844000_COMPAT_MODEL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_COMPAT_MODEL_IDX_1 "cryptocell-312" #define DT_N_S_soc_S_crypto_50844000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_crypto_50844000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_crypto_50844000_P_reg {1350844416 /* 0x50844000 */, 4096 /* 0x1000 */, 1350848512 /* 0x50845000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_0 1350844416 #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_2_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_2 1350848512 #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_3_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_3 4096 #define DT_N_S_soc_S_crypto_50844000_P_reg_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_interrupts {68 /* 0x44 */, 1 /* 0x1 */} #define DT_N_S_soc_S_crypto_50844000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_interrupts_IDX_0 68 #define DT_N_S_soc_S_crypto_50844000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_crypto_50844000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_status "okay" #define DT_N_S_soc_S_crypto_50844000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_crypto_50844000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_crypto_50844000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_crypto_50844000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_crypto_50844000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_crypto_50844000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000, status, 0) #define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000, status, 0) #define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50844000_P_status_LEN 1 #define DT_N_S_soc_S_crypto_50844000_P_status_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_compatible {"nordic,cryptocell", "arm,cryptocell-312"} #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0 "nordic,cryptocell" #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_STRING_UNQUOTED nordic,cryptocell #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_STRING_TOKEN nordic_cryptocell #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_CRYPTOCELL #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_1 "arm,cryptocell-312" #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_1_STRING_UNQUOTED arm,cryptocell-312 #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_1_STRING_TOKEN arm_cryptocell_312 #define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_1_STRING_UPPER_TOKEN ARM_CRYPTOCELL_312 #define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0) \ fn(DT_N_S_soc_S_crypto_50844000, compatible, 1) #define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_crypto_50844000, compatible, 1) #define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_crypto_50844000, compatible, 1, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_crypto_50844000, compatible, 1, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50844000_P_compatible_LEN 2 #define DT_N_S_soc_S_crypto_50844000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_reg_names {"wrapper", "core"} #define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_0 "wrapper" #define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_0_STRING_UNQUOTED wrapper #define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_0_STRING_TOKEN wrapper #define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_0_STRING_UPPER_TOKEN WRAPPER #define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_1 "core" #define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_1_STRING_UNQUOTED core #define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_1_STRING_TOKEN core #define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_1_STRING_UPPER_TOKEN CORE #define DT_N_S_soc_S_crypto_50844000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000, reg_names, 0) \ fn(DT_N_S_soc_S_crypto_50844000, reg_names, 1) #define DT_N_S_soc_S_crypto_50844000_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000, reg_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_crypto_50844000, reg_names, 1) #define DT_N_S_soc_S_crypto_50844000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, reg_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_crypto_50844000, reg_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50844000_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_crypto_50844000, reg_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_crypto_50844000_P_reg_names_LEN 2 #define DT_N_S_soc_S_crypto_50844000_P_reg_names_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_crypto_50844000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_wakeup_source 0 #define DT_N_S_soc_S_crypto_50844000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_crypto_50844000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_crypto_50844000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/ficr@ff0000 * * Node identifier: DT_N_S_soc_S_ficr_ff0000 * * Binding (compatible = nordic,nrf-ficr): * $ZEPHYR_BASE/dts/bindings/misc/nordic,nrf-ficr.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_ficr_ff0000_PATH "/soc/ficr@ff0000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_ficr_ff0000_FULL_NAME "ficr@ff0000" #define DT_N_S_soc_S_ficr_ff0000_FULL_NAME_UNQUOTED ficr@ff0000 #define DT_N_S_soc_S_ficr_ff0000_FULL_NAME_TOKEN ficr_ff0000 #define DT_N_S_soc_S_ficr_ff0000_FULL_NAME_UPPER_TOKEN FICR_FF0000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_ficr_ff0000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_ficr_ff0000_CHILD_IDX 2 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_ficr_ff0000_NODELABEL_NUM 1 #define DT_N_S_soc_S_ficr_ff0000_FOREACH_NODELABEL(fn) fn(ficr) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(ficr, __VA_ARGS__) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_ficr_ff0000_CHILD_NUM 0 #define DT_N_S_soc_S_ficr_ff0000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_ficr_ff0000_ORD 110 #define DT_N_S_soc_S_ficr_ff0000_ORD_STR_SORTABLE 00110 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_ficr_ff0000_REQUIRES_ORDS \ 8, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_ficr_ff0000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_ficr_ff0000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_ficr DT_N_S_soc_S_ficr_ff0000 #define DT_N_NODELABEL_ficr DT_N_S_soc_S_ficr_ff0000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_ficr_ff0000_REG_NUM 1 #define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_ADDRESS 16711680 /* 0xff0000 */ #define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_ficr_ff0000_RANGES_NUM 0 #define DT_N_S_soc_S_ficr_ff0000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_ficr_ff0000_IRQ_NUM 0 #define DT_N_S_soc_S_ficr_ff0000_IRQ_LEVEL 0 #define DT_N_S_soc_S_ficr_ff0000_COMPAT_MATCHES_nordic_nrf_ficr 1 #define DT_N_S_soc_S_ficr_ff0000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_ficr_ff0000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_COMPAT_MODEL_IDX_0 "nrf-ficr" #define DT_N_S_soc_S_ficr_ff0000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_ficr_ff0000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_ficr_ff0000_P_reg {16711680 /* 0xff0000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_0 16711680 #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_ficr_ff0000_P_reg_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_status "okay" #define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_ficr_ff0000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_ficr_ff0000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_ficr_ff0000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, status, 0) #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, status, 0) #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_ficr_ff0000_P_status_LEN 1 #define DT_N_S_soc_S_ficr_ff0000_P_status_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_compatible {"nordic,nrf-ficr"} #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0 "nordic,nrf-ficr" #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ficr #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ficr #define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_FICR #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0) #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0) #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_ficr_ff0000_P_compatible_LEN 1 #define DT_N_S_soc_S_ficr_ff0000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_ficr_ff0000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_wakeup_source 0 #define DT_N_S_soc_S_ficr_ff0000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_ficr_ff0000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_ficr_ff0000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/gpiote@4002f000 * * Node identifier: DT_N_S_soc_S_gpiote_4002f000 * * Binding (compatible = nordic,nrf-gpiote): * $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpiote.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_gpiote_4002f000_PATH "/soc/gpiote@4002f000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_gpiote_4002f000_FULL_NAME "gpiote@4002f000" #define DT_N_S_soc_S_gpiote_4002f000_FULL_NAME_UNQUOTED gpiote@4002f000 #define DT_N_S_soc_S_gpiote_4002f000_FULL_NAME_TOKEN gpiote_4002f000 #define DT_N_S_soc_S_gpiote_4002f000_FULL_NAME_UPPER_TOKEN GPIOTE_4002F000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_gpiote_4002f000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_gpiote_4002f000_CHILD_IDX 8 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_gpiote_4002f000_NODELABEL_NUM 1 #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_NODELABEL(fn) fn(gpiote1) #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiote1, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_gpiote_4002f000_CHILD_NUM 0 #define DT_N_S_soc_S_gpiote_4002f000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_gpiote_4002f000_ORD 111 #define DT_N_S_soc_S_gpiote_4002f000_ORD_STR_SORTABLE 00111 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_gpiote_4002f000_REQUIRES_ORDS \ 8, /* /soc */ \ 9, /* /soc/interrupt-controller@e000e100 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_gpiote_4002f000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_gpiote_4002f000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_4002f000 #define DT_N_NODELABEL_gpiote1 DT_N_S_soc_S_gpiote_4002f000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_gpiote_4002f000_REG_NUM 1 #define DT_N_S_soc_S_gpiote_4002f000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_REG_IDX_0_VAL_ADDRESS 1073934336 /* 0x4002f000 */ #define DT_N_S_soc_S_gpiote_4002f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_gpiote_4002f000_RANGES_NUM 0 #define DT_N_S_soc_S_gpiote_4002f000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_gpiote_4002f000_IRQ_NUM 1 #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_irq 47 #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_priority 5 #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_gpiote_4002f000_IRQ_LEVEL 1 #define DT_N_S_soc_S_gpiote_4002f000_COMPAT_MATCHES_nordic_nrf_gpiote 1 #define DT_N_S_soc_S_gpiote_4002f000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_gpiote_4002f000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_COMPAT_MODEL_IDX_0 "nrf-gpiote" #define DT_N_S_soc_S_gpiote_4002f000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_gpiote_4002f000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_gpiote_4002f000_P_reg {1073934336 /* 0x4002f000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_0 1073934336 #define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_gpiote_4002f000_P_reg_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts {47 /* 0x2f */, 5 /* 0x5 */} #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_0 47 #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_1 5 #define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_instance 1 #define DT_N_S_soc_S_gpiote_4002f000_P_instance_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_status "disabled" #define DT_N_S_soc_S_gpiote_4002f000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_gpiote_4002f000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_gpiote_4002f000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_gpiote_4002f000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_gpiote_4002f000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_gpiote_4002f000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0) #define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0) #define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_4002f000_P_status_LEN 1 #define DT_N_S_soc_S_gpiote_4002f000_P_status_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_compatible {"nordic,nrf-gpiote"} #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0 "nordic,nrf-gpiote" #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpiote #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0) #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0) #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_LEN 1 #define DT_N_S_soc_S_gpiote_4002f000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_gpiote_4002f000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_wakeup_source 0 #define DT_N_S_soc_S_gpiote_4002f000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_gpiote_4002f000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_gpiote_4002f000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/memory@20000000 * * Node identifier: DT_N_S_soc_S_memory_20000000 * * Binding (compatible = mmio-sram): * $ZEPHYR_BASE/dts/bindings/sram/mmio-sram.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_memory_20000000_PATH "/soc/memory@20000000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_memory_20000000_FULL_NAME "memory@20000000" #define DT_N_S_soc_S_memory_20000000_FULL_NAME_UNQUOTED memory@20000000 #define DT_N_S_soc_S_memory_20000000_FULL_NAME_TOKEN memory_20000000 #define DT_N_S_soc_S_memory_20000000_FULL_NAME_UPPER_TOKEN MEMORY_20000000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_memory_20000000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_memory_20000000_CHILD_IDX 4 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_memory_20000000_NODELABEL_NUM 1 #define DT_N_S_soc_S_memory_20000000_FOREACH_NODELABEL(fn) fn(sram0) #define DT_N_S_soc_S_memory_20000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0, __VA_ARGS__) #define DT_N_S_soc_S_memory_20000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_memory_20000000_CHILD_NUM 0 #define DT_N_S_soc_S_memory_20000000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_memory_20000000_ORD 112 #define DT_N_S_soc_S_memory_20000000_ORD_STR_SORTABLE 00112 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS \ 8, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_memory_20000000_EXISTS 1 #define DT_N_INST_0_mmio_sram DT_N_S_soc_S_memory_20000000 #define DT_N_NODELABEL_sram0 DT_N_S_soc_S_memory_20000000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_memory_20000000_REG_NUM 1 #define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */ #define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE 524288 /* 0x80000 */ #define DT_N_S_soc_S_memory_20000000_RANGES_NUM 0 #define DT_N_S_soc_S_memory_20000000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_memory_20000000_IRQ_NUM 0 #define DT_N_S_soc_S_memory_20000000_IRQ_LEVEL 0 #define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1 #define DT_N_S_soc_S_memory_20000000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_memory_20000000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 524288 /* 0x80000 */} #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0 536870912 #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1 524288 #define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_compatible {"mmio-sram"} #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0 "mmio-sram" #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UNQUOTED mmio-sram #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_TOKEN mmio_sram #define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UPPER_TOKEN MMIO_SRAM #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_20000000, compatible, 0) #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_20000000, compatible, 0) #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_memory_20000000_P_compatible_LEN 1 #define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_memory_20000000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_wakeup_source 0 #define DT_N_S_soc_S_memory_20000000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/spu@50003000 * * Node identifier: DT_N_S_soc_S_spu_50003000 * * Binding (compatible = nordic,nrf-spu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-spu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_spu_50003000_PATH "/soc/spu@50003000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_spu_50003000_FULL_NAME "spu@50003000" #define DT_N_S_soc_S_spu_50003000_FULL_NAME_UNQUOTED spu@50003000 #define DT_N_S_soc_S_spu_50003000_FULL_NAME_TOKEN spu_50003000 #define DT_N_S_soc_S_spu_50003000_FULL_NAME_UPPER_TOKEN SPU_50003000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_spu_50003000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_spu_50003000_CHILD_IDX 6 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_spu_50003000_NODELABEL_NUM 1 #define DT_N_S_soc_S_spu_50003000_FOREACH_NODELABEL(fn) fn(spu) #define DT_N_S_soc_S_spu_50003000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spu, __VA_ARGS__) #define DT_N_S_soc_S_spu_50003000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_spu_50003000_CHILD_NUM 0 #define DT_N_S_soc_S_spu_50003000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_spu_50003000_ORD 113 #define DT_N_S_soc_S_spu_50003000_ORD_STR_SORTABLE 00113 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spu_50003000_REQUIRES_ORDS \ 8, /* /soc */ \ 9, /* /soc/interrupt-controller@e000e100 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_spu_50003000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_spu_50003000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_spu DT_N_S_soc_S_spu_50003000 #define DT_N_NODELABEL_spu DT_N_S_soc_S_spu_50003000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_spu_50003000_REG_NUM 1 #define DT_N_S_soc_S_spu_50003000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_ADDRESS 1342189568 /* 0x50003000 */ #define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_spu_50003000_RANGES_NUM 0 #define DT_N_S_soc_S_spu_50003000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_spu_50003000_IRQ_NUM 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq 3 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_spu_50003000_IRQ_LEVEL 1 #define DT_N_S_soc_S_spu_50003000_COMPAT_MATCHES_nordic_nrf_spu 1 #define DT_N_S_soc_S_spu_50003000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_spu_50003000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_COMPAT_MODEL_IDX_0 "nrf-spu" #define DT_N_S_soc_S_spu_50003000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_spu_50003000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_spu_50003000_P_reg {1342189568 /* 0x50003000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_0 1342189568 #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_spu_50003000_P_reg_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_interrupts {3 /* 0x3 */, 1 /* 0x1 */} #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_0 3 #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_spu_50003000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_status "okay" #define DT_N_S_soc_S_spu_50003000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_spu_50003000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_spu_50003000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_spu_50003000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_spu_50003000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_spu_50003000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, status, 0) #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, status, 0) #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_spu_50003000_P_status_LEN 1 #define DT_N_S_soc_S_spu_50003000_P_status_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_compatible {"nordic,nrf-spu"} #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0 "nordic,nrf-spu" #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spu #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spu #define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPU #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, compatible, 0) #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, compatible, 0) #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_spu_50003000_P_compatible_LEN 1 #define DT_N_S_soc_S_spu_50003000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_spu_50003000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_wakeup_source 0 #define DT_N_S_soc_S_spu_50003000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_spu_50003000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_spu_50003000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timer@e000e010 * * Node identifier: DT_N_S_soc_S_timer_e000e010 * * Binding (compatible = arm,armv8m-systick): * $ZEPHYR_BASE/dts/bindings/timer/arm,armv8m-systick.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_timer_e000e010_PATH "/soc/timer@e000e010" /* Node's name with unit-address: */ #define DT_N_S_soc_S_timer_e000e010_FULL_NAME "timer@e000e010" #define DT_N_S_soc_S_timer_e000e010_FULL_NAME_UNQUOTED timer@e000e010 #define DT_N_S_soc_S_timer_e000e010_FULL_NAME_TOKEN timer_e000e010 #define DT_N_S_soc_S_timer_e000e010_FULL_NAME_UPPER_TOKEN TIMER_E000E010 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_timer_e000e010_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_timer_e000e010_NODELABEL_NUM 1 #define DT_N_S_soc_S_timer_e000e010_FOREACH_NODELABEL(fn) fn(systick) #define DT_N_S_soc_S_timer_e000e010_FOREACH_NODELABEL_VARGS(fn, ...) fn(systick, __VA_ARGS__) #define DT_N_S_soc_S_timer_e000e010_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_timer_e000e010_CHILD_NUM 0 #define DT_N_S_soc_S_timer_e000e010_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_timer_e000e010_ORD 114 #define DT_N_S_soc_S_timer_e000e010_ORD_STR_SORTABLE 00114 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \ 8, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timer_e000e010_EXISTS 1 #define DT_N_INST_0_arm_armv8m_systick DT_N_S_soc_S_timer_e000e010 #define DT_N_NODELABEL_systick DT_N_S_soc_S_timer_e000e010 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timer_e000e010_REG_NUM 1 #define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */ #define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */ #define DT_N_S_soc_S_timer_e000e010_RANGES_NUM 0 #define DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0 #define DT_N_S_soc_S_timer_e000e010_IRQ_LEVEL 0 #define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick 1 #define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0 "ARM Ltd." #define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0 "armv8m-systick" #define DT_N_S_soc_S_timer_e000e010_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */} #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744 #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16 #define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_status "disabled" #define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timer_e000e010_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timer_e000e010_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timer_e000e010_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_timer_e000e010_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, status, 0) #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, status, 0) #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_timer_e000e010_P_status_LEN 1 #define DT_N_S_soc_S_timer_e000e010_P_status_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv8m-systick"} #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv8m-systick" #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-systick #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_systick #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_SYSTICK #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0) #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0) #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1 #define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_wakeup_source 0 #define DT_N_S_soc_S_timer_e000e010_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/uicr@ff8000 * * Node identifier: DT_N_S_soc_S_uicr_ff8000 * * Binding (compatible = nordic,nrf-uicr): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-uicr.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_uicr_ff8000_PATH "/soc/uicr@ff8000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_uicr_ff8000_FULL_NAME "uicr@ff8000" #define DT_N_S_soc_S_uicr_ff8000_FULL_NAME_UNQUOTED uicr@ff8000 #define DT_N_S_soc_S_uicr_ff8000_FULL_NAME_TOKEN uicr_ff8000 #define DT_N_S_soc_S_uicr_ff8000_FULL_NAME_UPPER_TOKEN UICR_FF8000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_uicr_ff8000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_uicr_ff8000_CHILD_IDX 3 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_uicr_ff8000_NODELABEL_NUM 1 #define DT_N_S_soc_S_uicr_ff8000_FOREACH_NODELABEL(fn) fn(uicr) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uicr, __VA_ARGS__) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_uicr_ff8000_CHILD_NUM 0 #define DT_N_S_soc_S_uicr_ff8000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_uicr_ff8000_ORD 115 #define DT_N_S_soc_S_uicr_ff8000_ORD_STR_SORTABLE 00115 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_uicr_ff8000_REQUIRES_ORDS \ 8, /* /soc */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_uicr_ff8000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_uicr_ff8000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_uicr DT_N_S_soc_S_uicr_ff8000 #define DT_N_NODELABEL_uicr DT_N_S_soc_S_uicr_ff8000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_uicr_ff8000_REG_NUM 1 #define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_ADDRESS 16744448 /* 0xff8000 */ #define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_uicr_ff8000_RANGES_NUM 0 #define DT_N_S_soc_S_uicr_ff8000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_uicr_ff8000_IRQ_NUM 0 #define DT_N_S_soc_S_uicr_ff8000_IRQ_LEVEL 0 #define DT_N_S_soc_S_uicr_ff8000_COMPAT_MATCHES_nordic_nrf_uicr 1 #define DT_N_S_soc_S_uicr_ff8000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_uicr_ff8000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_COMPAT_MODEL_IDX_0 "nrf-uicr" #define DT_N_S_soc_S_uicr_ff8000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_uicr_ff8000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_uicr_ff8000_P_reg {16744448 /* 0xff8000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_0 16744448 #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_uicr_ff8000_P_reg_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_nfct_pins_as_gpios 1 #define DT_N_S_soc_S_uicr_ff8000_P_nfct_pins_as_gpios_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_gpio_as_nreset 0 #define DT_N_S_soc_S_uicr_ff8000_P_gpio_as_nreset_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_status "okay" #define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_uicr_ff8000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_uicr_ff8000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_uicr_ff8000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, status, 0) #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, status, 0) #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_uicr_ff8000_P_status_LEN 1 #define DT_N_S_soc_S_uicr_ff8000_P_status_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_compatible {"nordic,nrf-uicr"} #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0 "nordic,nrf-uicr" #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uicr #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uicr #define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UICR #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0) #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0) #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_uicr_ff8000_P_compatible_LEN 1 #define DT_N_S_soc_S_uicr_ff8000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_uicr_ff8000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_wakeup_source 0 #define DT_N_S_soc_S_uicr_ff8000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_uicr_ff8000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_uicr_ff8000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/clock@5000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_clock_5000 * * Binding (compatible = nordic,nrf-clock): * $ZEPHYR_BASE/dts/bindings/clock/nordic,nrf-clock.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PATH "/soc/peripheral@50000000/clock@5000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FULL_NAME "clock@5000" #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FULL_NAME_UNQUOTED clock@5000 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FULL_NAME_TOKEN clock_5000 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FULL_NAME_UPPER_TOKEN CLOCK_5000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_CHILD_IDX 3 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_NODELABEL(fn) fn(clock) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_NODELABEL_VARGS(fn, ...) fn(clock, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_ORD 116 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_ORD_STR_SORTABLE 00116 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_clock DT_N_S_soc_S_peripheral_50000000_S_clock_5000 #define DT_N_NODELABEL_clock DT_N_S_soc_S_peripheral_50000000_S_clock_5000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq 5 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MATCHES_nordic_nrf_clock 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MODEL_IDX_0 "nrf-clock" #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_0 20480 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_0 5 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible {"nordic,nrf-clock"} #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0 "nordic,nrf-clock" #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-clock #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_clock #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CLOCK #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/comparator@1a000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000 * * Binding (compatible = nordic,nrf-comp): * $ZEPHYR_BASE/dts/bindings/comparator/nordic,nrf-comp.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_PATH "/soc/peripheral@50000000/comparator@1a000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FULL_NAME "comparator@1a000" #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FULL_NAME_UNQUOTED comparator@1a000 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FULL_NAME_TOKEN comparator_1a000 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FULL_NAME_UPPER_TOKEN COMPARATOR_1A000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_CHILD_IDX 29 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_NODELABEL(fn) fn(comp) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(comp, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_ORD 117 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_ORD_STR_SORTABLE 00117 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_comp DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000 #define DT_N_NODELABEL_comp DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_IDX_0_VAL_ADDRESS 1342283776 /* 0x5001a000 */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_irq 26 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_MATCHES_nordic_nrf_comp 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_MODEL_IDX_0 "nrf-comp" #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_enable_hyst 0 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_enable_hyst_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible {"nordic,nrf-comp"} #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0 "nordic,nrf-comp" #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-comp #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_comp #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_COMP #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg {106496 /* 0x1a000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_0 106496 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts {26 /* 0x1a */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_0 26 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/ctrlap@6000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000 * * Binding (compatible = nordic,nrf-ctrlapperi): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-ctrlapperi.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_PATH "/soc/peripheral@50000000/ctrlap@6000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FULL_NAME "ctrlap@6000" #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FULL_NAME_UNQUOTED ctrlap@6000 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FULL_NAME_TOKEN ctrlap_6000 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FULL_NAME_UPPER_TOKEN CTRLAP_6000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_CHILD_IDX 6 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_NODELABEL(fn) fn(ctrlap) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_NODELABEL_VARGS(fn, ...) fn(ctrlap, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_ORD 118 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_ORD_STR_SORTABLE 00118 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_ctrlapperi DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000 #define DT_N_NODELABEL_ctrlap DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_IDX_0_VAL_ADDRESS 1342201856 /* 0x50006000 */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_MATCHES_nordic_nrf_ctrlapperi 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_MODEL_IDX_0 "nrf-ctrlapperi" #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg {24576 /* 0x6000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_0 24576 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible {"nordic,nrf-ctrlapperi"} #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0 "nordic,nrf-ctrlapperi" #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ctrlapperi #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ctrlapperi #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CTRLAPPERI #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/dcnf@0 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_dcnf_0 * * Binding (compatible = nordic,nrf-dcnf): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-dcnf.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_PATH "/soc/peripheral@50000000/dcnf@0" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FULL_NAME "dcnf@0" #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FULL_NAME_UNQUOTED dcnf@0 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FULL_NAME_TOKEN dcnf_0 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FULL_NAME_UPPER_TOKEN DCNF_0 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_NODELABEL(fn) fn(dcnf) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcnf, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_ORD 119 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_ORD_STR_SORTABLE 00119 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_EXISTS 1 #define DT_N_INST_0_nordic_nrf_dcnf DT_N_S_soc_S_peripheral_50000000_S_dcnf_0 #define DT_N_NODELABEL_dcnf DT_N_S_soc_S_peripheral_50000000_S_dcnf_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_IDX_0_VAL_ADDRESS 1342177280 /* 0x50000000 */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_MATCHES_nordic_nrf_dcnf 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_MODEL_IDX_0 "nrf-dcnf" #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg {0 /* 0x0 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible {"nordic,nrf-dcnf"} #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0 "nordic,nrf-dcnf" #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-dcnf #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dcnf #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DCNF #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/dppic@17000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_dppic_17000 * * Binding (compatible = nordic,nrf-dppic): * $ZEPHYR_BASE/dts/bindings/misc/nordic,nrf-dppic.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PATH "/soc/peripheral@50000000/dppic@17000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FULL_NAME "dppic@17000" #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FULL_NAME_UNQUOTED dppic@17000 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FULL_NAME_TOKEN dppic_17000 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FULL_NAME_UPPER_TOKEN DPPIC_17000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_CHILD_IDX 26 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_NODELABEL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_NODELABEL(fn) fn(dppic0) fn(dppic) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dppic0, __VA_ARGS__) fn(dppic, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_ORD 120 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_ORD_STR_SORTABLE 00120 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_dppic DT_N_S_soc_S_peripheral_50000000_S_dppic_17000 #define DT_N_NODELABEL_dppic0 DT_N_S_soc_S_peripheral_50000000_S_dppic_17000 #define DT_N_NODELABEL_dppic DT_N_S_soc_S_peripheral_50000000_S_dppic_17000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_ADDRESS 1342271488 /* 0x50017000 */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MATCHES_nordic_nrf_dppic 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MODEL_IDX_0 "nrf-dppic" #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg {94208 /* 0x17000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_0 94208 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible {"nordic,nrf-dppic"} #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0 "nordic,nrf-dppic" #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-dppic #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dppic #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DPPIC #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@1b000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1b000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PATH "/soc/peripheral@50000000/egu@1b000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FULL_NAME "egu@1b000" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FULL_NAME_UNQUOTED egu@1b000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FULL_NAME_TOKEN egu_1b000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FULL_NAME_UPPER_TOKEN EGU_1B000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_CHILD_IDX 30 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_NODELABEL(fn) fn(egu0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_ORD 121 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_ORD_STR_SORTABLE 00121 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1b000 #define DT_N_NODELABEL_egu0 DT_N_S_soc_S_peripheral_50000000_S_egu_1b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_ADDRESS 1342287872 /* 0x5001b000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq 27 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg {110592 /* 0x1b000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_0 110592 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts {27 /* 0x1b */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_0 27 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@1c000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1c000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PATH "/soc/peripheral@50000000/egu@1c000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FULL_NAME "egu@1c000" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FULL_NAME_UNQUOTED egu@1c000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FULL_NAME_TOKEN egu_1c000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FULL_NAME_UPPER_TOKEN EGU_1C000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_CHILD_IDX 31 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_NODELABEL(fn) fn(egu1) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_ORD 122 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_ORD_STR_SORTABLE 00122 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1c000 #define DT_N_NODELABEL_egu1 DT_N_S_soc_S_peripheral_50000000_S_egu_1c000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_ADDRESS 1342291968 /* 0x5001c000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq 28 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg {114688 /* 0x1c000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_0 114688 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts {28 /* 0x1c */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_0 28 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@1d000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1d000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PATH "/soc/peripheral@50000000/egu@1d000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FULL_NAME "egu@1d000" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FULL_NAME_UNQUOTED egu@1d000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FULL_NAME_TOKEN egu_1d000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FULL_NAME_UPPER_TOKEN EGU_1D000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_CHILD_IDX 32 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_NODELABEL(fn) fn(egu2) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_ORD 123 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_ORD_STR_SORTABLE 00123 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1d000 #define DT_N_NODELABEL_egu2 DT_N_S_soc_S_peripheral_50000000_S_egu_1d000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_ADDRESS 1342296064 /* 0x5001d000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq 29 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg {118784 /* 0x1d000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_0 118784 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts {29 /* 0x1d */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_0 29 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@1e000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1e000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PATH "/soc/peripheral@50000000/egu@1e000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FULL_NAME "egu@1e000" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FULL_NAME_UNQUOTED egu@1e000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FULL_NAME_TOKEN egu_1e000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FULL_NAME_UPPER_TOKEN EGU_1E000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_CHILD_IDX 33 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_NODELABEL(fn) fn(egu3) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu3, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_ORD 124 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_ORD_STR_SORTABLE 00124 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_EXISTS 1 #define DT_N_INST_3_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1e000 #define DT_N_NODELABEL_egu3 DT_N_S_soc_S_peripheral_50000000_S_egu_1e000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_ADDRESS 1342300160 /* 0x5001e000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq 30 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg {122880 /* 0x1e000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_0 122880 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts {30 /* 0x1e */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_0 30 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@1f000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1f000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PATH "/soc/peripheral@50000000/egu@1f000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FULL_NAME "egu@1f000" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FULL_NAME_UNQUOTED egu@1f000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FULL_NAME_TOKEN egu_1f000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FULL_NAME_UPPER_TOKEN EGU_1F000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_CHILD_IDX 34 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_NODELABEL(fn) fn(egu4) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu4, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_ORD 125 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_ORD_STR_SORTABLE 00125 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_EXISTS 1 #define DT_N_INST_4_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1f000 #define DT_N_NODELABEL_egu4 DT_N_S_soc_S_peripheral_50000000_S_egu_1f000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_ADDRESS 1342304256 /* 0x5001f000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq 31 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg {126976 /* 0x1f000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_0 126976 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts {31 /* 0x1f */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_0 31 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/egu@20000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_20000 * * Binding (compatible = nordic,nrf-egu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PATH "/soc/peripheral@50000000/egu@20000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FULL_NAME "egu@20000" #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FULL_NAME_UNQUOTED egu@20000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FULL_NAME_TOKEN egu_20000 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FULL_NAME_UPPER_TOKEN EGU_20000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_CHILD_IDX 35 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_NODELABEL(fn) fn(egu5) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu5, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_ORD 126 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_ORD_STR_SORTABLE 00126 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_EXISTS 1 #define DT_N_INST_5_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_20000 #define DT_N_NODELABEL_egu5 DT_N_S_soc_S_peripheral_50000000_S_egu_20000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_ADDRESS 1342308352 /* 0x50020000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq 32 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MATCHES_nordic_nrf_egu 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MODEL_IDX_0 "nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg {131072 /* 0x20000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_0 131072 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts {32 /* 0x20 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_0 32 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible {"nordic,nrf-egu"} #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0 "nordic,nrf-egu" #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2c@8000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_8000 * * Binding (compatible = nordic,nrf-twim): * $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PATH "/soc/peripheral@50000000/i2c@8000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FULL_NAME "i2c@8000" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FULL_NAME_UNQUOTED i2c@8000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FULL_NAME_TOKEN i2c_8000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FULL_NAME_UPPER_TOKEN I2C_8000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_CHILD_IDX 7 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_NODELABEL(fn) fn(i2c0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_ORD 127 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_ORD_STR_SORTABLE 00127 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_8000 #define DT_N_NODELABEL_i2c0 DT_N_S_soc_S_peripheral_50000000_S_i2c_8000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq 8 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MATCHES_nordic_nrf_twim 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MODEL_IDX_0 "nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_concat_buf_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_concat_buf_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_flash_buf_max_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_flash_buf_max_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_0 32768 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_0 8 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_easydma_maxcnt_bits 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_sq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_sq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_cq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible {"nordic,nrf-twim"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0 "nordic,nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_pm_device_runtime_auto 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2c@b000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_b000 * * Binding (compatible = nordic,nrf-twim): * $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PATH "/soc/peripheral@50000000/i2c@b000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FULL_NAME "i2c@b000" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FULL_NAME_UNQUOTED i2c@b000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FULL_NAME_TOKEN i2c_b000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FULL_NAME_UPPER_TOKEN I2C_B000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_CHILD_IDX 14 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_NODELABEL(fn) fn(i2c2) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_ORD 128 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_ORD_STR_SORTABLE 00128 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_b000 #define DT_N_NODELABEL_i2c2 DT_N_S_soc_S_peripheral_50000000_S_i2c_b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq 11 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MATCHES_nordic_nrf_twim 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MODEL_IDX_0 "nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_concat_buf_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_concat_buf_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_flash_buf_max_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_flash_buf_max_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_0 45056 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_0 11 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_easydma_maxcnt_bits 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_sq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_sq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_cq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible {"nordic,nrf-twim"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0 "nordic,nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_pm_device_runtime_auto 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2c@c000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_c000 * * Binding (compatible = nordic,nrf-twim): * $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_PATH "/soc/peripheral@50000000/i2c@c000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FULL_NAME "i2c@c000" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FULL_NAME_UNQUOTED i2c@c000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FULL_NAME_TOKEN i2c_c000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FULL_NAME_UPPER_TOKEN I2C_C000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_CHILD_IDX 17 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_NODELABEL(fn) fn(i2c3) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c3, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_ORD 129 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_ORD_STR_SORTABLE 00129 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_EXISTS 1 #define DT_N_INST_3_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_c000 #define DT_N_NODELABEL_i2c3 DT_N_S_soc_S_peripheral_50000000_S_i2c_c000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_irq 12 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_MATCHES_nordic_nrf_twim 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_MODEL_IDX_0 "nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_concat_buf_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_concat_buf_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_flash_buf_max_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_flash_buf_max_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_0 49152 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_0 12 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_easydma_maxcnt_bits 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_sq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_sq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_cq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible {"nordic,nrf-twim"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0 "nordic,nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_pm_device_runtime_auto 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2s@28000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2s_28000 * * Binding (compatible = nordic,nrf-i2s): * $ZEPHYR_BASE/dts/bindings/i2s/nordic,nrf-i2s.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PATH "/soc/peripheral@50000000/i2s@28000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FULL_NAME "i2s@28000" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FULL_NAME_UNQUOTED i2s@28000 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FULL_NAME_TOKEN i2s_28000 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FULL_NAME_UPPER_TOKEN I2S_28000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_CHILD_IDX 41 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_NODELABEL(fn) fn(i2s0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2s0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_ORD 130 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_ORD_STR_SORTABLE 00130 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_i2s DT_N_S_soc_S_peripheral_50000000_S_i2s_28000 #define DT_N_NODELABEL_i2s0 DT_N_S_soc_S_peripheral_50000000_S_i2s_28000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_ADDRESS 1342341120 /* 0x50028000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq 40 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MATCHES_nordic_nrf_i2s 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MODEL_IDX_0 "nrf-i2s" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg {163840 /* 0x28000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_0 163840 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts {40 /* 0x28 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_0 40 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source "PCLK32M_HFXO" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_IDX_0 "PCLK32M_HFXO" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_IDX_0_ENUM_VAL_PCLK32M_HFXO_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible {"nordic,nrf-i2s"} #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0 "nordic,nrf-i2s" #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-i2s #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_i2s #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_I2S #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/ieee802154 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_ieee802154 * * Binding (compatible = nordic,nrf-ieee802154): * $ZEPHYR_BASE/dts/bindings/ieee802154/nordic,nrf-ieee802154.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_PATH "/soc/peripheral@50000000/ieee802154" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FULL_NAME "ieee802154" #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FULL_NAME_UNQUOTED ieee802154 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FULL_NAME_TOKEN ieee802154 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FULL_NAME_UPPER_TOKEN IEEE802154 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_CHILD_IDX 55 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_NODELABEL(fn) fn(ieee802154) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_NODELABEL_VARGS(fn, ...) fn(ieee802154, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_ORD 131 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_ORD_STR_SORTABLE 00131 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_EXISTS 1 #define DT_N_INST_0_nordic_nrf_ieee802154 DT_N_S_soc_S_peripheral_50000000_S_ieee802154 #define DT_N_NODELABEL_ieee802154 DT_N_S_soc_S_peripheral_50000000_S_ieee802154 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_REG_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_MATCHES_nordic_nrf_ieee802154 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_MODEL_IDX_0 "nrf-ieee802154" #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible {"nordic,nrf-ieee802154"} #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0 "nordic,nrf-ieee802154" #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ieee802154 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ieee802154 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_IEEE802154 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/kmu@39000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_kmu_39000 * * Binding (compatible = nordic,nrf-kmu): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-kmu.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PATH "/soc/peripheral@50000000/kmu@39000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FULL_NAME "kmu@39000" #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FULL_NAME_UNQUOTED kmu@39000 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FULL_NAME_TOKEN kmu_39000 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FULL_NAME_UPPER_TOKEN KMU_39000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_CHILD_IDX 51 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_NODELABEL(fn) fn(kmu) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_NODELABEL_VARGS(fn, ...) fn(kmu, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_ORD 132 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_ORD_STR_SORTABLE 00132 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_kmu DT_N_S_soc_S_peripheral_50000000_S_kmu_39000 #define DT_N_NODELABEL_kmu DT_N_S_soc_S_peripheral_50000000_S_kmu_39000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq 57 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MATCHES_nordic_nrf_kmu 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MODEL_IDX_0 "nrf-kmu" #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_0 233472 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts {57 /* 0x39 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_0 57 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible {"nordic,nrf-kmu"} #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0 "nordic,nrf-kmu" #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-kmu #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_kmu #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_KMU #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/mutex@30000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_mutex_30000 * * Binding (compatible = nordic,nrf-mutex): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-mutex.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_PATH "/soc/peripheral@50000000/mutex@30000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FULL_NAME "mutex@30000" #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FULL_NAME_UNQUOTED mutex@30000 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FULL_NAME_TOKEN mutex_30000 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FULL_NAME_UPPER_TOKEN MUTEX_30000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_CHILD_IDX 45 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_NODELABEL(fn) fn(mutex) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_NODELABEL_VARGS(fn, ...) fn(mutex, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_ORD 133 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_ORD_STR_SORTABLE 00133 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_mutex DT_N_S_soc_S_peripheral_50000000_S_mutex_30000 #define DT_N_NODELABEL_mutex DT_N_S_soc_S_peripheral_50000000_S_mutex_30000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_IDX_0_VAL_ADDRESS 1342373888 /* 0x50030000 */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_MATCHES_nordic_nrf_mutex 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_MODEL_IDX_0 "nrf-mutex" #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg {196608 /* 0x30000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_0 196608 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible {"nordic,nrf-mutex"} #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0 "nordic,nrf-mutex" #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-mutex #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_mutex #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_MUTEX #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/nfct@2d000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000 * * Binding (compatible = nordic,nrf-nfct): * $ZEPHYR_BASE/dts/bindings/net/wireless/nordic,nrf-nfct.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_PATH "/soc/peripheral@50000000/nfct@2d000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FULL_NAME "nfct@2d000" #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FULL_NAME_UNQUOTED nfct@2d000 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FULL_NAME_TOKEN nfct_2d000 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FULL_NAME_UPPER_TOKEN NFCT_2D000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_CHILD_IDX 44 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_NODELABEL(fn) fn(nfct) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_NODELABEL_VARGS(fn, ...) fn(nfct, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_ORD 134 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_ORD_STR_SORTABLE 00134 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_nfct DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000 #define DT_N_NODELABEL_nfct DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_IDX_0_VAL_ADDRESS 1342361600 /* 0x5002d000 */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_irq 45 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_MATCHES_nordic_nrf_nfct 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_MODEL_IDX_0 "nrf-nfct" #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg {184320 /* 0x2d000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_0 184320 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts {45 /* 0x2d */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_0 45 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible {"nordic,nrf-nfct"} #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0 "nordic,nrf-nfct" #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-nfct #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_nfct #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_NFCT #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/pdm@26000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pdm_26000 * * Binding (compatible = nordic,nrf-pdm): * $ZEPHYR_BASE/dts/bindings/audio/nordic,nrf-pdm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PATH "/soc/peripheral@50000000/pdm@26000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FULL_NAME "pdm@26000" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FULL_NAME_UNQUOTED pdm@26000 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FULL_NAME_TOKEN pdm_26000 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FULL_NAME_UPPER_TOKEN PDM_26000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_CHILD_IDX 40 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_NODELABEL(fn) fn(pdm0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pdm0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_ORD 135 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_ORD_STR_SORTABLE 00135 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_pdm DT_N_S_soc_S_peripheral_50000000_S_pdm_26000 #define DT_N_NODELABEL_pdm0 DT_N_S_soc_S_peripheral_50000000_S_pdm_26000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_ADDRESS 1342332928 /* 0x50026000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq 38 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MATCHES_nordic_nrf_pdm 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MODEL_IDX_0 "nrf-pdm" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg {155648 /* 0x26000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_0 155648 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts {38 /* 0x26 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_0 38 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source "PCLK32M_HFXO" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_IDX_0 "PCLK32M_HFXO" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_IDX_0_ENUM_VAL_PCLK32M_HFXO_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_queue_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_queue_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible {"nordic,nrf-pdm"} #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0 "nordic,nrf-pdm" #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pdm #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pdm #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PDM #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/pwm@22000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_22000 * * Binding (compatible = nordic,nrf-pwm): * $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PATH "/soc/peripheral@50000000/pwm@22000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FULL_NAME "pwm@22000" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FULL_NAME_UNQUOTED pwm@22000 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FULL_NAME_TOKEN pwm_22000 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FULL_NAME_UPPER_TOKEN PWM_22000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_CHILD_IDX 37 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_NODELABEL(fn) fn(pwm1) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_ORD 136 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_ORD_STR_SORTABLE 00136 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_EXISTS 1 #define DT_N_INST_3_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_22000 #define DT_N_NODELABEL_pwm1 DT_N_S_soc_S_peripheral_50000000_S_pwm_22000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_ADDRESS 1342316544 /* 0x50022000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq 34 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MATCHES_nordic_nrf_pwm 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MODEL_IDX_0 "nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg {139264 /* 0x22000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_0 139264 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible {"nordic,nrf-pwm"} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0 "nordic,nrf-pwm" #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts {34 /* 0x22 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_0 34 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/qdec@33000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qdec_33000 * * Binding (compatible = nordic,nrf-qdec): * $ZEPHYR_BASE/dts/bindings/sensor/nordic,nrf-qdec.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_PATH "/soc/peripheral@50000000/qdec@33000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FULL_NAME "qdec@33000" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FULL_NAME_UNQUOTED qdec@33000 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FULL_NAME_TOKEN qdec_33000 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FULL_NAME_UPPER_TOKEN QDEC_33000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_CHILD_IDX 46 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_NODELABEL(fn) fn(qdec0) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_NODELABEL_VARGS(fn, ...) fn(qdec0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_ORD 137 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_ORD_STR_SORTABLE 00137 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_qdec DT_N_S_soc_S_peripheral_50000000_S_qdec_33000 #define DT_N_NODELABEL_qdec0 DT_N_S_soc_S_peripheral_50000000_S_qdec_33000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_IDX_0_VAL_ADDRESS 1342386176 /* 0x50033000 */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_irq 51 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_MATCHES_nordic_nrf_qdec 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_MODEL_IDX_0 "nrf-qdec" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg {208896 /* 0x33000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_0 208896 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts {51 /* 0x33 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_0 51 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible {"nordic,nrf-qdec"} #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0 "nordic,nrf-qdec" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qdec #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qdec #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QDEC #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/qdec@34000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qdec_34000 * * Binding (compatible = nordic,nrf-qdec): * $ZEPHYR_BASE/dts/bindings/sensor/nordic,nrf-qdec.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_PATH "/soc/peripheral@50000000/qdec@34000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FULL_NAME "qdec@34000" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FULL_NAME_UNQUOTED qdec@34000 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FULL_NAME_TOKEN qdec_34000 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FULL_NAME_UPPER_TOKEN QDEC_34000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_CHILD_IDX 47 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_NODELABEL(fn) fn(qdec1) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_NODELABEL_VARGS(fn, ...) fn(qdec1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_ORD 138 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_ORD_STR_SORTABLE 00138 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_qdec DT_N_S_soc_S_peripheral_50000000_S_qdec_34000 #define DT_N_NODELABEL_qdec1 DT_N_S_soc_S_peripheral_50000000_S_qdec_34000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_IDX_0_VAL_ADDRESS 1342390272 /* 0x50034000 */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_irq 52 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_MATCHES_nordic_nrf_qdec 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_MODEL_IDX_0 "nrf-qdec" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg {212992 /* 0x34000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_0 212992 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts {52 /* 0x34 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_0 52 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible {"nordic,nrf-qdec"} #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0 "nordic,nrf-qdec" #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qdec #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qdec #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QDEC #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/regulator@37000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_37000 * * Binding (compatible = nordic,nrf-usbreg): * $ZEPHYR_BASE/dts/bindings/power/nordic,nrf-usbreg.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_PATH "/soc/peripheral@50000000/regulator@37000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FULL_NAME "regulator@37000" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FULL_NAME_UNQUOTED regulator@37000 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FULL_NAME_TOKEN regulator_37000 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FULL_NAME_UPPER_TOKEN REGULATOR_37000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_CHILD_IDX 49 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_NODELABEL(fn) fn(usbreg) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_NODELABEL_VARGS(fn, ...) fn(usbreg, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_ORD 139 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_ORD_STR_SORTABLE 00139 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_usbreg DT_N_S_soc_S_peripheral_50000000_S_regulator_37000 #define DT_N_NODELABEL_usbreg DT_N_S_soc_S_peripheral_50000000_S_regulator_37000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_IDX_0_VAL_ADDRESS 1342402560 /* 0x50037000 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_irq 55 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_MATCHES_nordic_nrf_usbreg 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_MODEL_IDX_0 "nrf-usbreg" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg {225280 /* 0x37000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_0 225280 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts {55 /* 0x37 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_0 55 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible {"nordic,nrf-usbreg"} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0 "nordic,nrf-usbreg" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-usbreg #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_usbreg #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_USBREG #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/reset-controller@5000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000 * * Binding (compatible = nordic,nrf-reset): * $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-reset.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_PATH "/soc/peripheral@50000000/reset-controller@5000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FULL_NAME "reset-controller@5000" #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FULL_NAME_UNQUOTED reset-controller@5000 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FULL_NAME_TOKEN reset_controller_5000 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FULL_NAME_UPPER_TOKEN RESET_CONTROLLER_5000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_CHILD_IDX 5 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_NODELABEL(fn) fn(reset) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_NODELABEL_VARGS(fn, ...) fn(reset, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_ORD 140 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_ORD_STR_SORTABLE 00140 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_reset DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000 #define DT_N_NODELABEL_reset DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_MATCHES_nordic_nrf_reset 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_MODEL_IDX_0 "nrf-reset" #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_0 20480 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible {"nordic,nrf-reset"} #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0 "nordic,nrf-reset" #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-reset #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_reset #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RESET #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/rtc@14000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_14000 * * Binding (compatible = nordic,nrf-rtc): * $ZEPHYR_BASE/dts/bindings/rtc/nordic,nrf-rtc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PATH "/soc/peripheral@50000000/rtc@14000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FULL_NAME "rtc@14000" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FULL_NAME_UNQUOTED rtc@14000 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FULL_NAME_TOKEN rtc_14000 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FULL_NAME_UPPER_TOKEN RTC_14000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_CHILD_IDX 24 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_NODELABEL(fn) fn(rtc0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_NODELABEL_VARGS(fn, ...) fn(rtc0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_ORD 141 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_ORD_STR_SORTABLE 00141 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_14000 #define DT_N_NODELABEL_rtc0 DT_N_S_soc_S_peripheral_50000000_S_rtc_14000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_ADDRESS 1342259200 /* 0x50014000 */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq 20 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MATCHES_nordic_nrf_rtc 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MODEL_IDX_0 "nrf-rtc" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg {81920 /* 0x14000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_0 81920 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_cc_num 4 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_cc_num_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zli 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zli_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency 32768 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts {20 /* 0x14 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_0 20 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible {"nordic,nrf-rtc"} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0 "nordic,nrf-rtc" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rtc #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/rtc@15000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_15000 * * Binding (compatible = nordic,nrf-rtc): * $ZEPHYR_BASE/dts/bindings/rtc/nordic,nrf-rtc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PATH "/soc/peripheral@50000000/rtc@15000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FULL_NAME "rtc@15000" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FULL_NAME_UNQUOTED rtc@15000 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FULL_NAME_TOKEN rtc_15000 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FULL_NAME_UPPER_TOKEN RTC_15000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_CHILD_IDX 25 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_NODELABEL(fn) fn(rtc1) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_NODELABEL_VARGS(fn, ...) fn(rtc1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_ORD 142 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_ORD_STR_SORTABLE 00142 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_15000 #define DT_N_NODELABEL_rtc1 DT_N_S_soc_S_peripheral_50000000_S_rtc_15000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_ADDRESS 1342263296 /* 0x50015000 */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq 21 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MATCHES_nordic_nrf_rtc 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MODEL_IDX_0 "nrf-rtc" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg {86016 /* 0x15000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_0 86016 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_cc_num 4 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_cc_num_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zli 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zli_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency 32768 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts {21 /* 0x15 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_0 21 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible {"nordic,nrf-rtc"} #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0 "nordic,nrf-rtc" #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rtc #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/spi@9000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_9000 * * Binding (compatible = nordic,nrf-spim): * $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PATH "/soc/peripheral@50000000/spi@9000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FULL_NAME "spi@9000" #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FULL_NAME_UNQUOTED spi@9000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FULL_NAME_TOKEN spi_9000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FULL_NAME_UPPER_TOKEN SPI_9000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_CHILD_IDX 11 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_NODELABEL(fn) fn(spi1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_ORD 143 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_ORD_STR_SORTABLE 00143 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_9000 #define DT_N_NODELABEL_spi1 DT_N_S_soc_S_peripheral_50000000_S_spi_9000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq 9 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MATCHES_nordic_nrf_spim 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MODEL_IDX_0 "nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_anomaly_58_workaround 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_anomaly_58_workaround_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_rx_delay_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_rx_delay_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_0 36864 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_0 9 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_max_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_overrun_character 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_overrun_character_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_easydma_maxcnt_bits 16 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible {"nordic,nrf-spim"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0 "nordic,nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/spi@a000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_a000 * * Binding (compatible = nordic,nrf-spim): * $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PATH "/soc/peripheral@50000000/spi@a000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FULL_NAME "spi@a000" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FULL_NAME_UNQUOTED spi@a000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FULL_NAME_TOKEN spi_a000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FULL_NAME_UPPER_TOKEN SPI_A000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_CHILD_IDX 13 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_NODELABEL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_NODELABEL(fn) fn(spi4) fn(arduino_spi) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi4, __VA_ARGS__) fn(arduino_spi, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_ORD 144 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_ORD_STR_SORTABLE 00144 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 16, /* /soc/peripheral@50000000/gpio@842800 */ \ 75, /* /pin-controller/spi4_default */ \ 77, /* /pin-controller/spi4_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_EXISTS 1 #define DT_N_INST_3_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_a000 #define DT_N_NODELABEL_spi4 DT_N_S_soc_S_peripheral_50000000_S_spi_a000 #define DT_N_NODELABEL_arduino_spi DT_N_S_soc_S_peripheral_50000000_S_spi_a000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_ADDRESS 1342218240 /* 0x5000a000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq 10 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MATCHES_nordic_nrf_spim 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MODEL_IDX_0 "nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi4_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi4_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_anomaly_58_workaround 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_anomaly_58_workaround_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_supported 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_IDX_0_ENUM_VAL_2_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_0 40960 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_0 10 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi4_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi4_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_max_frequency 32000000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_overrun_character 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_overrun_character_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_easydma_maxcnt_bits 16 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842800 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin 12 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible {"nordic,nrf-spim"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0 "nordic,nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi4_sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi4_sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/spi@b000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_b000 * * Binding (compatible = nordic,nrf-spim): * $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PATH "/soc/peripheral@50000000/spi@b000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FULL_NAME "spi@b000" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FULL_NAME_UNQUOTED spi@b000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FULL_NAME_TOKEN spi_b000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FULL_NAME_UPPER_TOKEN SPI_B000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_CHILD_IDX 15 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_NODELABEL(fn) fn(spi2) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_ORD 145 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_ORD_STR_SORTABLE 00145 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_EXISTS 1 #define DT_N_INST_4_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_b000 #define DT_N_NODELABEL_spi2 DT_N_S_soc_S_peripheral_50000000_S_spi_b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq 11 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MATCHES_nordic_nrf_spim 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MODEL_IDX_0 "nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_anomaly_58_workaround 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_anomaly_58_workaround_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_rx_delay_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_rx_delay_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_0 45056 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_0 11 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_max_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_overrun_character 255 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_overrun_character_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_easydma_maxcnt_bits 16 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible {"nordic,nrf-spim"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0 "nordic,nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/timer@f000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_f000 * * Binding (compatible = nordic,nrf-timer): * $ZEPHYR_BASE/dts/bindings/counter/nordic,nrf-timer.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PATH "/soc/peripheral@50000000/timer@f000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FULL_NAME "timer@f000" #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FULL_NAME_UNQUOTED timer@f000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FULL_NAME_TOKEN timer_f000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FULL_NAME_UPPER_TOKEN TIMER_F000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_CHILD_IDX 21 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_NODELABEL(fn) fn(timer0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_ORD 146 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_ORD_STR_SORTABLE 00146 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_f000 #define DT_N_NODELABEL_timer0 DT_N_S_soc_S_peripheral_50000000_S_timer_f000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_ADDRESS 1342238720 /* 0x5000f000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq 15 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MATCHES_nordic_nrf_timer 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MODEL_IDX_0 "nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg {61440 /* 0xf000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_0 61440 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_cc_num 6 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_cc_num_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_bit_width 32 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_bit_width_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts {15 /* 0xf */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_0 15 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_frequency 16000000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zli 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zli_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible {"nordic,nrf-timer"} #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0 "nordic,nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/timer@11000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_11000 * * Binding (compatible = nordic,nrf-timer): * $ZEPHYR_BASE/dts/bindings/counter/nordic,nrf-timer.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PATH "/soc/peripheral@50000000/timer@11000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FULL_NAME "timer@11000" #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FULL_NAME_UNQUOTED timer@11000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FULL_NAME_TOKEN timer_11000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FULL_NAME_UPPER_TOKEN TIMER_11000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_CHILD_IDX 23 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_NODELABEL(fn) fn(timer2) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_ORD 147 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_ORD_STR_SORTABLE 00147 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_11000 #define DT_N_NODELABEL_timer2 DT_N_S_soc_S_peripheral_50000000_S_timer_11000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_ADDRESS 1342246912 /* 0x50011000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq 17 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MATCHES_nordic_nrf_timer 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MODEL_IDX_0 "nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg {69632 /* 0x11000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_0 69632 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_cc_num 6 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_cc_num_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_bit_width 32 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_bit_width_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts {17 /* 0x11 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_0 17 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_frequency 16000000 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zli 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zli_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible {"nordic,nrf-timer"} #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0 "nordic,nrf-timer" #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/uart@8000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_8000 * * Binding (compatible = nordic,nrf-uarte): * $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PATH "/soc/peripheral@50000000/uart@8000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FULL_NAME "uart@8000" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FULL_NAME_UNQUOTED uart@8000 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FULL_NAME_TOKEN uart_8000 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FULL_NAME_UPPER_TOKEN UART_8000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_CHILD_IDX 9 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_NODELABEL(fn) fn(uart0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_ORD 148 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_ORD_STR_SORTABLE 00148 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 79, /* /pin-controller/uart0_default */ \ 82, /* /pin-controller/uart0_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_8000 #define DT_N_NODELABEL_uart0 DT_N_S_soc_S_peripheral_50000000_S_uart_8000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq 8 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MATCHES_nordic_nrf_uarte 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MODEL_IDX_0 "nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart0_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart0_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_endtx_stoptx_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_endtx_stoptx_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_frame_timeout_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_frame_timeout_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_0 32768 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_0 8 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart0_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart0_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_disable_rx 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_disable_rx_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed 115200 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_IDX_0_ENUM_IDX 12 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_IDX_0_ENUM_VAL_115200_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible {"nordic,nrf-uarte"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0 "nordic,nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart0_sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart0_sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_pinctrl_1_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/uart@9000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_9000 * * Binding (compatible = nordic,nrf-uarte): * $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PATH "/soc/peripheral@50000000/uart@9000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FULL_NAME "uart@9000" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FULL_NAME_UNQUOTED uart@9000 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FULL_NAME_TOKEN uart_9000 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FULL_NAME_UPPER_TOKEN UART_9000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_CHILD_IDX 12 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_NODELABEL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_NODELABEL(fn) fn(uart1) fn(arduino_serial) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart1, __VA_ARGS__) fn(arduino_serial, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_ORD 149 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_ORD_STR_SORTABLE 00149 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 84, /* /pin-controller/uart1_default */ \ 87, /* /pin-controller/uart1_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_EXISTS 1 #define DT_N_INST_2_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_9000 #define DT_N_NODELABEL_uart1 DT_N_S_soc_S_peripheral_50000000_S_uart_9000 #define DT_N_NODELABEL_arduino_serial DT_N_S_soc_S_peripheral_50000000_S_uart_9000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq 9 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MATCHES_nordic_nrf_uarte 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MODEL_IDX_0 "nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart1_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart1_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_endtx_stoptx_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_endtx_stoptx_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_frame_timeout_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_frame_timeout_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_0 36864 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_0 9 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart1_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart1_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_disable_rx 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_disable_rx_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed 115200 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed_IDX_0_ENUM_IDX 12 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed_IDX_0_ENUM_VAL_115200_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_current_speed_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible {"nordic,nrf-uarte"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0 "nordic,nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart1_sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart1_sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_pinctrl_1_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/uart@b000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_b000 * * Binding (compatible = nordic,nrf-uarte): * $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PATH "/soc/peripheral@50000000/uart@b000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FULL_NAME "uart@b000" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FULL_NAME_UNQUOTED uart@b000 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FULL_NAME_TOKEN uart_b000 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FULL_NAME_UPPER_TOKEN UART_B000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_CHILD_IDX 16 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_NODELABEL(fn) fn(uart2) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_ORD 150 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_ORD_STR_SORTABLE 00150 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 89, /* /pin-controller/uart2_default */ \ 92, /* /pin-controller/uart2_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_b000 #define DT_N_NODELABEL_uart2 DT_N_S_soc_S_peripheral_50000000_S_uart_b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq 11 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MATCHES_nordic_nrf_uarte 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MODEL_IDX_0 "nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart2_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart2_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_endtx_stoptx_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_endtx_stoptx_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_frame_timeout_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_frame_timeout_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_0 45056 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_0 11 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart2_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart2_default #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_disable_rx 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_disable_rx_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_current_speed 115200 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_current_speed_IDX_0_ENUM_IDX 12 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_current_speed_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_current_speed_IDX_0_ENUM_VAL_115200_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_current_speed_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible {"nordic,nrf-uarte"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0 "nordic,nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart2_sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart2_sleep #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_pinctrl_1_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/uart@c000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_c000 * * Binding (compatible = nordic,nrf-uarte): * $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_PATH "/soc/peripheral@50000000/uart@c000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FULL_NAME "uart@c000" #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FULL_NAME_UNQUOTED uart@c000 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FULL_NAME_TOKEN uart_c000 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FULL_NAME_UPPER_TOKEN UART_C000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_CHILD_IDX 19 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_NODELABEL(fn) fn(uart3) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart3, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_ORD 151 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_ORD_STR_SORTABLE 00151 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_EXISTS 1 #define DT_N_INST_3_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_c000 #define DT_N_NODELABEL_uart3 DT_N_S_soc_S_peripheral_50000000_S_uart_c000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_irq 12 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_MATCHES_nordic_nrf_uarte 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_MODEL_IDX_0 "nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_endtx_stoptx_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_endtx_stoptx_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_frame_timeout_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_frame_timeout_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_0 49152 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_0 12 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_disable_rx 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_disable_rx_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_hw_flow_control 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible {"nordic,nrf-uarte"} #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0 "nordic,nrf-uarte" #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/usbd@36000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_usbd_36000 * * Binding (compatible = nordic,nrf-usbd): * $ZEPHYR_BASE/dts/bindings/usb/nordic,nrf-usbd.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_PATH "/soc/peripheral@50000000/usbd@36000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FULL_NAME "usbd@36000" #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FULL_NAME_UNQUOTED usbd@36000 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FULL_NAME_TOKEN usbd_36000 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FULL_NAME_UPPER_TOKEN USBD_36000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_CHILD_IDX 48 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_NODELABEL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_NODELABEL(fn) fn(usbd) fn(zephyr_udc0) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_NODELABEL_VARGS(fn, ...) fn(usbd, __VA_ARGS__) fn(zephyr_udc0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_ORD 152 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_ORD_STR_SORTABLE 00152 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_usbd DT_N_S_soc_S_peripheral_50000000_S_usbd_36000 #define DT_N_NODELABEL_usbd DT_N_S_soc_S_peripheral_50000000_S_usbd_36000 #define DT_N_NODELABEL_zephyr_udc0 DT_N_S_soc_S_peripheral_50000000_S_usbd_36000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_IDX_0_VAL_ADDRESS 1342398464 /* 0x50036000 */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_irq 54 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_MATCHES_nordic_nrf_usbd 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_MODEL_IDX_0 "nrf-usbd" #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg {221184 /* 0x36000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_0 221184 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts {54 /* 0x36 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_0 54 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoin_endpoints 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoin_endpoints_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoout_endpoints 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoout_endpoints_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_bidir_endpoints 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_bidir_endpoints_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_in_endpoints 7 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_in_endpoints_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_out_endpoints 7 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_out_endpoints_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible {"nordic,nrf-usbd"} #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0 "nordic,nrf-usbd" #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-usbd #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_usbd #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_USBD #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/vmc@81000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_vmc_81000 * * Binding (compatible = nordic,nrf-vmc): * $ZEPHYR_BASE/dts/bindings/power/nordic,nrf-vmc.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_PATH "/soc/peripheral@50000000/vmc@81000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FULL_NAME "vmc@81000" #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FULL_NAME_UNQUOTED vmc@81000 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FULL_NAME_TOKEN vmc_81000 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FULL_NAME_UPPER_TOKEN VMC_81000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_CHILD_IDX 52 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_NODELABEL(fn) fn(vmc) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_NODELABEL_VARGS(fn, ...) fn(vmc, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_ORD 153 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_ORD_STR_SORTABLE 00153 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_vmc DT_N_S_soc_S_peripheral_50000000_S_vmc_81000 #define DT_N_NODELABEL_vmc DT_N_S_soc_S_peripheral_50000000_S_vmc_81000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_VAL_ADDRESS 1342705664 /* 0x50081000 */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_MATCHES_nordic_nrf_vmc 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_MODEL_IDX_0 "nrf-vmc" #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg {528384 /* 0x81000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_0 528384 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible {"nordic,nrf-vmc"} #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0 "nordic,nrf-vmc" #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-vmc #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_vmc #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_VMC #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/watchdog@18000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000 * * Binding (compatible = nordic,nrf-wdt): * $ZEPHYR_BASE/dts/bindings/watchdog/nordic,nrf-wdt.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PATH "/soc/peripheral@50000000/watchdog@18000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FULL_NAME "watchdog@18000" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FULL_NAME_UNQUOTED watchdog@18000 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FULL_NAME_TOKEN watchdog_18000 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FULL_NAME_UPPER_TOKEN WATCHDOG_18000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_CHILD_IDX 27 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_NODELABEL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_NODELABEL(fn) fn(wdt) fn(wdt0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_NODELABEL_VARGS(fn, ...) fn(wdt, __VA_ARGS__) fn(wdt0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_ORD 154 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_ORD_STR_SORTABLE 00154 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_EXISTS 1 #define DT_N_ALIAS_watchdog0 DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000 #define DT_N_INST_0_nordic_nrf_wdt DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000 #define DT_N_NODELABEL_wdt DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000 #define DT_N_NODELABEL_wdt0 DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_ADDRESS 1342275584 /* 0x50018000 */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq 24 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MATCHES_nordic_nrf_wdt 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MODEL_IDX_0 "nrf-wdt" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg {98304 /* 0x18000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_0 98304 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts {24 /* 0x18 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_0 24 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible {"nordic,nrf-wdt"} #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0 "nordic,nrf-wdt" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-wdt #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_wdt #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_WDT #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/watchdog@19000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000 * * Binding (compatible = nordic,nrf-wdt): * $ZEPHYR_BASE/dts/bindings/watchdog/nordic,nrf-wdt.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_PATH "/soc/peripheral@50000000/watchdog@19000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FULL_NAME "watchdog@19000" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FULL_NAME_UNQUOTED watchdog@19000 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FULL_NAME_TOKEN watchdog_19000 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FULL_NAME_UPPER_TOKEN WATCHDOG_19000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_CHILD_IDX 28 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_NODELABEL(fn) fn(wdt1) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_NODELABEL_VARGS(fn, ...) fn(wdt1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_ORD 155 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_ORD_STR_SORTABLE 00155 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_EXISTS 1 #define DT_N_INST_1_nordic_nrf_wdt DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000 #define DT_N_NODELABEL_wdt1 DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_VAL_ADDRESS 1342279680 /* 0x50019000 */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_irq 25 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_MATCHES_nordic_nrf_wdt 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_MODEL_IDX_0 "nrf-wdt" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg {102400 /* 0x19000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_0 102400 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts {25 /* 0x19 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_0 25 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible {"nordic,nrf-wdt"} #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0 "nordic,nrf-wdt" #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-wdt #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_wdt #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_WDT #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/adc@e000/channel@5 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_PATH "/soc/peripheral@50000000/adc@e000/channel@5" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FULL_NAME "channel@5" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FULL_NAME_UNQUOTED channel@5 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FULL_NAME_TOKEN channel_5 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FULL_NAME_UPPER_TOKEN CHANNEL_5 /* Node parent (/soc/peripheral@50000000/adc@e000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_PARENT DT_N_S_soc_S_peripheral_50000000_S_adc_e000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_NODELABEL_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_NODELABEL(fn) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_ORD 156 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_ORD_STR_SORTABLE 00156 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_REQUIRES_ORDS \ 13, /* /soc/peripheral@50000000/adc@e000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_EXISTS 1 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_REG_IDX_0_VAL_ADDRESS 5 /* 0x5 */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_reg {5 /* 0x5 */} #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_reg_IDX_0 5 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain "ADC_GAIN_1_2" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1_2 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1_2 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1_2 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_IDX_0 "ADC_GAIN_1_2" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_IDX_0_ENUM_IDX 6 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_2_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, zephyr_gain, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, zephyr_gain, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, zephyr_gain, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, zephyr_gain, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_gain_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference "ADC_REF_INTERNAL" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_IDX_0_ENUM_IDX 4 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, zephyr_reference, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, zephyr_reference, 0) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, zephyr_reference, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, zephyr_reference, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_reference_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_acquisition_time 16383 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_acquisition_time_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_differential 0 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_differential_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_input_positive 6 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_input_positive_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_resolution 12 #define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5_P_zephyr_resolution_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/clock-controller@4000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000 * * Binding (compatible = nordic,nrf53-oscillators): * $ZEPHYR_BASE/dts/bindings/clock/nordic,nrf53-oscillators.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_PATH "/soc/peripheral@50000000/clock-controller@4000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FULL_NAME "clock-controller@4000" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FULL_NAME_UNQUOTED clock-controller@4000 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FULL_NAME_TOKEN clock_controller_4000 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FULL_NAME_UPPER_TOKEN CLOCK_CONTROLLER_4000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_NODELABEL(fn) fn(oscillators) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_NODELABEL_VARGS(fn, ...) fn(oscillators, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_CHILD_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_ORD 157 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_ORD_STR_SORTABLE 00157 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_SUPPORTS_ORDS \ 158, /* /soc/peripheral@50000000/clock-controller@4000/hfxo */ \ 159, /* /soc/peripheral@50000000/clock-controller@4000/lfxo */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_EXISTS 1 #define DT_N_INST_0_nordic_nrf53_oscillators DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000 #define DT_N_NODELABEL_oscillators DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_REG_IDX_0_VAL_ADDRESS 1342193664 /* 0x50004000 */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_COMPAT_MATCHES_nordic_nrf53_oscillators 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_COMPAT_MODEL_IDX_0 "nrf53-oscillators" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_reg {16384 /* 0x4000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_reg_IDX_0 16384 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible {"nordic,nrf53-oscillators"} #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible_IDX_0 "nordic,nrf53-oscillators" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf53-oscillators #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf53_oscillators #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF53_OSCILLATORS #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/clock-controller@4000/hfxo * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo * * Binding (compatible = nordic,nrf53-hfxo): * $ZEPHYR_BASE/dts/bindings/clock/nordic,nrf53-hfxo.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_PATH "/soc/peripheral@50000000/clock-controller@4000/hfxo" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FULL_NAME "hfxo" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FULL_NAME_UNQUOTED hfxo #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FULL_NAME_TOKEN hfxo #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FULL_NAME_UPPER_TOKEN HFXO /* Node parent (/soc/peripheral@50000000/clock-controller@4000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_PARENT DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_NODELABEL(fn) fn(hfxo) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_NODELABEL_VARGS(fn, ...) fn(hfxo, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_ORD 158 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_ORD_STR_SORTABLE 00158 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_REQUIRES_ORDS \ 157, /* /soc/peripheral@50000000/clock-controller@4000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_EXISTS 1 #define DT_N_INST_0_nordic_nrf53_hfxo DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo #define DT_N_NODELABEL_hfxo DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_REG_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_COMPAT_MATCHES_nordic_nrf53_hfxo 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_COMPAT_MODEL_IDX_0 "nrf53-hfxo" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_clock_frequency 32000000 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible {"nordic,nrf53-hfxo"} #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible_IDX_0 "nordic,nrf53-hfxo" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf53-hfxo #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible_IDX_0_STRING_TOKEN nordic_nrf53_hfxo #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF53_HFXO #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/clock-controller@4000/lfxo * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo * * Binding (compatible = nordic,nrf53-lfxo): * $ZEPHYR_BASE/dts/bindings/clock/nordic,nrf53-lfxo.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_PATH "/soc/peripheral@50000000/clock-controller@4000/lfxo" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FULL_NAME "lfxo" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FULL_NAME_UNQUOTED lfxo #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FULL_NAME_TOKEN lfxo #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FULL_NAME_UPPER_TOKEN LFXO /* Node parent (/soc/peripheral@50000000/clock-controller@4000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_PARENT DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_NODELABEL(fn) fn(lfxo) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_NODELABEL_VARGS(fn, ...) fn(lfxo, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_ORD 159 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_ORD_STR_SORTABLE 00159 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_REQUIRES_ORDS \ 157, /* /soc/peripheral@50000000/clock-controller@4000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_EXISTS 1 #define DT_N_INST_0_nordic_nrf53_lfxo DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo #define DT_N_NODELABEL_lfxo DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_REG_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_COMPAT_MATCHES_nordic_nrf53_lfxo 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_COMPAT_MODEL_IDX_0 "nrf53-lfxo" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_clock_frequency 32768 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors "internal" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_STRING_UNQUOTED internal #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_STRING_TOKEN internal #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_STRING_UPPER_TOKEN INTERNAL #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_IDX_0 "internal" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_IDX_0_ENUM_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_IDX_0_ENUM_VAL_internal_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, load_capacitors, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, load_capacitors, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, load_capacitors, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, load_capacitors, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitors_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitance_picofarad 7 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitance_picofarad_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitance_picofarad_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitance_picofarad_IDX_0_ENUM_VAL_7_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_load_capacitance_picofarad_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible {"nordic,nrf53-lfxo"} #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible_IDX_0 "nordic,nrf53-lfxo" #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf53-lfxo #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible_IDX_0_STRING_TOKEN nordic_nrf53_lfxo #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF53_LFXO #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000 * * Binding (compatible = nordic,nrf53-flash-controller): * $ZEPHYR_BASE/dts/bindings/flash_controller/nordic,nrf53-flash-controller.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PATH "/soc/peripheral@50000000/flash-controller@39000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FULL_NAME "flash-controller@39000" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FULL_NAME_UNQUOTED flash-controller@39000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FULL_NAME_TOKEN flash_controller_39000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FULL_NAME_UPPER_TOKEN FLASH_CONTROLLER_39000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_CHILD_IDX 50 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_NODELABEL(fn) fn(flash_controller) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_NODELABEL_VARGS(fn, ...) fn(flash_controller, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_CHILD_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_ORD 160 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_ORD_STR_SORTABLE 00160 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_SUPPORTS_ORDS \ 161, /* /soc/peripheral@50000000/flash-controller@39000/flash@0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_EXISTS 1 #define DT_N_INST_0_nordic_nrf53_flash_controller DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000 #define DT_N_NODELABEL_flash_controller DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MATCHES_nordic_nrf53_flash_controller 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MODEL_IDX_0 "nrf53-flash-controller" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_partial_erase 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_partial_erase_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_0 233472 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible {"nordic,nrf53-flash-controller"} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0 "nordic,nrf53-flash-controller" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf53-flash-controller #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf53_flash_controller #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF53_FLASH_CONTROLLER #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0 * * Binding (compatible = soc-nv-flash): * $ZEPHYR_BASE/dts/bindings/mtd/soc-nv-flash.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FULL_NAME "flash@0" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FULL_NAME_UNQUOTED flash@0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FULL_NAME_TOKEN flash_0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FULL_NAME_UPPER_TOKEN FLASH_0 /* Node parent (/soc/peripheral@50000000/flash-controller@39000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_NODELABEL(fn) fn(flash0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(flash0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_CHILD_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_ORD 161 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_ORD_STR_SORTABLE 00161 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REQUIRES_ORDS \ 160, /* /soc/peripheral@50000000/flash-controller@39000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_SUPPORTS_ORDS \ 162, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_EXISTS 1 #define DT_N_INST_0_soc_nv_flash DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0 #define DT_N_NODELABEL_flash0 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_SIZE 1048576 /* 0x100000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_COMPAT_MATCHES_soc_nv_flash 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size 4096 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible {"soc-nv-flash"} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0 "soc-nv-flash" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_UNQUOTED soc-nv-flash #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_TOKEN soc_nv_flash #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SOC_NV_FLASH #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg {0 /* 0x0 */, 1048576 /* 0x100000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1 1048576 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions * * Binding (compatible = fixed-partitions): * $ZEPHYR_BASE/dts/bindings/mtd/fixed-partitions.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FULL_NAME "partitions" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FULL_NAME_UNQUOTED partitions #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FULL_NAME_TOKEN partitions #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FULL_NAME_UPPER_TOKEN PARTITIONS /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_NODELABEL_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_NODELABEL(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_NODELABEL_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_NUM 9 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_NUM_STATUS_OKAY 9 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD 162 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD_STR_SORTABLE 00162 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_REQUIRES_ORDS \ 161, /* /soc/peripheral@50000000/flash-controller@39000/flash@0 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_SUPPORTS_ORDS \ 163, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0 */ \ 164, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000 */ \ 165, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000 */ \ 166, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000 */ \ 167, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000 */ \ 168, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f0000 */ \ 169, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f4000 */ \ 170, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f6000 */ \ 171, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f8000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_EXISTS 1 #define DT_N_INST_0_fixed_partitions DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_REG_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PINCTRL_NUM 0 /* (No generic property macros) */ /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FULL_NAME "partition@0" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FULL_NAME_UNQUOTED partition@0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FULL_NAME_TOKEN partition_0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FULL_NAME_UPPER_TOKEN PARTITION_0 /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_NODELABEL(fn) fn(boot_partition) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(boot_partition, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD 163 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD_STR_SORTABLE 00163 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REQUIRES_ORDS \ 162, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_EXISTS 1 #define DT_N_NODELABEL_boot_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label "mcuboot" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UNQUOTED mcuboot #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_TOKEN mcuboot #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN MCUBOOT #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_IDX_0 "mcuboot" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 65536 /* 0x10000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1 65536 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME "partition@10000" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME_UNQUOTED partition@10000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME_TOKEN partition_10000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME_UPPER_TOKEN PARTITION_10000 /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_NODELABEL(fn) fn(slot0_partition) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot0_partition, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD 164 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD_STR_SORTABLE 00164 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REQUIRES_ORDS \ 162, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_EXISTS 1 #define DT_N_NODELABEL_slot0_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_ADDRESS 65536 /* 0x10000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARTITION_ID 1 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label "image-0" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UNQUOTED image-0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_TOKEN image_0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UPPER_TOKEN IMAGE_0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_IDX_0 "image-0" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg {65536 /* 0x10000 */, 262144 /* 0x40000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0 65536 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1 262144 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@50000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FULL_NAME "partition@50000" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FULL_NAME_UNQUOTED partition@50000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FULL_NAME_TOKEN partition_50000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FULL_NAME_UPPER_TOKEN PARTITION_50000 /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_CHILD_IDX 2 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_NODELABEL(fn) fn(slot0_ns_partition) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot0_ns_partition, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_ORD 165 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_ORD_STR_SORTABLE 00165 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REQUIRES_ORDS \ 162, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_EXISTS 1 #define DT_N_NODELABEL_slot0_ns_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_ADDRESS 327680 /* 0x50000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARTITION_ID 2 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label "image-0-nonsecure" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_UNQUOTED image-0-nonsecure #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_TOKEN image_0_nonsecure #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_UPPER_TOKEN IMAGE_0_NONSECURE #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_IDX_0 "image-0-nonsecure" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg {327680 /* 0x50000 */, 196608 /* 0x30000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0 327680 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1 196608 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FULL_NAME "partition@80000" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FULL_NAME_UNQUOTED partition@80000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FULL_NAME_TOKEN partition_80000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FULL_NAME_UPPER_TOKEN PARTITION_80000 /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_CHILD_IDX 3 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_NODELABEL(fn) fn(slot1_partition) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot1_partition, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_ORD 166 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_ORD_STR_SORTABLE 00166 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REQUIRES_ORDS \ 162, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_EXISTS 1 #define DT_N_NODELABEL_slot1_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_ADDRESS 524288 /* 0x80000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARTITION_ID 3 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label "image-1" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_UNQUOTED image-1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_TOKEN image_1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_UPPER_TOKEN IMAGE_1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_IDX_0 "image-1" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg {524288 /* 0x80000 */, 262144 /* 0x40000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0 524288 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1 262144 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@c0000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FULL_NAME "partition@c0000" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FULL_NAME_UNQUOTED partition@c0000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FULL_NAME_TOKEN partition_c0000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FULL_NAME_UPPER_TOKEN PARTITION_C0000 /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_CHILD_IDX 4 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_NODELABEL(fn) fn(slot1_ns_partition) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot1_ns_partition, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_ORD 167 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_ORD_STR_SORTABLE 00167 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REQUIRES_ORDS \ 162, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_EXISTS 1 #define DT_N_NODELABEL_slot1_ns_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_ADDRESS 786432 /* 0xc0000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARTITION_ID 4 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label "image-1-nonsecure" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_UNQUOTED image-1-nonsecure #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_TOKEN image_1_nonsecure #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_UPPER_TOKEN IMAGE_1_NONSECURE #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_IDX_0 "image-1-nonsecure" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg {786432 /* 0xc0000 */, 196608 /* 0x30000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0 786432 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1 196608 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f0000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f0000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FULL_NAME "partition@f0000" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FULL_NAME_UNQUOTED partition@f0000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FULL_NAME_TOKEN partition_f0000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FULL_NAME_UPPER_TOKEN PARTITION_F0000 /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_CHILD_IDX 5 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_NODELABEL(fn) fn(tfm_ps_partition) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(tfm_ps_partition, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_ORD 168 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_ORD_STR_SORTABLE 00168 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REQUIRES_ORDS \ 162, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_EXISTS 1 #define DT_N_NODELABEL_tfm_ps_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_ADDRESS 983040 /* 0xf0000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_SIZE 16384 /* 0x4000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARTITION_ID 5 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label "tfm-ps" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_STRING_UNQUOTED tfm-ps #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_STRING_TOKEN tfm_ps #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_STRING_UPPER_TOKEN TFM_PS #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_IDX_0 "tfm-ps" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg {983040 /* 0xf0000 */, 16384 /* 0x4000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0 983040 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1 16384 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f4000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f4000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FULL_NAME "partition@f4000" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FULL_NAME_UNQUOTED partition@f4000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FULL_NAME_TOKEN partition_f4000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FULL_NAME_UPPER_TOKEN PARTITION_F4000 /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_CHILD_IDX 6 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_NODELABEL(fn) fn(tfm_its_partition) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_NODELABEL_VARGS(fn, ...) fn(tfm_its_partition, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_ORD 169 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_ORD_STR_SORTABLE 00169 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_REQUIRES_ORDS \ 162, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_EXISTS 1 #define DT_N_NODELABEL_tfm_its_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_REG_IDX_0_VAL_ADDRESS 999424 /* 0xf4000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_REG_IDX_0_VAL_SIZE 8192 /* 0x2000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_PARTITION_ID 6 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label "tfm-its" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label_STRING_UNQUOTED tfm-its #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label_STRING_TOKEN tfm_its #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label_STRING_UPPER_TOKEN TFM_ITS #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label_IDX_0 "tfm-its" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_reg {999424 /* 0xf4000 */, 8192 /* 0x2000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_reg_IDX_0 999424 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_reg_IDX_1 8192 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f6000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f6000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FULL_NAME "partition@f6000" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FULL_NAME_UNQUOTED partition@f6000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FULL_NAME_TOKEN partition_f6000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FULL_NAME_UPPER_TOKEN PARTITION_F6000 /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_CHILD_IDX 7 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_NODELABEL(fn) fn(tfm_otp_partition) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_NODELABEL_VARGS(fn, ...) fn(tfm_otp_partition, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_ORD 170 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_ORD_STR_SORTABLE 00170 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_REQUIRES_ORDS \ 162, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_EXISTS 1 #define DT_N_NODELABEL_tfm_otp_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_REG_IDX_0_VAL_ADDRESS 1007616 /* 0xf6000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_REG_IDX_0_VAL_SIZE 8192 /* 0x2000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_PARTITION_ID 7 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label "tfm-otp" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label_STRING_UNQUOTED tfm-otp #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label_STRING_TOKEN tfm_otp #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label_STRING_UPPER_TOKEN TFM_OTP #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label_IDX_0 "tfm-otp" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_reg {1007616 /* 0xf6000 */, 8192 /* 0x2000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_reg_IDX_0 1007616 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_reg_IDX_1 8192 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f8000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000 * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f8000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FULL_NAME "partition@f8000" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FULL_NAME_UNQUOTED partition@f8000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FULL_NAME_TOKEN partition_f8000 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FULL_NAME_UPPER_TOKEN PARTITION_F8000 /* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_CHILD_IDX 8 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_NODELABEL(fn) fn(storage_partition) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(storage_partition, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_ORD 171 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_ORD_STR_SORTABLE 00171 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_REQUIRES_ORDS \ 162, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_EXISTS 1 #define DT_N_NODELABEL_storage_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_REG_IDX_0_VAL_ADDRESS 1015808 /* 0xf8000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_PARTITION_ID 8 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label "storage" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_STRING_UNQUOTED storage #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_STRING_TOKEN storage #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_STRING_UPPER_TOKEN STORAGE #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_IDX_0 "storage" #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_read_only 0 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_read_only_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg {1015808 /* 0xf8000 */, 32768 /* 0x8000 */} #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_0 1015808 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_1 32768 #define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000_P_reg_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2c@9000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_9000 * * Binding (compatible = nordic,nrf-twim): * $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PATH "/soc/peripheral@50000000/i2c@9000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FULL_NAME "i2c@9000" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FULL_NAME_UNQUOTED i2c@9000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FULL_NAME_TOKEN i2c_9000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FULL_NAME_UPPER_TOKEN I2C_9000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_CHILD_IDX 10 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_NODELABEL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_NODELABEL(fn) fn(i2c1) fn(arduino_i2c) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1, __VA_ARGS__) fn(arduino_i2c, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_CHILD_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_ORD 172 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_ORD_STR_SORTABLE 00172 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 46, /* /pin-controller/i2c1_default */ \ 48, /* /pin-controller/i2c1_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_SUPPORTS_ORDS \ 173, /* /soc/peripheral@50000000/i2c@9000/bmi270@68 */ \ 174, /* /soc/peripheral@50000000/i2c@9000/rv-8263-c8@51 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_9000 #define DT_N_NODELABEL_i2c1 DT_N_S_soc_S_peripheral_50000000_S_i2c_9000 #define DT_N_NODELABEL_arduino_i2c DT_N_S_soc_S_peripheral_50000000_S_i2c_9000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq 9 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MATCHES_nordic_nrf_twim 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MODEL_IDX_0 "nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_i2c1_default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_i2c1_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_concat_buf_size 257 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_concat_buf_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_flash_buf_max_size 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_flash_buf_max_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_0 36864 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_0 9 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_i2c1_default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_i2c1_default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_easydma_maxcnt_bits 16 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_clock_frequency 100000 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_sq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_sq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_cq_size 4 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible {"nordic,nrf-twim"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0 "nordic,nrf-twim" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_pm_device_runtime_auto 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_i2c1_sleep #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_i2c1_sleep #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_pinctrl_1_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2c@9000/bmi270@68 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68 */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_PATH "/soc/peripheral@50000000/i2c@9000/bmi270@68" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FULL_NAME "bmi270@68" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FULL_NAME_UNQUOTED bmi270@68 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FULL_NAME_TOKEN bmi270_68 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FULL_NAME_UPPER_TOKEN BMI270_68 /* Node parent (/soc/peripheral@50000000/i2c@9000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_PARENT DT_N_S_soc_S_peripheral_50000000_S_i2c_9000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_NODELABEL(fn) fn(bmi270) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_NODELABEL_VARGS(fn, ...) fn(bmi270, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_ORD 173 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_ORD_STR_SORTABLE 00173 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_REQUIRES_ORDS \ 172, /* /soc/peripheral@50000000/i2c@9000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_EXISTS 1 #define DT_N_ALIAS_imu DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68 #define DT_N_INST_0_i2c_device DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68 #define DT_N_NODELABEL_bmi270 DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68 /* Bus info (controller: '/soc/peripheral@50000000/i2c@9000', type: '['i2c']') */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_BUS_i2c 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_BUS DT_N_S_soc_S_peripheral_50000000_S_i2c_9000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_REG_IDX_0_VAL_ADDRESS 104 /* 0x68 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_COMPAT_MATCHES_i2c_device 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible {"i2c-device"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible_IDX_0 "i2c-device" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible_IDX_0_STRING_UNQUOTED i2c-device #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible_IDX_0_STRING_TOKEN i2c_device #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible_IDX_0_STRING_UPPER_TOKEN I2C_DEVICE #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_reg {104 /* 0x68 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_reg_IDX_0 104 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label "bmi270" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label_STRING_UNQUOTED bmi270 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label_STRING_TOKEN bmi270 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label_STRING_UPPER_TOKEN BMI270 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label_IDX_0 "bmi270" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68_P_label_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/i2c@9000/rv-8263-c8@51 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51 * * Binding (compatible = microcrystal,rv-8263-c8): * $ZEPHYR_BASE/dts/bindings/rtc/microcrystal,rv-8263-c8.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_PATH "/soc/peripheral@50000000/i2c@9000/rv-8263-c8@51" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FULL_NAME "rv-8263-c8@51" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FULL_NAME_UNQUOTED rv-8263-c8@51 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FULL_NAME_TOKEN rv_8263_c8_51 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FULL_NAME_UPPER_TOKEN RV_8263_C8_51 /* Node parent (/soc/peripheral@50000000/i2c@9000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_PARENT DT_N_S_soc_S_peripheral_50000000_S_i2c_9000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_NODELABEL(fn) fn(rv_8263_c8) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_NODELABEL_VARGS(fn, ...) fn(rv_8263_c8, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_ORD 174 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_ORD_STR_SORTABLE 00174 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_REQUIRES_ORDS \ 172, /* /soc/peripheral@50000000/i2c@9000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_EXISTS 1 #define DT_N_INST_0_microcrystal_rv_8263_c8 DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51 #define DT_N_NODELABEL_rv_8263_c8 DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51 /* Bus info (controller: '/soc/peripheral@50000000/i2c@9000', type: '['i2c']') */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_BUS_i2c 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_BUS DT_N_S_soc_S_peripheral_50000000_S_i2c_9000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_REG_IDX_0_VAL_ADDRESS 81 /* 0x51 */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_COMPAT_MATCHES_microcrystal_rv_8263_c8 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_COMPAT_VENDOR_IDX_0 "Micro Crystal AG" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_COMPAT_MODEL_IDX_0 "rv-8263-c8" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_clkout 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_clkout_IDX_0_ENUM_IDX 7 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_clkout_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_clkout_IDX_0_ENUM_VAL_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_clkout_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_alarms_count 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_alarms_count_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible {"microcrystal,rv-8263-c8"} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible_IDX_0 "microcrystal,rv-8263-c8" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible_IDX_0_STRING_UNQUOTED microcrystal,rv-8263-c8 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible_IDX_0_STRING_TOKEN microcrystal_rv_8263_c8 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible_IDX_0_STRING_UPPER_TOKEN MICROCRYSTAL_RV_8263_C8 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_reg {81 /* 0x51 */} #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_reg_IDX_0 81 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label "rv-8263-c8" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label_STRING_UNQUOTED rv-8263-c8 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label_STRING_TOKEN rv_8263_c8 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label_STRING_UPPER_TOKEN RV_8263_C8 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label_IDX_0 "rv-8263-c8" #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, label, 0) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, label, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_label_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/power@5000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000 * * Binding (compatible = nordic,nrf-power): * $ZEPHYR_BASE/dts/bindings/power/nordic,nrf-power.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PATH "/soc/peripheral@50000000/power@5000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FULL_NAME "power@5000" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FULL_NAME_UNQUOTED power@5000 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FULL_NAME_TOKEN power_5000 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FULL_NAME_UPPER_TOKEN POWER_5000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_CHILD_IDX 4 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_NODELABEL(fn) fn(power) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_NODELABEL_VARGS(fn, ...) fn(power, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_CHILD_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_CHILD_NUM_STATUS_OKAY 2 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_ORD 175 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_ORD_STR_SORTABLE 00175 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_SUPPORTS_ORDS \ 176, /* /soc/peripheral@50000000/power@5000/gpregret1@51c */ \ 177, /* /soc/peripheral@50000000/power@5000/gpregret2@520 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_power DT_N_S_soc_S_peripheral_50000000_S_power_5000 #define DT_N_NODELABEL_power DT_N_S_soc_S_peripheral_50000000_S_power_5000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 20480 /* 0x5000 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_VAL_LENGTH 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq 5 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MATCHES_nordic_nrf_power 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MODEL_IDX_0 "nrf-power" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_0 20480 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_0 5 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible {"nordic,nrf-power"} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0 "nordic,nrf-power" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-power #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_power #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_POWER #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/power@5000/gpregret1@51c * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c * * Binding (compatible = nordic,nrf-gpregret): * $ZEPHYR_BASE/dts/bindings/retained_mem/nordic,nrf-gpreget.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_PATH "/soc/peripheral@50000000/power@5000/gpregret1@51c" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FULL_NAME "gpregret1@51c" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FULL_NAME_UNQUOTED gpregret1@51c #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FULL_NAME_TOKEN gpregret1_51c #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FULL_NAME_UPPER_TOKEN GPREGRET1_51C /* Node parent (/soc/peripheral@50000000/power@5000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_PARENT DT_N_S_soc_S_peripheral_50000000_S_power_5000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_NODELABEL(fn) fn(gpregret1) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpregret1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_ORD 176 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_ORD_STR_SORTABLE 00176 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REQUIRES_ORDS \ 175, /* /soc/peripheral@50000000/power@5000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_EXISTS 1 #define DT_N_INST_0_nordic_nrf_gpregret DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c #define DT_N_NODELABEL_gpregret1 DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_IDX_0_VAL_ADDRESS 1342199068 /* 0x5000551c */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_IDX_0_VAL_SIZE 1 /* 0x1 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_MATCHES_nordic_nrf_gpregret 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_MODEL_IDX_0 "nrf-gpregret" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg {1308 /* 0x51c */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_0 1308 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible {"nordic,nrf-gpregret"} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0 "nordic,nrf-gpregret" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/power@5000/gpregret2@520 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520 * * Binding (compatible = nordic,nrf-gpregret): * $ZEPHYR_BASE/dts/bindings/retained_mem/nordic,nrf-gpreget.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_PATH "/soc/peripheral@50000000/power@5000/gpregret2@520" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FULL_NAME "gpregret2@520" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FULL_NAME_UNQUOTED gpregret2@520 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FULL_NAME_TOKEN gpregret2_520 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FULL_NAME_UPPER_TOKEN GPREGRET2_520 /* Node parent (/soc/peripheral@50000000/power@5000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_PARENT DT_N_S_soc_S_peripheral_50000000_S_power_5000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_NODELABEL(fn) fn(gpregret2) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpregret2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_ORD 177 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_ORD_STR_SORTABLE 00177 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REQUIRES_ORDS \ 175, /* /soc/peripheral@50000000/power@5000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_EXISTS 1 #define DT_N_INST_1_nordic_nrf_gpregret DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520 #define DT_N_NODELABEL_gpregret2 DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_IDX_0_VAL_ADDRESS 1342199072 /* 0x50005520 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_IDX_0_VAL_SIZE 1 /* 0x1 */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_MATCHES_nordic_nrf_gpregret 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_MODEL_IDX_0 "nrf-gpregret" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg {1312 /* 0x520 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_0 1312 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible {"nordic,nrf-gpregret"} #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0 "nordic,nrf-gpregret" #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/qspi@2b000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000 * * Binding (compatible = nordic,nrf-qspi): * $ZEPHYR_BASE/dts/bindings/flash_controller/nordic,nrf-qspi.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PATH "/soc/peripheral@50000000/qspi@2b000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FULL_NAME "qspi@2b000" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FULL_NAME_UNQUOTED qspi@2b000 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FULL_NAME_TOKEN qspi_2b000 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FULL_NAME_UPPER_TOKEN QSPI_2B000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_CHILD_IDX 43 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_NODELABEL(fn) fn(qspi) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(qspi, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_CHILD_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_ORD 178 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_ORD_STR_SORTABLE 00178 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 64, /* /pin-controller/qspi_default */ \ 66, /* /pin-controller/qspi_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_SUPPORTS_ORDS \ 179, /* /soc/peripheral@50000000/qspi@2b000/mx25r6435f@0 */ \ 180, /* /soc/peripheral@50000000/qspi@2b000/mx25r8035f@0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_qspi DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000 #define DT_N_NODELABEL_qspi DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_ADDRESS 1342353408 /* 0x5002b000 */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_ADDRESS 268435456 /* 0x10000000 */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_SIZE 268435456 /* 0x10000000 */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_VAL_ADDRESS DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_ADDRESS #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_VAL_SIZE DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_SIZE #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_mm_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_mm_VAL_ADDRESS DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_ADDRESS #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_mm_VAL_SIZE DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_SIZE #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_irq 43 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_MATCHES_nordic_nrf_qspi 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_MODEL_IDX_0 "nrf-qspi" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_qspi_default #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_qspi_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts {43 /* 0x2b */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_0 43 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_qspi_default #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_qspi_default #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg {176128 /* 0x2b000 */, 4096 /* 0x1000 */, 268435456 /* 0x10000000 */, 268435456 /* 0x10000000 */} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_0 176128 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_2_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_2 268435456 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_3_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_3 268435456 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible {"nordic,nrf-qspi"} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0 "nordic,nrf-qspi" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qspi #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qspi #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QSPI #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names {"qspi", "qspi_mm"} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0 "qspi" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_STRING_UNQUOTED qspi #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_STRING_TOKEN qspi #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_STRING_UPPER_TOKEN QSPI #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1 "qspi_mm" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_STRING_UNQUOTED qspi_mm #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_STRING_TOKEN qspi_mm #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_STRING_UPPER_TOKEN QSPI_MM #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_qspi_sleep #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_qspi_sleep #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_pinctrl_1_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/qspi@2b000/mx25r6435f@0 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0 * * Binding (compatible = nordic,qspi-nor): * $ZEPHYR_BASE/dts/bindings/mtd/nordic,qspi-nor.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_PATH "/soc/peripheral@50000000/qspi@2b000/mx25r6435f@0" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FULL_NAME "mx25r6435f@0" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FULL_NAME_UNQUOTED mx25r6435f@0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FULL_NAME_TOKEN mx25r6435f_0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FULL_NAME_UPPER_TOKEN MX25R6435F_0 /* Node parent (/soc/peripheral@50000000/qspi@2b000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_NODELABEL(fn) fn(mx25r64) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(mx25r64, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_ORD 179 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_ORD_STR_SORTABLE 00179 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_REQUIRES_ORDS \ 178, /* /soc/peripheral@50000000/qspi@2b000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_EXISTS 1 #define DT_N_INST_1_nordic_qspi_nor DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0 #define DT_N_NODELABEL_mx25r64 DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0 /* Bus info (controller: '/soc/peripheral@50000000/qspi@2b000', type: '['qspi']') */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_BUS_qspi 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_BUS DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_COMPAT_MATCHES_nordic_qspi_nor 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_COMPAT_MODEL_IDX_0 "qspi-nor" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg {0 /* 0x0 */} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id {194 /* 0xc2 */, 40 /* 0x28 */, 23 /* 0x17 */} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_0 194 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_1 40 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_2_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_IDX_2 23 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 1) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 2) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 2) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 1, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, jedec_id, 2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_LEN 3 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_jedec_id_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_size 67108864 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements "S1B6" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_STRING_UNQUOTED S1B6 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_STRING_TOKEN S1B6 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_STRING_UPPER_TOKEN S1B6 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_IDX_0 "S1B6" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_IDX_0_ENUM_VAL_S1B6_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, quad_enable_requirements, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_quad_enable_requirements_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc "read4io" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_STRING_UNQUOTED read4io #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_STRING_TOKEN read4io #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_STRING_UPPER_TOKEN READ4IO #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_IDX_0 "read4io" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_IDX_0_ENUM_IDX 4 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_IDX_0_ENUM_VAL_read4io_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, readoc, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_readoc_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc "pp4io" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_STRING_UNQUOTED pp4io #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_STRING_TOKEN pp4io #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_STRING_UPPER_TOKEN PP4IO #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_IDX_0 "pp4io" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_IDX_0_ENUM_IDX 3 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_IDX_0_ENUM_VAL_pp4io_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, writeoc, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_writeoc_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_address_size_32 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_address_size_32_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_ppsize_512 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_ppsize_512_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sck_delay 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sck_delay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_cpha 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_cpha_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_cpol 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_cpol_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sck_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sck_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible {"nordic,qspi-nor"} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_IDX_0 "nordic,qspi-nor" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_UNQUOTED nordic,qspi-nor #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_TOKEN nordic_qspi_nor #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_QSPI_NOR #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_requires_ulbpr 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_requires_ulbpr_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_has_dpd 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_has_dpd_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_t_enter_dpd 10000 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_t_enter_dpd_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_t_exit_dpd 35000 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_t_exit_dpd_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_use_4b_addr_opcodes 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_use_4b_addr_opcodes_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp {229 /* 0xe5 */, 32 /* 0x20 */, 241 /* 0xf1 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 3 /* 0x3 */, 68 /* 0x44 */, 235 /* 0xeb */, 8 /* 0x8 */, 107 /* 0x6b */, 8 /* 0x8 */, 59 /* 0x3b */, 4 /* 0x4 */, 187 /* 0xbb */, 238 /* 0xee */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 12 /* 0xc */, 32 /* 0x20 */, 15 /* 0xf */, 82 /* 0x52 */, 16 /* 0x10 */, 216 /* 0xd8 */, 0 /* 0x0 */, 255 /* 0xff */, 35 /* 0x23 */, 114 /* 0x72 */, 245 /* 0xf5 */, 0 /* 0x0 */, 130 /* 0x82 */, 237 /* 0xed */, 4 /* 0x4 */, 204 /* 0xcc */, 68 /* 0x44 */, 131 /* 0x83 */, 104 /* 0x68 */, 68 /* 0x44 */, 48 /* 0x30 */, 176 /* 0xb0 */, 48 /* 0x30 */, 176 /* 0xb0 */, 247 /* 0xf7 */, 196 /* 0xc4 */, 213 /* 0xd5 */, 92 /* 0x5c */, 0 /* 0x0 */, 190 /* 0xbe */, 41 /* 0x29 */, 255 /* 0xff */, 240 /* 0xf0 */, 208 /* 0xd0 */, 255 /* 0xff */, 255 /* 0xff */} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_0 229 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_1 32 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_2_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_2 241 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_3_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_3 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_4_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_4 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_5_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_5 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_6_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_6 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_7_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_7 3 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_8_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_8 68 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_9_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_9 235 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_10_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_10 8 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_11_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_11 107 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_12_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_12 8 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_13_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_13 59 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_14_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_14 4 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_15_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_15 187 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_16_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_16 238 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_17_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_17 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_18_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_18 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_19_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_19 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_20_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_20 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_21_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_21 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_22_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_22 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_23_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_23 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_24_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_24 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_25_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_25 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_26_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_26 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_27_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_27 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_28_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_28 12 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_29_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_29 32 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_30_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_30 15 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_31_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_31 82 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_32_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_32 16 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_33_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_33 216 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_34_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_34 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_35_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_35 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_36_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_36 35 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_37_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_37 114 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_38_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_38 245 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_39_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_39 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_40_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_40 130 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_41_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_41 237 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_42_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_42 4 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_43_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_43 204 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_44_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_44 68 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_45_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_45 131 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_46_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_46 104 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_47_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_47 68 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_48_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_48 48 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_49_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_49 176 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_50_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_50 48 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_51_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_51 176 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_52_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_52 247 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_53_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_53 196 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_54_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_54 213 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_55_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_55 92 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_56_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_56 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_57_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_57 190 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_58_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_58 41 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_59_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_59 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_60_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_60 240 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_61_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_61 208 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_62_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_62 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_63_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_IDX_63 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 1) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 2) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 3) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 4) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 5) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 6) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 7) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 8) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 9) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 10) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 11) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 12) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 13) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 14) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 15) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 16) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 17) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 18) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 19) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 20) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 21) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 22) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 23) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 24) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 25) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 26) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 27) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 28) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 29) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 30) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 31) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 32) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 33) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 34) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 35) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 36) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 37) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 38) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 39) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 40) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 41) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 42) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 43) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 44) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 45) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 46) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 47) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 48) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 49) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 50) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 51) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 52) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 53) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 54) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 55) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 56) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 57) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 58) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 59) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 60) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 61) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 62) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 63) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 3) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 4) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 5) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 6) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 7) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 8) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 9) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 10) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 11) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 12) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 13) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 14) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 15) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 16) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 17) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 18) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 19) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 20) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 21) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 22) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 23) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 24) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 25) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 26) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 27) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 28) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 29) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 30) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 31) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 32) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 33) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 34) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 35) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 36) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 37) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 38) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 39) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 40) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 41) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 42) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 43) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 44) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 45) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 46) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 47) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 48) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 49) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 50) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 51) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 52) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 53) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 54) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 55) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 56) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 57) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 58) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 59) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 60) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 61) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 62) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 63) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 1, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 2, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 3, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 4, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 5, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 6, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 7, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 8, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 9, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 10, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 11, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 12, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 13, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 14, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 15, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 16, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 17, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 18, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 19, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 20, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 21, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 22, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 23, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 24, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 25, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 26, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 27, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 28, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 29, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 30, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 31, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 32, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 33, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 34, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 35, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 36, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 37, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 38, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 39, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 40, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 41, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 42, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 43, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 44, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 45, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 46, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 47, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 48, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 49, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 50, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 51, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 52, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 53, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 54, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 55, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 56, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 57, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 58, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 59, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 60, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 61, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 62, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 63, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 21, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 22, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 23, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 24, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 25, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 26, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 27, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 28, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 29, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 30, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 31, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 32, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 33, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 34, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 35, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 36, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 37, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 38, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 39, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 40, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 41, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 42, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 43, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 44, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 45, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 46, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 47, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 48, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 49, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 50, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 51, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 52, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 53, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 54, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 55, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 56, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 57, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 58, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 59, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 60, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 61, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 62, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, sfdp_bfp, 63, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_LEN 64 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0_P_sfdp_bfp_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/qspi@2b000/mx25r8035f@0 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0 * * Binding (compatible = nordic,qspi-nor): * $ZEPHYR_BASE/dts/bindings/mtd/nordic,qspi-nor.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_PATH "/soc/peripheral@50000000/qspi@2b000/mx25r8035f@0" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FULL_NAME "mx25r8035f@0" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FULL_NAME_UNQUOTED mx25r8035f@0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FULL_NAME_TOKEN mx25r8035f_0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FULL_NAME_UPPER_TOKEN MX25R8035F_0 /* Node parent (/soc/peripheral@50000000/qspi@2b000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_NODELABEL(fn) fn(mx25r80) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(mx25r80, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_ORD 180 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_ORD_STR_SORTABLE 00180 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_REQUIRES_ORDS \ 178, /* /soc/peripheral@50000000/qspi@2b000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_EXISTS 1 #define DT_N_INST_0_nordic_qspi_nor DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0 #define DT_N_NODELABEL_mx25r80 DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0 /* Bus info (controller: '/soc/peripheral@50000000/qspi@2b000', type: '['qspi']') */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_BUS_qspi 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_BUS DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_COMPAT_MATCHES_nordic_qspi_nor 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_COMPAT_MODEL_IDX_0 "qspi-nor" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_reg {0 /* 0x0 */} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id {194 /* 0xc2 */, 40 /* 0x28 */, 20 /* 0x14 */} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_IDX_0 194 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_IDX_1 40 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_IDX_2_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_IDX_2 20 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 1) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 2) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 2) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 1, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, jedec_id, 2, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_LEN 3 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_jedec_id_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_size 8388608 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_size_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements "S1B6" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_STRING_UNQUOTED S1B6 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_STRING_TOKEN S1B6 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_STRING_UPPER_TOKEN S1B6 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_IDX_0 "S1B6" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_IDX_0_ENUM_IDX 2 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_IDX_0_ENUM_VAL_S1B6_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, quad_enable_requirements, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, quad_enable_requirements, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, quad_enable_requirements, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, quad_enable_requirements, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_quad_enable_requirements_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc "read4io" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_STRING_UNQUOTED read4io #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_STRING_TOKEN read4io #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_STRING_UPPER_TOKEN READ4IO #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_IDX_0 "read4io" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_IDX_0_ENUM_IDX 4 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_IDX_0_ENUM_VAL_read4io_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, readoc, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, readoc, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, readoc, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, readoc, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_readoc_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc "pp4io" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_STRING_UNQUOTED pp4io #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_STRING_TOKEN pp4io #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_STRING_UPPER_TOKEN PP4IO #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_IDX_0 "pp4io" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_IDX_0_ENUM_IDX 3 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_IDX_0_ENUM_VAL_pp4io_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, writeoc, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, writeoc, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, writeoc, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, writeoc, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_writeoc_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_address_size_32 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_address_size_32_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_ppsize_512 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_ppsize_512_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sck_delay 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sck_delay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_cpha 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_cpha_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_cpol 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_cpol_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sck_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sck_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible {"nordic,qspi-nor"} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible_IDX_0 "nordic,qspi-nor" #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible_IDX_0_STRING_UNQUOTED nordic,qspi-nor #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible_IDX_0_STRING_TOKEN nordic_qspi_nor #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_QSPI_NOR #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_requires_ulbpr 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_requires_ulbpr_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_has_dpd 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_has_dpd_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_t_enter_dpd 10000 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_t_enter_dpd_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_t_exit_dpd 35000 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_t_exit_dpd_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_use_4b_addr_opcodes 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_use_4b_addr_opcodes_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp {229 /* 0xe5 */, 32 /* 0x20 */, 241 /* 0xf1 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 127 /* 0x7f */, 0 /* 0x0 */, 68 /* 0x44 */, 235 /* 0xeb */, 8 /* 0x8 */, 107 /* 0x6b */, 8 /* 0x8 */, 59 /* 0x3b */, 4 /* 0x4 */, 187 /* 0xbb */, 238 /* 0xee */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 12 /* 0xc */, 32 /* 0x20 */, 15 /* 0xf */, 82 /* 0x52 */, 16 /* 0x10 */, 216 /* 0xd8 */, 0 /* 0x0 */, 255 /* 0xff */, 35 /* 0x23 */, 114 /* 0x72 */, 245 /* 0xf5 */, 0 /* 0x0 */, 130 /* 0x82 */, 237 /* 0xed */, 4 /* 0x4 */, 183 /* 0xb7 */, 68 /* 0x44 */, 131 /* 0x83 */, 56 /* 0x38 */, 68 /* 0x44 */, 48 /* 0x30 */, 176 /* 0xb0 */, 48 /* 0x30 */, 176 /* 0xb0 */, 247 /* 0xf7 */, 196 /* 0xc4 */, 213 /* 0xd5 */, 92 /* 0x5c */, 0 /* 0x0 */, 190 /* 0xbe */, 41 /* 0x29 */, 255 /* 0xff */, 240 /* 0xf0 */, 208 /* 0xd0 */, 255 /* 0xff */, 255 /* 0xff */} #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_0 229 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_1 32 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_2_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_2 241 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_3_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_3 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_4_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_4 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_5_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_5 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_6_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_6 127 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_7_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_7 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_8_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_8 68 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_9_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_9 235 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_10_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_10 8 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_11_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_11 107 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_12_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_12 8 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_13_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_13 59 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_14_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_14 4 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_15_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_15 187 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_16_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_16 238 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_17_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_17 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_18_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_18 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_19_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_19 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_20_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_20 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_21_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_21 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_22_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_22 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_23_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_23 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_24_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_24 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_25_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_25 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_26_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_26 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_27_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_27 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_28_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_28 12 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_29_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_29 32 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_30_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_30 15 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_31_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_31 82 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_32_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_32 16 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_33_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_33 216 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_34_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_34 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_35_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_35 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_36_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_36 35 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_37_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_37 114 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_38_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_38 245 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_39_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_39 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_40_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_40 130 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_41_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_41 237 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_42_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_42 4 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_43_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_43 183 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_44_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_44 68 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_45_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_45 131 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_46_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_46 56 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_47_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_47 68 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_48_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_48 48 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_49_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_49 176 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_50_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_50 48 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_51_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_51 176 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_52_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_52 247 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_53_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_53 196 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_54_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_54 213 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_55_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_55 92 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_56_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_56 0 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_57_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_57 190 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_58_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_58 41 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_59_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_59 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_60_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_60 240 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_61_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_61 208 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_62_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_62 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_63_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_IDX_63 255 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 1) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 2) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 3) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 4) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 5) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 6) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 7) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 8) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 9) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 10) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 11) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 12) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 13) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 14) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 15) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 16) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 17) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 18) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 19) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 20) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 21) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 22) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 23) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 24) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 25) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 26) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 27) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 28) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 29) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 30) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 31) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 32) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 33) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 34) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 35) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 36) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 37) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 38) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 39) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 40) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 41) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 42) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 43) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 44) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 45) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 46) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 47) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 48) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 49) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 50) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 51) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 52) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 53) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 54) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 55) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 56) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 57) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 58) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 59) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 60) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 61) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 62) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 63) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 2) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 3) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 4) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 5) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 6) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 7) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 8) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 9) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 10) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 11) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 12) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 13) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 14) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 15) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 16) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 17) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 18) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 19) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 20) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 21) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 22) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 23) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 24) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 25) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 26) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 27) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 28) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 29) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 30) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 31) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 32) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 33) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 34) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 35) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 36) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 37) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 38) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 39) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 40) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 41) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 42) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 43) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 44) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 45) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 46) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 47) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 48) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 49) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 50) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 51) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 52) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 53) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 54) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 55) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 56) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 57) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 58) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 59) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 60) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 61) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 62) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 63) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 1, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 2, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 3, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 4, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 5, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 6, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 7, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 8, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 9, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 10, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 11, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 12, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 13, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 14, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 15, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 16, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 17, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 18, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 19, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 20, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 21, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 22, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 23, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 24, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 25, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 26, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 27, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 28, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 29, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 30, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 31, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 32, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 33, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 34, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 35, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 36, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 37, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 38, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 39, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 40, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 41, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 42, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 43, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 44, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 45, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 46, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 47, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 48, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 49, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 50, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 51, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 52, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 53, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 54, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 55, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 56, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 57, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 58, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 59, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 60, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 61, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 62, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 63, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 21, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 22, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 23, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 24, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 25, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 26, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 27, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 28, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 29, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 30, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 31, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 32, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 33, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 34, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 35, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 36, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 37, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 38, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 39, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 40, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 41, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 42, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 43, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 44, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 45, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 46, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 47, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 48, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 49, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 50, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 51, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 52, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 53, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 54, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 55, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 56, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 57, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 58, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 59, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 60, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 61, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 62, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, sfdp_bfp, 63, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_LEN 64 #define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0_P_sfdp_bfp_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/regulator@4000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000 * * Binding (compatible = nordic,nrf53x-regulators): * $ZEPHYR_BASE/dts/bindings/regulator/nordic,nrf53x-regulators.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PATH "/soc/peripheral@50000000/regulator@4000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FULL_NAME "regulator@4000" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FULL_NAME_UNQUOTED regulator@4000 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FULL_NAME_TOKEN regulator_4000 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FULL_NAME_UPPER_TOKEN REGULATOR_4000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_CHILD_IDX 2 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_NODELABEL(fn) fn(regulators) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_NODELABEL_VARGS(fn, ...) fn(regulators, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_CHILD_NUM 3 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_CHILD_NUM_STATUS_OKAY 3 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_ORD 181 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_ORD_STR_SORTABLE 00181 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REQUIRES_ORDS \ 10, /* /soc/peripheral@50000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_SUPPORTS_ORDS \ 182, /* /soc/peripheral@50000000/regulator@4000/regulator@4704 */ \ 183, /* /soc/peripheral@50000000/regulator@4000/regulator@4904 */ \ 184, /* /soc/peripheral@50000000/regulator@4000/regulator@4b00 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_EXISTS 1 #define DT_N_INST_0_nordic_nrf53x_regulators DT_N_S_soc_S_peripheral_50000000_S_regulator_4000 #define DT_N_NODELABEL_regulators DT_N_S_soc_S_peripheral_50000000_S_regulator_4000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_ADDRESS 1342193664 /* 0x50004000 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MATCHES_nordic_nrf53x_regulators 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MODEL_IDX_0 "nrf53x-regulators" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg {16384 /* 0x4000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_0 16384 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible {"nordic,nrf53x-regulators"} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0 "nordic,nrf53x-regulators" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf53x-regulators #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf53x_regulators #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF53X_REGULATORS #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/regulator@4000/regulator@4704 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704 * * Binding (compatible = nordic,nrf5x-regulator): * $ZEPHYR_BASE/dts/bindings/regulator/nordic,nrf5x-regulator.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_PATH "/soc/peripheral@50000000/regulator@4000/regulator@4704" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FULL_NAME "regulator@4704" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FULL_NAME_UNQUOTED regulator@4704 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FULL_NAME_TOKEN regulator_4704 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FULL_NAME_UPPER_TOKEN REGULATOR_4704 /* Node parent (/soc/peripheral@50000000/regulator@4000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_PARENT DT_N_S_soc_S_peripheral_50000000_S_regulator_4000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_NODELABEL(fn) fn(vregmain) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_NODELABEL_VARGS(fn, ...) fn(vregmain, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_ORD 182 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_ORD_STR_SORTABLE 00182 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_REQUIRES_ORDS \ 181, /* /soc/peripheral@50000000/regulator@4000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_EXISTS 1 #define DT_N_INST_0_nordic_nrf5x_regulator DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704 #define DT_N_NODELABEL_vregmain DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_REG_IDX_0_VAL_ADDRESS 18180 /* 0x4704 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_REG_IDX_0_VAL_SIZE 1 /* 0x1 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_COMPAT_MATCHES_nordic_nrf5x_regulator 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_COMPAT_MODEL_IDX_0 "nrf5x-regulator" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg {18180 /* 0x4704 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg_IDX_0 18180 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name "VREGMAIN" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_STRING_UNQUOTED VREGMAIN #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_STRING_TOKEN VREGMAIN #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_STRING_UPPER_TOKEN VREGMAIN #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_IDX_0 "VREGMAIN" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, regulator_name, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, regulator_name, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, regulator_name, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, regulator_name, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_initial_mode 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_initial_mode_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible {"nordic,nrf5x-regulator"} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_IDX_0 "nordic,nrf5x-regulator" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf5x-regulator #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_IDX_0_STRING_TOKEN nordic_nrf5x_regulator #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF5X_REGULATOR #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/regulator@4000/regulator@4904 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904 * * Binding (compatible = nordic,nrf5x-regulator): * $ZEPHYR_BASE/dts/bindings/regulator/nordic,nrf5x-regulator.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_PATH "/soc/peripheral@50000000/regulator@4000/regulator@4904" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FULL_NAME "regulator@4904" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FULL_NAME_UNQUOTED regulator@4904 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FULL_NAME_TOKEN regulator_4904 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FULL_NAME_UPPER_TOKEN REGULATOR_4904 /* Node parent (/soc/peripheral@50000000/regulator@4000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_PARENT DT_N_S_soc_S_peripheral_50000000_S_regulator_4000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_CHILD_IDX 1 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_NODELABEL(fn) fn(vregradio) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_NODELABEL_VARGS(fn, ...) fn(vregradio, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_ORD 183 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_ORD_STR_SORTABLE 00183 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_REQUIRES_ORDS \ 181, /* /soc/peripheral@50000000/regulator@4000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_EXISTS 1 #define DT_N_INST_1_nordic_nrf5x_regulator DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904 #define DT_N_NODELABEL_vregradio DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_REG_IDX_0_VAL_ADDRESS 18692 /* 0x4904 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_REG_IDX_0_VAL_SIZE 1 /* 0x1 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_COMPAT_MATCHES_nordic_nrf5x_regulator 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_COMPAT_MODEL_IDX_0 "nrf5x-regulator" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg {18692 /* 0x4904 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg_IDX_0 18692 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name "VREGRADIO" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_STRING_UNQUOTED VREGRADIO #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_STRING_TOKEN VREGRADIO #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_STRING_UPPER_TOKEN VREGRADIO #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_IDX_0 "VREGRADIO" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, regulator_name, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, regulator_name, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, regulator_name, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, regulator_name, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_initial_mode 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_initial_mode_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible {"nordic,nrf5x-regulator"} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_IDX_0 "nordic,nrf5x-regulator" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf5x-regulator #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_IDX_0_STRING_TOKEN nordic_nrf5x_regulator #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF5X_REGULATOR #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/regulator@4000/regulator@4b00 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00 * * Binding (compatible = nordic,nrf53x-regulator-hv): * $ZEPHYR_BASE/dts/bindings/regulator/nordic,nrf53x-regulator-hv.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_PATH "/soc/peripheral@50000000/regulator@4000/regulator@4b00" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FULL_NAME "regulator@4b00" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FULL_NAME_UNQUOTED regulator@4b00 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FULL_NAME_TOKEN regulator_4b00 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FULL_NAME_UPPER_TOKEN REGULATOR_4B00 /* Node parent (/soc/peripheral@50000000/regulator@4000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_PARENT DT_N_S_soc_S_peripheral_50000000_S_regulator_4000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_CHILD_IDX 2 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_NODELABEL(fn) fn(vregh) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_NODELABEL_VARGS(fn, ...) fn(vregh, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_ORD 184 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_ORD_STR_SORTABLE 00184 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_REQUIRES_ORDS \ 181, /* /soc/peripheral@50000000/regulator@4000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_EXISTS 1 #define DT_N_INST_0_nordic_nrf53x_regulator_hv DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00 #define DT_N_NODELABEL_vregh DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_REG_IDX_0_VAL_ADDRESS 19200 /* 0x4b00 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_REG_IDX_0_VAL_SIZE 68 /* 0x44 */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_COMPAT_MATCHES_nordic_nrf53x_regulator_hv 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_COMPAT_MODEL_IDX_0 "nrf53x-regulator-hv" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg {19200 /* 0x4b00 */, 68 /* 0x44 */} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg_IDX_0 19200 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg_IDX_1 68 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name "VREGH" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_STRING_UNQUOTED VREGH #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_STRING_TOKEN VREGH #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_STRING_UPPER_TOKEN VREGH #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_IDX_0 "VREGH" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, regulator_name, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, regulator_name, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, regulator_name, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, regulator_name, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible {"nordic,nrf53x-regulator-hv"} #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_IDX_0 "nordic,nrf53x-regulator-hv" #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf53x-regulator-hv #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_IDX_0_STRING_TOKEN nordic_nrf53x_regulator_hv #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF53X_REGULATOR_HV #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/spi@8000 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_8000 * * Binding (compatible = nordic,nrf-spim): * $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PATH "/soc/peripheral@50000000/spi@8000" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FULL_NAME "spi@8000" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FULL_NAME_UNQUOTED spi@8000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FULL_NAME_TOKEN spi_8000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FULL_NAME_UPPER_TOKEN SPI_8000 /* Node parent (/soc/peripheral@50000000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PARENT DT_N_S_soc_S_peripheral_50000000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_CHILD_IDX 8 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_NODELABEL(fn) fn(spi0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_CHILD_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_CHILD_NUM_STATUS_OKAY 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_ORD 185 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_ORD_STR_SORTABLE 00185 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REQUIRES_ORDS \ 9, /* /soc/interrupt-controller@e000e100 */ \ 10, /* /soc/peripheral@50000000 */ \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 69, /* /pin-controller/spi0_sx128x_default */ \ 71, /* /pin-controller/spi0_sx128x_sleep */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_SUPPORTS_ORDS \ 186, /* /soc/peripheral@50000000/spi@8000/sx1280@0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_EXISTS 1 #define DT_N_INST_0_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_8000 #define DT_N_NODELABEL_spi0 DT_N_S_soc_S_peripheral_50000000_S_spi_8000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq 8 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_LEVEL 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MATCHES_nordic_nrf_spim 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MODEL_IDX_0 "nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_NUM 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_IDX_0_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_NAME_default_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_NAME_default_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi0_sx128x_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_IDX_1_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_NAME_sleep_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_NAME_sleep_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi0_sx128x_sleep /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_anomaly_58_workaround 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_anomaly_58_workaround_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_rx_delay_supported 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_rx_delay_supported_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_0 32768 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_0 8 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi0_sx128x_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi0_sx128x_default #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_0_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_0, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_0, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_0_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names {"default", "sleep"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_IDX_1 "sleep" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_names, 0) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_names, 1) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_names, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_LEN 2 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_max_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_overrun_character 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_overrun_character_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_easydma_maxcnt_bits 16 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_easydma_maxcnt_bits_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_IDX_0_VAL_pin 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_IDX_0_VAL_flags 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, cs_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, cs_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, cs_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, cs_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_cs_gpios_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible {"nordic,nrf-spim"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0 "nordic,nrf-spim" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi0_sx128x_sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi0_sx128x_sleep #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_1_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_1, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, pinctrl_1, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_1_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_pinctrl_1_EXISTS 1 /* * Devicetree node: /soc/peripheral@50000000/spi@8000/sx1280@0 * * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0 * * Binding (compatible = semtech,sx1262): * $ZEPHYR_BASE/dts/bindings/lora/semtech,sx1262.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_PATH "/soc/peripheral@50000000/spi@8000/sx1280@0" /* Node's name with unit-address: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FULL_NAME "sx1280@0" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FULL_NAME_UNQUOTED sx1280@0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FULL_NAME_TOKEN sx1280_0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FULL_NAME_UPPER_TOKEN SX1280_0 /* Node parent (/soc/peripheral@50000000/spi@8000) identifier: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_spi_8000 /* Node's index in its parent's list of children: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_NODELABEL_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_NODELABEL(fn) fn(sx1280) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(sx1280, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc) fn(DT_N) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_CHILD_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_CHILD_NUM_STATUS_OKAY 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_CHILD(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_CHILD_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_CHILD_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_CHILD_STATUS_OKAY(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_ORD 186 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_ORD_STR_SORTABLE 00186 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_REQUIRES_ORDS \ 15, /* /soc/peripheral@50000000/gpio@842500 */ \ 16, /* /soc/peripheral@50000000/gpio@842800 */ \ 185, /* /soc/peripheral@50000000/spi@8000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_EXISTS 1 #define DT_N_ALIAS_sx1280 DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0 #define DT_N_INST_0_semtech_sx1262 DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0 #define DT_N_NODELABEL_sx1280 DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0 /* Bus info (controller: '/soc/peripheral@50000000/spi@8000', type: '['spi']') */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_BUS_spi 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_BUS DT_N_S_soc_S_peripheral_50000000_S_spi_8000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_REG_NUM 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_REG_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_RANGES_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_IRQ_NUM 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_IRQ_LEVEL 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_COMPAT_MATCHES_semtech_sx1262 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_COMPAT_VENDOR_IDX_0 "Semtech Corporation" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_COMPAT_MODEL_IDX_0 "sx1262" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_PINCTRL_NUM 0 /* Generic property macros: */ #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_IDX_0_VAL_pin 9 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_IDX_0_VAL_flags 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, reset_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, reset_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, reset_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, reset_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reset_gpios_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842800 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_IDX_0_VAL_pin 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_IDX_0_VAL_flags 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, busy_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, busy_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, busy_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, busy_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_busy_gpios_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_IDX_0_VAL_pin 10 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_IDX_0_VAL_flags 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, dio1_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, dio1_gpios, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, dio1_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, dio1_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio1_gpios_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio2_tx_enable 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_dio2_tx_enable_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reg {0 /* 0x0 */} #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_reg_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_spi_max_frequency 8000000 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_spi_max_frequency_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_duplex 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_duplex_IDX_0_ENUM_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_duplex_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_duplex_IDX_0_ENUM_VAL_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_duplex_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_frame_format 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_frame_format_IDX_0_ENUM_IDX 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_frame_format_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_frame_format_IDX_0_ENUM_VAL_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_frame_format_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_spi_cpol 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_spi_cpol_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_spi_cpha 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_spi_cpha_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_spi_hold_cs 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_spi_hold_cs_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status "okay" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_IDX_0 "okay" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_IDX_0_ENUM_IDX 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, status, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, status, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_status_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible {"semtech,sx1262"} #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible_IDX_0 "semtech,sx1262" #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible_IDX_0_STRING_UNQUOTED semtech,sx1262 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible_IDX_0_STRING_TOKEN semtech_sx1262 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SEMTECH_SX1262 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, compatible, 0) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible_LEN 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_compatible_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_wakeup_source 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Chosen nodes */ #define DT_CHOSEN_zephyr_entropy DT_N_S_soc_S_crypto_50844000 #define DT_CHOSEN_zephyr_entropy_EXISTS 1 #define DT_CHOSEN_zephyr_flash_controller DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000 #define DT_CHOSEN_zephyr_flash_controller_EXISTS 1 #define DT_CHOSEN_zephyr_console DT_N_S_soc_S_peripheral_50000000_S_uart_8000 #define DT_CHOSEN_zephyr_console_EXISTS 1 #define DT_CHOSEN_zephyr_shell_uart DT_N_S_soc_S_peripheral_50000000_S_uart_8000 #define DT_CHOSEN_zephyr_shell_uart_EXISTS 1 #define DT_CHOSEN_zephyr_uart_mcumgr DT_N_S_soc_S_peripheral_50000000_S_uart_8000 #define DT_CHOSEN_zephyr_uart_mcumgr_EXISTS 1 #define DT_CHOSEN_zephyr_bt_mon_uart DT_N_S_soc_S_peripheral_50000000_S_uart_8000 #define DT_CHOSEN_zephyr_bt_mon_uart_EXISTS 1 #define DT_CHOSEN_zephyr_bt_c2h_uart DT_N_S_soc_S_peripheral_50000000_S_uart_8000 #define DT_CHOSEN_zephyr_bt_c2h_uart_EXISTS 1 #define DT_CHOSEN_zephyr_bt_hci DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0 #define DT_CHOSEN_zephyr_bt_hci_EXISTS 1 #define DT_CHOSEN_nordic_802154_spinel_ipc DT_N_S_ipc_S_ipc0 #define DT_CHOSEN_nordic_802154_spinel_ipc_EXISTS 1 #define DT_CHOSEN_zephyr_ieee802154 DT_N_S_soc_S_peripheral_50000000_S_ieee802154 #define DT_CHOSEN_zephyr_ieee802154_EXISTS 1 #define DT_CHOSEN_zephyr_sram DT_N_S_reserved_memory_S_image_20000000 #define DT_CHOSEN_zephyr_sram_EXISTS 1 #define DT_CHOSEN_zephyr_flash DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0 #define DT_CHOSEN_zephyr_flash_EXISTS 1 #define DT_CHOSEN_zephyr_code_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000 #define DT_CHOSEN_zephyr_code_partition_EXISTS 1 #define DT_CHOSEN_zephyr_sram_secure_partition DT_N_S_reserved_memory_S_image_s_20000000 #define DT_CHOSEN_zephyr_sram_secure_partition_EXISTS 1 #define DT_CHOSEN_zephyr_sram_non_secure_partition DT_N_S_reserved_memory_S_image_ns_20040000 #define DT_CHOSEN_zephyr_sram_non_secure_partition_EXISTS 1 #define DT_CHOSEN_zephyr_display DT_N_S_mipi_dbi_st7789v_S_st7789v_0 #define DT_CHOSEN_zephyr_display_EXISTS 1 #define DT_CHOSEN_zephyr_rtc DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51 #define DT_CHOSEN_zephyr_rtc_EXISTS 1 #define DT_CHOSEN_nordic_pm_ext_flash DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0 #define DT_CHOSEN_nordic_pm_ext_flash_EXISTS 1 /* Macros for iterating over all nodes and enabled nodes */ #define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_gpiote_4002f000) fn(DT_N_S_soc_S_crypto_50844000) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_default_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_default_S_group1) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm0_backlight_default) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm2_motor_default) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi0_sx128x_default) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart2_default) fn(DT_N_S_pin_controller_S_uart2_default_S_group1) fn(DT_N_S_pin_controller_S_uart2_default_S_group2) fn(DT_N_S_pin_controller_S_uart2_sleep) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi3_st7789v_default) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_sw_pwm) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_ipc) fn(DT_N_S_ipc_S_ipc0) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0) fn(DT_N_S_ipc_S_ipc1) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_buttons) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) fn(DT_N_S_connector) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_pwm_led_0) fn(DT_N_S_pwmleds_S_backlight) fn(DT_N_S_pwmleds_S_motor) fn(DT_N_S_pwmleds_S_buzzer) fn(DT_N_S_analog_connector) fn(DT_N_S_nrf_gpio_forwarder) fn(DT_N_S_reserved_memory) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_image_ns_app_20040000) fn(DT_N_S_reserved_memory_S_memory_20070000) fn(DT_N_S_reserved_memory_S_memory_20078000) fn(DT_N_S_gpio_fwd) fn(DT_N_S_mipi_dbi_st7789v) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0) fn(DT_N_S_pins_io) fn(DT_N_S_pins_io_S_key1) fn(DT_N_S_pins_io_S_en_motor) fn(DT_N_S_zephyr_user) #define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_crypto_50844000) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_default_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_default_S_group1) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm0_backlight_default) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm2_motor_default) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi0_sx128x_default) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart2_default) fn(DT_N_S_pin_controller_S_uart2_default_S_group1) fn(DT_N_S_pin_controller_S_uart2_default_S_group2) fn(DT_N_S_pin_controller_S_uart2_sleep) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi3_st7789v_default) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_ipc) fn(DT_N_S_ipc_S_ipc0) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0) fn(DT_N_S_ipc_S_ipc1) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_buttons) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_pwm_led_0) fn(DT_N_S_pwmleds_S_backlight) fn(DT_N_S_pwmleds_S_motor) fn(DT_N_S_pwmleds_S_buzzer) fn(DT_N_S_reserved_memory) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_image_ns_app_20040000) fn(DT_N_S_reserved_memory_S_memory_20070000) fn(DT_N_S_reserved_memory_S_memory_20078000) fn(DT_N_S_mipi_dbi_st7789v) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0) fn(DT_N_S_pins_io) fn(DT_N_S_pins_io_S_key1) fn(DT_N_S_pins_io_S_en_motor) fn(DT_N_S_zephyr_user) #define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_lfxo, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r6435f_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_4002f000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_sw_pwm, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_ipc, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc1, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) fn(DT_N_S_pwmleds_S_backlight, __VA_ARGS__) fn(DT_N_S_pwmleds_S_motor, __VA_ARGS__) fn(DT_N_S_pwmleds_S_buzzer, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__) fn(DT_N_S_nrf_gpio_forwarder, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_app_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20070000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__) fn(DT_N_S_gpio_fwd, __VA_ARGS__) fn(DT_N_S_mipi_dbi_st7789v, __VA_ARGS__) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, __VA_ARGS__) fn(DT_N_S_pins_io, __VA_ARGS__) fn(DT_N_S_pins_io_S_key1, __VA_ARGS__) fn(DT_N_S_pins_io_S_en_motor, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) #define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_backlight_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm2_motor_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm3_buzzer_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sx128x_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_st7789v_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_ipc, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc1, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) fn(DT_N_S_pwmleds_S_backlight, __VA_ARGS__) fn(DT_N_S_pwmleds_S_motor, __VA_ARGS__) fn(DT_N_S_pwmleds_S_buzzer, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_app_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20070000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__) fn(DT_N_S_mipi_dbi_st7789v, __VA_ARGS__) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, __VA_ARGS__) fn(DT_N_S_pins_io, __VA_ARGS__) fn(DT_N_S_pins_io_S_key1, __VA_ARGS__) fn(DT_N_S_pins_io_S_en_motor, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) #define DT_COMPAT_fixed_partitions_LABEL_mcuboot DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0 #define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_image_0 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000 #define DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000 #define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_image_1 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000 #define DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000 #define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_tfm_ps DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000 #define DT_COMPAT_fixed_partitions_LABEL_tfm_ps_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_tfm_its DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f4000 #define DT_COMPAT_fixed_partitions_LABEL_tfm_its_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_tfm_otp DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f6000 #define DT_COMPAT_fixed_partitions_LABEL_tfm_otp_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_storage DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f8000 #define DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS 1 /* * Macros for compatibles with status "okay" nodes */ #define DT_COMPAT_HAS_OKAY_nordic_nrf5340_dk_nrf5340_cpuapp 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpuapp_qkaa 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpuapp 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf53 1 #define DT_COMPAT_HAS_OKAY_simple_bus 1 #define DT_COMPAT_HAS_OKAY_arm_v8m_nvic 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_ficr 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_uicr 1 #define DT_COMPAT_HAS_OKAY_mmio_sram 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_dcnf 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf53_oscillators 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf53_hfxo 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf53x_regulators 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf5x_regulator 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf53x_regulator_hv 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_clock 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_power 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_gpregret 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_reset 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_ctrlapperi 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_spim 1 #define DT_COMPAT_HAS_OKAY_semtech_sx1262 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_twim 1 #define DT_COMPAT_HAS_OKAY_microcrystal_rv_8263_c8 1 #define DT_COMPAT_HAS_OKAY_i2c_device 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_uarte 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_saadc 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_rtc 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_dppic 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_wdt 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_egu 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_pwm 1 #define DT_COMPAT_HAS_OKAY_nordic_mbox_nrf_ipc 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_ipc 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_qspi 1 #define DT_COMPAT_HAS_OKAY_nordic_qspi_nor 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_mutex 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_usbreg 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf53_flash_controller 1 #define DT_COMPAT_HAS_OKAY_soc_nv_flash 1 #define DT_COMPAT_HAS_OKAY_fixed_partitions 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_kmu 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_vmc 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_ieee802154 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_spu 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote 1 #define DT_COMPAT_HAS_OKAY_nordic_cryptocell 1 #define DT_COMPAT_HAS_OKAY_arm_cryptocell_312 1 #define DT_COMPAT_HAS_OKAY_nordic_nrf_pinctrl 1 #define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_entropy 1 #define DT_COMPAT_HAS_OKAY_arm_cortex_m33f 1 #define DT_COMPAT_HAS_OKAY_arm_armv8m_itm 1 #define DT_COMPAT_HAS_OKAY_arm_armv8m_mpu 1 #define DT_COMPAT_HAS_OKAY_zephyr_ipc_openamp_static_vrings 1 #define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_ipc 1 #define DT_COMPAT_HAS_OKAY_gpio_leds 1 #define DT_COMPAT_HAS_OKAY_gpio_keys 1 #define DT_COMPAT_HAS_OKAY_pwm_leds 1 #define DT_COMPAT_HAS_OKAY_zephyr_mipi_dbi_spi 1 #define DT_COMPAT_HAS_OKAY_sitronix_st7789v 1 /* * Macros for status "okay" instances of each compatible */ #define DT_N_INST_nordic_nrf5340_dk_nrf5340_cpuapp_NUM_OKAY 1 #define DT_N_INST_nordic_nrf5340_cpuapp_qkaa_NUM_OKAY 1 #define DT_N_INST_nordic_nrf5340_cpuapp_NUM_OKAY 1 #define DT_N_INST_nordic_nrf53_NUM_OKAY 1 #define DT_N_INST_simple_bus_NUM_OKAY 1 #define DT_N_INST_arm_v8m_nvic_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_ficr_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_uicr_NUM_OKAY 1 #define DT_N_INST_mmio_sram_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_dcnf_NUM_OKAY 1 #define DT_N_INST_nordic_nrf53_oscillators_NUM_OKAY 1 #define DT_N_INST_nordic_nrf53_hfxo_NUM_OKAY 1 #define DT_N_INST_nordic_nrf53x_regulators_NUM_OKAY 1 #define DT_N_INST_nordic_nrf5x_regulator_NUM_OKAY 2 #define DT_N_INST_nordic_nrf53x_regulator_hv_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_clock_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_power_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_gpregret_NUM_OKAY 2 #define DT_N_INST_nordic_nrf_reset_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_ctrlapperi_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_spim_NUM_OKAY 2 #define DT_N_INST_semtech_sx1262_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_twim_NUM_OKAY 1 #define DT_N_INST_microcrystal_rv_8263_c8_NUM_OKAY 1 #define DT_N_INST_i2c_device_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_uarte_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_saadc_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_rtc_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_dppic_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_wdt_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_egu_NUM_OKAY 6 #define DT_N_INST_nordic_nrf_pwm_NUM_OKAY 3 #define DT_N_INST_nordic_mbox_nrf_ipc_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_ipc_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_qspi_NUM_OKAY 1 #define DT_N_INST_nordic_qspi_nor_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_mutex_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_usbreg_NUM_OKAY 1 #define DT_N_INST_nordic_nrf53_flash_controller_NUM_OKAY 1 #define DT_N_INST_soc_nv_flash_NUM_OKAY 1 #define DT_N_INST_fixed_partitions_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_kmu_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_vmc_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_gpio_NUM_OKAY 2 #define DT_N_INST_nordic_nrf_ieee802154_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_spu_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY 1 #define DT_N_INST_nordic_cryptocell_NUM_OKAY 1 #define DT_N_INST_arm_cryptocell_312_NUM_OKAY 1 #define DT_N_INST_nordic_nrf_pinctrl_NUM_OKAY 1 #define DT_N_INST_zephyr_bt_hci_entropy_NUM_OKAY 1 #define DT_N_INST_arm_cortex_m33f_NUM_OKAY 1 #define DT_N_INST_arm_armv8m_itm_NUM_OKAY 1 #define DT_N_INST_arm_armv8m_mpu_NUM_OKAY 1 #define DT_N_INST_zephyr_ipc_openamp_static_vrings_NUM_OKAY 2 #define DT_N_INST_zephyr_bt_hci_ipc_NUM_OKAY 1 #define DT_N_INST_gpio_leds_NUM_OKAY 1 #define DT_N_INST_gpio_keys_NUM_OKAY 2 #define DT_N_INST_pwm_leds_NUM_OKAY 1 #define DT_N_INST_zephyr_mipi_dbi_spi_NUM_OKAY 1 #define DT_N_INST_sitronix_st7789v_NUM_OKAY 1 #define DT_FOREACH_OKAY_nordic_nrf5340_dk_nrf5340_cpuapp(fn) fn(DT_N) #define DT_FOREACH_OKAY_VARGS_nordic_nrf5340_dk_nrf5340_cpuapp(fn, ...) fn(DT_N, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf5340_dk_nrf5340_cpuapp(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf5340_dk_nrf5340_cpuapp(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf5340_cpuapp_qkaa(fn) fn(DT_N_S_soc) #define DT_FOREACH_OKAY_VARGS_nordic_nrf5340_cpuapp_qkaa(fn, ...) fn(DT_N_S_soc, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpuapp_qkaa(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf5340_cpuapp_qkaa(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf5340_cpuapp(fn) fn(DT_N_S_soc) #define DT_FOREACH_OKAY_VARGS_nordic_nrf5340_cpuapp(fn, ...) fn(DT_N_S_soc, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpuapp(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf5340_cpuapp(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf53(fn) fn(DT_N_S_soc) #define DT_FOREACH_OKAY_VARGS_nordic_nrf53(fn, ...) fn(DT_N_S_soc, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf53(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf53(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_simple_bus(fn) fn(DT_N_S_soc) #define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...) fn(DT_N_S_soc, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_arm_v8m_nvic(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) #define DT_FOREACH_OKAY_VARGS_arm_v8m_nvic(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arm_v8m_nvic(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_arm_v8m_nvic(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_ficr(fn) fn(DT_N_S_soc_S_ficr_ff0000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_ficr(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_ficr(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ficr(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_uicr(fn) fn(DT_N_S_soc_S_uicr_ff8000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_uicr(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_uicr(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uicr(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_mmio_sram(fn) fn(DT_N_S_soc_S_memory_20000000) #define DT_FOREACH_OKAY_VARGS_mmio_sram(fn, ...) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_mmio_sram(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_dcnf(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_dcnf(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_dcnf(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_dcnf(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf53_oscillators(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf53_oscillators(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf53_oscillators(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf53_oscillators(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf53_hfxo(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo) #define DT_FOREACH_OKAY_VARGS_nordic_nrf53_hfxo(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_controller_4000_S_hfxo, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf53_hfxo(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf53_hfxo(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf53x_regulators(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf53x_regulators(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf53x_regulators(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf53x_regulators(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf5x_regulator(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904) #define DT_FOREACH_OKAY_VARGS_nordic_nrf5x_regulator(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf5x_regulator(fn) fn(0) fn(1) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf5x_regulator(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf53x_regulator_hv(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00) #define DT_FOREACH_OKAY_VARGS_nordic_nrf53x_regulator_hv(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf53x_regulator_hv(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf53x_regulator_hv(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_clock(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_clock(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_clock(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_clock(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_power(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_power(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_power(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_power(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_gpregret(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpregret(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_gpregret(fn) fn(0) fn(1) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpregret(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_reset(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_reset(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_reset(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_reset(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_ctrlapperi(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_ctrlapperi(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_ctrlapperi(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ctrlapperi(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_spim(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_spim(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_spim(fn) fn(0) fn(1) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spim(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) #define DT_FOREACH_OKAY_semtech_sx1262(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0) #define DT_FOREACH_OKAY_VARGS_semtech_sx1262(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000_S_sx1280_0, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_semtech_sx1262(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_semtech_sx1262(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_twim(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_twim(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_twim(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_twim(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_microcrystal_rv_8263_c8(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51) #define DT_FOREACH_OKAY_VARGS_microcrystal_rv_8263_c8(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_rv_8263_c8_51, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_microcrystal_rv_8263_c8(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_microcrystal_rv_8263_c8(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_i2c_device(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68) #define DT_FOREACH_OKAY_VARGS_i2c_device(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_S_bmi270_68, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_i2c_device(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_i2c_device(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_uarte(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_uarte(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_uarte(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uarte(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_saadc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_saadc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_saadc(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_saadc(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_rtc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_rtc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_rtc(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_rtc(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_dppic(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_dppic(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_dppic(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_dppic(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_wdt(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_wdt(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_wdt(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_wdt(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_egu(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_egu(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_egu(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_egu(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_pwm(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_pwm(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_pwm(fn) fn(0) fn(1) fn(2) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pwm(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_mbox_nrf_ipc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) #define DT_FOREACH_OKAY_VARGS_nordic_mbox_nrf_ipc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_mbox_nrf_ipc(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_mbox_nrf_ipc(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_ipc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_ipc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_ipc(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ipc(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_qspi(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_qspi(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_qspi(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_qspi(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_qspi_nor(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0) #define DT_FOREACH_OKAY_VARGS_nordic_qspi_nor(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_S_mx25r8035f_0, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_qspi_nor(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_qspi_nor(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_mutex(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_mutex(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_mutex(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_mutex(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_usbreg(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_usbreg(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_usbreg(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_usbreg(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf53_flash_controller(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf53_flash_controller(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf53_flash_controller(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf53_flash_controller(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_soc_nv_flash(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) #define DT_FOREACH_OKAY_VARGS_soc_nv_flash(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_fixed_partitions(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) #define DT_FOREACH_OKAY_VARGS_fixed_partitions(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_fixed_partitions(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_fixed_partitions(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_kmu(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_kmu(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_kmu(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_kmu(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_vmc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_vmc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_vmc(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_vmc(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_gpio(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpio(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_gpio(fn) fn(0) fn(1) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpio(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_ieee802154(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_ieee802154(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_ieee802154(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ieee802154(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_spu(fn) fn(DT_N_S_soc_S_spu_50003000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_spu(fn, ...) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_spu(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spu(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_gpiote(fn) fn(DT_N_S_soc_S_gpiote_5000d000) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpiote(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpiote(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_cryptocell(fn) fn(DT_N_S_soc_S_crypto_50844000) #define DT_FOREACH_OKAY_VARGS_nordic_cryptocell(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_cryptocell(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_cryptocell(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_arm_cryptocell_312(fn) fn(DT_N_S_soc_S_crypto_50844000) #define DT_FOREACH_OKAY_VARGS_arm_cryptocell_312(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arm_cryptocell_312(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_arm_cryptocell_312(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_nordic_nrf_pinctrl(fn) fn(DT_N_S_pin_controller) #define DT_FOREACH_OKAY_VARGS_nordic_nrf_pinctrl(fn, ...) fn(DT_N_S_pin_controller, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_nordic_nrf_pinctrl(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pinctrl(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_zephyr_bt_hci_entropy(fn) fn(DT_N_S_entropy_bt_hci) #define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_zephyr_bt_hci_entropy(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_arm_cortex_m33f(fn) fn(DT_N_S_cpus_S_cpu_0) #define DT_FOREACH_OKAY_VARGS_arm_cortex_m33f(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arm_cortex_m33f(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m33f(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_arm_armv8m_itm(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) #define DT_FOREACH_OKAY_VARGS_arm_armv8m_itm(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arm_armv8m_itm(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_itm(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_arm_armv8m_mpu(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) #define DT_FOREACH_OKAY_VARGS_arm_armv8m_mpu(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arm_armv8m_mpu(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_mpu(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_zephyr_ipc_openamp_static_vrings(fn) fn(DT_N_S_ipc_S_ipc0) fn(DT_N_S_ipc_S_ipc1) #define DT_FOREACH_OKAY_VARGS_zephyr_ipc_openamp_static_vrings(fn, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc1, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_zephyr_ipc_openamp_static_vrings(fn) fn(0) fn(1) #define DT_FOREACH_OKAY_INST_VARGS_zephyr_ipc_openamp_static_vrings(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) #define DT_FOREACH_OKAY_zephyr_bt_hci_ipc(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0) #define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_ipc(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_zephyr_bt_hci_ipc(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_ipc(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_gpio_leds(fn) fn(DT_N_S_leds) #define DT_FOREACH_OKAY_VARGS_gpio_leds(fn, ...) fn(DT_N_S_leds, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_gpio_leds(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_gpio_keys(fn) fn(DT_N_S_buttons) fn(DT_N_S_pins_io) #define DT_FOREACH_OKAY_VARGS_gpio_keys(fn, ...) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_pins_io, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_gpio_keys(fn) fn(0) fn(1) #define DT_FOREACH_OKAY_INST_VARGS_gpio_keys(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) #define DT_FOREACH_OKAY_pwm_leds(fn) fn(DT_N_S_pwmleds) #define DT_FOREACH_OKAY_VARGS_pwm_leds(fn, ...) fn(DT_N_S_pwmleds, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_pwm_leds(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_pwm_leds(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_zephyr_mipi_dbi_spi(fn) fn(DT_N_S_mipi_dbi_st7789v) #define DT_FOREACH_OKAY_VARGS_zephyr_mipi_dbi_spi(fn, ...) fn(DT_N_S_mipi_dbi_st7789v, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_zephyr_mipi_dbi_spi(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_zephyr_mipi_dbi_spi(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_sitronix_st7789v(fn) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0) #define DT_FOREACH_OKAY_VARGS_sitronix_st7789v(fn, ...) fn(DT_N_S_mipi_dbi_st7789v_S_st7789v_0, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_sitronix_st7789v(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_sitronix_st7789v(fn, ...) fn(0, __VA_ARGS__) /* * Bus information for status "okay" nodes of each compatible */ #define DT_COMPAT_semtech_sx1262_BUS_spi 1 #define DT_COMPAT_microcrystal_rv_8263_c8_BUS_i2c 1 #define DT_COMPAT_i2c_device_BUS_i2c 1 #define DT_COMPAT_nordic_qspi_nor_BUS_qspi 1 #define DT_COMPAT_sitronix_st7789v_BUS_mipi_dbi 1