
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_table>:
	return cb(str, strl, ctx);
}

int cbvprintf_package(void *packaged, size_t len, uint32_t flags,
		      const char *fmt, va_list ap)
{
   0:	40 16 00 20 75 15 00 00 c9 43 00 00 49 15 00 00     @.. u....C..I...
	bool rws_pos_en = !!(flags & CBPRINTF_PACKAGE_ADD_RW_STR_POS);
	/* Get number of first read only strings present in the string.
	 * There is always at least 1 (fmt) but flags can indicate more, e.g
	 * fixed prefix appended to all strings.
	 */
	int fros_cnt = 1 + Z_CBPRINTF_PACKAGE_FIRST_RO_STR_CNT_GET(flags);
  10:	49 15 00 00 49 15 00 00 49 15 00 00 00 00 00 00     I...I...I.......
	...

	/*
	 * Otherwise we must ensure we can store at least
	 * the pointer to the format string itself.
	 */
	if (buf0 != NULL && BUF_OFFSET + sizeof(char *) > len) {
  2c:	b1 11 00 00 49 15 00 00 00 00 00 00 5d 11 00 00     ....I.......]...
		buf += len % CBPRINTF_PACKAGE_ALIGNMENT;
  3c:	49 15 00 00                                         I...

00000040 <_irq_vector_table>:
		len = CBPRINTF_PACKAGE_ALIGNMENT - (len % CBPRINTF_PACKAGE_ALIGNMENT);
  40:	61 12 00 00 61 12 00 00 61 12 00 00 61 12 00 00     a...a...a...a...
	int arg_idx	      = -1; /* Argument index. Preincremented thus starting from -1.*/
  50:	61 12 00 00 61 12 00 00 61 12 00 00 61 12 00 00     a...a...a...a...

		/* copy va_list data over to our buffer */
		if (is_str_arg) {
			s = va_arg(ap, char *);
process_string:
			if (buf0 != NULL) {
  60:	61 12 00 00 61 12 00 00 61 12 00 00 61 12 00 00     a...a...a...a...
#else
	#define RO_START 0
	#define RO_END 0
#endif

	return (((const char *)addr >= (const char *)RO_START) &&
  70:	61 12 00 00 61 12 00 00 61 12 00 00 61 12 00 00     a...a...a...a...
			bool do_ro = !!(flags & CBPRINTF_PACKAGE_ADD_RO_STR_POS);

			if (is_ro && !do_ro) {
				/* nothing to do */
			} else {
				uint32_t s_ptr_idx = BUF_OFFSET / sizeof(int);
  80:	61 12 00 00 61 12 00 00 61 12 00 00 61 12 00 00     a...a...a...a...
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
					__ASSERT(false, "String with too many arguments");
					return -EINVAL;
				}

				if (s_idx >= ARRAY_SIZE(str_ptr_pos)) {
  90:	61 12 00 00 61 12 00 00 61 12 00 00 61 12 00 00     a...a...a...a...
				if (buf0 != NULL) {
					/*
					 * Remember string pointer location.
					 * We will append non-ro strings later.
					 */
					str_ptr_pos[s_idx] = s_ptr_idx;
  a0:	61 12 00 00 61 12 00 00 61 12 00 00 61 12 00 00     a...a...a...a...
					if (is_ro) {
						/* flag read-only string. */
						str_ptr_pos[s_idx] |= STR_POS_RO_FLAG;
						s_ro_cnt++;
					} else {
						s_rw_cnt++;
  b0:	61 12 00 00 61 12 00 00 61 12 00 00 61 12 00 00     a...a...a...a...
			switch (*fmt) {
  c0:	61 12 00 00 61 12 00 00 61 12 00 00 61 12 00 00     a...a...a...a...
  d0:	61 12 00 00 61 12 00 00 61 12 00 00                 a...a...a...

Disassembly of section text:

000000dc <__aeabi_uldivmod>:
      dc:	b953      	cbnz	r3, f4 <__aeabi_uldivmod+0x18>
      de:	b94a      	cbnz	r2, f4 <__aeabi_uldivmod+0x18>
      e0:	2900      	cmp	r1, #0
      e2:	bf08      	it	eq
      e4:	2800      	cmpeq	r0, #0
      e6:	bf1c      	itt	ne
      e8:	f04f 31ff 	movne.w	r1, #4294967295
      ec:	f04f 30ff 	movne.w	r0, #4294967295
      f0:	f000 b80c 	b.w	10c <__aeabi_idiv0>
      f4:	f1ad 0c08 	sub.w	ip, sp, #8
      f8:	e96d ce04 	strd	ip, lr, [sp, #-16]!
      fc:	f000 f808 	bl	110 <__udivmoddi4>
     100:	f8dd e004 	ldr.w	lr, [sp, #4]
     104:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     108:	b004      	add	sp, #16
     10a:	4770      	bx	lr

0000010c <__aeabi_idiv0>:
     10c:	4770      	bx	lr
     10e:	bf00      	nop

00000110 <__udivmoddi4>:
     110:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     114:	4686      	mov	lr, r0
     116:	468c      	mov	ip, r1
     118:	4608      	mov	r0, r1
     11a:	9e08      	ldr	r6, [sp, #32]
     11c:	4615      	mov	r5, r2
				align = VA_STACK_ALIGN(void *);
     11e:	4674      	mov	r4, lr
     120:	4619      	mov	r1, r3
     122:	2b00      	cmp	r3, #0
			switch (*fmt) {
     124:	f040 80c2 	bne.w	2ac <CONFIG_FLASH_SIZE+0xac>
     128:	4285      	cmp	r5, r0
     12a:	fab2 f282 	clz	r2, r2
     12e:	d945      	bls.n	1bc <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x4f>
     130:	b14a      	cbz	r2, 146 <CONFIG_IDLE_STACK_SIZE+0x6>
     132:	f1c2 0320 	rsb	r3, r2, #32
     136:	fa00 fc02 	lsl.w	ip, r0, r2
     13a:	fa2e f303 	lsr.w	r3, lr, r3
     13e:	4095      	lsls	r5, r2
     140:	ea43 0c0c 	orr.w	ip, r3, ip
		buf = (void *) ROUND_UP(buf, align);
     144:	4094      	lsls	r4, r2
     146:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     14a:	b2a8      	uxth	r0, r5
     14c:	fbbc f8fe 	udiv	r8, ip, lr
		if (buf0 != NULL && BUF_OFFSET + size > len) {
     150:	0c23      	lsrs	r3, r4, #16
     152:	fb0e cc18 	mls	ip, lr, r8, ip
     156:	fb08 f900 	mul.w	r9, r8, r0
     15a:	ea43 430c 	orr.w	r3, r3, ip, lsl #16
     15e:	4599      	cmp	r9, r3
		if (is_str_arg) {
     160:	d928      	bls.n	1b4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x47>
     162:	18eb      	adds	r3, r5, r3
				s_idx++;
			}
			buf += sizeof(char *);

			is_str_arg = false;
		} else if (size == sizeof(int)) {
     164:	f108 37ff 	add.w	r7, r8, #4294967295
			int v = va_arg(ap, int);
     168:	d204      	bcs.n	174 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x7>
     16a:	4599      	cmp	r9, r3

			if (buf0 != NULL) {
				*(int *)buf = v;
     16c:	d902      	bls.n	174 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x7>
			}
			buf += sizeof(int);
     16e:	f1a8 0702 	sub.w	r7, r8, #2
     172:	442b      	add	r3, r5
				arg_idx--;
     174:	eba3 0309 	sub.w	r3, r3, r9
     178:	b2a4      	uxth	r4, r4
				parsing = false;
     17a:	fbb3 fcfe 	udiv	ip, r3, lr
				continue;
     17e:	fb0e 331c 	mls	r3, lr, ip, r3
				if (fmt[-1] == 'l') {
     182:	fb0c f000 	mul.w	r0, ip, r0
     186:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
					if (fmt[-2] == 'l') {
     18a:	42a0      	cmp	r0, r4
     18c:	d914      	bls.n	1b8 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x4b>
     18e:	192c      	adds	r4, r5, r4
				parsing = false;
     190:	f10c 33ff 	add.w	r3, ip, #4294967295
						align = VA_STACK_ALIGN(long long);
     194:	d204      	bcs.n	1a0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x33>
     196:	42a0      	cmp	r0, r4
				size = sizeof(void *);
     198:	d902      	bls.n	1a0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x33>
     19a:	f1ac 0302 	sub.w	r3, ip, #2
					v.ld = va_arg(ap, long double);
     19e:	442c      	add	r4, r5
     1a0:	1a24      	subs	r4, r4, r0
     1a2:	ea43 4007 	orr.w	r0, r3, r7, lsl #16
     1a6:	b11e      	cbz	r6, 1b0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x43>
     1a8:	40d4      	lsrs	r4, r2
				buf = (void *) ROUND_UP(buf, align);
     1aa:	2300      	movs	r3, #0
     1ac:	6034      	str	r4, [r6, #0]
				if (buf0 != NULL) {
     1ae:	6073      	str	r3, [r6, #4]
					if (BUF_OFFSET + size > len) {
     1b0:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     1b4:	4647      	mov	r7, r8
     1b6:	e7dd      	b.n	174 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x7>
     1b8:	4663      	mov	r3, ip
						*(long double *)buf = v.ld;
     1ba:	e7f1      	b.n	1a0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x33>
     1bc:	bb92      	cbnz	r2, 224 <CONFIG_FLASH_SIZE+0x24>
				buf += size;
     1be:	1b43      	subs	r3, r0, r5
				parsing = false;
     1c0:	2101      	movs	r1, #1
     1c2:	ea4f 4e15 	mov.w	lr, r5, lsr #16
			switch (*fmt) {
     1c6:	b2af      	uxth	r7, r5
     1c8:	fbb3 fcfe 	udiv	ip, r3, lr
			if (*++fmt == '\0') {
     1cc:	0c20      	lsrs	r0, r4, #16
     1ce:	fb0e 331c 	mls	r3, lr, ip, r3
			if (!parsing) {
     1d2:	fb0c f807 	mul.w	r8, ip, r7
     1d6:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
				if (*fmt == '%') {
     1da:	4598      	cmp	r8, r3
     1dc:	d962      	bls.n	2a4 <CONFIG_FLASH_SIZE+0xa4>
					arg_idx++;
     1de:	18eb      	adds	r3, r5, r3
     1e0:	f10c 30ff 	add.w	r0, ip, #4294967295
					parsing = true;
     1e4:	d204      	bcs.n	1f0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x83>
     1e6:	4598      	cmp	r8, r3
				align = VA_STACK_ALIGN(size_t);
     1e8:	d902      	bls.n	1f0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x83>
     1ea:	f1ac 0002 	sub.w	r0, ip, #2
			switch (*fmt) {
     1ee:	442b      	add	r3, r5
     1f0:	eba3 0308 	sub.w	r3, r3, r8
				parsing = false;
     1f4:	b2a4      	uxth	r4, r4
     1f6:	fbb3 fcfe 	udiv	ip, r3, lr

			if (buf0 != NULL) {
				*(long *)buf = v;
			}
			buf += sizeof(long);
		} else if (size == sizeof(long long)) {
     1fa:	fb0e 331c 	mls	r3, lr, ip, r3
					return -EINVAL;
     1fe:	fb0c f707 	mul.w	r7, ip, r7
			long long v = va_arg(ap, long long);
     202:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     206:	42a7      	cmp	r7, r4
     208:	d94e      	bls.n	2a8 <CONFIG_FLASH_SIZE+0xa8>
     20a:	192c      	adds	r4, r5, r4
     20c:	f10c 33ff 	add.w	r3, ip, #4294967295

			if (buf0 != NULL) {
				if (Z_CBPRINTF_VA_STACK_LL_DBL_MEMCPY) {
					memcpy(buf, &v, sizeof(long long));
				} else {
					*(long long *)buf = v;
     210:	d204      	bcs.n	21c <CONFIG_FLASH_SIZE+0x1c>
				}
			}
			buf += sizeof(long long);
     212:	42a7      	cmp	r7, r4
     214:	d902      	bls.n	21c <CONFIG_FLASH_SIZE+0x1c>
     216:	f1ac 0302 	sub.w	r3, ip, #2
		} else if (size == sizeof(int)) {
     21a:	442c      	add	r4, r5
     21c:	1be4      	subs	r4, r4, r7
			int v = va_arg(ap, int);
     21e:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
			if (buf0 != NULL) {
     222:	e7c0      	b.n	1a6 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x39>
		} else if (size == sizeof(long long)) {
     224:	f1c2 0320 	rsb	r3, r2, #32
			long long v = va_arg(ap, long long);
     228:	fa20 f103 	lsr.w	r1, r0, r3
     22c:	4095      	lsls	r5, r2
     22e:	4090      	lsls	r0, r2
     230:	fa2e f303 	lsr.w	r3, lr, r3
			if (buf0 != NULL) {
     234:	4303      	orrs	r3, r0
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     236:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     23a:	b2af      	uxth	r7, r5
			s = va_arg(ap, char *);
     23c:	fbb1 fcfe 	udiv	ip, r1, lr
     240:	fb0e 101c 	mls	r0, lr, ip, r1
			if (is_ro && !do_ro) {
     244:	0c19      	lsrs	r1, r3, #16
     246:	fb0c f807 	mul.w	r8, ip, r7
				uint32_t s_ptr_idx = BUF_OFFSET / sizeof(int);
     24a:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
     24e:	4588      	cmp	r8, r1
     250:	fa04 f402 	lsl.w	r4, r4, r2
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     254:	d922      	bls.n	29c <CONFIG_FLASH_SIZE+0x9c>
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
     256:	1869      	adds	r1, r5, r1
     258:	f10c 30ff 	add.w	r0, ip, #4294967295
				if (s_idx >= ARRAY_SIZE(str_ptr_pos)) {
     25c:	d204      	bcs.n	268 <CONFIG_FLASH_SIZE+0x68>
     25e:	4588      	cmp	r8, r1
				if (buf0 != NULL) {
     260:	d902      	bls.n	268 <CONFIG_FLASH_SIZE+0x68>
					str_ptr_pos[s_idx] = s_ptr_idx;
     262:	f1ac 0002 	sub.w	r0, ip, #2
     266:	4429      	add	r1, r5
     268:	eba1 0108 	sub.w	r1, r1, r8
					str_ptr_arg[s_idx] = arg_idx;
     26c:	b29b      	uxth	r3, r3
					str_ptr_pos[s_idx] = s_ptr_idx;
     26e:	fbb1 fcfe 	udiv	ip, r1, lr
					str_ptr_arg[s_idx] = arg_idx;
     272:	fb0e 111c 	mls	r1, lr, ip, r1
					if (is_ro) {
     276:	fb0c f707 	mul.w	r7, ip, r7
     27a:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
						str_ptr_pos[s_idx] |= STR_POS_RO_FLAG;
     27e:	429f      	cmp	r7, r3
     280:	d90e      	bls.n	2a0 <CONFIG_FLASH_SIZE+0xa0>
     282:	18eb      	adds	r3, r5, r3
     284:	f10c 31ff 	add.w	r1, ip, #4294967295
						s_ro_cnt++;
     288:	d204      	bcs.n	294 <CONFIG_FLASH_SIZE+0x94>
				s_idx++;
     28a:	429f      	cmp	r7, r3
					if (BUF_OFFSET + size > len) {
     28c:	d902      	bls.n	294 <CONFIG_FLASH_SIZE+0x94>
     28e:	f1ac 0102 	sub.w	r1, ip, #2
     292:	442b      	add	r3, r5
			switch (*fmt) {
     294:	1bdb      	subs	r3, r3, r7
     296:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     29a:	e792      	b.n	1c2 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x55>
     29c:	4660      	mov	r0, ip
     29e:	e7e3      	b.n	268 <CONFIG_FLASH_SIZE+0x68>
				} else if (is_ro) {
     2a0:	4661      	mov	r1, ip
     2a2:	e7f7      	b.n	294 <CONFIG_FLASH_SIZE+0x94>
     2a4:	4660      	mov	r0, ip
					len += 1;
     2a6:	e7a3      	b.n	1f0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x83>
     2a8:	4663      	mov	r3, ip
				} else if (rws_pos_en) {
     2aa:	e7b7      	b.n	21c <CONFIG_FLASH_SIZE+0x1c>
					len += 2;
     2ac:	4283      	cmp	r3, r0
				} else if (rws_pos_en) {
     2ae:	d906      	bls.n	2be <CONFIG_FLASH_SIZE+0xbe>
     2b0:	b916      	cbnz	r6, 2b8 <CONFIG_FLASH_SIZE+0xb8>
					len += strlen(s) + 1 + 1;
     2b2:	2100      	movs	r1, #0
     2b4:	4608      	mov	r0, r1
     2b6:	e77b      	b.n	1b0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x43>
     2b8:	e9c6 e000 	strd	lr, r0, [r6]
     2bc:	e7f9      	b.n	2b2 <CONFIG_FLASH_SIZE+0xb2>
     2be:	fab3 f783 	clz	r7, r3
     2c2:	b98f      	cbnz	r7, 2e8 <CONFIG_FLASH_SIZE+0xe8>
	 * We remember the size of the argument list as a multiple of
	 * sizeof(int) and limit it to a 8-bit field. That means 1020 bytes
	 * worth of va_list, or about 127 arguments on a 64-bit system
	 * (twice that on 32-bit systems). That ought to be good enough.
	 */
	if (BUF_OFFSET / sizeof(int) > 255) {
     2c4:	4283      	cmp	r3, r0
     2c6:	d301      	bcc.n	2cc <CONFIG_FLASH_SIZE+0xcc>
     2c8:	4572      	cmp	r2, lr
     2ca:	d808      	bhi.n	2de <CONFIG_FLASH_SIZE+0xde>

	/*
	 * If all we wanted was to count required buffer size
	 * then we have it now.
	 */
	if (buf0 == NULL) {
     2cc:	ebbe 0402 	subs.w	r4, lr, r2
		return BUF_OFFSET + len - CBPRINTF_PACKAGE_ALIGNMENT;
     2d0:	eb60 0303 	sbc.w	r3, r0, r3
     2d4:	2001      	movs	r0, #1
     2d6:	469c      	mov	ip, r3
     2d8:	b91e      	cbnz	r6, 2e2 <CONFIG_FLASH_SIZE+0xe2>
     2da:	2100      	movs	r1, #0
     2dc:	e768      	b.n	1b0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x43>
     2de:	4638      	mov	r0, r7
	*(char **)buf0 = NULL;

	/* Record end of argument list. */
	pkg_hdr->desc.len = BUF_OFFSET / sizeof(int);

	if (rws_pos_en) {
     2e0:	e7fa      	b.n	2d8 <CONFIG_FLASH_SIZE+0xd8>
	*(char **)buf0 = NULL;
     2e2:	e9c6 4c00 	strd	r4, ip, [r6]
	pkg_hdr->desc.len = BUF_OFFSET / sizeof(int);
     2e6:	e7f8      	b.n	2da <CONFIG_FLASH_SIZE+0xda>
		/* Strings are appended, update location counter. */
		pkg_hdr->desc.str_cnt = 0;
		pkg_hdr->desc.rw_str_cnt = s_rw_cnt;
     2e8:	f1c7 0c20 	rsb	ip, r7, #32
	if (rws_pos_en) {
     2ec:	40bb      	lsls	r3, r7
		pkg_hdr->desc.rw_str_cnt = s_rw_cnt;
     2ee:	fa22 f40c 	lsr.w	r4, r2, ip
		/* Strings are appended, update append counter. */
		pkg_hdr->desc.str_cnt = s_rw_cnt;
		pkg_hdr->desc.rw_str_cnt = 0;
	}

	pkg_hdr->desc.ro_str_cnt = s_ro_cnt;
     2f2:	431c      	orrs	r4, r3
#ifdef CONFIG_CBPRINTF_PACKAGE_HEADER_STORE_CREATION_FLAGS
	pkg_hdr->desc.pkg_flags = flags;
#endif

	/* Store strings pointer locations of read only strings. */
	if (s_ro_cnt) {
     2f4:	fa2e f10c 	lsr.w	r1, lr, ip
     2f8:	fa20 f30c 	lsr.w	r3, r0, ip
		for (i = 0; i < s_idx; i++) {
     2fc:	40b8      	lsls	r0, r7
			}

			uint8_t pos = str_ptr_pos[i] & STR_POS_MASK;

			/* make sure it fits */
			if (BUF_OFFSET + 1 > len) {
     2fe:	4301      	orrs	r1, r0
     300:	ea4f 4914 	mov.w	r9, r4, lsr #16
		for (i = 0; i < s_idx; i++) {
     304:	fa0e f507 	lsl.w	r5, lr, r7
			/* find the string length including terminating '\0' */
			size = strlen(s) + 1;
		}

		/* make sure it fits */
		if (BUF_OFFSET + 1 + size > len) {
     308:	fbb3 f8f9 	udiv	r8, r3, r9
     30c:	fa1f fe84 	uxth.w	lr, r4
			*buf++ = str_ptr_arg[i];
     310:	fb09 3018 	mls	r0, r9, r8, r3
     314:	0c0b      	lsrs	r3, r1, #16
     316:	fb08 fa0e 	mul.w	sl, r8, lr
	for (i = 0; i < s_idx; i++) {
     31a:	ea43 4300 	orr.w	r3, r3, r0, lsl #16
	/*
	 * TODO: remove pointers for appended strings since they're useless.
	 * TODO: explore leveraging same mechanism to remove alignment padding
	 */

	return BUF_OFFSET;
     31e:	459a      	cmp	sl, r3
		pkg_hdr->desc.str_cnt = s_rw_cnt;
     320:	fa02 f207 	lsl.w	r2, r2, r7
			if (!(str_ptr_pos[i] & STR_POS_RO_FLAG)) {
     324:	d940      	bls.n	3a8 <CONFIG_FLASH_SIZE+0x1a8>
     326:	18e3      	adds	r3, r4, r3
     328:	f108 30ff 	add.w	r0, r8, #4294967295
			if (BUF_OFFSET + 1 > len) {
     32c:	d204      	bcs.n	338 <CONFIG_FLASH_SIZE+0x138>
     32e:	459a      	cmp	sl, r3
     330:	d902      	bls.n	338 <CONFIG_FLASH_SIZE+0x138>
			uint8_t pos = str_ptr_pos[i] & STR_POS_MASK;
     332:	f1a8 0002 	sub.w	r0, r8, #2
			if (BUF_OFFSET + 1 > len) {
     336:	4423      	add	r3, r4
     338:	eba3 030a 	sub.w	r3, r3, sl
			*buf++ = pos;
     33c:	b289      	uxth	r1, r1
		for (i = 0; i < s_idx; i++) {
     33e:	fbb3 f8f9 	udiv	r8, r3, r9
		if (s_ro_cnt && str_ptr_pos[i] & STR_POS_RO_FLAG) {
     342:	fb09 3318 	mls	r3, r9, r8, r3
     346:	fb08 fe0e 	mul.w	lr, r8, lr
     34a:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
     34e:	458e      	cmp	lr, r1
		if (rws_pos_en) {
     350:	d92c      	bls.n	3ac <CONFIG_FLASH_SIZE+0x1ac>
     352:	1861      	adds	r1, r4, r1
			*buf++ = str_ptr_arg[i];
     354:	f108 33ff 	add.w	r3, r8, #4294967295
     358:	d204      	bcs.n	364 <CONFIG_FLASH_SIZE+0x164>
     35a:	458e      	cmp	lr, r1
			size = 0;
     35c:	d902      	bls.n	364 <CONFIG_FLASH_SIZE+0x164>
		if (BUF_OFFSET + 1 + size > len) {
     35e:	f1a8 0302 	sub.w	r3, r8, #2
     362:	4421      	add	r1, r4
     364:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
     368:	fba0 9802 	umull	r9, r8, r0, r2
		*buf++ = str_ptr_pos[i];
     36c:	eba1 010e 	sub.w	r1, r1, lr
     370:	4541      	cmp	r1, r8
		memcpy(buf, s, size);
     372:	46ce      	mov	lr, r9
     374:	4643      	mov	r3, r8
     376:	d302      	bcc.n	37e <CONFIG_FLASH_SIZE+0x17e>
     378:	d106      	bne.n	388 <CONFIG_FLASH_SIZE+0x188>
     37a:	454d      	cmp	r5, r9
		buf += size;
     37c:	d204      	bcs.n	388 <CONFIG_FLASH_SIZE+0x188>
     37e:	ebb9 0e02 	subs.w	lr, r9, r2
	for (i = 0; i < s_idx; i++) {
     382:	eb68 0304 	sbc.w	r3, r8, r4
     386:	3801      	subs	r0, #1
     388:	2e00      	cmp	r6, #0
			s = *(char **)(buf0 + str_ptr_pos[i] * sizeof(int));
     38a:	d0a6      	beq.n	2da <CONFIG_FLASH_SIZE+0xda>
     38c:	ebb5 020e 	subs.w	r2, r5, lr
     390:	eb61 0103 	sbc.w	r1, r1, r3
			*(char **)(buf0 + str_ptr_pos[i] * sizeof(int)) = NULL;
     394:	fa01 fc0c 	lsl.w	ip, r1, ip
     398:	fa22 f307 	lsr.w	r3, r2, r7
			size = strlen(s) + 1;
     39c:	ea4c 0303 	orr.w	r3, ip, r3
     3a0:	40f9      	lsrs	r1, r7
     3a2:	e9c6 3100 	strd	r3, r1, [r6]
		return -EFAULT;
     3a6:	e798      	b.n	2da <CONFIG_FLASH_SIZE+0xda>
     3a8:	4640      	mov	r0, r8
     3aa:	e7c5      	b.n	338 <CONFIG_FLASH_SIZE+0x138>
     3ac:	4643      	mov	r3, r8
     3ae:	e7d9      	b.n	364 <CONFIG_FLASH_SIZE+0x164>

000003b0 <main>:
 * See the sample documentation for information on how to fix this.
 */
static const struct gpio_dt_spec led = GPIO_DT_SPEC_GET(LED0_NODE, gpios);

int main(void)
{
     3b0:	b538      	push	{r3, r4, r5, lr}
 */
__syscall bool device_is_ready(const struct device *dev);

static inline bool z_impl_device_is_ready(const struct device *dev)
{
	return z_device_is_ready(dev);
     3b2:	4c10      	ldr	r4, [pc, #64]	; (3f4 <main+0x44>)
     3b4:	4620      	mov	r0, r4
     3b6:	f004 fb57 	bl	4a68 <z_device_is_ready>
	if (!gpio_is_ready_dt(&led))
     3ba:	b1c8      	cbz	r0, 3f0 <main+0x40>
{
	const struct gpio_driver_api *api =
		(const struct gpio_driver_api *)port->api;
	__unused const struct gpio_driver_config *const cfg =
		(const struct gpio_driver_config *)port->config;
	struct gpio_driver_data *data =
     3bc:	6922      	ldr	r2, [r4, #16]
	const struct gpio_driver_api *api =
     3be:	68a5      	ldr	r5, [r4, #8]

	__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
		 "Unsupported pin");

	if ((flags & GPIO_ACTIVE_LOW) != 0) {
		data->invert |= (gpio_port_pins_t)BIT(pin);
     3c0:	6813      	ldr	r3, [r2, #0]
     3c2:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
     3c6:	6013      	str	r3, [r2, #0]
	} else {
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
	}

	return api->pin_configure(port, pin, flags);
     3c8:	682b      	ldr	r3, [r5, #0]
     3ca:	4a0b      	ldr	r2, [pc, #44]	; (3f8 <main+0x48>)
     3cc:	2118      	movs	r1, #24
     3ce:	4620      	mov	r0, r4
     3d0:	4798      	blx	r3
	{
		return 0;
	}

	int ret = gpio_pin_configure_dt(&led, GPIO_OUTPUT_ACTIVE);
	if (ret < 0)
     3d2:	2800      	cmp	r0, #0
     3d4:	db0c      	blt.n	3f0 <main+0x40>
					       gpio_port_pins_t pins)
{
	const struct gpio_driver_api *api =
		(const struct gpio_driver_api *)port->api;

	return api->port_toggle_bits(port, pins);
     3d6:	f04f 7180 	mov.w	r1, #16777216	; 0x1000000
     3da:	696b      	ldr	r3, [r5, #20]
     3dc:	4620      	mov	r0, r4
     3de:	4798      	blx	r3
		return 0;

	while (1) 
	{
		ret = gpio_pin_toggle_dt(&led);
		if (ret < 0)
     3e0:	2800      	cmp	r0, #0
     3e2:	db05      	blt.n	3f0 <main+0x40>
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm0 = { .val = timeout };
		return (int32_t) arch_syscall_invoke2(parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SLEEP);
	}
#endif
	compiler_barrier();
	return z_impl_k_sleep(timeout);
     3e4:	2100      	movs	r1, #0
     3e6:	f44f 4000 	mov.w	r0, #32768	; 0x8000
     3ea:	f003 fcb3 	bl	3d54 <z_impl_k_sleep>
 * @return Zero if the requested time has elapsed or the number of milliseconds
 * left to sleep, if thread was woken up by \ref k_wakeup call.
 */
static inline int32_t k_msleep(int32_t ms)
{
	return k_sleep(Z_TIMEOUT_MS(ms));
     3ee:	e7f2      	b.n	3d6 <main+0x26>
		
		k_msleep(SLEEP_TIME_MS);
	}
	
	return 0;
}
     3f0:	2000      	movs	r0, #0
     3f2:	bd38      	pop	{r3, r4, r5, pc}
     3f4:	00004cd0 	.word	0x00004cd0
     3f8:	00060001 	.word	0x00060001

000003fc <char_out>:
}

static int char_out(int c, void *ctx_p)
{
	(void) ctx_p;
	return _char_out(c);
     3fc:	4b01      	ldr	r3, [pc, #4]	; (404 <CONFIG_MAIN_STACK_SIZE+0x4>)
     3fe:	681b      	ldr	r3, [r3, #0]
     400:	4718      	bx	r3
     402:	bf00      	nop
     404:	20000000 	.word	0x20000000

00000408 <vprintk>:
}

void vprintk(const char *fmt, va_list ap)
{
     408:	b507      	push	{r0, r1, r2, lr}
     40a:	460b      	mov	r3, r1
int cbvprintf(cbprintf_cb out, void *ctx, const char *format, va_list ap);
#else
static inline
int cbvprintf(cbprintf_cb out, void *ctx, const char *format, va_list ap)
{
	return z_cbvprintf_impl(out, ctx, format, ap, 0);
     40c:	2100      	movs	r1, #0
     40e:	4602      	mov	r2, r0
     410:	9100      	str	r1, [sp, #0]
     412:	4803      	ldr	r0, [pc, #12]	; (420 <vprintk+0x18>)
     414:	f000 f914 	bl	640 <z_cbvprintf_impl>

#ifdef CONFIG_PRINTK_SYNC
		k_spin_unlock(&lock, key);
#endif
	}
}
     418:	b003      	add	sp, #12
     41a:	f85d fb04 	ldr.w	pc, [sp], #4
     41e:	bf00      	nop
     420:	000003fd 	.word	0x000003fd

00000424 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     424:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     428:	8b05      	ldrh	r5, [r0, #24]
{
     42a:	4604      	mov	r4, r0
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     42c:	0728      	lsls	r0, r5, #28
{
     42e:	4690      	mov	r8, r2
	if (processing) {
     430:	d411      	bmi.n	456 <process_event+0x32>

	sys_slist_init(&clients);
	do {
		onoff_transition_fn transit = NULL;

		if (evt == EVT_RECHECK) {
     432:	2902      	cmp	r1, #2
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     434:	f005 0507 	and.w	r5, r5, #7
		if (evt == EVT_RECHECK) {
     438:	f040 80cd 	bne.w	5d6 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xee>
			evt = process_recheck(mgr);
     43c:	4620      	mov	r0, r4
     43e:	f003 fe82 	bl	4146 <process_recheck>
		}

		if (evt == EVT_NOP) {
     442:	b178      	cbz	r0, 464 <process_event+0x40>
			break;
		}

		res = 0;
		if (evt == EVT_COMPLETE) {
     444:	3801      	subs	r0, #1
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     446:	8b21      	ldrh	r1, [r4, #24]
     448:	2804      	cmp	r0, #4
     44a:	d811      	bhi.n	470 <process_event+0x4c>
     44c:	e8df f000 	tbb	[pc, r0]
     450:	856d10c3 	.word	0x856d10c3
     454:	95          	.byte	0x95
     455:	00          	.byte	0x00
		if (evt == EVT_COMPLETE) {
     456:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     458:	bf0c      	ite	eq
     45a:	f045 0510 	orreq.w	r5, r5, #16
			mgr->flags |= ONOFF_FLAG_RECHECK;
     45e:	f045 0520 	orrne.w	r5, r5, #32
     462:	8325      	strh	r5, [r4, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     464:	f388 8811 	msr	BASEPRI, r8
     468:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     46c:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     470:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     474:	45aa      	cmp	sl, r5
     476:	f000 80a6 	beq.w	5c6 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xde>
	 * a memory barrier when used like this, and we don't have a
	 * Zephyr framework for that.
	 */
	atomic_clear(&l->locked);
#endif
	arch_irq_unlock(key.key);
     47a:	2700      	movs	r7, #0
     47c:	46b9      	mov	r9, r7
     47e:	463e      	mov	r6, r7
     480:	68a3      	ldr	r3, [r4, #8]
     482:	2b00      	cmp	r3, #0
     484:	f000 80bd 	beq.w	602 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x11a>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     488:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     48c:	8321      	strh	r1, [r4, #24]
     48e:	f388 8811 	msr	BASEPRI, r8
     492:	f3bf 8f6f 	isb	sy
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     496:	68a1      	ldr	r1, [r4, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     498:	2900      	cmp	r1, #0
     49a:	f000 80bb 	beq.w	614 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x12c>
	return node->next;
     49e:	680d      	ldr	r5, [r1, #0]
     4a0:	2900      	cmp	r1, #0
     4a2:	f000 80b7 	beq.w	614 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x12c>
		mon->callback(mgr, mon, state, res);
     4a6:	f8d1 8004 	ldr.w	r8, [r1, #4]
     4aa:	4633      	mov	r3, r6
     4ac:	4652      	mov	r2, sl
     4ae:	4620      	mov	r0, r4
     4b0:	47c0      	blx	r8
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     4b2:	2d00      	cmp	r5, #0
     4b4:	d076      	beq.n	5a4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xbc>
     4b6:	682b      	ldr	r3, [r5, #0]
     4b8:	4629      	mov	r1, r5
     4ba:	461d      	mov	r5, r3
     4bc:	e7f0      	b.n	4a0 <process_event+0x7c>
     4be:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
     4c2:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
     4c4:	2a01      	cmp	r2, #1
     4c6:	d81b      	bhi.n	500 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x18>
	list->head = NULL;
     4c8:	2200      	movs	r2, #0
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     4ca:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
     4ce:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
     4d0:	6827      	ldr	r7, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     4d2:	b289      	uxth	r1, r1
	list->tail = NULL;
     4d4:	e9c4 2200 	strd	r2, r2, [r4]
		if (state == ONOFF_STATE_TO_ON) {
     4d8:	d109      	bne.n	4ee <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x6>
     4da:	463b      	mov	r3, r7
     4dc:	e003      	b.n	4e6 <process_event+0xc2>
				mgr->refs += 1U;
     4de:	8b62      	ldrh	r2, [r4, #26]
     4e0:	3201      	adds	r2, #1
     4e2:	8362      	strh	r2, [r4, #26]
	return node->next;
     4e4:	681b      	ldr	r3, [r3, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     4e6:	2b00      	cmp	r3, #0
     4e8:	d1f9      	bne.n	4de <process_event+0xba>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     4ea:	f041 0102 	orr.w	r1, r1, #2
	mgr->flags = (state & ONOFF_STATE_MASK)
     4ee:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     4f0:	4620      	mov	r0, r4
     4f2:	f003 fe28 	bl	4146 <process_recheck>
     4f6:	2800      	cmp	r0, #0
     4f8:	d07b      	beq.n	5f2 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x10a>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     4fa:	f041 0120 	orr.w	r1, r1, #32
     4fe:	e077      	b.n	5f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x108>
	} else if (state == ONOFF_STATE_TO_OFF) {
     500:	2b04      	cmp	r3, #4
     502:	d10a      	bne.n	51a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x32>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     504:	f021 0107 	bic.w	r1, r1, #7
     508:	b289      	uxth	r1, r1
	mgr->flags = (state & ONOFF_STATE_MASK)
     50a:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     50c:	4620      	mov	r0, r4
     50e:	f003 fe1a 	bl	4146 <process_recheck>
     512:	b110      	cbz	r0, 51a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x32>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     514:	f041 0120 	orr.w	r1, r1, #32
     518:	8321      	strh	r1, [r4, #24]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     51a:	8b21      	ldrh	r1, [r4, #24]
     51c:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     520:	45aa      	cmp	sl, r5
     522:	d050      	beq.n	5c6 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xde>
     524:	2700      	movs	r7, #0
		onoff_transition_fn transit = NULL;
     526:	46b9      	mov	r9, r7
     528:	e7aa      	b.n	480 <process_event+0x5c>
			transit = mgr->transitions->start;
     52a:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     52c:	f021 0107 	bic.w	r1, r1, #7
     530:	f041 0106 	orr.w	r1, r1, #6
				   && !sys_slist_is_empty(&mgr->monitors);
     534:	2d06      	cmp	r5, #6
			transit = mgr->transitions->start;
     536:	f8d3 9000 	ldr.w	r9, [r3]
	mgr->flags = (state & ONOFF_STATE_MASK)
     53a:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
     53c:	d12d      	bne.n	59a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xb2>
		    || (transit != NULL)) {
     53e:	f1b9 0f00 	cmp.w	r9, #0
     542:	d040      	beq.n	5c6 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xde>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     544:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     548:	8321      	strh	r1, [r4, #24]
     54a:	f388 8811 	msr	BASEPRI, r8
     54e:	f3bf 8f6f 	isb	sy
				transit(mgr, transition_complete);
     552:	493a      	ldr	r1, [pc, #232]	; (63c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x154>)
     554:	4620      	mov	r0, r4
     556:	47c8      	blx	r9
     558:	e029      	b.n	5ae <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc6>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     55a:	f021 0107 	bic.w	r1, r1, #7
			transit = mgr->transitions->stop;
     55e:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     560:	f041 0104 	orr.w	r1, r1, #4
     564:	b289      	uxth	r1, r1
				   && !sys_slist_is_empty(&mgr->monitors);
     566:	2d04      	cmp	r5, #4
			transit = mgr->transitions->stop;
     568:	f8d3 9004 	ldr.w	r9, [r3, #4]
	mgr->flags = (state & ONOFF_STATE_MASK)
     56c:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
     56e:	d0e6      	beq.n	53e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x56>
     570:	2700      	movs	r7, #0
		res = 0;
     572:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     574:	f04f 0a04 	mov.w	sl, #4
     578:	e782      	b.n	480 <process_event+0x5c>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     57a:	f021 0107 	bic.w	r1, r1, #7
			transit = mgr->transitions->reset;
     57e:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     580:	f041 0105 	orr.w	r1, r1, #5
     584:	b289      	uxth	r1, r1
				   && !sys_slist_is_empty(&mgr->monitors);
     586:	2d05      	cmp	r5, #5
			transit = mgr->transitions->reset;
     588:	f8d3 9008 	ldr.w	r9, [r3, #8]
	mgr->flags = (state & ONOFF_STATE_MASK)
     58c:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
     58e:	d0d6      	beq.n	53e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x56>
     590:	2700      	movs	r7, #0
		res = 0;
     592:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     594:	f04f 0a05 	mov.w	sl, #5
     598:	e772      	b.n	480 <process_event+0x5c>
				   && !sys_slist_is_empty(&mgr->monitors);
     59a:	2700      	movs	r7, #0
		res = 0;
     59c:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     59e:	f04f 0a06 	mov.w	sl, #6
     5a2:	e76d      	b.n	480 <process_event+0x5c>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     5a4:	462b      	mov	r3, r5
     5a6:	e787      	b.n	4b8 <process_event+0x94>
			if (transit != NULL) {
     5a8:	f1b9 0f00 	cmp.w	r9, #0
     5ac:	d1d1      	bne.n	552 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x6a>
	__asm__ volatile(
     5ae:	f04f 0320 	mov.w	r3, #32
     5b2:	f3ef 8811 	mrs	r8, BASEPRI
     5b6:	f383 8812 	msr	BASEPRI_MAX, r3
     5ba:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     5be:	8b23      	ldrh	r3, [r4, #24]
     5c0:	f023 0308 	bic.w	r3, r3, #8
     5c4:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     5c6:	8b25      	ldrh	r5, [r4, #24]
     5c8:	06ea      	lsls	r2, r5, #27
     5ca:	d52e      	bpl.n	62a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x142>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     5cc:	f025 0310 	bic.w	r3, r5, #16
     5d0:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
     5d2:	f005 0507 	and.w	r5, r5, #7
			res = mgr->last_res;
     5d6:	6966      	ldr	r6, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     5d8:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
     5da:	2e00      	cmp	r6, #0
     5dc:	f6bf af6f 	bge.w	4be <process_event+0x9a>
	list->head = NULL;
     5e0:	2300      	movs	r3, #0
		*clients = mgr->clients;
     5e2:	6827      	ldr	r7, [r4, #0]
	list->tail = NULL;
     5e4:	e9c4 3300 	strd	r3, r3, [r4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     5e8:	f021 0107 	bic.w	r1, r1, #7
     5ec:	f041 0101 	orr.w	r1, r1, #1
			mgr->flags |= ONOFF_FLAG_RECHECK;
     5f0:	8321      	strh	r1, [r4, #24]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     5f2:	8b21      	ldrh	r1, [r4, #24]
     5f4:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     5f8:	45aa      	cmp	sl, r5
     5fa:	f04f 0900 	mov.w	r9, #0
     5fe:	f47f af3f 	bne.w	480 <process_event+0x5c>
		    || !sys_slist_is_empty(&clients)
     602:	2f00      	cmp	r7, #0
     604:	d09b      	beq.n	53e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x56>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     606:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     60a:	8321      	strh	r1, [r4, #24]
	__asm__ volatile(
     60c:	f388 8811 	msr	BASEPRI, r8
     610:	f3bf 8f6f 	isb	sy
			if (!sys_slist_is_empty(&clients)) {
     614:	2f00      	cmp	r7, #0
     616:	d0c7      	beq.n	5a8 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc0>
	return node->next;
     618:	683d      	ldr	r5, [r7, #0]
		notify_one(mgr, cli, state, res);
     61a:	4639      	mov	r1, r7
     61c:	4633      	mov	r3, r6
     61e:	4652      	mov	r2, sl
     620:	4620      	mov	r0, r4
     622:	f003 fdbc 	bl	419e <notify_one>
	list->head = node;
     626:	462f      	mov	r7, r5
	while (!sys_slist_is_empty(list)) {
     628:	e7f4      	b.n	614 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x12c>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     62a:	06ab      	lsls	r3, r5, #26
     62c:	f57f af1a 	bpl.w	464 <process_event+0x40>
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     630:	f025 0320 	bic.w	r3, r5, #32
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     634:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
     636:	f005 0507 	and.w	r5, r5, #7
		if (evt == EVT_RECHECK) {
     63a:	e6ff      	b.n	43c <process_event+0x18>
     63c:	000041cb 	.word	0x000041cb

00000640 <z_cbvprintf_impl>:
	return (int)count;
}

int z_cbvprintf_impl(cbprintf_cb out, void *ctx, const char *fp,
		     va_list ap, uint32_t flags)
{
     640:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     644:	4681      	mov	r9, r0
     646:	b095      	sub	sp, #84	; 0x54
     648:	468b      	mov	fp, r1
     64a:	4617      	mov	r7, r2
     64c:	461c      	mov	r4, r3
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
     64e:	2500      	movs	r5, #0
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
     650:	7838      	ldrb	r0, [r7, #0]
     652:	b908      	cbnz	r0, 658 <z_cbvprintf_impl+0x18>
			OUTC(' ');
			--width;
		}
	}

	return count;
     654:	4628      	mov	r0, r5
     656:	e358      	b.n	d0a <__z_interrupt_stack_SIZEOF+0x4ca>
			OUTC(*fp++);
     658:	1c7b      	adds	r3, r7, #1
		if (*fp != '%') {
     65a:	2825      	cmp	r0, #37	; 0x25
			OUTC(*fp++);
     65c:	9303      	str	r3, [sp, #12]
		if (*fp != '%') {
     65e:	d006      	beq.n	66e <z_cbvprintf_impl+0x2e>
			OUTC('%');
     660:	4659      	mov	r1, fp
     662:	47c8      	blx	r9
     664:	2800      	cmp	r0, #0
     666:	f2c0 8350 	blt.w	d0a <__z_interrupt_stack_SIZEOF+0x4ca>
     66a:	3501      	adds	r5, #1
		if (bps == NULL) {
     66c:	e1fb      	b.n	a66 <__z_interrupt_stack_SIZEOF+0x226>
		} state = {
     66e:	2218      	movs	r2, #24
     670:	2100      	movs	r1, #0
     672:	a80e      	add	r0, sp, #56	; 0x38
     674:	f003 fed4 	bl	4420 <memset>
	if (*sp == '%') {
     678:	787b      	ldrb	r3, [r7, #1]
     67a:	2b25      	cmp	r3, #37	; 0x25
     67c:	d07d      	beq.n	77a <z_cbvprintf_impl+0x13a>
     67e:	2300      	movs	r3, #0
     680:	1c78      	adds	r0, r7, #1
     682:	4698      	mov	r8, r3
     684:	469e      	mov	lr, r3
     686:	469c      	mov	ip, r3
     688:	461e      	mov	r6, r3
     68a:	4601      	mov	r1, r0
		switch (*sp) {
     68c:	f810 2b01 	ldrb.w	r2, [r0], #1
     690:	2a2b      	cmp	r2, #43	; 0x2b
     692:	f000 80a1 	beq.w	7d8 <z_cbvprintf_impl+0x198>
     696:	f200 8098 	bhi.w	7ca <z_cbvprintf_impl+0x18a>
     69a:	2a20      	cmp	r2, #32
     69c:	f000 809f 	beq.w	7de <z_cbvprintf_impl+0x19e>
     6a0:	2a23      	cmp	r2, #35	; 0x23
     6a2:	f000 809f 	beq.w	7e4 <z_cbvprintf_impl+0x1a4>
     6a6:	b12b      	cbz	r3, 6b4 <z_cbvprintf_impl+0x74>
     6a8:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     6ac:	f043 0340 	orr.w	r3, r3, #64	; 0x40
     6b0:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
     6b4:	f1b8 0f00 	cmp.w	r8, #0
     6b8:	d005      	beq.n	6c6 <z_cbvprintf_impl+0x86>
     6ba:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     6be:	f043 0320 	orr.w	r3, r3, #32
     6c2:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
     6c6:	f1be 0f00 	cmp.w	lr, #0
     6ca:	d005      	beq.n	6d8 <z_cbvprintf_impl+0x98>
     6cc:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     6d0:	f043 0310 	orr.w	r3, r3, #16
     6d4:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
     6d8:	f1bc 0f00 	cmp.w	ip, #0
     6dc:	d005      	beq.n	6ea <z_cbvprintf_impl+0xaa>
     6de:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     6e2:	f043 0308 	orr.w	r3, r3, #8
     6e6:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
     6ea:	b12e      	cbz	r6, 6f8 <z_cbvprintf_impl+0xb8>
     6ec:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     6f0:	f043 0304 	orr.w	r3, r3, #4
     6f4:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
	if (conv->flag_zero && conv->flag_dash) {
     6f8:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     6fc:	f003 0044 	and.w	r0, r3, #68	; 0x44
     700:	2844      	cmp	r0, #68	; 0x44
     702:	d103      	bne.n	70c <z_cbvprintf_impl+0xcc>
		conv->flag_zero = false;
     704:	f36f 1386 	bfc	r3, #6, #1
     708:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
	conv->width_present = true;
     70c:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
	if (*sp == '*') {
     710:	2a2a      	cmp	r2, #42	; 0x2a
	conv->width_present = true;
     712:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     716:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
	if (*sp == '*') {
     71a:	d17f      	bne.n	81c <CONFIG_ISR_STACK_SIZE+0x1c>
		conv->width_star = true;
     71c:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     720:	f042 0201 	orr.w	r2, r2, #1
		return ++sp;
     724:	1c4b      	adds	r3, r1, #1
		conv->width_star = true;
     726:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
	conv->prec_present = (*sp == '.');
     72a:	781a      	ldrb	r2, [r3, #0]
     72c:	2a2e      	cmp	r2, #46	; 0x2e
     72e:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     732:	bf0c      	ite	eq
     734:	2101      	moveq	r1, #1
     736:	2100      	movne	r1, #0
     738:	f361 0241 	bfi	r2, r1, #1, #1
     73c:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
	if (!conv->prec_present) {
     740:	d178      	bne.n	834 <CONFIG_ISR_STACK_SIZE+0x34>
	if (*sp == '*') {
     742:	785a      	ldrb	r2, [r3, #1]
     744:	2a2a      	cmp	r2, #42	; 0x2a
     746:	d06e      	beq.n	826 <CONFIG_ISR_STACK_SIZE+0x26>
	++sp;
     748:	3301      	adds	r3, #1
	size_t val = 0;
     74a:	2200      	movs	r2, #0
		val = 10U * val + *sp++ - '0';
     74c:	f04f 0c0a 	mov.w	ip, #10
			(((unsigned)c) <= (unsigned)'~'));
}

static inline int isdigit(int a)
{
	return (int)(((unsigned)(a)-(unsigned)'0') < 10U);
     750:	4619      	mov	r1, r3
     752:	f811 0b01 	ldrb.w	r0, [r1], #1
     756:	f1a0 0630 	sub.w	r6, r0, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp) != 0) {
     75a:	2e09      	cmp	r6, #9
     75c:	f240 8095 	bls.w	88a <__z_interrupt_stack_SIZEOF+0x4a>
	conv->unsupported |= ((conv->prec_value < 0)
     760:	f89d 1040 	ldrb.w	r1, [sp, #64]	; 0x40
	conv->prec_value = prec;
     764:	9212      	str	r2, [sp, #72]	; 0x48
	conv->unsupported |= ((conv->prec_value < 0)
     766:	f3c1 0040 	ubfx	r0, r1, #1, #1
     76a:	ea40 70d2 	orr.w	r0, r0, r2, lsr #31
     76e:	460a      	mov	r2, r1
     770:	f360 0241 	bfi	r2, r0, #1, #1
     774:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
	return sp;
     778:	e05c      	b.n	834 <CONFIG_ISR_STACK_SIZE+0x34>
		conv->specifier = *sp++;
     77a:	1cba      	adds	r2, r7, #2
     77c:	9203      	str	r2, [sp, #12]
     77e:	f88d 3043 	strb.w	r3, [sp, #67]	; 0x43
		if (conv->width_star) {
     782:	f89d 3041 	ldrb.w	r3, [sp, #65]	; 0x41
     786:	07da      	lsls	r2, r3, #31
     788:	f140 812e 	bpl.w	9e8 <__z_interrupt_stack_SIZEOF+0x1a8>
			width = va_arg(ap, int);
     78c:	f854 8b04 	ldr.w	r8, [r4], #4
			if (width < 0) {
     790:	f1b8 0f00 	cmp.w	r8, #0
     794:	da07      	bge.n	7a6 <z_cbvprintf_impl+0x166>
				conv->flag_dash = true;
     796:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
     79a:	f042 0204 	orr.w	r2, r2, #4
     79e:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
				width = -width;
     7a2:	f1c8 0800 	rsb	r8, r8, #0
		if (conv->prec_star) {
     7a6:	075e      	lsls	r6, r3, #29
     7a8:	f140 8127 	bpl.w	9fa <__z_interrupt_stack_SIZEOF+0x1ba>
			int arg = va_arg(ap, int);
     7ac:	f854 ab04 	ldr.w	sl, [r4], #4
			if (arg < 0) {
     7b0:	f1ba 0f00 	cmp.w	sl, #0
     7b4:	f280 8126 	bge.w	a04 <__z_interrupt_stack_SIZEOF+0x1c4>
				conv->prec_present = false;
     7b8:	f89d 3041 	ldrb.w	r3, [sp, #65]	; 0x41
     7bc:	f36f 0341 	bfc	r3, #1, #1
     7c0:	f88d 3041 	strb.w	r3, [sp, #65]	; 0x41
		int precision = -1;
     7c4:	f04f 3aff 	mov.w	sl, #4294967295
     7c8:	e11c      	b.n	a04 <__z_interrupt_stack_SIZEOF+0x1c4>
		switch (*sp) {
     7ca:	2a2d      	cmp	r2, #45	; 0x2d
     7cc:	d00d      	beq.n	7ea <z_cbvprintf_impl+0x1aa>
     7ce:	2a30      	cmp	r2, #48	; 0x30
     7d0:	f47f af69 	bne.w	6a6 <z_cbvprintf_impl+0x66>
     7d4:	2301      	movs	r3, #1
	} while (loop);
     7d6:	e758      	b.n	68a <z_cbvprintf_impl+0x4a>
		switch (*sp) {
     7d8:	f04f 0c01 	mov.w	ip, #1
     7dc:	e755      	b.n	68a <z_cbvprintf_impl+0x4a>
     7de:	f04f 0e01 	mov.w	lr, #1
     7e2:	e752      	b.n	68a <z_cbvprintf_impl+0x4a>
     7e4:	f04f 0801 	mov.w	r8, #1
     7e8:	e74f      	b.n	68a <z_cbvprintf_impl+0x4a>
     7ea:	2601      	movs	r6, #1
     7ec:	e74d      	b.n	68a <z_cbvprintf_impl+0x4a>
		val = 10U * val + *sp++ - '0';
     7ee:	fb0e 6202 	mla	r2, lr, r2, r6
     7f2:	3a30      	subs	r2, #48	; 0x30
     7f4:	4603      	mov	r3, r0
     7f6:	4618      	mov	r0, r3
     7f8:	f810 6b01 	ldrb.w	r6, [r0], #1
     7fc:	f1a6 0c30 	sub.w	ip, r6, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp) != 0) {
     800:	f1bc 0f09 	cmp.w	ip, #9
     804:	d9f3      	bls.n	7ee <z_cbvprintf_impl+0x1ae>
	if (sp != wp) {
     806:	4299      	cmp	r1, r3
     808:	d08f      	beq.n	72a <z_cbvprintf_impl+0xea>
		conv->unsupported |= ((conv->width_value < 0)
     80a:	f89d 1040 	ldrb.w	r1, [sp, #64]	; 0x40
		conv->width_value = width;
     80e:	9211      	str	r2, [sp, #68]	; 0x44
				      || (width != (size_t)conv->width_value));
     810:	0fd2      	lsrs	r2, r2, #31
		conv->unsupported |= ((conv->width_value < 0)
     812:	f362 0141 	bfi	r1, r2, #1, #1
     816:	f88d 1040 	strb.w	r1, [sp, #64]	; 0x40
     81a:	e786      	b.n	72a <z_cbvprintf_impl+0xea>
     81c:	460b      	mov	r3, r1
	size_t val = 0;
     81e:	2200      	movs	r2, #0
		val = 10U * val + *sp++ - '0';
     820:	f04f 0e0a 	mov.w	lr, #10
     824:	e7e7      	b.n	7f6 <z_cbvprintf_impl+0x1b6>
		conv->prec_star = true;
     826:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     82a:	f042 0204 	orr.w	r2, r2, #4
     82e:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
		return ++sp;
     832:	3302      	adds	r3, #2
	switch (*sp) {
     834:	781a      	ldrb	r2, [r3, #0]
     836:	2a6c      	cmp	r2, #108	; 0x6c
     838:	d047      	beq.n	8ca <__z_interrupt_stack_SIZEOF+0x8a>
     83a:	d82b      	bhi.n	894 <__z_interrupt_stack_SIZEOF+0x54>
     83c:	2a68      	cmp	r2, #104	; 0x68
     83e:	d031      	beq.n	8a4 <__z_interrupt_stack_SIZEOF+0x64>
     840:	2a6a      	cmp	r2, #106	; 0x6a
     842:	d04b      	beq.n	8dc <__z_interrupt_stack_SIZEOF+0x9c>
     844:	2a4c      	cmp	r2, #76	; 0x4c
     846:	d051      	beq.n	8ec <__z_interrupt_stack_SIZEOF+0xac>
	conv->specifier = *sp++;
     848:	461a      	mov	r2, r3
     84a:	f812 3b01 	ldrb.w	r3, [r2], #1
     84e:	9203      	str	r2, [sp, #12]
	switch (conv->specifier) {
     850:	2b78      	cmp	r3, #120	; 0x78
		if (conv->length_mod == LENGTH_UPPER_L) {
     852:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
	conv->specifier = *sp++;
     856:	f88d 3043 	strb.w	r3, [sp, #67]	; 0x43
	switch (conv->specifier) {
     85a:	f200 80be 	bhi.w	9da <__z_interrupt_stack_SIZEOF+0x19a>
     85e:	2b6d      	cmp	r3, #109	; 0x6d
     860:	d851      	bhi.n	906 <__z_interrupt_stack_SIZEOF+0xc6>
     862:	2b69      	cmp	r3, #105	; 0x69
     864:	f200 80b9 	bhi.w	9da <__z_interrupt_stack_SIZEOF+0x19a>
     868:	2b57      	cmp	r3, #87	; 0x57
     86a:	d867      	bhi.n	93c <__z_interrupt_stack_SIZEOF+0xfc>
     86c:	2b41      	cmp	r3, #65	; 0x41
     86e:	d003      	beq.n	878 <__z_interrupt_stack_SIZEOF+0x38>
     870:	3b45      	subs	r3, #69	; 0x45
     872:	2b02      	cmp	r3, #2
     874:	f200 80b1 	bhi.w	9da <__z_interrupt_stack_SIZEOF+0x19a>
		conv->specifier_cat = SPECIFIER_FP;
     878:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     87c:	2204      	movs	r2, #4
     87e:	f362 0302 	bfi	r3, r2, #0, #3
     882:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
			unsupported = true;
     886:	2301      	movs	r3, #1
			break;
     888:	e073      	b.n	972 <__z_interrupt_stack_SIZEOF+0x132>
		val = 10U * val + *sp++ - '0';
     88a:	fb0c 0202 	mla	r2, ip, r2, r0
     88e:	3a30      	subs	r2, #48	; 0x30
     890:	460b      	mov	r3, r1
     892:	e75d      	b.n	750 <z_cbvprintf_impl+0x110>
	switch (*sp) {
     894:	2a74      	cmp	r2, #116	; 0x74
     896:	d025      	beq.n	8e4 <__z_interrupt_stack_SIZEOF+0xa4>
     898:	2a7a      	cmp	r2, #122	; 0x7a
     89a:	d1d5      	bne.n	848 <__z_interrupt_stack_SIZEOF+0x8>
		conv->length_mod = LENGTH_Z;
     89c:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     8a0:	2106      	movs	r1, #6
     8a2:	e00c      	b.n	8be <__z_interrupt_stack_SIZEOF+0x7e>
		if (*++sp == 'h') {
     8a4:	785a      	ldrb	r2, [r3, #1]
     8a6:	2a68      	cmp	r2, #104	; 0x68
     8a8:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     8ac:	d106      	bne.n	8bc <__z_interrupt_stack_SIZEOF+0x7c>
			conv->length_mod = LENGTH_HH;
     8ae:	2101      	movs	r1, #1
			conv->length_mod = LENGTH_LL;
     8b0:	f361 02c6 	bfi	r2, r1, #3, #4
     8b4:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
			++sp;
     8b8:	3302      	adds	r3, #2
     8ba:	e7c5      	b.n	848 <__z_interrupt_stack_SIZEOF+0x8>
			conv->length_mod = LENGTH_H;
     8bc:	2102      	movs	r1, #2
     8be:	f361 02c6 	bfi	r2, r1, #3, #4
     8c2:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
		if (*++sp == 'h') {
     8c6:	3301      	adds	r3, #1
     8c8:	e7be      	b.n	848 <__z_interrupt_stack_SIZEOF+0x8>
		if (*++sp == 'l') {
     8ca:	785a      	ldrb	r2, [r3, #1]
     8cc:	2a6c      	cmp	r2, #108	; 0x6c
     8ce:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     8d2:	d101      	bne.n	8d8 <__z_interrupt_stack_SIZEOF+0x98>
			conv->length_mod = LENGTH_LL;
     8d4:	2104      	movs	r1, #4
     8d6:	e7eb      	b.n	8b0 <__z_interrupt_stack_SIZEOF+0x70>
			conv->length_mod = LENGTH_L;
     8d8:	2103      	movs	r1, #3
     8da:	e7f0      	b.n	8be <__z_interrupt_stack_SIZEOF+0x7e>
		conv->length_mod = LENGTH_J;
     8dc:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     8e0:	2105      	movs	r1, #5
     8e2:	e7ec      	b.n	8be <__z_interrupt_stack_SIZEOF+0x7e>
		conv->length_mod = LENGTH_T;
     8e4:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     8e8:	2107      	movs	r1, #7
     8ea:	e7e8      	b.n	8be <__z_interrupt_stack_SIZEOF+0x7e>
		conv->unsupported = true;
     8ec:	f8bd 2040 	ldrh.w	r2, [sp, #64]	; 0x40
     8f0:	f422 42f0 	bic.w	r2, r2, #30720	; 0x7800
     8f4:	f022 0202 	bic.w	r2, r2, #2
     8f8:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
     8fc:	f042 0202 	orr.w	r2, r2, #2
     900:	f8ad 2040 	strh.w	r2, [sp, #64]	; 0x40
		break;
     904:	e7df      	b.n	8c6 <__z_interrupt_stack_SIZEOF+0x86>
	switch (conv->specifier) {
     906:	3b6e      	subs	r3, #110	; 0x6e
     908:	b2d9      	uxtb	r1, r3
     90a:	2301      	movs	r3, #1
     90c:	408b      	lsls	r3, r1
     90e:	f240 4182 	movw	r1, #1154	; 0x482
     912:	420b      	tst	r3, r1
     914:	d137      	bne.n	986 <__z_interrupt_stack_SIZEOF+0x146>
     916:	f013 0f24 	tst.w	r3, #36	; 0x24
     91a:	d151      	bne.n	9c0 <__z_interrupt_stack_SIZEOF+0x180>
     91c:	07d8      	lsls	r0, r3, #31
     91e:	d55c      	bpl.n	9da <__z_interrupt_stack_SIZEOF+0x19a>
		conv->specifier_cat = SPECIFIER_PTR;
     920:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     924:	2103      	movs	r1, #3
     926:	f361 0302 	bfi	r3, r1, #0, #3
     92a:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
		if (conv->length_mod == LENGTH_UPPER_L) {
     92e:	f002 0378 	and.w	r3, r2, #120	; 0x78
     932:	f1a3 0140 	sub.w	r1, r3, #64	; 0x40
     936:	424b      	negs	r3, r1
     938:	414b      	adcs	r3, r1
     93a:	e01a      	b.n	972 <__z_interrupt_stack_SIZEOF+0x132>
	switch (conv->specifier) {
     93c:	f1a3 0158 	sub.w	r1, r3, #88	; 0x58
     940:	b2c9      	uxtb	r1, r1
     942:	2001      	movs	r0, #1
     944:	fa00 f101 	lsl.w	r1, r0, r1
     948:	f411 4f62 	tst.w	r1, #57856	; 0xe200
     94c:	d194      	bne.n	878 <__z_interrupt_stack_SIZEOF+0x38>
     94e:	f640 0601 	movw	r6, #2049	; 0x801
     952:	4231      	tst	r1, r6
     954:	d11d      	bne.n	992 <__z_interrupt_stack_SIZEOF+0x152>
     956:	f411 3f04 	tst.w	r1, #135168	; 0x21000
     95a:	d03e      	beq.n	9da <__z_interrupt_stack_SIZEOF+0x19a>
		conv->specifier_cat = SPECIFIER_SINT;
     95c:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     960:	f360 0302 	bfi	r3, r0, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     964:	f002 0278 	and.w	r2, r2, #120	; 0x78
     968:	2a40      	cmp	r2, #64	; 0x40
		conv->specifier_cat = SPECIFIER_SINT;
     96a:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
		if (conv->length_mod == LENGTH_UPPER_L) {
     96e:	d034      	beq.n	9da <__z_interrupt_stack_SIZEOF+0x19a>
	bool unsupported = false;
     970:	2300      	movs	r3, #0
	conv->unsupported |= unsupported;
     972:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
     976:	f3c2 0140 	ubfx	r1, r2, #1, #1
     97a:	430b      	orrs	r3, r1
     97c:	f363 0241 	bfi	r2, r3, #1, #1
     980:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
	return sp;
     984:	e6fd      	b.n	782 <z_cbvprintf_impl+0x142>
		conv->specifier_cat = SPECIFIER_UINT;
     986:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     98a:	2102      	movs	r1, #2
     98c:	f361 0302 	bfi	r3, r1, #0, #3
     990:	e7e8      	b.n	964 <__z_interrupt_stack_SIZEOF+0x124>
     992:	f89d 1042 	ldrb.w	r1, [sp, #66]	; 0x42
     996:	2002      	movs	r0, #2
		if (conv->length_mod == LENGTH_UPPER_L) {
     998:	f002 0278 	and.w	r2, r2, #120	; 0x78
		conv->specifier_cat = SPECIFIER_UINT;
     99c:	f360 0102 	bfi	r1, r0, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     9a0:	2a40      	cmp	r2, #64	; 0x40
		conv->specifier_cat = SPECIFIER_UINT;
     9a2:	f88d 1042 	strb.w	r1, [sp, #66]	; 0x42
			conv->invalid = true;
     9a6:	bf02      	ittt	eq
     9a8:	f89d 1040 	ldrbeq.w	r1, [sp, #64]	; 0x40
     9ac:	f041 0101 	orreq.w	r1, r1, #1
     9b0:	f88d 1040 	strbeq.w	r1, [sp, #64]	; 0x40
		if (conv->specifier == 'c') {
     9b4:	2b63      	cmp	r3, #99	; 0x63
     9b6:	d1db      	bne.n	970 <__z_interrupt_stack_SIZEOF+0x130>
			unsupported = (conv->length_mod != LENGTH_NONE);
     9b8:	1e13      	subs	r3, r2, #0
     9ba:	bf18      	it	ne
     9bc:	2301      	movne	r3, #1
     9be:	e7d8      	b.n	972 <__z_interrupt_stack_SIZEOF+0x132>
		conv->specifier_cat = SPECIFIER_PTR;
     9c0:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     9c4:	2103      	movs	r1, #3
     9c6:	f361 0302 	bfi	r3, r1, #0, #3
		if (conv->length_mod != LENGTH_NONE) {
     9ca:	f012 0f78 	tst.w	r2, #120	; 0x78
		conv->specifier_cat = SPECIFIER_PTR;
     9ce:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
		if (conv->length_mod != LENGTH_NONE) {
     9d2:	bf14      	ite	ne
     9d4:	2301      	movne	r3, #1
     9d6:	2300      	moveq	r3, #0
     9d8:	e7cb      	b.n	972 <__z_interrupt_stack_SIZEOF+0x132>
		conv->invalid = true;
     9da:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     9de:	f043 0301 	orr.w	r3, r3, #1
     9e2:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
		break;
     9e6:	e7c3      	b.n	970 <__z_interrupt_stack_SIZEOF+0x130>
		} else if (conv->width_present) {
     9e8:	f99d 2040 	ldrsb.w	r2, [sp, #64]	; 0x40
     9ec:	2a00      	cmp	r2, #0
			width = conv->width_value;
     9ee:	bfb4      	ite	lt
     9f0:	f8dd 8044 	ldrlt.w	r8, [sp, #68]	; 0x44
		int width = -1;
     9f4:	f04f 38ff 	movge.w	r8, #4294967295
     9f8:	e6d5      	b.n	7a6 <z_cbvprintf_impl+0x166>
		} else if (conv->prec_present) {
     9fa:	0798      	lsls	r0, r3, #30
     9fc:	f57f aee2 	bpl.w	7c4 <z_cbvprintf_impl+0x184>
			precision = conv->prec_value;
     a00:	f8dd a048 	ldr.w	sl, [sp, #72]	; 0x48
			= (enum length_mod_enum)conv->length_mod;
     a04:	f89d 1041 	ldrb.w	r1, [sp, #65]	; 0x41
		conv->pad0_value = 0;
     a08:	2300      	movs	r3, #0
		conv->pad0_pre_exp = 0;
     a0a:	e9cd 3311 	strd	r3, r3, [sp, #68]	; 0x44
			= (enum specifier_cat_enum)conv->specifier_cat;
     a0e:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
		enum specifier_cat_enum specifier_cat
     a12:	f003 0307 	and.w	r3, r3, #7
		if (specifier_cat == SPECIFIER_SINT) {
     a16:	2b01      	cmp	r3, #1
			= (enum length_mod_enum)conv->length_mod;
     a18:	f3c1 01c3 	ubfx	r1, r1, #3, #4
		if (specifier_cat == SPECIFIER_SINT) {
     a1c:	d133      	bne.n	a86 <__z_interrupt_stack_SIZEOF+0x246>
			switch (length_mod) {
     a1e:	1ecb      	subs	r3, r1, #3
     a20:	2b04      	cmp	r3, #4
     a22:	d804      	bhi.n	a2e <__z_interrupt_stack_SIZEOF+0x1ee>
     a24:	e8df f003 	tbb	[pc, r3]
     a28:	21464621 	.word	0x21464621
     a2c:	21          	.byte	0x21
     a2d:	00          	.byte	0x00
				value->sint = va_arg(ap, int);
     a2e:	6823      	ldr	r3, [r4, #0]
			if (length_mod == LENGTH_HH) {
     a30:	2901      	cmp	r1, #1
				value->sint = va_arg(ap, int);
     a32:	ea4f 72e3 	mov.w	r2, r3, asr #31
     a36:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
			if (length_mod == LENGTH_HH) {
     a3a:	d11c      	bne.n	a76 <__z_interrupt_stack_SIZEOF+0x236>
				value->sint = (signed char)value->sint;
     a3c:	f99d 3038 	ldrsb.w	r3, [sp, #56]	; 0x38
     a40:	17da      	asrs	r2, r3, #31
     a42:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
				value->sint = va_arg(ap, int);
     a46:	3404      	adds	r4, #4
		if (conv->invalid || conv->unsupported) {
     a48:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     a4c:	f013 0603 	ands.w	r6, r3, #3
     a50:	d050      	beq.n	af4 <__z_interrupt_stack_SIZEOF+0x2b4>
			OUTS(sp, fp);
     a52:	9b03      	ldr	r3, [sp, #12]
     a54:	463a      	mov	r2, r7
     a56:	4659      	mov	r1, fp
     a58:	4648      	mov	r0, r9
     a5a:	f003 fc93 	bl	4384 <outs>
     a5e:	2800      	cmp	r0, #0
     a60:	f2c0 8153 	blt.w	d0a <__z_interrupt_stack_SIZEOF+0x4ca>
     a64:	4405      	add	r5, r0
			continue;
     a66:	9f03      	ldr	r7, [sp, #12]
     a68:	e5f2      	b.n	650 <z_cbvprintf_impl+0x10>
					(sint_value_type)va_arg(ap, ptrdiff_t);
     a6a:	f854 3b04 	ldr.w	r3, [r4], #4
     a6e:	17da      	asrs	r2, r3, #31
				value->uint = (unsigned char)value->uint;
     a70:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
     a74:	e7e8      	b.n	a48 <__z_interrupt_stack_SIZEOF+0x208>
			} else if (length_mod == LENGTH_H) {
     a76:	2902      	cmp	r1, #2
     a78:	d1e5      	bne.n	a46 <__z_interrupt_stack_SIZEOF+0x206>
				value->sint = (short)value->sint;
     a7a:	b21a      	sxth	r2, r3
     a7c:	f343 33c0 	sbfx	r3, r3, #15, #1
     a80:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
     a84:	e7df      	b.n	a46 <__z_interrupt_stack_SIZEOF+0x206>
		} else if (specifier_cat == SPECIFIER_UINT) {
     a86:	2b02      	cmp	r3, #2
     a88:	d124      	bne.n	ad4 <__z_interrupt_stack_SIZEOF+0x294>
			switch (length_mod) {
     a8a:	1ecb      	subs	r3, r1, #3
     a8c:	2b04      	cmp	r3, #4
     a8e:	d804      	bhi.n	a9a <__z_interrupt_stack_SIZEOF+0x25a>
     a90:	e8df f003 	tbb	[pc, r3]
     a94:	18101018 	.word	0x18101018
     a98:	18          	.byte	0x18
     a99:	00          	.byte	0x00
			if (length_mod == LENGTH_HH) {
     a9a:	2901      	cmp	r1, #1
				value->uint = va_arg(ap, unsigned int);
     a9c:	f854 3b04 	ldr.w	r3, [r4], #4
			if (length_mod == LENGTH_HH) {
     aa0:	f04f 0200 	mov.w	r2, #0
     aa4:	d014      	beq.n	ad0 <__z_interrupt_stack_SIZEOF+0x290>
			} else if (length_mod == LENGTH_H) {
     aa6:	2902      	cmp	r1, #2
				value->uint = va_arg(ap, unsigned int);
     aa8:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
			} else if (length_mod == LENGTH_H) {
     aac:	d1cc      	bne.n	a48 <__z_interrupt_stack_SIZEOF+0x208>
				value->uint = (unsigned short)value->uint;
     aae:	b29b      	uxth	r3, r3
			value->ptr = va_arg(ap, void *);
     ab0:	930e      	str	r3, [sp, #56]	; 0x38
     ab2:	e7c9      	b.n	a48 <__z_interrupt_stack_SIZEOF+0x208>
					(uint_value_type)va_arg(ap,
     ab4:	3407      	adds	r4, #7
     ab6:	f024 0407 	bic.w	r4, r4, #7
				value->uint =
     aba:	e8f4 2302 	ldrd	r2, r3, [r4], #8
     abe:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
			if (length_mod == LENGTH_HH) {
     ac2:	e7c1      	b.n	a48 <__z_interrupt_stack_SIZEOF+0x208>
					(uint_value_type)va_arg(ap, size_t);
     ac4:	f854 3b04 	ldr.w	r3, [r4], #4
     ac8:	930e      	str	r3, [sp, #56]	; 0x38
     aca:	2300      	movs	r3, #0
     acc:	930f      	str	r3, [sp, #60]	; 0x3c
			} else if (length_mod == LENGTH_H) {
     ace:	e7bb      	b.n	a48 <__z_interrupt_stack_SIZEOF+0x208>
				value->uint = (unsigned char)value->uint;
     ad0:	b2db      	uxtb	r3, r3
     ad2:	e7cd      	b.n	a70 <__z_interrupt_stack_SIZEOF+0x230>
		} else if (specifier_cat == SPECIFIER_FP) {
     ad4:	2b04      	cmp	r3, #4
     ad6:	d108      	bne.n	aea <__z_interrupt_stack_SIZEOF+0x2aa>
					(sint_value_type)va_arg(ap, long long);
     ad8:	3407      	adds	r4, #7
				value->ldbl = va_arg(ap, long double);
     ada:	f024 0407 	bic.w	r4, r4, #7
     ade:	e9d4 2300 	ldrd	r2, r3, [r4]
     ae2:	3408      	adds	r4, #8
     ae4:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
     ae8:	e7ae      	b.n	a48 <__z_interrupt_stack_SIZEOF+0x208>
		} else if (specifier_cat == SPECIFIER_PTR) {
     aea:	2b03      	cmp	r3, #3
     aec:	d1ac      	bne.n	a48 <__z_interrupt_stack_SIZEOF+0x208>
			value->ptr = va_arg(ap, void *);
     aee:	f854 3b04 	ldr.w	r3, [r4], #4
     af2:	e7dd      	b.n	ab0 <__z_interrupt_stack_SIZEOF+0x270>
		switch (conv->specifier) {
     af4:	f89d 0043 	ldrb.w	r0, [sp, #67]	; 0x43
     af8:	2878      	cmp	r0, #120	; 0x78
     afa:	d8b4      	bhi.n	a66 <__z_interrupt_stack_SIZEOF+0x226>
     afc:	2862      	cmp	r0, #98	; 0x62
     afe:	d81c      	bhi.n	b3a <__z_interrupt_stack_SIZEOF+0x2fa>
     b00:	2825      	cmp	r0, #37	; 0x25
     b02:	f43f adad 	beq.w	660 <z_cbvprintf_impl+0x20>
     b06:	2858      	cmp	r0, #88	; 0x58
     b08:	d1ad      	bne.n	a66 <__z_interrupt_stack_SIZEOF+0x226>
			bps = encode_uint(value->uint, conv, buf, bpe);
     b0a:	f10d 0336 	add.w	r3, sp, #54	; 0x36
     b0e:	9300      	str	r3, [sp, #0]
     b10:	e9dd 010e 	ldrd	r0, r1, [sp, #56]	; 0x38
     b14:	ab08      	add	r3, sp, #32
     b16:	aa10      	add	r2, sp, #64	; 0x40
     b18:	f003 fbee 	bl	42f8 <encode_uint>
			if (precision >= 0) {
     b1c:	f1ba 0f00 	cmp.w	sl, #0
			bps = encode_uint(value->uint, conv, buf, bpe);
     b20:	4607      	mov	r7, r0
			if (precision >= 0) {
     b22:	f280 809a 	bge.w	c5a <__z_interrupt_stack_SIZEOF+0x41a>
		if (bps == NULL) {
     b26:	2f00      	cmp	r7, #0
     b28:	d09d      	beq.n	a66 <__z_interrupt_stack_SIZEOF+0x226>
		size_t nj_len = (bpe - bps);
     b2a:	f10d 0336 	add.w	r3, sp, #54	; 0x36
     b2e:	1bd8      	subs	r0, r3, r7
		if (sign != 0) {
     b30:	2e00      	cmp	r6, #0
     b32:	f000 80c1 	beq.w	cb8 <__z_interrupt_stack_SIZEOF+0x478>
			nj_len += 1U;
     b36:	3001      	adds	r0, #1
     b38:	e0be      	b.n	cb8 <__z_interrupt_stack_SIZEOF+0x478>
		switch (conv->specifier) {
     b3a:	3863      	subs	r0, #99	; 0x63
     b3c:	2815      	cmp	r0, #21
     b3e:	d892      	bhi.n	a66 <__z_interrupt_stack_SIZEOF+0x226>
     b40:	a201      	add	r2, pc, #4	; (adr r2, b48 <__z_interrupt_stack_SIZEOF+0x308>)
     b42:	f852 f020 	ldr.w	pc, [r2, r0, lsl #2]
     b46:	bf00      	nop
     b48:	00000c1d 	.word	0x00000c1d
     b4c:	00000c2f 	.word	0x00000c2f
     b50:	00000a67 	.word	0x00000a67
     b54:	00000a67 	.word	0x00000a67
     b58:	00000a67 	.word	0x00000a67
     b5c:	00000a67 	.word	0x00000a67
     b60:	00000c2f 	.word	0x00000c2f
     b64:	00000a67 	.word	0x00000a67
     b68:	00000a67 	.word	0x00000a67
     b6c:	00000a67 	.word	0x00000a67
     b70:	00000a67 	.word	0x00000a67
     b74:	00000cbd 	.word	0x00000cbd
     b78:	00000c55 	.word	0x00000c55
     b7c:	00000c7b 	.word	0x00000c7b
     b80:	00000a67 	.word	0x00000a67
     b84:	00000a67 	.word	0x00000a67
     b88:	00000ba1 	.word	0x00000ba1
     b8c:	00000a67 	.word	0x00000a67
     b90:	00000c55 	.word	0x00000c55
     b94:	00000a67 	.word	0x00000a67
     b98:	00000a67 	.word	0x00000a67
     b9c:	00000c55 	.word	0x00000c55
			if (precision >= 0) {
     ba0:	f1ba 0f00 	cmp.w	sl, #0
			bps = (const char *)value->ptr;
     ba4:	9f0e      	ldr	r7, [sp, #56]	; 0x38
			if (precision >= 0) {
     ba6:	db35      	blt.n	c14 <__z_interrupt_stack_SIZEOF+0x3d4>
				len = strnlen(bps, precision);
     ba8:	4651      	mov	r1, sl
     baa:	4638      	mov	r0, r7
     bac:	f003 fc24 	bl	43f8 <strnlen>
			bpe = bps + len;
     bb0:	eb07 0a00 	add.w	sl, r7, r0
		if (bps == NULL) {
     bb4:	2f00      	cmp	r7, #0
     bb6:	f43f af56 	beq.w	a66 <__z_interrupt_stack_SIZEOF+0x226>
		char sign = 0;
     bba:	2600      	movs	r6, #0
		if (conv->altform_0c) {
     bbc:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     bc0:	f013 0210 	ands.w	r2, r3, #16
     bc4:	9205      	str	r2, [sp, #20]
     bc6:	f000 8093 	beq.w	cf0 <__z_interrupt_stack_SIZEOF+0x4b0>
			nj_len += 2U;
     bca:	3002      	adds	r0, #2
		if (conv->pad_fp) {
     bcc:	065b      	lsls	r3, r3, #25
		nj_len += conv->pad0_value;
     bce:	9a11      	ldr	r2, [sp, #68]	; 0x44
			nj_len += conv->pad0_pre_exp;
     bd0:	bf48      	it	mi
     bd2:	9b12      	ldrmi	r3, [sp, #72]	; 0x48
		nj_len += conv->pad0_value;
     bd4:	9204      	str	r2, [sp, #16]
     bd6:	4410      	add	r0, r2
			nj_len += conv->pad0_pre_exp;
     bd8:	bf48      	it	mi
     bda:	18c0      	addmi	r0, r0, r3
		if (width > 0) {
     bdc:	f1b8 0f00 	cmp.w	r8, #0
     be0:	f340 80a0 	ble.w	d24 <__z_interrupt_stack_SIZEOF+0x4e4>
			if (!conv->flag_dash) {
     be4:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
			width -= (int)nj_len;
     be8:	eba8 0800 	sub.w	r8, r8, r0
			if (!conv->flag_dash) {
     bec:	f3c2 0380 	ubfx	r3, r2, #2, #1
     bf0:	0750      	lsls	r0, r2, #29
     bf2:	9306      	str	r3, [sp, #24]
     bf4:	f100 8096 	bmi.w	d24 <__z_interrupt_stack_SIZEOF+0x4e4>
				if (conv->flag_zero) {
     bf8:	0651      	lsls	r1, r2, #25
     bfa:	f140 8089 	bpl.w	d10 <__z_interrupt_stack_SIZEOF+0x4d0>
					if (sign != 0) {
     bfe:	b13e      	cbz	r6, c10 <__z_interrupt_stack_SIZEOF+0x3d0>
						OUTC(sign);
     c00:	4659      	mov	r1, fp
     c02:	4630      	mov	r0, r6
     c04:	47c8      	blx	r9
     c06:	2800      	cmp	r0, #0
     c08:	db7f      	blt.n	d0a <__z_interrupt_stack_SIZEOF+0x4ca>
     c0a:	9b06      	ldr	r3, [sp, #24]
     c0c:	3501      	adds	r5, #1
     c0e:	461e      	mov	r6, r3
					pad = '0';
     c10:	2230      	movs	r2, #48	; 0x30
     c12:	e07e      	b.n	d12 <__z_interrupt_stack_SIZEOF+0x4d2>
				len = strlen(bps);
     c14:	4638      	mov	r0, r7
     c16:	f003 fbe8 	bl	43ea <strlen>
     c1a:	e7c9      	b.n	bb0 <__z_interrupt_stack_SIZEOF+0x370>
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     c1c:	9b0e      	ldr	r3, [sp, #56]	; 0x38
     c1e:	f88d 3020 	strb.w	r3, [sp, #32]
		char sign = 0;
     c22:	2600      	movs	r6, #0
			bps = buf;
     c24:	af08      	add	r7, sp, #32
			bpe = buf + 1;
     c26:	f10d 0a21 	add.w	sl, sp, #33	; 0x21
		size_t nj_len = (bpe - bps);
     c2a:	2001      	movs	r0, #1
     c2c:	e7c6      	b.n	bbc <__z_interrupt_stack_SIZEOF+0x37c>
			if (conv->flag_plus) {
     c2e:	0719      	lsls	r1, r3, #28
			} else if (conv->flag_space) {
     c30:	bf5c      	itt	pl
     c32:	f3c3 1300 	ubfxpl	r3, r3, #4, #1
     c36:	015e      	lslpl	r6, r3, #5
			sint = value->sint;
     c38:	e9dd 230e 	ldrd	r2, r3, [sp, #56]	; 0x38
				sign = '+';
     c3c:	bf48      	it	mi
     c3e:	262b      	movmi	r6, #43	; 0x2b
			if (sint < 0) {
     c40:	2b00      	cmp	r3, #0
     c42:	f6bf af62 	bge.w	b0a <__z_interrupt_stack_SIZEOF+0x2ca>
				value->uint = (uint_value_type)-sint;
     c46:	4252      	negs	r2, r2
     c48:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
     c4c:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
				sign = '-';
     c50:	262d      	movs	r6, #45	; 0x2d
     c52:	e75a      	b.n	b0a <__z_interrupt_stack_SIZEOF+0x2ca>
		switch (conv->specifier) {
     c54:	2600      	movs	r6, #0
     c56:	e758      	b.n	b0a <__z_interrupt_stack_SIZEOF+0x2ca>
		char sign = 0;
     c58:	2600      	movs	r6, #0
				conv->flag_zero = false;
     c5a:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
				size_t len = bpe - bps;
     c5e:	f10d 0336 	add.w	r3, sp, #54	; 0x36
     c62:	1bdb      	subs	r3, r3, r7
				conv->flag_zero = false;
     c64:	f36f 1286 	bfc	r2, #6, #1
				if (len < (size_t)precision) {
     c68:	459a      	cmp	sl, r3
				conv->flag_zero = false;
     c6a:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
				if (len < (size_t)precision) {
     c6e:	f67f af5a 	bls.w	b26 <__z_interrupt_stack_SIZEOF+0x2e6>
					conv->pad0_value = precision - (int)len;
     c72:	ebaa 0303 	sub.w	r3, sl, r3
     c76:	9311      	str	r3, [sp, #68]	; 0x44
     c78:	e755      	b.n	b26 <__z_interrupt_stack_SIZEOF+0x2e6>
			if (value->ptr != NULL) {
     c7a:	980e      	ldr	r0, [sp, #56]	; 0x38
     c7c:	b390      	cbz	r0, ce4 <__z_interrupt_stack_SIZEOF+0x4a4>
				bps = encode_uint((uintptr_t)value->ptr, conv,
     c7e:	f10d 0336 	add.w	r3, sp, #54	; 0x36
     c82:	9300      	str	r3, [sp, #0]
     c84:	aa10      	add	r2, sp, #64	; 0x40
     c86:	ab08      	add	r3, sp, #32
     c88:	2100      	movs	r1, #0
     c8a:	f003 fb35 	bl	42f8 <encode_uint>
				conv->altform_0c = true;
     c8e:	f8bd 3042 	ldrh.w	r3, [sp, #66]	; 0x42
     c92:	f003 03ef 	and.w	r3, r3, #239	; 0xef
     c96:	f443 43f0 	orr.w	r3, r3, #30720	; 0x7800
     c9a:	f043 0310 	orr.w	r3, r3, #16
			if (precision >= 0) {
     c9e:	f1ba 0f00 	cmp.w	sl, #0
				bps = encode_uint((uintptr_t)value->ptr, conv,
     ca2:	4607      	mov	r7, r0
				conv->altform_0c = true;
     ca4:	f8ad 3042 	strh.w	r3, [sp, #66]	; 0x42
			if (precision >= 0) {
     ca8:	dad6      	bge.n	c58 <__z_interrupt_stack_SIZEOF+0x418>
		if (bps == NULL) {
     caa:	2800      	cmp	r0, #0
     cac:	f43f aedb 	beq.w	a66 <__z_interrupt_stack_SIZEOF+0x226>
		size_t nj_len = (bpe - bps);
     cb0:	f10d 0336 	add.w	r3, sp, #54	; 0x36
     cb4:	1a18      	subs	r0, r3, r0
		char sign = 0;
     cb6:	2600      	movs	r6, #0
     cb8:	469a      	mov	sl, r3
     cba:	e77f      	b.n	bbc <__z_interrupt_stack_SIZEOF+0x37c>
				store_count(conv, value->ptr, count);
     cbc:	9b0e      	ldr	r3, [sp, #56]	; 0x38
	switch ((enum length_mod_enum)conv->length_mod) {
     cbe:	2907      	cmp	r1, #7
     cc0:	f63f aed1 	bhi.w	a66 <__z_interrupt_stack_SIZEOF+0x226>
     cc4:	e8df f001 	tbb	[pc, r1]
     cc8:	0c06040c 	.word	0x0c06040c
     ccc:	0c0c0808 	.word	0x0c0c0808
		*(signed char *)dp = (signed char)count;
     cd0:	701d      	strb	r5, [r3, #0]
		if (bps == NULL) {
     cd2:	e6c8      	b.n	a66 <__z_interrupt_stack_SIZEOF+0x226>
		*(short *)dp = (short)count;
     cd4:	801d      	strh	r5, [r3, #0]
		if (bps == NULL) {
     cd6:	e6c6      	b.n	a66 <__z_interrupt_stack_SIZEOF+0x226>
		*(intmax_t *)dp = (intmax_t)count;
     cd8:	17ea      	asrs	r2, r5, #31
     cda:	e9c3 5200 	strd	r5, r2, [r3]
		if (bps == NULL) {
     cde:	e6c2      	b.n	a66 <__z_interrupt_stack_SIZEOF+0x226>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
     ce0:	601d      	str	r5, [r3, #0]
		if (bps == NULL) {
     ce2:	e6c0      	b.n	a66 <__z_interrupt_stack_SIZEOF+0x226>
     ce4:	4f2e      	ldr	r7, [pc, #184]	; (da0 <__z_interrupt_stack_SIZEOF+0x560>)
		char sign = 0;
     ce6:	4606      	mov	r6, r0
			bpe = bps + 5;
     ce8:	f107 0a05 	add.w	sl, r7, #5
		size_t nj_len = (bpe - bps);
     cec:	2005      	movs	r0, #5
     cee:	e765      	b.n	bbc <__z_interrupt_stack_SIZEOF+0x37c>
		} else if (conv->altform_0) {
     cf0:	071a      	lsls	r2, r3, #28
			nj_len += 1U;
     cf2:	bf48      	it	mi
     cf4:	3001      	addmi	r0, #1
     cf6:	e769      	b.n	bcc <__z_interrupt_stack_SIZEOF+0x38c>
     cf8:	9307      	str	r3, [sp, #28]
					OUTC(pad);
     cfa:	4610      	mov	r0, r2
     cfc:	9206      	str	r2, [sp, #24]
     cfe:	4659      	mov	r1, fp
     d00:	47c8      	blx	r9
     d02:	2800      	cmp	r0, #0
     d04:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
     d08:	da04      	bge.n	d14 <__z_interrupt_stack_SIZEOF+0x4d4>
#undef OUTS
#undef OUTC
}
     d0a:	b015      	add	sp, #84	; 0x54
     d0c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				char pad = ' ';
     d10:	2220      	movs	r2, #32
					pad = '0';
     d12:	4643      	mov	r3, r8
				while (width-- > 0) {
     d14:	4619      	mov	r1, r3
     d16:	2900      	cmp	r1, #0
     d18:	f103 33ff 	add.w	r3, r3, #4294967295
     d1c:	dcec      	bgt.n	cf8 <__z_interrupt_stack_SIZEOF+0x4b8>
     d1e:	4445      	add	r5, r8
     d20:	1a6d      	subs	r5, r5, r1
     d22:	4698      	mov	r8, r3
		if (sign != 0) {
     d24:	b12e      	cbz	r6, d32 <__z_interrupt_stack_SIZEOF+0x4f2>
			OUTC(sign);
     d26:	4659      	mov	r1, fp
     d28:	4630      	mov	r0, r6
     d2a:	47c8      	blx	r9
     d2c:	2800      	cmp	r0, #0
     d2e:	dbec      	blt.n	d0a <__z_interrupt_stack_SIZEOF+0x4ca>
     d30:	3501      	adds	r5, #1
			if (conv->altform_0c | conv->altform_0) {
     d32:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     d36:	06da      	lsls	r2, r3, #27
     d38:	d401      	bmi.n	d3e <__z_interrupt_stack_SIZEOF+0x4fe>
     d3a:	071b      	lsls	r3, r3, #28
     d3c:	d505      	bpl.n	d4a <__z_interrupt_stack_SIZEOF+0x50a>
				OUTC('0');
     d3e:	4659      	mov	r1, fp
     d40:	2030      	movs	r0, #48	; 0x30
     d42:	47c8      	blx	r9
     d44:	2800      	cmp	r0, #0
     d46:	dbe0      	blt.n	d0a <__z_interrupt_stack_SIZEOF+0x4ca>
     d48:	3501      	adds	r5, #1
			if (conv->altform_0c) {
     d4a:	9b05      	ldr	r3, [sp, #20]
     d4c:	b133      	cbz	r3, d5c <__z_interrupt_stack_SIZEOF+0x51c>
				OUTC(conv->specifier);
     d4e:	f89d 0043 	ldrb.w	r0, [sp, #67]	; 0x43
     d52:	4659      	mov	r1, fp
     d54:	47c8      	blx	r9
     d56:	2800      	cmp	r0, #0
     d58:	dbd7      	blt.n	d0a <__z_interrupt_stack_SIZEOF+0x4ca>
     d5a:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
     d5c:	9e04      	ldr	r6, [sp, #16]
     d5e:	442e      	add	r6, r5
     d60:	e005      	b.n	d6e <__z_interrupt_stack_SIZEOF+0x52e>
				OUTC('0');
     d62:	4659      	mov	r1, fp
     d64:	2030      	movs	r0, #48	; 0x30
     d66:	47c8      	blx	r9
     d68:	2800      	cmp	r0, #0
     d6a:	dbce      	blt.n	d0a <__z_interrupt_stack_SIZEOF+0x4ca>
     d6c:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
     d6e:	1b73      	subs	r3, r6, r5
     d70:	2b00      	cmp	r3, #0
     d72:	dcf6      	bgt.n	d62 <__z_interrupt_stack_SIZEOF+0x522>
			OUTS(bps, bpe);
     d74:	4653      	mov	r3, sl
     d76:	463a      	mov	r2, r7
     d78:	4659      	mov	r1, fp
     d7a:	4648      	mov	r0, r9
     d7c:	f003 fb02 	bl	4384 <outs>
     d80:	2800      	cmp	r0, #0
     d82:	dbc2      	blt.n	d0a <__z_interrupt_stack_SIZEOF+0x4ca>
     d84:	4405      	add	r5, r0
		while (width > 0) {
     d86:	44a8      	add	r8, r5
     d88:	eba8 0305 	sub.w	r3, r8, r5
     d8c:	2b00      	cmp	r3, #0
     d8e:	f77f ae6a 	ble.w	a66 <__z_interrupt_stack_SIZEOF+0x226>
			OUTC(' ');
     d92:	4659      	mov	r1, fp
     d94:	2020      	movs	r0, #32
     d96:	47c8      	blx	r9
     d98:	2800      	cmp	r0, #0
     d9a:	dbb6      	blt.n	d0a <__z_interrupt_stack_SIZEOF+0x4ca>
     d9c:	3501      	adds	r5, #1
			--width;
     d9e:	e7f3      	b.n	d88 <__z_interrupt_stack_SIZEOF+0x548>
     da0:	0000503d 	.word	0x0000503d

00000da4 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
     da4:	f001 bbde 	b.w	2564 <SystemInit>

00000da8 <pm_state_notify>:
/*
 * Function called to notify when the system is entering / exiting a
 * power state
 */
static inline void pm_state_notify(bool entering_state)
{
     da8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
     dac:	4605      	mov	r5, r0
	__asm__ volatile(
     dae:	f04f 0320 	mov.w	r3, #32
     db2:	f3ef 8611 	mrs	r6, BASEPRI
     db6:	f383 8812 	msr	BASEPRI_MAX, r3
     dba:	f3bf 8f6f 	isb	sy
	return list->head;
     dbe:	4b0e      	ldr	r3, [pc, #56]	; (df8 <pm_state_notify+0x50>)
		} else {
			callback = notifier->state_exit;
		}

		if (callback) {
			callback(z_cpus_pm_state[_current_cpu->id].state);
     dc0:	4f0e      	ldr	r7, [pc, #56]	; (dfc <pm_state_notify+0x54>)
     dc2:	681c      	ldr	r4, [r3, #0]
     dc4:	f8df 8038 	ldr.w	r8, [pc, #56]	; e00 <pm_state_notify+0x58>
     dc8:	f04f 090c 	mov.w	r9, #12
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
     dcc:	b92c      	cbnz	r4, dda <pm_state_notify+0x32>
	__asm__ volatile(
     dce:	f386 8811 	msr	BASEPRI, r6
     dd2:	f3bf 8f6f 	isb	sy
		}
	}
	k_spin_unlock(&pm_notifier_lock, pm_notifier_key);
}
     dd6:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			callback = notifier->state_exit;
     dda:	e9d4 2301 	ldrd	r2, r3, [r4, #4]
			callback = notifier->state_entry;
     dde:	2d00      	cmp	r5, #0
     de0:	bf18      	it	ne
     de2:	4613      	movne	r3, r2
		if (callback) {
     de4:	b12b      	cbz	r3, df2 <pm_state_notify+0x4a>
			callback(z_cpus_pm_state[_current_cpu->id].state);
     de6:	f898 2010 	ldrb.w	r2, [r8, #16]
     dea:	fb09 f202 	mul.w	r2, r9, r2
     dee:	5cb8      	ldrb	r0, [r7, r2]
     df0:	4798      	blx	r3
	return node->next;
     df2:	6824      	ldr	r4, [r4, #0]
     df4:	e7ea      	b.n	dcc <pm_state_notify+0x24>
     df6:	bf00      	nop
     df8:	20000290 	.word	0x20000290
     dfc:	20000284 	.word	0x20000284
     e00:	20000428 	.word	0x20000428

00000e04 <pm_system_resume>:

void pm_system_resume(void)
{
     e04:	b570      	push	{r4, r5, r6, lr}
	uint8_t id = CURRENT_CPU;
     e06:	4b19      	ldr	r3, [pc, #100]	; (e6c <pm_system_resume+0x68>)
     e08:	7c1c      	ldrb	r4, [r3, #16]
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
     e0a:	f3bf 8f5b 	dmb	ish
 *
 * @return true if the bit was set, false if it wasn't.
 */
static inline bool atomic_test_and_clear_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);
     e0e:	f004 031f 	and.w	r3, r4, #31
     e12:	2201      	movs	r2, #1
     e14:	409a      	lsls	r2, r3
     e16:	4b16      	ldr	r3, [pc, #88]	; (e70 <pm_system_resume+0x6c>)
	atomic_val_t old;

	old = atomic_and(ATOMIC_ELEM(target, bit), ~mask);
     e18:	0961      	lsrs	r1, r4, #5
     e1a:	eb03 0381 	add.w	r3, r3, r1, lsl #2
     e1e:	43d0      	mvns	r0, r2
     e20:	e853 1f00 	ldrex	r1, [r3]
     e24:	ea01 0500 	and.w	r5, r1, r0
     e28:	e843 5600 	strex	r6, r5, [r3]
     e2c:	2e00      	cmp	r6, #0
     e2e:	d1f7      	bne.n	e20 <pm_system_resume+0x1c>
     e30:	f3bf 8f5b 	dmb	ish
	 * that caused the wake. This hook will be called from the ISR.
	 * For such CPU LPS states, do post operations and restores here.
	 * The kernel scheduler will get control after the ISR finishes
	 * and it may schedule another thread.
	 */
	if (atomic_test_and_clear_bit(z_post_ops_required, id)) {
     e34:	420a      	tst	r2, r1
     e36:	d013      	beq.n	e60 <pm_system_resume+0x5c>
	if (pm_state_exit_post_ops != NULL) {
     e38:	4b0e      	ldr	r3, [pc, #56]	; (e74 <pm_system_resume+0x70>)
     e3a:	4d0f      	ldr	r5, [pc, #60]	; (e78 <pm_system_resume+0x74>)
     e3c:	b18b      	cbz	r3, e62 <pm_system_resume+0x5e>
		pm_state_exit_post_ops(info->state, info->substate_id);
     e3e:	230c      	movs	r3, #12
     e40:	4363      	muls	r3, r4
     e42:	18ea      	adds	r2, r5, r3
     e44:	5ce8      	ldrb	r0, [r5, r3]
     e46:	7851      	ldrb	r1, [r2, #1]
     e48:	f003 faff 	bl	444a <pm_state_exit_post_ops>
		pm_exit_pos_ops(&z_cpus_pm_state[id]);
		pm_state_notify(false);
     e4c:	2000      	movs	r0, #0
     e4e:	f7ff ffab 	bl	da8 <pm_state_notify>
		z_cpus_pm_state[id] = (struct pm_state_info){PM_STATE_ACTIVE,
     e52:	230c      	movs	r3, #12
     e54:	435c      	muls	r4, r3
     e56:	192a      	adds	r2, r5, r4
     e58:	2300      	movs	r3, #0
     e5a:	512b      	str	r3, [r5, r4]
     e5c:	e9c2 3301 	strd	r3, r3, [r2, #4]
			0, 0};
	}
}
     e60:	bd70      	pop	{r4, r5, r6, pc}
     e62:	f383 8811 	msr	BASEPRI, r3
     e66:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
     e6a:	e7ef      	b.n	e4c <pm_system_resume+0x48>
     e6c:	20000428 	.word	0x20000428
     e70:	20000298 	.word	0x20000298
     e74:	0000444b 	.word	0x0000444b
     e78:	20000284 	.word	0x20000284

00000e7c <pm_system_suspend>:

	return true;
}

bool pm_system_suspend(int32_t ticks)
{
     e7c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint8_t id = CURRENT_CPU;
     e80:	4b35      	ldr	r3, [pc, #212]	; (f58 <pm_system_suspend+0xdc>)
{
     e82:	4607      	mov	r7, r0
	uint8_t id = CURRENT_CPU;
     e84:	7c1d      	ldrb	r5, [r3, #16]
	__asm__ volatile(
     e86:	f04f 0320 	mov.w	r3, #32
     e8a:	f3ef 8811 	mrs	r8, BASEPRI
     e8e:	f383 8812 	msr	BASEPRI_MAX, r3
     e92:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key;

	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);

	key = k_spin_lock(&pm_forced_state_lock);
	if (z_cpus_pm_forced_state[id].state != PM_STATE_ACTIVE) {
     e96:	240c      	movs	r4, #12
     e98:	4b30      	ldr	r3, [pc, #192]	; (f5c <pm_system_suspend+0xe0>)
     e9a:	4e31      	ldr	r6, [pc, #196]	; (f60 <pm_system_suspend+0xe4>)
     e9c:	436c      	muls	r4, r5
     e9e:	191a      	adds	r2, r3, r4
     ea0:	5d19      	ldrb	r1, [r3, r4]
     ea2:	2900      	cmp	r1, #0
     ea4:	d04c      	beq.n	f40 <pm_system_suspend+0xc4>
		z_cpus_pm_state[id] = z_cpus_pm_forced_state[id];
     ea6:	ca07      	ldmia	r2, {r0, r1, r2}
     ea8:	eb06 0c04 	add.w	ip, r6, r4
     eac:	e88c 0007 	stmia.w	ip, {r0, r1, r2}
		z_cpus_pm_forced_state[id].state = PM_STATE_ACTIVE;
     eb0:	2200      	movs	r2, #0
     eb2:	551a      	strb	r2, [r3, r4]
	__asm__ volatile(
     eb4:	f388 8811 	msr	BASEPRI, r8
     eb8:	f3bf 8f6f 	isb	sy
			z_cpus_pm_state[id] = *info;
		}
	}
	k_spin_unlock(&pm_forced_state_lock, key);

	if (z_cpus_pm_state[id].state == PM_STATE_ACTIVE) {
     ebc:	230c      	movs	r3, #12
     ebe:	436b      	muls	r3, r5
     ec0:	18f2      	adds	r2, r6, r3
     ec2:	5cf0      	ldrb	r0, [r6, r3]
     ec4:	2800      	cmp	r0, #0
     ec6:	d039      	beq.n	f3c <pm_system_suspend+0xc0>
		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);
		return false;
	}

	if (ticks != K_TICKS_FOREVER) {
     ec8:	1c7b      	adds	r3, r7, #1
     eca:	d010      	beq.n	eee <pm_system_suspend+0x72>
		} else {
			return t * ((uint64_t)to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
     ecc:	f8d2 c008 	ldr.w	ip, [r2, #8]
     ed0:	4c24      	ldr	r4, [pc, #144]	; (f64 <pm_system_suspend+0xe8>)
     ed2:	4a25      	ldr	r2, [pc, #148]	; (f68 <pm_system_suspend+0xec>)
     ed4:	f44f 4000 	mov.w	r0, #32768	; 0x8000
     ed8:	2100      	movs	r1, #0
     eda:	fbec 4100 	umlal	r4, r1, ip, r0
     ede:	2300      	movs	r3, #0
     ee0:	4620      	mov	r0, r4
     ee2:	f7ff f8fb 	bl	dc <__aeabi_uldivmod>
		/*
		 * We need to set the timer to interrupt a little bit early to
		 * accommodate the time required by the CPU to fully wake up.
		 */
		sys_clock_set_timeout(ticks -
     ee6:	2101      	movs	r1, #1
     ee8:	1a38      	subs	r0, r7, r0
     eea:	f001 fae3 	bl	24b4 <sys_clock_set_timeout>
	 * state. We don't want to be scheduled out yet, first we need
	 * to send a notification about leaving the idle state. So,
	 * we lock the scheduler here and unlock just after we have
	 * sent the notification in pm_system_resume().
	 */
	k_sched_lock();
     eee:	f002 fe77 	bl	3be0 <k_sched_lock>
	pm_stats_start();
	/* Enter power state */
	pm_state_notify(true);
     ef2:	2001      	movs	r0, #1
     ef4:	f7ff ff58 	bl	da8 <pm_state_notify>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
     ef8:	f3bf 8f5b 	dmb	ish
     efc:	4b1b      	ldr	r3, [pc, #108]	; (f6c <pm_system_suspend+0xf0>)
 */
static inline void atomic_set_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);

	(void)atomic_or(ATOMIC_ELEM(target, bit), mask);
     efe:	096a      	lsrs	r2, r5, #5
     f00:	eb03 0382 	add.w	r3, r3, r2, lsl #2
	atomic_val_t mask = ATOMIC_MASK(bit);
     f04:	f005 011f 	and.w	r1, r5, #31
     f08:	2201      	movs	r2, #1
     f0a:	408a      	lsls	r2, r1
     f0c:	e853 0f00 	ldrex	r0, [r3]
     f10:	4310      	orrs	r0, r2
     f12:	e843 0100 	strex	r1, r0, [r3]
     f16:	2900      	cmp	r1, #0
     f18:	d1f8      	bne.n	f0c <pm_system_suspend+0x90>
     f1a:	f3bf 8f5b 	dmb	ish
	if (pm_state_set != NULL) {
     f1e:	4b14      	ldr	r3, [pc, #80]	; (f70 <pm_system_suspend+0xf4>)
     f20:	b13b      	cbz	r3, f32 <pm_system_suspend+0xb6>
		pm_state_set(info->state, info->substate_id);
     f22:	230c      	movs	r3, #12
     f24:	fb03 f005 	mul.w	r0, r3, r5
     f28:	1833      	adds	r3, r6, r0
     f2a:	5c30      	ldrb	r0, [r6, r0]
     f2c:	7859      	ldrb	r1, [r3, #1]
     f2e:	f003 fa80 	bl	4432 <pm_state_set>
	if (atomic_add(&z_cpus_active, 1) == 0) {
		pm_resume_devices();
	}
#endif
	pm_stats_update(z_cpus_pm_state[id].state);
	pm_system_resume();
     f32:	f7ff ff67 	bl	e04 <pm_system_resume>
	k_sched_unlock();
     f36:	f002 fe67 	bl	3c08 <k_sched_unlock>
	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);

	return true;
     f3a:	2001      	movs	r0, #1
}
     f3c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		info = pm_policy_next_state(id, ticks);
     f40:	4601      	mov	r1, r0
     f42:	4628      	mov	r0, r5
     f44:	f000 f816 	bl	f74 <pm_policy_next_state>
		if (info != NULL) {
     f48:	2800      	cmp	r0, #0
     f4a:	d0b3      	beq.n	eb4 <pm_system_suspend+0x38>
			z_cpus_pm_state[id] = *info;
     f4c:	c807      	ldmia	r0, {r0, r1, r2}
     f4e:	4434      	add	r4, r6
     f50:	e884 0007 	stmia.w	r4, {r0, r1, r2}
     f54:	e7ae      	b.n	eb4 <pm_system_suspend+0x38>
     f56:	bf00      	nop
     f58:	20000428 	.word	0x20000428
     f5c:	20000278 	.word	0x20000278
     f60:	20000284 	.word	0x20000284
     f64:	000f423f 	.word	0x000f423f
     f68:	000f4240 	.word	0x000f4240
     f6c:	20000298 	.word	0x20000298
     f70:	00004433 	.word	0x00004433

00000f74 <pm_policy_next_state>:
	}
}

#ifdef CONFIG_PM_POLICY_DEFAULT
const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks)
{
     f74:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     f78:	b085      	sub	sp, #20
     f7a:	460e      	mov	r6, r1
	uint8_t num_cpu_states;
	const struct pm_state_info *cpu_states;

	num_cpu_states = pm_state_cpu_get_all(cpu, &cpu_states);
     f7c:	a903      	add	r1, sp, #12
     f7e:	f000 f843 	bl	1008 <pm_state_cpu_get_all>

		min_residency = k_us_to_ticks_ceil32(state->min_residency_us);
		exit_latency = k_us_to_ticks_ceil32(state->exit_latency_us);

		/* skip state if it brings too much latency */
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
     f82:	4b1e      	ldr	r3, [pc, #120]	; (ffc <pm_policy_next_state+0x88>)
     f84:	9d03      	ldr	r5, [sp, #12]
     f86:	f8d3 a000 	ldr.w	sl, [r3]
     f8a:	f8df 8074 	ldr.w	r8, [pc, #116]	; 1000 <CONFIG_FPROTECT_BLOCK_SIZE>
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
     f8e:	1e43      	subs	r3, r0, #1
     f90:	b21b      	sxth	r3, r3
     f92:	eb03 0343 	add.w	r3, r3, r3, lsl #1
	num_cpu_states = pm_state_cpu_get_all(cpu, &cpu_states);
     f96:	4604      	mov	r4, r0
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
     f98:	eb05 0583 	add.w	r5, r5, r3, lsl #2
     f9c:	f44f 4700 	mov.w	r7, #32768	; 0x8000
     fa0:	f04f 0b00 	mov.w	fp, #0
     fa4:	b924      	cbnz	r4, fb0 <pm_policy_next_state+0x3c>
		    (ticks >= (min_residency + exit_latency))) {
			return state;
		}
	}

	return NULL;
     fa6:	46a1      	mov	r9, r4
}
     fa8:	4648      	mov	r0, r9
     faa:	b005      	add	sp, #20
     fac:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
     fb0:	6868      	ldr	r0, [r5, #4]
     fb2:	4a14      	ldr	r2, [pc, #80]	; (1004 <CONFIG_FPROTECT_BLOCK_SIZE+0x4>)
     fb4:	46c4      	mov	ip, r8
     fb6:	4659      	mov	r1, fp
     fb8:	fbe0 c107 	umlal	ip, r1, r0, r7
     fbc:	2300      	movs	r3, #0
     fbe:	4660      	mov	r0, ip
     fc0:	f7ff f88c 	bl	dc <__aeabi_uldivmod>
     fc4:	9001      	str	r0, [sp, #4]
     fc6:	68a8      	ldr	r0, [r5, #8]
     fc8:	4a0e      	ldr	r2, [pc, #56]	; (1004 <CONFIG_FPROTECT_BLOCK_SIZE+0x4>)
     fca:	46c4      	mov	ip, r8
     fcc:	4659      	mov	r1, fp
     fce:	fbe0 c107 	umlal	ip, r1, r0, r7
     fd2:	2300      	movs	r3, #0
     fd4:	4660      	mov	r0, ip
     fd6:	f7ff f881 	bl	dc <__aeabi_uldivmod>
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
     fda:	f1ba 3fff 	cmp.w	sl, #4294967295
		const struct pm_state_info *state = &cpu_states[i];
     fde:	46a9      	mov	r9, r5
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
     fe0:	d001      	beq.n	fe6 <pm_policy_next_state+0x72>
     fe2:	4582      	cmp	sl, r0
     fe4:	d905      	bls.n	ff2 <pm_policy_next_state+0x7e>
		if ((ticks == K_TICKS_FOREVER) ||
     fe6:	1c73      	adds	r3, r6, #1
     fe8:	d0de      	beq.n	fa8 <pm_policy_next_state+0x34>
		    (ticks >= (min_residency + exit_latency))) {
     fea:	9b01      	ldr	r3, [sp, #4]
     fec:	4418      	add	r0, r3
		if ((ticks == K_TICKS_FOREVER) ||
     fee:	42b0      	cmp	r0, r6
     ff0:	d9da      	bls.n	fa8 <pm_policy_next_state+0x34>
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
     ff2:	3c01      	subs	r4, #1
     ff4:	b2a4      	uxth	r4, r4
     ff6:	3d0c      	subs	r5, #12
     ff8:	e7d4      	b.n	fa4 <pm_policy_next_state+0x30>
     ffa:	bf00      	nop
     ffc:	20000004 	.word	0x20000004
    1000:	000f423f 	.word	0x000f423f
    1004:	000f4240 	.word	0x000f4240

00001008 <pm_state_cpu_get_all>:
	DT_FOREACH_CHILD_SEP(DT_PATH(cpus), DT_NUM_CPU_POWER_STATES, (,))
};

uint8_t pm_state_cpu_get_all(uint8_t cpu, const struct pm_state_info **states)
{
	if (cpu >= ARRAY_SIZE(cpus_states)) {
    1008:	b908      	cbnz	r0, 100e <pm_state_cpu_get_all+0x6>
		return 0;
	}

	*states = cpus_states[cpu];
    100a:	4b02      	ldr	r3, [pc, #8]	; (1014 <pm_state_cpu_get_all+0xc>)
    100c:	600b      	str	r3, [r1, #0]

	return states_per_cpu[cpu];
}
    100e:	2000      	movs	r0, #0
    1010:	4770      	bx	lr
    1012:	bf00      	nop
    1014:	00004ed8 	.word	0x00004ed8

00001018 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    1018:	4901      	ldr	r1, [pc, #4]	; (1020 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    101a:	2210      	movs	r2, #16
	str	r2, [r1]
    101c:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    101e:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    1020:	e000ed10 	.word	0xe000ed10

00001024 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    1024:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    1026:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    1028:	f380 8811 	msr	BASEPRI, r0
	isb
    102c:	f3bf 8f6f 	isb	sy
	 * (i.e. if the caller sets _kernel.idle).
	 */
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */

	/* Enter low power state */
	_sleep_if_allowed wfi
    1030:	f3bf 8f4f 	dsb	sy
    1034:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    1036:	b662      	cpsie	i
	isb
    1038:	f3bf 8f6f 	isb	sy

	bx	lr
    103c:	4770      	bx	lr
    103e:	bf00      	nop

00001040 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    1040:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    1042:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    1044:	f381 8811 	msr	BASEPRI, r1

	_sleep_if_allowed wfe
    1048:	f3bf 8f4f 	dsb	sy
    104c:	bf20      	wfe

	msr	BASEPRI, r0
    104e:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    1052:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    1054:	4770      	bx	lr
    1056:	bf00      	nop

00001058 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    1058:	b240      	sxtb	r0, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    105a:	2800      	cmp	r0, #0
    105c:	db07      	blt.n	106e <arch_irq_enable+0x16>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    105e:	4a04      	ldr	r2, [pc, #16]	; (1070 <arch_irq_enable+0x18>)
    1060:	0941      	lsrs	r1, r0, #5
    1062:	2301      	movs	r3, #1
    1064:	f000 001f 	and.w	r0, r0, #31
    1068:	4083      	lsls	r3, r0
    106a:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
}
    106e:	4770      	bx	lr
    1070:	e000e100 	.word	0xe000e100

00001074 <arch_irq_disable>:

void arch_irq_disable(unsigned int irq)
{
	NVIC_DisableIRQ((IRQn_Type)irq);
    1074:	b240      	sxtb	r0, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    1076:	2800      	cmp	r0, #0
    1078:	db0c      	blt.n	1094 <arch_irq_disable+0x20>
  {
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    107a:	0943      	lsrs	r3, r0, #5
    107c:	4906      	ldr	r1, [pc, #24]	; (1098 <arch_irq_disable+0x24>)
    107e:	f000 001f 	and.w	r0, r0, #31
    1082:	3320      	adds	r3, #32
    1084:	2201      	movs	r2, #1
    1086:	4082      	lsls	r2, r0
    1088:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    108c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1090:	f3bf 8f6f 	isb	sy
}
    1094:	4770      	bx	lr
    1096:	bf00      	nop
    1098:	e000e100 	.word	0xe000e100

0000109c <arch_irq_is_enabled>:

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    109c:	4b05      	ldr	r3, [pc, #20]	; (10b4 <arch_irq_is_enabled+0x18>)
    109e:	0942      	lsrs	r2, r0, #5
    10a0:	f000 001f 	and.w	r0, r0, #31
    10a4:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    10a8:	2301      	movs	r3, #1
    10aa:	fa03 f000 	lsl.w	r0, r3, r0
}
    10ae:	4010      	ands	r0, r2
    10b0:	4770      	bx	lr
    10b2:	bf00      	nop
    10b4:	e000e100 	.word	0xe000e100

000010b8 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    10b8:	b240      	sxtb	r0, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    10ba:	2800      	cmp	r0, #0
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    10bc:	bfa8      	it	ge
    10be:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
		prio += _IRQ_PRIO_OFFSET;
    10c2:	f101 0101 	add.w	r1, r1, #1
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    10c6:	bfb8      	it	lt
    10c8:	4b06      	ldrlt	r3, [pc, #24]	; (10e4 <z_arm_irq_priority_set+0x2c>)
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    10ca:	ea4f 1141 	mov.w	r1, r1, lsl #5
    10ce:	bfac      	ite	ge
    10d0:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    10d4:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    10d8:	b2c9      	uxtb	r1, r1
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    10da:	bfb4      	ite	lt
    10dc:	5419      	strblt	r1, [r3, r0]
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    10de:	f880 1300 	strbge.w	r1, [r0, #768]	; 0x300
}
    10e2:	4770      	bx	lr
    10e4:	e000ed14 	.word	0xe000ed14

000010e8 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    10e8:	bf30      	wfi
    b z_SysNmiOnReset
    10ea:	f7ff bffd 	b.w	10e8 <z_SysNmiOnReset>
    10ee:	bf00      	nop

000010f0 <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    10f0:	4a0b      	ldr	r2, [pc, #44]	; (1120 <z_arm_prep_c+0x30>)
 *
 * This routine prepares for the execution of and runs C code.
 *
 */
void z_arm_prep_c(void)
{
    10f2:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    10f4:	4b0b      	ldr	r3, [pc, #44]	; (1124 <z_arm_prep_c+0x34>)
    10f6:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    10fa:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    10fc:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1100:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    1104:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    1108:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    110c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    1110:	f002 f9e2 	bl	34d8 <z_bss_zero>
	z_data_copy();
    1114:	f002 fe9e 	bl	3e54 <z_data_copy>
#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    1118:	f000 fa20 	bl	155c <z_arm_interrupt_init>
	z_cstart();
    111c:	f002 fa20 	bl	3560 <z_cstart>
    1120:	00000000 	.word	0x00000000
    1124:	e000ed00 	.word	0xe000ed00

00001128 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    1128:	4a09      	ldr	r2, [pc, #36]	; (1150 <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    112a:	490a      	ldr	r1, [pc, #40]	; (1154 <arch_swap+0x2c>)
	_current->arch.basepri = key;
    112c:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    112e:	6809      	ldr	r1, [r1, #0]
    1130:	6799      	str	r1, [r3, #120]	; 0x78

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    1132:	4909      	ldr	r1, [pc, #36]	; (1158 <arch_swap+0x30>)
	_current->arch.basepri = key;
    1134:	6758      	str	r0, [r3, #116]	; 0x74
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    1136:	684b      	ldr	r3, [r1, #4]
    1138:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    113c:	604b      	str	r3, [r1, #4]
    113e:	2300      	movs	r3, #0
    1140:	f383 8811 	msr	BASEPRI, r3
    1144:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    1148:	6893      	ldr	r3, [r2, #8]
}
    114a:	6f98      	ldr	r0, [r3, #120]	; 0x78
    114c:	4770      	bx	lr
    114e:	bf00      	nop
    1150:	20000428 	.word	0x20000428
    1154:	00005010 	.word	0x00005010
    1158:	e000ed00 	.word	0xe000ed00

0000115c <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    115c:	4912      	ldr	r1, [pc, #72]	; (11a8 <z_arm_pendsv+0x4c>)
    ldr r2, [r1, #_kernel_offset_to_current]
    115e:	688a      	ldr	r2, [r1, #8]
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    1160:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    1164:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    1166:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    116a:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    116e:	2020      	movs	r0, #32
    msr BASEPRI_MAX, r0
    1170:	f380 8812 	msr	BASEPRI_MAX, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    1174:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    1178:	4f0c      	ldr	r7, [pc, #48]	; (11ac <z_arm_pendsv+0x50>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    117a:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    117e:	698a      	ldr	r2, [r1, #24]

    str r2, [r1, #_kernel_offset_to_current]
    1180:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    1182:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    1184:	6f50      	ldr	r0, [r2, #116]	; 0x74
    movs r3, #0
    1186:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    1188:	6753      	str	r3, [r2, #116]	; 0x74
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    118a:	f380 8811 	msr	BASEPRI, r0
    isb
#endif

#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
    /* Re-program dynamic memory map */
    push {r2,lr}
    118e:	b504      	push	{r2, lr}
    mov r0, r2 /* _current thread */
    1190:	4610      	mov	r0, r2
    bl z_arm_configure_dynamic_mpu_regions
    1192:	f000 fa7f 	bl	1694 <z_arm_configure_dynamic_mpu_regions>
    pop {r2,lr}
    1196:	e8bd 4004 	ldmia.w	sp!, {r2, lr}
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    119a:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    119e:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    11a2:	f38c 8809 	msr	PSP, ip

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    11a6:	4770      	bx	lr
    ldr r1, =_kernel
    11a8:	20000428 	.word	0x20000428
    ldr v4, =_SCS_ICSR
    11ac:	e000ed04 	.word	0xe000ed04

000011b0 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    11b0:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    11b4:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    11b6:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    11ba:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    11be:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    11c0:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    11c4:	2902      	cmp	r1, #2
    beq _oops
    11c6:	d0ff      	beq.n	11c8 <_oops>

000011c8 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    11c8:	b501      	push	{r0, lr}
    push {r1, r2}
    push {r4-r11}
    mov  r1, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    bl z_do_kernel_oops
    11ca:	f003 f8f5 	bl	43b8 <z_do_kernel_oops>
     * the MSP to its value prior to entering the function
     */
    add sp, #40
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    pop {r0, pc}
    11ce:	bd01      	pop	{r0, pc}

000011d0 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    11d0:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    11d4:	9b00      	ldr	r3, [sp, #0]
    11d6:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->pc &= 0xfffffffe;
    11da:	490a      	ldr	r1, [pc, #40]	; (1204 <arch_new_thread+0x34>)
	iframe->a3 = (uint32_t)p2;
    11dc:	9b01      	ldr	r3, [sp, #4]
    11de:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    11e2:	9b02      	ldr	r3, [sp, #8]
    11e4:	f842 3c14 	str.w	r3, [r2, #-20]
	iframe->pc &= 0xfffffffe;
    11e8:	f021 0101 	bic.w	r1, r1, #1

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    11ec:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    11f0:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->pc &= 0xfffffffe;
    11f4:	f842 1c08 	str.w	r1, [r2, #-8]
		((uintptr_t)iframe - sizeof(struct __fpu_sf));
	memset(iframe, 0, sizeof(struct __fpu_sf));
#endif

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    11f8:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    11fa:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    11fc:	6502      	str	r2, [r0, #80]	; 0x50
	thread->arch.basepri = 0;
    11fe:	6743      	str	r3, [r0, #116]	; 0x74
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    1200:	4770      	bx	lr
    1202:	bf00      	nop
    1204:	00004133 	.word	0x00004133

00001208 <z_check_thread_stack_fail>:
 *         thread stack corruption, otherwise return 0.
 */
uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp)
{
#if defined(CONFIG_MULTITHREADING)
	const struct k_thread *thread = _current;
    1208:	4a09      	ldr	r2, [pc, #36]	; (1230 <z_check_thread_stack_fail+0x28>)
{
    120a:	4603      	mov	r3, r0
	const struct k_thread *thread = _current;
    120c:	6890      	ldr	r0, [r2, #8]

	if (thread == NULL) {
    120e:	b170      	cbz	r0, 122e <z_check_thread_stack_fail+0x26>
			return thread->stack_info.start;
		}
	}
#else /* CONFIG_USERSPACE */
#if defined(CONFIG_MULTITHREADING)
	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
    1210:	f113 0f16 	cmn.w	r3, #22
    1214:	6e40      	ldr	r0, [r0, #100]	; 0x64
    1216:	d005      	beq.n	1224 <z_check_thread_stack_fail+0x1c>
    1218:	f1a0 0240 	sub.w	r2, r0, #64	; 0x40
    121c:	429a      	cmp	r2, r3
    121e:	d805      	bhi.n	122c <z_check_thread_stack_fail+0x24>
    1220:	4283      	cmp	r3, r0
    1222:	d203      	bcs.n	122c <z_check_thread_stack_fail+0x24>
		return 0;
    1224:	4281      	cmp	r1, r0
    1226:	bf28      	it	cs
    1228:	2000      	movcs	r0, #0
    122a:	4770      	bx	lr
    122c:	2000      	movs	r0, #0
	}
#endif
#endif /* CONFIG_USERSPACE */

	return 0;
}
    122e:	4770      	bx	lr
    1230:	20000428 	.word	0x20000428

00001234 <arch_switch_to_main_thread>:
#endif /* CONFIG_FPU */
}

void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
    1234:	b508      	push	{r3, lr}
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    1236:	4b09      	ldr	r3, [pc, #36]	; (125c <arch_switch_to_main_thread+0x28>)
{
    1238:	460d      	mov	r5, r1
    123a:	4614      	mov	r4, r2
	_current = main_thread;
    123c:	6098      	str	r0, [r3, #8]
#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
	/*
	 * If stack protection is enabled, make sure to set it
	 * before jumping to thread entry function
	 */
	z_arm_configure_dynamic_mpu_regions(main_thread);
    123e:	f000 fa29 	bl	1694 <z_arm_configure_dynamic_mpu_regions>

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    1242:	4620      	mov	r0, r4
    1244:	f385 8809 	msr	PSP, r5
    1248:	2100      	movs	r1, #0
    124a:	b663      	cpsie	if
    124c:	f381 8811 	msr	BASEPRI, r1
    1250:	f3bf 8f6f 	isb	sy
    1254:	2200      	movs	r2, #0
    1256:	2300      	movs	r3, #0
    1258:	f002 ff6b 	bl	4132 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    125c:	20000428 	.word	0x20000428

00001260 <_isr_wrapper>:
 *
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    1260:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    1262:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    1264:	4a0b      	ldr	r2, [pc, #44]	; (1294 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    1266:	6950      	ldr	r0, [r2, #20]
	cmp r0, #0
    1268:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    126a:	bf1e      	ittt	ne
	movne	r1, #0
    126c:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    126e:	6151      	strne	r1, [r2, #20]
		blne	z_pm_save_idle_exit
    1270:	f003 fc2a 	blne	4ac8 <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    1274:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    1276:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    127a:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    127e:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    1282:	4905      	ldr	r1, [pc, #20]	; (1298 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    1284:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    1286:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    1288:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    128a:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    128e:	4903      	ldr	r1, [pc, #12]	; (129c <_isr_wrapper+0x3c>)
	bx r1
    1290:	4708      	bx	r1
    1292:	0000      	.short	0x0000
	ldr r2, =_kernel
    1294:	20000428 	.word	0x20000428
	ldr r1, =_sw_isr_table
    1298:	00004d18 	.word	0x00004d18
	ldr r1, =z_arm_int_exit
    129c:	000012a1 	.word	0x000012a1

000012a0 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    12a0:	4b04      	ldr	r3, [pc, #16]	; (12b4 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    12a2:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    12a4:	6998      	ldr	r0, [r3, #24]
	cmp r0, r1
    12a6:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    12a8:	d003      	beq.n	12b2 <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    12aa:	4903      	ldr	r1, [pc, #12]	; (12b8 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    12ac:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    12b0:	600a      	str	r2, [r1, #0]

000012b2 <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    12b2:	4770      	bx	lr
	ldr r3, =_kernel
    12b4:	20000428 	.word	0x20000428
	ldr r1, =_SCS_ICSR
    12b8:	e000ed04 	.word	0xe000ed04

000012bc <mem_manage_fault>:
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
			      bool *recoverable)
{
    12bc:	b570      	push	{r4, r5, r6, lr}
	uint32_t reason = K_ERR_ARM_MEM_GENERIC;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    12be:	4b26      	ldr	r3, [pc, #152]	; (1358 <mem_manage_fault+0x9c>)
{
    12c0:	4615      	mov	r5, r2
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    12c2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	uint32_t reason = K_ERR_ARM_MEM_GENERIC;
    12c4:	f012 0f10 	tst.w	r2, #16
		reason = K_ERR_ARM_MEM_STACKING;
		PR_FAULT_INFO("  Stacking error (context area might be"
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    12c8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	uint32_t reason = K_ERR_ARM_MEM_GENERIC;
    12ca:	bf14      	ite	ne
    12cc:	2411      	movne	r4, #17
    12ce:	2410      	moveq	r4, #16
		reason = K_ERR_ARM_MEM_UNSTACKING;
    12d0:	f012 0f08 	tst.w	r2, #8
		PR_FAULT_INFO("  Unstacking error");
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    12d4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_MEM_UNSTACKING;
    12d6:	bf18      	it	ne
    12d8:	2412      	movne	r4, #18
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    12da:	0792      	lsls	r2, r2, #30
{
    12dc:	4606      	mov	r6, r0
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    12de:	d50a      	bpl.n	12f6 <mem_manage_fault+0x3a>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		uint32_t temp = SCB->MMFAR;
    12e0:	6b58      	ldr	r0, [r3, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    12e2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    12e4:	0614      	lsls	r4, r2, #24
    12e6:	d534      	bpl.n	1352 <mem_manage_fault+0x96>
			mmfar = temp;
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
			if (from_hard_fault != 0) {
    12e8:	b119      	cbz	r1, 12f2 <mem_manage_fault+0x36>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    12ea:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    12ec:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    12f0:	629a      	str	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_MEM_DATA_ACCESS;
    12f2:	2413      	movs	r4, #19
    12f4:	e001      	b.n	12fa <mem_manage_fault+0x3e>
	uint32_t mmfar = -EINVAL;
    12f6:	f06f 0015 	mvn.w	r0, #21
			}
		}
	}
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    12fa:	4b17      	ldr	r3, [pc, #92]	; (1358 <mem_manage_fault+0x9c>)
    12fc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_MEM_INSTRUCTION_ACCESS;
    12fe:	f012 0f01 	tst.w	r2, #1
		PR_FAULT_INFO("  Instruction Access Violation");
	}
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    1302:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_MEM_INSTRUCTION_ACCESS;
    1304:	bf18      	it	ne
    1306:	2414      	movne	r4, #20
		reason = K_ERR_ARM_MEM_FP_LAZY_STATE_PRESERVATION;
    1308:	f012 0f20 	tst.w	r2, #32
	 * crossed into an area beyond the thread stack.]
	 *
	 * Data Access Violation errors may or may not be caused by
	 * thread stack overflows.
	 */
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    130c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_MEM_FP_LAZY_STATE_PRESERVATION;
    130e:	bf18      	it	ne
    1310:	2415      	movne	r4, #21
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1312:	06d2      	lsls	r2, r2, #27
    1314:	d402      	bmi.n	131c <mem_manage_fault+0x60>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    1316:	6a9b      	ldr	r3, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1318:	079b      	lsls	r3, r3, #30
    131a:	d50a      	bpl.n	1332 <mem_manage_fault+0x76>
		 * not accompanied by a data access violation error (i.e.
		 * when stack overflows due to the exception entry frame
		 * stacking): z_check_thread_stack_fail() shall be able to
		 * handle the case of 'mmfar' holding the -EINVAL value.
		 */
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
    131c:	4b0e      	ldr	r3, [pc, #56]	; (1358 <mem_manage_fault+0x9c>)
    131e:	685b      	ldr	r3, [r3, #4]
    1320:	0519      	lsls	r1, r3, #20
    1322:	d506      	bpl.n	1332 <mem_manage_fault+0x76>
			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
    1324:	4631      	mov	r1, r6
    1326:	f7ff ff6f 	bl	1208 <z_check_thread_stack_fail>
				((uint32_t) &esf[0]));

			if (min_stack_ptr) {
    132a:	b110      	cbz	r0, 1332 <mem_manage_fault+0x76>
  \details Assigns the given value to the Process Stack Pointer (PSP).
  \param [in]    topOfProcStack  Process Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
{
  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
    132c:	f380 8809 	msr	PSP, r0
				 * fatal error and a thread that corrupted its
				 * stack needs to be aborted.
				 */
				__set_PSP(min_stack_ptr);

				reason = K_ERR_STACK_CHK_FAIL;
    1330:	2402      	movs	r4, #2
	 * lazy stacking Memory Manage fault. At the time of writing, this
	 * can happen when printing.  If that's true, we should clear the
	 * pending flag in addition to the clearing the reason for the fault
	 */
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    1332:	4b09      	ldr	r3, [pc, #36]	; (1358 <mem_manage_fault+0x9c>)
    1334:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1336:	0692      	lsls	r2, r2, #26
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
    1338:	bf42      	ittt	mi
    133a:	6a5a      	ldrmi	r2, [r3, #36]	; 0x24
    133c:	f422 5200 	bicmi.w	r2, r2, #8192	; 0x2000
    1340:	625a      	strmi	r2, [r3, #36]	; 0x24
	}
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    1342:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1344:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    1348:	629a      	str	r2, [r3, #40]	; 0x28

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf, true);
    134a:	2300      	movs	r3, #0
    134c:	702b      	strb	r3, [r5, #0]

	return reason;
}
    134e:	4620      	mov	r0, r4
    1350:	bd70      	pop	{r4, r5, r6, pc}
	uint32_t mmfar = -EINVAL;
    1352:	f06f 0015 	mvn.w	r0, #21
    1356:	e7cc      	b.n	12f2 <mem_manage_fault+0x36>
    1358:	e000ed00 	.word	0xe000ed00

0000135c <usage_fault.constprop.0>:
	uint32_t reason = K_ERR_ARM_USAGE_GENERIC;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    135c:	4b13      	ldr	r3, [pc, #76]	; (13ac <usage_fault.constprop.0+0x50>)
    135e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	uint32_t reason = K_ERR_ARM_USAGE_GENERIC;
    1360:	f012 7f00 	tst.w	r2, #33554432	; 0x2000000
		reason = K_ERR_ARM_USAGE_DIV_0;
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    1364:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	uint32_t reason = K_ERR_ARM_USAGE_GENERIC;
    1366:	bf14      	ite	ne
    1368:	201e      	movne	r0, #30
    136a:	201d      	moveq	r0, #29
		reason = K_ERR_ARM_USAGE_UNALIGNED_ACCESS;
    136c:	f012 7f80 	tst.w	r2, #16777216	; 0x1000000
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    1370:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_USAGE_UNALIGNED_ACCESS;
    1372:	bf18      	it	ne
    1374:	201f      	movne	r0, #31
		reason = K_ERR_ARM_USAGE_NO_COPROCESSOR;
    1376:	f412 2f00 	tst.w	r2, #524288	; 0x80000
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    137a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_USAGE_NO_COPROCESSOR;
    137c:	bf18      	it	ne
    137e:	2021      	movne	r0, #33	; 0x21
		reason = K_ERR_ARM_USAGE_ILLEGAL_EXC_RETURN;
    1380:	f412 2f80 	tst.w	r2, #262144	; 0x40000
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    1384:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_USAGE_ILLEGAL_EXC_RETURN;
    1386:	bf18      	it	ne
    1388:	2022      	movne	r0, #34	; 0x22
		reason = K_ERR_ARM_USAGE_ILLEGAL_EPSR;
    138a:	f412 3f00 	tst.w	r2, #131072	; 0x20000
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    138e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_USAGE_ILLEGAL_EPSR;
    1390:	bf18      	it	ne
    1392:	2023      	movne	r0, #35	; 0x23
		reason = K_ERR_ARM_USAGE_UNDEFINED_INSTRUCTION;
    1394:	f412 3f80 	tst.w	r2, #65536	; 0x10000
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    1398:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    139a:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    139e:	ea6f 4212 	mvn.w	r2, r2, lsr #16
    13a2:	629a      	str	r2, [r3, #40]	; 0x28

	return reason;
}
    13a4:	bf18      	it	ne
    13a6:	2024      	movne	r0, #36	; 0x24
    13a8:	4770      	bx	lr
    13aa:	bf00      	nop
    13ac:	e000ed00 	.word	0xe000ed00

000013b0 <bus_fault.constprop.0>:
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    13b0:	b510      	push	{r4, lr}
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    13b2:	4b19      	ldr	r3, [pc, #100]	; (1418 <bus_fault.constprop.0+0x68>)
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    13b4:	4602      	mov	r2, r0
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    13b6:	6a98      	ldr	r0, [r3, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    13b8:	6a9c      	ldr	r4, [r3, #40]	; 0x28
	uint32_t reason = K_ERR_ARM_BUS_GENERIC;
    13ba:	f410 5f80 	tst.w	r0, #4096	; 0x1000
    13be:	bf14      	ite	ne
    13c0:	2017      	movne	r0, #23
    13c2:	2016      	moveq	r0, #22
		reason = K_ERR_ARM_BUS_UNSTACKING;
    13c4:	f414 6f00 	tst.w	r4, #2048	; 0x800
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    13c8:	6a9c      	ldr	r4, [r3, #40]	; 0x28
		reason = K_ERR_ARM_BUS_UNSTACKING;
    13ca:	bf18      	it	ne
    13cc:	2018      	movne	r0, #24
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    13ce:	05a4      	lsls	r4, r4, #22
    13d0:	d509      	bpl.n	13e6 <bus_fault.constprop.0+0x36>
		STORE_xFAR(bfar, SCB->BFAR);
    13d2:	6b98      	ldr	r0, [r3, #56]	; 0x38
		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    13d4:	6a98      	ldr	r0, [r3, #40]	; 0x28
    13d6:	0400      	lsls	r0, r0, #16
    13d8:	d504      	bpl.n	13e4 <bus_fault.constprop.0+0x34>
			if (from_hard_fault != 0) {
    13da:	b11a      	cbz	r2, 13e4 <bus_fault.constprop.0+0x34>
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    13dc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    13de:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    13e2:	629a      	str	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_BUS_PRECISE_DATA_BUS;
    13e4:	2019      	movs	r0, #25
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    13e6:	4b0c      	ldr	r3, [pc, #48]	; (1418 <bus_fault.constprop.0+0x68>)
    13e8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_BUS_IMPRECISE_DATA_BUS;
    13ea:	f412 6f80 	tst.w	r2, #1024	; 0x400
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    13ee:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		reason = K_ERR_ARM_BUS_IMPRECISE_DATA_BUS;
    13f0:	bf18      	it	ne
    13f2:	201a      	movne	r0, #26
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    13f4:	05d2      	lsls	r2, r2, #23
    13f6:	d40c      	bmi.n	1412 <bus_fault.constprop.0+0x62>
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    13f8:	6a9b      	ldr	r3, [r3, #40]	; 0x28
		reason = K_ERR_ARM_BUS_FP_LAZY_STATE_PRESERVATION;
    13fa:	f413 5f00 	tst.w	r3, #8192	; 0x2000
    13fe:	bf18      	it	ne
    1400:	201c      	movne	r0, #28
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    1402:	4a05      	ldr	r2, [pc, #20]	; (1418 <bus_fault.constprop.0+0x68>)
    1404:	6a93      	ldr	r3, [r2, #40]	; 0x28
    1406:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    140a:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    140c:	2300      	movs	r3, #0
    140e:	700b      	strb	r3, [r1, #0]
}
    1410:	bd10      	pop	{r4, pc}
		reason = K_ERR_ARM_BUS_INSTRUCTION_BUS;
    1412:	201b      	movs	r0, #27
    1414:	e7f5      	b.n	1402 <bus_fault.constprop.0+0x52>
    1416:	bf00      	nop
    1418:	e000ed00 	.word	0xe000ed00

0000141c <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    141c:	b570      	push	{r4, r5, r6, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    141e:	4b45      	ldr	r3, [pc, #276]	; (1534 <z_arm_fault+0x118>)
    1420:	685b      	ldr	r3, [r3, #4]
{
    1422:	b08a      	sub	sp, #40	; 0x28
    1424:	4605      	mov	r5, r0
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    1426:	f3c3 0308 	ubfx	r3, r3, #0, #9
    142a:	2600      	movs	r6, #0
    142c:	f386 8811 	msr	BASEPRI, r6
    1430:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    1434:	f002 407f 	and.w	r0, r2, #4278190080	; 0xff000000
    1438:	f1b0 4f7f 	cmp.w	r0, #4278190080	; 0xff000000
    143c:	d111      	bne.n	1462 <z_arm_fault+0x46>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    143e:	f002 000c 	and.w	r0, r2, #12
    1442:	2808      	cmp	r0, #8
    1444:	d00d      	beq.n	1462 <z_arm_fault+0x46>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    1446:	0710      	lsls	r0, r2, #28
			ptr_esf =  (z_arch_esf_t *)psp;
    1448:	bf4c      	ite	mi
    144a:	460d      	movmi	r5, r1
			*nested_exc = true;
    144c:	2601      	movpl	r6, #1
	*recoverable = false;
    144e:	2200      	movs	r2, #0
	switch (fault) {
    1450:	3b03      	subs	r3, #3
	*recoverable = false;
    1452:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
    1456:	2b03      	cmp	r3, #3
    1458:	d805      	bhi.n	1466 <z_arm_fault+0x4a>
    145a:	e8df f003 	tbb	[pc, r3]
    145e:	5d1e      	.short	0x5d1e
    1460:	5a61      	.short	0x5a61
		return NULL;
    1462:	4635      	mov	r5, r6
    1464:	e7f3      	b.n	144e <z_arm_fault+0x32>
    1466:	2400      	movs	r4, #0
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    1468:	f89d 3007 	ldrb.w	r3, [sp, #7]
    146c:	b99b      	cbnz	r3, 1496 <z_arm_fault+0x7a>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    146e:	2220      	movs	r2, #32
    1470:	4629      	mov	r1, r5
    1472:	a802      	add	r0, sp, #8
    1474:	f002 ffc9 	bl	440a <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    1478:	9b09      	ldr	r3, [sp, #36]	; 0x24
    147a:	2e00      	cmp	r6, #0
    147c:	d054      	beq.n	1528 <z_arm_fault+0x10c>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    147e:	f3c3 0208 	ubfx	r2, r3, #0, #9
    1482:	b922      	cbnz	r2, 148e <z_arm_fault+0x72>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    1484:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    1488:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    148c:	9309      	str	r3, [sp, #36]	; 0x24

	if (IS_ENABLED(CONFIG_SIMPLIFIED_EXCEPTION_CODES) && (reason >= K_ERR_ARCH_START)) {
		reason = K_ERR_CPU_EXCEPTION;
	}

	z_arm_fatal_error(reason, &esf_copy);
    148e:	a902      	add	r1, sp, #8
    1490:	4620      	mov	r0, r4
    1492:	f002 ff8f 	bl	43b4 <z_arm_fatal_error>
}
    1496:	b00a      	add	sp, #40	; 0x28
    1498:	bd70      	pop	{r4, r5, r6, pc}
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    149a:	4b26      	ldr	r3, [pc, #152]	; (1534 <z_arm_fault+0x118>)
    149c:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    149e:	0791      	lsls	r1, r2, #30
    14a0:	d4e1      	bmi.n	1466 <z_arm_fault+0x4a>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    14a2:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    14a4:	2a00      	cmp	r2, #0
    14a6:	dbde      	blt.n	1466 <z_arm_fault+0x4a>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    14a8:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    14aa:	0052      	lsls	r2, r2, #1
    14ac:	d5db      	bpl.n	1466 <z_arm_fault+0x4a>
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    14ae:	695a      	ldr	r2, [r3, #20]
	uint16_t *ret_addr = (uint16_t *)esf->basic.pc;
    14b0:	69a9      	ldr	r1, [r5, #24]
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    14b2:	f442 7280 	orr.w	r2, r2, #256	; 0x100
    14b6:	615a      	str	r2, [r3, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    14b8:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    14bc:	f3bf 8f6f 	isb	sy
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    14c0:	695a      	ldr	r2, [r3, #20]
	uint16_t fault_insn = *(ret_addr - 1);
    14c2:	f831 1c02 	ldrh.w	r1, [r1, #-2]
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    14c6:	f422 7280 	bic.w	r2, r2, #256	; 0x100
    14ca:	615a      	str	r2, [r3, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    14cc:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    14d0:	f3bf 8f6f 	isb	sy
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    14d4:	f64d 7202 	movw	r2, #57090	; 0xdf02
    14d8:	4291      	cmp	r1, r2
    14da:	d00a      	beq.n	14f2 <z_arm_fault+0xd6>
		} else if ((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) != 0) {
    14dc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    14de:	b2d2      	uxtb	r2, r2
    14e0:	b14a      	cbz	r2, 14f6 <z_arm_fault+0xda>
			reason = mem_manage_fault(esf, 1, recoverable);
    14e2:	f10d 0207 	add.w	r2, sp, #7
    14e6:	2101      	movs	r1, #1
		reason = mem_manage_fault(esf, 0, recoverable);
    14e8:	4628      	mov	r0, r5
    14ea:	f7ff fee7 	bl	12bc <mem_manage_fault>
		reason = usage_fault(esf);
    14ee:	4604      	mov	r4, r0
		break;
    14f0:	e7ba      	b.n	1468 <z_arm_fault+0x4c>
			reason = esf->basic.r0;
    14f2:	682c      	ldr	r4, [r5, #0]
    14f4:	e7b8      	b.n	1468 <z_arm_fault+0x4c>
		} else if ((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) != 0) {
    14f6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    14f8:	f412 4f7f 	tst.w	r2, #65280	; 0xff00
    14fc:	d005      	beq.n	150a <z_arm_fault+0xee>
			reason = bus_fault(esf, 1, recoverable);
    14fe:	f10d 0107 	add.w	r1, sp, #7
    1502:	2001      	movs	r0, #1
		reason = bus_fault(esf, 0, recoverable);
    1504:	f7ff ff54 	bl	13b0 <bus_fault.constprop.0>
    1508:	e7f1      	b.n	14ee <z_arm_fault+0xd2>
		} else if ((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) != 0) {
    150a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    150c:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
    1510:	d3a9      	bcc.n	1466 <z_arm_fault+0x4a>
		reason = usage_fault(esf);
    1512:	f7ff ff23 	bl	135c <usage_fault.constprop.0>
    1516:	e7ea      	b.n	14ee <z_arm_fault+0xd2>
		reason = mem_manage_fault(esf, 0, recoverable);
    1518:	f10d 0207 	add.w	r2, sp, #7
    151c:	2100      	movs	r1, #0
    151e:	e7e3      	b.n	14e8 <z_arm_fault+0xcc>
		reason = bus_fault(esf, 0, recoverable);
    1520:	f10d 0107 	add.w	r1, sp, #7
    1524:	2000      	movs	r0, #0
    1526:	e7ed      	b.n	1504 <z_arm_fault+0xe8>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    1528:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    152c:	f023 0301 	bic.w	r3, r3, #1
    1530:	e7ac      	b.n	148c <z_arm_fault+0x70>
    1532:	bf00      	nop
    1534:	e000ed00 	.word	0xe000ed00

00001538 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    1538:	4a02      	ldr	r2, [pc, #8]	; (1544 <z_arm_fault_init+0xc>)
    153a:	6953      	ldr	r3, [r2, #20]
    153c:	f043 0310 	orr.w	r3, r3, #16
    1540:	6153      	str	r3, [r2, #20]
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
#ifdef CONFIG_TRAP_UNALIGNED_ACCESS
	SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif /* CONFIG_TRAP_UNALIGNED_ACCESS */
}
    1542:	4770      	bx	lr
    1544:	e000ed00 	.word	0xe000ed00

00001548 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    1548:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    154c:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    1550:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    1552:	4672      	mov	r2, lr
	bl z_arm_fault
    1554:	f7ff ff62 	bl	141c <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    1558:	bd01      	pop	{r0, pc}
    155a:	bf00      	nop

0000155c <z_arm_interrupt_init>:
    155c:	4804      	ldr	r0, [pc, #16]	; (1570 <z_arm_interrupt_init+0x14>)
 *
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    155e:	2300      	movs	r3, #0
    1560:	2120      	movs	r1, #32
    1562:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    1564:	3301      	adds	r3, #1
    1566:	2b27      	cmp	r3, #39	; 0x27
    1568:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    156c:	d1f9      	bne.n	1562 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    156e:	4770      	bx	lr
    1570:	e000e100 	.word	0xe000e100

00001574 <__start>:
    strb r0, [r1]
#endif /* CONFIG_DEBUG_THREAD_INFO */

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    1574:	2000      	movs	r0, #0
    msr CONTROL, r0
    1576:	f380 8814 	msr	CONTROL, r0
    isb
    157a:	f3bf 8f6f 	isb	sy
#if defined(CONFIG_PM_S2RAM)
    bl arch_pm_s2ram_resume
#endif /* CONFIG_PM_S2RAM */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    157e:	f7ff fc11 	bl	da4 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    1582:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    1584:	490d      	ldr	r1, [pc, #52]	; (15bc <__start+0x48>)
    str r0, [r1]
    1586:	6008      	str	r0, [r1, #0]
    dsb
    1588:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    158c:	480c      	ldr	r0, [pc, #48]	; (15c0 <__start+0x4c>)
    msr msp, r0
    158e:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    1592:	f000 f82b 	bl	15ec <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    1596:	2020      	movs	r0, #32
    msr BASEPRI, r0
    1598:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    159c:	4809      	ldr	r0, [pc, #36]	; (15c4 <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    159e:	f44f 6104 	mov.w	r1, #2112	; 0x840
    adds r0, r0, r1
    15a2:	1840      	adds	r0, r0, r1
    msr PSP, r0
    15a4:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    15a8:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    15ac:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    15ae:	4308      	orrs	r0, r1
    msr CONTROL, r0
    15b0:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    15b4:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    15b8:	f7ff fd9a 	bl	10f0 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    15bc:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    15c0:	20001640 	.word	0x20001640
    ldr r0, =z_interrupt_stacks
    15c4:	20000880 	.word	0x20000880

000015c8 <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    15c8:	4907      	ldr	r1, [pc, #28]	; (15e8 <z_arm_clear_arm_mpu_config+0x20>)
    15ca:	f8d1 2090 	ldr.w	r2, [r1, #144]	; 0x90

	for (i = 0; i < num_regions; i++) {
    15ce:	2300      	movs	r3, #0
	int num_regions =
    15d0:	f3c2 2207 	ubfx	r2, r2, #8, #8
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
  MPU->RASR = 0U;
    15d4:	4618      	mov	r0, r3
	for (i = 0; i < num_regions; i++) {
    15d6:	4293      	cmp	r3, r2
    15d8:	db00      	blt.n	15dc <z_arm_clear_arm_mpu_config+0x14>
		ARM_MPU_ClrRegion(i);
	}
}
    15da:	4770      	bx	lr
  MPU->RNR = rnr;
    15dc:	f8c1 3098 	str.w	r3, [r1, #152]	; 0x98
  MPU->RASR = 0U;
    15e0:	f8c1 00a0 	str.w	r0, [r1, #160]	; 0xa0
	for (i = 0; i < num_regions; i++) {
    15e4:	3301      	adds	r3, #1
    15e6:	e7f6      	b.n	15d6 <z_arm_clear_arm_mpu_config+0xe>
    15e8:	e000ed00 	.word	0xe000ed00

000015ec <z_arm_init_arch_hw_at_boot>:
 * This routine resets Cortex-M system control block
 * components and core registers.
 *
 */
void z_arm_init_arch_hw_at_boot(void)
{
    15ec:	b508      	push	{r3, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    15ee:	b672      	cpsid	i
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    15f0:	2300      	movs	r3, #0
    15f2:	f383 8813 	msr	FAULTMASK, r3

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    15f6:	f7ff ffe7 	bl	15c8 <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    15fa:	4b14      	ldr	r3, [pc, #80]	; (164c <z_arm_init_arch_hw_at_boot+0x60>)
    15fc:	f04f 32ff 	mov.w	r2, #4294967295
    1600:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
    1604:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
    1608:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    160c:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
    1610:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
    1614:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
    1618:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    161c:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    1620:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    1624:	f8c3 2184 	str.w	r2, [r3, #388]	; 0x184
    1628:	f8c3 2188 	str.w	r2, [r3, #392]	; 0x188
    162c:	f8c3 218c 	str.w	r2, [r3, #396]	; 0x18c
    1630:	f8c3 2190 	str.w	r2, [r3, #400]	; 0x190
    1634:	f8c3 2194 	str.w	r2, [r3, #404]	; 0x194
    1638:	f8c3 2198 	str.w	r2, [r3, #408]	; 0x198
    163c:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c
  __ASM volatile ("cpsie i" : : : "memory");
    1640:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    1642:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1646:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    164a:	bd08      	pop	{r3, pc}
    164c:	e000e100 	.word	0xe000e100

00001650 <z_impl_k_thread_abort>:
#include <zephyr/wait_q.h>
#include <zephyr/sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
	if (_current == thread) {
    1650:	4b08      	ldr	r3, [pc, #32]	; (1674 <z_impl_k_thread_abort+0x24>)
    1652:	689b      	ldr	r3, [r3, #8]
    1654:	4283      	cmp	r3, r0
    1656:	d10b      	bne.n	1670 <z_impl_k_thread_abort+0x20>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    1658:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    165c:	b143      	cbz	r3, 1670 <z_impl_k_thread_abort+0x20>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    165e:	4b06      	ldr	r3, [pc, #24]	; (1678 <z_impl_k_thread_abort+0x28>)
    1660:	685a      	ldr	r2, [r3, #4]
    1662:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
    1666:	605a      	str	r2, [r3, #4]
			/* Clear any system calls that may be pending
			 * as they have a higher priority than the PendSV
			 * handler and will check the stack of the thread
			 * being aborted.
			 */
			SCB->SHCSR &= ~SCB_SHCSR_SVCALLPENDED_Msk;
    1668:	6a5a      	ldr	r2, [r3, #36]	; 0x24
    166a:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    166e:	625a      	str	r2, [r3, #36]	; 0x24
		}
	}

	z_thread_abort(thread);
    1670:	f002 bb90 	b.w	3d94 <z_thread_abort>
    1674:	20000428 	.word	0x20000428
    1678:	e000ed00 	.word	0xe000ed00

0000167c <z_arm_configure_static_mpu_regions>:
	 * into account the unused SRAM area, as well.
	 */
#ifdef CONFIG_AARCH32_ARMV8_R
	arm_core_mpu_disable();
#endif
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    167c:	4b02      	ldr	r3, [pc, #8]	; (1688 <z_arm_configure_static_mpu_regions+0xc>)
    167e:	4a03      	ldr	r2, [pc, #12]	; (168c <z_arm_configure_static_mpu_regions+0x10>)
    1680:	4803      	ldr	r0, [pc, #12]	; (1690 <z_arm_configure_static_mpu_regions+0x14>)
    1682:	2101      	movs	r1, #1
    1684:	f000 b870 	b.w	1768 <arm_core_mpu_configure_static_mpu_regions>
    1688:	2000fc00 	.word	0x2000fc00
    168c:	20000000 	.word	0x20000000
    1690:	00004ed8 	.word	0x00004ed8

00001694 <z_arm_configure_dynamic_mpu_regions>:
#endif /* CONFIG_USERSPACE */
	{
		/* A supervisor thread only has the normal thread stack to
		 * protect with a stack guard.
		 */
		guard_start = thread->stack_info.start - guard_size;
    1694:	6e42      	ldr	r2, [r0, #100]	; 0x64
	}

	__ASSERT(region_num < _MAX_DYNAMIC_MPU_REGIONS_NUM,
		"Out-of-bounds error for dynamic region map.");

	dynamic_regions[region_num].start = guard_start;
    1696:	4b05      	ldr	r3, [pc, #20]	; (16ac <z_arm_configure_dynamic_mpu_regions+0x18>)
		guard_start = thread->stack_info.start - guard_size;
    1698:	3a40      	subs	r2, #64	; 0x40
	dynamic_regions[region_num].start = guard_start;
    169a:	601a      	str	r2, [r3, #0]
	dynamic_regions[region_num].size = guard_size;
	dynamic_regions[region_num].attr = K_MEM_PARTITION_P_RO_U_NA;
    169c:	4a04      	ldr	r2, [pc, #16]	; (16b0 <z_arm_configure_dynamic_mpu_regions+0x1c>)
    169e:	2140      	movs	r1, #64	; 0x40
    16a0:	e9c3 1201 	strd	r1, r2, [r3, #4]

	/* Configure the dynamic MPU regions */
#ifdef CONFIG_AARCH32_ARMV8_R
	arm_core_mpu_disable();
#endif
	arm_core_mpu_configure_dynamic_mpu_regions(dynamic_regions,
    16a4:	4618      	mov	r0, r3
    16a6:	2101      	movs	r1, #1
    16a8:	f000 b868 	b.w	177c <arm_core_mpu_configure_dynamic_mpu_regions>
    16ac:	2000029c 	.word	0x2000029c
    16b0:	150b0000 	.word	0x150b0000

000016b4 <mpu_configure_regions>:
 * sanity check of the memory regions to be programmed.
 */
static int mpu_configure_regions(const struct z_arm_mpu_partition
	regions[], uint8_t regions_num, uint8_t start_reg_index,
	bool do_sanity_check)
{
    16b4:	b5f0      	push	{r4, r5, r6, r7, lr}
#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */
}

static inline void set_region_number(uint32_t index)
{
	MPU->RNR = index;
    16b6:	4e20      	ldr	r6, [pc, #128]	; (1738 <mpu_configure_regions+0x84>)
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    16b8:	2500      	movs	r5, #0
    16ba:	428d      	cmp	r5, r1
    16bc:	da39      	bge.n	1732 <mpu_configure_regions+0x7e>
		if (regions[i].size == 0U) {
    16be:	6844      	ldr	r4, [r0, #4]
    16c0:	b374      	cbz	r4, 1720 <mpu_configure_regions+0x6c>
			continue;
		}
		/* Non-empty region. */

		if (do_sanity_check &&
    16c2:	b153      	cbz	r3, 16da <mpu_configure_regions+0x26>
	 * and greater or equal to the minimum
	 * MPU region size. Start address of the
	 * partition must align with size.
	 */
	int partition_is_valid =
		((part->size & (part->size - 1U)) == 0U)
    16c4:	f104 3cff 	add.w	ip, r4, #4294967295
		&&
		(part->size >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
		&&
    16c8:	ea14 0f0c 	tst.w	r4, ip
    16cc:	d12f      	bne.n	172e <mpu_configure_regions+0x7a>
		&&
    16ce:	2c1f      	cmp	r4, #31
    16d0:	d92d      	bls.n	172e <mpu_configure_regions+0x7a>
		((part->start & (part->size - 1U)) == 0U);
    16d2:	6807      	ldr	r7, [r0, #0]
		&&
    16d4:	ea1c 0f07 	tst.w	ip, r7
    16d8:	d129      	bne.n	172e <mpu_configure_regions+0x7a>
 * to that power-of-two value.
 */
static inline uint32_t size_to_mpu_rasr_size(uint32_t size)
{
	/* The minimal supported region size is 32 bytes */
	if (size <= 32U) {
    16da:	2c20      	cmp	r4, #32
	region_conf.base = new_region->start;
    16dc:	6807      	ldr	r7, [r0, #0]
#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
	(void) size;

	p_attr->rasr = attr->rasr_attr;
#else
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    16de:	f8d0 c008 	ldr.w	ip, [r0, #8]
				(!mpu_partition_is_valid(&regions[i]))) {
			LOG_ERR("Partition %u: sanity check failed.", i);
			return -EINVAL;
		}

		reg_index = mpu_configure_region(reg_index, &regions[i]);
    16e2:	fa5f fe82 	uxtb.w	lr, r2
	if (size <= 32U) {
    16e6:	d91e      	bls.n	1726 <mpu_configure_regions+0x72>
	if (size > (1UL << 31)) {
    16e8:	f1b4 4f00 	cmp.w	r4, #2147483648	; 0x80000000
    16ec:	d81d      	bhi.n	172a <mpu_configure_regions+0x76>
	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    16ee:	3c01      	subs	r4, #1
    16f0:	fab4 f484 	clz	r4, r4
    16f4:	f1c4 041f 	rsb	r4, r4, #31
    16f8:	0064      	lsls	r4, r4, #1
	if (index > (get_num_regions() - 1U)) {
    16fa:	f1be 0f07 	cmp.w	lr, #7
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    16fe:	ea4c 0c04 	orr.w	ip, ip, r4
    1702:	d814      	bhi.n	172e <mpu_configure_regions+0x7a>
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    1704:	f027 041f 	bic.w	r4, r7, #31
				| MPU_RBAR_VALID_Msk | index;
    1708:	4314      	orrs	r4, r2
    170a:	f044 0410 	orr.w	r4, r4, #16
    170e:	f8c6 2098 	str.w	r2, [r6, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    1712:	f8c6 409c 	str.w	r4, [r6, #156]	; 0x9c
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    1716:	f04c 0401 	orr.w	r4, ip, #1
    171a:	f8c6 40a0 	str.w	r4, [r6, #160]	; 0xa0
		if (reg_index == -EINVAL) {
			return reg_index;
		}

		/* Increment number of programmed MPU indices. */
		reg_index++;
    171e:	3201      	adds	r2, #1
	for (i = 0; i < regions_num; i++) {
    1720:	3501      	adds	r5, #1
    1722:	300c      	adds	r0, #12
    1724:	e7c9      	b.n	16ba <mpu_configure_regions+0x6>
		return REGION_32B;
    1726:	2408      	movs	r4, #8
    1728:	e7e7      	b.n	16fa <mpu_configure_regions+0x46>
		return REGION_4G;
    172a:	243e      	movs	r4, #62	; 0x3e
    172c:	e7e5      	b.n	16fa <mpu_configure_regions+0x46>
			return -EINVAL;
    172e:	f06f 0215 	mvn.w	r2, #21
	}

	return reg_index;
}
    1732:	4610      	mov	r0, r2
    1734:	bdf0      	pop	{r4, r5, r6, r7, pc}
    1736:	bf00      	nop
    1738:	e000ed00 	.word	0xe000ed00

0000173c <arm_core_mpu_enable>:
	 * background region for privileged software access if desired.
	 */
#if defined(CONFIG_MPU_DISABLE_BACKGROUND_MAP)
	MPU->CTRL = MPU_CTRL_ENABLE_Msk;
#else
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    173c:	4b04      	ldr	r3, [pc, #16]	; (1750 <arm_core_mpu_enable+0x14>)
    173e:	2205      	movs	r2, #5
    1740:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
  __ASM volatile ("dsb 0xF":::"memory");
    1744:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1748:	f3bf 8f6f 	isb	sy
#endif

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    174c:	4770      	bx	lr
    174e:	bf00      	nop
    1750:	e000ed00 	.word	0xe000ed00

00001754 <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    1754:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    1758:	4b02      	ldr	r3, [pc, #8]	; (1764 <arm_core_mpu_disable+0x10>)
    175a:	2200      	movs	r2, #0
    175c:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
}
    1760:	4770      	bx	lr
    1762:	bf00      	nop
    1764:	e000ed00 	.word	0xe000ed00

00001768 <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	*static_regions, const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    1768:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    176a:	4c03      	ldr	r4, [pc, #12]	; (1778 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    176c:	2301      	movs	r3, #1
    176e:	7822      	ldrb	r2, [r4, #0]
    1770:	f7ff ffa0 	bl	16b4 <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    1774:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    1776:	bd10      	pop	{r4, pc}
    1778:	2000045c 	.word	0x2000045c

0000177c <arm_core_mpu_configure_dynamic_mpu_regions>:
/**
 * @brief configure dynamic MPU regions.
 */
void arm_core_mpu_configure_dynamic_mpu_regions(const struct z_arm_mpu_partition
	*dynamic_regions, uint8_t regions_num)
{
    177c:	b508      	push	{r3, lr}

	/* In ARMv7-M architecture the dynamic regions are
	 * programmed on top of existing SRAM region configuration.
	 */

	mpu_reg_index = mpu_configure_regions(dynamic_regions,
    177e:	4a09      	ldr	r2, [pc, #36]	; (17a4 <arm_core_mpu_configure_dynamic_mpu_regions+0x28>)
    1780:	2300      	movs	r3, #0
    1782:	7812      	ldrb	r2, [r2, #0]
    1784:	f7ff ff96 	bl	16b4 <mpu_configure_regions>
		regions_num, mpu_reg_index, false);

	if (mpu_reg_index != -EINVAL) {
    1788:	f110 0f16 	cmn.w	r0, #22
    178c:	d002      	beq.n	1794 <arm_core_mpu_configure_dynamic_mpu_regions+0x18>
  MPU->RNR = rnr;
    178e:	4a06      	ldr	r2, [pc, #24]	; (17a8 <arm_core_mpu_configure_dynamic_mpu_regions+0x2c>)

		/* Disable the non-programmed MPU regions. */
		for (int i = mpu_reg_index; i < get_num_regions(); i++) {
    1790:	2807      	cmp	r0, #7
    1792:	dd00      	ble.n	1796 <arm_core_mpu_configure_dynamic_mpu_regions+0x1a>
		== -EINVAL) {

		__ASSERT(0, "Configuring %u dynamic MPU regions failed\n",
			regions_num);
	}
}
    1794:	bd08      	pop	{r3, pc}
    1796:	f8c2 0098 	str.w	r0, [r2, #152]	; 0x98
  MPU->RASR = 0U;
    179a:	f8c2 30a0 	str.w	r3, [r2, #160]	; 0xa0
    179e:	3001      	adds	r0, #1
    17a0:	e7f6      	b.n	1790 <arm_core_mpu_configure_dynamic_mpu_regions+0x14>
    17a2:	bf00      	nop
    17a4:	2000045c 	.word	0x2000045c
    17a8:	e000ed00 	.word	0xe000ed00

000017ac <z_arm_mpu_init>:
 */
int z_arm_mpu_init(void)
{
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    17ac:	4914      	ldr	r1, [pc, #80]	; (1800 <z_arm_mpu_init+0x54>)
    17ae:	6808      	ldr	r0, [r1, #0]
    17b0:	2808      	cmp	r0, #8
{
    17b2:	b510      	push	{r4, lr}
	if (mpu_config.num_regions > get_num_regions()) {
    17b4:	d821      	bhi.n	17fa <z_arm_mpu_init+0x4e>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    17b6:	f7ff ffcd 	bl	1754 <arm_core_mpu_disable>
    17ba:	4c12      	ldr	r4, [pc, #72]	; (1804 <z_arm_mpu_init+0x58>)
    17bc:	6849      	ldr	r1, [r1, #4]

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    17be:	2200      	movs	r2, #0
    17c0:	4290      	cmp	r0, r2
    17c2:	f101 010c 	add.w	r1, r1, #12
    17c6:	d105      	bne.n	17d4 <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    17c8:	4b0f      	ldr	r3, [pc, #60]	; (1808 <z_arm_mpu_init+0x5c>)
    17ca:	7018      	strb	r0, [r3, #0]


	arm_core_mpu_enable();
    17cc:	f7ff ffb6 	bl	173c <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    17d0:	2000      	movs	r0, #0
}
    17d2:	bd10      	pop	{r4, pc}
    17d4:	f8c4 2098 	str.w	r2, [r4, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    17d8:	f851 3c0c 	ldr.w	r3, [r1, #-12]
    17dc:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    17e0:	4313      	orrs	r3, r2
    17e2:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    17e6:	f8c4 309c 	str.w	r3, [r4, #156]	; 0x9c
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    17ea:	f851 3c04 	ldr.w	r3, [r1, #-4]
    17ee:	f043 0301 	orr.w	r3, r3, #1
    17f2:	f8c4 30a0 	str.w	r3, [r4, #160]	; 0xa0
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    17f6:	3201      	adds	r2, #1
    17f8:	e7e2      	b.n	17c0 <z_arm_mpu_init+0x14>
		return -1;
    17fa:	f04f 30ff 	mov.w	r0, #4294967295
    17fe:	e7e8      	b.n	17d2 <z_arm_mpu_init+0x26>
    1800:	00004ee4 	.word	0x00004ee4
    1804:	e000ed00 	.word	0xe000ed00
    1808:	2000045c 	.word	0x2000045c

0000180c <nordicsemi_nrf52_init>:
	__asm__ volatile(
    180c:	f04f 0220 	mov.w	r2, #32
    1810:	f3ef 8311 	mrs	r3, BASEPRI
    1814:	f382 8812 	msr	BASEPRI_MAX, r2
    1818:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    181c:	4a04      	ldr	r2, [pc, #16]	; (1830 <nordicsemi_nrf52_init+0x24>)
    181e:	2101      	movs	r1, #1
    1820:	f8c2 1540 	str.w	r1, [r2, #1344]	; 0x540
	__asm__ volatile(
    1824:	f383 8811 	msr	BASEPRI, r3
    1828:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    182c:	2000      	movs	r0, #0
    182e:	4770      	bx	lr
    1830:	4001e000 	.word	0x4001e000

00001834 <sys_arch_reboot>:
    }
    else
    {
        p_gpregret = &((volatile uint32_t *)&p_reg->GPREGRET)[0];
    }
    *p_gpregret = val;
    1834:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1838:	b2c0      	uxtb	r0, r0
    183a:	f8c3 051c 	str.w	r0, [r3, #1308]	; 0x51c
  __ASM volatile ("dsb 0xF":::"memory");
    183e:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    1842:	4905      	ldr	r1, [pc, #20]	; (1858 <sys_arch_reboot+0x24>)
    1844:	4b05      	ldr	r3, [pc, #20]	; (185c <sys_arch_reboot+0x28>)
    1846:	68ca      	ldr	r2, [r1, #12]
    1848:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    184c:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    184e:	60cb      	str	r3, [r1, #12]
    1850:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    1854:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    1856:	e7fd      	b.n	1854 <sys_arch_reboot+0x20>
    1858:	e000ed00 	.word	0xe000ed00
    185c:	05fa0004 	.word	0x05fa0004

00001860 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    1860:	b120      	cbz	r0, 186c <arch_busy_wait+0xc>
    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    1862:	4b03      	ldr	r3, [pc, #12]	; (1870 <arch_busy_wait+0x10>)
    1864:	0180      	lsls	r0, r0, #6
    1866:	f043 0301 	orr.w	r3, r3, #1
    186a:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    186c:	4770      	bx	lr
    186e:	bf00      	nop
    1870:	00004ed0 	.word	0x00004ed0

00001874 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    1874:	4b08      	ldr	r3, [pc, #32]	; (1898 <onoff_stop+0x24>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    1876:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1878:	1ac3      	subs	r3, r0, r3
{
    187a:	460d      	mov	r5, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    187c:	4907      	ldr	r1, [pc, #28]	; (189c <onoff_stop+0x28>)
	size_t offset = (size_t)(mgr - data->mgr);
    187e:	109b      	asrs	r3, r3, #2
{
    1880:	4604      	mov	r4, r0
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    1882:	4359      	muls	r1, r3
    1884:	4806      	ldr	r0, [pc, #24]	; (18a0 <onoff_stop+0x2c>)
    1886:	2240      	movs	r2, #64	; 0x40
    1888:	f002 fe01 	bl	448e <stop>
	notify(mgr, res);
    188c:	462b      	mov	r3, r5
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    188e:	4601      	mov	r1, r0
	notify(mgr, res);
    1890:	4620      	mov	r0, r4
}
    1892:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    1896:	4718      	bx	r3
    1898:	200002bc 	.word	0x200002bc
    189c:	b6db6db7 	.word	0xb6db6db7
    18a0:	00004cb8 	.word	0x00004cb8

000018a4 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    18a4:	b573      	push	{r0, r1, r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    18a6:	4c0c      	ldr	r4, [pc, #48]	; (18d8 <onoff_start+0x34>)
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    18a8:	4a0c      	ldr	r2, [pc, #48]	; (18dc <onoff_start+0x38>)
    18aa:	2340      	movs	r3, #64	; 0x40
	size_t offset = (size_t)(mgr - data->mgr);
    18ac:	1b04      	subs	r4, r0, r4
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    18ae:	9300      	str	r3, [sp, #0]
{
    18b0:	460d      	mov	r5, r1
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    18b2:	460b      	mov	r3, r1
    18b4:	490a      	ldr	r1, [pc, #40]	; (18e0 <onoff_start+0x3c>)
	size_t offset = (size_t)(mgr - data->mgr);
    18b6:	10a4      	asrs	r4, r4, #2
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    18b8:	4361      	muls	r1, r4
{
    18ba:	4606      	mov	r6, r0
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    18bc:	4809      	ldr	r0, [pc, #36]	; (18e4 <onoff_start+0x40>)
    18be:	f002 fe13 	bl	44e8 <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    18c2:	1e01      	subs	r1, r0, #0
    18c4:	da05      	bge.n	18d2 <onoff_start+0x2e>
		notify(mgr, err);
    18c6:	4630      	mov	r0, r6
    18c8:	462b      	mov	r3, r5
	}
}
    18ca:	b002      	add	sp, #8
    18cc:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		notify(mgr, err);
    18d0:	4718      	bx	r3
}
    18d2:	b002      	add	sp, #8
    18d4:	bd70      	pop	{r4, r5, r6, pc}
    18d6:	bf00      	nop
    18d8:	200002bc 	.word	0x200002bc
    18dc:	00004555 	.word	0x00004555
    18e0:	b6db6db7 	.word	0xb6db6db7
    18e4:	00004cb8 	.word	0x00004cb8

000018e8 <generic_hfclk_stop>:
{
    18e8:	b510      	push	{r4, lr}
	__asm__ volatile(
    18ea:	f04f 0320 	mov.w	r3, #32
    18ee:	f3ef 8411 	mrs	r4, BASEPRI
    18f2:	f383 8812 	msr	BASEPRI_MAX, r3
    18f6:	f3bf 8f6f 	isb	sy
	hfclk_users &= ~HF_USER_GENERIC;
    18fa:	4a07      	ldr	r2, [pc, #28]	; (1918 <generic_hfclk_stop+0x30>)
    18fc:	6813      	ldr	r3, [r2, #0]
    18fe:	f023 0102 	bic.w	r1, r3, #2
	if (!(hfclk_users & HF_USER_BT)) {
    1902:	07db      	lsls	r3, r3, #31
	hfclk_users &= ~HF_USER_GENERIC;
    1904:	6011      	str	r1, [r2, #0]
	if (!(hfclk_users & HF_USER_BT)) {
    1906:	d402      	bmi.n	190e <generic_hfclk_stop+0x26>
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    1908:	2001      	movs	r0, #1
    190a:	f003 f840 	bl	498e <nrfx_clock_stop>
	__asm__ volatile(
    190e:	f384 8811 	msr	BASEPRI, r4
    1912:	f3bf 8f6f 	isb	sy
}
    1916:	bd10      	pop	{r4, pc}
    1918:	2000030c 	.word	0x2000030c

0000191c <clk_init>:
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    191c:	2200      	movs	r2, #0
{
    191e:	b570      	push	{r4, r5, r6, lr}
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1920:	2101      	movs	r1, #1
{
    1922:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1924:	4610      	mov	r0, r2
    1926:	f7ff fbc7 	bl	10b8 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);

	nrfx_err = nrfx_clock_init(clock_event_handler);
    192a:	480f      	ldr	r0, [pc, #60]	; (1968 <clk_init+0x4c>)
    192c:	f000 fffa 	bl	2924 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    1930:	4b0e      	ldr	r3, [pc, #56]	; (196c <clk_init+0x50>)
    1932:	4298      	cmp	r0, r3
    1934:	d115      	bne.n	1962 <clk_init+0x46>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    1936:	f003 f81d 	bl	4974 <nrfx_clock_enable>
	struct nrf_clock_control_data *data = dev->data;
    193a:	6926      	ldr	r6, [r4, #16]
	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);

		err = onoff_manager_init(get_onoff_manager(dev, i),
    193c:	490c      	ldr	r1, [pc, #48]	; (1970 <clk_init+0x54>)
    193e:	4630      	mov	r0, r6
    1940:	f002 fc51 	bl	41e6 <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    1944:	2800      	cmp	r0, #0
    1946:	db0b      	blt.n	1960 <clk_init+0x44>
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1948:	2501      	movs	r5, #1
    194a:	6435      	str	r5, [r6, #64]	; 0x40
	struct nrf_clock_control_data *data = dev->data;
    194c:	6924      	ldr	r4, [r4, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    194e:	4908      	ldr	r1, [pc, #32]	; (1970 <clk_init+0x54>)
    1950:	f104 001c 	add.w	r0, r4, #28
    1954:	f002 fc47 	bl	41e6 <onoff_manager_init>
		if (err < 0) {
    1958:	2800      	cmp	r0, #0
    195a:	db01      	blt.n	1960 <clk_init+0x44>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    195c:	64e5      	str	r5, [r4, #76]	; 0x4c
	}

	return 0;
    195e:	2000      	movs	r0, #0
}
    1960:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    1962:	f06f 0004 	mvn.w	r0, #4
    1966:	e7fb      	b.n	1960 <clk_init+0x44>
    1968:	000019a9 	.word	0x000019a9
    196c:	0bad0000 	.word	0x0bad0000
    1970:	00004f04 	.word	0x00004f04

00001974 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    1974:	b570      	push	{r4, r5, r6, lr}
    1976:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    1978:	230c      	movs	r3, #12
    197a:	4809      	ldr	r0, [pc, #36]	; (19a0 <clkstarted_handle.constprop.0+0x2c>)
    197c:	434b      	muls	r3, r1
    197e:	18c4      	adds	r4, r0, r3
	void *user_data = sub_data->user_data;
    1980:	e9d4 560e 	ldrd	r5, r6, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    1984:	3340      	adds	r3, #64	; 0x40
	sub_data->cb = NULL;
    1986:	2200      	movs	r2, #0
	set_on_state(&sub_data->flags);
    1988:	4418      	add	r0, r3
	sub_data->cb = NULL;
    198a:	63a2      	str	r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    198c:	f002 fd6c 	bl	4468 <set_on_state>
	if (callback) {
    1990:	b12d      	cbz	r5, 199e <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    1992:	4632      	mov	r2, r6
    1994:	462b      	mov	r3, r5
    1996:	4803      	ldr	r0, [pc, #12]	; (19a4 <clkstarted_handle.constprop.0+0x30>)
}
    1998:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    199c:	4718      	bx	r3
}
    199e:	bd70      	pop	{r4, r5, r6, pc}
    19a0:	200002bc 	.word	0x200002bc
    19a4:	00004cb8 	.word	0x00004cb8

000019a8 <clock_event_handler>:
	switch (event) {
    19a8:	b110      	cbz	r0, 19b0 <clock_event_handler+0x8>
    19aa:	2801      	cmp	r0, #1
    19ac:	d004      	beq.n	19b8 <clock_event_handler+0x10>
    19ae:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    19b0:	4b03      	ldr	r3, [pc, #12]	; (19c0 <clock_event_handler+0x18>)
    19b2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    19b4:	075b      	lsls	r3, r3, #29
    19b6:	d101      	bne.n	19bc <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    19b8:	f7ff bfdc 	b.w	1974 <clkstarted_handle.constprop.0>
}
    19bc:	4770      	bx	lr
    19be:	bf00      	nop
    19c0:	200002bc 	.word	0x200002bc

000019c4 <generic_hfclk_start>:
{
    19c4:	b508      	push	{r3, lr}
	__asm__ volatile(
    19c6:	f04f 0320 	mov.w	r3, #32
    19ca:	f3ef 8111 	mrs	r1, BASEPRI
    19ce:	f383 8812 	msr	BASEPRI_MAX, r3
    19d2:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    19d6:	4a12      	ldr	r2, [pc, #72]	; (1a20 <generic_hfclk_start+0x5c>)
    19d8:	6813      	ldr	r3, [r2, #0]
    19da:	f043 0002 	orr.w	r0, r3, #2
    19de:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    19e0:	07da      	lsls	r2, r3, #31
    19e2:	d408      	bmi.n	19f6 <generic_hfclk_start+0x32>
	__asm__ volatile(
    19e4:	f381 8811 	msr	BASEPRI, r1
    19e8:	f3bf 8f6f 	isb	sy
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    19ec:	2001      	movs	r0, #1
}
    19ee:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    19f2:	f000 bfa7 	b.w	2944 <nrfx_clock_start>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    19f6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    19fa:	f8d3 240c 	ldr.w	r2, [r3, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    19fe:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    1a02:	07d3      	lsls	r3, r2, #31
    1a04:	d5ee      	bpl.n	19e4 <generic_hfclk_start+0x20>
			set_on_state(get_hf_flags());
    1a06:	4807      	ldr	r0, [pc, #28]	; (1a24 <generic_hfclk_start+0x60>)
    1a08:	f002 fd2e 	bl	4468 <set_on_state>
    1a0c:	f381 8811 	msr	BASEPRI, r1
    1a10:	f3bf 8f6f 	isb	sy
		clkstarted_handle(CLOCK_DEVICE,
    1a14:	2000      	movs	r0, #0
}
    1a16:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    1a1a:	f7ff bfab 	b.w	1974 <clkstarted_handle.constprop.0>
    1a1e:	bf00      	nop
    1a20:	2000030c 	.word	0x2000030c
    1a24:	200002fc 	.word	0x200002fc

00001a28 <api_blocking_start>:
{
    1a28:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1a2a:	2200      	movs	r2, #0
    1a2c:	2301      	movs	r3, #1
    1a2e:	e9cd 2302 	strd	r2, r3, [sp, #8]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1a32:	4a09      	ldr	r2, [pc, #36]	; (1a58 <api_blocking_start+0x30>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1a34:	f8cd d000 	str.w	sp, [sp]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1a38:	466b      	mov	r3, sp
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1a3a:	f8cd d004 	str.w	sp, [sp, #4]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1a3e:	f002 fd82 	bl	4546 <api_start>
	if (err < 0) {
    1a42:	2800      	cmp	r0, #0
    1a44:	db05      	blt.n	1a52 <api_blocking_start+0x2a>
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm1 = { .val = timeout };
		return (int) arch_syscall_invoke3(parm0.x, parm1.split.lo, parm1.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    1a46:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    1a4a:	2300      	movs	r3, #0
    1a4c:	4668      	mov	r0, sp
    1a4e:	f001 febf 	bl	37d0 <z_impl_k_sem_take>
}
    1a52:	b005      	add	sp, #20
    1a54:	f85d fb04 	ldr.w	pc, [sp], #4
    1a58:	0000456d 	.word	0x0000456d

00001a5c <lfclk_start>:
{
    1a5c:	b510      	push	{r4, lr}
	if (!once) {
    1a5e:	4c07      	ldr	r4, [pc, #28]	; (1a7c <lfclk_start+0x20>)
    1a60:	7823      	ldrb	r3, [r4, #0]
    1a62:	b92b      	cbnz	r3, 1a70 <lfclk_start+0x14>
	z_impl_k_busy_wait(usec_to_wait);
    1a64:	f44f 70a5 	mov.w	r0, #330	; 0x14a
    1a68:	f003 f901 	bl	4c6e <z_impl_k_busy_wait>
		once = true;
    1a6c:	2301      	movs	r3, #1
    1a6e:	7023      	strb	r3, [r4, #0]
}
    1a70:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    1a74:	2000      	movs	r0, #0
    1a76:	f000 bf65 	b.w	2944 <nrfx_clock_start>
    1a7a:	bf00      	nop
    1a7c:	2000045d 	.word	0x2000045d

00001a80 <z_nrf_clock_control_lf_on>:
{
    1a80:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    1a84:	4938      	ldr	r1, [pc, #224]	; (1b68 <z_nrf_clock_control_lf_on+0xe8>)
    1a86:	f3bf 8f5b 	dmb	ish
    1a8a:	4607      	mov	r7, r0
    1a8c:	2201      	movs	r2, #1
    1a8e:	e851 3f00 	ldrex	r3, [r1]
    1a92:	e841 2000 	strex	r0, r2, [r1]
    1a96:	2800      	cmp	r0, #0
    1a98:	d1f9      	bne.n	1a8e <z_nrf_clock_control_lf_on+0xe>
    1a9a:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    1a9e:	b933      	cbnz	r3, 1aae <z_nrf_clock_control_lf_on+0x2e>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    1aa0:	4932      	ldr	r1, [pc, #200]	; (1b6c <z_nrf_clock_control_lf_on+0xec>)
		err = onoff_request(mgr, &cli);
    1aa2:	4833      	ldr	r0, [pc, #204]	; (1b70 <z_nrf_clock_control_lf_on+0xf0>)
    1aa4:	604b      	str	r3, [r1, #4]
    1aa6:	60cb      	str	r3, [r1, #12]
    1aa8:	608a      	str	r2, [r1, #8]
    1aaa:	f002 fbaf 	bl	420c <onoff_request>
	switch (start_mode) {
    1aae:	1e7b      	subs	r3, r7, #1
    1ab0:	2b01      	cmp	r3, #1
    1ab2:	d82b      	bhi.n	1b0c <z_nrf_clock_control_lf_on+0x8c>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    1ab4:	2f01      	cmp	r7, #1
    1ab6:	d107      	bne.n	1ac8 <z_nrf_clock_control_lf_on+0x48>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    1ab8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1abc:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
    1ac0:	f003 0303 	and.w	r3, r3, #3
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    1ac4:	2b01      	cmp	r3, #1
    1ac6:	d021      	beq.n	1b0c <z_nrf_clock_control_lf_on+0x8c>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    1ac8:	f002 fff8 	bl	4abc <k_is_in_isr>
    1acc:	4605      	mov	r5, r0
    1ace:	b9f8      	cbnz	r0, 1b10 <z_nrf_clock_control_lf_on+0x90>
 */
static inline bool k_is_pre_kernel(void)
{
	extern bool z_sys_post_kernel; /* in init.c */

	return !z_sys_post_kernel;
    1ad0:	4b28      	ldr	r3, [pc, #160]	; (1b74 <z_nrf_clock_control_lf_on+0xf4>)
    1ad2:	781b      	ldrb	r3, [r3, #0]
    1ad4:	b1e3      	cbz	r3, 1b10 <z_nrf_clock_control_lf_on+0x90>
    p_reg->INTENCLR = mask;
    1ad6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1ada:	2202      	movs	r2, #2
    1adc:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
	int key = isr_mode ? irq_lock() : 0;
    1ae0:	4606      	mov	r6, r0
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1ae2:	f8df 8094 	ldr.w	r8, [pc, #148]	; 1b78 <z_nrf_clock_control_lf_on+0xf8>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    1ae6:	f04f 4480 	mov.w	r4, #1073741824	; 0x40000000
    1aea:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    1aee:	f8d4 2418 	ldr.w	r2, [r4, #1048]	; 0x418
    1af2:	03d2      	lsls	r2, r2, #15
    1af4:	d516      	bpl.n	1b24 <z_nrf_clock_control_lf_on+0xa4>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    1af6:	f003 0303 	and.w	r3, r3, #3
	while (!(nrfx_clock_is_running(d, (void *)&type)
    1afa:	2b01      	cmp	r3, #1
    1afc:	d001      	beq.n	1b02 <z_nrf_clock_control_lf_on+0x82>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    1afe:	2f01      	cmp	r7, #1
    1b00:	d110      	bne.n	1b24 <z_nrf_clock_control_lf_on+0xa4>
	if (isr_mode) {
    1b02:	b35d      	cbz	r5, 1b5c <z_nrf_clock_control_lf_on+0xdc>
    1b04:	f386 8811 	msr	BASEPRI, r6
    1b08:	f3bf 8f6f 	isb	sy
}
    1b0c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	__asm__ volatile(
    1b10:	f04f 0320 	mov.w	r3, #32
    1b14:	f3ef 8611 	mrs	r6, BASEPRI
    1b18:	f383 8812 	msr	BASEPRI_MAX, r3
    1b1c:	f3bf 8f6f 	isb	sy
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    1b20:	2501      	movs	r5, #1
    1b22:	e7de      	b.n	1ae2 <z_nrf_clock_control_lf_on+0x62>
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    1b24:	b1ad      	cbz	r5, 1b52 <z_nrf_clock_control_lf_on+0xd2>
 *
 * @param key Interrupt locking key obtained from irq_lock().
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    1b26:	4630      	mov	r0, r6
    1b28:	f7ff fa8a 	bl	1040 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    1b2c:	f8d4 3518 	ldr.w	r3, [r4, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    1b30:	2b00      	cmp	r3, #0
    1b32:	d1da      	bne.n	1aea <z_nrf_clock_control_lf_on+0x6a>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    1b34:	f8d4 2104 	ldr.w	r2, [r4, #260]	; 0x104
		    && nrf_clock_event_check(NRF_CLOCK,
    1b38:	2a00      	cmp	r2, #0
    1b3a:	d0d6      	beq.n	1aea <z_nrf_clock_control_lf_on+0x6a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    1b3c:	f8c4 3104 	str.w	r3, [r4, #260]	; 0x104
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    1b40:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    p_reg->LFCLKSRC = (uint32_t)(source);
    1b44:	2301      	movs	r3, #1
    1b46:	f8c4 3518 	str.w	r3, [r4, #1304]	; 0x518
    1b4a:	f8c8 3180 	str.w	r3, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    1b4e:	60a3      	str	r3, [r4, #8]
}
    1b50:	e7cb      	b.n	1aea <z_nrf_clock_control_lf_on+0x6a>
	return z_impl_k_sleep(timeout);
    1b52:	2100      	movs	r1, #0
    1b54:	2021      	movs	r0, #33	; 0x21
    1b56:	f002 f8fd 	bl	3d54 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    1b5a:	e7e7      	b.n	1b2c <z_nrf_clock_control_lf_on+0xac>
    p_reg->INTENSET = mask;
    1b5c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1b60:	2202      	movs	r2, #2
    1b62:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    1b66:	e7d1      	b.n	1b0c <z_nrf_clock_control_lf_on+0x8c>
    1b68:	200002b8 	.word	0x200002b8
    1b6c:	200002a8 	.word	0x200002a8
    1b70:	200002d8 	.word	0x200002d8
    1b74:	2000086e 	.word	0x2000086e
    1b78:	e000e100 	.word	0xe000e100

00001b7c <gpio_nrfx_pin_interrupt_configure>:

static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
					     gpio_pin_t pin,
					     enum gpio_int_mode mode,
					     enum gpio_int_trig trig)
{
    1b7c:	b530      	push	{r4, r5, lr}
	return port->config;
    1b7e:	6840      	ldr	r0, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    1b80:	7b05      	ldrb	r5, [r0, #12]
    1b82:	f001 041f 	and.w	r4, r1, #31
	nrfx_err_t err;
	uint8_t ch;

	if (mode == GPIO_INT_MODE_DISABLED) {
    1b86:	f5b2 1f00 	cmp.w	r2, #2097152	; 0x200000
{
    1b8a:	b085      	sub	sp, #20
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    1b8c:	ea44 1445 	orr.w	r4, r4, r5, lsl #5
	if (mode == GPIO_INT_MODE_DISABLED) {
    1b90:	d105      	bne.n	1b9e <gpio_nrfx_pin_interrupt_configure+0x22>
		nrfx_gpiote_trigger_disable(abs_pin);
    1b92:	4620      	mov	r0, r4
    1b94:	f001 f99a 	bl	2ecc <nrfx_gpiote_trigger_disable>

		return 0;
    1b98:	2000      	movs	r0, #0
	}

	nrfx_gpiote_trigger_enable(abs_pin, true);

	return 0;
}
    1b9a:	b005      	add	sp, #20
    1b9c:	bd30      	pop	{r4, r5, pc}
	nrfx_gpiote_trigger_config_t trigger_config = {
    1b9e:	2500      	movs	r5, #0
	if (mode == GPIO_INT_MODE_LEVEL) {
    1ba0:	f5b2 0f80 	cmp.w	r2, #4194304	; 0x400000
	nrfx_gpiote_trigger_config_t trigger_config = {
    1ba4:	e9cd 5502 	strd	r5, r5, [sp, #8]
	if (mode == GPIO_INT_MODE_LEVEL) {
    1ba8:	d114      	bne.n	1bd4 <gpio_nrfx_pin_interrupt_configure+0x58>
		return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
    1baa:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
	nrfx_gpiote_trigger_config_t trigger_config = {
    1bae:	bf0c      	ite	eq
    1bb0:	2304      	moveq	r3, #4
    1bb2:	2305      	movne	r3, #5
    1bb4:	f88d 3008 	strb.w	r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    1bb8:	2300      	movs	r3, #0
    1bba:	4619      	mov	r1, r3
    1bbc:	aa02      	add	r2, sp, #8
    1bbe:	4620      	mov	r0, r4
    1bc0:	f000 ffba 	bl	2b38 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    1bc4:	4b1d      	ldr	r3, [pc, #116]	; (1c3c <gpio_nrfx_pin_interrupt_configure+0xc0>)
    1bc6:	4298      	cmp	r0, r3
    1bc8:	d135      	bne.n	1c36 <gpio_nrfx_pin_interrupt_configure+0xba>
	nrfx_gpiote_trigger_enable(abs_pin, true);
    1bca:	2101      	movs	r1, #1
    1bcc:	4620      	mov	r0, r4
    1bce:	f001 f939 	bl	2e44 <nrfx_gpiote_trigger_enable>
	return 0;
    1bd2:	e7e1      	b.n	1b98 <gpio_nrfx_pin_interrupt_configure+0x1c>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    1bd4:	f1b3 6fc0 	cmp.w	r3, #100663296	; 0x6000000
    1bd8:	d022      	beq.n	1c20 <gpio_nrfx_pin_interrupt_configure+0xa4>
    1bda:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    1bde:	bf14      	ite	ne
    1be0:	2301      	movne	r3, #1
    1be2:	2302      	moveq	r3, #2
	nrfx_gpiote_trigger_config_t trigger_config = {
    1be4:	f88d 3008 	strb.w	r3, [sp, #8]
	if (!(BIT(pin) & get_port_cfg(port)->edge_sense) &&
    1be8:	6883      	ldr	r3, [r0, #8]
    1bea:	40cb      	lsrs	r3, r1
    1bec:	07d9      	lsls	r1, r3, #31
    1bee:	d4e3      	bmi.n	1bb8 <gpio_nrfx_pin_interrupt_configure+0x3c>
    1bf0:	f1b2 7fa0 	cmp.w	r2, #20971520	; 0x1400000
    1bf4:	d1e0      	bne.n	1bb8 <gpio_nrfx_pin_interrupt_configure+0x3c>
}

NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;
    1bf6:	f004 031f 	and.w	r3, r4, #31
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    1bfa:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    1bfe:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    1c02:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    1c06:	07db      	lsls	r3, r3, #31
    1c08:	d4d6      	bmi.n	1bb8 <gpio_nrfx_pin_interrupt_configure+0x3c>
		err = nrfx_gpiote_channel_get(abs_pin, &ch);
    1c0a:	f10d 0507 	add.w	r5, sp, #7
    1c0e:	4629      	mov	r1, r5
    1c10:	4620      	mov	r0, r4
    1c12:	f001 f8c3 	bl	2d9c <nrfx_gpiote_channel_get>
		if (err == NRFX_ERROR_INVALID_PARAM) {
    1c16:	4b0a      	ldr	r3, [pc, #40]	; (1c40 <gpio_nrfx_pin_interrupt_configure+0xc4>)
    1c18:	4298      	cmp	r0, r3
    1c1a:	d003      	beq.n	1c24 <gpio_nrfx_pin_interrupt_configure+0xa8>
		trigger_config.p_in_channel = &ch;
    1c1c:	9503      	str	r5, [sp, #12]
    1c1e:	e7cb      	b.n	1bb8 <gpio_nrfx_pin_interrupt_configure+0x3c>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    1c20:	2303      	movs	r3, #3
    1c22:	e7df      	b.n	1be4 <gpio_nrfx_pin_interrupt_configure+0x68>
			err = nrfx_gpiote_channel_alloc(&ch);
    1c24:	4628      	mov	r0, r5
    1c26:	f001 f907 	bl	2e38 <nrfx_gpiote_channel_alloc>
			if (err != NRFX_SUCCESS) {
    1c2a:	4b04      	ldr	r3, [pc, #16]	; (1c3c <gpio_nrfx_pin_interrupt_configure+0xc0>)
    1c2c:	4298      	cmp	r0, r3
    1c2e:	d0f5      	beq.n	1c1c <gpio_nrfx_pin_interrupt_configure+0xa0>
				return -ENOMEM;
    1c30:	f06f 000b 	mvn.w	r0, #11
    1c34:	e7b1      	b.n	1b9a <gpio_nrfx_pin_interrupt_configure+0x1e>
		return -EINVAL;
    1c36:	f06f 0015 	mvn.w	r0, #21
    1c3a:	e7ae      	b.n	1b9a <gpio_nrfx_pin_interrupt_configure+0x1e>
    1c3c:	0bad0000 	.word	0x0bad0000
    1c40:	0bad0004 	.word	0x0bad0004

00001c44 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    1c44:	b510      	push	{r4, lr}
	nrfx_err_t err;

	if (nrfx_gpiote_is_init()) {
    1c46:	f001 f8e7 	bl	2e18 <nrfx_gpiote_is_init>
    1c4a:	4604      	mov	r4, r0
    1c4c:	b968      	cbnz	r0, 1c6a <gpio_nrfx_init+0x26>
		return 0;
	}

	err = nrfx_gpiote_init(0/*not used*/);
    1c4e:	f001 f8bb 	bl	2dc8 <nrfx_gpiote_init>
	if (err != NRFX_SUCCESS) {
    1c52:	4b08      	ldr	r3, [pc, #32]	; (1c74 <gpio_nrfx_init+0x30>)
    1c54:	4298      	cmp	r0, r3
    1c56:	d10a      	bne.n	1c6e <gpio_nrfx_init+0x2a>
		return -EIO;
	}

	nrfx_gpiote_global_callback_set(nrfx_gpio_handler, NULL);
    1c58:	4807      	ldr	r0, [pc, #28]	; (1c78 <gpio_nrfx_init+0x34>)
    1c5a:	4621      	mov	r1, r4
    1c5c:	f001 f898 	bl	2d90 <nrfx_gpiote_global_callback_set>

	IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    1c60:	4622      	mov	r2, r4
    1c62:	2105      	movs	r1, #5
    1c64:	2006      	movs	r0, #6
    1c66:	f7ff fa27 	bl	10b8 <z_arm_irq_priority_set>
		return 0;
    1c6a:	2000      	movs	r0, #0
		    nrfx_isr, nrfx_gpiote_irq_handler, 0);

	return 0;
}
    1c6c:	bd10      	pop	{r4, pc}
		return -EIO;
    1c6e:	f06f 0004 	mvn.w	r0, #4
    1c72:	e7fb      	b.n	1c6c <gpio_nrfx_init+0x28>
    1c74:	0bad0000 	.word	0x0bad0000
    1c78:	00001c7d 	.word	0x00001c7d

00001c7c <nrfx_gpio_handler>:
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    1c7c:	0943      	lsrs	r3, r0, #5
{
    1c7e:	b570      	push	{r4, r5, r6, lr}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    1c80:	d107      	bne.n	1c92 <nrfx_gpio_handler+0x16>
	return list->head;
    1c82:	4b0b      	ldr	r3, [pc, #44]	; (1cb0 <nrfx_gpio_handler+0x34>)
    1c84:	6859      	ldr	r1, [r3, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    1c86:	b121      	cbz	r1, 1c92 <nrfx_gpio_handler+0x16>
	gpio_fire_callbacks(list, port, BIT(pin));
    1c88:	2501      	movs	r5, #1
	return node->next;
    1c8a:	680c      	ldr	r4, [r1, #0]
		if (cb->pin_mask & pins) {
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    1c8c:	4e09      	ldr	r6, [pc, #36]	; (1cb4 <nrfx_gpio_handler+0x38>)
    1c8e:	4085      	lsls	r5, r0
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    1c90:	b901      	cbnz	r1, 1c94 <nrfx_gpio_handler+0x18>
}
    1c92:	bd70      	pop	{r4, r5, r6, pc}
		if (cb->pin_mask & pins) {
    1c94:	688a      	ldr	r2, [r1, #8]
    1c96:	402a      	ands	r2, r5
    1c98:	d002      	beq.n	1ca0 <nrfx_gpio_handler+0x24>
			cb->handler(port, cb, cb->pin_mask & pins);
    1c9a:	684b      	ldr	r3, [r1, #4]
    1c9c:	4630      	mov	r0, r6
    1c9e:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    1ca0:	b11c      	cbz	r4, 1caa <nrfx_gpio_handler+0x2e>
    1ca2:	6823      	ldr	r3, [r4, #0]
    1ca4:	4621      	mov	r1, r4
    1ca6:	461c      	mov	r4, r3
    1ca8:	e7f2      	b.n	1c90 <nrfx_gpio_handler+0x14>
    1caa:	4623      	mov	r3, r4
    1cac:	e7fa      	b.n	1ca4 <nrfx_gpio_handler+0x28>
    1cae:	bf00      	nop
    1cb0:	20000310 	.word	0x20000310
    1cb4:	00004cd0 	.word	0x00004cd0

00001cb8 <gpio_nrfx_pin_configure>:
{
    1cb8:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
	return port->config;
    1cbc:	6847      	ldr	r7, [r0, #4]
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    1cbe:	7b3b      	ldrb	r3, [r7, #12]
    1cc0:	f001 051f 	and.w	r5, r1, #31
    1cc4:	ea45 1543 	orr.w	r5, r5, r3, lsl #5
{
    1cc8:	460e      	mov	r6, r1
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    1cca:	4628      	mov	r0, r5
    1ccc:	f10d 0103 	add.w	r1, sp, #3
{
    1cd0:	4614      	mov	r4, r2
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    1cd2:	f001 f863 	bl	2d9c <nrfx_gpiote_channel_get>
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    1cd6:	f414 3f40 	tst.w	r4, #196608	; 0x30000
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    1cda:	4680      	mov	r8, r0
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    1cdc:	d10b      	bne.n	1cf6 <gpio_nrfx_pin_configure+0x3e>
		(void)nrfx_gpiote_pin_uninit(abs_pin);
    1cde:	4628      	mov	r0, r5
    1ce0:	f001 f91c 	bl	2f1c <nrfx_gpiote_pin_uninit>
		if (free_ch) {
    1ce4:	4b3d      	ldr	r3, [pc, #244]	; (1ddc <gpio_nrfx_pin_configure+0x124>)
    1ce6:	4598      	cmp	r8, r3
    1ce8:	d103      	bne.n	1cf2 <gpio_nrfx_pin_configure+0x3a>
			err = nrfx_gpiote_channel_free(ch);
    1cea:	f89d 0003 	ldrb.w	r0, [sp, #3]
    1cee:	f001 f89d 	bl	2e2c <nrfx_gpiote_channel_free>
		return 0;
    1cf2:	2000      	movs	r0, #0
    1cf4:	e00c      	b.n	1d10 <gpio_nrfx_pin_configure+0x58>
	nrfx_gpiote_trigger_config_t trigger_config = {
    1cf6:	2300      	movs	r3, #0
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    1cf8:	4619      	mov	r1, r3
    1cfa:	aa02      	add	r2, sp, #8
    1cfc:	4628      	mov	r0, r5
	nrfx_gpiote_trigger_config_t trigger_config = {
    1cfe:	e9cd 3302 	strd	r3, r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    1d02:	f000 ff19 	bl	2b38 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    1d06:	4b35      	ldr	r3, [pc, #212]	; (1ddc <gpio_nrfx_pin_configure+0x124>)
    1d08:	4298      	cmp	r0, r3
    1d0a:	d004      	beq.n	1d16 <gpio_nrfx_pin_configure+0x5e>
		return NRF_GPIO_PIN_PULLUP;
    1d0c:	f06f 0015 	mvn.w	r0, #21
}
    1d10:	b004      	add	sp, #16
    1d12:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if (free_ch) {
    1d16:	4580      	cmp	r8, r0
    1d18:	d103      	bne.n	1d22 <gpio_nrfx_pin_configure+0x6a>
		err = nrfx_gpiote_channel_free(ch);
    1d1a:	f89d 0003 	ldrb.w	r0, [sp, #3]
    1d1e:	f001 f885 	bl	2e2c <nrfx_gpiote_channel_free>
	if (flags & GPIO_OUTPUT) {
    1d22:	03a3      	lsls	r3, r4, #14
    1d24:	d54b      	bpl.n	1dbe <gpio_nrfx_pin_configure+0x106>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    1d26:	f240 3306 	movw	r3, #774	; 0x306
    1d2a:	4023      	ands	r3, r4
    1d2c:	f5b3 7f83 	cmp.w	r3, #262	; 0x106
    1d30:	d019      	beq.n	1d66 <gpio_nrfx_pin_configure+0xae>
    1d32:	d80c      	bhi.n	1d4e <gpio_nrfx_pin_configure+0x96>
    1d34:	2b06      	cmp	r3, #6
    1d36:	d017      	beq.n	1d68 <gpio_nrfx_pin_configure+0xb0>
    1d38:	d804      	bhi.n	1d44 <gpio_nrfx_pin_configure+0x8c>
    1d3a:	b1ab      	cbz	r3, 1d68 <gpio_nrfx_pin_configure+0xb0>
    1d3c:	2b02      	cmp	r3, #2
    1d3e:	d1e5      	bne.n	1d0c <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_D0S1;
    1d40:	2304      	movs	r3, #4
    1d42:	e011      	b.n	1d68 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    1d44:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
    1d48:	d1e0      	bne.n	1d0c <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_H0S1;
    1d4a:	2301      	movs	r3, #1
    1d4c:	e00c      	b.n	1d68 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    1d4e:	f240 2202 	movw	r2, #514	; 0x202
    1d52:	4293      	cmp	r3, r2
    1d54:	d027      	beq.n	1da6 <gpio_nrfx_pin_configure+0xee>
    1d56:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
    1d5a:	d026      	beq.n	1daa <gpio_nrfx_pin_configure+0xf2>
    1d5c:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    1d60:	d1d4      	bne.n	1d0c <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_S0H1;
    1d62:	2302      	movs	r3, #2
    1d64:	e000      	b.n	1d68 <gpio_nrfx_pin_configure+0xb0>
		*drive = NRF_GPIO_PIN_H0D1;
    1d66:	2307      	movs	r3, #7
		nrfx_gpiote_output_config_t output_config = {
    1d68:	f88d 3004 	strb.w	r3, [sp, #4]
				NRF_GPIO_PIN_INPUT_CONNECT :
    1d6c:	f484 3380 	eor.w	r3, r4, #65536	; 0x10000
    1d70:	f3c3 4300 	ubfx	r3, r3, #16, #1
	if (flags & GPIO_PULL_UP) {
    1d74:	06e0      	lsls	r0, r4, #27
		nrfx_gpiote_output_config_t output_config = {
    1d76:	f88d 3005 	strb.w	r3, [sp, #5]
	} else if (flags & GPIO_PULL_DOWN) {
    1d7a:	bf54      	ite	pl
    1d7c:	f3c4 1340 	ubfxpl	r3, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    1d80:	2303      	movmi	r3, #3
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    1d82:	0321      	lsls	r1, r4, #12
		nrfx_gpiote_output_config_t output_config = {
    1d84:	f88d 3006 	strb.w	r3, [sp, #6]
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    1d88:	d511      	bpl.n	1dae <gpio_nrfx_pin_configure+0xf6>
			nrf_gpio_port_out_set(cfg->port, BIT(pin));
    1d8a:	687a      	ldr	r2, [r7, #4]
    1d8c:	2301      	movs	r3, #1
    1d8e:	40b3      	lsls	r3, r6
    p_reg->OUTSET = set_mask;
    1d90:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
		err = nrfx_gpiote_output_configure(abs_pin, &output_config, NULL);
    1d94:	2200      	movs	r2, #0
    1d96:	a901      	add	r1, sp, #4
    1d98:	4628      	mov	r0, r5
    1d9a:	f000 ff7b 	bl	2c94 <nrfx_gpiote_output_configure>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    1d9e:	4b0f      	ldr	r3, [pc, #60]	; (1ddc <gpio_nrfx_pin_configure+0x124>)
    1da0:	4298      	cmp	r0, r3
    1da2:	d0a6      	beq.n	1cf2 <gpio_nrfx_pin_configure+0x3a>
    1da4:	e7b2      	b.n	1d0c <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_D0H1;
    1da6:	2305      	movs	r3, #5
    1da8:	e7de      	b.n	1d68 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    1daa:	2303      	movs	r3, #3
    1dac:	e7dc      	b.n	1d68 <gpio_nrfx_pin_configure+0xb0>
		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
    1dae:	0362      	lsls	r2, r4, #13
			nrf_gpio_port_out_clear(cfg->port, BIT(pin));
    1db0:	bf41      	itttt	mi
    1db2:	2301      	movmi	r3, #1
    1db4:	687a      	ldrmi	r2, [r7, #4]
    1db6:	40b3      	lslmi	r3, r6
    p_reg->OUTCLR = clr_mask;
    1db8:	f8c2 350c 	strmi.w	r3, [r2, #1292]	; 0x50c
}
    1dbc:	e7ea      	b.n	1d94 <gpio_nrfx_pin_configure+0xdc>
	if (flags & GPIO_PULL_UP) {
    1dbe:	06e3      	lsls	r3, r4, #27
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    1dc0:	f04f 0300 	mov.w	r3, #0
	} else if (flags & GPIO_PULL_DOWN) {
    1dc4:	bf54      	ite	pl
    1dc6:	f3c4 1440 	ubfxpl	r4, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    1dca:	2403      	movmi	r4, #3
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    1dcc:	461a      	mov	r2, r3
    1dce:	a901      	add	r1, sp, #4
    1dd0:	4628      	mov	r0, r5
	nrfx_gpiote_input_config_t input_config = {
    1dd2:	f88d 4004 	strb.w	r4, [sp, #4]
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    1dd6:	f000 feaf 	bl	2b38 <nrfx_gpiote_input_configure>
    1dda:	e7e0      	b.n	1d9e <gpio_nrfx_pin_configure+0xe6>
    1ddc:	0bad0000 	.word	0x0bad0000

00001de0 <transfer_next_chunk>:
	spi_context_complete(ctx, dev, error);
	dev_data->busy = false;
}

static void transfer_next_chunk(const struct device *dev)
{
    1de0:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
    1de2:	4605      	mov	r5, r0
	const struct spi_nrfx_config *dev_config = dev->config;
    1de4:	6840      	ldr	r0, [r0, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    1de6:	692a      	ldr	r2, [r5, #16]
 * directions have a continuous buffer, i.e. the maximum SPI transfer that
 * can be done with DMA that handles only non-scattered buffers.
 */
static inline size_t spi_context_max_continuous_chunk(struct spi_context *ctx)
{
	if (!ctx->tx_len) {
    1de8:	6c93      	ldr	r3, [r2, #72]	; 0x48
		return ctx->rx_len;
    1dea:	6d11      	ldr	r1, [r2, #80]	; 0x50
	if (!ctx->tx_len) {
    1dec:	b9e3      	cbnz	r3, 1e28 <transfer_next_chunk+0x48>
	struct spi_context *ctx = &dev_data->ctx;
	int error = 0;

	size_t chunk_len = spi_context_max_continuous_chunk(ctx);

	if (chunk_len > 0) {
    1dee:	b1a9      	cbz	r1, 1e1c <transfer_next_chunk+0x3c>
		nrfx_spi_xfer_desc_t xfer;
		nrfx_err_t result;

		dev_data->chunk_len = chunk_len;

		xfer.p_tx_buffer = ctx->tx_buf;
    1df0:	6c54      	ldr	r4, [r2, #68]	; 0x44
		dev_data->chunk_len = chunk_len;
    1df2:	6591      	str	r1, [r2, #88]	; 0x58
		xfer.tx_length   = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
    1df4:	461e      	mov	r6, r3
		xfer.p_tx_buffer = ctx->tx_buf;
    1df6:	460b      	mov	r3, r1
		xfer.p_rx_buffer = ctx->rx_buf;
    1df8:	6cd2      	ldr	r2, [r2, #76]	; 0x4c
    1dfa:	9202      	str	r2, [sp, #8]
		xfer.tx_length   = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
    1dfc:	e9cd 4600 	strd	r4, r6, [sp]
	return !!(ctx->rx_buf && ctx->rx_len);
    1e00:	b1ea      	cbz	r2, 1e3e <transfer_next_chunk+0x5e>
    1e02:	2900      	cmp	r1, #0
    1e04:	bf18      	it	ne
    1e06:	4619      	movne	r1, r3
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    1e08:	9103      	str	r1, [sp, #12]
		result = nrfx_spi_xfer(&dev_config->spi, &xfer, 0);
    1e0a:	2200      	movs	r2, #0
    1e0c:	4669      	mov	r1, sp
    1e0e:	f001 fa51 	bl	32b4 <nrfx_spi_xfer>
		if (result == NRFX_SUCCESS) {
    1e12:	4b0d      	ldr	r3, [pc, #52]	; (1e48 <transfer_next_chunk+0x68>)
    1e14:	4298      	cmp	r0, r3
    1e16:	d014      	beq.n	1e42 <transfer_next_chunk+0x62>
			return;
		}

		error = -EIO;
    1e18:	f06f 0104 	mvn.w	r1, #4
	}

	finish_transaction(dev, error);
    1e1c:	6928      	ldr	r0, [r5, #16]
}
    1e1e:	b004      	add	sp, #16
    1e20:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	finish_transaction(dev, error);
    1e24:	f002 bd28 	b.w	4878 <finish_transaction.isra.0>
	} else if (!ctx->rx_len) {
    1e28:	6c54      	ldr	r4, [r2, #68]	; 0x44
    1e2a:	b111      	cbz	r1, 1e32 <transfer_next_chunk+0x52>
		return ctx->tx_len;
	}

	return MIN(ctx->tx_len, ctx->rx_len);
    1e2c:	428b      	cmp	r3, r1
    1e2e:	bf28      	it	cs
    1e30:	460b      	movcs	r3, r1
		return ctx->tx_len;
    1e32:	2c00      	cmp	r4, #0
		dev_data->chunk_len = chunk_len;
    1e34:	6593      	str	r3, [r2, #88]	; 0x58
    1e36:	bf14      	ite	ne
    1e38:	461e      	movne	r6, r3
    1e3a:	2600      	moveq	r6, #0
    1e3c:	e7dc      	b.n	1df8 <transfer_next_chunk+0x18>
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    1e3e:	4611      	mov	r1, r2
    1e40:	e7e2      	b.n	1e08 <transfer_next_chunk+0x28>
}
    1e42:	b004      	add	sp, #16
    1e44:	bd70      	pop	{r4, r5, r6, pc}
    1e46:	bf00      	nop
    1e48:	0bad0000 	.word	0x0bad0000

00001e4c <spi_nrfx_transceive>:

static int spi_nrfx_transceive(const struct device *dev,
			       const struct spi_config *spi_cfg,
			       const struct spi_buf_set *tx_bufs,
			       const struct spi_buf_set *rx_bufs)
{
    1e4c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1e50:	b08b      	sub	sp, #44	; 0x2c
    1e52:	4698      	mov	r8, r3
	const struct spi_nrfx_config *dev_config = dev->config;
    1e54:	6843      	ldr	r3, [r0, #4]
    1e56:	9303      	str	r3, [sp, #12]
	if ((spi_cfg->operation & SPI_LOCK_ON) &&
    1e58:	888b      	ldrh	r3, [r1, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    1e5a:	6904      	ldr	r4, [r0, #16]
    1e5c:	049b      	lsls	r3, r3, #18
{
    1e5e:	4607      	mov	r7, r0
    1e60:	460e      	mov	r6, r1
    1e62:	4691      	mov	r9, r2
    1e64:	f100 80ec 	bmi.w	2040 <spi_nrfx_transceive+0x1f4>
	return z_impl_k_sem_take(sem, timeout);
    1e68:	f04f 32ff 	mov.w	r2, #4294967295
    1e6c:	f04f 33ff 	mov.w	r3, #4294967295
    1e70:	f104 0010 	add.w	r0, r4, #16
    1e74:	f001 fcac 	bl	37d0 <z_impl_k_sem_take>
	ctx->owner = spi_cfg;
    1e78:	6066      	str	r6, [r4, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    1e7a:	f8d7 a010 	ldr.w	sl, [r7, #16]
	const struct spi_nrfx_config *dev_config = dev->config;
    1e7e:	687b      	ldr	r3, [r7, #4]
    1e80:	9301      	str	r3, [sp, #4]
	if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) {
    1e82:	f89a 305d 	ldrb.w	r3, [sl, #93]	; 0x5d
    1e86:	9302      	str	r3, [sp, #8]
    1e88:	b11b      	cbz	r3, 1e92 <spi_nrfx_transceive+0x46>
    1e8a:	f8da 3000 	ldr.w	r3, [sl]
    1e8e:	429e      	cmp	r6, r3
    1e90:	d063      	beq.n	1f5a <spi_nrfx_transceive+0x10e>
	if (spi_cfg->operation & SPI_HALF_DUPLEX) {
    1e92:	f8b6 c004 	ldrh.w	ip, [r6, #4]
    1e96:	f41c 6f00 	tst.w	ip, #2048	; 0x800
    1e9a:	f040 8100 	bne.w	209e <spi_nrfx_transceive+0x252>
	if (spi_cfg->operation & SPI_MODE_LOOP) {
    1e9e:	f01c 0f09 	tst.w	ip, #9
    1ea2:	f040 80f9 	bne.w	2098 <spi_nrfx_transceive+0x24c>
	if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
    1ea6:	f3cc 1345 	ubfx	r3, ip, #5, #6
    1eaa:	2b08      	cmp	r3, #8
    1eac:	f040 80f4 	bne.w	2098 <spi_nrfx_transceive+0x24c>
	if (spi_cfg->frequency < 125000) {
    1eb0:	6835      	ldr	r5, [r6, #0]
    1eb2:	4b8c      	ldr	r3, [pc, #560]	; (20e4 <spi_nrfx_transceive+0x298>)
    1eb4:	429d      	cmp	r5, r3
    1eb6:	f240 80ef 	bls.w	2098 <spi_nrfx_transceive+0x24c>
	config = dev_config->def_config;
    1eba:	9b01      	ldr	r3, [sp, #4]
    1ebc:	f103 0b08 	add.w	fp, r3, #8
    1ec0:	e8bb 000f 	ldmia.w	fp!, {r0, r1, r2, r3}
    1ec4:	f10d 0e14 	add.w	lr, sp, #20
    1ec8:	e8ae 000f 	stmia.w	lr!, {r0, r1, r2, r3}
    1ecc:	f8db 3000 	ldr.w	r3, [fp]
    1ed0:	f8ce 3000 	str.w	r3, [lr]
	if (frequency < 250000) {
    1ed4:	4b84      	ldr	r3, [pc, #528]	; (20e8 <spi_nrfx_transceive+0x29c>)
    1ed6:	429d      	cmp	r5, r3
    1ed8:	f240 80bb 	bls.w	2052 <spi_nrfx_transceive+0x206>
	} else if (frequency < 500000) {
    1edc:	4b83      	ldr	r3, [pc, #524]	; (20ec <spi_nrfx_transceive+0x2a0>)
    1ede:	429d      	cmp	r5, r3
    1ee0:	f240 80ba 	bls.w	2058 <spi_nrfx_transceive+0x20c>
	} else if (frequency < 1000000) {
    1ee4:	4b82      	ldr	r3, [pc, #520]	; (20f0 <spi_nrfx_transceive+0x2a4>)
    1ee6:	429d      	cmp	r5, r3
    1ee8:	f240 80b9 	bls.w	205e <spi_nrfx_transceive+0x212>
	} else if (frequency < 2000000) {
    1eec:	4b81      	ldr	r3, [pc, #516]	; (20f4 <spi_nrfx_transceive+0x2a8>)
    1eee:	429d      	cmp	r5, r3
    1ef0:	f240 80b8 	bls.w	2064 <spi_nrfx_transceive+0x218>
	} else if (frequency < 4000000) {
    1ef4:	4b80      	ldr	r3, [pc, #512]	; (20f8 <spi_nrfx_transceive+0x2ac>)
    1ef6:	429d      	cmp	r5, r3
    1ef8:	f240 80b7 	bls.w	206a <spi_nrfx_transceive+0x21e>
		return NRF_SPI_FREQ_4M;
    1efc:	4b7f      	ldr	r3, [pc, #508]	; (20fc <spi_nrfx_transceive+0x2b0>)
    1efe:	429d      	cmp	r5, r3
    1f00:	bf2c      	ite	cs
    1f02:	f04f 4500 	movcs.w	r5, #2147483648	; 0x80000000
    1f06:	f04f 4580 	movcc.w	r5, #1073741824	; 0x40000000
	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
    1f0a:	f01c 0f02 	tst.w	ip, #2
	config.frequency = get_nrf_spi_frequency(spi_cfg->frequency);
    1f0e:	9507      	str	r5, [sp, #28]
	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
    1f10:	f00c 0304 	and.w	r3, ip, #4
    1f14:	f000 80ac 	beq.w	2070 <spi_nrfx_transceive+0x224>
			return NRF_SPI_MODE_2;
    1f18:	2b00      	cmp	r3, #0
    1f1a:	bf14      	ite	ne
    1f1c:	2303      	movne	r3, #3
    1f1e:	2302      	moveq	r3, #2
	config.mode      = get_nrf_spi_mode(spi_cfg->operation);
    1f20:	f88d 3020 	strb.w	r3, [sp, #32]
	if (dev_data->initialized) {
    1f24:	9b02      	ldr	r3, [sp, #8]
	if (operation & SPI_TRANSFER_LSB) {
    1f26:	f3cc 1c00 	ubfx	ip, ip, #4, #1
	config.bit_order = get_nrf_spi_bit_order(spi_cfg->operation);
    1f2a:	f88d c021 	strb.w	ip, [sp, #33]	; 0x21
	if (dev_data->initialized) {
    1f2e:	b12b      	cbz	r3, 1f3c <spi_nrfx_transceive+0xf0>
		nrfx_spi_uninit(&dev_config->spi);
    1f30:	9801      	ldr	r0, [sp, #4]
    1f32:	f001 f96d 	bl	3210 <nrfx_spi_uninit>
		dev_data->initialized = false;
    1f36:	2300      	movs	r3, #0
    1f38:	f88a 305d 	strb.w	r3, [sl, #93]	; 0x5d
	result = nrfx_spi_init(&dev_config->spi, &config,
    1f3c:	4653      	mov	r3, sl
    1f3e:	4a70      	ldr	r2, [pc, #448]	; (2100 <spi_nrfx_transceive+0x2b4>)
    1f40:	9801      	ldr	r0, [sp, #4]
    1f42:	a905      	add	r1, sp, #20
    1f44:	f001 f8b6 	bl	30b4 <nrfx_spi_init>
	if (result != NRFX_SUCCESS) {
    1f48:	4b6e      	ldr	r3, [pc, #440]	; (2104 <spi_nrfx_transceive+0x2b8>)
    1f4a:	4298      	cmp	r0, r3
    1f4c:	f040 8094 	bne.w	2078 <spi_nrfx_transceive+0x22c>
	dev_data->initialized = true;
    1f50:	2301      	movs	r3, #1
    1f52:	f88a 305d 	strb.w	r3, [sl, #93]	; 0x5d
	ctx->config = spi_cfg;
    1f56:	f8ca 6000 	str.w	r6, [sl]
		dev_data->busy = true;
    1f5a:	2301      	movs	r3, #1
    1f5c:	f884 305c 	strb.w	r3, [r4, #92]	; 0x5c
	ctx->current_tx = tx_bufs ? tx_bufs->buffers : NULL;
    1f60:	f1b9 0f00 	cmp.w	r9, #0
    1f64:	f040 809e 	bne.w	20a4 <spi_nrfx_transceive+0x258>
    1f68:	f8c4 9034 	str.w	r9, [r4, #52]	; 0x34
	ctx->tx_count = ctx->current_tx ? tx_bufs->count : 0;
    1f6c:	2300      	movs	r3, #0
    1f6e:	63a3      	str	r3, [r4, #56]	; 0x38
		spi_context_get_next_buf(&ctx->current_tx, &ctx->tx_count,
    1f70:	f104 0248 	add.w	r2, r4, #72	; 0x48
    1f74:	f104 0138 	add.w	r1, r4, #56	; 0x38
    1f78:	f104 0034 	add.w	r0, r4, #52	; 0x34
    1f7c:	f002 fbbb 	bl	46f6 <spi_context_get_next_buf.constprop.0>
	ctx->tx_buf = (const uint8_t *)
    1f80:	6460      	str	r0, [r4, #68]	; 0x44
	ctx->current_rx = rx_bufs ? rx_bufs->buffers : NULL;
    1f82:	f1b8 0f00 	cmp.w	r8, #0
    1f86:	f040 8096 	bne.w	20b6 <spi_nrfx_transceive+0x26a>
    1f8a:	f8c4 803c 	str.w	r8, [r4, #60]	; 0x3c
	ctx->rx_count = ctx->current_rx ? rx_bufs->count : 0;
    1f8e:	2300      	movs	r3, #0
    1f90:	6423      	str	r3, [r4, #64]	; 0x40
		spi_context_get_next_buf(&ctx->current_rx, &ctx->rx_count,
    1f92:	f104 0250 	add.w	r2, r4, #80	; 0x50
    1f96:	f104 0140 	add.w	r1, r4, #64	; 0x40
    1f9a:	f104 003c 	add.w	r0, r4, #60	; 0x3c
    1f9e:	f002 fbaa 	bl	46f6 <spi_context_get_next_buf.constprop.0>
	ctx->sync_status = 0;
    1fa2:	2500      	movs	r5, #0
	_spi_context_cs_control(ctx, on, false);
    1fa4:	462a      	mov	r2, r5
	ctx->rx_buf = (uint8_t *)
    1fa6:	64e0      	str	r0, [r4, #76]	; 0x4c
	_spi_context_cs_control(ctx, on, false);
    1fa8:	2101      	movs	r1, #1
    1faa:	4620      	mov	r0, r4
	ctx->sync_status = 0;
    1fac:	6325      	str	r5, [r4, #48]	; 0x30
	_spi_context_cs_control(ctx, on, false);
    1fae:	f002 fbc9 	bl	4744 <_spi_context_cs_control>
		transfer_next_chunk(dev);
    1fb2:	4638      	mov	r0, r7
    1fb4:	f7ff ff14 	bl	1de0 <transfer_next_chunk>
static inline size_t spi_context_total_tx_len(struct spi_context *ctx)
{
	size_t n;
	size_t total_len = 0;

	for (n = 0; n < ctx->tx_count; ++n) {
    1fb8:	6ba0      	ldr	r0, [r4, #56]	; 0x38
	size_t total_len = 0;
    1fba:	462a      	mov	r2, r5
	for (n = 0; n < ctx->tx_count; ++n) {
    1fbc:	462b      	mov	r3, r5
    1fbe:	4283      	cmp	r3, r0
    1fc0:	f040 8082 	bne.w	20c8 <spi_nrfx_transceive+0x27c>
}

static inline size_t spi_context_total_rx_len(struct spi_context *ctx)
{
	size_t n;
	size_t total_len = 0;
    1fc4:	2300      	movs	r3, #0

	for (n = 0; n < ctx->rx_count; ++n) {
    1fc6:	6c25      	ldr	r5, [r4, #64]	; 0x40
    1fc8:	4619      	mov	r1, r3
    1fca:	42a9      	cmp	r1, r5
    1fcc:	f040 8083 	bne.w	20d6 <spi_nrfx_transceive+0x28a>
			timeout_ms = MAX(tx_len, rx_len) * 8 * 1000 /
    1fd0:	4293      	cmp	r3, r2
				     ctx->config->frequency;
    1fd2:	4626      	mov	r6, r4
			timeout_ms = MAX(tx_len, rx_len) * 8 * 1000 /
    1fd4:	bf38      	it	cc
    1fd6:	4613      	movcc	r3, r2
    1fd8:	f44f 52fa 	mov.w	r2, #8000	; 0x1f40
    1fdc:	fb02 f503 	mul.w	r5, r2, r3
				     ctx->config->frequency;
    1fe0:	f856 3b20 	ldr.w	r3, [r6], #32
			/* Faster algorithm but source is first multiplied by target frequency
			 * and it can overflow even though final result would not overflow.
			 * Kconfig option shall prevent use of this algorithm when there is a
			 * risk of overflow.
			 */
			return ((t * to_hz + off) / from_hz);
    1fe4:	f04f 0800 	mov.w	r8, #0
			timeout_ms = MAX(tx_len, rx_len) * 8 * 1000 /
    1fe8:	681b      	ldr	r3, [r3, #0]
    1fea:	fbb5 f5f3 	udiv	r5, r5, r3
    1fee:	f44f 4c00 	mov.w	ip, #32768	; 0x8000
			timeout_ms += CONFIG_SPI_COMPLETION_TIMEOUT_TOLERANCE;
    1ff2:	35c8      	adds	r5, #200	; 0xc8
    1ff4:	4641      	mov	r1, r8
    1ff6:	f240 30e7 	movw	r0, #999	; 0x3e7
    1ffa:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    1ffe:	2300      	movs	r3, #0
    2000:	fbe5 010c 	umlal	r0, r1, r5, ip
    2004:	f7fe f86a 	bl	dc <__aeabi_uldivmod>
    2008:	4602      	mov	r2, r0
    200a:	460b      	mov	r3, r1
    200c:	4630      	mov	r0, r6
    200e:	f001 fbdf 	bl	37d0 <z_impl_k_sem_take>
		if (k_sem_take(&ctx->sync, timeout)) {
    2012:	b918      	cbnz	r0, 201c <spi_nrfx_transceive+0x1d0>
		status = ctx->sync_status;
    2014:	6b25      	ldr	r5, [r4, #48]	; 0x30
		if (error == -ETIMEDOUT) {
    2016:	f115 0f74 	cmn.w	r5, #116	; 0x74
    201a:	d12f      	bne.n	207c <spi_nrfx_transceive+0x230>
			nrfx_spi_uninit(&dev_config->spi);
    201c:	9803      	ldr	r0, [sp, #12]
			dev_data->chunk_len = 0;
    201e:	f8c4 8058 	str.w	r8, [r4, #88]	; 0x58
			nrfx_spi_uninit(&dev_config->spi);
    2022:	f001 f8f5 	bl	3210 <nrfx_spi_uninit>
			dev_data->initialized = false;
    2026:	f884 805d 	strb.w	r8, [r4, #93]	; 0x5d
			finish_transaction(dev, -ETIMEDOUT);
    202a:	6938      	ldr	r0, [r7, #16]
    202c:	f06f 0173 	mvn.w	r1, #115	; 0x73
    2030:	f002 fc22 	bl	4878 <finish_transaction.isra.0>
		(void) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_SEM_RESET);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_reset(sem);
    2034:	4630      	mov	r0, r6
    2036:	f001 fbf3 	bl	3820 <z_impl_k_sem_reset>
		error = spi_context_wait_for_completion(&dev_data->ctx);
    203a:	f06f 0573 	mvn.w	r5, #115	; 0x73
}
    203e:	e01d      	b.n	207c <spi_nrfx_transceive+0x230>
	if ((spi_cfg->operation & SPI_LOCK_ON) &&
    2040:	69a3      	ldr	r3, [r4, #24]
    2042:	2b00      	cmp	r3, #0
    2044:	f47f af10 	bne.w	1e68 <spi_nrfx_transceive+0x1c>
		(k_sem_count_get(&ctx->lock) == 0) &&
    2048:	6863      	ldr	r3, [r4, #4]
    204a:	4299      	cmp	r1, r3
    204c:	f47f af0c 	bne.w	1e68 <spi_nrfx_transceive+0x1c>
    2050:	e713      	b.n	1e7a <spi_nrfx_transceive+0x2e>
		return NRF_SPI_FREQ_125K;
    2052:	f04f 7500 	mov.w	r5, #33554432	; 0x2000000
    2056:	e758      	b.n	1f0a <spi_nrfx_transceive+0xbe>
		return NRF_SPI_FREQ_250K;
    2058:	f04f 6580 	mov.w	r5, #67108864	; 0x4000000
    205c:	e755      	b.n	1f0a <spi_nrfx_transceive+0xbe>
		return NRF_SPI_FREQ_500K;
    205e:	f04f 6500 	mov.w	r5, #134217728	; 0x8000000
    2062:	e752      	b.n	1f0a <spi_nrfx_transceive+0xbe>
		return NRF_SPI_FREQ_1M;
    2064:	f04f 5580 	mov.w	r5, #268435456	; 0x10000000
    2068:	e74f      	b.n	1f0a <spi_nrfx_transceive+0xbe>
		return NRF_SPI_FREQ_2M;
    206a:	f04f 5500 	mov.w	r5, #536870912	; 0x20000000
    206e:	e74c      	b.n	1f0a <spi_nrfx_transceive+0xbe>
		if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
    2070:	3b00      	subs	r3, #0
    2072:	bf18      	it	ne
    2074:	2301      	movne	r3, #1
    2076:	e753      	b.n	1f20 <spi_nrfx_transceive+0xd4>
		return -EIO;
    2078:	f06f 0504 	mvn.w	r5, #4
	if (!(ctx->config->operation & SPI_LOCK_ON)) {
    207c:	6823      	ldr	r3, [r4, #0]
    207e:	889b      	ldrh	r3, [r3, #4]
    2080:	f413 5300 	ands.w	r3, r3, #8192	; 0x2000
    2084:	d104      	bne.n	2090 <spi_nrfx_transceive+0x244>
		ctx->owner = NULL;
    2086:	6063      	str	r3, [r4, #4]
	z_impl_k_sem_give(sem);
    2088:	f104 0010 	add.w	r0, r4, #16
    208c:	f001 fb80 	bl	3790 <z_impl_k_sem_give>
	return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
}
    2090:	4628      	mov	r0, r5
    2092:	b00b      	add	sp, #44	; 0x2c
    2094:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		return -EINVAL;
    2098:	f06f 0515 	mvn.w	r5, #21
    209c:	e7ee      	b.n	207c <spi_nrfx_transceive+0x230>
		return -ENOTSUP;
    209e:	f06f 0585 	mvn.w	r5, #133	; 0x85
    20a2:	e7eb      	b.n	207c <spi_nrfx_transceive+0x230>
	ctx->current_tx = tx_bufs ? tx_bufs->buffers : NULL;
    20a4:	f8d9 3000 	ldr.w	r3, [r9]
    20a8:	6363      	str	r3, [r4, #52]	; 0x34
	ctx->tx_count = ctx->current_tx ? tx_bufs->count : 0;
    20aa:	2b00      	cmp	r3, #0
    20ac:	f43f af5e 	beq.w	1f6c <spi_nrfx_transceive+0x120>
    20b0:	f8d9 3004 	ldr.w	r3, [r9, #4]
    20b4:	e75b      	b.n	1f6e <spi_nrfx_transceive+0x122>
	ctx->current_rx = rx_bufs ? rx_bufs->buffers : NULL;
    20b6:	f8d8 3000 	ldr.w	r3, [r8]
    20ba:	63e3      	str	r3, [r4, #60]	; 0x3c
	ctx->rx_count = ctx->current_rx ? rx_bufs->count : 0;
    20bc:	2b00      	cmp	r3, #0
    20be:	f43f af66 	beq.w	1f8e <spi_nrfx_transceive+0x142>
    20c2:	f8d8 3004 	ldr.w	r3, [r8, #4]
    20c6:	e763      	b.n	1f90 <spi_nrfx_transceive+0x144>
		total_len += ctx->current_tx[n].len;
    20c8:	6b61      	ldr	r1, [r4, #52]	; 0x34
    20ca:	eb01 01c3 	add.w	r1, r1, r3, lsl #3
	for (n = 0; n < ctx->tx_count; ++n) {
    20ce:	3301      	adds	r3, #1
		total_len += ctx->current_tx[n].len;
    20d0:	6849      	ldr	r1, [r1, #4]
    20d2:	440a      	add	r2, r1
	for (n = 0; n < ctx->tx_count; ++n) {
    20d4:	e773      	b.n	1fbe <spi_nrfx_transceive+0x172>
		total_len += ctx->current_rx[n].len;
    20d6:	6be0      	ldr	r0, [r4, #60]	; 0x3c
    20d8:	eb00 00c1 	add.w	r0, r0, r1, lsl #3
	for (n = 0; n < ctx->rx_count; ++n) {
    20dc:	3101      	adds	r1, #1
		total_len += ctx->current_rx[n].len;
    20de:	6840      	ldr	r0, [r0, #4]
    20e0:	4403      	add	r3, r0
	for (n = 0; n < ctx->rx_count; ++n) {
    20e2:	e772      	b.n	1fca <spi_nrfx_transceive+0x17e>
    20e4:	0001e847 	.word	0x0001e847
    20e8:	0003d08f 	.word	0x0003d08f
    20ec:	0007a11f 	.word	0x0007a11f
    20f0:	000f423f 	.word	0x000f423f
    20f4:	001e847f 	.word	0x001e847f
    20f8:	003d08ff 	.word	0x003d08ff
    20fc:	007a1200 	.word	0x007a1200
    2100:	00004899 	.word	0x00004899
    2104:	0bad0000 	.word	0x0bad0000

00002108 <compare_int_lock>:
	return 0;
#endif
}

static bool compare_int_lock(int32_t chan)
{
    2108:	b570      	push	{r4, r5, r6, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    210a:	2301      	movs	r3, #1
    210c:	4083      	lsls	r3, r0
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    210e:	4a0e      	ldr	r2, [pc, #56]	; (2148 <compare_int_lock+0x40>)
    2110:	f3bf 8f5b 	dmb	ish
    2114:	43dc      	mvns	r4, r3
    2116:	e852 1f00 	ldrex	r1, [r2]
    211a:	ea01 0504 	and.w	r5, r1, r4
    211e:	e842 5600 	strex	r6, r5, [r2]
    2122:	2e00      	cmp	r6, #0
    2124:	d1f7      	bne.n	2116 <compare_int_lock+0xe>
    2126:	f3bf 8f5b 	dmb	ish

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    212a:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    212e:	4082      	lsls	r2, r0
    p_reg->INTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->INTENCLR = mask;
    2130:	4806      	ldr	r0, [pc, #24]	; (214c <compare_int_lock+0x44>)
    2132:	f8c0 2308 	str.w	r2, [r0, #776]	; 0x308
  __ASM volatile ("dmb 0xF":::"memory");
    2136:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    213a:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    213e:	420b      	tst	r3, r1
}
    2140:	bf14      	ite	ne
    2142:	2001      	movne	r0, #1
    2144:	2000      	moveq	r0, #0
    2146:	bd70      	pop	{r4, r5, r6, pc}
    2148:	20000320 	.word	0x20000320
    214c:	40011000 	.word	0x40011000

00002150 <sys_clock_timeout_handler>:
}

static void sys_clock_timeout_handler(int32_t chan,
				      uint64_t expire_time,
				      void *user_data)
{
    2150:	b470      	push	{r4, r5, r6}
	uint32_t cc_value = absolute_time_to_cc(expire_time);
	uint32_t dticks = (uint32_t)(expire_time - last_count) / CYC_PER_TICK;
    2152:	490e      	ldr	r1, [pc, #56]	; (218c <sys_clock_timeout_handler+0x3c>)
    2154:	e9d1 3400 	ldrd	r3, r4, [r1]
    2158:	1ad0      	subs	r0, r2, r3

	last_count += dticks * CYC_PER_TICK;
    215a:	18c3      	adds	r3, r0, r3
    215c:	f144 0400 	adc.w	r4, r4, #0
	return absolute_time & COUNTER_MAX;
    2160:	f022 467f 	bic.w	r6, r2, #4278190080	; 0xff000000
	last_count += dticks * CYC_PER_TICK;
    2164:	e9c1 3400 	strd	r3, r4, [r1]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    2168:	f5a6 1300 	sub.w	r3, r6, #2097152	; 0x200000
	if (in_anchor_range(cc_value)) {
    216c:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    2170:	d209      	bcs.n	2186 <sys_clock_timeout_handler+0x36>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    2172:	4b07      	ldr	r3, [pc, #28]	; (2190 <sys_clock_timeout_handler+0x40>)
    2174:	681b      	ldr	r3, [r3, #0]
    2176:	0a1a      	lsrs	r2, r3, #8
    2178:	061b      	lsls	r3, r3, #24
    217a:	199c      	adds	r4, r3, r6
    217c:	4b05      	ldr	r3, [pc, #20]	; (2194 <sys_clock_timeout_handler+0x44>)
    217e:	f142 0500 	adc.w	r5, r2, #0
    2182:	e9c3 4500 	strd	r4, r5, [r3]
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(dticks);
}
    2186:	bc70      	pop	{r4, r5, r6}
	sys_clock_announce(dticks);
    2188:	f001 bf3a 	b.w	4000 <sys_clock_announce>
    218c:	20000148 	.word	0x20000148
    2190:	20000324 	.word	0x20000324
    2194:	20000150 	.word	0x20000150

00002198 <compare_int_unlock>:
	if (key) {
    2198:	b311      	cbz	r1, 21e0 <compare_int_unlock+0x48>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    219a:	f3bf 8f5b 	dmb	ish
		atomic_or(&int_mask, BIT(chan));
    219e:	2301      	movs	r3, #1
    21a0:	4a10      	ldr	r2, [pc, #64]	; (21e4 <compare_int_unlock+0x4c>)
    21a2:	4083      	lsls	r3, r0
    21a4:	e852 cf00 	ldrex	ip, [r2]
    21a8:	ea4c 0c03 	orr.w	ip, ip, r3
    21ac:	e842 c100 	strex	r1, ip, [r2]
    21b0:	2900      	cmp	r1, #0
    21b2:	d1f7      	bne.n	21a4 <compare_int_unlock+0xc>
    21b4:	f3bf 8f5b 	dmb	ish
    p_reg->INTENSET = mask;
    21b8:	4a0b      	ldr	r2, [pc, #44]	; (21e8 <compare_int_unlock+0x50>)
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    21ba:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    21be:	4083      	lsls	r3, r0
    21c0:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    21c4:	4b09      	ldr	r3, [pc, #36]	; (21ec <compare_int_unlock+0x54>)
    21c6:	f3bf 8f5b 	dmb	ish
    21ca:	681b      	ldr	r3, [r3, #0]
    21cc:	f3bf 8f5b 	dmb	ish
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    21d0:	40c3      	lsrs	r3, r0
    21d2:	07db      	lsls	r3, r3, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    21d4:	bf42      	ittt	mi
    21d6:	4b06      	ldrmi	r3, [pc, #24]	; (21f0 <compare_int_unlock+0x58>)
    21d8:	f44f 3200 	movmi.w	r2, #131072	; 0x20000
    21dc:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
}
    21e0:	4770      	bx	lr
    21e2:	bf00      	nop
    21e4:	20000320 	.word	0x20000320
    21e8:	40011000 	.word	0x40011000
    21ec:	2000031c 	.word	0x2000031c
    21f0:	e000e100 	.word	0xe000e100

000021f4 <z_nrf_rtc_timer_read>:
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    21f4:	4b0d      	ldr	r3, [pc, #52]	; (222c <z_nrf_rtc_timer_read+0x38>)
    21f6:	6818      	ldr	r0, [r3, #0]
    21f8:	0a01      	lsrs	r1, r0, #8
    21fa:	0600      	lsls	r0, r0, #24
  __ASM volatile ("dmb 0xF":::"memory");
    21fc:	f3bf 8f5f 	dmb	sy
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type const * p_reg)
{
     return p_reg->COUNTER;
    2200:	4b0b      	ldr	r3, [pc, #44]	; (2230 <z_nrf_rtc_timer_read+0x3c>)
    2202:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	val += cntr;
    2206:	1818      	adds	r0, r3, r0
    2208:	f141 0100 	adc.w	r1, r1, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    220c:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    2210:	d20a      	bcs.n	2228 <z_nrf_rtc_timer_read+0x34>
		if (val < anchor) {
    2212:	4b08      	ldr	r3, [pc, #32]	; (2234 <z_nrf_rtc_timer_read+0x40>)
    2214:	e9d3 2300 	ldrd	r2, r3, [r3]
    2218:	4290      	cmp	r0, r2
    221a:	eb71 0303 	sbcs.w	r3, r1, r3
    221e:	d203      	bcs.n	2228 <z_nrf_rtc_timer_read+0x34>
			val += COUNTER_SPAN;
    2220:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    2224:	f141 0100 	adc.w	r1, r1, #0
}
    2228:	4770      	bx	lr
    222a:	bf00      	nop
    222c:	20000324 	.word	0x20000324
    2230:	40011000 	.word	0x40011000
    2234:	20000150 	.word	0x20000150

00002238 <compare_set>:
{
    2238:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    223c:	4616      	mov	r6, r2
    223e:	461f      	mov	r7, r3
    2240:	4604      	mov	r4, r0
	key = compare_int_lock(chan);
    2242:	f7ff ff61 	bl	2108 <compare_int_lock>
    2246:	9000      	str	r0, [sp, #0]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    2248:	f7ff ffd4 	bl	21f4 <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    224c:	42b0      	cmp	r0, r6
    224e:	eb71 0307 	sbcs.w	r3, r1, r7
    2252:	d251      	bcs.n	22f8 <compare_set+0xc0>
		if (target_time - curr_time > COUNTER_HALF_SPAN) {
    2254:	4b3a      	ldr	r3, [pc, #232]	; (2340 <compare_set+0x108>)
    2256:	1a30      	subs	r0, r6, r0
    2258:	eb67 0101 	sbc.w	r1, r7, r1
    225c:	4298      	cmp	r0, r3
    225e:	f171 0100 	sbcs.w	r1, r1, #0
    2262:	d26a      	bcs.n	233a <compare_set+0x102>
		if (target_time != cc_data[chan].target_time) {
    2264:	4b37      	ldr	r3, [pc, #220]	; (2344 <compare_set+0x10c>)
    2266:	eb03 1304 	add.w	r3, r3, r4, lsl #4
    226a:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
    226e:	429f      	cmp	r7, r3
    2270:	bf08      	it	eq
    2272:	4296      	cmpeq	r6, r2
    2274:	d04e      	beq.n	2314 <compare_set+0xdc>
    p_reg->EVTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    2276:	4934      	ldr	r1, [pc, #208]	; (2348 <compare_set+0x110>)
	nrf_rtc_event_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2278:	f44f 3980 	mov.w	r9, #65536	; 0x10000
	return nrf_rtc_event_check(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    227c:	f104 0550 	add.w	r5, r4, #80	; 0x50
	nrf_rtc_event_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2280:	fa09 f904 	lsl.w	r9, r9, r4
	return nrf_rtc_event_check(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    2284:	00ad      	lsls	r5, r5, #2
    2286:	f8c1 9348 	str.w	r9, [r1, #840]	; 0x348
	event_clear(chan);
    228a:	4620      	mov	r0, r4
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    228c:	b2ad      	uxth	r5, r5
    228e:	f002 fb50 	bl	4932 <event_clear>
	return absolute_time & COUNTER_MAX;
    2292:	f026 4b7f 	bic.w	fp, r6, #4278190080	; 0xff000000
    2296:	f105 4580 	add.w	r5, r5, #1073741824	; 0x40000000
    p_reg->CC[ch] = cc_val;
    229a:	f504 73a8 	add.w	r3, r4, #336	; 0x150
		if (counter_sub(cc_val, now + MIN_CYCLES_FROM_NOW) >
    229e:	4a2b      	ldr	r2, [pc, #172]	; (234c <compare_set+0x114>)
    22a0:	9301      	str	r3, [sp, #4]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    22a2:	f505 3588 	add.w	r5, r5, #69632	; 0x11000
	uint32_t cc_val = req_cc;
    22a6:	46dc      	mov	ip, fp
	uint32_t cc_inc = MIN_CYCLES_FROM_NOW;
    22a8:	f04f 0a03 	mov.w	sl, #3
    p_reg->CC[ch] = cc_val;
    22ac:	9b01      	ldr	r3, [sp, #4]
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    22ae:	f02c 407f 	bic.w	r0, ip, #4278190080	; 0xff000000
    22b2:	f841 0023 	str.w	r0, [r1, r3, lsl #2]
    p_reg->EVTENSET = mask;
    22b6:	f8c1 9344 	str.w	r9, [r1, #836]	; 0x344
     return p_reg->COUNTER;
    22ba:	f8d1 8504 	ldr.w	r8, [r1, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    22be:	f06f 0002 	mvn.w	r0, #2
    22c2:	eba0 0008 	sub.w	r0, r0, r8
    22c6:	4460      	add	r0, ip
    22c8:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
		if (counter_sub(cc_val, now + MIN_CYCLES_FROM_NOW) >
    22cc:	4290      	cmp	r0, r2
    22ce:	d921      	bls.n	2314 <compare_set+0xdc>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    22d0:	6828      	ldr	r0, [r5, #0]
			if (event_check(chan)) {
    22d2:	b160      	cbz	r0, 22ee <compare_set+0xb6>
     return p_reg->COUNTER;
    22d4:	f8d1 8504 	ldr.w	r8, [r1, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    22d8:	eba8 000b 	sub.w	r0, r8, fp
    22dc:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
				if (counter_sub(now, req_cc) > COUNTER_HALF_SPAN) {
    22e0:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    22e4:	d916      	bls.n	2314 <compare_set+0xdc>
					event_clear(chan);
    22e6:	4620      	mov	r0, r4
    22e8:	f002 fb23 	bl	4932 <event_clear>
    22ec:	4a17      	ldr	r2, [pc, #92]	; (234c <compare_set+0x114>)
			cc_val = now + cc_inc;
    22ee:	eb0a 0c08 	add.w	ip, sl, r8
			cc_inc++;
    22f2:	f10a 0a01 	add.w	sl, sl, #1
	for (;;) {
    22f6:	e7d9      	b.n	22ac <compare_set+0x74>
		atomic_or(&force_isr_mask, BIT(chan));
    22f8:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    22fa:	4a15      	ldr	r2, [pc, #84]	; (2350 <compare_set+0x118>)
    22fc:	f3bf 8f5b 	dmb	ish
    2300:	40a3      	lsls	r3, r4
    2302:	e852 0f00 	ldrex	r0, [r2]
    2306:	4318      	orrs	r0, r3
    2308:	e842 0100 	strex	r1, r0, [r2]
    230c:	2900      	cmp	r1, #0
    230e:	d1f8      	bne.n	2302 <compare_set+0xca>
    2310:	f3bf 8f5b 	dmb	ish
	cc_data[chan].target_time = target_time;
    2314:	490b      	ldr	r1, [pc, #44]	; (2344 <compare_set+0x10c>)
	cc_data[chan].callback = handler;
    2316:	980c      	ldr	r0, [sp, #48]	; 0x30
	cc_data[chan].target_time = target_time;
    2318:	0123      	lsls	r3, r4, #4
    231a:	eb01 1204 	add.w	r2, r1, r4, lsl #4
    231e:	e9c2 6702 	strd	r6, r7, [r2, #8]
	cc_data[chan].callback = handler;
    2322:	50c8      	str	r0, [r1, r3]
	cc_data[chan].user_context = user_data;
    2324:	9b0d      	ldr	r3, [sp, #52]	; 0x34
    2326:	6053      	str	r3, [r2, #4]
	return ret;
    2328:	2500      	movs	r5, #0
	compare_int_unlock(chan, key);
    232a:	4620      	mov	r0, r4
    232c:	9900      	ldr	r1, [sp, #0]
    232e:	f7ff ff33 	bl	2198 <compare_int_unlock>
}
    2332:	4628      	mov	r0, r5
    2334:	b003      	add	sp, #12
    2336:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			return -EINVAL;
    233a:	f06f 0515 	mvn.w	r5, #21
    233e:	e7f4      	b.n	232a <compare_set+0xf2>
    2340:	00800001 	.word	0x00800001
    2344:	20000138 	.word	0x20000138
    2348:	40011000 	.word	0x40011000
    234c:	007ffffd 	.word	0x007ffffd
    2350:	2000031c 	.word	0x2000031c

00002354 <sys_clock_driver_init>:
	int_event_disable_rtc();
	NVIC_ClearPendingIRQ(RTC_IRQn);
}

static int sys_clock_driver_init(void)
{
    2354:	b573      	push	{r0, r1, r4, r5, r6, lr}
    p_reg->INTENCLR = mask;
    2356:	4c1b      	ldr	r4, [pc, #108]	; (23c4 <sys_clock_driver_init+0x70>)
    2358:	4b1b      	ldr	r3, [pc, #108]	; (23c8 <sys_clock_driver_init+0x74>)
    235a:	f8c4 3308 	str.w	r3, [r4, #776]	; 0x308
    p_reg->EVTENCLR = mask;
    235e:	f8c4 3348 	str.w	r3, [r4, #840]	; 0x348
	int_event_disable_rtc();

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    2362:	4b1a      	ldr	r3, [pc, #104]	; (23cc <sys_clock_driver_init+0x78>)
    p_reg->PRESCALER = val;
    2364:	2500      	movs	r5, #0
    2366:	f04f 30ff 	mov.w	r0, #4294967295
    236a:	f04f 31ff 	mov.w	r1, #4294967295
    236e:	f8c4 5508 	str.w	r5, [r4, #1288]	; 0x508
    2372:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    2376:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    237a:	f8c4 3304 	str.w	r3, [r4, #772]	; 0x304
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    237e:	4b14      	ldr	r3, [pc, #80]	; (23d0 <sys_clock_driver_init+0x7c>)
    2380:	2602      	movs	r6, #2
    2382:	f44f 3200 	mov.w	r2, #131072	; 0x20000

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    2386:	2101      	movs	r1, #1
    2388:	f8c4 6304 	str.w	r6, [r4, #772]	; 0x304
    238c:	2011      	movs	r0, #17
    238e:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    2392:	462a      	mov	r2, r5
    2394:	f7fe fe90 	bl	10b8 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    2398:	2011      	movs	r0, #17
    239a:	f7fe fe5d 	bl	1058 <arch_irq_enable>

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    239e:	4a0d      	ldr	r2, [pc, #52]	; (23d4 <sys_clock_driver_init+0x80>)
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    23a0:	2301      	movs	r3, #1
    23a2:	60a3      	str	r3, [r4, #8]
    23a4:	6023      	str	r3, [r4, #0]
    23a6:	6013      	str	r3, [r2, #0]
	}

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
		MAX_CYCLES : CYC_PER_TICK;

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    23a8:	4b0b      	ldr	r3, [pc, #44]	; (23d8 <sys_clock_driver_init+0x84>)
    23aa:	4a0c      	ldr	r2, [pc, #48]	; (23dc <sys_clock_driver_init+0x88>)
    23ac:	9300      	str	r3, [sp, #0]
    23ae:	9501      	str	r5, [sp, #4]
    23b0:	2300      	movs	r3, #0
    23b2:	4628      	mov	r0, r5
    23b4:	f7ff ff40 	bl	2238 <compare_set>

	z_nrf_clock_control_lf_on(mode);
    23b8:	4630      	mov	r0, r6
    23ba:	f7ff fb61 	bl	1a80 <z_nrf_clock_control_lf_on>

	return 0;
}
    23be:	4628      	mov	r0, r5
    23c0:	b002      	add	sp, #8
    23c2:	bd70      	pop	{r4, r5, r6, pc}
    23c4:	40011000 	.word	0x40011000
    23c8:	000f0003 	.word	0x000f0003
    23cc:	20000138 	.word	0x20000138
    23d0:	e000e100 	.word	0xe000e100
    23d4:	20000320 	.word	0x20000320
    23d8:	00002151 	.word	0x00002151
    23dc:	007fffff 	.word	0x007fffff

000023e0 <rtc_nrf_isr>:
{
    23e0:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    return p_reg->INTENSET & mask;
    23e4:	4c2f      	ldr	r4, [pc, #188]	; (24a4 <rtc_nrf_isr+0xc4>)
    23e6:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    23ea:	0799      	lsls	r1, r3, #30
    23ec:	d50b      	bpl.n	2406 <rtc_nrf_isr+0x26>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    23ee:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    23f2:	b143      	cbz	r3, 2406 <rtc_nrf_isr+0x26>
		overflow_cnt++;
    23f4:	4a2c      	ldr	r2, [pc, #176]	; (24a8 <rtc_nrf_isr+0xc8>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    23f6:	2300      	movs	r3, #0
    23f8:	f8c4 3104 	str.w	r3, [r4, #260]	; 0x104
    23fc:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    2400:	6813      	ldr	r3, [r2, #0]
    2402:	3301      	adds	r3, #1
    2404:	6013      	str	r3, [r2, #0]
    return p_reg->INTENSET & mask;
    2406:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    240a:	03da      	lsls	r2, r3, #15
    240c:	d52a      	bpl.n	2464 <rtc_nrf_isr+0x84>
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    240e:	f3bf 8f5b 	dmb	ish
    2412:	4b26      	ldr	r3, [pc, #152]	; (24ac <rtc_nrf_isr+0xcc>)
    2414:	e853 2f00 	ldrex	r2, [r3]
    2418:	f022 0101 	bic.w	r1, r2, #1
    241c:	e843 1000 	strex	r0, r1, [r3]
    2420:	2800      	cmp	r0, #0
    2422:	d1f7      	bne.n	2414 <rtc_nrf_isr+0x34>
    2424:	f3bf 8f5b 	dmb	ish
		if ((atomic_and(&force_isr_mask, ~BIT(chan)) & BIT(chan)) ||
    2428:	07d3      	lsls	r3, r2, #31
    242a:	d402      	bmi.n	2432 <rtc_nrf_isr+0x52>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    242c:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
    2430:	b1c3      	cbz	r3, 2464 <rtc_nrf_isr+0x84>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2432:	2500      	movs	r5, #0
    2434:	f8c4 5140 	str.w	r5, [r4, #320]	; 0x140
    2438:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
		curr_time = z_nrf_rtc_timer_read();
    243c:	f7ff feda 	bl	21f4 <z_nrf_rtc_timer_read>
    2440:	f04f 0320 	mov.w	r3, #32
    2444:	f3ef 8211 	mrs	r2, BASEPRI
    2448:	f383 8812 	msr	BASEPRI_MAX, r3
    244c:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    2450:	4b17      	ldr	r3, [pc, #92]	; (24b0 <rtc_nrf_isr+0xd0>)
    2452:	e9d3 6702 	ldrd	r6, r7, [r3, #8]
		if (curr_time >= expire_time) {
    2456:	42b0      	cmp	r0, r6
    2458:	41b9      	sbcs	r1, r7
    245a:	d206      	bcs.n	246a <rtc_nrf_isr+0x8a>
	__asm__ volatile(
    245c:	f382 8811 	msr	BASEPRI, r2
    2460:	f3bf 8f6f 	isb	sy
}
    2464:	b003      	add	sp, #12
    2466:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    246a:	f04f 38ff 	mov.w	r8, #4294967295
    246e:	f04f 39ff 	mov.w	r9, #4294967295
    2472:	e9c3 8902 	strd	r8, r9, [r3, #8]
			user_context = cc_data[chan].user_context;
    2476:	e9d3 1000 	ldrd	r1, r0, [r3]
			cc_data[chan].callback = NULL;
    247a:	601d      	str	r5, [r3, #0]
    p_reg->EVTENCLR = mask;
    247c:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    2480:	f8c4 3348 	str.w	r3, [r4, #840]	; 0x348
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2484:	f8c4 5140 	str.w	r5, [r4, #320]	; 0x140
    2488:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
    248c:	f382 8811 	msr	BASEPRI, r2
    2490:	f3bf 8f6f 	isb	sy
		if (handler) {
    2494:	2900      	cmp	r1, #0
    2496:	d0e5      	beq.n	2464 <rtc_nrf_isr+0x84>
			handler(chan, expire_time, user_context);
    2498:	9000      	str	r0, [sp, #0]
    249a:	4632      	mov	r2, r6
    249c:	463b      	mov	r3, r7
    249e:	4628      	mov	r0, r5
    24a0:	4788      	blx	r1
    24a2:	e7df      	b.n	2464 <rtc_nrf_isr+0x84>
    24a4:	40011000 	.word	0x40011000
    24a8:	20000324 	.word	0x20000324
    24ac:	2000031c 	.word	0x2000031c
    24b0:	20000138 	.word	0x20000138

000024b4 <sys_clock_set_timeout>:
	if (ticks == K_TICKS_FOREVER) {
    24b4:	1c43      	adds	r3, r0, #1
{
    24b6:	b513      	push	{r0, r1, r4, lr}
	if (ticks == K_TICKS_FOREVER) {
    24b8:	d022      	beq.n	2500 <sys_clock_set_timeout+0x4c>
		cyc = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
    24ba:	2801      	cmp	r0, #1
    24bc:	dd22      	ble.n	2504 <sys_clock_set_timeout+0x50>
    24be:	4a12      	ldr	r2, [pc, #72]	; (2508 <sys_clock_set_timeout+0x54>)
    24c0:	4b12      	ldr	r3, [pc, #72]	; (250c <sys_clock_set_timeout+0x58>)
    24c2:	4290      	cmp	r0, r2
    24c4:	bfd4      	ite	le
    24c6:	4604      	movle	r4, r0
    24c8:	461c      	movgt	r4, r3
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    24ca:	f7ff fe93 	bl	21f4 <z_nrf_rtc_timer_read>
    24ce:	4b10      	ldr	r3, [pc, #64]	; (2510 <sys_clock_set_timeout+0x5c>)
	if (cyc > MAX_CYCLES) {
    24d0:	490e      	ldr	r1, [pc, #56]	; (250c <sys_clock_set_timeout+0x58>)
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    24d2:	e9d3 2300 	ldrd	r2, r3, [r3]
    24d6:	1a80      	subs	r0, r0, r2
		cyc = 0;
    24d8:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    24dc:	bf28      	it	cs
    24de:	2400      	movcs	r4, #0
	cyc += unannounced;
    24e0:	4404      	add	r4, r0
	if (cyc > MAX_CYCLES) {
    24e2:	428c      	cmp	r4, r1
    24e4:	bf28      	it	cs
    24e6:	460c      	movcs	r4, r1
	uint64_t target_time = cyc + last_count;
    24e8:	18a2      	adds	r2, r4, r2
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    24ea:	490a      	ldr	r1, [pc, #40]	; (2514 <sys_clock_set_timeout+0x60>)
    24ec:	9100      	str	r1, [sp, #0]
	uint64_t target_time = cyc + last_count;
    24ee:	f04f 0000 	mov.w	r0, #0
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    24f2:	9001      	str	r0, [sp, #4]
    24f4:	f143 0300 	adc.w	r3, r3, #0
    24f8:	f7ff fe9e 	bl	2238 <compare_set>
}
    24fc:	b002      	add	sp, #8
    24fe:	bd10      	pop	{r4, pc}
		cyc = MAX_TICKS * CYC_PER_TICK;
    2500:	4c02      	ldr	r4, [pc, #8]	; (250c <sys_clock_set_timeout+0x58>)
    2502:	e7e2      	b.n	24ca <sys_clock_set_timeout+0x16>
		cyc = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
    2504:	2401      	movs	r4, #1
    2506:	e7e0      	b.n	24ca <sys_clock_set_timeout+0x16>
    2508:	007ffffe 	.word	0x007ffffe
    250c:	007fffff 	.word	0x007fffff
    2510:	20000148 	.word	0x20000148
    2514:	00002151 	.word	0x00002151

00002518 <sys_clock_elapsed>:
{
    2518:	b508      	push	{r3, lr}
	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    251a:	f7ff fe6b 	bl	21f4 <z_nrf_rtc_timer_read>
    251e:	4b02      	ldr	r3, [pc, #8]	; (2528 <sys_clock_elapsed+0x10>)
    2520:	681b      	ldr	r3, [r3, #0]
}
    2522:	1ac0      	subs	r0, r0, r3
    2524:	bd08      	pop	{r3, pc}
    2526:	bf00      	nop
    2528:	20000148 	.word	0x20000148

0000252c <nrf52_errata_16>:
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    252c:	f04f 4370 	mov.w	r3, #4026531840	; 0xf0000000
    2530:	f893 2fe0 	ldrb.w	r2, [r3, #4064]	; 0xfe0
            uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    2534:	2a06      	cmp	r2, #6
    2536:	d109      	bne.n	254c <nrf52_errata_16+0x20>
            uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
    2538:	f8d3 3fe8 	ldr.w	r3, [r3, #4072]	; 0xfe8
    253c:	f3c3 1303 	ubfx	r3, r3, #4, #4
    2540:	3b03      	subs	r3, #3
    2542:	2b04      	cmp	r3, #4
    2544:	d802      	bhi.n	254c <nrf52_errata_16+0x20>
    2546:	4a02      	ldr	r2, [pc, #8]	; (2550 <nrf52_errata_16+0x24>)
    2548:	5cd0      	ldrb	r0, [r2, r3]
    254a:	4770      	bx	lr
                switch(var2)
                {
                    case 0x03ul:
                        return true;
                    case 0x04ul:
                        return false;
    254c:	2000      	movs	r0, #0
                }
            }
        #endif
        return false;
    #endif
}
    254e:	4770      	bx	lr
    2550:	000050ca 	.word	0x000050ca

00002554 <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    2554:	4a02      	ldr	r2, [pc, #8]	; (2560 <nvmc_wait+0xc>)
    2556:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    255a:	2b00      	cmp	r3, #0
    255c:	d0fb      	beq.n	2556 <nvmc_wait+0x2>
}
    255e:	4770      	bx	lr
    2560:	4001e000 	.word	0x4001e000

00002564 <SystemInit>:
{
    SystemCoreClock = __SYSTEM_CLOCK_DEFAULT;
}

void SystemInit(void)
{
    2564:	b510      	push	{r4, lr}
    #endif

    #if NRF52_ERRATA_12_ENABLE_WORKAROUND
        /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_12()){
    2566:	f002 f9f4 	bl	4952 <nrf52_errata_108>
    256a:	b140      	cbz	r0, 257e <SystemInit+0x1a>
            *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
    256c:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    2570:	4a8e      	ldr	r2, [pc, #568]	; (27ac <SystemInit+0x248>)
    2572:	f8d3 3324 	ldr.w	r3, [r3, #804]	; 0x324
    2576:	f3c3 2304 	ubfx	r3, r3, #8, #5
    257a:	f8c2 3540 	str.w	r3, [r2, #1344]	; 0x540
    #endif

    #if NRF52_ERRATA_16_ENABLE_WORKAROUND
        /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_16()){
    257e:	f7ff ffd5 	bl	252c <nrf52_errata_16>
    2582:	b110      	cbz	r0, 258a <SystemInit+0x26>
            *(volatile uint32_t *)0x4007C074 = 3131961357ul;
    2584:	4b8a      	ldr	r3, [pc, #552]	; (27b0 <SystemInit+0x24c>)
    2586:	4a8b      	ldr	r2, [pc, #556]	; (27b4 <SystemInit+0x250>)
    2588:	675a      	str	r2, [r3, #116]	; 0x74
    #endif

    #if NRF52_ERRATA_31_ENABLE_WORKAROUND
        /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_31()){
    258a:	f002 f9e2 	bl	4952 <nrf52_errata_108>
    258e:	b148      	cbz	r0, 25a4 <SystemInit+0x40>
            *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
    2590:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    2594:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    2598:	f8d3 3244 	ldr.w	r3, [r3, #580]	; 0x244
    259c:	f3c3 3342 	ubfx	r3, r3, #13, #3
    25a0:	f8c2 353c 	str.w	r3, [r2, #1340]	; 0x53c
    #endif

    #if NRF52_ERRATA_32_ENABLE_WORKAROUND
        /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_32()){
    25a4:	f7ff ffc2 	bl	252c <nrf52_errata_16>
    25a8:	b130      	cbz	r0, 25b8 <SystemInit+0x54>
            CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
    25aa:	4a83      	ldr	r2, [pc, #524]	; (27b8 <SystemInit+0x254>)
    25ac:	f8d2 30fc 	ldr.w	r3, [r2, #252]	; 0xfc
    25b0:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
    25b4:	f8c2 30fc 	str.w	r3, [r2, #252]	; 0xfc
    #endif

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
    25b8:	f002 f9cb 	bl	4952 <nrf52_errata_108>
    25bc:	b140      	cbz	r0, 25d0 <SystemInit+0x6c>
            NRF_CLOCK->EVENTS_DONE = 0;
    25be:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    25c2:	2200      	movs	r2, #0
    25c4:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    25c8:	f8c3 2110 	str.w	r2, [r3, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    25cc:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    #endif

    #if NRF52_ERRATA_37_ENABLE_WORKAROUND
        /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_37()){
    25d0:	f7ff ffac 	bl	252c <nrf52_errata_16>
    25d4:	b120      	cbz	r0, 25e0 <SystemInit+0x7c>
            *(volatile uint32_t *)0x400005A0 = 0x3;
    25d6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    25da:	2203      	movs	r2, #3
    25dc:	f8c3 25a0 	str.w	r2, [r3, #1440]	; 0x5a0
    #endif

    #if NRF52_ERRATA_57_ENABLE_WORKAROUND
        /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_57()){
    25e0:	f7ff ffa4 	bl	252c <nrf52_errata_16>
    25e4:	b160      	cbz	r0, 2600 <SystemInit+0x9c>
            *(volatile uint32_t *)0x40005610 = 0x00000005;
    25e6:	4b75      	ldr	r3, [pc, #468]	; (27bc <SystemInit+0x258>)
    25e8:	2205      	movs	r2, #5
    25ea:	f8c3 2610 	str.w	r2, [r3, #1552]	; 0x610
            *(volatile uint32_t *)0x40005688 = 0x00000001;
    25ee:	2201      	movs	r2, #1
    25f0:	f8c3 2688 	str.w	r2, [r3, #1672]	; 0x688
            *(volatile uint32_t *)0x40005618 = 0x00000000;
    25f4:	2200      	movs	r2, #0
    25f6:	f8c3 2618 	str.w	r2, [r3, #1560]	; 0x618
            *(volatile uint32_t *)0x40005614 = 0x0000003F;
    25fa:	223f      	movs	r2, #63	; 0x3f
    25fc:	f8c3 2614 	str.w	r2, [r3, #1556]	; 0x614
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1;
            uint32_t var2;

            if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF)
    2600:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    2604:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    2608:	1c51      	adds	r1, r2, #1
            {
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    260a:	bf09      	itett	eq
    260c:	f04f 4370 	moveq.w	r3, #4026531840	; 0xf0000000
                var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
            }
            else
            {
                var1 = *(uint32_t *)0x10000130ul;
                var2 = *(uint32_t *)0x10000134ul;
    2610:	f8d3 3134 	ldrne.w	r3, [r3, #308]	; 0x134
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    2614:	f893 2fe0 	ldrbeq.w	r2, [r3, #4064]	; 0xfe0
                var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
    2618:	f8d3 3fe8 	ldreq.w	r3, [r3, #4072]	; 0xfe8
    261c:	bf08      	it	eq
    261e:	f3c3 1303 	ubfxeq	r3, r3, #4, #4
            uint32_t var1 = *(uint32_t *)0x10000130ul;
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    2622:	2a06      	cmp	r2, #6
    2624:	d14d      	bne.n	26c2 <SystemInit+0x15e>
            {
                switch(var2)
    2626:	3b03      	subs	r3, #3
    2628:	2b04      	cmp	r3, #4
    262a:	d803      	bhi.n	2634 <SystemInit+0xd0>
    #endif

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
    262c:	4a64      	ldr	r2, [pc, #400]	; (27c0 <SystemInit+0x25c>)
    262e:	5cd3      	ldrb	r3, [r2, r3]
    2630:	2b00      	cmp	r3, #0
    2632:	d046      	beq.n	26c2 <SystemInit+0x15e>
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    2634:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
    2638:	4b62      	ldr	r3, [pc, #392]	; (27c4 <SystemInit+0x260>)
    263a:	f8d2 1404 	ldr.w	r1, [r2, #1028]	; 0x404
    263e:	f8c3 1520 	str.w	r1, [r3, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    2642:	f8d2 1408 	ldr.w	r1, [r2, #1032]	; 0x408
    2646:	f8c3 1524 	str.w	r1, [r3, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    264a:	f8d2 140c 	ldr.w	r1, [r2, #1036]	; 0x40c
    264e:	f8c3 1528 	str.w	r1, [r3, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    2652:	f8d2 1410 	ldr.w	r1, [r2, #1040]	; 0x410
    2656:	f8c3 152c 	str.w	r1, [r3, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    265a:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
    265e:	f8c3 1530 	str.w	r1, [r3, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    2662:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    2666:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    266a:	f8d2 141c 	ldr.w	r1, [r2, #1052]	; 0x41c
    266e:	f8c3 1540 	str.w	r1, [r3, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    2672:	f8d2 1420 	ldr.w	r1, [r2, #1056]	; 0x420
    2676:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    267a:	f8d2 1424 	ldr.w	r1, [r2, #1060]	; 0x424
    267e:	f8c3 1548 	str.w	r1, [r3, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    2682:	f8d2 1428 	ldr.w	r1, [r2, #1064]	; 0x428
    2686:	f8c3 154c 	str.w	r1, [r3, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    268a:	f8d2 142c 	ldr.w	r1, [r2, #1068]	; 0x42c
    268e:	f8c3 1550 	str.w	r1, [r3, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    2692:	f8d2 1430 	ldr.w	r1, [r2, #1072]	; 0x430
    2696:	f8c3 1554 	str.w	r1, [r3, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    269a:	f8d2 1434 	ldr.w	r1, [r2, #1076]	; 0x434
    269e:	f8c3 1560 	str.w	r1, [r3, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    26a2:	f8d2 1438 	ldr.w	r1, [r2, #1080]	; 0x438
    26a6:	f8c3 1564 	str.w	r1, [r3, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    26aa:	f8d2 143c 	ldr.w	r1, [r2, #1084]	; 0x43c
    26ae:	f8c3 1568 	str.w	r1, [r3, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    26b2:	f8d2 1440 	ldr.w	r1, [r2, #1088]	; 0x440
    26b6:	f8c3 156c 	str.w	r1, [r3, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    26ba:	f8d2 2444 	ldr.w	r2, [r2, #1092]	; 0x444
    26be:	f8c3 2570 	str.w	r2, [r3, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_108_ENABLE_WORKAROUND
        /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_108()){
    26c2:	f002 f946 	bl	4952 <nrf52_errata_108>
    26c6:	b148      	cbz	r0, 26dc <SystemInit+0x178>
            *(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful;
    26c8:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    26cc:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    26d0:	f8d3 3258 	ldr.w	r3, [r3, #600]	; 0x258
    26d4:	f003 034f 	and.w	r3, r3, #79	; 0x4f
    26d8:	f8c2 3ee4 	str.w	r3, [r2, #3812]	; 0xee4
    #endif

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
    26dc:	f002 f939 	bl	4952 <nrf52_errata_108>
    26e0:	b148      	cbz	r0, 26f6 <SystemInit+0x192>
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    26e2:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    26e6:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    26ea:	07d2      	lsls	r2, r2, #31
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    26ec:	bf44      	itt	mi
    26ee:	f06f 0201 	mvnmi.w	r2, #1
    26f2:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    26f6:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    26fa:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    26fe:	2a06      	cmp	r2, #6
    2700:	d126      	bne.n	2750 <SystemInit+0x1ec>
            {
                switch(var2)
    2702:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
    2706:	3b03      	subs	r3, #3
    2708:	2b04      	cmp	r3, #4
    270a:	d802      	bhi.n	2712 <SystemInit+0x1ae>
    #endif

    #if NRF52_ERRATA_182_ENABLE_WORKAROUND
        /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_182()){
    270c:	4a2e      	ldr	r2, [pc, #184]	; (27c8 <SystemInit+0x264>)
    270e:	5cd3      	ldrb	r3, [r2, r3]
    2710:	b163      	cbz	r3, 272c <SystemInit+0x1c8>
            *(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
    2712:	4a2e      	ldr	r2, [pc, #184]	; (27cc <SystemInit+0x268>)
    2714:	f8d2 373c 	ldr.w	r3, [r2, #1852]	; 0x73c
    2718:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
    271c:	f8c2 373c 	str.w	r3, [r2, #1852]	; 0x73c
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2720:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    2724:	f8d3 3130 	ldr.w	r3, [r3, #304]	; 0x130
    2728:	2b06      	cmp	r3, #6
    272a:	d111      	bne.n	2750 <SystemInit+0x1ec>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    272c:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    2730:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
    2734:	3b03      	subs	r3, #3
    2736:	2b04      	cmp	r3, #4
    2738:	d802      	bhi.n	2740 <SystemInit+0x1dc>
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_configuration_249())
    273a:	4a25      	ldr	r2, [pc, #148]	; (27d0 <SystemInit+0x26c>)
    273c:	5cd3      	ldrb	r3, [r2, r3]
    273e:	b13b      	cbz	r3, 2750 <SystemInit+0x1ec>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    2740:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    2744:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    2748:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    274c:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    2750:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    2754:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    2758:	2a00      	cmp	r2, #0
    275a:	db03      	blt.n	2764 <SystemInit+0x200>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    275c:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    2760:	2b00      	cmp	r3, #0
    2762:	da22      	bge.n	27aa <SystemInit+0x246>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    2764:	491b      	ldr	r1, [pc, #108]	; (27d4 <SystemInit+0x270>)
    2766:	2301      	movs	r3, #1
            nvmc_config(NVMC_CONFIG_WEN_Wen);
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    2768:	f04f 2010 	mov.w	r0, #268439552	; 0x10001000
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    276c:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    2770:	2415      	movs	r4, #21
    nvmc_wait();
    2772:	f7ff feef 	bl	2554 <nvmc_wait>
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    2776:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
            nvmc_wait();
    277a:	f7ff feeb 	bl	2554 <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    277e:	f8c0 4204 	str.w	r4, [r0, #516]	; 0x204
            nvmc_wait();
    2782:	f7ff fee7 	bl	2554 <nvmc_wait>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    2786:	2300      	movs	r3, #0
    2788:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    278c:	f7ff fee2 	bl	2554 <nvmc_wait>
  __ASM volatile ("dsb 0xF":::"memory");
    2790:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2794:	4908      	ldr	r1, [pc, #32]	; (27b8 <SystemInit+0x254>)
    2796:	4b10      	ldr	r3, [pc, #64]	; (27d8 <SystemInit+0x274>)
    2798:	68ca      	ldr	r2, [r1, #12]
    279a:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    279e:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    27a0:	60cb      	str	r3, [r1, #12]
    27a2:	f3bf 8f4f 	dsb	sy
    __NOP();
    27a6:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    27a8:	e7fd      	b.n	27a6 <SystemInit+0x242>
            nvmc_wait();
            nvmc_config(NVMC_CONFIG_WEN_Ren);
            NVIC_SystemReset();
        }
    #endif
}
    27aa:	bd10      	pop	{r4, pc}
    27ac:	40013000 	.word	0x40013000
    27b0:	4007c000 	.word	0x4007c000
    27b4:	baadf00d 	.word	0xbaadf00d
    27b8:	e000ed00 	.word	0xe000ed00
    27bc:	40005000 	.word	0x40005000
    27c0:	000050c5 	.word	0x000050c5
    27c4:	4000c000 	.word	0x4000c000
    27c8:	000050c0 	.word	0x000050c0
    27cc:	40001000 	.word	0x40001000
    27d0:	000050bb 	.word	0x000050bb
    27d4:	4001e000 	.word	0x4001e000
    27d8:	05fa0004 	.word	0x05fa0004

000027dc <nrfx_flag32_alloc>:
{
    return (mask & NRFX_BIT(bitpos)) ? false : true;
}

nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag)
{
    27dc:	b570      	push	{r4, r5, r6, lr}
        idx = 31 - NRF_CLZ(prev_mask);
        if (idx < 0) {
            return NRFX_ERROR_NO_MEM;
        }

        new_mask = prev_mask & ~NRFX_BIT(idx);
    27de:	2501      	movs	r5, #1
        prev_mask = *p_mask;
    27e0:	6802      	ldr	r2, [r0, #0]
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    27e2:	f3bf 8f5b 	dmb	ish
        idx = 31 - NRF_CLZ(prev_mask);
    27e6:	fab2 f382 	clz	r3, r2
    27ea:	f1c3 031f 	rsb	r3, r3, #31
    27ee:	b2db      	uxtb	r3, r3
        new_mask = prev_mask & ~NRFX_BIT(idx);
    27f0:	fa05 f403 	lsl.w	r4, r5, r3
    27f4:	ea22 0404 	bic.w	r4, r2, r4
    27f8:	e850 6f00 	ldrex	r6, [r0]
    27fc:	4296      	cmp	r6, r2
    27fe:	d104      	bne.n	280a <nrfx_flag32_alloc+0x2e>
    2800:	e840 4c00 	strex	ip, r4, [r0]
    2804:	f1bc 0f00 	cmp.w	ip, #0
    2808:	d1f6      	bne.n	27f8 <nrfx_flag32_alloc+0x1c>
    280a:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    280e:	d1e7      	bne.n	27e0 <nrfx_flag32_alloc+0x4>

    *p_flag = idx;

    return NRFX_SUCCESS;
}
    2810:	4801      	ldr	r0, [pc, #4]	; (2818 <nrfx_flag32_alloc+0x3c>)
    *p_flag = idx;
    2812:	700b      	strb	r3, [r1, #0]
}
    2814:	bd70      	pop	{r4, r5, r6, pc}
    2816:	bf00      	nop
    2818:	0bad0000 	.word	0x0bad0000

0000281c <nrfx_flag32_free>:

nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag)
{
    281c:	b510      	push	{r4, lr}
    uint32_t new_mask, prev_mask;

    if ((NRFX_BIT(flag) & *p_mask))
    281e:	6803      	ldr	r3, [r0, #0]
    2820:	40cb      	lsrs	r3, r1
    2822:	07db      	lsls	r3, r3, #31
    2824:	d414      	bmi.n	2850 <nrfx_flag32_free+0x34>
        return NRFX_ERROR_INVALID_PARAM;
    }

    do {
        prev_mask = *p_mask;
        new_mask = prev_mask | NRFX_BIT(flag);
    2826:	2301      	movs	r3, #1
    2828:	408b      	lsls	r3, r1
        prev_mask = *p_mask;
    282a:	6802      	ldr	r2, [r0, #0]
    282c:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask | NRFX_BIT(flag);
    2830:	ea43 0102 	orr.w	r1, r3, r2
    2834:	e850 4f00 	ldrex	r4, [r0]
    2838:	4294      	cmp	r4, r2
    283a:	d104      	bne.n	2846 <nrfx_flag32_free+0x2a>
    283c:	e840 1c00 	strex	ip, r1, [r0]
    2840:	f1bc 0f00 	cmp.w	ip, #0
    2844:	d1f6      	bne.n	2834 <nrfx_flag32_free+0x18>
    2846:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    284a:	d1ee      	bne.n	282a <nrfx_flag32_free+0xe>

    return NRFX_SUCCESS;
    284c:	4801      	ldr	r0, [pc, #4]	; (2854 <nrfx_flag32_free+0x38>)
}
    284e:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    2850:	4801      	ldr	r0, [pc, #4]	; (2858 <nrfx_flag32_free+0x3c>)
    2852:	e7fc      	b.n	284e <nrfx_flag32_free+0x32>
    2854:	0bad0000 	.word	0x0bad0000
    2858:	0bad0004 	.word	0x0bad0004

0000285c <clock_stop>:
    CoreDebug->DEMCR = core_debug;
}
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)

static void clock_stop(nrf_clock_domain_t domain)
{
    285c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    switch (domain)
    285e:	4604      	mov	r4, r0
    2860:	b118      	cbz	r0, 286a <clock_stop+0xe>
    2862:	2801      	cmp	r0, #1
    2864:	d022      	beq.n	28ac <clock_stop+0x50>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    2866:	b003      	add	sp, #12
    2868:	bdf0      	pop	{r4, r5, r6, r7, pc}
    p_reg->INTENCLR = mask;
    286a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    286e:	2202      	movs	r2, #2
    2870:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2874:	f8c3 0104 	str.w	r0, [r3, #260]	; 0x104
    2878:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    287c:	2201      	movs	r2, #1
    287e:	60da      	str	r2, [r3, #12]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    2880:	4607      	mov	r7, r0
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    2882:	2301      	movs	r3, #1
    2884:	f88d 3007 	strb.w	r3, [sp, #7]
    2888:	f242 7510 	movw	r5, #10000	; 0x2710
    288c:	f04f 4680 	mov.w	r6, #1073741824	; 0x40000000
    switch (domain)
    2890:	b1cc      	cbz	r4, 28c6 <clock_stop+0x6a>
    2892:	2c01      	cmp	r4, #1
    2894:	d1e7      	bne.n	2866 <clock_stop+0xa>
            if (p_clk_src != NULL)
    2896:	b3c7      	cbz	r7, 290a <clock_stop+0xae>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2898:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    289c:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    28a0:	703b      	strb	r3, [r7, #0]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    28a2:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    28a6:	03da      	lsls	r2, r3, #15
    28a8:	d521      	bpl.n	28ee <clock_stop+0x92>
    28aa:	e016      	b.n	28da <clock_stop+0x7e>
    p_reg->INTENCLR = mask;
    28ac:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    28b0:	2200      	movs	r2, #0
    p_reg->INTENCLR = mask;
    28b2:	f8c3 0308 	str.w	r0, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    28b6:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    28ba:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    28be:	6058      	str	r0, [r3, #4]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    28c0:	f10d 0707 	add.w	r7, sp, #7
    28c4:	e7dd      	b.n	2882 <clock_stop+0x26>
            if (p_clk_src != NULL)
    28c6:	b1b7      	cbz	r7, 28f6 <clock_stop+0x9a>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    28c8:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    28cc:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    28d0:	603b      	str	r3, [r7, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    28d2:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    28d6:	03d8      	lsls	r0, r3, #15
    28d8:	d5c5      	bpl.n	2866 <clock_stop+0xa>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    28da:	f89d 0007 	ldrb.w	r0, [sp, #7]
    28de:	2801      	cmp	r0, #1
    28e0:	d103      	bne.n	28ea <clock_stop+0x8e>
    28e2:	f002 f845 	bl	4970 <nrfx_busy_wait>
    28e6:	3d01      	subs	r5, #1
    28e8:	d1d2      	bne.n	2890 <clock_stop+0x34>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    28ea:	2c01      	cmp	r4, #1
    28ec:	d1bb      	bne.n	2866 <clock_stop+0xa>
            m_clock_cb.hfclk_started = false;
    28ee:	4b0c      	ldr	r3, [pc, #48]	; (2920 <clock_stop+0xc4>)
    28f0:	2200      	movs	r2, #0
    28f2:	715a      	strb	r2, [r3, #5]
    28f4:	e7b7      	b.n	2866 <clock_stop+0xa>
    28f6:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    28fa:	03d9      	lsls	r1, r3, #15
    28fc:	d5b3      	bpl.n	2866 <clock_stop+0xa>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    28fe:	2001      	movs	r0, #1
    2900:	f002 f836 	bl	4970 <nrfx_busy_wait>
    2904:	3d01      	subs	r5, #1
    2906:	d1f6      	bne.n	28f6 <clock_stop+0x9a>
    2908:	e7ad      	b.n	2866 <clock_stop+0xa>
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    290a:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    290e:	03db      	lsls	r3, r3, #15
    2910:	d5ed      	bpl.n	28ee <clock_stop+0x92>
    2912:	2001      	movs	r0, #1
    2914:	f002 f82c 	bl	4970 <nrfx_busy_wait>
    2918:	3d01      	subs	r5, #1
    291a:	d1f6      	bne.n	290a <clock_stop+0xae>
    291c:	e7e7      	b.n	28ee <clock_stop+0x92>
    291e:	bf00      	nop
    2920:	20000328 	.word	0x20000328

00002924 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    2924:	4b04      	ldr	r3, [pc, #16]	; (2938 <nrfx_clock_init+0x14>)
    2926:	791a      	ldrb	r2, [r3, #4]
    2928:	b922      	cbnz	r2, 2934 <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    292a:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    292c:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    292e:	809a      	strh	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    2930:	4802      	ldr	r0, [pc, #8]	; (293c <nrfx_clock_init+0x18>)
    2932:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    2934:	4802      	ldr	r0, [pc, #8]	; (2940 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    2936:	4770      	bx	lr
    2938:	20000328 	.word	0x20000328
    293c:	0bad0000 	.word	0x0bad0000
    2940:	0bad000c 	.word	0x0bad000c

00002944 <nrfx_clock_start>:
    m_clock_cb.module_initialized = false;
    NRFX_LOG_INFO("Uninitialized.");
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    2944:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    2946:	b110      	cbz	r0, 294e <nrfx_clock_start+0xa>
    2948:	2801      	cmp	r0, #1
    294a:	d043      	beq.n	29d4 <nrfx_clock_start+0x90>
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    294c:	bd38      	pop	{r3, r4, r5, pc}
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    294e:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    2952:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2956:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    295a:	03c8      	lsls	r0, r1, #15
    295c:	d40b      	bmi.n	2976 <nrfx_clock_start+0x32>
            return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
    295e:	f8d2 3414 	ldr.w	r3, [r2, #1044]	; 0x414
                else if (nrf_clock_start_task_check(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK))
    2962:	07d9      	lsls	r1, r3, #31
    2964:	d50f      	bpl.n	2986 <nrfx_clock_start+0x42>
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    2966:	f8d2 341c 	ldr.w	r3, [r2, #1052]	; 0x41c
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    296a:	079b      	lsls	r3, r3, #30
    296c:	d408      	bmi.n	2980 <nrfx_clock_start+0x3c>
    p_reg->INTENSET = mask;
    296e:	2302      	movs	r3, #2
    2970:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
                        break;
    2974:	e7ea      	b.n	294c <nrfx_clock_start+0x8>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    2976:	f003 0303 	and.w	r3, r3, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    297a:	2b01      	cmp	r3, #1
    297c:	d004      	beq.n	2988 <nrfx_clock_start+0x44>
    297e:	b113      	cbz	r3, 2986 <nrfx_clock_start+0x42>
        clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    2980:	2000      	movs	r0, #0
    2982:	f7ff ff6b 	bl	285c <clock_stop>
        *p_lfclksrc = clock_initial_lfclksrc_get();
    2986:	2300      	movs	r3, #0
    p_reg->LFCLKSRC = (uint32_t)(source);
    2988:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    298c:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2990:	2300      	movs	r3, #0
    2992:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
    2996:	f8d2 3104 	ldr.w	r3, [r2, #260]	; 0x104
    p_reg->INTENSET = mask;
    299a:	2302      	movs	r3, #2
    299c:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
    core_debug = CoreDebug->DEMCR;
    29a0:	4a12      	ldr	r2, [pc, #72]	; (29ec <nrfx_clock_start+0xa8>)
    29a2:	f8d2 00fc 	ldr.w	r0, [r2, #252]	; 0xfc
    CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk;
    29a6:	f040 7380 	orr.w	r3, r0, #16777216	; 0x1000000
    29aa:	f8c2 30fc 	str.w	r3, [r2, #252]	; 0xfc
    dwt_ctrl = DWT->CTRL;
    29ae:	4b10      	ldr	r3, [pc, #64]	; (29f0 <nrfx_clock_start+0xac>)
    29b0:	681c      	ldr	r4, [r3, #0]
    DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk;
    29b2:	f044 0101 	orr.w	r1, r4, #1
    29b6:	6019      	str	r1, [r3, #0]
    cyccnt_inital = DWT->CYCCNT;
    29b8:	685d      	ldr	r5, [r3, #4]
    while ((DWT->CYCCNT - cyccnt_inital) < ANOMALY_132_DELAY_CYCLES)
    29ba:	6859      	ldr	r1, [r3, #4]
    29bc:	1b49      	subs	r1, r1, r5
    29be:	f5b1 5f0a 	cmp.w	r1, #8832	; 0x2280
    29c2:	d3fa      	bcc.n	29ba <nrfx_clock_start+0x76>
    DWT->CTRL = dwt_ctrl;
    29c4:	601c      	str	r4, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    29c6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    CoreDebug->DEMCR = core_debug;
    29ca:	f8c2 00fc 	str.w	r0, [r2, #252]	; 0xfc
    29ce:	2201      	movs	r2, #1
    29d0:	609a      	str	r2, [r3, #8]
}
    29d2:	e7bb      	b.n	294c <nrfx_clock_start+0x8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    29d4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    29d8:	2200      	movs	r2, #0
    29da:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    29de:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENSET = mask;
    29e2:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    29e6:	6018      	str	r0, [r3, #0]
}
    29e8:	e7b0      	b.n	294c <nrfx_clock_start+0x8>
    29ea:	bf00      	nop
    29ec:	e000ed00 	.word	0xe000ed00
    29f0:	e0001000 	.word	0xe0001000

000029f4 <nrfx_power_clock_irq_handler>:
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    29f4:	b510      	push	{r4, lr}
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    29f6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    29fa:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    29fe:	b16a      	cbz	r2, 2a1c <nrfx_power_clock_irq_handler+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a00:	2200      	movs	r2, #0
    2a02:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    2a06:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENCLR = mask;
    2a0a:	2201      	movs	r2, #1
    2a0c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);

#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
        if (!m_clock_cb.hfclk_started)
    2a10:	4b11      	ldr	r3, [pc, #68]	; (2a58 <nrfx_power_clock_irq_handler+0x64>)
    2a12:	7958      	ldrb	r0, [r3, #5]
    2a14:	b910      	cbnz	r0, 2a1c <nrfx_power_clock_irq_handler+0x28>
        {
            m_clock_cb.hfclk_started = true;
    2a16:	715a      	strb	r2, [r3, #5]
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    2a18:	681b      	ldr	r3, [r3, #0]
    2a1a:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2a1c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2a20:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    2a24:	b172      	cbz	r2, 2a44 <nrfx_power_clock_irq_handler+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a26:	2200      	movs	r2, #0
    2a28:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    2a2c:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    2a30:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2a34:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    2a38:	0792      	lsls	r2, r2, #30
    2a3a:	d104      	bne.n	2a46 <nrfx_power_clock_irq_handler+0x52>
    p_reg->LFCLKSRC = (uint32_t)(source);
    2a3c:	2201      	movs	r2, #1
    2a3e:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2a42:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    2a44:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    2a46:	2202      	movs	r2, #2
    2a48:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    2a4c:	4b02      	ldr	r3, [pc, #8]	; (2a58 <nrfx_power_clock_irq_handler+0x64>)
}
    2a4e:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    2a52:	681b      	ldr	r3, [r3, #0]
    2a54:	2001      	movs	r0, #1
    2a56:	4718      	bx	r3
    2a58:	20000328 	.word	0x20000328

00002a5c <pin_in_use_by_te>:
 *
 * @return True if pin uses GPIOTE task/event.
 */
static bool pin_in_use_by_te(uint32_t pin)
{
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    2a5c:	4b03      	ldr	r3, [pc, #12]	; (2a6c <pin_in_use_by_te+0x10>)
    2a5e:	3008      	adds	r0, #8
    2a60:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    2a64:	f3c0 1040 	ubfx	r0, r0, #5, #1
    2a68:	4770      	bx	lr
    2a6a:	bf00      	nop
    2a6c:	200000c8 	.word	0x200000c8

00002a70 <call_handler>:
    nrf_gpiote_event_t event = nrfx_gpiote_in_event_get(pin);
    return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}

static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger)
{
    2a70:	b570      	push	{r4, r5, r6, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    2a72:	f100 0308 	add.w	r3, r0, #8
    2a76:	4c0c      	ldr	r4, [pc, #48]	; (2aa8 <call_handler+0x38>)
    2a78:	f834 3013 	ldrh.w	r3, [r4, r3, lsl #1]
    2a7c:	05da      	lsls	r2, r3, #23
{
    2a7e:	4605      	mov	r5, r0
    2a80:	460e      	mov	r6, r1
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    2a82:	d507      	bpl.n	2a94 <call_handler+0x24>
    2a84:	f3c3 2343 	ubfx	r3, r3, #9, #4
    nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin);

    if (handler)
    {
        handler->handler(pin, trigger, handler->p_context);
    2a88:	eb04 02c3 	add.w	r2, r4, r3, lsl #3
    2a8c:	f854 3033 	ldr.w	r3, [r4, r3, lsl #3]
    2a90:	6852      	ldr	r2, [r2, #4]
    2a92:	4798      	blx	r3
    }
    if (m_cb.global_handler.handler)
    2a94:	68a3      	ldr	r3, [r4, #8]
    2a96:	b12b      	cbz	r3, 2aa4 <call_handler+0x34>
    {
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    2a98:	68e2      	ldr	r2, [r4, #12]
    2a9a:	4631      	mov	r1, r6
    2a9c:	4628      	mov	r0, r5
    }
}
    2a9e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    2aa2:	4718      	bx	r3
}
    2aa4:	bd70      	pop	{r4, r5, r6, pc}
    2aa6:	bf00      	nop
    2aa8:	200000c8 	.word	0x200000c8

00002aac <release_handler>:
{
    2aac:	b410      	push	{r4}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    2aae:	4a12      	ldr	r2, [pc, #72]	; (2af8 <release_handler+0x4c>)
    2ab0:	3008      	adds	r0, #8
    2ab2:	f832 3010 	ldrh.w	r3, [r2, r0, lsl #1]
    2ab6:	05d9      	lsls	r1, r3, #23
    2ab8:	d51b      	bpl.n	2af2 <release_handler+0x46>
    2aba:	f3c3 2143 	ubfx	r1, r3, #9, #4
    m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK;
    2abe:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    2ac2:	f822 3010 	strh.w	r3, [r2, r0, lsl #1]
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    2ac6:	f102 040e 	add.w	r4, r2, #14
    2aca:	2000      	movs	r0, #0
        if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id)
    2acc:	f834 3f02 	ldrh.w	r3, [r4, #2]!
    2ad0:	f413 7f80 	tst.w	r3, #256	; 0x100
    2ad4:	d003      	beq.n	2ade <release_handler+0x32>
    2ad6:	f3c3 2343 	ubfx	r3, r3, #9, #4
    2ada:	4299      	cmp	r1, r3
    2adc:	d009      	beq.n	2af2 <release_handler+0x46>
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    2ade:	3001      	adds	r0, #1
    2ae0:	2820      	cmp	r0, #32
    2ae2:	d1f3      	bne.n	2acc <release_handler+0x20>
        m_cb.handlers[handler_id].handler = NULL;
    2ae4:	2300      	movs	r3, #0
    2ae6:	f842 3031 	str.w	r3, [r2, r1, lsl #3]
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    2aea:	4804      	ldr	r0, [pc, #16]	; (2afc <release_handler+0x50>)
}
    2aec:	bc10      	pop	{r4}
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    2aee:	f7ff be95 	b.w	281c <nrfx_flag32_free>
}
    2af2:	bc10      	pop	{r4}
    2af4:	4770      	bx	lr
    2af6:	bf00      	nop
    2af8:	200000c8 	.word	0x200000c8
    2afc:	2000011c 	.word	0x2000011c

00002b00 <pin_handler_trigger_uninit>:
{
    2b00:	b538      	push	{r3, r4, r5, lr}
    2b02:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    2b04:	f7ff ffaa 	bl	2a5c <pin_in_use_by_te>
    2b08:	4c09      	ldr	r4, [pc, #36]	; (2b30 <pin_handler_trigger_uninit+0x30>)
    2b0a:	f102 0508 	add.w	r5, r2, #8
    2b0e:	b140      	cbz	r0, 2b22 <pin_handler_trigger_uninit+0x22>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    2b10:	f834 3015 	ldrh.w	r3, [r4, r5, lsl #1]
                         ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}

NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
    p_reg->CONFIG[idx] = 0;
    2b14:	4907      	ldr	r1, [pc, #28]	; (2b34 <pin_handler_trigger_uninit+0x34>)
        nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin));
    2b16:	0b5b      	lsrs	r3, r3, #13
    2b18:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    2b1c:	2000      	movs	r0, #0
    2b1e:	f841 0023 	str.w	r0, [r1, r3, lsl #2]
    release_handler(pin);
    2b22:	4610      	mov	r0, r2
    2b24:	f7ff ffc2 	bl	2aac <release_handler>
    m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED;
    2b28:	2300      	movs	r3, #0
    2b2a:	f824 3015 	strh.w	r3, [r4, r5, lsl #1]
}
    2b2e:	bd38      	pop	{r3, r4, r5, pc}
    2b30:	200000c8 	.word	0x200000c8
    2b34:	40006000 	.word	0x40006000

00002b38 <nrfx_gpiote_input_configure>:
{
    2b38:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    2b3c:	4604      	mov	r4, r0
    2b3e:	461d      	mov	r5, r3
    if (p_input_config)
    2b40:	b309      	cbz	r1, 2b86 <nrfx_gpiote_input_configure+0x4e>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2b42:	4f4f      	ldr	r7, [pc, #316]	; (2c80 <nrfx_gpiote_input_configure+0x148>)
    2b44:	f100 0808 	add.w	r8, r0, #8
    2b48:	f837 6018 	ldrh.w	r6, [r7, r8, lsl #1]
    return pin_is_output(pin) && pin_in_use_by_te(pin);
    2b4c:	07b3      	lsls	r3, r6, #30
    2b4e:	d506      	bpl.n	2b5e <nrfx_gpiote_input_configure+0x26>
    2b50:	f7ff ff84 	bl	2a5c <pin_in_use_by_te>
    2b54:	b118      	cbz	r0, 2b5e <nrfx_gpiote_input_configure+0x26>
            return NRFX_ERROR_INVALID_PARAM;
    2b56:	484b      	ldr	r0, [pc, #300]	; (2c84 <nrfx_gpiote_input_configure+0x14c>)
}
    2b58:	b002      	add	sp, #8
    2b5a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    *p_pin = pin_number & 0x1F;
    2b5e:	f004 031f 	and.w	r3, r4, #31
    2b62:	009b      	lsls	r3, r3, #2
    2b64:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    2b68:	7809      	ldrb	r1, [r1, #0]
    uint32_t cnf = reg->PIN_CNF[pin_number];
    2b6a:	f8d3 0700 	ldr.w	r0, [r3, #1792]	; 0x700
        m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT;
    2b6e:	f026 0602 	bic.w	r6, r6, #2
    cnf &= ~to_update;
    2b72:	f020 000f 	bic.w	r0, r0, #15
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    2b76:	f046 0601 	orr.w	r6, r6, #1
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    2b7a:	ea40 0181 	orr.w	r1, r0, r1, lsl #2
    2b7e:	f827 6018 	strh.w	r6, [r7, r8, lsl #1]
    reg->PIN_CNF[pin_number] = cnf;
    2b82:	f8c3 1700 	str.w	r1, [r3, #1792]	; 0x700
    if (p_trigger_config)
    2b86:	b19a      	cbz	r2, 2bb0 <nrfx_gpiote_input_configure+0x78>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2b88:	4b3d      	ldr	r3, [pc, #244]	; (2c80 <nrfx_gpiote_input_configure+0x148>)
        nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger;
    2b8a:	7817      	ldrb	r7, [r2, #0]
        bool use_evt = p_trigger_config->p_in_channel ? true : false;
    2b8c:	6850      	ldr	r0, [r2, #4]
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2b8e:	f104 0608 	add.w	r6, r4, #8
    2b92:	f833 1016 	ldrh.w	r1, [r3, r6, lsl #1]
        if (pin_is_output(pin))
    2b96:	f011 0f02 	tst.w	r1, #2
    2b9a:	d00d      	beq.n	2bb8 <nrfx_gpiote_input_configure+0x80>
            if (use_evt)
    2b9c:	2800      	cmp	r0, #0
    2b9e:	d1da      	bne.n	2b56 <nrfx_gpiote_input_configure+0x1e>
        m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK;
    2ba0:	f833 2016 	ldrh.w	r2, [r3, r6, lsl #1]
    2ba4:	f022 021c 	bic.w	r2, r2, #28
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    2ba8:	ea42 0287 	orr.w	r2, r2, r7, lsl #2
    2bac:	f823 2016 	strh.w	r2, [r3, r6, lsl #1]
    if (p_handler_config)
    2bb0:	2d00      	cmp	r5, #0
    2bb2:	d13b      	bne.n	2c2c <nrfx_gpiote_input_configure+0xf4>
        err = NRFX_SUCCESS;
    2bb4:	4834      	ldr	r0, [pc, #208]	; (2c88 <nrfx_gpiote_input_configure+0x150>)
    2bb6:	e7cf      	b.n	2b58 <nrfx_gpiote_input_configure+0x20>
            m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED);
    2bb8:	f021 0120 	bic.w	r1, r1, #32
    2bbc:	04c9      	lsls	r1, r1, #19
    2bbe:	0cc9      	lsrs	r1, r1, #19
    2bc0:	f823 1016 	strh.w	r1, [r3, r6, lsl #1]
            if (use_evt)
    2bc4:	2800      	cmp	r0, #0
    2bc6:	d0eb      	beq.n	2ba0 <nrfx_gpiote_input_configure+0x68>
                if (!edge)
    2bc8:	2f03      	cmp	r7, #3
    2bca:	d8c4      	bhi.n	2b56 <nrfx_gpiote_input_configure+0x1e>
                uint8_t ch = *p_trigger_config->p_in_channel;
    2bcc:	6852      	ldr	r2, [r2, #4]
    2bce:	f892 c000 	ldrb.w	ip, [r2]
                if (trigger == NRFX_GPIOTE_TRIGGER_NONE)
    2bd2:	b92f      	cbnz	r7, 2be0 <nrfx_gpiote_input_configure+0xa8>
    2bd4:	4a2d      	ldr	r2, [pc, #180]	; (2c8c <nrfx_gpiote_input_configure+0x154>)
    2bd6:	f50c 7ca2 	add.w	ip, ip, #324	; 0x144
    2bda:	f842 702c 	str.w	r7, [r2, ip, lsl #2]
#if defined(NRF53_SERIES) || defined(NRF91_SERIES)
    p_reg->CONFIG[idx] = 0;
#endif
}
    2bde:	e7df      	b.n	2ba0 <nrfx_gpiote_input_configure+0x68>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    2be0:	ea4f 028c 	mov.w	r2, ip, lsl #2
    2be4:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    2be8:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
                    m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    2bec:	ea41 314c 	orr.w	r1, r1, ip, lsl #13
    2bf0:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    2bf4:	f020 0003 	bic.w	r0, r0, #3
    2bf8:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    2bfc:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    2c00:	f420 3047 	bic.w	r0, r0, #203776	; 0x31c00
    2c04:	f420 7040 	bic.w	r0, r0, #768	; 0x300
    2c08:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2c0c:	0220      	lsls	r0, r4, #8
    2c0e:	f8d2 e510 	ldr.w	lr, [r2, #1296]	; 0x510
    2c12:	f400 50f8 	and.w	r0, r0, #7936	; 0x1f00
    2c16:	ea40 4007 	orr.w	r0, r0, r7, lsl #16
    2c1a:	ea40 000e 	orr.w	r0, r0, lr
    2c1e:	f041 0120 	orr.w	r1, r1, #32
    2c22:	f823 1016 	strh.w	r1, [r3, r6, lsl #1]
    2c26:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
    2c2a:	e7b9      	b.n	2ba0 <nrfx_gpiote_input_configure+0x68>
        err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context);
    2c2c:	e9d5 6700 	ldrd	r6, r7, [r5]
    release_handler(pin);
    2c30:	4620      	mov	r0, r4
    2c32:	f7ff ff3b 	bl	2aac <release_handler>
    if (!handler)
    2c36:	2e00      	cmp	r6, #0
    2c38:	d0bc      	beq.n	2bb4 <nrfx_gpiote_input_configure+0x7c>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    2c3a:	4d11      	ldr	r5, [pc, #68]	; (2c80 <nrfx_gpiote_input_configure+0x148>)
    2c3c:	e9d5 2300 	ldrd	r2, r3, [r5]
    2c40:	4296      	cmp	r6, r2
    2c42:	d101      	bne.n	2c48 <nrfx_gpiote_input_configure+0x110>
    2c44:	429f      	cmp	r7, r3
    2c46:	d019      	beq.n	2c7c <nrfx_gpiote_input_configure+0x144>
        err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id);
    2c48:	4811      	ldr	r0, [pc, #68]	; (2c90 <nrfx_gpiote_input_configure+0x158>)
    2c4a:	f10d 0107 	add.w	r1, sp, #7
    2c4e:	f7ff fdc5 	bl	27dc <nrfx_flag32_alloc>
        if (err != NRFX_SUCCESS)
    2c52:	4b0d      	ldr	r3, [pc, #52]	; (2c88 <nrfx_gpiote_input_configure+0x150>)
    2c54:	4298      	cmp	r0, r3
    2c56:	f47f af7f 	bne.w	2b58 <nrfx_gpiote_input_configure+0x20>
        handler_id = (int32_t)id;
    2c5a:	f89d 2007 	ldrb.w	r2, [sp, #7]
    m_cb.handlers[handler_id].handler = handler;
    2c5e:	f845 6032 	str.w	r6, [r5, r2, lsl #3]
    m_cb.handlers[handler_id].p_context = p_context;
    2c62:	eb05 03c2 	add.w	r3, r5, r2, lsl #3
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    2c66:	3408      	adds	r4, #8
    m_cb.handlers[handler_id].p_context = p_context;
    2c68:	605f      	str	r7, [r3, #4]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    2c6a:	f835 3014 	ldrh.w	r3, [r5, r4, lsl #1]
    2c6e:	ea43 2342 	orr.w	r3, r3, r2, lsl #9
    2c72:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    2c76:	f825 3014 	strh.w	r3, [r5, r4, lsl #1]
    return NRFX_SUCCESS;
    2c7a:	e79b      	b.n	2bb4 <nrfx_gpiote_input_configure+0x7c>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    2c7c:	2200      	movs	r2, #0
    2c7e:	e7ee      	b.n	2c5e <nrfx_gpiote_input_configure+0x126>
    2c80:	200000c8 	.word	0x200000c8
    2c84:	0bad0004 	.word	0x0bad0004
    2c88:	0bad0000 	.word	0x0bad0000
    2c8c:	40006000 	.word	0x40006000
    2c90:	2000011c 	.word	0x2000011c

00002c94 <nrfx_gpiote_output_configure>:
{
    2c94:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2c96:	4604      	mov	r4, r0
    if (p_config)
    2c98:	b389      	cbz	r1, 2cfe <nrfx_gpiote_output_configure+0x6a>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2c9a:	4e3a      	ldr	r6, [pc, #232]	; (2d84 <nrfx_gpiote_output_configure+0xf0>)
    2c9c:	f100 0708 	add.w	r7, r0, #8
    2ca0:	f836 5017 	ldrh.w	r5, [r6, r7, lsl #1]
        if (pin_is_input(pin) && pin_in_use_by_te(pin))
    2ca4:	07ab      	lsls	r3, r5, #30
    2ca6:	d404      	bmi.n	2cb2 <nrfx_gpiote_output_configure+0x1e>
    2ca8:	f7ff fed8 	bl	2a5c <pin_in_use_by_te>
    2cac:	b108      	cbz	r0, 2cb2 <nrfx_gpiote_output_configure+0x1e>
{
    2cae:	4836      	ldr	r0, [pc, #216]	; (2d88 <nrfx_gpiote_output_configure+0xf4>)
}
    2cb0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    2cb2:	f015 0f1c 	tst.w	r5, #28
    2cb6:	784b      	ldrb	r3, [r1, #1]
    2cb8:	d124      	bne.n	2d04 <nrfx_gpiote_output_configure+0x70>
    *p_pin = pin_number & 0x1F;
    2cba:	f004 001f 	and.w	r0, r4, #31
    uint32_t cnf = reg->PIN_CNF[pin_number];
    2cbe:	f500 7ee0 	add.w	lr, r0, #448	; 0x1c0
    2cc2:	f04f 4ca0 	mov.w	ip, #1342177280	; 0x50000000
           ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
    2cc6:	005b      	lsls	r3, r3, #1
    uint32_t cnf = reg->PIN_CNF[pin_number];
    2cc8:	f85c c02e 	ldr.w	ip, [ip, lr, lsl #2]
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    2ccc:	f891 e002 	ldrb.w	lr, [r1, #2]
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    2cd0:	7809      	ldrb	r1, [r1, #0]
    cnf &= ~to_update;
    2cd2:	f42c 6ce1 	bic.w	ip, ip, #1800	; 0x708
    2cd6:	ea43 038e 	orr.w	r3, r3, lr, lsl #2
    2cda:	f02c 0c07 	bic.w	ip, ip, #7
    2cde:	ea43 030c 	orr.w	r3, r3, ip
    2ce2:	ea43 2301 	orr.w	r3, r3, r1, lsl #8
    reg->PIN_CNF[pin_number] = cnf;
    2ce6:	f500 70e0 	add.w	r0, r0, #448	; 0x1c0
    2cea:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    2cee:	f043 0301 	orr.w	r3, r3, #1
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT;
    2cf2:	f045 0503 	orr.w	r5, r5, #3
    reg->PIN_CNF[pin_number] = cnf;
    2cf6:	f841 3020 	str.w	r3, [r1, r0, lsl #2]
    2cfa:	f826 5017 	strh.w	r5, [r6, r7, lsl #1]
    if (p_task_config)
    2cfe:	b922      	cbnz	r2, 2d0a <nrfx_gpiote_output_configure+0x76>
    return NRFX_SUCCESS;
    2d00:	4822      	ldr	r0, [pc, #136]	; (2d8c <nrfx_gpiote_output_configure+0xf8>)
    2d02:	e7d5      	b.n	2cb0 <nrfx_gpiote_output_configure+0x1c>
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    2d04:	2b01      	cmp	r3, #1
    2d06:	d1d8      	bne.n	2cba <nrfx_gpiote_output_configure+0x26>
    2d08:	e7d1      	b.n	2cae <nrfx_gpiote_output_configure+0x1a>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2d0a:	4e1e      	ldr	r6, [pc, #120]	; (2d84 <nrfx_gpiote_output_configure+0xf0>)
    2d0c:	f104 0708 	add.w	r7, r4, #8
    2d10:	f836 0017 	ldrh.w	r0, [r6, r7, lsl #1]
        if (pin_is_input(pin))
    2d14:	0783      	lsls	r3, r0, #30
    2d16:	d5ca      	bpl.n	2cae <nrfx_gpiote_output_configure+0x1a>
        uint32_t ch = p_task_config->task_ch;
    2d18:	f892 c000 	ldrb.w	ip, [r2]
    p_reg->CONFIG[idx] = 0;
    2d1c:	4661      	mov	r1, ip
    2d1e:	0089      	lsls	r1, r1, #2
        m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK);
    2d20:	f020 0020 	bic.w	r0, r0, #32
    2d24:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    2d28:	04c0      	lsls	r0, r0, #19
    2d2a:	f501 41c0 	add.w	r1, r1, #24576	; 0x6000
    2d2e:	0cc0      	lsrs	r0, r0, #19
    2d30:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    2d34:	2300      	movs	r3, #0
    2d36:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
        if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE)
    2d3a:	7855      	ldrb	r5, [r2, #1]
    2d3c:	2d00      	cmp	r5, #0
    2d3e:	d0df      	beq.n	2d00 <nrfx_gpiote_output_configure+0x6c>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
    2d40:	f8d1 3510 	ldr.w	r3, [r1, #1296]	; 0x510
                                      p_task_config->init_val);
    2d44:	7892      	ldrb	r2, [r2, #2]
    2d46:	f423 1398 	bic.w	r3, r3, #1245184	; 0x130000
    2d4a:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    2d4e:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2d52:	f8d1 e510 	ldr.w	lr, [r1, #1296]	; 0x510
    2d56:	0223      	lsls	r3, r4, #8
    2d58:	f403 53f8 	and.w	r3, r3, #7936	; 0x1f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    2d5c:	042d      	lsls	r5, r5, #16
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2d5e:	ea43 030e 	orr.w	r3, r3, lr
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    2d62:	f405 3540 	and.w	r5, r5, #196608	; 0x30000
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    2d66:	0512      	lsls	r2, r2, #20
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2d68:	432b      	orrs	r3, r5
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    2d6a:	f402 1280 	and.w	r2, r2, #1048576	; 0x100000
            m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    2d6e:	ea40 304c 	orr.w	r0, r0, ip, lsl #13
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2d72:	4313      	orrs	r3, r2
    2d74:	f040 0020 	orr.w	r0, r0, #32
    2d78:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    2d7c:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    2d80:	e7be      	b.n	2d00 <nrfx_gpiote_output_configure+0x6c>
    2d82:	bf00      	nop
    2d84:	200000c8 	.word	0x200000c8
    2d88:	0bad0004 	.word	0x0bad0004
    2d8c:	0bad0000 	.word	0x0bad0000

00002d90 <nrfx_gpiote_global_callback_set>:
    m_cb.global_handler.handler = handler;
    2d90:	4b01      	ldr	r3, [pc, #4]	; (2d98 <nrfx_gpiote_global_callback_set+0x8>)
    m_cb.global_handler.p_context = p_context;
    2d92:	e9c3 0102 	strd	r0, r1, [r3, #8]
}
    2d96:	4770      	bx	lr
    2d98:	200000c8 	.word	0x200000c8

00002d9c <nrfx_gpiote_channel_get>:
{
    2d9c:	b508      	push	{r3, lr}
    2d9e:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    2da0:	f7ff fe5c 	bl	2a5c <pin_in_use_by_te>
    2da4:	b138      	cbz	r0, 2db6 <nrfx_gpiote_channel_get+0x1a>
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    2da6:	4b05      	ldr	r3, [pc, #20]	; (2dbc <nrfx_gpiote_channel_get+0x20>)
        return NRFX_SUCCESS;
    2da8:	4805      	ldr	r0, [pc, #20]	; (2dc0 <nrfx_gpiote_channel_get+0x24>)
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    2daa:	3208      	adds	r2, #8
    2dac:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    2db0:	0b5b      	lsrs	r3, r3, #13
    2db2:	700b      	strb	r3, [r1, #0]
}
    2db4:	bd08      	pop	{r3, pc}
        return NRFX_ERROR_INVALID_PARAM;
    2db6:	4803      	ldr	r0, [pc, #12]	; (2dc4 <nrfx_gpiote_channel_get+0x28>)
    2db8:	e7fc      	b.n	2db4 <nrfx_gpiote_channel_get+0x18>
    2dba:	bf00      	nop
    2dbc:	200000c8 	.word	0x200000c8
    2dc0:	0bad0000 	.word	0x0bad0000
    2dc4:	0bad0004 	.word	0x0bad0004

00002dc8 <nrfx_gpiote_init>:
{
    2dc8:	b538      	push	{r3, r4, r5, lr}
    if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    2dca:	4c0f      	ldr	r4, [pc, #60]	; (2e08 <nrfx_gpiote_init+0x40>)
    2dcc:	f894 5058 	ldrb.w	r5, [r4, #88]	; 0x58
    2dd0:	b9bd      	cbnz	r5, 2e02 <nrfx_gpiote_init+0x3a>
    memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags));
    2dd2:	2240      	movs	r2, #64	; 0x40
    2dd4:	4629      	mov	r1, r5
    2dd6:	f104 0010 	add.w	r0, r4, #16
    2dda:	f001 fb21 	bl	4420 <memset>
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE));
    2dde:	2006      	movs	r0, #6
    2de0:	f7fe f93a 	bl	1058 <arch_irq_enable>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2de4:	4b09      	ldr	r3, [pc, #36]	; (2e0c <nrfx_gpiote_init+0x44>)
    return err_code;
    2de6:	480a      	ldr	r0, [pc, #40]	; (2e10 <nrfx_gpiote_init+0x48>)
    2de8:	f8c3 517c 	str.w	r5, [r3, #380]	; 0x17c
    2dec:	f8d3 217c 	ldr.w	r2, [r3, #380]	; 0x17c
    p_reg->INTENSET = mask;
    2df0:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    2df4:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    m_cb.state = NRFX_DRV_STATE_INITIALIZED;
    2df8:	2301      	movs	r3, #1
    2dfa:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS);
    2dfe:	6563      	str	r3, [r4, #84]	; 0x54
}
    2e00:	bd38      	pop	{r3, r4, r5, pc}
        return err_code;
    2e02:	4804      	ldr	r0, [pc, #16]	; (2e14 <nrfx_gpiote_init+0x4c>)
    2e04:	e7fc      	b.n	2e00 <nrfx_gpiote_init+0x38>
    2e06:	bf00      	nop
    2e08:	200000c8 	.word	0x200000c8
    2e0c:	40006000 	.word	0x40006000
    2e10:	0bad0000 	.word	0x0bad0000
    2e14:	0bad0005 	.word	0x0bad0005

00002e18 <nrfx_gpiote_is_init>:
    return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false;
    2e18:	4b03      	ldr	r3, [pc, #12]	; (2e28 <nrfx_gpiote_is_init+0x10>)
    2e1a:	f893 0058 	ldrb.w	r0, [r3, #88]	; 0x58
}
    2e1e:	3800      	subs	r0, #0
    2e20:	bf18      	it	ne
    2e22:	2001      	movne	r0, #1
    2e24:	4770      	bx	lr
    2e26:	bf00      	nop
    2e28:	200000c8 	.word	0x200000c8

00002e2c <nrfx_gpiote_channel_free>:
{
    2e2c:	4601      	mov	r1, r0
    return nrfx_flag32_free(&m_cb.available_channels_mask, channel);
    2e2e:	4801      	ldr	r0, [pc, #4]	; (2e34 <nrfx_gpiote_channel_free+0x8>)
    2e30:	f7ff bcf4 	b.w	281c <nrfx_flag32_free>
    2e34:	20000118 	.word	0x20000118

00002e38 <nrfx_gpiote_channel_alloc>:
{
    2e38:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel);
    2e3a:	4801      	ldr	r0, [pc, #4]	; (2e40 <nrfx_gpiote_channel_alloc+0x8>)
    2e3c:	f7ff bcce 	b.w	27dc <nrfx_flag32_alloc>
    2e40:	20000118 	.word	0x20000118

00002e44 <nrfx_gpiote_trigger_enable>:
{
    2e44:	b510      	push	{r4, lr}
    2e46:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    2e48:	f7ff fe08 	bl	2a5c <pin_in_use_by_te>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2e4c:	f102 0408 	add.w	r4, r2, #8
    2e50:	4b1c      	ldr	r3, [pc, #112]	; (2ec4 <nrfx_gpiote_trigger_enable+0x80>)
    2e52:	f833 3014 	ldrh.w	r3, [r3, r4, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    2e56:	b1e0      	cbz	r0, 2e92 <nrfx_gpiote_trigger_enable+0x4e>
    2e58:	f013 0402 	ands.w	r4, r3, #2
    2e5c:	d119      	bne.n	2e92 <nrfx_gpiote_trigger_enable+0x4e>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    2e5e:	0b5b      	lsrs	r3, r3, #13
#endif

NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
{
    NRFX_ASSERT(index < GPIOTE_CH_NUM);
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    2e60:	009a      	lsls	r2, r3, #2
    return ((uint32_t)p_reg + event);
    2e62:	f102 4080 	add.w	r0, r2, #1073741824	; 0x40000000
    2e66:	f500 40c2 	add.w	r0, r0, #24832	; 0x6100
    2e6a:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    2e6e:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2e72:	6004      	str	r4, [r0, #0]
    2e74:	6800      	ldr	r0, [r0, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    2e76:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    2e7a:	f040 0001 	orr.w	r0, r0, #1
    2e7e:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
        if (int_enable)
    2e82:	b129      	cbz	r1, 2e90 <nrfx_gpiote_trigger_enable+0x4c>
            nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch));
    2e84:	2201      	movs	r2, #1
    2e86:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->INTENSET = mask;
    2e8a:	4a0f      	ldr	r2, [pc, #60]	; (2ec8 <nrfx_gpiote_trigger_enable+0x84>)
    2e8c:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    2e90:	bd10      	pop	{r4, pc}
    nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    2e92:	f3c3 0382 	ubfx	r3, r3, #2, #3
    if (trigger == NRFX_GPIOTE_TRIGGER_LOW)
    2e96:	2b04      	cmp	r3, #4
    2e98:	d010      	beq.n	2ebc <nrfx_gpiote_trigger_enable+0x78>
    else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH)
    2e9a:	2b05      	cmp	r3, #5
    2e9c:	d010      	beq.n	2ec0 <nrfx_gpiote_trigger_enable+0x7c>
    return p_reg->IN;
    2e9e:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    2ea2:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
    *p_pin = pin_number & 0x1F;
    2ea6:	f002 031f 	and.w	r3, r2, #31
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    2eaa:	40d9      	lsrs	r1, r3
    2eac:	f001 0101 	and.w	r1, r1, #1
    2eb0:	3102      	adds	r1, #2
}
    2eb2:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    2eb6:	4610      	mov	r0, r2
    2eb8:	f001 bd6b 	b.w	4992 <nrf_gpio_cfg_sense_set>
        sense = NRF_GPIO_PIN_SENSE_LOW;
    2ebc:	2103      	movs	r1, #3
    2ebe:	e7f8      	b.n	2eb2 <nrfx_gpiote_trigger_enable+0x6e>
        sense = NRF_GPIO_PIN_SENSE_HIGH;
    2ec0:	2102      	movs	r1, #2
    2ec2:	e7f6      	b.n	2eb2 <nrfx_gpiote_trigger_enable+0x6e>
    2ec4:	200000c8 	.word	0x200000c8
    2ec8:	40006000 	.word	0x40006000

00002ecc <nrfx_gpiote_trigger_disable>:
{
    2ecc:	b508      	push	{r3, lr}
    2ece:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    2ed0:	f7ff fdc4 	bl	2a5c <pin_in_use_by_te>
    2ed4:	b1c0      	cbz	r0, 2f08 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2ed6:	f102 0108 	add.w	r1, r2, #8
    2eda:	4b0e      	ldr	r3, [pc, #56]	; (2f14 <nrfx_gpiote_trigger_disable+0x48>)
    2edc:	f833 3011 	ldrh.w	r3, [r3, r1, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    2ee0:	0799      	lsls	r1, r3, #30
    2ee2:	d411      	bmi.n	2f08 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    2ee4:	0b5b      	lsrs	r3, r3, #13
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    2ee6:	2201      	movs	r2, #1
    2ee8:	409a      	lsls	r2, r3
    p_reg->INTENCLR = mask;
    2eea:	009b      	lsls	r3, r3, #2
    2eec:	490a      	ldr	r1, [pc, #40]	; (2f18 <nrfx_gpiote_trigger_disable+0x4c>)
    2eee:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    2ef2:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    2ef6:	f8c1 2308 	str.w	r2, [r1, #776]	; 0x308
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    2efa:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    2efe:	f022 0203 	bic.w	r2, r2, #3
    2f02:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    2f06:	bd08      	pop	{r3, pc}
    2f08:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    2f0c:	2100      	movs	r1, #0
    2f0e:	4610      	mov	r0, r2
    2f10:	f001 bd3f 	b.w	4992 <nrf_gpio_cfg_sense_set>
    2f14:	200000c8 	.word	0x200000c8
    2f18:	40006000 	.word	0x40006000

00002f1c <nrfx_gpiote_pin_uninit>:
{
    2f1c:	b510      	push	{r4, lr}
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    2f1e:	4b0d      	ldr	r3, [pc, #52]	; (2f54 <nrfx_gpiote_pin_uninit+0x38>)
    2f20:	f100 0208 	add.w	r2, r0, #8
{
    2f24:	4604      	mov	r4, r0
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    2f26:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (!pin_in_use(pin))
    2f2a:	07db      	lsls	r3, r3, #31
    2f2c:	d50f      	bpl.n	2f4e <nrfx_gpiote_pin_uninit+0x32>
    nrfx_gpiote_trigger_disable(pin);
    2f2e:	f7ff ffcd 	bl	2ecc <nrfx_gpiote_trigger_disable>
    pin_handler_trigger_uninit(pin);
    2f32:	4620      	mov	r0, r4
    *p_pin = pin_number & 0x1F;
    2f34:	f004 041f 	and.w	r4, r4, #31
    2f38:	f7ff fde2 	bl	2b00 <pin_handler_trigger_uninit>
    reg->PIN_CNF[pin_number] = cnf;
    2f3c:	f504 74e0 	add.w	r4, r4, #448	; 0x1c0
    2f40:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    2f44:	2202      	movs	r2, #2
    2f46:	f843 2024 	str.w	r2, [r3, r4, lsl #2]
    2f4a:	4803      	ldr	r0, [pc, #12]	; (2f58 <nrfx_gpiote_pin_uninit+0x3c>)
}
    2f4c:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    2f4e:	4803      	ldr	r0, [pc, #12]	; (2f5c <nrfx_gpiote_pin_uninit+0x40>)
    2f50:	e7fc      	b.n	2f4c <nrfx_gpiote_pin_uninit+0x30>
    2f52:	bf00      	nop
    2f54:	200000c8 	.word	0x200000c8
    2f58:	0bad0000 	.word	0x0bad0000
    2f5c:	0bad0004 	.word	0x0bad0004

00002f60 <nrfx_gpiote_irq_handler>:
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    }
}

void nrfx_gpiote_irq_handler(void)
{
    2f60:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    2f64:	4b4f      	ldr	r3, [pc, #316]	; (30a4 <nrfx_gpiote_irq_handler+0x144>)
    return p_reg->INTENSET & mask;
    2f66:	4850      	ldr	r0, [pc, #320]	; (30a8 <nrfx_gpiote_irq_handler+0x148>)
    uint32_t i;
    nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0;
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;

    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    2f68:	4950      	ldr	r1, [pc, #320]	; (30ac <nrfx_gpiote_irq_handler+0x14c>)
    uint32_t status = 0;
    2f6a:	2500      	movs	r5, #0
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
    2f6c:	2201      	movs	r2, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2f6e:	462c      	mov	r4, r5
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2f70:	681e      	ldr	r6, [r3, #0]
    {
        if (nrf_gpiote_event_check(NRF_GPIOTE, event) &&
    2f72:	b136      	cbz	r6, 2f82 <nrfx_gpiote_irq_handler+0x22>
    return p_reg->INTENSET & mask;
    2f74:	f8d0 6304 	ldr.w	r6, [r0, #772]	; 0x304
    2f78:	4216      	tst	r6, r2
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2f7a:	bf1e      	ittt	ne
    2f7c:	601c      	strne	r4, [r3, #0]
    2f7e:	681e      	ldrne	r6, [r3, #0]
            nrf_gpiote_int_enable_check(NRF_GPIOTE, mask))
        {
            nrf_gpiote_event_clear(NRF_GPIOTE, event);
            status |= mask;
    2f80:	4315      	orrne	r5, r2
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    2f82:	3304      	adds	r3, #4
    2f84:	428b      	cmp	r3, r1
        }
        mask <<= 1;
    2f86:	ea4f 0242 	mov.w	r2, r2, lsl #1
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    2f8a:	d1f1      	bne.n	2f70 <nrfx_gpiote_irq_handler+0x10>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2f8c:	4b46      	ldr	r3, [pc, #280]	; (30a8 <nrfx_gpiote_irq_handler+0x148>)
    2f8e:	f8d3 317c 	ldr.w	r3, [r3, #380]	; 0x17c
         * in ascending order. */
        event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t));
    }

    /* handle PORT event */
    if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
    2f92:	b1bb      	cbz	r3, 2fc4 <nrfx_gpiote_irq_handler+0x64>
        *p_masks = gpio_regs[i]->LATCH;
    2f94:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
    2f98:	f8d6 3520 	ldr.w	r3, [r6, #1312]	; 0x520
    2f9c:	9301      	str	r3, [sp, #4]
        gpio_regs[i]->LATCH = *p_masks;
    2f9e:	f8c6 3520 	str.w	r3, [r6, #1312]	; 0x520
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
    uint8_t * p_mask8 = (uint8_t *)p_mask;
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    bit = BITMASK_RELBIT_GET(bit);
    p_mask8[byte_idx] &= ~(1 << bit);
    2fa2:	af01      	add	r7, sp, #4
    2fa4:	f04f 0801 	mov.w	r8, #1
            while (latch[i])
    2fa8:	9c01      	ldr	r4, [sp, #4]
    2faa:	b98c      	cbnz	r4, 2fd0 <nrfx_gpiote_irq_handler+0x70>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2fac:	4b3e      	ldr	r3, [pc, #248]	; (30a8 <nrfx_gpiote_irq_handler+0x148>)
    2fae:	f8c3 417c 	str.w	r4, [r3, #380]	; 0x17c
    2fb2:	f8d3 317c 	ldr.w	r3, [r3, #380]	; 0x17c
        *p_masks = gpio_regs[i]->LATCH;
    2fb6:	f8d6 3520 	ldr.w	r3, [r6, #1312]	; 0x520
    2fba:	9301      	str	r3, [sp, #4]
        gpio_regs[i]->LATCH = *p_masks;
    2fbc:	f8c6 3520 	str.w	r3, [r6, #1312]	; 0x520
        if (latch[port_idx])
    2fc0:	2b00      	cmp	r3, #0
    2fc2:	d1ee      	bne.n	2fa2 <nrfx_gpiote_irq_handler+0x42>
        mask &= ~NRFX_BIT(ch);
    2fc4:	2401      	movs	r4, #1
    while (mask)
    2fc6:	2d00      	cmp	r5, #0
    2fc8:	d153      	bne.n	3072 <nrfx_gpiote_irq_handler+0x112>
        port_event_handle();
    }

    /* Process pin events. */
    gpiote_evt_handle(status);
}
    2fca:	b003      	add	sp, #12
    2fcc:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
                uint32_t pin = NRF_CTZ(latch[i]);
    2fd0:	fa94 f4a4 	rbit	r4, r4
    2fd4:	fab4 f484 	clz	r4, r4
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    2fd8:	4a35      	ldr	r2, [pc, #212]	; (30b0 <nrfx_gpiote_irq_handler+0x150>)
    2fda:	f104 0308 	add.w	r3, r4, #8
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    2fde:	08e0      	lsrs	r0, r4, #3
    2fe0:	f832 1013 	ldrh.w	r1, [r2, r3, lsl #1]
    p_mask8[byte_idx] &= ~(1 << bit);
    2fe4:	5c3b      	ldrb	r3, [r7, r0]
    bit = BITMASK_RELBIT_GET(bit);
    2fe6:	f004 0207 	and.w	r2, r4, #7
    p_mask8[byte_idx] &= ~(1 << bit);
    2fea:	fa08 f202 	lsl.w	r2, r8, r2
    2fee:	ea23 0302 	bic.w	r3, r3, r2
    2ff2:	543b      	strb	r3, [r7, r0]
    2ff4:	00a3      	lsls	r3, r4, #2
    2ff6:	f103 49a0 	add.w	r9, r3, #1342177280	; 0x50000000
    2ffa:	f3c1 0a82 	ubfx	sl, r1, #2, #3
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    2ffe:	f8d9 2700 	ldr.w	r2, [r9, #1792]	; 0x700
    if (is_level(trigger))
    3002:	06cb      	lsls	r3, r1, #27
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3004:	46d3      	mov	fp, sl
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    3006:	f3c2 4201 	ubfx	r2, r2, #16, #2
    if (is_level(trigger))
    300a:	d518      	bpl.n	303e <nrfx_gpiote_irq_handler+0xde>
        call_handler(pin, trigger);
    300c:	4659      	mov	r1, fp
    300e:	4620      	mov	r0, r4
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    3010:	fa5f fa82 	uxtb.w	sl, r2
    3014:	f7ff fd2c 	bl	2a70 <call_handler>
    3018:	f8d9 3700 	ldr.w	r3, [r9, #1792]	; 0x700
        if (nrf_gpio_pin_sense_get(pin) == sense)
    301c:	f3c3 4301 	ubfx	r3, r3, #16, #2
    3020:	459a      	cmp	sl, r3
    3022:	d107      	bne.n	3034 <nrfx_gpiote_irq_handler+0xd4>
            nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    3024:	2100      	movs	r1, #0
    3026:	4620      	mov	r0, r4
    3028:	f001 fcb3 	bl	4992 <nrf_gpio_cfg_sense_set>
            nrf_gpio_cfg_sense_set(pin, sense);
    302c:	4651      	mov	r1, sl
    302e:	4620      	mov	r0, r4
    3030:	f001 fcaf 	bl	4992 <nrf_gpio_cfg_sense_set>
    reg->LATCH = (1 << pin_number);
    3034:	fa08 f404 	lsl.w	r4, r8, r4
    3038:	f8c6 4520 	str.w	r4, [r6, #1312]	; 0x520
}
    303c:	e7b4      	b.n	2fa8 <nrfx_gpiote_irq_handler+0x48>
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    303e:	2a02      	cmp	r2, #2
    3040:	d10c      	bne.n	305c <nrfx_gpiote_irq_handler+0xfc>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    3042:	2103      	movs	r1, #3
    3044:	4620      	mov	r0, r4
    3046:	f001 fca4 	bl	4992 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    304a:	f00a 0305 	and.w	r3, sl, #5
    304e:	2b01      	cmp	r3, #1
    3050:	d1f0      	bne.n	3034 <nrfx_gpiote_irq_handler+0xd4>
            call_handler(pin, trigger);
    3052:	4659      	mov	r1, fp
    3054:	4620      	mov	r0, r4
    3056:	f7ff fd0b 	bl	2a70 <call_handler>
    305a:	e7eb      	b.n	3034 <nrfx_gpiote_irq_handler+0xd4>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    305c:	2102      	movs	r1, #2
    305e:	4620      	mov	r0, r4
    3060:	f001 fc97 	bl	4992 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    3064:	f1ba 0f03 	cmp.w	sl, #3
    3068:	d0f3      	beq.n	3052 <nrfx_gpiote_irq_handler+0xf2>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    306a:	2a03      	cmp	r2, #3
    306c:	d1e2      	bne.n	3034 <nrfx_gpiote_irq_handler+0xd4>
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    306e:	458a      	cmp	sl, r1
    3070:	e7ee      	b.n	3050 <nrfx_gpiote_irq_handler+0xf0>
        uint32_t ch = NRF_CTZ(mask);
    3072:	fa95 f3a5 	rbit	r3, r5
    3076:	fab3 f383 	clz	r3, r3
        mask &= ~NRFX_BIT(ch);
    307a:	fa04 f203 	lsl.w	r2, r4, r3
    307e:	009b      	lsls	r3, r3, #2
    3080:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    3084:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    3088:	ea25 0502 	bic.w	r5, r5, r2
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    308c:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    3090:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    3094:	f3c0 2004 	ubfx	r0, r0, #8, #5
    3098:	f3c1 4101 	ubfx	r1, r1, #16, #2
    309c:	f7ff fce8 	bl	2a70 <call_handler>
    30a0:	e791      	b.n	2fc6 <nrfx_gpiote_irq_handler+0x66>
    30a2:	bf00      	nop
    30a4:	40006100 	.word	0x40006100
    30a8:	40006000 	.word	0x40006000
    30ac:	40006120 	.word	0x40006120
    30b0:	200000c8 	.word	0x200000c8

000030b4 <nrfx_spi_init>:

nrfx_err_t nrfx_spi_init(nrfx_spi_t const *        p_instance,
                         nrfx_spi_config_t const * p_config,
                         nrfx_spi_evt_handler_t    handler,
                         void *                    p_context)
{
    30b4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    NRFX_ASSERT(p_config);
    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    30b6:	7906      	ldrb	r6, [r0, #4]
    NRF_SPI_Type * p_spi = p_instance->p_reg;
    nrfx_err_t err_code;

    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    30b8:	4c52      	ldr	r4, [pc, #328]	; (3204 <nrfx_spi_init+0x150>)
    30ba:	f04f 0c28 	mov.w	ip, #40	; 0x28
    30be:	fb0c fc06 	mul.w	ip, ip, r6
    30c2:	eb04 070c 	add.w	r7, r4, ip
    30c6:	7f3d      	ldrb	r5, [r7, #28]
    30c8:	2d00      	cmp	r5, #0
    30ca:	f040 8098 	bne.w	31fe <nrfx_spi_init+0x14a>
    NRF_SPI_Type * p_spi = p_instance->p_reg;
    30ce:	6805      	ldr	r5, [r0, #0]
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
#endif // NRFX_CHECK(NRFX_PRS_ENABLED)

    p_cb->handler = handler;
    30d0:	f844 200c 	str.w	r2, [r4, ip]
    p_cb->p_context = p_context;
    30d4:	607b      	str	r3, [r7, #4]

    p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg;
    30d6:	7bcb      	ldrb	r3, [r1, #15]
    30d8:	f887 3025 	strb.w	r3, [r7, #37]	; 0x25
    p_cb->ss_pin = p_config->ss_pin;
    30dc:	78cb      	ldrb	r3, [r1, #3]
    30de:	77bb      	strb	r3, [r7, #30]
    p_cb->orc = p_config->orc;
    30e0:	794b      	ldrb	r3, [r1, #5]
    30e2:	77fb      	strb	r3, [r7, #31]
    if (!p_config->skip_gpio_cfg)
    30e4:	7bcb      	ldrb	r3, [r1, #15]
    30e6:	2b00      	cmp	r3, #0
    30e8:	d149      	bne.n	317e <nrfx_spi_init+0xca>
    *p_pin = pin_number & 0x1F;
    30ea:	780f      	ldrb	r7, [r1, #0]
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    30ec:	2301      	movs	r3, #1
    *p_pin = pin_number & 0x1F;
    30ee:	f007 071f 	and.w	r7, r7, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    30f2:	40bb      	lsls	r3, r7
    if (value == 0)
    30f4:	7b0f      	ldrb	r7, [r1, #12]
    30f6:	2f01      	cmp	r7, #1
    30f8:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    30fc:	f04f 4ca0 	mov.w	ip, #1342177280	; 0x50000000
    p_reg->OUTCLR = clr_mask;
    3100:	bf94      	ite	ls
    3102:	f8c7 350c 	strls.w	r3, [r7, #1292]	; 0x50c
    p_reg->OUTSET = set_mask;
    3106:	f8c7 3508 	strhi.w	r3, [r7, #1288]	; 0x508
    *p_pin = pin_number & 0x1F;
    310a:	780b      	ldrb	r3, [r1, #0]
    310c:	f003 031f 	and.w	r3, r3, #31
    reg->PIN_CNF[pin_number] = cnf;
    3110:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    3114:	2701      	movs	r7, #1
    3116:	f84c 7023 	str.w	r7, [ip, r3, lsl #2]
        if (p_config->mosi_pin != NRFX_SPI_PIN_NOT_USED)
    311a:	784b      	ldrb	r3, [r1, #1]
    311c:	2bff      	cmp	r3, #255	; 0xff
    311e:	d00c      	beq.n	313a <nrfx_spi_init+0x86>
    *p_pin = pin_number & 0x1F;
    3120:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    3124:	409f      	lsls	r7, r3
    p_reg->OUTCLR = clr_mask;
    3126:	f8cc 750c 	str.w	r7, [ip, #1292]	; 0x50c
    *p_pin = pin_number & 0x1F;
    312a:	784b      	ldrb	r3, [r1, #1]
    312c:	f003 031f 	and.w	r3, r3, #31
    reg->PIN_CNF[pin_number] = cnf;
    3130:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    3134:	2703      	movs	r7, #3
    3136:	f84c 7023 	str.w	r7, [ip, r3, lsl #2]
        if (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED)
    313a:	788b      	ldrb	r3, [r1, #2]
    313c:	2bff      	cmp	r3, #255	; 0xff
    313e:	d009      	beq.n	3154 <nrfx_spi_init+0xa0>
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    3140:	7b8f      	ldrb	r7, [r1, #14]
    *p_pin = pin_number & 0x1F;
    3142:	f003 031f 	and.w	r3, r3, #31
    reg->PIN_CNF[pin_number] = cnf;
    3146:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    314a:	f04f 4ca0 	mov.w	ip, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    314e:	00bf      	lsls	r7, r7, #2
    reg->PIN_CNF[pin_number] = cnf;
    3150:	f84c 7023 	str.w	r7, [ip, r3, lsl #2]
        if (p_config->ss_pin != NRFX_SPI_PIN_NOT_USED)
    3154:	78cb      	ldrb	r3, [r1, #3]
    3156:	2bff      	cmp	r3, #255	; 0xff
    3158:	d011      	beq.n	317e <nrfx_spi_init+0xca>
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    315a:	2701      	movs	r7, #1
    *p_pin = pin_number & 0x1F;
    315c:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    3160:	fa07 f303 	lsl.w	r3, r7, r3
    p_reg->OUTSET = set_mask;
    3164:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    3168:	f04f 0c03 	mov.w	ip, #3
    p_reg->OUTSET = set_mask;
    316c:	f8c7 3508 	str.w	r3, [r7, #1288]	; 0x508
    *p_pin = pin_number & 0x1F;
    3170:	78cb      	ldrb	r3, [r1, #3]
    3172:	f003 031f 	and.w	r3, r3, #31
    reg->PIN_CNF[pin_number] = cnf;
    3176:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    317a:	f847 c023 	str.w	ip, [r7, r3, lsl #2]
    if (!p_config->skip_psel_cfg)
    317e:	7c0b      	ldrb	r3, [r1, #16]
    3180:	b99b      	cbnz	r3, 31aa <nrfx_spi_init+0xf6>
        uint32_t mosi_pin = (p_config->mosi_pin != NRFX_SPI_PIN_NOT_USED)
    3182:	784b      	ldrb	r3, [r1, #1]
        nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin);
    3184:	f891 c000 	ldrb.w	ip, [r1]
                            : NRF_SPI_PIN_NOT_CONNECTED;
    3188:	2bff      	cmp	r3, #255	; 0xff
    318a:	bf18      	it	ne
    318c:	461f      	movne	r7, r3
        uint32_t miso_pin = (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED)
    318e:	788b      	ldrb	r3, [r1, #2]
                                        uint32_t       miso_pin)
{
#if defined(SPI_PSEL_SCK_CONNECT_Pos)
    p_reg->PSEL.SCK = sck_pin;
#else
    p_reg->PSELSCK  = sck_pin;
    3190:	f8c5 c508 	str.w	ip, [r5, #1288]	; 0x508
                            : NRF_SPI_PIN_NOT_CONNECTED;
    3194:	bf08      	it	eq
    3196:	f04f 37ff 	moveq.w	r7, #4294967295
                            : NRF_SPI_PIN_NOT_CONNECTED;
    319a:	2bff      	cmp	r3, #255	; 0xff
    319c:	bf08      	it	eq
    319e:	f04f 33ff 	moveq.w	r3, #4294967295
#endif

#if defined(SPI_PSEL_MOSI_CONNECT_Pos)
    p_reg->PSEL.MOSI = mosi_pin;
#else
    p_reg->PSELMOSI = mosi_pin;
    31a2:	f8c5 750c 	str.w	r7, [r5, #1292]	; 0x50c
#endif

#if defined(SPI_PSEL_MISO_CONNECT_Pos)
    p_reg->PSEL.MISO = miso_pin;
#else
    p_reg->PSELMISO = miso_pin;
    31a6:	f8c5 3510 	str.w	r3, [r5, #1296]	; 0x510
}

NRF_STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type *      p_reg,
                                             nrf_spi_frequency_t frequency)
{
    p_reg->FREQUENCY = (uint32_t)frequency;
    31aa:	688b      	ldr	r3, [r1, #8]
    31ac:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
NRF_STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type *      p_reg,
                                         nrf_spi_mode_t      spi_mode,
                                         nrf_spi_bit_order_t spi_bit_order)
{
    uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ?
        SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst);
    31b0:	7b4b      	ldrb	r3, [r1, #13]

    configure_pins(p_spi, p_config);

    nrf_spi_frequency_set(p_spi, p_config->frequency);
    nrf_spi_configure(p_spi, p_config->mode, p_config->bit_order);
    31b2:	7b0f      	ldrb	r7, [r1, #12]
    31b4:	3b00      	subs	r3, #0
    31b6:	bf18      	it	ne
    31b8:	2301      	movne	r3, #1
    switch (spi_mode)
    31ba:	2f02      	cmp	r7, #2
    31bc:	d019      	beq.n	31f2 <nrfx_spi_init+0x13e>
    31be:	2f03      	cmp	r7, #3
    31c0:	d01a      	beq.n	31f8 <nrfx_spi_init+0x144>
    31c2:	2f01      	cmp	r7, #1
    31c4:	d101      	bne.n	31ca <nrfx_spi_init+0x116>
        config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
                  (SPI_CONFIG_CPHA_Leading    << SPI_CONFIG_CPHA_Pos);
        break;

    case NRF_SPI_MODE_1:
        config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
    31c6:	f043 0302 	orr.w	r3, r3, #2
    case NRF_SPI_MODE_3:
        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
                  (SPI_CONFIG_CPHA_Trailing   << SPI_CONFIG_CPHA_Pos);
        break;
    }
    p_reg->CONFIG = config;
    31ca:	f8c5 3554 	str.w	r3, [r5, #1364]	; 0x554
    p_reg->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
    31ce:	2301      	movs	r3, #1
    31d0:	f8c5 3500 	str.w	r3, [r5, #1280]	; 0x500

    nrf_spi_enable(p_spi);

    if (p_cb->handler)
    31d4:	b122      	cbz	r2, 31e0 <nrfx_spi_init+0x12c>
    return ((((uint32_t)p_object) & 0x3u) == 0u);
}

NRF_STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg)
{
    return (IRQn_Type)NRFX_IRQ_NUMBER_GET(p_reg);
    31d6:	6800      	ldr	r0, [r0, #0]
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg),
            p_config->irq_priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg));
    31d8:	f340 3007 	sbfx	r0, r0, #12, #8
    31dc:	f7fd ff3c 	bl	1058 <arch_irq_enable>
    }

    p_cb->transfer_in_progress = false;
    31e0:	2328      	movs	r3, #40	; 0x28
    31e2:	fb03 4406 	mla	r4, r3, r6, r4
    31e6:	2300      	movs	r3, #0
    31e8:	7763      	strb	r3, [r4, #29]
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;

    err_code = NRFX_SUCCESS;
    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
    31ea:	4807      	ldr	r0, [pc, #28]	; (3208 <nrfx_spi_init+0x154>)
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    31ec:	2301      	movs	r3, #1
    31ee:	7723      	strb	r3, [r4, #28]
}
    31f0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
    31f2:	f043 0304 	orr.w	r3, r3, #4
        break;
    31f6:	e7e8      	b.n	31ca <nrfx_spi_init+0x116>
        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
    31f8:	f043 0306 	orr.w	r3, r3, #6
        break;
    31fc:	e7e5      	b.n	31ca <nrfx_spi_init+0x116>
        return err_code;
    31fe:	4803      	ldr	r0, [pc, #12]	; (320c <nrfx_spi_init+0x158>)
    3200:	e7f6      	b.n	31f0 <nrfx_spi_init+0x13c>
    3202:	bf00      	nop
    3204:	20000330 	.word	0x20000330
    3208:	0bad0000 	.word	0x0bad0000
    320c:	0bad0005 	.word	0x0bad0005

00003210 <nrfx_spi_uninit>:

void nrfx_spi_uninit(nrfx_spi_t const * p_instance)
{
    3210:	b570      	push	{r4, r5, r6, lr}
    spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    3212:	7906      	ldrb	r6, [r0, #4]
    NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
    NRF_SPI_Type * p_spi = p_instance->p_reg;

    if (p_cb->handler)
    3214:	4c26      	ldr	r4, [pc, #152]	; (32b0 <nrfx_spi_uninit+0xa0>)
    NRF_SPI_Type * p_spi = p_instance->p_reg;
    3216:	6805      	ldr	r5, [r0, #0]
    if (p_cb->handler)
    3218:	2328      	movs	r3, #40	; 0x28
    321a:	4373      	muls	r3, r6
    321c:	58e3      	ldr	r3, [r4, r3]
    321e:	b133      	cbz	r3, 322e <nrfx_spi_uninit+0x1e>
    {
        NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg));
    3220:	f345 3007 	sbfx	r0, r5, #12, #8
    3224:	f7fd ff26 	bl	1074 <arch_irq_disable>
    p_reg->INTENCLR = mask;
    3228:	2304      	movs	r3, #4
    322a:	f8c5 3308 	str.w	r3, [r5, #776]	; 0x308
    p_reg->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
    322e:	2300      	movs	r3, #0
    3230:	f8c5 3500 	str.w	r3, [r5, #1280]	; 0x500
        nrf_spi_int_disable(p_spi, NRF_SPI_ALL_INTS_MASK);
    }

    nrf_spi_disable(p_spi);

    if (!p_cb->skip_gpio_cfg)
    3234:	2328      	movs	r3, #40	; 0x28
    3236:	fb03 4306 	mla	r3, r3, r6, r4
    323a:	f893 3025 	ldrb.w	r3, [r3, #37]	; 0x25
    323e:	bb83      	cbnz	r3, 32a2 <nrfx_spi_uninit+0x92>
    return p_reg->PSELSCK;
    3240:	f8d5 3508 	ldr.w	r3, [r5, #1288]	; 0x508
    *p_pin = pin_number & 0x1F;
    3244:	f003 031f 	and.w	r3, r3, #31
    reg->PIN_CNF[pin_number] = cnf;
    3248:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    324c:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    3250:	2102      	movs	r1, #2
    3252:	f842 1023 	str.w	r1, [r2, r3, lsl #2]
    return p_reg->PSELMISO;
    3256:	f8d5 3510 	ldr.w	r3, [r5, #1296]	; 0x510
    {
        nrf_gpio_cfg_default(nrf_spi_sck_pin_get(p_spi));

        uint32_t miso_pin = nrf_spi_miso_pin_get(p_spi);
        if (miso_pin != NRF_SPI_PIN_NOT_CONNECTED)
    325a:	1c58      	adds	r0, r3, #1
    *p_pin = pin_number & 0x1F;
    325c:	bf1e      	ittt	ne
    325e:	f003 031f 	andne.w	r3, r3, #31
    reg->PIN_CNF[pin_number] = cnf;
    3262:	f503 73e0 	addne.w	r3, r3, #448	; 0x1c0
    3266:	f842 1023 	strne.w	r1, [r2, r3, lsl #2]
    return p_reg->PSELMOSI;
    326a:	f8d5 350c 	ldr.w	r3, [r5, #1292]	; 0x50c
        {
            nrf_gpio_cfg_default(miso_pin);
        }

        uint32_t mosi_pin = nrf_spi_mosi_pin_get(p_spi);
        if (mosi_pin != NRF_SPI_PIN_NOT_CONNECTED)
    326e:	1c5a      	adds	r2, r3, #1
    3270:	d008      	beq.n	3284 <nrfx_spi_uninit+0x74>
    *p_pin = pin_number & 0x1F;
    3272:	f003 031f 	and.w	r3, r3, #31
    reg->PIN_CNF[pin_number] = cnf;
    3276:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    327a:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    327e:	2102      	movs	r1, #2
    3280:	f842 1023 	str.w	r1, [r2, r3, lsl #2]
        {
            nrf_gpio_cfg_default(mosi_pin);
        }

        if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    3284:	2328      	movs	r3, #40	; 0x28
    3286:	fb03 4306 	mla	r3, r3, r6, r4
    328a:	7f9b      	ldrb	r3, [r3, #30]
    328c:	2bff      	cmp	r3, #255	; 0xff
    328e:	d008      	beq.n	32a2 <nrfx_spi_uninit+0x92>
    *p_pin = pin_number & 0x1F;
    3290:	f003 031f 	and.w	r3, r3, #31
    reg->PIN_CNF[pin_number] = cnf;
    3294:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    3298:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    329c:	2102      	movs	r1, #2
    329e:	f842 1023 	str.w	r1, [r2, r3, lsl #2]

#if NRFX_CHECK(NRFX_PRS_ENABLED)
    nrfx_prs_release(p_instance->p_reg);
#endif

    p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
    32a2:	2328      	movs	r3, #40	; 0x28
    32a4:	fb03 4406 	mla	r4, r3, r6, r4
    32a8:	2300      	movs	r3, #0
    32aa:	7723      	strb	r3, [r4, #28]
}
    32ac:	bd70      	pop	{r4, r5, r6, pc}
    32ae:	bf00      	nop
    32b0:	20000330 	.word	0x20000330

000032b4 <nrfx_spi_xfer>:
}

nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const *           p_instance,
                         nrfx_spi_xfer_desc_t const * p_xfer_desc,
                         uint32_t                     flags)
{
    32b4:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    32b8:	7907      	ldrb	r7, [r0, #4]
    NRFX_ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0);
    NRFX_ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0);

    nrfx_err_t err_code = NRFX_SUCCESS;

    if (p_cb->transfer_in_progress)
    32ba:	4e41      	ldr	r6, [pc, #260]	; (33c0 <nrfx_spi_xfer+0x10c>)
    32bc:	2328      	movs	r3, #40	; 0x28
    32be:	437b      	muls	r3, r7
{
    32c0:	4694      	mov	ip, r2
    if (p_cb->transfer_in_progress)
    32c2:	18f2      	adds	r2, r6, r3
{
    32c4:	460d      	mov	r5, r1
    if (p_cb->transfer_in_progress)
    32c6:	7f51      	ldrb	r1, [r2, #29]
{
    32c8:	4686      	mov	lr, r0
    if (p_cb->transfer_in_progress)
    32ca:	2900      	cmp	r1, #0
    32cc:	d176      	bne.n	33bc <nrfx_spi_xfer+0x108>
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
    else
    {
        if (p_cb->handler)
    32ce:	f856 8003 	ldr.w	r8, [r6, r3]
    32d2:	f1b8 0f00 	cmp.w	r8, #0
    32d6:	d001      	beq.n	32dc <nrfx_spi_xfer+0x28>
        {
            p_cb->transfer_in_progress = true;
    32d8:	2301      	movs	r3, #1
    32da:	7753      	strb	r3, [r2, #29]
        }
    }

    p_cb->evt.xfer_desc = *p_xfer_desc;
    32dc:	e895 000f 	ldmia.w	r5, {r0, r1, r2, r3}
    32e0:	2428      	movs	r4, #40	; 0x28
    32e2:	fb04 6407 	mla	r4, r4, r7, r6
    32e6:	f104 090c 	add.w	r9, r4, #12
    32ea:	e889 000f 	stmia.w	r9, {r0, r1, r2, r3}
    p_cb->abort = false;
    32ee:	2300      	movs	r3, #0
    32f0:	f884 3024 	strb.w	r3, [r4, #36]	; 0x24

    if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    32f4:	7fa3      	ldrb	r3, [r4, #30]
    32f6:	2bff      	cmp	r3, #255	; 0xff
    32f8:	d008      	beq.n	330c <nrfx_spi_xfer+0x58>
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    32fa:	2201      	movs	r2, #1
    *p_pin = pin_number & 0x1F;
    32fc:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    3300:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->OUTCLR = clr_mask;
    3304:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    3308:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
    {
        nrf_gpio_pin_write(p_cb->ss_pin, 0);
    }
    if (flags)
    330c:	2328      	movs	r3, #40	; 0x28
    330e:	f1bc 0f00 	cmp.w	ip, #0
    3312:	d006      	beq.n	3322 <nrfx_spi_xfer+0x6e>
    {
        p_cb->transfer_in_progress = false;
    3314:	fb03 6307 	mla	r3, r3, r7, r6
    3318:	2200      	movs	r2, #0
        err_code = NRFX_ERROR_NOT_SUPPORTED;
    331a:	482a      	ldr	r0, [pc, #168]	; (33c4 <nrfx_spi_xfer+0x110>)
        p_cb->transfer_in_progress = false;
    331c:	775a      	strb	r2, [r3, #29]
    }
    NRFX_LOG_INFO("Function: %s, error code: %s.",
                  __func__,
                  NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    331e:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        spi_xfer(p_instance->p_reg, p_cb, p_xfer_desc);
    3322:	f8de 4000 	ldr.w	r4, [lr]
    p_cb->bytes_transferred = 0;
    3326:	fb03 6307 	mla	r3, r3, r7, r6
    p_reg->INTENCLR = mask;
    332a:	2204      	movs	r2, #4
    332c:	f8c4 2308 	str.w	r2, [r4, #776]	; 0x308
    3330:	f8c3 c020 	str.w	ip, [r3, #32]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3334:	f8c4 c108 	str.w	ip, [r4, #264]	; 0x108
    3338:	f8d4 2108 	ldr.w	r2, [r4, #264]	; 0x108
    nrf_spi_txd_set(p_spi,
    333c:	686a      	ldr	r2, [r5, #4]
    333e:	b192      	cbz	r2, 3366 <nrfx_spi_xfer+0xb2>
    3340:	682b      	ldr	r3, [r5, #0]
    3342:	781b      	ldrb	r3, [r3, #0]
    p_reg->TXD = data;
    3344:	f8c4 351c 	str.w	r3, [r4, #1308]	; 0x51c
    if (p_xfer_desc->tx_length > 1)
    3348:	686b      	ldr	r3, [r5, #4]
    334a:	2b01      	cmp	r3, #1
    334c:	d90d      	bls.n	336a <nrfx_spi_xfer+0xb6>
        nrf_spi_txd_set(p_spi, p_xfer_desc->p_tx_buffer[1]);
    334e:	682b      	ldr	r3, [r5, #0]
    3350:	785b      	ldrb	r3, [r3, #1]
    3352:	f8c4 351c 	str.w	r3, [r4, #1308]	; 0x51c
    if (p_cb->handler)
    3356:	f1b8 0f00 	cmp.w	r8, #0
    335a:	d00e      	beq.n	337a <nrfx_spi_xfer+0xc6>
    p_reg->INTENSET = mask;
    335c:	2304      	movs	r3, #4
    335e:	f8c4 3304 	str.w	r3, [r4, #772]	; 0x304
    nrfx_err_t err_code = NRFX_SUCCESS;
    3362:	4819      	ldr	r0, [pc, #100]	; (33c8 <nrfx_spi_xfer+0x114>)
    3364:	e7db      	b.n	331e <nrfx_spi_xfer+0x6a>
    nrf_spi_txd_set(p_spi,
    3366:	7fdb      	ldrb	r3, [r3, #31]
    3368:	e7ec      	b.n	3344 <nrfx_spi_xfer+0x90>
    else if (p_xfer_desc->rx_length > 1)
    336a:	68eb      	ldr	r3, [r5, #12]
    336c:	2b01      	cmp	r3, #1
    336e:	d9f2      	bls.n	3356 <nrfx_spi_xfer+0xa2>
        nrf_spi_txd_set(p_spi, p_cb->orc);
    3370:	2328      	movs	r3, #40	; 0x28
    3372:	fb03 6307 	mla	r3, r3, r7, r6
    p_reg->TXD = data;
    3376:	7fdb      	ldrb	r3, [r3, #31]
    3378:	e7eb      	b.n	3352 <nrfx_spi_xfer+0x9e>
    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    337a:	eb07 0187 	add.w	r1, r7, r7, lsl #2
    337e:	eb06 01c1 	add.w	r1, r6, r1, lsl #3
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3382:	f8d4 3108 	ldr.w	r3, [r4, #264]	; 0x108
            while (!nrf_spi_event_check(p_spi, NRF_SPI_EVENT_READY)) {}
    3386:	2b00      	cmp	r3, #0
    3388:	d0fb      	beq.n	3382 <nrfx_spi_xfer+0xce>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    338a:	f8c4 8108 	str.w	r8, [r4, #264]	; 0x108
        } while (transfer_byte(p_spi, p_cb));
    338e:	4620      	mov	r0, r4
    3390:	f8d4 3108 	ldr.w	r3, [r4, #264]	; 0x108
    3394:	f001 fb0b 	bl	49ae <transfer_byte>
    3398:	2800      	cmp	r0, #0
    339a:	d1f2      	bne.n	3382 <nrfx_spi_xfer+0xce>
        if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    339c:	2328      	movs	r3, #40	; 0x28
    339e:	fb03 6607 	mla	r6, r3, r7, r6
    33a2:	7fb3      	ldrb	r3, [r6, #30]
    33a4:	2bff      	cmp	r3, #255	; 0xff
    33a6:	d0dc      	beq.n	3362 <nrfx_spi_xfer+0xae>
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    33a8:	2201      	movs	r2, #1
    *p_pin = pin_number & 0x1F;
    33aa:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    33ae:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->OUTSET = set_mask;
    33b2:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    33b6:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
}
    33ba:	e7d2      	b.n	3362 <nrfx_spi_xfer+0xae>
        return err_code;
    33bc:	4803      	ldr	r0, [pc, #12]	; (33cc <nrfx_spi_xfer+0x118>)
    33be:	e7ae      	b.n	331e <nrfx_spi_xfer+0x6a>
    33c0:	20000330 	.word	0x20000330
    33c4:	0bad0003 	.word	0x0bad0003
    33c8:	0bad0000 	.word	0x0bad0000
    33cc:	0bad000b 	.word	0x0bad000b

000033d0 <nrfx_spi_0_irq_handler>:
}

#if NRFX_CHECK(NRFX_SPI0_ENABLED)
void nrfx_spi_0_irq_handler(void)
{
    irq_handler(NRF_SPI0, &m_cb[NRFX_SPI0_INST_IDX]);
    33d0:	4901      	ldr	r1, [pc, #4]	; (33d8 <nrfx_spi_0_irq_handler+0x8>)
    33d2:	4802      	ldr	r0, [pc, #8]	; (33dc <nrfx_spi_0_irq_handler+0xc>)
    33d4:	f001 bb1e 	b.w	4a14 <irq_handler>
    33d8:	20000330 	.word	0x20000330
    33dc:	40003000 	.word	0x40003000

000033e0 <nrfx_spi_1_irq_handler>:
#endif

#if NRFX_CHECK(NRFX_SPI1_ENABLED)
void nrfx_spi_1_irq_handler(void)
{
    irq_handler(NRF_SPI1, &m_cb[NRFX_SPI1_INST_IDX]);
    33e0:	4902      	ldr	r1, [pc, #8]	; (33ec <nrfx_spi_1_irq_handler+0xc>)
    33e2:	f04f 2040 	mov.w	r0, #1073758208	; 0x40004000
    33e6:	f001 bb15 	b.w	4a14 <irq_handler>
    33ea:	bf00      	nop
    33ec:	20000358 	.word	0x20000358

000033f0 <_DoInit>:
                      _DoInit();                                                                     \
                    }                                                                                \
                  } while (0);                                                                       \
                }

static void _DoInit(void) {
    33f0:	b510      	push	{r4, lr}
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    33f2:	4c14      	ldr	r4, [pc, #80]	; (3444 <_DoInit+0x54>)
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    33f4:	4a14      	ldr	r2, [pc, #80]	; (3448 <_DoInit+0x58>)
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    33f6:	4915      	ldr	r1, [pc, #84]	; (344c <_DoInit+0x5c>)
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    33f8:	2303      	movs	r3, #3
    33fa:	6123      	str	r3, [r4, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    33fc:	6163      	str	r3, [r4, #20]
  p->aUp[0].pBuffer       = _acUpBuffer;
    33fe:	4b14      	ldr	r3, [pc, #80]	; (3450 <_DoInit+0x60>)
  p->aUp[0].sName         = "Terminal";
    3400:	61a2      	str	r2, [r4, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    3402:	61e3      	str	r3, [r4, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    3404:	f44f 6380 	mov.w	r3, #1024	; 0x400
    3408:	6223      	str	r3, [r4, #32]
  p->aUp[0].RdOff         = 0u;
    340a:	2300      	movs	r3, #0
    340c:	62a3      	str	r3, [r4, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    340e:	6263      	str	r3, [r4, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    3410:	62e3      	str	r3, [r4, #44]	; 0x2c
  p->aDown[0].sName         = "Terminal";
    3412:	6622      	str	r2, [r4, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    3414:	4a0f      	ldr	r2, [pc, #60]	; (3454 <_DoInit+0x64>)
    3416:	6662      	str	r2, [r4, #100]	; 0x64
  STRCPY((char*)&p->acID[7], "RTT");
    3418:	1de0      	adds	r0, r4, #7
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    341a:	2210      	movs	r2, #16
    341c:	66a2      	str	r2, [r4, #104]	; 0x68
  p->aDown[0].RdOff         = 0u;
    341e:	6723      	str	r3, [r4, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    3420:	66e3      	str	r3, [r4, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    3422:	6763      	str	r3, [r4, #116]	; 0x74
  STRCPY((char*)&p->acID[7], "RTT");
    3424:	f000 ffd7 	bl	43d6 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    3428:	f3bf 8f5f 	dmb	sy
  STRCPY((char*)&p->acID[0], "SEGGER");
    342c:	490a      	ldr	r1, [pc, #40]	; (3458 <_DoInit+0x68>)
    342e:	4620      	mov	r0, r4
    3430:	f000 ffd1 	bl	43d6 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    3434:	f3bf 8f5f 	dmb	sy
  p->acID[6] = ' ';
    3438:	2320      	movs	r3, #32
    343a:	71a3      	strb	r3, [r4, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    343c:	f3bf 8f5f 	dmb	sy
}
    3440:	bd10      	pop	{r4, pc}
    3442:	bf00      	nop
    3444:	20000380 	.word	0x20000380
    3448:	000050ef 	.word	0x000050ef
    344c:	000050f8 	.word	0x000050f8
    3450:	2000046e 	.word	0x2000046e
    3454:	2000045e 	.word	0x2000045e
    3458:	000050fc 	.word	0x000050fc

0000345c <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    345c:	4b10      	ldr	r3, [pc, #64]	; (34a0 <z_sys_init_run_level+0x44>)
{
    345e:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3460:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    3464:	3001      	adds	r0, #1
    3466:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    346a:	42a6      	cmp	r6, r4
    346c:	d800      	bhi.n	3470 <z_sys_init_run_level+0x14>
			}
		} else {
			(void)entry->init_fn.sys();
		}
	}
}
    346e:	bd70      	pop	{r4, r5, r6, pc}
			int rc = entry->init_fn.dev(dev);
    3470:	e9d4 3500 	ldrd	r3, r5, [r4]
		if (dev != NULL) {
    3474:	b18d      	cbz	r5, 349a <z_sys_init_run_level+0x3e>
			int rc = entry->init_fn.dev(dev);
    3476:	4628      	mov	r0, r5
    3478:	4798      	blx	r3
			if (rc != 0) {
    347a:	b138      	cbz	r0, 348c <z_sys_init_run_level+0x30>
				if (rc < 0) {
    347c:	2800      	cmp	r0, #0
    347e:	bfb8      	it	lt
    3480:	4240      	neglt	r0, r0
				dev->state->init_res = rc;
    3482:	68eb      	ldr	r3, [r5, #12]
				if (rc > UINT8_MAX) {
    3484:	28ff      	cmp	r0, #255	; 0xff
    3486:	bfa8      	it	ge
    3488:	20ff      	movge	r0, #255	; 0xff
				dev->state->init_res = rc;
    348a:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    348c:	68ea      	ldr	r2, [r5, #12]
    348e:	7853      	ldrb	r3, [r2, #1]
    3490:	f043 0301 	orr.w	r3, r3, #1
    3494:	7053      	strb	r3, [r2, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3496:	3408      	adds	r4, #8
    3498:	e7e7      	b.n	346a <z_sys_init_run_level+0xe>
			(void)entry->init_fn.sys();
    349a:	4798      	blx	r3
    349c:	e7fb      	b.n	3496 <z_sys_init_run_level+0x3a>
    349e:	bf00      	nop
    34a0:	00005014 	.word	0x00005014

000034a4 <bg_thread_main>:
 * This routine completes kernel initialization by invoking the remaining
 * init functions, then invokes application's main() routine.
 */
__boot_func
static void bg_thread_main(void *unused1, void *unused2, void *unused3)
{
    34a4:	b508      	push	{r3, lr}
	 * may perform memory management tasks (except for z_phys_map() which
	 * is allowed at any time)
	 */
	z_mem_manage_init();
#endif /* CONFIG_MMU */
	z_sys_post_kernel = true;
    34a6:	4b0a      	ldr	r3, [pc, #40]	; (34d0 <bg_thread_main+0x2c>)
    34a8:	2201      	movs	r2, #1

	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    34aa:	2003      	movs	r0, #3
	z_sys_post_kernel = true;
    34ac:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    34ae:	f7ff ffd5 	bl	345c <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    34b2:	f000 fe29 	bl	4108 <boot_banner>
	void z_cpp_init_static(void);
	z_cpp_init_static();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(INIT_LEVEL_APPLICATION);
    34b6:	2004      	movs	r0, #4
    34b8:	f7ff ffd0 	bl	345c <z_sys_init_run_level>

	z_init_static_threads();
    34bc:	f000 f8f0 	bl	36a0 <z_init_static_threads>
	z_mem_manage_boot_finish();
#endif /* CONFIG_MMU */

	extern int main(void);

	(void)main();
    34c0:	f7fc ff76 	bl	3b0 <main>

	/* Mark nonessential since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    34c4:	4a03      	ldr	r2, [pc, #12]	; (34d4 <bg_thread_main+0x30>)
    34c6:	7b13      	ldrb	r3, [r2, #12]
    34c8:	f023 0301 	bic.w	r3, r3, #1
    34cc:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    34ce:	bd08      	pop	{r3, pc}
    34d0:	2000086e 	.word	0x2000086e
    34d4:	200001d8 	.word	0x200001d8

000034d8 <z_bss_zero>:
{
    34d8:	b508      	push	{r3, lr}
	z_early_memset(__bss_start, 0, __bss_end - __bss_start);
    34da:	4803      	ldr	r0, [pc, #12]	; (34e8 <z_bss_zero+0x10>)
    34dc:	4a03      	ldr	r2, [pc, #12]	; (34ec <z_bss_zero+0x14>)
    34de:	2100      	movs	r1, #0
    34e0:	1a12      	subs	r2, r2, r0
    34e2:	f001 fae7 	bl	4ab4 <z_early_memset>
}
    34e6:	bd08      	pop	{r3, pc}
    34e8:	20000138 	.word	0x20000138
    34ec:	20000870 	.word	0x20000870

000034f0 <z_init_cpu>:
	thread->base.is_idle = 1U;
#endif
}

void z_init_cpu(int id)
{
    34f0:	b570      	push	{r4, r5, r6, lr}
	z_setup_new_thread(thread, stack,
    34f2:	2300      	movs	r3, #0
{
    34f4:	b086      	sub	sp, #24
	z_setup_new_thread(thread, stack,
    34f6:	2201      	movs	r2, #1
    34f8:	e9cd 2304 	strd	r2, r3, [sp, #16]
	struct k_thread *thread = &z_idle_threads[i];
    34fc:	4e13      	ldr	r6, [pc, #76]	; (354c <z_init_cpu+0x5c>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    34fe:	4d14      	ldr	r5, [pc, #80]	; (3550 <z_init_cpu+0x60>)
	z_setup_new_thread(thread, stack,
    3500:	9301      	str	r3, [sp, #4]
    3502:	220f      	movs	r2, #15
    3504:	e9cd 3202 	strd	r3, r2, [sp, #8]
    3508:	4912      	ldr	r1, [pc, #72]	; (3554 <z_init_cpu+0x64>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    350a:	2314      	movs	r3, #20
    350c:	fb03 5500 	mla	r5, r3, r0, r5
	struct k_thread *thread = &z_idle_threads[i];
    3510:	eb06 16c0 	add.w	r6, r6, r0, lsl #7
{
    3514:	4604      	mov	r4, r0
	z_setup_new_thread(thread, stack,
    3516:	f44f 70c0 	mov.w	r0, #384	; 0x180
    351a:	fb00 1104 	mla	r1, r0, r4, r1
    351e:	4b0e      	ldr	r3, [pc, #56]	; (3558 <z_init_cpu+0x68>)
    3520:	9500      	str	r5, [sp, #0]
    3522:	f44f 72a0 	mov.w	r2, #320	; 0x140
    3526:	4630      	mov	r0, r6
    3528:	f000 f888 	bl	363c <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    352c:	7b73      	ldrb	r3, [r6, #13]
	init_idle_thread(id);
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
	_kernel.cpus[id].id = id;
	_kernel.cpus[id].irq_stack =
		(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) +
    352e:	4a0b      	ldr	r2, [pc, #44]	; (355c <z_init_cpu+0x6c>)
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
    3530:	60ee      	str	r6, [r5, #12]
    3532:	f023 0304 	bic.w	r3, r3, #4
    3536:	7373      	strb	r3, [r6, #13]
		(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) +
    3538:	f44f 6304 	mov.w	r3, #2112	; 0x840
    353c:	fb04 3303 	mla	r3, r4, r3, r3
    3540:	4413      	add	r3, r2
	_kernel.cpus[id].id = id;
    3542:	742c      	strb	r4, [r5, #16]
	_kernel.cpus[id].irq_stack =
    3544:	606b      	str	r3, [r5, #4]
		 K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[id]));
#ifdef CONFIG_SCHED_THREAD_USAGE_ALL
	_kernel.cpus[id].usage.track_usage =
		CONFIG_SCHED_THREAD_USAGE_AUTO_ENABLE;
#endif
}
    3546:	b006      	add	sp, #24
    3548:	bd70      	pop	{r4, r5, r6, pc}
    354a:	bf00      	nop
    354c:	20000158 	.word	0x20000158
    3550:	20000428 	.word	0x20000428
    3554:	200010c0 	.word	0x200010c0
    3558:	00003759 	.word	0x00003759
    355c:	20000880 	.word	0x20000880

00003560 <z_cstart>:
 * @return Does not return
 */
__boot_func
FUNC_NO_STACK_PROTECTOR
FUNC_NORETURN void z_cstart(void)
{
    3560:	b580      	push	{r7, lr}
	/* gcov hook needed to get the coverage report.*/
	gcov_static_init();

	/* initialize early init calls */
	z_sys_init_run_level(INIT_LEVEL_EARLY);
    3562:	2000      	movs	r0, #0
{
    3564:	b0a6      	sub	sp, #152	; 0x98
	z_sys_init_run_level(INIT_LEVEL_EARLY);
    3566:	f7ff ff79 	bl	345c <z_sys_init_run_level>
 * pointer) register, and switched to automatically when taking an exception.
 *
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    356a:	4b2d      	ldr	r3, [pc, #180]	; (3620 <z_cstart+0xc0>)
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    356c:	f383 8808 	msr	MSP, r3
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    3570:	4d2c      	ldr	r5, [pc, #176]	; (3624 <z_cstart+0xc4>)

#ifdef CONFIG_TIMESLICE_PER_THREAD
	dummy_thread->base.slice_ticks = 0;
#endif

	_current_cpu->current = dummy_thread;
    3572:	4e2d      	ldr	r6, [pc, #180]	; (3628 <z_cstart+0xc8>)
    3574:	696b      	ldr	r3, [r5, #20]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3576:	4f2d      	ldr	r7, [pc, #180]	; (362c <z_cstart+0xcc>)
    3578:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    357c:	616b      	str	r3, [r5, #20]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    357e:	2400      	movs	r4, #0
    3580:	23e0      	movs	r3, #224	; 0xe0
    3582:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    3586:	77ec      	strb	r4, [r5, #31]
    3588:	762c      	strb	r4, [r5, #24]
    358a:	766c      	strb	r4, [r5, #25]
    358c:	76ac      	strb	r4, [r5, #26]
    358e:	f885 4020 	strb.w	r4, [r5, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    3592:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    3594:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    3598:	626b      	str	r3, [r5, #36]	; 0x24
    359a:	f885 4023 	strb.w	r4, [r5, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    359e:	f7fd ffcb 	bl	1538 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    35a2:	f7fd fd39 	bl	1018 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    35a6:	f04f 33ff 	mov.w	r3, #4294967295
    35aa:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    35ac:	62eb      	str	r3, [r5, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    35ae:	f7fe f8fd 	bl	17ac <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    35b2:	f7fe f863 	bl	167c <z_arm_configure_static_mpu_regions>
	dummy_thread->base.user_options = K_ESSENTIAL;
    35b6:	f240 1301 	movw	r3, #257	; 0x101
    35ba:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    35be:	ab06      	add	r3, sp, #24
    35c0:	60b3      	str	r3, [r6, #8]
	dummy_thread->stack_info.size = 0U;
    35c2:	e9cd 441f 	strd	r4, r4, [sp, #124]	; 0x7c
	dummy_thread->resource_pool = NULL;
    35c6:	9422      	str	r4, [sp, #136]	; 0x88
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    35c8:	f001 fa4d 	bl	4a66 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_1);
    35cc:	2001      	movs	r0, #1
    35ce:	f7ff ff45 	bl	345c <z_sys_init_run_level>
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_2);
    35d2:	2002      	movs	r0, #2
	_kernel.ready_q.cache = &z_main_thread;
    35d4:	4d16      	ldr	r5, [pc, #88]	; (3630 <z_cstart+0xd0>)
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_2);
    35d6:	f7ff ff41 	bl	345c <z_sys_init_run_level>
	z_sched_init();
    35da:	f000 fb31 	bl	3c40 <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    35de:	4b15      	ldr	r3, [pc, #84]	; (3634 <z_cstart+0xd4>)
	_kernel.ready_q.cache = &z_main_thread;
    35e0:	61b5      	str	r5, [r6, #24]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    35e2:	9305      	str	r3, [sp, #20]
    35e4:	2301      	movs	r3, #1
    35e6:	4914      	ldr	r1, [pc, #80]	; (3638 <z_cstart+0xd8>)
    35e8:	9400      	str	r4, [sp, #0]
    35ea:	e9cd 4303 	strd	r4, r3, [sp, #12]
    35ee:	f44f 6280 	mov.w	r2, #1024	; 0x400
    35f2:	463b      	mov	r3, r7
    35f4:	e9cd 4401 	strd	r4, r4, [sp, #4]
    35f8:	4628      	mov	r0, r5
    35fa:	f000 f81f 	bl	363c <z_setup_new_thread>
    35fe:	7b6a      	ldrb	r2, [r5, #13]
    3600:	4606      	mov	r6, r0
    3602:	f022 0204 	bic.w	r2, r2, #4
	z_ready_thread(&z_main_thread);
    3606:	4628      	mov	r0, r5
    3608:	736a      	strb	r2, [r5, #13]
    360a:	f001 fa9e 	bl	4b4a <z_ready_thread>
	z_init_cpu(0);
    360e:	4620      	mov	r0, r4
    3610:	f7ff ff6e 	bl	34f0 <z_init_cpu>
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    3614:	463a      	mov	r2, r7
    3616:	4631      	mov	r1, r6
    3618:	4628      	mov	r0, r5
    361a:	f7fd fe0b 	bl	1234 <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    361e:	bf00      	nop
    3620:	200010c0 	.word	0x200010c0
    3624:	e000ed00 	.word	0xe000ed00
    3628:	20000428 	.word	0x20000428
    362c:	000034a5 	.word	0x000034a5
    3630:	200001d8 	.word	0x200001d8
    3634:	00005103 	.word	0x00005103
    3638:	20001240 	.word	0x20001240

0000363c <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    363c:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
	thread_base->user_options = (uint8_t)options;
    3640:	9e0e      	ldr	r6, [sp, #56]	; 0x38
    3642:	7306      	strb	r6, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    3644:	2604      	movs	r6, #4
    3646:	7346      	strb	r6, [r0, #13]

	thread_base->prio = priority;
    3648:	9e0d      	ldr	r6, [sp, #52]	; 0x34
    364a:	7386      	strb	r6, [r0, #14]
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    364c:	f100 0558 	add.w	r5, r0, #88	; 0x58
{
    3650:	460f      	mov	r7, r1
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    3652:	1dd6      	adds	r6, r2, #7
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
	list->tail = (sys_dnode_t *)list;
    3654:	e9c0 5516 	strd	r5, r5, [r0, #88]	; 0x58
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3658:	9a0c      	ldr	r2, [sp, #48]	; 0x30
	thread_base->pended_on = NULL;
    365a:	2500      	movs	r5, #0
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    365c:	f026 0607 	bic.w	r6, r6, #7

/** @} */

static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym)
{
	return (char *)sym + K_KERNEL_STACK_RESERVED;
    3660:	3740      	adds	r7, #64	; 0x40
 */

static inline void sys_dnode_init(sys_dnode_t *node)
{
	node->next = NULL;
	node->prev = NULL;
    3662:	e9c0 5506 	strd	r5, r5, [r0, #24]
	new_thread->stack_info.size = stack_buf_size;
    3666:	e9c0 7619 	strd	r7, r6, [r0, #100]	; 0x64
	thread_base->pended_on = NULL;
    366a:	6085      	str	r5, [r0, #8]

	thread_base->sched_locked = 0U;
    366c:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    366e:	66c5      	str	r5, [r0, #108]	; 0x6c
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    3670:	f106 0840 	add.w	r8, r6, #64	; 0x40
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3674:	9202      	str	r2, [sp, #8]
    3676:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    3678:	9201      	str	r2, [sp, #4]
	stack_ptr = (char *)stack + stack_obj_size;
    367a:	4488      	add	r8, r1
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    367c:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    367e:	9200      	str	r2, [sp, #0]
    3680:	4642      	mov	r2, r8
{
    3682:	4604      	mov	r4, r0
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3684:	f7fd fda4 	bl	11d0 <arch_new_thread>
	if (!_current) {
    3688:	4b04      	ldr	r3, [pc, #16]	; (369c <z_setup_new_thread+0x60>)
	new_thread->init_data = NULL;
    368a:	6565      	str	r5, [r4, #84]	; 0x54
	if (!_current) {
    368c:	689b      	ldr	r3, [r3, #8]
    368e:	b103      	cbz	r3, 3692 <z_setup_new_thread+0x56>
	new_thread->resource_pool = _current->resource_pool;
    3690:	6f1b      	ldr	r3, [r3, #112]	; 0x70
	return stack_ptr;
    3692:	6723      	str	r3, [r4, #112]	; 0x70
}
    3694:	4640      	mov	r0, r8
    3696:	b004      	add	sp, #16
    3698:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    369c:	20000428 	.word	0x20000428

000036a0 <z_init_static_threads>:
{
    36a0:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    36a4:	4c29      	ldr	r4, [pc, #164]	; (374c <z_init_static_threads+0xac>)
	_FOREACH_STATIC_THREAD(thread_data) {
    36a6:	4d2a      	ldr	r5, [pc, #168]	; (3750 <z_init_static_threads+0xb0>)
{
    36a8:	b087      	sub	sp, #28
    36aa:	4626      	mov	r6, r4
	_FOREACH_STATIC_THREAD(thread_data) {
    36ac:	42ae      	cmp	r6, r5
    36ae:	f104 042c 	add.w	r4, r4, #44	; 0x2c
    36b2:	d30f      	bcc.n	36d4 <z_init_static_threads+0x34>
	k_sched_lock();
    36b4:	f000 fa94 	bl	3be0 <k_sched_lock>
	_FOREACH_STATIC_THREAD(thread_data) {
    36b8:	4c24      	ldr	r4, [pc, #144]	; (374c <z_init_static_threads+0xac>)

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    36ba:	f8df 9098 	ldr.w	r9, [pc, #152]	; 3754 <z_init_static_threads+0xb4>
    36be:	f44f 4600 	mov.w	r6, #32768	; 0x8000
    36c2:	f240 37e7 	movw	r7, #999	; 0x3e7
    36c6:	42ac      	cmp	r4, r5
    36c8:	d320      	bcc.n	370c <z_init_static_threads+0x6c>
}
    36ca:	b007      	add	sp, #28
    36cc:	e8bd 43f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, lr}
	k_sched_unlock();
    36d0:	f000 ba9a 	b.w	3c08 <k_sched_unlock>
		z_setup_new_thread(
    36d4:	f854 3c04 	ldr.w	r3, [r4, #-4]
    36d8:	9305      	str	r3, [sp, #20]
    36da:	f854 3c0c 	ldr.w	r3, [r4, #-12]
    36de:	9304      	str	r3, [sp, #16]
    36e0:	f854 3c10 	ldr.w	r3, [r4, #-16]
    36e4:	9303      	str	r3, [sp, #12]
    36e6:	f854 3c14 	ldr.w	r3, [r4, #-20]
    36ea:	9302      	str	r3, [sp, #8]
    36ec:	f854 3c18 	ldr.w	r3, [r4, #-24]
    36f0:	9301      	str	r3, [sp, #4]
    36f2:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    36f6:	9300      	str	r3, [sp, #0]
    36f8:	e954 2309 	ldrd	r2, r3, [r4, #-36]	; 0x24
    36fc:	e954 010b 	ldrd	r0, r1, [r4, #-44]	; 0x2c
    3700:	f7ff ff9c 	bl	363c <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    3704:	f854 3c2c 	ldr.w	r3, [r4, #-44]
    3708:	655e      	str	r6, [r3, #84]	; 0x54
	_FOREACH_STATIC_THREAD(thread_data) {
    370a:	e7ce      	b.n	36aa <z_init_static_threads+0xa>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    370c:	6a63      	ldr	r3, [r4, #36]	; 0x24
    370e:	1c5a      	adds	r2, r3, #1
    3710:	d00d      	beq.n	372e <z_init_static_threads+0x8e>
					    K_MSEC(thread_data->init_delay));
    3712:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    3716:	2100      	movs	r1, #0
    3718:	4638      	mov	r0, r7
    371a:	fbc3 0106 	smlal	r0, r1, r3, r6
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    371e:	ea51 33c3 	orrs.w	r3, r1, r3, lsl #15
			schedule_new_thread(thread_data->init_thread,
    3722:	f8d4 8000 	ldr.w	r8, [r4]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3726:	d104      	bne.n	3732 <z_init_static_threads+0x92>
	z_sched_start(thread);
    3728:	4640      	mov	r0, r8
    372a:	f000 fa09 	bl	3b40 <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    372e:	342c      	adds	r4, #44	; 0x2c
    3730:	e7c9      	b.n	36c6 <z_init_static_threads+0x26>
    3732:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    3736:	2300      	movs	r3, #0
    3738:	f7fc fcd0 	bl	dc <__aeabi_uldivmod>
    373c:	4602      	mov	r2, r0
    373e:	460b      	mov	r3, r1
    3740:	f108 0018 	add.w	r0, r8, #24
    3744:	4649      	mov	r1, r9
    3746:	f000 fbe5 	bl	3f14 <z_add_timeout>
    374a:	e7f0      	b.n	372e <z_init_static_threads+0x8e>
    374c:	00004e50 	.word	0x00004e50
    3750:	00004e50 	.word	0x00004e50
    3754:	00004baf 	.word	0x00004baf

00003758 <idle>:
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
}

void idle(void *unused1, void *unused2, void *unused3)
{
    3758:	b508      	push	{r3, lr}
		 * higher level construct.
		 */
		(void) arch_irq_lock();

#ifdef CONFIG_PM
		_kernel.idle = z_get_next_timeout_expiry();
    375a:	4c0b      	ldr	r4, [pc, #44]	; (3788 <idle+0x30>)
	return !z_sys_post_kernel;
    375c:	4d0b      	ldr	r5, [pc, #44]	; (378c <idle+0x34>)
	__asm__ volatile(
    375e:	f04f 0220 	mov.w	r2, #32
    3762:	f3ef 8311 	mrs	r3, BASEPRI
    3766:	f382 8812 	msr	BASEPRI_MAX, r2
    376a:	f3bf 8f6f 	isb	sy
    376e:	f001 fa6a 	bl	4c46 <z_get_next_timeout_expiry>
		 * processing in those cases i.e. skips k_cpu_idle().
		 * The kernel's idle processing re-enables interrupts
		 * which is essential for the kernel's scheduling
		 * logic.
		 */
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    3772:	782b      	ldrb	r3, [r5, #0]
		_kernel.idle = z_get_next_timeout_expiry();
    3774:	6160      	str	r0, [r4, #20]
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    3776:	b913      	cbnz	r3, 377e <idle+0x26>
	arch_cpu_idle();
    3778:	f7fd fc54 	bl	1024 <arch_cpu_idle>
}
    377c:	e7ef      	b.n	375e <idle+0x6>
    377e:	f7fd fb7d 	bl	e7c <pm_system_suspend>
    3782:	2800      	cmp	r0, #0
    3784:	d1eb      	bne.n	375e <idle+0x6>
    3786:	e7f7      	b.n	3778 <idle+0x20>
    3788:	20000428 	.word	0x20000428
    378c:	2000086e 	.word	0x2000086e

00003790 <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    3790:	b538      	push	{r3, r4, r5, lr}
    3792:	4604      	mov	r4, r0
    3794:	f04f 0320 	mov.w	r3, #32
    3798:	f3ef 8511 	mrs	r5, BASEPRI
    379c:	f383 8812 	msr	BASEPRI_MAX, r3
    37a0:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    37a4:	f001 fa07 	bl	4bb6 <z_unpend_first_thread>

	if (thread != NULL) {
    37a8:	b148      	cbz	r0, 37be <z_impl_k_sem_give+0x2e>
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    37aa:	2200      	movs	r2, #0
    37ac:	6782      	str	r2, [r0, #120]	; 0x78
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    37ae:	f001 f9cc 	bl	4b4a <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    37b2:	4629      	mov	r1, r5
    37b4:	4805      	ldr	r0, [pc, #20]	; (37cc <z_impl_k_sem_give+0x3c>)

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    37b6:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    37ba:	f000 b9af 	b.w	3b1c <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    37be:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    37c2:	429a      	cmp	r2, r3
    37c4:	bf18      	it	ne
    37c6:	3301      	addne	r3, #1
    37c8:	60a3      	str	r3, [r4, #8]
}
    37ca:	e7f2      	b.n	37b2 <z_impl_k_sem_give+0x22>
    37cc:	2000086f 	.word	0x2000086f

000037d0 <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    37d0:	b513      	push	{r0, r1, r4, lr}
    37d2:	f04f 0420 	mov.w	r4, #32
    37d6:	f3ef 8111 	mrs	r1, BASEPRI
    37da:	f384 8812 	msr	BASEPRI_MAX, r4
    37de:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    37e2:	6884      	ldr	r4, [r0, #8]
    37e4:	b144      	cbz	r4, 37f8 <z_impl_k_sem_take+0x28>
		sem->count--;
    37e6:	3c01      	subs	r4, #1
    37e8:	6084      	str	r4, [r0, #8]
	__asm__ volatile(
    37ea:	f381 8811 	msr	BASEPRI, r1
    37ee:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    37f2:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    37f4:	b002      	add	sp, #8
    37f6:	bd10      	pop	{r4, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    37f8:	ea52 0403 	orrs.w	r4, r2, r3
    37fc:	d106      	bne.n	380c <z_impl_k_sem_take+0x3c>
    37fe:	f381 8811 	msr	BASEPRI, r1
    3802:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    3806:	f06f 000f 	mvn.w	r0, #15
    380a:	e7f3      	b.n	37f4 <z_impl_k_sem_take+0x24>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    380c:	e9cd 2300 	strd	r2, r3, [sp]
    3810:	4602      	mov	r2, r0
    3812:	4802      	ldr	r0, [pc, #8]	; (381c <z_impl_k_sem_take+0x4c>)
    3814:	f000 f964 	bl	3ae0 <z_pend_curr>
	return ret;
    3818:	e7ec      	b.n	37f4 <z_impl_k_sem_take+0x24>
    381a:	bf00      	nop
    381c:	2000086f 	.word	0x2000086f

00003820 <z_impl_k_sem_reset>:

void z_impl_k_sem_reset(struct k_sem *sem)
{
    3820:	b570      	push	{r4, r5, r6, lr}
    3822:	4604      	mov	r4, r0
	__asm__ volatile(
    3824:	f04f 0320 	mov.w	r3, #32
    3828:	f3ef 8511 	mrs	r5, BASEPRI
    382c:	f383 8812 	msr	BASEPRI_MAX, r3
    3830:	f3bf 8f6f 	isb	sy
    3834:	f06f 060a 	mvn.w	r6, #10
	struct k_thread *thread;
	k_spinlock_key_t key = k_spin_lock(&lock);

	while (true) {
		thread = z_unpend_first_thread(&sem->wait_q);
    3838:	4620      	mov	r0, r4
    383a:	f001 f9bc 	bl	4bb6 <z_unpend_first_thread>
		if (thread == NULL) {
    383e:	b118      	cbz	r0, 3848 <z_impl_k_sem_reset+0x28>
    3840:	6786      	str	r6, [r0, #120]	; 0x78
			break;
		}
		arch_thread_return_value_set(thread, -EAGAIN);
		z_ready_thread(thread);
    3842:	f001 f982 	bl	4b4a <z_ready_thread>
		thread = z_unpend_first_thread(&sem->wait_q);
    3846:	e7f7      	b.n	3838 <z_impl_k_sem_reset+0x18>
	}
	sem->count = 0;
    3848:	60a0      	str	r0, [r4, #8]

	SYS_PORT_TRACING_OBJ_FUNC(k_sem, reset, sem);

	handle_poll_events(sem);

	z_reschedule(&lock, key);
    384a:	4629      	mov	r1, r5
    384c:	4802      	ldr	r0, [pc, #8]	; (3858 <z_impl_k_sem_reset+0x38>)
}
    384e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	z_reschedule(&lock, key);
    3852:	f000 b963 	b.w	3b1c <z_reschedule>
    3856:	bf00      	nop
    3858:	2000086f 	.word	0x2000086f

0000385c <sliceable>:
{
	bool ret = is_preempt(thread)
		&& slice_time(thread) != 0
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
		&& !z_is_thread_prevented_from_running(thread)
		&& !z_is_idle_thread_object(thread);
    385c:	89c3      	ldrh	r3, [r0, #14]
    385e:	2b7f      	cmp	r3, #127	; 0x7f
    3860:	d812      	bhi.n	3888 <sliceable+0x2c>
	int ret = slice_ticks;
    3862:	4b0a      	ldr	r3, [pc, #40]	; (388c <sliceable+0x30>)
    3864:	681b      	ldr	r3, [r3, #0]
		&& slice_time(thread) != 0
    3866:	b163      	cbz	r3, 3882 <sliceable+0x26>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    3868:	4b09      	ldr	r3, [pc, #36]	; (3890 <sliceable+0x34>)
    386a:	f990 200e 	ldrsb.w	r2, [r0, #14]
    386e:	681b      	ldr	r3, [r3, #0]
    3870:	429a      	cmp	r2, r3
    3872:	db09      	blt.n	3888 <sliceable+0x2c>
		&& !z_is_thread_prevented_from_running(thread)
    3874:	7b43      	ldrb	r3, [r0, #13]
    3876:	06db      	lsls	r3, r3, #27
    3878:	d106      	bne.n	3888 <sliceable+0x2c>
		&& !z_is_idle_thread_object(thread);
    387a:	4b06      	ldr	r3, [pc, #24]	; (3894 <sliceable+0x38>)
    387c:	1ac3      	subs	r3, r0, r3
    387e:	bf18      	it	ne
    3880:	2301      	movne	r3, #1
#ifdef CONFIG_TIMESLICE_PER_THREAD
	ret |= thread->base.slice_ticks != 0;
#endif

	return ret;
}
    3882:	f003 0001 	and.w	r0, r3, #1
    3886:	4770      	bx	lr
		&& !z_is_idle_thread_object(thread);
    3888:	2300      	movs	r3, #0
    388a:	e7fa      	b.n	3882 <sliceable+0x26>
    388c:	20000454 	.word	0x20000454
    3890:	20000450 	.word	0x20000450
    3894:	20000158 	.word	0x20000158

00003898 <slice_timeout>:

static void slice_timeout(struct _timeout *t)
{
	int cpu = ARRAY_INDEX(slice_timeouts, t);
    3898:	4b04      	ldr	r3, [pc, #16]	; (38ac <slice_timeout+0x14>)
    389a:	1ac0      	subs	r0, r0, r3
    389c:	4b04      	ldr	r3, [pc, #16]	; (38b0 <slice_timeout+0x18>)
    389e:	10c0      	asrs	r0, r0, #3
    38a0:	4358      	muls	r0, r3

	slice_expired[cpu] = true;
    38a2:	4b04      	ldr	r3, [pc, #16]	; (38b4 <slice_timeout+0x1c>)
    38a4:	2201      	movs	r2, #1
    38a6:	541a      	strb	r2, [r3, r0]
	 * the specific core, but that's not part of the API yet.
	 */
	if (IS_ENABLED(CONFIG_SMP) && cpu != _current_cpu->id) {
		flag_ipi();
	}
}
    38a8:	4770      	bx	lr
    38aa:	bf00      	nop
    38ac:	20000258 	.word	0x20000258
    38b0:	aaaaaaab 	.word	0xaaaaaaab
    38b4:	2000086f 	.word	0x2000086f

000038b8 <z_reset_time_slice>:

void z_reset_time_slice(struct k_thread *curr)
{
    38b8:	b570      	push	{r4, r5, r6, lr}
	int cpu = _current_cpu->id;
    38ba:	4b0e      	ldr	r3, [pc, #56]	; (38f4 <z_reset_time_slice+0x3c>)

	z_abort_timeout(&slice_timeouts[cpu]);
    38bc:	4c0e      	ldr	r4, [pc, #56]	; (38f8 <z_reset_time_slice+0x40>)
	int cpu = _current_cpu->id;
    38be:	7c1e      	ldrb	r6, [r3, #16]
	z_abort_timeout(&slice_timeouts[cpu]);
    38c0:	eb06 0346 	add.w	r3, r6, r6, lsl #1
    38c4:	eb04 04c3 	add.w	r4, r4, r3, lsl #3
{
    38c8:	4605      	mov	r5, r0
	z_abort_timeout(&slice_timeouts[cpu]);
    38ca:	4620      	mov	r0, r4
    38cc:	f001 f9a5 	bl	4c1a <z_abort_timeout>
	slice_expired[cpu] = false;
    38d0:	4b0a      	ldr	r3, [pc, #40]	; (38fc <z_reset_time_slice+0x44>)
    38d2:	2200      	movs	r2, #0
	if (sliceable(curr)) {
    38d4:	4628      	mov	r0, r5
	slice_expired[cpu] = false;
    38d6:	559a      	strb	r2, [r3, r6]
	if (sliceable(curr)) {
    38d8:	f7ff ffc0 	bl	385c <sliceable>
    38dc:	b148      	cbz	r0, 38f2 <z_reset_time_slice+0x3a>
	int ret = slice_ticks;
    38de:	4b08      	ldr	r3, [pc, #32]	; (3900 <z_reset_time_slice+0x48>)
		z_add_timeout(&slice_timeouts[cpu], slice_timeout,
    38e0:	4908      	ldr	r1, [pc, #32]	; (3904 <z_reset_time_slice+0x4c>)
			      K_TICKS(slice_time(curr) - 1));
    38e2:	681a      	ldr	r2, [r3, #0]
    38e4:	3a01      	subs	r2, #1
		z_add_timeout(&slice_timeouts[cpu], slice_timeout,
    38e6:	4620      	mov	r0, r4
    38e8:	17d3      	asrs	r3, r2, #31
	}
}
    38ea:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_add_timeout(&slice_timeouts[cpu], slice_timeout,
    38ee:	f000 bb11 	b.w	3f14 <z_add_timeout>
}
    38f2:	bd70      	pop	{r4, r5, r6, pc}
    38f4:	20000428 	.word	0x20000428
    38f8:	20000258 	.word	0x20000258
    38fc:	2000086f 	.word	0x2000086f
    3900:	20000454 	.word	0x20000454
    3904:	00003899 	.word	0x00003899

00003908 <update_cache>:
	}
#endif
}

static void update_cache(int preempt_ok)
{
    3908:	b538      	push	{r3, r4, r5, lr}
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    390a:	4d0d      	ldr	r5, [pc, #52]	; (3940 <update_cache+0x38>)
    390c:	462b      	mov	r3, r5
    390e:	f853 4f1c 	ldr.w	r4, [r3, #28]!
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3912:	429c      	cmp	r4, r3
    3914:	d000      	beq.n	3918 <update_cache+0x10>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    3916:	b904      	cbnz	r4, 391a <update_cache+0x12>
    3918:	68ec      	ldr	r4, [r5, #12]
	if (z_is_thread_prevented_from_running(_current)) {
    391a:	68ab      	ldr	r3, [r5, #8]
	if (preempt_ok != 0) {
    391c:	b938      	cbnz	r0, 392e <update_cache+0x26>
	if (z_is_thread_prevented_from_running(_current)) {
    391e:	7b5a      	ldrb	r2, [r3, #13]
    3920:	06d2      	lsls	r2, r2, #27
    3922:	d104      	bne.n	392e <update_cache+0x26>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    3924:	69a2      	ldr	r2, [r4, #24]
    3926:	b912      	cbnz	r2, 392e <update_cache+0x26>
	if (is_preempt(_current) || is_metairq(thread)) {
    3928:	89da      	ldrh	r2, [r3, #14]
    392a:	2a7f      	cmp	r2, #127	; 0x7f
    392c:	d805      	bhi.n	393a <update_cache+0x32>
#ifndef CONFIG_SMP
	struct k_thread *thread = next_up();

	if (should_preempt(thread, preempt_ok)) {
#ifdef CONFIG_TIMESLICING
		if (thread != _current) {
    392e:	429c      	cmp	r4, r3
    3930:	d002      	beq.n	3938 <update_cache+0x30>
			z_reset_time_slice(thread);
    3932:	4620      	mov	r0, r4
    3934:	f7ff ffc0 	bl	38b8 <z_reset_time_slice>
		}
#endif
		update_metairq_preempt(thread);
		_kernel.ready_q.cache = thread;
    3938:	4623      	mov	r3, r4
    393a:	61ab      	str	r3, [r5, #24]
	 * thread because if the thread gets preempted for whatever
	 * reason the scheduler will make the same decision anyway.
	 */
	_current_cpu->swap_ok = preempt_ok;
#endif
}
    393c:	bd38      	pop	{r3, r4, r5, pc}
    393e:	bf00      	nop
    3940:	20000428 	.word	0x20000428

00003944 <move_thread_to_end_of_prio_q>:
{
    3944:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    3946:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return (thread->base.thread_state & state) != 0U;
    394a:	7b43      	ldrb	r3, [r0, #13]
    394c:	2a00      	cmp	r2, #0
{
    394e:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    3950:	da04      	bge.n	395c <move_thread_to_end_of_prio_q+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3952:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3956:	7343      	strb	r3, [r0, #13]

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
    3958:	f001 f8bd 	bl	4ad6 <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    395c:	7b4b      	ldrb	r3, [r1, #13]
	return list->head == list;
    395e:	4a15      	ldr	r2, [pc, #84]	; (39b4 <move_thread_to_end_of_prio_q+0x70>)
    3960:	f063 037f 	orn	r3, r3, #127	; 0x7f
    3964:	4610      	mov	r0, r2
    3966:	734b      	strb	r3, [r1, #13]
    3968:	f850 3f1c 	ldr.w	r3, [r0, #28]!
 */

static inline sys_dnode_t *sys_dlist_peek_next_no_check(sys_dlist_t *list,
							sys_dnode_t *node)
{
	return (node == list->tail) ? NULL : node->next;
    396c:	6a14      	ldr	r4, [r2, #32]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    396e:	4283      	cmp	r3, r0
    3970:	bf08      	it	eq
    3972:	2300      	moveq	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3974:	b923      	cbnz	r3, 3980 <move_thread_to_end_of_prio_q+0x3c>
static inline void sys_dlist_append(sys_dlist_t *list, sys_dnode_t *node)
{
	sys_dnode_t *const tail = list->tail;

	node->next = list;
	node->prev = tail;
    3976:	e9c1 0400 	strd	r0, r4, [r1]

	tail->next = node;
    397a:	6021      	str	r1, [r4, #0]
	list->tail = node;
    397c:	6211      	str	r1, [r2, #32]
}
    397e:	e00c      	b.n	399a <move_thread_to_end_of_prio_q+0x56>
	int32_t b1 = thread_1->base.prio;
    3980:	f991 500e 	ldrsb.w	r5, [r1, #14]
	int32_t b2 = thread_2->base.prio;
    3984:	f993 600e 	ldrsb.w	r6, [r3, #14]
	if (b1 != b2) {
    3988:	42b5      	cmp	r5, r6
    398a:	d00e      	beq.n	39aa <move_thread_to_end_of_prio_q+0x66>
		if (z_sched_prio_cmp(thread, t) > 0) {
    398c:	42ae      	cmp	r6, r5
    398e:	dd0c      	ble.n	39aa <move_thread_to_end_of_prio_q+0x66>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    3990:	6858      	ldr	r0, [r3, #4]

	node->prev = prev;
	node->next = successor;
    3992:	e9c1 3000 	strd	r3, r0, [r1]
	prev->next = node;
    3996:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    3998:	6059      	str	r1, [r3, #4]
	update_cache(thread == _current);
    399a:	6890      	ldr	r0, [r2, #8]
    399c:	1a43      	subs	r3, r0, r1
    399e:	4258      	negs	r0, r3
}
    39a0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    39a4:	4158      	adcs	r0, r3
    39a6:	f7ff bfaf 	b.w	3908 <update_cache>
	return (node == list->tail) ? NULL : node->next;
    39aa:	429c      	cmp	r4, r3
    39ac:	d0e3      	beq.n	3976 <move_thread_to_end_of_prio_q+0x32>
    39ae:	681b      	ldr	r3, [r3, #0]
    39b0:	e7e0      	b.n	3974 <move_thread_to_end_of_prio_q+0x30>
    39b2:	bf00      	nop
    39b4:	20000428 	.word	0x20000428

000039b8 <ready_thread>:
{
    39b8:	b470      	push	{r4, r5, r6}
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    39ba:	f990 300d 	ldrsb.w	r3, [r0, #13]
    39be:	7b42      	ldrb	r2, [r0, #13]
    39c0:	2b00      	cmp	r3, #0
    39c2:	db29      	blt.n	3a18 <ready_thread+0x60>
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    39c4:	06d3      	lsls	r3, r2, #27
    39c6:	d127      	bne.n	3a18 <ready_thread+0x60>
	return node->next != NULL;
    39c8:	6983      	ldr	r3, [r0, #24]
    39ca:	bb2b      	cbnz	r3, 3a18 <ready_thread+0x60>
	return list->head == list;
    39cc:	4913      	ldr	r1, [pc, #76]	; (3a1c <ready_thread+0x64>)
	thread->base.thread_state |= _THREAD_QUEUED;
    39ce:	f062 027f 	orn	r2, r2, #127	; 0x7f
    39d2:	7342      	strb	r2, [r0, #13]
    39d4:	460a      	mov	r2, r1
    39d6:	f852 4f1c 	ldr.w	r4, [r2, #28]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    39da:	4294      	cmp	r4, r2
    39dc:	bf18      	it	ne
    39de:	4623      	movne	r3, r4
	return (node == list->tail) ? NULL : node->next;
    39e0:	6a0c      	ldr	r4, [r1, #32]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    39e2:	b923      	cbnz	r3, 39ee <ready_thread+0x36>
	node->prev = tail;
    39e4:	e9c0 2400 	strd	r2, r4, [r0]
	tail->next = node;
    39e8:	6020      	str	r0, [r4, #0]
	list->tail = node;
    39ea:	6208      	str	r0, [r1, #32]
}
    39ec:	e00c      	b.n	3a08 <ready_thread+0x50>
	int32_t b1 = thread_1->base.prio;
    39ee:	f990 500e 	ldrsb.w	r5, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    39f2:	f993 600e 	ldrsb.w	r6, [r3, #14]
	if (b1 != b2) {
    39f6:	42b5      	cmp	r5, r6
    39f8:	d00a      	beq.n	3a10 <ready_thread+0x58>
		if (z_sched_prio_cmp(thread, t) > 0) {
    39fa:	42ae      	cmp	r6, r5
    39fc:	dd08      	ble.n	3a10 <ready_thread+0x58>
	sys_dnode_t *const prev = successor->prev;
    39fe:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    3a00:	e9c0 3200 	strd	r3, r2, [r0]
	prev->next = node;
    3a04:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    3a06:	6058      	str	r0, [r3, #4]
}
    3a08:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    3a0a:	2000      	movs	r0, #0
    3a0c:	f7ff bf7c 	b.w	3908 <update_cache>
	return (node == list->tail) ? NULL : node->next;
    3a10:	42a3      	cmp	r3, r4
    3a12:	d0e7      	beq.n	39e4 <ready_thread+0x2c>
    3a14:	681b      	ldr	r3, [r3, #0]
    3a16:	e7e4      	b.n	39e2 <ready_thread+0x2a>
}
    3a18:	bc70      	pop	{r4, r5, r6}
    3a1a:	4770      	bx	lr
    3a1c:	20000428 	.word	0x20000428

00003a20 <unready_thread>:
{
    3a20:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    3a22:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return (thread->base.thread_state & state) != 0U;
    3a26:	7b43      	ldrb	r3, [r0, #13]
    3a28:	2a00      	cmp	r2, #0
{
    3a2a:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    3a2c:	da04      	bge.n	3a38 <unready_thread+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3a2e:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3a32:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    3a34:	f001 f84f 	bl	4ad6 <sys_dlist_remove>
	update_cache(thread == _current);
    3a38:	4b04      	ldr	r3, [pc, #16]	; (3a4c <unready_thread+0x2c>)
    3a3a:	6898      	ldr	r0, [r3, #8]
    3a3c:	1a43      	subs	r3, r0, r1
    3a3e:	4258      	negs	r0, r3
    3a40:	4158      	adcs	r0, r3
}
    3a42:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    3a46:	f7ff bf5f 	b.w	3908 <update_cache>
    3a4a:	bf00      	nop
    3a4c:	20000428 	.word	0x20000428

00003a50 <pend_locked>:
{
    3a50:	b570      	push	{r4, r5, r6, lr}
    3a52:	4615      	mov	r5, r2
    3a54:	461c      	mov	r4, r3
    3a56:	4606      	mov	r6, r0
	add_to_waitq_locked(thread, wait_q);
    3a58:	f001 f84f 	bl	4afa <add_to_waitq_locked>
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3a5c:	f1b4 3fff 	cmp.w	r4, #4294967295
    3a60:	bf08      	it	eq
    3a62:	f1b5 3fff 	cmpeq.w	r5, #4294967295
    3a66:	d008      	beq.n	3a7a <pend_locked+0x2a>
    3a68:	462a      	mov	r2, r5
    3a6a:	4623      	mov	r3, r4
    3a6c:	f106 0018 	add.w	r0, r6, #24
    3a70:	4902      	ldr	r1, [pc, #8]	; (3a7c <pend_locked+0x2c>)
}
    3a72:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    3a76:	f000 ba4d 	b.w	3f14 <z_add_timeout>
    3a7a:	bd70      	pop	{r4, r5, r6, pc}
    3a7c:	00004baf 	.word	0x00004baf

00003a80 <z_time_slice>:
{
    3a80:	b538      	push	{r3, r4, r5, lr}
    3a82:	f04f 0320 	mov.w	r3, #32
    3a86:	f3ef 8511 	mrs	r5, BASEPRI
    3a8a:	f383 8812 	msr	BASEPRI_MAX, r3
    3a8e:	f3bf 8f6f 	isb	sy
	struct k_thread *curr = _current;
    3a92:	4b10      	ldr	r3, [pc, #64]	; (3ad4 <z_time_slice+0x54>)
	if (pending_current == curr) {
    3a94:	4a10      	ldr	r2, [pc, #64]	; (3ad8 <z_time_slice+0x58>)
	struct k_thread *curr = _current;
    3a96:	689c      	ldr	r4, [r3, #8]
	if (pending_current == curr) {
    3a98:	6810      	ldr	r0, [r2, #0]
    3a9a:	42a0      	cmp	r0, r4
    3a9c:	d106      	bne.n	3aac <z_time_slice+0x2c>
		z_reset_time_slice(curr);
    3a9e:	f7ff ff0b 	bl	38b8 <z_reset_time_slice>
	__asm__ volatile(
    3aa2:	f385 8811 	msr	BASEPRI, r5
    3aa6:	f3bf 8f6f 	isb	sy
}
    3aaa:	bd38      	pop	{r3, r4, r5, pc}
	pending_current = NULL;
    3aac:	2100      	movs	r1, #0
	if (slice_expired[_current_cpu->id] && sliceable(curr)) {
    3aae:	7c1b      	ldrb	r3, [r3, #16]
	pending_current = NULL;
    3ab0:	6011      	str	r1, [r2, #0]
	if (slice_expired[_current_cpu->id] && sliceable(curr)) {
    3ab2:	4a0a      	ldr	r2, [pc, #40]	; (3adc <z_time_slice+0x5c>)
    3ab4:	5cd3      	ldrb	r3, [r2, r3]
    3ab6:	2b00      	cmp	r3, #0
    3ab8:	d0f3      	beq.n	3aa2 <z_time_slice+0x22>
    3aba:	4620      	mov	r0, r4
    3abc:	f7ff fece 	bl	385c <sliceable>
    3ac0:	2800      	cmp	r0, #0
    3ac2:	d0ee      	beq.n	3aa2 <z_time_slice+0x22>
		if (!z_is_thread_prevented_from_running(curr)) {
    3ac4:	7b63      	ldrb	r3, [r4, #13]
    3ac6:	06db      	lsls	r3, r3, #27
    3ac8:	d102      	bne.n	3ad0 <z_time_slice+0x50>
			move_thread_to_end_of_prio_q(curr);
    3aca:	4620      	mov	r0, r4
    3acc:	f7ff ff3a 	bl	3944 <move_thread_to_end_of_prio_q>
		z_reset_time_slice(curr);
    3ad0:	4620      	mov	r0, r4
    3ad2:	e7e4      	b.n	3a9e <z_time_slice+0x1e>
    3ad4:	20000428 	.word	0x20000428
    3ad8:	2000044c 	.word	0x2000044c
    3adc:	2000086f 	.word	0x2000086f

00003ae0 <z_pend_curr>:
{
    3ae0:	b570      	push	{r4, r5, r6, lr}
	pending_current = _current;
    3ae2:	480c      	ldr	r0, [pc, #48]	; (3b14 <z_pend_curr+0x34>)
    3ae4:	4d0c      	ldr	r5, [pc, #48]	; (3b18 <z_pend_curr+0x38>)
    3ae6:	6886      	ldr	r6, [r0, #8]
    3ae8:	602e      	str	r6, [r5, #0]
{
    3aea:	460c      	mov	r4, r1
    3aec:	4611      	mov	r1, r2
    3aee:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
	__asm__ volatile(
    3af2:	f04f 0620 	mov.w	r6, #32
    3af6:	f3ef 8511 	mrs	r5, BASEPRI
    3afa:	f386 8812 	msr	BASEPRI_MAX, r6
    3afe:	f3bf 8f6f 	isb	sy
	pend_locked(_current, wait_q, timeout);
    3b02:	6880      	ldr	r0, [r0, #8]
    3b04:	f7ff ffa4 	bl	3a50 <pend_locked>
	ret = arch_swap(key);
    3b08:	4620      	mov	r0, r4
}
    3b0a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    3b0e:	f7fd bb0b 	b.w	1128 <arch_swap>
    3b12:	bf00      	nop
    3b14:	20000428 	.word	0x20000428
    3b18:	2000044c 	.word	0x2000044c

00003b1c <z_reschedule>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    3b1c:	b949      	cbnz	r1, 3b32 <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    3b1e:	f3ef 8005 	mrs	r0, IPSR
    3b22:	b930      	cbnz	r0, 3b32 <z_reschedule+0x16>
	new_thread = _kernel.ready_q.cache;
    3b24:	4b05      	ldr	r3, [pc, #20]	; (3b3c <z_reschedule+0x20>)
	if (resched(key.key) && need_swap()) {
    3b26:	699a      	ldr	r2, [r3, #24]
    3b28:	689b      	ldr	r3, [r3, #8]
    3b2a:	429a      	cmp	r2, r3
    3b2c:	d001      	beq.n	3b32 <z_reschedule+0x16>
    3b2e:	f7fd bafb 	b.w	1128 <arch_swap>
	__asm__ volatile(
    3b32:	f381 8811 	msr	BASEPRI, r1
    3b36:	f3bf 8f6f 	isb	sy
}
    3b3a:	4770      	bx	lr
    3b3c:	20000428 	.word	0x20000428

00003b40 <z_sched_start>:
{
    3b40:	b510      	push	{r4, lr}
	__asm__ volatile(
    3b42:	f04f 0220 	mov.w	r2, #32
    3b46:	f3ef 8411 	mrs	r4, BASEPRI
    3b4a:	f382 8812 	msr	BASEPRI_MAX, r2
    3b4e:	f3bf 8f6f 	isb	sy
	return (thread->base.thread_state & _THREAD_PRESTART) == 0U;
    3b52:	7b42      	ldrb	r2, [r0, #13]
	if (z_has_thread_started(thread)) {
    3b54:	0751      	lsls	r1, r2, #29
    3b56:	d404      	bmi.n	3b62 <z_sched_start+0x22>
	__asm__ volatile(
    3b58:	f384 8811 	msr	BASEPRI, r4
    3b5c:	f3bf 8f6f 	isb	sy
}
    3b60:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    3b62:	f022 0204 	bic.w	r2, r2, #4
    3b66:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    3b68:	f7ff ff26 	bl	39b8 <ready_thread>
	z_reschedule(&sched_spinlock, key);
    3b6c:	4621      	mov	r1, r4
    3b6e:	4802      	ldr	r0, [pc, #8]	; (3b78 <z_sched_start+0x38>)
}
    3b70:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    3b74:	f7ff bfd2 	b.w	3b1c <z_reschedule>
    3b78:	20000870 	.word	0x20000870

00003b7c <z_impl_k_thread_suspend>:
{
    3b7c:	b570      	push	{r4, r5, r6, lr}
    3b7e:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    3b80:	3018      	adds	r0, #24
    3b82:	f001 f84a 	bl	4c1a <z_abort_timeout>
	__asm__ volatile(
    3b86:	f04f 0320 	mov.w	r3, #32
    3b8a:	f3ef 8611 	mrs	r6, BASEPRI
    3b8e:	f383 8812 	msr	BASEPRI_MAX, r3
    3b92:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    3b96:	f994 200d 	ldrsb.w	r2, [r4, #13]
	return (thread->base.thread_state & state) != 0U;
    3b9a:	7b63      	ldrb	r3, [r4, #13]
    3b9c:	2a00      	cmp	r2, #0
    3b9e:	da05      	bge.n	3bac <z_impl_k_thread_suspend+0x30>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3ba0:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3ba4:	7363      	strb	r3, [r4, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    3ba6:	4620      	mov	r0, r4
    3ba8:	f000 ff95 	bl	4ad6 <sys_dlist_remove>
		update_cache(thread == _current);
    3bac:	4d0b      	ldr	r5, [pc, #44]	; (3bdc <z_impl_k_thread_suspend+0x60>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    3bae:	7b63      	ldrb	r3, [r4, #13]
    3bb0:	68a8      	ldr	r0, [r5, #8]
    3bb2:	f043 0310 	orr.w	r3, r3, #16
    3bb6:	7363      	strb	r3, [r4, #13]
    3bb8:	1b03      	subs	r3, r0, r4
    3bba:	4258      	negs	r0, r3
    3bbc:	4158      	adcs	r0, r3
    3bbe:	f7ff fea3 	bl	3908 <update_cache>
	__asm__ volatile(
    3bc2:	f386 8811 	msr	BASEPRI, r6
    3bc6:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    3bca:	68ab      	ldr	r3, [r5, #8]
    3bcc:	42a3      	cmp	r3, r4
    3bce:	d103      	bne.n	3bd8 <z_impl_k_thread_suspend+0x5c>
}
    3bd0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    3bd4:	f001 b817 	b.w	4c06 <z_reschedule_unlocked>
}
    3bd8:	bd70      	pop	{r4, r5, r6, pc}
    3bda:	bf00      	nop
    3bdc:	20000428 	.word	0x20000428

00003be0 <k_sched_lock>:
	__asm__ volatile(
    3be0:	f04f 0320 	mov.w	r3, #32
    3be4:	f3ef 8111 	mrs	r1, BASEPRI
    3be8:	f383 8812 	msr	BASEPRI_MAX, r3
    3bec:	f3bf 8f6f 	isb	sy
static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1U, "");

	--_current->base.sched_locked;
    3bf0:	4b04      	ldr	r3, [pc, #16]	; (3c04 <k_sched_lock+0x24>)
    3bf2:	689a      	ldr	r2, [r3, #8]
    3bf4:	7bd3      	ldrb	r3, [r2, #15]
    3bf6:	3b01      	subs	r3, #1
    3bf8:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    3bfa:	f381 8811 	msr	BASEPRI, r1
    3bfe:	f3bf 8f6f 	isb	sy
}
    3c02:	4770      	bx	lr
    3c04:	20000428 	.word	0x20000428

00003c08 <k_sched_unlock>:
{
    3c08:	b510      	push	{r4, lr}
	__asm__ volatile(
    3c0a:	f04f 0320 	mov.w	r3, #32
    3c0e:	f3ef 8411 	mrs	r4, BASEPRI
    3c12:	f383 8812 	msr	BASEPRI_MAX, r3
    3c16:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    3c1a:	4b08      	ldr	r3, [pc, #32]	; (3c3c <k_sched_unlock+0x34>)
    3c1c:	689a      	ldr	r2, [r3, #8]
    3c1e:	7bd3      	ldrb	r3, [r2, #15]
    3c20:	3301      	adds	r3, #1
    3c22:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    3c24:	2000      	movs	r0, #0
    3c26:	f7ff fe6f 	bl	3908 <update_cache>
	__asm__ volatile(
    3c2a:	f384 8811 	msr	BASEPRI, r4
    3c2e:	f3bf 8f6f 	isb	sy
}
    3c32:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    3c36:	f000 bfe6 	b.w	4c06 <z_reschedule_unlocked>
    3c3a:	bf00      	nop
    3c3c:	20000428 	.word	0x20000428

00003c40 <z_sched_init>:
	list->head = (sys_dnode_t *)list;
    3c40:	4b02      	ldr	r3, [pc, #8]	; (3c4c <z_sched_init+0xc>)
    3c42:	f103 021c 	add.w	r2, r3, #28
	list->tail = (sys_dnode_t *)list;
    3c46:	e9c3 2207 	strd	r2, r2, [r3, #28]
		init_ready_q(&_kernel.cpus[i].ready_q);
	}
#else
	init_ready_q(&_kernel.ready_q);
#endif
}
    3c4a:	4770      	bx	lr
    3c4c:	20000428 	.word	0x20000428

00003c50 <z_impl_k_yield>:
	return !(k_is_pre_kernel() || k_is_in_isr() ||
		 z_is_idle_thread_object(_current));
}

void z_impl_k_yield(void)
{
    3c50:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	__asm__ volatile(
    3c52:	f04f 0320 	mov.w	r3, #32
    3c56:	f3ef 8511 	mrs	r5, BASEPRI
    3c5a:	f383 8812 	msr	BASEPRI_MAX, r3
    3c5e:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if (!IS_ENABLED(CONFIG_SMP) ||
	    z_is_thread_queued(_current)) {
		dequeue_thread(_current);
    3c62:	4919      	ldr	r1, [pc, #100]	; (3cc8 <z_impl_k_yield+0x78>)
    3c64:	6888      	ldr	r0, [r1, #8]
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3c66:	7b43      	ldrb	r3, [r0, #13]
    3c68:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3c6c:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    3c6e:	f000 ff32 	bl	4ad6 <sys_dlist_remove>
	}
	queue_thread(_current);
    3c72:	688b      	ldr	r3, [r1, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    3c74:	7b5a      	ldrb	r2, [r3, #13]
	return list->head == list;
    3c76:	4608      	mov	r0, r1
    3c78:	f062 027f 	orn	r2, r2, #127	; 0x7f
    3c7c:	735a      	strb	r2, [r3, #13]
    3c7e:	f850 2f1c 	ldr.w	r2, [r0, #28]!
	return (node == list->tail) ? NULL : node->next;
    3c82:	6a0c      	ldr	r4, [r1, #32]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3c84:	4282      	cmp	r2, r0
    3c86:	bf08      	it	eq
    3c88:	2200      	moveq	r2, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3c8a:	b922      	cbnz	r2, 3c96 <z_impl_k_yield+0x46>
	node->prev = tail;
    3c8c:	e9c3 0400 	strd	r0, r4, [r3]
	tail->next = node;
    3c90:	6023      	str	r3, [r4, #0]
	list->tail = node;
    3c92:	620b      	str	r3, [r1, #32]
}
    3c94:	e00c      	b.n	3cb0 <z_impl_k_yield+0x60>
	int32_t b1 = thread_1->base.prio;
    3c96:	f993 600e 	ldrsb.w	r6, [r3, #14]
	int32_t b2 = thread_2->base.prio;
    3c9a:	f992 700e 	ldrsb.w	r7, [r2, #14]
	if (b1 != b2) {
    3c9e:	42be      	cmp	r6, r7
    3ca0:	d00e      	beq.n	3cc0 <z_impl_k_yield+0x70>
		if (z_sched_prio_cmp(thread, t) > 0) {
    3ca2:	42b7      	cmp	r7, r6
    3ca4:	dd0c      	ble.n	3cc0 <z_impl_k_yield+0x70>
	sys_dnode_t *const prev = successor->prev;
    3ca6:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
    3ca8:	e9c3 2100 	strd	r2, r1, [r3]
	prev->next = node;
    3cac:	600b      	str	r3, [r1, #0]
	successor->prev = node;
    3cae:	6053      	str	r3, [r2, #4]
	update_cache(1);
    3cb0:	2001      	movs	r0, #1
    3cb2:	f7ff fe29 	bl	3908 <update_cache>
    3cb6:	4628      	mov	r0, r5
	z_swap(&sched_spinlock, key);
}
    3cb8:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    3cbc:	f7fd ba34 	b.w	1128 <arch_swap>
	return (node == list->tail) ? NULL : node->next;
    3cc0:	42a2      	cmp	r2, r4
    3cc2:	d0e3      	beq.n	3c8c <z_impl_k_yield+0x3c>
    3cc4:	6812      	ldr	r2, [r2, #0]
    3cc6:	e7e0      	b.n	3c8a <z_impl_k_yield+0x3a>
    3cc8:	20000428 	.word	0x20000428

00003ccc <z_tick_sleep>:
	__ASSERT(!arch_is_in_isr(), "");

	LOG_DBG("thread %p for %lu ticks", _current, (unsigned long)ticks);

	/* wait of 0 ms is treated as a 'yield' */
	if (ticks == 0) {
    3ccc:	ea50 0301 	orrs.w	r3, r0, r1
{
    3cd0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3cd4:	4605      	mov	r5, r0
    3cd6:	460e      	mov	r6, r1
	if (ticks == 0) {
    3cd8:	d103      	bne.n	3ce2 <z_tick_sleep+0x16>
	z_impl_k_yield();
    3cda:	f7ff ffb9 	bl	3c50 <z_impl_k_yield>
		k_yield();
		return 0;
    3cde:	2000      	movs	r0, #0
    3ce0:	e02c      	b.n	3d3c <z_tick_sleep+0x70>
	}

	k_timeout_t timeout = Z_TIMEOUT_TICKS(ticks);
	if (Z_TICK_ABS(ticks) <= 0) {
    3ce2:	1c83      	adds	r3, r0, #2
    3ce4:	f171 33ff 	sbcs.w	r3, r1, #4294967295
    3ce8:	db2a      	blt.n	3d40 <z_tick_sleep+0x74>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    3cea:	f000 ffbc 	bl	4c66 <sys_clock_tick_get_32>
    3cee:	182c      	adds	r4, r5, r0
    3cf0:	f04f 0320 	mov.w	r3, #32
    3cf4:	f3ef 8811 	mrs	r8, BASEPRI
    3cf8:	f383 8812 	msr	BASEPRI_MAX, r3
    3cfc:	f3bf 8f6f 	isb	sy
	}

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

#if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC)
	pending_current = _current;
    3d00:	4f11      	ldr	r7, [pc, #68]	; (3d48 <z_tick_sleep+0x7c>)
    3d02:	4b12      	ldr	r3, [pc, #72]	; (3d4c <z_tick_sleep+0x80>)
    3d04:	68b8      	ldr	r0, [r7, #8]
    3d06:	6018      	str	r0, [r3, #0]
#endif
	unready_thread(_current);
    3d08:	f7ff fe8a 	bl	3a20 <unready_thread>
	z_add_thread_timeout(_current, timeout);
    3d0c:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    3d0e:	4910      	ldr	r1, [pc, #64]	; (3d50 <z_tick_sleep+0x84>)
    3d10:	462a      	mov	r2, r5
    3d12:	4633      	mov	r3, r6
    3d14:	3018      	adds	r0, #24
    3d16:	f000 f8fd 	bl	3f14 <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    3d1a:	68ba      	ldr	r2, [r7, #8]
	thread->base.thread_state |= _THREAD_SUSPENDED;
    3d1c:	7b53      	ldrb	r3, [r2, #13]
    3d1e:	f043 0310 	orr.w	r3, r3, #16
    3d22:	7353      	strb	r3, [r2, #13]
    3d24:	4640      	mov	r0, r8
    3d26:	f7fd f9ff 	bl	1128 <arch_swap>

	(void)z_swap(&sched_spinlock, key);

	__ASSERT(!z_is_thread_state_set(_current, _THREAD_SUSPENDED), "");

	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    3d2a:	f000 ff9c 	bl	4c66 <sys_clock_tick_get_32>
    3d2e:	1a20      	subs	r0, r4, r0
    3d30:	eb63 0303 	sbc.w	r3, r3, r3
	if (ticks > 0) {
    3d34:	2801      	cmp	r0, #1
    3d36:	f173 0300 	sbcs.w	r3, r3, #0
    3d3a:	dbd0      	blt.n	3cde <z_tick_sleep+0x12>
		return ticks;
	}
#endif

	return 0;
}
    3d3c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		expected_wakeup_ticks = Z_TICK_ABS(ticks);
    3d40:	f06f 0401 	mvn.w	r4, #1
    3d44:	1a24      	subs	r4, r4, r0
    3d46:	e7d3      	b.n	3cf0 <z_tick_sleep+0x24>
    3d48:	20000428 	.word	0x20000428
    3d4c:	2000044c 	.word	0x2000044c
    3d50:	00004baf 	.word	0x00004baf

00003d54 <z_impl_k_sleep>:
	__ASSERT(!arch_is_in_isr(), "");

	SYS_PORT_TRACING_FUNC_ENTER(k_thread, sleep, timeout);

	/* in case of K_FOREVER, we suspend */
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3d54:	f1b1 3fff 	cmp.w	r1, #4294967295
    3d58:	bf08      	it	eq
    3d5a:	f1b0 3fff 	cmpeq.w	r0, #4294967295
{
    3d5e:	b508      	push	{r3, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3d60:	d106      	bne.n	3d70 <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
    3d62:	4b08      	ldr	r3, [pc, #32]	; (3d84 <z_impl_k_sleep+0x30>)
    3d64:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    3d66:	f7ff ff09 	bl	3b7c <z_impl_k_thread_suspend>

		SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER);

		return (int32_t) K_TICKS_FOREVER;
    3d6a:	f04f 30ff 	mov.w	r0, #4294967295
	int32_t ret = k_ticks_to_ms_floor64(ticks);

	SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ret);

	return ret;
}
    3d6e:	bd08      	pop	{r3, pc}
	ticks = z_tick_sleep(ticks);
    3d70:	f7ff ffac 	bl	3ccc <z_tick_sleep>
    3d74:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    3d78:	fb80 0303 	smull	r0, r3, r0, r3
    3d7c:	0bc0      	lsrs	r0, r0, #15
    3d7e:	ea40 4043 	orr.w	r0, r0, r3, lsl #17
	return ret;
    3d82:	e7f4      	b.n	3d6e <z_impl_k_sleep+0x1a>
    3d84:	20000428 	.word	0x20000428

00003d88 <z_impl_z_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    3d88:	4b01      	ldr	r3, [pc, #4]	; (3d90 <z_impl_z_current_get+0x8>)
    3d8a:	6898      	ldr	r0, [r3, #8]
    3d8c:	4770      	bx	lr
    3d8e:	bf00      	nop
    3d90:	20000428 	.word	0x20000428

00003d94 <z_thread_abort>:
#endif
	}
}

void z_thread_abort(struct k_thread *thread)
{
    3d94:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3d98:	4604      	mov	r4, r0
    3d9a:	f04f 0320 	mov.w	r3, #32
    3d9e:	f3ef 8611 	mrs	r6, BASEPRI
    3da2:	f383 8812 	msr	BASEPRI_MAX, r3
    3da6:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.user_options & K_ESSENTIAL) != 0) {
    3daa:	7b03      	ldrb	r3, [r0, #12]
    3dac:	07d9      	lsls	r1, r3, #31
    3dae:	d50b      	bpl.n	3dc8 <z_thread_abort+0x34>
	__asm__ volatile(
    3db0:	f386 8811 	msr	BASEPRI, r6
    3db4:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&sched_spinlock, key);
		__ASSERT(false, "aborting essential thread %p", thread);
		k_panic();
    3db8:	4040      	eors	r0, r0
    3dba:	f380 8811 	msr	BASEPRI, r0
    3dbe:	f04f 0004 	mov.w	r0, #4
    3dc2:	df02      	svc	2
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
	}
	k_spin_unlock(&sched_spinlock, key);
}
    3dc4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    3dc8:	7b43      	ldrb	r3, [r0, #13]
    3dca:	071a      	lsls	r2, r3, #28
    3dcc:	d504      	bpl.n	3dd8 <z_thread_abort+0x44>
    3dce:	f386 8811 	msr	BASEPRI, r6
    3dd2:	f3bf 8f6f 	isb	sy
    3dd6:	e7f5      	b.n	3dc4 <z_thread_abort+0x30>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    3dd8:	f023 0220 	bic.w	r2, r3, #32
    3ddc:	f042 0108 	orr.w	r1, r2, #8
		if (z_is_thread_queued(thread)) {
    3de0:	09d2      	lsrs	r2, r2, #7
    3de2:	d120      	bne.n	3e26 <z_thread_abort+0x92>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    3de4:	7341      	strb	r1, [r0, #13]
		if (thread->base.pended_on != NULL) {
    3de6:	68a3      	ldr	r3, [r4, #8]
    3de8:	b113      	cbz	r3, 3df0 <z_thread_abort+0x5c>
			unpend_thread_no_timeout(thread);
    3dea:	4620      	mov	r0, r4
    3dec:	f000 fe7b 	bl	4ae6 <unpend_thread_no_timeout>
	return z_abort_timeout(&thread->base.timeout);
    3df0:	f104 0018 	add.w	r0, r4, #24
    3df4:	f000 ff11 	bl	4c1a <z_abort_timeout>
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    3df8:	f104 0758 	add.w	r7, r4, #88	; 0x58
    3dfc:	f04f 0800 	mov.w	r8, #0
	return list->head == list;
    3e00:	6da5      	ldr	r5, [r4, #88]	; 0x58
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3e02:	42bd      	cmp	r5, r7
    3e04:	d000      	beq.n	3e08 <z_thread_abort+0x74>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    3e06:	b9b5      	cbnz	r5, 3e36 <z_thread_abort+0xa2>
		update_cache(1);
    3e08:	2001      	movs	r0, #1
    3e0a:	f7ff fd7d 	bl	3908 <update_cache>
	if (thread == _current && !arch_is_in_isr()) {
    3e0e:	4b10      	ldr	r3, [pc, #64]	; (3e50 <z_thread_abort+0xbc>)
    3e10:	689b      	ldr	r3, [r3, #8]
    3e12:	42a3      	cmp	r3, r4
    3e14:	d1db      	bne.n	3dce <z_thread_abort+0x3a>
    3e16:	f3ef 8305 	mrs	r3, IPSR
    3e1a:	2b00      	cmp	r3, #0
    3e1c:	d1d7      	bne.n	3dce <z_thread_abort+0x3a>
    3e1e:	4630      	mov	r0, r6
    3e20:	f7fd f982 	bl	1128 <arch_swap>
	return ret;
    3e24:	e7d3      	b.n	3dce <z_thread_abort+0x3a>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3e26:	f003 035f 	and.w	r3, r3, #95	; 0x5f
    3e2a:	f043 0308 	orr.w	r3, r3, #8
    3e2e:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    3e30:	f000 fe51 	bl	4ad6 <sys_dlist_remove>
}
    3e34:	e7d7      	b.n	3de6 <z_thread_abort+0x52>
		unpend_thread_no_timeout(thread);
    3e36:	4628      	mov	r0, r5
    3e38:	f000 fe55 	bl	4ae6 <unpend_thread_no_timeout>
    3e3c:	f105 0018 	add.w	r0, r5, #24
    3e40:	f000 feeb 	bl	4c1a <z_abort_timeout>
    3e44:	f8c5 8078 	str.w	r8, [r5, #120]	; 0x78
		ready_thread(thread);
    3e48:	4628      	mov	r0, r5
    3e4a:	f7ff fdb5 	bl	39b8 <ready_thread>
    3e4e:	e7d7      	b.n	3e00 <z_thread_abort+0x6c>
    3e50:	20000428 	.word	0x20000428

00003e54 <z_data_copy>:
 * @brief Copy the data section from ROM to RAM
 *
 * This routine copies the data section from ROM to RAM.
 */
void z_data_copy(void)
{
    3e54:	b508      	push	{r3, lr}
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
		       __data_region_end - __data_region_start);
    3e56:	4806      	ldr	r0, [pc, #24]	; (3e70 <z_data_copy+0x1c>)
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
    3e58:	4a06      	ldr	r2, [pc, #24]	; (3e74 <z_data_copy+0x20>)
    3e5a:	4907      	ldr	r1, [pc, #28]	; (3e78 <z_data_copy+0x24>)
    3e5c:	1a12      	subs	r2, r2, r0
    3e5e:	f000 fe2b 	bl	4ab8 <z_early_memcpy>
#else
	z_early_memcpy(&_app_smem_start, &_app_smem_rom_start,
		       _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    3e62:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_early_memcpy(&__ramfunc_start, &__ramfunc_load_start,
    3e66:	4a05      	ldr	r2, [pc, #20]	; (3e7c <z_data_copy+0x28>)
    3e68:	4905      	ldr	r1, [pc, #20]	; (3e80 <z_data_copy+0x2c>)
    3e6a:	4806      	ldr	r0, [pc, #24]	; (3e84 <z_data_copy+0x30>)
    3e6c:	f000 be24 	b.w	4ab8 <z_early_memcpy>
    3e70:	20000000 	.word	0x20000000
    3e74:	20000134 	.word	0x20000134
    3e78:	0000513c 	.word	0x0000513c
    3e7c:	00000000 	.word	0x00000000
    3e80:	0000513c 	.word	0x0000513c
    3e84:	20000000 	.word	0x20000000

00003e88 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    3e88:	4b03      	ldr	r3, [pc, #12]	; (3e98 <elapsed+0x10>)
    3e8a:	681b      	ldr	r3, [r3, #0]
    3e8c:	b90b      	cbnz	r3, 3e92 <elapsed+0xa>
    3e8e:	f7fe bb43 	b.w	2518 <sys_clock_elapsed>
}
    3e92:	2000      	movs	r0, #0
    3e94:	4770      	bx	lr
    3e96:	bf00      	nop
    3e98:	20000458 	.word	0x20000458

00003e9c <next_timeout>:

static int32_t next_timeout(void)
{
    3e9c:	b510      	push	{r4, lr}
	return list->head == list;
    3e9e:	4b0e      	ldr	r3, [pc, #56]	; (3ed8 <next_timeout+0x3c>)
    3ea0:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3ea2:	429c      	cmp	r4, r3
    3ea4:	d104      	bne.n	3eb0 <next_timeout+0x14>
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    3ea6:	f7ff ffef 	bl	3e88 <elapsed>
	int32_t ret;

	if ((to == NULL) ||
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
		ret = MAX_WAIT;
    3eaa:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
	} else {
		ret = MAX(0, to->dticks - ticks_elapsed);
	}

	return ret;
}
    3eae:	bd10      	pop	{r4, pc}
	int32_t ticks_elapsed = elapsed();
    3eb0:	f7ff ffea 	bl	3e88 <elapsed>
	if ((to == NULL) ||
    3eb4:	2c00      	cmp	r4, #0
    3eb6:	d0f8      	beq.n	3eaa <next_timeout+0xe>
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
    3eb8:	e9d4 3204 	ldrd	r3, r2, [r4, #16]
    3ebc:	1a1b      	subs	r3, r3, r0
    3ebe:	eb62 72e0 	sbc.w	r2, r2, r0, asr #31
	if ((to == NULL) ||
    3ec2:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    3ec6:	f172 0100 	sbcs.w	r1, r2, #0
    3eca:	daee      	bge.n	3eaa <next_timeout+0xe>
		ret = MAX(0, to->dticks - ticks_elapsed);
    3ecc:	2a00      	cmp	r2, #0
    3ece:	bfac      	ite	ge
    3ed0:	4618      	movge	r0, r3
    3ed2:	2000      	movlt	r0, #0
	return ret;
    3ed4:	e7eb      	b.n	3eae <next_timeout+0x12>
    3ed6:	bf00      	nop
    3ed8:	20000124 	.word	0x20000124

00003edc <remove_timeout>:
{
    3edc:	b530      	push	{r4, r5, lr}
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3ede:	b170      	cbz	r0, 3efe <remove_timeout+0x22>
	return (node == list->tail) ? NULL : node->next;
    3ee0:	4b0b      	ldr	r3, [pc, #44]	; (3f10 <remove_timeout+0x34>)
    3ee2:	685b      	ldr	r3, [r3, #4]
    3ee4:	4298      	cmp	r0, r3
    3ee6:	d00a      	beq.n	3efe <remove_timeout+0x22>
    3ee8:	6803      	ldr	r3, [r0, #0]
	if (next(t) != NULL) {
    3eea:	b143      	cbz	r3, 3efe <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    3eec:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    3ef0:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    3ef4:	1912      	adds	r2, r2, r4
    3ef6:	eb41 0105 	adc.w	r1, r1, r5
    3efa:	e9c3 2104 	strd	r2, r1, [r3, #16]
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
	sys_dnode_t *const next = node->next;
    3efe:	e9d0 3200 	ldrd	r3, r2, [r0]

	prev->next = next;
    3f02:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    3f04:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    3f06:	2300      	movs	r3, #0
	node->prev = NULL;
    3f08:	e9c0 3300 	strd	r3, r3, [r0]
}
    3f0c:	bd30      	pop	{r4, r5, pc}
    3f0e:	bf00      	nop
    3f10:	20000124 	.word	0x20000124

00003f14 <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3f14:	f1b3 3fff 	cmp.w	r3, #4294967295
    3f18:	bf08      	it	eq
    3f1a:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    3f1e:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3f20:	4604      	mov	r4, r0
    3f22:	461d      	mov	r5, r3
    3f24:	4616      	mov	r6, r2
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3f26:	d05c      	beq.n	3fe2 <z_add_timeout+0xce>
#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    3f28:	6081      	str	r1, [r0, #8]
	__asm__ volatile(
    3f2a:	f04f 0320 	mov.w	r3, #32
    3f2e:	f3ef 8711 	mrs	r7, BASEPRI
    3f32:	f383 8812 	msr	BASEPRI_MAX, r3
    3f36:	f3bf 8f6f 	isb	sy

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    3f3a:	3201      	adds	r2, #1
    3f3c:	f175 33ff 	sbcs.w	r3, r5, #4294967295
    3f40:	da24      	bge.n	3f8c <z_add_timeout+0x78>
		    Z_TICK_ABS(timeout.ticks) >= 0) {
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    3f42:	492d      	ldr	r1, [pc, #180]	; (3ff8 <z_add_timeout+0xe4>)
    3f44:	e9d1 2000 	ldrd	r2, r0, [r1]
    3f48:	f06f 0301 	mvn.w	r3, #1
    3f4c:	1a9b      	subs	r3, r3, r2
    3f4e:	f04f 32ff 	mov.w	r2, #4294967295
    3f52:	eb62 0000 	sbc.w	r0, r2, r0
    3f56:	1b9e      	subs	r6, r3, r6
    3f58:	eb60 0005 	sbc.w	r0, r0, r5

			to->dticks = MAX(1, ticks);
    3f5c:	2e01      	cmp	r6, #1
    3f5e:	f170 0300 	sbcs.w	r3, r0, #0
    3f62:	da01      	bge.n	3f68 <z_add_timeout+0x54>
    3f64:	2601      	movs	r6, #1
    3f66:	2000      	movs	r0, #0
    3f68:	e9c4 6004 	strd	r6, r0, [r4, #16]
	return list->head == list;
    3f6c:	4e23      	ldr	r6, [pc, #140]	; (3ffc <z_add_timeout+0xe8>)
    3f6e:	f8d6 c000 	ldr.w	ip, [r6]
	return (node == list->tail) ? NULL : node->next;
    3f72:	6875      	ldr	r5, [r6, #4]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3f74:	45b4      	cmp	ip, r6
    3f76:	bf08      	it	eq
    3f78:	f04f 0c00 	moveq.w	ip, #0
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
		}

		for (t = first(); t != NULL; t = next(t)) {
    3f7c:	f1bc 0f00 	cmp.w	ip, #0
    3f80:	d10d      	bne.n	3f9e <z_add_timeout+0x8a>
	node->prev = tail;
    3f82:	e9c4 6500 	strd	r6, r5, [r4]
	tail->next = node;
    3f86:	602c      	str	r4, [r5, #0]
	list->tail = node;
    3f88:	6074      	str	r4, [r6, #4]
}
    3f8a:	e01c      	b.n	3fc6 <z_add_timeout+0xb2>
			to->dticks = timeout.ticks + 1 + elapsed();
    3f8c:	f7ff ff7c 	bl	3e88 <elapsed>
    3f90:	3601      	adds	r6, #1
    3f92:	f145 0500 	adc.w	r5, r5, #0
    3f96:	1836      	adds	r6, r6, r0
    3f98:	eb45 70e0 	adc.w	r0, r5, r0, asr #31
    3f9c:	e7e4      	b.n	3f68 <z_add_timeout+0x54>
			if (t->dticks > to->dticks) {
    3f9e:	e9dc 2004 	ldrd	r2, r0, [ip, #16]
    3fa2:	e9d4 3104 	ldrd	r3, r1, [r4, #16]
    3fa6:	4293      	cmp	r3, r2
    3fa8:	eb71 0e00 	sbcs.w	lr, r1, r0
    3fac:	da1a      	bge.n	3fe4 <z_add_timeout+0xd0>
				t->dticks -= to->dticks;
    3fae:	1ad2      	subs	r2, r2, r3
	sys_dnode_t *const prev = successor->prev;
    3fb0:	f8dc 3004 	ldr.w	r3, [ip, #4]
    3fb4:	eb60 0001 	sbc.w	r0, r0, r1
    3fb8:	e9cc 2004 	strd	r2, r0, [ip, #16]
	node->next = successor;
    3fbc:	e9c4 c300 	strd	ip, r3, [r4]
	prev->next = node;
    3fc0:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    3fc2:	f8cc 4004 	str.w	r4, [ip, #4]
	return list->head == list;
    3fc6:	6833      	ldr	r3, [r6, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3fc8:	42b3      	cmp	r3, r6
    3fca:	d006      	beq.n	3fda <z_add_timeout+0xc6>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    3fcc:	429c      	cmp	r4, r3
    3fce:	d104      	bne.n	3fda <z_add_timeout+0xc6>
			sys_clock_set_timeout(next_timeout(), false);
    3fd0:	f7ff ff64 	bl	3e9c <next_timeout>
    3fd4:	2100      	movs	r1, #0
    3fd6:	f7fe fa6d 	bl	24b4 <sys_clock_set_timeout>
	__asm__ volatile(
    3fda:	f387 8811 	msr	BASEPRI, r7
    3fde:	f3bf 8f6f 	isb	sy
		}
	}
}
    3fe2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
			to->dticks -= t->dticks;
    3fe4:	1a9b      	subs	r3, r3, r2
    3fe6:	eb61 0100 	sbc.w	r1, r1, r0
	return (node == list->tail) ? NULL : node->next;
    3fea:	45ac      	cmp	ip, r5
    3fec:	e9c4 3104 	strd	r3, r1, [r4, #16]
    3ff0:	d0c7      	beq.n	3f82 <z_add_timeout+0x6e>
    3ff2:	f8dc c000 	ldr.w	ip, [ip]
    3ff6:	e7c1      	b.n	3f7c <z_add_timeout+0x68>
    3ff8:	20000270 	.word	0x20000270
    3ffc:	20000124 	.word	0x20000124

00004000 <sys_clock_announce>:
	}
	return ret;
}

void sys_clock_announce(int32_t ticks)
{
    4000:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	__asm__ volatile(
    4004:	f04f 0320 	mov.w	r3, #32
    4008:	f3ef 8c11 	mrs	ip, BASEPRI
    400c:	f383 8812 	msr	BASEPRI_MAX, r3
    4010:	f3bf 8f6f 	isb	sy
	return list->head == list;
    4014:	f8df a0b0 	ldr.w	sl, [pc, #176]	; 40c8 <sys_clock_announce+0xc8>
		announce_remaining += ticks;
		k_spin_unlock(&timeout_lock, key);
		return;
	}

	announce_remaining = ticks;
    4018:	f8df 90b0 	ldr.w	r9, [pc, #176]	; 40cc <sys_clock_announce+0xcc>
	for (t = first();
	     (t != NULL) && (t->dticks <= announce_remaining);
	     t = first()) {
		int dt = t->dticks;

		curr_tick += dt;
    401c:	4f2c      	ldr	r7, [pc, #176]	; (40d0 <sys_clock_announce+0xd0>)
	announce_remaining = ticks;
    401e:	f8c9 0000 	str.w	r0, [r9]
    4022:	f8da 0000 	ldr.w	r0, [sl]
		t->dticks = 0;
    4026:	2400      	movs	r4, #0
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4028:	4550      	cmp	r0, sl
    402a:	bf08      	it	eq
    402c:	2000      	moveq	r0, #0
    402e:	2500      	movs	r5, #0
		curr_tick += dt;
    4030:	e9d7 2100 	ldrd	r2, r1, [r7]
	     (t != NULL) && (t->dticks <= announce_remaining);
    4034:	f8d9 3000 	ldr.w	r3, [r9]
    4038:	46e0      	mov	r8, ip
    403a:	b380      	cbz	r0, 409e <sys_clock_announce+0x9e>
    403c:	e9d0 6c04 	ldrd	r6, ip, [r0, #16]
    4040:	ea4f 7ee3 	mov.w	lr, r3, asr #31
    4044:	42b3      	cmp	r3, r6
    4046:	eb7e 0b0c 	sbcs.w	fp, lr, ip
    404a:	da05      	bge.n	4058 <sys_clock_announce+0x58>
		key = k_spin_lock(&timeout_lock);
		announce_remaining -= dt;
	}

	if (t != NULL) {
		t->dticks -= announce_remaining;
    404c:	1af6      	subs	r6, r6, r3
    404e:	eb6c 040e 	sbc.w	r4, ip, lr
    4052:	e9c0 6404 	strd	r6, r4, [r0, #16]
    4056:	e022      	b.n	409e <sys_clock_announce+0x9e>
		curr_tick += dt;
    4058:	18b2      	adds	r2, r6, r2
    405a:	eb41 71e6 	adc.w	r1, r1, r6, asr #31
		t->dticks = 0;
    405e:	e9c0 4504 	strd	r4, r5, [r0, #16]
		curr_tick += dt;
    4062:	e9c7 2100 	strd	r2, r1, [r7]
		remove_timeout(t);
    4066:	f7ff ff39 	bl	3edc <remove_timeout>
	__asm__ volatile(
    406a:	f388 8811 	msr	BASEPRI, r8
    406e:	f3bf 8f6f 	isb	sy
		t->fn(t);
    4072:	6883      	ldr	r3, [r0, #8]
    4074:	4798      	blx	r3
	__asm__ volatile(
    4076:	f04f 0320 	mov.w	r3, #32
    407a:	f3ef 8811 	mrs	r8, BASEPRI
    407e:	f383 8812 	msr	BASEPRI_MAX, r3
    4082:	f3bf 8f6f 	isb	sy
		announce_remaining -= dt;
    4086:	f8d9 3000 	ldr.w	r3, [r9]
	return list->head == list;
    408a:	f8da 0000 	ldr.w	r0, [sl]
    408e:	1b9b      	subs	r3, r3, r6
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4090:	4550      	cmp	r0, sl
	k.key = arch_irq_lock();
    4092:	46c4      	mov	ip, r8
    4094:	f8c9 3000 	str.w	r3, [r9]
    4098:	d1ca      	bne.n	4030 <sys_clock_announce+0x30>
		curr_tick += dt;
    409a:	e9d7 2100 	ldrd	r2, r1, [r7]
	}

	curr_tick += announce_remaining;
    409e:	189a      	adds	r2, r3, r2
    40a0:	eb41 73e3 	adc.w	r3, r1, r3, asr #31
	announce_remaining = 0;
    40a4:	2400      	movs	r4, #0
	curr_tick += announce_remaining;
    40a6:	e9c7 2300 	strd	r2, r3, [r7]
	announce_remaining = 0;
    40aa:	f8c9 4000 	str.w	r4, [r9]

	sys_clock_set_timeout(next_timeout(), false);
    40ae:	f7ff fef5 	bl	3e9c <next_timeout>
    40b2:	4621      	mov	r1, r4
    40b4:	f7fe f9fe 	bl	24b4 <sys_clock_set_timeout>
	__asm__ volatile(
    40b8:	f388 8811 	msr	BASEPRI, r8
    40bc:	f3bf 8f6f 	isb	sy
	k_spin_unlock(&timeout_lock, key);

#ifdef CONFIG_TIMESLICING
	z_time_slice();
#endif
}
    40c0:	e8bd 4ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	z_time_slice();
    40c4:	f7ff bcdc 	b.w	3a80 <z_time_slice>
    40c8:	20000124 	.word	0x20000124
    40cc:	20000458 	.word	0x20000458
    40d0:	20000270 	.word	0x20000270

000040d4 <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    40d4:	b510      	push	{r4, lr}
	__asm__ volatile(
    40d6:	f04f 0320 	mov.w	r3, #32
    40da:	f3ef 8411 	mrs	r4, BASEPRI
    40de:	f383 8812 	msr	BASEPRI_MAX, r3
    40e2:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + elapsed();
    40e6:	f7ff fecf 	bl	3e88 <elapsed>
    40ea:	4a06      	ldr	r2, [pc, #24]	; (4104 <sys_clock_tick_get+0x30>)
    40ec:	4603      	mov	r3, r0
    40ee:	e9d2 0100 	ldrd	r0, r1, [r2]
    40f2:	1818      	adds	r0, r3, r0
    40f4:	eb41 71e3 	adc.w	r1, r1, r3, asr #31
	__asm__ volatile(
    40f8:	f384 8811 	msr	BASEPRI, r4
    40fc:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    4100:	bd10      	pop	{r4, pc}
    4102:	bf00      	nop
    4104:	20000270 	.word	0x20000270

00004108 <boot_banner>:
	printk("***** delaying boot " DELAY_STR "ms (per build configuration) *****\n");
	k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
#endif /* defined(CONFIG_BOOT_DELAY) && (CONFIG_BOOT_DELAY > 0) */

#if CONFIG_BOOT_BANNER
	printk("*** Booting Zephyr OS build " BANNER_VERSION BANNER_POSTFIX " ***\n");
    4108:	4801      	ldr	r0, [pc, #4]	; (4110 <boot_banner+0x8>)
    410a:	f000 b805 	b.w	4118 <printk>
    410e:	bf00      	nop
    4110:	0000510b 	.word	0x0000510b

00004114 <arch_printk_char_out>:
}
    4114:	2000      	movs	r0, #0
    4116:	4770      	bx	lr

00004118 <printk>:
 *
 * @param fmt formatted string to output
 */

void printk(const char *fmt, ...)
{
    4118:	b40f      	push	{r0, r1, r2, r3}
    411a:	b507      	push	{r0, r1, r2, lr}
    411c:	a904      	add	r1, sp, #16
    411e:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    4122:	9101      	str	r1, [sp, #4]

	vprintk(fmt, ap);
    4124:	f7fc f970 	bl	408 <vprintk>

	va_end(ap);
}
    4128:	b003      	add	sp, #12
    412a:	f85d eb04 	ldr.w	lr, [sp], #4
    412e:	b004      	add	sp, #16
    4130:	4770      	bx	lr

00004132 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    4132:	4604      	mov	r4, r0
    4134:	b508      	push	{r3, lr}
    4136:	4608      	mov	r0, r1
    4138:	4611      	mov	r1, r2
#ifdef CONFIG_THREAD_LOCAL_STORAGE
	z_tls_current = z_current_get();
#endif
	entry(p1, p2, p3);
    413a:	461a      	mov	r2, r3
    413c:	47a0      	blx	r4
	return z_impl_z_current_get();
    413e:	f7ff fe23 	bl	3d88 <z_impl_z_current_get>
	z_impl_k_thread_abort(thread);
    4142:	f7fd fa85 	bl	1650 <z_impl_k_thread_abort>

00004146 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    4146:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    4148:	f013 0307 	ands.w	r3, r3, #7
    414c:	d105      	bne.n	415a <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    414e:	6803      	ldr	r3, [r0, #0]
		evt = EVT_START;
    4150:	2b00      	cmp	r3, #0
    4152:	bf0c      	ite	eq
    4154:	2000      	moveq	r0, #0
    4156:	2003      	movne	r0, #3
    4158:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    415a:	2b02      	cmp	r3, #2
    415c:	d105      	bne.n	416a <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    415e:	8b40      	ldrh	r0, [r0, #26]
    4160:	fab0 f080 	clz	r0, r0
    4164:	0940      	lsrs	r0, r0, #5
    4166:	0080      	lsls	r0, r0, #2
    4168:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    416a:	2b01      	cmp	r3, #1
    416c:	d105      	bne.n	417a <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    416e:	6803      	ldr	r3, [r0, #0]
		evt = EVT_RESET;
    4170:	2b00      	cmp	r3, #0
    4172:	bf0c      	ite	eq
    4174:	2000      	moveq	r0, #0
    4176:	2005      	movne	r0, #5
    4178:	4770      	bx	lr
	int evt = EVT_NOP;
    417a:	2000      	movs	r0, #0
}
    417c:	4770      	bx	lr

0000417e <validate_args>:
{
    417e:	b510      	push	{r4, lr}
    4180:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    4182:	b100      	cbz	r0, 4186 <validate_args+0x8>
    4184:	b911      	cbnz	r1, 418c <validate_args+0xe>
		return -EINVAL;
    4186:	f06f 0015 	mvn.w	r0, #21
}
    418a:	bd10      	pop	{r4, pc}
	int rv = sys_notify_validate(&cli->notify);
    418c:	1d08      	adds	r0, r1, #4
    418e:	f000 f895 	bl	42bc <sys_notify_validate>
	if ((rv == 0)
    4192:	2800      	cmp	r0, #0
    4194:	d1f9      	bne.n	418a <validate_args+0xc>
	    && ((cli->notify.flags
    4196:	68a3      	ldr	r3, [r4, #8]
    4198:	2b03      	cmp	r3, #3
    419a:	d9f6      	bls.n	418a <validate_args+0xc>
    419c:	e7f3      	b.n	4186 <validate_args+0x8>

0000419e <notify_one>:
{
    419e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    41a2:	460d      	mov	r5, r1
    41a4:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    41a6:	4619      	mov	r1, r3
    41a8:	1d28      	adds	r0, r5, #4
{
    41aa:	4690      	mov	r8, r2
    41ac:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    41ae:	f000 f896 	bl	42de <sys_notify_finalize>
	if (cb) {
    41b2:	4604      	mov	r4, r0
    41b4:	b138      	cbz	r0, 41c6 <notify_one+0x28>
		cb(mgr, cli, state, res);
    41b6:	4633      	mov	r3, r6
    41b8:	4642      	mov	r2, r8
    41ba:	4629      	mov	r1, r5
    41bc:	4638      	mov	r0, r7
    41be:	46a4      	mov	ip, r4
}
    41c0:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    41c4:	4760      	bx	ip
}
    41c6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

000041ca <transition_complete>:
{
    41ca:	b410      	push	{r4}
	__asm__ volatile(
    41cc:	f04f 0420 	mov.w	r4, #32
    41d0:	f3ef 8211 	mrs	r2, BASEPRI
    41d4:	f384 8812 	msr	BASEPRI_MAX, r4
    41d8:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    41dc:	6141      	str	r1, [r0, #20]
}
    41de:	bc10      	pop	{r4}
	process_event(mgr, EVT_COMPLETE, key);
    41e0:	2101      	movs	r1, #1
    41e2:	f7fc b91f 	b.w	424 <process_event>

000041e6 <onoff_manager_init>:
{
    41e6:	b538      	push	{r3, r4, r5, lr}
    41e8:	460c      	mov	r4, r1
	if ((mgr == NULL)
    41ea:	4605      	mov	r5, r0
    41ec:	b158      	cbz	r0, 4206 <onoff_manager_init+0x20>
	    || (transitions == NULL)
    41ee:	b151      	cbz	r1, 4206 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    41f0:	680b      	ldr	r3, [r1, #0]
    41f2:	b143      	cbz	r3, 4206 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    41f4:	684b      	ldr	r3, [r1, #4]
    41f6:	b133      	cbz	r3, 4206 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    41f8:	221c      	movs	r2, #28
    41fa:	2100      	movs	r1, #0
    41fc:	f000 f910 	bl	4420 <memset>
    4200:	612c      	str	r4, [r5, #16]
	return 0;
    4202:	2000      	movs	r0, #0
}
    4204:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    4206:	f06f 0015 	mvn.w	r0, #21
    420a:	e7fb      	b.n	4204 <onoff_manager_init+0x1e>

0000420c <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    420c:	b570      	push	{r4, r5, r6, lr}
    420e:	4605      	mov	r5, r0
    4210:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    4212:	f7ff ffb4 	bl	417e <validate_args>

	if (rv < 0) {
    4216:	1e04      	subs	r4, r0, #0
    4218:	db15      	blt.n	4246 <onoff_request+0x3a>
    421a:	f04f 0320 	mov.w	r3, #32
    421e:	f3ef 8211 	mrs	r2, BASEPRI
    4222:	f383 8812 	msr	BASEPRI_MAX, r3
    4226:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    422a:	8b6b      	ldrh	r3, [r5, #26]
    422c:	8b2c      	ldrh	r4, [r5, #24]
    422e:	f64f 71ff 	movw	r1, #65535	; 0xffff
    4232:	428b      	cmp	r3, r1
    4234:	f004 0407 	and.w	r4, r4, #7
    4238:	d107      	bne.n	424a <onoff_request+0x3e>
	__asm__ volatile(
    423a:	f382 8811 	msr	BASEPRI, r2
    423e:	f3bf 8f6f 	isb	sy
		rv = -EAGAIN;
    4242:	f06f 040a 	mvn.w	r4, #10
			notify_one(mgr, cli, state, 0);
		}
	}

	return rv;
}
    4246:	4620      	mov	r0, r4
    4248:	bd70      	pop	{r4, r5, r6, pc}
	if (state == ONOFF_STATE_ON) {
    424a:	2c02      	cmp	r4, #2
    424c:	d10c      	bne.n	4268 <onoff_request+0x5c>
		mgr->refs += 1U;
    424e:	3301      	adds	r3, #1
    4250:	836b      	strh	r3, [r5, #26]
    4252:	f382 8811 	msr	BASEPRI, r2
    4256:	f3bf 8f6f 	isb	sy
			notify_one(mgr, cli, state, 0);
    425a:	2300      	movs	r3, #0
    425c:	4622      	mov	r2, r4
    425e:	4631      	mov	r1, r6
    4260:	4628      	mov	r0, r5
    4262:	f7ff ff9c 	bl	419e <notify_one>
    4266:	e7ee      	b.n	4246 <onoff_request+0x3a>
	} else if ((state == ONOFF_STATE_OFF)
    4268:	2c06      	cmp	r4, #6
    426a:	d814      	bhi.n	4296 <onoff_request+0x8a>
    426c:	e8df f004 	tbb	[pc, r4]
    4270:	13131304 	.word	0x13131304
    4274:	1a04      	.short	0x1a04
    4276:	04          	.byte	0x04
    4277:	00          	.byte	0x00
	parent->next = child;
    4278:	2300      	movs	r3, #0
    427a:	6033      	str	r3, [r6, #0]
 *
 * @return A pointer on the last node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_tail(sys_slist_t *list)
{
	return list->tail;
    427c:	686b      	ldr	r3, [r5, #4]
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
				    sys_snode_t *node);

Z_GENLIST_APPEND(slist, snode)
    427e:	b93b      	cbnz	r3, 4290 <onoff_request+0x84>
	list->head = node;
    4280:	e9c5 6600 	strd	r6, r6, [r5]
	if (start) {
    4284:	b9ac      	cbnz	r4, 42b2 <onoff_request+0xa6>
		process_event(mgr, EVT_RECHECK, key);
    4286:	2102      	movs	r1, #2
    4288:	4628      	mov	r0, r5
    428a:	f7fc f8cb 	bl	424 <process_event>
    428e:	e7da      	b.n	4246 <onoff_request+0x3a>
	parent->next = child;
    4290:	601e      	str	r6, [r3, #0]
	list->tail = node;
    4292:	606e      	str	r6, [r5, #4]
}
    4294:	e7f6      	b.n	4284 <onoff_request+0x78>
    4296:	f382 8811 	msr	BASEPRI, r2
    429a:	f3bf 8f6f 	isb	sy
		rv = -EIO;
    429e:	f06f 0404 	mvn.w	r4, #4
    42a2:	e7d0      	b.n	4246 <onoff_request+0x3a>
    42a4:	f382 8811 	msr	BASEPRI, r2
    42a8:	f3bf 8f6f 	isb	sy
    42ac:	f06f 0485 	mvn.w	r4, #133	; 0x85
    42b0:	e7c9      	b.n	4246 <onoff_request+0x3a>
    42b2:	f382 8811 	msr	BASEPRI, r2
    42b6:	f3bf 8f6f 	isb	sy
		if (notify) {
    42ba:	e7c4      	b.n	4246 <onoff_request+0x3a>

000042bc <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    42bc:	4603      	mov	r3, r0
    42be:	b158      	cbz	r0, 42d8 <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    42c0:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    42c2:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    42c6:	2a01      	cmp	r2, #1
    42c8:	d003      	beq.n	42d2 <sys_notify_validate+0x16>
    42ca:	2a03      	cmp	r2, #3
    42cc:	d104      	bne.n	42d8 <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    42ce:	6802      	ldr	r2, [r0, #0]
    42d0:	b112      	cbz	r2, 42d8 <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    42d2:	2000      	movs	r0, #0
    42d4:	6098      	str	r0, [r3, #8]
    42d6:	4770      	bx	lr
    42d8:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    42dc:	4770      	bx	lr

000042de <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    42de:	6842      	ldr	r2, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    42e0:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    42e2:	f002 0203 	and.w	r2, r2, #3
	switch (method) {
    42e6:	2a03      	cmp	r2, #3
    42e8:	f04f 0200 	mov.w	r2, #0
{
    42ec:	4603      	mov	r3, r0
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    42ee:	bf0c      	ite	eq
    42f0:	6800      	ldreq	r0, [r0, #0]
	sys_notify_generic_callback rv = NULL;
    42f2:	4610      	movne	r0, r2
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    42f4:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    42f6:	4770      	bx	lr

000042f8 <encode_uint>:
{
    42f8:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    42fc:	469a      	mov	sl, r3
	bool upcase = isupper((int)conv->specifier) != 0;
    42fe:	78d3      	ldrb	r3, [r2, #3]
	switch (specifier) {
    4300:	2b6f      	cmp	r3, #111	; 0x6f
{
    4302:	4680      	mov	r8, r0
    4304:	460f      	mov	r7, r1
    4306:	4615      	mov	r5, r2
	return (int)(((unsigned)(a)-(unsigned)'A') < 26U);
    4308:	f1a3 0b41 	sub.w	fp, r3, #65	; 0x41
	switch (specifier) {
    430c:	d029      	beq.n	4362 <encode_uint+0x6a>
    430e:	d824      	bhi.n	435a <encode_uint+0x62>
		return 10;
    4310:	2b58      	cmp	r3, #88	; 0x58
    4312:	bf0c      	ite	eq
    4314:	2610      	moveq	r6, #16
    4316:	260a      	movne	r6, #10
	char *bp = bps + (bpe - bps);
    4318:	f8dd 9028 	ldr.w	r9, [sp, #40]	; 0x28
		unsigned int lsv = (unsigned int)(value % radix);
    431c:	4632      	mov	r2, r6
    431e:	2300      	movs	r3, #0
    4320:	4640      	mov	r0, r8
    4322:	4639      	mov	r1, r7
    4324:	f7fb feda 	bl	dc <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    4328:	2a09      	cmp	r2, #9
    432a:	b2d4      	uxtb	r4, r2
    432c:	d81e      	bhi.n	436c <encode_uint+0x74>
    432e:	3430      	adds	r4, #48	; 0x30
	} while ((value != 0) && (bps < bp));
    4330:	45b0      	cmp	r8, r6
		*--bp = (lsv <= 9) ? ('0' + lsv)
    4332:	b2e4      	uxtb	r4, r4
	} while ((value != 0) && (bps < bp));
    4334:	f177 0700 	sbcs.w	r7, r7, #0
		*--bp = (lsv <= 9) ? ('0' + lsv)
    4338:	f809 4d01 	strb.w	r4, [r9, #-1]!
	} while ((value != 0) && (bps < bp));
    433c:	d301      	bcc.n	4342 <encode_uint+0x4a>
    433e:	45d1      	cmp	r9, sl
    4340:	d811      	bhi.n	4366 <encode_uint+0x6e>
	if (conv->flag_hash) {
    4342:	782b      	ldrb	r3, [r5, #0]
    4344:	069b      	lsls	r3, r3, #26
    4346:	d505      	bpl.n	4354 <encode_uint+0x5c>
		if (radix == 8) {
    4348:	2e08      	cmp	r6, #8
    434a:	d115      	bne.n	4378 <encode_uint+0x80>
			conv->altform_0 = true;
    434c:	78ab      	ldrb	r3, [r5, #2]
    434e:	f043 0308 	orr.w	r3, r3, #8
			conv->altform_0c = true;
    4352:	70ab      	strb	r3, [r5, #2]
}
    4354:	4648      	mov	r0, r9
    4356:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	switch (specifier) {
    435a:	f003 03f7 	and.w	r3, r3, #247	; 0xf7
		return 10;
    435e:	2b70      	cmp	r3, #112	; 0x70
    4360:	e7d7      	b.n	4312 <encode_uint+0x1a>
	switch (specifier) {
    4362:	2608      	movs	r6, #8
    4364:	e7d8      	b.n	4318 <encode_uint+0x20>
		value /= radix;
    4366:	4680      	mov	r8, r0
    4368:	460f      	mov	r7, r1
    436a:	e7d7      	b.n	431c <encode_uint+0x24>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    436c:	f1bb 0f19 	cmp.w	fp, #25
    4370:	bf94      	ite	ls
    4372:	3437      	addls	r4, #55	; 0x37
    4374:	3457      	addhi	r4, #87	; 0x57
    4376:	e7db      	b.n	4330 <encode_uint+0x38>
		} else if (radix == 16) {
    4378:	2e10      	cmp	r6, #16
    437a:	d1eb      	bne.n	4354 <encode_uint+0x5c>
			conv->altform_0c = true;
    437c:	78ab      	ldrb	r3, [r5, #2]
    437e:	f043 0310 	orr.w	r3, r3, #16
    4382:	e7e6      	b.n	4352 <encode_uint+0x5a>

00004384 <outs>:
{
    4384:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4388:	4607      	mov	r7, r0
    438a:	4688      	mov	r8, r1
    438c:	4615      	mov	r5, r2
    438e:	461e      	mov	r6, r3
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    4390:	4614      	mov	r4, r2
    4392:	42b4      	cmp	r4, r6
    4394:	d305      	bcc.n	43a2 <outs+0x1e>
    4396:	b10e      	cbz	r6, 439c <outs+0x18>
	return (int)count;
    4398:	1b60      	subs	r0, r4, r5
    439a:	e008      	b.n	43ae <outs+0x2a>
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    439c:	7823      	ldrb	r3, [r4, #0]
    439e:	2b00      	cmp	r3, #0
    43a0:	d0fa      	beq.n	4398 <outs+0x14>
		int rc = out((int)*sp++, ctx);
    43a2:	f814 0b01 	ldrb.w	r0, [r4], #1
    43a6:	4641      	mov	r1, r8
    43a8:	47b8      	blx	r7
		if (rc < 0) {
    43aa:	2800      	cmp	r0, #0
    43ac:	daf1      	bge.n	4392 <outs+0xe>
}
    43ae:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

000043b2 <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_STRIP_PATHS, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_WARN_DEPRECATED, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_ENFORCE_ZEPHYR_STDINT, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    43b2:	4770      	bx	lr

000043b4 <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    43b4:	f000 bb63 	b.w	4a7e <z_fatal_error>

000043b8 <z_do_kernel_oops>:
 *
 * @param esf exception frame
 * @param callee_regs Callee-saved registers (R4-R11)
 */
void z_do_kernel_oops(const z_arch_esf_t *esf, _callee_saved_t *callee_regs)
{
    43b8:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
    43ba:	6800      	ldr	r0, [r0, #0]
    43bc:	f000 bb5f 	b.w	4a7e <z_fatal_error>

000043c0 <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    43c0:	2100      	movs	r1, #0
    43c2:	2001      	movs	r0, #1
    43c4:	f7ff bff6 	b.w	43b4 <z_arm_fatal_error>

000043c8 <z_arm_nmi>:
 * Simply call what is installed in 'static void(*handler)(void)'.
 *
 */

void z_arm_nmi(void)
{
    43c8:	b508      	push	{r3, lr}
	handler();
    43ca:	f7fc fe8d 	bl	10e8 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    43ce:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    43d2:	f7fc bf65 	b.w	12a0 <z_arm_exc_exit>

000043d6 <strcpy>:

char *strcpy(char *ZRESTRICT d, const char *ZRESTRICT s)
{
	char *dest = d;

	while (*s != '\0') {
    43d6:	3901      	subs	r1, #1
    43d8:	4603      	mov	r3, r0
    43da:	f811 2f01 	ldrb.w	r2, [r1, #1]!
    43de:	b90a      	cbnz	r2, 43e4 <strcpy+0xe>
		*d = *s;
		d++;
		s++;
	}

	*d = '\0';
    43e0:	701a      	strb	r2, [r3, #0]

	return dest;
}
    43e2:	4770      	bx	lr
		*d = *s;
    43e4:	f803 2b01 	strb.w	r2, [r3], #1
		s++;
    43e8:	e7f7      	b.n	43da <strcpy+0x4>

000043ea <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    43ea:	4603      	mov	r3, r0
	size_t n = 0;
    43ec:	2000      	movs	r0, #0

	while (*s != '\0') {
    43ee:	5c1a      	ldrb	r2, [r3, r0]
    43f0:	b902      	cbnz	r2, 43f4 <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    43f2:	4770      	bx	lr
		n++;
    43f4:	3001      	adds	r0, #1
    43f6:	e7fa      	b.n	43ee <strlen+0x4>

000043f8 <strnlen>:
 *
 * @return number of bytes in fixed-size string <s>
 */

size_t strnlen(const char *s, size_t maxlen)
{
    43f8:	4603      	mov	r3, r0
	size_t n = 0;
    43fa:	2000      	movs	r0, #0

	while (*s != '\0' && n < maxlen) {
    43fc:	5c1a      	ldrb	r2, [r3, r0]
    43fe:	b10a      	cbz	r2, 4404 <strnlen+0xc>
    4400:	4288      	cmp	r0, r1
    4402:	d100      	bne.n	4406 <strnlen+0xe>
		s++;
		n++;
	}

	return n;
}
    4404:	4770      	bx	lr
		n++;
    4406:	3001      	adds	r0, #1
    4408:	e7f8      	b.n	43fc <strnlen+0x4>

0000440a <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n)
{
    440a:	b510      	push	{r4, lr}
    440c:	1e43      	subs	r3, r0, #1
    440e:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
    4410:	4291      	cmp	r1, r2
    4412:	d100      	bne.n	4416 <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    4414:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
    4416:	f811 4b01 	ldrb.w	r4, [r1], #1
    441a:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    441e:	e7f7      	b.n	4410 <memcpy+0x6>

00004420 <memset>:
void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
	unsigned char c_byte = (unsigned char)c;
    4420:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
    4422:	4402      	add	r2, r0
	unsigned char *d_byte = (unsigned char *)buf;
    4424:	4603      	mov	r3, r0
	while (n > 0) {
    4426:	4293      	cmp	r3, r2
    4428:	d100      	bne.n	442c <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    442a:	4770      	bx	lr
		*(d_byte++) = c_byte;
    442c:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    4430:	e7f9      	b.n	4426 <memset+0x6>

00004432 <pm_state_set>:
/* Invoke Low Power/System Off specific Tasks */
__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
{
	ARG_UNUSED(substate_id);

	switch (state) {
    4432:	2806      	cmp	r0, #6
    4434:	d108      	bne.n	4448 <pm_state_set+0x16>
    p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
    4436:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    443a:	2201      	movs	r2, #1
    443c:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  __ASM volatile ("dsb 0xF":::"memory");
    4440:	f3bf 8f4f 	dsb	sy
        __WFE();
    4444:	bf20      	wfe
    while (true)
    4446:	e7fd      	b.n	4444 <pm_state_set+0x12>
		break;
	default:
		LOG_DBG("Unsupported power state %u", state);
		break;
	}
}
    4448:	4770      	bx	lr

0000444a <pm_state_exit_post_ops>:
    444a:	2300      	movs	r3, #0
    444c:	f383 8811 	msr	BASEPRI, r3
    4450:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
    4454:	4770      	bx	lr

00004456 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    4456:	6903      	ldr	r3, [r0, #16]
    4458:	b2c9      	uxtb	r1, r1
    445a:	220c      	movs	r2, #12
    445c:	fb01 3302 	mla	r3, r1, r2, r3
    4460:	6c18      	ldr	r0, [r3, #64]	; 0x40
}
    4462:	f000 0007 	and.w	r0, r0, #7
    4466:	4770      	bx	lr

00004468 <set_on_state>:
	__asm__ volatile(
    4468:	f04f 0320 	mov.w	r3, #32
    446c:	f3ef 8211 	mrs	r2, BASEPRI
    4470:	f383 8812 	msr	BASEPRI_MAX, r3
    4474:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    4478:	6803      	ldr	r3, [r0, #0]
    447a:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    447e:	f043 0302 	orr.w	r3, r3, #2
    4482:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    4484:	f382 8811 	msr	BASEPRI, r2
    4488:	f3bf 8f6f 	isb	sy
}
    448c:	4770      	bx	lr

0000448e <stop>:
{
    448e:	b570      	push	{r4, r5, r6, lr}
    4490:	b2c9      	uxtb	r1, r1
	struct nrf_clock_control_data *data = dev->data;
    4492:	6903      	ldr	r3, [r0, #16]
	__asm__ volatile(
    4494:	f04f 0420 	mov.w	r4, #32
    4498:	f3ef 8511 	mrs	r5, BASEPRI
    449c:	f384 8812 	msr	BASEPRI_MAX, r4
    44a0:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    44a4:	260c      	movs	r6, #12
    44a6:	fb06 3401 	mla	r4, r6, r1, r3
    44aa:	6c24      	ldr	r4, [r4, #64]	; 0x40
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    44ac:	f014 04c0 	ands.w	r4, r4, #192	; 0xc0
    44b0:	d008      	beq.n	44c4 <stop+0x36>
    44b2:	42a2      	cmp	r2, r4
    44b4:	d006      	beq.n	44c4 <stop+0x36>
	__asm__ volatile(
    44b6:	f385 8811 	msr	BASEPRI, r5
    44ba:	f3bf 8f6f 	isb	sy
		err = -EPERM;
    44be:	f04f 30ff 	mov.w	r0, #4294967295
}
    44c2:	bd70      	pop	{r4, r5, r6, pc}
		*flags = CLOCK_CONTROL_STATUS_OFF;
    44c4:	fb06 3301 	mla	r3, r6, r1, r3
    44c8:	2201      	movs	r2, #1
    44ca:	641a      	str	r2, [r3, #64]	; 0x40
    44cc:	f385 8811 	msr	BASEPRI, r5
    44d0:	f3bf 8f6f 	isb	sy
	get_sub_config(dev, type)->stop();
    44d4:	6843      	ldr	r3, [r0, #4]
    44d6:	eb03 03c1 	add.w	r3, r3, r1, lsl #3
    44da:	685b      	ldr	r3, [r3, #4]
    44dc:	4798      	blx	r3
	return 0;
    44de:	2000      	movs	r0, #0
    44e0:	e7ef      	b.n	44c2 <stop+0x34>

000044e2 <api_stop>:
	return stop(dev, subsys, CTX_API);
    44e2:	2280      	movs	r2, #128	; 0x80
    44e4:	f7ff bfd3 	b.w	448e <stop>

000044e8 <async_start>:
{
    44e8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    44ea:	9f06      	ldr	r7, [sp, #24]
	struct nrf_clock_control_data *data = dev->data;
    44ec:	6904      	ldr	r4, [r0, #16]
	return &data->subsys[type];
    44ee:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    44f0:	f04f 0520 	mov.w	r5, #32
    44f4:	f3ef 8611 	mrs	r6, BASEPRI
    44f8:	f385 8812 	msr	BASEPRI_MAX, r5
    44fc:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    4500:	250c      	movs	r5, #12
    4502:	fb05 4401 	mla	r4, r5, r1, r4
    4506:	6c25      	ldr	r5, [r4, #64]	; 0x40
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    4508:	f005 0c07 	and.w	ip, r5, #7
    450c:	f1bc 0f01 	cmp.w	ip, #1
    4510:	d10c      	bne.n	452c <async_start+0x44>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    4512:	6427      	str	r7, [r4, #64]	; 0x40
	__asm__ volatile(
    4514:	f386 8811 	msr	BASEPRI, r6
    4518:	f3bf 8f6f 	isb	sy
	subdata->user_data = user_data;
    451c:	e9c4 230e 	strd	r2, r3, [r4, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    4520:	6843      	ldr	r3, [r0, #4]
    4522:	f853 3031 	ldr.w	r3, [r3, r1, lsl #3]
    4526:	4798      	blx	r3
	return 0;
    4528:	2000      	movs	r0, #0
}
    452a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    452c:	f005 05c0 	and.w	r5, r5, #192	; 0xc0
	} else if (current_ctx != ctx) {
    4530:	42af      	cmp	r7, r5
    4532:	f386 8811 	msr	BASEPRI, r6
    4536:	f3bf 8f6f 	isb	sy
		err = -EALREADY;
    453a:	bf0c      	ite	eq
    453c:	f06f 0077 	mvneq.w	r0, #119	; 0x77
		err = -EPERM;
    4540:	f04f 30ff 	movne.w	r0, #4294967295
    4544:	e7f1      	b.n	452a <async_start+0x42>

00004546 <api_start>:
{
    4546:	b513      	push	{r0, r1, r4, lr}
	return async_start(dev, subsys, cb, user_data, CTX_API);
    4548:	2480      	movs	r4, #128	; 0x80
    454a:	9400      	str	r4, [sp, #0]
    454c:	f7ff ffcc 	bl	44e8 <async_start>
}
    4550:	b002      	add	sp, #8
    4552:	bd10      	pop	{r4, pc}

00004554 <onoff_started_callback>:
{
    4554:	b410      	push	{r4}
	return &data->mgr[type];
    4556:	6900      	ldr	r0, [r0, #16]
    4558:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    455a:	241c      	movs	r4, #28
    455c:	fb03 0004 	mla	r0, r3, r4, r0
    4560:	2100      	movs	r1, #0
}
    4562:	bc10      	pop	{r4}
	notify(mgr, 0);
    4564:	4710      	bx	r2

00004566 <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    4566:	2000      	movs	r0, #0
    4568:	f000 ba11 	b.w	498e <nrfx_clock_stop>

0000456c <blocking_start_callback>:
{
    456c:	4610      	mov	r0, r2
	z_impl_k_sem_give(sem);
    456e:	f7ff b90f 	b.w	3790 <z_impl_k_sem_give>

00004572 <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    4572:	6843      	ldr	r3, [r0, #4]
    4574:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    4576:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    457a:	600b      	str	r3, [r1, #0]
}
    457c:	2000      	movs	r0, #0
    457e:	4770      	bx	lr

00004580 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    4580:	6843      	ldr	r3, [r0, #4]
    4582:	685b      	ldr	r3, [r3, #4]
	const uint32_t set_mask = value & mask;
    4584:	ea02 0001 	and.w	r0, r2, r1
	const uint32_t clear_mask = (~set_mask) & mask;
    4588:	ea21 0102 	bic.w	r1, r1, r2
    p_reg->OUTSET = set_mask;
    458c:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
    p_reg->OUTCLR = clr_mask;
    4590:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
}
    4594:	2000      	movs	r0, #0
    4596:	4770      	bx	lr

00004598 <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    4598:	6843      	ldr	r3, [r0, #4]
    459a:	685b      	ldr	r3, [r3, #4]
}
    459c:	2000      	movs	r0, #0
    p_reg->OUTSET = set_mask;
    459e:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
    45a2:	4770      	bx	lr

000045a4 <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    45a4:	6843      	ldr	r3, [r0, #4]
    45a6:	685b      	ldr	r3, [r3, #4]
}
    45a8:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    45aa:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
    45ae:	4770      	bx	lr

000045b0 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    45b0:	6843      	ldr	r3, [r0, #4]
    45b2:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    45b4:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	const uint32_t set_mask = value & mask;
    45b8:	ea21 0003 	bic.w	r0, r1, r3
	const uint32_t clear_mask = (~value) & mask;
    45bc:	400b      	ands	r3, r1
    p_reg->OUTSET = set_mask;
    45be:	f8c2 0508 	str.w	r0, [r2, #1288]	; 0x508
    p_reg->OUTCLR = clr_mask;
    45c2:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
}
    45c6:	2000      	movs	r0, #0
    45c8:	4770      	bx	lr

000045ca <gpio_nrfx_manage_callback>:
{
    45ca:	b510      	push	{r4, lr}
	return port->data;
    45cc:	6903      	ldr	r3, [r0, #16]
	return list->head;
    45ce:	6858      	ldr	r0, [r3, #4]
	if (!sys_slist_is_empty(callbacks)) {
    45d0:	b1f8      	cbz	r0, 4612 <gpio_nrfx_manage_callback+0x48>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    45d2:	4288      	cmp	r0, r1
    45d4:	d119      	bne.n	460a <gpio_nrfx_manage_callback+0x40>
Z_GENLIST_REMOVE(slist, snode)
    45d6:	689c      	ldr	r4, [r3, #8]
	return node->next;
    45d8:	6808      	ldr	r0, [r1, #0]
	list->head = node;
    45da:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    45dc:	42a1      	cmp	r1, r4
    45de:	d100      	bne.n	45e2 <gpio_nrfx_manage_callback+0x18>
	list->tail = node;
    45e0:	6098      	str	r0, [r3, #8]
	parent->next = child;
    45e2:	2000      	movs	r0, #0
    45e4:	6008      	str	r0, [r1, #0]
	if (set) {
    45e6:	b12a      	cbz	r2, 45f4 <gpio_nrfx_manage_callback+0x2a>
	return list->head;
    45e8:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
    45ea:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
    45ec:	689a      	ldr	r2, [r3, #8]
	list->head = node;
    45ee:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    45f0:	b902      	cbnz	r2, 45f4 <gpio_nrfx_manage_callback+0x2a>
	list->tail = node;
    45f2:	6099      	str	r1, [r3, #8]
	return 0;
    45f4:	2000      	movs	r0, #0
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    45f6:	e010      	b.n	461a <gpio_nrfx_manage_callback+0x50>
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    45f8:	4281      	cmp	r1, r0
    45fa:	d106      	bne.n	460a <gpio_nrfx_manage_callback+0x40>
	return node->next;
    45fc:	6808      	ldr	r0, [r1, #0]
	parent->next = child;
    45fe:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
    4600:	6898      	ldr	r0, [r3, #8]
    4602:	4281      	cmp	r1, r0
    4604:	d1ed      	bne.n	45e2 <gpio_nrfx_manage_callback+0x18>
	list->tail = node;
    4606:	609c      	str	r4, [r3, #8]
}
    4608:	e7eb      	b.n	45e2 <gpio_nrfx_manage_callback+0x18>
	return node->next;
    460a:	4604      	mov	r4, r0
    460c:	6800      	ldr	r0, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    460e:	2800      	cmp	r0, #0
    4610:	d1f2      	bne.n	45f8 <gpio_nrfx_manage_callback+0x2e>
			if (!set) {
    4612:	2a00      	cmp	r2, #0
    4614:	d1e8      	bne.n	45e8 <gpio_nrfx_manage_callback+0x1e>
				return -EINVAL;
    4616:	f06f 0015 	mvn.w	r0, #21
}
    461a:	bd10      	pop	{r4, pc}

0000461c <pinctrl_lookup_state>:

#include <zephyr/drivers/pinctrl.h>

int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
			 const struct pinctrl_state **state)
{
    461c:	b530      	push	{r4, r5, lr}
	*state = &config->states[0];
    461e:	6843      	ldr	r3, [r0, #4]
    4620:	6013      	str	r3, [r2, #0]
	while (*state < &config->states[config->state_cnt]) {
    4622:	7a05      	ldrb	r5, [r0, #8]
    4624:	6844      	ldr	r4, [r0, #4]
    4626:	eb04 04c5 	add.w	r4, r4, r5, lsl #3
    462a:	42a3      	cmp	r3, r4
    462c:	d302      	bcc.n	4634 <pinctrl_lookup_state+0x18>
		}

		(*state)++;
	}

	return -ENOENT;
    462e:	f06f 0001 	mvn.w	r0, #1
}
    4632:	bd30      	pop	{r4, r5, pc}
		if (id == (*state)->id) {
    4634:	795c      	ldrb	r4, [r3, #5]
    4636:	428c      	cmp	r4, r1
    4638:	d001      	beq.n	463e <pinctrl_lookup_state+0x22>
		(*state)++;
    463a:	3308      	adds	r3, #8
    463c:	e7f0      	b.n	4620 <pinctrl_lookup_state+0x4>
			return 0;
    463e:	2000      	movs	r0, #0
    4640:	e7f7      	b.n	4632 <pinctrl_lookup_state+0x16>

00004642 <pinctrl_configure_pins>:
#define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
#endif

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
			   uintptr_t reg)
{
    4642:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4646:	eb00 0181 	add.w	r1, r0, r1, lsl #2
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    464a:	2701      	movs	r7, #1
    p_reg->OUTCLR = clr_mask;
    464c:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    4650:	4281      	cmp	r1, r0
    4652:	d102      	bne.n	465a <pinctrl_configure_pins+0x18>
			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
				     drive, NRF_GPIO_PIN_NOSENSE);
		}
	}

	return 0;
    4654:	2000      	movs	r0, #0
}
    4656:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    465a:	6805      	ldr	r5, [r0, #0]
		uint32_t pin = NRF_GET_PIN(pins[i]);
    465c:	f005 047f 	and.w	r4, r5, #127	; 0x7f
			pin = 0xFFFFFFFFU;
    4660:	2c7f      	cmp	r4, #127	; 0x7f
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    4662:	f3c5 2343 	ubfx	r3, r5, #9, #4
		switch (NRF_GET_FUN(pins[i])) {
    4666:	ea4f 4515 	mov.w	r5, r5, lsr #16
			pin = 0xFFFFFFFFU;
    466a:	bf08      	it	eq
    466c:	f04f 34ff 	moveq.w	r4, #4294967295
		switch (NRF_GET_FUN(pins[i])) {
    4670:	2d05      	cmp	r5, #5
    4672:	d00f      	beq.n	4694 <pinctrl_configure_pins+0x52>
    4674:	2d06      	cmp	r5, #6
    4676:	d011      	beq.n	469c <pinctrl_configure_pins+0x5a>
    4678:	2d04      	cmp	r5, #4
    467a:	d12f      	bne.n	46dc <pinctrl_configure_pins+0x9a>
			NRF_PSEL_SPIM(reg, SCK) = pin;
    467c:	f8c2 4508 	str.w	r4, [r2, #1288]	; 0x508
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    4680:	2500      	movs	r5, #0
    *p_pin = pin_number & 0x1F;
    4682:	f004 0c1f 	and.w	ip, r4, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    4686:	fa07 fc0c 	lsl.w	ip, r7, ip
    p_reg->OUTCLR = clr_mask;
    468a:	f8c6 c50c 	str.w	ip, [r6, #1292]	; 0x50c
}
    468e:	f04f 0c01 	mov.w	ip, #1
    4692:	e007      	b.n	46a4 <pinctrl_configure_pins+0x62>
			NRF_PSEL_SPIM(reg, MOSI) = pin;
    4694:	f8c2 450c 	str.w	r4, [r2, #1292]	; 0x50c
			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    4698:	2501      	movs	r5, #1
    469a:	e7f2      	b.n	4682 <pinctrl_configure_pins+0x40>
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    469c:	2500      	movs	r5, #0
			NRF_PSEL_SPIM(reg, MISO) = pin;
    469e:	f8c2 4510 	str.w	r4, [r2, #1296]	; 0x510
			dir = NRF_GPIO_PIN_DIR_INPUT;
    46a2:	46ac      	mov	ip, r5
			if (NRF_GET_LP(pins[i]) == NRF_LP_ENABLE) {
    46a4:	f850 eb04 	ldr.w	lr, [r0], #4
    46a8:	f40e 5800 	and.w	r8, lr, #8192	; 0x2000
				input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    46ac:	f1b8 0f00 	cmp.w	r8, #0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    46b0:	f3ce 1ec1 	ubfx	lr, lr, #7, #2
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    46b4:	ea4f 2303 	mov.w	r3, r3, lsl #8
    46b8:	bf18      	it	ne
    46ba:	f04f 0c00 	movne.w	ip, #0
    *p_pin = pin_number & 0x1F;
    46be:	f004 041f 	and.w	r4, r4, #31
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    46c2:	ea43 038e 	orr.w	r3, r3, lr, lsl #2
    46c6:	bf18      	it	ne
    46c8:	2501      	movne	r5, #1
    46ca:	ea43 030c 	orr.w	r3, r3, ip
    reg->PIN_CNF[pin_number] = cnf;
    46ce:	f504 74e0 	add.w	r4, r4, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    46d2:	ea43 0345 	orr.w	r3, r3, r5, lsl #1
    reg->PIN_CNF[pin_number] = cnf;
    46d6:	f846 3024 	str.w	r3, [r6, r4, lsl #2]
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    46da:	e7b9      	b.n	4650 <pinctrl_configure_pins+0xe>
		switch (NRF_GET_FUN(pins[i])) {
    46dc:	f06f 0085 	mvn.w	r0, #133	; 0x85
    46e0:	e7b9      	b.n	4656 <pinctrl_configure_pins+0x14>

000046e2 <irq_connect0>:
		      &spi_##idx##z_config,				       \
		      POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,		       \
		      &spi_nrfx_driver_api)

#ifdef CONFIG_SPI_0_NRF_SPI
SPI_NRFX_SPI_DEFINE(0);
    46e2:	2200      	movs	r2, #0
    46e4:	2101      	movs	r1, #1
    46e6:	2003      	movs	r0, #3
    46e8:	f7fc bce6 	b.w	10b8 <z_arm_irq_priority_set>

000046ec <irq_connect1>:
#endif

#ifdef CONFIG_SPI_1_NRF_SPI
SPI_NRFX_SPI_DEFINE(1);
    46ec:	2200      	movs	r2, #0
    46ee:	2101      	movs	r1, #1
    46f0:	2004      	movs	r0, #4
    46f2:	f7fc bce1 	b.w	10b8 <z_arm_irq_priority_set>

000046f6 <spi_context_get_next_buf.constprop.0>:
static inline void *spi_context_get_next_buf(const struct spi_buf **current,
    46f6:	b510      	push	{r4, lr}
	while (*count) {
    46f8:	680b      	ldr	r3, [r1, #0]
    46fa:	b913      	cbnz	r3, 4702 <spi_context_get_next_buf.constprop.0+0xc>
	*buf_len = 0;
    46fc:	6013      	str	r3, [r2, #0]
	return NULL;
    46fe:	4618      	mov	r0, r3
    4700:	e005      	b.n	470e <spi_context_get_next_buf.constprop.0+0x18>
		if (((*current)->len / dfs) != 0) {
    4702:	6803      	ldr	r3, [r0, #0]
    4704:	685c      	ldr	r4, [r3, #4]
    4706:	b11c      	cbz	r4, 4710 <spi_context_get_next_buf.constprop.0+0x1a>
			*buf_len = (*current)->len / dfs;
    4708:	6014      	str	r4, [r2, #0]
			return (*current)->buf;
    470a:	6803      	ldr	r3, [r0, #0]
    470c:	6818      	ldr	r0, [r3, #0]
}
    470e:	bd10      	pop	{r4, pc}
		++(*current);
    4710:	3308      	adds	r3, #8
    4712:	6003      	str	r3, [r0, #0]
		--(*count);
    4714:	680b      	ldr	r3, [r1, #0]
    4716:	3b01      	subs	r3, #1
    4718:	600b      	str	r3, [r1, #0]
    471a:	e7ed      	b.n	46f8 <spi_context_get_next_buf.constprop.0+0x2>

0000471c <gpio_pin_set_dt.isra.0>:
 *
 * @param spec GPIO specification from devicetree
 * @param value Value assigned to the pin.
 * @return a value from gpio_pin_set()
 */
static inline int gpio_pin_set_dt(const struct gpio_dt_spec *spec, int value)
    471c:	4603      	mov	r3, r0
    471e:	460a      	mov	r2, r1
{
	return gpio_pin_set(spec->port, spec->pin, value);
    4720:	6800      	ldr	r0, [r0, #0]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    4722:	7919      	ldrb	r1, [r3, #4]
    4724:	2301      	movs	r3, #1
    4726:	fa03 f101 	lsl.w	r1, r3, r1
    472a:	6903      	ldr	r3, [r0, #16]
    472c:	681b      	ldr	r3, [r3, #0]
    472e:	4219      	tst	r1, r3
		value = (value != 0) ? 0 : 1;
    4730:	bf18      	it	ne
    4732:	f082 0201 	eorne.w	r2, r2, #1
	if (value != 0)	{
    4736:	b112      	cbz	r2, 473e <gpio_pin_set_dt.isra.0+0x22>
	return api->port_set_bits_raw(port, pins);
    4738:	6883      	ldr	r3, [r0, #8]
    473a:	68db      	ldr	r3, [r3, #12]
	return api->port_clear_bits_raw(port, pins);
    473c:	4718      	bx	r3
    473e:	6883      	ldr	r3, [r0, #8]
    4740:	691b      	ldr	r3, [r3, #16]
    4742:	e7fb      	b.n	473c <gpio_pin_set_dt.isra.0+0x20>

00004744 <_spi_context_cs_control>:
{
    4744:	b538      	push	{r3, r4, r5, lr}
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio.port) {
    4746:	6803      	ldr	r3, [r0, #0]
{
    4748:	4604      	mov	r4, r0
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio.port) {
    474a:	b1e3      	cbz	r3, 4786 <_spi_context_cs_control+0x42>
    474c:	6898      	ldr	r0, [r3, #8]
    474e:	b1d0      	cbz	r0, 4786 <_spi_context_cs_control+0x42>
    4750:	6805      	ldr	r5, [r0, #0]
    4752:	b1c5      	cbz	r5, 4786 <_spi_context_cs_control+0x42>
		if (on) {
    4754:	b149      	cbz	r1, 476a <_spi_context_cs_control+0x26>
			gpio_pin_set_dt(&ctx->config->cs->gpio, 1);
    4756:	2101      	movs	r1, #1
    4758:	f7ff ffe0 	bl	471c <gpio_pin_set_dt.isra.0>
			k_busy_wait(ctx->config->cs->delay);
    475c:	6823      	ldr	r3, [r4, #0]
    475e:	689b      	ldr	r3, [r3, #8]
    4760:	6898      	ldr	r0, [r3, #8]
}
    4762:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_impl_k_busy_wait(usec_to_wait);
    4766:	f000 ba82 	b.w	4c6e <z_impl_k_busy_wait>
			if (!force_off &&
    476a:	b912      	cbnz	r2, 4772 <_spi_context_cs_control+0x2e>
    476c:	889b      	ldrh	r3, [r3, #4]
    476e:	04db      	lsls	r3, r3, #19
    4770:	d409      	bmi.n	4786 <_spi_context_cs_control+0x42>
			k_busy_wait(ctx->config->cs->delay);
    4772:	6880      	ldr	r0, [r0, #8]
    4774:	f000 fa7b 	bl	4c6e <z_impl_k_busy_wait>
			gpio_pin_set_dt(&ctx->config->cs->gpio, 0);
    4778:	6823      	ldr	r3, [r4, #0]
    477a:	2100      	movs	r1, #0
    477c:	6898      	ldr	r0, [r3, #8]
}
    477e:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
			gpio_pin_set_dt(&ctx->config->cs->gpio, 0);
    4782:	f7ff bfcb 	b.w	471c <gpio_pin_set_dt.isra.0>
}
    4786:	bd38      	pop	{r3, r4, r5, pc}

00004788 <spi_context_unlock_unconditionally>:
{
    4788:	b510      	push	{r4, lr}
	_spi_context_cs_control(ctx, false, true);
    478a:	2201      	movs	r2, #1
    478c:	2100      	movs	r1, #0
{
    478e:	4604      	mov	r4, r0
	_spi_context_cs_control(ctx, false, true);
    4790:	f7ff ffd8 	bl	4744 <_spi_context_cs_control>
	if (!k_sem_count_get(&ctx->lock)) {
    4794:	69a3      	ldr	r3, [r4, #24]
    4796:	b933      	cbnz	r3, 47a6 <spi_context_unlock_unconditionally+0x1e>
		ctx->owner = NULL;
    4798:	6063      	str	r3, [r4, #4]
	z_impl_k_sem_give(sem);
    479a:	f104 0010 	add.w	r0, r4, #16
}
    479e:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    47a2:	f7fe bff5 	b.w	3790 <z_impl_k_sem_give>
    47a6:	bd10      	pop	{r4, pc}

000047a8 <spi_nrfx_release>:
{
    47a8:	b510      	push	{r4, lr}
	struct spi_nrfx_data *dev_data = dev->data;
    47aa:	6900      	ldr	r0, [r0, #16]
	if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
    47ac:	6803      	ldr	r3, [r0, #0]
    47ae:	428b      	cmp	r3, r1
    47b0:	d106      	bne.n	47c0 <spi_nrfx_release+0x18>
	if (dev_data->busy) {
    47b2:	f890 405c 	ldrb.w	r4, [r0, #92]	; 0x5c
    47b6:	b934      	cbnz	r4, 47c6 <spi_nrfx_release+0x1e>
	spi_context_unlock_unconditionally(&dev_data->ctx);
    47b8:	f7ff ffe6 	bl	4788 <spi_context_unlock_unconditionally>
	return 0;
    47bc:	4620      	mov	r0, r4
}
    47be:	bd10      	pop	{r4, pc}
		return -EINVAL;
    47c0:	f06f 0015 	mvn.w	r0, #21
    47c4:	e7fb      	b.n	47be <spi_nrfx_release+0x16>
		return -EBUSY;
    47c6:	f06f 000f 	mvn.w	r0, #15
    47ca:	e7f8      	b.n	47be <spi_nrfx_release+0x16>

000047cc <spi_nrfx_init>:
{
    47cc:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
	const struct spi_nrfx_config *dev_config = dev->config;
    47d0:	6844      	ldr	r4, [r0, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    47d2:	6905      	ldr	r5, [r0, #16]
	err = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
    47d4:	6a26      	ldr	r6, [r4, #32]
				      uint8_t id)
{
	int ret;
	const struct pinctrl_state *state;

	ret = pinctrl_lookup_state(config, id, &state);
    47d6:	aa01      	add	r2, sp, #4
    47d8:	2100      	movs	r1, #0
    47da:	4630      	mov	r0, r6
    47dc:	f7ff ff1e 	bl	461c <pinctrl_lookup_state>
	if (ret < 0) {
    47e0:	2800      	cmp	r0, #0
    47e2:	db43      	blt.n	486c <spi_nrfx_init+0xa0>
		return ret;
	}

	return pinctrl_apply_state_direct(config, state);
    47e4:	9b01      	ldr	r3, [sp, #4]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    47e6:	6832      	ldr	r2, [r6, #0]
    47e8:	7919      	ldrb	r1, [r3, #4]
    47ea:	6818      	ldr	r0, [r3, #0]
    47ec:	f7ff ff29 	bl	4642 <pinctrl_configure_pins>
	if (err < 0) {
    47f0:	2800      	cmp	r0, #0
    47f2:	db3b      	blt.n	486c <spi_nrfx_init+0xa0>
	dev_config->irq_connect();
    47f4:	69e3      	ldr	r3, [r4, #28]
    47f6:	4798      	blx	r3
	for (cs_gpio = ctx->cs_gpios; cs_gpio < &ctx->cs_gpios[ctx->num_cs_gpios]; cs_gpio++) {
    47f8:	68ac      	ldr	r4, [r5, #8]
		data->invert |= (gpio_port_pins_t)BIT(pin);
    47fa:	2601      	movs	r6, #1
    47fc:	3408      	adds	r4, #8
    47fe:	e9d5 3202 	ldrd	r3, r2, [r5, #8]
    4802:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
    4806:	f1a4 0208 	sub.w	r2, r4, #8
    480a:	4293      	cmp	r3, r2
    480c:	d804      	bhi.n	4818 <spi_nrfx_init+0x4c>
	spi_context_unlock_unconditionally(&dev_data->ctx);
    480e:	4628      	mov	r0, r5
    4810:	f7ff ffba 	bl	4788 <spi_context_unlock_unconditionally>
	return 0;
    4814:	2000      	movs	r0, #0
	return 0;
    4816:	e029      	b.n	486c <spi_nrfx_init+0xa0>
		if (!device_is_ready(cs_gpio->port)) {
    4818:	f854 0c08 	ldr.w	r0, [r4, #-8]
    481c:	f000 f924 	bl	4a68 <z_device_is_ready>
    4820:	b338      	cbz	r0, 4872 <spi_nrfx_init+0xa6>
	return gpio_pin_configure(spec->port,
    4822:	f854 0c08 	ldr.w	r0, [r4, #-8]
				  spec->pin,
    4826:	f814 1c04 	ldrb.w	r1, [r4, #-4]
				  spec->dt_flags | extra_flags);
    482a:	f834 3c02 	ldrh.w	r3, [r4, #-2]
	struct gpio_driver_data *data =
    482e:	f8d0 c010 	ldr.w	ip, [r0, #16]
	const struct gpio_driver_api *api =
    4832:	f8d0 8008 	ldr.w	r8, [r0, #8]
		data->invert |= (gpio_port_pins_t)BIT(pin);
    4836:	f8dc 7000 	ldr.w	r7, [ip]
	    && ((flags & GPIO_ACTIVE_LOW) != 0)) {
    483a:	07da      	lsls	r2, r3, #31
	return gpio_pin_configure(spec->port,
    483c:	bf54      	ite	pl
    483e:	f443 13b0 	orrpl.w	r3, r3, #1441792	; 0x160000
		flags ^= GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH;
    4842:	f483 13d0 	eormi.w	r3, r3, #1703936	; 0x1a0000
	flags &= ~GPIO_OUTPUT_INIT_LOGICAL;
    4846:	f423 1280 	bic.w	r2, r3, #1048576	; 0x100000
		data->invert |= (gpio_port_pins_t)BIT(pin);
    484a:	fa06 fe01 	lsl.w	lr, r6, r1
	if ((flags & GPIO_ACTIVE_LOW) != 0) {
    484e:	07db      	lsls	r3, r3, #31
		data->invert |= (gpio_port_pins_t)BIT(pin);
    4850:	bf4c      	ite	mi
    4852:	ea4e 0707 	orrmi.w	r7, lr, r7
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
    4856:	ea27 070e 	bicpl.w	r7, r7, lr
    485a:	f8cc 7000 	str.w	r7, [ip]
	return api->pin_configure(port, pin, flags);
    485e:	f8d8 3000 	ldr.w	r3, [r8]
    4862:	4798      	blx	r3
		if (ret < 0) {
    4864:	2800      	cmp	r0, #0
    4866:	f104 0408 	add.w	r4, r4, #8
    486a:	dac8      	bge.n	47fe <spi_nrfx_init+0x32>
}
    486c:	b002      	add	sp, #8
    486e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
			return -ENODEV;
    4872:	f06f 0012 	mvn.w	r0, #18
	if (err < 0) {
    4876:	e7f9      	b.n	486c <spi_nrfx_init+0xa0>

00004878 <finish_transaction.isra.0>:
static void finish_transaction(const struct device *dev, int error)
    4878:	b538      	push	{r3, r4, r5, lr}
	_spi_context_cs_control(ctx, on, false);
    487a:	2200      	movs	r2, #0
    487c:	4604      	mov	r4, r0
    487e:	460d      	mov	r5, r1
    4880:	4611      	mov	r1, r2
    4882:	f7ff ff5f 	bl	4744 <_spi_context_cs_control>
	ctx->sync_status = status;
    4886:	6325      	str	r5, [r4, #48]	; 0x30
    4888:	f104 0020 	add.w	r0, r4, #32
    488c:	f7fe ff80 	bl	3790 <z_impl_k_sem_give>
	dev_data->busy = false;
    4890:	2300      	movs	r3, #0
    4892:	f884 305c 	strb.w	r3, [r4, #92]	; 0x5c
}
    4896:	bd38      	pop	{r3, r4, r5, pc}

00004898 <event_handler>:
{
    4898:	b538      	push	{r3, r4, r5, lr}
	if (p_event->type == NRFX_SPI_EVENT_DONE) {
    489a:	7803      	ldrb	r3, [r0, #0]
{
    489c:	460c      	mov	r4, r1
	if (p_event->type == NRFX_SPI_EVENT_DONE) {
    489e:	2b00      	cmp	r3, #0
    48a0:	d145      	bne.n	492e <event_handler+0x96>
		if (dev_data->chunk_len == 0) {
    48a2:	6d8d      	ldr	r5, [r1, #88]	; 0x58
    48a4:	b93d      	cbnz	r5, 48b6 <event_handler+0x1e>
			finish_transaction(dev_data->dev, -ETIMEDOUT);
    48a6:	6d4b      	ldr	r3, [r1, #84]	; 0x54
    48a8:	f06f 0173 	mvn.w	r1, #115	; 0x73
    48ac:	6918      	ldr	r0, [r3, #16]
}
    48ae:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
			finish_transaction(dev_data->dev, -ETIMEDOUT);
    48b2:	f7ff bfe1 	b.w	4878 <finish_transaction.isra.0>
	if (!ctx->tx_len) {
    48b6:	6c8b      	ldr	r3, [r1, #72]	; 0x48
    48b8:	b193      	cbz	r3, 48e0 <event_handler+0x48>
	if (len > ctx->tx_len) {
    48ba:	429d      	cmp	r5, r3
    48bc:	d810      	bhi.n	48e0 <event_handler+0x48>
	ctx->tx_len -= len;
    48be:	1b5b      	subs	r3, r3, r5
    48c0:	648b      	str	r3, [r1, #72]	; 0x48
	if (!ctx->tx_len) {
    48c2:	bb43      	cbnz	r3, 4916 <event_handler+0x7e>
		++ctx->current_tx;
    48c4:	6b4b      	ldr	r3, [r1, #52]	; 0x34
    48c6:	3308      	adds	r3, #8
    48c8:	634b      	str	r3, [r1, #52]	; 0x34
		--ctx->tx_count;
    48ca:	6b8b      	ldr	r3, [r1, #56]	; 0x38
    48cc:	3b01      	subs	r3, #1
    48ce:	638b      	str	r3, [r1, #56]	; 0x38
			spi_context_get_next_buf(&ctx->current_tx,
    48d0:	f101 0248 	add.w	r2, r1, #72	; 0x48
    48d4:	f104 0034 	add.w	r0, r4, #52	; 0x34
    48d8:	3138      	adds	r1, #56	; 0x38
    48da:	f7ff ff0c 	bl	46f6 <spi_context_get_next_buf.constprop.0>
		ctx->tx_buf = (const uint8_t *)
    48de:	6460      	str	r0, [r4, #68]	; 0x44
	if (!ctx->rx_len) {
    48e0:	6d23      	ldr	r3, [r4, #80]	; 0x50
    48e2:	b19b      	cbz	r3, 490c <event_handler+0x74>
	if (len > ctx->rx_len) {
    48e4:	429d      	cmp	r5, r3
    48e6:	d811      	bhi.n	490c <event_handler+0x74>
	ctx->rx_len -= len;
    48e8:	1b5b      	subs	r3, r3, r5
    48ea:	6523      	str	r3, [r4, #80]	; 0x50
	if (!ctx->rx_len) {
    48ec:	b9cb      	cbnz	r3, 4922 <event_handler+0x8a>
		++ctx->current_rx;
    48ee:	6be3      	ldr	r3, [r4, #60]	; 0x3c
    48f0:	3308      	adds	r3, #8
    48f2:	63e3      	str	r3, [r4, #60]	; 0x3c
		--ctx->rx_count;
    48f4:	6c23      	ldr	r3, [r4, #64]	; 0x40
    48f6:	3b01      	subs	r3, #1
    48f8:	6423      	str	r3, [r4, #64]	; 0x40
			spi_context_get_next_buf(&ctx->current_rx,
    48fa:	f104 0250 	add.w	r2, r4, #80	; 0x50
    48fe:	f104 0140 	add.w	r1, r4, #64	; 0x40
    4902:	f104 003c 	add.w	r0, r4, #60	; 0x3c
    4906:	f7ff fef6 	bl	46f6 <spi_context_get_next_buf.constprop.0>
		ctx->rx_buf = (uint8_t *)
    490a:	64e0      	str	r0, [r4, #76]	; 0x4c
		transfer_next_chunk(dev_data->dev);
    490c:	6d60      	ldr	r0, [r4, #84]	; 0x54
}
    490e:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
		transfer_next_chunk(dev_data->dev);
    4912:	f7fd ba65 	b.w	1de0 <transfer_next_chunk>
	} else if (ctx->tx_buf) {
    4916:	6c4b      	ldr	r3, [r1, #68]	; 0x44
    4918:	2b00      	cmp	r3, #0
    491a:	d0e1      	beq.n	48e0 <event_handler+0x48>
		ctx->tx_buf += dfs * len;
    491c:	442b      	add	r3, r5
    491e:	644b      	str	r3, [r1, #68]	; 0x44
    4920:	e7de      	b.n	48e0 <event_handler+0x48>
	} else if (ctx->rx_buf) {
    4922:	6ce3      	ldr	r3, [r4, #76]	; 0x4c
    4924:	2b00      	cmp	r3, #0
    4926:	d0f1      	beq.n	490c <event_handler+0x74>
		ctx->rx_buf += dfs * len;
    4928:	442b      	add	r3, r5
    492a:	64e3      	str	r3, [r4, #76]	; 0x4c
    492c:	e7ee      	b.n	490c <event_handler+0x74>
}
    492e:	bd38      	pop	{r3, r4, r5, pc}

00004930 <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
    4930:	4770      	bx	lr

00004932 <event_clear>:
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    4932:	f100 0350 	add.w	r3, r0, #80	; 0x50
    4936:	009b      	lsls	r3, r3, #2
    4938:	b29b      	uxth	r3, r3
    493a:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    493e:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    4942:	2200      	movs	r2, #0
    4944:	601a      	str	r2, [r3, #0]
    4946:	681b      	ldr	r3, [r3, #0]
}
    4948:	4770      	bx	lr

0000494a <k_sys_fatal_error_handler>:

extern void sys_arch_reboot(int type);

void k_sys_fatal_error_handler(unsigned int reason,
			       const z_arch_esf_t *esf)
{
    494a:	b508      	push	{r3, lr}

	LOG_PANIC();

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
		sys_arch_reboot(0);
    494c:	2000      	movs	r0, #0
    494e:	f7fc ff71 	bl	1834 <sys_arch_reboot>

00004952 <nrf52_errata_108>:
            if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF)
    4952:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    4956:	f8d3 0130 	ldr.w	r0, [r3, #304]	; 0x130
    495a:	1c42      	adds	r2, r0, #1
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    495c:	bf04      	itt	eq
    495e:	f04f 4370 	moveq.w	r3, #4026531840	; 0xf0000000
    4962:	f893 0fe0 	ldrbeq.w	r0, [r3, #4064]	; 0xfe0
}
    4966:	1f83      	subs	r3, r0, #6
    4968:	4258      	negs	r0, r3
    496a:	4158      	adcs	r0, r3
    496c:	4770      	bx	lr

0000496e <nrfx_isr>:
#include <zephyr/kernel.h>
#include <soc/nrfx_coredep.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    496e:	4700      	bx	r0

00004970 <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    4970:	f000 b97d 	b.w	4c6e <z_impl_k_busy_wait>

00004974 <nrfx_clock_enable>:
{
    4974:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    4976:	2000      	movs	r0, #0
    4978:	f7fc fb90 	bl	109c <arch_irq_is_enabled>
    497c:	b908      	cbnz	r0, 4982 <nrfx_clock_enable+0xe>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    497e:	f7fc fb6b 	bl	1058 <arch_irq_enable>
    p_reg->LFCLKSRC = (uint32_t)(source);
    4982:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4986:	2200      	movs	r2, #0
    4988:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    498c:	bd08      	pop	{r3, pc}

0000498e <nrfx_clock_stop>:
    clock_stop(domain);
    498e:	f7fd bf65 	b.w	285c <clock_stop>

00004992 <nrf_gpio_cfg_sense_set>:
    *p_pin = pin_number & 0x1F;
    4992:	f000 001f 	and.w	r0, r0, #31
    4996:	0080      	lsls	r0, r0, #2
    4998:	f100 40a0 	add.w	r0, r0, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number];
    499c:	f8d0 3700 	ldr.w	r3, [r0, #1792]	; 0x700
    cnf &= ~to_update;
    49a0:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    49a4:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
    reg->PIN_CNF[pin_number] = cnf;
    49a8:	f8c0 3700 	str.w	r3, [r0, #1792]	; 0x700
}
    49ac:	4770      	bx	lr

000049ae <transfer_byte>:
{
    49ae:	b537      	push	{r0, r1, r2, r4, r5, lr}
    return p_reg->RXD;
    49b0:	f8d0 3518 	ldr.w	r3, [r0, #1304]	; 0x518
    if (p_cb->bytes_transferred < p_cb->evt.xfer_desc.rx_length)
    49b4:	698a      	ldr	r2, [r1, #24]
    49b6:	b2db      	uxtb	r3, r3
    volatile uint8_t rx_data = nrf_spi_rxd_get(p_spi);
    49b8:	f88d 3007 	strb.w	r3, [sp, #7]
    if (p_cb->bytes_transferred < p_cb->evt.xfer_desc.rx_length)
    49bc:	6a0b      	ldr	r3, [r1, #32]
    49be:	4293      	cmp	r3, r2
        p_cb->evt.xfer_desc.p_rx_buffer[p_cb->bytes_transferred] = rx_data;
    49c0:	bf3e      	ittt	cc
    49c2:	694a      	ldrcc	r2, [r1, #20]
    49c4:	f89d 4007 	ldrbcc.w	r4, [sp, #7]
    49c8:	54d4      	strbcc	r4, [r2, r3]
    ++p_cb->bytes_transferred;
    49ca:	6a0b      	ldr	r3, [r1, #32]
    if (p_cb->abort)
    49cc:	f891 5024 	ldrb.w	r5, [r1, #36]	; 0x24
        if (bytes_used < p_cb->evt.xfer_desc.tx_length)
    49d0:	690c      	ldr	r4, [r1, #16]
    ++p_cb->bytes_transferred;
    49d2:	1c5a      	adds	r2, r3, #1
    49d4:	620a      	str	r2, [r1, #32]
    size_t bytes_used = p_cb->bytes_transferred + 1;
    49d6:	3302      	adds	r3, #2
    if (p_cb->abort)
    49d8:	b135      	cbz	r5, 49e8 <transfer_byte+0x3a>
        if (bytes_used < p_cb->evt.xfer_desc.tx_length)
    49da:	42a3      	cmp	r3, r4
        if (bytes_used < p_cb->evt.xfer_desc.rx_length)
    49dc:	698c      	ldr	r4, [r1, #24]
            p_cb->evt.xfer_desc.tx_length = bytes_used;
    49de:	bf38      	it	cc
    49e0:	610b      	strcc	r3, [r1, #16]
        if (bytes_used < p_cb->evt.xfer_desc.rx_length)
    49e2:	429c      	cmp	r4, r3
            p_cb->evt.xfer_desc.rx_length = bytes_used;
    49e4:	bf88      	it	hi
    49e6:	618b      	strhi	r3, [r1, #24]
    if (bytes_used < p_cb->evt.xfer_desc.tx_length)
    49e8:	690d      	ldr	r5, [r1, #16]
    49ea:	429d      	cmp	r5, r3
    49ec:	d905      	bls.n	49fa <transfer_byte+0x4c>
        nrf_spi_txd_set(p_spi, p_cb->evt.xfer_desc.p_tx_buffer[bytes_used]);
    49ee:	68ca      	ldr	r2, [r1, #12]
    p_reg->TXD = data;
    49f0:	5cd3      	ldrb	r3, [r2, r3]
    49f2:	f8c0 351c 	str.w	r3, [r0, #1308]	; 0x51c
    return (p_cb->bytes_transferred < p_cb->evt.xfer_desc.tx_length ||
    49f6:	2001      	movs	r0, #1
    49f8:	e00a      	b.n	4a10 <transfer_byte+0x62>
    else if (bytes_used < p_cb->evt.xfer_desc.rx_length)
    49fa:	698c      	ldr	r4, [r1, #24]
    49fc:	429c      	cmp	r4, r3
    49fe:	d901      	bls.n	4a04 <transfer_byte+0x56>
    4a00:	7fcb      	ldrb	r3, [r1, #31]
    4a02:	e7f6      	b.n	49f2 <transfer_byte+0x44>
    return (p_cb->bytes_transferred < p_cb->evt.xfer_desc.tx_length ||
    4a04:	42aa      	cmp	r2, r5
    4a06:	d3f6      	bcc.n	49f6 <transfer_byte+0x48>
    4a08:	42a2      	cmp	r2, r4
    4a0a:	bf2c      	ite	cs
    4a0c:	2000      	movcs	r0, #0
    4a0e:	2001      	movcc	r0, #1
}
    4a10:	b003      	add	sp, #12
    4a12:	bd30      	pop	{r4, r5, pc}

00004a14 <irq_handler>:
{
    4a14:	b510      	push	{r4, lr}
    4a16:	4603      	mov	r3, r0
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4a18:	2200      	movs	r2, #0
    4a1a:	f8c0 2108 	str.w	r2, [r0, #264]	; 0x108
    4a1e:	f8d3 3108 	ldr.w	r3, [r3, #264]	; 0x108
    4a22:	460c      	mov	r4, r1
    if (!transfer_byte(p_spi, p_cb))
    4a24:	f7ff ffc3 	bl	49ae <transfer_byte>
    4a28:	b9a8      	cbnz	r0, 4a56 <irq_handler+0x42>
    if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    4a2a:	7f8b      	ldrb	r3, [r1, #30]
    4a2c:	2bff      	cmp	r3, #255	; 0xff
    4a2e:	d008      	beq.n	4a42 <irq_handler+0x2e>
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    4a30:	2201      	movs	r2, #1
    *p_pin = pin_number & 0x1F;
    4a32:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    4a36:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->OUTSET = set_mask;
    4a3a:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    4a3e:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
    p_cb->transfer_in_progress = false;
    4a42:	2300      	movs	r3, #0
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    4a44:	4620      	mov	r0, r4
    p_cb->transfer_in_progress = false;
    4a46:	7763      	strb	r3, [r4, #29]
    p_cb->evt.type = NRFX_SPI_EVENT_DONE;
    4a48:	7223      	strb	r3, [r4, #8]
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    4a4a:	6861      	ldr	r1, [r4, #4]
    4a4c:	f850 3b08 	ldr.w	r3, [r0], #8
}
    4a50:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    4a54:	4718      	bx	r3
}
    4a56:	bd10      	pop	{r4, pc}

00004a58 <SEGGER_RTT_Init>:
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
  _DoInit();
    4a58:	f7fe bcca 	b.w	33f0 <_DoInit>

00004a5c <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(void)
{
    4a5c:	b508      	push	{r3, lr}

	SEGGER_RTT_Init();
    4a5e:	f7ff fffb 	bl	4a58 <SEGGER_RTT_Init>

	return 0;
}
    4a62:	2000      	movs	r0, #0
    4a64:	bd08      	pop	{r3, pc}

00004a66 <z_device_state_init>:

	while (dev < __device_end) {
		z_object_init(dev);
		++dev;
	}
}
    4a66:	4770      	bx	lr

00004a68 <z_device_is_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    4a68:	b140      	cbz	r0, 4a7c <z_device_is_ready+0x14>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    4a6a:	68c3      	ldr	r3, [r0, #12]
    4a6c:	7858      	ldrb	r0, [r3, #1]
    4a6e:	f010 0001 	ands.w	r0, r0, #1
    4a72:	bf1e      	ittt	ne
    4a74:	7818      	ldrbne	r0, [r3, #0]
    4a76:	fab0 f080 	clzne	r0, r0
    4a7a:	0940      	lsrne	r0, r0, #5
}
    4a7c:	4770      	bx	lr

00004a7e <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    4a7e:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4a80:	4605      	mov	r5, r0
    4a82:	460e      	mov	r6, r1
	__asm__ volatile(
    4a84:	f04f 0320 	mov.w	r3, #32
    4a88:	f3ef 8711 	mrs	r7, BASEPRI
    4a8c:	f383 8812 	msr	BASEPRI_MAX, r3
    4a90:	f3bf 8f6f 	isb	sy
	return z_impl_z_current_get();
    4a94:	f7ff f978 	bl	3d88 <z_impl_z_current_get>

#ifndef CONFIG_XTENSA
	coredump(reason, esf, thread);
#endif

	k_sys_fatal_error_handler(reason, esf);
    4a98:	4631      	mov	r1, r6
    4a9a:	4604      	mov	r4, r0
    4a9c:	4628      	mov	r0, r5
    4a9e:	f7ff ff54 	bl	494a <k_sys_fatal_error_handler>
	__asm__ volatile(
    4aa2:	f387 8811 	msr	BASEPRI, r7
    4aa6:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    4aaa:	4620      	mov	r0, r4
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    4aac:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    4ab0:	f7fc bdce 	b.w	1650 <z_impl_k_thread_abort>

00004ab4 <z_early_memset>:
	(void) memset(dst, c, n);
    4ab4:	f7ff bcb4 	b.w	4420 <memset>

00004ab8 <z_early_memcpy>:
	(void) memcpy(dst, src, n);
    4ab8:	f7ff bca7 	b.w	440a <memcpy>

00004abc <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    4abc:	f3ef 8005 	mrs	r0, IPSR
}
    4ac0:	3800      	subs	r0, #0
    4ac2:	bf18      	it	ne
    4ac4:	2001      	movne	r0, #1
    4ac6:	4770      	bx	lr

00004ac8 <z_pm_save_idle_exit>:
{
    4ac8:	b508      	push	{r3, lr}
	pm_system_resume();
    4aca:	f7fc f99b 	bl	e04 <pm_system_resume>
}
    4ace:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	sys_clock_idle_exit();
    4ad2:	f7ff bf2d 	b.w	4930 <sys_clock_idle_exit>

00004ad6 <sys_dlist_remove>:
	sys_dnode_t *const next = node->next;
    4ad6:	e9d0 3200 	ldrd	r3, r2, [r0]
	prev->next = next;
    4ada:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    4adc:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    4ade:	2300      	movs	r3, #0
	node->prev = NULL;
    4ae0:	e9c0 3300 	strd	r3, r3, [r0]
	sys_dnode_init(node);
}
    4ae4:	4770      	bx	lr

00004ae6 <unpend_thread_no_timeout>:
{
    4ae6:	b508      	push	{r3, lr}
	sys_dlist_remove(&thread->base.qnode_dlist);
    4ae8:	f7ff fff5 	bl	4ad6 <sys_dlist_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    4aec:	7b43      	ldrb	r3, [r0, #13]
    4aee:	f023 0302 	bic.w	r3, r3, #2
    4af2:	7343      	strb	r3, [r0, #13]
	thread->base.pended_on = NULL;
    4af4:	2300      	movs	r3, #0
    4af6:	6083      	str	r3, [r0, #8]
}
    4af8:	bd08      	pop	{r3, pc}

00004afa <add_to_waitq_locked>:
{
    4afa:	b538      	push	{r3, r4, r5, lr}
    4afc:	4604      	mov	r4, r0
    4afe:	460d      	mov	r5, r1
	unready_thread(thread);
    4b00:	f7fe ff8e 	bl	3a20 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    4b04:	7b63      	ldrb	r3, [r4, #13]
    4b06:	f043 0302 	orr.w	r3, r3, #2
    4b0a:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    4b0c:	b1e5      	cbz	r5, 4b48 <add_to_waitq_locked+0x4e>
		thread->base.pended_on = wait_q;
    4b0e:	60a5      	str	r5, [r4, #8]
	return list->head == list;
    4b10:	682b      	ldr	r3, [r5, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4b12:	429d      	cmp	r5, r3
    4b14:	d109      	bne.n	4b2a <add_to_waitq_locked+0x30>
	sys_dnode_t *const tail = list->tail;
    4b16:	686b      	ldr	r3, [r5, #4]
	node->prev = tail;
    4b18:	e9c4 5300 	strd	r5, r3, [r4]
	tail->next = node;
    4b1c:	601c      	str	r4, [r3, #0]
	list->tail = node;
    4b1e:	606c      	str	r4, [r5, #4]
}
    4b20:	e012      	b.n	4b48 <add_to_waitq_locked+0x4e>
	return (node == list->tail) ? NULL : node->next;
    4b22:	686a      	ldr	r2, [r5, #4]
    4b24:	4293      	cmp	r3, r2
    4b26:	d0f6      	beq.n	4b16 <add_to_waitq_locked+0x1c>
    4b28:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4b2a:	2b00      	cmp	r3, #0
    4b2c:	d0f3      	beq.n	4b16 <add_to_waitq_locked+0x1c>
	int32_t b1 = thread_1->base.prio;
    4b2e:	f994 200e 	ldrsb.w	r2, [r4, #14]
	int32_t b2 = thread_2->base.prio;
    4b32:	f993 100e 	ldrsb.w	r1, [r3, #14]
	if (b1 != b2) {
    4b36:	428a      	cmp	r2, r1
    4b38:	d0f3      	beq.n	4b22 <add_to_waitq_locked+0x28>
		if (z_sched_prio_cmp(thread, t) > 0) {
    4b3a:	4291      	cmp	r1, r2
    4b3c:	ddf1      	ble.n	4b22 <add_to_waitq_locked+0x28>
	sys_dnode_t *const prev = successor->prev;
    4b3e:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    4b40:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    4b44:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    4b46:	605c      	str	r4, [r3, #4]
}
    4b48:	bd38      	pop	{r3, r4, r5, pc}

00004b4a <z_ready_thread>:
{
    4b4a:	b510      	push	{r4, lr}
	__asm__ volatile(
    4b4c:	f04f 0320 	mov.w	r3, #32
    4b50:	f3ef 8411 	mrs	r4, BASEPRI
    4b54:	f383 8812 	msr	BASEPRI_MAX, r3
    4b58:	f3bf 8f6f 	isb	sy
			ready_thread(thread);
    4b5c:	f7fe ff2c 	bl	39b8 <ready_thread>
	__asm__ volatile(
    4b60:	f384 8811 	msr	BASEPRI, r4
    4b64:	f3bf 8f6f 	isb	sy
}
    4b68:	bd10      	pop	{r4, pc}

00004b6a <z_sched_wake_thread>:
{
    4b6a:	b538      	push	{r3, r4, r5, lr}
    4b6c:	4604      	mov	r4, r0
	__asm__ volatile(
    4b6e:	f04f 0320 	mov.w	r3, #32
    4b72:	f3ef 8511 	mrs	r5, BASEPRI
    4b76:	f383 8812 	msr	BASEPRI_MAX, r3
    4b7a:	f3bf 8f6f 	isb	sy
		if (!killed) {
    4b7e:	7b43      	ldrb	r3, [r0, #13]
    4b80:	f013 0f28 	tst.w	r3, #40	; 0x28
    4b84:	d10b      	bne.n	4b9e <z_sched_wake_thread+0x34>
			if (thread->base.pended_on != NULL) {
    4b86:	6883      	ldr	r3, [r0, #8]
    4b88:	b10b      	cbz	r3, 4b8e <z_sched_wake_thread+0x24>
				unpend_thread_no_timeout(thread);
    4b8a:	f7ff ffac 	bl	4ae6 <unpend_thread_no_timeout>
	thread->base.thread_state &= ~_THREAD_PRESTART;
    4b8e:	7b63      	ldrb	r3, [r4, #13]
			if (is_timeout) {
    4b90:	b951      	cbnz	r1, 4ba8 <z_sched_wake_thread+0x3e>
    4b92:	f003 03fb 	and.w	r3, r3, #251	; 0xfb
    4b96:	7363      	strb	r3, [r4, #13]
			ready_thread(thread);
    4b98:	4620      	mov	r0, r4
    4b9a:	f7fe ff0d 	bl	39b8 <ready_thread>
	__asm__ volatile(
    4b9e:	f385 8811 	msr	BASEPRI, r5
    4ba2:	f3bf 8f6f 	isb	sy
}
    4ba6:	bd38      	pop	{r3, r4, r5, pc}
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    4ba8:	f003 03eb 	and.w	r3, r3, #235	; 0xeb
}
    4bac:	e7f3      	b.n	4b96 <z_sched_wake_thread+0x2c>

00004bae <z_thread_timeout>:
	z_sched_wake_thread(thread, true);
    4bae:	2101      	movs	r1, #1
    4bb0:	3818      	subs	r0, #24
    4bb2:	f7ff bfda 	b.w	4b6a <z_sched_wake_thread>

00004bb6 <z_unpend_first_thread>:
{
    4bb6:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    4bb8:	f04f 0320 	mov.w	r3, #32
    4bbc:	f3ef 8511 	mrs	r5, BASEPRI
    4bc0:	f383 8812 	msr	BASEPRI_MAX, r3
    4bc4:	f3bf 8f6f 	isb	sy
	return list->head == list;
    4bc8:	6804      	ldr	r4, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4bca:	42a0      	cmp	r0, r4
    4bcc:	d00d      	beq.n	4bea <z_unpend_first_thread+0x34>
		if (thread != NULL) {
    4bce:	b134      	cbz	r4, 4bde <z_unpend_first_thread+0x28>
			unpend_thread_no_timeout(thread);
    4bd0:	4620      	mov	r0, r4
    4bd2:	f7ff ff88 	bl	4ae6 <unpend_thread_no_timeout>
    4bd6:	f104 0018 	add.w	r0, r4, #24
    4bda:	f000 f81e 	bl	4c1a <z_abort_timeout>
	__asm__ volatile(
    4bde:	f385 8811 	msr	BASEPRI, r5
    4be2:	f3bf 8f6f 	isb	sy
}
    4be6:	4620      	mov	r0, r4
    4be8:	bd38      	pop	{r3, r4, r5, pc}
    4bea:	2400      	movs	r4, #0
    4bec:	e7f7      	b.n	4bde <z_unpend_first_thread+0x28>

00004bee <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    4bee:	4603      	mov	r3, r0
    4bf0:	b920      	cbnz	r0, 4bfc <z_reschedule_irqlock+0xe>
    4bf2:	f3ef 8205 	mrs	r2, IPSR
    4bf6:	b90a      	cbnz	r2, 4bfc <z_reschedule_irqlock+0xe>
	ret = arch_swap(key);
    4bf8:	f7fc ba96 	b.w	1128 <arch_swap>
    4bfc:	f383 8811 	msr	BASEPRI, r3
    4c00:	f3bf 8f6f 	isb	sy
}
    4c04:	4770      	bx	lr

00004c06 <z_reschedule_unlocked>:
	__asm__ volatile(
    4c06:	f04f 0320 	mov.w	r3, #32
    4c0a:	f3ef 8011 	mrs	r0, BASEPRI
    4c0e:	f383 8812 	msr	BASEPRI_MAX, r3
    4c12:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    4c16:	f7ff bfea 	b.w	4bee <z_reschedule_irqlock>

00004c1a <z_abort_timeout>:
{
    4c1a:	b510      	push	{r4, lr}
    4c1c:	f04f 0220 	mov.w	r2, #32
    4c20:	f3ef 8411 	mrs	r4, BASEPRI
    4c24:	f382 8812 	msr	BASEPRI_MAX, r2
    4c28:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
    4c2c:	6803      	ldr	r3, [r0, #0]
    4c2e:	b13b      	cbz	r3, 4c40 <z_abort_timeout+0x26>
			remove_timeout(to);
    4c30:	f7ff f954 	bl	3edc <remove_timeout>
			ret = 0;
    4c34:	2000      	movs	r0, #0
	__asm__ volatile(
    4c36:	f384 8811 	msr	BASEPRI, r4
    4c3a:	f3bf 8f6f 	isb	sy
}
    4c3e:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
    4c40:	f06f 0015 	mvn.w	r0, #21
    4c44:	e7f7      	b.n	4c36 <z_abort_timeout+0x1c>

00004c46 <z_get_next_timeout_expiry>:
{
    4c46:	b510      	push	{r4, lr}
	__asm__ volatile(
    4c48:	f04f 0320 	mov.w	r3, #32
    4c4c:	f3ef 8411 	mrs	r4, BASEPRI
    4c50:	f383 8812 	msr	BASEPRI_MAX, r3
    4c54:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
    4c58:	f7ff f920 	bl	3e9c <next_timeout>
	__asm__ volatile(
    4c5c:	f384 8811 	msr	BASEPRI, r4
    4c60:	f3bf 8f6f 	isb	sy
}
    4c64:	bd10      	pop	{r4, pc}

00004c66 <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
    4c66:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
    4c68:	f7ff fa34 	bl	40d4 <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    4c6c:	bd08      	pop	{r3, pc}

00004c6e <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    4c6e:	b108      	cbz	r0, 4c74 <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    4c70:	f7fc bdf6 	b.w	1860 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    4c74:	4770      	bx	lr

00004c76 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    4c76:	4770      	bx	lr
