/*
 * Copyright (c) 2021 Pimax. All rights reserved.
 * Author    Date          ChangeLog
 * Master    2021-03-19    First version
 */
#ifndef __SGM4151X_H__
#define __SGM4151X_H__
#include "platform_if.h"
#include "sensor_error.h"

#define SGM4151X_7BIT_ADDR      (0x6B)

/*********************REG00 register*********************/
#define REG00_ADDR              (0x00)
#define EN_HIZ_BIT_POS          (7)
#define EN_HIZ_BIT_MASK         (1 << EN_HIZ_BIT_POS)

#define EN_ICHG_MON_BIT_POS     (5)
#define EN_ICHG_MON_BIT_MASK    (3 << EN_ICHG_MON_BIT_POS)

#define IINDPM_BIT_POS          (0)
#define IINDPM_BIT_MASK         (0x1F << 0)

/*
 * In HIZ mode, the VBUS pin is effectively
 * disconnected from internal circuit. Some
 * leakage current may exist
*/
typedef enum sgm4151x_hiz_mode{
    HIZ_MODE_DISABLE = (0 << EN_HIZ_BIT_POS),  // (default)
    HIZ_MODE_ENABLE  = (1 << EN_HIZ_BIT_POS),
}SGM4151X_HIZ_MODE_t;


/*
 * These bits turn on or off the function of the
 * STAT open-drain output pin (charge status indicator).
*/
typedef enum sgm4151x_stat_pin{
    STAT_PIN_ENABLE    = (0 << EN_ICHG_MON_BIT_POS),  // (DEFAULT)
    STAT_PIN_RESERVED0 = (1 << EN_ICHG_MON_BIT_POS),
    STAT_PIN_RESERVED1 = (2 << EN_ICHG_MON_BIT_POS),
    STAT_PIN_DISABLE   = (2 << EN_ICHG_MON_BIT_POS),  // float pin
}SGM4151X_STAT_PIN_t;


/*
 * Input Current Limit Value (n: 5 bits):= 100 + 100n (mA)
 * IINDPM changes based on PSEL state after an input source 
 * detection as follows:
 * PSEL = High → IINDPM = 500mA
 * PSEL = Low → IINDPM = 2400mA
 * Host can overwrite IINDPM after input source detection is completed.
*/
typedef enum sgm4151x_iindpm{
    IINDPM_100MA  =  (0 << IINDPM_BIT_POS),
    IINDPM_200MA  =  (2 << IINDPM_BIT_POS),
    IINDPM_300MA  =  (3 << IINDPM_BIT_POS),
    IINDPM_400MA  =  (4 << IINDPM_BIT_POS),
    IINDPM_500MA  =  (5 << IINDPM_BIT_POS),
    IINDPM_600MA  =  (6 << IINDPM_BIT_POS),
    IINDPM_700MA  =  (7 << IINDPM_BIT_POS),
    IINDPM_800MA  =  (8 << IINDPM_BIT_POS),
    IINDPM_900MA  =  (9 << IINDPM_BIT_POS),
    IINDPM_1000MA =  (10 << IINDPM_BIT_POS),
    IINDPM_1100MA =  (11 << IINDPM_BIT_POS),
    IINDPM_1200MA =  (12 << IINDPM_BIT_POS),
    IINDPM_1300MA =  (13 << IINDPM_BIT_POS),
    IINDPM_1400MA =  (14 << IINDPM_BIT_POS),
    IINDPM_1500MA =  (15 << IINDPM_BIT_POS),
    IINDPM_1600MA =  (16 << IINDPM_BIT_POS),
    IINDPM_1700MA =  (17 << IINDPM_BIT_POS),
    IINDPM_1800MA =  (18 << IINDPM_BIT_POS),
    IINDPM_1900MA =  (19 << IINDPM_BIT_POS),
    IINDPM_2000MA =  (20 << IINDPM_BIT_POS),
    IINDPM_2100MA =  (21 << IINDPM_BIT_POS),
    IINDPM_2200MA =  (22 << IINDPM_BIT_POS),
    IINDPM_2300MA =  (23 << IINDPM_BIT_POS),
    IINDPM_2400MA =  (24 << IINDPM_BIT_POS),  // DEFAULT
    IINDPM_2500MA =  (25 << IINDPM_BIT_POS),
    IINDPM_2600MA =  (26 << IINDPM_BIT_POS),
    IINDPM_2700MA =  (27 << IINDPM_BIT_POS),
    IINDPM_2800MA =  (28 << IINDPM_BIT_POS),
    IINDPM_2900MA =  (29 << IINDPM_BIT_POS),
    IINDPM_3000MA =  (30 << IINDPM_BIT_POS),
    IINDPM_3100MA =  (31 << IINDPM_BIT_POS),
    IINDPM_3200MA =  (32 << IINDPM_BIT_POS),
}SGM4151X_IINDPM_t;

/******************REG01*******************************/
#define REG01_ADDR              (0x01)
#define PFM_DIS_BIT_POS         (7)
#define PFM_DIS_BIT_MASK        (1 << PFM_DIS_BIT_POS)

#define WD_RST_BIT_POS          (6)
#define WD_RST_BIT_MASK         (1 < WD_RST_BIT_POS)

#define OTG_CONFIG_BIT_POS      (5)
#define OTG_CONFIG_BIT_MASK     (1 << OTG_CONFIG_BIT_POS)

#define CHG_CONFIG_BIT_POS      (4)
#define CHG_CONFIG_BIT_MASK     (1 << CHG_CONFIG_BIT_POS)

#define SYS_MIN_BIT_POS         (1)
#define SYS_MIN_BIT_MASK        (7 << SYS_MIN_BIT_POS)

#define MIN_BAT_SEL_BIT_POS     (0)
#define MIN_BAT_SEL_BIT_MASK    (1 << MIN_BAT_SEL_BIT_POS)

/*
 * Enable Pulse Frequency Modulation. PFM is normally used 
 * to save power at light load by reducing converter switching
 * frequency.
*/
typedef enum sgm4151x_pfm_mode{
    PFM_ENABLE  = (0 << PFM_DIS_BIT_POS),
    PFM_DISABLE = (1 << PFM_DIS_BIT_POS),
}SGM4151X_PFM_MODE_t;

/* 
 * Watchdog Timer Reset Control Bit.
 * Write 1 to this bit to avoid watchdog expiry.
 * WD_RST resets to 0 after watchdog timer reset (expiry)
*/
typedef enum sgm4151x_wd_rst{
    WD_NORMAL = (0 << WD_RST_BIT_POS),  // DEAFULT
    WD_RESET  = (1 << WD_RST_BIT_POS),
}SGM4151X_WD_RST_t;


/*
 * This bit has priority over charge enable in
 * the CHG_CONFIG
*/
typedef enum sgm4151x_otg_config{
    OTG_DISABLE = (0 << OTG_CONFIG_BIT_POS),  // DEAFULT
    OTG_ENABLE  = (1 << OTG_CONFIG_BIT_POS),
}SGM4151X_OTG_CONFIG_t;


/*
 * Charge is enabled when CHG_CONFIG bit
 * is 1 and nCE pin is pulled low.
*/
typedef enum sgm4151x_chg_config{
    CHARGE_DISABLE = (0 << CHG_CONFIG_BIT_POS),
    CHARGE_ENABLE  = (1 << CHG_CONFIG_BIT_POS),  // DEAFULT
}SGM4151X_CHG_CONFIG_t;

/*
 * Minimum System Voltage Value.
 * Offset: 2.6V
 * Range: 2.6V (000) - 3.7V (111)
 * Default: 3.5V (101)
*/
typedef enum sgm4151x_sys_min{
    SYS_MIN_VOLTAGE_2_6V = (0 << SYS_MIN_BIT_POS),
    SYS_MIN_VOLTAGE_2_8V = (1 << SYS_MIN_BIT_POS),
    SYS_MIN_VOLTAGE_3_0V = (2 << SYS_MIN_BIT_POS),
    SYS_MIN_VOLTAGE_3_2V = (3 << SYS_MIN_BIT_POS),
    SYS_MIN_VOLTAGE_3_4V = (4 << SYS_MIN_BIT_POS),
    SYS_MIN_VOLTAGE_3_5V = (5 << SYS_MIN_BIT_POS),  // default
    SYS_MIN_VOLTAGE_3_6V = (6 << SYS_MIN_BIT_POS),
    SYS_MIN_VOLTAGE_3_7V = (7 << SYS_MIN_BIT_POS),
}SGM4151X_SYS_MIN_t;


/*
 * Minimum Battery Voltage for OTG Mode
 * 0 = 2.8V VBAT falling (default)
 * 1 = 2.5V VBAT falling
*/
typedef enum sgm4151x_min_bat_sel{
    MIN_BAT_IN_OTG_2_8V = (0 << MIN_BAT_SEL_BIT_POS),  // DEAFULT
    MIN_BAT_IN_OTG_2_5V = (1 << MIN_BAT_SEL_BIT_POS),
}SGM4151X_MIN_BAT_SEL_t;


/***************************reg02********************************/
#define REG02_ADDR              (0x02)
#define BOOST_LIM_BIT_POS       (7)
#define BOOST_LIN_BIT_MASK      (1 << BOOST_LIM_BIT_POS)

#define Q1_FULLON_BIT_POS       (6)
#define Q1_FULLON_BIT_MASK      (1 << Q1_FULLON_BIT_POS)

#define ICHG_BIT_POS            (0)
#define ICHG_BIT_MASK           (0x1F << ICHG_BIT_POS)

/*
 * The current limit options listed values are the
 * minimum specs. Actual value is typically higher.
*/
typedef enum sgm4151x_boost_lim{
    BOOST_MODE_CURRENT_LIM_0_5A = (0 << BOOST_LIM_BIT_POS),
    BOOST_MODE_CURRENT_LIM_1_2A = (1 << BOOST_LIM_BIT_POS),  // default
}SGM4151X_BOOST_LIM_t;


typedef enum sgm4151x_q1_fullon{
    /* Use higher RDSON if IINDPM < 700mA (for better accuracy */
    USE_HIGHER_RDSON = (0 << Q1_FULLON_BIT_POS),
    /* Use lower RDSON always(fully ON for better efficiency */
    USE_LOWER_RDSON =  (1 << Q1_FULLON_BIT_POS),
}SGM4151X_Q1_FULLON_t;


/* 
 * Fast Charge Current Value (n: 6 bits):= 60n (mA) (n ≤ 50) 
 * Offset: 0mA
 * Range: 0mA (000000) - 3000mA (110010)
 * Default: 2040mA (100010)
 * Notes:Setting ICHG = 0mA disables charge.
 * Values above 50D = 110010 (3000mA) are
 * clamped to 50D = 110010 (3000mA)
 * notice:ma must be a multiple of 60
*/
#define FAST_CHARGE_MA_TO_REG_VALUE(ma)  (((uint8_t)((ma)/60) << ICHG_BIT_POS) & ICHG_BIT_MASK)

/* REG03 (Pre-Charge and Termination Current Settings) */
#define REG03_ADDR              (0x03)
#define IPRECHG_BIT_POS         (4)
#define IPRECHG_BIT_MASK        (0x0F << IPRECHG_BIT_POS)

#define ITERM_BIT_POS           (0)
#define ITERM_BIT_MASK          (0x0F << ITERM_BIT_POS)


/*
 * Pre-Charge Current Limit (n: 4 bits):
 * = 60 + 60n (mA) (n ≤ 12)
 * Offset: 60mA
 * Range: 60mA (0000) - 780mA (1100)
 * Default: 180mA (0010)
 * Note:
 * Values above 12D = 1100 (780mA) are
 * clamped to 12D = 1100 (780mA)
 * notice:ma must be a multiple of 60
*/
#define IPRECHG_MA_TO_REG_VALUE(ma)  (((uint8_t)(((ma) - 60)/60) << IPRECHG_BIT_POS) & IPRECHG_BIT_MASK)

/*
 * Termination Current Limit (n: 4 bits):
 * = 60 + 60n (mA)
 * Offset: 60mA
 * Range: 60mA (0000) - 960mA (1111)
 * Default: 180mA (0010)
*/
#define ITERM_MA_TO_REG_VALUE(ma)    (((uint8_t)(((ma) - 60)/60) << ITERM_BIT_POS) & ITERM_BIT_MASK)


/**********************REG04**********************************/
#define REG04_ADDR              (0x04)
#define VREG_BIT_POS            (3)
#define VREG_BIT_MASK           (0x1F << VREG_BIT_POS)

#define TOPOFF_TIMER_BIT_POS    (1)
#define TOPOFF_TIMER_BIT_MASK   (3 << TOPOFF_TIMER_BIT_POS)

#define VRECHG_BIT_POS          (0)
#define VRECHG_BIT_MASK         (1 << VRECHG_BIT_POS)

/*
 * Charge Voltage Limit (n: 5 bits):
 * = 3856 + 32n (mV) if n ≤ 24, n≠15;
 * = 4.352V if n = 15
 * Offset: 3.856V
 * Range: 3.856V (00000) - 4.624V (11000)
 * Default: 4.208V (01011)
 * Special Value: 4.352V (01111)
 * Note:
 * Values above 24D = 11000 (4.624V) are
 * clamped to 24D = 11000 (4.624V)
 * Notice: the base value is 3856, and the offset value must multiple of 32
*/
#define VREG_REG_VALUE_TO_MV(n)       (3856 + 32*(n >> VREG_BIT_POS))
#define VREF_MV_TO_REG_VALUE(mv)      (((uint8_t)(((mv) - 3856)/32) << VREG_BIT_POS) & VREG_BIT_MASK)


/*
 * The charge extension time added after the
 * termination condition is detected.
 * If disabled, charging terminates as soon as
 * termination conditions are met.
*/
typedef enum topoff_timer{
    TOPOFF_TIMER_DISABLED = (0 << TOPOFF_TIMER_BIT_POS),
    TOPOFF_TIMER_15MIN    = (1 << TOPOFF_TIMER_BIT_POS),
    TOPOFF_TIMER_30MIN    = (2 << TOPOFF_TIMER_BIT_POS),
    TOPOFF_TIMER_45MIN    = (3 << TOPOFF_TIMER_BIT_POS),
}TOPOFF_TIMER_t;


/*
 * A recharge cycle will start if a fully charged
 * battery voltage drops below VREG - VRECHG settings.
*/
typedef enum sgm4151x_battery_recharge_threshold{
    BELOW_VRECHG_100MV  = (0 << VRECHG_BIT_POS),  // default
    BEWLOW_VRECHG_200MV = (1 << VRECHG_BIT_POS),
}SGM4151X_BAT_RECHARGE_THRE_t;


/**********************REG05**********************************/
#define REG05_ADDR              (0x05)
#define EN_TERM_BIT_POS         (7)
#define EN_TERM_BIT_MASK        (1 << EN_TERM_BIT_POS)

#define WATCHDOG_BIT_POS        (4)
#define WATCHDOG_BIT_MASK       (3 << WATCHDOG_BIT_POS)

#define EN_TIMER_BIT_POS        (3)
#define EN_TIMER_BIT_MASK       (1 << EN_TIMER_BIT_POS)

#define CHG_TIMER_BIT_POS       (2)
#define CHG_TIMER_BIT_MASK      (1 << CHG_TIMER_BIT_POS)

#define TREG_BIT_POS            (1)
#define TREG_BIT_MASK           (1 << TREG_BIT_POS)

#define JEITA_ISET_BIT_POS      (0)
#define JEITA_ISET_BIT_MASK     (1 << JETA_ISET_BIT_POS)


typedef enum sgm4151x_term_state{
    TERM_DISABLE = (0 << EN_TERM_BIT_POS),
    TERM_ENABLE  = (1 << EN_TERM_BIT_POS),  // default
}SGM4151X_TERM_STATE_t;


/**
 * Expiry time of the watchdog timer if it is not reset. 
 */
typedef enum sgm4151x_watchdog_setting{
    WATCHDOG_TIMER_DISABLE = (0 << WATCHDOG_BIT_POS),
    WATCHDOG_TIMER_40S     = (1 << WATCHDOG_BIT_POS),
    WATCHDOG_TIMER_80S     = (2 << WATCHDOG_BIT_POS),
    WATCHDOG_TIMER_160S    = (3 << WATCHDOG_BIT_POS),
}SGM4151X_WATCHDOG_SETTING_t;


/*
 * When enabled the pre-charge and fast
 * charge periods are included in the timing.
*/
typedef enum sgm4151x_charge_safety_timer_state{
    CHARGE_SAFETY_DISABLE = (0 << EN_TIMER_BIT_POS),
    CHARGE_SAFETY_ENABLE  = (1 << EN_TIMER_BIT_POS),
}SGM4151X_CHARGE_SAFETY_TIMER_STATE_t;


typedef enum sgm4151x_charge_safety_timer_setting{
    CHARGE_SAFETY_4HRS = (0 << CHG_TIMER_BIT_POS),
    CHARGE_SAFETY_6HRS = (1 << CHG_TIMER_BIT_POS),
}SGM4151X_CHARGE_SAFETY_TIMER_SETTING_t;

/**
 * For buck mode 
 */
typedef enum sgm4151x_thermal_regulation_threshold{
    THERMAL_REGULATION_THRESHOLD_80C  = (0 << TREG_BIT_POS),
    THERMAL_REGULATION_THRESHOLD_120C = (1 << TREG_BIT_POS),
}SGM4151X_THERMAL_REGULATION_THRESHOLD_t;


typedef enum sgm4151x_jeita_charging_current{
    ICHG_PERCENT_OF_50 = (0 << JEITA_ISET_BIT_POS),
    ICHG_PERCENT_OF_20 = (1 << JEITA_ISET_BIT_POS),  // default
}SGM4151X_JEITA_CHARGING_CURRENT_t;


/**********************REG06**********************************/
#define REG06_ADDR              (0x06)

#define OVP_BIT_POS             (6)
#define OVP_BIT_MASK            (3 << OVP_BIT_POS)

#define BOOSTV_BIT_POS          (4)
#define BOOSTV_BIT_MASK         (3 << BOOSTV_BIT_POS)

#define VINDPM_BIT_POS          (0)
#define VINDPM_BIT_MASK         (0x0F << VINDPM_BIT_POS)


/**
 * OVP Threshold for Input Supply 
 */
typedef enum sgm4151x_ovp_threshold{
    OVP_THRESHOLD_5_5V  = (0 << OVP_BIT_POS),
    OVP_THRESHOLD_6_5V  = (1 << OVP_BIT_POS),  // (5V input) (default)
    OVP_THRESHOLD_10_5V = (2 << OVP_BIT_POS),  // (9V input)
    OVP_THRESHOLD_14V   = (3 << OVP_BIT_POS),  // (12V input)
}SGM4151X_OVP_THRESHOLD_t;


/**
 * Boost Mode Voltage Regulation 
 */
typedef enum sgm4151x_boostv{
    BOOSTV_4_85V = (0 << BOOSTV_BIT_POS),
    BOOSTV_5V    = (1 << BOOSTV_BIT_POS),
    BOOSTV_5_15V = (2 << BOOSTV_BIT_POS),
    BOOSTV_5_3V  = (3 << BOOSTV_BIT_POS),
}SGM4151X_BOOSTV_t;


/**
 * VINDPM Threshold (n: 4 bits):= 3.9V + 0.1n (V)
 * Offset: 3.9V
 * Range: 3.9V (0000) - 5.4V (1111)
 * Default: 4.5V (0110)
 */
#define VINDPM_MV_TO_REG_VALUE(mv)   (((uint8_t)(((mv)-3900) / 0.1) << VINDPM_BIT_POS)&VINDPM_BIT_MASK)


/**********************REG07**********************************/
#define REG07_ADDR              (0x07)
#define IINDET_EN_BIT_POS       (7)
#define IINDET_EN_BIT_MASK      (1 << IINDET_EN_BIT_POS)

#define TMR2X_EN_BIT_POS        (6)
#define TMR2X_EN_BIT_MASK       (1 << TMR2X_EN_BIT_POS)

#define BATFET_DIS_BIT_POS      (5)
#define BATFET_DIS_BIT_MASK     (1 << BATFET_DIS_BIT_POS)

#define JEITA_VSET_BIT_POS      (4)
#define JEITA_VSET_BIT_MASK     (1 << JEITA_VSET_BIT_POS)

#define BATFET_DLY_BIT_POS      (3)
#define BATFET_DLY_BIT_MASK     (1 << BATFET_DLY_BIT_POS)

#define BATFET_RST_BIT_POS      (2)
#define BATFET_RST_BIT_MASK     (1 << BATFET_RST_BIT_POS)


#define VDPM_BAT_TRACK_BIT_POS  (0)
#define VDPM_BAT_TRACK_BIT_MASK (3 << VDPM_BAT_TRACK_BIT_POS)


/**
 * Reloads with 0 when input detection is completed. 
 */
typedef enum sgm4151x_input_current_limit_det{
    NO_INPUT_LIMIT_DET    = (0 << IINDET_EN_BIT_POS),
    FORCE_INPUT_LIMIT_DET = (1 << IINDET_EN_BIT_POS), 
}SGM4151X_INPUT_CURRENT_LIMIT_DET_t;


typedef enum sgm4151x_tmr2x_state{
    TMR2X_DISABLE = (0 << TMR2X_EN_BIT_POS),
    /* Safety timer slow down during DPM, JEITA cool, or thermal
     * regulation (default)
     */
    TMR2X_ENABLE  = (1 << TMR2X_EN_BIT_POS),
}SGM4151X_TMR2X_STATE_t;


typedef enum sgm4151x_batfet_state{
    BATFET_TURN_ON  = (0 << BATFET_DIS_BIT_POS),  /* Allow BATFET (Q4) to turn on */
    /* Turn off BATFET (Q4) after a tSM_DLY delay time (REG07 D[3]) */
    BATFET_TURN_OFF = (1 << BATFET_DIS_BIT_POS),  
}SGM4151X_BATFET_STATE_t;


typedef enum sgm4151x_jeita_vset{
    /* JEITA Charging Voltage 0 = Set charge voltage to 4.1V (MAX) (default)*/
    CHARGE_VOLTAGE_4_1V = (0 << JEITA_VSET_BIT_POS),
    /* 1 = Set charge voltage to VREG */
    CHARGE_VOLTAGE_VREG = (1 << JEITA_VSET_BIT_POS),
}SGM4151X_JEITA_VSET_t;


typedef enum sgm4151x_batfet_dly{
    /* Turn off BATFET immediately */
    TURN_OFF_BATFET_NO_DLY = (0 << BATFET_DLY_BIT_POS),
    /*  Turn off BATFET after tSM_DLY */
    TURN_OFF_BATFET_DLY_SM = (1 << BATFET_DLY_BIT_POS),
}SGM4151X_BATFET_DLY_t;

typedef enum sgm4151x_batfet_rst_state{
    BATFET_RST_DISABLE = (0 << BATFET_RST_BIT_POS),
    /* Enable BATFET reset (default) */
    BATFET_RST_ENABLE  = (1 << BATFET_RST_BIT_POS),
}SGM4151X_BATFET_RST_STATE_t;


typedef enum sgm4151x_vdpm_bat_track{
    /* Disable (VINDPM set by register) */
    DYNAMIC_VINDPM_TRACKING_DISABLE = (0 << VDPM_BAT_TRACK_BIT_POS),
    /*  VBAT + 200mV */
    DYNAMIC_VINDPM_TRACKING_200MV   = (1 << VDPM_BAT_TRACK_BIT_POS),
    DYNAMIC_VINDPM_TRACKING_250MV   = (2 << VDPM_BAT_TRACK_BIT_POS),
    DYNAMIC_VINDPM_TRACKING_300MV   = (3 << VDPM_BAT_TRACK_BIT_POS),
}SGM4151X_VDPM_BAT_TRACK_t;


/**********************REG08**********************************/
#define REG08_ADDR              (0x08)   // read only register

#define VBUS_STAT_BIT_POS       (5)
#define VBUS_STATE_BIT_MASK     (7 << VBUS_STAT_BIT_POS)

#define CHRG_STAT_BIT_POS       (3)
#define CHRG_STAT_BIT_MASK      (3 << CHRG_STAT_BIT_POS)

#define PG_STAT_BIT_POS         (2)
#define PG_STAT_BIT_MASK        (1 << PG_STAT_BIT_POS)

#define THERM_STAT_BIT_POS      (1)
#define THERM_STAT_BIT_MASK     (1 << THERM_STAT_BIT_POS)

#define VSYS_STAT_BIT_POS       (0)
#define VSYS_STAT_BIT_MASK      (1 << VSYS_STAT_BIT_POS)

/* 
 * VBUS Status Register (SGM41511) 
 * Other values are reserved.
 * Current limit value is reported in IINDPM[4:0] register.
*/
typedef enum sgm4151x_vbus_stat{
    VBUS_NO_INPUT = (0 << VBUS_STAT_BIT_POS), 
    USB_HOST_SDP  = (1 << VBUS_STAT_BIT_POS),
    ADAPTER_2_4V  = (2 << VBUS_STAT_BIT_POS),
    VBUS_OTG      = (3 << VBUS_STAT_BIT_POS),
}SGN4151X_VBUS_STAT_t;


/* Charging Status */
typedef enum sgm4151x_chrg_stat{
    CHARGE_DISABLE_STATE = (0 << CHRG_STAT_BIT_POS),
    PRE_CHARGE_STATE     = (1 << CHRG_STAT_BIT_POS),
    FAST_CHARGING_STATE  = (2 << CHRG_STAT_BIT_POS),
    CHARGING_TERM_STATE  = (3 << CHRG_STAT_BIT_POS),
}SGM4151X_CHRG_STAT_t;


/* Input Power Status (VBUS in good voltage range and not poor) */
typedef enum sgm4151x_pg_stat{
    POWER_SOURCE_NOT_GOOD = (0 << PG_STAT_BIT_POS),
    POWER_SOURCE_GOOD     = (1 << PG_STAT_BIT_POS),
}SGM4151X_OG_STAT_t;


typedef enum sgm4151x_therm_stat{
    NOT_IN_THERMAL_REGULATION = (0 << THERM_STAT_BIT_POS),
    IN_THERMAL_REGULATION     = (1 << THERM_STAT_BIT_POS),
}SGM4151X_THERM_STAT_t;


typedef enum sgm4151x_vsys_stat{
    /*  Not in VSYSMIN regulation (VBAT > VSYS_MIN) */
    NOT_IN_VSYSMIN_REGULATION = (0 << VSYS_STAT_BIT_POS),
    /*  In VSYSMIN regulation (VBAT < VSYS_MIN) */
    IN_VSYSMIN_REGULATION     = (1 << VSYS_STAT_BIT_POS),
}SGM4151X_VSYS_STAT_t;


/**********************REG09**********************************/
#define REG09_ADDR              (0x09)

#define WATCHDOG_FAULT_BIT_POS  (7)
#define WATCHDOG_FAULT_BIT_MASK (1 << WATCHDOG_FAULT_BIT_POS)

#define BOOST_FAULT_BIT_POS     (6)
#define BOOST_FAULT_BIT_MASK    (1 << BOOST_FAULT_BIT_POS)

#define CHRG_FAULT_BIT_POS      (4)
#define CHRG_FAULT_BIT_MASK     (3 << CHRG_FAULT_BIT_POS)

#define BAT_FAULT_BIT_POS       (3)
#define BAT_FAULT_BIT_MASK      (1 << BAT_FAULT_BIT_POS)

#define NTC_FAULT_BIT_POS       (0)
#define NTC_FAULT_BIT_MASK      (6 << NTC_FAULT_BIT_POS)


typedef enum sgm4151x_watchdog_fault_status{
    WATCHDOG_NO_FAULT      = (0 << WATCHDOG_FAULT_BIT_POS),
    WATCHDOG_TIMER_EXPIRED = (1 << WATCHDOG_FAULT_BIT_POS),
}SGM4151_WATCHDOG_FAULT_STATUS_t;


typedef enum sgm4151x_boost_fault_status{
    BOOST_FAULT_NORMAL = (0 << BOOST_FAULT_BIT_POS),
    /* VBUS overloaded in OTG, or VBUS OVP, or battery voltage too low
     * (any condition that prevents boost starting)*/
    BOOST_FAULT        = (1 << BOOST_FAULT_BIT_POS),
}SGM4151_BOOST_FAULT_STATUS_t;

typedef enum sgm4151x_chrg_fault_status{
    CHRG_NORMAL = (0 << CHRG_FAULT_BIT_POS),
    INPUT_FAULT = (1 << CHRG_FAULT_BIT_POS),
    THERMAL_SHUTDOWM = (2 << CHRG_FAULT_BIT_POS),
    CHARGE_SAFETY_TIMER_EXPIRED = (3 << CHRG_FAULT_BIT_POS),
}SGM4151_CHRG_FAULT_STATUS_t;

typedef enum sgm4151x_bat_fault_status{
    BAT_NORMAL = (0 << BAT_FAULT_BIT_POS),
    BAT_OVER_VOLTAGE = (1 << BAT_FAULT_BIT_POS),
}SGM4151_BAT_FAULT_STATUS_t;


/**
 * JEITA Condition Based on Battery NTC Temperature Measurement.
 * NTC fault bits are updated in real time and does not need a read to reset 
 */
typedef enum sgm4151x_ntc_fault_status{
    NTC_NORMAL = (0 << NTC_FAULT_BIT_POS),
    NTC_WARM   = (2 << NTC_FAULT_BIT_POS),
    NTC_COOL   = (3 << NTC_FAULT_BIT_POS),
    NTC_COLD   = (5 << NTC_FAULT_BIT_POS),
    NTC_HOT    = (6 << NTC_FAULT_BIT_POS),
}SGM4151_NTC_FAULT_STATUS_t;


/**********************REG0A**********************************/
#define REG10_ADDR              (0x0A)

#define VBUS_GD_BIT_POS         (7)
#define VBUS_GD_BIT_MASK        (1 << VBUS_GD_BIT_POS)

#define VINDPM_STAT_BIT_POS     (6)
#define VINDPM_STAT_BIT_MASK    (1 << VINDPM_STAT_BIT_POS)

#define IINDPM_STAT_BIT_POS     (5)
#define IINDPM_STAT_BIT_MASK    (1 << IINDPM_STAT_BIT_POS)

#define TOPOFF_ACTIVE_BIT_POS   (3)
#define TOPOFF_ACTIVE_BIT_MASK  (1 << TOPOFF_ACTIVE_BIT_POS)

#define ACOV_STAT_BIT_POS       (2)
#define ACOV_STAT_BIT_MASK      (1 << ACOV_STAT_BIT_POS)

#define VINDPM_INT_MASK_POS     (1)
#define VINDPM_INT_MASK_MASK    (1 << VINDPM_INT_MASK_POS)

#define IINDPM_INT_MASK_POS     (0)
#define IINDPM_INT_MASK_MASK    (1 << IINDPM_INT_MASK_POS)


// read only
typedef enum sgm4151x_source_detected{
    VBUS_NOT_ATTACHED = (0 << VBUS_GD_BIT_POS),
    VBUS_ATTACHED     = (1 << VBUS_GD_BIT_POS),
}SGM4151X_SOURCE_DETECTED_t;


// read only
typedef enum sgm4151x_vindpm_stat{
    NOT_IN_VINDPM = (0 << VINDPM_STAT_BIT_POS),
    IN_VINDPM     = (1 << VINDPM_STAT_BIT_POS),
}SGM4151X_VINDPM_STAT_t;


// read only
typedef enum
{
    NOT_IN_IINDPM = (0 << IINDPM_STAT_BIT_POS),
    IN_IINDPM     = (1 << IINDPM_STAT_BIT_POS),
}SGM4151X_IINDPM_STAT_t;


// read only
typedef enum sgm4151x_topoff_timer_status{
    TOPOFF_TIMER_NOT_COUNTING = (0 << TOPOFF_ACTIVE_BIT_POS),
    TOPOFF_TIMER_COUNTING     = (1 << TOPOFF_ACTIVE_BIT_POS),
}SGM4151X_TOPOFF_TIMER_STATUS_t;


// read only
typedef enum sgm4151x_acov_stat{
    NO_ACOV  = (0 << ACOV_STAT_BIT_POS),
    ACOV_DET = (1 << ACOV_STAT_BIT_POS),
}SGM4151X_ACOV_STAT_t;


// W/R
typedef enum sgm4151x_vindpm_int_mask{
    ALLOW_VINDPM_INT = (0 << VINDPM_INT_MASK_POS),
    MASK_VINDPM_INT  = (1 << VINDPM_INT_MASK_POS),
}SGM4151X_VINDPM_INT_MASK_t;

// W/R
typedef enum sgm4151x_iindpm_int_mask{
    ALLOW_IINDPM_INT = (0 << IINDPM_INT_MASK_POS),
    MASK_IINDPM_INT  = (1 << IINDPM_INT_MASK_POS),
}SGM4151X_IINDPM_INT_MASK_t;


/**********************REG0B**********************************/
#define REG11_ADDR              (0x0B)

#define REG_RST_BIT_POS         (7)
#define REG_RST_BIT_MASK        (1 << REG_RST_BIT_POS)

#define DEVICE_PART_ID_POS      (3)
#define DEVICE_PART_ID_MASK     (0x0F << DEVICE_PART_ID_POS)
#define DEVICE_PART_ID          (0x02)

typedef enum sgm4151x_reg_rst{
    NO_EFFECT = (0 << REG_RST_BIT_POS),
    /* Reset R/W bits of all registers to the default and reset safety timer
      (It also resets itself to 0 after register reset is completed.) */
    RESET_ALL = (1 << REG_RST_BIT_POS),
}SGM4151X_REG_RST_t;


typedef enum sgm4151x_charge_mode{
    /* Used to control the on-resistance of Q1 (VBUS switch) 
       for better input current measurement accuracy.
       In boost mode, full FET is always used, and
       this bit has no effect. 
    */
    VBUS_FET_SWITCH_Q1 = 0,
    BATFET_Q4,
}SGM4151X_CHARGE_MODE_t;


typedef struct sgm4151x_dev{
    sensor_serial_if_t *driver;
    char *name;

    // reg00, USB Input Current Regulation Limit
    SGM4151X_IINDPM_t iindpm;  // Input Current Limit Value (n: 5 bits):= 100 + 100n (mA)
    // reg01
    SGM4151X_SYS_MIN_t sys_min_vol; // Minimum System Voltage
    // reg02
    // Fast Charge Current Value (n: 6 bits):= 60n (mA) (n ≤ 50)through FAST_CHARGE_MA_TO_REG_VALUE
    uint8_t fast_charge_current; 
    // reg03
    uint8_t iprechg; // Pre-Charge Current Limit,IPRECHG_MA_TO_REG_VALUE
    uint8_t iterm;   // Termination Current Limit, ITERM_MA_TO_REG_VALUE
    // reg04
    uint8_t vreg;    // Charge Voltage Limit (n: 5 bits):,VREF_MV_TO_REG_VALUE   
}sgm4151x_dev_t;


bool sgm4151x_check_part_number(sgm4151x_dev_t *dev);

int sgm4151x_device_init(sgm4151x_dev_t *dev);

#endif  // @page end

