
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_table>:
   0:	60 5d 00 20 91 2d 00 00 53 64 00 00 65 2d 00 00     `]. .-..Sd..e-..
  10:	65 2d 00 00 65 2d 00 00 65 2d 00 00 00 00 00 00     e-..e-..e-......
	...
  2c:	e9 28 00 00 65 2d 00 00 00 00 00 00 65 2d 00 00     .(..e-......e-..
  3c:	65 2d 00 00                                         e-..

00000040 <_irq_vector_table>:
  40:	65 29 00 00 65 29 00 00 65 29 00 00 65 29 00 00     e)..e)..e)..e)..
  50:	65 29 00 00 65 29 00 00 65 29 00 00 65 29 00 00     e)..e)..e)..e)..
  60:	65 29 00 00 65 29 00 00 65 29 00 00 65 29 00 00     e)..e)..e)..e)..
  70:	65 29 00 00 65 29 00 00 65 29 00 00 65 29 00 00     e)..e)..e)..e)..
  80:	65 29 00 00 65 29 00 00 65 29 00 00 65 29 00 00     e)..e)..e)..e)..
  90:	65 29 00 00 65 29 00 00 65 29 00 00 65 29 00 00     e)..e)..e)..e)..
  a0:	65 29 00 00 65 29 00 00 65 29 00 00 65 29 00 00     e)..e)..e)..e)..
  b0:	65 29 00 00 65 29 00 00 65 29 00 00 65 29 00 00     e)..e)..e)..e)..
  c0:	65 29 00 00 65 29 00 00 65 29 00 00 65 29 00 00     e)..e)..e)..e)..
  d0:	65 29 00 00 65 29 00 00 65 29 00 00                 e)..e)..e)..

Disassembly of section text:

000000dc <__aeabi_uldivmod>:
      dc:	b953      	cbnz	r3, f4 <__aeabi_uldivmod+0x18>
      de:	b94a      	cbnz	r2, f4 <__aeabi_uldivmod+0x18>
      e0:	2900      	cmp	r1, #0
      e2:	bf08      	it	eq
      e4:	2800      	cmpeq	r0, #0
      e6:	bf1c      	itt	ne
      e8:	f04f 31ff 	movne.w	r1, #4294967295
      ec:	f04f 30ff 	movne.w	r0, #4294967295
      f0:	f000 b80c 	b.w	10c <__aeabi_idiv0>
      f4:	f1ad 0c08 	sub.w	ip, sp, #8
      f8:	e96d ce04 	strd	ip, lr, [sp, #-16]!
      fc:	f000 f808 	bl	110 <__udivmoddi4>
     100:	f8dd e004 	ldr.w	lr, [sp, #4]
     104:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     108:	b004      	add	sp, #16
     10a:	4770      	bx	lr

0000010c <__aeabi_idiv0>:
     10c:	4770      	bx	lr
     10e:	bf00      	nop

00000110 <__udivmoddi4>:
     110:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     114:	4607      	mov	r7, r0
     116:	468c      	mov	ip, r1
     118:	4608      	mov	r0, r1
     11a:	9e09      	ldr	r6, [sp, #36]	; 0x24
     11c:	4615      	mov	r5, r2
     11e:	463c      	mov	r4, r7
     120:	4619      	mov	r1, r3
     122:	2b00      	cmp	r3, #0
     124:	f040 80c6 	bne.w	2b4 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xb4>
     128:	4282      	cmp	r2, r0
     12a:	fab2 f782 	clz	r7, r2
     12e:	d946      	bls.n	1be <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x51>
     130:	b14f      	cbz	r7, 146 <CONFIG_IDLE_STACK_SIZE+0x6>
     132:	f1c7 0e20 	rsb	lr, r7, #32
     136:	fa24 fe0e 	lsr.w	lr, r4, lr
     13a:	fa00 f307 	lsl.w	r3, r0, r7
     13e:	40bd      	lsls	r5, r7
     140:	ea4e 0c03 	orr.w	ip, lr, r3
     144:	40bc      	lsls	r4, r7
     146:	ea4f 4815 	mov.w	r8, r5, lsr #16
     14a:	fa1f fe85 	uxth.w	lr, r5
     14e:	fbbc f9f8 	udiv	r9, ip, r8
     152:	0c22      	lsrs	r2, r4, #16
     154:	fb08 c319 	mls	r3, r8, r9, ip
     158:	fb09 fa0e 	mul.w	sl, r9, lr
     15c:	ea42 4303 	orr.w	r3, r2, r3, lsl #16
     160:	459a      	cmp	sl, r3
     162:	d928      	bls.n	1b6 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x49>
     164:	18eb      	adds	r3, r5, r3
     166:	f109 30ff 	add.w	r0, r9, #4294967295
     16a:	d204      	bcs.n	176 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x9>
     16c:	459a      	cmp	sl, r3
     16e:	d902      	bls.n	176 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x9>
     170:	f1a9 0002 	sub.w	r0, r9, #2
     174:	442b      	add	r3, r5
     176:	eba3 030a 	sub.w	r3, r3, sl
     17a:	b2a4      	uxth	r4, r4
     17c:	fbb3 f2f8 	udiv	r2, r3, r8
     180:	fb08 3312 	mls	r3, r8, r2, r3
     184:	fb02 fe0e 	mul.w	lr, r2, lr
     188:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     18c:	45a6      	cmp	lr, r4
     18e:	d914      	bls.n	1ba <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x4d>
     190:	192c      	adds	r4, r5, r4
     192:	f102 33ff 	add.w	r3, r2, #4294967295
     196:	d203      	bcs.n	1a0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x33>
     198:	45a6      	cmp	lr, r4
     19a:	d901      	bls.n	1a0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x33>
     19c:	1e93      	subs	r3, r2, #2
     19e:	442c      	add	r4, r5
     1a0:	eba4 040e 	sub.w	r4, r4, lr
     1a4:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
     1a8:	b11e      	cbz	r6, 1b2 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x45>
     1aa:	40fc      	lsrs	r4, r7
     1ac:	2300      	movs	r3, #0
     1ae:	6034      	str	r4, [r6, #0]
     1b0:	6073      	str	r3, [r6, #4]
     1b2:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
     1b6:	4648      	mov	r0, r9
     1b8:	e7dd      	b.n	176 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x9>
     1ba:	4613      	mov	r3, r2
     1bc:	e7f0      	b.n	1a0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x33>
     1be:	b902      	cbnz	r2, 1c2 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x55>
     1c0:	deff      	udf	#255	; 0xff
     1c2:	bb87      	cbnz	r7, 226 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0x26>
     1c4:	1a83      	subs	r3, r0, r2
     1c6:	2101      	movs	r1, #1
     1c8:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     1cc:	b2aa      	uxth	r2, r5
     1ce:	fbb3 fcfe 	udiv	ip, r3, lr
     1d2:	0c20      	lsrs	r0, r4, #16
     1d4:	fb0e 331c 	mls	r3, lr, ip, r3
     1d8:	fb0c f802 	mul.w	r8, ip, r2
     1dc:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
     1e0:	4598      	cmp	r8, r3
     1e2:	d963      	bls.n	2ac <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xac>
     1e4:	18eb      	adds	r3, r5, r3
     1e6:	f10c 30ff 	add.w	r0, ip, #4294967295
     1ea:	d204      	bcs.n	1f6 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x89>
     1ec:	4598      	cmp	r8, r3
     1ee:	d902      	bls.n	1f6 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x89>
     1f0:	f1ac 0002 	sub.w	r0, ip, #2
     1f4:	442b      	add	r3, r5
     1f6:	eba3 0308 	sub.w	r3, r3, r8
     1fa:	b2a4      	uxth	r4, r4
     1fc:	fbb3 fcfe 	udiv	ip, r3, lr
     200:	fb0e 331c 	mls	r3, lr, ip, r3
     204:	fb0c f202 	mul.w	r2, ip, r2
     208:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     20c:	42a2      	cmp	r2, r4
     20e:	d94f      	bls.n	2b0 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xb0>
     210:	192c      	adds	r4, r5, r4
     212:	f10c 33ff 	add.w	r3, ip, #4294967295
     216:	d204      	bcs.n	222 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0x22>
     218:	42a2      	cmp	r2, r4
     21a:	d902      	bls.n	222 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0x22>
     21c:	f1ac 0302 	sub.w	r3, ip, #2
     220:	442c      	add	r4, r5
     222:	1aa4      	subs	r4, r4, r2
     224:	e7be      	b.n	1a4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x37>
     226:	f1c7 0c20 	rsb	ip, r7, #32
     22a:	fa20 f80c 	lsr.w	r8, r0, ip
     22e:	fa00 f307 	lsl.w	r3, r0, r7
     232:	fa24 fc0c 	lsr.w	ip, r4, ip
     236:	40bd      	lsls	r5, r7
     238:	ea4c 0203 	orr.w	r2, ip, r3
     23c:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     240:	b2ab      	uxth	r3, r5
     242:	fbb8 fcfe 	udiv	ip, r8, lr
     246:	0c11      	lsrs	r1, r2, #16
     248:	fb0e 801c 	mls	r0, lr, ip, r8
     24c:	fb0c f903 	mul.w	r9, ip, r3
     250:	ea41 4000 	orr.w	r0, r1, r0, lsl #16
     254:	4581      	cmp	r9, r0
     256:	fa04 f407 	lsl.w	r4, r4, r7
     25a:	d923      	bls.n	2a4 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xa4>
     25c:	1828      	adds	r0, r5, r0
     25e:	f10c 31ff 	add.w	r1, ip, #4294967295
     262:	d204      	bcs.n	26e <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0x6e>
     264:	4581      	cmp	r9, r0
     266:	d902      	bls.n	26e <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0x6e>
     268:	f1ac 0102 	sub.w	r1, ip, #2
     26c:	4428      	add	r0, r5
     26e:	eba0 0009 	sub.w	r0, r0, r9
     272:	b292      	uxth	r2, r2
     274:	fbb0 fcfe 	udiv	ip, r0, lr
     278:	fb0e 001c 	mls	r0, lr, ip, r0
     27c:	fb0c f803 	mul.w	r8, ip, r3
     280:	ea42 4300 	orr.w	r3, r2, r0, lsl #16
     284:	4598      	cmp	r8, r3
     286:	d90f      	bls.n	2a8 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xa8>
     288:	18eb      	adds	r3, r5, r3
     28a:	f10c 32ff 	add.w	r2, ip, #4294967295
     28e:	d204      	bcs.n	29a <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0x9a>
     290:	4598      	cmp	r8, r3
     292:	d902      	bls.n	29a <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0x9a>
     294:	f1ac 0202 	sub.w	r2, ip, #2
     298:	442b      	add	r3, r5
     29a:	eba3 0308 	sub.w	r3, r3, r8
     29e:	ea42 4101 	orr.w	r1, r2, r1, lsl #16
     2a2:	e791      	b.n	1c8 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x5b>
     2a4:	4661      	mov	r1, ip
     2a6:	e7e2      	b.n	26e <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0x6e>
     2a8:	4662      	mov	r2, ip
     2aa:	e7f6      	b.n	29a <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0x9a>
     2ac:	4660      	mov	r0, ip
     2ae:	e7a2      	b.n	1f6 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x89>
     2b0:	4663      	mov	r3, ip
     2b2:	e7b6      	b.n	222 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0x22>
     2b4:	4283      	cmp	r3, r0
     2b6:	d905      	bls.n	2c4 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xc4>
     2b8:	b10e      	cbz	r6, 2be <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xbe>
     2ba:	e9c6 7000 	strd	r7, r0, [r6]
     2be:	2100      	movs	r1, #0
     2c0:	4608      	mov	r0, r1
     2c2:	e776      	b.n	1b2 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x45>
     2c4:	fab3 f183 	clz	r1, r3
     2c8:	b981      	cbnz	r1, 2ec <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xec>
     2ca:	4283      	cmp	r3, r0
     2cc:	d301      	bcc.n	2d2 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xd2>
     2ce:	42ba      	cmp	r2, r7
     2d0:	d80a      	bhi.n	2e8 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xe8>
     2d2:	1abc      	subs	r4, r7, r2
     2d4:	eb60 0303 	sbc.w	r3, r0, r3
     2d8:	2001      	movs	r0, #1
     2da:	469c      	mov	ip, r3
     2dc:	2e00      	cmp	r6, #0
     2de:	d068      	beq.n	3b2 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xb2>
     2e0:	e9c6 4c00 	strd	r4, ip, [r6]
     2e4:	2100      	movs	r1, #0
     2e6:	e764      	b.n	1b2 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x45>
     2e8:	4608      	mov	r0, r1
     2ea:	e7f7      	b.n	2dc <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xdc>
     2ec:	f1c1 0c20 	rsb	ip, r1, #32
     2f0:	408b      	lsls	r3, r1
     2f2:	fa22 f40c 	lsr.w	r4, r2, ip
     2f6:	431c      	orrs	r4, r3
     2f8:	fa02 f501 	lsl.w	r5, r2, r1
     2fc:	fa00 f301 	lsl.w	r3, r0, r1
     300:	fa27 f20c 	lsr.w	r2, r7, ip
     304:	fa20 fb0c 	lsr.w	fp, r0, ip
     308:	ea4f 4914 	mov.w	r9, r4, lsr #16
     30c:	4313      	orrs	r3, r2
     30e:	fbbb f8f9 	udiv	r8, fp, r9
     312:	fa1f fe84 	uxth.w	lr, r4
     316:	fb09 bb18 	mls	fp, r9, r8, fp
     31a:	0c1a      	lsrs	r2, r3, #16
     31c:	fb08 fa0e 	mul.w	sl, r8, lr
     320:	ea42 420b 	orr.w	r2, r2, fp, lsl #16
     324:	4592      	cmp	sl, r2
     326:	fa07 f701 	lsl.w	r7, r7, r1
     32a:	d93e      	bls.n	3aa <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xaa>
     32c:	18a2      	adds	r2, r4, r2
     32e:	f108 30ff 	add.w	r0, r8, #4294967295
     332:	d204      	bcs.n	33e <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x3e>
     334:	4592      	cmp	sl, r2
     336:	d902      	bls.n	33e <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x3e>
     338:	f1a8 0002 	sub.w	r0, r8, #2
     33c:	4422      	add	r2, r4
     33e:	eba2 020a 	sub.w	r2, r2, sl
     342:	b29b      	uxth	r3, r3
     344:	fbb2 f8f9 	udiv	r8, r2, r9
     348:	fb09 2218 	mls	r2, r9, r8, r2
     34c:	fb08 fe0e 	mul.w	lr, r8, lr
     350:	ea43 4202 	orr.w	r2, r3, r2, lsl #16
     354:	4596      	cmp	lr, r2
     356:	d92a      	bls.n	3ae <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xae>
     358:	18a2      	adds	r2, r4, r2
     35a:	f108 33ff 	add.w	r3, r8, #4294967295
     35e:	d204      	bcs.n	36a <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x6a>
     360:	4596      	cmp	lr, r2
     362:	d902      	bls.n	36a <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x6a>
     364:	f1a8 0302 	sub.w	r3, r8, #2
     368:	4422      	add	r2, r4
     36a:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
     36e:	fba0 9305 	umull	r9, r3, r0, r5
     372:	eba2 020e 	sub.w	r2, r2, lr
     376:	429a      	cmp	r2, r3
     378:	46ce      	mov	lr, r9
     37a:	4698      	mov	r8, r3
     37c:	d302      	bcc.n	384 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x84>
     37e:	d106      	bne.n	38e <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x8e>
     380:	454f      	cmp	r7, r9
     382:	d204      	bcs.n	38e <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x8e>
     384:	ebb9 0e05 	subs.w	lr, r9, r5
     388:	eb63 0804 	sbc.w	r8, r3, r4
     38c:	3801      	subs	r0, #1
     38e:	b186      	cbz	r6, 3b2 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xb2>
     390:	ebb7 030e 	subs.w	r3, r7, lr
     394:	eb62 0708 	sbc.w	r7, r2, r8
     398:	fa07 fc0c 	lsl.w	ip, r7, ip
     39c:	40cb      	lsrs	r3, r1
     39e:	ea4c 0303 	orr.w	r3, ip, r3
     3a2:	40cf      	lsrs	r7, r1
     3a4:	e9c6 3700 	strd	r3, r7, [r6]
     3a8:	e79c      	b.n	2e4 <CONFIG_BOOT_MAX_LINE_INPUT_LEN+0xe4>
     3aa:	4640      	mov	r0, r8
     3ac:	e7c7      	b.n	33e <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x3e>
     3ae:	4643      	mov	r3, r8
     3b0:	e7db      	b.n	36a <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x6a>
     3b2:	4631      	mov	r1, r6
     3b4:	e6fd      	b.n	1b2 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x45>
	...

000003b8 <main>:
    return detect_value == expected;
}
#endif

void main(void)
{
     3b8:	b570      	push	{r4, r5, r6, lr}
}

NRF_STATIC_INLINE void nrf_wdt_reload_request_set(NRF_WDT_Type *        p_reg,
                                                  nrf_wdt_rr_register_t rr_register)
{
    p_reg->RR[rr_register] = NRF_WDT_RR_VALUE;
     3ba:	4b4d      	ldr	r3, [pc, #308]	; (4f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x8>)
     3bc:	4a4d      	ldr	r2, [pc, #308]	; (4f4 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xc>)
     3be:	f8c3 2600 	str.w	r2, [r3, #1536]	; 0x600
    fih_int fih_rc = FIH_FAILURE;

    MCUBOOT_WATCHDOG_FEED();

#if !defined(MCUBOOT_DIRECT_XIP)
    BOOT_LOG_INF("Starting bootloader");
     3c2:	484d      	ldr	r0, [pc, #308]	; (4f8 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x10>)
     3c4:	f8c3 2604 	str.w	r2, [r3, #1540]	; 0x604
{
     3c8:	b086      	sub	sp, #24
     3ca:	f8c3 2608 	str.w	r2, [r3, #1544]	; 0x608
    BOOT_LOG_INF("Starting bootloader");
     3ce:	2149      	movs	r1, #73	; 0x49
     3d0:	f8c3 260c 	str.w	r2, [r3, #1548]	; 0x60c
     3d4:	f8c3 2610 	str.w	r2, [r3, #1552]	; 0x610
     3d8:	f8c3 2614 	str.w	r2, [r3, #1556]	; 0x614
     3dc:	f8c3 2618 	str.w	r2, [r3, #1560]	; 0x618
     3e0:	f8c3 261c 	str.w	r2, [r3, #1564]	; 0x61c
     3e4:	f005 fd2b 	bl	5e3e <z_log_minimal_printk>
#ifdef CONFIG_MCUBOOT_INDICATION_LED
    /* LED init */
    led_init();
#endif

    os_heap_init();
     3e8:	f000 f8d4 	bl	594 <os_heap_init>
    ZEPHYR_BOOT_LOG_START();

    (void)rc;

#if (!defined(CONFIG_XTENSA) && DT_HAS_CHOSEN(zephyr_flash_controller))
    if (!flash_device_get_binding(DT_LABEL(DT_CHOSEN(zephyr_flash_controller)))) {
     3ec:	4843      	ldr	r0, [pc, #268]	; (4fc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x14>)
     3ee:	f000 f8a3 	bl	538 <flash_device_get_binding>
     3f2:	b928      	cbnz	r0, 400 <CONFIG_MPSL_WORK_STACK_SIZE>
        BOOT_LOG_ERR("Flash device %s not found",
     3f4:	4a41      	ldr	r2, [pc, #260]	; (4fc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x14>)
     3f6:	4842      	ldr	r0, [pc, #264]	; (500 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x18>)
     3f8:	2145      	movs	r1, #69	; 0x45
     3fa:	f005 fd20 	bl	5e3e <z_log_minimal_printk>
		     DT_LABEL(DT_CHOSEN(zephyr_flash_controller)));
        while (1)
     3fe:	e7fe      	b.n	3fe <main+0x46>
        BOOT_LOG_ERR("Flash device %s not found", JEDEC_SPI_NOR_0_LABEL);
        while (1)
            ;
    }
#endif
	BOOT_LOG_INF("Check detect pin");
     400:	4840      	ldr	r0, [pc, #256]	; (504 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x1c>)
     402:	2149      	movs	r1, #73	; 0x49
     404:	f005 fd1b 	bl	5e3e <z_log_minimal_printk>
		union { uintptr_t x; const char * val; } parm0 = { .val = name };
		return (const struct device *) arch_syscall_invoke1(parm0.x, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
     408:	483f      	ldr	r0, [pc, #252]	; (508 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x20>)
     40a:	f005 f831 	bl	5470 <z_impl_device_get_binding>
     40e:	4604      	mov	r4, r0
{
	const struct gpio_driver_api *api =
		(const struct gpio_driver_api *)port->api;
	const struct gpio_driver_config *const cfg =
		(const struct gpio_driver_config *)port->config;
	struct gpio_driver_data *data =
     410:	6902      	ldr	r2, [r0, #16]
	const struct gpio_driver_api *api =
     412:	6881      	ldr	r1, [r0, #8]
		 "Unsupported pin");

	if ((flags & GPIO_ACTIVE_LOW) != 0) {
		data->invert |= (gpio_port_pins_t)BIT(pin);
	} else {
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
     414:	6813      	ldr	r3, [r2, #0]
     416:	f023 0320 	bic.w	r3, r3, #32
     41a:	6013      	str	r3, [r2, #0]
	}

	return api->pin_configure(port, pin, flags);
     41c:	680b      	ldr	r3, [r1, #0]
     41e:	4a3b      	ldr	r2, [pc, #236]	; (50c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x24>)
     420:	2105      	movs	r1, #5
     422:	4798      	blx	r3
					   gpio_port_value_t *value)
{
	const struct gpio_driver_api *api =
		(const struct gpio_driver_api *)port->api;

	return api->port_get_raw(port, value);
     424:	68a3      	ldr	r3, [r4, #8]
     426:	4620      	mov	r0, r4
     428:	685b      	ldr	r3, [r3, #4]
     42a:	a903      	add	r1, sp, #12
     42c:	4798      	blx	r3
	(void)cfg;
	__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
		 "Unsupported pin");

	ret = gpio_port_get_raw(port, &value);
	if (ret == 0) {
     42e:	4604      	mov	r4, r0
     430:	b910      	cbnz	r0, 438 <CONFIG_MPSL_WORK_STACK_SIZE+0x38>
		ret = (value & (gpio_port_pins_t)BIT(pin)) != 0 ? 1 : 0;
     432:	9c03      	ldr	r4, [sp, #12]
     434:	f3c4 1440 	ubfx	r4, r4, #5, #1
	BOOT_LOG_INF("detect_pin %d %d %d", pin, expected, detect_value);
     438:	4835      	ldr	r0, [pc, #212]	; (510 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x28>)
     43a:	9400      	str	r4, [sp, #0]
     43c:	2300      	movs	r3, #0
     43e:	2205      	movs	r2, #5
     440:	2149      	movs	r1, #73	; 0x49
     442:	f005 fcfc 	bl	5e3e <z_log_minimal_printk>
#ifdef CONFIG_MCUBOOT_SERIAL
    if (detect_pin(CONFIG_BOOT_SERIAL_DETECT_PORT,
     446:	b97c      	cbnz	r4, 468 <CONFIG_MPSL_WORK_STACK_SIZE+0x68>
#endif // defined(DPPI_PRESENT)

#if NRF_POWER_HAS_RESETREAS
NRF_STATIC_INLINE uint32_t nrf_power_resetreas_get(NRF_POWER_Type const * p_reg)
{
    return p_reg->RESETREAS;
     448:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
     44c:	f8d3 3400 	ldr.w	r3, [r3, #1024]	; 0x400
    return !(rr == 0 || (rr & NRFX_RESET_REASON_RESETPIN_MASK));
     450:	b10b      	cbz	r3, 456 <CONFIG_MPSL_WORK_STACK_SIZE+0x56>
     452:	07db      	lsls	r3, r3, #31
     454:	d508      	bpl.n	468 <CONFIG_MPSL_WORK_STACK_SIZE+0x68>
            !boot_skip_serial_recovery()) {
#ifdef CONFIG_MCUBOOT_INDICATION_LED
        gpio_pin_set(led, LED0_GPIO_PIN, 1);
#endif

        BOOT_LOG_INF("Enter the serial recovery mode");
     456:	482f      	ldr	r0, [pc, #188]	; (514 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2c>)
     458:	2149      	movs	r1, #73	; 0x49
     45a:	f005 fcf0 	bl	5e3e <z_log_minimal_printk>
        rc = boot_console_init();
     45e:	f001 fd2d 	bl	1ebc <boot_console_init>
        __ASSERT(rc == 0, "Error initializing boot console.\n");
        boot_serial_start(&boot_funcs);
     462:	482d      	ldr	r0, [pc, #180]	; (518 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x30>)
     464:	f002 f892 	bl	258c <boot_serial_start>
        __ASSERT(0, "Bootloader serial process was terminated unexpectedly.\n");
    }
#endif
	BOOT_LOG_INF("pin pass");
     468:	482c      	ldr	r0, [pc, #176]	; (51c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x34>)
     46a:	2149      	movs	r1, #73	; 0x49
     46c:	f005 fce7 	bl	5e3e <z_log_minimal_printk>

00000470 <FIH_LABEL_FIH_CALL_START_589>:
    rc = boot_console_init();
    int timeout_in_ms = CONFIG_BOOT_SERIAL_WAIT_FOR_DFU_TIMEOUT;
    uint32_t start = k_uptime_get_32();
#endif

    FIH_CALL(boot_go, fih_rc, &rsp);
     470:	a803      	add	r0, sp, #12
     472:	f000 fceb 	bl	e4c <boot_go>

00000476 <FIH_LABEL_FIH_CALL_END_602>:
        timeout_in_ms = 1;
    }
   boot_serial_check_start(&boot_funcs,timeout_in_ms);
#endif

    if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     476:	4b2a      	ldr	r3, [pc, #168]	; (520 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x38>)
     478:	681b      	ldr	r3, [r3, #0]
     47a:	4283      	cmp	r3, r0
     47c:	d004      	beq.n	488 <FIH_LABEL_FIH_CALL_END_602+0x12>
        BOOT_LOG_ERR("Unable to find bootable image");
     47e:	4829      	ldr	r0, [pc, #164]	; (524 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x3c>)
     480:	2145      	movs	r1, #69	; 0x45
     482:	f005 fcdc 	bl	5e3e <z_log_minimal_printk>
        FIH_PANIC;
     486:	e7fe      	b.n	486 <FIH_LABEL_FIH_CALL_END_602+0x10>
    }

    BOOT_LOG_INF("Bootloader chainload address offset: 0x%x",
     488:	9a05      	ldr	r2, [sp, #20]
     48a:	4827      	ldr	r0, [pc, #156]	; (528 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x40>)
     48c:	2149      	movs	r1, #73	; 0x49
     48e:	f005 fcd6 	bl	5e3e <z_log_minimal_printk>
                 rsp.br_image_off);

#if defined(MCUBOOT_DIRECT_XIP)
    BOOT_LOG_INF("Jumping to the image slot");
#else
    BOOT_LOG_INF("Jumping to the first image slot");
     492:	4826      	ldr	r0, [pc, #152]	; (52c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x44>)
     494:	2149      	movs	r1, #73	; 0x49
     496:	f005 fcd2 	bl	5e3e <z_log_minimal_printk>
/* There is only one instance of MCUBoot */
#define PROTECT_SIZE (PM_MCUBOOT_PRIMARY_ADDRESS - PM_MCUBOOT_ADDRESS)
#define PROTECT_ADDR PM_MCUBOOT_ADDRESS
#endif

    rc = fprotect_area(PROTECT_ADDR, PROTECT_SIZE);
     49a:	f44f 4140 	mov.w	r1, #49152	; 0xc000
     49e:	2000      	movs	r0, #0
     4a0:	f006 fbd7 	bl	6c52 <fprotect_area>

    if (rc != 0) {
     4a4:	b120      	cbz	r0, 4b0 <FIH_LABEL_FIH_CALL_END_602+0x3a>
        BOOT_LOG_ERR("Protect mcuboot flash failed, cancel startup.");
     4a6:	4822      	ldr	r0, [pc, #136]	; (530 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x48>)
     4a8:	2145      	movs	r1, #69	; 0x45
     4aa:	f005 fcc8 	bl	5e3e <z_log_minimal_printk>
        while (1)
     4ae:	e7fe      	b.n	4ae <FIH_LABEL_FIH_CALL_END_602+0x38>
    rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
     4b0:	a902      	add	r1, sp, #8
     4b2:	f89d 0010 	ldrb.w	r0, [sp, #16]
     4b6:	f000 f84b 	bl	550 <flash_device_base>
    vt = (struct arm_vector_table *)(flash_base +
     4ba:	9b02      	ldr	r3, [sp, #8]
     4bc:	9c05      	ldr	r4, [sp, #20]
     4be:	441c      	add	r4, r3
                                     rsp->br_hdr->ih_hdr_size);
     4c0:	9b03      	ldr	r3, [sp, #12]
     4c2:	891d      	ldrh	r5, [r3, #8]
    nrf_cleanup_peripheral();
     4c4:	f000 ff7e 	bl	13c4 <nrf_cleanup_peripheral>
                                     rsp->br_image_off +
     4c8:	1966      	adds	r6, r4, r5
		:
		: "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	unsigned int tmp;

	__asm__ volatile(
     4ca:	f04f 0220 	mov.w	r2, #32
     4ce:	f3ef 8311 	mrs	r3, BASEPRI
     4d2:	f382 8812 	msr	BASEPRI_MAX, r2
     4d6:	f3bf 8f6f 	isb	sy
  \details Assigns the given value to the Main Stack Pointer (MSP).
  \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
     4da:	5963      	ldr	r3, [r4, r5]
     4dc:	f383 8808 	msr	MSP, r3
    ((void (*)(void))vt->reset)();
     4e0:	6873      	ldr	r3, [r6, #4]
     4e2:	4798      	blx	r3

    ZEPHYR_BOOT_LOG_STOP();

    do_boot(&rsp);

    BOOT_LOG_ERR("Never should get here");
     4e4:	4813      	ldr	r0, [pc, #76]	; (534 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x4c>)
     4e6:	2145      	movs	r1, #69	; 0x45
     4e8:	f005 fca9 	bl	5e3e <z_log_minimal_printk>
    while (1)
     4ec:	e7fe      	b.n	4ec <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x4>
     4ee:	bf00      	nop
     4f0:	40010000 	.word	0x40010000
     4f4:	6e524635 	.word	0x6e524635
     4f8:	00008ca0 	.word	0x00008ca0
     4fc:	00008cb9 	.word	0x00008cb9
     500:	00008ccc 	.word	0x00008ccc
     504:	00008ceb 	.word	0x00008ceb
     508:	00008d01 	.word	0x00008d01
     50c:	00010010 	.word	0x00010010
     510:	00008d08 	.word	0x00008d08
     514:	00008d21 	.word	0x00008d21
     518:	00008998 	.word	0x00008998
     51c:	00008d45 	.word	0x00008d45
     520:	20000194 	.word	0x20000194
     524:	00008d53 	.word	0x00008d53
     528:	00008d76 	.word	0x00008d76
     52c:	00008da5 	.word	0x00008da5
     530:	00008dca 	.word	0x00008dca
     534:	00008dfd 	.word	0x00008dfd

00000538 <flash_device_get_binding>:
#endif

static const struct device *flash_dev;

const struct device *flash_device_get_binding(char *dev_name)
{
     538:	b510      	push	{r4, lr}
    if (!flash_dev) {
     53a:	4c04      	ldr	r4, [pc, #16]	; (54c <flash_device_get_binding+0x14>)
     53c:	6823      	ldr	r3, [r4, #0]
     53e:	b913      	cbnz	r3, 546 <flash_device_get_binding+0xe>
     540:	f004 ff96 	bl	5470 <z_impl_device_get_binding>
        flash_dev = device_get_binding(dev_name);
     544:	6020      	str	r0, [r4, #0]
    }
    return flash_dev;
}
     546:	6820      	ldr	r0, [r4, #0]
     548:	bd10      	pop	{r4, pc}
     54a:	bf00      	nop
     54c:	20000190 	.word	0x20000190

00000550 <flash_device_base>:

int flash_device_base(uint8_t fd_id, uintptr_t *ret)
{
     550:	b508      	push	{r3, lr}
    if (fd_id != FLASH_DEVICE_ID) {
     552:	4602      	mov	r2, r0
     554:	b138      	cbz	r0, 566 <flash_device_base+0x16>
        BOOT_LOG_ERR("invalid flash ID %d; expected %d",
     556:	4805      	ldr	r0, [pc, #20]	; (56c <flash_device_base+0x1c>)
     558:	2300      	movs	r3, #0
     55a:	2145      	movs	r1, #69	; 0x45
     55c:	f005 fc6f 	bl	5e3e <z_log_minimal_printk>
                     fd_id, FLASH_DEVICE_ID);
        return -EINVAL;
     560:	f06f 0015 	mvn.w	r0, #21
    }
    *ret = FLASH_DEVICE_BASE;
    return 0;
}
     564:	bd08      	pop	{r3, pc}
    *ret = FLASH_DEVICE_BASE;
     566:	6008      	str	r0, [r1, #0]
    return 0;
     568:	e7fc      	b.n	564 <flash_device_base+0x14>
     56a:	bf00      	nop
     56c:	00008e20 	.word	0x00008e20

00000570 <flash_area_sector_from_off>:
    return -EINVAL;
}
#endif

int flash_area_sector_from_off(off_t off, struct flash_sector *sector)
{
     570:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    int rc;
    struct flash_pages_info page;

    rc = flash_get_page_info_by_offs(flash_dev, off, &page);
     572:	4a07      	ldr	r2, [pc, #28]	; (590 <flash_area_sector_from_off+0x20>)
{
     574:	4603      	mov	r3, r0
     576:	460c      	mov	r4, r1
    rc = flash_get_page_info_by_offs(flash_dev, off, &page);
     578:	6810      	ldr	r0, [r2, #0]
		union { uintptr_t x; struct flash_pages_info * val; } parm2 = { .val = info };
		return (int) arch_syscall_invoke3(parm0.x, parm1.x, parm2.x, K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS);
	}
#endif
	compiler_barrier();
	return z_impl_flash_get_page_info_by_offs(dev, offset, info);
     57a:	aa01      	add	r2, sp, #4
     57c:	4619      	mov	r1, r3
     57e:	f006 f8f5 	bl	676c <z_impl_flash_get_page_info_by_offs>
    if (rc) {
     582:	b918      	cbnz	r0, 58c <flash_area_sector_from_off+0x1c>
        return rc;
    }

    sector->fs_off = page.start_offset;
     584:	9b01      	ldr	r3, [sp, #4]
     586:	6023      	str	r3, [r4, #0]
    sector->fs_size = page.size;
     588:	9b02      	ldr	r3, [sp, #8]
     58a:	6063      	str	r3, [r4, #4]

    return rc;
}
     58c:	b004      	add	sp, #16
     58e:	bd10      	pop	{r4, pc}
     590:	20000190 	.word	0x20000190

00000594 <os_heap_init>:
/*
 * Initialize mbedtls to be able to use the local heap.
 */
void os_heap_init(void)
{
    mbedtls_memory_buffer_alloc_init(mempool, sizeof(mempool));
     594:	4802      	ldr	r0, [pc, #8]	; (5a0 <os_heap_init+0xc>)
     596:	f44f 51c0 	mov.w	r1, #6144	; 0x1800
     59a:	f003 bedf 	b.w	435c <mbedtls_memory_buffer_alloc_init>
     59e:	bf00      	nop
     5a0:	20001396 	.word	0x20001396

000005a4 <bootutil_img_validate>:
fih_int
bootutil_img_validate(struct enc_key_data *enc_state, int image_index,
                      struct image_header *hdr, const struct flash_area *fap,
                      uint8_t *tmp_buf, uint32_t tmp_buf_sz, uint8_t *seed,
                      int seed_len, uint8_t *out_hash)
{
     5a4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     5a8:	b0f9      	sub	sp, #484	; 0x1e4
     5aa:	e9dd 4884 	ldrd	r4, r8, [sp, #528]	; 0x210
    uint32_t off;
    uint16_t len;
    uint16_t type;
    int sha256_valid = 0;
#ifdef EXPECTED_SIG_TLV
    fih_int valid_signature = FIH_FAILURE;
     5ae:	f8df a1e8 	ldr.w	sl, [pc, #488]	; 798 <FIH_LABEL_FIH_CALL_END_646+0x2e>
#if defined(MCUBOOT_USE_MBED_TLS)
typedef mbedtls_sha256_context bootutil_sha256_context;

static inline void bootutil_sha256_init(bootutil_sha256_context *ctx)
{
    mbedtls_sha256_init(ctx);
     5b2:	a838      	add	r0, sp, #224	; 0xe0
     5b4:	f8da 6000 	ldr.w	r6, [sl]
{
     5b8:	4617      	mov	r7, r2
     5ba:	461d      	mov	r5, r3
     5bc:	f007 ff33 	bl	8426 <mbedtls_sha256_init>
    (void)mbedtls_sha256_starts_ret(ctx, 0);
     5c0:	2100      	movs	r1, #0
     5c2:	a838      	add	r0, sp, #224	; 0xe0
     5c4:	f003 ffda 	bl	457c <mbedtls_sha256_starts>
    if (seed && (seed_len > 0)) {
     5c8:	b13c      	cbz	r4, 5da <bootutil_img_validate+0x36>
     5ca:	f1b8 0f00 	cmp.w	r8, #0
     5ce:	dd04      	ble.n	5da <bootutil_img_validate+0x36>

static inline int bootutil_sha256_update(bootutil_sha256_context *ctx,
                                         const void *data,
                                         uint32_t data_len)
{
    return mbedtls_sha256_update_ret(ctx, data, data_len);
     5d0:	4642      	mov	r2, r8
     5d2:	4621      	mov	r1, r4
     5d4:	a838      	add	r0, sp, #224	; 0xe0
     5d6:	f007 ff2a 	bl	842e <mbedtls_sha256_update>
    size += hdr->ih_protect_tlv_size;
     5da:	897b      	ldrh	r3, [r7, #10]
    size = hdr_size = hdr->ih_hdr_size;
     5dc:	f8b7 8008 	ldrh.w	r8, [r7, #8]
     5e0:	4498      	add	r8, r3
    size += hdr->ih_protect_tlv_size;
     5e2:	68fb      	ldr	r3, [r7, #12]
    for (off = 0; off < size; off += blk_sz) {
     5e4:	f04f 0900 	mov.w	r9, #0
    size += hdr->ih_protect_tlv_size;
     5e8:	4498      	add	r8, r3
    for (off = 0; off < size; off += blk_sz) {
     5ea:	45c8      	cmp	r8, r9
     5ec:	d84b      	bhi.n	686 <FIH_LABEL_FIH_CALL_END_311+0x10>
}

static inline int bootutil_sha256_finish(bootutil_sha256_context *ctx,
                                          uint8_t *output)
{
    return mbedtls_sha256_finish_ret(ctx, output);
     5ee:	a90d      	add	r1, sp, #52	; 0x34
     5f0:	a838      	add	r0, sp, #224	; 0xe0
     5f2:	f007 ff59 	bl	84a8 <mbedtls_sha256_finish>
            tmp_buf_sz, hash, seed, seed_len);
    if (rc) {
        goto out;
    }

    if (out_hash) {
     5f6:	9b86      	ldr	r3, [sp, #536]	; 0x218
     5f8:	b123      	cbz	r3, 604 <CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN+0x28>
        memcpy(out_hash, hash, 32);
     5fa:	2220      	movs	r2, #32
     5fc:	a90d      	add	r1, sp, #52	; 0x34
     5fe:	4618      	mov	r0, r3
     600:	f005 ff74 	bl	64ec <memcpy>
    }

    rc = bootutil_tlv_iter_begin(&it, hdr, fap, IMAGE_TLV_ANY, false);
     604:	2300      	movs	r3, #0
     606:	9300      	str	r3, [sp, #0]
     608:	462a      	mov	r2, r5
     60a:	f64f 73ff 	movw	r3, #65535	; 0xffff
     60e:	4639      	mov	r1, r7
     610:	a807      	add	r0, sp, #28
     612:	f005 f8be 	bl	5792 <bootutil_tlv_iter_begin>
    if (rc) {
     616:	4604      	mov	r4, r0
     618:	2800      	cmp	r0, #0
     61a:	f040 80b6 	bne.w	78a <FIH_LABEL_FIH_CALL_END_646+0x20>
             * can be multiple signatures, each preceded by a key.
             */
#endif /* !MCUBOOT_HW_KEY */
        } else if (type == EXPECTED_SIG_TLV) {
            /* Ignore this signature if it is out of bounds. */
            if (key_id < 0 || key_id >= bootutil_key_cnt) {
     61e:	f8df 917c 	ldr.w	r9, [pc, #380]	; 79c <FIH_LABEL_FIH_CALL_END_646+0x32>
    int sha256_valid = 0;
     622:	4680      	mov	r8, r0
    int key_id = -1;
     624:	f04f 37ff 	mov.w	r7, #4294967295
        rc = bootutil_tlv_iter_next(&it, &off, &len, &type);
     628:	f10d 0316 	add.w	r3, sp, #22
     62c:	aa05      	add	r2, sp, #20
     62e:	a906      	add	r1, sp, #24
     630:	a807      	add	r0, sp, #28
     632:	f005 f8fa 	bl	582a <bootutil_tlv_iter_next>
        if (rc < 0) {
     636:	1e04      	subs	r4, r0, #0
     638:	f2c0 80a7 	blt.w	78a <FIH_LABEL_FIH_CALL_END_646+0x20>
        } else if (rc > 0) {
     63c:	f040 8098 	bne.w	770 <FIH_LABEL_FIH_CALL_END_646+0x6>
        if (type == IMAGE_TLV_SHA256) {
     640:	f8bd b016 	ldrh.w	fp, [sp, #22]
     644:	f1bb 0f10 	cmp.w	fp, #16
     648:	d134      	bne.n	6b4 <FIH_LABEL_FIH_CALL_END_311+0x3e>
            if (len != sizeof(hash)) {
     64a:	f8bd 8014 	ldrh.w	r8, [sp, #20]
     64e:	f1b8 0f20 	cmp.w	r8, #32
     652:	f040 8098 	bne.w	786 <FIH_LABEL_FIH_CALL_END_646+0x1c>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, sizeof(hash));
     656:	9906      	ldr	r1, [sp, #24]
     658:	4643      	mov	r3, r8
     65a:	aa38      	add	r2, sp, #224	; 0xe0
     65c:	4628      	mov	r0, r5
     65e:	f005 fbfc 	bl	5e5a <flash_area_read>
            if (rc) {
     662:	4604      	mov	r4, r0
     664:	2800      	cmp	r0, #0
     666:	f040 8090 	bne.w	78a <FIH_LABEL_FIH_CALL_END_646+0x20>

0000066a <FIH_LABEL_FIH_CALL_START_292>:
            FIH_CALL(boot_fih_memequal, fih_rc, hash, buf, sizeof(hash));
     66a:	4642      	mov	r2, r8
     66c:	a938      	add	r1, sp, #224	; 0xe0
     66e:	a80d      	add	r0, sp, #52	; 0x34
     670:	f005 f926 	bl	58c0 <boot_fih_memequal>
     674:	4604      	mov	r4, r0

00000676 <FIH_LABEL_FIH_CALL_END_311>:
            if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     676:	4b4a      	ldr	r3, [pc, #296]	; (7a0 <FIH_LABEL_FIH_CALL_END_646+0x36>)
     678:	681b      	ldr	r3, [r3, #0]
     67a:	4283      	cmp	r3, r0
     67c:	f040 8085 	bne.w	78a <FIH_LABEL_FIH_CALL_END_646+0x20>
            sha256_valid = 1;
     680:	f04f 0801 	mov.w	r8, #1
     684:	e7d0      	b.n	628 <CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN+0x4c>
        blk_sz = size - off;
     686:	f8dd b20c 	ldr.w	fp, [sp, #524]	; 0x20c
        rc = flash_area_read(fap, off, tmp_buf, blk_sz);
     68a:	9a82      	ldr	r2, [sp, #520]	; 0x208
        blk_sz = size - off;
     68c:	eba8 0309 	sub.w	r3, r8, r9
        if (blk_sz > tmp_buf_sz) {
     690:	459b      	cmp	fp, r3
     692:	bf28      	it	cs
     694:	469b      	movcs	fp, r3
        rc = flash_area_read(fap, off, tmp_buf, blk_sz);
     696:	465b      	mov	r3, fp
     698:	4649      	mov	r1, r9
     69a:	4628      	mov	r0, r5
     69c:	f005 fbdd 	bl	5e5a <flash_area_read>
        if (rc) {
     6a0:	4604      	mov	r4, r0
     6a2:	2800      	cmp	r0, #0
     6a4:	d171      	bne.n	78a <FIH_LABEL_FIH_CALL_END_646+0x20>
    return mbedtls_sha256_update_ret(ctx, data, data_len);
     6a6:	9982      	ldr	r1, [sp, #520]	; 0x208
     6a8:	465a      	mov	r2, fp
     6aa:	a838      	add	r0, sp, #224	; 0xe0
     6ac:	f007 febf 	bl	842e <mbedtls_sha256_update>
    for (off = 0; off < size; off += blk_sz) {
     6b0:	44d9      	add	r9, fp
     6b2:	e79a      	b.n	5ea <CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN+0xe>
        } else if (type == IMAGE_TLV_KEYHASH) {
     6b4:	f1bb 0f01 	cmp.w	fp, #1
     6b8:	d136      	bne.n	728 <FIH_LABEL_FIH_CALL_END_311+0xb2>
            if (len > 32) {
     6ba:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     6be:	2b20      	cmp	r3, #32
     6c0:	d861      	bhi.n	786 <FIH_LABEL_FIH_CALL_END_646+0x1c>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
     6c2:	9906      	ldr	r1, [sp, #24]
     6c4:	aa38      	add	r2, sp, #224	; 0xe0
     6c6:	4628      	mov	r0, r5
     6c8:	f005 fbc7 	bl	5e5a <flash_area_read>
            if (rc) {
     6cc:	4604      	mov	r4, r0
     6ce:	2800      	cmp	r0, #0
     6d0:	d15b      	bne.n	78a <FIH_LABEL_FIH_CALL_END_646+0x20>
            key_id = bootutil_find_key(buf, len);
     6d2:	f89d b014 	ldrb.w	fp, [sp, #20]
    if (keyhash_len > 32) {
     6d6:	f1bb 0f20 	cmp.w	fp, #32
     6da:	d903      	bls.n	6e4 <FIH_LABEL_FIH_CALL_END_311+0x6e>
        return -1;
     6dc:	f04f 34ff 	mov.w	r4, #4294967295
            key_id = bootutil_find_key(buf, len);
     6e0:	4627      	mov	r7, r4
     6e2:	e7a1      	b.n	628 <CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN+0x4c>
    for (i = 0; i < bootutil_key_cnt; i++) {
     6e4:	f8d9 3000 	ldr.w	r3, [r9]
     6e8:	4f2e      	ldr	r7, [pc, #184]	; (7a4 <FIH_LABEL_FIH_CALL_END_646+0x3a>)
     6ea:	9303      	str	r3, [sp, #12]
     6ec:	9b03      	ldr	r3, [sp, #12]
     6ee:	429c      	cmp	r4, r3
     6f0:	daf4      	bge.n	6dc <FIH_LABEL_FIH_CALL_END_311+0x66>
    mbedtls_sha256_init(ctx);
     6f2:	a81d      	add	r0, sp, #116	; 0x74
     6f4:	f007 fe97 	bl	8426 <mbedtls_sha256_init>
    (void)mbedtls_sha256_starts_ret(ctx, 0);
     6f8:	2100      	movs	r1, #0
     6fa:	a81d      	add	r0, sp, #116	; 0x74
     6fc:	f003 ff3e 	bl	457c <mbedtls_sha256_starts>
        bootutil_sha256_update(&sha256_ctx, key->key, *key->len);
     700:	687a      	ldr	r2, [r7, #4]
    return mbedtls_sha256_update_ret(ctx, data, data_len);
     702:	f857 1b08 	ldr.w	r1, [r7], #8
     706:	6812      	ldr	r2, [r2, #0]
     708:	a81d      	add	r0, sp, #116	; 0x74
     70a:	f007 fe90 	bl	842e <mbedtls_sha256_update>
    return mbedtls_sha256_finish_ret(ctx, output);
     70e:	a915      	add	r1, sp, #84	; 0x54
     710:	a81d      	add	r0, sp, #116	; 0x74
     712:	f007 fec9 	bl	84a8 <mbedtls_sha256_finish>
        if (!memcmp(hash, keyhash, keyhash_len)) {
     716:	465a      	mov	r2, fp
     718:	a938      	add	r1, sp, #224	; 0xe0
     71a:	a815      	add	r0, sp, #84	; 0x54
     71c:	f005 febd 	bl	649a <memcmp>
     720:	2800      	cmp	r0, #0
     722:	d0dd      	beq.n	6e0 <FIH_LABEL_FIH_CALL_END_311+0x6a>
    for (i = 0; i < bootutil_key_cnt; i++) {
     724:	3401      	adds	r4, #1
     726:	e7e1      	b.n	6ec <FIH_LABEL_FIH_CALL_END_311+0x76>
        } else if (type == EXPECTED_SIG_TLV) {
     728:	f1bb 0f20 	cmp.w	fp, #32
     72c:	f47f af7c 	bne.w	628 <CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN+0x4c>
            if (key_id < 0 || key_id >= bootutil_key_cnt) {
     730:	1c7b      	adds	r3, r7, #1
     732:	f43f af79 	beq.w	628 <CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN+0x4c>
     736:	f8d9 3000 	ldr.w	r3, [r9]
     73a:	42bb      	cmp	r3, r7
     73c:	dd15      	ble.n	76a <FIH_LABEL_FIH_CALL_END_646>
                key_id = -1;
                continue;
            }
            if (!EXPECTED_SIG_LEN(len) || len > sizeof(buf)) {
     73e:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     742:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
     746:	d11e      	bne.n	786 <FIH_LABEL_FIH_CALL_END_646+0x1c>
                rc = -1;
                goto out;
            }
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
     748:	9906      	ldr	r1, [sp, #24]
     74a:	aa38      	add	r2, sp, #224	; 0xe0
     74c:	4628      	mov	r0, r5
     74e:	f005 fb84 	bl	5e5a <flash_area_read>
            if (rc) {
     752:	4604      	mov	r4, r0
     754:	b9c8      	cbnz	r0, 78a <FIH_LABEL_FIH_CALL_END_646+0x20>

00000756 <FIH_LABEL_FIH_CALL_START_624>:
                goto out;
            }
            FIH_CALL(bootutil_verify_sig, valid_signature, hash, sizeof(hash),
     756:	b2ff      	uxtb	r7, r7
     758:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     75c:	9700      	str	r7, [sp, #0]
     75e:	aa38      	add	r2, sp, #224	; 0xe0
     760:	4659      	mov	r1, fp
     762:	a80d      	add	r0, sp, #52	; 0x34
     764:	f000 f820 	bl	7a8 <bootutil_verify_sig>
     768:	4606      	mov	r6, r0

0000076a <FIH_LABEL_FIH_CALL_END_646>:
                key_id = -1;
     76a:	f04f 37ff 	mov.w	r7, #4294967295
     76e:	e75b      	b.n	628 <CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN+0x4c>
#endif /* MCUBOOT_HW_ROLLBACK_PROT */
        }
    }

    rc = !sha256_valid;
    if (rc) {
     770:	f1b8 0f00 	cmp.w	r8, #0
     774:	d00d      	beq.n	792 <FIH_LABEL_FIH_CALL_END_646+0x28>
        goto out;
    }
#ifdef EXPECTED_SIG_TLV
    fih_rc = fih_int_encode_zero_equality(fih_not_eq(valid_signature,
     776:	4b0a      	ldr	r3, [pc, #40]	; (7a0 <FIH_LABEL_FIH_CALL_END_646+0x36>)
 * value that is not FIH_SUCCESS
 */
__attribute__((always_inline)) inline
fih_int fih_int_encode_zero_equality(int x)
{
    if (x) {
     778:	681b      	ldr	r3, [r3, #0]
     77a:	42b3      	cmp	r3, r6
     77c:	d001      	beq.n	782 <FIH_LABEL_FIH_CALL_END_646+0x18>
        return FIH_FAILURE;
     77e:	f8da 6000 	ldr.w	r6, [sl]
                rc = -1;
     782:	4634      	mov	r4, r6
     784:	e001      	b.n	78a <FIH_LABEL_FIH_CALL_END_646+0x20>
     786:	f04f 34ff 	mov.w	r4, #4294967295
    if (rc) {
        fih_rc = fih_int_encode(rc);
    }

    FIH_RET(fih_rc);
}
     78a:	4620      	mov	r0, r4
     78c:	b079      	add	sp, #484	; 0x1e4
     78e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
     792:	2401      	movs	r4, #1
    FIH_RET(fih_rc);
     794:	e7f9      	b.n	78a <FIH_LABEL_FIH_CALL_END_646+0x20>
     796:	bf00      	nop
     798:	20000000 	.word	0x20000000
     79c:	000089a0 	.word	0x000089a0
     7a0:	20000194 	.word	0x20000194
     7a4:	000089a4 	.word	0x000089a4

000007a8 <bootutil_verify_sig>:
}

fih_int
bootutil_verify_sig(uint8_t *hash, uint32_t hlen, uint8_t *sig, size_t slen,
  uint8_t key_id)
{
     7a8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     7ac:	4698      	mov	r8, r3
     7ae:	f5ad 7d4b 	sub.w	sp, sp, #812	; 0x32c
    mbedtls_rsa_context ctx;
    int rc;
    fih_int fih_rc = FIH_FAILURE;
     7b2:	4b6b      	ldr	r3, [pc, #428]	; (960 <FIH_LABEL_FIH_CALL_END_672+0x4>)
{
     7b4:	f89d 6350 	ldrb.w	r6, [sp, #848]	; 0x350
    fih_int fih_rc = FIH_FAILURE;
     7b8:	681d      	ldr	r5, [r3, #0]
{
     7ba:	4607      	mov	r7, r0
    uint8_t *cp;
    uint8_t *end;

#if MBEDTLS_VERSION_NUMBER >= 0x03000000
    mbedtls_rsa_init(&ctx);
     7bc:	a827      	add	r0, sp, #156	; 0x9c
{
     7be:	468a      	mov	sl, r1
     7c0:	4691      	mov	r9, r2
    mbedtls_rsa_init(&ctx);
     7c2:	f007 fded 	bl	83a0 <mbedtls_rsa_init>
#else
    mbedtls_rsa_init(&ctx, 0, 0);
#endif

    cp = (uint8_t *)bootutil_keys[key_id].key;
     7c6:	4b67      	ldr	r3, [pc, #412]	; (964 <FIH_LABEL_FIH_CALL_END_672+0x8>)
     7c8:	f853 4036 	ldr.w	r4, [r3, r6, lsl #3]
     7cc:	9402      	str	r4, [sp, #8]
    end = cp + *bootutil_keys[key_id].len;
     7ce:	eb03 03c6 	add.w	r3, r3, r6, lsl #3
    if ((rc = mbedtls_asn1_get_tag(p, end, &len,
     7d2:	aa8a      	add	r2, sp, #552	; 0x228
    end = cp + *bootutil_keys[key_id].len;
     7d4:	685b      	ldr	r3, [r3, #4]
     7d6:	6819      	ldr	r1, [r3, #0]
     7d8:	440c      	add	r4, r1
    if ((rc = mbedtls_asn1_get_tag(p, end, &len,
     7da:	2330      	movs	r3, #48	; 0x30
     7dc:	4621      	mov	r1, r4
     7de:	a802      	add	r0, sp, #8
     7e0:	f006 fb74 	bl	6ecc <mbedtls_asn1_get_tag>
     7e4:	bb68      	cbnz	r0, 842 <CONFIG_BOOT_SIGNATURE_TYPE_RSA_LEN+0x42>
    if (*p + len != end) {
     7e6:	9b02      	ldr	r3, [sp, #8]
     7e8:	9a8a      	ldr	r2, [sp, #552]	; 0x228
     7ea:	4413      	add	r3, r2
     7ec:	429c      	cmp	r4, r3
     7ee:	d128      	bne.n	842 <CONFIG_BOOT_SIGNATURE_TYPE_RSA_LEN+0x42>
    if ((rc = mbedtls_asn1_get_mpi(p, end, &ctx->MBEDTLS_CONTEXT_MEMBER(N))) != 0 ||
     7f0:	aa29      	add	r2, sp, #164	; 0xa4
     7f2:	4621      	mov	r1, r4
     7f4:	a802      	add	r0, sp, #8
     7f6:	f006 fb7d 	bl	6ef4 <mbedtls_asn1_get_mpi>
     7fa:	bb10      	cbnz	r0, 842 <CONFIG_BOOT_SIGNATURE_TYPE_RSA_LEN+0x42>
        (rc = mbedtls_asn1_get_mpi(p, end, &ctx->MBEDTLS_CONTEXT_MEMBER(E))) != 0) {
     7fc:	f10d 0bb0 	add.w	fp, sp, #176	; 0xb0
     800:	465a      	mov	r2, fp
     802:	4621      	mov	r1, r4
     804:	a802      	add	r0, sp, #8
     806:	f006 fb75 	bl	6ef4 <mbedtls_asn1_get_mpi>
    if ((rc = mbedtls_asn1_get_mpi(p, end, &ctx->MBEDTLS_CONTEXT_MEMBER(N))) != 0 ||
     80a:	4606      	mov	r6, r0
     80c:	b9c8      	cbnz	r0, 842 <CONFIG_BOOT_SIGNATURE_TYPE_RSA_LEN+0x42>
    ctx->MBEDTLS_CONTEXT_MEMBER(len) = mbedtls_mpi_size(&ctx->MBEDTLS_CONTEXT_MEMBER(N));
     80e:	a829      	add	r0, sp, #164	; 0xa4
     810:	f006 fed0 	bl	75b4 <mbedtls_mpi_size>
    if (*p != end) {
     814:	9b02      	ldr	r3, [sp, #8]
    ctx->MBEDTLS_CONTEXT_MEMBER(len) = mbedtls_mpi_size(&ctx->MBEDTLS_CONTEXT_MEMBER(N));
     816:	9028      	str	r0, [sp, #160]	; 0xa0
    if (*p != end) {
     818:	429c      	cmp	r4, r3
     81a:	d112      	bne.n	842 <CONFIG_BOOT_SIGNATURE_TYPE_RSA_LEN+0x42>
    rc = mbedtls_rsa_import(ctx, &ctx->MBEDTLS_CONTEXT_MEMBER(N), NULL,
     81c:	e9cd 6b00 	strd	r6, fp, [sp]
     820:	4633      	mov	r3, r6
     822:	4632      	mov	r2, r6
     824:	a929      	add	r1, sp, #164	; 0xa4
     826:	a827      	add	r0, sp, #156	; 0x9c
     828:	f007 fd76 	bl	8318 <mbedtls_rsa_import>
    if (rc != 0) {
     82c:	b948      	cbnz	r0, 842 <CONFIG_BOOT_SIGNATURE_TYPE_RSA_LEN+0x42>
    rc = mbedtls_rsa_check_pubkey(ctx);
     82e:	a827      	add	r0, sp, #156	; 0x9c
     830:	f003 fe42 	bl	44b8 <mbedtls_rsa_check_pubkey>
    if (rc != 0) {
     834:	b928      	cbnz	r0, 842 <CONFIG_BOOT_SIGNATURE_TYPE_RSA_LEN+0x42>
    ctx->MBEDTLS_CONTEXT_MEMBER(len) = mbedtls_mpi_size(&ctx->MBEDTLS_CONTEXT_MEMBER(N));
     836:	a829      	add	r0, sp, #164	; 0xa4
     838:	f006 febc 	bl	75b4 <mbedtls_mpi_size>

    rc = bootutil_parse_rsakey(&ctx, &cp, end);
    if (rc || slen != ctx.MBEDTLS_CONTEXT_MEMBER(len)) {
     83c:	4580      	cmp	r8, r0
    ctx->MBEDTLS_CONTEXT_MEMBER(len) = mbedtls_mpi_size(&ctx->MBEDTLS_CONTEXT_MEMBER(N));
     83e:	9028      	str	r0, [sp, #160]	; 0xa0
    if (rc || slen != ctx.MBEDTLS_CONTEXT_MEMBER(len)) {
     840:	d00a      	beq.n	858 <FIH_LABEL_FIH_CALL_START_226>
        mbedtls_rsa_free(&ctx);
     842:	a827      	add	r0, sp, #156	; 0x9c
     844:	f007 fdb6 	bl	83b4 <mbedtls_rsa_free>
        goto out;
    }
    FIH_CALL(bootutil_cmp_rsasig, fih_rc, &ctx, hash, hlen, sig);

out:
    mbedtls_rsa_free(&ctx);
     848:	a827      	add	r0, sp, #156	; 0x9c
     84a:	f007 fdb3 	bl	83b4 <mbedtls_rsa_free>

    FIH_RET(fih_rc);
}
     84e:	4628      	mov	r0, r5
     850:	f50d 7d4b 	add.w	sp, sp, #812	; 0x32c
     854:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}

00000858 <FIH_LABEL_FIH_CALL_START_226>:
    if (ctx->MBEDTLS_CONTEXT_MEMBER(len) != PSS_EMLEN ||
     858:	f5b8 7f80 	cmp.w	r8, #256	; 0x100
     85c:	d002      	beq.n	864 <FIH_LABEL_FIH_CALL_END_287+0x2>
     85e:	f04f 35ff 	mov.w	r5, #4294967295

00000862 <FIH_LABEL_FIH_CALL_END_287>:
    FIH_CALL(bootutil_cmp_rsasig, fih_rc, &ctx, hash, hlen, sig);
     862:	e7f1      	b.n	848 <CONFIG_BOOT_SIGNATURE_TYPE_RSA_LEN+0x48>
    if (hlen != PSS_HLEN) {
     864:	f1ba 0f20 	cmp.w	sl, #32
     868:	d1f9      	bne.n	85e <FIH_LABEL_FIH_CALL_START_226+0x6>
    if (mbedtls_rsa_public(ctx, sig, em)) {
     86a:	aa8a      	add	r2, sp, #552	; 0x228
     86c:	4649      	mov	r1, r9
     86e:	a827      	add	r0, sp, #156	; 0x9c
     870:	f003 fe46 	bl	4500 <mbedtls_rsa_public>
     874:	4604      	mov	r4, r0
     876:	2800      	cmp	r0, #0
     878:	d1f1      	bne.n	85e <FIH_LABEL_FIH_CALL_START_226+0x6>
    if (em[PSS_EMLEN - 1] != 0xbc) {
     87a:	f89d 3327 	ldrb.w	r3, [sp, #807]	; 0x327
     87e:	2bbc      	cmp	r3, #188	; 0xbc
     880:	d1ed      	bne.n	85e <FIH_LABEL_FIH_CALL_START_226+0x6>
    uint8_t counter[4] = { 0, 0, 0, 0 };
     882:	f50d 78a4 	add.w	r8, sp, #328	; 0x148
     886:	9003      	str	r0, [sp, #12]
    int count = PSS_MASK_LEN;
     888:	26df      	movs	r6, #223	; 0xdf
     88a:	4645      	mov	r5, r8
    mbedtls_sha256_init(ctx);
     88c:	a80c      	add	r0, sp, #48	; 0x30
     88e:	f007 fdca 	bl	8426 <mbedtls_sha256_init>
    (void)mbedtls_sha256_starts_ret(ctx, 0);
     892:	2100      	movs	r1, #0
     894:	a80c      	add	r0, sp, #48	; 0x30
     896:	f003 fe71 	bl	457c <mbedtls_sha256_starts>
    return mbedtls_sha256_update_ret(ctx, data, data_len);
     89a:	2220      	movs	r2, #32
     89c:	f20d 3107 	addw	r1, sp, #775	; 0x307
     8a0:	a80c      	add	r0, sp, #48	; 0x30
     8a2:	f007 fdc4 	bl	842e <mbedtls_sha256_update>
     8a6:	2204      	movs	r2, #4
     8a8:	a903      	add	r1, sp, #12
     8aa:	a80c      	add	r0, sp, #48	; 0x30
     8ac:	f007 fdbf 	bl	842e <mbedtls_sha256_update>
    return mbedtls_sha256_finish_ret(ctx, output);
     8b0:	a904      	add	r1, sp, #16
     8b2:	a80c      	add	r0, sp, #48	; 0x30
     8b4:	f007 fdf8 	bl	84a8 <mbedtls_sha256_finish>
        if (bytes > count)
     8b8:	2e1f      	cmp	r6, #31
        counter[3]++;
     8ba:	f89d 300f 	ldrb.w	r3, [sp, #15]
        if (bytes > count)
     8be:	bfd4      	ite	le
     8c0:	46b1      	movle	r9, r6
     8c2:	f04f 0920 	movgt.w	r9, #32
        counter[3]++;
     8c6:	3301      	adds	r3, #1
        memcpy(mask, htmp, bytes);
     8c8:	4640      	mov	r0, r8
     8ca:	464a      	mov	r2, r9
     8cc:	a904      	add	r1, sp, #16
        count -= bytes;
     8ce:	eba6 0609 	sub.w	r6, r6, r9
        counter[3]++;
     8d2:	f88d 300f 	strb.w	r3, [sp, #15]
        memcpy(mask, htmp, bytes);
     8d6:	f005 fe09 	bl	64ec <memcpy>
    while (count > 0) {
     8da:	2e00      	cmp	r6, #0
        mask += bytes;
     8dc:	44c8      	add	r8, r9
    while (count > 0) {
     8de:	dcd5      	bgt.n	88c <FIH_LABEL_FIH_CALL_END_287+0x2a>
    for (i = 0; i < PSS_MASK_LEN; i++) {
     8e0:	4628      	mov	r0, r5
     8e2:	ae8a      	add	r6, sp, #552	; 0x228
     8e4:	462a      	mov	r2, r5
     8e6:	23df      	movs	r3, #223	; 0xdf
        db_mask[i] ^= em[i];
     8e8:	7811      	ldrb	r1, [r2, #0]
     8ea:	f816 cb01 	ldrb.w	ip, [r6], #1
    for (i = 0; i < PSS_MASK_LEN; i++) {
     8ee:	3b01      	subs	r3, #1
        db_mask[i] ^= em[i];
     8f0:	ea81 010c 	eor.w	r1, r1, ip
     8f4:	f802 1b01 	strb.w	r1, [r2], #1
    for (i = 0; i < PSS_MASK_LEN; i++) {
     8f8:	d1f6      	bne.n	8e8 <FIH_LABEL_FIH_CALL_END_287+0x86>
    db_mask[0] &= 0x7F;
     8fa:	782b      	ldrb	r3, [r5, #0]
     8fc:	f003 037f 	and.w	r3, r3, #127	; 0x7f
     900:	702b      	strb	r3, [r5, #0]
        if (db_mask[i] != 0) {
     902:	f810 6b01 	ldrb.w	r6, [r0], #1
     906:	2e00      	cmp	r6, #0
     908:	d1a9      	bne.n	85e <FIH_LABEL_FIH_CALL_START_226+0x6>
    for (i = 0; i < PSS_MASK_ZERO_COUNT; i++) {
     90a:	3401      	adds	r4, #1
     90c:	2cbe      	cmp	r4, #190	; 0xbe
     90e:	d1f8      	bne.n	902 <FIH_LABEL_FIH_CALL_END_287+0xa0>
    if (db_mask[PSS_MASK_ONE_POS] != 1) {
     910:	f895 30be 	ldrb.w	r3, [r5, #190]	; 0xbe
     914:	2b01      	cmp	r3, #1
     916:	d1a2      	bne.n	85e <FIH_LABEL_FIH_CALL_START_226+0x6>
    mbedtls_sha256_init(ctx);
     918:	a80c      	add	r0, sp, #48	; 0x30
     91a:	f007 fd84 	bl	8426 <mbedtls_sha256_init>
    (void)mbedtls_sha256_starts_ret(ctx, 0);
     91e:	4631      	mov	r1, r6
     920:	a80c      	add	r0, sp, #48	; 0x30
     922:	f003 fe2b 	bl	457c <mbedtls_sha256_starts>
    return mbedtls_sha256_update_ret(ctx, data, data_len);
     926:	4910      	ldr	r1, [pc, #64]	; (968 <FIH_LABEL_FIH_CALL_END_672+0xc>)
     928:	2208      	movs	r2, #8
     92a:	a80c      	add	r0, sp, #48	; 0x30
     92c:	f007 fd7f 	bl	842e <mbedtls_sha256_update>
     930:	4639      	mov	r1, r7
     932:	2220      	movs	r2, #32
     934:	a80c      	add	r0, sp, #48	; 0x30
     936:	f007 fd7a 	bl	842e <mbedtls_sha256_update>
     93a:	2220      	movs	r2, #32
     93c:	f20d 2107 	addw	r1, sp, #519	; 0x207
     940:	a80c      	add	r0, sp, #48	; 0x30
     942:	f007 fd74 	bl	842e <mbedtls_sha256_update>
    return mbedtls_sha256_finish_ret(ctx, output);
     946:	a904      	add	r1, sp, #16
     948:	a80c      	add	r0, sp, #48	; 0x30
     94a:	f007 fdad 	bl	84a8 <mbedtls_sha256_finish>

0000094e <FIH_LABEL_FIH_CALL_START_651>:
    FIH_CALL(boot_fih_memequal, fih_rc, h2, &em[PSS_HASH_OFFSET], PSS_HLEN);
     94e:	2220      	movs	r2, #32
     950:	f20d 3107 	addw	r1, sp, #775	; 0x307
     954:	a804      	add	r0, sp, #16
     956:	f004 ffb3 	bl	58c0 <boot_fih_memequal>
     95a:	4605      	mov	r5, r0

0000095c <FIH_LABEL_FIH_CALL_END_672>:
    if (rc) {
     95c:	e781      	b.n	862 <FIH_LABEL_FIH_CALL_END_287>
     95e:	bf00      	nop
     960:	20000000 	.word	0x20000000
     964:	000089a4 	.word	0x000089a4
     968:	00008e46 	.word	0x00008e46

0000096c <boot_read_swap_size>:
    return -1;
}

int
boot_read_swap_size(int image_index, uint32_t *swap_size)
{
     96c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
     970:	b086      	sub	sp, #24
    uint8_t areas[2] = {
     972:	2302      	movs	r3, #2
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
     974:	f8df 806c 	ldr.w	r8, [pc, #108]	; 9e4 <boot_read_swap_size+0x78>
    uint8_t areas[2] = {
     978:	f8ad 3000 	strh.w	r3, [sp]
{
     97c:	460d      	mov	r5, r1
     97e:	466f      	mov	r7, sp
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     980:	2600      	movs	r6, #0
        rc = flash_area_open(areas[i], fap);
     982:	f817 0b01 	ldrb.w	r0, [r7], #1
     986:	a901      	add	r1, sp, #4
     988:	f001 f9a0 	bl	1ccc <flash_area_open>
        if (rc != 0) {
     98c:	4604      	mov	r4, r0
     98e:	b9a0      	cbnz	r0, 9ba <boot_read_swap_size+0x4e>
        off = boot_magic_off(*fap);
     990:	9801      	ldr	r0, [sp, #4]
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
     992:	6881      	ldr	r1, [r0, #8]
        rc = flash_area_read(*fap, off, magic, BOOT_MAGIC_SZ);
     994:	2310      	movs	r3, #16
     996:	aa02      	add	r2, sp, #8
     998:	3910      	subs	r1, #16
     99a:	f005 fa5e 	bl	5e5a <flash_area_read>
     99e:	4604      	mov	r4, r0
        flash_area_close(*fap);
     9a0:	9801      	ldr	r0, [sp, #4]
     9a2:	f005 fa59 	bl	5e58 <flash_area_close>
        if (rc != 0) {
     9a6:	b944      	cbnz	r4, 9ba <boot_read_swap_size+0x4e>
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
     9a8:	2210      	movs	r2, #16
     9aa:	4641      	mov	r1, r8
     9ac:	a802      	add	r0, sp, #8
     9ae:	f005 fd74 	bl	649a <memcmp>
     9b2:	b140      	cbz	r0, 9c6 <boot_read_swap_size+0x5a>
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     9b4:	b12e      	cbz	r6, 9c2 <boot_read_swap_size+0x56>
    return -1;
     9b6:	f04f 34ff 	mov.w	r4, #4294967295
        rc = flash_area_read(fap, off, swap_size, sizeof *swap_size);
        flash_area_close(fap);
    }

    return rc;
}
     9ba:	4620      	mov	r0, r4
     9bc:	b006      	add	sp, #24
     9be:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
     9c2:	2601      	movs	r6, #1
     9c4:	e7dd      	b.n	982 <boot_read_swap_size+0x16>
    return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
     9c6:	9801      	ldr	r0, [sp, #4]
     9c8:	f006 f997 	bl	6cfa <boot_swap_info_off>
        rc = flash_area_read(fap, off, swap_size, sizeof *swap_size);
     9cc:	2304      	movs	r3, #4
     9ce:	f1a0 0108 	sub.w	r1, r0, #8
     9d2:	462a      	mov	r2, r5
     9d4:	9801      	ldr	r0, [sp, #4]
     9d6:	f005 fa40 	bl	5e5a <flash_area_read>
     9da:	4604      	mov	r4, r0
        flash_area_close(fap);
     9dc:	9801      	ldr	r0, [sp, #4]
     9de:	f005 fa3b 	bl	5e58 <flash_area_close>
     9e2:	e7ea      	b.n	9ba <boot_read_swap_size+0x4e>
     9e4:	00008c90 	.word	0x00008c90

000009e8 <boot_validate_slot.isra.0>:
 *         FIH_SUCCESS                      if image was successfully validated
 *         1 (or its fih_int encoded form)  if no bootloable image was found
 *         FIH_FAILURE                      on any errors
 */
static fih_int
boot_validate_slot(struct boot_loader_state *state, int slot,
     9e8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
                   struct boot_status *bs)
{
    const struct flash_area *fap;
    struct image_header *hdr;
    int area_id;
    fih_int fih_rc = FIH_FAILURE;
     9ec:	4b38      	ldr	r3, [pc, #224]	; (ad0 <FIH_LABEL_FIH_CALL_END_294+0x80>)
boot_validate_slot(struct boot_loader_state *state, int slot,
     9ee:	b088      	sub	sp, #32
     9f0:	4606      	mov	r6, r0
    int rc;

    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     9f2:	2000      	movs	r0, #0
boot_validate_slot(struct boot_loader_state *state, int slot,
     9f4:	460d      	mov	r5, r1
    fih_int fih_rc = FIH_FAILURE;
     9f6:	681c      	ldr	r4, [r3, #0]
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     9f8:	f004 fec0 	bl	577c <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
     9fc:	a906      	add	r1, sp, #24
     9fe:	b2c0      	uxtb	r0, r0
     a00:	f001 f964 	bl	1ccc <flash_area_open>
    if (rc != 0) {
     a04:	2800      	cmp	r0, #0
     a06:	d157      	bne.n	ab8 <FIH_LABEL_FIH_CALL_END_294+0x68>
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     a08:	4629      	mov	r1, r5
     a0a:	f004 feb7 	bl	577c <flash_area_id_from_multi_image_slot>
     ((swap_type) == BOOT_SWAP_TYPE_PERM))

static inline struct image_header*
boot_img_hdr(struct boot_loader_state *state, size_t slot)
{
    return &BOOT_IMG(state, slot).hdr;
     a0e:	242c      	movs	r4, #44	; 0x2c
    rc = flash_area_open(area_id, &fap);
     a10:	a907      	add	r1, sp, #28
     a12:	b2c0      	uxtb	r0, r0
     a14:	fb04 6405 	mla	r4, r4, r5, r6
     a18:	f001 f958 	bl	1ccc <flash_area_open>
    if (rc != 0) {
     a1c:	2800      	cmp	r0, #0
     a1e:	d036      	beq.n	a8e <FIH_LABEL_FIH_CALL_END_294+0x3e>
        FIH_RET(fih_rc);
    }

    hdr = boot_img_hdr(state, slot);
    if (boot_check_header_erased(state, slot) == 0 ||
        (hdr->ih_flags & IMAGE_F_NON_BOOTABLE)) {
     a20:	f04f 082c 	mov.w	r8, #44	; 0x2c
     a24:	fb08 f805 	mul.w	r8, r8, r5
     a28:	eb06 0708 	add.w	r7, r6, r8
     a2c:	6939      	ldr	r1, [r7, #16]
    if (boot_check_header_erased(state, slot) == 0 ||
     a2e:	f011 0110 	ands.w	r1, r1, #16
     a32:	d137      	bne.n	aa4 <FIH_LABEL_FIH_CALL_END_294+0x54>

00000a34 <FIH_LABEL_FIH_CALL_START_238>:
    FIH_CALL(bootutil_img_validate, fih_rc, BOOT_CURR_ENC(state), image_index,
     a34:	f44f 7380 	mov.w	r3, #256	; 0x100
     a38:	9301      	str	r3, [sp, #4]
     a3a:	4b26      	ldr	r3, [pc, #152]	; (ad4 <FIH_LABEL_FIH_CALL_END_294+0x84>)
     a3c:	9300      	str	r3, [sp, #0]
     a3e:	4622      	mov	r2, r4
     a40:	e9cd 1103 	strd	r1, r1, [sp, #12]
     a44:	9b06      	ldr	r3, [sp, #24]
     a46:	9102      	str	r1, [sp, #8]
     a48:	4608      	mov	r0, r1
     a4a:	f7ff fdab 	bl	5a4 <bootutil_img_validate>
     a4e:	4604      	mov	r4, r0

00000a50 <FIH_LABEL_FIH_CALL_END_294>:
    if (hdr->ih_magic != IMAGE_MAGIC) {
     a50:	4b21      	ldr	r3, [pc, #132]	; (ad8 <FIH_LABEL_FIH_CALL_END_294+0x88>)
     a52:	f856 2008 	ldr.w	r2, [r6, r8]
                       fih_rc, BOOT_CURR_IMG(state), slot);
    if (fih_eq(fih_rc, fih_int_encode(BOOT_HOOK_REGULAR)))
    {
        FIH_CALL(boot_image_check, fih_rc, state, hdr, fap, bs);
    }
    if (!boot_is_header_valid(hdr, fap) || fih_not_eq(fih_rc, FIH_SUCCESS)) {
     a56:	9806      	ldr	r0, [sp, #24]
    if (hdr->ih_magic != IMAGE_MAGIC) {
     a58:	429a      	cmp	r2, r3
     a5a:	d10c      	bne.n	a76 <FIH_LABEL_FIH_CALL_END_294+0x26>
    if (!boot_u32_safe_add(&size, hdr->ih_img_size, hdr->ih_hdr_size)) {
     a5c:	893a      	ldrh	r2, [r7, #8]
     a5e:	68fb      	ldr	r3, [r7, #12]
    if (a > UINT32_MAX - b) {
     a60:	43d1      	mvns	r1, r2
     a62:	428b      	cmp	r3, r1
     a64:	d807      	bhi.n	a76 <FIH_LABEL_FIH_CALL_END_294+0x26>
        *dest = a + b;
     a66:	4413      	add	r3, r2
    if (size >= flash_area_get_size(fap)) {
     a68:	6882      	ldr	r2, [r0, #8]
     a6a:	4293      	cmp	r3, r2
     a6c:	d203      	bcs.n	a76 <FIH_LABEL_FIH_CALL_END_294+0x26>
    if (!boot_is_header_valid(hdr, fap) || fih_not_eq(fih_rc, FIH_SUCCESS)) {
     a6e:	4b1b      	ldr	r3, [pc, #108]	; (adc <FIH_LABEL_FIH_CALL_END_294+0x8c>)
     a70:	681b      	ldr	r3, [r3, #0]
     a72:	42a3      	cmp	r3, r4
     a74:	d01d      	beq.n	ab2 <FIH_LABEL_FIH_CALL_END_294+0x62>
        if ((slot != BOOT_PRIMARY_SLOT) || ARE_SLOTS_EQUIVALENT()) {
     a76:	b345      	cbz	r5, aca <FIH_LABEL_FIH_CALL_END_294+0x7a>
            flash_area_erase(fap, 0, flash_area_get_size(fap));
     a78:	6882      	ldr	r2, [r0, #8]
     a7a:	2100      	movs	r1, #0
     a7c:	f005 fa25 	bl	5eca <flash_area_erase>
            /* Image is invalid, erase it to prevent further unnecessary
             * attempts to validate and boot it.
             */
        }
#if !defined(__BOOTSIM__)
        BOOT_LOG_ERR("Image in the %s slot is not valid!",
     a80:	4a17      	ldr	r2, [pc, #92]	; (ae0 <FIH_LABEL_FIH_CALL_END_294+0x90>)
     a82:	4818      	ldr	r0, [pc, #96]	; (ae4 <FIH_LABEL_FIH_CALL_END_294+0x94>)
     a84:	2145      	movs	r1, #69	; 0x45
     a86:	f005 f9da 	bl	5e3e <z_log_minimal_printk>
        fih_rc = fih_int_encode(1);
     a8a:	2401      	movs	r4, #1
     a8c:	e011      	b.n	ab2 <FIH_LABEL_FIH_CALL_END_294+0x62>
    erased_val = flash_area_erased_val(fap);
     a8e:	9807      	ldr	r0, [sp, #28]
     a90:	f005 fa3b 	bl	5f0a <flash_area_erased_val>
     a94:	4607      	mov	r7, r0
    flash_area_close(fap);
     a96:	9807      	ldr	r0, [sp, #28]
     a98:	f005 f9de 	bl	5e58 <flash_area_close>
boot_data_is_set_to(uint8_t val, void *data, size_t len)
     a9c:	1e63      	subs	r3, r4, #1
     a9e:	1ce2      	adds	r2, r4, #3
    for (i = 0; i < len; i++) {
     aa0:	4293      	cmp	r3, r2
     aa2:	d10d      	bne.n	ac0 <FIH_LABEL_FIH_CALL_END_294+0x70>
        if (slot != BOOT_PRIMARY_SLOT) {
     aa4:	2d00      	cmp	r5, #0
     aa6:	d0f0      	beq.n	a8a <FIH_LABEL_FIH_CALL_END_294+0x3a>
            swap_erase_trailer_sectors(state, fap);
     aa8:	9906      	ldr	r1, [sp, #24]
     aaa:	4630      	mov	r0, r6
     aac:	f005 f802 	bl	5ab4 <swap_erase_trailer_sectors>
        fih_rc = fih_int_encode(1);
     ab0:	462c      	mov	r4, r5
        }
    }
#endif

out:
    flash_area_close(fap);
     ab2:	9806      	ldr	r0, [sp, #24]
     ab4:	f005 f9d0 	bl	5e58 <flash_area_close>

    FIH_RET(fih_rc);
}
     ab8:	4620      	mov	r0, r4
     aba:	b008      	add	sp, #32
     abc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        if (val != p[i]) {
     ac0:	f813 1f01 	ldrb.w	r1, [r3, #1]!
     ac4:	42b9      	cmp	r1, r7
     ac6:	d0eb      	beq.n	aa0 <FIH_LABEL_FIH_CALL_END_294+0x50>
     ac8:	e7aa      	b.n	a20 <boot_validate_slot.isra.0+0x38>
        BOOT_LOG_ERR("Image in the %s slot is not valid!",
     aca:	4a07      	ldr	r2, [pc, #28]	; (ae8 <FIH_LABEL_FIH_CALL_END_294+0x98>)
     acc:	e7d9      	b.n	a82 <FIH_LABEL_FIH_CALL_END_294+0x32>
     ace:	bf00      	nop
     ad0:	20000000 	.word	0x20000000
     ad4:	20002b96 	.word	0x20002b96
     ad8:	96f3b83d 	.word	0x96f3b83d
     adc:	20000194 	.word	0x20000194
     ae0:	00008e4e 	.word	0x00008e4e
     ae4:	00008e60 	.word	0x00008e60
     ae8:	00008e58 	.word	0x00008e58

00000aec <boot_swap_image>:
 *
 * @return                      0 on success; nonzero on failure.
 */
static int
boot_swap_image(struct boot_loader_state *state, struct boot_status *bs)
{
     aec:	b573      	push	{r0, r1, r4, r5, r6, lr}
     aee:	460d      	mov	r5, r1
     af0:	4604      	mov	r4, r0
    uint8_t image_index;
    int rc;

    /* FIXME: just do this if asked by user? */

    size = copy_size = 0;
     af2:	2100      	movs	r1, #0
    image_index = BOOT_CURR_IMG(state);

    if (boot_status_is_reset(bs)) {
     af4:	4628      	mov	r0, r5
    size = copy_size = 0;
     af6:	e9cd 1100 	strd	r1, r1, [sp]
    if (boot_status_is_reset(bs)) {
     afa:	f004 ff9a 	bl	5a32 <boot_status_is_reset>
     afe:	b330      	cbz	r0, b4e <boot_swap_image+0x62>
        /*
         * No swap ever happened, so need to find the largest image which
         * will be used to determine the amount of sectors to swap.
         */
        hdr = boot_img_hdr(state, BOOT_PRIMARY_SLOT);
        if (hdr->ih_magic == IMAGE_MAGIC) {
     b00:	4e16      	ldr	r6, [pc, #88]	; (b5c <boot_swap_image+0x70>)
     b02:	6823      	ldr	r3, [r4, #0]
     b04:	42b3      	cmp	r3, r6
     b06:	d103      	bne.n	b10 <boot_swap_image+0x24>
            rc = boot_read_image_size(state, BOOT_PRIMARY_SLOT, &copy_size);
     b08:	aa01      	add	r2, sp, #4
     b0a:	4620      	mov	r0, r4
     b0c:	f004 ff26 	bl	595c <boot_read_image_size.isra.0>
            memset(bs->enckey[0], 0xff, BOOT_ENC_KEY_ALIGN_SIZE);
        }
#endif

        hdr = boot_img_hdr(state, BOOT_SECONDARY_SLOT);
        if (hdr->ih_magic == IMAGE_MAGIC) {
     b10:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
     b12:	42b3      	cmp	r3, r6
     b14:	d104      	bne.n	b20 <boot_swap_image+0x34>
            rc = boot_read_image_size(state, BOOT_SECONDARY_SLOT, &size);
     b16:	466a      	mov	r2, sp
     b18:	2101      	movs	r1, #1
     b1a:	4620      	mov	r0, r4
     b1c:	f004 ff1e 	bl	595c <boot_read_image_size.isra.0>
        } else {
            memset(bs->enckey[1], 0xff, BOOT_ENC_KEY_ALIGN_SIZE);
        }
#endif

        if (size > copy_size) {
     b20:	e9dd 3200 	ldrd	r3, r2, [sp]
     b24:	4293      	cmp	r3, r2
            copy_size = size;
     b26:	bf88      	it	hi
     b28:	9301      	strhi	r3, [sp, #4]
        }

        bs->swap_size = copy_size;
     b2a:	9b01      	ldr	r3, [sp, #4]
     b2c:	60ab      	str	r3, [r5, #8]
            }
        }
#endif
    }

    swap_run(state, bs, copy_size);
     b2e:	9a01      	ldr	r2, [sp, #4]
     b30:	4629      	mov	r1, r5
     b32:	4620      	mov	r0, r4
     b34:	f000 fb34 	bl	11a0 <swap_run>

#ifdef MCUBOOT_VALIDATE_PRIMARY_SLOT
    extern int boot_status_fails;
    if (boot_status_fails > 0) {
     b38:	4b09      	ldr	r3, [pc, #36]	; (b60 <boot_swap_image+0x74>)
     b3a:	681a      	ldr	r2, [r3, #0]
     b3c:	2a00      	cmp	r2, #0
     b3e:	dd03      	ble.n	b48 <boot_swap_image+0x5c>
        BOOT_LOG_WRN("%d status write fails performing the swap",
     b40:	4808      	ldr	r0, [pc, #32]	; (b64 <boot_swap_image+0x78>)
     b42:	2157      	movs	r1, #87	; 0x57
     b44:	f005 f97b 	bl	5e3e <z_log_minimal_printk>
                     boot_status_fails);
    }
#endif

    return 0;
}
     b48:	2000      	movs	r0, #0
     b4a:	b002      	add	sp, #8
     b4c:	bd70      	pop	{r4, r5, r6, pc}
        rc = boot_read_swap_size(image_index, &bs->swap_size);
     b4e:	f105 0108 	add.w	r1, r5, #8
     b52:	f7ff ff0b 	bl	96c <boot_read_swap_size>
        copy_size = bs->swap_size;
     b56:	68ab      	ldr	r3, [r5, #8]
     b58:	9301      	str	r3, [sp, #4]
     b5a:	e7e8      	b.n	b2e <boot_swap_image+0x42>
     b5c:	96f3b83d 	.word	0x96f3b83d
     b60:	20000df8 	.word	0x20000df8
     b64:	00008e88 	.word	0x00008e88

00000b68 <boot_copy_region>:
{
     b68:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     b6c:	f8df b070 	ldr.w	fp, [pc, #112]	; be0 <boot_copy_region+0x78>
     b70:	4c1c      	ldr	r4, [pc, #112]	; (be4 <boot_copy_region+0x7c>)
     b72:	4d1d      	ldr	r5, [pc, #116]	; (be8 <boot_copy_region+0x80>)
{
     b74:	4688      	mov	r8, r1
     b76:	4691      	mov	r9, r2
     b78:	469a      	mov	sl, r3
    bytes_copied = 0;
     b7a:	2600      	movs	r6, #0
    while (bytes_copied < sz) {
     b7c:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
     b7e:	429e      	cmp	r6, r3
     b80:	d301      	bcc.n	b86 <boot_copy_region+0x1e>
    return 0;
     b82:	2000      	movs	r0, #0
     b84:	e00f      	b.n	ba6 <boot_copy_region+0x3e>
        if (sz - bytes_copied > sizeof buf) {
     b86:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     b88:	4a15      	ldr	r2, [pc, #84]	; (be0 <boot_copy_region+0x78>)
        if (sz - bytes_copied > sizeof buf) {
     b8a:	1b9f      	subs	r7, r3, r6
     b8c:	f5b7 6f80 	cmp.w	r7, #1024	; 0x400
     b90:	bf28      	it	cs
     b92:	f44f 6780 	movcs.w	r7, #1024	; 0x400
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     b96:	463b      	mov	r3, r7
     b98:	eb06 010a 	add.w	r1, r6, sl
     b9c:	4640      	mov	r0, r8
     b9e:	f005 f95c 	bl	5e5a <flash_area_read>
        if (rc != 0) {
     ba2:	b110      	cbz	r0, baa <boot_copy_region+0x42>
            return BOOT_EFLASH;
     ba4:	2001      	movs	r0, #1
}
     ba6:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
        rc = flash_area_write(fap_dst, off_dst + bytes_copied, buf, chunk_sz);
     baa:	990a      	ldr	r1, [sp, #40]	; 0x28
     bac:	463b      	mov	r3, r7
     bae:	465a      	mov	r2, fp
     bb0:	1871      	adds	r1, r6, r1
     bb2:	4648      	mov	r0, r9
     bb4:	f005 f96d 	bl	5e92 <flash_area_write>
        if (rc != 0) {
     bb8:	2800      	cmp	r0, #0
     bba:	d1f3      	bne.n	ba4 <boot_copy_region+0x3c>
     bbc:	f8c4 5600 	str.w	r5, [r4, #1536]	; 0x600
        bytes_copied += chunk_sz;
     bc0:	443e      	add	r6, r7
     bc2:	f8c4 5604 	str.w	r5, [r4, #1540]	; 0x604
     bc6:	f8c4 5608 	str.w	r5, [r4, #1544]	; 0x608
     bca:	f8c4 560c 	str.w	r5, [r4, #1548]	; 0x60c
     bce:	f8c4 5610 	str.w	r5, [r4, #1552]	; 0x610
     bd2:	f8c4 5614 	str.w	r5, [r4, #1556]	; 0x614
     bd6:	f8c4 5618 	str.w	r5, [r4, #1560]	; 0x618
     bda:	f8c4 561c 	str.w	r5, [r4, #1564]	; 0x61c
        MCUBOOT_WATCHDOG_FEED();
     bde:	e7cd      	b.n	b7c <boot_copy_region+0x14>
     be0:	200001f8 	.word	0x200001f8
     be4:	40010000 	.word	0x40010000
     be8:	6e524635 	.word	0x6e524635

00000bec <context_boot_go>:
#endif
}

fih_int
context_boot_go(struct boot_loader_state *state, struct boot_rsp *rsp)
{
     bec:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    size_t slot;
    struct boot_status bs;
    int rc = -1;
    fih_int fih_rc = FIH_FAILURE;
     bf0:	4b8e      	ldr	r3, [pc, #568]	; (e2c <FIH_LABEL_FIH_CALL_END_2417+0x46>)
     bf2:	681e      	ldr	r6, [r3, #0]
        boot_enc_zeroize(BOOT_CURR_ENC(state));
#endif

        image_index = BOOT_CURR_IMG(state);

        BOOT_IMG(state, BOOT_PRIMARY_SLOT).sectors =
     bf4:	4b8e      	ldr	r3, [pc, #568]	; (e30 <FIH_LABEL_FIH_CALL_END_2417+0x4a>)
     bf6:	6243      	str	r3, [r0, #36]	; 0x24
{
     bf8:	460f      	mov	r7, r1
            primary_slot_sectors[image_index];
        BOOT_IMG(state, BOOT_SECONDARY_SLOT).sectors =
     bfa:	4b8e      	ldr	r3, [pc, #568]	; (e34 <FIH_LABEL_FIH_CALL_END_2417+0x4e>)
     bfc:	6503      	str	r3, [r0, #80]	; 0x50

        /* Open primary and secondary image areas for the duration
         * of this call.
         */
        for (slot = 0; slot < BOOT_NUM_SLOTS; slot++) {
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     bfe:	2100      	movs	r1, #0
{
     c00:	b085      	sub	sp, #20
     c02:	4604      	mov	r4, r0
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     c04:	4608      	mov	r0, r1
     c06:	f004 fdb9 	bl	577c <flash_area_id_from_multi_image_slot>
            rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, slot));
     c0a:	f104 0120 	add.w	r1, r4, #32
     c0e:	b2c0      	uxtb	r0, r0
     c10:	f001 f85c 	bl	1ccc <flash_area_open>
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     c14:	2101      	movs	r1, #1
     c16:	2000      	movs	r0, #0
     c18:	f004 fdb0 	bl	577c <flash_area_id_from_multi_image_slot>
            rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, slot));
     c1c:	f104 014c 	add.w	r1, r4, #76	; 0x4c
     c20:	b2c0      	uxtb	r0, r0
     c22:	f001 f853 	bl	1ccc <flash_area_open>
     c26:	4605      	mov	r5, r0
    rc = boot_read_sectors(state);
     c28:	4620      	mov	r0, r4
     c2a:	f004 fed8 	bl	59de <boot_read_sectors>
    if (rc != 0) {
     c2e:	4680      	mov	r8, r0
     c30:	b968      	cbnz	r0, c4e <context_boot_go+0x62>
    rc = boot_read_image_headers(state, false, NULL);
     c32:	2200      	movs	r2, #0
     c34:	4611      	mov	r1, r2
     c36:	4620      	mov	r0, r4
     c38:	f004 fe78 	bl	592c <boot_read_image_headers>
    if (rc != 0) {
     c3c:	4680      	mov	r8, r0
     c3e:	b300      	cbz	r0, c82 <context_boot_go+0x96>
        BOOT_LOG_WRN("Failed reading image headers; Image=%u",
     c40:	487d      	ldr	r0, [pc, #500]	; (e38 <FIH_LABEL_FIH_CALL_END_2417+0x52>)
     c42:	2200      	movs	r2, #0
     c44:	2157      	movs	r1, #87	; 0x57
            BOOT_LOG_WRN("Failed reading boot status; Image=%u",
     c46:	f005 f8fa 	bl	5e3e <z_log_minimal_printk>
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     c4a:	2301      	movs	r3, #1
     c4c:	e091      	b.n	d72 <FIH_LABEL_FIH_CALL_END_2204+0xe>
        BOOT_LOG_WRN("Failed reading sectors; BOOT_MAX_IMG_SECTORS=%d"
     c4e:	487b      	ldr	r0, [pc, #492]	; (e3c <FIH_LABEL_FIH_CALL_END_2417+0x56>)
     c50:	2280      	movs	r2, #128	; 0x80
     c52:	2157      	movs	r1, #87	; 0x57
     c54:	f005 f8f3 	bl	5e3e <z_log_minimal_printk>
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     c58:	2301      	movs	r3, #1
        if (rc == BOOT_EFLASH)
     c5a:	4598      	cmp	r8, r3
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     c5c:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
        if (rc == BOOT_EFLASH)
     c60:	d1e7      	bne.n	c32 <context_boot_go+0x46>
#endif

        /* Determine swap type and complete swap if it has been aborted. */
        boot_prepare_image_for_update(state, &bs);

        if (BOOT_IS_UPGRADE(BOOT_SWAP_TYPE(state))) {
     c62:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
        /* Indicate that swap is not aborted */
        boot_status_reset(&bs);
#endif /* (BOOT_IMAGE_NUMBER > 1) */

        /* Set the previously determined swap type */
        bs.swap_type = BOOT_SWAP_TYPE(state);
     c66:	f88d 3007 	strb.w	r3, [sp, #7]

        switch (BOOT_SWAP_TYPE(state)) {
     c6a:	2b04      	cmp	r3, #4
     c6c:	f200 8084 	bhi.w	d78 <FIH_LABEL_FIH_CALL_END_2204+0x14>
     c70:	2b01      	cmp	r3, #1
     c72:	f200 8088 	bhi.w	d86 <FIH_LABEL_FIH_CALL_END_2204+0x22>
     c76:	f000 809f 	beq.w	db8 <FIH_LABEL_FIH_CALL_END_2204+0x54>
            }
#endif /* !MCUBOOT_OVERWRITE_ONLY */
            break;

        default:
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     c7a:	23ff      	movs	r3, #255	; 0xff
     c7c:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
     c80:	e09a      	b.n	db8 <FIH_LABEL_FIH_CALL_END_2204+0x54>
    if (boot_slots_compatible(state)) {
     c82:	4620      	mov	r0, r4
     c84:	f000 f9a4 	bl	fd0 <boot_slots_compatible>
     c88:	2800      	cmp	r0, #0
     c8a:	d0de      	beq.n	c4a <context_boot_go+0x5e>
        boot_status_reset(bs);
     c8c:	4668      	mov	r0, sp
     c8e:	f004 fec7 	bl	5a20 <boot_status_reset>
        rc = swap_read_status(state, bs);
     c92:	4669      	mov	r1, sp
     c94:	4620      	mov	r0, r4
     c96:	f004 ff62 	bl	5b5e <swap_read_status>
        if (rc != 0) {
     c9a:	b118      	cbz	r0, ca4 <context_boot_go+0xb8>
            BOOT_LOG_WRN("Failed reading boot status; Image=%u",
     c9c:	4868      	ldr	r0, [pc, #416]	; (e40 <FIH_LABEL_FIH_CALL_END_2417+0x5a>)
     c9e:	4642      	mov	r2, r8
     ca0:	2157      	movs	r1, #87	; 0x57
     ca2:	e7d0      	b.n	c46 <context_boot_go+0x5a>
        rc = boot_read_image_headers(state, !boot_status_is_reset(bs), bs);
     ca4:	4668      	mov	r0, sp
     ca6:	f004 fec4 	bl	5a32 <boot_status_is_reset>
     caa:	f080 0101 	eor.w	r1, r0, #1
     cae:	466a      	mov	r2, sp
     cb0:	b2c9      	uxtb	r1, r1
     cb2:	4620      	mov	r0, r4
     cb4:	f004 fe3a 	bl	592c <boot_read_image_headers>
        if (rc != 0) {
     cb8:	4602      	mov	r2, r0
     cba:	2800      	cmp	r0, #0
     cbc:	d1c0      	bne.n	c40 <context_boot_go+0x54>
        if (!boot_status_is_reset(bs)) {
     cbe:	4668      	mov	r0, sp
     cc0:	f004 feb7 	bl	5a32 <boot_status_is_reset>
     cc4:	4680      	mov	r8, r0
     cc6:	bb60      	cbnz	r0, d22 <context_boot_go+0x136>
    rc = boot_swap_image(state, bs);
     cc8:	4669      	mov	r1, sp
     cca:	4620      	mov	r0, r4
     ccc:	f7ff ff0e 	bl	aec <boot_swap_image>
    BOOT_SWAP_TYPE(state) = bs->swap_type;
     cd0:	f89d 3007 	ldrb.w	r3, [sp, #7]
     cd4:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    if (bs->swap_type == BOOT_SWAP_TYPE_REVERT ||
     cd8:	3b03      	subs	r3, #3
     cda:	2b01      	cmp	r3, #1
     cdc:	d806      	bhi.n	cec <context_boot_go+0x100>
        rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     cde:	4640      	mov	r0, r8
     ce0:	f004 ff8b 	bl	5bfa <swap_set_image_ok>
        if (rc != 0) {
     ce4:	b110      	cbz	r0, cec <context_boot_go+0x100>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     ce6:	23ff      	movs	r3, #255	; 0xff
     ce8:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    if (BOOT_IS_UPGRADE(bs->swap_type)) {
     cec:	f89d 3007 	ldrb.w	r3, [sp, #7]
     cf0:	3b02      	subs	r3, #2
     cf2:	2b02      	cmp	r3, #2
     cf4:	d80b      	bhi.n	d0e <context_boot_go+0x122>
        rc = swap_set_copy_done(BOOT_CURR_IMG(state));
     cf6:	2000      	movs	r0, #0
     cf8:	f004 ff6d 	bl	5bd6 <swap_set_copy_done>
        if (rc != 0) {
     cfc:	b138      	cbz	r0, d0e <context_boot_go+0x122>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     cfe:	23ff      	movs	r3, #255	; 0xff
     d00:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
        BOOT_LOG_ERR("panic!");
     d04:	484f      	ldr	r0, [pc, #316]	; (e44 <FIH_LABEL_FIH_CALL_END_2417+0x5e>)
     d06:	2145      	movs	r1, #69	; 0x45
     d08:	f005 f899 	bl	5e3e <z_log_minimal_printk>
        while (1) {}
     d0c:	e7fe      	b.n	d0c <context_boot_go+0x120>
    if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
     d0e:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
     d12:	2bff      	cmp	r3, #255	; 0xff
     d14:	d0f6      	beq.n	d04 <context_boot_go+0x118>
            rc = boot_read_image_headers(state, false, bs);
     d16:	466a      	mov	r2, sp
     d18:	2100      	movs	r1, #0
     d1a:	4620      	mov	r0, r4
     d1c:	f004 fe06 	bl	592c <boot_read_image_headers>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     d20:	e793      	b.n	c4a <context_boot_go+0x5e>
            if (bs->swap_type == BOOT_SWAP_TYPE_NONE) {
     d22:	f89d 9007 	ldrb.w	r9, [sp, #7]
     d26:	f1b9 0f01 	cmp.w	r9, #1
     d2a:	d117      	bne.n	d5c <FIH_LABEL_FIH_CALL_START_2184>
    swap_type = boot_swap_type_multi(BOOT_CURR_IMG(state));
     d2c:	4610      	mov	r0, r2
     d2e:	f003 f943 	bl	3fb8 <boot_swap_type_multi>
    if (BOOT_IS_UPGRADE(swap_type)) {
     d32:	1e83      	subs	r3, r0, #2
     d34:	2b02      	cmp	r3, #2
    swap_type = boot_swap_type_multi(BOOT_CURR_IMG(state));
     d36:	4680      	mov	r8, r0
    if (BOOT_IS_UPGRADE(swap_type)) {
     d38:	d80d      	bhi.n	d56 <FIH_LABEL_FIH_CALL_END_2119+0x14>

00000d3a <FIH_LABEL_FIH_CALL_START_2095>:
        FIH_CALL(boot_validate_slot, fih_rc, state, BOOT_SECONDARY_SLOT, bs);
     d3a:	4649      	mov	r1, r9
     d3c:	4620      	mov	r0, r4
     d3e:	f7ff fe53 	bl	9e8 <boot_validate_slot.isra.0>

00000d42 <FIH_LABEL_FIH_CALL_END_2119>:
        if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     d42:	4b41      	ldr	r3, [pc, #260]	; (e48 <FIH_LABEL_FIH_CALL_END_2417+0x62>)
     d44:	681b      	ldr	r3, [r3, #0]
     d46:	4298      	cmp	r0, r3
     d48:	d005      	beq.n	d56 <FIH_LABEL_FIH_CALL_END_2119+0x14>
                swap_type = BOOT_SWAP_TYPE_FAIL;
     d4a:	2801      	cmp	r0, #1
     d4c:	bf0c      	ite	eq
     d4e:	f04f 0801 	moveq.w	r8, #1
     d52:	f04f 0805 	movne.w	r8, #5
                BOOT_SWAP_TYPE(state) = boot_validated_swap_type(state, bs);
     d56:	f884 8058 	strb.w	r8, [r4, #88]	; 0x58
     d5a:	e782      	b.n	c62 <context_boot_go+0x76>

00000d5c <FIH_LABEL_FIH_CALL_START_2184>:
                FIH_CALL(boot_validate_slot, fih_rc,
     d5c:	2101      	movs	r1, #1
     d5e:	4620      	mov	r0, r4
     d60:	f7ff fe42 	bl	9e8 <boot_validate_slot.isra.0>

00000d64 <FIH_LABEL_FIH_CALL_END_2204>:
                if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     d64:	4b38      	ldr	r3, [pc, #224]	; (e48 <FIH_LABEL_FIH_CALL_END_2417+0x62>)
     d66:	681b      	ldr	r3, [r3, #0]
     d68:	4298      	cmp	r0, r3
                    BOOT_SWAP_TYPE(state) = bs->swap_type;
     d6a:	bf0c      	ite	eq
     d6c:	f89d 3007 	ldrbeq.w	r3, [sp, #7]
                    BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_FAIL;
     d70:	2305      	movne	r3, #5
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     d72:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
     d76:	e774      	b.n	c62 <context_boot_go+0x76>
        switch (BOOT_SWAP_TYPE(state)) {
     d78:	2b05      	cmp	r3, #5
     d7a:	f47f af7e 	bne.w	c7a <context_boot_go+0x8e>
            rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     d7e:	2000      	movs	r0, #0
     d80:	f004 ff3b 	bl	5bfa <swap_set_image_ok>
     d84:	e013      	b.n	dae <FIH_LABEL_FIH_CALL_END_2204+0x4a>
        rc = boot_swap_image(state, bs);
     d86:	4669      	mov	r1, sp
     d88:	4620      	mov	r0, r4
     d8a:	f7ff feaf 	bl	aec <boot_swap_image>
    swap_type = BOOT_SWAP_TYPE(state);
     d8e:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
    if (swap_type == BOOT_SWAP_TYPE_REVERT ||
     d92:	1eda      	subs	r2, r3, #3
     d94:	2a01      	cmp	r2, #1
        rc = boot_swap_image(state, bs);
     d96:	4605      	mov	r5, r0
    if (swap_type == BOOT_SWAP_TYPE_REVERT ||
     d98:	d80c      	bhi.n	db4 <FIH_LABEL_FIH_CALL_END_2204+0x50>
        rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     d9a:	2000      	movs	r0, #0
     d9c:	f004 ff2d 	bl	5bfa <swap_set_image_ok>
        if (rc != 0) {
     da0:	4605      	mov	r5, r0
     da2:	2800      	cmp	r0, #0
     da4:	f47f af69 	bne.w	c7a <context_boot_go+0x8e>
        rc = swap_set_copy_done(BOOT_CURR_IMG(state));
     da8:	2000      	movs	r0, #0
     daa:	f004 ff14 	bl	5bd6 <swap_set_copy_done>
            if (rc != 0) {
     dae:	4605      	mov	r5, r0
     db0:	b110      	cbz	r0, db8 <FIH_LABEL_FIH_CALL_END_2204+0x54>
     db2:	e762      	b.n	c7a <context_boot_go+0x8e>
    if (BOOT_IS_UPGRADE(swap_type)) {
     db4:	2b02      	cmp	r3, #2
     db6:	d0f7      	beq.n	da8 <FIH_LABEL_FIH_CALL_END_2204+0x44>
        }

        if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
     db8:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
     dbc:	2bff      	cmp	r3, #255	; 0xff
     dbe:	d104      	bne.n	dca <FIH_LABEL_FIH_CALL_END_2204+0x66>
            BOOT_LOG_ERR("panic!");
     dc0:	4820      	ldr	r0, [pc, #128]	; (e44 <FIH_LABEL_FIH_CALL_END_2417+0x5e>)
     dc2:	2145      	movs	r1, #69	; 0x45
     dc4:	f005 f83b 	bl	5e3e <z_log_minimal_printk>
            assert(0);

            /* Loop forever... */
            FIH_PANIC;
     dc8:	e7fe      	b.n	dc8 <FIH_LABEL_FIH_CALL_END_2204+0x64>
#if BOOT_IMAGE_NUMBER > 1
        if (state->img_mask[BOOT_CURR_IMG(state)]) {
            continue;
        }
#endif
        if (BOOT_SWAP_TYPE(state) != BOOT_SWAP_TYPE_NONE) {
     dca:	2b01      	cmp	r3, #1
     dcc:	d006      	beq.n	ddc <FIH_LABEL_FIH_CALL_START_2401>
            /* Attempt to read an image header from each slot. Ensure that image
             * headers in slots are aligned with headers in boot_data.
             */
            rc = boot_read_image_headers(state, false, &bs);
     dce:	466a      	mov	r2, sp
     dd0:	2100      	movs	r1, #0
     dd2:	4620      	mov	r0, r4
     dd4:	f004 fdaa 	bl	592c <boot_read_image_headers>
            if (rc != 0) {
     dd8:	4605      	mov	r5, r0
     dda:	b9d0      	cbnz	r0, e12 <FIH_LABEL_FIH_CALL_END_2417+0x2c>

00000ddc <FIH_LABEL_FIH_CALL_START_2401>:
	 * primary.
	 */
	if (BOOT_CURR_IMG(state) == 0)
#endif
	{
            FIH_CALL(boot_validate_slot, fih_rc, state, BOOT_PRIMARY_SLOT, NULL);
     ddc:	2100      	movs	r1, #0
     dde:	4620      	mov	r0, r4
     de0:	f7ff fe02 	bl	9e8 <boot_validate_slot.isra.0>
     de4:	4606      	mov	r6, r0

00000de6 <FIH_LABEL_FIH_CALL_END_2417>:
            if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     de6:	f8df 8060 	ldr.w	r8, [pc, #96]	; e48 <FIH_LABEL_FIH_CALL_END_2417+0x62>
     dea:	f8d8 3000 	ldr.w	r3, [r8]
     dee:	4298      	cmp	r0, r3
     df0:	d10f      	bne.n	e12 <FIH_LABEL_FIH_CALL_END_2417+0x2c>
    /*
     * Since the boot_status struct stores plaintext encryption keys, reset
     * them here to avoid the possibility of jumping into an image that could
     * easily recover them.
     */
    memset(&bs, 0, sizeof(struct boot_status));
     df2:	2210      	movs	r2, #16
     df4:	2100      	movs	r1, #0
     df6:	4668      	mov	r0, sp
     df8:	f005 fb83 	bl	6502 <memset>
    rsp->br_flash_dev_id = flash_area_get_device_id(BOOT_IMG_AREA(state, active_slot));
     dfc:	6a20      	ldr	r0, [r4, #32]
     dfe:	f004 fcc6 	bl	578e <flash_area_get_device_id>
     e02:	7138      	strb	r0, [r7, #4]
 */
int flash_area_sector_from_off(off_t off, struct flash_sector *sector);

static inline uint32_t flash_area_get_off(const struct flash_area *fa)
{
	return (uint32_t)fa->fa_off;
     e04:	6a23      	ldr	r3, [r4, #32]

    fill_rsp(state, rsp);

    fih_rc = FIH_SUCCESS;
     e06:	f8d8 6000 	ldr.w	r6, [r8]
    rsp->br_image_off = boot_img_slot_off(state, active_slot);
     e0a:	685b      	ldr	r3, [r3, #4]
     e0c:	60bb      	str	r3, [r7, #8]
    rsp->br_hdr = boot_img_hdr(state, active_slot);
     e0e:	603c      	str	r4, [r7, #0]
        rc = boot_add_shared_data(state, BOOT_PRIMARY_SLOT);
     e10:	2500      	movs	r5, #0
            flash_area_close(BOOT_IMG_AREA(state, BOOT_NUM_SLOTS - 1 - slot));
     e12:	6ce0      	ldr	r0, [r4, #76]	; 0x4c
     e14:	f005 f820 	bl	5e58 <flash_area_close>
     e18:	6a20      	ldr	r0, [r4, #32]
     e1a:	f005 f81d 	bl	5e58 <flash_area_close>
    if (rc) {
        fih_rc = fih_int_encode(rc);
    }

    FIH_RET(fih_rc);
}
     e1e:	2d00      	cmp	r5, #0
     e20:	bf14      	ite	ne
     e22:	4628      	movne	r0, r5
     e24:	4630      	moveq	r0, r6
     e26:	b005      	add	sp, #20
     e28:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
     e2c:	20000000 	.word	0x20000000
     e30:	200005f8 	.word	0x200005f8
     e34:	200009f8 	.word	0x200009f8
     e38:	00008ef9 	.word	0x00008ef9
     e3c:	00008eb7 	.word	0x00008eb7
     e40:	00008f25 	.word	0x00008f25
     e44:	00008f4f 	.word	0x00008f4f
     e48:	20000194 	.word	0x20000194

00000e4c <boot_go>:
 *
 * @return                      FIH_SUCCESS on success; nonzero on failure.
 */
fih_int
boot_go(struct boot_rsp *rsp)
{
     e4c:	b538      	push	{r3, r4, r5, lr}
void boot_state_clear(struct boot_loader_state *state)
{
    if (state != NULL) {
        memset(state, 0, sizeof(struct boot_loader_state));
    } else {
        memset(&boot_data, 0, sizeof(struct boot_loader_state));
     e4e:	4d06      	ldr	r5, [pc, #24]	; (e68 <FIH_LABEL_FIH_CALL_END_3095+0x4>)
{
     e50:	4604      	mov	r4, r0
        memset(&boot_data, 0, sizeof(struct boot_loader_state));
     e52:	2260      	movs	r2, #96	; 0x60
     e54:	2100      	movs	r1, #0
     e56:	4628      	mov	r0, r5
     e58:	f005 fb53 	bl	6502 <memset>

00000e5c <FIH_LABEL_FIH_CALL_START_3080>:
    FIH_CALL(context_boot_go, fih_rc, &boot_data, rsp);
     e5c:	4621      	mov	r1, r4
     e5e:	4628      	mov	r0, r5
     e60:	f7ff fec4 	bl	bec <context_boot_go>

00000e64 <FIH_LABEL_FIH_CALL_END_3095>:
}
     e64:	bd38      	pop	{r3, r4, r5, pc}
     e66:	bf00      	nop
     e68:	20000198 	.word	0x20000198

00000e6c <boot_read_image_header>:
static uint32_t g_last_idx = UINT32_MAX;

int
boot_read_image_header(struct boot_loader_state *state, int slot,
                       struct image_header *out_hdr, struct boot_status *bs)
{
     e6c:	b573      	push	{r0, r1, r4, r5, r6, lr}
     e6e:	4616      	mov	r6, r2
#if (BOOT_IMAGE_NUMBER == 1)
    (void)state;
#endif

    off = 0;
    if (bs) {
     e70:	461c      	mov	r4, r3
     e72:	b333      	cbz	r3, ec2 <boot_read_image_header+0x56>
	return fs->fs_off;
}

static inline uint32_t flash_sector_get_size(const struct flash_sector *fs)
{
	return fs->fs_size;
     e74:	6a43      	ldr	r3, [r0, #36]	; 0x24
     e76:	685d      	ldr	r5, [r3, #4]
        sz = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, 0);
        if (bs->op == BOOT_STATUS_OP_MOVE) {
     e78:	7963      	ldrb	r3, [r4, #5]
     e7a:	2b01      	cmp	r3, #1
     e7c:	d115      	bne.n	eaa <boot_read_image_header+0x3e>
            if (slot == 0 && bs->idx > g_last_idx) {
     e7e:	bb01      	cbnz	r1, ec2 <boot_read_image_header+0x56>
     e80:	4b1f      	ldr	r3, [pc, #124]	; (f00 <boot_read_image_header+0x94>)
     e82:	6822      	ldr	r2, [r4, #0]
     e84:	681b      	ldr	r3, [r3, #0]
    off = 0;
     e86:	429a      	cmp	r2, r3
     e88:	bf98      	it	ls
     e8a:	2500      	movls	r5, #0
                }
            }
        }
    }

    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     e8c:	2000      	movs	r0, #0
     e8e:	f004 fc75 	bl	577c <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
     e92:	a901      	add	r1, sp, #4
     e94:	b2c0      	uxtb	r0, r0
     e96:	f000 ff19 	bl	1ccc <flash_area_open>
    if (rc != 0) {
     e9a:	b1f0      	cbz	r0, eda <boot_read_image_header+0x6e>
        rc = BOOT_EFLASH;
     e9c:	2501      	movs	r5, #1
    }

    rc = 0;

done:
    flash_area_close(fap);
     e9e:	9801      	ldr	r0, [sp, #4]
     ea0:	f004 ffda 	bl	5e58 <flash_area_close>
    return rc;
}
     ea4:	4628      	mov	r0, r5
     ea6:	b002      	add	sp, #8
     ea8:	bd70      	pop	{r4, r5, r6, pc}
        } else if (bs->op == BOOT_STATUS_OP_SWAP) {
     eaa:	2b02      	cmp	r3, #2
     eac:	d109      	bne.n	ec2 <boot_read_image_header+0x56>
            if (bs->idx > 1 && bs->idx <= g_last_idx) {
     eae:	6823      	ldr	r3, [r4, #0]
     eb0:	2b01      	cmp	r3, #1
     eb2:	d908      	bls.n	ec6 <boot_read_image_header+0x5a>
     eb4:	4a12      	ldr	r2, [pc, #72]	; (f00 <boot_read_image_header+0x94>)
     eb6:	6812      	ldr	r2, [r2, #0]
     eb8:	4293      	cmp	r3, r2
     eba:	d802      	bhi.n	ec2 <boot_read_image_header+0x56>
                if (slot == 0) {
     ebc:	fab1 f181 	clz	r1, r1
     ec0:	0949      	lsrs	r1, r1, #5
    off = 0;
     ec2:	2500      	movs	r5, #0
     ec4:	e7e2      	b.n	e8c <boot_read_image_header+0x20>
            } else if (bs->idx == 1) {
     ec6:	d1fc      	bne.n	ec2 <boot_read_image_header+0x56>
                if (slot == 0) {
     ec8:	2900      	cmp	r1, #0
     eca:	d0df      	beq.n	e8c <boot_read_image_header+0x20>
                if (slot == 1 && bs->state == 2) {
     ecc:	2901      	cmp	r1, #1
     ece:	d1f8      	bne.n	ec2 <boot_read_image_header+0x56>
     ed0:	7921      	ldrb	r1, [r4, #4]
     ed2:	3902      	subs	r1, #2
     ed4:	bf18      	it	ne
     ed6:	2101      	movne	r1, #1
     ed8:	e7f3      	b.n	ec2 <boot_read_image_header+0x56>
    rc = flash_area_read(fap, off, out_hdr, sizeof *out_hdr);
     eda:	4629      	mov	r1, r5
     edc:	9801      	ldr	r0, [sp, #4]
     ede:	2320      	movs	r3, #32
     ee0:	4632      	mov	r2, r6
     ee2:	f004 ffba 	bl	5e5a <flash_area_read>
    if (rc != 0) {
     ee6:	4605      	mov	r5, r0
     ee8:	2800      	cmp	r0, #0
     eea:	d1d7      	bne.n	e9c <boot_read_image_header+0x30>
    if (bs != NULL && out_hdr->ih_magic != IMAGE_MAGIC) {
     eec:	2c00      	cmp	r4, #0
     eee:	d0d6      	beq.n	e9e <boot_read_image_header+0x32>
     ef0:	6835      	ldr	r5, [r6, #0]
     ef2:	4804      	ldr	r0, [pc, #16]	; (f04 <boot_read_image_header+0x98>)
     ef4:	1a2d      	subs	r5, r5, r0
     ef6:	bf18      	it	ne
     ef8:	f04f 35ff 	movne.w	r5, #4294967295
     efc:	e7cf      	b.n	e9e <boot_read_image_header+0x32>
     efe:	bf00      	nop
     f00:	20000004 	.word	0x20000004
     f04:	96f3b83d 	.word	0x96f3b83d

00000f08 <swap_read_status_bytes>:

int
swap_read_status_bytes(const struct flash_area *fap,
        struct boot_loader_state *state, struct boot_status *bs)
{
     f08:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     f0c:	4607      	mov	r7, r0
     f0e:	b085      	sub	sp, #20
     f10:	460c      	mov	r4, r1
    int rc;
    int last_rc;
    int erased_sections;
    int i;

    max_entries = boot_status_entries(BOOT_CURR_IMG(state), fap);
     f12:	4601      	mov	r1, r0
     f14:	2000      	movs	r0, #0
{
     f16:	4616      	mov	r6, r2
    max_entries = boot_status_entries(BOOT_CURR_IMG(state), fap);
     f18:	f004 fcd9 	bl	58ce <boot_status_entries>
    if (max_entries < 0) {
     f1c:	1e05      	subs	r5, r0, #0
     f1e:	db51      	blt.n	fc4 <swap_read_status_bytes+0xbc>
    erased_sections = 0;
    found_idx = -1;
    /* skip erased sectors at the end */
    last_rc = 1;
    write_sz = BOOT_WRITE_SZ(state);
    off = boot_status_off(fap);
     f20:	4638      	mov	r0, r7
    write_sz = BOOT_WRITE_SZ(state);
     f22:	6de4      	ldr	r4, [r4, #92]	; 0x5c
    off = boot_status_off(fap);
     f24:	f004 fce0 	bl	58e8 <boot_status_off>
    for (i = max_entries; i > 0; i--) {
     f28:	fa5f f984 	uxtb.w	r9, r4
     f2c:	f105 38ff 	add.w	r8, r5, #4294967295
     f30:	fb09 0808 	mla	r8, r9, r8, r0
    erased_sections = 0;
     f34:	f04f 0a00 	mov.w	sl, #0
    last_rc = 1;
     f38:	f04f 0b01 	mov.w	fp, #1
    found_idx = -1;
     f3c:	f04f 34ff 	mov.w	r4, #4294967295
    for (i = max_entries; i > 0; i--) {
     f40:	b99d      	cbnz	r5, f6a <swap_read_status_bytes+0x62>
            }
        }
        last_rc = rc;
    }

    if (erased_sections > 1) {
     f42:	f1ba 0f01 	cmp.w	sl, #1
     f46:	dd03      	ble.n	f50 <swap_read_status_bytes+0x48>
        /* This means there was an error writing status on the last
         * swap. Tell user and move on to validation!
         */
#if !defined(__BOOTSIM__)
        BOOT_LOG_ERR("Detected inconsistent status!");
     f48:	4820      	ldr	r0, [pc, #128]	; (fcc <swap_read_status_bytes+0xc4>)
     f4a:	2145      	movs	r1, #69	; 0x45
     f4c:	f004 ff77 	bl	5e3e <z_log_minimal_printk>
        assert(0);
#endif
    }

    move_entries = BOOT_MAX_IMG_SECTORS * BOOT_STATUS_MOVE_STATE_COUNT;
    if (found_idx == -1) {
     f50:	1c63      	adds	r3, r4, #1
     f52:	d006      	beq.n	f62 <swap_read_status_bytes+0x5a>
        /* no swap status found; nothing to do */
    } else if (found_idx < move_entries) {
     f54:	2c7f      	cmp	r4, #127	; 0x7f
     f56:	dc2a      	bgt.n	fae <swap_read_status_bytes+0xa6>
        bs->op = BOOT_STATUS_OP_MOVE;
        bs->idx = (found_idx  / BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_IDX_0;
     f58:	3401      	adds	r4, #1
        bs->state = (found_idx % BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_STATE_0;;
     f5a:	f240 1301 	movw	r3, #257	; 0x101
        bs->idx = (found_idx  / BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_IDX_0;
     f5e:	6034      	str	r4, [r6, #0]
        bs->state = (found_idx % BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_STATE_0;;
     f60:	80b3      	strh	r3, [r6, #4]
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
    }

    return 0;
}
     f62:	4628      	mov	r0, r5
     f64:	b005      	add	sp, #20
     f66:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        rc = flash_area_read(fap, off + (i - 1) * write_sz, &status, 1);
     f6a:	1e6b      	subs	r3, r5, #1
     f6c:	9300      	str	r3, [sp, #0]
     f6e:	f10d 020f 	add.w	r2, sp, #15
     f72:	2301      	movs	r3, #1
     f74:	4641      	mov	r1, r8
     f76:	4638      	mov	r0, r7
     f78:	f004 ff6f 	bl	5e5a <flash_area_read>
        if (rc < 0) {
     f7c:	1e03      	subs	r3, r0, #0
     f7e:	9301      	str	r3, [sp, #4]
     f80:	db22      	blt.n	fc8 <swap_read_status_bytes+0xc0>
        if (bootutil_buffer_is_erased(fap, &status, 1)) {
     f82:	2201      	movs	r2, #1
     f84:	f10d 010f 	add.w	r1, sp, #15
     f88:	4638      	mov	r0, r7
     f8a:	f005 feca 	bl	6d22 <bootutil_buffer_is_erased>
     f8e:	9b01      	ldr	r3, [sp, #4]
     f90:	b140      	cbz	r0, fa4 <swap_read_status_bytes+0x9c>
            if (rc != last_rc) {
     f92:	455b      	cmp	r3, fp
     f94:	d001      	beq.n	f9a <swap_read_status_bytes+0x92>
                erased_sections++;
     f96:	f10a 0a01 	add.w	sl, sl, #1
            if (found_idx == -1) {
     f9a:	9d00      	ldr	r5, [sp, #0]
     f9c:	eba8 0809 	sub.w	r8, r8, r9
     fa0:	469b      	mov	fp, r3
     fa2:	e7cd      	b.n	f40 <swap_read_status_bytes+0x38>
     fa4:	f1b4 3fff 	cmp.w	r4, #4294967295
     fa8:	bf08      	it	eq
     faa:	462c      	moveq	r4, r5
     fac:	e7f5      	b.n	f9a <swap_read_status_bytes+0x92>
        bs->op = BOOT_STATUS_OP_SWAP;
     fae:	2302      	movs	r3, #2
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     fb0:	3c80      	subs	r4, #128	; 0x80
        bs->op = BOOT_STATUS_OP_SWAP;
     fb2:	7173      	strb	r3, [r6, #5]
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     fb4:	1063      	asrs	r3, r4, #1
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     fb6:	f004 0401 	and.w	r4, r4, #1
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     fba:	3301      	adds	r3, #1
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     fbc:	3401      	adds	r4, #1
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     fbe:	6033      	str	r3, [r6, #0]
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     fc0:	7134      	strb	r4, [r6, #4]
     fc2:	e7ce      	b.n	f62 <swap_read_status_bytes+0x5a>
        return BOOT_EBADARGS;
     fc4:	2507      	movs	r5, #7
     fc6:	e7cc      	b.n	f62 <swap_read_status_bytes+0x5a>
            return BOOT_EFLASH;
     fc8:	2501      	movs	r5, #1
     fca:	e7ca      	b.n	f62 <swap_read_status_bytes+0x5a>
     fcc:	00008f5b 	.word	0x00008f5b

00000fd0 <boot_slots_compatible>:
}

static inline size_t
boot_img_num_sectors(const struct boot_loader_state *state, size_t slot)
{
    return BOOT_IMG(state, slot).num_sectors;
     fd0:	6a81      	ldr	r1, [r0, #40]	; 0x28
     fd2:	6d42      	ldr	r2, [r0, #84]	; 0x54
    size_t sector_sz_sec = 0;
    size_t i;

    num_sectors_pri = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT);
    num_sectors_sec = boot_img_num_sectors(state, BOOT_SECONDARY_SLOT);
    if ((num_sectors_pri != num_sectors_sec) &&
     fd4:	4291      	cmp	r1, r2
{
     fd6:	b538      	push	{r3, r4, r5, lr}
    if ((num_sectors_pri != num_sectors_sec) &&
     fd8:	d008      	beq.n	fec <boot_slots_compatible+0x1c>
            (num_sectors_pri != (num_sectors_sec + 1))) {
     fda:	1c53      	adds	r3, r2, #1
    if ((num_sectors_pri != num_sectors_sec) &&
     fdc:	428b      	cmp	r3, r1
     fde:	d005      	beq.n	fec <boot_slots_compatible+0x1c>
        BOOT_LOG_WRN("Cannot upgrade: not a compatible amount of sectors");
     fe0:	4813      	ldr	r0, [pc, #76]	; (1030 <CONFIG_FPROTECT_BLOCK_SIZE+0x30>)
     fe2:	2157      	movs	r1, #87	; 0x57

    for (i = 0; i < num_sectors_sec; i++) {
        sector_sz_pri = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, i);
        sector_sz_sec = boot_img_sector_size(state, BOOT_SECONDARY_SLOT, i);
        if (sector_sz_pri != sector_sz_sec) {
            BOOT_LOG_WRN("Cannot upgrade: not same sector layout");
     fe4:	f004 ff2b 	bl	5e3e <z_log_minimal_printk>
            return 0;
     fe8:	2000      	movs	r0, #0
        }
    }

    return 1;
#endif /* PM_S1_ADDRESS */
}
     fea:	bd38      	pop	{r3, r4, r5, pc}
    if (num_sectors_pri > BOOT_MAX_IMG_SECTORS) {
     fec:	2980      	cmp	r1, #128	; 0x80
     fee:	d91c      	bls.n	102a <CONFIG_FPROTECT_BLOCK_SIZE+0x2a>
        BOOT_LOG_WRN("Cannot upgrade: more sectors than allowed");
     ff0:	4810      	ldr	r0, [pc, #64]	; (1034 <CONFIG_FPROTECT_BLOCK_SIZE+0x34>)
     ff2:	2157      	movs	r1, #87	; 0x57
     ff4:	e7f6      	b.n	fe4 <boot_slots_compatible+0x14>
     ff6:	6a44      	ldr	r4, [r0, #36]	; 0x24
     ff8:	6d05      	ldr	r5, [r0, #80]	; 0x50
     ffa:	eb04 04c3 	add.w	r4, r4, r3, lsl #3
     ffe:	eb05 05c3 	add.w	r5, r5, r3, lsl #3
    1002:	6864      	ldr	r4, [r4, #4]
        if (sector_sz_pri != sector_sz_sec) {
    1004:	686d      	ldr	r5, [r5, #4]
    1006:	42ac      	cmp	r4, r5
    1008:	d002      	beq.n	1010 <CONFIG_FPROTECT_BLOCK_SIZE+0x10>
            BOOT_LOG_WRN("Cannot upgrade: not same sector layout");
    100a:	480b      	ldr	r0, [pc, #44]	; (1038 <CONFIG_FPROTECT_BLOCK_SIZE+0x38>)
    100c:	2157      	movs	r1, #87	; 0x57
    100e:	e7e9      	b.n	fe4 <boot_slots_compatible+0x14>
    for (i = 0; i < num_sectors_sec; i++) {
    1010:	3301      	adds	r3, #1
    1012:	429a      	cmp	r2, r3
    1014:	d1ef      	bne.n	ff6 <boot_slots_compatible+0x26>
    if (num_sectors_pri > num_sectors_sec) {
    1016:	4291      	cmp	r1, r2
    1018:	d905      	bls.n	1026 <CONFIG_FPROTECT_BLOCK_SIZE+0x26>
    101a:	6a43      	ldr	r3, [r0, #36]	; 0x24
    101c:	eb03 02c2 	add.w	r2, r3, r2, lsl #3
        if (sector_sz_pri != boot_img_sector_size(state, BOOT_PRIMARY_SLOT, i)) {
    1020:	6853      	ldr	r3, [r2, #4]
    1022:	42a3      	cmp	r3, r4
    1024:	d1f1      	bne.n	100a <CONFIG_FPROTECT_BLOCK_SIZE+0xa>
    return 1;
    1026:	2001      	movs	r0, #1
    1028:	e7df      	b.n	fea <boot_slots_compatible+0x1a>
    for (i = 0; i < num_sectors_sec; i++) {
    102a:	2300      	movs	r3, #0
    size_t sector_sz_pri = 0;
    102c:	461c      	mov	r4, r3
    102e:	e7f0      	b.n	1012 <CONFIG_FPROTECT_BLOCK_SIZE+0x12>
    1030:	00008f7e 	.word	0x00008f7e
    1034:	00008fb6 	.word	0x00008fb6
    1038:	00008fe5 	.word	0x00008fe5

0000103c <swap_status_source>:
                 (state)->copy_done,                                \
                 (state)->image_ok)

int
swap_status_source(struct boot_loader_state *state)
{
    103c:	b500      	push	{lr}
    103e:	b089      	sub	sp, #36	; 0x24
    (void)state;
#endif

    image_index = BOOT_CURR_IMG(state);

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
    1040:	a904      	add	r1, sp, #16
    1042:	2002      	movs	r0, #2
    1044:	f005 fed3 	bl	6dee <boot_read_swap_state_by_id>
            &state_primary_slot);
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Primary image", &state_primary_slot);
    1048:	f89d 2010 	ldrb.w	r2, [sp, #16]
    104c:	2a01      	cmp	r2, #1
    104e:	d041      	beq.n	10d4 <swap_status_source+0x98>
    1050:	4b25      	ldr	r3, [pc, #148]	; (10e8 <swap_status_source+0xac>)
    1052:	4926      	ldr	r1, [pc, #152]	; (10ec <swap_status_source+0xb0>)
    1054:	2a03      	cmp	r2, #3
    1056:	bf18      	it	ne
    1058:	460b      	movne	r3, r1
    105a:	f89d 2013 	ldrb.w	r2, [sp, #19]
    105e:	9202      	str	r2, [sp, #8]
    1060:	f89d 2012 	ldrb.w	r2, [sp, #18]
    1064:	9201      	str	r2, [sp, #4]
    1066:	f89d 2011 	ldrb.w	r2, [sp, #17]
    106a:	4821      	ldr	r0, [pc, #132]	; (10f0 <swap_status_source+0xb4>)
    106c:	9200      	str	r2, [sp, #0]
    106e:	2149      	movs	r1, #73	; 0x49
    1070:	4a20      	ldr	r2, [pc, #128]	; (10f4 <swap_status_source+0xb8>)
    1072:	f004 fee4 	bl	5e3e <z_log_minimal_printk>

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    1076:	a906      	add	r1, sp, #24
    1078:	2005      	movs	r0, #5
    107a:	f005 feb8 	bl	6dee <boot_read_swap_state_by_id>
            &state_secondary_slot);
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Secondary image", &state_secondary_slot);
    107e:	f89d 2018 	ldrb.w	r2, [sp, #24]
    1082:	2a01      	cmp	r2, #1
    1084:	d028      	beq.n	10d8 <swap_status_source+0x9c>
    1086:	4b18      	ldr	r3, [pc, #96]	; (10e8 <swap_status_source+0xac>)
    1088:	4918      	ldr	r1, [pc, #96]	; (10ec <swap_status_source+0xb0>)
    108a:	2a03      	cmp	r2, #3
    108c:	bf18      	it	ne
    108e:	460b      	movne	r3, r1
    1090:	f89d 201b 	ldrb.w	r2, [sp, #27]
    1094:	9202      	str	r2, [sp, #8]
    1096:	f89d 201a 	ldrb.w	r2, [sp, #26]
    109a:	9201      	str	r2, [sp, #4]
    109c:	f89d 2019 	ldrb.w	r2, [sp, #25]
    10a0:	9200      	str	r2, [sp, #0]
    10a2:	4813      	ldr	r0, [pc, #76]	; (10f0 <swap_status_source+0xb4>)
    10a4:	4a14      	ldr	r2, [pc, #80]	; (10f8 <swap_status_source+0xbc>)
    10a6:	2149      	movs	r1, #73	; 0x49
    10a8:	f004 fec9 	bl	5e3e <z_log_minimal_printk>

    if (state_primary_slot.magic == BOOT_MAGIC_GOOD &&
    10ac:	f89d 3010 	ldrb.w	r3, [sp, #16]
    10b0:	2b01      	cmp	r3, #1
    10b2:	d113      	bne.n	10dc <swap_status_source+0xa0>
    10b4:	f89d 3012 	ldrb.w	r3, [sp, #18]
    10b8:	2b03      	cmp	r3, #3
    10ba:	d10f      	bne.n	10dc <swap_status_source+0xa0>
            state_primary_slot.copy_done == BOOT_FLAG_UNSET &&
    10bc:	f89d 3018 	ldrb.w	r3, [sp, #24]
    10c0:	2b01      	cmp	r3, #1
    10c2:	d00b      	beq.n	10dc <swap_status_source+0xa0>
            state_secondary_slot.magic != BOOT_MAGIC_GOOD) {

        source = BOOT_STATUS_SOURCE_PRIMARY_SLOT;

        BOOT_LOG_INF("Boot source: primary slot");
    10c4:	480d      	ldr	r0, [pc, #52]	; (10fc <swap_status_source+0xc0>)
    10c6:	2149      	movs	r1, #73	; 0x49
    10c8:	f004 feb9 	bl	5e3e <z_log_minimal_printk>
        return source;
    10cc:	2002      	movs	r0, #2
    }

    BOOT_LOG_INF("Boot source: none");
    return BOOT_STATUS_SOURCE_NONE;
}
    10ce:	b009      	add	sp, #36	; 0x24
    10d0:	f85d fb04 	ldr.w	pc, [sp], #4
    BOOT_LOG_SWAP_STATE("Primary image", &state_primary_slot);
    10d4:	4b0a      	ldr	r3, [pc, #40]	; (1100 <swap_status_source+0xc4>)
    10d6:	e7c0      	b.n	105a <swap_status_source+0x1e>
    BOOT_LOG_SWAP_STATE("Secondary image", &state_secondary_slot);
    10d8:	4b09      	ldr	r3, [pc, #36]	; (1100 <swap_status_source+0xc4>)
    10da:	e7d9      	b.n	1090 <swap_status_source+0x54>
    BOOT_LOG_INF("Boot source: none");
    10dc:	4809      	ldr	r0, [pc, #36]	; (1104 <swap_status_source+0xc8>)
    10de:	2149      	movs	r1, #73	; 0x49
    10e0:	f004 fead 	bl	5e3e <z_log_minimal_printk>
    return BOOT_STATUS_SOURCE_NONE;
    10e4:	2000      	movs	r0, #0
    10e6:	e7f2      	b.n	10ce <swap_status_source+0x92>
    10e8:	00009016 	.word	0x00009016
    10ec:	0000901c 	.word	0x0000901c
    10f0:	0000902e 	.word	0x0000902e
    10f4:	00009020 	.word	0x00009020
    10f8:	0000906f 	.word	0x0000906f
    10fc:	0000907f 	.word	0x0000907f
    1100:	00009011 	.word	0x00009011
    1104:	0000909e 	.word	0x0000909e

00001108 <fixup_revert>:
 * upgrade (by initializing the secondary slot).
 */
void
fixup_revert(const struct boot_loader_state *state, struct boot_status *bs,
        const struct flash_area *fap_sec)
{
    1108:	b570      	push	{r4, r5, r6, lr}
#if (BOOT_IMAGE_NUMBER == 1)
    (void)state;
#endif

    /* No fixup required */
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
    110a:	684b      	ldr	r3, [r1, #4]
{
    110c:	4614      	mov	r4, r2
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
    110e:	4a1e      	ldr	r2, [pc, #120]	; (1188 <fixup_revert+0x80>)
    1110:	f003 23ff 	and.w	r3, r3, #4278255360	; 0xff00ff00
    1114:	4293      	cmp	r3, r2
{
    1116:	b086      	sub	sp, #24
    1118:	4606      	mov	r6, r0
    111a:	460d      	mov	r5, r1
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
    111c:	d12f      	bne.n	117e <fixup_revert+0x76>
        bs->op != BOOT_STATUS_OP_MOVE ||
    111e:	680b      	ldr	r3, [r1, #0]
    1120:	2b01      	cmp	r3, #1
    1122:	d12c      	bne.n	117e <fixup_revert+0x76>
        bs->idx != BOOT_STATUS_IDX_0) {
        return;
    }

    rc = boot_read_swap_state(fap_sec, &swap_state);
    1124:	a904      	add	r1, sp, #16
    1126:	4620      	mov	r0, r4
    1128:	f002 fef2 	bl	3f10 <boot_read_swap_state>
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Secondary image", &swap_state);
    112c:	f89d 2010 	ldrb.w	r2, [sp, #16]
    1130:	2a01      	cmp	r2, #1
    1132:	d026      	beq.n	1182 <fixup_revert+0x7a>
    1134:	4b15      	ldr	r3, [pc, #84]	; (118c <fixup_revert+0x84>)
    1136:	4916      	ldr	r1, [pc, #88]	; (1190 <fixup_revert+0x88>)
    1138:	2a03      	cmp	r2, #3
    113a:	bf18      	it	ne
    113c:	460b      	movne	r3, r1
    113e:	f89d 2013 	ldrb.w	r2, [sp, #19]
    1142:	9202      	str	r2, [sp, #8]
    1144:	f89d 2012 	ldrb.w	r2, [sp, #18]
    1148:	9201      	str	r2, [sp, #4]
    114a:	f89d 2011 	ldrb.w	r2, [sp, #17]
    114e:	9200      	str	r2, [sp, #0]
    1150:	4810      	ldr	r0, [pc, #64]	; (1194 <fixup_revert+0x8c>)
    1152:	4a11      	ldr	r2, [pc, #68]	; (1198 <fixup_revert+0x90>)
    1154:	2149      	movs	r1, #73	; 0x49
    1156:	f004 fe72 	bl	5e3e <z_log_minimal_printk>

    if (swap_state.magic == BOOT_MAGIC_UNSET) {
    115a:	f89d 3010 	ldrb.w	r3, [sp, #16]
    115e:	2b03      	cmp	r3, #3
    1160:	d10d      	bne.n	117e <fixup_revert+0x76>
        rc = swap_erase_trailer_sectors(state, fap_sec);
    1162:	4621      	mov	r1, r4
    1164:	4630      	mov	r0, r6
    1166:	f004 fca5 	bl	5ab4 <swap_erase_trailer_sectors>
        assert(rc == 0);

        rc = boot_write_image_ok(fap_sec);
    116a:	4620      	mov	r0, r4
    116c:	f005 fe32 	bl	6dd4 <boot_write_image_ok>
        assert(rc == 0);

        rc = boot_write_swap_size(fap_sec, bs->swap_size);
    1170:	68a9      	ldr	r1, [r5, #8]
    1172:	4620      	mov	r0, r4
    1174:	f004 fbcb 	bl	590e <boot_write_swap_size>
        assert(rc == 0);

        rc = boot_write_magic(fap_sec);
    1178:	4620      	mov	r0, r4
    117a:	f002 fea9 	bl	3ed0 <boot_write_magic>
        assert(rc == 0);
    }
}
    117e:	b006      	add	sp, #24
    1180:	bd70      	pop	{r4, r5, r6, pc}
    BOOT_LOG_SWAP_STATE("Secondary image", &swap_state);
    1182:	4b06      	ldr	r3, [pc, #24]	; (119c <fixup_revert+0x94>)
    1184:	e7db      	b.n	113e <fixup_revert+0x36>
    1186:	bf00      	nop
    1188:	04000100 	.word	0x04000100
    118c:	00009016 	.word	0x00009016
    1190:	0000901c 	.word	0x0000901c
    1194:	0000902e 	.word	0x0000902e
    1198:	0000906f 	.word	0x0000906f
    119c:	00009011 	.word	0x00009011

000011a0 <swap_run>:

void
swap_run(struct boot_loader_state *state, struct boot_status *bs,
         uint32_t copy_size)
{
    11a0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    11a4:	4605      	mov	r5, r0
    11a6:	b089      	sub	sp, #36	; 0x24
    uint8_t image_index;
    const struct flash_area *fap_pri;
    const struct flash_area *fap_sec;
    int rc;

    BOOT_LOG_INF("Starting swap using move algorithm.");
    11a8:	4881      	ldr	r0, [pc, #516]	; (13b0 <swap_run+0x210>)
{
    11aa:	460c      	mov	r4, r1
    BOOT_LOG_INF("Starting swap using move algorithm.");
    11ac:	2149      	movs	r1, #73	; 0x49
{
    11ae:	4617      	mov	r7, r2
    BOOT_LOG_INF("Starting swap using move algorithm.");
    11b0:	f004 fe45 	bl	5e3e <z_log_minimal_printk>
    11b4:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    11b6:	2201      	movs	r2, #1
    11b8:	685e      	ldr	r6, [r3, #4]

    sz = 0;
    11ba:	2300      	movs	r3, #0
    g_last_idx = 0;

    sector_sz = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, 0);
    while (1) {
        sz += sector_sz;
    11bc:	4433      	add	r3, r6
        /* Skip to next sector because all sectors will be moved up. */
        g_last_idx++;
        if (sz >= copy_size) {
    11be:	429f      	cmp	r7, r3
    11c0:	4611      	mov	r1, r2
    11c2:	f102 0201 	add.w	r2, r2, #1
    11c6:	d8f9      	bhi.n	11bc <swap_run+0x1c>
    11c8:	f8df a1e8 	ldr.w	sl, [pc, #488]	; 13b4 <swap_run+0x214>
    }

    /*
     * When starting a new swap upgrade, check that there is enough space.
     */
    if (boot_status_is_reset(bs)) {
    11cc:	4620      	mov	r0, r4
    11ce:	f8ca 1000 	str.w	r1, [sl]
    11d2:	f004 fc2e 	bl	5a32 <boot_status_is_reset>
    11d6:	b308      	cbz	r0, 121c <swap_run+0x7c>
        sz = 0;
        trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    11d8:	6de8      	ldr	r0, [r5, #92]	; 0x5c
    11da:	f004 fb73 	bl	58c4 <boot_trailer_sz>
        first_trailer_idx = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT) - 1;
    11de:	6aaf      	ldr	r7, [r5, #40]	; 0x28
        sz = 0;
    11e0:	2300      	movs	r3, #0
        first_trailer_idx = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT) - 1;
    11e2:	3f01      	subs	r7, #1

        while (1) {
            sz += sector_sz;
    11e4:	4433      	add	r3, r6
            if  (sz >= trailer_sz) {
    11e6:	4283      	cmp	r3, r0
    11e8:	d201      	bcs.n	11ee <swap_run+0x4e>
                break;
            }
            first_trailer_idx--;
    11ea:	3f01      	subs	r7, #1
            sz += sector_sz;
    11ec:	e7fa      	b.n	11e4 <swap_run+0x44>
        }

        if (g_last_idx >= first_trailer_idx) {
    11ee:	f8da 3000 	ldr.w	r3, [sl]
    11f2:	42bb      	cmp	r3, r7
    11f4:	d312      	bcc.n	121c <swap_run+0x7c>
            BOOT_LOG_WRN("Not enough free space to run swap upgrade");
    11f6:	4870      	ldr	r0, [pc, #448]	; (13b8 <swap_run+0x218>)
    11f8:	2157      	movs	r1, #87	; 0x57
    11fa:	f004 fe20 	bl	5e3e <z_log_minimal_printk>
            BOOT_LOG_WRN("required %d bytes but only %d are available",
    11fe:	f8da 2000 	ldr.w	r2, [sl]
    1202:	486e      	ldr	r0, [pc, #440]	; (13bc <swap_run+0x21c>)
    1204:	fb07 f306 	mul.w	r3, r7, r6
    1208:	fb02 6206 	mla	r2, r2, r6, r6
    120c:	2157      	movs	r1, #87	; 0x57
    120e:	f004 fe16 	bl	5e3e <z_log_minimal_printk>
                         (g_last_idx + 1) * sector_sz ,
                         first_trailer_idx * sector_sz);
            bs->swap_type = BOOT_SWAP_TYPE_NONE;
    1212:	2301      	movs	r3, #1
    1214:	71e3      	strb	r3, [r4, #7]
        idx++;
    }

    flash_area_close(fap_pri);
    flash_area_close(fap_sec);
}
    1216:	b009      	add	sp, #36	; 0x24
    1218:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index), &fap_pri);
    121c:	a906      	add	r1, sp, #24
    121e:	2002      	movs	r0, #2
    1220:	f000 fd54 	bl	1ccc <flash_area_open>
    rc = flash_area_open(FLASH_AREA_IMAGE_SECONDARY(image_index), &fap_sec);
    1224:	a907      	add	r1, sp, #28
    1226:	2005      	movs	r0, #5
    1228:	f000 fd50 	bl	1ccc <flash_area_open>
    fixup_revert(state, bs, fap_sec);
    122c:	9a07      	ldr	r2, [sp, #28]
    122e:	4621      	mov	r1, r4
    1230:	4628      	mov	r0, r5
    1232:	f7ff ff69 	bl	1108 <fixup_revert>
    if (bs->op == BOOT_STATUS_OP_MOVE) {
    1236:	7963      	ldrb	r3, [r4, #5]
    1238:	2b01      	cmp	r3, #1
    123a:	d108      	bne.n	124e <swap_run+0xae>
        idx = g_last_idx;
    123c:	f8da 7000 	ldr.w	r7, [sl]
    BOOT_STATUS_ASSERT(rc == 0);
    1240:	f8df b17c 	ldr.w	fp, [pc, #380]	; 13c0 <swap_run+0x220>
            if (idx <= (g_last_idx - bs->idx + 1)) {
    1244:	f8da 3000 	ldr.w	r3, [sl]
        while (idx > 0) {
    1248:	b9a7      	cbnz	r7, 1274 <swap_run+0xd4>
        bs->idx = BOOT_STATUS_IDX_0;
    124a:	2301      	movs	r3, #1
    124c:	6023      	str	r3, [r4, #0]
    bs->op = BOOT_STATUS_OP_SWAP;
    124e:	f04f 0302 	mov.w	r3, #2
        BOOT_STATUS_ASSERT(rc == 0);
    1252:	f8df 816c 	ldr.w	r8, [pc, #364]	; 13c0 <swap_run+0x220>
    bs->op = BOOT_STATUS_OP_SWAP;
    1256:	7163      	strb	r3, [r4, #5]
    idx = 1;
    1258:	2701      	movs	r7, #1
    while (idx <= g_last_idx) {
    125a:	f8da 3000 	ldr.w	r3, [sl]
            boot_swap_sectors(idx, sector_sz, state, bs, fap_pri, fap_sec);
    125e:	f8dd 9018 	ldr.w	r9, [sp, #24]
    while (idx <= g_last_idx) {
    1262:	429f      	cmp	r7, r3
    1264:	d94b      	bls.n	12fe <swap_run+0x15e>
    flash_area_close(fap_pri);
    1266:	4648      	mov	r0, r9
    1268:	f004 fdf6 	bl	5e58 <flash_area_close>
    flash_area_close(fap_sec);
    126c:	9807      	ldr	r0, [sp, #28]
    126e:	f004 fdf3 	bl	5e58 <flash_area_close>
    1272:	e7d0      	b.n	1216 <swap_run+0x76>
            if (idx <= (g_last_idx - bs->idx + 1)) {
    1274:	6822      	ldr	r2, [r4, #0]
    1276:	3301      	adds	r3, #1
    1278:	1a9b      	subs	r3, r3, r2
    127a:	429f      	cmp	r7, r3
    127c:	d83d      	bhi.n	12fa <swap_run+0x15a>

static inline uint32_t
boot_img_sector_off(const struct boot_loader_state *state, size_t slot,
                    size_t sector)
{
    return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -
    127e:	6a6b      	ldr	r3, [r5, #36]	; 0x24
                boot_move_sector_up(idx, sector_sz, state, bs, fap_pri, fap_sec);
    1280:	f8dd 8018 	ldr.w	r8, [sp, #24]
	return fs->fs_off;
    1284:	6819      	ldr	r1, [r3, #0]
    1286:	f853 0037 	ldr.w	r0, [r3, r7, lsl #3]
    128a:	eb03 03c7 	add.w	r3, r3, r7, lsl #3
    if (bs->idx == BOOT_STATUS_IDX_0) {
    128e:	2a01      	cmp	r2, #1
    1290:	f853 3c08 	ldr.w	r3, [r3, #-8]
    1294:	eba3 0301 	sub.w	r3, r3, r1
    1298:	eba0 0901 	sub.w	r9, r0, r1
    129c:	9302      	str	r3, [sp, #8]
    129e:	d112      	bne.n	12c6 <swap_run+0x126>
        if (bs->source != BOOT_STATUS_SOURCE_PRIMARY_SLOT) {
    12a0:	68e2      	ldr	r2, [r4, #12]
                boot_move_sector_up(idx, sector_sz, state, bs, fap_pri, fap_sec);
    12a2:	9b07      	ldr	r3, [sp, #28]
        if (bs->source != BOOT_STATUS_SOURCE_PRIMARY_SLOT) {
    12a4:	2a02      	cmp	r2, #2
    12a6:	d00a      	beq.n	12be <swap_run+0x11e>
            rc = swap_erase_trailer_sectors(state, fap_pri);
    12a8:	4641      	mov	r1, r8
    12aa:	4628      	mov	r0, r5
    12ac:	9303      	str	r3, [sp, #12]
    12ae:	f004 fc01 	bl	5ab4 <swap_erase_trailer_sectors>
            rc = swap_status_init(state, fap_pri, bs);
    12b2:	4622      	mov	r2, r4
    12b4:	4641      	mov	r1, r8
    12b6:	4628      	mov	r0, r5
    12b8:	f004 fc32 	bl	5b20 <swap_status_init>
    12bc:	9b03      	ldr	r3, [sp, #12]
        rc = swap_erase_trailer_sectors(state, fap_sec);
    12be:	4619      	mov	r1, r3
    12c0:	4628      	mov	r0, r5
    12c2:	f004 fbf7 	bl	5ab4 <swap_erase_trailer_sectors>
    rc = boot_erase_region(fap_pri, new_off, sz);
    12c6:	4632      	mov	r2, r6
    12c8:	4649      	mov	r1, r9
    12ca:	4640      	mov	r0, r8
    12cc:	f004 fbf0 	bl	5ab0 <boot_erase_region>
    rc = boot_copy_region(state, fap_pri, fap_pri, old_off, new_off, sz);
    12d0:	9b02      	ldr	r3, [sp, #8]
    12d2:	4642      	mov	r2, r8
    12d4:	4641      	mov	r1, r8
    12d6:	e9cd 9600 	strd	r9, r6, [sp]
    12da:	4628      	mov	r0, r5
    12dc:	f7ff fc44 	bl	b68 <boot_copy_region>
    rc = boot_write_status(state, bs);
    12e0:	4621      	mov	r1, r4
    12e2:	4628      	mov	r0, r5
    12e4:	f004 fbb2 	bl	5a4c <boot_write_status>
    bs->idx++;
    12e8:	6823      	ldr	r3, [r4, #0]
    12ea:	3301      	adds	r3, #1
    12ec:	6023      	str	r3, [r4, #0]
    BOOT_STATUS_ASSERT(rc == 0);
    12ee:	b120      	cbz	r0, 12fa <swap_run+0x15a>
    12f0:	f8db 3000 	ldr.w	r3, [fp]
    12f4:	3301      	adds	r3, #1
    12f6:	f8cb 3000 	str.w	r3, [fp]
            idx--;
    12fa:	3f01      	subs	r7, #1
    12fc:	e7a2      	b.n	1244 <swap_run+0xa4>
        if (idx >= bs->idx) {
    12fe:	6823      	ldr	r3, [r4, #0]
    1300:	429f      	cmp	r7, r3
    1302:	d352      	bcc.n	13aa <swap_run+0x20a>
    1304:	6a6a      	ldr	r2, [r5, #36]	; 0x24
            boot_swap_sectors(idx, sector_sz, state, bs, fap_pri, fap_sec);
    1306:	f8dd b01c 	ldr.w	fp, [sp, #28]
    130a:	f852 1037 	ldr.w	r1, [r2, r7, lsl #3]
    130e:	9104      	str	r1, [sp, #16]
    1310:	00fb      	lsls	r3, r7, #3
    1312:	6811      	ldr	r1, [r2, #0]
    1314:	9103      	str	r1, [sp, #12]
    1316:	3b08      	subs	r3, #8
    1318:	6d29      	ldr	r1, [r5, #80]	; 0x50
    131a:	58c8      	ldr	r0, [r1, r3]
    131c:	6809      	ldr	r1, [r1, #0]
    131e:	1a41      	subs	r1, r0, r1
    1320:	9102      	str	r1, [sp, #8]
    if (bs->state == BOOT_STATUS_STATE_0) {
    1322:	7921      	ldrb	r1, [r4, #4]
    1324:	2901      	cmp	r1, #1
    1326:	d13e      	bne.n	13a6 <swap_run+0x206>
    1328:	58d1      	ldr	r1, [r2, r3]
    132a:	9b03      	ldr	r3, [sp, #12]
        rc = boot_erase_region(fap_pri, pri_off, sz);
    132c:	4632      	mov	r2, r6
    132e:	1ac9      	subs	r1, r1, r3
    1330:	4648      	mov	r0, r9
    1332:	9105      	str	r1, [sp, #20]
    1334:	f004 fbbc 	bl	5ab0 <boot_erase_region>
        rc = boot_copy_region(state, fap_sec, fap_pri, sec_off, pri_off, sz);
    1338:	9905      	ldr	r1, [sp, #20]
    133a:	9b02      	ldr	r3, [sp, #8]
    133c:	9100      	str	r1, [sp, #0]
    133e:	464a      	mov	r2, r9
    1340:	4659      	mov	r1, fp
    1342:	9601      	str	r6, [sp, #4]
    1344:	4628      	mov	r0, r5
    1346:	f7ff fc0f 	bl	b68 <boot_copy_region>
        rc = boot_write_status(state, bs);
    134a:	4621      	mov	r1, r4
    134c:	4628      	mov	r0, r5
    134e:	f004 fb7d 	bl	5a4c <boot_write_status>
        bs->state = BOOT_STATUS_STATE_1;
    1352:	f04f 0302 	mov.w	r3, #2
    1356:	7123      	strb	r3, [r4, #4]
        BOOT_STATUS_ASSERT(rc == 0);
    1358:	b120      	cbz	r0, 1364 <swap_run+0x1c4>
    135a:	f8d8 3000 	ldr.w	r3, [r8]
    135e:	3301      	adds	r3, #1
    1360:	f8c8 3000 	str.w	r3, [r8]
        rc = boot_erase_region(fap_sec, sec_off, sz);
    1364:	9902      	ldr	r1, [sp, #8]
    1366:	4632      	mov	r2, r6
    1368:	4658      	mov	r0, fp
    136a:	f004 fba1 	bl	5ab0 <boot_erase_region>
        rc = boot_copy_region(state, fap_pri, fap_sec, pri_up_off, sec_off, sz);
    136e:	9b02      	ldr	r3, [sp, #8]
    1370:	9300      	str	r3, [sp, #0]
    1372:	e9dd 2303 	ldrd	r2, r3, [sp, #12]
    1376:	4649      	mov	r1, r9
    1378:	1a9b      	subs	r3, r3, r2
    137a:	9601      	str	r6, [sp, #4]
    137c:	465a      	mov	r2, fp
    137e:	4628      	mov	r0, r5
    1380:	f7ff fbf2 	bl	b68 <boot_copy_region>
        rc = boot_write_status(state, bs);
    1384:	4621      	mov	r1, r4
    1386:	4628      	mov	r0, r5
    1388:	f004 fb60 	bl	5a4c <boot_write_status>
        bs->idx++;
    138c:	6823      	ldr	r3, [r4, #0]
    138e:	3301      	adds	r3, #1
    1390:	6023      	str	r3, [r4, #0]
        bs->state = BOOT_STATUS_STATE_0;
    1392:	f04f 0301 	mov.w	r3, #1
    1396:	7123      	strb	r3, [r4, #4]
        BOOT_STATUS_ASSERT(rc == 0);
    1398:	b138      	cbz	r0, 13aa <swap_run+0x20a>
    139a:	f8d8 3000 	ldr.w	r3, [r8]
    139e:	3301      	adds	r3, #1
    13a0:	f8c8 3000 	str.w	r3, [r8]
    13a4:	e001      	b.n	13aa <swap_run+0x20a>
    if (bs->state == BOOT_STATUS_STATE_1) {
    13a6:	2902      	cmp	r1, #2
    13a8:	d0dc      	beq.n	1364 <swap_run+0x1c4>
        idx++;
    13aa:	3701      	adds	r7, #1
    13ac:	e755      	b.n	125a <swap_run+0xba>
    13ae:	bf00      	nop
    13b0:	000090b5 	.word	0x000090b5
    13b4:	20000004 	.word	0x20000004
    13b8:	000090de 	.word	0x000090de
    13bc:	0000910d 	.word	0x0000910d
    13c0:	20000df8 	.word	0x20000df8

000013c4 <nrf_cleanup_peripheral>:
    return (uint32_t)p_reg + task;
}

NRF_STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_reg, nrf_rtc_task_t task)
{
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    13c4:	4a13      	ldr	r2, [pc, #76]	; (1414 <nrf_cleanup_peripheral+0x50>)
    p_reg->EVTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    13c6:	f04f 33ff 	mov.w	r3, #4294967295
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    13ca:	2101      	movs	r1, #1
    13cc:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    13ce:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    13d2:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    13d6:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    13da:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    13dc:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    13e0:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    13e4:	f502 3298 	add.w	r2, r2, #77824	; 0x13000
    13e8:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    13ea:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    13ee:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
}

NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
{
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    13f2:	f5a2 3208 	sub.w	r2, r2, #139264	; 0x22000
    13f6:	2100      	movs	r1, #0
    13f8:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    13fc:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    }
}

NRF_STATIC_INLINE void nrf_ppi_channels_disable_all(NRF_PPI_Type * p_reg)
{
    p_reg->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
    1400:	f502 32e8 	add.w	r2, r2, #118784	; 0x1d000
    1404:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
    p_reg->INTENSET = mask;
}

NRF_STATIC_INLINE void nrf_clock_int_disable(NRF_CLOCK_Type * p_reg, uint32_t mask)
{
    p_reg->INTENCLR = mask;
    1408:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    140c:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
#endif
#if defined(NRF_DPPIC)
    nrf_dppi_channels_disable_all(NRF_DPPIC);
#endif
    nrf_cleanup_clock();
}
    1410:	4770      	bx	lr
    1412:	bf00      	nop
    1414:	4000b000 	.word	0x4000b000

00001418 <base64_encode>:
/*
 * Encode a buffer into base64 format
 */
int base64_encode(uint8_t *dst, size_t dlen, size_t *olen, const uint8_t *src,
		  size_t slen)
{
    1418:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    141c:	4605      	mov	r5, r0
    141e:	9807      	ldr	r0, [sp, #28]
	size_t i, n;
	int C1, C2, C3;
	uint8_t *p;

	if (slen == 0) {
    1420:	b910      	cbnz	r0, 1428 <base64_encode+0x10>
		*olen = 0;
    1422:	6010      	str	r0, [r2, #0]

	*olen = p - dst;
	*p = 0U;

	return 0;
}
    1424:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
	n = slen / 3 + (slen % 3 != 0);
    1428:	2403      	movs	r4, #3
    142a:	fbb0 f4f4 	udiv	r4, r0, r4
    142e:	eb04 0744 	add.w	r7, r4, r4, lsl #1
    1432:	42b8      	cmp	r0, r7
    1434:	bf18      	it	ne
    1436:	3401      	addne	r4, #1
	if (n > (BASE64_SIZE_T_MAX - 1) / 4) {
    1438:	f1b4 4f80 	cmp.w	r4, #1073741824	; 0x40000000
    143c:	d305      	bcc.n	144a <base64_encode+0x32>
		*olen = BASE64_SIZE_T_MAX;
    143e:	f04f 33ff 	mov.w	r3, #4294967295
    1442:	6013      	str	r3, [r2, #0]
		return -ENOMEM;
    1444:	f06f 000b 	mvn.w	r0, #11
    1448:	e7ec      	b.n	1424 <base64_encode+0xc>
	n *= 4;
    144a:	00a4      	lsls	r4, r4, #2
	if ((dlen < n + 1) || (!dst)) {
    144c:	3401      	adds	r4, #1
    144e:	428c      	cmp	r4, r1
    1450:	d800      	bhi.n	1454 <base64_encode+0x3c>
    1452:	b90d      	cbnz	r5, 1458 <base64_encode+0x40>
		*olen = n + 1;
    1454:	6014      	str	r4, [r2, #0]
    1456:	e7f5      	b.n	1444 <base64_encode+0x2c>
		*p++ = base64_enc_map[(C1 >> 2) & 0x3F];
    1458:	f8df e0bc 	ldr.w	lr, [pc, #188]	; 1518 <base64_encode+0x100>
    145c:	462e      	mov	r6, r5
	for (i = 0, p = dst; i < n; i += 3) {
    145e:	2400      	movs	r4, #0
    1460:	42bc      	cmp	r4, r7
    1462:	4631      	mov	r1, r6
    1464:	469c      	mov	ip, r3
    1466:	f106 0604 	add.w	r6, r6, #4
    146a:	f103 0303 	add.w	r3, r3, #3
    146e:	d32c      	bcc.n	14ca <base64_encode+0xb2>
	if (i < slen) {
    1470:	4284      	cmp	r4, r0
    1472:	d225      	bcs.n	14c0 <base64_encode+0xa8>
		C1 = *src++;
    1474:	f89c 6000 	ldrb.w	r6, [ip]
		*p++ = base64_enc_map[(C1 >> 2) & 0x3F];
    1478:	4f27      	ldr	r7, [pc, #156]	; (1518 <base64_encode+0x100>)
		C2 = ((i + 1) < slen) ? *src++ : 0;
    147a:	3401      	adds	r4, #1
    147c:	4284      	cmp	r4, r0
    147e:	bf38      	it	cc
    1480:	f89c 3001 	ldrbcc.w	r3, [ip, #1]
		*p++ = base64_enc_map[(C1 >> 2) & 0x3F];
    1484:	ea4f 0ca6 	mov.w	ip, r6, asr #2
		C2 = ((i + 1) < slen) ? *src++ : 0;
    1488:	bf28      	it	cs
    148a:	2300      	movcs	r3, #0
		*p++ = base64_enc_map[(C1 >> 2) & 0x3F];
    148c:	f817 c00c 	ldrb.w	ip, [r7, ip]
    1490:	f881 c000 	strb.w	ip, [r1]
		if ((i + 1) < slen) {
    1494:	4284      	cmp	r4, r0
		*p++ = base64_enc_map[(((C1 & 3) << 4) + (C2 >> 4)) & 0x3F];
    1496:	eb07 1c13 	add.w	ip, r7, r3, lsr #4
			*p++ = base64_enc_map[((C2 & 15) << 2) & 0x3F];
    149a:	bf3c      	itt	cc
    149c:	009b      	lslcc	r3, r3, #2
    149e:	f003 033c 	andcc.w	r3, r3, #60	; 0x3c
		*p++ = base64_enc_map[(((C1 & 3) << 4) + (C2 >> 4)) & 0x3F];
    14a2:	ea4f 1606 	mov.w	r6, r6, lsl #4
    14a6:	f006 0630 	and.w	r6, r6, #48	; 0x30
			*p++ = base64_enc_map[((C2 & 15) << 2) & 0x3F];
    14aa:	bf38      	it	cc
    14ac:	5cfb      	ldrbcc	r3, [r7, r3]
		*p++ = base64_enc_map[(((C1 & 3) << 4) + (C2 >> 4)) & 0x3F];
    14ae:	f81c 6006 	ldrb.w	r6, [ip, r6]
    14b2:	704e      	strb	r6, [r1, #1]
			*p++ = '=';
    14b4:	bf28      	it	cs
    14b6:	233d      	movcs	r3, #61	; 0x3d
    14b8:	708b      	strb	r3, [r1, #2]
		*p++ = '=';
    14ba:	233d      	movs	r3, #61	; 0x3d
    14bc:	70cb      	strb	r3, [r1, #3]
    14be:	3104      	adds	r1, #4
	*olen = p - dst;
    14c0:	1b4d      	subs	r5, r1, r5
	*p = 0U;
    14c2:	2000      	movs	r0, #0
	*olen = p - dst;
    14c4:	6015      	str	r5, [r2, #0]
	*p = 0U;
    14c6:	7008      	strb	r0, [r1, #0]
	return 0;
    14c8:	e7ac      	b.n	1424 <base64_encode+0xc>
		C1 = *src++;
    14ca:	f813 cc03 	ldrb.w	ip, [r3, #-3]
		C2 = *src++;
    14ce:	f813 1c02 	ldrb.w	r1, [r3, #-2]
		C3 = *src++;
    14d2:	f813 8c01 	ldrb.w	r8, [r3, #-1]
		*p++ = base64_enc_map[(C1 >> 2) & 0x3F];
    14d6:	ea4f 09ac 	mov.w	r9, ip, asr #2
		*p++ = base64_enc_map[(((C1 &  3) << 4) + (C2 >> 4)) & 0x3F];
    14da:	ea4f 1c0c 	mov.w	ip, ip, lsl #4
		*p++ = base64_enc_map[(C1 >> 2) & 0x3F];
    14de:	f81e 9009 	ldrb.w	r9, [lr, r9]
    14e2:	f806 9c04 	strb.w	r9, [r6, #-4]
		*p++ = base64_enc_map[(((C1 &  3) << 4) + (C2 >> 4)) & 0x3F];
    14e6:	f00c 0c30 	and.w	ip, ip, #48	; 0x30
    14ea:	eb0e 1911 	add.w	r9, lr, r1, lsr #4
		*p++ = base64_enc_map[(((C2 & 15) << 2) + (C3 >> 6)) & 0x3F];
    14ee:	0089      	lsls	r1, r1, #2
		*p++ = base64_enc_map[(((C1 &  3) << 4) + (C2 >> 4)) & 0x3F];
    14f0:	f819 c00c 	ldrb.w	ip, [r9, ip]
    14f4:	f806 cc03 	strb.w	ip, [r6, #-3]
		*p++ = base64_enc_map[(((C2 & 15) << 2) + (C3 >> 6)) & 0x3F];
    14f8:	f001 013c 	and.w	r1, r1, #60	; 0x3c
    14fc:	eb0e 1c98 	add.w	ip, lr, r8, lsr #6
		*p++ = base64_enc_map[C3 & 0x3F];
    1500:	f008 083f 	and.w	r8, r8, #63	; 0x3f
		*p++ = base64_enc_map[(((C2 & 15) << 2) + (C3 >> 6)) & 0x3F];
    1504:	f81c 1001 	ldrb.w	r1, [ip, r1]
    1508:	f806 1c02 	strb.w	r1, [r6, #-2]
		*p++ = base64_enc_map[C3 & 0x3F];
    150c:	f81e 1008 	ldrb.w	r1, [lr, r8]
    1510:	f806 1c01 	strb.w	r1, [r6, #-1]
	for (i = 0, p = dst; i < n; i += 3) {
    1514:	3403      	adds	r4, #3
    1516:	e7a3      	b.n	1460 <base64_encode+0x48>
    1518:	000092cc 	.word	0x000092cc

0000151c <base64_decode>:
/*
 * Decode a base64-formatted buffer
 */
int base64_decode(uint8_t *dst, size_t dlen, size_t *olen, const uint8_t *src,
		  size_t slen)
{
    151c:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    1520:	468c      	mov	ip, r1
    1522:	9e07      	ldr	r6, [sp, #28]

		if (src[i] == '=' && ++j > 2) {
			return -EINVAL;
		}

		if (src[i] > 127 || base64_dec_map[src[i]] == 127U) {
    1524:	f8df 8120 	ldr.w	r8, [pc, #288]	; 1648 <base64_decode+0x12c>
	for (i = n = j = 0U; i < slen; i++) {
    1528:	2100      	movs	r1, #0
{
    152a:	4607      	mov	r7, r0
	for (i = n = j = 0U; i < slen; i++) {
    152c:	460d      	mov	r5, r1
    152e:	4608      	mov	r0, r1
    1530:	42b5      	cmp	r5, r6
    1532:	d30a      	bcc.n	154a <base64_decode+0x2e>
    1534:	462e      	mov	r6, r5
    1536:	e004      	b.n	1542 <base64_decode+0x26>
			++i;
    1538:	3501      	adds	r5, #1
		while (i < slen && src[i] == ' ') {
    153a:	42ae      	cmp	r6, r5
			++x;
    153c:	f10e 0e01 	add.w	lr, lr, #1
		while (i < slen && src[i] == ' ') {
    1540:	d105      	bne.n	154e <base64_decode+0x32>
		}

		n++;
	}

	if (n == 0) {
    1542:	bb90      	cbnz	r0, 15aa <base64_decode+0x8e>
		*olen = 0;
    1544:	6010      	str	r0, [r2, #0]
	}

	*olen = p - dst;

	return 0;
}
    1546:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
		x = 0U;
    154a:	f04f 0e00 	mov.w	lr, #0
		while (i < slen && src[i] == ' ') {
    154e:	5d5c      	ldrb	r4, [r3, r5]
    1550:	2c20      	cmp	r4, #32
    1552:	d0f1      	beq.n	1538 <base64_decode+0x1c>
		if (i == slen) {
    1554:	42ae      	cmp	r6, r5
    1556:	d0f4      	beq.n	1542 <base64_decode+0x26>
		if ((slen - i) >= 2 && src[i] == '\r' && src[i + 1] == '\n') {
    1558:	eba6 0905 	sub.w	r9, r6, r5
    155c:	f1b9 0f01 	cmp.w	r9, #1
    1560:	d013      	beq.n	158a <base64_decode+0x6e>
    1562:	2c0d      	cmp	r4, #13
    1564:	d111      	bne.n	158a <base64_decode+0x6e>
    1566:	eb03 0905 	add.w	r9, r3, r5
    156a:	f899 9001 	ldrb.w	r9, [r9, #1]
    156e:	f1b9 0f0a 	cmp.w	r9, #10
		if (src[i] == '\n') {
    1572:	d018      	beq.n	15a6 <base64_decode+0x8a>
		if (x != 0U) {
    1574:	f1be 0f00 	cmp.w	lr, #0
    1578:	d104      	bne.n	1584 <base64_decode+0x68>
		if (src[i] == '=' && ++j > 2) {
    157a:	2c3d      	cmp	r4, #61	; 0x3d
    157c:	d107      	bne.n	158e <base64_decode+0x72>
    157e:	3101      	adds	r1, #1
    1580:	2902      	cmp	r1, #2
    1582:	d907      	bls.n	1594 <base64_decode+0x78>
			return -EINVAL;
    1584:	f06f 0015 	mvn.w	r0, #21
    1588:	e7dd      	b.n	1546 <base64_decode+0x2a>
		if (src[i] == '\n') {
    158a:	2c0a      	cmp	r4, #10
    158c:	e7f1      	b.n	1572 <base64_decode+0x56>
		if (src[i] > 127 || base64_dec_map[src[i]] == 127U) {
    158e:	f014 0f80 	tst.w	r4, #128	; 0x80
    1592:	d1f7      	bne.n	1584 <base64_decode+0x68>
    1594:	f818 4004 	ldrb.w	r4, [r8, r4]
    1598:	2c7f      	cmp	r4, #127	; 0x7f
    159a:	d0f3      	beq.n	1584 <base64_decode+0x68>
		if (base64_dec_map[src[i]] < 64 && j != 0U) {
    159c:	2c3f      	cmp	r4, #63	; 0x3f
    159e:	d801      	bhi.n	15a4 <base64_decode+0x88>
    15a0:	2900      	cmp	r1, #0
    15a2:	d1ef      	bne.n	1584 <base64_decode+0x68>
		n++;
    15a4:	3001      	adds	r0, #1
	for (i = n = j = 0U; i < slen; i++) {
    15a6:	3501      	adds	r5, #1
    15a8:	e7c2      	b.n	1530 <base64_decode+0x14>
	n = (6 * (n >> 3)) + ((6 * (n & 0x7) + 7) >> 3);
    15aa:	f04f 0e06 	mov.w	lr, #6
    15ae:	f000 0507 	and.w	r5, r0, #7
    15b2:	08c4      	lsrs	r4, r0, #3
    15b4:	fb0e f505 	mul.w	r5, lr, r5
    15b8:	fb0e f404 	mul.w	r4, lr, r4
    15bc:	3507      	adds	r5, #7
	n -= j;
    15be:	1a64      	subs	r4, r4, r1
    15c0:	eb04 04d5 	add.w	r4, r4, r5, lsr #3
	if (dst == NULL || dlen < n) {
    15c4:	b18f      	cbz	r7, 15ea <base64_decode+0xce>
    15c6:	4564      	cmp	r4, ip
    15c8:	d80f      	bhi.n	15ea <base64_decode+0xce>
	for (j = 3U, n = x = 0U, p = dst; i > 0; i--, src++) {
    15ca:	2400      	movs	r4, #0
		j -= (base64_dec_map[*src] == 64U);
    15cc:	f8df e078 	ldr.w	lr, [pc, #120]	; 1648 <base64_decode+0x12c>
		if (*src == '\r' || *src == '\n' || *src == ' ') {
    15d0:	f8df 8078 	ldr.w	r8, [pc, #120]	; 164c <base64_decode+0x130>
    15d4:	469c      	mov	ip, r3
    15d6:	441e      	add	r6, r3
	for (j = 3U, n = x = 0U, p = dst; i > 0; i--, src++) {
    15d8:	2003      	movs	r0, #3
	if (dst == NULL || dlen < n) {
    15da:	463b      	mov	r3, r7
	for (j = 3U, n = x = 0U, p = dst; i > 0; i--, src++) {
    15dc:	4621      	mov	r1, r4
    15de:	4566      	cmp	r6, ip
    15e0:	d107      	bne.n	15f2 <base64_decode+0xd6>
	*olen = p - dst;
    15e2:	1bdb      	subs	r3, r3, r7
    15e4:	6013      	str	r3, [r2, #0]
	return 0;
    15e6:	2000      	movs	r0, #0
    15e8:	e7ad      	b.n	1546 <base64_decode+0x2a>
		*olen = n;
    15ea:	6014      	str	r4, [r2, #0]
		return -ENOMEM;
    15ec:	f06f 000b 	mvn.w	r0, #11
    15f0:	e7a9      	b.n	1546 <base64_decode+0x2a>
		if (*src == '\r' || *src == '\n' || *src == ' ') {
    15f2:	f81c 9b01 	ldrb.w	r9, [ip], #1
    15f6:	f1a9 050a 	sub.w	r5, r9, #10
    15fa:	b2ed      	uxtb	r5, r5
    15fc:	2d16      	cmp	r5, #22
    15fe:	d803      	bhi.n	1608 <base64_decode+0xec>
    1600:	fa28 f505 	lsr.w	r5, r8, r5
    1604:	07ed      	lsls	r5, r5, #31
    1606:	d4ea      	bmi.n	15de <base64_decode+0xc2>
		j -= (base64_dec_map[*src] == 64U);
    1608:	f81e 5009 	ldrb.w	r5, [lr, r9]
		if (++n == 4) {
    160c:	3101      	adds	r1, #1
		j -= (base64_dec_map[*src] == 64U);
    160e:	2d40      	cmp	r5, #64	; 0x40
    1610:	bf08      	it	eq
    1612:	3801      	subeq	r0, #1
		x  = (x << 6) | (base64_dec_map[*src] & 0x3F);
    1614:	f005 053f 	and.w	r5, r5, #63	; 0x3f
		if (++n == 4) {
    1618:	2904      	cmp	r1, #4
		x  = (x << 6) | (base64_dec_map[*src] & 0x3F);
    161a:	ea45 1484 	orr.w	r4, r5, r4, lsl #6
		if (++n == 4) {
    161e:	d1de      	bne.n	15de <base64_decode+0xc2>
			if (j > 0) {
    1620:	b178      	cbz	r0, 1642 <base64_decode+0x126>
				*p++ = (unsigned char)(x >> 16);
    1622:	0c21      	lsrs	r1, r4, #16
			if (j > 1) {
    1624:	2801      	cmp	r0, #1
				*p++ = (unsigned char)(x >> 16);
    1626:	7019      	strb	r1, [r3, #0]
			if (j > 1) {
    1628:	d102      	bne.n	1630 <base64_decode+0x114>
				*p++ = (unsigned char)(x >> 16);
    162a:	3301      	adds	r3, #1
			n = 0;
    162c:	2100      	movs	r1, #0
    162e:	e7d6      	b.n	15de <base64_decode+0xc2>
			if (j > 2) {
    1630:	2802      	cmp	r0, #2
				*p++ = (unsigned char)(x >> 8);
    1632:	ea4f 2114 	mov.w	r1, r4, lsr #8
    1636:	7059      	strb	r1, [r3, #1]
				*p++ = (unsigned char)(x);
    1638:	bf16      	itet	ne
    163a:	709c      	strbne	r4, [r3, #2]
				*p++ = (unsigned char)(x >> 8);
    163c:	3302      	addeq	r3, #2
				*p++ = (unsigned char)(x);
    163e:	3303      	addne	r3, #3
    1640:	e7f4      	b.n	162c <base64_decode+0x110>
			n = 0;
    1642:	4601      	mov	r1, r0
	for (j = 3U, n = x = 0U, p = dst; i > 0; i--, src++) {
    1644:	e7cb      	b.n	15de <base64_decode+0xc2>
    1646:	bf00      	nop
    1648:	0000924c 	.word	0x0000924c
    164c:	00400009 	.word	0x00400009

00001650 <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
    1650:	680b      	ldr	r3, [r1, #0]
    1652:	3301      	adds	r3, #1
    1654:	600b      	str	r3, [r1, #0]
	return _char_out(c);
    1656:	4b01      	ldr	r3, [pc, #4]	; (165c <char_out+0xc>)
    1658:	681b      	ldr	r3, [r3, #0]
    165a:	4718      	bx	r3
    165c:	20000008 	.word	0x20000008

00001660 <__printk_hook_install>:
	_char_out = fn;
    1660:	4b01      	ldr	r3, [pc, #4]	; (1668 <__printk_hook_install+0x8>)
    1662:	6018      	str	r0, [r3, #0]
}
    1664:	4770      	bx	lr
    1666:	bf00      	nop
    1668:	20000008 	.word	0x20000008

0000166c <vprintk>:
}

void vprintk(const char *fmt, va_list ap)
{
    166c:	b507      	push	{r0, r1, r2, lr}
    166e:	460b      	mov	r3, r1

		if (ctx.buf_count) {
			buf_flush(&ctx);
		}
	} else {
		struct out_context ctx = { 0 };
    1670:	2100      	movs	r1, #0
{
    1672:	4602      	mov	r2, r0
		struct out_context ctx = { 0 };
    1674:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
		k_spinlock_key_t key = k_spin_lock(&lock);
#endif

		cbvprintf(char_out, &ctx, fmt, ap);
    1676:	4803      	ldr	r0, [pc, #12]	; (1684 <vprintk+0x18>)
    1678:	a901      	add	r1, sp, #4
    167a:	f000 f8e5 	bl	1848 <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
		k_spin_unlock(&lock, key);
#endif
	}
}
    167e:	b003      	add	sp, #12
    1680:	f85d fb04 	ldr.w	pc, [sp], #4
    1684:	00001651 	.word	0x00001651

00001688 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
    1688:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    168c:	f8b0 9018 	ldrh.w	r9, [r0, #24]
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
    1690:	f019 0808 	ands.w	r8, r9, #8
{
    1694:	4604      	mov	r4, r0
    1696:	4693      	mov	fp, r2
	if (processing) {
    1698:	d00d      	beq.n	16b6 <process_event+0x2e>
		if (evt == EVT_COMPLETE) {
    169a:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
    169c:	bf0c      	ite	eq
    169e:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
    16a2:	f049 0920 	orrne.w	r9, r9, #32
    16a6:	f8a0 9018 	strh.w	r9, [r0, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
    16aa:	f38b 8811 	msr	BASEPRI, fp
    16ae:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
    16b2:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    16b6:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
    16ba:	2902      	cmp	r1, #2
    16bc:	d107      	bne.n	16ce <process_event+0x46>
			evt = process_recheck(mgr);
    16be:	4620      	mov	r0, r4
    16c0:	f004 fb11 	bl	5ce6 <process_recheck>
		if (evt == EVT_NOP) {
    16c4:	2800      	cmp	r0, #0
    16c6:	d0f0      	beq.n	16aa <process_event+0x22>
		if (evt == EVT_COMPLETE) {
    16c8:	2801      	cmp	r0, #1
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    16ca:	8b23      	ldrh	r3, [r4, #24]
		if (evt == EVT_COMPLETE) {
    16cc:	d14e      	bne.n	176c <process_event+0xe4>
			res = mgr->last_res;
    16ce:	6967      	ldr	r7, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    16d0:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
    16d2:	2f00      	cmp	r7, #0
    16d4:	da15      	bge.n	1702 <process_event+0x7a>
		*clients = mgr->clients;
    16d6:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    16d8:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
    16dc:	e9c4 8800 	strd	r8, r8, [r4]
    16e0:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
    16e4:	8321      	strh	r1, [r4, #24]
		onoff_transition_fn transit = NULL;
    16e6:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    16e8:	8b21      	ldrh	r1, [r4, #24]
    16ea:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
    16ee:	45ca      	cmp	sl, r9
    16f0:	d002      	beq.n	16f8 <process_event+0x70>
		if (do_monitors
    16f2:	68a3      	ldr	r3, [r4, #8]
    16f4:	2b00      	cmp	r3, #0
    16f6:	d15a      	bne.n	17ae <process_event+0x126>
		    || !sys_slist_is_empty(&clients)
    16f8:	b90d      	cbnz	r5, 16fe <process_event+0x76>
		    || (transit != NULL)) {
    16fa:	2e00      	cmp	r6, #0
    16fc:	d071      	beq.n	17e2 <process_event+0x15a>
    16fe:	2300      	movs	r3, #0
    1700:	e056      	b.n	17b0 <process_event+0x128>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    1702:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
    1706:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
    1708:	2a01      	cmp	r2, #1
    170a:	d81e      	bhi.n	174a <process_event+0xc2>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    170c:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
    1710:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
    1712:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1714:	b289      	uxth	r1, r1
    1716:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
    171a:	d10a      	bne.n	1732 <process_event+0xaa>
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    171c:	b13d      	cbz	r5, 172e <process_event+0xa6>
    171e:	8b63      	ldrh	r3, [r4, #26]
    1720:	462a      	mov	r2, r5

#define SYS_SLIST_STATIC_INIT(ptr_to_list) {NULL, NULL}

static inline sys_snode_t *z_snode_next_peek(sys_snode_t *node)
{
	return node->next;
    1722:	6812      	ldr	r2, [r2, #0]
				mgr->refs += 1U;
    1724:	3301      	adds	r3, #1
    1726:	b29b      	uxth	r3, r3
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    1728:	2a00      	cmp	r2, #0
    172a:	d1fa      	bne.n	1722 <process_event+0x9a>
    172c:	8363      	strh	r3, [r4, #26]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    172e:	f041 0102 	orr.w	r1, r1, #2
	mgr->flags = (state & ONOFF_STATE_MASK)
    1732:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    1734:	4620      	mov	r0, r4
    1736:	f004 fad6 	bl	5ce6 <process_recheck>
    173a:	4606      	mov	r6, r0
    173c:	2800      	cmp	r0, #0
    173e:	d0d3      	beq.n	16e8 <process_event+0x60>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    1740:	8b23      	ldrh	r3, [r4, #24]
    1742:	f043 0320 	orr.w	r3, r3, #32
    1746:	8323      	strh	r3, [r4, #24]
    1748:	e7cd      	b.n	16e6 <process_event+0x5e>
	} else if (state == ONOFF_STATE_TO_OFF) {
    174a:	2b04      	cmp	r3, #4
    174c:	d10c      	bne.n	1768 <process_event+0xe0>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    174e:	f021 0107 	bic.w	r1, r1, #7
    1752:	b289      	uxth	r1, r1
	mgr->flags = (state & ONOFF_STATE_MASK)
    1754:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    1756:	4620      	mov	r0, r4
    1758:	f004 fac5 	bl	5ce6 <process_recheck>
    175c:	4605      	mov	r5, r0
    175e:	2800      	cmp	r0, #0
    1760:	d0c1      	beq.n	16e6 <process_event+0x5e>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    1762:	f041 0120 	orr.w	r1, r1, #32
    1766:	8321      	strh	r1, [r4, #24]
    1768:	2500      	movs	r5, #0
    176a:	e7bc      	b.n	16e6 <process_event+0x5e>
		} else if (evt == EVT_START) {
    176c:	2803      	cmp	r0, #3
    176e:	d109      	bne.n	1784 <process_event+0xfc>
			transit = mgr->transitions->start;
    1770:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1772:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
    1776:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1778:	f043 0306 	orr.w	r3, r3, #6
	mgr->flags = (state & ONOFF_STATE_MASK)
    177c:	8323      	strh	r3, [r4, #24]
}
    177e:	2500      	movs	r5, #0
		res = 0;
    1780:	462f      	mov	r7, r5
    1782:	e7b1      	b.n	16e8 <process_event+0x60>
		} else if (evt == EVT_STOP) {
    1784:	2804      	cmp	r0, #4
    1786:	d106      	bne.n	1796 <process_event+0x10e>
			transit = mgr->transitions->stop;
    1788:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    178a:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
    178e:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1790:	f043 0304 	orr.w	r3, r3, #4
    1794:	e7f2      	b.n	177c <process_event+0xf4>
		} else if (evt == EVT_RESET) {
    1796:	2805      	cmp	r0, #5
    1798:	d106      	bne.n	17a8 <process_event+0x120>
			transit = mgr->transitions->reset;
    179a:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    179c:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
    17a0:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    17a2:	f043 0305 	orr.w	r3, r3, #5
    17a6:	e7e9      	b.n	177c <process_event+0xf4>
    17a8:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
    17aa:	462e      	mov	r6, r5
    17ac:	e7e8      	b.n	1780 <process_event+0xf8>
				   && !sys_slist_is_empty(&mgr->monitors);
    17ae:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
    17b0:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
    17b4:	8321      	strh	r1, [r4, #24]
    17b6:	f38b 8811 	msr	BASEPRI, fp
    17ba:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
    17be:	b9fb      	cbnz	r3, 1800 <process_event+0x178>
	while (!sys_slist_is_empty(list)) {
    17c0:	bb85      	cbnz	r5, 1824 <process_event+0x19c>
			if (transit != NULL) {
    17c2:	b116      	cbz	r6, 17ca <process_event+0x142>
				transit(mgr, transition_complete);
    17c4:	491f      	ldr	r1, [pc, #124]	; (1844 <process_event+0x1bc>)
    17c6:	4620      	mov	r0, r4
    17c8:	47b0      	blx	r6
	__asm__ volatile(
    17ca:	f04f 0320 	mov.w	r3, #32
    17ce:	f3ef 8b11 	mrs	fp, BASEPRI
    17d2:	f383 8812 	msr	BASEPRI_MAX, r3
    17d6:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
    17da:	8b23      	ldrh	r3, [r4, #24]
    17dc:	f023 0308 	bic.w	r3, r3, #8
    17e0:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
    17e2:	8b23      	ldrh	r3, [r4, #24]
    17e4:	06da      	lsls	r2, r3, #27
    17e6:	d525      	bpl.n	1834 <process_event+0x1ac>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
    17e8:	f023 0310 	bic.w	r3, r3, #16
    17ec:	8323      	strh	r3, [r4, #24]
			evt = EVT_COMPLETE;
    17ee:	2101      	movs	r1, #1
		state = mgr->flags & ONOFF_STATE_MASK;
    17f0:	f8b4 9018 	ldrh.w	r9, [r4, #24]
    17f4:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
    17f8:	2900      	cmp	r1, #0
    17fa:	f47f af5e 	bne.w	16ba <process_event+0x32>
out:
    17fe:	e754      	b.n	16aa <process_event+0x22>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
    1800:	68a1      	ldr	r1, [r4, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    1802:	2900      	cmp	r1, #0
    1804:	d0dc      	beq.n	17c0 <process_event+0x138>
	return node->next;
    1806:	f8d1 9000 	ldr.w	r9, [r1]
		mon->callback(mgr, mon, state, res);
    180a:	f8d1 b004 	ldr.w	fp, [r1, #4]
    180e:	463b      	mov	r3, r7
    1810:	4652      	mov	r2, sl
    1812:	4620      	mov	r0, r4
    1814:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    1816:	f1b9 0f00 	cmp.w	r9, #0
    181a:	d0d1      	beq.n	17c0 <process_event+0x138>
    181c:	4649      	mov	r1, r9
    181e:	f8d9 9000 	ldr.w	r9, [r9]
    1822:	e7f2      	b.n	180a <process_event+0x182>
    1824:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
    1826:	463b      	mov	r3, r7
    1828:	4652      	mov	r2, sl
    182a:	4620      	mov	r0, r4
    182c:	682d      	ldr	r5, [r5, #0]
    182e:	f004 fa76 	bl	5d1e <notify_one>
    1832:	e7c5      	b.n	17c0 <process_event+0x138>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
    1834:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
    1838:	bf1e      	ittt	ne
    183a:	f023 0320 	bicne.w	r3, r3, #32
    183e:	8323      	strhne	r3, [r4, #24]
			evt = EVT_RECHECK;
    1840:	2102      	movne	r1, #2
    1842:	e7d5      	b.n	17f0 <process_event+0x168>
    1844:	00005d4b 	.word	0x00005d4b

00001848 <cbvprintf>:
 * @param ap Variable parameters
 *
 * @return printed byte count if CONFIG_CBPRINTF_LIBC_SUBSTS is set
 */
int cbvprintf(cbprintf_cb out, void *ctx, const char *fmt, va_list ap)
{
    1848:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    184c:	b08f      	sub	sp, #60	; 0x3c
    184e:	461d      	mov	r5, r3
	char *prefix, *data;
	int min_width, precision, data_len;
	char padding_mode, length_mod, special;

	/* we pre-increment in the loop  afterwards */
	fmt--;
    1850:	1e53      	subs	r3, r2, #1
{
    1852:	9001      	str	r0, [sp, #4]
    1854:	468a      	mov	sl, r1
	fmt--;
    1856:	9302      	str	r3, [sp, #8]
	size_t count = 0;
    1858:	f04f 0900 	mov.w	r9, #0

start:
	while (*++fmt != '%') {
    185c:	9b02      	ldr	r3, [sp, #8]
    185e:	7858      	ldrb	r0, [r3, #1]
    1860:	2825      	cmp	r0, #37	; 0x25
    1862:	f103 0401 	add.w	r4, r3, #1
    1866:	d121      	bne.n	18ac <cbvprintf+0x64>
	min_width = -1;
	precision = -1;
	prefix = "";
	padding_mode = 0;
	length_mod = 0;
	special = 0;
    1868:	f04f 0c00 	mov.w	ip, #0

	for (fmt++ ; ; fmt++) {
    186c:	4618      	mov	r0, r3
	precision = -1;
    186e:	f04f 37ff 	mov.w	r7, #4294967295
	for (fmt++ ; ; fmt++) {
    1872:	3002      	adds	r0, #2
	length_mod = 0;
    1874:	4661      	mov	r1, ip
	padding_mode = 0;
    1876:	f8cd c00c 	str.w	ip, [sp, #12]
	min_width = -1;
    187a:	463c      	mov	r4, r7
				precision = 10 * precision + *fmt - '0';
			} else {
				if (min_width < 0) {
					min_width = 0;
				}
				min_width = 10 * min_width + *fmt - '0';
    187c:	260a      	movs	r6, #10
		switch (*fmt) {
    187e:	7802      	ldrb	r2, [r0, #0]
    1880:	9002      	str	r0, [sp, #8]
    1882:	2a39      	cmp	r2, #57	; 0x39
    1884:	f100 0001 	add.w	r0, r0, #1
    1888:	d858      	bhi.n	193c <cbvprintf+0xf4>
    188a:	2a1f      	cmp	r2, #31
    188c:	d818      	bhi.n	18c0 <cbvprintf+0x78>
    188e:	2a00      	cmp	r2, #0
    1890:	f000 81f6 	beq.w	1c80 <cbvprintf+0x438>
			precision = 0;
			break;
		}

		default:
			OUTC('%');
    1894:	9b01      	ldr	r3, [sp, #4]
    1896:	4651      	mov	r1, sl
    1898:	2025      	movs	r0, #37	; 0x25
    189a:	4798      	blx	r3
			OUTC(*fmt);
    189c:	9b02      	ldr	r3, [sp, #8]
    189e:	4651      	mov	r1, sl
    18a0:	7818      	ldrb	r0, [r3, #0]
    18a2:	9b01      	ldr	r3, [sp, #4]
    18a4:	4798      	blx	r3
    18a6:	f109 0902 	add.w	r9, r9, #2
			goto start;
    18aa:	e7d7      	b.n	185c <cbvprintf+0x14>
		if (*fmt == '\0') {
    18ac:	2800      	cmp	r0, #0
    18ae:	f000 81e7 	beq.w	1c80 <cbvprintf+0x438>
		OUTC(*fmt);
    18b2:	9b01      	ldr	r3, [sp, #4]
    18b4:	4651      	mov	r1, sl
    18b6:	4798      	blx	r3
    18b8:	f109 0901 	add.w	r9, r9, #1
	while (*++fmt != '%') {
    18bc:	9402      	str	r4, [sp, #8]
    18be:	e7cd      	b.n	185c <cbvprintf+0x14>
		switch (*fmt) {
    18c0:	f1a2 0320 	sub.w	r3, r2, #32
    18c4:	2b19      	cmp	r3, #25
    18c6:	d8e5      	bhi.n	1894 <cbvprintf+0x4c>
    18c8:	f20f 0e04 	addw	lr, pc, #4
    18cc:	f85e f023 	ldr.w	pc, [lr, r3, lsl #2]
    18d0:	00001939 	.word	0x00001939
    18d4:	00001895 	.word	0x00001895
    18d8:	00001895 	.word	0x00001895
    18dc:	00001939 	.word	0x00001939
    18e0:	00001895 	.word	0x00001895
    18e4:	000019bd 	.word	0x000019bd
    18e8:	00001895 	.word	0x00001895
    18ec:	00001895 	.word	0x00001895
    18f0:	00001895 	.word	0x00001895
    18f4:	00001895 	.word	0x00001895
    18f8:	000019ff 	.word	0x000019ff
    18fc:	00001939 	.word	0x00001939
    1900:	00001895 	.word	0x00001895
    1904:	00001a13 	.word	0x00001a13
    1908:	000019cb 	.word	0x000019cb
    190c:	00001895 	.word	0x00001895
    1910:	000019d7 	.word	0x000019d7
    1914:	000019f3 	.word	0x000019f3
    1918:	000019f3 	.word	0x000019f3
    191c:	000019f3 	.word	0x000019f3
    1920:	000019f3 	.word	0x000019f3
    1924:	000019f3 	.word	0x000019f3
    1928:	000019f3 	.word	0x000019f3
    192c:	000019f3 	.word	0x000019f3
    1930:	000019f3 	.word	0x000019f3
    1934:	000019f3 	.word	0x000019f3
    1938:	4694      	mov	ip, r2
    193a:	e7a0      	b.n	187e <cbvprintf+0x36>
    193c:	2a58      	cmp	r2, #88	; 0x58
    193e:	f000 811b 	beq.w	1b78 <cbvprintf+0x330>
    1942:	f1a2 0363 	sub.w	r3, r2, #99	; 0x63
    1946:	fa5f fe83 	uxtb.w	lr, r3
    194a:	f1be 0f17 	cmp.w	lr, #23
    194e:	d8a1      	bhi.n	1894 <cbvprintf+0x4c>
    1950:	2b17      	cmp	r3, #23
    1952:	d89f      	bhi.n	1894 <cbvprintf+0x4c>
    1954:	f20f 0e04 	addw	lr, pc, #4
    1958:	f85e f023 	ldr.w	pc, [lr, r3, lsl #2]
    195c:	00001bdb 	.word	0x00001bdb
    1960:	00001a39 	.word	0x00001a39
    1964:	00001895 	.word	0x00001895
    1968:	00001895 	.word	0x00001895
    196c:	00001895 	.word	0x00001895
    1970:	00001a19 	.word	0x00001a19
    1974:	00001a39 	.word	0x00001a39
    1978:	00001895 	.word	0x00001895
    197c:	00001895 	.word	0x00001895
    1980:	00001a19 	.word	0x00001a19
    1984:	00001895 	.word	0x00001895
    1988:	00001895 	.word	0x00001895
    198c:	00001895 	.word	0x00001895
    1990:	00001b23 	.word	0x00001b23
    1994:	00001895 	.word	0x00001895
    1998:	00001895 	.word	0x00001895
    199c:	00001bbb 	.word	0x00001bbb
    19a0:	00001895 	.word	0x00001895
    19a4:	00001a39 	.word	0x00001a39
    19a8:	00001895 	.word	0x00001895
    19ac:	00001895 	.word	0x00001895
    19b0:	00001b23 	.word	0x00001b23
    19b4:	00001895 	.word	0x00001895
    19b8:	00001a19 	.word	0x00001a19
			OUTC('%');
    19bc:	9b01      	ldr	r3, [sp, #4]
    19be:	4651      	mov	r1, sl
    19c0:	2025      	movs	r0, #37	; 0x25
    19c2:	4798      	blx	r3
    19c4:	f109 0901 	add.w	r9, r9, #1
			goto start;
    19c8:	e748      	b.n	185c <cbvprintf+0x14>
			padding_mode &= (char)~PAD_ZERO;
    19ca:	9b03      	ldr	r3, [sp, #12]
    19cc:	f003 03fe 	and.w	r3, r3, #254	; 0xfe
    19d0:	9303      	str	r3, [sp, #12]
			precision = 0;
    19d2:	2700      	movs	r7, #0
			continue;
    19d4:	e753      	b.n	187e <cbvprintf+0x36>
			if (min_width < 0 && precision < 0 && !padding_mode) {
    19d6:	2c00      	cmp	r4, #0
    19d8:	da0b      	bge.n	19f2 <cbvprintf+0x1aa>
    19da:	2f00      	cmp	r7, #0
    19dc:	da0b      	bge.n	19f6 <cbvprintf+0x1ae>
    19de:	9b03      	ldr	r3, [sp, #12]
    19e0:	2b00      	cmp	r3, #0
    19e2:	f000 8149 	beq.w	1c78 <cbvprintf+0x430>
				min_width = 10 * min_width + *fmt - '0';
    19e6:	ea24 74e4 	bic.w	r4, r4, r4, asr #31
    19ea:	fb06 2404 	mla	r4, r6, r4, r2
    19ee:	3c30      	subs	r4, #48	; 0x30
    19f0:	e745      	b.n	187e <cbvprintf+0x36>
			if (precision >= 0) {
    19f2:	2f00      	cmp	r7, #0
    19f4:	dbf7      	blt.n	19e6 <cbvprintf+0x19e>
				precision = 10 * precision + *fmt - '0';
    19f6:	fb06 2707 	mla	r7, r6, r7, r2
    19fa:	3f30      	subs	r7, #48	; 0x30
    19fc:	e73f      	b.n	187e <cbvprintf+0x36>
			if (precision >= 0) {
    19fe:	2f00      	cmp	r7, #0
    1a00:	f855 3b04 	ldr.w	r3, [r5], #4
    1a04:	db01      	blt.n	1a0a <cbvprintf+0x1c2>
				precision = va_arg(ap, int);
    1a06:	461f      	mov	r7, r3
    1a08:	e739      	b.n	187e <cbvprintf+0x36>
				if (min_width < 0) {
    1a0a:	1e1c      	subs	r4, r3, #0
    1a0c:	f6bf af37 	bge.w	187e <cbvprintf+0x36>
					min_width = -min_width;
    1a10:	4264      	negs	r4, r4
		switch (*fmt) {
    1a12:	2302      	movs	r3, #2
				padding_mode = PAD_ZERO;
    1a14:	9303      	str	r3, [sp, #12]
    1a16:	e732      	b.n	187e <cbvprintf+0x36>
			if (*fmt == 'h' && length_mod == 'h') {
    1a18:	2a68      	cmp	r2, #104	; 0x68
    1a1a:	d103      	bne.n	1a24 <cbvprintf+0x1dc>
    1a1c:	2968      	cmp	r1, #104	; 0x68
    1a1e:	d106      	bne.n	1a2e <cbvprintf+0x1e6>
				length_mod = 'H';
    1a20:	2148      	movs	r1, #72	; 0x48
    1a22:	e72c      	b.n	187e <cbvprintf+0x36>
			} else if (*fmt == 'l' && length_mod == 'l') {
    1a24:	2a6c      	cmp	r2, #108	; 0x6c
    1a26:	d102      	bne.n	1a2e <cbvprintf+0x1e6>
    1a28:	296c      	cmp	r1, #108	; 0x6c
    1a2a:	f000 8127 	beq.w	1c7c <cbvprintf+0x434>
			} else if (length_mod == '\0') {
    1a2e:	2900      	cmp	r1, #0
    1a30:	f47f af30 	bne.w	1894 <cbvprintf+0x4c>
    1a34:	4611      	mov	r1, r2
		switch (*fmt) {
    1a36:	e722      	b.n	187e <cbvprintf+0x36>
			if (length_mod == 'z') {
    1a38:	297a      	cmp	r1, #122	; 0x7a
    1a3a:	d107      	bne.n	1a4c <cbvprintf+0x204>
			} else if (*fmt == 'u') {
    1a3c:	2a75      	cmp	r2, #117	; 0x75
				precision = va_arg(ap, int);
    1a3e:	f105 0604 	add.w	r6, r5, #4
				d = va_arg(ap, unsigned int);
    1a42:	682d      	ldr	r5, [r5, #0]
			} else if (*fmt == 'u') {
    1a44:	d162      	bne.n	1b0c <cbvprintf+0x2c4>
				d = va_arg(ap, unsigned int);
    1a46:	f04f 0800 	mov.w	r8, #0
    1a4a:	e00d      	b.n	1a68 <cbvprintf+0x220>
			} else if (length_mod == 'l') {
    1a4c:	296c      	cmp	r1, #108	; 0x6c
    1a4e:	d0f5      	beq.n	1a3c <cbvprintf+0x1f4>
			} else if (length_mod == 'L') {
    1a50:	294c      	cmp	r1, #76	; 0x4c
    1a52:	d1f3      	bne.n	1a3c <cbvprintf+0x1f4>
					unsigned long long llu =
    1a54:	1deb      	adds	r3, r5, #7
    1a56:	f023 0307 	bic.w	r3, r3, #7
    1a5a:	461e      	mov	r6, r3
				if (*fmt == 'u') {
    1a5c:	2a75      	cmp	r2, #117	; 0x75
					unsigned long long llu =
    1a5e:	e8f6 0102 	ldrd	r0, r1, [r6], #8
				if (*fmt == 'u') {
    1a62:	d107      	bne.n	1a74 <cbvprintf+0x22c>
					unsigned long long llu =
    1a64:	e9d3 5800 	ldrd	r5, r8, [r3]
			} else if (special == ' ') {
    1a68:	f1bc 0f20 	cmp.w	ip, #32
    1a6c:	d151      	bne.n	1b12 <cbvprintf+0x2ca>
				prefix = " ";
    1a6e:	4b86      	ldr	r3, [pc, #536]	; (1c88 <cbvprintf+0x440>)
				min_width--;
    1a70:	3c01      	subs	r4, #1
    1a72:	e009      	b.n	1a88 <cbvprintf+0x240>
					d = (int_value_type) lld;
    1a74:	4605      	mov	r5, r0
    1a76:	4688      	mov	r8, r1
			if (*fmt != 'u' && (int_value_type)d < 0) {
    1a78:	f1b8 0f00 	cmp.w	r8, #0
    1a7c:	daf4      	bge.n	1a68 <cbvprintf+0x220>
				d = -d;
    1a7e:	426d      	negs	r5, r5
				prefix = "-";
    1a80:	4b82      	ldr	r3, [pc, #520]	; (1c8c <cbvprintf+0x444>)
				d = -d;
    1a82:	eb68 0848 	sbc.w	r8, r8, r8, lsl #1
				min_width--;
    1a86:	3c01      	subs	r4, #1
	prefix = "";
    1a88:	9300      	str	r3, [sp, #0]
	int i = 0;
    1a8a:	ab0d      	add	r3, sp, #52	; 0x34
    1a8c:	9305      	str	r3, [sp, #20]
    1a8e:	f04f 0b00 	mov.w	fp, #0
		unsigned int c = num % base;
    1a92:	4628      	mov	r0, r5
    1a94:	4641      	mov	r1, r8
    1a96:	220a      	movs	r2, #10
    1a98:	2300      	movs	r3, #0
    1a9a:	f8cd b010 	str.w	fp, [sp, #16]
    1a9e:	f7fe fb1d 	bl	dc <__aeabi_uldivmod>
		buftop[--i] = c + '0';
    1aa2:	9b05      	ldr	r3, [sp, #20]
    1aa4:	f8cd 801c 	str.w	r8, [sp, #28]
    1aa8:	3230      	adds	r2, #48	; 0x30
    1aaa:	f803 2901 	strb.w	r2, [r3], #-1
		num /= base;
    1aae:	4628      	mov	r0, r5
    1ab0:	e9cd 3505 	strd	r3, r5, [sp, #20]
    1ab4:	4641      	mov	r1, r8
    1ab6:	2300      	movs	r3, #0
    1ab8:	220a      	movs	r2, #10
    1aba:	f7fe fb0f 	bl	dc <__aeabi_uldivmod>
	} while (num);
    1abe:	9b06      	ldr	r3, [sp, #24]
    1ac0:	2b0a      	cmp	r3, #10
    1ac2:	9b07      	ldr	r3, [sp, #28]
    1ac4:	f173 0300 	sbcs.w	r3, r3, #0
		buftop[--i] = c + '0';
    1ac8:	f10b 3bff 	add.w	fp, fp, #4294967295
		num /= base;
    1acc:	4605      	mov	r5, r0
    1ace:	4688      	mov	r8, r1
	} while (num);
    1ad0:	d2df      	bcs.n	1a92 <cbvprintf+0x24a>
	return -i;
    1ad2:	9b04      	ldr	r3, [sp, #16]
			data = buf + sizeof(buf) - data_len;
    1ad4:	9a04      	ldr	r2, [sp, #16]
	return -i;
    1ad6:	f1c3 0b01 	rsb	fp, r3, #1
			data = buf + sizeof(buf) - data_len;
    1ada:	ab0e      	add	r3, sp, #56	; 0x38
    1adc:	189d      	adds	r5, r3, r2
		}

		if (precision < 0 && (padding_mode & PAD_ZERO)) {
    1ade:	2f00      	cmp	r7, #0
			data = buf + sizeof(buf) - data_len;
    1ae0:	f1a5 0504 	sub.w	r5, r5, #4
		if (precision < 0 && (padding_mode & PAD_ZERO)) {
    1ae4:	da04      	bge.n	1af0 <cbvprintf+0x2a8>
    1ae6:	9b03      	ldr	r3, [sp, #12]
    1ae8:	f013 0f01 	tst.w	r3, #1
    1aec:	bf18      	it	ne
    1aee:	4627      	movne	r7, r4
		precision -= data_len;
		if (precision > 0) {
			min_width -= precision;
		}

		if (!(padding_mode & PAD_TAIL)) {
    1af0:	9b03      	ldr	r3, [sp, #12]
		precision -= data_len;
    1af2:	eba7 080b 	sub.w	r8, r7, fp
		if (precision > 0) {
    1af6:	f1b8 0f00 	cmp.w	r8, #0
		min_width -= data_len;
    1afa:	bfd4      	ite	le
    1afc:	eba4 040b 	suble.w	r4, r4, fp
			min_width -= precision;
    1b00:	1be4      	subgt	r4, r4, r7
		if (!(padding_mode & PAD_TAIL)) {
    1b02:	079b      	lsls	r3, r3, #30
    1b04:	f100 8081 	bmi.w	1c0a <cbvprintf+0x3c2>
    1b08:	4627      	mov	r7, r4
    1b0a:	e077      	b.n	1bfc <cbvprintf+0x3b4>
				d = va_arg(ap, int);
    1b0c:	ea4f 78e5 	mov.w	r8, r5, asr #31
    1b10:	e7b2      	b.n	1a78 <cbvprintf+0x230>
			} else if (special == '+') {
    1b12:	f1bc 0f2b 	cmp.w	ip, #43	; 0x2b
				prefix = "+";
    1b16:	bf0a      	itet	eq
    1b18:	4b5d      	ldreq	r3, [pc, #372]	; (1c90 <cbvprintf+0x448>)
	prefix = "";
    1b1a:	4b5e      	ldrne	r3, [pc, #376]	; (1c94 <cbvprintf+0x44c>)
				min_width--;
    1b1c:	f104 34ff 	addeq.w	r4, r4, #4294967295
    1b20:	e7b2      	b.n	1a88 <cbvprintf+0x240>
			if (*fmt == 'p') {
    1b22:	2a70      	cmp	r2, #112	; 0x70
    1b24:	d128      	bne.n	1b78 <cbvprintf+0x330>
				x = (uintptr_t)va_arg(ap, void *);
    1b26:	462e      	mov	r6, r5
    1b28:	2300      	movs	r3, #0
    1b2a:	f856 1b04 	ldr.w	r1, [r6], #4
				if (x == (uint_value_type)0) {
    1b2e:	2900      	cmp	r1, #0
    1b30:	d05c      	beq.n	1bec <cbvprintf+0x3a4>
				prefix = (*fmt & 0x20) ? "0x" : "0X";
    1b32:	4859      	ldr	r0, [pc, #356]	; (1c98 <cbvprintf+0x450>)
    1b34:	9000      	str	r0, [sp, #0]
				min_width -= 2;
    1b36:	3c02      	subs	r4, #2
			data_len = convert_value(x, 16, ALPHA(*fmt),
    1b38:	f002 0260 	and.w	r2, r2, #96	; 0x60
    1b3c:	f1a2 0839 	sub.w	r8, r2, #57	; 0x39
	int i = 0;
    1b40:	f10d 0e34 	add.w	lr, sp, #52	; 0x34
    1b44:	2500      	movs	r5, #0
		unsigned int c = num % base;
    1b46:	f001 020f 	and.w	r2, r1, #15
		if (c >= 10) {
    1b4a:	2a09      	cmp	r2, #9
			c += alpha;
    1b4c:	bf88      	it	hi
    1b4e:	4442      	addhi	r2, r8
		buftop[--i] = c + '0';
    1b50:	3230      	adds	r2, #48	; 0x30
    1b52:	f80e 2901 	strb.w	r2, [lr], #-1
	} while (num);
    1b56:	2910      	cmp	r1, #16
		num /= base;
    1b58:	ea4f 1211 	mov.w	r2, r1, lsr #4
    1b5c:	ea42 7203 	orr.w	r2, r2, r3, lsl #28
    1b60:	ea4f 1013 	mov.w	r0, r3, lsr #4
	} while (num);
    1b64:	f173 0300 	sbcs.w	r3, r3, #0
		buftop[--i] = c + '0';
    1b68:	f105 3cff 	add.w	ip, r5, #4294967295
	} while (num);
    1b6c:	d221      	bcs.n	1bb2 <cbvprintf+0x36a>
			data = buf + sizeof(buf) - data_len;
    1b6e:	ab0e      	add	r3, sp, #56	; 0x38
	return -i;
    1b70:	f1c5 0b01 	rsb	fp, r5, #1
			data = buf + sizeof(buf) - data_len;
    1b74:	441d      	add	r5, r3
    1b76:	e7b2      	b.n	1ade <cbvprintf+0x296>
			} else if (length_mod == 'l') {
    1b78:	296c      	cmp	r1, #108	; 0x6c
    1b7a:	d104      	bne.n	1b86 <cbvprintf+0x33e>
				x = va_arg(ap, unsigned int);
    1b7c:	462e      	mov	r6, r5
    1b7e:	2300      	movs	r3, #0
    1b80:	f856 1b04 	ldr.w	r1, [r6], #4
    1b84:	e008      	b.n	1b98 <cbvprintf+0x350>
			} else if (length_mod == 'L') {
    1b86:	294c      	cmp	r1, #76	; 0x4c
    1b88:	d1f8      	bne.n	1b7c <cbvprintf+0x334>
				unsigned long long llx =
    1b8a:	3507      	adds	r5, #7
    1b8c:	f025 0507 	bic.w	r5, r5, #7
    1b90:	462e      	mov	r6, r5
    1b92:	686b      	ldr	r3, [r5, #4]
    1b94:	f856 1b08 	ldr.w	r1, [r6], #8
			if (special == '#') {
    1b98:	f1bc 0f23 	cmp.w	ip, #35	; 0x23
    1b9c:	d106      	bne.n	1bac <cbvprintf+0x364>
				prefix = (*fmt & 0x20) ? "0x" : "0X";
    1b9e:	4d3f      	ldr	r5, [pc, #252]	; (1c9c <cbvprintf+0x454>)
    1ba0:	483d      	ldr	r0, [pc, #244]	; (1c98 <cbvprintf+0x450>)
    1ba2:	f012 0f20 	tst.w	r2, #32
    1ba6:	bf08      	it	eq
    1ba8:	4628      	moveq	r0, r5
    1baa:	e7c3      	b.n	1b34 <cbvprintf+0x2ec>
	prefix = "";
    1bac:	4839      	ldr	r0, [pc, #228]	; (1c94 <cbvprintf+0x44c>)
    1bae:	9000      	str	r0, [sp, #0]
    1bb0:	e7c2      	b.n	1b38 <cbvprintf+0x2f0>
		buftop[--i] = c + '0';
    1bb2:	4665      	mov	r5, ip
		num /= base;
    1bb4:	4611      	mov	r1, r2
    1bb6:	4603      	mov	r3, r0
    1bb8:	e7c5      	b.n	1b46 <cbvprintf+0x2fe>
			data = va_arg(ap, char *);
    1bba:	462e      	mov	r6, r5
    1bbc:	f856 5b04 	ldr.w	r5, [r6], #4
			data_len = strlen(data);
    1bc0:	4628      	mov	r0, r5
    1bc2:	f004 fc57 	bl	6474 <strlen>
			if (precision >= 0 && data_len > precision) {
    1bc6:	2f00      	cmp	r7, #0
			data_len = strlen(data);
    1bc8:	4683      	mov	fp, r0
			if (precision >= 0 && data_len > precision) {
    1bca:	db02      	blt.n	1bd2 <cbvprintf+0x38a>
    1bcc:	42b8      	cmp	r0, r7
    1bce:	bfa8      	it	ge
    1bd0:	46bb      	movge	fp, r7
    1bd2:	4b30      	ldr	r3, [pc, #192]	; (1c94 <cbvprintf+0x44c>)
    1bd4:	9300      	str	r3, [sp, #0]
    1bd6:	2700      	movs	r7, #0
    1bd8:	e78a      	b.n	1af0 <cbvprintf+0x2a8>
			int c = va_arg(ap, int);
    1bda:	462e      	mov	r6, r5
			data_len = 1;
    1bdc:	f04f 0b01 	mov.w	fp, #1
			buf[0] = c;
    1be0:	f856 3b04 	ldr.w	r3, [r6], #4
    1be4:	f88d 3020 	strb.w	r3, [sp, #32]
			data = buf;
    1be8:	ad08      	add	r5, sp, #32
    1bea:	e7f2      	b.n	1bd2 <cbvprintf+0x38a>
					data = "(nil)";
    1bec:	4d2c      	ldr	r5, [pc, #176]	; (1ca0 <cbvprintf+0x458>)
					data_len = 5;
    1bee:	f04f 0b05 	mov.w	fp, #5
    1bf2:	e7ee      	b.n	1bd2 <cbvprintf+0x38a>
			while (--min_width >= 0) {
				OUTC(' ');
    1bf4:	9b01      	ldr	r3, [sp, #4]
    1bf6:	4651      	mov	r1, sl
    1bf8:	2020      	movs	r0, #32
    1bfa:	4798      	blx	r3
			while (--min_width >= 0) {
    1bfc:	3f01      	subs	r7, #1
    1bfe:	d5f9      	bpl.n	1bf4 <cbvprintf+0x3ac>
    1c00:	ea24 73e4 	bic.w	r3, r4, r4, asr #31
    1c04:	3c01      	subs	r4, #1
    1c06:	4499      	add	r9, r3
    1c08:	1ae4      	subs	r4, r4, r3
    1c0a:	9b00      	ldr	r3, [sp, #0]
    1c0c:	eba9 0903 	sub.w	r9, r9, r3
    1c10:	e004      	b.n	1c1c <cbvprintf+0x3d4>
    1c12:	9300      	str	r3, [sp, #0]
			}
		}
		while (*prefix) {
			OUTC(*prefix++);
    1c14:	4651      	mov	r1, sl
    1c16:	9b01      	ldr	r3, [sp, #4]
    1c18:	4798      	blx	r3
    1c1a:	9b00      	ldr	r3, [sp, #0]
    1c1c:	eb09 0703 	add.w	r7, r9, r3
		while (*prefix) {
    1c20:	f813 0b01 	ldrb.w	r0, [r3], #1
    1c24:	2800      	cmp	r0, #0
    1c26:	d1f4      	bne.n	1c12 <cbvprintf+0x3ca>
		precision -= data_len;
    1c28:	46c1      	mov	r9, r8
		}
		while (--precision >= 0) {
    1c2a:	f1b9 0901 	subs.w	r9, r9, #1
    1c2e:	d513      	bpl.n	1c58 <cbvprintf+0x410>
    1c30:	ea28 78e8 	bic.w	r8, r8, r8, asr #31
    1c34:	46d9      	mov	r9, fp
			OUTC('0');
		}
		while (--data_len >= 0) {
    1c36:	f1b9 0901 	subs.w	r9, r9, #1
    1c3a:	d512      	bpl.n	1c62 <cbvprintf+0x41a>
    1c3c:	f1bb 0f00 	cmp.w	fp, #0
    1c40:	bfa8      	it	ge
    1c42:	44d8      	addge	r8, fp
    1c44:	4625      	mov	r5, r4
			OUTC(*data++);
		}
		while (--min_width >= 0) {
    1c46:	3d01      	subs	r5, #1
    1c48:	d511      	bpl.n	1c6e <cbvprintf+0x426>
    1c4a:	2c00      	cmp	r4, #0
    1c4c:	bfa8      	it	ge
    1c4e:	44a0      	addge	r8, r4
    1c50:	eb08 0907 	add.w	r9, r8, r7
    1c54:	4635      	mov	r5, r6
    1c56:	e601      	b.n	185c <cbvprintf+0x14>
			OUTC('0');
    1c58:	9b01      	ldr	r3, [sp, #4]
    1c5a:	4651      	mov	r1, sl
    1c5c:	2030      	movs	r0, #48	; 0x30
    1c5e:	4798      	blx	r3
    1c60:	e7e3      	b.n	1c2a <cbvprintf+0x3e2>
			OUTC(*data++);
    1c62:	f815 0b01 	ldrb.w	r0, [r5], #1
    1c66:	9b01      	ldr	r3, [sp, #4]
    1c68:	4651      	mov	r1, sl
    1c6a:	4798      	blx	r3
    1c6c:	e7e3      	b.n	1c36 <cbvprintf+0x3ee>
			OUTC(' ');
    1c6e:	9b01      	ldr	r3, [sp, #4]
    1c70:	4651      	mov	r1, sl
    1c72:	2020      	movs	r0, #32
    1c74:	4798      	blx	r3
    1c76:	e7e6      	b.n	1c46 <cbvprintf+0x3fe>
				padding_mode = PAD_ZERO;
    1c78:	2301      	movs	r3, #1
    1c7a:	e6cb      	b.n	1a14 <cbvprintf+0x1cc>
				length_mod = 'L';
    1c7c:	214c      	movs	r1, #76	; 0x4c
    1c7e:	e5fe      	b.n	187e <cbvprintf+0x36>
		}

		goto start;
	}
}
    1c80:	4648      	mov	r0, r9
    1c82:	b00f      	add	sp, #60	; 0x3c
    1c84:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    1c88:	000097fb 	.word	0x000097fb
    1c8c:	0000930c 	.word	0x0000930c
    1c90:	0000930e 	.word	0x0000930e
    1c94:	00009b92 	.word	0x00009b92
    1c98:	00009313 	.word	0x00009313
    1c9c:	00009310 	.word	0x00009310
    1ca0:	00009316 	.word	0x00009316

00001ca4 <sys_reboot>:
#include <sys/printk.h>

extern void sys_arch_reboot(int type);

FUNC_NORETURN void sys_reboot(int type)
{
    1ca4:	b508      	push	{r3, lr}
    1ca6:	f04f 0220 	mov.w	r2, #32
    1caa:	f3ef 8311 	mrs	r3, BASEPRI
    1cae:	f382 8812 	msr	BASEPRI_MAX, r2
    1cb2:	f3bf 8f6f 	isb	sy
	(void)irq_lock();
	sys_clock_disable();

	sys_arch_reboot(type);
    1cb6:	f001 f9a3 	bl	3000 <sys_arch_reboot>

	/* should never get here */
	printk("Failed to reboot: spinning endlessly...\n");
    1cba:	4803      	ldr	r0, [pc, #12]	; (1cc8 <sys_reboot+0x24>)
    1cbc:	f004 f806 	bl	5ccc <printk>
 * @note In some architectures, before returning, the function unmasks interrupts
 * unconditionally.
 */
static inline void k_cpu_idle(void)
{
	arch_cpu_idle();
    1cc0:	f000 fd76 	bl	27b0 <arch_cpu_idle>
    1cc4:	e7fc      	b.n	1cc0 <sys_reboot+0x1c>
    1cc6:	bf00      	nop
    1cc8:	0000931c 	.word	0x0000931c

00001ccc <flash_area_open>:

int flash_area_open(uint8_t id, const struct flash_area **fap)
{
	const struct flash_area *area;

	if (flash_map == NULL) {
    1ccc:	4b0c      	ldr	r3, [pc, #48]	; (1d00 <flash_area_open+0x34>)
    1cce:	681b      	ldr	r3, [r3, #0]
{
    1cd0:	b570      	push	{r4, r5, r6, lr}
	if (flash_map == NULL) {
    1cd2:	b173      	cbz	r3, 1cf2 <flash_area_open+0x26>
extern const struct flash_area *flash_map;
extern const int flash_map_entries;

static inline struct flash_area const *get_flash_area_from_id(int idx)
{
	for (int i = 0; i < flash_map_entries; i++) {
    1cd4:	4a0b      	ldr	r2, [pc, #44]	; (1d04 <flash_area_open+0x38>)
    1cd6:	6815      	ldr	r5, [r2, #0]
    1cd8:	2200      	movs	r2, #0
    1cda:	42aa      	cmp	r2, r5
    1cdc:	db02      	blt.n	1ce4 <flash_area_open+0x18>
		return -EACCES;
	}

	area = get_flash_area_from_id(id);
	if (area == NULL) {
		return -ENOENT;
    1cde:	f06f 0001 	mvn.w	r0, #1
	}

	*fap = area;
	return 0;
}
    1ce2:	bd70      	pop	{r4, r5, r6, pc}
		if (flash_map[i].fa_id == idx) {
    1ce4:	461c      	mov	r4, r3
    1ce6:	f813 6b10 	ldrb.w	r6, [r3], #16
    1cea:	4286      	cmp	r6, r0
    1cec:	d004      	beq.n	1cf8 <flash_area_open+0x2c>
	for (int i = 0; i < flash_map_entries; i++) {
    1cee:	3201      	adds	r2, #1
    1cf0:	e7f3      	b.n	1cda <flash_area_open+0xe>
		return -EACCES;
    1cf2:	f06f 000c 	mvn.w	r0, #12
    1cf6:	e7f4      	b.n	1ce2 <flash_area_open+0x16>
	*fap = area;
    1cf8:	600c      	str	r4, [r1, #0]
	return 0;
    1cfa:	2000      	movs	r0, #0
    1cfc:	e7f1      	b.n	1ce2 <flash_area_open+0x16>
    1cfe:	bf00      	nop
    1d00:	2000000c 	.word	0x2000000c
    1d04:	00008a20 	.word	0x00008a20

00001d08 <flash_area_get_sectors>:

	return true;
}

int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
{
    1d08:	b570      	push	{r4, r5, r6, lr}
    1d0a:	b088      	sub	sp, #32
    1d0c:	4605      	mov	r5, r0
    1d0e:	460c      	mov	r4, r1
	int rc = flash_area_open(idx, &fa);
    1d10:	b2c0      	uxtb	r0, r0
    1d12:	4669      	mov	r1, sp
{
    1d14:	4616      	mov	r6, r2
	int rc = flash_area_open(idx, &fa);
    1d16:	f7ff ffd9 	bl	1ccc <flash_area_open>
	if (rc < 0 || fa == NULL) {
    1d1a:	2800      	cmp	r0, #0
    1d1c:	db1f      	blt.n	1d5e <flash_area_get_sectors+0x56>
    1d1e:	9b00      	ldr	r3, [sp, #0]
    1d20:	b1eb      	cbz	r3, 1d5e <flash_area_get_sectors+0x56>
	cb_data->area_off = fa->fa_off;
    1d22:	685a      	ldr	r2, [r3, #4]
    1d24:	9202      	str	r2, [sp, #8]
	cb_data->area_len = fa->fa_size;
    1d26:	689a      	ldr	r2, [r3, #8]
	cb_data->ret_len = *cnt;
    1d28:	6821      	ldr	r1, [r4, #0]
	flash_dev = device_get_binding(fa->fa_dev_name);
    1d2a:	68d8      	ldr	r0, [r3, #12]
	cb_data->area_idx = idx;
    1d2c:	9501      	str	r5, [sp, #4]
	cb_data->ret = ret;
    1d2e:	e9cd 2603 	strd	r2, r6, [sp, #12]
	cb_data->ret_idx = 0U;
    1d32:	2200      	movs	r2, #0
	cb_data->status = 0;
    1d34:	e9cd 1206 	strd	r1, r2, [sp, #24]
	cb_data->ret_idx = 0U;
    1d38:	9205      	str	r2, [sp, #20]
    1d3a:	f003 fb99 	bl	5470 <z_impl_device_get_binding>
    1d3e:	4605      	mov	r5, r0
	flash_area_close(fa);
    1d40:	9800      	ldr	r0, [sp, #0]
    1d42:	f004 f889 	bl	5e58 <flash_area_close>
	if (flash_dev == NULL) {
    1d46:	b16d      	cbz	r5, 1d64 <flash_area_get_sectors+0x5c>
	flash_page_foreach(flash_dev, cb, cb_data);
    1d48:	4628      	mov	r0, r5
    1d4a:	4908      	ldr	r1, [pc, #32]	; (1d6c <flash_area_get_sectors+0x64>)
    1d4c:	aa01      	add	r2, sp, #4
    1d4e:	f004 fd11 	bl	6774 <flash_page_foreach>
	if (cb_data->status == 0) {
    1d52:	9807      	ldr	r0, [sp, #28]
    1d54:	b908      	cbnz	r0, 1d5a <flash_area_get_sectors+0x52>
		*cnt = cb_data->ret_idx;
    1d56:	9b05      	ldr	r3, [sp, #20]
    1d58:	6023      	str	r3, [r4, #0]
	struct layout_data data;

	return flash_area_layout(idx, cnt, ret, get_sectors_cb, &data);
}
    1d5a:	b008      	add	sp, #32
    1d5c:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    1d5e:	f06f 0015 	mvn.w	r0, #21
    1d62:	e7fa      	b.n	1d5a <flash_area_get_sectors+0x52>
		return -ENODEV;
    1d64:	f06f 0012 	mvn.w	r0, #18
	return flash_area_layout(idx, cnt, ret, get_sectors_cb, &data);
    1d68:	e7f7      	b.n	1d5a <flash_area_get_sectors+0x52>
    1d6a:	bf00      	nop
    1d6c:	00005f1d 	.word	0x00005f1d

00001d70 <boot_uart_fifo_callback>:
	return boot_uart_fifo_init();
}

static void
boot_uart_fifo_callback(const struct device *dev, void *user_data)
{
    1d70:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
	static struct line_input *cmd;
	uint8_t byte;
	int rx;

	uart_irq_update(uart_dev);
    1d72:	4e24      	ldr	r6, [pc, #144]	; (1e04 <boot_uart_fifo_callback+0x94>)
    1d74:	6830      	ldr	r0, [r6, #0]
{
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	if (api->irq_update == NULL) {
    1d76:	6883      	ldr	r3, [r0, #8]
    1d78:	6c5b      	ldr	r3, [r3, #68]	; 0x44
    1d7a:	b103      	cbz	r3, 1d7e <boot_uart_fifo_callback+0xe>
		return -ENOSYS;
	}
	return api->irq_update(dev);
    1d7c:	4798      	blx	r3

	if (!uart_irq_rx_ready(uart_dev)) {
    1d7e:	6830      	ldr	r0, [r6, #0]
	if (api->irq_rx_ready == NULL) {
    1d80:	6883      	ldr	r3, [r0, #8]
    1d82:	6b5b      	ldr	r3, [r3, #52]	; 0x34
    1d84:	b9a3      	cbnz	r3, 1db0 <boot_uart_fifo_callback+0x40>
		rx = uart_fifo_read(uart_dev, &byte, 1);
		if (rx != 1) {
			break;
		}

		if (!cmd) {
    1d86:	4c20      	ldr	r4, [pc, #128]	; (1e08 <boot_uart_fifo_callback+0x98>)
	return list->head;
    1d88:	4d20      	ldr	r5, [pc, #128]	; (1e0c <boot_uart_fifo_callback+0x9c>)
		rx = uart_fifo_read(uart_dev, &byte, 1);
    1d8a:	6830      	ldr	r0, [r6, #0]
	if (api->fifo_read == NULL) {
    1d8c:	6883      	ldr	r3, [r0, #8]
    1d8e:	699b      	ldr	r3, [r3, #24]
    1d90:	b18b      	cbz	r3, 1db6 <boot_uart_fifo_callback+0x46>
	return api->fifo_read(dev, rx_data, size);
    1d92:	2201      	movs	r2, #1
    1d94:	f10d 0107 	add.w	r1, sp, #7
    1d98:	4798      	blx	r3
		if (rx != 1) {
    1d9a:	2801      	cmp	r0, #1
    1d9c:	d10b      	bne.n	1db6 <boot_uart_fifo_callback+0x46>
		if (!cmd) {
    1d9e:	6823      	ldr	r3, [r4, #0]
    1da0:	b993      	cbnz	r3, 1dc8 <boot_uart_fifo_callback+0x58>
    1da2:	682b      	ldr	r3, [r5, #0]
 *
 * @return A pointer to the first node of the list (or NULL if empty)
 */
static inline sys_snode_t *sys_slist_get(sys_slist_t *list);

Z_GENLIST_GET(slist, snode)
    1da4:	b94b      	cbnz	r3, 1dba <boot_uart_fifo_callback+0x4a>
			sys_snode_t *node;

			node = sys_slist_get(&avail_queue);
			if (!node) {
				BOOT_LOG_ERR("Not enough memory to store"
    1da6:	481a      	ldr	r0, [pc, #104]	; (1e10 <boot_uart_fifo_callback+0xa0>)
    1da8:	2145      	movs	r1, #69	; 0x45
    1daa:	f004 f848 	bl	5e3e <z_log_minimal_printk>
					     " incoming data!");
				return;
    1dae:	e002      	b.n	1db6 <boot_uart_fifo_callback+0x46>
	return api->irq_rx_ready(dev);
    1db0:	4798      	blx	r3
	if (!uart_irq_rx_ready(uart_dev)) {
    1db2:	2800      	cmp	r0, #0
    1db4:	d1e7      	bne.n	1d86 <boot_uart_fifo_callback+0x16>
			sys_slist_append(&lines_queue, &cmd->node);
			cur = 0;
			cmd = NULL;
		}
	}
}
    1db6:	b003      	add	sp, #12
    1db8:	bdf0      	pop	{r4, r5, r6, r7, pc}
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    1dba:	6869      	ldr	r1, [r5, #4]
	return node->next;
    1dbc:	681a      	ldr	r2, [r3, #0]
	list->head = node;
    1dbe:	602a      	str	r2, [r5, #0]
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    1dc0:	428b      	cmp	r3, r1
    1dc2:	d100      	bne.n	1dc6 <boot_uart_fifo_callback+0x56>
	list->tail = node;
    1dc4:	606a      	str	r2, [r5, #4]
			cmd = CONTAINER_OF(node, struct line_input, node);
    1dc6:	6023      	str	r3, [r4, #0]
		if (cur < CONFIG_BOOT_MAX_LINE_INPUT_LEN) {
    1dc8:	4a12      	ldr	r2, [pc, #72]	; (1e14 <boot_uart_fifo_callback+0xa4>)
			cmd->line[cur++] = byte;
    1dca:	f89d 0007 	ldrb.w	r0, [sp, #7]
		if (cur < CONFIG_BOOT_MAX_LINE_INPUT_LEN) {
    1dce:	8811      	ldrh	r1, [r2, #0]
    1dd0:	f5b1 7f00 	cmp.w	r1, #512	; 0x200
    1dd4:	d204      	bcs.n	1de0 <boot_uart_fifo_callback+0x70>
			cmd->line[cur++] = byte;
    1dd6:	6823      	ldr	r3, [r4, #0]
    1dd8:	440b      	add	r3, r1
    1dda:	1c4f      	adds	r7, r1, #1
    1ddc:	8017      	strh	r7, [r2, #0]
    1dde:	7218      	strb	r0, [r3, #8]
		if (byte ==  '\n') {
    1de0:	280a      	cmp	r0, #10
    1de2:	d1d2      	bne.n	1d8a <boot_uart_fifo_callback+0x1a>
			cmd->len = cur;
    1de4:	6823      	ldr	r3, [r4, #0]
    1de6:	8811      	ldrh	r1, [r2, #0]
    1de8:	6059      	str	r1, [r3, #4]
	return list->tail;
    1dea:	490b      	ldr	r1, [pc, #44]	; (1e18 <boot_uart_fifo_callback+0xa8>)
    1dec:	684d      	ldr	r5, [r1, #4]
	parent->next = child;
    1dee:	2000      	movs	r0, #0
    1df0:	6018      	str	r0, [r3, #0]
Z_GENLIST_APPEND(slist, snode)
    1df2:	b925      	cbnz	r5, 1dfe <boot_uart_fifo_callback+0x8e>
	list->head = node;
    1df4:	e9c1 3300 	strd	r3, r3, [r1]
			cur = 0;
    1df8:	8010      	strh	r0, [r2, #0]
			cmd = NULL;
    1dfa:	6020      	str	r0, [r4, #0]
    1dfc:	e7c4      	b.n	1d88 <boot_uart_fifo_callback+0x18>
	parent->next = child;
    1dfe:	602b      	str	r3, [r5, #0]
	list->tail = node;
    1e00:	604b      	str	r3, [r1, #4]
}
    1e02:	e7f9      	b.n	1df8 <boot_uart_fifo_callback+0x88>
    1e04:	20001224 	.word	0x20001224
    1e08:	20000e04 	.word	0x20000e04
    1e0c:	20000dfc 	.word	0x20000dfc
    1e10:	00009345 	.word	0x00009345
    1e14:	20001394 	.word	0x20001394
    1e18:	2000121c 	.word	0x2000121c

00001e1c <console_out>:
	uart_poll_out(uart_dev, c);
    1e1c:	4b04      	ldr	r3, [pc, #16]	; (1e30 <console_out+0x14>)
{
    1e1e:	b510      	push	{r4, lr}
    1e20:	4604      	mov	r4, r0
	uart_poll_out(uart_dev, c);
    1e22:	6818      	ldr	r0, [r3, #0]
	api->poll_out(dev, out_char);
    1e24:	6883      	ldr	r3, [r0, #8]
    1e26:	b2e1      	uxtb	r1, r4
    1e28:	685b      	ldr	r3, [r3, #4]
    1e2a:	4798      	blx	r3
}
    1e2c:	4620      	mov	r0, r4
    1e2e:	bd10      	pop	{r4, pc}
    1e30:	20001224 	.word	0x20001224

00001e34 <console_read>:
{
    1e34:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    1e36:	4606      	mov	r6, r0
    1e38:	460f      	mov	r7, r1
    1e3a:	4615      	mov	r5, r2
    1e3c:	f04f 0320 	mov.w	r3, #32
    1e40:	f3ef 8c11 	mrs	ip, BASEPRI
    1e44:	f383 8812 	msr	BASEPRI_MAX, r3
    1e48:	f3bf 8f6f 	isb	sy
	sys_snode_t *node;
	int key;

	key = irq_lock();
	/* Recycle cmd buffer returned previous time */
	if (cmd != NULL) {
    1e4c:	4918      	ldr	r1, [pc, #96]	; (1eb0 <console_read+0x7c>)
    1e4e:	680b      	ldr	r3, [r1, #0]
    1e50:	b143      	cbz	r3, 1e64 <console_read+0x30>
	return list->tail;
    1e52:	4a18      	ldr	r2, [pc, #96]	; (1eb4 <console_read+0x80>)
    1e54:	6850      	ldr	r0, [r2, #4]
		if (sys_slist_peek_tail(&avail_queue) != &cmd->node) {
    1e56:	4298      	cmp	r0, r3
    1e58:	d004      	beq.n	1e64 <console_read+0x30>
	parent->next = child;
    1e5a:	2400      	movs	r4, #0
    1e5c:	601c      	str	r4, [r3, #0]
Z_GENLIST_APPEND(slist, snode)
    1e5e:	b990      	cbnz	r0, 1e86 <console_read+0x52>
	list->head = node;
    1e60:	e9c2 3300 	strd	r3, r3, [r2]
	return list->head;
    1e64:	4b14      	ldr	r3, [pc, #80]	; (1eb8 <console_read+0x84>)
    1e66:	6818      	ldr	r0, [r3, #0]
Z_GENLIST_GET(slist, snode)
    1e68:	b128      	cbz	r0, 1e76 <console_read+0x42>
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    1e6a:	685c      	ldr	r4, [r3, #4]
	return node->next;
    1e6c:	6802      	ldr	r2, [r0, #0]
	list->head = node;
    1e6e:	601a      	str	r2, [r3, #0]
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    1e70:	42a0      	cmp	r0, r4
	list->tail = node;
    1e72:	bf08      	it	eq
    1e74:	605a      	streq	r2, [r3, #4]
	__asm__ volatile(
    1e76:	f38c 8811 	msr	BASEPRI, ip
    1e7a:	f3bf 8f6f 	isb	sy

	node = sys_slist_get(&lines_queue);
	irq_unlock(key);

	if (node == NULL) {
		cmd = NULL;
    1e7e:	6008      	str	r0, [r1, #0]
	if (node == NULL) {
    1e80:	b920      	cbnz	r0, 1e8c <console_read+0x58>
		*newline = 0;
    1e82:	6028      	str	r0, [r5, #0]
}
    1e84:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	parent->next = child;
    1e86:	6003      	str	r3, [r0, #0]
	list->tail = node;
    1e88:	6053      	str	r3, [r2, #4]
}
    1e8a:	e7eb      	b.n	1e64 <console_read+0x30>
		return 0;
	}

	cmd = CONTAINER_OF(node, struct line_input, node);
	*line = cmd->line;
	return cmd->len;
    1e8c:	6844      	ldr	r4, [r0, #4]
	if (len > str_size - 1) {
    1e8e:	42a7      	cmp	r7, r4
		len = str_size - 1;
    1e90:	bfd8      	it	le
    1e92:	f107 34ff 	addle.w	r4, r7, #4294967295
	*line = cmd->line;
    1e96:	f100 0108 	add.w	r1, r0, #8
	memcpy(str, line, len);
    1e9a:	4622      	mov	r2, r4
    1e9c:	4630      	mov	r0, r6
    1e9e:	f004 fb25 	bl	64ec <memcpy>
	str[len] = '\0';
    1ea2:	2300      	movs	r3, #0
    1ea4:	5533      	strb	r3, [r6, r4]
	*newline = 1;
    1ea6:	2301      	movs	r3, #1
    1ea8:	602b      	str	r3, [r5, #0]
	return len + 1;
    1eaa:	18e0      	adds	r0, r4, r3
    1eac:	e7ea      	b.n	1e84 <console_read+0x50>
    1eae:	bf00      	nop
    1eb0:	20000e08 	.word	0x20000e08
    1eb4:	20000dfc 	.word	0x20000dfc
    1eb8:	2000121c 	.word	0x2000121c

00001ebc <boot_console_init>:
	list->head = NULL;
    1ebc:	4b1d      	ldr	r3, [pc, #116]	; (1f34 <boot_console_init+0x78>)
{
    1ebe:	b537      	push	{r0, r1, r2, r4, r5, lr}
    1ec0:	2500      	movs	r5, #0
	list->tail = NULL;
    1ec2:	e9c3 5500 	strd	r5, r5, [r3]
	list->head = node;
    1ec6:	4b1c      	ldr	r3, [pc, #112]	; (1f38 <boot_console_init+0x7c>)
    1ec8:	4a1c      	ldr	r2, [pc, #112]	; (1f3c <boot_console_init+0x80>)

static int
boot_uart_fifo_init(void)
{
#ifdef CONFIG_BOOT_SERIAL_UART
	uart_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console));
    1eca:	4c1d      	ldr	r4, [pc, #116]	; (1f40 <boot_console_init+0x84>)
    1ecc:	481d      	ldr	r0, [pc, #116]	; (1f44 <boot_console_init+0x88>)
    1ece:	6013      	str	r3, [r2, #0]
	parent->next = child;
    1ed0:	f503 7102 	add.w	r1, r3, #520	; 0x208
    1ed4:	f8c3 5208 	str.w	r5, [r3, #520]	; 0x208
    1ed8:	6019      	str	r1, [r3, #0]
	list->tail = node;
    1eda:	6051      	str	r1, [r2, #4]
    1edc:	6020      	str	r0, [r4, #0]
 */
__syscall bool device_is_ready(const struct device *dev);

static inline bool z_impl_device_is_ready(const struct device *dev)
{
	return z_device_is_ready(dev);
    1ede:	f006 fbfd 	bl	86dc <z_device_is_ready>
#elif CONFIG_BOOT_SERIAL_CDC_ACM
	uart_dev = DEVICE_DT_GET_ONE(zephyr_cdc_acm_uart);
#endif

	if (!device_is_ready(uart_dev)) {
    1ee2:	b310      	cbz	r0, 1f2a <boot_console_init+0x6e>
	if (rc) {
		return (-1);
	}
#endif

	uart_irq_callback_set(uart_dev, boot_uart_fifo_callback);
    1ee4:	6820      	ldr	r0, [r4, #0]
static inline void uart_irq_callback_user_data_set(const struct device *dev,
						   uart_irq_callback_user_data_t cb,
						   void *user_data)
{
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
	const struct uart_driver_api *api =
    1ee6:	6883      	ldr	r3, [r0, #8]
		(const struct uart_driver_api *)dev->api;

	if ((api != NULL) && (api->irq_callback_set != NULL)) {
    1ee8:	b123      	cbz	r3, 1ef4 <boot_console_init+0x38>
    1eea:	6c9b      	ldr	r3, [r3, #72]	; 0x48
    1eec:	b113      	cbz	r3, 1ef4 <boot_console_init+0x38>
		api->irq_callback_set(dev, cb, user_data);
    1eee:	4916      	ldr	r1, [pc, #88]	; (1f48 <boot_console_init+0x8c>)
    1ef0:	462a      	mov	r2, r5
    1ef2:	4798      	blx	r3

	/* Drain the fifo */
	if (uart_irq_rx_ready(uart_dev)) {
    1ef4:	6820      	ldr	r0, [r4, #0]
	if (api->irq_rx_ready == NULL) {
    1ef6:	6883      	ldr	r3, [r0, #8]
    1ef8:	6b5b      	ldr	r3, [r3, #52]	; 0x34
    1efa:	b10b      	cbz	r3, 1f00 <boot_console_init+0x44>
	return api->irq_rx_ready(dev);
    1efc:	4798      	blx	r3
    1efe:	b148      	cbz	r0, 1f14 <boot_console_init+0x58>
		uint8_t c;

		while (uart_fifo_read(uart_dev, &c, 1)) {
    1f00:	6820      	ldr	r0, [r4, #0]
	if (api->fifo_read == NULL) {
    1f02:	6883      	ldr	r3, [r0, #8]
    1f04:	699b      	ldr	r3, [r3, #24]
    1f06:	b903      	cbnz	r3, 1f0a <boot_console_init+0x4e>
    1f08:	e7fe      	b.n	1f08 <boot_console_init+0x4c>
	return api->fifo_read(dev, rx_data, size);
    1f0a:	2201      	movs	r2, #1
    1f0c:	f10d 0107 	add.w	r1, sp, #7
    1f10:	4798      	blx	r3
    1f12:	e7f4      	b.n	1efe <boot_console_init+0x42>
			;
		}
	}

	cur = 0;
    1f14:	4b0d      	ldr	r3, [pc, #52]	; (1f4c <boot_console_init+0x90>)

	uart_irq_rx_enable(uart_dev);
    1f16:	6820      	ldr	r0, [r4, #0]
	cur = 0;
    1f18:	2500      	movs	r5, #0
    1f1a:	801d      	strh	r5, [r3, #0]
	if (api->irq_rx_enable != NULL) {
    1f1c:	6883      	ldr	r3, [r0, #8]
    1f1e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    1f20:	b133      	cbz	r3, 1f30 <boot_console_init+0x74>
		api->irq_rx_enable(dev);
    1f22:	4798      	blx	r3

	return 0;
    1f24:	4628      	mov	r0, r5
}
    1f26:	b003      	add	sp, #12
    1f28:	bd30      	pop	{r4, r5, pc}
		return (-1);
    1f2a:	f04f 30ff 	mov.w	r0, #4294967295
    1f2e:	e7fa      	b.n	1f26 <boot_console_init+0x6a>
	return 0;
    1f30:	4618      	mov	r0, r3
	return boot_uart_fifo_init();
    1f32:	e7f8      	b.n	1f26 <boot_console_init+0x6a>
    1f34:	2000121c 	.word	0x2000121c
    1f38:	20000e0c 	.word	0x20000e0c
    1f3c:	20000dfc 	.word	0x20000dfc
    1f40:	20001224 	.word	0x20001224
    1f44:	00008794 	.word	0x00008794
    1f48:	00001d71 	.word	0x00001d71
    1f4c:	20001394 	.word	0x20001394

00001f50 <boot_serial_output>:
#endif
}

static void
boot_serial_output(void)
{
    1f50:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    char encoded_buf[BASE64_ENCODE_SIZE(sizeof(buf))];

    data = bs_obuf;
    len = (uint32_t)cbor_state.payload_mut - (uint32_t)bs_obuf;

    bs_hdr->nh_op++;
    1f54:	f8df 90f0 	ldr.w	r9, [pc, #240]	; 2048 <boot_serial_output+0xf8>
    len = (uint32_t)cbor_state.payload_mut - (uint32_t)bs_obuf;
    1f58:	f8df 80f0 	ldr.w	r8, [pc, #240]	; 204c <boot_serial_output+0xfc>
    bs_hdr->nh_op++;
    1f5c:	f8d9 1000 	ldr.w	r1, [r9]
    crc = crc16_ccitt(CRC16_INITIAL_CRC, bs_hdr, sizeof(*bs_hdr));
    crc = crc16_ccitt(crc, data, len);
#endif
    crc = htons(crc);

    boot_uf->write(pkt_start, sizeof(pkt_start));
    1f60:	4e3b      	ldr	r6, [pc, #236]	; (2050 <boot_serial_output+0x100>)
{
    1f62:	b0d9      	sub	sp, #356	; 0x164
    char pkt_start[2] = { SHELL_NLIP_PKT_START1, SHELL_NLIP_PKT_START2 };
    1f64:	f640 1306 	movw	r3, #2310	; 0x906
    1f68:	f8ad 3008 	strh.w	r3, [sp, #8]
    len = (uint32_t)cbor_state.payload_mut - (uint32_t)bs_obuf;
    1f6c:	4b39      	ldr	r3, [pc, #228]	; (2054 <boot_serial_output+0x104>)
    1f6e:	681f      	ldr	r7, [r3, #0]
    bs_hdr->nh_op++;
    1f70:	780b      	ldrb	r3, [r1, #0]
    len = (uint32_t)cbor_state.payload_mut - (uint32_t)bs_obuf;
    1f72:	eba7 0708 	sub.w	r7, r7, r8
    bs_hdr->nh_op++;
    1f76:	3301      	adds	r3, #1
    1f78:	700b      	strb	r3, [r1, #0]
    bs_hdr->nh_len = htons(len);
    1f7a:	ba7b      	rev16	r3, r7
    1f7c:	804b      	strh	r3, [r1, #2]
    bs_hdr->nh_group = htons(bs_hdr->nh_group);
    1f7e:	888b      	ldrh	r3, [r1, #4]
    bs_hdr->nh_flags = 0;
    1f80:	2000      	movs	r0, #0
    bs_hdr->nh_group = htons(bs_hdr->nh_group);
    1f82:	ba5b      	rev16	r3, r3
    1f84:	808b      	strh	r3, [r1, #4]
    bs_hdr->nh_flags = 0;
    1f86:	7048      	strb	r0, [r1, #1]
    crc =  crc16_itu_t(CRC16_INITIAL_CRC, (uint8_t *)bs_hdr, sizeof(*bs_hdr));
    1f88:	2208      	movs	r2, #8
    1f8a:	f003 fe6b 	bl	5c64 <crc16_itu_t>
    crc =  crc16_itu_t(crc, data, len);
    1f8e:	463a      	mov	r2, r7
    1f90:	4641      	mov	r1, r8
    crc =  crc16_itu_t(CRC16_INITIAL_CRC, (uint8_t *)bs_hdr, sizeof(*bs_hdr));
    1f92:	f8ad 000c 	strh.w	r0, [sp, #12]
    crc =  crc16_itu_t(crc, data, len);
    1f96:	f003 fe65 	bl	5c64 <crc16_itu_t>
    boot_uf->write(pkt_start, sizeof(pkt_start));
    1f9a:	6833      	ldr	r3, [r6, #0]
    crc = htons(crc);
    1f9c:	ba40      	rev16	r0, r0
    1f9e:	b2bc      	uxth	r4, r7
    1fa0:	f8ad 000c 	strh.w	r0, [sp, #12]
    boot_uf->write(pkt_start, sizeof(pkt_start));
    1fa4:	685b      	ldr	r3, [r3, #4]
    1fa6:	a802      	add	r0, sp, #8
    1fa8:	2102      	movs	r1, #2
    1faa:	4798      	blx	r3

    totlen = len + sizeof(*bs_hdr) + sizeof(crc);
    1fac:	f104 030a 	add.w	r3, r4, #10
    totlen = htons(totlen);
    1fb0:	ba5b      	rev16	r3, r3

    memcpy(buf, &totlen, sizeof(totlen));
    1fb2:	f10d 010e 	add.w	r1, sp, #14
    1fb6:	2202      	movs	r2, #2
    1fb8:	a805      	add	r0, sp, #20
    totlen = sizeof(totlen);
    1fba:	2502      	movs	r5, #2
    totlen = htons(totlen);
    1fbc:	f8ad 300e 	strh.w	r3, [sp, #14]
    memcpy(buf, &totlen, sizeof(totlen));
    1fc0:	f004 fa94 	bl	64ec <memcpy>
    memcpy(&buf[totlen], bs_hdr, sizeof(*bs_hdr));
    1fc4:	f8d9 1000 	ldr.w	r1, [r9]
    totlen = sizeof(totlen);
    1fc8:	f8ad 500e 	strh.w	r5, [sp, #14]
    memcpy(&buf[totlen], bs_hdr, sizeof(*bs_hdr));
    1fcc:	2208      	movs	r2, #8
    1fce:	f10d 0016 	add.w	r0, sp, #22
    1fd2:	f004 fa8b 	bl	64ec <memcpy>
    totlen += sizeof(*bs_hdr);
    1fd6:	f8bd 000e 	ldrh.w	r0, [sp, #14]
    1fda:	3008      	adds	r0, #8
    memcpy(&buf[totlen], data, len);
    1fdc:	ab05      	add	r3, sp, #20
    totlen += sizeof(*bs_hdr);
    1fde:	b280      	uxth	r0, r0
    1fe0:	f8ad 000e 	strh.w	r0, [sp, #14]
    memcpy(&buf[totlen], data, len);
    1fe4:	463a      	mov	r2, r7
    1fe6:	4641      	mov	r1, r8
    1fe8:	4418      	add	r0, r3
    1fea:	f004 fa7f 	bl	64ec <memcpy>
    totlen += len;
    1fee:	f8bd 000e 	ldrh.w	r0, [sp, #14]
    1ff2:	4420      	add	r0, r4
    memcpy(&buf[totlen], &crc, sizeof(crc));
    1ff4:	ab05      	add	r3, sp, #20
    totlen += len;
    1ff6:	b280      	uxth	r0, r0
    1ff8:	f8ad 000e 	strh.w	r0, [sp, #14]
    memcpy(&buf[totlen], &crc, sizeof(crc));
    1ffc:	462a      	mov	r2, r5
    1ffe:	a903      	add	r1, sp, #12
    2000:	4418      	add	r0, r3
    2002:	f004 fa73 	bl	64ec <memcpy>
    totlen += sizeof(crc);
    2006:	f8bd 300e 	ldrh.w	r3, [sp, #14]
    200a:	442b      	add	r3, r5
    200c:	b29b      	uxth	r3, r3
#ifdef __ZEPHYR__
    size_t enc_len;
    base64_encode(encoded_buf, sizeof(encoded_buf), &enc_len, buf, totlen);
    200e:	aa04      	add	r2, sp, #16
    totlen += sizeof(crc);
    2010:	f8ad 300e 	strh.w	r3, [sp, #14]
    base64_encode(encoded_buf, sizeof(encoded_buf), &enc_len, buf, totlen);
    2014:	9300      	str	r3, [sp, #0]
    2016:	21bd      	movs	r1, #189	; 0xbd
    2018:	ab05      	add	r3, sp, #20
    201a:	a828      	add	r0, sp, #160	; 0xa0
    201c:	f7ff f9fc 	bl	1418 <base64_encode>
    totlen = enc_len;
    2020:	9904      	ldr	r1, [sp, #16]
#else
    totlen = base64_encode(buf, totlen, encoded_buf, 1);
#endif
    boot_uf->write(encoded_buf, totlen);
    2022:	6833      	ldr	r3, [r6, #0]
    totlen = enc_len;
    2024:	f8ad 100e 	strh.w	r1, [sp, #14]
    boot_uf->write(encoded_buf, totlen);
    2028:	a828      	add	r0, sp, #160	; 0xa0
    202a:	685b      	ldr	r3, [r3, #4]
    202c:	b289      	uxth	r1, r1
    202e:	4798      	blx	r3
    boot_uf->write("\n\r", 2);
    2030:	6833      	ldr	r3, [r6, #0]
    2032:	4809      	ldr	r0, [pc, #36]	; (2058 <boot_serial_output+0x108>)
    2034:	685b      	ldr	r3, [r3, #4]
    2036:	4629      	mov	r1, r5
    2038:	4798      	blx	r3
    BOOT_LOG_INF("TX");
    203a:	4808      	ldr	r0, [pc, #32]	; (205c <boot_serial_output+0x10c>)
    203c:	2149      	movs	r1, #73	; 0x49
    203e:	f003 fefe 	bl	5e3e <z_log_minimal_printk>
}
    2042:	b059      	add	sp, #356	; 0x164
    2044:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    2048:	2000122c 	.word	0x2000122c
    204c:	20002c97 	.word	0x20002c97
    2050:	20001228 	.word	0x20001228
    2054:	20000010 	.word	0x20000010
    2058:	0000939e 	.word	0x0000939e
    205c:	000093a1 	.word	0x000093a1

00002060 <bs_rc_rsp>:
{
    2060:	b537      	push	{r0, r1, r2, r4, r5, lr}
    map_start_encode(&cbor_state, 10);
    2062:	4c0e      	ldr	r4, [pc, #56]	; (209c <bs_rc_rsp+0x3c>)
{
    2064:	4605      	mov	r5, r0
    map_start_encode(&cbor_state, 10);
    2066:	210a      	movs	r1, #10
    2068:	4620      	mov	r0, r4
    206a:	f004 f955 	bl	6318 <map_start_encode>
    tstrx_put(&cbor_state, "rc");
    206e:	4a0c      	ldr	r2, [pc, #48]	; (20a0 <bs_rc_rsp+0x40>)
    2070:	e892 0003 	ldmia.w	r2, {r0, r1}
    2074:	466b      	mov	r3, sp
    2076:	e883 0003 	stmia.w	r3, {r0, r1}
    207a:	4619      	mov	r1, r3
    207c:	4620      	mov	r0, r4
    207e:	f004 f93c 	bl	62fa <tstrx_encode>
    uintx32_put(&cbor_state, rc_code);
    2082:	4629      	mov	r1, r5
    2084:	4620      	mov	r0, r4
    2086:	f004 f92f 	bl	62e8 <uintx32_put>
    map_end_encode(&cbor_state, 10);
    208a:	210a      	movs	r1, #10
    208c:	4620      	mov	r0, r4
    208e:	f004 f95e 	bl	634e <map_end_encode>
    boot_serial_output();
    2092:	f7ff ff5d 	bl	1f50 <boot_serial_output>
}
    2096:	b003      	add	sp, #12
    2098:	bd30      	pop	{r4, r5, pc}
    209a:	bf00      	nop
    209c:	20000010 	.word	0x20000010
    20a0:	00008960 	.word	0x00008960

000020a4 <boot_serial_in_dec.constprop.0>:

/*
 * Returns 1 if full packet has been received.
 */
static int
boot_serial_in_dec(char *in, int inlen, char *out, int *out_off, int maxout)
    20a4:	b5f0      	push	{r4, r5, r6, r7, lr}
    uint16_t crc;
    uint16_t len;

#ifdef __ZEPHYR__
    int err;
    err = base64_decode( &out[*out_off], maxout - *out_off, &rc, in, inlen - 2);
    20a6:	680c      	ldr	r4, [r1, #0]
    20a8:	4f16      	ldr	r7, [pc, #88]	; (2104 <boot_serial_in_dec.constprop.0+0x60>)
    20aa:	4b17      	ldr	r3, [pc, #92]	; (2108 <boot_serial_in_dec.constprop.0+0x64>)
boot_serial_in_dec(char *in, int inlen, char *out, int *out_off, int maxout)
    20ac:	b085      	sub	sp, #20
    err = base64_decode( &out[*out_off], maxout - *out_off, &rc, in, inlen - 2);
    20ae:	3802      	subs	r0, #2
boot_serial_in_dec(char *in, int inlen, char *out, int *out_off, int maxout)
    20b0:	460d      	mov	r5, r1
    err = base64_decode( &out[*out_off], maxout - *out_off, &rc, in, inlen - 2);
    20b2:	f5c4 7100 	rsb	r1, r4, #512	; 0x200
    20b6:	9000      	str	r0, [sp, #0]
    20b8:	aa03      	add	r2, sp, #12
    20ba:	1938      	adds	r0, r7, r4
    20bc:	3101      	adds	r1, #1
    20be:	f7ff fa2d 	bl	151c <base64_decode>
    if (err) {
    20c2:	4604      	mov	r4, r0
    20c4:	b9d8      	cbnz	r0, 20fe <boot_serial_in_dec.constprop.0+0x5a>
    if (rc < 0) {
        return -1;
    }
#endif

    *out_off += rc;
    20c6:	682b      	ldr	r3, [r5, #0]
    20c8:	9a03      	ldr	r2, [sp, #12]
    20ca:	4413      	add	r3, r2
    if (*out_off <= sizeof(uint16_t)) {
    20cc:	2b02      	cmp	r3, #2
    *out_off += rc;
    20ce:	602b      	str	r3, [r5, #0]
    if (*out_off <= sizeof(uint16_t)) {
    20d0:	d912      	bls.n	20f8 <boot_serial_in_dec.constprop.0+0x54>
        return 0;
    }

    len = ntohs(*(uint16_t *)out);
    20d2:	883e      	ldrh	r6, [r7, #0]
    20d4:	ba76      	rev16	r6, r6
    20d6:	b2b6      	uxth	r6, r6
    if (len != *out_off - sizeof(uint16_t)) {
    20d8:	3b02      	subs	r3, #2
    20da:	429e      	cmp	r6, r3
    20dc:	d10c      	bne.n	20f8 <boot_serial_in_dec.constprop.0+0x54>
        len = *out_off - sizeof(uint16_t);
    }

    out += sizeof(uint16_t);
#ifdef __ZEPHYR__
    crc = crc16_itu_t(CRC16_INITIAL_CRC, out, len);
    20de:	4632      	mov	r2, r6
    20e0:	1cb9      	adds	r1, r7, #2
    20e2:	f003 fdbf 	bl	5c64 <crc16_itu_t>
#else
    crc = crc16_ccitt(CRC16_INITIAL_CRC, out, len);
#endif
    if (crc || len <= sizeof(crc)) {
    20e6:	b938      	cbnz	r0, 20f8 <boot_serial_in_dec.constprop.0+0x54>
    20e8:	2e02      	cmp	r6, #2
    20ea:	d905      	bls.n	20f8 <boot_serial_in_dec.constprop.0+0x54>
        return 0;
    }
    *out_off -= sizeof(crc);
    20ec:	682b      	ldr	r3, [r5, #0]
    20ee:	3b02      	subs	r3, #2
    out[*out_off] = '\0';
    20f0:	441f      	add	r7, r3
    *out_off -= sizeof(crc);
    20f2:	602b      	str	r3, [r5, #0]
    out[*out_off] = '\0';
    20f4:	70bc      	strb	r4, [r7, #2]

    return 1;
    20f6:	2401      	movs	r4, #1
}
    20f8:	4620      	mov	r0, r4
    20fa:	b005      	add	sp, #20
    20fc:	bdf0      	pop	{r4, r5, r6, r7, pc}
        return -1;
    20fe:	f04f 34ff 	mov.w	r4, #4294967295
    2102:	e7f9      	b.n	20f8 <boot_serial_in_dec.constprop.0+0x54>
    2104:	20002d17 	.word	0x20002d17
    2108:	20002f1a 	.word	0x20002f1a

0000210c <reset_cbor_state>:
    cbor_state.payload_mut = (uint8_t *)bs_obuf;
    210c:	4a03      	ldr	r2, [pc, #12]	; (211c <reset_cbor_state+0x10>)
    210e:	4b04      	ldr	r3, [pc, #16]	; (2120 <reset_cbor_state+0x14>)
    2110:	6013      	str	r3, [r2, #0]
    cbor_state.payload_end = (const uint8_t *)bs_obuf
    2112:	3380      	adds	r3, #128	; 0x80
    2114:	60d3      	str	r3, [r2, #12]
    cbor_state.elem_count = 0;
    2116:	2300      	movs	r3, #0
    2118:	6093      	str	r3, [r2, #8]
}
    211a:	4770      	bx	lr
    211c:	20000010 	.word	0x20000010
    2120:	20002c97 	.word	0x20002c97

00002124 <boot_serial_input>:
{
    2124:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    if (len < sizeof(*hdr) ||
    2128:	2907      	cmp	r1, #7
{
    212a:	b0a8      	sub	sp, #160	; 0xa0
    212c:	4604      	mov	r4, r0
    if (len < sizeof(*hdr) ||
    212e:	f240 80b6 	bls.w	229e <boot_serial_input+0x17a>
    2132:	7802      	ldrb	r2, [r0, #0]
    2134:	f012 05fd 	ands.w	r5, r2, #253	; 0xfd
    2138:	f040 80b1 	bne.w	229e <boot_serial_input+0x17a>
      (ntohs(hdr->nh_len) < len - sizeof(*hdr))) {
    213c:	8843      	ldrh	r3, [r0, #2]
    213e:	ba5b      	rev16	r3, r3
    2140:	f1a1 0608 	sub.w	r6, r1, #8
    2144:	b29b      	uxth	r3, r3
      (hdr->nh_op != NMGR_OP_READ && hdr->nh_op != NMGR_OP_WRITE) ||
    2146:	42b3      	cmp	r3, r6
    2148:	f0c0 80a9 	bcc.w	229e <boot_serial_input+0x17a>
    bs_hdr = hdr;
    214c:	4ba1      	ldr	r3, [pc, #644]	; (23d4 <FIH_LABEL_FIH_CALL_END_971+0x110>)
    214e:	6018      	str	r0, [r3, #0]
    hdr->nh_group = ntohs(hdr->nh_group);
    2150:	8883      	ldrh	r3, [r0, #4]
    2152:	ba5b      	rev16	r3, r3
    2154:	8083      	strh	r3, [r0, #4]
    reset_cbor_state();
    2156:	f7ff ffd9 	bl	210c <reset_cbor_state>
    if (hdr->nh_group == MGMT_GROUP_ID_IMAGE) {
    215a:	8880      	ldrh	r0, [r0, #4]
    215c:	2801      	cmp	r0, #1
    215e:	f040 81ef 	bne.w	2540 <FIH_LABEL_FIH_CALL_END_971+0x27c>
        switch (hdr->nh_id) {
    2162:	79e7      	ldrb	r7, [r4, #7]
    2164:	b147      	cbz	r7, 2178 <boot_serial_input+0x54>
    2166:	2f01      	cmp	r7, #1
    2168:	f000 80ad 	beq.w	22c6 <FIH_LABEL_FIH_CALL_END_971+0x2>
        bs_rc_rsp(MGMT_ERR_ENOTSUP);
    216c:	2008      	movs	r0, #8
}
    216e:	b028      	add	sp, #160	; 0xa0
    2170:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
        bs_rc_rsp(MGMT_ERR_ENOTSUP);
    2174:	f7ff bf74 	b.w	2060 <bs_rc_rsp>
    tstrx_put(&cbor_state, "images");
    2178:	4e97      	ldr	r6, [pc, #604]	; (23d8 <FIH_LABEL_FIH_CALL_END_971+0x114>)
            if (hdr.ih_magic == IMAGE_MAGIC)
    217a:	f8df 8260 	ldr.w	r8, [pc, #608]	; 23dc <FIH_LABEL_FIH_CALL_END_971+0x118>
    map_start_encode(&cbor_state, 1);
    217e:	4601      	mov	r1, r0
    2180:	4897      	ldr	r0, [pc, #604]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    2182:	f004 f8c9 	bl	6318 <map_start_encode>
    tstrx_put(&cbor_state, "images");
    2186:	e896 0003 	ldmia.w	r6, {r0, r1}
    218a:	ab08      	add	r3, sp, #32
    218c:	e883 0003 	stmia.w	r3, {r0, r1}
    2190:	4619      	mov	r1, r3
    2192:	4893      	ldr	r0, [pc, #588]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    2194:	f004 f8b1 	bl	62fa <tstrx_encode>
    list_start_encode(&cbor_state, 5);
    2198:	4891      	ldr	r0, [pc, #580]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    219a:	2105      	movs	r1, #5
    219c:	f004 f8b0 	bl	6300 <list_start_encode>
        for (slot = 0; slot < 2; slot++) {
    21a0:	463c      	mov	r4, r7
            tstrx_put(&cbor_state, "slot");
    21a2:	f106 0708 	add.w	r7, r6, #8
            tstrx_put(&cbor_state, "version");
    21a6:	3610      	adds	r6, #16
            area_id = flash_area_id_from_multi_image_slot(image_index, slot);
    21a8:	4621      	mov	r1, r4
    21aa:	2000      	movs	r0, #0
    21ac:	f003 fae6 	bl	577c <flash_area_id_from_multi_image_slot>
            if (flash_area_open(area_id, &fap)) {
    21b0:	a907      	add	r1, sp, #28
    21b2:	b2c0      	uxtb	r0, r0
    21b4:	f7ff fd8a 	bl	1ccc <flash_area_open>
    21b8:	4605      	mov	r5, r0
    21ba:	2800      	cmp	r0, #0
    21bc:	d164      	bne.n	2288 <boot_serial_input+0x164>
                flash_area_read(fap, 0, &hdr, sizeof(hdr));
    21be:	2320      	movs	r3, #32
    21c0:	4601      	mov	r1, r0
    21c2:	aa10      	add	r2, sp, #64	; 0x40
    21c4:	9807      	ldr	r0, [sp, #28]
    21c6:	f003 fe48 	bl	5e5a <flash_area_read>
            if (hdr.ih_magic == IMAGE_MAGIC)
    21ca:	9b10      	ldr	r3, [sp, #64]	; 0x40
    21cc:	4543      	cmp	r3, r8
    21ce:	d06b      	beq.n	22a8 <FIH_LABEL_FIH_CALL_START_941>
            fih_int fih_rc = FIH_FAILURE;
    21d0:	4b84      	ldr	r3, [pc, #528]	; (23e4 <FIH_LABEL_FIH_CALL_END_971+0x120>)
    21d2:	681d      	ldr	r5, [r3, #0]
            flash_area_close(fap);
    21d4:	9807      	ldr	r0, [sp, #28]
    21d6:	f003 fe3f 	bl	5e58 <flash_area_close>
            if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
    21da:	4b83      	ldr	r3, [pc, #524]	; (23e8 <FIH_LABEL_FIH_CALL_END_971+0x124>)
    21dc:	681b      	ldr	r3, [r3, #0]
    21de:	42ab      	cmp	r3, r5
    21e0:	d152      	bne.n	2288 <boot_serial_input+0x164>
            map_start_encode(&cbor_state, 20);
    21e2:	2114      	movs	r1, #20
    21e4:	487e      	ldr	r0, [pc, #504]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    21e6:	f004 f897 	bl	6318 <map_start_encode>
            tstrx_put(&cbor_state, "slot");
    21ea:	e897 0003 	ldmia.w	r7, {r0, r1}
    21ee:	ab0a      	add	r3, sp, #40	; 0x28
    21f0:	e883 0003 	stmia.w	r3, {r0, r1}
    21f4:	4619      	mov	r1, r3
    21f6:	487a      	ldr	r0, [pc, #488]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    21f8:	f004 f87f 	bl	62fa <tstrx_encode>
            uintx32_put(&cbor_state, slot);
    21fc:	4621      	mov	r1, r4
    21fe:	4878      	ldr	r0, [pc, #480]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    2200:	f004 f872 	bl	62e8 <uintx32_put>
            tstrx_put(&cbor_state, "version");
    2204:	e896 0003 	ldmia.w	r6, {r0, r1}
    2208:	ab0c      	add	r3, sp, #48	; 0x30
    off = u32toa(dst, ver->iv_major);
    220a:	f10d 0960 	add.w	r9, sp, #96	; 0x60
            tstrx_put(&cbor_state, "version");
    220e:	e883 0003 	stmia.w	r3, {r0, r1}
    2212:	4619      	mov	r1, r3
    2214:	4872      	ldr	r0, [pc, #456]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    2216:	f004 f870 	bl	62fa <tstrx_encode>
    off = u32toa(dst, ver->iv_major);
    221a:	f89d 1054 	ldrb.w	r1, [sp, #84]	; 0x54
    221e:	4648      	mov	r0, r9
    2220:	f003 fea8 	bl	5f74 <u32toa>
    dst[off++] = '.';
    2224:	ab28      	add	r3, sp, #160	; 0xa0
    2226:	1c45      	adds	r5, r0, #1
    2228:	4418      	add	r0, r3
    222a:	f04f 0a2e 	mov.w	sl, #46	; 0x2e
    off += u32toa(dst + off, ver->iv_minor);
    222e:	f89d 1055 	ldrb.w	r1, [sp, #85]	; 0x55
    dst[off++] = '.';
    2232:	f800 ac40 	strb.w	sl, [r0, #-64]
    off += u32toa(dst + off, ver->iv_minor);
    2236:	eb09 0005 	add.w	r0, r9, r5
    223a:	f003 fe9b 	bl	5f74 <u32toa>
    dst[off++] = '.';
    223e:	ab28      	add	r3, sp, #160	; 0xa0
    off += u32toa(dst + off, ver->iv_minor);
    2240:	4428      	add	r0, r5
    dst[off++] = '.';
    2242:	1c45      	adds	r5, r0, #1
    2244:	4418      	add	r0, r3
    off += u32toa(dst + off, ver->iv_revision);
    2246:	f8bd 1056 	ldrh.w	r1, [sp, #86]	; 0x56
    dst[off++] = '.';
    224a:	f800 ac40 	strb.w	sl, [r0, #-64]
    off += u32toa(dst + off, ver->iv_revision);
    224e:	eb09 0005 	add.w	r0, r9, r5
    2252:	f003 fe8f 	bl	5f74 <u32toa>
    dst[off++] = '.';
    2256:	ab28      	add	r3, sp, #160	; 0xa0
    off += u32toa(dst + off, ver->iv_revision);
    2258:	4405      	add	r5, r0
    dst[off++] = '.';
    225a:	442b      	add	r3, r5
    225c:	3501      	adds	r5, #1
    off += u32toa(dst + off, ver->iv_build_num);
    225e:	9916      	ldr	r1, [sp, #88]	; 0x58
    dst[off++] = '.';
    2260:	f803 ac40 	strb.w	sl, [r3, #-64]
    off += u32toa(dst + off, ver->iv_build_num);
    2264:	eb09 0005 	add.w	r0, r9, r5
    2268:	f003 fe84 	bl	5f74 <u32toa>
            tstrx_put_term(&cbor_state, (char *)tmpbuf);
    226c:	4648      	mov	r0, r9
    226e:	f8cd 9038 	str.w	r9, [sp, #56]	; 0x38
    2272:	f004 f8ff 	bl	6474 <strlen>
    2276:	a90e      	add	r1, sp, #56	; 0x38
    2278:	900f      	str	r0, [sp, #60]	; 0x3c
    227a:	4859      	ldr	r0, [pc, #356]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    227c:	f004 f83d 	bl	62fa <tstrx_encode>
            map_end_encode(&cbor_state, 20);
    2280:	4857      	ldr	r0, [pc, #348]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    2282:	2114      	movs	r1, #20
    2284:	f004 f863 	bl	634e <map_end_encode>
        for (slot = 0; slot < 2; slot++) {
    2288:	b164      	cbz	r4, 22a4 <boot_serial_input+0x180>
    list_end_encode(&cbor_state, 5);
    228a:	2105      	movs	r1, #5
    228c:	4854      	ldr	r0, [pc, #336]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    228e:	f004 f85b 	bl	6348 <list_end_encode>
    map_end_encode(&cbor_state, 1);
    2292:	4621      	mov	r1, r4
    2294:	4852      	ldr	r0, [pc, #328]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    2296:	f004 f85a 	bl	634e <map_end_encode>
    boot_serial_output();
    229a:	f7ff fe59 	bl	1f50 <boot_serial_output>
}
    229e:	b028      	add	sp, #160	; 0xa0
    22a0:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    22a4:	2401      	movs	r4, #1
    22a6:	e77f      	b.n	21a8 <boot_serial_input+0x84>

000022a8 <FIH_LABEL_FIH_CALL_START_941>:
                    FIH_CALL(bootutil_img_validate, fih_rc, NULL, 0, &hdr, fap, tmpbuf, sizeof(tmpbuf),
    22a8:	2340      	movs	r3, #64	; 0x40
    22aa:	9301      	str	r3, [sp, #4]
    22ac:	ab18      	add	r3, sp, #96	; 0x60
    22ae:	e9cd 5503 	strd	r5, r5, [sp, #12]
    22b2:	9502      	str	r5, [sp, #8]
    22b4:	9300      	str	r3, [sp, #0]
    22b6:	4629      	mov	r1, r5
    22b8:	9b07      	ldr	r3, [sp, #28]
    22ba:	aa10      	add	r2, sp, #64	; 0x40
    22bc:	4628      	mov	r0, r5
    22be:	f7fe f971 	bl	5a4 <bootutil_img_validate>
    22c2:	4605      	mov	r5, r0

000022c4 <FIH_LABEL_FIH_CALL_END_971>:
    22c4:	e786      	b.n	21d4 <boot_serial_input+0xb0>
    bool result = cbor_decode_Upload((const uint8_t *)buf, len, &upload, &decoded_len);
    22c6:	ab0a      	add	r3, sp, #40	; 0x28
    22c8:	aa18      	add	r2, sp, #96	; 0x60
    22ca:	4631      	mov	r1, r6
    22cc:	f104 0008 	add.w	r0, r4, #8
    const struct flash_area *fap = NULL;
    22d0:	9508      	str	r5, [sp, #32]
    bool result = cbor_decode_Upload((const uint8_t *)buf, len, &upload, &decoded_len);
    22d2:	f000 fa59 	bl	2788 <cbor_decode_Upload>
    if (!result || (len != decoded_len)) {
    22d6:	b908      	cbnz	r0, 22dc <FIH_LABEL_FIH_CALL_END_971+0x18>
        rc = MGMT_ERR_EINVAL;
    22d8:	2403      	movs	r4, #3
    22da:	e034      	b.n	2346 <FIH_LABEL_FIH_CALL_END_971+0x82>
    if (!result || (len != decoded_len)) {
    22dc:	9b0a      	ldr	r3, [sp, #40]	; 0x28
    22de:	429e      	cmp	r6, r3
    22e0:	d1fa      	bne.n	22d8 <FIH_LABEL_FIH_CALL_END_971+0x14>
    long long int data_len = UINT64_MAX;
    22e2:	f04f 34ff 	mov.w	r4, #4294967295
    22e6:	9f27      	ldr	r7, [sp, #156]	; 0x9c
    22e8:	ab18      	add	r3, sp, #96	; 0x60
    for (int i = 0; i < upload._Upload_members_count; i++) {
    22ea:	462a      	mov	r2, r5
    img_num = 0;
    22ec:	4628      	mov	r0, r5
    long long int data_len = UINT64_MAX;
    22ee:	46a2      	mov	sl, r4
    long long int off = UINT64_MAX;
    22f0:	4626      	mov	r6, r4
    22f2:	46a1      	mov	r9, r4
    const uint8_t *img_data = NULL;
    22f4:	46a8      	mov	r8, r5
    for (int i = 0; i < upload._Upload_members_count; i++) {
    22f6:	4297      	cmp	r7, r2
    22f8:	d155      	bne.n	23a6 <FIH_LABEL_FIH_CALL_END_971+0xe2>
    if (off == UINT64_MAX || img_data == NULL) {
    22fa:	f1b9 3fff 	cmp.w	r9, #4294967295
    22fe:	bf08      	it	eq
    2300:	f1b6 3fff 	cmpeq.w	r6, #4294967295
    2304:	d0e8      	beq.n	22d8 <FIH_LABEL_FIH_CALL_END_971+0x14>
    2306:	f1b8 0f00 	cmp.w	r8, #0
    230a:	d0e5      	beq.n	22d8 <FIH_LABEL_FIH_CALL_END_971+0x14>
    rc = flash_area_open(flash_area_id_from_multi_image_slot(img_num, 0), &fap);
    230c:	2100      	movs	r1, #0
    230e:	f003 fa35 	bl	577c <flash_area_id_from_multi_image_slot>
    2312:	a908      	add	r1, sp, #32
    2314:	b2c0      	uxtb	r0, r0
    2316:	f7ff fcd9 	bl	1ccc <flash_area_open>
    if (rc) {
    231a:	2800      	cmp	r0, #0
    231c:	d1dc      	bne.n	22d8 <FIH_LABEL_FIH_CALL_END_971+0x14>
    if (off == 0) {
    231e:	ea56 0309 	orrs.w	r3, r6, r9
    2322:	4f32      	ldr	r7, [pc, #200]	; (23ec <FIH_LABEL_FIH_CALL_END_971+0x128>)
    2324:	d108      	bne.n	2338 <FIH_LABEL_FIH_CALL_END_971+0x74>
	return (uint32_t)fa->fa_size;
    2326:	9b08      	ldr	r3, [sp, #32]
        curr_off = 0;
    2328:	6038      	str	r0, [r7, #0]
        if (data_len > flash_area_get_size(fap)) {
    232a:	689b      	ldr	r3, [r3, #8]
    232c:	42a3      	cmp	r3, r4
    232e:	eb70 030a 	sbcs.w	r3, r0, sl
    2332:	dbd1      	blt.n	22d8 <FIH_LABEL_FIH_CALL_END_971+0x14>
        img_size = data_len;
    2334:	4b2e      	ldr	r3, [pc, #184]	; (23f0 <FIH_LABEL_FIH_CALL_END_971+0x12c>)
    2336:	601c      	str	r4, [r3, #0]
    if (off != curr_off) {
    2338:	683b      	ldr	r3, [r7, #0]
    233a:	2400      	movs	r4, #0
    233c:	454c      	cmp	r4, r9
    233e:	bf08      	it	eq
    2340:	42b3      	cmpeq	r3, r6
    2342:	d05b      	beq.n	23fc <FIH_LABEL_FIH_CALL_END_971+0x138>
        rc = 0;
    2344:	2400      	movs	r4, #0
    BOOT_LOG_INF("RX: 0x%x", rc);
    2346:	4622      	mov	r2, r4
    2348:	482a      	ldr	r0, [pc, #168]	; (23f4 <FIH_LABEL_FIH_CALL_END_971+0x130>)
    tstrx_put(&cbor_state, "rc");
    234a:	4d2b      	ldr	r5, [pc, #172]	; (23f8 <FIH_LABEL_FIH_CALL_END_971+0x134>)
    BOOT_LOG_INF("RX: 0x%x", rc);
    234c:	2149      	movs	r1, #73	; 0x49
    234e:	f003 fd76 	bl	5e3e <z_log_minimal_printk>
    map_start_encode(&cbor_state, 10);
    2352:	210a      	movs	r1, #10
    2354:	4822      	ldr	r0, [pc, #136]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    2356:	f003 ffdf 	bl	6318 <map_start_encode>
    tstrx_put(&cbor_state, "rc");
    235a:	e895 0003 	ldmia.w	r5, {r0, r1}
    235e:	ab10      	add	r3, sp, #64	; 0x40
    2360:	e883 0003 	stmia.w	r3, {r0, r1}
    2364:	4619      	mov	r1, r3
    2366:	481e      	ldr	r0, [pc, #120]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    2368:	f003 ffc7 	bl	62fa <tstrx_encode>
    uintx32_put(&cbor_state, rc);
    236c:	481c      	ldr	r0, [pc, #112]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    236e:	4621      	mov	r1, r4
    2370:	f003 ffba 	bl	62e8 <uintx32_put>
    if (rc == 0) {
    2374:	b96c      	cbnz	r4, 2392 <FIH_LABEL_FIH_CALL_END_971+0xce>
        tstrx_put(&cbor_state, "off");
    2376:	e9d5 0108 	ldrd	r0, r1, [r5, #32]
    237a:	ab0e      	add	r3, sp, #56	; 0x38
    237c:	e883 0003 	stmia.w	r3, {r0, r1}
    2380:	4619      	mov	r1, r3
    2382:	4817      	ldr	r0, [pc, #92]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    2384:	f003 ffb9 	bl	62fa <tstrx_encode>
        uintx32_put(&cbor_state, curr_off);
    2388:	4b18      	ldr	r3, [pc, #96]	; (23ec <FIH_LABEL_FIH_CALL_END_971+0x128>)
    238a:	4815      	ldr	r0, [pc, #84]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    238c:	6819      	ldr	r1, [r3, #0]
    238e:	f003 ffab 	bl	62e8 <uintx32_put>
    map_end_encode(&cbor_state, 10);
    2392:	210a      	movs	r1, #10
    2394:	4812      	ldr	r0, [pc, #72]	; (23e0 <FIH_LABEL_FIH_CALL_END_971+0x11c>)
    2396:	f003 ffda 	bl	634e <map_end_encode>
    boot_serial_output();
    239a:	f7ff fdd9 	bl	1f50 <boot_serial_output>
    flash_area_close(fap);
    239e:	9808      	ldr	r0, [sp, #32]
    23a0:	f003 fd5a 	bl	5e58 <flash_area_close>
}
    23a4:	e77b      	b.n	229e <boot_serial_input+0x17a>
        switch(member->_Member_choice) {
    23a6:	7a19      	ldrb	r1, [r3, #8]
    23a8:	2903      	cmp	r1, #3
    23aa:	d804      	bhi.n	23b6 <FIH_LABEL_FIH_CALL_END_971+0xf2>
    23ac:	e8df f001 	tbb	[pc, r1]
    23b0:	0d090602 	.word	0x0d090602
                img_num = member->_Member_image;
    23b4:	6818      	ldr	r0, [r3, #0]
    for (int i = 0; i < upload._Upload_members_count; i++) {
    23b6:	3201      	adds	r2, #1
    23b8:	330c      	adds	r3, #12
    23ba:	e79c      	b.n	22f6 <FIH_LABEL_FIH_CALL_END_971+0x32>
                slen = member->_Member_data.len;
    23bc:	e9d3 8500 	ldrd	r8, r5, [r3]
                break;
    23c0:	e7f9      	b.n	23b6 <FIH_LABEL_FIH_CALL_END_971+0xf2>
                data_len = member->_Member_len;
    23c2:	681c      	ldr	r4, [r3, #0]
    23c4:	ea4f 7ae4 	mov.w	sl, r4, asr #31
                break;
    23c8:	e7f5      	b.n	23b6 <FIH_LABEL_FIH_CALL_END_971+0xf2>
                off = member->_Member_off;
    23ca:	681e      	ldr	r6, [r3, #0]
    23cc:	ea4f 79e6 	mov.w	r9, r6, asr #31
                break;
    23d0:	e7f1      	b.n	23b6 <FIH_LABEL_FIH_CALL_END_971+0xf2>
    23d2:	bf00      	nop
    23d4:	2000122c 	.word	0x2000122c
    23d8:	00008968 	.word	0x00008968
    23dc:	96f3b83d 	.word	0x96f3b83d
    23e0:	20000010 	.word	0x20000010
    23e4:	20000000 	.word	0x20000000
    23e8:	20000194 	.word	0x20000194
    23ec:	20001230 	.word	0x20001230
    23f0:	20001240 	.word	0x20001240
    23f4:	00009474 	.word	0x00009474
    23f8:	00008960 	.word	0x00008960
    if (curr_off + img_blen > img_size) {
    23fc:	f8df a16c 	ldr.w	sl, [pc, #364]	; 256c <FIH_LABEL_FIH_CALL_END_971+0x2a8>
    2400:	f8da 2000 	ldr.w	r2, [sl]
    2404:	442b      	add	r3, r5
    2406:	4293      	cmp	r3, r2
    2408:	f63f af66 	bhi.w	22d8 <FIH_LABEL_FIH_CALL_END_971+0x14>
    rem_bytes = img_blen % flash_area_align(fap);
    240c:	9808      	ldr	r0, [sp, #32]
    240e:	f003 fd73 	bl	5ef8 <flash_area_align>
    2412:	fbb5 f6f0 	udiv	r6, r5, r0
    2416:	fb06 5010 	mls	r0, r6, r0, r5
    241a:	b2c6      	uxtb	r6, r0
    if ((curr_off + img_blen < img_size) && rem_bytes) {
    241c:	6838      	ldr	r0, [r7, #0]
    241e:	f8da 3000 	ldr.w	r3, [sl]
    2422:	1942      	adds	r2, r0, r5
    2424:	429a      	cmp	r2, r3
    2426:	d202      	bcs.n	242e <FIH_LABEL_FIH_CALL_END_971+0x16a>
    2428:	b10e      	cbz	r6, 242e <FIH_LABEL_FIH_CALL_END_971+0x16a>
        img_blen -= rem_bytes;
    242a:	1bad      	subs	r5, r5, r6
        rem_bytes = 0;
    242c:	4626      	mov	r6, r4
    rc = flash_area_sector_from_off(curr_off + img_blen, &sector);
    242e:	a90c      	add	r1, sp, #48	; 0x30
    2430:	4428      	add	r0, r5
    2432:	f7fe f89d 	bl	570 <flash_area_sector_from_off>
    if (rc) {
    2436:	4604      	mov	r4, r0
    2438:	b120      	cbz	r0, 2444 <FIH_LABEL_FIH_CALL_END_971+0x180>
        BOOT_LOG_ERR("Unable to determine flash sector size");
    243a:	484d      	ldr	r0, [pc, #308]	; (2570 <FIH_LABEL_FIH_CALL_END_971+0x2ac>)
    243c:	2145      	movs	r1, #69	; 0x45
                BOOT_LOG_ERR("Unable to determine flash sector of"
    243e:	f003 fcfe 	bl	5e3e <z_log_minimal_printk>
                goto out;
    2442:	e780      	b.n	2346 <FIH_LABEL_FIH_CALL_END_971+0x82>
    if (off_last != flash_sector_get_off(&sector)) {
    2444:	f8df 912c 	ldr.w	r9, [pc, #300]	; 2574 <FIH_LABEL_FIH_CALL_END_971+0x2b0>
	return fs->fs_off;
    2448:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    244a:	f8d9 3000 	ldr.w	r3, [r9]
    244e:	429a      	cmp	r2, r3
    2450:	d012      	beq.n	2478 <FIH_LABEL_FIH_CALL_END_971+0x1b4>
        BOOT_LOG_INF("Erasing sector at offset 0x%x", flash_sector_get_off(&sector));
    2452:	4849      	ldr	r0, [pc, #292]	; (2578 <FIH_LABEL_FIH_CALL_END_971+0x2b4>)
        off_last = flash_sector_get_off(&sector);
    2454:	f8c9 2000 	str.w	r2, [r9]
        BOOT_LOG_INF("Erasing sector at offset 0x%x", flash_sector_get_off(&sector));
    2458:	2149      	movs	r1, #73	; 0x49
    245a:	f003 fcf0 	bl	5e3e <z_log_minimal_printk>
        rc = flash_area_erase(fap, flash_sector_get_off(&sector),
    245e:	e9dd 120c 	ldrd	r1, r2, [sp, #48]	; 0x30
    2462:	9808      	ldr	r0, [sp, #32]
    2464:	f003 fd31 	bl	5eca <flash_area_erase>
        if (rc) {
    2468:	4604      	mov	r4, r0
    246a:	b128      	cbz	r0, 2478 <FIH_LABEL_FIH_CALL_END_971+0x1b4>
                    BOOT_LOG_ERR("Error %d while erasing sector", rc);
    246c:	4843      	ldr	r0, [pc, #268]	; (257c <FIH_LABEL_FIH_CALL_END_971+0x2b8>)
    246e:	4622      	mov	r2, r4
    2470:	2145      	movs	r1, #69	; 0x45
    2472:	f003 fce4 	bl	5e3e <z_log_minimal_printk>
                    goto out;
    2476:	e766      	b.n	2346 <FIH_LABEL_FIH_CALL_END_971+0x82>
    BOOT_LOG_INF("Writing at 0x%x until 0x%x", curr_off, curr_off + img_blen);
    2478:	683a      	ldr	r2, [r7, #0]
    247a:	4841      	ldr	r0, [pc, #260]	; (2580 <FIH_LABEL_FIH_CALL_END_971+0x2bc>)
    247c:	18ab      	adds	r3, r5, r2
    247e:	2149      	movs	r1, #73	; 0x49
    2480:	f003 fcdd 	bl	5e3e <z_log_minimal_printk>
    if (rem_bytes) {
    2484:	2e00      	cmp	r6, #0
    2486:	d042      	beq.n	250e <FIH_LABEL_FIH_CALL_END_971+0x24a>
        if (w_size) {
    2488:	1bac      	subs	r4, r5, r6
    248a:	d02b      	beq.n	24e4 <FIH_LABEL_FIH_CALL_END_971+0x220>
            rc = flash_area_write(fap, curr_off, img_data, w_size);
    248c:	6839      	ldr	r1, [r7, #0]
    248e:	9808      	ldr	r0, [sp, #32]
    2490:	4623      	mov	r3, r4
    2492:	4642      	mov	r2, r8
    2494:	f003 fcfd 	bl	5e92 <flash_area_write>
            if (rc) {
    2498:	2800      	cmp	r0, #0
    249a:	f47f af1d 	bne.w	22d8 <FIH_LABEL_FIH_CALL_END_971+0x14>
            curr_off += w_size;
    249e:	683b      	ldr	r3, [r7, #0]
    24a0:	4423      	add	r3, r4
    24a2:	603b      	str	r3, [r7, #0]
            img_data += w_size;
    24a4:	44a0      	add	r8, r4
            img_blen -= w_size;
    24a6:	4635      	mov	r5, r6
            memcpy(wbs_aligned, img_data, rem_bytes);
    24a8:	4632      	mov	r2, r6
    24aa:	4641      	mov	r1, r8
    24ac:	a810      	add	r0, sp, #64	; 0x40
    24ae:	f004 f81d 	bl	64ec <memcpy>
            memset(wbs_aligned + rem_bytes, flash_area_erased_val(fap),
    24b2:	9808      	ldr	r0, [sp, #32]
    24b4:	f003 fd29 	bl	5f0a <flash_area_erased_val>
    24b8:	ab10      	add	r3, sp, #64	; 0x40
    24ba:	4601      	mov	r1, r0
    24bc:	f1c6 0208 	rsb	r2, r6, #8
    24c0:	1998      	adds	r0, r3, r6
    24c2:	f004 f81e 	bl	6502 <memset>
            rc = flash_area_write(fap, curr_off, wbs_aligned, flash_area_align(fap));
    24c6:	9c08      	ldr	r4, [sp, #32]
    24c8:	683e      	ldr	r6, [r7, #0]
    24ca:	4620      	mov	r0, r4
    24cc:	f003 fd14 	bl	5ef8 <flash_area_align>
    24d0:	aa10      	add	r2, sp, #64	; 0x40
    24d2:	4603      	mov	r3, r0
    24d4:	4631      	mov	r1, r6
    24d6:	4620      	mov	r0, r4
        rc = flash_area_write(fap, curr_off, img_data, img_blen);
    24d8:	f003 fcdb 	bl	5e92 <flash_area_write>
    if (rc == 0) {
    24dc:	2800      	cmp	r0, #0
    24de:	f47f aefb 	bne.w	22d8 <FIH_LABEL_FIH_CALL_END_971+0x14>
    24e2:	e001      	b.n	24e8 <FIH_LABEL_FIH_CALL_END_971+0x224>
        if (img_blen) {
    24e4:	2d00      	cmp	r5, #0
    24e6:	d1df      	bne.n	24a8 <FIH_LABEL_FIH_CALL_END_971+0x1e4>
        curr_off += img_blen;
    24e8:	683b      	ldr	r3, [r7, #0]
    24ea:	441d      	add	r5, r3
        if (curr_off == img_size) {
    24ec:	f8da 3000 	ldr.w	r3, [sl]
        curr_off += img_blen;
    24f0:	603d      	str	r5, [r7, #0]
        if (curr_off == img_size) {
    24f2:	429d      	cmp	r5, r3
    24f4:	f47f af26 	bne.w	2344 <FIH_LABEL_FIH_CALL_END_971+0x80>
            rc = flash_area_sector_from_off(boot_status_off(fap), &sector);
    24f8:	9808      	ldr	r0, [sp, #32]
    24fa:	f003 f9f5 	bl	58e8 <boot_status_off>
    24fe:	a90c      	add	r1, sp, #48	; 0x30
    2500:	f7fe f836 	bl	570 <flash_area_sector_from_off>
            if (rc) {
    2504:	4604      	mov	r4, r0
    2506:	b138      	cbz	r0, 2518 <FIH_LABEL_FIH_CALL_END_971+0x254>
                BOOT_LOG_ERR("Unable to determine flash sector of"
    2508:	481e      	ldr	r0, [pc, #120]	; (2584 <FIH_LABEL_FIH_CALL_END_971+0x2c0>)
    250a:	2145      	movs	r1, #69	; 0x45
    250c:	e797      	b.n	243e <FIH_LABEL_FIH_CALL_END_971+0x17a>
        rc = flash_area_write(fap, curr_off, img_data, img_blen);
    250e:	6839      	ldr	r1, [r7, #0]
    2510:	9808      	ldr	r0, [sp, #32]
    2512:	462b      	mov	r3, r5
    2514:	4642      	mov	r2, r8
    2516:	e7df      	b.n	24d8 <FIH_LABEL_FIH_CALL_END_971+0x214>
    2518:	9a0c      	ldr	r2, [sp, #48]	; 0x30
            if (off_last < flash_sector_get_off(&sector)) {
    251a:	f8d9 3000 	ldr.w	r3, [r9]
    251e:	429a      	cmp	r2, r3
    2520:	f67f af10 	bls.w	2344 <FIH_LABEL_FIH_CALL_END_971+0x80>
                BOOT_LOG_INF("Erasing sector at offset 0x%x",
    2524:	4814      	ldr	r0, [pc, #80]	; (2578 <FIH_LABEL_FIH_CALL_END_971+0x2b4>)
    2526:	2149      	movs	r1, #73	; 0x49
    2528:	f003 fc89 	bl	5e3e <z_log_minimal_printk>
                rc = flash_area_erase(fap, flash_sector_get_off(&sector),
    252c:	e9dd 120c 	ldrd	r1, r2, [sp, #48]	; 0x30
    2530:	9808      	ldr	r0, [sp, #32]
    2532:	f003 fcca 	bl	5eca <flash_area_erase>
                if (rc) {
    2536:	4604      	mov	r4, r0
    2538:	2800      	cmp	r0, #0
    253a:	f43f af04 	beq.w	2346 <FIH_LABEL_FIH_CALL_END_971+0x82>
    253e:	e795      	b.n	246c <FIH_LABEL_FIH_CALL_END_971+0x1a8>
    } else if (hdr->nh_group == MGMT_GROUP_ID_DEFAULT) {
    2540:	2800      	cmp	r0, #0
    2542:	f47f ae13 	bne.w	216c <boot_serial_input+0x48>
        switch (hdr->nh_id) {
    2546:	79e3      	ldrb	r3, [r4, #7]
    2548:	2b01      	cmp	r3, #1
    254a:	f43f ae10 	beq.w	216e <boot_serial_input+0x4a>
    254e:	2b05      	cmp	r3, #5
    2550:	d003      	beq.n	255a <FIH_LABEL_FIH_CALL_END_971+0x296>
    2552:	2b00      	cmp	r3, #0
    2554:	f47f ae0a 	bne.w	216c <boot_serial_input+0x48>
    2558:	e6a1      	b.n	229e <boot_serial_input+0x17a>
    bs_rc_rsp(0);
    255a:	f7ff fd81 	bl	2060 <bs_rc_rsp>
		(void) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_BUSY_WAIT);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_busy_wait(usec_to_wait);
    255e:	480a      	ldr	r0, [pc, #40]	; (2588 <FIH_LABEL_FIH_CALL_END_971+0x2c4>)
    2560:	f006 f8d0 	bl	8704 <z_impl_k_busy_wait>
    sys_reboot(SYS_REBOOT_COLD);
    2564:	2001      	movs	r0, #1
    2566:	f7ff fb9d 	bl	1ca4 <sys_reboot>
    256a:	bf00      	nop
    256c:	20001240 	.word	0x20001240
    2570:	000093a9 	.word	0x000093a9
    2574:	20000024 	.word	0x20000024
    2578:	000093d4 	.word	0x000093d4
    257c:	000093f7 	.word	0x000093f7
    2580:	0000941a 	.word	0x0000941a
    2584:	0000943a 	.word	0x0000943a
    2588:	0003d090 	.word	0x0003d090

0000258c <boot_serial_start>:
 * Task which waits reading console, expecting to get image over
 * serial port.
 */
void
boot_serial_start(const struct boot_uart_funcs *f)
{
    258c:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    bs_entry = true;
    2590:	f8df 80a0 	ldr.w	r8, [pc, #160]	; 2634 <boot_serial_start+0xa8>
    2594:	4d28      	ldr	r5, [pc, #160]	; (2638 <boot_serial_start+0xac>)
        rc = f->read(in_buf + off, sizeof(in_buf) - off, &full_line);
    2596:	4f29      	ldr	r7, [pc, #164]	; (263c <boot_serial_start+0xb0>)
    bs_entry = true;
    2598:	2301      	movs	r3, #1
    259a:	f888 3000 	strb.w	r3, [r8]
    boot_uf = f;
    259e:	4b28      	ldr	r3, [pc, #160]	; (2640 <boot_serial_start+0xb4>)
    int dec_off = 0;
    25a0:	2400      	movs	r4, #0
{
    25a2:	4606      	mov	r6, r0
    int dec_off = 0;
    25a4:	9400      	str	r4, [sp, #0]
    boot_uf = f;
    25a6:	6018      	str	r0, [r3, #0]
    25a8:	f000 f902 	bl	27b0 <arch_cpu_idle>
    25ac:	4b25      	ldr	r3, [pc, #148]	; (2644 <boot_serial_start+0xb8>)
        rc = f->read(in_buf + off, sizeof(in_buf) - off, &full_line);
    25ae:	f5c4 7100 	rsb	r1, r4, #512	; 0x200
    25b2:	f8c3 5600 	str.w	r5, [r3, #1536]	; 0x600
    25b6:	aa01      	add	r2, sp, #4
    25b8:	f8c3 5604 	str.w	r5, [r3, #1540]	; 0x604
    25bc:	3101      	adds	r1, #1
    25be:	f8c3 5608 	str.w	r5, [r3, #1544]	; 0x608
    25c2:	1938      	adds	r0, r7, r4
    25c4:	f8c3 560c 	str.w	r5, [r3, #1548]	; 0x60c
    25c8:	f8c3 5610 	str.w	r5, [r3, #1552]	; 0x610
    25cc:	f8c3 5614 	str.w	r5, [r3, #1556]	; 0x614
    25d0:	f8c3 5618 	str.w	r5, [r3, #1560]	; 0x618
    25d4:	f8c3 561c 	str.w	r5, [r3, #1564]	; 0x61c
    25d8:	6833      	ldr	r3, [r6, #0]
    25da:	4798      	blx	r3
        if (rc <= 0 && !full_line) {
    25dc:	2800      	cmp	r0, #0
    25de:	9b01      	ldr	r3, [sp, #4]
    25e0:	dc00      	bgt.n	25e4 <boot_serial_start+0x58>
    25e2:	b133      	cbz	r3, 25f2 <boot_serial_start+0x66>
        off += rc;
    25e4:	4404      	add	r4, r0
        if (!full_line) {
    25e6:	b95b      	cbnz	r3, 2600 <boot_serial_start+0x74>
            if (off == max_input) {
    25e8:	f240 2301 	movw	r3, #513	; 0x201
    25ec:	429c      	cmp	r4, r3
    25ee:	d100      	bne.n	25f2 <boot_serial_start+0x66>
        off = 0;
    25f0:	2400      	movs	r4, #0
    while (timeout_in_ms > 0 || bs_entry) {
    25f2:	f898 3000 	ldrb.w	r3, [r8]
    25f6:	2b00      	cmp	r3, #0
    25f8:	d1d6      	bne.n	25a8 <boot_serial_start+0x1c>
    boot_serial_read_console(f,0);
}
    25fa:	b002      	add	sp, #8
    25fc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        if (in_buf[0] == SHELL_NLIP_PKT_START1 &&
    2600:	783b      	ldrb	r3, [r7, #0]
    2602:	2b06      	cmp	r3, #6
    2604:	d109      	bne.n	261a <boot_serial_start+0x8e>
    2606:	787b      	ldrb	r3, [r7, #1]
    2608:	2b09      	cmp	r3, #9
    260a:	d10b      	bne.n	2624 <boot_serial_start+0x98>
            dec_off = 0;
    260c:	2300      	movs	r3, #0
    260e:	9300      	str	r3, [sp, #0]
            rc = boot_serial_in_dec(&in_buf[2], off - 2, dec_buf, &dec_off, max_input);
    2610:	4669      	mov	r1, sp
    2612:	1ea0      	subs	r0, r4, #2
    2614:	f7ff fd46 	bl	20a4 <boot_serial_in_dec.constprop.0>
    2618:	e004      	b.n	2624 <boot_serial_start+0x98>
        } else if (in_buf[0] == SHELL_NLIP_DATA_START1 &&
    261a:	2b04      	cmp	r3, #4
    261c:	d102      	bne.n	2624 <boot_serial_start+0x98>
    261e:	787b      	ldrb	r3, [r7, #1]
    2620:	2b14      	cmp	r3, #20
    2622:	d0f5      	beq.n	2610 <boot_serial_start+0x84>
        if (rc == 1) {
    2624:	2801      	cmp	r0, #1
    2626:	d1e3      	bne.n	25f0 <boot_serial_start+0x64>
            boot_serial_input(&dec_buf[2], dec_off - 2);
    2628:	9900      	ldr	r1, [sp, #0]
    262a:	4807      	ldr	r0, [pc, #28]	; (2648 <boot_serial_start+0xbc>)
    262c:	3902      	subs	r1, #2
    262e:	f7ff fd79 	bl	2124 <boot_serial_input>
    2632:	e7dd      	b.n	25f0 <boot_serial_start+0x64>
    2634:	20002c96 	.word	0x20002c96
    2638:	6e524635 	.word	0x6e524635
    263c:	20002f18 	.word	0x20002f18
    2640:	20001228 	.word	0x20001228
    2644:	40010000 	.word	0x40010000
    2648:	20002d19 	.word	0x20002d19

0000264c <decode_Upload>:
	return tmp_result;
}

static bool decode_Upload(
		cbor_state_t *state, struct Upload *result)
{
    264c:	b530      	push	{r4, r5, lr}
    264e:	b085      	sub	sp, #20
    2650:	4605      	mov	r5, r0
    2652:	460c      	mov	r4, r1
	cbor_print("%s\n", __func__);
	bool int_res;

	bool tmp_result = (((map_start_decode(state) && (int_res = (multi_decode(1, 5, &(*result)._Upload_members_count, (void *)decode_Member, state, (&(*result)._Upload_members), sizeof(struct Member_))), ((map_end_decode(state)) && int_res)))));
    2654:	f003 fd7a 	bl	614c <map_start_decode>
    2658:	b920      	cbnz	r0, 2664 <decode_Upload+0x18>
    265a:	2400      	movs	r4, #0

	if (!tmp_result)
		cbor_trace();

	return tmp_result;
}
    265c:	f004 0001 	and.w	r0, r4, #1
    2660:	b005      	add	sp, #20
    2662:	bd30      	pop	{r4, r5, pc}
	bool tmp_result = (((map_start_decode(state) && (int_res = (multi_decode(1, 5, &(*result)._Upload_members_count, (void *)decode_Member, state, (&(*result)._Upload_members), sizeof(struct Member_))), ((map_end_decode(state)) && int_res)))));
    2664:	230c      	movs	r3, #12
    2666:	e9cd 4301 	strd	r4, r3, [sp, #4]
    266a:	f104 023c 	add.w	r2, r4, #60	; 0x3c
    266e:	4b06      	ldr	r3, [pc, #24]	; (2688 <decode_Upload+0x3c>)
    2670:	9500      	str	r5, [sp, #0]
    2672:	2105      	movs	r1, #5
    2674:	2001      	movs	r0, #1
    2676:	f003 fd79 	bl	616c <multi_decode>
    267a:	4604      	mov	r4, r0
    267c:	4628      	mov	r0, r5
    267e:	f003 fd73 	bl	6168 <map_end_decode>
    2682:	2800      	cmp	r0, #0
    2684:	d0e9      	beq.n	265a <decode_Upload+0xe>
    2686:	e7e9      	b.n	265c <decode_Upload+0x10>
    2688:	0000268d 	.word	0x0000268d

0000268c <decode_Member>:
{
    268c:	b573      	push	{r0, r1, r4, r5, r6, lr}
    268e:	4604      	mov	r4, r0
    2690:	460e      	mov	r6, r1
	bool tmp_result = (((union_start_code(state) && (int_res = (((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"image",
    2692:	f003 fe99 	bl	63c8 <union_start_code>
    2696:	4605      	mov	r5, r0
    2698:	b338      	cbz	r0, 26ea <decode_Member+0x5e>
    269a:	4b36      	ldr	r3, [pc, #216]	; (2774 <decode_Member+0xe8>)
    269c:	9300      	str	r3, [sp, #0]
    269e:	4669      	mov	r1, sp
    tmp_str.len = sizeof("image") - 1, &tmp_str)))))
    26a0:	2305      	movs	r3, #5
	bool tmp_result = (((union_start_code(state) && (int_res = (((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"image",
    26a2:	4620      	mov	r0, r4
    tmp_str.len = sizeof("image") - 1, &tmp_str)))))
    26a4:	9301      	str	r3, [sp, #4]
	bool tmp_result = (((union_start_code(state) && (int_res = (((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"image",
    26a6:	f003 fd4e 	bl	6146 <tstrx_expect>
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"sha",
    26aa:	b138      	cbz	r0, 26bc <decode_Member+0x30>
	&& (intx32_decode(state, (&(*result)._Member_image)))) && (((*result)._Member_choice = _Member_image) || 1))
    26ac:	4631      	mov	r1, r6
    26ae:	4620      	mov	r0, r4
    26b0:	f003 fcfd 	bl	60ae <intx32_decode>
    26b4:	b110      	cbz	r0, 26bc <decode_Member+0x30>
    26b6:	2300      	movs	r3, #0
	&& (bstrx_decode(state, (&(*result)._Member_sha)))) && (((*result)._Member_choice = _Member_sha) || 1)))), union_end_code(state), int_res))));
    26b8:	7233      	strb	r3, [r6, #8]
    26ba:	e040      	b.n	273e <decode_Member+0xb2>
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"data",
    26bc:	4620      	mov	r0, r4
    26be:	f003 fe86 	bl	63ce <union_elem_code>
    26c2:	b1a8      	cbz	r0, 26f0 <decode_Member+0x64>
    26c4:	4b2c      	ldr	r3, [pc, #176]	; (2778 <decode_Member+0xec>)
    26c6:	9300      	str	r3, [sp, #0]
    26c8:	4669      	mov	r1, sp
    tmp_str.len = sizeof("data") - 1, &tmp_str)))))
    26ca:	2304      	movs	r3, #4
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"data",
    26cc:	4620      	mov	r0, r4
    tmp_str.len = sizeof("data") - 1, &tmp_str)))))
    26ce:	9301      	str	r3, [sp, #4]
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"data",
    26d0:	f003 fd39 	bl	6146 <tstrx_expect>
    26d4:	b160      	cbz	r0, 26f0 <decode_Member+0x64>
	&& (bstrx_decode(state, (&(*result)._Member_data)))) && (((*result)._Member_choice = _Member_data) || 1)))
    26d6:	4631      	mov	r1, r6
    26d8:	4620      	mov	r0, r4
    26da:	f003 fd31 	bl	6140 <bstrx_decode>
    26de:	b138      	cbz	r0, 26f0 <decode_Member+0x64>
    26e0:	2501      	movs	r5, #1
    26e2:	7235      	strb	r5, [r6, #8]
	&& (bstrx_decode(state, (&(*result)._Member_sha)))) && (((*result)._Member_choice = _Member_sha) || 1)))), union_end_code(state), int_res))));
    26e4:	4620      	mov	r0, r4
    26e6:	f003 fe76 	bl	63d6 <union_end_code>
}
    26ea:	4628      	mov	r0, r5
    26ec:	b002      	add	sp, #8
    26ee:	bd70      	pop	{r4, r5, r6, pc}
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"len",
    26f0:	4620      	mov	r0, r4
    26f2:	f003 fe6c 	bl	63ce <union_elem_code>
    26f6:	b178      	cbz	r0, 2718 <decode_Member+0x8c>
    26f8:	4b20      	ldr	r3, [pc, #128]	; (277c <decode_Member+0xf0>)
    26fa:	9300      	str	r3, [sp, #0]
    26fc:	4669      	mov	r1, sp
    tmp_str.len = sizeof("len") - 1, &tmp_str)))))
    26fe:	2303      	movs	r3, #3
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"len",
    2700:	4620      	mov	r0, r4
    tmp_str.len = sizeof("len") - 1, &tmp_str)))))
    2702:	9301      	str	r3, [sp, #4]
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"len",
    2704:	f003 fd1f 	bl	6146 <tstrx_expect>
    2708:	b130      	cbz	r0, 2718 <decode_Member+0x8c>
	&& (intx32_decode(state, (&(*result)._Member_len)))) && (((*result)._Member_choice = _Member_len) || 1)))
    270a:	4631      	mov	r1, r6
    270c:	4620      	mov	r0, r4
    270e:	f003 fcce 	bl	60ae <intx32_decode>
    2712:	b108      	cbz	r0, 2718 <decode_Member+0x8c>
    2714:	2302      	movs	r3, #2
    2716:	e7cf      	b.n	26b8 <decode_Member+0x2c>
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"off",
    2718:	4620      	mov	r0, r4
    271a:	f003 fe58 	bl	63ce <union_elem_code>
    271e:	b180      	cbz	r0, 2742 <decode_Member+0xb6>
    2720:	4b17      	ldr	r3, [pc, #92]	; (2780 <decode_Member+0xf4>)
    2722:	9300      	str	r3, [sp, #0]
    tmp_str.len = sizeof("off") - 1, &tmp_str)))))
    2724:	2503      	movs	r5, #3
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"off",
    2726:	4669      	mov	r1, sp
    2728:	4620      	mov	r0, r4
    tmp_str.len = sizeof("off") - 1, &tmp_str)))))
    272a:	9501      	str	r5, [sp, #4]
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"off",
    272c:	f003 fd0b 	bl	6146 <tstrx_expect>
    2730:	b138      	cbz	r0, 2742 <decode_Member+0xb6>
	&& (intx32_decode(state, (&(*result)._Member_off)))) && (((*result)._Member_choice = _Member_off) || 1)))
    2732:	4631      	mov	r1, r6
    2734:	4620      	mov	r0, r4
    2736:	f003 fcba 	bl	60ae <intx32_decode>
    273a:	b110      	cbz	r0, 2742 <decode_Member+0xb6>
    273c:	7235      	strb	r5, [r6, #8]
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"sha",
    273e:	2501      	movs	r5, #1
    2740:	e7d0      	b.n	26e4 <decode_Member+0x58>
    2742:	4620      	mov	r0, r4
    2744:	f003 fe43 	bl	63ce <union_elem_code>
    2748:	b908      	cbnz	r0, 274e <decode_Member+0xc2>
    274a:	2500      	movs	r5, #0
    274c:	e7ca      	b.n	26e4 <decode_Member+0x58>
    274e:	4b0d      	ldr	r3, [pc, #52]	; (2784 <decode_Member+0xf8>)
    2750:	9300      	str	r3, [sp, #0]
    2752:	4669      	mov	r1, sp
    tmp_str.len = sizeof("sha") - 1, &tmp_str)))))
    2754:	2303      	movs	r3, #3
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"sha",
    2756:	4620      	mov	r0, r4
    tmp_str.len = sizeof("sha") - 1, &tmp_str)))))
    2758:	9301      	str	r3, [sp, #4]
	|| (union_elem_code(state) && ((((tstrx_expect(state, ((tmp_str.value = (const uint8_t *)"sha",
    275a:	f003 fcf4 	bl	6146 <tstrx_expect>
    275e:	2800      	cmp	r0, #0
    2760:	d0f3      	beq.n	274a <decode_Member+0xbe>
	&& (bstrx_decode(state, (&(*result)._Member_sha)))) && (((*result)._Member_choice = _Member_sha) || 1)))), union_end_code(state), int_res))));
    2762:	4631      	mov	r1, r6
    2764:	4620      	mov	r0, r4
    2766:	f003 fceb 	bl	6140 <bstrx_decode>
    276a:	2800      	cmp	r0, #0
    276c:	d0ed      	beq.n	274a <decode_Member+0xbe>
    276e:	2304      	movs	r3, #4
    2770:	e7a2      	b.n	26b8 <decode_Member+0x2c>
    2772:	bf00      	nop
    2774:	00009079 	.word	0x00009079
    2778:	00009482 	.word	0x00009482
    277c:	00009487 	.word	0x00009487
    2780:	0000939a 	.word	0x0000939a
    2784:	0000948b 	.word	0x0000948b

00002788 <cbor_decode_Upload>:

bool cbor_decode_Upload(
		const uint8_t *payload, uint32_t payload_len,
		struct Upload *result,
		uint32_t *payload_len_out)
{
    2788:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	return entry_function(payload, payload_len, (const void *)result,
    278a:	f04f 0c02 	mov.w	ip, #2
    278e:	2401      	movs	r4, #1
    2790:	e9cd 4c01 	strd	r4, ip, [sp, #4]
    2794:	4c02      	ldr	r4, [pc, #8]	; (27a0 <cbor_decode_Upload+0x18>)
    2796:	9400      	str	r4, [sp, #0]
    2798:	f003 fe21 	bl	63de <entry_function>
		payload_len_out, (void *)decode_Upload,
		1, 2);
}
    279c:	b004      	add	sp, #16
    279e:	bd10      	pop	{r4, pc}
    27a0:	0000264d 	.word	0x0000264d

000027a4 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    27a4:	4901      	ldr	r1, [pc, #4]	; (27ac <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    27a6:	2210      	movs	r2, #16
	str	r2, [r1]
    27a8:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    27aa:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    27ac:	e000ed10 	.word	0xe000ed10

000027b0 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    27b0:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    27b2:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    27b4:	f380 8811 	msr	BASEPRI, r0
	isb
    27b8:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    27bc:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    27c0:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    27c2:	b662      	cpsie	i
	isb
    27c4:	f3bf 8f6f 	isb	sy

	bx	lr
    27c8:	4770      	bx	lr
    27ca:	bf00      	nop

000027cc <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    27cc:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    27ce:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    27d0:	f381 8811 	msr	BASEPRI, r1

	wfe
    27d4:	bf20      	wfe

	msr	BASEPRI, r0
    27d6:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    27da:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    27dc:	4770      	bx	lr
    27de:	bf00      	nop

000027e0 <z_arm_fatal_error>:
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
		esf->basic.pc);
}

void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    27e0:	b537      	push	{r0, r1, r2, r4, r5, lr}
    27e2:	4605      	mov	r5, r0

	if (esf != NULL) {
    27e4:	460c      	mov	r4, r1
    27e6:	b1c9      	cbz	r1, 281c <CONFIG_MAIN_STACK_SIZE+0x1c>
	LOG_ERR("r0/a1:  0x%08x  r1/a2:  0x%08x  r2/a3:  0x%08x",
    27e8:	688b      	ldr	r3, [r1, #8]
    27ea:	9300      	str	r3, [sp, #0]
    27ec:	e9d1 2300 	ldrd	r2, r3, [r1]
    27f0:	480e      	ldr	r0, [pc, #56]	; (282c <CONFIG_MAIN_STACK_SIZE+0x2c>)
    27f2:	2145      	movs	r1, #69	; 0x45
    27f4:	f003 fb23 	bl	5e3e <z_log_minimal_printk>
	LOG_ERR("r3/a4:  0x%08x r12/ip:  0x%08x r14/lr:  0x%08x",
    27f8:	6963      	ldr	r3, [r4, #20]
    27fa:	9300      	str	r3, [sp, #0]
    27fc:	e9d4 2303 	ldrd	r2, r3, [r4, #12]
    2800:	480b      	ldr	r0, [pc, #44]	; (2830 <CONFIG_MAIN_STACK_SIZE+0x30>)
    2802:	2145      	movs	r1, #69	; 0x45
    2804:	f003 fb1b 	bl	5e3e <z_log_minimal_printk>
	LOG_ERR(" xpsr:  0x%08x", esf->basic.xpsr);
    2808:	69e2      	ldr	r2, [r4, #28]
    280a:	480a      	ldr	r0, [pc, #40]	; (2834 <CONFIG_MAIN_STACK_SIZE+0x34>)
    280c:	2145      	movs	r1, #69	; 0x45
    280e:	f003 fb16 	bl	5e3e <z_log_minimal_printk>
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
    2812:	69a2      	ldr	r2, [r4, #24]
    2814:	4808      	ldr	r0, [pc, #32]	; (2838 <CONFIG_MAIN_STACK_SIZE+0x38>)
    2816:	2145      	movs	r1, #69	; 0x45
    2818:	f003 fb11 	bl	5e3e <z_log_minimal_printk>
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    281c:	4621      	mov	r1, r4
    281e:	4628      	mov	r0, r5
}
    2820:	b003      	add	sp, #12
    2822:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
	z_fatal_error(reason, esf);
    2826:	f002 be4d 	b.w	54c4 <z_fatal_error>
    282a:	bf00      	nop
    282c:	0000948f 	.word	0x0000948f
    2830:	000094c3 	.word	0x000094c3
    2834:	000094f7 	.word	0x000094f7
    2838:	0000950b 	.word	0x0000950b

0000283c <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    283c:	b243      	sxtb	r3, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    283e:	2b00      	cmp	r3, #0
    2840:	db08      	blt.n	2854 <arch_irq_enable+0x18>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2842:	2201      	movs	r2, #1
    2844:	f000 001f 	and.w	r0, r0, #31
    2848:	fa02 f000 	lsl.w	r0, r2, r0
    284c:	095b      	lsrs	r3, r3, #5
    284e:	4a02      	ldr	r2, [pc, #8]	; (2858 <arch_irq_enable+0x1c>)
    2850:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    2854:	4770      	bx	lr
    2856:	bf00      	nop
    2858:	e000e100 	.word	0xe000e100

0000285c <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    285c:	4b05      	ldr	r3, [pc, #20]	; (2874 <arch_irq_is_enabled+0x18>)
    285e:	0942      	lsrs	r2, r0, #5
    2860:	f000 001f 	and.w	r0, r0, #31
    2864:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    2868:	2301      	movs	r3, #1
    286a:	fa03 f000 	lsl.w	r0, r3, r0
}
    286e:	4010      	ands	r0, r2
    2870:	4770      	bx	lr
    2872:	bf00      	nop
    2874:	e000e100 	.word	0xe000e100

00002878 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    2878:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    287a:	2b00      	cmp	r3, #0
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    287c:	bfa8      	it	ge
    287e:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
		prio += _IRQ_PRIO_OFFSET;
    2882:	f101 0101 	add.w	r1, r1, #1
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2886:	bfb8      	it	lt
    2888:	4b06      	ldrlt	r3, [pc, #24]	; (28a4 <z_arm_irq_priority_set+0x2c>)
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    288a:	ea4f 1141 	mov.w	r1, r1, lsl #5
    288e:	bfac      	ite	ge
    2890:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2894:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2898:	b2c9      	uxtb	r1, r1
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    289a:	bfb4      	ite	lt
    289c:	5419      	strblt	r1, [r3, r0]
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    289e:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
}
    28a2:	4770      	bx	lr
    28a4:	e000ed14 	.word	0xe000ed14

000028a8 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    28a8:	bf30      	wfi
    b z_SysNmiOnReset
    28aa:	f7ff bffd 	b.w	28a8 <z_SysNmiOnReset>
    28ae:	bf00      	nop

000028b0 <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    28b0:	4a0b      	ldr	r2, [pc, #44]	; (28e0 <z_arm_prep_c+0x30>)
 *
 * This routine prepares for the execution of and runs C code.
 *
 */
void z_arm_prep_c(void)
{
    28b2:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    28b4:	4b0b      	ldr	r3, [pc, #44]	; (28e4 <z_arm_prep_c+0x34>)
    28b6:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    28ba:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    28bc:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    28c0:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    28c4:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    28c8:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    28cc:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    28d0:	f002 fe4e 	bl	5570 <z_bss_zero>
	z_data_copy();
    28d4:	f002 fe92 	bl	55fc <z_data_copy>
#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    28d8:	f000 fa4e 	bl	2d78 <z_arm_interrupt_init>
	z_cstart();
    28dc:	f002 fe54 	bl	5588 <z_cstart>
    28e0:	00000000 	.word	0x00000000
    28e4:	e000ed00 	.word	0xe000ed00

000028e8 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    28e8:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    28ec:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    28ee:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    28f2:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    28f6:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    28f8:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    28fc:	2902      	cmp	r1, #2
    beq _oops
    28fe:	d0ff      	beq.n	2900 <_oops>

00002900 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    2900:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    2902:	f003 fd9e 	bl	6442 <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    2906:	bd01      	pop	{r0, pc}

00002908 <z_check_thread_stack_fail>:
			fault_addr, psp)) {
		/* Thread stack corruption */
		return thread->stack_info.start;
	}
#else
	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack,
    2908:	f110 0f16 	cmn.w	r0, #22
    290c:	4b07      	ldr	r3, [pc, #28]	; (292c <z_check_thread_stack_fail+0x24>)
    290e:	d008      	beq.n	2922 <z_check_thread_stack_fail+0x1a>
    2910:	4298      	cmp	r0, r3
    2912:	d308      	bcc.n	2926 <z_check_thread_stack_fail+0x1e>
    2914:	3320      	adds	r3, #32
    2916:	4283      	cmp	r3, r0
    2918:	d905      	bls.n	2926 <z_check_thread_stack_fail+0x1e>
    291a:	428b      	cmp	r3, r1
    291c:	d903      	bls.n	2926 <z_check_thread_stack_fail+0x1e>
			guard_len,
			fault_addr, psp)) {
		/* Thread stack corruption */
		return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack);
    291e:	4804      	ldr	r0, [pc, #16]	; (2930 <z_check_thread_stack_fail+0x28>)
    2920:	4770      	bx	lr
	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack,
    2922:	3320      	adds	r3, #32
    2924:	e7f9      	b.n	291a <z_check_thread_stack_fail+0x12>
	}
#endif
#endif /* CONFIG_USERSPACE */

	return 0;
    2926:	2000      	movs	r0, #0
}
    2928:	4770      	bx	lr
    292a:	bf00      	nop
    292c:	20003560 	.word	0x20003560
    2930:	20003580 	.word	0x20003580

00002934 <z_arm_switch_to_main_no_multithreading>:

#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M)

FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
	k_thread_entry_t main_entry, void *p1, void *p2, void *p3)
{
    2934:	4604      	mov	r4, r0
	 */
	register void *p1_inreg __asm__("r0") = p1;
	register void *p2_inreg __asm__("r1") = p2;
	register void *p3_inreg __asm__("r2") = p3;

	__asm__ volatile (
    2936:	2520      	movs	r5, #32
	register void *p1_inreg __asm__("r0") = p1;
    2938:	4608      	mov	r0, r1
	register void *p2_inreg __asm__("r1") = p2;
    293a:	4611      	mov	r1, r2
	register void *p3_inreg __asm__("r2") = p3;
    293c:	461a      	mov	r2, r3
	__asm__ volatile (
    293e:	4b08      	ldr	r3, [pc, #32]	; (2960 <loop+0x4>)
    2940:	f383 8809 	msr	PSP, r3
    2944:	b663      	cpsie	if
    2946:	f04f 0300 	mov.w	r3, #0
    294a:	f383 8811 	msr	BASEPRI, r3
    294e:	f3bf 8f6f 	isb	sy
    2952:	47a0      	blx	r4
    2954:	f385 8811 	msr	BASEPRI, r5
    2958:	f3bf 8f6f 	isb	sy

0000295c <loop>:
    295c:	e7fe      	b.n	295c <loop>
	, [_psplim]"r" (psplim)
#endif
	:
	);

	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    295e:	bf00      	nop
    2960:	20005d80 	.word	0x20005d80

00002964 <_isr_wrapper>:
 *
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    2964:	b501      	push	{r0, lr}
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    2966:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    296a:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    296e:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    2972:	4904      	ldr	r1, [pc, #16]	; (2984 <_isr_wrapper+0x20>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    2974:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    2976:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    2978:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    297a:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    297e:	4902      	ldr	r1, [pc, #8]	; (2988 <_isr_wrapper+0x24>)
	bx r1
    2980:	4708      	bx	r1
    2982:	0000      	.short	0x0000
	ldr r1, =_sw_isr_table
    2984:	000087c4 	.word	0x000087c4
	ldr r1, =z_arm_int_exit
    2988:	0000298d 	.word	0x0000298d

0000298c <z_arm_exc_exit>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    298c:	4770      	bx	lr
    298e:	bf00      	nop

00002990 <mem_manage_fault>:
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
			      bool *recoverable)
{
    2990:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    2994:	4c32      	ldr	r4, [pc, #200]	; (2a60 <mem_manage_fault+0xd0>)
{
    2996:	4607      	mov	r7, r0
    2998:	4688      	mov	r8, r1
	PR_FAULT_INFO("***** MPU FAULT *****");
    299a:	4832      	ldr	r0, [pc, #200]	; (2a64 <mem_manage_fault+0xd4>)
    299c:	2145      	movs	r1, #69	; 0x45
{
    299e:	4615      	mov	r5, r2
	PR_FAULT_INFO("***** MPU FAULT *****");
    29a0:	f003 fa4d 	bl	5e3e <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    29a4:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    29a6:	06de      	lsls	r6, r3, #27
    29a8:	d503      	bpl.n	29b2 <mem_manage_fault+0x22>
		PR_FAULT_INFO("  Stacking error (context area might be"
    29aa:	482f      	ldr	r0, [pc, #188]	; (2a68 <mem_manage_fault+0xd8>)
    29ac:	2145      	movs	r1, #69	; 0x45
    29ae:	f003 fa46 	bl	5e3e <z_log_minimal_printk>
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    29b2:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    29b4:	071c      	lsls	r4, r3, #28
    29b6:	d503      	bpl.n	29c0 <mem_manage_fault+0x30>
		PR_FAULT_INFO("  Unstacking error");
    29b8:	482c      	ldr	r0, [pc, #176]	; (2a6c <mem_manage_fault+0xdc>)
    29ba:	2145      	movs	r1, #69	; 0x45
    29bc:	f003 fa3f 	bl	5e3e <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    29c0:	4c27      	ldr	r4, [pc, #156]	; (2a60 <mem_manage_fault+0xd0>)
    29c2:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    29c4:	0798      	lsls	r0, r3, #30
    29c6:	d428      	bmi.n	2a1a <mem_manage_fault+0x8a>
	uint32_t mmfar = -EINVAL;
    29c8:	f06f 0615 	mvn.w	r6, #21
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
			}
		}
	}
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    29cc:	4c24      	ldr	r4, [pc, #144]	; (2a60 <mem_manage_fault+0xd0>)
    29ce:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    29d0:	07da      	lsls	r2, r3, #31
    29d2:	d503      	bpl.n	29dc <mem_manage_fault+0x4c>
		PR_FAULT_INFO("  Instruction Access Violation");
    29d4:	4826      	ldr	r0, [pc, #152]	; (2a70 <mem_manage_fault+0xe0>)
    29d6:	2145      	movs	r1, #69	; 0x45
    29d8:	f003 fa31 	bl	5e3e <z_log_minimal_printk>
	}
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    29dc:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    29de:	069b      	lsls	r3, r3, #26
    29e0:	d503      	bpl.n	29ea <mem_manage_fault+0x5a>
		PR_FAULT_INFO(
    29e2:	4824      	ldr	r0, [pc, #144]	; (2a74 <mem_manage_fault+0xe4>)
    29e4:	2145      	movs	r1, #69	; 0x45
    29e6:	f003 fa2a 	bl	5e3e <z_log_minimal_printk>
	 * crossed into an area beyond the thread stack.]
	 *
	 * Data Access Violation errors may or may not be caused by
	 * thread stack overflows.
	 */
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    29ea:	4b1d      	ldr	r3, [pc, #116]	; (2a60 <mem_manage_fault+0xd0>)
    29ec:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    29ee:	06d4      	lsls	r4, r2, #27
    29f0:	d428      	bmi.n	2a44 <mem_manage_fault+0xb4>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    29f2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    29f4:	0790      	lsls	r0, r2, #30
    29f6:	d425      	bmi.n	2a44 <mem_manage_fault+0xb4>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    29f8:	2000      	movs	r0, #0
	 * lazy stacking Memory Manage fault. At the time of writing, this
	 * can happen when printing.  If that's true, we should clear the
	 * pending flag in addition to the clearing the reason for the fault
	 */
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    29fa:	4b19      	ldr	r3, [pc, #100]	; (2a60 <mem_manage_fault+0xd0>)
    29fc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    29fe:	0692      	lsls	r2, r2, #26
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
    2a00:	bf42      	ittt	mi
    2a02:	6a5a      	ldrmi	r2, [r3, #36]	; 0x24
    2a04:	f422 5200 	bicmi.w	r2, r2, #8192	; 0x2000
    2a08:	625a      	strmi	r2, [r3, #36]	; 0x24
	}
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    2a0a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    2a0c:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    2a10:	629a      	str	r2, [r3, #40]	; 0x28

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf, true);
    2a12:	2300      	movs	r3, #0
    2a14:	702b      	strb	r3, [r5, #0]

	return reason;
}
    2a16:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		PR_FAULT_INFO("  Data Access Violation");
    2a1a:	2145      	movs	r1, #69	; 0x45
    2a1c:	4816      	ldr	r0, [pc, #88]	; (2a78 <mem_manage_fault+0xe8>)
    2a1e:	f003 fa0e 	bl	5e3e <z_log_minimal_printk>
		uint32_t temp = SCB->MMFAR;
    2a22:	6b66      	ldr	r6, [r4, #52]	; 0x34
		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    2a24:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2a26:	0619      	lsls	r1, r3, #24
    2a28:	d5ce      	bpl.n	29c8 <mem_manage_fault+0x38>
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
    2a2a:	4814      	ldr	r0, [pc, #80]	; (2a7c <mem_manage_fault+0xec>)
    2a2c:	4632      	mov	r2, r6
    2a2e:	2145      	movs	r1, #69	; 0x45
    2a30:	f003 fa05 	bl	5e3e <z_log_minimal_printk>
			if (from_hard_fault != 0) {
    2a34:	f1b8 0f00 	cmp.w	r8, #0
    2a38:	d0c8      	beq.n	29cc <mem_manage_fault+0x3c>
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    2a3a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2a3c:	f023 0380 	bic.w	r3, r3, #128	; 0x80
    2a40:	62a3      	str	r3, [r4, #40]	; 0x28
    2a42:	e7c3      	b.n	29cc <mem_manage_fault+0x3c>
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
    2a44:	685b      	ldr	r3, [r3, #4]
    2a46:	0519      	lsls	r1, r3, #20
    2a48:	d5d6      	bpl.n	29f8 <mem_manage_fault+0x68>
			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
    2a4a:	4639      	mov	r1, r7
    2a4c:	4630      	mov	r0, r6
    2a4e:	f7ff ff5b 	bl	2908 <z_check_thread_stack_fail>
			if (min_stack_ptr) {
    2a52:	2800      	cmp	r0, #0
    2a54:	d0d0      	beq.n	29f8 <mem_manage_fault+0x68>
  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
    2a56:	f380 8809 	msr	PSP, r0
				reason = K_ERR_STACK_CHK_FAIL;
    2a5a:	2002      	movs	r0, #2
    2a5c:	e7cd      	b.n	29fa <mem_manage_fault+0x6a>
    2a5e:	bf00      	nop
    2a60:	e000ed00 	.word	0xe000ed00
    2a64:	0000953e 	.word	0x0000953e
    2a68:	00009559 	.word	0x00009559
    2a6c:	00009591 	.word	0x00009591
    2a70:	000095e1 	.word	0x000095e1
    2a74:	00009605 	.word	0x00009605
    2a78:	000095a9 	.word	0x000095a9
    2a7c:	000095c6 	.word	0x000095c6

00002a80 <usage_fault.constprop.0>:
 *
 * See z_arm_fault_dump() for example.
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t usage_fault(const z_arch_esf_t *esf)
    2a80:	b510      	push	{r4, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    2a82:	4c1d      	ldr	r4, [pc, #116]	; (2af8 <usage_fault.constprop.0+0x78>)
	PR_FAULT_INFO("***** USAGE FAULT *****");
    2a84:	481d      	ldr	r0, [pc, #116]	; (2afc <usage_fault.constprop.0+0x7c>)
    2a86:	2145      	movs	r1, #69	; 0x45
    2a88:	f003 f9d9 	bl	5e3e <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    2a8c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2a8e:	019b      	lsls	r3, r3, #6
    2a90:	d503      	bpl.n	2a9a <usage_fault.constprop.0+0x1a>
		PR_FAULT_INFO("  Division by zero");
    2a92:	481b      	ldr	r0, [pc, #108]	; (2b00 <usage_fault.constprop.0+0x80>)
    2a94:	2145      	movs	r1, #69	; 0x45
    2a96:	f003 f9d2 	bl	5e3e <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    2a9a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2a9c:	01dc      	lsls	r4, r3, #7
    2a9e:	d503      	bpl.n	2aa8 <usage_fault.constprop.0+0x28>
		PR_FAULT_INFO("  Unaligned memory access");
    2aa0:	4818      	ldr	r0, [pc, #96]	; (2b04 <usage_fault.constprop.0+0x84>)
    2aa2:	2145      	movs	r1, #69	; 0x45
    2aa4:	f003 f9cb 	bl	5e3e <z_log_minimal_printk>
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    2aa8:	4c13      	ldr	r4, [pc, #76]	; (2af8 <usage_fault.constprop.0+0x78>)
    2aaa:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2aac:	0318      	lsls	r0, r3, #12
    2aae:	d503      	bpl.n	2ab8 <usage_fault.constprop.0+0x38>
		PR_FAULT_INFO("  No coprocessor instructions");
    2ab0:	4815      	ldr	r0, [pc, #84]	; (2b08 <usage_fault.constprop.0+0x88>)
    2ab2:	2145      	movs	r1, #69	; 0x45
    2ab4:	f003 f9c3 	bl	5e3e <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    2ab8:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2aba:	0359      	lsls	r1, r3, #13
    2abc:	d503      	bpl.n	2ac6 <usage_fault.constprop.0+0x46>
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
    2abe:	4813      	ldr	r0, [pc, #76]	; (2b0c <usage_fault.constprop.0+0x8c>)
    2ac0:	2145      	movs	r1, #69	; 0x45
    2ac2:	f003 f9bc 	bl	5e3e <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    2ac6:	4c0c      	ldr	r4, [pc, #48]	; (2af8 <usage_fault.constprop.0+0x78>)
    2ac8:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2aca:	039a      	lsls	r2, r3, #14
    2acc:	d503      	bpl.n	2ad6 <usage_fault.constprop.0+0x56>
		PR_FAULT_INFO("  Illegal use of the EPSR");
    2ace:	4810      	ldr	r0, [pc, #64]	; (2b10 <usage_fault.constprop.0+0x90>)
    2ad0:	2145      	movs	r1, #69	; 0x45
    2ad2:	f003 f9b4 	bl	5e3e <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    2ad6:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2ad8:	03db      	lsls	r3, r3, #15
    2ada:	d503      	bpl.n	2ae4 <usage_fault.constprop.0+0x64>
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
    2adc:	480d      	ldr	r0, [pc, #52]	; (2b14 <usage_fault.constprop.0+0x94>)
    2ade:	2145      	movs	r1, #69	; 0x45
    2ae0:	f003 f9ad 	bl	5e3e <z_log_minimal_printk>
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    2ae4:	4a04      	ldr	r2, [pc, #16]	; (2af8 <usage_fault.constprop.0+0x78>)
    2ae6:	6a93      	ldr	r3, [r2, #40]	; 0x28
    2ae8:	ea6f 4303 	mvn.w	r3, r3, lsl #16
    2aec:	ea6f 4313 	mvn.w	r3, r3, lsr #16
    2af0:	6293      	str	r3, [r2, #40]	; 0x28

	return reason;
}
    2af2:	2000      	movs	r0, #0
    2af4:	bd10      	pop	{r4, pc}
    2af6:	bf00      	nop
    2af8:	e000ed00 	.word	0xe000ed00
    2afc:	00009639 	.word	0x00009639
    2b00:	00009656 	.word	0x00009656
    2b04:	0000966e 	.word	0x0000966e
    2b08:	0000968d 	.word	0x0000968d
    2b0c:	000096b0 	.word	0x000096b0
    2b10:	000096da 	.word	0x000096da
    2b14:	000096f9 	.word	0x000096f9

00002b18 <bus_fault.constprop.0>:
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    2b18:	b570      	push	{r4, r5, r6, lr}
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    2b1a:	4c23      	ldr	r4, [pc, #140]	; (2ba8 <bus_fault.constprop.0+0x90>)
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    2b1c:	4606      	mov	r6, r0
    2b1e:	460d      	mov	r5, r1
	PR_FAULT_INFO("***** BUS FAULT *****");
    2b20:	4822      	ldr	r0, [pc, #136]	; (2bac <bus_fault.constprop.0+0x94>)
    2b22:	2145      	movs	r1, #69	; 0x45
    2b24:	f003 f98b 	bl	5e3e <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    2b28:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2b2a:	04d9      	lsls	r1, r3, #19
    2b2c:	d503      	bpl.n	2b36 <bus_fault.constprop.0+0x1e>
		PR_FAULT_INFO("  Stacking error");
    2b2e:	4820      	ldr	r0, [pc, #128]	; (2bb0 <bus_fault.constprop.0+0x98>)
    2b30:	2145      	movs	r1, #69	; 0x45
    2b32:	f003 f984 	bl	5e3e <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    2b36:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2b38:	051a      	lsls	r2, r3, #20
    2b3a:	d503      	bpl.n	2b44 <bus_fault.constprop.0+0x2c>
		PR_FAULT_INFO("  Unstacking error");
    2b3c:	481d      	ldr	r0, [pc, #116]	; (2bb4 <bus_fault.constprop.0+0x9c>)
    2b3e:	2145      	movs	r1, #69	; 0x45
    2b40:	f003 f97d 	bl	5e3e <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    2b44:	4c18      	ldr	r4, [pc, #96]	; (2ba8 <bus_fault.constprop.0+0x90>)
    2b46:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2b48:	059b      	lsls	r3, r3, #22
    2b4a:	d510      	bpl.n	2b6e <bus_fault.constprop.0+0x56>
		PR_FAULT_INFO("  Precise data bus error");
    2b4c:	481a      	ldr	r0, [pc, #104]	; (2bb8 <bus_fault.constprop.0+0xa0>)
    2b4e:	2145      	movs	r1, #69	; 0x45
    2b50:	f003 f975 	bl	5e3e <z_log_minimal_printk>
		STORE_xFAR(bfar, SCB->BFAR);
    2b54:	6ba2      	ldr	r2, [r4, #56]	; 0x38
		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    2b56:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2b58:	0418      	lsls	r0, r3, #16
    2b5a:	d508      	bpl.n	2b6e <bus_fault.constprop.0+0x56>
			PR_EXC("  BFAR Address: 0x%x", bfar);
    2b5c:	4817      	ldr	r0, [pc, #92]	; (2bbc <bus_fault.constprop.0+0xa4>)
    2b5e:	2145      	movs	r1, #69	; 0x45
    2b60:	f003 f96d 	bl	5e3e <z_log_minimal_printk>
			if (from_hard_fault != 0) {
    2b64:	b11e      	cbz	r6, 2b6e <bus_fault.constprop.0+0x56>
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    2b66:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2b68:	f423 4300 	bic.w	r3, r3, #32768	; 0x8000
    2b6c:	62a3      	str	r3, [r4, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    2b6e:	4c0e      	ldr	r4, [pc, #56]	; (2ba8 <bus_fault.constprop.0+0x90>)
    2b70:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2b72:	0559      	lsls	r1, r3, #21
    2b74:	d503      	bpl.n	2b7e <bus_fault.constprop.0+0x66>
		PR_FAULT_INFO("  Imprecise data bus error");
    2b76:	4812      	ldr	r0, [pc, #72]	; (2bc0 <bus_fault.constprop.0+0xa8>)
    2b78:	2145      	movs	r1, #69	; 0x45
    2b7a:	f003 f960 	bl	5e3e <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    2b7e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2b80:	05da      	lsls	r2, r3, #23
    2b82:	d50b      	bpl.n	2b9c <bus_fault.constprop.0+0x84>
		PR_FAULT_INFO("  Instruction bus error");
    2b84:	480f      	ldr	r0, [pc, #60]	; (2bc4 <bus_fault.constprop.0+0xac>)
    2b86:	2145      	movs	r1, #69	; 0x45
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    2b88:	f003 f959 	bl	5e3e <z_log_minimal_printk>
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    2b8c:	4a06      	ldr	r2, [pc, #24]	; (2ba8 <bus_fault.constprop.0+0x90>)
    2b8e:	6a93      	ldr	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    2b90:	2000      	movs	r0, #0
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    2b92:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    2b96:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    2b98:	7028      	strb	r0, [r5, #0]
}
    2b9a:	bd70      	pop	{r4, r5, r6, pc}
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    2b9c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2b9e:	049b      	lsls	r3, r3, #18
    2ba0:	d5f4      	bpl.n	2b8c <bus_fault.constprop.0+0x74>
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    2ba2:	4809      	ldr	r0, [pc, #36]	; (2bc8 <bus_fault.constprop.0+0xb0>)
    2ba4:	2145      	movs	r1, #69	; 0x45
    2ba6:	e7ef      	b.n	2b88 <bus_fault.constprop.0+0x70>
    2ba8:	e000ed00 	.word	0xe000ed00
    2bac:	00009729 	.word	0x00009729
    2bb0:	00009744 	.word	0x00009744
    2bb4:	00009591 	.word	0x00009591
    2bb8:	0000975a 	.word	0x0000975a
    2bbc:	00009778 	.word	0x00009778
    2bc0:	00009792 	.word	0x00009792
    2bc4:	000097b2 	.word	0x000097b2
    2bc8:	00009605 	.word	0x00009605

00002bcc <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    2bcc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    2bd0:	4b55      	ldr	r3, [pc, #340]	; (2d28 <z_arm_fault+0x15c>)
    2bd2:	685f      	ldr	r7, [r3, #4]
{
    2bd4:	b08a      	sub	sp, #40	; 0x28
    2bd6:	460d      	mov	r5, r1
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    2bd8:	f3c7 0408 	ubfx	r4, r7, #0, #9
    2bdc:	2600      	movs	r6, #0
    2bde:	f386 8811 	msr	BASEPRI, r6
    2be2:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    2be6:	f002 437f 	and.w	r3, r2, #4278190080	; 0xff000000
    2bea:	f1b3 4f7f 	cmp.w	r3, #4278190080	; 0xff000000
    2bee:	d107      	bne.n	2c00 <z_arm_fault+0x34>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    2bf0:	f002 030c 	and.w	r3, r2, #12
    2bf4:	2b08      	cmp	r3, #8
    2bf6:	d105      	bne.n	2c04 <z_arm_fault+0x38>
		PR_EXC("SPSEL in thread mode does not indicate PSP");
    2bf8:	484c      	ldr	r0, [pc, #304]	; (2d2c <z_arm_fault+0x160>)
    2bfa:	2145      	movs	r1, #69	; 0x45
    2bfc:	f003 f91f 	bl	5e3e <z_log_minimal_printk>
		return NULL;
    2c00:	4635      	mov	r5, r6
    2c02:	e003      	b.n	2c0c <z_arm_fault+0x40>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    2c04:	0712      	lsls	r2, r2, #28
    2c06:	d401      	bmi.n	2c0c <z_arm_fault+0x40>
			ptr_esf = (z_arch_esf_t *)msp;
    2c08:	4605      	mov	r5, r0
			*nested_exc = true;
    2c0a:	2601      	movs	r6, #1
	*recoverable = false;
    2c0c:	f04f 0800 	mov.w	r8, #0
	switch (fault) {
    2c10:	1ee3      	subs	r3, r4, #3
	*recoverable = false;
    2c12:	f88d 8007 	strb.w	r8, [sp, #7]
	switch (fault) {
    2c16:	2b09      	cmp	r3, #9
    2c18:	d873      	bhi.n	2d02 <z_arm_fault+0x136>
    2c1a:	e8df f003 	tbb	[pc, r3]
    2c1e:	6705      	.short	0x6705
    2c20:	7272646b 	.word	0x7272646b
    2c24:	6f727272 	.word	0x6f727272
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    2c28:	4f3f      	ldr	r7, [pc, #252]	; (2d28 <z_arm_fault+0x15c>)
	PR_FAULT_INFO("***** HARD FAULT *****");
    2c2a:	4841      	ldr	r0, [pc, #260]	; (2d30 <z_arm_fault+0x164>)
    2c2c:	2145      	movs	r1, #69	; 0x45
    2c2e:	f003 f906 	bl	5e3e <z_log_minimal_printk>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    2c32:	6afc      	ldr	r4, [r7, #44]	; 0x2c
	*recoverable = false;
    2c34:	f88d 8007 	strb.w	r8, [sp, #7]
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    2c38:	f014 0402 	ands.w	r4, r4, #2
    2c3c:	d005      	beq.n	2c4a <z_arm_fault+0x7e>
		PR_EXC("  Bus fault on vector table read");
    2c3e:	483d      	ldr	r0, [pc, #244]	; (2d34 <z_arm_fault+0x168>)
    2c40:	2145      	movs	r1, #69	; 0x45
	PR_FAULT_INFO(
    2c42:	f003 f8fc 	bl	5e3e <z_log_minimal_printk>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    2c46:	2400      	movs	r4, #0
}
    2c48:	e006      	b.n	2c58 <z_arm_fault+0x8c>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    2c4a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
    2c4c:	2b00      	cmp	r3, #0
    2c4e:	da1d      	bge.n	2c8c <z_arm_fault+0xc0>
		PR_EXC("  Debug event");
    2c50:	4839      	ldr	r0, [pc, #228]	; (2d38 <z_arm_fault+0x16c>)
    2c52:	2145      	movs	r1, #69	; 0x45
    2c54:	f003 f8f3 	bl	5e3e <z_log_minimal_printk>
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    2c58:	f89d 3007 	ldrb.w	r3, [sp, #7]
    2c5c:	b99b      	cbnz	r3, 2c86 <z_arm_fault+0xba>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    2c5e:	2220      	movs	r2, #32
    2c60:	4629      	mov	r1, r5
    2c62:	a802      	add	r0, sp, #8
    2c64:	f003 fc42 	bl	64ec <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    2c68:	9b09      	ldr	r3, [sp, #36]	; 0x24
    2c6a:	2e00      	cmp	r6, #0
    2c6c:	d056      	beq.n	2d1c <z_arm_fault+0x150>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    2c6e:	f3c3 0208 	ubfx	r2, r3, #0, #9
    2c72:	b922      	cbnz	r2, 2c7e <z_arm_fault+0xb2>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    2c74:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    2c78:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    2c7c:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    2c7e:	a902      	add	r1, sp, #8
    2c80:	4620      	mov	r0, r4
    2c82:	f7ff fdad 	bl	27e0 <z_arm_fatal_error>
}
    2c86:	b00a      	add	sp, #40	; 0x28
    2c88:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    2c8c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
    2c8e:	005b      	lsls	r3, r3, #1
    2c90:	d5e2      	bpl.n	2c58 <z_arm_fault+0x8c>
		PR_EXC("  Fault escalation (see below)");
    2c92:	482a      	ldr	r0, [pc, #168]	; (2d3c <z_arm_fault+0x170>)
    2c94:	2145      	movs	r1, #69	; 0x45
    2c96:	f003 f8d2 	bl	5e3e <z_log_minimal_printk>
	uint16_t fault_insn = *(ret_addr - 1);
    2c9a:	69ab      	ldr	r3, [r5, #24]
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    2c9c:	f833 2c02 	ldrh.w	r2, [r3, #-2]
    2ca0:	f64d 7302 	movw	r3, #57090	; 0xdf02
    2ca4:	429a      	cmp	r2, r3
    2ca6:	d00a      	beq.n	2cbe <z_arm_fault+0xf2>
		} else if (SCB_MMFSR != 0) {
    2ca8:	f897 3028 	ldrb.w	r3, [r7, #40]	; 0x28
    2cac:	b173      	cbz	r3, 2ccc <z_arm_fault+0x100>
			reason = mem_manage_fault(esf, 1, recoverable);
    2cae:	f10d 0207 	add.w	r2, sp, #7
    2cb2:	2101      	movs	r1, #1
		reason = mem_manage_fault(esf, 0, recoverable);
    2cb4:	4628      	mov	r0, r5
    2cb6:	f7ff fe6b 	bl	2990 <mem_manage_fault>
    2cba:	4604      	mov	r4, r0
		break;
    2cbc:	e7cc      	b.n	2c58 <z_arm_fault+0x8c>
			PR_EXC("ARCH_EXCEPT with reason %x\n", esf->basic.r0);
    2cbe:	682a      	ldr	r2, [r5, #0]
    2cc0:	481f      	ldr	r0, [pc, #124]	; (2d40 <z_arm_fault+0x174>)
    2cc2:	2145      	movs	r1, #69	; 0x45
    2cc4:	f003 f8bb 	bl	5e3e <z_log_minimal_printk>
			reason = esf->basic.r0;
    2cc8:	682c      	ldr	r4, [r5, #0]
    2cca:	e7c5      	b.n	2c58 <z_arm_fault+0x8c>
		} else if (SCB_BFSR != 0) {
    2ccc:	f897 3029 	ldrb.w	r3, [r7, #41]	; 0x29
    2cd0:	b12b      	cbz	r3, 2cde <z_arm_fault+0x112>
			reason = bus_fault(esf, 1, recoverable);
    2cd2:	f10d 0107 	add.w	r1, sp, #7
    2cd6:	2001      	movs	r0, #1
		reason = bus_fault(esf, 0, recoverable);
    2cd8:	f7ff ff1e 	bl	2b18 <bus_fault.constprop.0>
    2cdc:	e7ed      	b.n	2cba <z_arm_fault+0xee>
		} else if (SCB_UFSR != 0) {
    2cde:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
    2ce0:	b29b      	uxth	r3, r3
    2ce2:	2b00      	cmp	r3, #0
    2ce4:	d0b8      	beq.n	2c58 <z_arm_fault+0x8c>
		reason = usage_fault(esf);
    2ce6:	f7ff fecb 	bl	2a80 <usage_fault.constprop.0>
    2cea:	e7e6      	b.n	2cba <z_arm_fault+0xee>
		reason = mem_manage_fault(esf, 0, recoverable);
    2cec:	f10d 0207 	add.w	r2, sp, #7
    2cf0:	2100      	movs	r1, #0
    2cf2:	e7df      	b.n	2cb4 <z_arm_fault+0xe8>
		reason = bus_fault(esf, 0, recoverable);
    2cf4:	f10d 0107 	add.w	r1, sp, #7
    2cf8:	2000      	movs	r0, #0
    2cfa:	e7ed      	b.n	2cd8 <z_arm_fault+0x10c>
	PR_FAULT_INFO(
    2cfc:	4811      	ldr	r0, [pc, #68]	; (2d44 <z_arm_fault+0x178>)
    2cfe:	2145      	movs	r1, #69	; 0x45
    2d00:	e79f      	b.n	2c42 <z_arm_fault+0x76>
	PR_FAULT_INFO("***** %s %d) *****",
    2d02:	4911      	ldr	r1, [pc, #68]	; (2d48 <z_arm_fault+0x17c>)
    2d04:	4a11      	ldr	r2, [pc, #68]	; (2d4c <z_arm_fault+0x180>)
    2d06:	4812      	ldr	r0, [pc, #72]	; (2d50 <z_arm_fault+0x184>)
    2d08:	f417 7ff8 	tst.w	r7, #496	; 0x1f0
    2d0c:	bf08      	it	eq
    2d0e:	460a      	moveq	r2, r1
    2d10:	f1a4 0310 	sub.w	r3, r4, #16
    2d14:	2145      	movs	r1, #69	; 0x45
    2d16:	f003 f892 	bl	5e3e <z_log_minimal_printk>
    2d1a:	e794      	b.n	2c46 <z_arm_fault+0x7a>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    2d1c:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    2d20:	f023 0301 	bic.w	r3, r3, #1
    2d24:	e7aa      	b.n	2c7c <z_arm_fault+0xb0>
    2d26:	bf00      	nop
    2d28:	e000ed00 	.word	0xe000ed00
    2d2c:	000097fd 	.word	0x000097fd
    2d30:	0000982d 	.word	0x0000982d
    2d34:	00009849 	.word	0x00009849
    2d38:	0000986f 	.word	0x0000986f
    2d3c:	00009882 	.word	0x00009882
    2d40:	000098a6 	.word	0x000098a6
    2d44:	000098c7 	.word	0x000098c7
    2d48:	000097cf 	.word	0x000097cf
    2d4c:	000097e4 	.word	0x000097e4
    2d50:	000098f0 	.word	0x000098f0

00002d54 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    2d54:	4a02      	ldr	r2, [pc, #8]	; (2d60 <z_arm_fault_init+0xc>)
    2d56:	6953      	ldr	r3, [r2, #20]
    2d58:	f043 0310 	orr.w	r3, r3, #16
    2d5c:	6153      	str	r3, [r2, #20]
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
#ifdef CONFIG_TRAP_UNALIGNED_ACCESS
	SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif /* CONFIG_TRAP_UNALIGNED_ACCESS */
}
    2d5e:	4770      	bx	lr
    2d60:	e000ed00 	.word	0xe000ed00

00002d64 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    2d64:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    2d68:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    2d6c:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    2d6e:	4672      	mov	r2, lr
	bl z_arm_fault
    2d70:	f7ff ff2c 	bl	2bcc <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    2d74:	bd01      	pop	{r0, pc}
    2d76:	bf00      	nop

00002d78 <z_arm_interrupt_init>:
    2d78:	4804      	ldr	r0, [pc, #16]	; (2d8c <z_arm_interrupt_init+0x14>)
 *
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    2d7a:	2300      	movs	r3, #0
    2d7c:	2120      	movs	r1, #32
    2d7e:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    2d80:	3301      	adds	r3, #1
    2d82:	2b27      	cmp	r3, #39	; 0x27
    2d84:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    2d88:	d1f9      	bne.n	2d7e <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    2d8a:	4770      	bx	lr
    2d8c:	e000e100 	.word	0xe000e100

00002d90 <__start>:
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    2d90:	2000      	movs	r0, #0
    msr CONTROL, r0
    2d92:	f380 8814 	msr	CONTROL, r0
    isb
    2d96:	f3bf 8f6f 	isb	sy
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    2d9a:	f005 fcb9 	bl	8710 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    2d9e:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    2da0:	490d      	ldr	r1, [pc, #52]	; (2dd8 <__start+0x48>)
    str r0, [r1]
    2da2:	6008      	str	r0, [r1, #0]
    dsb
    2da4:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    2da8:	480c      	ldr	r0, [pc, #48]	; (2ddc <__start+0x4c>)
    msr msp, r0
    2daa:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    2dae:	f000 f82b 	bl	2e08 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    2db2:	2020      	movs	r0, #32
    msr BASEPRI, r0
    2db4:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    2db8:	4809      	ldr	r0, [pc, #36]	; (2de0 <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    2dba:	f44f 6102 	mov.w	r1, #2080	; 0x820
    adds r0, r0, r1
    2dbe:	1840      	adds	r0, r0, r1
    msr PSP, r0
    2dc0:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    2dc4:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    2dc8:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    2dca:	4308      	orrs	r0, r1
    msr CONTROL, r0
    2dcc:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    2dd0:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    2dd4:	f7ff fd6c 	bl	28b0 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    2dd8:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    2ddc:	20005d60 	.word	0x20005d60
    ldr r0, =z_interrupt_stacks
    2de0:	20005d80 	.word	0x20005d80

00002de4 <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    2de4:	4907      	ldr	r1, [pc, #28]	; (2e04 <z_arm_clear_arm_mpu_config+0x20>)
    2de6:	f8d1 2090 	ldr.w	r2, [r1, #144]	; 0x90

	for (i = 0; i < num_regions; i++) {
    2dea:	2300      	movs	r3, #0
	int num_regions =
    2dec:	f3c2 2207 	ubfx	r2, r2, #8, #8
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
  MPU->RASR = 0U;
    2df0:	4618      	mov	r0, r3
	for (i = 0; i < num_regions; i++) {
    2df2:	4293      	cmp	r3, r2
    2df4:	d100      	bne.n	2df8 <z_arm_clear_arm_mpu_config+0x14>
		ARM_MPU_ClrRegion(i);
	}
}
    2df6:	4770      	bx	lr
  MPU->RNR = rnr;
    2df8:	f8c1 3098 	str.w	r3, [r1, #152]	; 0x98
  MPU->RASR = 0U;
    2dfc:	f8c1 00a0 	str.w	r0, [r1, #160]	; 0xa0
	for (i = 0; i < num_regions; i++) {
    2e00:	3301      	adds	r3, #1
    2e02:	e7f6      	b.n	2df2 <z_arm_clear_arm_mpu_config+0xe>
    2e04:	e000ed00 	.word	0xe000ed00

00002e08 <z_arm_init_arch_hw_at_boot>:
 * This routine resets Cortex-M system control block
 * components and core registers.
 *
 */
void z_arm_init_arch_hw_at_boot(void)
{
    2e08:	b508      	push	{r3, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    2e0a:	b672      	cpsid	i
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    2e0c:	2300      	movs	r3, #0
    2e0e:	f383 8813 	msr	FAULTMASK, r3

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    2e12:	f7ff ffe7 	bl	2de4 <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    2e16:	4b14      	ldr	r3, [pc, #80]	; (2e68 <z_arm_init_arch_hw_at_boot+0x60>)
    2e18:	f04f 32ff 	mov.w	r2, #4294967295
    2e1c:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
    2e20:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
    2e24:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    2e28:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
    2e2c:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
    2e30:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
    2e34:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    2e38:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    2e3c:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    2e40:	f8c3 2184 	str.w	r2, [r3, #388]	; 0x184
    2e44:	f8c3 2188 	str.w	r2, [r3, #392]	; 0x188
    2e48:	f8c3 218c 	str.w	r2, [r3, #396]	; 0x18c
    2e4c:	f8c3 2190 	str.w	r2, [r3, #400]	; 0x190
    2e50:	f8c3 2194 	str.w	r2, [r3, #404]	; 0x194
    2e54:	f8c3 2198 	str.w	r2, [r3, #408]	; 0x198
    2e58:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c
  __ASM volatile ("cpsie i" : : : "memory");
    2e5c:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    2e5e:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2e62:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    2e66:	bd08      	pop	{r3, pc}
    2e68:	e000e100 	.word	0xe000e100

00002e6c <z_arm_configure_static_mpu_regions>:
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    2e6c:	4b02      	ldr	r3, [pc, #8]	; (2e78 <z_arm_configure_static_mpu_regions+0xc>)
    2e6e:	4a03      	ldr	r2, [pc, #12]	; (2e7c <z_arm_configure_static_mpu_regions+0x10>)
    2e70:	4803      	ldr	r0, [pc, #12]	; (2e80 <z_arm_configure_static_mpu_regions+0x14>)
    2e72:	2102      	movs	r1, #2
    2e74:	f000 b86c 	b.w	2f50 <arm_core_mpu_configure_static_mpu_regions>
    2e78:	20010000 	.word	0x20010000
    2e7c:	20000000 	.word	0x20000000
    2e80:	00008a24 	.word	0x00008a24

00002e84 <mpu_configure_regions>:
 * sanity check of the memory regions to be programmed.
 */
static int mpu_configure_regions(const struct z_arm_mpu_partition
	regions[], uint8_t regions_num, uint8_t start_reg_index,
	bool do_sanity_check)
{
    2e84:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */
}

static inline void set_region_number(uint32_t index)
{
	MPU->RNR = index;
    2e86:	4f24      	ldr	r7, [pc, #144]	; (2f18 <mpu_configure_regions+0x94>)
	int i;
	int reg_index = start_reg_index;
    2e88:	4615      	mov	r5, r2

	for (i = 0; i < regions_num; i++) {
    2e8a:	2200      	movs	r2, #0
    2e8c:	428a      	cmp	r2, r1
    2e8e:	da0e      	bge.n	2eae <mpu_configure_regions+0x2a>
		if (regions[i].size == 0U) {
    2e90:	6844      	ldr	r4, [r0, #4]
    2e92:	2c00      	cmp	r4, #0
    2e94:	d03c      	beq.n	2f10 <mpu_configure_regions+0x8c>
			continue;
		}
		/* Non-empty region. */

		if (do_sanity_check &&
    2e96:	b193      	cbz	r3, 2ebe <mpu_configure_regions+0x3a>
	 * and greater or equal to the minimum
	 * MPU region size. Start address of the
	 * partition must align with size.
	 */
	int partition_is_valid =
		((part->size & (part->size - 1U)) == 0U)
    2e98:	f104 3cff 	add.w	ip, r4, #4294967295
		&&
		(part->size >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
		&&
    2e9c:	ea14 0f0c 	tst.w	r4, ip
    2ea0:	d007      	beq.n	2eb2 <mpu_configure_regions+0x2e>
				(!mpu_partition_is_valid(&regions[i]))) {
			LOG_ERR("Partition %u: sanity check failed.", i);
    2ea2:	481e      	ldr	r0, [pc, #120]	; (2f1c <mpu_configure_regions+0x98>)
    2ea4:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    2ea6:	f002 ffca 	bl	5e3e <z_log_minimal_printk>
			return -EINVAL;
		}

		reg_index = mpu_configure_region(reg_index, &regions[i]);
    2eaa:	f06f 0515 	mvn.w	r5, #21
		/* Increment number of programmed MPU indices. */
		reg_index++;
	}

	return reg_index;
}
    2eae:	4628      	mov	r0, r5
    2eb0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		&&
    2eb2:	2c1f      	cmp	r4, #31
    2eb4:	d9f5      	bls.n	2ea2 <mpu_configure_regions+0x1e>
		((part->start & (part->size - 1U)) == 0U);
    2eb6:	6806      	ldr	r6, [r0, #0]
		&&
    2eb8:	ea1c 0f06 	tst.w	ip, r6
    2ebc:	d1f1      	bne.n	2ea2 <mpu_configure_regions+0x1e>
 * to that power-of-two value.
 */
static inline uint32_t size_to_mpu_rasr_size(uint32_t size)
{
	/* The minimal supported region size is 32 bytes */
	if (size <= 32U) {
    2ebe:	2c20      	cmp	r4, #32
	region_conf.base = new_region->start;
    2ec0:	6806      	ldr	r6, [r0, #0]
#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
	(void) size;

	p_attr->rasr = attr->rasr_attr;
#else
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    2ec2:	f8d0 c008 	ldr.w	ip, [r0, #8]
		reg_index = mpu_configure_region(reg_index, &regions[i]);
    2ec6:	b2ed      	uxtb	r5, r5
	if (size <= 32U) {
    2ec8:	d910      	bls.n	2eec <mpu_configure_regions+0x68>
	if (size > (1UL << 31)) {
    2eca:	f1b4 4f00 	cmp.w	r4, #2147483648	; 0x80000000
    2ece:	d80f      	bhi.n	2ef0 <mpu_configure_regions+0x6c>
	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    2ed0:	3c01      	subs	r4, #1
    2ed2:	fab4 f484 	clz	r4, r4
    2ed6:	f1c4 041f 	rsb	r4, r4, #31
    2eda:	0064      	lsls	r4, r4, #1
	if (index > (get_num_regions() - 1U)) {
    2edc:	2d07      	cmp	r5, #7
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    2ede:	ea4c 0404 	orr.w	r4, ip, r4
    2ee2:	d907      	bls.n	2ef4 <mpu_configure_regions+0x70>
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    2ee4:	480e      	ldr	r0, [pc, #56]	; (2f20 <mpu_configure_regions+0x9c>)
    2ee6:	462a      	mov	r2, r5
    2ee8:	2145      	movs	r1, #69	; 0x45
    2eea:	e7dc      	b.n	2ea6 <mpu_configure_regions+0x22>
		return REGION_32B;
    2eec:	2408      	movs	r4, #8
    2eee:	e7f5      	b.n	2edc <mpu_configure_regions+0x58>
		return REGION_4G;
    2ef0:	243e      	movs	r4, #62	; 0x3e
    2ef2:	e7f3      	b.n	2edc <mpu_configure_regions+0x58>
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2ef4:	f026 061f 	bic.w	r6, r6, #31
				| MPU_RBAR_VALID_Msk | index;
    2ef8:	432e      	orrs	r6, r5
    2efa:	f046 0610 	orr.w	r6, r6, #16
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2efe:	f044 0401 	orr.w	r4, r4, #1
    2f02:	f8c7 5098 	str.w	r5, [r7, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2f06:	f8c7 609c 	str.w	r6, [r7, #156]	; 0x9c
		reg_index++;
    2f0a:	3501      	adds	r5, #1
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2f0c:	f8c7 40a0 	str.w	r4, [r7, #160]	; 0xa0
	for (i = 0; i < regions_num; i++) {
    2f10:	3201      	adds	r2, #1
    2f12:	300c      	adds	r0, #12
    2f14:	e7ba      	b.n	2e8c <mpu_configure_regions+0x8>
    2f16:	bf00      	nop
    2f18:	e000ed00 	.word	0xe000ed00
    2f1c:	0000990c 	.word	0x0000990c
    2f20:	00009934 	.word	0x00009934

00002f24 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    2f24:	4b04      	ldr	r3, [pc, #16]	; (2f38 <arm_core_mpu_enable+0x14>)
    2f26:	2205      	movs	r2, #5
    2f28:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
  __ASM volatile ("dsb 0xF":::"memory");
    2f2c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2f30:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    2f34:	4770      	bx	lr
    2f36:	bf00      	nop
    2f38:	e000ed00 	.word	0xe000ed00

00002f3c <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    2f3c:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    2f40:	4b02      	ldr	r3, [pc, #8]	; (2f4c <arm_core_mpu_disable+0x10>)
    2f42:	2200      	movs	r2, #0
    2f44:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
}
    2f48:	4770      	bx	lr
    2f4a:	bf00      	nop
    2f4c:	e000ed00 	.word	0xe000ed00

00002f50 <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    2f50:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    2f52:	4c03      	ldr	r4, [pc, #12]	; (2f60 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    2f54:	2301      	movs	r3, #1
    2f56:	7822      	ldrb	r2, [r4, #0]
    2f58:	f7ff ff94 	bl	2e84 <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    2f5c:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    2f5e:	bd10      	pop	{r4, pc}
    2f60:	20003119 	.word	0x20003119

00002f64 <z_arm_mpu_init>:
 */
int z_arm_mpu_init(void)
{
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    2f64:	4914      	ldr	r1, [pc, #80]	; (2fb8 <z_arm_mpu_init+0x54>)
    2f66:	6808      	ldr	r0, [r1, #0]
    2f68:	2808      	cmp	r0, #8
{
    2f6a:	b510      	push	{r4, lr}
	if (mpu_config.num_regions > get_num_regions()) {
    2f6c:	d821      	bhi.n	2fb2 <z_arm_mpu_init+0x4e>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    2f6e:	f7ff ffe5 	bl	2f3c <arm_core_mpu_disable>
    2f72:	4c12      	ldr	r4, [pc, #72]	; (2fbc <z_arm_mpu_init+0x58>)
    2f74:	6849      	ldr	r1, [r1, #4]

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2f76:	2200      	movs	r2, #0
    2f78:	4290      	cmp	r0, r2
    2f7a:	f101 010c 	add.w	r1, r1, #12
    2f7e:	d105      	bne.n	2f8c <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    2f80:	4b0f      	ldr	r3, [pc, #60]	; (2fc0 <z_arm_mpu_init+0x5c>)
    2f82:	7018      	strb	r0, [r3, #0]


	arm_core_mpu_enable();
    2f84:	f7ff ffce 	bl	2f24 <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    2f88:	2000      	movs	r0, #0
}
    2f8a:	bd10      	pop	{r4, pc}
    2f8c:	f8c4 2098 	str.w	r2, [r4, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2f90:	f851 3c0c 	ldr.w	r3, [r1, #-12]
    2f94:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    2f98:	4313      	orrs	r3, r2
    2f9a:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2f9e:	f8c4 309c 	str.w	r3, [r4, #156]	; 0x9c
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2fa2:	f851 3c04 	ldr.w	r3, [r1, #-4]
    2fa6:	f043 0301 	orr.w	r3, r3, #1
    2faa:	f8c4 30a0 	str.w	r3, [r4, #160]	; 0xa0
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2fae:	3201      	adds	r2, #1
    2fb0:	e7e2      	b.n	2f78 <z_arm_mpu_init+0x14>
		return -1;
    2fb2:	f04f 30ff 	mov.w	r0, #4294967295
    2fb6:	e7e8      	b.n	2f8a <z_arm_mpu_init+0x26>
    2fb8:	00008a3c 	.word	0x00008a3c
    2fbc:	e000ed00 	.word	0xe000ed00
    2fc0:	20003119 	.word	0x20003119

00002fc4 <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
    2fc4:	4b01      	ldr	r3, [pc, #4]	; (2fcc <__stdout_hook_install+0x8>)
    2fc6:	6018      	str	r0, [r3, #0]
}
    2fc8:	4770      	bx	lr
    2fca:	bf00      	nop
    2fcc:	20000028 	.word	0x20000028

00002fd0 <nordicsemi_nrf52_init>:
	__asm__ volatile(
    2fd0:	f04f 0320 	mov.w	r3, #32
    2fd4:	f3ef 8211 	mrs	r2, BASEPRI
    2fd8:	f383 8812 	msr	BASEPRI_MAX, r3
    2fdc:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    2fe0:	4906      	ldr	r1, [pc, #24]	; (2ffc <nordicsemi_nrf52_init+0x2c>)
    2fe2:	2301      	movs	r3, #1
    2fe4:	f8c1 3540 	str.w	r3, [r1, #1344]	; 0x540
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    2fe8:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    2fec:	f8c1 3578 	str.w	r3, [r1, #1400]	; 0x578
	__asm__ volatile(
    2ff0:	f382 8811 	msr	BASEPRI, r2
    2ff4:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    2ff8:	2000      	movs	r0, #0
    2ffa:	4770      	bx	lr
    2ffc:	4001e000 	.word	0x4001e000

00003000 <sys_arch_reboot>:
    *p_gpregret = val;
    3000:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3004:	b2c0      	uxtb	r0, r0
    3006:	f8c3 051c 	str.w	r0, [r3, #1308]	; 0x51c
  __ASM volatile ("dsb 0xF":::"memory");
    300a:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    300e:	4905      	ldr	r1, [pc, #20]	; (3024 <sys_arch_reboot+0x24>)
    3010:	4b05      	ldr	r3, [pc, #20]	; (3028 <sys_arch_reboot+0x28>)
    3012:	68ca      	ldr	r2, [r1, #12]
    3014:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    3018:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    301a:	60cb      	str	r3, [r1, #12]
    301c:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    3020:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    3022:	e7fd      	b.n	3020 <sys_arch_reboot+0x20>
    3024:	e000ed00 	.word	0xe000ed00
    3028:	05fa0004 	.word	0x05fa0004

0000302c <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    302c:	b120      	cbz	r0, 3038 <arch_busy_wait+0xc>
    };

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    302e:	4b03      	ldr	r3, [pc, #12]	; (303c <arch_busy_wait+0x10>)
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    3030:	0180      	lsls	r0, r0, #6
    3032:	f043 0301 	orr.w	r3, r3, #1
    3036:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    3038:	4770      	bx	lr
    303a:	bf00      	nop
    303c:	00008990 	.word	0x00008990

00003040 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    3040:	4b08      	ldr	r3, [pc, #32]	; (3064 <onoff_stop+0x24>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    3042:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    3044:	1ac3      	subs	r3, r0, r3
{
    3046:	460d      	mov	r5, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    3048:	4907      	ldr	r1, [pc, #28]	; (3068 <onoff_stop+0x28>)
	size_t offset = (size_t)(mgr - data->mgr);
    304a:	109b      	asrs	r3, r3, #2
{
    304c:	4604      	mov	r4, r0
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    304e:	4359      	muls	r1, r3
    3050:	4806      	ldr	r0, [pc, #24]	; (306c <onoff_stop+0x2c>)
    3052:	2240      	movs	r2, #64	; 0x40
    3054:	f003 fa7d 	bl	6552 <stop>
	notify(mgr, res);
    3058:	462b      	mov	r3, r5
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    305a:	4601      	mov	r1, r0
	notify(mgr, res);
    305c:	4620      	mov	r0, r4
}
    305e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    3062:	4718      	bx	r3
    3064:	20001254 	.word	0x20001254
    3068:	b6db6db7 	.word	0xb6db6db7
    306c:	00008764 	.word	0x00008764

00003070 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    3070:	b573      	push	{r0, r1, r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    3072:	4c0c      	ldr	r4, [pc, #48]	; (30a4 <onoff_start+0x34>)
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    3074:	4a0c      	ldr	r2, [pc, #48]	; (30a8 <onoff_start+0x38>)
    3076:	2340      	movs	r3, #64	; 0x40
	size_t offset = (size_t)(mgr - data->mgr);
    3078:	1b04      	subs	r4, r0, r4
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    307a:	9300      	str	r3, [sp, #0]
{
    307c:	460d      	mov	r5, r1
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    307e:	460b      	mov	r3, r1
    3080:	490a      	ldr	r1, [pc, #40]	; (30ac <onoff_start+0x3c>)
	size_t offset = (size_t)(mgr - data->mgr);
    3082:	10a4      	asrs	r4, r4, #2
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    3084:	4361      	muls	r1, r4
{
    3086:	4606      	mov	r6, r0
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    3088:	4809      	ldr	r0, [pc, #36]	; (30b0 <onoff_start+0x40>)
    308a:	f003 fa8f 	bl	65ac <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    308e:	1e01      	subs	r1, r0, #0
    3090:	da05      	bge.n	309e <onoff_start+0x2e>
		notify(mgr, err);
    3092:	4630      	mov	r0, r6
    3094:	462b      	mov	r3, r5
	}
}
    3096:	b002      	add	sp, #8
    3098:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		notify(mgr, err);
    309c:	4718      	bx	r3
}
    309e:	b002      	add	sp, #8
    30a0:	bd70      	pop	{r4, r5, r6, pc}
    30a2:	bf00      	nop
    30a4:	20001254 	.word	0x20001254
    30a8:	00006621 	.word	0x00006621
    30ac:	b6db6db7 	.word	0xb6db6db7
    30b0:	00008764 	.word	0x00008764

000030b4 <clk_init>:
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    30b4:	2200      	movs	r2, #0
{
    30b6:	b570      	push	{r4, r5, r6, lr}
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    30b8:	2101      	movs	r1, #1
{
    30ba:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    30bc:	4610      	mov	r0, r2
    30be:	f7ff fbdb 	bl	2878 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);

	nrfx_err = nrfx_clock_init(clock_event_handler);
    30c2:	480f      	ldr	r0, [pc, #60]	; (3100 <clk_init+0x4c>)
    30c4:	f001 fd52 	bl	4b6c <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    30c8:	4b0e      	ldr	r3, [pc, #56]	; (3104 <clk_init+0x50>)
    30ca:	4298      	cmp	r0, r3
    30cc:	d115      	bne.n	30fa <clk_init+0x46>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    30ce:	f005 fa7f 	bl	85d0 <nrfx_clock_enable>
	struct nrf_clock_control_data *data = dev->data;
    30d2:	6926      	ldr	r6, [r4, #16]
	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);

		err = onoff_manager_init(get_onoff_manager(dev, i),
    30d4:	490c      	ldr	r1, [pc, #48]	; (3108 <clk_init+0x54>)
    30d6:	4630      	mov	r0, r6
    30d8:	f002 fe54 	bl	5d84 <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    30dc:	2800      	cmp	r0, #0
    30de:	db0b      	blt.n	30f8 <clk_init+0x44>
	struct nrf_clock_control_data *data = dev->data;
    30e0:	6924      	ldr	r4, [r4, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    30e2:	4909      	ldr	r1, [pc, #36]	; (3108 <clk_init+0x54>)
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    30e4:	2501      	movs	r5, #1
    30e6:	6435      	str	r5, [r6, #64]	; 0x40
		err = onoff_manager_init(get_onoff_manager(dev, i),
    30e8:	f104 001c 	add.w	r0, r4, #28
    30ec:	f002 fe4a 	bl	5d84 <onoff_manager_init>
		if (err < 0) {
    30f0:	2800      	cmp	r0, #0
    30f2:	db01      	blt.n	30f8 <clk_init+0x44>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    30f4:	64e5      	str	r5, [r4, #76]	; 0x4c
	}

	return 0;
    30f6:	2000      	movs	r0, #0
}
    30f8:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    30fa:	f06f 0004 	mvn.w	r0, #4
    30fe:	e7fb      	b.n	30f8 <clk_init+0x44>
    3100:	00003141 	.word	0x00003141
    3104:	0bad0000 	.word	0x0bad0000
    3108:	00008a8c 	.word	0x00008a8c

0000310c <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    310c:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    310e:	230c      	movs	r3, #12
    3110:	4809      	ldr	r0, [pc, #36]	; (3138 <clkstarted_handle.constprop.0+0x2c>)
    3112:	434b      	muls	r3, r1
static void clkstarted_handle(const struct device *dev,
    3114:	b570      	push	{r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    3116:	18c4      	adds	r4, r0, r3
	void *user_data = sub_data->user_data;
    3118:	e9d4 560e 	ldrd	r5, r6, [r4, #56]	; 0x38
	sub_data->cb = NULL;
    311c:	2200      	movs	r2, #0
	set_on_state(&sub_data->flags);
    311e:	3340      	adds	r3, #64	; 0x40
	sub_data->cb = NULL;
    3120:	63a2      	str	r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    3122:	4418      	add	r0, r3
    3124:	f003 fa02 	bl	652c <set_on_state>
	if (callback) {
    3128:	b12d      	cbz	r5, 3136 <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    312a:	4632      	mov	r2, r6
    312c:	462b      	mov	r3, r5
    312e:	4803      	ldr	r0, [pc, #12]	; (313c <clkstarted_handle.constprop.0+0x30>)
}
    3130:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    3134:	4718      	bx	r3
}
    3136:	bd70      	pop	{r4, r5, r6, pc}
    3138:	20001254 	.word	0x20001254
    313c:	00008764 	.word	0x00008764

00003140 <clock_event_handler>:
	switch (event) {
    3140:	b110      	cbz	r0, 3148 <clock_event_handler+0x8>
    3142:	2801      	cmp	r0, #1
    3144:	d004      	beq.n	3150 <clock_event_handler+0x10>
    3146:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    3148:	4b03      	ldr	r3, [pc, #12]	; (3158 <clock_event_handler+0x18>)
    314a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    314c:	075b      	lsls	r3, r3, #29
    314e:	d101      	bne.n	3154 <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    3150:	f7ff bfdc 	b.w	310c <clkstarted_handle.constprop.0>
}
    3154:	4770      	bx	lr
    3156:	bf00      	nop
    3158:	20001254 	.word	0x20001254

0000315c <generic_hfclk_start>:
{
    315c:	b508      	push	{r3, lr}
	__asm__ volatile(
    315e:	f04f 0320 	mov.w	r3, #32
    3162:	f3ef 8111 	mrs	r1, BASEPRI
    3166:	f383 8812 	msr	BASEPRI_MAX, r3
    316a:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    316e:	4a12      	ldr	r2, [pc, #72]	; (31b8 <generic_hfclk_start+0x5c>)
    3170:	6813      	ldr	r3, [r2, #0]
    3172:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
    3176:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
    317a:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    317c:	d00c      	beq.n	3198 <generic_hfclk_start+0x3c>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    317e:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    3182:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    3186:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    318a:	f013 0301 	ands.w	r3, r3, #1
    318e:	d003      	beq.n	3198 <generic_hfclk_start+0x3c>
			set_on_state(get_hf_flags());
    3190:	480a      	ldr	r0, [pc, #40]	; (31bc <generic_hfclk_start+0x60>)
    3192:	f003 f9cb 	bl	652c <set_on_state>
			already_started = true;
    3196:	2301      	movs	r3, #1
	__asm__ volatile(
    3198:	f381 8811 	msr	BASEPRI, r1
    319c:	f3bf 8f6f 	isb	sy
	if (already_started) {
    31a0:	b123      	cbz	r3, 31ac <generic_hfclk_start+0x50>
}
    31a2:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    31a6:	2000      	movs	r0, #0
    31a8:	f7ff bfb0 	b.w	310c <clkstarted_handle.constprop.0>
}
    31ac:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    31b0:	2001      	movs	r0, #1
    31b2:	f001 bceb 	b.w	4b8c <nrfx_clock_start>
    31b6:	bf00      	nop
    31b8:	200012a4 	.word	0x200012a4
    31bc:	20001294 	.word	0x20001294

000031c0 <lfclk_start>:
{
    31c0:	b510      	push	{r4, lr}
	if (!once) {
    31c2:	4c07      	ldr	r4, [pc, #28]	; (31e0 <lfclk_start+0x20>)
    31c4:	7823      	ldrb	r3, [r4, #0]
    31c6:	b92b      	cbnz	r3, 31d4 <lfclk_start+0x14>
    31c8:	f44f 70a5 	mov.w	r0, #330	; 0x14a
    31cc:	f005 fa9a 	bl	8704 <z_impl_k_busy_wait>
		once = true;
    31d0:	2301      	movs	r3, #1
    31d2:	7023      	strb	r3, [r4, #0]
}
    31d4:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    31d8:	2000      	movs	r0, #0
    31da:	f001 bcd7 	b.w	4b8c <nrfx_clock_start>
    31de:	bf00      	nop
    31e0:	2000311a 	.word	0x2000311a

000031e4 <generic_hfclk_stop>:
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    31e4:	4b09      	ldr	r3, [pc, #36]	; (320c <generic_hfclk_stop+0x28>)
    31e6:	f3bf 8f5b 	dmb	ish
    31ea:	e853 2f00 	ldrex	r2, [r3]
    31ee:	f022 0102 	bic.w	r1, r2, #2
    31f2:	e843 1000 	strex	r0, r1, [r3]
    31f6:	2800      	cmp	r0, #0
    31f8:	d1f7      	bne.n	31ea <generic_hfclk_stop+0x6>
    31fa:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    31fe:	07d3      	lsls	r3, r2, #31
    3200:	d402      	bmi.n	3208 <generic_hfclk_stop+0x24>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    3202:	2001      	movs	r0, #1
    3204:	f005 b9f1 	b.w	85ea <nrfx_clock_stop>
}
    3208:	4770      	bx	lr
    320a:	bf00      	nop
    320c:	200012a4 	.word	0x200012a4

00003210 <z_nrf_clock_control_lf_on>:
{
    3210:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    3214:	4937      	ldr	r1, [pc, #220]	; (32f4 <z_nrf_clock_control_lf_on+0xe4>)
    3216:	f3bf 8f5b 	dmb	ish
    321a:	4607      	mov	r7, r0
    321c:	2201      	movs	r2, #1
    321e:	e851 3f00 	ldrex	r3, [r1]
    3222:	e841 2000 	strex	r0, r2, [r1]
    3226:	2800      	cmp	r0, #0
    3228:	d1f9      	bne.n	321e <z_nrf_clock_control_lf_on+0xe>
    322a:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    322e:	b933      	cbnz	r3, 323e <z_nrf_clock_control_lf_on+0x2e>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    3230:	4931      	ldr	r1, [pc, #196]	; (32f8 <z_nrf_clock_control_lf_on+0xe8>)
		err = onoff_request(mgr, &cli);
    3232:	4832      	ldr	r0, [pc, #200]	; (32fc <z_nrf_clock_control_lf_on+0xec>)
    3234:	604b      	str	r3, [r1, #4]
    3236:	60cb      	str	r3, [r1, #12]
    3238:	608a      	str	r2, [r1, #8]
    323a:	f002 fdb6 	bl	5daa <onoff_request>
	switch (start_mode) {
    323e:	1e7b      	subs	r3, r7, #1
    3240:	2b01      	cmp	r3, #1
    3242:	d831      	bhi.n	32a8 <z_nrf_clock_control_lf_on+0x98>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    3244:	2f01      	cmp	r7, #1
    3246:	d107      	bne.n	3258 <z_nrf_clock_control_lf_on+0x48>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    3248:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    324c:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
    3250:	f003 0303 	and.w	r3, r3, #3
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    3254:	2b01      	cmp	r3, #1
    3256:	d027      	beq.n	32a8 <z_nrf_clock_control_lf_on+0x98>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    3258:	f005 fa4e 	bl	86f8 <k_is_in_isr>
    325c:	4604      	mov	r4, r0
    325e:	b918      	cbnz	r0, 3268 <z_nrf_clock_control_lf_on+0x58>
	return !z_sys_post_kernel;
    3260:	4b27      	ldr	r3, [pc, #156]	; (3300 <z_nrf_clock_control_lf_on+0xf0>)
	int key = isr_mode ? irq_lock() : 0;
    3262:	781b      	ldrb	r3, [r3, #0]
    3264:	2b00      	cmp	r3, #0
    3266:	d13d      	bne.n	32e4 <z_nrf_clock_control_lf_on+0xd4>
	__asm__ volatile(
    3268:	f04f 0320 	mov.w	r3, #32
    326c:	f3ef 8611 	mrs	r6, BASEPRI
    3270:	f383 8812 	msr	BASEPRI_MAX, r3
    3274:	f3bf 8f6f 	isb	sy
    3278:	2401      	movs	r4, #1
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    327a:	f8df 9088 	ldr.w	r9, [pc, #136]	; 3304 <z_nrf_clock_control_lf_on+0xf4>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    327e:	f04f 4580 	mov.w	r5, #1073741824	; 0x40000000
    p_reg->LFCLKSRC = (uint32_t)(source);
    3282:	f04f 0801 	mov.w	r8, #1
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    3286:	f8d5 3418 	ldr.w	r3, [r5, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    328a:	f8d5 2418 	ldr.w	r2, [r5, #1048]	; 0x418
    328e:	03d2      	lsls	r2, r2, #15
    3290:	d50c      	bpl.n	32ac <z_nrf_clock_control_lf_on+0x9c>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    3292:	f003 0303 	and.w	r3, r3, #3
	while (!(nrfx_clock_is_running(d, (void *)&type)
    3296:	2b01      	cmp	r3, #1
    3298:	d001      	beq.n	329e <z_nrf_clock_control_lf_on+0x8e>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    329a:	2f01      	cmp	r7, #1
    329c:	d106      	bne.n	32ac <z_nrf_clock_control_lf_on+0x9c>
	if (isr_mode) {
    329e:	b1dc      	cbz	r4, 32d8 <z_nrf_clock_control_lf_on+0xc8>
	__asm__ volatile(
    32a0:	f386 8811 	msr	BASEPRI, r6
    32a4:	f3bf 8f6f 	isb	sy
}
    32a8:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 *
 * @param key Interrupt locking key obtained from irq_lock().
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    32ac:	4630      	mov	r0, r6
    32ae:	f7ff fa8d 	bl	27cc <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    32b2:	f8d5 3518 	ldr.w	r3, [r5, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    32b6:	2b00      	cmp	r3, #0
    32b8:	d1e5      	bne.n	3286 <z_nrf_clock_control_lf_on+0x76>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    32ba:	f8d5 2104 	ldr.w	r2, [r5, #260]	; 0x104
		    && nrf_clock_event_check(NRF_CLOCK,
    32be:	2a00      	cmp	r2, #0
    32c0:	d0e1      	beq.n	3286 <z_nrf_clock_control_lf_on+0x76>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    32c2:	f8c5 3104 	str.w	r3, [r5, #260]	; 0x104
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    32c6:	f8d5 3104 	ldr.w	r3, [r5, #260]	; 0x104
    p_reg->LFCLKSRC = (uint32_t)(source);
    32ca:	f8c5 8518 	str.w	r8, [r5, #1304]	; 0x518
    32ce:	f8c9 8180 	str.w	r8, [r9, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    32d2:	f8c5 8008 	str.w	r8, [r5, #8]
}
    32d6:	e7d6      	b.n	3286 <z_nrf_clock_control_lf_on+0x76>
    p_reg->INTENSET = mask;
    32d8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    32dc:	2202      	movs	r2, #2
    32de:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    32e2:	e7e1      	b.n	32a8 <z_nrf_clock_control_lf_on+0x98>
    p_reg->INTENCLR = mask;
    32e4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    32e8:	2202      	movs	r2, #2
    32ea:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
	int key = isr_mode ? irq_lock() : 0;
    32ee:	4606      	mov	r6, r0
}
    32f0:	e7c3      	b.n	327a <z_nrf_clock_control_lf_on+0x6a>
    32f2:	bf00      	nop
    32f4:	200012a8 	.word	0x200012a8
    32f8:	20001244 	.word	0x20001244
    32fc:	20001270 	.word	0x20001270
    3300:	2000354c 	.word	0x2000354c
    3304:	e000e100 	.word	0xe000e100

00003308 <rtt_console_init>:

	return character;
}

static int rtt_console_init(const struct device *d)
{
    3308:	b510      	push	{r4, lr}
	ARG_UNUSED(d);

	__printk_hook_install(rtt_console_out);
    330a:	4c04      	ldr	r4, [pc, #16]	; (331c <rtt_console_init+0x14>)
    330c:	4620      	mov	r0, r4
    330e:	f7fe f9a7 	bl	1660 <__printk_hook_install>
	__stdout_hook_install(rtt_console_out);
    3312:	4620      	mov	r0, r4
    3314:	f7ff fe56 	bl	2fc4 <__stdout_hook_install>

	return 0;
}
    3318:	2000      	movs	r0, #0
    331a:	bd10      	pop	{r4, pc}
    331c:	00003321 	.word	0x00003321

00003320 <rtt_console_out>:
{
    3320:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    3322:	4e10      	ldr	r6, [pc, #64]	; (3364 <rtt_console_out+0x44>)
	char c = (char)character;
    3324:	f88d 0007 	strb.w	r0, [sp, #7]
{
    3328:	4604      	mov	r4, r0
	char c = (char)character;
    332a:	2503      	movs	r5, #3
		SEGGER_RTT_LOCK();
    332c:	f3ef 8711 	mrs	r7, BASEPRI
    3330:	f04f 0120 	mov.w	r1, #32
    3334:	f381 8811 	msr	BASEPRI, r1
		cnt = SEGGER_RTT_WriteNoLock(0, &c, 1);
    3338:	2201      	movs	r2, #1
    333a:	f10d 0107 	add.w	r1, sp, #7
    333e:	2000      	movs	r0, #0
    3340:	f002 f846 	bl	53d0 <SEGGER_RTT_WriteNoLock>
		SEGGER_RTT_UNLOCK();
    3344:	f387 8811 	msr	BASEPRI, r7
		if (cnt) {
    3348:	b120      	cbz	r0, 3354 <rtt_console_out+0x34>
			host_present = true;
    334a:	2301      	movs	r3, #1
    334c:	7033      	strb	r3, [r6, #0]
}
    334e:	4620      	mov	r0, r4
    3350:	b003      	add	sp, #12
    3352:	bdf0      	pop	{r4, r5, r6, r7, pc}
		} else if (host_present) {
    3354:	7833      	ldrb	r3, [r6, #0]
    3356:	2b00      	cmp	r3, #0
    3358:	d0f9      	beq.n	334e <rtt_console_out+0x2e>
			if (max_cnt) {
    335a:	3d01      	subs	r5, #1
    335c:	d1e6      	bne.n	332c <rtt_console_out+0xc>
				host_present = false;
    335e:	7035      	strb	r5, [r6, #0]
    3360:	e7f5      	b.n	334e <rtt_console_out+0x2e>
    3362:	bf00      	nop
    3364:	2000311b 	.word	0x2000311b

00003368 <gpio_nrfx_pin_interrupt_configure>:

static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
					     gpio_pin_t pin,
					     enum gpio_int_mode mode,
					     enum gpio_int_trig trig)
{
    3368:	b530      	push	{r4, r5, lr}
	return port->config;
    336a:	6840      	ldr	r0, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    336c:	7b04      	ldrb	r4, [r0, #12]
    336e:	f001 051f 	and.w	r5, r1, #31
	nrfx_err_t err;

	if (mode == GPIO_INT_MODE_DISABLED) {
    3372:	f5b2 1f00 	cmp.w	r2, #2097152	; 0x200000
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    3376:	ea45 1544 	orr.w	r5, r5, r4, lsl #5
{
    337a:	b085      	sub	sp, #20
    337c:	f04f 0400 	mov.w	r4, #0
	if (mode == GPIO_INT_MODE_DISABLED) {
    3380:	d104      	bne.n	338c <gpio_nrfx_pin_interrupt_configure+0x24>
		nrfx_gpiote_trigger_disable(abs_pin);
    3382:	4628      	mov	r0, r5
    3384:	f001 febc 	bl	5100 <nrfx_gpiote_trigger_disable>
		return -EIO;
	}

	nrfx_gpiote_trigger_enable(abs_pin, true);

	return 0;
    3388:	2000      	movs	r0, #0
    338a:	e02e      	b.n	33ea <gpio_nrfx_pin_interrupt_configure+0x82>
	if (mode == GPIO_INT_MODE_LEVEL) {
    338c:	f5b2 0f80 	cmp.w	r2, #4194304	; 0x400000
	nrfx_gpiote_trigger_config_t trigger_config = {
    3390:	e9cd 4402 	strd	r4, r4, [sp, #8]
	if (mode == GPIO_INT_MODE_LEVEL) {
    3394:	d12b      	bne.n	33ee <gpio_nrfx_pin_interrupt_configure+0x86>
		return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
    3396:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    339a:	bf0c      	ite	eq
    339c:	2304      	moveq	r3, #4
    339e:	2305      	movne	r3, #5
	nrfx_gpiote_trigger_config_t trigger_config = {
    33a0:	f88d 3008 	strb.w	r3, [sp, #8]
	if (!(BIT(pin) & get_port_cfg(port)->edge_sense) &&
    33a4:	6883      	ldr	r3, [r0, #8]
    33a6:	fa23 f101 	lsr.w	r1, r3, r1
    33aa:	07c9      	lsls	r1, r1, #31
    33ac:	d42b      	bmi.n	3406 <gpio_nrfx_pin_interrupt_configure+0x9e>
    33ae:	f1b2 7fa0 	cmp.w	r2, #20971520	; 0x1400000
    33b2:	d128      	bne.n	3406 <gpio_nrfx_pin_interrupt_configure+0x9e>
}

NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;
    33b4:	f005 031f 	and.w	r3, r5, #31
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    33b8:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    33bc:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    33c0:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    33c4:	07db      	lsls	r3, r3, #31
    33c6:	d41e      	bmi.n	3406 <gpio_nrfx_pin_interrupt_configure+0x9e>
		err = nrfx_gpiote_channel_get(abs_pin, &ch);
    33c8:	f10d 0407 	add.w	r4, sp, #7
    33cc:	4621      	mov	r1, r4
    33ce:	4628      	mov	r0, r5
    33d0:	f001 fdfe 	bl	4fd0 <nrfx_gpiote_channel_get>
		if (err == NRFX_ERROR_INVALID_PARAM) {
    33d4:	4b14      	ldr	r3, [pc, #80]	; (3428 <gpio_nrfx_pin_interrupt_configure+0xc0>)
    33d6:	4298      	cmp	r0, r3
    33d8:	d114      	bne.n	3404 <gpio_nrfx_pin_interrupt_configure+0x9c>
			err = nrfx_gpiote_channel_alloc(&ch);
    33da:	4620      	mov	r0, r4
    33dc:	f001 fe46 	bl	506c <nrfx_gpiote_channel_alloc>
			if (err != NRFX_SUCCESS) {
    33e0:	4b12      	ldr	r3, [pc, #72]	; (342c <gpio_nrfx_pin_interrupt_configure+0xc4>)
    33e2:	4298      	cmp	r0, r3
    33e4:	d00e      	beq.n	3404 <gpio_nrfx_pin_interrupt_configure+0x9c>
				return -ENOMEM;
    33e6:	f06f 000b 	mvn.w	r0, #11
}
    33ea:	b005      	add	sp, #20
    33ec:	bd30      	pop	{r4, r5, pc}
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    33ee:	f1b3 6fc0 	cmp.w	r3, #100663296	; 0x6000000
    33f2:	d005      	beq.n	3400 <gpio_nrfx_pin_interrupt_configure+0x98>
    33f4:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    33f8:	bf0c      	ite	eq
    33fa:	2302      	moveq	r3, #2
    33fc:	2301      	movne	r3, #1
    33fe:	e7cf      	b.n	33a0 <gpio_nrfx_pin_interrupt_configure+0x38>
    3400:	2303      	movs	r3, #3
    3402:	e7cd      	b.n	33a0 <gpio_nrfx_pin_interrupt_configure+0x38>
		trigger_config.p_in_channel = &ch;
    3404:	9403      	str	r4, [sp, #12]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    3406:	2300      	movs	r3, #0
    3408:	4619      	mov	r1, r3
    340a:	aa02      	add	r2, sp, #8
    340c:	4628      	mov	r0, r5
    340e:	f001 fcb7 	bl	4d80 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    3412:	4b06      	ldr	r3, [pc, #24]	; (342c <gpio_nrfx_pin_interrupt_configure+0xc4>)
    3414:	4298      	cmp	r0, r3
    3416:	d104      	bne.n	3422 <gpio_nrfx_pin_interrupt_configure+0xba>
	nrfx_gpiote_trigger_enable(abs_pin, true);
    3418:	2101      	movs	r1, #1
    341a:	4628      	mov	r0, r5
    341c:	f001 fe2c 	bl	5078 <nrfx_gpiote_trigger_enable>
    3420:	e7b2      	b.n	3388 <gpio_nrfx_pin_interrupt_configure+0x20>
		return -EIO;
    3422:	f06f 0004 	mvn.w	r0, #4
    3426:	e7e0      	b.n	33ea <gpio_nrfx_pin_interrupt_configure+0x82>
    3428:	0bad0004 	.word	0x0bad0004
    342c:	0bad0000 	.word	0x0bad0000

00003430 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    3430:	b510      	push	{r4, lr}
	nrfx_err_t err;

	if (nrfx_gpiote_is_init()) {
    3432:	f001 fe0b 	bl	504c <nrfx_gpiote_is_init>
    3436:	4604      	mov	r4, r0
    3438:	b968      	cbnz	r0, 3456 <gpio_nrfx_init+0x26>
		return 0;
	}

	err = nrfx_gpiote_init(0/*not used*/);
    343a:	f001 fddf 	bl	4ffc <nrfx_gpiote_init>
	if (err != NRFX_SUCCESS) {
    343e:	4b08      	ldr	r3, [pc, #32]	; (3460 <gpio_nrfx_init+0x30>)
    3440:	4298      	cmp	r0, r3
    3442:	d10a      	bne.n	345a <gpio_nrfx_init+0x2a>
		return -EIO;
	}

	nrfx_gpiote_global_callback_set(nrfx_gpio_handler, NULL);
    3444:	4807      	ldr	r0, [pc, #28]	; (3464 <gpio_nrfx_init+0x34>)
    3446:	4621      	mov	r1, r4
    3448:	f001 fdbc 	bl	4fc4 <nrfx_gpiote_global_callback_set>

	IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    344c:	4622      	mov	r2, r4
    344e:	2105      	movs	r1, #5
    3450:	2006      	movs	r0, #6
    3452:	f7ff fa11 	bl	2878 <z_arm_irq_priority_set>
		return 0;
    3456:	2000      	movs	r0, #0
		    nrfx_isr, nrfx_gpiote_irq_handler, 0);

	return 0;
}
    3458:	bd10      	pop	{r4, pc}
		return -EIO;
    345a:	f06f 0004 	mvn.w	r0, #4
    345e:	e7fb      	b.n	3458 <gpio_nrfx_init+0x28>
    3460:	0bad0000 	.word	0x0bad0000
    3464:	00003469 	.word	0x00003469

00003468 <nrfx_gpio_handler>:
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    3468:	0943      	lsrs	r3, r0, #5
{
    346a:	b570      	push	{r4, r5, r6, lr}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    346c:	d110      	bne.n	3490 <nrfx_gpio_handler+0x28>
	return list->head;
    346e:	4b09      	ldr	r3, [pc, #36]	; (3494 <nrfx_gpio_handler+0x2c>)
    3470:	6859      	ldr	r1, [r3, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    3472:	b169      	cbz	r1, 3490 <nrfx_gpio_handler+0x28>
	gpio_fire_callbacks(list, port, BIT(pin));
    3474:	2501      	movs	r5, #1
	return node->next;
    3476:	680c      	ldr	r4, [r1, #0]
		if (cb->pin_mask & pins) {
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    3478:	4e07      	ldr	r6, [pc, #28]	; (3498 <nrfx_gpio_handler+0x30>)
    347a:	4085      	lsls	r5, r0
		if (cb->pin_mask & pins) {
    347c:	688a      	ldr	r2, [r1, #8]
    347e:	402a      	ands	r2, r5
    3480:	d002      	beq.n	3488 <nrfx_gpio_handler+0x20>
			cb->handler(port, cb, cb->pin_mask & pins);
    3482:	684b      	ldr	r3, [r1, #4]
    3484:	4630      	mov	r0, r6
    3486:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    3488:	b114      	cbz	r4, 3490 <nrfx_gpio_handler+0x28>
    348a:	4621      	mov	r1, r4
    348c:	6824      	ldr	r4, [r4, #0]
    348e:	e7f5      	b.n	347c <nrfx_gpio_handler+0x14>
}
    3490:	bd70      	pop	{r4, r5, r6, pc}
    3492:	bf00      	nop
    3494:	200012ac 	.word	0x200012ac
    3498:	0000877c 	.word	0x0000877c

0000349c <gpio_nrfx_pin_configure>:
{
    349c:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
	return port->config;
    34a0:	6847      	ldr	r7, [r0, #4]
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    34a2:	7b3b      	ldrb	r3, [r7, #12]
    34a4:	f001 051f 	and.w	r5, r1, #31
{
    34a8:	b085      	sub	sp, #20
    34aa:	460e      	mov	r6, r1
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    34ac:	ea45 1543 	orr.w	r5, r5, r3, lsl #5
	if (flags == GPIO_DISCONNECTED) {
    34b0:	4614      	mov	r4, r2
    34b2:	b9ca      	cbnz	r2, 34e8 <gpio_nrfx_pin_configure+0x4c>
	err = nrfx_gpiote_channel_get(pin, &ch);
    34b4:	a902      	add	r1, sp, #8
    34b6:	4628      	mov	r0, r5
    34b8:	f001 fd8a 	bl	4fd0 <nrfx_gpiote_channel_get>
    34bc:	4604      	mov	r4, r0
	err = nrfx_gpiote_pin_uninit(pin);
    34be:	4628      	mov	r0, r5
    34c0:	f001 fe46 	bl	5150 <nrfx_gpiote_pin_uninit>
	if (err != NRFX_SUCCESS) {
    34c4:	4b4a      	ldr	r3, [pc, #296]	; (35f0 <gpio_nrfx_pin_configure+0x154>)
    34c6:	4298      	cmp	r0, r3
    34c8:	d004      	beq.n	34d4 <gpio_nrfx_pin_configure+0x38>
		return -EIO;
    34ca:	f06f 0004 	mvn.w	r0, #4
}
    34ce:	b005      	add	sp, #20
    34d0:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
	if (free_ch) {
    34d4:	4284      	cmp	r4, r0
    34d6:	d105      	bne.n	34e4 <gpio_nrfx_pin_configure+0x48>
		err = nrfx_gpiote_channel_free(ch);
    34d8:	f89d 0008 	ldrb.w	r0, [sp, #8]
    34dc:	f001 fdc0 	bl	5060 <nrfx_gpiote_channel_free>
	return (err != NRFX_SUCCESS) ? -EIO : 0;
    34e0:	42a0      	cmp	r0, r4
    34e2:	d1f2      	bne.n	34ca <gpio_nrfx_pin_configure+0x2e>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    34e4:	2000      	movs	r0, #0
    34e6:	e7f2      	b.n	34ce <gpio_nrfx_pin_configure+0x32>
	nrfx_gpiote_trigger_config_t trigger_config = {
    34e8:	f04f 0900 	mov.w	r9, #0
	err = nrfx_gpiote_channel_get(pin, &ch);
    34ec:	f10d 0103 	add.w	r1, sp, #3
    34f0:	4630      	mov	r0, r6
	nrfx_gpiote_trigger_config_t trigger_config = {
    34f2:	e9cd 9902 	strd	r9, r9, [sp, #8]
	err = nrfx_gpiote_channel_get(pin, &ch);
    34f6:	f001 fd6b 	bl	4fd0 <nrfx_gpiote_channel_get>
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    34fa:	464b      	mov	r3, r9
	err = nrfx_gpiote_channel_get(pin, &ch);
    34fc:	4680      	mov	r8, r0
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    34fe:	aa02      	add	r2, sp, #8
    3500:	4649      	mov	r1, r9
    3502:	4628      	mov	r0, r5
    3504:	f001 fc3c 	bl	4d80 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    3508:	4b39      	ldr	r3, [pc, #228]	; (35f0 <gpio_nrfx_pin_configure+0x154>)
    350a:	4298      	cmp	r0, r3
    350c:	d002      	beq.n	3514 <gpio_nrfx_pin_configure+0x78>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    350e:	f06f 0015 	mvn.w	r0, #21
    3512:	e7dc      	b.n	34ce <gpio_nrfx_pin_configure+0x32>
	if (free_ch) {
    3514:	4580      	cmp	r8, r0
    3516:	d103      	bne.n	3520 <gpio_nrfx_pin_configure+0x84>
		err = nrfx_gpiote_channel_free(ch);
    3518:	f89d 0003 	ldrb.w	r0, [sp, #3]
    351c:	f001 fda0 	bl	5060 <nrfx_gpiote_channel_free>
	if (flags & GPIO_OUTPUT) {
    3520:	03a3      	lsls	r3, r4, #14
    3522:	d551      	bpl.n	35c8 <gpio_nrfx_pin_configure+0x12c>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    3524:	f240 6306 	movw	r3, #1542	; 0x606
    3528:	4023      	ands	r3, r4
    352a:	f240 2206 	movw	r2, #518	; 0x206
    352e:	4293      	cmp	r3, r2
    3530:	d03b      	beq.n	35aa <gpio_nrfx_pin_configure+0x10e>
    3532:	d80c      	bhi.n	354e <gpio_nrfx_pin_configure+0xb2>
    3534:	2b06      	cmp	r3, #6
    3536:	d015      	beq.n	3564 <gpio_nrfx_pin_configure+0xc8>
    3538:	d804      	bhi.n	3544 <gpio_nrfx_pin_configure+0xa8>
    353a:	b19b      	cbz	r3, 3564 <gpio_nrfx_pin_configure+0xc8>
    353c:	2b02      	cmp	r3, #2
    353e:	d1e6      	bne.n	350e <gpio_nrfx_pin_configure+0x72>
    3540:	2304      	movs	r3, #4
    3542:	e00f      	b.n	3564 <gpio_nrfx_pin_configure+0xc8>
    3544:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    3548:	d1e1      	bne.n	350e <gpio_nrfx_pin_configure+0x72>
		*drive = NRF_GPIO_PIN_H0S1;
    354a:	2301      	movs	r3, #1
    354c:	e00a      	b.n	3564 <gpio_nrfx_pin_configure+0xc8>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    354e:	f240 4202 	movw	r2, #1026	; 0x402
    3552:	4293      	cmp	r3, r2
    3554:	d02b      	beq.n	35ae <gpio_nrfx_pin_configure+0x112>
    3556:	f5b3 6fc0 	cmp.w	r3, #1536	; 0x600
    355a:	d02a      	beq.n	35b2 <gpio_nrfx_pin_configure+0x116>
    355c:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
    3560:	d1d5      	bne.n	350e <gpio_nrfx_pin_configure+0x72>
		*drive = NRF_GPIO_PIN_S0H1;
    3562:	2302      	movs	r3, #2
		nrfx_gpiote_output_config_t output_config = {
    3564:	f88d 3004 	strb.w	r3, [sp, #4]
				NRF_GPIO_PIN_INPUT_CONNECT :
    3568:	f484 3380 	eor.w	r3, r4, #65536	; 0x10000
    356c:	f3c3 4300 	ubfx	r3, r3, #16, #1
	if (flags & GPIO_PULL_UP) {
    3570:	06e0      	lsls	r0, r4, #27
		nrfx_gpiote_output_config_t output_config = {
    3572:	f88d 3005 	strb.w	r3, [sp, #5]
		return NRF_GPIO_PIN_PULLDOWN;
    3576:	bf54      	ite	pl
    3578:	f3c4 1340 	ubfxpl	r3, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    357c:	2303      	movmi	r3, #3
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    357e:	0321      	lsls	r1, r4, #12
		nrfx_gpiote_output_config_t output_config = {
    3580:	f88d 3006 	strb.w	r3, [sp, #6]
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    3584:	d517      	bpl.n	35b6 <gpio_nrfx_pin_configure+0x11a>
			nrf_gpio_port_out_set(cfg->port, BIT(pin));
    3586:	687b      	ldr	r3, [r7, #4]
    3588:	2101      	movs	r1, #1
    358a:	fa01 f606 	lsl.w	r6, r1, r6
    p_reg->OUTSET = set_mask;
    358e:	f8c3 6508 	str.w	r6, [r3, #1288]	; 0x508
		err = nrfx_gpiote_output_configure(abs_pin, &output_config, NULL);
    3592:	2200      	movs	r2, #0
    3594:	a901      	add	r1, sp, #4
    3596:	4628      	mov	r0, r5
    3598:	f001 fc9c 	bl	4ed4 <nrfx_gpiote_output_configure>
		return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    359c:	4b14      	ldr	r3, [pc, #80]	; (35f0 <gpio_nrfx_pin_configure+0x154>)
    359e:	4298      	cmp	r0, r3
    35a0:	bf14      	ite	ne
    35a2:	f06f 0015 	mvnne.w	r0, #21
    35a6:	2000      	moveq	r0, #0
    35a8:	e791      	b.n	34ce <gpio_nrfx_pin_configure+0x32>
		*drive = NRF_GPIO_PIN_H0D1;
    35aa:	2307      	movs	r3, #7
    35ac:	e7da      	b.n	3564 <gpio_nrfx_pin_configure+0xc8>
		*drive = NRF_GPIO_PIN_D0H1;
    35ae:	2305      	movs	r3, #5
    35b0:	e7d8      	b.n	3564 <gpio_nrfx_pin_configure+0xc8>
		*drive = NRF_GPIO_PIN_H0H1;
    35b2:	2303      	movs	r3, #3
    35b4:	e7d6      	b.n	3564 <gpio_nrfx_pin_configure+0xc8>
		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
    35b6:	0362      	lsls	r2, r4, #13
			nrf_gpio_port_out_clear(cfg->port, BIT(pin));
    35b8:	bf41      	itttt	mi
    35ba:	687b      	ldrmi	r3, [r7, #4]
    35bc:	2101      	movmi	r1, #1
    35be:	fa01 f606 	lslmi.w	r6, r1, r6
    p_reg->OUTCLR = clr_mask;
    35c2:	f8c3 650c 	strmi.w	r6, [r3, #1292]	; 0x50c
}
    35c6:	e7e4      	b.n	3592 <gpio_nrfx_pin_configure+0xf6>
	if (flags & GPIO_PULL_UP) {
    35c8:	06e3      	lsls	r3, r4, #27
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    35ca:	f04f 0300 	mov.w	r3, #0
		return NRF_GPIO_PIN_PULLUP;
    35ce:	bf54      	ite	pl
    35d0:	f3c4 1440 	ubfxpl	r4, r4, #5, #1
    35d4:	2403      	movmi	r4, #3
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    35d6:	461a      	mov	r2, r3
    35d8:	a901      	add	r1, sp, #4
    35da:	4628      	mov	r0, r5
	nrfx_gpiote_input_config_t input_config = {
    35dc:	f88d 4004 	strb.w	r4, [sp, #4]
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    35e0:	f001 fbce 	bl	4d80 <nrfx_gpiote_input_configure>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    35e4:	4b02      	ldr	r3, [pc, #8]	; (35f0 <gpio_nrfx_pin_configure+0x154>)
    35e6:	4298      	cmp	r0, r3
    35e8:	f43f af7c 	beq.w	34e4 <gpio_nrfx_pin_configure+0x48>
    35ec:	e78f      	b.n	350e <gpio_nrfx_pin_configure+0x72>
    35ee:	bf00      	nop
    35f0:	0bad0000 	.word	0x0bad0000

000035f4 <flash_nrf_pages_layout>:

static void flash_nrf_pages_layout(const struct device *dev,
				     const struct flash_pages_layout **layout,
				     size_t *layout_size)
{
	*layout = &dev_layout;
    35f4:	4b02      	ldr	r3, [pc, #8]	; (3600 <flash_nrf_pages_layout+0xc>)
    35f6:	600b      	str	r3, [r1, #0]
	*layout_size = 1;
    35f8:	2301      	movs	r3, #1
    35fa:	6013      	str	r3, [r2, #0]
}
    35fc:	4770      	bx	lr
    35fe:	bf00      	nop
    3600:	200012b8 	.word	0x200012b8

00003604 <flash_nrf_get_parameters>:
flash_nrf_get_parameters(const struct device *dev)
{
	ARG_UNUSED(dev);

	return &flash_nrf_parameters;
}
    3604:	4800      	ldr	r0, [pc, #0]	; (3608 <flash_nrf_get_parameters+0x4>)
    3606:	4770      	bx	lr
    3608:	00008ae0 	.word	0x00008ae0

0000360c <nrf_flash_init>:
	.page_layout = flash_nrf_pages_layout,
#endif
};

static int nrf_flash_init(const struct device *dev)
{
    360c:	b510      	push	{r4, lr}
#ifndef CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE
	nrf_flash_sync_init();
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

#if defined(CONFIG_FLASH_PAGE_LAYOUT)
	dev_layout.pages_count = nrfx_nvmc_flash_page_count_get();
    360e:	f005 f806 	bl	861e <nrfx_nvmc_flash_page_count_get>
    3612:	4c03      	ldr	r4, [pc, #12]	; (3620 <nrf_flash_init+0x14>)
    3614:	6020      	str	r0, [r4, #0]
	dev_layout.pages_size = nrfx_nvmc_flash_page_size_get();
    3616:	f004 fffe 	bl	8616 <nrfx_nvmc_flash_page_size_get>
    361a:	6060      	str	r0, [r4, #4]
#endif

	return 0;
}
    361c:	2000      	movs	r0, #0
    361e:	bd10      	pop	{r4, pc}
    3620:	200012b8 	.word	0x200012b8

00003624 <flash_nrf_erase>:
{
    3624:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3626:	460e      	mov	r6, r1
    3628:	4614      	mov	r4, r2
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    362a:	f004 fff4 	bl	8616 <nrfx_nvmc_flash_page_size_get>
	if (is_regular_addr_valid(addr, size)) {
    362e:	4621      	mov	r1, r4
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    3630:	4605      	mov	r5, r0
	if (is_regular_addr_valid(addr, size)) {
    3632:	4630      	mov	r0, r6
    3634:	f003 f851 	bl	66da <is_regular_addr_valid>
		if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
    3638:	4637      	mov	r7, r6
	if (is_regular_addr_valid(addr, size)) {
    363a:	b1f8      	cbz	r0, 367c <flash_nrf_erase+0x58>
		if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
    363c:	fbb6 f3f5 	udiv	r3, r6, r5
    3640:	fb05 6313 	mls	r3, r5, r3, r6
    3644:	b923      	cbnz	r3, 3650 <flash_nrf_erase+0x2c>
    3646:	fbb4 f0f5 	udiv	r0, r4, r5
    364a:	fb05 4010 	mls	r0, r5, r0, r4
    364e:	b140      	cbz	r0, 3662 <flash_nrf_erase+0x3e>
			LOG_ERR("unaligned address: 0x%08lx:%zu",
    3650:	480d      	ldr	r0, [pc, #52]	; (3688 <flash_nrf_erase+0x64>)
    3652:	4623      	mov	r3, r4
    3654:	4632      	mov	r2, r6
    3656:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("invalid address: 0x%08lx:%zu",
    3658:	f002 fbf1 	bl	5e3e <z_log_minimal_printk>
		return -EINVAL;
    365c:	f06f 0015 	mvn.w	r0, #21
    3660:	e00b      	b.n	367a <flash_nrf_erase+0x56>
		if (!n_pages) {
    3662:	42a5      	cmp	r5, r4
    3664:	d809      	bhi.n	367a <flash_nrf_erase+0x56>

#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

static int erase_op(void *context)
{
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    3666:	f004 ffd6 	bl	8616 <nrfx_nvmc_flash_page_size_get>
    366a:	4605      	mov	r5, r0
		if (nrfx_nvmc_page_partial_erase_continue()) {
			e_ctx->len -= pg_size;
			e_ctx->flash_addr += pg_size;
		}
#else
		(void)nrfx_nvmc_page_erase(e_ctx->flash_addr);
    366c:	4638      	mov	r0, r7
    366e:	f001 fe45 	bl	52fc <nrfx_nvmc_page_erase>
			}

		}
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

	} while (e_ctx->len > 0);
    3672:	1b64      	subs	r4, r4, r5
    3674:	442f      	add	r7, r5
    3676:	d1f9      	bne.n	366c <flash_nrf_erase+0x48>
	return ret;
    3678:	4620      	mov	r0, r4
}
    367a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		LOG_ERR("invalid address: 0x%08lx:%zu",
    367c:	4803      	ldr	r0, [pc, #12]	; (368c <flash_nrf_erase+0x68>)
    367e:	4623      	mov	r3, r4
    3680:	4632      	mov	r2, r6
    3682:	2145      	movs	r1, #69	; 0x45
    3684:	e7e8      	b.n	3658 <flash_nrf_erase+0x34>
    3686:	bf00      	nop
    3688:	00009992 	.word	0x00009992
    368c:	000099b6 	.word	0x000099b6

00003690 <flash_nrf_write>:
{
    3690:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3692:	460e      	mov	r6, r1
	if (is_regular_addr_valid(addr, len)) {
    3694:	4630      	mov	r0, r6
    3696:	4619      	mov	r1, r3
{
    3698:	4617      	mov	r7, r2
    369a:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    369c:	f003 f81d 	bl	66da <is_regular_addr_valid>
    36a0:	b940      	cbnz	r0, 36b4 <flash_nrf_write+0x24>
		LOG_ERR("invalid address: 0x%08lx:%zu",
    36a2:	4814      	ldr	r0, [pc, #80]	; (36f4 <flash_nrf_write+0x64>)
    36a4:	4623      	mov	r3, r4
    36a6:	4632      	mov	r2, r6
    36a8:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("not word-aligned: 0x%08lx:%zu",
    36aa:	f002 fbc8 	bl	5e3e <z_log_minimal_printk>
		return -EINVAL;
    36ae:	f06f 0015 	mvn.w	r0, #21
}
    36b2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return (data & 0x3) ? false : true;
    36b4:	ea44 0506 	orr.w	r5, r4, r6
	if (!is_aligned_32(addr) || (len % sizeof(uint32_t))) {
    36b8:	f015 0503 	ands.w	r5, r5, #3
    36bc:	d004      	beq.n	36c8 <flash_nrf_write+0x38>
		LOG_ERR("not word-aligned: 0x%08lx:%zu",
    36be:	480e      	ldr	r0, [pc, #56]	; (36f8 <flash_nrf_write+0x68>)
    36c0:	4623      	mov	r3, r4
    36c2:	4632      	mov	r2, r6
    36c4:	2145      	movs	r1, #69	; 0x45
    36c6:	e7f0      	b.n	36aa <flash_nrf_write+0x1a>
	if (!len) {
    36c8:	b18c      	cbz	r4, 36ee <flash_nrf_write+0x5e>
		}
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */
	}
#endif /* CONFIG_SOC_FLASH_NRF_EMULATE_ONE_BYTE_WRITE_ACCESS */
	/* Write all the 4-byte aligned data */
	while (w_ctx->len >= sizeof(uint32_t)) {
    36ca:	f024 0403 	bic.w	r4, r4, #3
    36ce:	42ac      	cmp	r4, r5
    36d0:	eb05 0006 	add.w	r0, r5, r6
    36d4:	d106      	bne.n	36e4 <flash_nrf_write+0x54>

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg)
{
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    36d6:	4a09      	ldr	r2, [pc, #36]	; (36fc <flash_nrf_write+0x6c>)
    36d8:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
	while (!nrfx_nvmc_write_done_check()) {
    36dc:	07db      	lsls	r3, r3, #31
    36de:	d5fb      	bpl.n	36d8 <flash_nrf_write+0x48>
	return ret;
    36e0:	2000      	movs	r0, #0
    36e2:	e7e6      	b.n	36b2 <flash_nrf_write+0x22>
		if (SUSPEND_POFWARN()) {
			return -ECANCELED;
		}

		nrfx_nvmc_word_write(w_ctx->flash_addr,
    36e4:	5979      	ldr	r1, [r7, r5]
    36e6:	f001 fe29 	bl	533c <nrfx_nvmc_word_write>
	w_ctx->len -= shift;
    36ea:	3504      	adds	r5, #4
}
    36ec:	e7ef      	b.n	36ce <flash_nrf_write+0x3e>
		return 0;
    36ee:	4620      	mov	r0, r4
    36f0:	e7df      	b.n	36b2 <flash_nrf_write+0x22>
    36f2:	bf00      	nop
    36f4:	000099b6 	.word	0x000099b6
    36f8:	000099d8 	.word	0x000099d8
    36fc:	4001e000 	.word	0x4001e000

00003700 <flash_nrf_read>:
{
    3700:	b570      	push	{r4, r5, r6, lr}
    3702:	460d      	mov	r5, r1
	if (is_regular_addr_valid(addr, len)) {
    3704:	4628      	mov	r0, r5
    3706:	4619      	mov	r1, r3
{
    3708:	4616      	mov	r6, r2
    370a:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    370c:	f002 ffe5 	bl	66da <is_regular_addr_valid>
    3710:	b940      	cbnz	r0, 3724 <flash_nrf_read+0x24>
		LOG_ERR("invalid address: 0x%08lx:%zu",
    3712:	4809      	ldr	r0, [pc, #36]	; (3738 <flash_nrf_read+0x38>)
    3714:	4623      	mov	r3, r4
    3716:	462a      	mov	r2, r5
    3718:	2145      	movs	r1, #69	; 0x45
    371a:	f002 fb90 	bl	5e3e <z_log_minimal_printk>
    371e:	f06f 0015 	mvn.w	r0, #21
}
    3722:	bd70      	pop	{r4, r5, r6, pc}
	if (!len) {
    3724:	b134      	cbz	r4, 3734 <flash_nrf_read+0x34>
	memcpy(data, (void *)addr, len);
    3726:	4622      	mov	r2, r4
    3728:	4629      	mov	r1, r5
    372a:	4630      	mov	r0, r6
    372c:	f002 fede 	bl	64ec <memcpy>
	return 0;
    3730:	2000      	movs	r0, #0
    3732:	e7f6      	b.n	3722 <flash_nrf_read+0x22>
		return 0;
    3734:	4620      	mov	r0, r4
    3736:	e7f4      	b.n	3722 <flash_nrf_read+0x22>
    3738:	000099b6 	.word	0x000099b6

0000373c <uarte_nrfx_poll_out>:
 *
 * @param dev UARTE device struct
 * @param c Character to send
 */
static void uarte_nrfx_poll_out(const struct device *dev, unsigned char c)
{
    373c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	struct uarte_nrfx_data *data = dev->data;
    373e:	6906      	ldr	r6, [r0, #16]
{
    3740:	4605      	mov	r5, r0
    3742:	460f      	mov	r7, r1
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    3744:	f004 ffd8 	bl	86f8 <k_is_in_isr>
    3748:	b910      	cbnz	r0, 3750 <uarte_nrfx_poll_out+0x14>
	return !z_sys_post_kernel;
    374a:	4b1e      	ldr	r3, [pc, #120]	; (37c4 <uarte_nrfx_poll_out+0x88>)
	int key;

	if (isr_mode) {
    374c:	781b      	ldrb	r3, [r3, #0]
    374e:	b9a3      	cbnz	r3, 377a <uarte_nrfx_poll_out+0x3e>
	__asm__ volatile(
    3750:	f04f 0320 	mov.w	r3, #32
    3754:	f3ef 8411 	mrs	r4, BASEPRI
    3758:	f383 8812 	msr	BASEPRI_MAX, r3
    375c:	f3bf 8f6f 	isb	sy
		while (1) {
			key = irq_lock();
			if (is_tx_ready(dev)) {
    3760:	6868      	ldr	r0, [r5, #4]
    3762:	f003 f8fb 	bl	695c <is_tx_ready.isra.0>
    3766:	bb00      	cbnz	r0, 37aa <uarte_nrfx_poll_out+0x6e>
	__asm__ volatile(
    3768:	f384 8811 	msr	BASEPRI, r4
    376c:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    3770:	e7ee      	b.n	3750 <uarte_nrfx_poll_out+0x14>
	__asm__ volatile(
    3772:	f384 8811 	msr	BASEPRI, r4
    3776:	f3bf 8f6f 	isb	sy
{
    377a:	2464      	movs	r4, #100	; 0x64
		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    377c:	6868      	ldr	r0, [r5, #4]
    377e:	f003 f8ed 	bl	695c <is_tx_ready.isra.0>
    3782:	b928      	cbnz	r0, 3790 <uarte_nrfx_poll_out+0x54>
    3784:	2001      	movs	r0, #1
    3786:	f004 ff21 	bl	85cc <nrfx_busy_wait>
    378a:	3c01      	subs	r4, #1
    378c:	d1f6      	bne.n	377c <uarte_nrfx_poll_out+0x40>
    378e:	e7f4      	b.n	377a <uarte_nrfx_poll_out+0x3e>
	__asm__ volatile(
    3790:	f04f 0320 	mov.w	r3, #32
    3794:	f3ef 8411 	mrs	r4, BASEPRI
    3798:	f383 8812 	msr	BASEPRI_MAX, r3
    379c:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    37a0:	6868      	ldr	r0, [r5, #4]
    37a2:	f003 f8db 	bl	695c <is_tx_ready.isra.0>
    37a6:	2800      	cmp	r0, #0
    37a8:	d0e3      	beq.n	3772 <uarte_nrfx_poll_out+0x36>
		}
	} else {
		key = wait_tx_ready(dev);
	}

	data->char_out = c;
    37aa:	4631      	mov	r1, r6
	tx_start(dev, &data->char_out, 1);
    37ac:	2201      	movs	r2, #1
	data->char_out = c;
    37ae:	f801 7f14 	strb.w	r7, [r1, #20]!
	tx_start(dev, &data->char_out, 1);
    37b2:	6868      	ldr	r0, [r5, #4]
    37b4:	f003 f8b7 	bl	6926 <tx_start.isra.0>
	__asm__ volatile(
    37b8:	f384 8811 	msr	BASEPRI, r4
    37bc:	f3bf 8f6f 	isb	sy

	irq_unlock(key);
}
    37c0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    37c2:	bf00      	nop
    37c4:	2000354c 	.word	0x2000354c

000037c8 <uarte_nrfx_configure>:
{
    37c8:	b570      	push	{r4, r5, r6, lr}
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
    37ca:	794b      	ldrb	r3, [r1, #5]
    37cc:	2b01      	cmp	r3, #1
    37ce:	d120      	bne.n	3812 <uarte_nrfx_configure+0x4a>
	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    37d0:	798b      	ldrb	r3, [r1, #6]
    37d2:	2b03      	cmp	r3, #3
    37d4:	d11d      	bne.n	3812 <uarte_nrfx_configure+0x4a>
	switch (cfg->flow_ctrl) {
    37d6:	79cc      	ldrb	r4, [r1, #7]
    37d8:	b10c      	cbz	r4, 37de <uarte_nrfx_configure+0x16>
    37da:	2c01      	cmp	r4, #1
    37dc:	d119      	bne.n	3812 <uarte_nrfx_configure+0x4a>
	switch (cfg->parity) {
    37de:	790a      	ldrb	r2, [r1, #4]
    37e0:	b112      	cbz	r2, 37e8 <uarte_nrfx_configure+0x20>
    37e2:	2a02      	cmp	r2, #2
    37e4:	d115      	bne.n	3812 <uarte_nrfx_configure+0x4a>
    37e6:	220e      	movs	r2, #14
	if (baudrate_set(dev, cfg->baudrate) != 0) {
    37e8:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    37ea:	6845      	ldr	r5, [r0, #4]
	switch (baudrate) {
    37ec:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    37f0:	682d      	ldr	r5, [r5, #0]
	switch (baudrate) {
    37f2:	d062      	beq.n	38ba <uarte_nrfx_configure+0xf2>
    37f4:	d82b      	bhi.n	384e <uarte_nrfx_configure+0x86>
    37f6:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    37fa:	d061      	beq.n	38c0 <uarte_nrfx_configure+0xf8>
    37fc:	d814      	bhi.n	3828 <uarte_nrfx_configure+0x60>
    37fe:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    3802:	d05f      	beq.n	38c4 <uarte_nrfx_configure+0xfc>
    3804:	d808      	bhi.n	3818 <uarte_nrfx_configure+0x50>
    3806:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    380a:	d05e      	beq.n	38ca <uarte_nrfx_configure+0x102>
    380c:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    3810:	d05e      	beq.n	38d0 <uarte_nrfx_configure+0x108>
    3812:	f06f 0085 	mvn.w	r0, #133	; 0x85
    3816:	e04f      	b.n	38b8 <uarte_nrfx_configure+0xf0>
    3818:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    381c:	d05b      	beq.n	38d6 <uarte_nrfx_configure+0x10e>
    381e:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    3822:	d1f6      	bne.n	3812 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    3824:	4b36      	ldr	r3, [pc, #216]	; (3900 <uarte_nrfx_configure+0x138>)
    3826:	e03c      	b.n	38a2 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    3828:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    382c:	d056      	beq.n	38dc <uarte_nrfx_configure+0x114>
    382e:	d807      	bhi.n	3840 <uarte_nrfx_configure+0x78>
    3830:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    3834:	d054      	beq.n	38e0 <uarte_nrfx_configure+0x118>
    3836:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    383a:	d1ea      	bne.n	3812 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    383c:	4b31      	ldr	r3, [pc, #196]	; (3904 <uarte_nrfx_configure+0x13c>)
    383e:	e030      	b.n	38a2 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    3840:	f647 2612 	movw	r6, #31250	; 0x7a12
    3844:	42b3      	cmp	r3, r6
    3846:	d1e4      	bne.n	3812 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    3848:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    384c:	e029      	b.n	38a2 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    384e:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    3852:	d047      	beq.n	38e4 <uarte_nrfx_configure+0x11c>
    3854:	d813      	bhi.n	387e <uarte_nrfx_configure+0xb6>
    3856:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    385a:	d046      	beq.n	38ea <uarte_nrfx_configure+0x122>
    385c:	d809      	bhi.n	3872 <uarte_nrfx_configure+0xaa>
    385e:	f64d 26c0 	movw	r6, #56000	; 0xdac0
    3862:	42b3      	cmp	r3, r6
    3864:	d043      	beq.n	38ee <uarte_nrfx_configure+0x126>
    3866:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    386a:	d1d2      	bne.n	3812 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    386c:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    3870:	e017      	b.n	38a2 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    3872:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    3876:	d1cc      	bne.n	3812 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    3878:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    387c:	e011      	b.n	38a2 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    387e:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    3882:	d037      	beq.n	38f4 <uarte_nrfx_configure+0x12c>
    3884:	d808      	bhi.n	3898 <uarte_nrfx_configure+0xd0>
    3886:	4e20      	ldr	r6, [pc, #128]	; (3908 <uarte_nrfx_configure+0x140>)
    3888:	42b3      	cmp	r3, r6
    388a:	d036      	beq.n	38fa <uarte_nrfx_configure+0x132>
    388c:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    3890:	d1bf      	bne.n	3812 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    3892:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    3896:	e004      	b.n	38a2 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    3898:	4e1c      	ldr	r6, [pc, #112]	; (390c <uarte_nrfx_configure+0x144>)
    389a:	42b3      	cmp	r3, r6
    389c:	d1b9      	bne.n	3812 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    389e:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
	struct uarte_nrfx_data *data = dev->data;
    38a2:	6900      	ldr	r0, [r0, #16]
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    38a4:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
	data->uart_config = *cfg;
    38a8:	1d03      	adds	r3, r0, #4
    38aa:	c903      	ldmia	r1, {r0, r1}
                    | (uint32_t)p_cfg->hwfc;
    38ac:	4322      	orrs	r2, r4
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    38ae:	f8c5 256c 	str.w	r2, [r5, #1388]	; 0x56c
    38b2:	e883 0003 	stmia.w	r3, {r0, r1}
	return 0;
    38b6:	2000      	movs	r0, #0
}
    38b8:	bd70      	pop	{r4, r5, r6, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    38ba:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    38be:	e7f0      	b.n	38a2 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    38c0:	4b13      	ldr	r3, [pc, #76]	; (3910 <uarte_nrfx_configure+0x148>)
    38c2:	e7ee      	b.n	38a2 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    38c4:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    38c8:	e7eb      	b.n	38a2 <uarte_nrfx_configure+0xda>
		nrf_baudrate = 0x00014000;
    38ca:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    38ce:	e7e8      	b.n	38a2 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    38d0:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    38d4:	e7e5      	b.n	38a2 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    38d6:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    38da:	e7e2      	b.n	38a2 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    38dc:	4b0d      	ldr	r3, [pc, #52]	; (3914 <uarte_nrfx_configure+0x14c>)
    38de:	e7e0      	b.n	38a2 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    38e0:	4b0d      	ldr	r3, [pc, #52]	; (3918 <uarte_nrfx_configure+0x150>)
    38e2:	e7de      	b.n	38a2 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    38e4:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    38e8:	e7db      	b.n	38a2 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    38ea:	4b0c      	ldr	r3, [pc, #48]	; (391c <uarte_nrfx_configure+0x154>)
    38ec:	e7d9      	b.n	38a2 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    38ee:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    38f2:	e7d6      	b.n	38a2 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    38f4:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    38f8:	e7d3      	b.n	38a2 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    38fa:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    38fe:	e7d0      	b.n	38a2 <uarte_nrfx_configure+0xda>
    3900:	0013b000 	.word	0x0013b000
    3904:	004ea000 	.word	0x004ea000
    3908:	0003d090 	.word	0x0003d090
    390c:	000f4240 	.word	0x000f4240
    3910:	00275000 	.word	0x00275000
    3914:	0075c000 	.word	0x0075c000
    3918:	003af000 	.word	0x003af000
    391c:	013a9000 	.word	0x013a9000

00003920 <uarte_0_init>:
				.tx_buffer = uarte##idx##_tx_buffer,	       \
				.tx_buff_size = sizeof(uarte##idx##_tx_buffer),\
			};))

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
    3920:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    3924:	4607      	mov	r7, r0
    3926:	2200      	movs	r2, #0
    3928:	2101      	movs	r1, #1
    392a:	2002      	movs	r0, #2
    392c:	f7fe ffa4 	bl	2878 <z_arm_irq_priority_set>
    3930:	2002      	movs	r0, #2
    3932:	f7fe ff83 	bl	283c <arch_irq_enable>
	const struct uarte_nrfx_config *config = dev->config;
    3936:	f8d7 8004 	ldr.w	r8, [r7, #4]
	struct uarte_nrfx_data *data = dev->data;
    393a:	693e      	ldr	r6, [r7, #16]
	return config->uarte_regs;
    393c:	f8d8 4000 	ldr.w	r4, [r8]
	err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
    3940:	f8d8 900c 	ldr.w	r9, [r8, #12]
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    3944:	2100      	movs	r1, #0
    3946:	f8c4 1500 	str.w	r1, [r4, #1280]	; 0x500
				      uint8_t id)
{
	int ret;
	const struct pinctrl_state *state;

	ret = pinctrl_lookup_state(config, id, &state);
    394a:	aa01      	add	r2, sp, #4
	data->dev = dev;
    394c:	6037      	str	r7, [r6, #0]
    394e:	4648      	mov	r0, r9
    3950:	f003 f8b1 	bl	6ab6 <pinctrl_lookup_state>
	if (ret < 0) {
    3954:	1e05      	subs	r5, r0, #0
    3956:	db1f      	blt.n	3998 <uarte_0_init+0x78>
		return ret;
	}

	return pinctrl_apply_state_direct(config, state);
    3958:	9b01      	ldr	r3, [sp, #4]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    395a:	f8d9 2000 	ldr.w	r2, [r9]
    395e:	7919      	ldrb	r1, [r3, #4]
    3960:	6818      	ldr	r0, [r3, #0]
    3962:	f003 f8ea 	bl	6b3a <pinctrl_configure_pins>
	if (err < 0) {
    3966:	1e05      	subs	r5, r0, #0
    3968:	db16      	blt.n	3998 <uarte_0_init+0x78>
	err = uarte_nrfx_configure(dev, &data->uart_config);
    396a:	1d31      	adds	r1, r6, #4
    396c:	4638      	mov	r0, r7
    396e:	f7ff ff2b 	bl	37c8 <uarte_nrfx_configure>
	if (err) {
    3972:	4605      	mov	r5, r0
    3974:	b980      	cbnz	r0, 3998 <uarte_0_init+0x78>
	    cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX) {
    3976:	f8d8 3004 	ldr.w	r3, [r8, #4]
	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
    397a:	0799      	lsls	r1, r3, #30
    397c:	d523      	bpl.n	39c6 <uarte_0_init+0xa6>
	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    397e:	f106 0016 	add.w	r0, r6, #22
    3982:	f001 fce9 	bl	5358 <nrfx_ppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    3986:	4b25      	ldr	r3, [pc, #148]	; (3a1c <uarte_0_init+0xfc>)
    3988:	4298      	cmp	r0, r3
    398a:	d009      	beq.n	39a0 <uarte_0_init+0x80>
		LOG_ERR("Failed to allocate PPI Channel");
    398c:	4824      	ldr	r0, [pc, #144]	; (3a20 <uarte_0_init+0x100>)
    398e:	2145      	movs	r1, #69	; 0x45
    3990:	f002 fa55 	bl	5e3e <z_log_minimal_printk>
		return -EIO;
    3994:	f06f 0504 	mvn.w	r5, #4
UART_NRF_UARTE_DEVICE(0);
    3998:	4628      	mov	r0, r5
    399a:	b003      	add	sp, #12
    399c:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
	nrfx_gppi_channel_endpoints_setup(data->ppi_ch_endtx,
    39a0:	7db0      	ldrb	r0, [r6, #22]
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    39a2:	00c3      	lsls	r3, r0, #3
    39a4:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    39a8:	f503 33f8 	add.w	r3, r3, #126976	; 0x1f000
    return (uint32_t)p_reg + (uint32_t)task;
    39ac:	f104 020c 	add.w	r2, r4, #12
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    39b0:	f504 7190 	add.w	r1, r4, #288	; 0x120
NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type *    p_reg,
                                                      nrf_ppi_channel_t channel,
                                                      uint32_t          eep,
                                                      uint32_t          tep)
{
    p_reg->CH[(uint32_t) channel].EEP = eep;
    39b4:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    p_reg->CH[(uint32_t) channel].TEP = tep;
    39b8:	f8c3 2514 	str.w	r2, [r3, #1300]	; 0x514
    p_reg->CHENSET = mask;
    39bc:	4a19      	ldr	r2, [pc, #100]	; (3a24 <uarte_0_init+0x104>)
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    39be:	2301      	movs	r3, #1
    39c0:	4083      	lsls	r3, r0
    39c2:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    39c6:	2308      	movs	r3, #8
    39c8:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
		if (!cfg->disable_rx) {
    39cc:	f898 3008 	ldrb.w	r3, [r8, #8]
    39d0:	b95b      	cbnz	r3, 39ea <uarte_0_init+0xca>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    39d2:	f8c4 3110 	str.w	r3, [r4, #272]	; 0x110
    39d6:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110
			nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
    39da:	f106 0315 	add.w	r3, r6, #21

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    39de:	f8c4 3534 	str.w	r3, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    39e2:	2301      	movs	r3, #1
    39e4:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    39e8:	6023      	str	r3, [r4, #0]
	if (!(cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX)) {
    39ea:	f8d8 3004 	ldr.w	r3, [r8, #4]
    39ee:	079a      	lsls	r2, r3, #30
    p_reg->INTENSET = mask;
    39f0:	bf5c      	itt	pl
    39f2:	f44f 7280 	movpl.w	r2, #256	; 0x100
    39f6:	f8c4 2304 	strpl.w	r2, [r4, #772]	; 0x304
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    39fa:	06db      	lsls	r3, r3, #27
    39fc:	bf44      	itt	mi
    39fe:	f44f 0380 	movmi.w	r3, #4194304	; 0x400000
    3a02:	f8c4 3304 	strmi.w	r3, [r4, #772]	; 0x304
	nrf_uarte_tx_buffer_set(uarte, &data->char_out, 0);
    3a06:	3614      	adds	r6, #20
    p_reg->TXD.MAXCNT = length;
    3a08:	2300      	movs	r3, #0
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    3a0a:	f8c4 6544 	str.w	r6, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    3a0e:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3a12:	2301      	movs	r3, #1
    3a14:	60a3      	str	r3, [r4, #8]
    3a16:	60e3      	str	r3, [r4, #12]
UART_NRF_UARTE_DEVICE(0);
    3a18:	e7be      	b.n	3998 <uarte_0_init+0x78>
    3a1a:	bf00      	nop
    3a1c:	0bad0000 	.word	0x0bad0000
    3a20:	00009a05 	.word	0x00009a05
    3a24:	4001f000 	.word	0x4001f000

00003a28 <compare_int_lock>:
	return 0;
#endif
}

static bool compare_int_lock(int32_t chan)
{
    3a28:	b510      	push	{r4, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    3a2a:	2301      	movs	r3, #1
    3a2c:	4083      	lsls	r3, r0
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    3a2e:	4a11      	ldr	r2, [pc, #68]	; (3a74 <compare_int_lock+0x4c>)
    3a30:	f3bf 8f5b 	dmb	ish
    3a34:	43dc      	mvns	r4, r3
    3a36:	e852 1f00 	ldrex	r1, [r2]
    3a3a:	ea01 0c04 	and.w	ip, r1, r4
    3a3e:	e842 ce00 	strex	lr, ip, [r2]
    3a42:	f1be 0f00 	cmp.w	lr, #0
    3a46:	d1f6      	bne.n	3a36 <compare_int_lock+0xe>
    3a48:	f3bf 8f5b 	dmb	ish

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    3a4c:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    3a50:	fa02 f000 	lsl.w	r0, r2, r0
    3a54:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    3a58:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
    3a5c:	f8c2 0308 	str.w	r0, [r2, #776]	; 0x308
  __ASM volatile ("dmb 0xF":::"memory");
    3a60:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    3a64:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    3a68:	420b      	tst	r3, r1
}
    3a6a:	bf14      	ite	ne
    3a6c:	2001      	movne	r0, #1
    3a6e:	2000      	moveq	r0, #0
    3a70:	bd10      	pop	{r4, pc}
    3a72:	bf00      	nop
    3a74:	200012c4 	.word	0x200012c4

00003a78 <sys_clock_timeout_handler>:
static void sys_clock_timeout_handler(int32_t chan,
				      uint64_t expire_time,
				      void *user_data)
{
	uint32_t cc_value = absolute_time_to_cc(expire_time);
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    3a78:	4919      	ldr	r1, [pc, #100]	; (3ae0 <sys_clock_timeout_handler+0x68>)
{
    3a7a:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3a7c:	4604      	mov	r4, r0
	return absolute_time & COUNTER_MAX;
    3a7e:	f022 457f 	bic.w	r5, r2, #4278190080	; 0xff000000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    3a82:	6808      	ldr	r0, [r1, #0]

	last_count += dticks * CYC_PER_TICK;
    3a84:	e9c1 2300 	strd	r2, r3, [r1]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    3a88:	f5a5 1300 	sub.w	r3, r5, #2097152	; 0x200000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    3a8c:	1a10      	subs	r0, r2, r0
	if (in_anchor_range(cc_value)) {
    3a8e:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    3a92:	d222      	bcs.n	3ada <sys_clock_timeout_handler+0x62>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    3a94:	4b13      	ldr	r3, [pc, #76]	; (3ae4 <sys_clock_timeout_handler+0x6c>)
    3a96:	681b      	ldr	r3, [r3, #0]
    3a98:	0a1a      	lsrs	r2, r3, #8
    3a9a:	061b      	lsls	r3, r3, #24
    3a9c:	195e      	adds	r6, r3, r5
    3a9e:	4b12      	ldr	r3, [pc, #72]	; (3ae8 <sys_clock_timeout_handler+0x70>)
    3aa0:	f142 0700 	adc.w	r7, r2, #0
    3aa4:	e9c3 6700 	strd	r6, r7, [r3]
		return true;
    3aa8:	2601      	movs	r6, #1
		 */
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    3aaa:	f001 fe03 	bl	56b4 <sys_clock_announce>
    return p_reg->CC[ch];
    3aae:	00a3      	lsls	r3, r4, #2
    3ab0:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    3ab4:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    3ab8:	f8d3 2540 	ldr.w	r2, [r3, #1344]	; 0x540
			   (int32_t)dticks : (dticks > 0));

	if (cc_value == get_comparator(chan)) {
    3abc:	42aa      	cmp	r2, r5
    3abe:	d10b      	bne.n	3ad8 <sys_clock_timeout_handler+0x60>
		 * If anchor was updated we can enable same CC value to trigger
		 * interrupt after full cycle. Else set event in anchor update
		 * range. Since anchor was not updated we know that it's very
		 * far from mid point so setting is done without any protection.
		 */
		if (!anchor_updated) {
    3ac0:	b91e      	cbnz	r6, 3aca <sys_clock_timeout_handler+0x52>
    p_reg->CC[ch] = cc_val;
    3ac2:	f44f 0200 	mov.w	r2, #8388608	; 0x800000
    3ac6:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    p_reg->EVTENSET = mask;
    3aca:	4b08      	ldr	r3, [pc, #32]	; (3aec <sys_clock_timeout_handler+0x74>)
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    3acc:	f44f 3080 	mov.w	r0, #65536	; 0x10000
    3ad0:	fa00 f404 	lsl.w	r4, r0, r4
    3ad4:	f8c3 4344 	str.w	r4, [r3, #836]	; 0x344
			set_comparator(chan, COUNTER_HALF_SPAN);
		}
		event_enable(chan);
	}
}
    3ad8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return false;
    3ada:	2600      	movs	r6, #0
    3adc:	e7e5      	b.n	3aaa <sys_clock_timeout_handler+0x32>
    3ade:	bf00      	nop
    3ae0:	20000100 	.word	0x20000100
    3ae4:	200012c8 	.word	0x200012c8
    3ae8:	200000e8 	.word	0x200000e8
    3aec:	40011000 	.word	0x40011000

00003af0 <compare_int_unlock>:
	if (key) {
    3af0:	b319      	cbz	r1, 3b3a <compare_int_unlock+0x4a>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    3af2:	f3bf 8f5b 	dmb	ish
		atomic_or(&int_mask, BIT(chan));
    3af6:	2301      	movs	r3, #1
    3af8:	4a10      	ldr	r2, [pc, #64]	; (3b3c <compare_int_unlock+0x4c>)
    3afa:	4083      	lsls	r3, r0
    3afc:	e852 1f00 	ldrex	r1, [r2]
    3b00:	4319      	orrs	r1, r3
    3b02:	e842 1c00 	strex	ip, r1, [r2]
    3b06:	f1bc 0f00 	cmp.w	ip, #0
    3b0a:	d1f7      	bne.n	3afc <compare_int_unlock+0xc>
    3b0c:	f3bf 8f5b 	dmb	ish
    p_reg->INTENSET = mask;
    3b10:	4a0b      	ldr	r2, [pc, #44]	; (3b40 <compare_int_unlock+0x50>)
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    3b12:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    3b16:	4083      	lsls	r3, r0
    3b18:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    3b1c:	4b09      	ldr	r3, [pc, #36]	; (3b44 <compare_int_unlock+0x54>)
    3b1e:	f3bf 8f5b 	dmb	ish
    3b22:	681b      	ldr	r3, [r3, #0]
    3b24:	f3bf 8f5b 	dmb	ish
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    3b28:	fa23 f000 	lsr.w	r0, r3, r0
    3b2c:	07c3      	lsls	r3, r0, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    3b2e:	bf42      	ittt	mi
    3b30:	4b05      	ldrmi	r3, [pc, #20]	; (3b48 <compare_int_unlock+0x58>)
    3b32:	f44f 3200 	movmi.w	r2, #131072	; 0x20000
    3b36:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
}
    3b3a:	4770      	bx	lr
    3b3c:	200012c4 	.word	0x200012c4
    3b40:	40011000 	.word	0x40011000
    3b44:	200012c0 	.word	0x200012c0
    3b48:	e000e100 	.word	0xe000e100

00003b4c <z_nrf_rtc_timer_read>:
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    3b4c:	4b0d      	ldr	r3, [pc, #52]	; (3b84 <z_nrf_rtc_timer_read+0x38>)
    3b4e:	6818      	ldr	r0, [r3, #0]
    3b50:	0a01      	lsrs	r1, r0, #8
    3b52:	0600      	lsls	r0, r0, #24
  __ASM volatile ("dmb 0xF":::"memory");
    3b54:	f3bf 8f5f 	dmb	sy
     return p_reg->COUNTER;
    3b58:	4b0b      	ldr	r3, [pc, #44]	; (3b88 <z_nrf_rtc_timer_read+0x3c>)
    3b5a:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	val += cntr;
    3b5e:	1818      	adds	r0, r3, r0
    3b60:	f141 0100 	adc.w	r1, r1, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    3b64:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    3b68:	d20a      	bcs.n	3b80 <z_nrf_rtc_timer_read+0x34>
		if (val < anchor) {
    3b6a:	4b08      	ldr	r3, [pc, #32]	; (3b8c <z_nrf_rtc_timer_read+0x40>)
    3b6c:	e9d3 2300 	ldrd	r2, r3, [r3]
    3b70:	4290      	cmp	r0, r2
    3b72:	eb71 0303 	sbcs.w	r3, r1, r3
    3b76:	d203      	bcs.n	3b80 <z_nrf_rtc_timer_read+0x34>
			val += COUNTER_SPAN;
    3b78:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    3b7c:	f141 0100 	adc.w	r1, r1, #0
}
    3b80:	4770      	bx	lr
    3b82:	bf00      	nop
    3b84:	200012c8 	.word	0x200012c8
    3b88:	40011000 	.word	0x40011000
    3b8c:	200000e8 	.word	0x200000e8

00003b90 <compare_set>:
{
    3b90:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3b94:	b085      	sub	sp, #20
    3b96:	4616      	mov	r6, r2
    3b98:	4698      	mov	r8, r3
    3b9a:	4605      	mov	r5, r0
	key = compare_int_lock(chan);
    3b9c:	f7ff ff44 	bl	3a28 <compare_int_lock>
    3ba0:	9000      	str	r0, [sp, #0]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    3ba2:	f7ff ffd3 	bl	3b4c <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    3ba6:	42b0      	cmp	r0, r6
    3ba8:	eb71 0308 	sbcs.w	r3, r1, r8
    3bac:	d278      	bcs.n	3ca0 <compare_set+0x110>
		if (target_time - curr_time > COUNTER_SPAN) {
    3bae:	4b46      	ldr	r3, [pc, #280]	; (3cc8 <compare_set+0x138>)
    3bb0:	1a30      	subs	r0, r6, r0
    3bb2:	eb68 0101 	sbc.w	r1, r8, r1
    3bb6:	4298      	cmp	r0, r3
    3bb8:	f171 0300 	sbcs.w	r3, r1, #0
    3bbc:	f080 8081 	bcs.w	3cc2 <compare_set+0x132>
		if (target_time != cc_data[chan].target_time) {
    3bc0:	4b42      	ldr	r3, [pc, #264]	; (3ccc <compare_set+0x13c>)
    3bc2:	eb03 1305 	add.w	r3, r3, r5, lsl #4
    3bc6:	e9d3 ab02 	ldrd	sl, fp, [r3, #8]
    3bca:	45d8      	cmp	r8, fp
    3bcc:	bf08      	it	eq
    3bce:	4556      	cmpeq	r6, sl
    3bd0:	d051      	beq.n	3c76 <compare_set+0xe6>
    3bd2:	ea4f 0985 	mov.w	r9, r5, lsl #2
    3bd6:	f109 4980 	add.w	r9, r9, #1073741824	; 0x40000000
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    3bda:	f105 0750 	add.w	r7, r5, #80	; 0x50
    3bde:	f509 3988 	add.w	r9, r9, #69632	; 0x11000
    3be2:	00bf      	lsls	r7, r7, #2
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    3be4:	f44f 3180 	mov.w	r1, #65536	; 0x10000
    3be8:	fa01 f305 	lsl.w	r3, r1, r5
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3bec:	b2bf      	uxth	r7, r7
	return absolute_time & COUNTER_MAX;
    3bee:	f026 427f 	bic.w	r2, r6, #4278190080	; 0xff000000
    3bf2:	f107 4780 	add.w	r7, r7, #1073741824	; 0x40000000
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    3bf6:	9301      	str	r3, [sp, #4]
    return p_reg->CC[ch];
    3bf8:	f8d9 0540 	ldr.w	r0, [r9, #1344]	; 0x540
     return p_reg->COUNTER;
    3bfc:	4b34      	ldr	r3, [pc, #208]	; (3cd0 <compare_set+0x140>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3bfe:	f507 3788 	add.w	r7, r7, #69632	; 0x11000
	uint32_t cc_val = abs_val & COUNTER_MAX;
    3c02:	4614      	mov	r4, r2
     return p_reg->COUNTER;
    3c04:	f8d3 1504 	ldr.w	r1, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    3c08:	1a40      	subs	r0, r0, r1
    3c0a:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    3c0e:	f021 4c7f 	bic.w	ip, r1, #4278190080	; 0xff000000
		if (counter_sub(prev_cc, now) == 1) {
    3c12:	2801      	cmp	r0, #1
    p_reg->CC[ch] = cc_val;
    3c14:	f8c9 c540 	str.w	ip, [r9, #1344]	; 0x540
    3c18:	d107      	bne.n	3c2a <compare_set+0x9a>
    3c1a:	e9cd 2102 	strd	r2, r1, [sp, #8]
    3c1e:	2013      	movs	r0, #19
    3c20:	f004 fd70 	bl	8704 <z_impl_k_busy_wait>
    3c24:	e9dd 2102 	ldrd	r2, r1, [sp, #8]
    3c28:	4b29      	ldr	r3, [pc, #164]	; (3cd0 <compare_set+0x140>)
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    3c2a:	f101 0c02 	add.w	ip, r1, #2
	return (a - b) & COUNTER_MAX;
    3c2e:	eba4 000c 	sub.w	r0, r4, ip
    3c32:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
			cc_val = now + 2;
    3c36:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    3c3a:	bf88      	it	hi
    3c3c:	4664      	movhi	r4, ip
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3c3e:	2000      	movs	r0, #0
    3c40:	6038      	str	r0, [r7, #0]
    3c42:	6838      	ldr	r0, [r7, #0]
    p_reg->EVTENSET = mask;
    3c44:	9801      	ldr	r0, [sp, #4]
    3c46:	f8c3 0344 	str.w	r0, [r3, #836]	; 0x344
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    3c4a:	f024 407f 	bic.w	r0, r4, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    3c4e:	f8c9 0540 	str.w	r0, [r9, #1344]	; 0x540
     return p_reg->COUNTER;
    3c52:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
		 (counter_sub(cc_val, now2 + 2) > COUNTER_HALF_SPAN));
    3c56:	4281      	cmp	r1, r0
    3c58:	d006      	beq.n	3c68 <compare_set+0xd8>
	return (a - b) & COUNTER_MAX;
    3c5a:	1a20      	subs	r0, r4, r0
    3c5c:	3802      	subs	r0, #2
    3c5e:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	} while ((now2 != now) &&
    3c62:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    3c66:	d819      	bhi.n	3c9c <compare_set+0x10c>
	return (a - b) & COUNTER_MAX;
    3c68:	1aa4      	subs	r4, r4, r2
    3c6a:	f024 447f 	bic.w	r4, r4, #4278190080	; 0xff000000
			target_time += counter_sub(cc_set, cc_value);
    3c6e:	eb14 0a06 	adds.w	sl, r4, r6
    3c72:	f148 0b00 	adc.w	fp, r8, #0
	cc_data[chan].target_time = target_time;
    3c76:	4915      	ldr	r1, [pc, #84]	; (3ccc <compare_set+0x13c>)
	cc_data[chan].callback = handler;
    3c78:	980e      	ldr	r0, [sp, #56]	; 0x38
	cc_data[chan].target_time = target_time;
    3c7a:	012b      	lsls	r3, r5, #4
    3c7c:	eb01 1205 	add.w	r2, r1, r5, lsl #4
    3c80:	e9c2 ab02 	strd	sl, fp, [r2, #8]
	cc_data[chan].callback = handler;
    3c84:	50c8      	str	r0, [r1, r3]
	cc_data[chan].user_context = user_data;
    3c86:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
    3c88:	6053      	str	r3, [r2, #4]
	return ret;
    3c8a:	2400      	movs	r4, #0
	compare_int_unlock(chan, key);
    3c8c:	4628      	mov	r0, r5
    3c8e:	9900      	ldr	r1, [sp, #0]
    3c90:	f7ff ff2e 	bl	3af0 <compare_int_unlock>
}
    3c94:	4620      	mov	r0, r4
    3c96:	b005      	add	sp, #20
    3c98:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    3c9c:	4620      	mov	r0, r4
    3c9e:	e7b1      	b.n	3c04 <compare_set+0x74>
		atomic_or(&force_isr_mask, BIT(chan));
    3ca0:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    3ca2:	4a0c      	ldr	r2, [pc, #48]	; (3cd4 <compare_set+0x144>)
    3ca4:	f3bf 8f5b 	dmb	ish
    3ca8:	40ab      	lsls	r3, r5
    3caa:	e852 1f00 	ldrex	r1, [r2]
    3cae:	4319      	orrs	r1, r3
    3cb0:	e842 1000 	strex	r0, r1, [r2]
    3cb4:	2800      	cmp	r0, #0
    3cb6:	d1f8      	bne.n	3caa <compare_set+0x11a>
    3cb8:	f3bf 8f5b 	dmb	ish
    3cbc:	46b2      	mov	sl, r6
    3cbe:	46c3      	mov	fp, r8
    3cc0:	e7d9      	b.n	3c76 <compare_set+0xe6>
			return -EINVAL;
    3cc2:	f06f 0415 	mvn.w	r4, #21
    3cc6:	e7e1      	b.n	3c8c <compare_set+0xfc>
    3cc8:	01000001 	.word	0x01000001
    3ccc:	200000f0 	.word	0x200000f0
    3cd0:	40011000 	.word	0x40011000
    3cd4:	200012c0 	.word	0x200012c0

00003cd8 <sys_clock_driver_init>:
{
	return (uint32_t)z_nrf_rtc_timer_read();
}

static int sys_clock_driver_init(const struct device *dev)
{
    3cd8:	b573      	push	{r0, r1, r4, r5, r6, lr}
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    3cda:	4b19      	ldr	r3, [pc, #100]	; (3d40 <sys_clock_driver_init+0x68>)
    p_reg->PRESCALER = val;
    3cdc:	4d19      	ldr	r5, [pc, #100]	; (3d44 <sys_clock_driver_init+0x6c>)
    3cde:	2400      	movs	r4, #0
    3ce0:	f04f 30ff 	mov.w	r0, #4294967295
    3ce4:	f04f 31ff 	mov.w	r1, #4294967295
    3ce8:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    3cec:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    3cf0:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    3cf4:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    3cf8:	4b13      	ldr	r3, [pc, #76]	; (3d48 <sys_clock_driver_init+0x70>)
    3cfa:	2602      	movs	r6, #2
    3cfc:	f44f 3200 	mov.w	r2, #131072	; 0x20000

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    3d00:	2101      	movs	r1, #1
    3d02:	f8c5 6304 	str.w	r6, [r5, #772]	; 0x304
    3d06:	2011      	movs	r0, #17
    3d08:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    3d0c:	4622      	mov	r2, r4
    3d0e:	f7fe fdb3 	bl	2878 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    3d12:	2011      	movs	r0, #17
    3d14:	f7fe fd92 	bl	283c <arch_irq_enable>

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    3d18:	4a0c      	ldr	r2, [pc, #48]	; (3d4c <sys_clock_driver_init+0x74>)
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    3d1a:	2301      	movs	r3, #1
    3d1c:	60ab      	str	r3, [r5, #8]
    3d1e:	602b      	str	r3, [r5, #0]
    3d20:	6013      	str	r3, [r2, #0]

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
		(COUNTER_HALF_SPAN - 1) :
		(counter() + CYC_PER_TICK);

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    3d22:	4b0b      	ldr	r3, [pc, #44]	; (3d50 <sys_clock_driver_init+0x78>)
    3d24:	4a0b      	ldr	r2, [pc, #44]	; (3d54 <sys_clock_driver_init+0x7c>)
    3d26:	9300      	str	r3, [sp, #0]
    3d28:	9401      	str	r4, [sp, #4]
    3d2a:	2300      	movs	r3, #0
    3d2c:	4620      	mov	r0, r4
    3d2e:	f7ff ff2f 	bl	3b90 <compare_set>

	z_nrf_clock_control_lf_on(mode);
    3d32:	4630      	mov	r0, r6
    3d34:	f7ff fa6c 	bl	3210 <z_nrf_clock_control_lf_on>

	return 0;
}
    3d38:	4620      	mov	r0, r4
    3d3a:	b002      	add	sp, #8
    3d3c:	bd70      	pop	{r4, r5, r6, pc}
    3d3e:	bf00      	nop
    3d40:	200000f0 	.word	0x200000f0
    3d44:	40011000 	.word	0x40011000
    3d48:	e000e100 	.word	0xe000e100
    3d4c:	200012c4 	.word	0x200012c4
    3d50:	00003a79 	.word	0x00003a79
    3d54:	007fffff 	.word	0x007fffff

00003d58 <rtc_nrf_isr>:
{
    3d58:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    return p_reg->INTENSET & mask;
    3d5c:	4c35      	ldr	r4, [pc, #212]	; (3e34 <rtc_nrf_isr+0xdc>)
    3d5e:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    3d62:	079a      	lsls	r2, r3, #30
    3d64:	d50b      	bpl.n	3d7e <rtc_nrf_isr+0x26>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3d66:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    3d6a:	b143      	cbz	r3, 3d7e <rtc_nrf_isr+0x26>
		overflow_cnt++;
    3d6c:	4a32      	ldr	r2, [pc, #200]	; (3e38 <rtc_nrf_isr+0xe0>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3d6e:	2300      	movs	r3, #0
    3d70:	f8c4 3104 	str.w	r3, [r4, #260]	; 0x104
    3d74:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    3d78:	6813      	ldr	r3, [r2, #0]
    3d7a:	3301      	adds	r3, #1
    3d7c:	6013      	str	r3, [r2, #0]
	__asm__ volatile(
    3d7e:	f04f 0320 	mov.w	r3, #32
    3d82:	f3ef 8211 	mrs	r2, BASEPRI
    3d86:	f383 8812 	msr	BASEPRI_MAX, r3
    3d8a:	f3bf 8f6f 	isb	sy
    return p_reg->INTENSET & mask;
    3d8e:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    3d92:	03db      	lsls	r3, r3, #15
    3d94:	d512      	bpl.n	3dbc <rtc_nrf_isr+0x64>
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    3d96:	f3bf 8f5b 	dmb	ish
    3d9a:	4b28      	ldr	r3, [pc, #160]	; (3e3c <rtc_nrf_isr+0xe4>)
    3d9c:	e853 1f00 	ldrex	r1, [r3]
    3da0:	f021 0001 	bic.w	r0, r1, #1
    3da4:	e843 0600 	strex	r6, r0, [r3]
    3da8:	2e00      	cmp	r6, #0
    3daa:	d1f7      	bne.n	3d9c <rtc_nrf_isr+0x44>
    3dac:	f3bf 8f5b 	dmb	ish
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    3db0:	2900      	cmp	r1, #0
    3db2:	d136      	bne.n	3e22 <rtc_nrf_isr+0xca>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3db4:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
		if (result) {
    3db8:	2b00      	cmp	r3, #0
    3dba:	d132      	bne.n	3e22 <rtc_nrf_isr+0xca>
{
    3dbc:	2300      	movs	r3, #0
	__asm__ volatile(
    3dbe:	f382 8811 	msr	BASEPRI, r2
    3dc2:	f3bf 8f6f 	isb	sy
	if (channel_processing_check_and_clear(chan)) {
    3dc6:	b34b      	cbz	r3, 3e1c <rtc_nrf_isr+0xc4>
		curr_time = z_nrf_rtc_timer_read();
    3dc8:	f7ff fec0 	bl	3b4c <z_nrf_rtc_timer_read>
	__asm__ volatile(
    3dcc:	f04f 0320 	mov.w	r3, #32
    3dd0:	f3ef 8c11 	mrs	ip, BASEPRI
    3dd4:	f383 8812 	msr	BASEPRI_MAX, r3
    3dd8:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    3ddc:	4b18      	ldr	r3, [pc, #96]	; (3e40 <rtc_nrf_isr+0xe8>)
    3dde:	e9d3 6702 	ldrd	r6, r7, [r3, #8]
		if (curr_time >= expire_time) {
    3de2:	42b0      	cmp	r0, r6
    3de4:	eb71 0207 	sbcs.w	r2, r1, r7
    3de8:	f04f 0200 	mov.w	r2, #0
    3dec:	d320      	bcc.n	3e30 <rtc_nrf_isr+0xd8>
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    3dee:	f04f 38ff 	mov.w	r8, #4294967295
    3df2:	f04f 39ff 	mov.w	r9, #4294967295
			user_context = cc_data[chan].user_context;
    3df6:	e9d3 1500 	ldrd	r1, r5, [r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    3dfa:	e9c3 8902 	strd	r8, r9, [r3, #8]
			cc_data[chan].callback = NULL;
    3dfe:	601a      	str	r2, [r3, #0]
    p_reg->EVTENCLR = mask;
    3e00:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    3e04:	f8c4 3348 	str.w	r3, [r4, #840]	; 0x348
	__asm__ volatile(
    3e08:	f38c 8811 	msr	BASEPRI, ip
    3e0c:	f3bf 8f6f 	isb	sy
		if (handler) {
    3e10:	b121      	cbz	r1, 3e1c <rtc_nrf_isr+0xc4>
			handler(chan, expire_time, user_context);
    3e12:	9500      	str	r5, [sp, #0]
    3e14:	4632      	mov	r2, r6
    3e16:	463b      	mov	r3, r7
    3e18:	2000      	movs	r0, #0
    3e1a:	4788      	blx	r1
}
    3e1c:	b003      	add	sp, #12
    3e1e:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3e22:	2300      	movs	r3, #0
    3e24:	f8c4 3140 	str.w	r3, [r4, #320]	; 0x140
    3e28:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    3e2c:	2301      	movs	r3, #1
}
    3e2e:	e7c6      	b.n	3dbe <rtc_nrf_isr+0x66>
		z_nrf_rtc_timer_compare_handler_t handler = NULL;
    3e30:	4611      	mov	r1, r2
    3e32:	e7e9      	b.n	3e08 <rtc_nrf_isr+0xb0>
    3e34:	40011000 	.word	0x40011000
    3e38:	200012c8 	.word	0x200012c8
    3e3c:	200012c0 	.word	0x200012c0
    3e40:	200000f0 	.word	0x200000f0

00003e44 <sys_clock_set_timeout>:
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    3e44:	1c43      	adds	r3, r0, #1
{
    3e46:	b513      	push	{r0, r1, r4, lr}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    3e48:	d021      	beq.n	3e8e <sys_clock_set_timeout+0x4a>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    3e4a:	2801      	cmp	r0, #1
    3e4c:	dd21      	ble.n	3e92 <sys_clock_set_timeout+0x4e>
    3e4e:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    3e52:	da20      	bge.n	3e96 <sys_clock_set_timeout+0x52>
    3e54:	1e44      	subs	r4, r0, #1
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    3e56:	f7ff fe79 	bl	3b4c <z_nrf_rtc_timer_read>
    3e5a:	4b10      	ldr	r3, [pc, #64]	; (3e9c <sys_clock_set_timeout+0x58>)
    3e5c:	e9d3 1300 	ldrd	r1, r3, [r3]
    3e60:	1a40      	subs	r0, r0, r1
		ticks = 0;
    3e62:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    3e66:	bf28      	it	cs
    3e68:	2400      	movcs	r4, #0
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    3e6a:	3001      	adds	r0, #1
    3e6c:	1902      	adds	r2, r0, r4
	uint64_t target_time = cyc + last_count;
    3e6e:	480c      	ldr	r0, [pc, #48]	; (3ea0 <sys_clock_set_timeout+0x5c>)
    3e70:	4282      	cmp	r2, r0
    3e72:	bf28      	it	cs
    3e74:	4602      	movcs	r2, r0
    3e76:	1852      	adds	r2, r2, r1
    3e78:	f04f 0000 	mov.w	r0, #0
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    3e7c:	4909      	ldr	r1, [pc, #36]	; (3ea4 <sys_clock_set_timeout+0x60>)
    3e7e:	9001      	str	r0, [sp, #4]
    3e80:	9100      	str	r1, [sp, #0]
    3e82:	f143 0300 	adc.w	r3, r3, #0
    3e86:	f7ff fe83 	bl	3b90 <compare_set>
}
    3e8a:	b002      	add	sp, #8
    3e8c:	bd10      	pop	{r4, pc}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    3e8e:	4804      	ldr	r0, [pc, #16]	; (3ea0 <sys_clock_set_timeout+0x5c>)
    3e90:	e7e0      	b.n	3e54 <sys_clock_set_timeout+0x10>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    3e92:	2400      	movs	r4, #0
    3e94:	e7df      	b.n	3e56 <sys_clock_set_timeout+0x12>
    3e96:	4c02      	ldr	r4, [pc, #8]	; (3ea0 <sys_clock_set_timeout+0x5c>)
    3e98:	e7dd      	b.n	3e56 <sys_clock_set_timeout+0x12>
    3e9a:	bf00      	nop
    3e9c:	20000100 	.word	0x20000100
    3ea0:	007fffff 	.word	0x007fffff
    3ea4:	00003a79 	.word	0x00003a79

00003ea8 <sys_clock_elapsed>:
{
    3ea8:	b508      	push	{r3, lr}
	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    3eaa:	f7ff fe4f 	bl	3b4c <z_nrf_rtc_timer_read>
    3eae:	4b02      	ldr	r3, [pc, #8]	; (3eb8 <sys_clock_elapsed+0x10>)
    3eb0:	681b      	ldr	r3, [r3, #0]
}
    3eb2:	1ac0      	subs	r0, r0, r3
    3eb4:	bd08      	pop	{r3, pc}
    3eb6:	bf00      	nop
    3eb8:	20000100 	.word	0x20000100

00003ebc <k_sys_fatal_error_handler>:
	defined(CONFIG_SPM_SERVICE_NS_HANDLER_FROM_SPM_FAULT)
	z_spm_ns_fatal_error_handler();
#endif

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
    3ebc:	4803      	ldr	r0, [pc, #12]	; (3ecc <k_sys_fatal_error_handler+0x10>)
{
    3ebe:	b508      	push	{r3, lr}
		LOG_ERR("Resetting system");
    3ec0:	2145      	movs	r1, #69	; 0x45
    3ec2:	f001 ffbc 	bl	5e3e <z_log_minimal_printk>
		sys_arch_reboot(0);
    3ec6:	2000      	movs	r0, #0
    3ec8:	f7ff f89a 	bl	3000 <sys_arch_reboot>
		for (;;) {
			/* Spin endlessly */
		}
	}

	CODE_UNREACHABLE;
    3ecc:	00009a40 	.word	0x00009a40

00003ed0 <boot_write_magic>:
    return rc;
}

int
boot_write_magic(const struct flash_area *fap)
{
    3ed0:	b530      	push	{r4, r5, lr}
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    3ed2:	6881      	ldr	r1, [r0, #8]
{
    3ed4:	b085      	sub	sp, #20
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    3ed6:	3910      	subs	r1, #16
     * returned by boot_magic_off() is the start of magic which is not the
     * start of the flash write boundary and thus writes to the magic will fail.
     * To account for this change, write to magic is first padded with 0xFF
     * before writing to the trailer.
     */
    pad_off = ALIGN_DOWN(off, BOOT_MAX_ALIGN);
    3ed8:	f021 0407 	bic.w	r4, r1, #7
{
    3edc:	4605      	mov	r5, r0

    erased_val = flash_area_erased_val(fap);
    3ede:	f002 f814 	bl	5f0a <flash_area_erased_val>

    memset(&magic[0], erased_val, sizeof(magic));
    3ee2:	2210      	movs	r2, #16
    erased_val = flash_area_erased_val(fap);
    3ee4:	4601      	mov	r1, r0
    memset(&magic[0], erased_val, sizeof(magic));
    3ee6:	4668      	mov	r0, sp
    3ee8:	f002 fb0b 	bl	6502 <memset>
    memcpy(&magic[BOOT_MAGIC_ALIGN_SIZE - BOOT_MAGIC_SZ], BOOT_IMG_MAGIC, BOOT_MAGIC_SZ);
    3eec:	4907      	ldr	r1, [pc, #28]	; (3f0c <boot_write_magic+0x3c>)
    3eee:	2210      	movs	r2, #16
    3ef0:	4668      	mov	r0, sp
    3ef2:	f002 fafb 	bl	64ec <memcpy>

    BOOT_LOG_DBG("writing magic; fa_id=%d off=0x%lx (0x%lx)",
                 flash_area_get_id(fap), (unsigned long)off,
                 (unsigned long)(flash_area_get_off(fap) + off));
    rc = flash_area_write(fap, pad_off, &magic[0], BOOT_MAGIC_ALIGN_SIZE);
    3ef6:	2310      	movs	r3, #16
    3ef8:	466a      	mov	r2, sp
    3efa:	4621      	mov	r1, r4
    3efc:	4628      	mov	r0, r5
    3efe:	f001 ffc8 	bl	5e92 <flash_area_write>
    if (rc != 0) {
        return BOOT_EFLASH;
    }

    return 0;
}
    3f02:	3800      	subs	r0, #0
    3f04:	bf18      	it	ne
    3f06:	2001      	movne	r0, #1
    3f08:	b005      	add	sp, #20
    3f0a:	bd30      	pop	{r4, r5, pc}
    3f0c:	00008c90 	.word	0x00008c90

00003f10 <boot_read_swap_state>:
{
    3f10:	b530      	push	{r4, r5, lr}
    3f12:	460c      	mov	r4, r1
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    3f14:	6881      	ldr	r1, [r0, #8]
{
    3f16:	b087      	sub	sp, #28
    rc = flash_area_read(fap, off, magic, BOOT_MAGIC_SZ);
    3f18:	2310      	movs	r3, #16
    3f1a:	aa02      	add	r2, sp, #8
    3f1c:	3910      	subs	r1, #16
{
    3f1e:	4605      	mov	r5, r0
    rc = flash_area_read(fap, off, magic, BOOT_MAGIC_SZ);
    3f20:	f001 ff9b 	bl	5e5a <flash_area_read>
    if (rc < 0) {
    3f24:	2800      	cmp	r0, #0
    3f26:	da02      	bge.n	3f2e <boot_read_swap_state+0x1e>
        return BOOT_EFLASH;
    3f28:	2001      	movs	r0, #1
}
    3f2a:	b007      	add	sp, #28
    3f2c:	bd30      	pop	{r4, r5, pc}
    if (buffer == NULL || len == 0) {
    3f2e:	2210      	movs	r2, #16
    3f30:	a902      	add	r1, sp, #8
    3f32:	4628      	mov	r0, r5
    3f34:	f002 fed0 	bl	6cd8 <bootutil_buffer_is_erased.part.0>
    if (bootutil_buffer_is_erased(fap, magic, BOOT_MAGIC_SZ)) {
    3f38:	b390      	cbz	r0, 3fa0 <boot_read_swap_state+0x90>
        state->magic = BOOT_MAGIC_UNSET;
    3f3a:	2303      	movs	r3, #3
        state->magic = boot_magic_decode(magic);
    3f3c:	7023      	strb	r3, [r4, #0]
    off = boot_swap_info_off(fap);
    3f3e:	4628      	mov	r0, r5
    3f40:	f002 fedb 	bl	6cfa <boot_swap_info_off>
    rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    3f44:	2301      	movs	r3, #1
    off = boot_swap_info_off(fap);
    3f46:	4601      	mov	r1, r0
    rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    3f48:	f10d 0207 	add.w	r2, sp, #7
    3f4c:	4628      	mov	r0, r5
    3f4e:	f001 ff84 	bl	5e5a <flash_area_read>
    if (rc < 0) {
    3f52:	2800      	cmp	r0, #0
    3f54:	dbe8      	blt.n	3f28 <boot_read_swap_state+0x18>
    state->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    3f56:	f89d 3007 	ldrb.w	r3, [sp, #7]
    3f5a:	f003 020f 	and.w	r2, r3, #15
    state->image_num = BOOT_GET_IMAGE_NUM(swap_info);
    3f5e:	091b      	lsrs	r3, r3, #4
    state->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    3f60:	7062      	strb	r2, [r4, #1]
    state->image_num = BOOT_GET_IMAGE_NUM(swap_info);
    3f62:	7123      	strb	r3, [r4, #4]
    if (buffer == NULL || len == 0) {
    3f64:	2201      	movs	r2, #1
    3f66:	f10d 0107 	add.w	r1, sp, #7
    3f6a:	4628      	mov	r0, r5
    3f6c:	f002 feb4 	bl	6cd8 <bootutil_buffer_is_erased.part.0>
    if (bootutil_buffer_is_erased(fap, &swap_info, sizeof swap_info) ||
    3f70:	b910      	cbnz	r0, 3f78 <boot_read_swap_state+0x68>
    3f72:	7863      	ldrb	r3, [r4, #1]
    3f74:	2b04      	cmp	r3, #4
    3f76:	d903      	bls.n	3f80 <boot_read_swap_state+0x70>
        state->swap_type = BOOT_SWAP_TYPE_NONE;
    3f78:	2301      	movs	r3, #1
    3f7a:	7063      	strb	r3, [r4, #1]
        state->image_num = 0;
    3f7c:	2300      	movs	r3, #0
    3f7e:	7123      	strb	r3, [r4, #4]
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    3f80:	68aa      	ldr	r2, [r5, #8]
    3f82:	3a18      	subs	r2, #24
    3f84:	f022 0207 	bic.w	r2, r2, #7
    return boot_read_flag(fap, copy_done, boot_copy_done_off(fap));
    3f88:	3a08      	subs	r2, #8
    3f8a:	1ca1      	adds	r1, r4, #2
    3f8c:	4628      	mov	r0, r5
    3f8e:	f002 fece 	bl	6d2e <boot_read_flag>
    if (rc) {
    3f92:	2800      	cmp	r0, #0
    3f94:	d1c8      	bne.n	3f28 <boot_read_swap_state+0x18>
    return boot_read_image_ok(fap, &state->image_ok);
    3f96:	1ce1      	adds	r1, r4, #3
    3f98:	4628      	mov	r0, r5
    3f9a:	f002 ff22 	bl	6de2 <boot_read_image_ok>
    3f9e:	e7c4      	b.n	3f2a <boot_read_swap_state+0x1a>
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
    3fa0:	4904      	ldr	r1, [pc, #16]	; (3fb4 <boot_read_swap_state+0xa4>)
    3fa2:	2210      	movs	r2, #16
    3fa4:	a802      	add	r0, sp, #8
    3fa6:	f002 fa78 	bl	649a <memcmp>
        return BOOT_MAGIC_GOOD;
    3faa:	2800      	cmp	r0, #0
    3fac:	bf14      	ite	ne
    3fae:	2302      	movne	r3, #2
    3fb0:	2301      	moveq	r3, #1
    3fb2:	e7c3      	b.n	3f3c <boot_read_swap_state+0x2c>
    3fb4:	00008c90 	.word	0x00008c90

00003fb8 <boot_swap_type_multi>:
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
}

int
boot_swap_type_multi(int image_index)
{
    3fb8:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    3fbc:	b085      	sub	sp, #20
    3fbe:	4606      	mov	r6, r0

    rc = BOOT_HOOK_CALL(boot_read_swap_state_primary_slot_hook,
                        BOOT_HOOK_REGULAR, image_index, &primary_slot);
    if (rc == BOOT_HOOK_REGULAR)
    {
        rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
    3fc0:	4669      	mov	r1, sp
    3fc2:	2002      	movs	r0, #2
    3fc4:	f002 ff13 	bl	6dee <boot_read_swap_state_by_id>
                                        &primary_slot);
    }
    if (rc) {
    3fc8:	4605      	mov	r5, r0
    3fca:	b118      	cbz	r0, 3fd4 <boot_swap_type_multi+0x1c>
        return BOOT_SWAP_TYPE_PANIC;
    3fcc:	20ff      	movs	r0, #255	; 0xff
        }
    }

    BOOT_LOG_INF("Swap type: none");
    return BOOT_SWAP_TYPE_NONE;
}
    3fce:	b005      	add	sp, #20
    3fd0:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    3fd4:	a902      	add	r1, sp, #8
    3fd6:	2005      	movs	r0, #5
    3fd8:	f002 ff09 	bl	6dee <boot_read_swap_state_by_id>
    if (rc == BOOT_EFLASH) {
    3fdc:	2801      	cmp	r0, #1
    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    3fde:	4604      	mov	r4, r0
    if (rc == BOOT_EFLASH) {
    3fe0:	d13f      	bne.n	4062 <boot_swap_type_multi+0xaa>
        BOOT_LOG_INF("Secondary image of image pair (%d.) "
    3fe2:	482d      	ldr	r0, [pc, #180]	; (4098 <boot_swap_type_multi+0xe0>)
    3fe4:	4632      	mov	r2, r6
    3fe6:	2149      	movs	r1, #73	; 0x49
    3fe8:	f001 ff29 	bl	5e3e <z_log_minimal_printk>
        secondary_slot.magic = BOOT_MAGIC_UNSET;
    3fec:	2303      	movs	r3, #3
    3fee:	f88d 3008 	strb.w	r3, [sp, #8]
        secondary_slot.swap_type = BOOT_SWAP_TYPE_NONE;
    3ff2:	f88d 4009 	strb.w	r4, [sp, #9]
        secondary_slot.copy_done = BOOT_FLAG_UNSET;
    3ff6:	f88d 300a 	strb.w	r3, [sp, #10]
        secondary_slot.image_ok = BOOT_FLAG_UNSET;
    3ffa:	f88d 300b 	strb.w	r3, [sp, #11]
        secondary_slot.image_num = 0;
    3ffe:	f88d 500c 	strb.w	r5, [sp, #12]
        if (boot_magic_compatible_check(table->magic_primary_slot,
    4002:	f89d 5000 	ldrb.w	r5, [sp]
            boot_magic_compatible_check(table->magic_secondary_slot,
    4006:	f89d 6008 	ldrb.w	r6, [sp, #8]
                table->image_ok_primary_slot == primary_slot.image_ok) &&
    400a:	f89d 7003 	ldrb.w	r7, [sp, #3]
                table->image_ok_secondary_slot == secondary_slot.image_ok) &&
    400e:	f89d 800b 	ldrb.w	r8, [sp, #11]
                table->copy_done_primary_slot == primary_slot.copy_done)) {
    4012:	f89d 9002 	ldrb.w	r9, [sp, #2]
    4016:	4c21      	ldr	r4, [pc, #132]	; (409c <boot_swap_type_multi+0xe4>)
    4018:	2200      	movs	r2, #0
        if (boot_magic_compatible_check(table->magic_primary_slot,
    401a:	7820      	ldrb	r0, [r4, #0]
    401c:	4629      	mov	r1, r5
    401e:	f002 fe72 	bl	6d06 <boot_magic_compatible_check>
    4022:	b318      	cbz	r0, 406c <boot_swap_type_multi+0xb4>
            boot_magic_compatible_check(table->magic_secondary_slot,
    4024:	7860      	ldrb	r0, [r4, #1]
    4026:	4631      	mov	r1, r6
    4028:	f002 fe6d 	bl	6d06 <boot_magic_compatible_check>
                                        primary_slot.magic) &&
    402c:	b1f0      	cbz	r0, 406c <boot_swap_type_multi+0xb4>
            (table->image_ok_primary_slot == BOOT_FLAG_ANY   ||
    402e:	78a3      	ldrb	r3, [r4, #2]
                                        secondary_slot.magic) &&
    4030:	2b04      	cmp	r3, #4
    4032:	d001      	beq.n	4038 <boot_swap_type_multi+0x80>
            (table->image_ok_primary_slot == BOOT_FLAG_ANY   ||
    4034:	42bb      	cmp	r3, r7
    4036:	d119      	bne.n	406c <boot_swap_type_multi+0xb4>
            (table->image_ok_secondary_slot == BOOT_FLAG_ANY ||
    4038:	78e3      	ldrb	r3, [r4, #3]
                table->image_ok_primary_slot == primary_slot.image_ok) &&
    403a:	2b04      	cmp	r3, #4
    403c:	d001      	beq.n	4042 <boot_swap_type_multi+0x8a>
            (table->image_ok_secondary_slot == BOOT_FLAG_ANY ||
    403e:	4543      	cmp	r3, r8
    4040:	d114      	bne.n	406c <boot_swap_type_multi+0xb4>
            (table->copy_done_primary_slot == BOOT_FLAG_ANY  ||
    4042:	7923      	ldrb	r3, [r4, #4]
                table->image_ok_secondary_slot == secondary_slot.image_ok) &&
    4044:	2b04      	cmp	r3, #4
    4046:	d10f      	bne.n	4068 <boot_swap_type_multi+0xb0>
            BOOT_LOG_INF("Swap type: %s",
    4048:	7963      	ldrb	r3, [r4, #5]
    404a:	2b02      	cmp	r3, #2
    404c:	d119      	bne.n	4082 <boot_swap_type_multi+0xca>
    404e:	4a14      	ldr	r2, [pc, #80]	; (40a0 <boot_swap_type_multi+0xe8>)
    4050:	4814      	ldr	r0, [pc, #80]	; (40a4 <boot_swap_type_multi+0xec>)
    4052:	2149      	movs	r1, #73	; 0x49
    4054:	f001 fef3 	bl	5e3e <z_log_minimal_printk>
            if (table->swap_type != BOOT_SWAP_TYPE_TEST &&
    4058:	7960      	ldrb	r0, [r4, #5]
    405a:	1e83      	subs	r3, r0, #2
    405c:	2b02      	cmp	r3, #2
    405e:	d9b6      	bls.n	3fce <boot_swap_type_multi+0x16>
    4060:	e7b4      	b.n	3fcc <boot_swap_type_multi+0x14>
    } else if (rc) {
    4062:	2800      	cmp	r0, #0
    4064:	d0cd      	beq.n	4002 <boot_swap_type_multi+0x4a>
    4066:	e7b1      	b.n	3fcc <boot_swap_type_multi+0x14>
            (table->copy_done_primary_slot == BOOT_FLAG_ANY  ||
    4068:	454b      	cmp	r3, r9
    406a:	d0ed      	beq.n	4048 <boot_swap_type_multi+0x90>
    for (i = 0; i < BOOT_SWAP_TABLES_COUNT; i++) {
    406c:	3201      	adds	r2, #1
    406e:	2a03      	cmp	r2, #3
    4070:	f104 0406 	add.w	r4, r4, #6
    4074:	d1d1      	bne.n	401a <boot_swap_type_multi+0x62>
    BOOT_LOG_INF("Swap type: none");
    4076:	480c      	ldr	r0, [pc, #48]	; (40a8 <boot_swap_type_multi+0xf0>)
    4078:	2149      	movs	r1, #73	; 0x49
    407a:	f001 fee0 	bl	5e3e <z_log_minimal_printk>
    return BOOT_SWAP_TYPE_NONE;
    407e:	2001      	movs	r0, #1
    4080:	e7a5      	b.n	3fce <boot_swap_type_multi+0x16>
            BOOT_LOG_INF("Swap type: %s",
    4082:	2b03      	cmp	r3, #3
    4084:	d005      	beq.n	4092 <boot_swap_type_multi+0xda>
    4086:	4a09      	ldr	r2, [pc, #36]	; (40ac <boot_swap_type_multi+0xf4>)
    4088:	4909      	ldr	r1, [pc, #36]	; (40b0 <boot_swap_type_multi+0xf8>)
    408a:	2b04      	cmp	r3, #4
    408c:	bf18      	it	ne
    408e:	460a      	movne	r2, r1
    4090:	e7de      	b.n	4050 <boot_swap_type_multi+0x98>
    4092:	4a08      	ldr	r2, [pc, #32]	; (40b4 <boot_swap_type_multi+0xfc>)
    4094:	e7dc      	b.n	4050 <boot_swap_type_multi+0x98>
    4096:	bf00      	nop
    4098:	00009a85 	.word	0x00009a85
    409c:	00009af8 	.word	0x00009af8
    40a0:	00009a69 	.word	0x00009a69
    40a4:	00009ad0 	.word	0x00009ad0
    40a8:	00009ae3 	.word	0x00009ae3
    40ac:	00009a62 	.word	0x00009a62
    40b0:	00009a73 	.word	0x00009a73
    40b4:	00009a6e 	.word	0x00009a6e

000040b8 <verify_header>:
}
#endif /* MBEDTLS_MEMORY_DEBUG */

static int verify_header( memory_header *hdr )
{
    if( hdr->magic1 != MAGIC1 )
    40b8:	6801      	ldr	r1, [r0, #0]
    40ba:	4a0e      	ldr	r2, [pc, #56]	; (40f4 <verify_header+0x3c>)
    40bc:	4291      	cmp	r1, r2
{
    40be:	4603      	mov	r3, r0
    if( hdr->magic1 != MAGIC1 )
    40c0:	d115      	bne.n	40ee <verify_header+0x36>
        mbedtls_fprintf( stderr, "FATAL: MAGIC1 mismatch\n" );
#endif
        return( 1 );
    }

    if( hdr->magic2 != MAGIC2 )
    40c2:	69c1      	ldr	r1, [r0, #28]
    40c4:	f1a2 2210 	sub.w	r2, r2, #268439552	; 0x10001000
    40c8:	f1a2 12ef 	sub.w	r2, r2, #15663343	; 0xef00ef
    40cc:	4291      	cmp	r1, r2
    40ce:	d10e      	bne.n	40ee <verify_header+0x36>
        mbedtls_fprintf( stderr, "FATAL: MAGIC2 mismatch\n" );
#endif
        return( 1 );
    }

    if( hdr->alloc > 1 )
    40d0:	6882      	ldr	r2, [r0, #8]
    40d2:	2a01      	cmp	r2, #1
    40d4:	d80b      	bhi.n	40ee <verify_header+0x36>
        mbedtls_fprintf( stderr, "FATAL: alloc has illegal value\n" );
#endif
        return( 1 );
    }

    if( hdr->prev != NULL && hdr->prev == hdr->next )
    40d6:	68c2      	ldr	r2, [r0, #12]
    40d8:	b112      	cbz	r2, 40e0 <verify_header+0x28>
    40da:	6901      	ldr	r1, [r0, #16]
    40dc:	428a      	cmp	r2, r1
    40de:	d006      	beq.n	40ee <verify_header+0x36>
        mbedtls_fprintf( stderr, "FATAL: prev == next\n" );
#endif
        return( 1 );
    }

    if( hdr->prev_free != NULL && hdr->prev_free == hdr->next_free )
    40e0:	6958      	ldr	r0, [r3, #20]
    40e2:	b128      	cbz	r0, 40f0 <verify_header+0x38>
    40e4:	699b      	ldr	r3, [r3, #24]
    40e6:	1a1b      	subs	r3, r3, r0
    40e8:	4258      	negs	r0, r3
    40ea:	4158      	adcs	r0, r3
    40ec:	4770      	bx	lr
        return( 1 );
    40ee:	2001      	movs	r0, #1
#endif
        return( 1 );
    }

    return( 0 );
}
    40f0:	4770      	bx	lr
    40f2:	bf00      	nop
    40f4:	ff00aa55 	.word	0xff00aa55

000040f8 <verify_chain>:

static int verify_chain( void )
{
    memory_header *prv = heap.first, *cur;
    40f8:	4b0d      	ldr	r3, [pc, #52]	; (4130 <verify_chain+0x38>)
{
    40fa:	b570      	push	{r4, r5, r6, lr}
    memory_header *prv = heap.first, *cur;
    40fc:	689e      	ldr	r6, [r3, #8]

    if( prv == NULL || verify_header( prv ) != 0 )
    40fe:	b1a6      	cbz	r6, 412a <verify_chain+0x32>
    4100:	4630      	mov	r0, r6
    4102:	f7ff ffd9 	bl	40b8 <verify_header>
    4106:	4604      	mov	r4, r0
    4108:	b978      	cbnz	r0, 412a <verify_chain+0x32>
                                  "failed\n" );
#endif
        return( 1 );
    }

    if( heap.first->prev != NULL )
    410a:	68f3      	ldr	r3, [r6, #12]
    410c:	b96b      	cbnz	r3, 412a <verify_chain+0x32>
                                  "first->prev != NULL\n" );
#endif
        return( 1 );
    }

    cur = heap.first->next;
    410e:	6935      	ldr	r5, [r6, #16]

    while( cur != NULL )
    4110:	b90d      	cbnz	r5, 4116 <verify_chain+0x1e>
        prv = cur;
        cur = cur->next;
    }

    return( 0 );
}
    4112:	4620      	mov	r0, r4
    4114:	bd70      	pop	{r4, r5, r6, pc}
        if( verify_header( cur ) != 0 )
    4116:	4628      	mov	r0, r5
    4118:	f7ff ffce 	bl	40b8 <verify_header>
    411c:	b928      	cbnz	r0, 412a <verify_chain+0x32>
        if( cur->prev != prv )
    411e:	68eb      	ldr	r3, [r5, #12]
    4120:	42b3      	cmp	r3, r6
    4122:	d102      	bne.n	412a <verify_chain+0x32>
        cur = cur->next;
    4124:	462e      	mov	r6, r5
    4126:	692d      	ldr	r5, [r5, #16]
    4128:	e7f2      	b.n	4110 <verify_chain+0x18>
        return( 1 );
    412a:	2401      	movs	r4, #1
    412c:	e7f1      	b.n	4112 <verify_chain+0x1a>
    412e:	bf00      	nop
    4130:	200012cc 	.word	0x200012cc

00004134 <buffer_alloc_calloc>:

static void *buffer_alloc_calloc( size_t n, size_t size )
{
    4134:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
#if defined(MBEDTLS_MEMORY_BACKTRACE)
    void *trace_buffer[MAX_BT];
    size_t trace_cnt;
#endif

    if( heap.buf == NULL || heap.first == NULL )
    4138:	4f40      	ldr	r7, [pc, #256]	; (423c <buffer_alloc_calloc+0x108>)
    413a:	683c      	ldr	r4, [r7, #0]
    413c:	b1d4      	cbz	r4, 4174 <buffer_alloc_calloc+0x40>
    413e:	68bc      	ldr	r4, [r7, #8]
    4140:	b1c4      	cbz	r4, 4174 <buffer_alloc_calloc+0x40>
        return( NULL );

    original_len = len = n * size;

    if( n == 0 || size == 0 || len / n != size )
    4142:	2800      	cmp	r0, #0
    4144:	d04d      	beq.n	41e2 <buffer_alloc_calloc+0xae>
    4146:	2900      	cmp	r1, #0
    4148:	d04b      	beq.n	41e2 <buffer_alloc_calloc+0xae>
    original_len = len = n * size;
    414a:	fb01 f500 	mul.w	r5, r1, r0
    if( n == 0 || size == 0 || len / n != size )
    414e:	fbb5 f0f0 	udiv	r0, r5, r0
    4152:	4288      	cmp	r0, r1
    4154:	d145      	bne.n	41e2 <buffer_alloc_calloc+0xae>
        return( NULL );
    else if( len > (size_t)-MBEDTLS_MEMORY_ALIGN_MULTIPLE )
    4156:	1d28      	adds	r0, r5, #4
    4158:	d843      	bhi.n	41e2 <buffer_alloc_calloc+0xae>
        return( NULL );

    if( len % MBEDTLS_MEMORY_ALIGN_MULTIPLE )
    415a:	07a9      	lsls	r1, r5, #30
    415c:	d00d      	beq.n	417a <buffer_alloc_calloc+0x46>
    {
        len -= len % MBEDTLS_MEMORY_ALIGN_MULTIPLE;
    415e:	f025 0603 	bic.w	r6, r5, #3
        len += MBEDTLS_MEMORY_ALIGN_MULTIPLE;
    4162:	3604      	adds	r6, #4
    memory_header *new, *cur = heap.first_free;
    4164:	68fc      	ldr	r4, [r7, #12]
    4166:	e003      	b.n	4170 <buffer_alloc_calloc+0x3c>

    // Find block that fits
    //
    while( cur != NULL )
    {
        if( cur->size >= len )
    4168:	6863      	ldr	r3, [r4, #4]
    416a:	42b3      	cmp	r3, r6
    416c:	d23b      	bcs.n	41e6 <buffer_alloc_calloc+0xb2>
            break;

        cur = cur->next_free;
    416e:	69a4      	ldr	r4, [r4, #24]
    while( cur != NULL )
    4170:	2c00      	cmp	r4, #0
    4172:	d1f9      	bne.n	4168 <buffer_alloc_calloc+0x34>

    ret = (unsigned char *) cur + sizeof( memory_header );
    memset( ret, 0, original_len );

    return( ret );
}
    4174:	4620      	mov	r0, r4
    4176:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    417a:	462e      	mov	r6, r5
    417c:	e7f2      	b.n	4164 <buffer_alloc_calloc+0x30>
            heap.first_free = cur->next_free;
    417e:	60f8      	str	r0, [r7, #12]
    4180:	e044      	b.n	420c <buffer_alloc_calloc+0xd8>
    p = ( (unsigned char *) cur ) + sizeof(memory_header) + len;
    4182:	f106 0c20 	add.w	ip, r6, #32
    4186:	eb04 030c 	add.w	r3, r4, ip
    new->size = cur->size - len - sizeof(memory_header);
    418a:	3920      	subs	r1, #32
    418c:	6059      	str	r1, [r3, #4]
    new->alloc = 0;
    418e:	2100      	movs	r1, #0
    new->prev = cur;
    4190:	e9c3 1402 	strd	r1, r4, [r3, #8]
    new->magic1 = MAGIC1;
    4194:	f8df e0a8 	ldr.w	lr, [pc, #168]	; 4240 <buffer_alloc_calloc+0x10c>
    new->next = cur->next;
    4198:	6921      	ldr	r1, [r4, #16]
    419a:	6119      	str	r1, [r3, #16]
    new->magic1 = MAGIC1;
    419c:	f844 e00c 	str.w	lr, [r4, ip]
    new->magic2 = MAGIC2;
    41a0:	f8df c0a0 	ldr.w	ip, [pc, #160]	; 4244 <buffer_alloc_calloc+0x110>
    41a4:	f8c3 c01c 	str.w	ip, [r3, #28]
    if( new->next != NULL )
    41a8:	b101      	cbz	r1, 41ac <buffer_alloc_calloc+0x78>
        new->next->prev = new;
    41aa:	60cb      	str	r3, [r1, #12]
    new->next_free = cur->next_free;
    41ac:	e9c3 2005 	strd	r2, r0, [r3, #20]
    if( new->prev_free != NULL )
    41b0:	b1aa      	cbz	r2, 41de <buffer_alloc_calloc+0xaa>
        new->prev_free->next_free = new;
    41b2:	6193      	str	r3, [r2, #24]
    if( new->next_free != NULL )
    41b4:	699a      	ldr	r2, [r3, #24]
    41b6:	b102      	cbz	r2, 41ba <buffer_alloc_calloc+0x86>
        new->next_free->prev_free = new;
    41b8:	6153      	str	r3, [r2, #20]
    cur->next = new;
    41ba:	6123      	str	r3, [r4, #16]
    cur->prev_free = NULL;
    41bc:	2300      	movs	r3, #0
    cur->next_free = NULL;
    41be:	e9c4 3305 	strd	r3, r3, [r4, #20]
    if( ( heap.verify & MBEDTLS_MEMORY_VERIFY_ALLOC ) && verify_chain() != 0 )
    41c2:	693b      	ldr	r3, [r7, #16]
    cur->alloc = 1;
    41c4:	f04f 0901 	mov.w	r9, #1
    if( ( heap.verify & MBEDTLS_MEMORY_VERIFY_ALLOC ) && verify_chain() != 0 )
    41c8:	07db      	lsls	r3, r3, #31
    cur->size = len;
    41ca:	e9c4 6901 	strd	r6, r9, [r4, #4]
    if( ( heap.verify & MBEDTLS_MEMORY_VERIFY_ALLOC ) && verify_chain() != 0 )
    41ce:	d52d      	bpl.n	422c <buffer_alloc_calloc+0xf8>
    41d0:	f7ff ff92 	bl	40f8 <verify_chain>
    41d4:	b350      	cbz	r0, 422c <buffer_alloc_calloc+0xf8>
        mbedtls_exit( 1 );
    41d6:	4b1c      	ldr	r3, [pc, #112]	; (4248 <buffer_alloc_calloc+0x114>)
    41d8:	4648      	mov	r0, r9
    41da:	681b      	ldr	r3, [r3, #0]
    41dc:	e025      	b.n	422a <buffer_alloc_calloc+0xf6>
        heap.first_free = new;
    41de:	60fb      	str	r3, [r7, #12]
    41e0:	e7e8      	b.n	41b4 <buffer_alloc_calloc+0x80>
        return( NULL );
    41e2:	2400      	movs	r4, #0
    41e4:	e7c6      	b.n	4174 <buffer_alloc_calloc+0x40>
    if( cur->alloc != 0 )
    41e6:	68a3      	ldr	r3, [r4, #8]
    41e8:	b11b      	cbz	r3, 41f2 <buffer_alloc_calloc+0xbe>
        mbedtls_exit( 1 );
    41ea:	4b17      	ldr	r3, [pc, #92]	; (4248 <buffer_alloc_calloc+0x114>)
    41ec:	2001      	movs	r0, #1
    41ee:	681b      	ldr	r3, [r3, #0]
    41f0:	4798      	blx	r3
    if( cur->size - len < sizeof(memory_header) +
    41f2:	6861      	ldr	r1, [r4, #4]
    41f4:	1b89      	subs	r1, r1, r6
    41f6:	2923      	cmp	r1, #35	; 0x23
            cur->prev_free->next_free = cur->next_free;
    41f8:	e9d4 2005 	ldrd	r2, r0, [r4, #20]
    41fc:	f104 0820 	add.w	r8, r4, #32
    if( cur->size - len < sizeof(memory_header) +
    4200:	d8bf      	bhi.n	4182 <buffer_alloc_calloc+0x4e>
        cur->alloc = 1;
    4202:	2301      	movs	r3, #1
    4204:	60a3      	str	r3, [r4, #8]
        if( cur->prev_free != NULL )
    4206:	2a00      	cmp	r2, #0
    4208:	d0b9      	beq.n	417e <buffer_alloc_calloc+0x4a>
            cur->prev_free->next_free = cur->next_free;
    420a:	6190      	str	r0, [r2, #24]
        if( cur->next_free != NULL )
    420c:	69a3      	ldr	r3, [r4, #24]
    420e:	b103      	cbz	r3, 4212 <buffer_alloc_calloc+0xde>
            cur->next_free->prev_free = cur->prev_free;
    4210:	615a      	str	r2, [r3, #20]
        cur->prev_free = NULL;
    4212:	2300      	movs	r3, #0
        cur->next_free = NULL;
    4214:	e9c4 3305 	strd	r3, r3, [r4, #20]
        if( ( heap.verify & MBEDTLS_MEMORY_VERIFY_ALLOC ) && verify_chain() != 0 )
    4218:	693b      	ldr	r3, [r7, #16]
    421a:	07da      	lsls	r2, r3, #31
    421c:	d506      	bpl.n	422c <buffer_alloc_calloc+0xf8>
    421e:	f7ff ff6b 	bl	40f8 <verify_chain>
    4222:	b118      	cbz	r0, 422c <buffer_alloc_calloc+0xf8>
            mbedtls_exit( 1 );
    4224:	4b08      	ldr	r3, [pc, #32]	; (4248 <buffer_alloc_calloc+0x114>)
    4226:	681b      	ldr	r3, [r3, #0]
    4228:	2001      	movs	r0, #1
        mbedtls_exit( 1 );
    422a:	4798      	blx	r3
    memset( ret, 0, original_len );
    422c:	462a      	mov	r2, r5
    422e:	2100      	movs	r1, #0
    4230:	4640      	mov	r0, r8
    ret = (unsigned char *) cur + sizeof( memory_header );
    4232:	4644      	mov	r4, r8
    memset( ret, 0, original_len );
    4234:	f002 f965 	bl	6502 <memset>
    return( ret );
    4238:	e79c      	b.n	4174 <buffer_alloc_calloc+0x40>
    423a:	bf00      	nop
    423c:	200012cc 	.word	0x200012cc
    4240:	ff00aa55 	.word	0xff00aa55
    4244:	ee119966 	.word	0xee119966
    4248:	2000005c 	.word	0x2000005c

0000424c <buffer_alloc_free>:

static void buffer_alloc_free( void *ptr )
{
    424c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    memory_header *hdr, *old = NULL;
    unsigned char *p = (unsigned char *) ptr;

    if( ptr == NULL || heap.buf == NULL || heap.first == NULL )
    4250:	4605      	mov	r5, r0
    4252:	2800      	cmp	r0, #0
    4254:	d07c      	beq.n	4350 <buffer_alloc_free+0x104>
    4256:	4f3f      	ldr	r7, [pc, #252]	; (4354 <buffer_alloc_free+0x108>)
    4258:	683b      	ldr	r3, [r7, #0]
    425a:	2b00      	cmp	r3, #0
    425c:	d078      	beq.n	4350 <buffer_alloc_free+0x104>
    425e:	68ba      	ldr	r2, [r7, #8]
    4260:	2a00      	cmp	r2, #0
    4262:	d075      	beq.n	4350 <buffer_alloc_free+0x104>
        return;

    if( p < heap.buf || p >= heap.buf + heap.len )
    4264:	4283      	cmp	r3, r0
    4266:	d803      	bhi.n	4270 <buffer_alloc_free+0x24>
    4268:	687a      	ldr	r2, [r7, #4]
    426a:	4413      	add	r3, r2
    426c:	4298      	cmp	r0, r3
    426e:	d303      	bcc.n	4278 <buffer_alloc_free+0x2c>
    {
#if defined(MBEDTLS_MEMORY_DEBUG)
        mbedtls_fprintf( stderr, "FATAL: mbedtls_free() outside of managed "
                                  "space\n" );
#endif
        mbedtls_exit( 1 );
    4270:	4b39      	ldr	r3, [pc, #228]	; (4358 <buffer_alloc_free+0x10c>)
    4272:	2001      	movs	r0, #1
    4274:	681b      	ldr	r3, [r3, #0]
    4276:	4798      	blx	r3
    }

    p -= sizeof(memory_header);
    4278:	f1a5 0420 	sub.w	r4, r5, #32
    hdr = (memory_header *) p;

    if( verify_header( hdr ) != 0 )
    427c:	4620      	mov	r0, r4
    427e:	f7ff ff1b 	bl	40b8 <verify_header>
    4282:	b118      	cbz	r0, 428c <buffer_alloc_free+0x40>
        mbedtls_exit( 1 );
    4284:	4b34      	ldr	r3, [pc, #208]	; (4358 <buffer_alloc_free+0x10c>)
    4286:	2001      	movs	r0, #1
    4288:	681b      	ldr	r3, [r3, #0]
    428a:	4798      	blx	r3

    if( hdr->alloc != 1 )
    428c:	f855 3c18 	ldr.w	r3, [r5, #-24]
    4290:	2b01      	cmp	r3, #1
    4292:	d003      	beq.n	429c <buffer_alloc_free+0x50>
    {
#if defined(MBEDTLS_MEMORY_DEBUG)
        mbedtls_fprintf( stderr, "FATAL: mbedtls_free() on unallocated "
                                  "data\n" );
#endif
        mbedtls_exit( 1 );
    4294:	4b30      	ldr	r3, [pc, #192]	; (4358 <buffer_alloc_free+0x10c>)
    4296:	2001      	movs	r0, #1
    4298:	681b      	ldr	r3, [r3, #0]
    429a:	4798      	blx	r3
    hdr->trace_count = 0;
#endif

    // Regroup with block before
    //
    if( hdr->prev != NULL && hdr->prev->alloc == 0 )
    429c:	f855 6c14 	ldr.w	r6, [r5, #-20]
    hdr->alloc = 0;
    42a0:	2300      	movs	r3, #0
    42a2:	f845 3c18 	str.w	r3, [r5, #-24]
    if( hdr->prev != NULL && hdr->prev->alloc == 0 )
    42a6:	b1ae      	cbz	r6, 42d4 <buffer_alloc_free+0x88>
    42a8:	68b2      	ldr	r2, [r6, #8]
    42aa:	b992      	cbnz	r2, 42d2 <buffer_alloc_free+0x86>
    {
#if defined(MBEDTLS_MEMORY_DEBUG)
        heap.header_count--;
#endif
        hdr->prev->size += sizeof(memory_header) + hdr->size;
    42ac:	f855 3c1c 	ldr.w	r3, [r5, #-28]
    42b0:	f103 0220 	add.w	r2, r3, #32
    42b4:	6873      	ldr	r3, [r6, #4]
    42b6:	4413      	add	r3, r2
    42b8:	6073      	str	r3, [r6, #4]
        hdr->prev->next = hdr->next;
    42ba:	f855 3c10 	ldr.w	r3, [r5, #-16]
    42be:	6133      	str	r3, [r6, #16]
        old = hdr;
        hdr = hdr->prev;

        if( hdr->next != NULL )
    42c0:	b103      	cbz	r3, 42c4 <buffer_alloc_free+0x78>
            hdr->next->prev = hdr;
    42c2:	60de      	str	r6, [r3, #12]

        memset( old, 0, sizeof(memory_header) );
    42c4:	4620      	mov	r0, r4
    42c6:	2220      	movs	r2, #32
    42c8:	2100      	movs	r1, #0
    42ca:	f002 f91a 	bl	6502 <memset>
    42ce:	4623      	mov	r3, r4
    42d0:	4634      	mov	r4, r6
    memory_header *hdr, *old = NULL;
    42d2:	461e      	mov	r6, r3
    }

    // Regroup with block after
    //
    if( hdr->next != NULL && hdr->next->alloc == 0 )
    42d4:	6920      	ldr	r0, [r4, #16]
    42d6:	2800      	cmp	r0, #0
    42d8:	d032      	beq.n	4340 <buffer_alloc_free+0xf4>
    42da:	6883      	ldr	r3, [r0, #8]
    42dc:	2b00      	cmp	r3, #0
    42de:	d12f      	bne.n	4340 <buffer_alloc_free+0xf4>
    {
#if defined(MBEDTLS_MEMORY_DEBUG)
        heap.header_count--;
#endif
        hdr->size += sizeof(memory_header) + hdr->next->size;
    42e0:	6863      	ldr	r3, [r4, #4]
    42e2:	6842      	ldr	r2, [r0, #4]
    42e4:	3320      	adds	r3, #32
    42e6:	4413      	add	r3, r2
        old = hdr->next;
        hdr->next = hdr->next->next;

        if( hdr->prev_free != NULL || hdr->next_free != NULL )
    42e8:	e9d4 2105 	ldrd	r2, r1, [r4, #20]
        hdr->size += sizeof(memory_header) + hdr->next->size;
    42ec:	6063      	str	r3, [r4, #4]
        hdr->next = hdr->next->next;
    42ee:	6903      	ldr	r3, [r0, #16]
    42f0:	6123      	str	r3, [r4, #16]
        if( hdr->prev_free != NULL || hdr->next_free != NULL )
    42f2:	b9da      	cbnz	r2, 432c <buffer_alloc_free+0xe0>
    42f4:	bb01      	cbnz	r1, 4338 <buffer_alloc_free+0xec>

            if( hdr->next_free != NULL )
                hdr->next_free->prev_free = hdr->prev_free;
        }

        hdr->prev_free = old->prev_free;
    42f6:	6942      	ldr	r2, [r0, #20]
        hdr->next_free = old->next_free;
    42f8:	6981      	ldr	r1, [r0, #24]
        hdr->prev_free = old->prev_free;
    42fa:	6162      	str	r2, [r4, #20]
        hdr->next_free = old->next_free;
    42fc:	61a1      	str	r1, [r4, #24]

        if( hdr->prev_free != NULL )
    42fe:	b1ea      	cbz	r2, 433c <buffer_alloc_free+0xf0>
            hdr->prev_free->next_free = hdr;
    4300:	6194      	str	r4, [r2, #24]
        else
            heap.first_free = hdr;

        if( hdr->next_free != NULL )
    4302:	69a2      	ldr	r2, [r4, #24]
    4304:	b102      	cbz	r2, 4308 <buffer_alloc_free+0xbc>
            hdr->next_free->prev_free = hdr;
    4306:	6154      	str	r4, [r2, #20]

        if( hdr->next != NULL )
    4308:	b103      	cbz	r3, 430c <buffer_alloc_free+0xc0>
            hdr->next->prev = hdr;
    430a:	60dc      	str	r4, [r3, #12]

        memset( old, 0, sizeof(memory_header) );
    430c:	2220      	movs	r2, #32
    430e:	2100      	movs	r1, #0
    4310:	f002 f8f7 	bl	6502 <memset>
        if( heap.first_free != NULL )
            heap.first_free->prev_free = hdr;
        heap.first_free = hdr;
    }

    if( ( heap.verify & MBEDTLS_MEMORY_VERIFY_FREE ) && verify_chain() != 0 )
    4314:	693b      	ldr	r3, [r7, #16]
    4316:	079b      	lsls	r3, r3, #30
    4318:	d51a      	bpl.n	4350 <buffer_alloc_free+0x104>
    431a:	f7ff feed 	bl	40f8 <verify_chain>
    431e:	b1b8      	cbz	r0, 4350 <buffer_alloc_free+0x104>
        mbedtls_exit( 1 );
    4320:	4b0d      	ldr	r3, [pc, #52]	; (4358 <buffer_alloc_free+0x10c>)
}
    4322:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
        mbedtls_exit( 1 );
    4326:	681b      	ldr	r3, [r3, #0]
    4328:	2001      	movs	r0, #1
    432a:	4718      	bx	r3
                hdr->prev_free->next_free = hdr->next_free;
    432c:	6191      	str	r1, [r2, #24]
            if( hdr->next_free != NULL )
    432e:	69a1      	ldr	r1, [r4, #24]
    4330:	2900      	cmp	r1, #0
    4332:	d0e0      	beq.n	42f6 <buffer_alloc_free+0xaa>
                hdr->next_free->prev_free = hdr->prev_free;
    4334:	614a      	str	r2, [r1, #20]
    4336:	e7de      	b.n	42f6 <buffer_alloc_free+0xaa>
                heap.first_free = hdr->next_free;
    4338:	60f9      	str	r1, [r7, #12]
    433a:	e7f8      	b.n	432e <buffer_alloc_free+0xe2>
            heap.first_free = hdr;
    433c:	60fc      	str	r4, [r7, #12]
    433e:	e7e0      	b.n	4302 <buffer_alloc_free+0xb6>
    if( old == NULL )
    4340:	2e00      	cmp	r6, #0
    4342:	d1e7      	bne.n	4314 <buffer_alloc_free+0xc8>
        hdr->next_free = heap.first_free;
    4344:	68fb      	ldr	r3, [r7, #12]
    4346:	61a3      	str	r3, [r4, #24]
        if( heap.first_free != NULL )
    4348:	b103      	cbz	r3, 434c <buffer_alloc_free+0x100>
            heap.first_free->prev_free = hdr;
    434a:	615c      	str	r4, [r3, #20]
        heap.first_free = hdr;
    434c:	60fc      	str	r4, [r7, #12]
    434e:	e7e1      	b.n	4314 <buffer_alloc_free+0xc8>
}
    4350:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4354:	200012cc 	.word	0x200012cc
    4358:	2000005c 	.word	0x2000005c

0000435c <mbedtls_memory_buffer_alloc_init>:
    (void) mbedtls_mutex_unlock( &heap.mutex );
}
#endif /* MBEDTLS_THREADING_C */

void mbedtls_memory_buffer_alloc_init( unsigned char *buf, size_t len )
{
    435c:	b538      	push	{r3, r4, r5, lr}
    memset( &heap, 0, sizeof( buffer_alloc_ctx ) );
    435e:	2214      	movs	r2, #20
{
    4360:	460d      	mov	r5, r1
    4362:	4604      	mov	r4, r0
    memset( &heap, 0, sizeof( buffer_alloc_ctx ) );
    4364:	2100      	movs	r1, #0
    4366:	4812      	ldr	r0, [pc, #72]	; (43b0 <mbedtls_memory_buffer_alloc_init+0x54>)
    4368:	f002 f8cb 	bl	6502 <memset>
#if defined(MBEDTLS_THREADING_C)
    mbedtls_mutex_init( &heap.mutex );
    mbedtls_platform_set_calloc_free( buffer_alloc_calloc_mutexed,
                              buffer_alloc_free_mutexed );
#else
    mbedtls_platform_set_calloc_free( buffer_alloc_calloc, buffer_alloc_free );
    436c:	4911      	ldr	r1, [pc, #68]	; (43b4 <mbedtls_memory_buffer_alloc_init+0x58>)
    436e:	4812      	ldr	r0, [pc, #72]	; (43b8 <mbedtls_memory_buffer_alloc_init+0x5c>)
    4370:	f000 f832 	bl	43d8 <mbedtls_platform_set_calloc_free>
#endif

    if( len < sizeof( memory_header ) + MBEDTLS_MEMORY_ALIGN_MULTIPLE )
    4374:	2d23      	cmp	r5, #35	; 0x23
    4376:	d91a      	bls.n	43ae <mbedtls_memory_buffer_alloc_init+0x52>
        return;
    else if( (size_t)buf % MBEDTLS_MEMORY_ALIGN_MULTIPLE )
    4378:	f014 0303 	ands.w	r3, r4, #3
    {
        /* Adjust len first since buf is used in the computation */
        len -= MBEDTLS_MEMORY_ALIGN_MULTIPLE
    437c:	bf1f      	itttt	ne
    437e:	3d04      	subne	r5, #4
    4380:	18ed      	addne	r5, r5, r3
             - (size_t)buf % MBEDTLS_MEMORY_ALIGN_MULTIPLE;
        buf += MBEDTLS_MEMORY_ALIGN_MULTIPLE
             - (size_t)buf % MBEDTLS_MEMORY_ALIGN_MULTIPLE;
    4382:	f1c3 0304 	rsbne	r3, r3, #4
        buf += MBEDTLS_MEMORY_ALIGN_MULTIPLE
    4386:	18e4      	addne	r4, r4, r3
    }

    memset( buf, 0, len );
    4388:	462a      	mov	r2, r5
    438a:	2100      	movs	r1, #0
    438c:	4620      	mov	r0, r4
    438e:	f002 f8b8 	bl	6502 <memset>

    heap.buf = buf;
    4392:	4b07      	ldr	r3, [pc, #28]	; (43b0 <mbedtls_memory_buffer_alloc_init+0x54>)
    heap.len = len;

    heap.first = (memory_header *)buf;
    heap.first->size = len - sizeof( memory_header );
    heap.first->magic1 = MAGIC1;
    4394:	4a09      	ldr	r2, [pc, #36]	; (43bc <mbedtls_memory_buffer_alloc_init+0x60>)
    heap.first = (memory_header *)buf;
    4396:	609c      	str	r4, [r3, #8]
    heap.len = len;
    4398:	e9c3 4500 	strd	r4, r5, [r3]
    heap.first->magic1 = MAGIC1;
    439c:	6022      	str	r2, [r4, #0]
    heap.first->magic2 = MAGIC2;
    439e:	f1a2 2210 	sub.w	r2, r2, #268439552	; 0x10001000
    heap.first->size = len - sizeof( memory_header );
    43a2:	3d20      	subs	r5, #32
    heap.first->magic2 = MAGIC2;
    43a4:	f1a2 12ef 	sub.w	r2, r2, #15663343	; 0xef00ef
    heap.first->size = len - sizeof( memory_header );
    43a8:	6065      	str	r5, [r4, #4]
    heap.first->magic2 = MAGIC2;
    43aa:	61e2      	str	r2, [r4, #28]
    heap.first_free = heap.first;
    43ac:	60dc      	str	r4, [r3, #12]
}
    43ae:	bd38      	pop	{r3, r4, r5, pc}
    43b0:	200012cc 	.word	0x200012cc
    43b4:	0000424d 	.word	0x0000424d
    43b8:	00004135 	.word	0x00004135
    43bc:	ff00aa55 	.word	0xff00aa55

000043c0 <mbedtls_calloc>:
void * (*mbedtls_calloc_func)( size_t, size_t ) = MBEDTLS_PLATFORM_STD_CALLOC;
void (*mbedtls_free_func)( void * ) = MBEDTLS_PLATFORM_STD_FREE;

void * mbedtls_calloc( size_t nmemb, size_t size )
{
    return (*mbedtls_calloc_func)( nmemb, size );
    43c0:	4b01      	ldr	r3, [pc, #4]	; (43c8 <mbedtls_calloc+0x8>)
    43c2:	681b      	ldr	r3, [r3, #0]
    43c4:	4718      	bx	r3
    43c6:	bf00      	nop
    43c8:	20000058 	.word	0x20000058

000043cc <mbedtls_free>:
}

void mbedtls_free( void * ptr )
{
    (*mbedtls_free_func)( ptr );
    43cc:	4b01      	ldr	r3, [pc, #4]	; (43d4 <mbedtls_free+0x8>)
    43ce:	681b      	ldr	r3, [r3, #0]
    43d0:	4718      	bx	r3
    43d2:	bf00      	nop
    43d4:	20000060 	.word	0x20000060

000043d8 <mbedtls_platform_set_calloc_free>:
}

int mbedtls_platform_set_calloc_free( void * (*calloc_func)( size_t, size_t ),
                              void (*free_func)( void * ) )
{
    mbedtls_calloc_func = calloc_func;
    43d8:	4b02      	ldr	r3, [pc, #8]	; (43e4 <mbedtls_platform_set_calloc_free+0xc>)
    43da:	6018      	str	r0, [r3, #0]
    mbedtls_free_func = free_func;
    43dc:	4b02      	ldr	r3, [pc, #8]	; (43e8 <mbedtls_platform_set_calloc_free+0x10>)
    return( 0 );
}
    43de:	2000      	movs	r0, #0
    mbedtls_free_func = free_func;
    43e0:	6019      	str	r1, [r3, #0]
}
    43e2:	4770      	bx	lr
    43e4:	20000058 	.word	0x20000058
    43e8:	20000060 	.word	0x20000060

000043ec <mbedtls_platform_zeroize>:

void mbedtls_platform_zeroize( void *buf, size_t len )
{
    MBEDTLS_INTERNAL_VALIDATE( len == 0 || buf != NULL );

    if( len > 0 )
    43ec:	460a      	mov	r2, r1
    43ee:	b119      	cbz	r1, 43f8 <mbedtls_platform_zeroize+0xc>
        memset_func( buf, 0, len );
    43f0:	4b02      	ldr	r3, [pc, #8]	; (43fc <mbedtls_platform_zeroize+0x10>)
    43f2:	2100      	movs	r1, #0
    43f4:	681b      	ldr	r3, [r3, #0]
    43f6:	4718      	bx	r3
}
    43f8:	4770      	bx	lr
    43fa:	bf00      	nop
    43fc:	20000064 	.word	0x20000064

00004400 <rsa_check_context.constprop.0>:
/*
 * Checks whether the context fields are set in such a way
 * that the RSA primitives will be able to execute without error.
 * It does *not* make guarantees for consistency of the parameters.
 */
static int rsa_check_context( mbedtls_rsa_context const *ctx, int is_priv,
    4400:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    /* blinding_needed is only used for NO_CRT to decide whether
     * P,Q need to be present or not. */
    ((void) blinding_needed);
#endif

    if( ctx->len != mbedtls_mpi_size( &ctx->N ) ||
    4402:	f100 0608 	add.w	r6, r0, #8
    4406:	6847      	ldr	r7, [r0, #4]
static int rsa_check_context( mbedtls_rsa_context const *ctx, int is_priv,
    4408:	4604      	mov	r4, r0
    if( ctx->len != mbedtls_mpi_size( &ctx->N ) ||
    440a:	4630      	mov	r0, r6
static int rsa_check_context( mbedtls_rsa_context const *ctx, int is_priv,
    440c:	460d      	mov	r5, r1
    if( ctx->len != mbedtls_mpi_size( &ctx->N ) ||
    440e:	f003 f8d1 	bl	75b4 <mbedtls_mpi_size>
    4412:	4287      	cmp	r7, r0
    4414:	d116      	bne.n	4444 <rsa_check_context.constprop.0+0x44>
    4416:	6863      	ldr	r3, [r4, #4]
    4418:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
    441c:	d812      	bhi.n	4444 <rsa_check_context.constprop.0+0x44>
     * 1. Modular exponentiation needs positive, odd moduli.
     */

    /* Modular exponentiation wrt. N is always used for
     * RSA public key operations. */
    if( mbedtls_mpi_cmp_int( &ctx->N, 0 ) <= 0 ||
    441e:	2100      	movs	r1, #0
    4420:	4630      	mov	r0, r6
    4422:	f003 fa26 	bl	7872 <mbedtls_mpi_cmp_int>
    4426:	2800      	cmp	r0, #0
    4428:	dd0c      	ble.n	4444 <rsa_check_context.constprop.0+0x44>
        mbedtls_mpi_get_bit( &ctx->N, 0 ) == 0  )
    442a:	2100      	movs	r1, #0
    442c:	4630      	mov	r0, r6
    442e:	f003 f894 	bl	755a <mbedtls_mpi_get_bit>
    if( mbedtls_mpi_cmp_int( &ctx->N, 0 ) <= 0 ||
    4432:	b138      	cbz	r0, 4444 <rsa_check_context.constprop.0+0x44>

#if !defined(MBEDTLS_RSA_NO_CRT)
    /* Modular exponentiation for P and Q is only
     * used for private key operations and if CRT
     * is used. */
    if( is_priv &&
    4434:	b945      	cbnz	r5, 4448 <rsa_check_context.constprop.0+0x48>
    /*
     * 2. Exponents must be positive
     */

    /* Always need E for public key operations */
    if( mbedtls_mpi_cmp_int( &ctx->E, 0 ) <= 0 )
    4436:	2100      	movs	r1, #0
    4438:	f104 0014 	add.w	r0, r4, #20
    443c:	f003 fa19 	bl	7872 <mbedtls_mpi_cmp_int>
    4440:	2800      	cmp	r0, #0
    4442:	dc1e      	bgt.n	4482 <rsa_check_context.constprop.0+0x82>
     * but check for QP >= 1 nonetheless. */
#if !defined(MBEDTLS_RSA_NO_CRT)
    if( is_priv &&
        mbedtls_mpi_cmp_int( &ctx->QP, 0 ) <= 0 )
    {
        return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA );
    4444:	481b      	ldr	r0, [pc, #108]	; (44b4 <rsa_check_context.constprop.0+0xb4>)
    4446:	e01e      	b.n	4486 <rsa_check_context.constprop.0+0x86>
        ( mbedtls_mpi_cmp_int( &ctx->P, 0 ) <= 0 ||
    4448:	f104 062c 	add.w	r6, r4, #44	; 0x2c
    444c:	2100      	movs	r1, #0
    444e:	4630      	mov	r0, r6
    4450:	f003 fa0f 	bl	7872 <mbedtls_mpi_cmp_int>
    if( is_priv &&
    4454:	2800      	cmp	r0, #0
    4456:	ddf5      	ble.n	4444 <rsa_check_context.constprop.0+0x44>
          mbedtls_mpi_get_bit( &ctx->P, 0 ) == 0 ||
    4458:	2100      	movs	r1, #0
    445a:	4630      	mov	r0, r6
    445c:	f003 f87d 	bl	755a <mbedtls_mpi_get_bit>
        ( mbedtls_mpi_cmp_int( &ctx->P, 0 ) <= 0 ||
    4460:	2800      	cmp	r0, #0
    4462:	d0ef      	beq.n	4444 <rsa_check_context.constprop.0+0x44>
          mbedtls_mpi_cmp_int( &ctx->Q, 0 ) <= 0 ||
    4464:	f104 0638 	add.w	r6, r4, #56	; 0x38
    4468:	2100      	movs	r1, #0
    446a:	4630      	mov	r0, r6
    446c:	f003 fa01 	bl	7872 <mbedtls_mpi_cmp_int>
          mbedtls_mpi_get_bit( &ctx->P, 0 ) == 0 ||
    4470:	2800      	cmp	r0, #0
    4472:	dde7      	ble.n	4444 <rsa_check_context.constprop.0+0x44>
          mbedtls_mpi_get_bit( &ctx->Q, 0 ) == 0  ) )
    4474:	2100      	movs	r1, #0
    4476:	4630      	mov	r0, r6
    4478:	f003 f86f 	bl	755a <mbedtls_mpi_get_bit>
          mbedtls_mpi_cmp_int( &ctx->Q, 0 ) <= 0 ||
    447c:	2800      	cmp	r0, #0
    447e:	d1da      	bne.n	4436 <rsa_check_context.constprop.0+0x36>
    4480:	e7e0      	b.n	4444 <rsa_check_context.constprop.0+0x44>
    if( is_priv &&
    4482:	b90d      	cbnz	r5, 4488 <rsa_check_context.constprop.0+0x88>
    }
#endif

    return( 0 );
    4484:	2000      	movs	r0, #0
}
    4486:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        ( mbedtls_mpi_cmp_int( &ctx->DP, 0 ) <= 0 ||
    4488:	2100      	movs	r1, #0
    448a:	f104 0044 	add.w	r0, r4, #68	; 0x44
    448e:	f003 f9f0 	bl	7872 <mbedtls_mpi_cmp_int>
    if( is_priv &&
    4492:	2800      	cmp	r0, #0
    4494:	ddd6      	ble.n	4444 <rsa_check_context.constprop.0+0x44>
          mbedtls_mpi_cmp_int( &ctx->DQ, 0 ) <= 0  ) )
    4496:	2100      	movs	r1, #0
    4498:	f104 0050 	add.w	r0, r4, #80	; 0x50
    449c:	f003 f9e9 	bl	7872 <mbedtls_mpi_cmp_int>
        ( mbedtls_mpi_cmp_int( &ctx->DP, 0 ) <= 0 ||
    44a0:	2800      	cmp	r0, #0
    44a2:	ddcf      	ble.n	4444 <rsa_check_context.constprop.0+0x44>
        mbedtls_mpi_cmp_int( &ctx->QP, 0 ) <= 0 )
    44a4:	2100      	movs	r1, #0
    44a6:	f104 005c 	add.w	r0, r4, #92	; 0x5c
    44aa:	f003 f9e2 	bl	7872 <mbedtls_mpi_cmp_int>
    if( is_priv &&
    44ae:	2800      	cmp	r0, #0
    44b0:	dce8      	bgt.n	4484 <rsa_check_context.constprop.0+0x84>
    44b2:	e7c7      	b.n	4444 <rsa_check_context.constprop.0+0x44>
    44b4:	ffffbf80 	.word	0xffffbf80

000044b8 <mbedtls_rsa_check_pubkey>:

/*
 * Check a public RSA key
 */
int mbedtls_rsa_check_pubkey( const mbedtls_rsa_context *ctx )
{
    44b8:	b570      	push	{r4, r5, r6, lr}
    RSA_VALIDATE_RET( ctx != NULL );

    if( rsa_check_context( ctx, 0 /* public */, 0 /* no blinding */ ) != 0 )
    44ba:	2100      	movs	r1, #0
{
    44bc:	4604      	mov	r4, r0
    if( rsa_check_context( ctx, 0 /* public */, 0 /* no blinding */ ) != 0 )
    44be:	f7ff ff9f 	bl	4400 <rsa_check_context.constprop.0>
    44c2:	4605      	mov	r5, r0
    44c4:	b9b8      	cbnz	r0, 44f6 <mbedtls_rsa_check_pubkey+0x3e>
        return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED );

    if( mbedtls_mpi_bitlen( &ctx->N ) < 128 )
    44c6:	f104 0608 	add.w	r6, r4, #8
    44ca:	4630      	mov	r0, r6
    44cc:	f003 f856 	bl	757c <mbedtls_mpi_bitlen>
    44d0:	287f      	cmp	r0, #127	; 0x7f
    44d2:	d910      	bls.n	44f6 <mbedtls_rsa_check_pubkey+0x3e>
    {
        return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED );
    }

    if( mbedtls_mpi_get_bit( &ctx->E, 0 ) == 0 ||
    44d4:	3414      	adds	r4, #20
    44d6:	4629      	mov	r1, r5
    44d8:	4620      	mov	r0, r4
    44da:	f003 f83e 	bl	755a <mbedtls_mpi_get_bit>
    44de:	b150      	cbz	r0, 44f6 <mbedtls_rsa_check_pubkey+0x3e>
        mbedtls_mpi_bitlen( &ctx->E )     < 2  ||
    44e0:	4620      	mov	r0, r4
    44e2:	f003 f84b 	bl	757c <mbedtls_mpi_bitlen>
    if( mbedtls_mpi_get_bit( &ctx->E, 0 ) == 0 ||
    44e6:	2801      	cmp	r0, #1
    44e8:	d905      	bls.n	44f6 <mbedtls_rsa_check_pubkey+0x3e>
        mbedtls_mpi_cmp_mpi( &ctx->E, &ctx->N ) >= 0 )
    44ea:	4631      	mov	r1, r6
    44ec:	4620      	mov	r0, r4
    44ee:	f003 f97f 	bl	77f0 <mbedtls_mpi_cmp_mpi>
        mbedtls_mpi_bitlen( &ctx->E )     < 2  ||
    44f2:	2800      	cmp	r0, #0
    44f4:	db00      	blt.n	44f8 <mbedtls_rsa_check_pubkey+0x40>
    {
        return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED );
    44f6:	4d01      	ldr	r5, [pc, #4]	; (44fc <mbedtls_rsa_check_pubkey+0x44>)
    }

    return( 0 );
}
    44f8:	4628      	mov	r0, r5
    44fa:	bd70      	pop	{r4, r5, r6, pc}
    44fc:	ffffbe00 	.word	0xffffbe00

00004500 <mbedtls_rsa_public>:
 * Do an RSA public key operation
 */
int mbedtls_rsa_public( mbedtls_rsa_context *ctx,
                const unsigned char *input,
                unsigned char *output )
{
    4500:	b5f0      	push	{r4, r5, r6, r7, lr}
    4502:	460c      	mov	r4, r1
    4504:	b087      	sub	sp, #28
    mbedtls_mpi T;
    RSA_VALIDATE_RET( ctx != NULL );
    RSA_VALIDATE_RET( input != NULL );
    RSA_VALIDATE_RET( output != NULL );

    if( rsa_check_context( ctx, 0 /* public */, 0 /* no blinding */ ) )
    4506:	2100      	movs	r1, #0
{
    4508:	4605      	mov	r5, r0
    450a:	4616      	mov	r6, r2
    if( rsa_check_context( ctx, 0 /* public */, 0 /* no blinding */ ) )
    450c:	f7ff ff78 	bl	4400 <rsa_check_context.constprop.0>
    4510:	bb80      	cbnz	r0, 4574 <mbedtls_rsa_public+0x74>
        return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA );

    mbedtls_mpi_init( &T );
    4512:	a803      	add	r0, sp, #12
    4514:	f002 ff4e 	bl	73b4 <mbedtls_mpi_init>
#if defined(MBEDTLS_THREADING_C)
    if( ( ret = mbedtls_mutex_lock( &ctx->mutex ) ) != 0 )
        return( ret );
#endif

    MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &T, input, ctx->len ) );
    4518:	4621      	mov	r1, r4
    451a:	686a      	ldr	r2, [r5, #4]
    451c:	a803      	add	r0, sp, #12
    451e:	f003 f84f 	bl	75c0 <mbedtls_mpi_read_binary>
    4522:	4604      	mov	r4, r0
    4524:	b9d0      	cbnz	r0, 455c <mbedtls_rsa_public+0x5c>

    if( mbedtls_mpi_cmp_mpi( &T, &ctx->N ) >= 0 )
    4526:	f105 0408 	add.w	r4, r5, #8
    452a:	4621      	mov	r1, r4
    452c:	a803      	add	r0, sp, #12
    452e:	f003 f95f 	bl	77f0 <mbedtls_mpi_cmp_mpi>
    4532:	2800      	cmp	r0, #0
    4534:	da1b      	bge.n	456e <mbedtls_rsa_public+0x6e>
        ret = MBEDTLS_ERR_MPI_BAD_INPUT_DATA;
        goto cleanup;
    }

    olen = ctx->len;
    MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &T, &T, &ctx->E, &ctx->N, &ctx->RN ) );
    4536:	f105 0368 	add.w	r3, r5, #104	; 0x68
    453a:	a903      	add	r1, sp, #12
    453c:	9300      	str	r3, [sp, #0]
    453e:	f105 0214 	add.w	r2, r5, #20
    4542:	4623      	mov	r3, r4
    4544:	4608      	mov	r0, r1
    olen = ctx->len;
    4546:	686f      	ldr	r7, [r5, #4]
    MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &T, &T, &ctx->E, &ctx->N, &ctx->RN ) );
    4548:	f003 fcb9 	bl	7ebe <mbedtls_mpi_exp_mod>
    454c:	4604      	mov	r4, r0
    454e:	b928      	cbnz	r0, 455c <mbedtls_rsa_public+0x5c>
    MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &T, output, olen ) );
    4550:	463a      	mov	r2, r7
    4552:	4631      	mov	r1, r6
    4554:	a803      	add	r0, sp, #12
    4556:	f003 f854 	bl	7602 <mbedtls_mpi_write_binary>
    455a:	4604      	mov	r4, r0
#if defined(MBEDTLS_THREADING_C)
    if( mbedtls_mutex_unlock( &ctx->mutex ) != 0 )
        return( MBEDTLS_ERR_THREADING_MUTEX_ERROR );
#endif

    mbedtls_mpi_free( &T );
    455c:	a803      	add	r0, sp, #12
    455e:	f002 ff2f 	bl	73c0 <mbedtls_mpi_free>

    if( ret != 0 )
    4562:	b10c      	cbz	r4, 4568 <mbedtls_rsa_public+0x68>
        ( *mbedtls_test_hook_error_add )( high, low, file, line );
#endif
    (void)file;
    (void)line;

    return( high + low );
    4564:	f5a4 4485 	sub.w	r4, r4, #17024	; 0x4280
        return( MBEDTLS_ERROR_ADD( MBEDTLS_ERR_RSA_PUBLIC_FAILED, ret ) );

    return( 0 );
}
    4568:	4620      	mov	r0, r4
    456a:	b007      	add	sp, #28
    456c:	bdf0      	pop	{r4, r5, r6, r7, pc}
        ret = MBEDTLS_ERR_MPI_BAD_INPUT_DATA;
    456e:	f06f 0403 	mvn.w	r4, #3
    4572:	e7f3      	b.n	455c <mbedtls_rsa_public+0x5c>
        return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA );
    4574:	4c00      	ldr	r4, [pc, #0]	; (4578 <mbedtls_rsa_public+0x78>)
    4576:	e7f7      	b.n	4568 <mbedtls_rsa_public+0x68>
    4578:	ffffbf80 	.word	0xffffbf80

0000457c <mbedtls_sha256_starts>:
    SHA256_VALIDATE_RET( is224 == 0 || is224 == 1 );
#else
    SHA256_VALIDATE_RET( is224 == 0 );
#endif

    ctx->total[0] = 0;
    457c:	2300      	movs	r3, #0
    ctx->total[1] = 0;
    457e:	e9c0 3300 	strd	r3, r3, [r0]

    if( is224 == 0 )
    4582:	b9c1      	cbnz	r1, 45b6 <mbedtls_sha256_starts+0x3a>
    {
        /* SHA-256 */
        ctx->state[0] = 0x6A09E667;
        ctx->state[1] = 0xBB67AE85;
    4584:	4a19      	ldr	r2, [pc, #100]	; (45ec <mbedtls_sha256_starts+0x70>)
    4586:	4b1a      	ldr	r3, [pc, #104]	; (45f0 <mbedtls_sha256_starts+0x74>)
        ctx->state[2] = 0x3C6EF372;
        ctx->state[3] = 0xA54FF53A;
    4588:	f8df c068 	ldr.w	ip, [pc, #104]	; 45f4 <mbedtls_sha256_starts+0x78>
        ctx->state[1] = 0xBB67AE85;
    458c:	e9c0 2302 	strd	r2, r3, [r0, #8]
        ctx->state[3] = 0xA54FF53A;
    4590:	4b19      	ldr	r3, [pc, #100]	; (45f8 <mbedtls_sha256_starts+0x7c>)
        ctx->state[4] = 0x510E527F;
        ctx->state[5] = 0x9B05688C;
    4592:	4a1a      	ldr	r2, [pc, #104]	; (45fc <mbedtls_sha256_starts+0x80>)
        ctx->state[3] = 0xA54FF53A;
    4594:	e9c0 c304 	strd	ip, r3, [r0, #16]
        ctx->state[5] = 0x9B05688C;
    4598:	4b19      	ldr	r3, [pc, #100]	; (4600 <mbedtls_sha256_starts+0x84>)
    459a:	e9c0 2306 	strd	r2, r3, [r0, #24]
        ctx->state[6] = 0x1F83D9AB;
    459e:	4b19      	ldr	r3, [pc, #100]	; (4604 <mbedtls_sha256_starts+0x88>)
    45a0:	6203      	str	r3, [r0, #32]
        ctx->state[7] = 0x5BE0CD19;
    45a2:	f103 5374 	add.w	r3, r3, #1023410176	; 0x3d000000
    45a6:	f5a3 0323 	sub.w	r3, r3, #10682368	; 0xa30000
    45aa:	f6a3 4392 	subw	r3, r3, #3218	; 0xc92
        ctx->state[2] = 0x3070DD17;
        ctx->state[3] = 0xF70E5939;
        ctx->state[4] = 0xFFC00B31;
        ctx->state[5] = 0x68581511;
        ctx->state[6] = 0x64F98FA7;
        ctx->state[7] = 0xBEFA4FA4;
    45ae:	6243      	str	r3, [r0, #36]	; 0x24
#endif
    }

    ctx->is224 = is224;
    45b0:	6681      	str	r1, [r0, #104]	; 0x68

    return( 0 );
}
    45b2:	2000      	movs	r0, #0
    45b4:	4770      	bx	lr
        ctx->state[1] = 0x367CD507;
    45b6:	4b14      	ldr	r3, [pc, #80]	; (4608 <mbedtls_sha256_starts+0x8c>)
    45b8:	4a14      	ldr	r2, [pc, #80]	; (460c <mbedtls_sha256_starts+0x90>)
        ctx->state[4] = 0xFFC00B31;
    45ba:	f8df c054 	ldr.w	ip, [pc, #84]	; 4610 <mbedtls_sha256_starts+0x94>
        ctx->state[1] = 0x367CD507;
    45be:	e9c0 2302 	strd	r2, r3, [r0, #8]
        ctx->state[2] = 0x3070DD17;
    45c2:	f103 4379 	add.w	r3, r3, #4177526784	; 0xf9000000
    45c6:	f503 0374 	add.w	r3, r3, #15990784	; 0xf40000
    45ca:	f503 6301 	add.w	r3, r3, #2064	; 0x810
    45ce:	6103      	str	r3, [r0, #16]
        ctx->state[4] = 0xFFC00B31;
    45d0:	4b10      	ldr	r3, [pc, #64]	; (4614 <mbedtls_sha256_starts+0x98>)
    45d2:	e9c0 c305 	strd	ip, r3, [r0, #20]
        ctx->state[5] = 0x68581511;
    45d6:	f103 43d1 	add.w	r3, r3, #1753219072	; 0x68800000
    45da:	f503 13c0 	add.w	r3, r3, #1572864	; 0x180000
    45de:	f503 631e 	add.w	r3, r3, #2528	; 0x9e0
    45e2:	61c3      	str	r3, [r0, #28]
        ctx->state[6] = 0x64F98FA7;
    45e4:	4b0c      	ldr	r3, [pc, #48]	; (4618 <mbedtls_sha256_starts+0x9c>)
    45e6:	6203      	str	r3, [r0, #32]
        ctx->state[7] = 0xBEFA4FA4;
    45e8:	4b0c      	ldr	r3, [pc, #48]	; (461c <mbedtls_sha256_starts+0xa0>)
    45ea:	e7e0      	b.n	45ae <mbedtls_sha256_starts+0x32>
    45ec:	6a09e667 	.word	0x6a09e667
    45f0:	bb67ae85 	.word	0xbb67ae85
    45f4:	3c6ef372 	.word	0x3c6ef372
    45f8:	a54ff53a 	.word	0xa54ff53a
    45fc:	510e527f 	.word	0x510e527f
    4600:	9b05688c 	.word	0x9b05688c
    4604:	1f83d9ab 	.word	0x1f83d9ab
    4608:	367cd507 	.word	0x367cd507
    460c:	c1059ed8 	.word	0xc1059ed8
    4610:	f70e5939 	.word	0xf70e5939
    4614:	ffc00b31 	.word	0xffc00b31
    4618:	64f98fa7 	.word	0x64f98fa7
    461c:	befa4fa4 	.word	0xbefa4fa4

00004620 <mbedtls_internal_sha256_process>:
        (d) += local.temp1; (h) = local.temp1 + local.temp2;        \
    } while( 0 )

int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx,
                                const unsigned char data[64] )
{
    4620:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4624:	b0d1      	sub	sp, #324	; 0x144
    4626:	ab48      	add	r3, sp, #288	; 0x120
    4628:	9301      	str	r3, [sp, #4]
    462a:	f100 0608 	add.w	r6, r0, #8
    462e:	f100 0328 	add.w	r3, r0, #40	; 0x28
    4632:	9a01      	ldr	r2, [sp, #4]
    4634:	9304      	str	r3, [sp, #16]
    4636:	4633      	mov	r3, r6

    SHA256_VALIDATE_RET( ctx != NULL );
    SHA256_VALIDATE_RET( (const unsigned char *)data != NULL );

    for( i = 0; i < 8; i++ )
        local.A[i] = ctx->state[i];
    4638:	f853 0b04 	ldr.w	r0, [r3], #4
    463c:	f842 0b04 	str.w	r0, [r2], #4
    for( i = 0; i < 8; i++ )
    4640:	9804      	ldr	r0, [sp, #16]
    4642:	4283      	cmp	r3, r0
    4644:	d1f8      	bne.n	4638 <mbedtls_internal_sha256_process+0x18>
    4646:	9b4f      	ldr	r3, [sp, #316]	; 0x13c
    4648:	9302      	str	r3, [sp, #8]
    464a:	ad4c      	add	r5, sp, #304	; 0x130
    464c:	e9dd e34a 	ldrd	lr, r3, [sp, #296]	; 0x128
    4650:	e895 1120 	ldmia.w	r5, {r5, r8, ip}
    4654:	e9dd 4748 	ldrd	r4, r7, [sp, #288]	; 0x120
    4658:	9303      	str	r3, [sp, #12]
    465a:	4b45      	ldr	r3, [pc, #276]	; (4770 <mbedtls_internal_sha256_process+0x150>)
    465c:	9305      	str	r3, [sp, #20]
    465e:	aa06      	add	r2, sp, #24

#if defined(MBEDTLS_SHA256_SMALLER)
    for( i = 0; i < 64; i++ )
    4660:	f04f 0900 	mov.w	r9, #0
    {
        if( i < 16 )
    4664:	f1b9 0f0f 	cmp.w	r9, #15
    4668:	d86a      	bhi.n	4740 <mbedtls_internal_sha256_process+0x120>
            GET_UINT32_BE( local.W[i], data, 4 * i );
    466a:	784b      	ldrb	r3, [r1, #1]
    466c:	f891 b000 	ldrb.w	fp, [r1]
    4670:	f891 a002 	ldrb.w	sl, [r1, #2]
    4674:	041b      	lsls	r3, r3, #16
    4676:	ea43 630b 	orr.w	r3, r3, fp, lsl #24
    467a:	f891 b003 	ldrb.w	fp, [r1, #3]
    467e:	ea43 030b 	orr.w	r3, r3, fp
    4682:	ea43 230a 	orr.w	r3, r3, sl, lsl #8
        else
            R( i );

        P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4],
    4686:	ea4f 20f5 	mov.w	r0, r5, ror #11
    468a:	ea80 10b5 	eor.w	r0, r0, r5, ror #6
    468e:	ea80 6a75 	eor.w	sl, r0, r5, ror #25
    4692:	ea8c 0008 	eor.w	r0, ip, r8
    4696:	f8dd b014 	ldr.w	fp, [sp, #20]
    469a:	6093      	str	r3, [r2, #8]
    469c:	4028      	ands	r0, r5
    469e:	ea80 000c 	eor.w	r0, r0, ip
    46a2:	4450      	add	r0, sl
    46a4:	f85b ab04 	ldr.w	sl, [fp], #4
    46a8:	f8cd b014 	str.w	fp, [sp, #20]
    46ac:	4482      	add	sl, r0
    46ae:	9802      	ldr	r0, [sp, #8]
    46b0:	4453      	add	r3, sl
    46b2:	4403      	add	r3, r0
    46b4:	ea4f 3a74 	mov.w	sl, r4, ror #13
    46b8:	ea44 0007 	orr.w	r0, r4, r7
    46bc:	ea8a 0ab4 	eor.w	sl, sl, r4, ror #2
    46c0:	ea00 000e 	and.w	r0, r0, lr
    46c4:	ea04 0b07 	and.w	fp, r4, r7
    46c8:	ea8a 5ab4 	eor.w	sl, sl, r4, ror #22
    46cc:	ea40 000b 	orr.w	r0, r0, fp
    46d0:	4450      	add	r0, sl
    for( i = 0; i < 64; i++ )
    46d2:	f109 0901 	add.w	r9, r9, #1
        P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4],
    46d6:	f8dd a00c 	ldr.w	sl, [sp, #12]
    for( i = 0; i < 64; i++ )
    46da:	f1b9 0f40 	cmp.w	r9, #64	; 0x40
        P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4],
    46de:	449a      	add	sl, r3
    46e0:	e9cd ce02 	strd	ip, lr, [sp, #8]
    46e4:	4403      	add	r3, r0
    for( i = 0; i < 64; i++ )
    46e6:	f102 0204 	add.w	r2, r2, #4
    46ea:	f101 0104 	add.w	r1, r1, #4
    46ee:	d120      	bne.n	4732 <mbedtls_internal_sha256_process+0x112>
    46f0:	e9cd 584d 	strd	r5, r8, [sp, #308]	; 0x134
    46f4:	e9cd 3448 	strd	r3, r4, [sp, #288]	; 0x120
    46f8:	f8cd c13c 	str.w	ip, [sp, #316]	; 0x13c
    46fc:	f8cd a130 	str.w	sl, [sp, #304]	; 0x130
    4700:	974a      	str	r7, [sp, #296]	; 0x128
    4702:	9007      	str	r0, [sp, #28]
    4704:	f8cd e12c 	str.w	lr, [sp, #300]	; 0x12c
    4708:	9306      	str	r3, [sp, #24]
           local.A[6], local.A[7], local.A[0], R(i+7), K[i+7] );
    }
#endif /* MBEDTLS_SHA256_SMALLER */

    for( i = 0; i < 8; i++ )
        ctx->state[i] += local.A[i];
    470a:	9901      	ldr	r1, [sp, #4]
    470c:	6833      	ldr	r3, [r6, #0]
    470e:	f851 2b04 	ldr.w	r2, [r1], #4
    4712:	9101      	str	r1, [sp, #4]
    4714:	4413      	add	r3, r2
    4716:	f846 3b04 	str.w	r3, [r6], #4
    for( i = 0; i < 8; i++ )
    471a:	9b04      	ldr	r3, [sp, #16]
    471c:	42b3      	cmp	r3, r6
    471e:	d1f4      	bne.n	470a <mbedtls_internal_sha256_process+0xea>

    /* Zeroise buffers and variables to clear sensitive data from memory. */
    mbedtls_platform_zeroize( &local, sizeof( local ) );
    4720:	a806      	add	r0, sp, #24
    4722:	f44f 7194 	mov.w	r1, #296	; 0x128
    4726:	f7ff fe61 	bl	43ec <mbedtls_platform_zeroize>

    return( 0 );
}
    472a:	2000      	movs	r0, #0
    472c:	b051      	add	sp, #324	; 0x144
    472e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    4732:	46be      	mov	lr, r7
    4734:	46c4      	mov	ip, r8
    4736:	4627      	mov	r7, r4
    4738:	46a8      	mov	r8, r5
        P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4],
    473a:	461c      	mov	r4, r3
    473c:	4655      	mov	r5, sl
    473e:	e791      	b.n	4664 <mbedtls_internal_sha256_process+0x44>
            R( i );
    4740:	6813      	ldr	r3, [r2, #0]
    4742:	f852 bc34 	ldr.w	fp, [r2, #-52]
    4746:	f852 0c38 	ldr.w	r0, [r2, #-56]
    474a:	ea4f 4af3 	mov.w	sl, r3, ror #19
    474e:	ea8a 4a73 	eor.w	sl, sl, r3, ror #17
    4752:	ea8a 2a93 	eor.w	sl, sl, r3, lsr #10
    4756:	f852 3c14 	ldr.w	r3, [r2, #-20]
    475a:	4403      	add	r3, r0
    475c:	ea4f 40bb 	mov.w	r0, fp, ror #18
    4760:	ea80 10fb 	eor.w	r0, r0, fp, ror #7
    4764:	449a      	add	sl, r3
    4766:	ea80 03db 	eor.w	r3, r0, fp, lsr #3
    476a:	4453      	add	r3, sl
    476c:	e78b      	b.n	4686 <mbedtls_internal_sha256_process+0x66>
    476e:	bf00      	nop
    4770:	00008b68 	.word	0x00008b68

00004774 <nrf52_errata_16>:
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    4774:	f04f 4370 	mov.w	r3, #4026531840	; 0xf0000000
    4778:	f893 2fe0 	ldrb.w	r2, [r3, #4064]	; 0xfe0
            uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    477c:	2a06      	cmp	r2, #6
    477e:	d109      	bne.n	4794 <nrf52_errata_16+0x20>
            uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
    4780:	f8d3 3fe8 	ldr.w	r3, [r3, #4072]	; 0xfe8
    4784:	f3c3 1303 	ubfx	r3, r3, #4, #4
    4788:	3b03      	subs	r3, #3
    478a:	2b04      	cmp	r3, #4
    478c:	d802      	bhi.n	4794 <nrf52_errata_16+0x20>
    478e:	4a02      	ldr	r2, [pc, #8]	; (4798 <nrf52_errata_16+0x24>)
    4790:	5cd0      	ldrb	r0, [r2, r3]
    4792:	4770      	bx	lr
                    default:
                        return false;
                }
            }
        #endif
        return false;
    4794:	2000      	movs	r0, #0
    #endif
}
    4796:	4770      	bx	lr
    4798:	00009b19 	.word	0x00009b19

0000479c <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    479c:	4a02      	ldr	r2, [pc, #8]	; (47a8 <nvmc_wait+0xc>)
    479e:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    47a2:	2b00      	cmp	r3, #0
    47a4:	d0fb      	beq.n	479e <nvmc_wait+0x2>
}
    47a6:	4770      	bx	lr
    47a8:	4001e000 	.word	0x4001e000

000047ac <SystemInit>:
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
}

void SystemInit(void)
{
    47ac:	b510      	push	{r4, lr}
    #endif

    #if NRF52_ERRATA_12_ENABLE_WORKAROUND
        /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_12()){
    47ae:	f003 fefe 	bl	85ae <nrf52_errata_108>
    47b2:	b140      	cbz	r0, 47c6 <SystemInit+0x1a>
            *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
    47b4:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    47b8:	4a90      	ldr	r2, [pc, #576]	; (49fc <SystemInit+0x250>)
    47ba:	f8d3 3324 	ldr.w	r3, [r3, #804]	; 0x324
    47be:	f3c3 2304 	ubfx	r3, r3, #8, #5
    47c2:	f8c2 3540 	str.w	r3, [r2, #1344]	; 0x540
    #endif

    #if NRF52_ERRATA_16_ENABLE_WORKAROUND
        /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_16()){
    47c6:	f7ff ffd5 	bl	4774 <nrf52_errata_16>
    47ca:	b110      	cbz	r0, 47d2 <SystemInit+0x26>
            *(volatile uint32_t *)0x4007C074 = 3131961357ul;
    47cc:	4b8c      	ldr	r3, [pc, #560]	; (4a00 <SystemInit+0x254>)
    47ce:	4a8d      	ldr	r2, [pc, #564]	; (4a04 <SystemInit+0x258>)
    47d0:	675a      	str	r2, [r3, #116]	; 0x74
    #endif

    #if NRF52_ERRATA_31_ENABLE_WORKAROUND
        /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_31()){
    47d2:	f003 feec 	bl	85ae <nrf52_errata_108>
    47d6:	b148      	cbz	r0, 47ec <SystemInit+0x40>
            *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
    47d8:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    47dc:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    47e0:	f8d3 3244 	ldr.w	r3, [r3, #580]	; 0x244
    47e4:	f3c3 3342 	ubfx	r3, r3, #13, #3
    47e8:	f8c2 353c 	str.w	r3, [r2, #1340]	; 0x53c
    #endif

    #if NRF52_ERRATA_32_ENABLE_WORKAROUND
        /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_32()){
    47ec:	f7ff ffc2 	bl	4774 <nrf52_errata_16>
    47f0:	b130      	cbz	r0, 4800 <SystemInit+0x54>
            CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
    47f2:	4a85      	ldr	r2, [pc, #532]	; (4a08 <SystemInit+0x25c>)
    47f4:	f8d2 30fc 	ldr.w	r3, [r2, #252]	; 0xfc
    47f8:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
    47fc:	f8c2 30fc 	str.w	r3, [r2, #252]	; 0xfc
    #endif

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
    4800:	f003 fed5 	bl	85ae <nrf52_errata_108>
    4804:	b140      	cbz	r0, 4818 <SystemInit+0x6c>
            NRF_CLOCK->EVENTS_DONE = 0;
    4806:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    480a:	2200      	movs	r2, #0
    480c:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    4810:	f8c3 2110 	str.w	r2, [r3, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    4814:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    #endif

    #if NRF52_ERRATA_37_ENABLE_WORKAROUND
        /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_37()){
    4818:	f7ff ffac 	bl	4774 <nrf52_errata_16>
    481c:	b120      	cbz	r0, 4828 <SystemInit+0x7c>
            *(volatile uint32_t *)0x400005A0 = 0x3;
    481e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4822:	2203      	movs	r2, #3
    4824:	f8c3 25a0 	str.w	r2, [r3, #1440]	; 0x5a0
    #endif

    #if NRF52_ERRATA_57_ENABLE_WORKAROUND
        /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_57()){
    4828:	f7ff ffa4 	bl	4774 <nrf52_errata_16>
    482c:	b160      	cbz	r0, 4848 <SystemInit+0x9c>
            *(volatile uint32_t *)0x40005610 = 0x00000005;
    482e:	4b77      	ldr	r3, [pc, #476]	; (4a0c <SystemInit+0x260>)
    4830:	2205      	movs	r2, #5
    4832:	f8c3 2610 	str.w	r2, [r3, #1552]	; 0x610
            *(volatile uint32_t *)0x40005688 = 0x00000001;
    4836:	2201      	movs	r2, #1
    4838:	f8c3 2688 	str.w	r2, [r3, #1672]	; 0x688
            *(volatile uint32_t *)0x40005618 = 0x00000000;
    483c:	2200      	movs	r2, #0
    483e:	f8c3 2618 	str.w	r2, [r3, #1560]	; 0x618
            *(volatile uint32_t *)0x40005614 = 0x0000003F;
    4842:	223f      	movs	r2, #63	; 0x3f
    4844:	f8c3 2614 	str.w	r2, [r3, #1556]	; 0x614
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1;
            uint32_t var2;

            if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF)
    4848:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    484c:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    4850:	1c51      	adds	r1, r2, #1
            {
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    4852:	bf09      	itett	eq
    4854:	f04f 4370 	moveq.w	r3, #4026531840	; 0xf0000000
                var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
            }
            else
            {
                var1 = *(uint32_t *)0x10000130ul;
                var2 = *(uint32_t *)0x10000134ul;
    4858:	f8d3 3134 	ldrne.w	r3, [r3, #308]	; 0x134
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    485c:	f893 2fe0 	ldrbeq.w	r2, [r3, #4064]	; 0xfe0
                var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
    4860:	f8d3 3fe8 	ldreq.w	r3, [r3, #4072]	; 0xfe8
    4864:	bf08      	it	eq
    4866:	f3c3 1303 	ubfxeq	r3, r3, #4, #4
            uint32_t var1 = *(uint32_t *)0x10000130ul;
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    486a:	2a06      	cmp	r2, #6
    486c:	d14d      	bne.n	490a <SystemInit+0x15e>
            {
                switch(var2)
    486e:	3b03      	subs	r3, #3
    4870:	2b04      	cmp	r3, #4
    4872:	d803      	bhi.n	487c <SystemInit+0xd0>
    #endif

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
    4874:	4a66      	ldr	r2, [pc, #408]	; (4a10 <SystemInit+0x264>)
    4876:	5cd3      	ldrb	r3, [r2, r3]
    4878:	2b00      	cmp	r3, #0
    487a:	d046      	beq.n	490a <SystemInit+0x15e>
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    487c:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
    4880:	4b64      	ldr	r3, [pc, #400]	; (4a14 <SystemInit+0x268>)
    4882:	f8d2 1404 	ldr.w	r1, [r2, #1028]	; 0x404
    4886:	f8c3 1520 	str.w	r1, [r3, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    488a:	f8d2 1408 	ldr.w	r1, [r2, #1032]	; 0x408
    488e:	f8c3 1524 	str.w	r1, [r3, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    4892:	f8d2 140c 	ldr.w	r1, [r2, #1036]	; 0x40c
    4896:	f8c3 1528 	str.w	r1, [r3, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    489a:	f8d2 1410 	ldr.w	r1, [r2, #1040]	; 0x410
    489e:	f8c3 152c 	str.w	r1, [r3, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    48a2:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
    48a6:	f8c3 1530 	str.w	r1, [r3, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    48aa:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    48ae:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    48b2:	f8d2 141c 	ldr.w	r1, [r2, #1052]	; 0x41c
    48b6:	f8c3 1540 	str.w	r1, [r3, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    48ba:	f8d2 1420 	ldr.w	r1, [r2, #1056]	; 0x420
    48be:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    48c2:	f8d2 1424 	ldr.w	r1, [r2, #1060]	; 0x424
    48c6:	f8c3 1548 	str.w	r1, [r3, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    48ca:	f8d2 1428 	ldr.w	r1, [r2, #1064]	; 0x428
    48ce:	f8c3 154c 	str.w	r1, [r3, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    48d2:	f8d2 142c 	ldr.w	r1, [r2, #1068]	; 0x42c
    48d6:	f8c3 1550 	str.w	r1, [r3, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    48da:	f8d2 1430 	ldr.w	r1, [r2, #1072]	; 0x430
    48de:	f8c3 1554 	str.w	r1, [r3, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    48e2:	f8d2 1434 	ldr.w	r1, [r2, #1076]	; 0x434
    48e6:	f8c3 1560 	str.w	r1, [r3, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    48ea:	f8d2 1438 	ldr.w	r1, [r2, #1080]	; 0x438
    48ee:	f8c3 1564 	str.w	r1, [r3, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    48f2:	f8d2 143c 	ldr.w	r1, [r2, #1084]	; 0x43c
    48f6:	f8c3 1568 	str.w	r1, [r3, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    48fa:	f8d2 1440 	ldr.w	r1, [r2, #1088]	; 0x440
    48fe:	f8c3 156c 	str.w	r1, [r3, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    4902:	f8d2 2444 	ldr.w	r2, [r2, #1092]	; 0x444
    4906:	f8c3 2570 	str.w	r2, [r3, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_108_ENABLE_WORKAROUND
        /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_108()){
    490a:	f003 fe50 	bl	85ae <nrf52_errata_108>
    490e:	b148      	cbz	r0, 4924 <SystemInit+0x178>
            *(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful;
    4910:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    4914:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    4918:	f8d3 3258 	ldr.w	r3, [r3, #600]	; 0x258
    491c:	f003 034f 	and.w	r3, r3, #79	; 0x4f
    4920:	f8c2 3ee4 	str.w	r3, [r2, #3812]	; 0xee4
    #endif

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
    4924:	f003 fe43 	bl	85ae <nrf52_errata_108>
    4928:	b148      	cbz	r0, 493e <SystemInit+0x192>
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    492a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    492e:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    4932:	07d2      	lsls	r2, r2, #31
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    4934:	bf44      	itt	mi
    4936:	f06f 0201 	mvnmi.w	r2, #1
    493a:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    493e:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    4942:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    4946:	2a06      	cmp	r2, #6
    4948:	d126      	bne.n	4998 <SystemInit+0x1ec>
            {
                switch(var2)
    494a:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
    494e:	3b03      	subs	r3, #3
    4950:	2b04      	cmp	r3, #4
    4952:	d802      	bhi.n	495a <SystemInit+0x1ae>
    #endif

    #if NRF52_ERRATA_182_ENABLE_WORKAROUND
        /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_182()){
    4954:	4a30      	ldr	r2, [pc, #192]	; (4a18 <SystemInit+0x26c>)
    4956:	5cd3      	ldrb	r3, [r2, r3]
    4958:	b163      	cbz	r3, 4974 <SystemInit+0x1c8>
            *(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
    495a:	4a30      	ldr	r2, [pc, #192]	; (4a1c <SystemInit+0x270>)
    495c:	f8d2 373c 	ldr.w	r3, [r2, #1852]	; 0x73c
    4960:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
    4964:	f8c2 373c 	str.w	r3, [r2, #1852]	; 0x73c
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    4968:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    496c:	f8d3 3130 	ldr.w	r3, [r3, #304]	; 0x130
    4970:	2b06      	cmp	r3, #6
    4972:	d111      	bne.n	4998 <SystemInit+0x1ec>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    4974:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    4978:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
    497c:	3b03      	subs	r3, #3
    497e:	2b04      	cmp	r3, #4
    4980:	d802      	bhi.n	4988 <SystemInit+0x1dc>
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_configuration_249())
    4982:	4a27      	ldr	r2, [pc, #156]	; (4a20 <SystemInit+0x274>)
    4984:	5cd3      	ldrb	r3, [r2, r3]
    4986:	b13b      	cbz	r3, 4998 <SystemInit+0x1ec>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    4988:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    498c:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    4990:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4994:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    4998:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    499c:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    49a0:	2a00      	cmp	r2, #0
    49a2:	db03      	blt.n	49ac <SystemInit+0x200>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    49a4:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    49a8:	2b00      	cmp	r3, #0
    49aa:	da22      	bge.n	49f2 <SystemInit+0x246>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    49ac:	491d      	ldr	r1, [pc, #116]	; (4a24 <SystemInit+0x278>)
    49ae:	2301      	movs	r3, #1
            nvmc_config(NVMC_CONFIG_WEN_Wen);
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    49b0:	f04f 2010 	mov.w	r0, #268439552	; 0x10001000
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    49b4:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    49b8:	2415      	movs	r4, #21
    nvmc_wait();
    49ba:	f7ff feef 	bl	479c <nvmc_wait>
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    49be:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
            nvmc_wait();
    49c2:	f7ff feeb 	bl	479c <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    49c6:	f8c0 4204 	str.w	r4, [r0, #516]	; 0x204
            nvmc_wait();
    49ca:	f7ff fee7 	bl	479c <nvmc_wait>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    49ce:	2300      	movs	r3, #0
    49d0:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    49d4:	f7ff fee2 	bl	479c <nvmc_wait>
  __ASM volatile ("dsb 0xF":::"memory");
    49d8:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    49dc:	490a      	ldr	r1, [pc, #40]	; (4a08 <SystemInit+0x25c>)
    49de:	4b12      	ldr	r3, [pc, #72]	; (4a28 <SystemInit+0x27c>)
    49e0:	68ca      	ldr	r2, [r1, #12]
    49e2:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    49e6:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    49e8:	60cb      	str	r3, [r1, #12]
    49ea:	f3bf 8f4f 	dsb	sy
    __NOP();
    49ee:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    49f0:	e7fd      	b.n	49ee <SystemInit+0x242>
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    49f2:	4b0e      	ldr	r3, [pc, #56]	; (4a2c <SystemInit+0x280>)
    49f4:	4a0e      	ldr	r2, [pc, #56]	; (4a30 <SystemInit+0x284>)
    49f6:	601a      	str	r2, [r3, #0]
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
}
    49f8:	bd10      	pop	{r4, pc}
    49fa:	bf00      	nop
    49fc:	40013000 	.word	0x40013000
    4a00:	4007c000 	.word	0x4007c000
    4a04:	baadf00d 	.word	0xbaadf00d
    4a08:	e000ed00 	.word	0xe000ed00
    4a0c:	40005000 	.word	0x40005000
    4a10:	00009b0a 	.word	0x00009b0a
    4a14:	4000c000 	.word	0x4000c000
    4a18:	00009b0f 	.word	0x00009b0f
    4a1c:	40001000 	.word	0x40001000
    4a20:	00009b14 	.word	0x00009b14
    4a24:	4001e000 	.word	0x4001e000
    4a28:	05fa0004 	.word	0x05fa0004
    4a2c:	20000068 	.word	0x20000068
    4a30:	03d09000 	.word	0x03d09000

00004a34 <nrfx_flag32_alloc>:
{
    return (mask & NRFX_BIT(bitpos)) ? false : true;
}

nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag)
{
    4a34:	b570      	push	{r4, r5, r6, lr}
        idx = 31 - NRF_CLZ(prev_mask);
        if (idx < 0) {
            return NRFX_ERROR_NO_MEM;
        }

        new_mask = prev_mask & ~NRFX_BIT(idx);
    4a36:	2501      	movs	r5, #1
        prev_mask = *p_mask;
    4a38:	6802      	ldr	r2, [r0, #0]
        idx = 31 - NRF_CLZ(prev_mask);
    4a3a:	fab2 f382 	clz	r3, r2
    4a3e:	f1c3 031f 	rsb	r3, r3, #31
        if (idx < 0) {
    4a42:	1c5e      	adds	r6, r3, #1
        idx = 31 - NRF_CLZ(prev_mask);
    4a44:	b2dc      	uxtb	r4, r3
        if (idx < 0) {
    4a46:	d014      	beq.n	4a72 <nrfx_flag32_alloc+0x3e>
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    4a48:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask & ~NRFX_BIT(idx);
    4a4c:	fa05 f303 	lsl.w	r3, r5, r3
    4a50:	ea22 0303 	bic.w	r3, r2, r3
    4a54:	e850 6f00 	ldrex	r6, [r0]
    4a58:	4296      	cmp	r6, r2
    4a5a:	d104      	bne.n	4a66 <nrfx_flag32_alloc+0x32>
    4a5c:	e840 3c00 	strex	ip, r3, [r0]
    4a60:	f1bc 0f00 	cmp.w	ip, #0
    4a64:	d1f6      	bne.n	4a54 <nrfx_flag32_alloc+0x20>
    4a66:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    4a6a:	d1e5      	bne.n	4a38 <nrfx_flag32_alloc+0x4>

    *p_flag = idx;

    return NRFX_SUCCESS;
    4a6c:	4802      	ldr	r0, [pc, #8]	; (4a78 <nrfx_flag32_alloc+0x44>)
    *p_flag = idx;
    4a6e:	700c      	strb	r4, [r1, #0]
}
    4a70:	bd70      	pop	{r4, r5, r6, pc}
            return NRFX_ERROR_NO_MEM;
    4a72:	4802      	ldr	r0, [pc, #8]	; (4a7c <nrfx_flag32_alloc+0x48>)
    4a74:	e7fc      	b.n	4a70 <nrfx_flag32_alloc+0x3c>
    4a76:	bf00      	nop
    4a78:	0bad0000 	.word	0x0bad0000
    4a7c:	0bad0002 	.word	0x0bad0002

00004a80 <nrfx_flag32_free>:

nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag)
{
    uint32_t new_mask, prev_mask;

    if ((NRFX_BIT(flag) & *p_mask))
    4a80:	6803      	ldr	r3, [r0, #0]
    4a82:	40cb      	lsrs	r3, r1
    4a84:	07db      	lsls	r3, r3, #31
{
    4a86:	b510      	push	{r4, lr}
    if ((NRFX_BIT(flag) & *p_mask))
    4a88:	d415      	bmi.n	4ab6 <nrfx_flag32_free+0x36>
        return NRFX_ERROR_INVALID_PARAM;
    }

    do {
        prev_mask = *p_mask;
        new_mask = prev_mask | NRFX_BIT(flag);
    4a8a:	2301      	movs	r3, #1
    4a8c:	fa03 f101 	lsl.w	r1, r3, r1
        prev_mask = *p_mask;
    4a90:	6803      	ldr	r3, [r0, #0]
    4a92:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask | NRFX_BIT(flag);
    4a96:	ea41 0203 	orr.w	r2, r1, r3
    4a9a:	e850 4f00 	ldrex	r4, [r0]
    4a9e:	429c      	cmp	r4, r3
    4aa0:	d104      	bne.n	4aac <nrfx_flag32_free+0x2c>
    4aa2:	e840 2c00 	strex	ip, r2, [r0]
    4aa6:	f1bc 0f00 	cmp.w	ip, #0
    4aaa:	d1f6      	bne.n	4a9a <nrfx_flag32_free+0x1a>
    4aac:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    4ab0:	d1ee      	bne.n	4a90 <nrfx_flag32_free+0x10>

    return NRFX_SUCCESS;
    4ab2:	4802      	ldr	r0, [pc, #8]	; (4abc <nrfx_flag32_free+0x3c>)
}
    4ab4:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    4ab6:	4802      	ldr	r0, [pc, #8]	; (4ac0 <nrfx_flag32_free+0x40>)
    4ab8:	e7fc      	b.n	4ab4 <nrfx_flag32_free+0x34>
    4aba:	bf00      	nop
    4abc:	0bad0000 	.word	0x0bad0000
    4ac0:	0bad0004 	.word	0x0bad0004

00004ac4 <clock_stop>:
    CoreDebug->DEMCR = core_debug;
}
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)

static void clock_stop(nrf_clock_domain_t domain)
{
    4ac4:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    switch (domain)
    4ac6:	4604      	mov	r4, r0
    4ac8:	b118      	cbz	r0, 4ad2 <clock_stop+0xe>
    4aca:	2801      	cmp	r0, #1
    4acc:	d029      	beq.n	4b22 <clock_stop+0x5e>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    4ace:	b003      	add	sp, #12
    4ad0:	bdf0      	pop	{r4, r5, r6, r7, pc}
    p_reg->INTENCLR = mask;
    4ad2:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4ad6:	2202      	movs	r2, #2
    4ad8:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4adc:	f8c3 0104 	str.w	r0, [r3, #260]	; 0x104
    4ae0:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4ae4:	2201      	movs	r2, #1
    4ae6:	60da      	str	r2, [r3, #12]
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    4ae8:	2301      	movs	r3, #1
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    4aea:	429c      	cmp	r4, r3
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    4aec:	f88d 3007 	strb.w	r3, [sp, #7]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    4af0:	bf14      	ite	ne
    4af2:	2500      	movne	r5, #0
    4af4:	f10d 0507 	addeq.w	r5, sp, #7
    4af8:	f242 7710 	movw	r7, #10000	; 0x2710
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    4afc:	f04f 4680 	mov.w	r6, #1073741824	; 0x40000000
    switch (domain)
    4b00:	b1d4      	cbz	r4, 4b38 <clock_stop+0x74>
    4b02:	2c01      	cmp	r4, #1
    4b04:	d1e3      	bne.n	4ace <clock_stop+0xa>
            if (p_clk_src != NULL)
    4b06:	b125      	cbz	r5, 4b12 <clock_stop+0x4e>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    4b08:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    4b0c:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    4b10:	702b      	strb	r3, [r5, #0]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    4b12:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    4b16:	03db      	lsls	r3, r3, #15
    4b18:	d418      	bmi.n	4b4c <clock_stop+0x88>
            m_clock_cb.hfclk_started = false;
    4b1a:	4b13      	ldr	r3, [pc, #76]	; (4b68 <clock_stop+0xa4>)
    4b1c:	2200      	movs	r2, #0
    4b1e:	715a      	strb	r2, [r3, #5]
    4b20:	e7d5      	b.n	4ace <clock_stop+0xa>
    p_reg->INTENCLR = mask;
    4b22:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4b26:	2200      	movs	r2, #0
    p_reg->INTENCLR = mask;
    4b28:	f8c3 0308 	str.w	r0, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4b2c:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    4b30:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4b34:	6058      	str	r0, [r3, #4]
}
    4b36:	e7d7      	b.n	4ae8 <clock_stop+0x24>
            if (p_clk_src != NULL)
    4b38:	b125      	cbz	r5, 4b44 <clock_stop+0x80>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    4b3a:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    4b3e:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    4b42:	602b      	str	r3, [r5, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    4b44:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    4b48:	03da      	lsls	r2, r3, #15
    4b4a:	d5c0      	bpl.n	4ace <clock_stop+0xa>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    4b4c:	b92d      	cbnz	r5, 4b5a <clock_stop+0x96>
    4b4e:	2001      	movs	r0, #1
    4b50:	f003 fd3c 	bl	85cc <nrfx_busy_wait>
    4b54:	3f01      	subs	r7, #1
    4b56:	d1d3      	bne.n	4b00 <clock_stop+0x3c>
    4b58:	e003      	b.n	4b62 <clock_stop+0x9e>
    4b5a:	f89d 3007 	ldrb.w	r3, [sp, #7]
    4b5e:	2b01      	cmp	r3, #1
    4b60:	d0f5      	beq.n	4b4e <clock_stop+0x8a>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    4b62:	2c01      	cmp	r4, #1
    4b64:	d0d9      	beq.n	4b1a <clock_stop+0x56>
    4b66:	e7b2      	b.n	4ace <clock_stop+0xa>
    4b68:	200012e0 	.word	0x200012e0

00004b6c <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    4b6c:	4b04      	ldr	r3, [pc, #16]	; (4b80 <nrfx_clock_init+0x14>)
    4b6e:	791a      	ldrb	r2, [r3, #4]
    4b70:	b922      	cbnz	r2, 4b7c <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    4b72:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    4b74:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    4b76:	809a      	strh	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    4b78:	4802      	ldr	r0, [pc, #8]	; (4b84 <nrfx_clock_init+0x18>)
    4b7a:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    4b7c:	4802      	ldr	r0, [pc, #8]	; (4b88 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    4b7e:	4770      	bx	lr
    4b80:	200012e0 	.word	0x200012e0
    4b84:	0bad0000 	.word	0x0bad0000
    4b88:	0bad000c 	.word	0x0bad000c

00004b8c <nrfx_clock_start>:
    m_clock_cb.module_initialized = false;
    NRFX_LOG_INFO("Uninitialized.");
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    4b8c:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    4b8e:	b110      	cbz	r0, 4b96 <nrfx_clock_start+0xa>
    4b90:	2801      	cmp	r0, #1
    4b92:	d044      	beq.n	4c1e <nrfx_clock_start+0x92>
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    4b94:	bd38      	pop	{r3, r4, r5, pc}
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    4b96:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    4b9a:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    4b9e:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
    4ba2:	f413 3380 	ands.w	r3, r3, #65536	; 0x10000
    4ba6:	d10b      	bne.n	4bc0 <nrfx_clock_start+0x34>
            return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
    4ba8:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
                else if (nrf_clock_start_task_check(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK))
    4bac:	07c9      	lsls	r1, r1, #31
    4bae:	d510      	bpl.n	4bd2 <nrfx_clock_start+0x46>
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    4bb0:	f8d2 341c 	ldr.w	r3, [r2, #1052]	; 0x41c
    if (!is_correct_clk)
    4bb4:	079b      	lsls	r3, r3, #30
    4bb6:	d408      	bmi.n	4bca <nrfx_clock_start+0x3e>
    p_reg->INTENSET = mask;
    4bb8:	2302      	movs	r3, #2
    4bba:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
                        break;
    4bbe:	e7e9      	b.n	4b94 <nrfx_clock_start+0x8>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    4bc0:	f001 0303 	and.w	r3, r1, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    4bc4:	2b01      	cmp	r3, #1
    4bc6:	d004      	beq.n	4bd2 <nrfx_clock_start+0x46>
    if (!is_correct_clk)
    4bc8:	b11b      	cbz	r3, 4bd2 <nrfx_clock_start+0x46>
        clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    4bca:	2000      	movs	r0, #0
    4bcc:	f7ff ff7a 	bl	4ac4 <clock_stop>
        *p_lfclksrc = clock_initial_lfclksrc_get();
    4bd0:	2300      	movs	r3, #0
    p_reg->LFCLKSRC = (uint32_t)(source);
    4bd2:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    4bd6:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4bda:	2300      	movs	r3, #0
    4bdc:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
    4be0:	f8d2 3104 	ldr.w	r3, [r2, #260]	; 0x104
    p_reg->INTENSET = mask;
    4be4:	2302      	movs	r3, #2
    4be6:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
    core_debug = CoreDebug->DEMCR;
    4bea:	4a12      	ldr	r2, [pc, #72]	; (4c34 <nrfx_clock_start+0xa8>)
    4bec:	f8d2 00fc 	ldr.w	r0, [r2, #252]	; 0xfc
    CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk;
    4bf0:	f040 7380 	orr.w	r3, r0, #16777216	; 0x1000000
    4bf4:	f8c2 30fc 	str.w	r3, [r2, #252]	; 0xfc
    dwt_ctrl = DWT->CTRL;
    4bf8:	4b0f      	ldr	r3, [pc, #60]	; (4c38 <nrfx_clock_start+0xac>)
    4bfa:	681c      	ldr	r4, [r3, #0]
    DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk;
    4bfc:	f044 0101 	orr.w	r1, r4, #1
    4c00:	6019      	str	r1, [r3, #0]
    cyccnt_inital = DWT->CYCCNT;
    4c02:	685d      	ldr	r5, [r3, #4]
    while ((DWT->CYCCNT - cyccnt_inital) < ANOMALY_132_DELAY_CYCLES)
    4c04:	6859      	ldr	r1, [r3, #4]
    4c06:	1b49      	subs	r1, r1, r5
    4c08:	f5b1 5f0a 	cmp.w	r1, #8832	; 0x2280
    4c0c:	d3fa      	bcc.n	4c04 <nrfx_clock_start+0x78>
    DWT->CTRL = dwt_ctrl;
    4c0e:	601c      	str	r4, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4c10:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    CoreDebug->DEMCR = core_debug;
    4c14:	f8c2 00fc 	str.w	r0, [r2, #252]	; 0xfc
    4c18:	2201      	movs	r2, #1
    4c1a:	609a      	str	r2, [r3, #8]
}
    4c1c:	e7ba      	b.n	4b94 <nrfx_clock_start+0x8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4c1e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4c22:	2200      	movs	r2, #0
    4c24:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    4c28:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENSET = mask;
    4c2c:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4c30:	6018      	str	r0, [r3, #0]
}
    4c32:	e7af      	b.n	4b94 <nrfx_clock_start+0x8>
    4c34:	e000ed00 	.word	0xe000ed00
    4c38:	e0001000 	.word	0xe0001000

00004c3c <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    4c3c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    4c40:	b510      	push	{r4, lr}
    4c42:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    4c46:	b16a      	cbz	r2, 4c64 <nrfx_power_clock_irq_handler+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4c48:	2200      	movs	r2, #0
    4c4a:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    4c4e:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENCLR = mask;
    4c52:	2201      	movs	r2, #1
    4c54:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);

#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
        if (!m_clock_cb.hfclk_started)
    4c58:	4b11      	ldr	r3, [pc, #68]	; (4ca0 <nrfx_power_clock_irq_handler+0x64>)
    4c5a:	7958      	ldrb	r0, [r3, #5]
    4c5c:	b910      	cbnz	r0, 4c64 <nrfx_power_clock_irq_handler+0x28>
        {
            m_clock_cb.hfclk_started = true;
    4c5e:	715a      	strb	r2, [r3, #5]
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    4c60:	681b      	ldr	r3, [r3, #0]
    4c62:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    4c64:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4c68:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    4c6c:	b172      	cbz	r2, 4c8c <nrfx_power_clock_irq_handler+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4c6e:	2200      	movs	r2, #0
    4c70:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    4c74:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    4c78:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    4c7c:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    4c80:	0792      	lsls	r2, r2, #30
    4c82:	d104      	bne.n	4c8e <nrfx_power_clock_irq_handler+0x52>
    p_reg->LFCLKSRC = (uint32_t)(source);
    4c84:	2201      	movs	r2, #1
    4c86:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4c8a:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    4c8c:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    4c8e:	2202      	movs	r2, #2
    4c90:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    4c94:	4b02      	ldr	r3, [pc, #8]	; (4ca0 <nrfx_power_clock_irq_handler+0x64>)
}
    4c96:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    4c9a:	681b      	ldr	r3, [r3, #0]
    4c9c:	2001      	movs	r0, #1
    4c9e:	4718      	bx	r3
    4ca0:	200012e0 	.word	0x200012e0

00004ca4 <pin_in_use_by_te>:
 *
 * @return True if pin uses GPIOTE task/event.
 */
static bool pin_in_use_by_te(uint32_t pin)
{
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    4ca4:	4b03      	ldr	r3, [pc, #12]	; (4cb4 <pin_in_use_by_te+0x10>)
    4ca6:	3008      	adds	r0, #8
    4ca8:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    4cac:	f3c0 1040 	ubfx	r0, r0, #5, #1
    4cb0:	4770      	bx	lr
    4cb2:	bf00      	nop
    4cb4:	2000006c 	.word	0x2000006c

00004cb8 <call_handler>:
    nrf_gpiote_event_t event = nrfx_gpiote_in_event_get(pin);
    return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}

static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger)
{
    4cb8:	b570      	push	{r4, r5, r6, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    4cba:	f100 0308 	add.w	r3, r0, #8
    4cbe:	4c0c      	ldr	r4, [pc, #48]	; (4cf0 <call_handler+0x38>)
    4cc0:	f834 3013 	ldrh.w	r3, [r4, r3, lsl #1]
    4cc4:	05da      	lsls	r2, r3, #23
{
    4cc6:	4605      	mov	r5, r0
    4cc8:	460e      	mov	r6, r1
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    4cca:	d507      	bpl.n	4cdc <call_handler+0x24>
    4ccc:	f3c3 2343 	ubfx	r3, r3, #9, #4
    nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin);

    if (handler)
    {
        handler->handler(pin, trigger, handler->p_context);
    4cd0:	eb04 02c3 	add.w	r2, r4, r3, lsl #3
    4cd4:	f854 3033 	ldr.w	r3, [r4, r3, lsl #3]
    4cd8:	6852      	ldr	r2, [r2, #4]
    4cda:	4798      	blx	r3
    }
    if (m_cb.global_handler.handler)
    4cdc:	68a3      	ldr	r3, [r4, #8]
    4cde:	b12b      	cbz	r3, 4cec <call_handler+0x34>
    {
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    4ce0:	68e2      	ldr	r2, [r4, #12]
    4ce2:	4631      	mov	r1, r6
    4ce4:	4628      	mov	r0, r5
    }
}
    4ce6:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    4cea:	4718      	bx	r3
}
    4cec:	bd70      	pop	{r4, r5, r6, pc}
    4cee:	bf00      	nop
    4cf0:	2000006c 	.word	0x2000006c

00004cf4 <release_handler>:
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    4cf4:	4a12      	ldr	r2, [pc, #72]	; (4d40 <release_handler+0x4c>)
    4cf6:	3008      	adds	r0, #8
{
    4cf8:	b410      	push	{r4}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    4cfa:	f832 3010 	ldrh.w	r3, [r2, r0, lsl #1]
    4cfe:	05d9      	lsls	r1, r3, #23
    4d00:	d51b      	bpl.n	4d3a <release_handler+0x46>
    4d02:	f3c3 2143 	ubfx	r1, r3, #9, #4
    m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK;
    4d06:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    4d0a:	f822 3010 	strh.w	r3, [r2, r0, lsl #1]
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    4d0e:	f102 0410 	add.w	r4, r2, #16
    4d12:	2000      	movs	r0, #0
        if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id)
    4d14:	f834 3b02 	ldrh.w	r3, [r4], #2
    4d18:	f413 7f80 	tst.w	r3, #256	; 0x100
    4d1c:	d003      	beq.n	4d26 <release_handler+0x32>
    4d1e:	f3c3 2343 	ubfx	r3, r3, #9, #4
    4d22:	4299      	cmp	r1, r3
    4d24:	d009      	beq.n	4d3a <release_handler+0x46>
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    4d26:	3001      	adds	r0, #1
    4d28:	2820      	cmp	r0, #32
    4d2a:	d1f3      	bne.n	4d14 <release_handler+0x20>
        m_cb.handlers[handler_id].handler = NULL;
    4d2c:	2300      	movs	r3, #0
    4d2e:	f842 3031 	str.w	r3, [r2, r1, lsl #3]
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    4d32:	4804      	ldr	r0, [pc, #16]	; (4d44 <release_handler+0x50>)
}
    4d34:	bc10      	pop	{r4}
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    4d36:	f7ff bea3 	b.w	4a80 <nrfx_flag32_free>
}
    4d3a:	bc10      	pop	{r4}
    4d3c:	4770      	bx	lr
    4d3e:	bf00      	nop
    4d40:	2000006c 	.word	0x2000006c
    4d44:	200000c0 	.word	0x200000c0

00004d48 <pin_handler_trigger_uninit>:
{
    4d48:	b538      	push	{r3, r4, r5, lr}
    4d4a:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    4d4c:	f7ff ffaa 	bl	4ca4 <pin_in_use_by_te>
    4d50:	4c09      	ldr	r4, [pc, #36]	; (4d78 <pin_handler_trigger_uninit+0x30>)
    4d52:	f102 0508 	add.w	r5, r2, #8
    4d56:	b140      	cbz	r0, 4d6a <pin_handler_trigger_uninit+0x22>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    4d58:	f834 3015 	ldrh.w	r3, [r4, r5, lsl #1]
                         ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}

NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
    p_reg->CONFIG[idx] = 0;
    4d5c:	4907      	ldr	r1, [pc, #28]	; (4d7c <pin_handler_trigger_uninit+0x34>)
        nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin));
    4d5e:	0b5b      	lsrs	r3, r3, #13
    4d60:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    4d64:	2000      	movs	r0, #0
    4d66:	f841 0023 	str.w	r0, [r1, r3, lsl #2]
    release_handler(pin);
    4d6a:	4610      	mov	r0, r2
    4d6c:	f7ff ffc2 	bl	4cf4 <release_handler>
    m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED;
    4d70:	2300      	movs	r3, #0
    4d72:	f824 3015 	strh.w	r3, [r4, r5, lsl #1]
}
    4d76:	bd38      	pop	{r3, r4, r5, pc}
    4d78:	2000006c 	.word	0x2000006c
    4d7c:	40006000 	.word	0x40006000

00004d80 <nrfx_gpiote_input_configure>:
{
    4d80:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    4d84:	4604      	mov	r4, r0
    4d86:	461e      	mov	r6, r3
    if (p_input_config)
    4d88:	b309      	cbz	r1, 4dce <nrfx_gpiote_input_configure+0x4e>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    4d8a:	4f4d      	ldr	r7, [pc, #308]	; (4ec0 <nrfx_gpiote_input_configure+0x140>)
    4d8c:	f100 0808 	add.w	r8, r0, #8
    4d90:	f837 5018 	ldrh.w	r5, [r7, r8, lsl #1]
    return pin_is_output(pin) && pin_in_use_by_te(pin);
    4d94:	07ab      	lsls	r3, r5, #30
    4d96:	d506      	bpl.n	4da6 <nrfx_gpiote_input_configure+0x26>
    4d98:	f7ff ff84 	bl	4ca4 <pin_in_use_by_te>
        if (pin_is_task_output(pin))
    4d9c:	b118      	cbz	r0, 4da6 <nrfx_gpiote_input_configure+0x26>
            return NRFX_ERROR_INVALID_PARAM;
    4d9e:	4849      	ldr	r0, [pc, #292]	; (4ec4 <nrfx_gpiote_input_configure+0x144>)
}
    4da0:	b002      	add	sp, #8
    4da2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    *p_pin = pin_number & 0x1F;
    4da6:	f004 001f 	and.w	r0, r4, #31
    4daa:	0080      	lsls	r0, r0, #2
    4dac:	f100 40a0 	add.w	r0, r0, #1342177280	; 0x50000000
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    4db0:	7809      	ldrb	r1, [r1, #0]
    uint32_t cnf = reg->PIN_CNF[pin_number];
    4db2:	f8d0 3700 	ldr.w	r3, [r0, #1792]	; 0x700
        m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT;
    4db6:	f025 0502 	bic.w	r5, r5, #2
    cnf &= ~to_update;
    4dba:	f023 030f 	bic.w	r3, r3, #15
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    4dbe:	f045 0501 	orr.w	r5, r5, #1
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    4dc2:	ea43 0381 	orr.w	r3, r3, r1, lsl #2
    4dc6:	f827 5018 	strh.w	r5, [r7, r8, lsl #1]
    reg->PIN_CNF[pin_number] = cnf;
    4dca:	f8c0 3700 	str.w	r3, [r0, #1792]	; 0x700
    if (p_trigger_config)
    4dce:	b192      	cbz	r2, 4df6 <nrfx_gpiote_input_configure+0x76>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    4dd0:	4b3b      	ldr	r3, [pc, #236]	; (4ec0 <nrfx_gpiote_input_configure+0x140>)
        nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger;
    4dd2:	7815      	ldrb	r5, [r2, #0]
        bool use_evt = p_trigger_config->p_in_channel ? true : false;
    4dd4:	6852      	ldr	r2, [r2, #4]
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    4dd6:	f104 0008 	add.w	r0, r4, #8
    4dda:	f833 1010 	ldrh.w	r1, [r3, r0, lsl #1]
        if (pin_is_output(pin))
    4dde:	078f      	lsls	r7, r1, #30
    4de0:	d50c      	bpl.n	4dfc <nrfx_gpiote_input_configure+0x7c>
            if (use_evt)
    4de2:	2a00      	cmp	r2, #0
    4de4:	d1db      	bne.n	4d9e <nrfx_gpiote_input_configure+0x1e>
        m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK;
    4de6:	f833 2010 	ldrh.w	r2, [r3, r0, lsl #1]
    4dea:	f022 021c 	bic.w	r2, r2, #28
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    4dee:	ea42 0285 	orr.w	r2, r2, r5, lsl #2
    4df2:	f823 2010 	strh.w	r2, [r3, r0, lsl #1]
    if (p_handler_config)
    4df6:	bbce      	cbnz	r6, 4e6c <nrfx_gpiote_input_configure+0xec>
    return NRFX_SUCCESS;
    4df8:	4833      	ldr	r0, [pc, #204]	; (4ec8 <nrfx_gpiote_input_configure+0x148>)
    4dfa:	e7d1      	b.n	4da0 <nrfx_gpiote_input_configure+0x20>
            m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED);
    4dfc:	f021 0120 	bic.w	r1, r1, #32
    4e00:	04c9      	lsls	r1, r1, #19
    4e02:	0cc9      	lsrs	r1, r1, #19
    4e04:	f823 1010 	strh.w	r1, [r3, r0, lsl #1]
            if (use_evt)
    4e08:	2a00      	cmp	r2, #0
    4e0a:	d0ec      	beq.n	4de6 <nrfx_gpiote_input_configure+0x66>
                if (!edge)
    4e0c:	2d03      	cmp	r5, #3
    4e0e:	d8c6      	bhi.n	4d9e <nrfx_gpiote_input_configure+0x1e>
                uint8_t ch = *p_trigger_config->p_in_channel;
    4e10:	7817      	ldrb	r7, [r2, #0]
                if (trigger == NRFX_GPIOTE_TRIGGER_NONE)
    4e12:	b92d      	cbnz	r5, 4e20 <nrfx_gpiote_input_configure+0xa0>
    4e14:	4a2d      	ldr	r2, [pc, #180]	; (4ecc <nrfx_gpiote_input_configure+0x14c>)
    4e16:	f507 71a2 	add.w	r1, r7, #324	; 0x144
    4e1a:	f842 5021 	str.w	r5, [r2, r1, lsl #2]
#if defined(NRF9160_XXAA) || defined(NRF5340_XXAA)
    p_reg->CONFIG[idx] = 0;
#endif
}
    4e1e:	e7e2      	b.n	4de6 <nrfx_gpiote_input_configure+0x66>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    4e20:	00ba      	lsls	r2, r7, #2
    4e22:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    4e26:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
                    m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    4e2a:	ea41 3147 	orr.w	r1, r1, r7, lsl #13
    4e2e:	f8d2 c510 	ldr.w	ip, [r2, #1296]	; 0x510
    4e32:	f02c 0c03 	bic.w	ip, ip, #3
    4e36:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    4e3a:	f8d2 c510 	ldr.w	ip, [r2, #1296]	; 0x510
    4e3e:	f42c 3c47 	bic.w	ip, ip, #203776	; 0x31c00
    4e42:	f42c 7c40 	bic.w	ip, ip, #768	; 0x300
    4e46:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    4e4a:	f8d2 e510 	ldr.w	lr, [r2, #1296]	; 0x510
    4e4e:	ea4f 2c04 	mov.w	ip, r4, lsl #8
    4e52:	f40c 5cf8 	and.w	ip, ip, #7936	; 0x1f00
    4e56:	ea4e 4e05 	orr.w	lr, lr, r5, lsl #16
    4e5a:	ea4c 0c0e 	orr.w	ip, ip, lr
    4e5e:	f041 0120 	orr.w	r1, r1, #32
    4e62:	f823 1010 	strh.w	r1, [r3, r0, lsl #1]
    4e66:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
    4e6a:	e7bc      	b.n	4de6 <nrfx_gpiote_input_configure+0x66>
        err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context);
    4e6c:	e9d6 7600 	ldrd	r7, r6, [r6]
    release_handler(pin);
    4e70:	4620      	mov	r0, r4
    4e72:	f7ff ff3f 	bl	4cf4 <release_handler>
    if (!handler)
    4e76:	2f00      	cmp	r7, #0
    4e78:	d0be      	beq.n	4df8 <nrfx_gpiote_input_configure+0x78>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    4e7a:	4d11      	ldr	r5, [pc, #68]	; (4ec0 <nrfx_gpiote_input_configure+0x140>)
    4e7c:	682b      	ldr	r3, [r5, #0]
    4e7e:	429f      	cmp	r7, r3
    4e80:	d104      	bne.n	4e8c <nrfx_gpiote_input_configure+0x10c>
    4e82:	686b      	ldr	r3, [r5, #4]
    4e84:	429e      	cmp	r6, r3
    4e86:	d101      	bne.n	4e8c <nrfx_gpiote_input_configure+0x10c>
    4e88:	2200      	movs	r2, #0
    4e8a:	e009      	b.n	4ea0 <nrfx_gpiote_input_configure+0x120>
        err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id);
    4e8c:	4810      	ldr	r0, [pc, #64]	; (4ed0 <nrfx_gpiote_input_configure+0x150>)
    4e8e:	f10d 0107 	add.w	r1, sp, #7
    4e92:	f7ff fdcf 	bl	4a34 <nrfx_flag32_alloc>
        if (err != NRFX_SUCCESS)
    4e96:	4b0c      	ldr	r3, [pc, #48]	; (4ec8 <nrfx_gpiote_input_configure+0x148>)
    4e98:	4298      	cmp	r0, r3
    4e9a:	d181      	bne.n	4da0 <nrfx_gpiote_input_configure+0x20>
        handler_id = (int32_t)id;
    4e9c:	f89d 2007 	ldrb.w	r2, [sp, #7]
    m_cb.handlers[handler_id].handler = handler;
    4ea0:	f845 7032 	str.w	r7, [r5, r2, lsl #3]
    m_cb.handlers[handler_id].p_context = p_context;
    4ea4:	eb05 03c2 	add.w	r3, r5, r2, lsl #3
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    4ea8:	3408      	adds	r4, #8
    m_cb.handlers[handler_id].p_context = p_context;
    4eaa:	605e      	str	r6, [r3, #4]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    4eac:	f835 3014 	ldrh.w	r3, [r5, r4, lsl #1]
    4eb0:	ea43 2342 	orr.w	r3, r3, r2, lsl #9
    4eb4:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    4eb8:	f825 3014 	strh.w	r3, [r5, r4, lsl #1]
    4ebc:	e79c      	b.n	4df8 <nrfx_gpiote_input_configure+0x78>
    4ebe:	bf00      	nop
    4ec0:	2000006c 	.word	0x2000006c
    4ec4:	0bad0004 	.word	0x0bad0004
    4ec8:	0bad0000 	.word	0x0bad0000
    4ecc:	40006000 	.word	0x40006000
    4ed0:	200000c0 	.word	0x200000c0

00004ed4 <nrfx_gpiote_output_configure>:
{
    4ed4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4ed6:	4604      	mov	r4, r0
    if (p_config)
    4ed8:	b371      	cbz	r1, 4f38 <nrfx_gpiote_output_configure+0x64>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    4eda:	4e37      	ldr	r6, [pc, #220]	; (4fb8 <nrfx_gpiote_output_configure+0xe4>)
    4edc:	f100 0708 	add.w	r7, r0, #8
    4ee0:	f836 5017 	ldrh.w	r5, [r6, r7, lsl #1]
        if (pin_is_input(pin) && pin_in_use_by_te(pin))
    4ee4:	07ab      	lsls	r3, r5, #30
    4ee6:	d404      	bmi.n	4ef2 <nrfx_gpiote_output_configure+0x1e>
    4ee8:	f7ff fedc 	bl	4ca4 <pin_in_use_by_te>
    4eec:	b108      	cbz	r0, 4ef2 <nrfx_gpiote_output_configure+0x1e>
    return NRFX_SUCCESS;
    4eee:	4833      	ldr	r0, [pc, #204]	; (4fbc <nrfx_gpiote_output_configure+0xe8>)
}
    4ef0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    4ef2:	f015 0f1c 	tst.w	r5, #28
    4ef6:	784b      	ldrb	r3, [r1, #1]
    4ef8:	d001      	beq.n	4efe <nrfx_gpiote_output_configure+0x2a>
    4efa:	2b01      	cmp	r3, #1
    4efc:	d0f7      	beq.n	4eee <nrfx_gpiote_output_configure+0x1a>
    *p_pin = pin_number & 0x1F;
    4efe:	f004 001f 	and.w	r0, r4, #31
    4f02:	0080      	lsls	r0, r0, #2
    4f04:	f100 40a0 	add.w	r0, r0, #1342177280	; 0x50000000
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    4f08:	f891 e000 	ldrb.w	lr, [r1]
    uint32_t cnf = reg->PIN_CNF[pin_number];
    4f0c:	f8d0 c700 	ldr.w	ip, [r0, #1792]	; 0x700
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    4f10:	7889      	ldrb	r1, [r1, #2]
           ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
    4f12:	005b      	lsls	r3, r3, #1
    cnf &= ~to_update;
    4f14:	f42c 6ce1 	bic.w	ip, ip, #1800	; 0x708
    4f18:	ea43 230e 	orr.w	r3, r3, lr, lsl #8
    4f1c:	f02c 0c07 	bic.w	ip, ip, #7
    4f20:	ea43 030c 	orr.w	r3, r3, ip
    4f24:	ea43 0381 	orr.w	r3, r3, r1, lsl #2
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT;
    4f28:	f045 0503 	orr.w	r5, r5, #3
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    4f2c:	f043 0301 	orr.w	r3, r3, #1
    4f30:	f826 5017 	strh.w	r5, [r6, r7, lsl #1]
    reg->PIN_CNF[pin_number] = cnf;
    4f34:	f8c0 3700 	str.w	r3, [r0, #1792]	; 0x700
    if (p_task_config)
    4f38:	b90a      	cbnz	r2, 4f3e <nrfx_gpiote_output_configure+0x6a>
    return NRFX_SUCCESS;
    4f3a:	4821      	ldr	r0, [pc, #132]	; (4fc0 <nrfx_gpiote_output_configure+0xec>)
    4f3c:	e7d8      	b.n	4ef0 <nrfx_gpiote_output_configure+0x1c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    4f3e:	4e1e      	ldr	r6, [pc, #120]	; (4fb8 <nrfx_gpiote_output_configure+0xe4>)
    4f40:	f104 0708 	add.w	r7, r4, #8
    4f44:	f836 0017 	ldrh.w	r0, [r6, r7, lsl #1]
        if (pin_is_input(pin))
    4f48:	0783      	lsls	r3, r0, #30
    4f4a:	d5d0      	bpl.n	4eee <nrfx_gpiote_output_configure+0x1a>
        uint32_t ch = p_task_config->task_ch;
    4f4c:	f892 c000 	ldrb.w	ip, [r2]
    p_reg->CONFIG[idx] = 0;
    4f50:	4661      	mov	r1, ip
    4f52:	0089      	lsls	r1, r1, #2
        m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK);
    4f54:	f020 0020 	bic.w	r0, r0, #32
    4f58:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    4f5c:	04c0      	lsls	r0, r0, #19
    4f5e:	f501 41c0 	add.w	r1, r1, #24576	; 0x6000
    4f62:	0cc0      	lsrs	r0, r0, #19
    4f64:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    4f68:	2300      	movs	r3, #0
    4f6a:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
        if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE)
    4f6e:	7855      	ldrb	r5, [r2, #1]
    4f70:	2d00      	cmp	r5, #0
    4f72:	d0e2      	beq.n	4f3a <nrfx_gpiote_output_configure+0x66>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
    4f74:	f8d1 3510 	ldr.w	r3, [r1, #1296]	; 0x510
            nrf_gpiote_task_configure(NRF_GPIOTE, ch, pin,
    4f78:	7892      	ldrb	r2, [r2, #2]
    4f7a:	f423 1398 	bic.w	r3, r3, #1245184	; 0x130000
    4f7e:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    4f82:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    4f86:	f8d1 e510 	ldr.w	lr, [r1, #1296]	; 0x510
    4f8a:	0223      	lsls	r3, r4, #8
    4f8c:	f403 53f8 	and.w	r3, r3, #7936	; 0x1f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    4f90:	042d      	lsls	r5, r5, #16
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    4f92:	ea43 030e 	orr.w	r3, r3, lr
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    4f96:	f405 3540 	and.w	r5, r5, #196608	; 0x30000
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    4f9a:	0512      	lsls	r2, r2, #20
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    4f9c:	432b      	orrs	r3, r5
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    4f9e:	f402 1280 	and.w	r2, r2, #1048576	; 0x100000
            m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    4fa2:	ea40 304c 	orr.w	r0, r0, ip, lsl #13
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    4fa6:	4313      	orrs	r3, r2
    4fa8:	f040 0020 	orr.w	r0, r0, #32
    4fac:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    4fb0:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    4fb4:	e7c1      	b.n	4f3a <nrfx_gpiote_output_configure+0x66>
    4fb6:	bf00      	nop
    4fb8:	2000006c 	.word	0x2000006c
    4fbc:	0bad0004 	.word	0x0bad0004
    4fc0:	0bad0000 	.word	0x0bad0000

00004fc4 <nrfx_gpiote_global_callback_set>:
    m_cb.global_handler.handler = handler;
    4fc4:	4b01      	ldr	r3, [pc, #4]	; (4fcc <nrfx_gpiote_global_callback_set+0x8>)
    m_cb.global_handler.p_context = p_context;
    4fc6:	e9c3 0102 	strd	r0, r1, [r3, #8]
}
    4fca:	4770      	bx	lr
    4fcc:	2000006c 	.word	0x2000006c

00004fd0 <nrfx_gpiote_channel_get>:
{
    4fd0:	b508      	push	{r3, lr}
    4fd2:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    4fd4:	f7ff fe66 	bl	4ca4 <pin_in_use_by_te>
    4fd8:	b138      	cbz	r0, 4fea <nrfx_gpiote_channel_get+0x1a>
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    4fda:	4b05      	ldr	r3, [pc, #20]	; (4ff0 <nrfx_gpiote_channel_get+0x20>)
        return NRFX_SUCCESS;
    4fdc:	4805      	ldr	r0, [pc, #20]	; (4ff4 <nrfx_gpiote_channel_get+0x24>)
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    4fde:	3208      	adds	r2, #8
    4fe0:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    4fe4:	0b5b      	lsrs	r3, r3, #13
    4fe6:	700b      	strb	r3, [r1, #0]
}
    4fe8:	bd08      	pop	{r3, pc}
        return NRFX_ERROR_INVALID_PARAM;
    4fea:	4803      	ldr	r0, [pc, #12]	; (4ff8 <nrfx_gpiote_channel_get+0x28>)
    4fec:	e7fc      	b.n	4fe8 <nrfx_gpiote_channel_get+0x18>
    4fee:	bf00      	nop
    4ff0:	2000006c 	.word	0x2000006c
    4ff4:	0bad0000 	.word	0x0bad0000
    4ff8:	0bad0004 	.word	0x0bad0004

00004ffc <nrfx_gpiote_init>:
{
    4ffc:	b538      	push	{r3, r4, r5, lr}
    if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    4ffe:	4c0f      	ldr	r4, [pc, #60]	; (503c <nrfx_gpiote_init+0x40>)
    5000:	f894 5058 	ldrb.w	r5, [r4, #88]	; 0x58
    5004:	b9bd      	cbnz	r5, 5036 <nrfx_gpiote_init+0x3a>
    memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags));
    5006:	2240      	movs	r2, #64	; 0x40
    5008:	4629      	mov	r1, r5
    500a:	f104 0010 	add.w	r0, r4, #16
    500e:	f001 fa78 	bl	6502 <memset>
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE));
    5012:	2006      	movs	r0, #6
    5014:	f7fd fc12 	bl	283c <arch_irq_enable>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    5018:	4b09      	ldr	r3, [pc, #36]	; (5040 <nrfx_gpiote_init+0x44>)
    return err_code;
    501a:	480a      	ldr	r0, [pc, #40]	; (5044 <nrfx_gpiote_init+0x48>)
    501c:	f8c3 517c 	str.w	r5, [r3, #380]	; 0x17c
    5020:	f8d3 217c 	ldr.w	r2, [r3, #380]	; 0x17c
    p_reg->INTENSET = mask;
    5024:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    5028:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    m_cb.state = NRFX_DRV_STATE_INITIALIZED;
    502c:	2301      	movs	r3, #1
    502e:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS);
    5032:	6563      	str	r3, [r4, #84]	; 0x54
}
    5034:	bd38      	pop	{r3, r4, r5, pc}
        return err_code;
    5036:	4804      	ldr	r0, [pc, #16]	; (5048 <nrfx_gpiote_init+0x4c>)
    5038:	e7fc      	b.n	5034 <nrfx_gpiote_init+0x38>
    503a:	bf00      	nop
    503c:	2000006c 	.word	0x2000006c
    5040:	40006000 	.word	0x40006000
    5044:	0bad0000 	.word	0x0bad0000
    5048:	0bad0005 	.word	0x0bad0005

0000504c <nrfx_gpiote_is_init>:
    return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false;
    504c:	4b03      	ldr	r3, [pc, #12]	; (505c <nrfx_gpiote_is_init+0x10>)
    504e:	f893 0058 	ldrb.w	r0, [r3, #88]	; 0x58
}
    5052:	3800      	subs	r0, #0
    5054:	bf18      	it	ne
    5056:	2001      	movne	r0, #1
    5058:	4770      	bx	lr
    505a:	bf00      	nop
    505c:	2000006c 	.word	0x2000006c

00005060 <nrfx_gpiote_channel_free>:
{
    5060:	4601      	mov	r1, r0
    return nrfx_flag32_free(&m_cb.available_channels_mask, channel);
    5062:	4801      	ldr	r0, [pc, #4]	; (5068 <nrfx_gpiote_channel_free+0x8>)
    5064:	f7ff bd0c 	b.w	4a80 <nrfx_flag32_free>
    5068:	200000bc 	.word	0x200000bc

0000506c <nrfx_gpiote_channel_alloc>:
{
    506c:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel);
    506e:	4801      	ldr	r0, [pc, #4]	; (5074 <nrfx_gpiote_channel_alloc+0x8>)
    5070:	f7ff bce0 	b.w	4a34 <nrfx_flag32_alloc>
    5074:	200000bc 	.word	0x200000bc

00005078 <nrfx_gpiote_trigger_enable>:
{
    5078:	b510      	push	{r4, lr}
    507a:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    507c:	f7ff fe12 	bl	4ca4 <pin_in_use_by_te>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    5080:	f102 0408 	add.w	r4, r2, #8
    5084:	4b1c      	ldr	r3, [pc, #112]	; (50f8 <nrfx_gpiote_trigger_enable+0x80>)
    5086:	f833 3014 	ldrh.w	r3, [r3, r4, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    508a:	b1e0      	cbz	r0, 50c6 <nrfx_gpiote_trigger_enable+0x4e>
    508c:	f013 0402 	ands.w	r4, r3, #2
    5090:	d119      	bne.n	50c6 <nrfx_gpiote_trigger_enable+0x4e>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    5092:	0b5b      	lsrs	r3, r3, #13
#endif

NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
{
    NRFX_ASSERT(index < GPIOTE_CH_NUM);
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    5094:	009a      	lsls	r2, r3, #2
    return ((uint32_t)p_reg + event);
    5096:	f102 4080 	add.w	r0, r2, #1073741824	; 0x40000000
    509a:	f500 40c2 	add.w	r0, r0, #24832	; 0x6100
    509e:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    50a2:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    50a6:	6004      	str	r4, [r0, #0]
    50a8:	6800      	ldr	r0, [r0, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    50aa:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    50ae:	f040 0001 	orr.w	r0, r0, #1
    50b2:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
        if (int_enable)
    50b6:	b129      	cbz	r1, 50c4 <nrfx_gpiote_trigger_enable+0x4c>
            nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch));
    50b8:	2201      	movs	r2, #1
    50ba:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->INTENSET = mask;
    50be:	4a0f      	ldr	r2, [pc, #60]	; (50fc <nrfx_gpiote_trigger_enable+0x84>)
    50c0:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    50c4:	bd10      	pop	{r4, pc}
    nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    50c6:	f3c3 0382 	ubfx	r3, r3, #2, #3
    if (trigger == NRFX_GPIOTE_TRIGGER_LOW)
    50ca:	2b04      	cmp	r3, #4
    50cc:	d010      	beq.n	50f0 <nrfx_gpiote_trigger_enable+0x78>
    else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH)
    50ce:	2b05      	cmp	r3, #5
    50d0:	d010      	beq.n	50f4 <nrfx_gpiote_trigger_enable+0x7c>
    return p_reg->IN;
    50d2:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    50d6:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
    *p_pin = pin_number & 0x1F;
    50da:	f002 031f 	and.w	r3, r2, #31
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    50de:	40d9      	lsrs	r1, r3
    50e0:	f001 0101 	and.w	r1, r1, #1
        sense = nrf_gpio_pin_read(pin) ? NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    50e4:	3102      	adds	r1, #2
}
    50e6:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    50ea:	4610      	mov	r0, r2
    50ec:	f003 ba7f 	b.w	85ee <nrf_gpio_cfg_sense_set>
        sense = NRF_GPIO_PIN_SENSE_LOW;
    50f0:	2103      	movs	r1, #3
    50f2:	e7f8      	b.n	50e6 <nrfx_gpiote_trigger_enable+0x6e>
        sense = NRF_GPIO_PIN_SENSE_HIGH;
    50f4:	2102      	movs	r1, #2
    50f6:	e7f6      	b.n	50e6 <nrfx_gpiote_trigger_enable+0x6e>
    50f8:	2000006c 	.word	0x2000006c
    50fc:	40006000 	.word	0x40006000

00005100 <nrfx_gpiote_trigger_disable>:
{
    5100:	b508      	push	{r3, lr}
    5102:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    5104:	f7ff fdce 	bl	4ca4 <pin_in_use_by_te>
    5108:	b1c0      	cbz	r0, 513c <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    510a:	f102 0108 	add.w	r1, r2, #8
    510e:	4b0e      	ldr	r3, [pc, #56]	; (5148 <nrfx_gpiote_trigger_disable+0x48>)
    5110:	f833 3011 	ldrh.w	r3, [r3, r1, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    5114:	0799      	lsls	r1, r3, #30
    5116:	d411      	bmi.n	513c <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    5118:	0b5b      	lsrs	r3, r3, #13
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    511a:	2201      	movs	r2, #1
    511c:	409a      	lsls	r2, r3
    p_reg->INTENCLR = mask;
    511e:	009b      	lsls	r3, r3, #2
    5120:	490a      	ldr	r1, [pc, #40]	; (514c <nrfx_gpiote_trigger_disable+0x4c>)
    5122:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    5126:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    512a:	f8c1 2308 	str.w	r2, [r1, #776]	; 0x308
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    512e:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    5132:	f022 0203 	bic.w	r2, r2, #3
    5136:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    513a:	bd08      	pop	{r3, pc}
    513c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    5140:	2100      	movs	r1, #0
    5142:	4610      	mov	r0, r2
    5144:	f003 ba53 	b.w	85ee <nrf_gpio_cfg_sense_set>
    5148:	2000006c 	.word	0x2000006c
    514c:	40006000 	.word	0x40006000

00005150 <nrfx_gpiote_pin_uninit>:
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    5150:	4b0d      	ldr	r3, [pc, #52]	; (5188 <nrfx_gpiote_pin_uninit+0x38>)
    5152:	f100 0208 	add.w	r2, r0, #8
{
    5156:	b510      	push	{r4, lr}
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    5158:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (!pin_in_use(pin))
    515c:	07db      	lsls	r3, r3, #31
{
    515e:	4604      	mov	r4, r0
    if (!pin_in_use(pin))
    5160:	d50f      	bpl.n	5182 <nrfx_gpiote_pin_uninit+0x32>
    nrfx_gpiote_trigger_disable(pin);
    5162:	f7ff ffcd 	bl	5100 <nrfx_gpiote_trigger_disable>
    pin_handler_trigger_uninit(pin);
    5166:	4620      	mov	r0, r4
    *p_pin = pin_number & 0x1F;
    5168:	f004 041f 	and.w	r4, r4, #31
    516c:	f7ff fdec 	bl	4d48 <pin_handler_trigger_uninit>
    reg->PIN_CNF[pin_number] = cnf;
    5170:	f504 74e0 	add.w	r4, r4, #448	; 0x1c0
    5174:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    5178:	2202      	movs	r2, #2
    517a:	f843 2024 	str.w	r2, [r3, r4, lsl #2]
    517e:	4803      	ldr	r0, [pc, #12]	; (518c <nrfx_gpiote_pin_uninit+0x3c>)
}
    5180:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    5182:	4803      	ldr	r0, [pc, #12]	; (5190 <nrfx_gpiote_pin_uninit+0x40>)
    5184:	e7fc      	b.n	5180 <nrfx_gpiote_pin_uninit+0x30>
    5186:	bf00      	nop
    5188:	2000006c 	.word	0x2000006c
    518c:	0bad0000 	.word	0x0bad0000
    5190:	0bad0004 	.word	0x0bad0004

00005194 <nrfx_gpiote_irq_handler>:
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    }
}

void nrfx_gpiote_irq_handler(void)
{
    5194:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    5198:	4b4e      	ldr	r3, [pc, #312]	; (52d4 <nrfx_gpiote_irq_handler+0x140>)
    return p_reg->INTENSET & mask;
    519a:	484f      	ldr	r0, [pc, #316]	; (52d8 <nrfx_gpiote_irq_handler+0x144>)
    uint32_t i;
    nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0;
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;

    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    519c:	494f      	ldr	r1, [pc, #316]	; (52dc <nrfx_gpiote_irq_handler+0x148>)
    uint32_t status = 0;
    519e:	2500      	movs	r5, #0
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
    51a0:	2201      	movs	r2, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    51a2:	462c      	mov	r4, r5
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    51a4:	681e      	ldr	r6, [r3, #0]
    {
        if (nrf_gpiote_event_check(NRF_GPIOTE, event) &&
    51a6:	b136      	cbz	r6, 51b6 <nrfx_gpiote_irq_handler+0x22>
    return p_reg->INTENSET & mask;
    51a8:	f8d0 6304 	ldr.w	r6, [r0, #772]	; 0x304
    51ac:	4216      	tst	r6, r2
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    51ae:	bf1e      	ittt	ne
    51b0:	601c      	strne	r4, [r3, #0]
    51b2:	681e      	ldrne	r6, [r3, #0]
            nrf_gpiote_int_enable_check(NRF_GPIOTE, mask))
        {
            nrf_gpiote_event_clear(NRF_GPIOTE, event);
            status |= mask;
    51b4:	4315      	orrne	r5, r2
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    51b6:	3304      	adds	r3, #4
    51b8:	428b      	cmp	r3, r1
        }
        mask <<= 1;
    51ba:	ea4f 0242 	mov.w	r2, r2, lsl #1
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    51be:	d1f1      	bne.n	51a4 <nrfx_gpiote_irq_handler+0x10>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    51c0:	4b45      	ldr	r3, [pc, #276]	; (52d8 <nrfx_gpiote_irq_handler+0x144>)
    51c2:	f8d3 317c 	ldr.w	r3, [r3, #380]	; 0x17c
         * in ascending order. */
        event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t));
    }

    /* handle PORT event */
    if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
    51c6:	b1bb      	cbz	r3, 51f8 <nrfx_gpiote_irq_handler+0x64>
        *p_masks = gpio_regs[i]->LATCH;
    51c8:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
    51cc:	f8d6 3520 	ldr.w	r3, [r6, #1312]	; 0x520
    51d0:	9301      	str	r3, [sp, #4]
        gpio_regs[i]->LATCH = *p_masks;
    51d2:	f8c6 3520 	str.w	r3, [r6, #1312]	; 0x520
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
    uint8_t * p_mask8 = (uint8_t *)p_mask;
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    bit = BITMASK_RELBIT_GET(bit);
    p_mask8[byte_idx] &= ~(1 << bit);
    51d6:	af01      	add	r7, sp, #4
    51d8:	f04f 0801 	mov.w	r8, #1
            while (latch[i])
    51dc:	9c01      	ldr	r4, [sp, #4]
    51de:	b96c      	cbnz	r4, 51fc <nrfx_gpiote_irq_handler+0x68>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    51e0:	4b3d      	ldr	r3, [pc, #244]	; (52d8 <nrfx_gpiote_irq_handler+0x144>)
    51e2:	f8c3 417c 	str.w	r4, [r3, #380]	; 0x17c
    51e6:	f8d3 317c 	ldr.w	r3, [r3, #380]	; 0x17c
        *p_masks = gpio_regs[i]->LATCH;
    51ea:	f8d6 3520 	ldr.w	r3, [r6, #1312]	; 0x520
    51ee:	9301      	str	r3, [sp, #4]
        gpio_regs[i]->LATCH = *p_masks;
    51f0:	f8c6 3520 	str.w	r3, [r6, #1312]	; 0x520
        if (latch[port_idx])
    51f4:	2b00      	cmp	r3, #0
    51f6:	d1ee      	bne.n	51d6 <nrfx_gpiote_irq_handler+0x42>
        mask &= ~NRFX_BIT(ch);
    51f8:	2401      	movs	r4, #1
    51fa:	e066      	b.n	52ca <nrfx_gpiote_irq_handler+0x136>
                uint32_t pin = NRF_CTZ(latch[i]);
    51fc:	fa94 f4a4 	rbit	r4, r4
    5200:	fab4 f484 	clz	r4, r4
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    5204:	4a36      	ldr	r2, [pc, #216]	; (52e0 <nrfx_gpiote_irq_handler+0x14c>)
    5206:	f104 0308 	add.w	r3, r4, #8
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    520a:	08e0      	lsrs	r0, r4, #3
    520c:	f832 1013 	ldrh.w	r1, [r2, r3, lsl #1]
    bit = BITMASK_RELBIT_GET(bit);
    5210:	f004 0307 	and.w	r3, r4, #7
    p_mask8[byte_idx] &= ~(1 << bit);
    5214:	fa08 f203 	lsl.w	r2, r8, r3
    5218:	5c3b      	ldrb	r3, [r7, r0]
    521a:	ea23 0302 	bic.w	r3, r3, r2
    521e:	543b      	strb	r3, [r7, r0]
    5220:	00a3      	lsls	r3, r4, #2
    5222:	f103 49a0 	add.w	r9, r3, #1342177280	; 0x50000000
    5226:	f3c1 0a82 	ubfx	sl, r1, #2, #3
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    522a:	f8d9 2700 	ldr.w	r2, [r9, #1792]	; 0x700
    if (is_level(trigger))
    522e:	06cb      	lsls	r3, r1, #27
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    5230:	46d3      	mov	fp, sl
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    5232:	f3c2 4201 	ubfx	r2, r2, #16, #2
    if (is_level(trigger))
    5236:	d518      	bpl.n	526a <nrfx_gpiote_irq_handler+0xd6>
        call_handler(pin, trigger);
    5238:	4659      	mov	r1, fp
    523a:	4620      	mov	r0, r4
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    523c:	fa5f fa82 	uxtb.w	sl, r2
    5240:	f7ff fd3a 	bl	4cb8 <call_handler>
    5244:	f8d9 3700 	ldr.w	r3, [r9, #1792]	; 0x700
        if (nrf_gpio_pin_sense_get(pin) == sense)
    5248:	f3c3 4301 	ubfx	r3, r3, #16, #2
    524c:	459a      	cmp	sl, r3
    524e:	d107      	bne.n	5260 <nrfx_gpiote_irq_handler+0xcc>
            nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    5250:	2100      	movs	r1, #0
    5252:	4620      	mov	r0, r4
    5254:	f003 f9cb 	bl	85ee <nrf_gpio_cfg_sense_set>
            nrf_gpio_cfg_sense_set(pin, sense);
    5258:	4651      	mov	r1, sl
    525a:	4620      	mov	r0, r4
    525c:	f003 f9c7 	bl	85ee <nrf_gpio_cfg_sense_set>
    reg->LATCH = (1 << pin_number);
    5260:	fa08 f404 	lsl.w	r4, r8, r4
    5264:	f8c6 4520 	str.w	r4, [r6, #1312]	; 0x520
}
    5268:	e7b8      	b.n	51dc <nrfx_gpiote_irq_handler+0x48>
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    526a:	2a02      	cmp	r2, #2
        nrf_gpio_cfg_sense_set(pin, next_sense);
    526c:	bf0c      	ite	eq
    526e:	2103      	moveq	r1, #3
    5270:	2102      	movne	r1, #2
    5272:	4620      	mov	r0, r4
    5274:	f003 f9bb 	bl	85ee <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    5278:	f1ba 0f03 	cmp.w	sl, #3
    527c:	d004      	beq.n	5288 <nrfx_gpiote_irq_handler+0xf4>
    527e:	2a02      	cmp	r2, #2
    5280:	d107      	bne.n	5292 <nrfx_gpiote_irq_handler+0xfe>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    5282:	f1ba 0f01 	cmp.w	sl, #1
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    5286:	d1eb      	bne.n	5260 <nrfx_gpiote_irq_handler+0xcc>
            call_handler(pin, trigger);
    5288:	4659      	mov	r1, fp
    528a:	4620      	mov	r0, r4
    528c:	f7ff fd14 	bl	4cb8 <call_handler>
    5290:	e7e6      	b.n	5260 <nrfx_gpiote_irq_handler+0xcc>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    5292:	2a03      	cmp	r2, #3
    5294:	d1e4      	bne.n	5260 <nrfx_gpiote_irq_handler+0xcc>
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    5296:	f1ba 0f02 	cmp.w	sl, #2
    529a:	e7f4      	b.n	5286 <nrfx_gpiote_irq_handler+0xf2>
        uint32_t ch = NRF_CTZ(mask);
    529c:	fa95 f3a5 	rbit	r3, r5
    52a0:	fab3 f383 	clz	r3, r3
        mask &= ~NRFX_BIT(ch);
    52a4:	fa04 f203 	lsl.w	r2, r4, r3
    52a8:	009b      	lsls	r3, r3, #2
    52aa:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    52ae:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    52b2:	ea25 0502 	bic.w	r5, r5, r2
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    52b6:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    52ba:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    52be:	f3c0 2004 	ubfx	r0, r0, #8, #5
    52c2:	f3c1 4101 	ubfx	r1, r1, #16, #2
    52c6:	f7ff fcf7 	bl	4cb8 <call_handler>
    while (mask)
    52ca:	2d00      	cmp	r5, #0
    52cc:	d1e6      	bne.n	529c <nrfx_gpiote_irq_handler+0x108>
        port_event_handle();
    }

    /* Process pin events. */
    gpiote_evt_handle(status);
}
    52ce:	b003      	add	sp, #12
    52d0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    52d4:	40006100 	.word	0x40006100
    52d8:	40006000 	.word	0x40006000
    52dc:	40006120 	.word	0x40006120
    52e0:	2000006c 	.word	0x2000006c

000052e4 <nvmc_word_write>:
    52e4:	4a04      	ldr	r2, [pc, #16]	; (52f8 <nvmc_word_write+0x14>)
    52e6:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
{
#if defined(NRF9160_XXAA)
    while (!nrf_nvmc_write_ready_check(NRF_NVMC))
    {}
#else
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    52ea:	07db      	lsls	r3, r3, #31
    52ec:	d5fb      	bpl.n	52e6 <nvmc_word_write+0x2>
    {}
#endif

    *(volatile uint32_t *)addr = value;
    52ee:	6001      	str	r1, [r0, #0]
  __ASM volatile ("dmb 0xF":::"memory");
    52f0:	f3bf 8f5f 	dmb	sy
    __DMB();
}
    52f4:	4770      	bx	lr
    52f6:	bf00      	nop
    52f8:	4001e000 	.word	0x4001e000

000052fc <nrfx_nvmc_page_erase>:
NRF_STATIC_INLINE uint32_t nrf_ficr_codepagesize_get(NRF_FICR_Type const * p_reg)
{
#if defined(FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk)
    return p_reg->INFO.CODEPAGESIZE;
#else
    return p_reg->CODEPAGESIZE;
    52fc:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    5300:	691a      	ldr	r2, [r3, #16]
    return !(addr % flash_page_size_get());
    5302:	fbb0 f3f2 	udiv	r3, r0, r2
    5306:	fb02 0313 	mls	r3, r2, r3, r0

nrfx_err_t nrfx_nvmc_page_erase(uint32_t addr)
{
    NRFX_ASSERT(is_valid_address(addr, false));

    if (!is_page_aligned_check(addr))
    530a:	b973      	cbnz	r3, 532a <nrfx_nvmc_page_erase+0x2e>
#endif

NRF_STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg,
                                         nrf_nvmc_mode_t mode)
{
    p_reg->CONFIG = (uint32_t)mode;
    530c:	4b08      	ldr	r3, [pc, #32]	; (5330 <nrfx_nvmc_page_erase+0x34>)
    530e:	2202      	movs	r2, #2
    5310:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    else
    {
        p_reg->ERASEPCR1 = page_addr;
    }
#elif defined(NRF52_SERIES)
    p_reg->ERASEPAGE = page_addr;
    5314:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    5318:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
        return NRFX_ERROR_INVALID_ADDR;
    }

    nvmc_erase_mode_set();
    nrf_nvmc_page_erase_start(NRF_NVMC, addr);
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    531c:	07d2      	lsls	r2, r2, #31
    531e:	d5fb      	bpl.n	5318 <nrfx_nvmc_page_erase+0x1c>
    p_reg->CONFIG = (uint32_t)mode;
    5320:	2200      	movs	r2, #0
    {}
    nvmc_readonly_mode_set();

    return NRFX_SUCCESS;
    5322:	4804      	ldr	r0, [pc, #16]	; (5334 <nrfx_nvmc_page_erase+0x38>)
    5324:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    5328:	4770      	bx	lr
        return NRFX_ERROR_INVALID_ADDR;
    532a:	4803      	ldr	r0, [pc, #12]	; (5338 <nrfx_nvmc_page_erase+0x3c>)
}
    532c:	4770      	bx	lr
    532e:	bf00      	nop
    5330:	4001e000 	.word	0x4001e000
    5334:	0bad0000 	.word	0x0bad0000
    5338:	0bad000a 	.word	0x0bad000a

0000533c <nrfx_nvmc_word_write>:

    nrfx_nvmc_word_write(aligned_addr, partial_word_create(addr, (const uint8_t *)&value, 2));
}

void nrfx_nvmc_word_write(uint32_t addr, uint32_t value)
{
    533c:	b510      	push	{r4, lr}
    533e:	4c05      	ldr	r4, [pc, #20]	; (5354 <nrfx_nvmc_word_write+0x18>)
    5340:	2301      	movs	r3, #1
    5342:	f8c4 3504 	str.w	r3, [r4, #1284]	; 0x504
    NRFX_ASSERT(is_valid_address(addr, true));
    NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));

    nvmc_write_mode_set();

    nvmc_word_write(addr, value);
    5346:	f7ff ffcd 	bl	52e4 <nvmc_word_write>
    534a:	2300      	movs	r3, #0
    534c:	f8c4 3504 	str.w	r3, [r4, #1284]	; 0x504

    nvmc_readonly_mode_set();
}
    5350:	bd10      	pop	{r4, pc}
    5352:	bf00      	nop
    5354:	4001e000 	.word	0x4001e000

00005358 <nrfx_ppi_channel_alloc>:
    nrfx_flag32_init(&m_groups_allocated, NRFX_PPI_ALL_APP_GROUPS_MASK);
}


nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel)
{
    5358:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_channels_allocated, (uint8_t *)p_channel);
    535a:	4801      	ldr	r0, [pc, #4]	; (5360 <nrfx_ppi_channel_alloc+0x8>)
    535c:	f7ff bb6a 	b.w	4a34 <nrfx_flag32_alloc>
    5360:	200000c8 	.word	0x200000c8

00005364 <_DoInit>:
                      _DoInit();                                                                     \
                    }                                                                                \
                  } while (0);                                                                       \
                }

static void _DoInit(void) {
    5364:	b510      	push	{r4, lr}
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    5366:	4c14      	ldr	r4, [pc, #80]	; (53b8 <_DoInit+0x54>)
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    5368:	4a14      	ldr	r2, [pc, #80]	; (53bc <_DoInit+0x58>)
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    536a:	4915      	ldr	r1, [pc, #84]	; (53c0 <_DoInit+0x5c>)
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    536c:	2303      	movs	r3, #3
    536e:	6123      	str	r3, [r4, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    5370:	6163      	str	r3, [r4, #20]
  p->aUp[0].pBuffer       = _acUpBuffer;
    5372:	4b14      	ldr	r3, [pc, #80]	; (53c4 <_DoInit+0x60>)
  p->aUp[0].sName         = "Terminal";
    5374:	61a2      	str	r2, [r4, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    5376:	61e3      	str	r3, [r4, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    5378:	f44f 6380 	mov.w	r3, #1024	; 0x400
    537c:	6223      	str	r3, [r4, #32]
  p->aUp[0].RdOff         = 0u;
    537e:	2300      	movs	r3, #0
    5380:	62a3      	str	r3, [r4, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    5382:	6263      	str	r3, [r4, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    5384:	62e3      	str	r3, [r4, #44]	; 0x2c
  p->aDown[0].sName         = "Terminal";
    5386:	6622      	str	r2, [r4, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    5388:	4a0f      	ldr	r2, [pc, #60]	; (53c8 <_DoInit+0x64>)
    538a:	6662      	str	r2, [r4, #100]	; 0x64
  STRCPY((char*)&p->acID[7], "RTT");
    538c:	1de0      	adds	r0, r4, #7
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    538e:	2210      	movs	r2, #16
    5390:	66a2      	str	r2, [r4, #104]	; 0x68
  p->aDown[0].RdOff         = 0u;
    5392:	6723      	str	r3, [r4, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    5394:	66e3      	str	r3, [r4, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    5396:	6763      	str	r3, [r4, #116]	; 0x74
  STRCPY((char*)&p->acID[7], "RTT");
    5398:	f001 f862 	bl	6460 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    539c:	f3bf 8f5f 	dmb	sy
  STRCPY((char*)&p->acID[0], "SEGGER");
    53a0:	490a      	ldr	r1, [pc, #40]	; (53cc <_DoInit+0x68>)
    53a2:	4620      	mov	r0, r4
    53a4:	f001 f85c 	bl	6460 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    53a8:	f3bf 8f5f 	dmb	sy
  p->acID[6] = ' ';
    53ac:	2320      	movs	r3, #32
    53ae:	71a3      	strb	r3, [r4, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    53b0:	f3bf 8f5f 	dmb	sy
}
    53b4:	bd10      	pop	{r4, pc}
    53b6:	bf00      	nop
    53b8:	200012e8 	.word	0x200012e8
    53bc:	00009b1e 	.word	0x00009b1e
    53c0:	00009b27 	.word	0x00009b27
    53c4:	2000314c 	.word	0x2000314c
    53c8:	2000313c 	.word	0x2000313c
    53cc:	00009b2b 	.word	0x00009b2b

000053d0 <SEGGER_RTT_WriteNoLock>:
*    (1) Data is stored according to buffer flags.
*    (2) For performance reasons this function does not call Init()
*        and may only be called after RTT has been initialized.
*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
*/
unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
    53d0:	b570      	push	{r4, r5, r6, lr}
  SEGGER_RTT_BUFFER_UP* pRing;
  //
  // Get "to-host" ring buffer.
  //
  pData = (const char *)pBuffer;
  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
    53d2:	4b16      	ldr	r3, [pc, #88]	; (542c <SEGGER_RTT_WriteNoLock+0x5c>)
    53d4:	2418      	movs	r4, #24
    53d6:	fb00 4504 	mla	r5, r0, r4, r4
    53da:	441d      	add	r5, r3
  //
  // How we output depends upon the mode...
  //
  switch (pRing->Flags) {
    53dc:	fb04 3300 	mla	r3, r4, r0, r3
unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
    53e0:	4616      	mov	r6, r2
  switch (pRing->Flags) {
    53e2:	6adc      	ldr	r4, [r3, #44]	; 0x2c
    53e4:	2c01      	cmp	r4, #1
    53e6:	d00e      	beq.n	5406 <SEGGER_RTT_WriteNoLock+0x36>
    53e8:	2c02      	cmp	r4, #2
    53ea:	d018      	beq.n	541e <SEGGER_RTT_WriteNoLock+0x4e>
    53ec:	b9e4      	cbnz	r4, 5428 <SEGGER_RTT_WriteNoLock+0x58>
  case SEGGER_RTT_MODE_NO_BLOCK_SKIP:
    //
    // If we are in skip mode and there is no space for the whole
    // of this output, don't bother.
    //
    Avail = _GetAvailWriteSpace(pRing);
    53ee:	4628      	mov	r0, r5
    53f0:	f003 f919 	bl	8626 <_GetAvailWriteSpace>
    if (Avail < NumBytes) {
    53f4:	4286      	cmp	r6, r0
    53f6:	d804      	bhi.n	5402 <SEGGER_RTT_WriteNoLock+0x32>
      Status = 0u;
    } else {
      Status = NumBytes;
      _WriteNoCheck(pRing, pData, NumBytes);
    53f8:	4632      	mov	r2, r6
    53fa:	4628      	mov	r0, r5
    53fc:	f003 f91c 	bl	8638 <_WriteNoCheck>
    5400:	4634      	mov	r4, r6
  }
  //
  // Finish up.
  //
  return Status;
}
    5402:	4620      	mov	r0, r4
    5404:	bd70      	pop	{r4, r5, r6, pc}
    Avail = _GetAvailWriteSpace(pRing);
    5406:	4628      	mov	r0, r5
    5408:	f003 f90d 	bl	8626 <_GetAvailWriteSpace>
    Status = Avail < NumBytes ? Avail : NumBytes;
    540c:	4286      	cmp	r6, r0
    540e:	4634      	mov	r4, r6
    5410:	bf28      	it	cs
    5412:	4604      	movcs	r4, r0
    _WriteNoCheck(pRing, pData, Status);
    5414:	4622      	mov	r2, r4
    5416:	4628      	mov	r0, r5
    5418:	f003 f90e 	bl	8638 <_WriteNoCheck>
    break;
    541c:	e7f1      	b.n	5402 <SEGGER_RTT_WriteNoLock+0x32>
    Status = _WriteBlocking(pRing, pData, NumBytes);
    541e:	4628      	mov	r0, r5
}
    5420:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    Status = _WriteBlocking(pRing, pData, NumBytes);
    5424:	f003 b926 	b.w	8674 <_WriteBlocking>
  switch (pRing->Flags) {
    5428:	2400      	movs	r4, #0
  return Status;
    542a:	e7ea      	b.n	5402 <SEGGER_RTT_WriteNoLock+0x32>
    542c:	200012e8 	.word	0x200012e8

00005430 <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    5430:	4b0e      	ldr	r3, [pc, #56]	; (546c <z_sys_init_run_level+0x3c>)
{
    5432:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    5434:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    5438:	3001      	adds	r0, #1
    543a:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    543e:	42a6      	cmp	r6, r4
    5440:	d800      	bhi.n	5444 <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    5442:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    5444:	e9d4 3500 	ldrd	r3, r5, [r4]
    5448:	4628      	mov	r0, r5
    544a:	4798      	blx	r3
		if (dev != NULL) {
    544c:	b165      	cbz	r5, 5468 <z_sys_init_run_level+0x38>
				dev->state->init_res = rc;
    544e:	68eb      	ldr	r3, [r5, #12]
			if (rc != 0) {
    5450:	b130      	cbz	r0, 5460 <z_sys_init_run_level+0x30>
				if (rc < 0) {
    5452:	2800      	cmp	r0, #0
    5454:	bfb8      	it	lt
    5456:	4240      	neglt	r0, r0
				dev->state->init_res = rc;
    5458:	28ff      	cmp	r0, #255	; 0xff
    545a:	bfa8      	it	ge
    545c:	20ff      	movge	r0, #255	; 0xff
    545e:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    5460:	785a      	ldrb	r2, [r3, #1]
    5462:	f042 0201 	orr.w	r2, r2, #1
    5466:	705a      	strb	r2, [r3, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    5468:	3408      	adds	r4, #8
    546a:	e7e8      	b.n	543e <z_sys_init_run_level+0xe>
    546c:	00008c68 	.word	0x00008c68

00005470 <z_impl_device_get_binding>:

const struct device *z_impl_device_get_binding(const char *name)
{
    5470:	b570      	push	{r4, r5, r6, lr}
	const struct device *dev;

	/* A null string identifies no device.  So does an empty
	 * string.
	 */
	if ((name == NULL) || (name[0] == '\0')) {
    5472:	4605      	mov	r5, r0
    5474:	b910      	cbnz	r0, 547c <z_impl_device_get_binding+0xc>
		return NULL;
    5476:	2400      	movs	r4, #0
			return dev;
		}
	}

	return NULL;
}
    5478:	4620      	mov	r0, r4
    547a:	bd70      	pop	{r4, r5, r6, pc}
	if ((name == NULL) || (name[0] == '\0')) {
    547c:	7803      	ldrb	r3, [r0, #0]
    547e:	2b00      	cmp	r3, #0
    5480:	d0f9      	beq.n	5476 <z_impl_device_get_binding+0x6>
	for (dev = __device_start; dev != __device_end; dev++) {
    5482:	4c0e      	ldr	r4, [pc, #56]	; (54bc <z_impl_device_get_binding+0x4c>)
    5484:	4e0e      	ldr	r6, [pc, #56]	; (54c0 <z_impl_device_get_binding+0x50>)
    5486:	42b4      	cmp	r4, r6
    5488:	d108      	bne.n	549c <z_impl_device_get_binding+0x2c>
	for (dev = __device_start; dev != __device_end; dev++) {
    548a:	4c0c      	ldr	r4, [pc, #48]	; (54bc <z_impl_device_get_binding+0x4c>)
    548c:	42b4      	cmp	r4, r6
    548e:	d0f2      	beq.n	5476 <z_impl_device_get_binding+0x6>
		if (z_device_is_ready(dev) && (strcmp(name, dev->name) == 0)) {
    5490:	4620      	mov	r0, r4
    5492:	f003 f923 	bl	86dc <z_device_is_ready>
    5496:	b950      	cbnz	r0, 54ae <z_impl_device_get_binding+0x3e>
	for (dev = __device_start; dev != __device_end; dev++) {
    5498:	3418      	adds	r4, #24
    549a:	e7f7      	b.n	548c <z_impl_device_get_binding+0x1c>
		if (z_device_is_ready(dev) && (dev->name == name)) {
    549c:	4620      	mov	r0, r4
    549e:	f003 f91d 	bl	86dc <z_device_is_ready>
    54a2:	b110      	cbz	r0, 54aa <z_impl_device_get_binding+0x3a>
    54a4:	6823      	ldr	r3, [r4, #0]
    54a6:	42ab      	cmp	r3, r5
    54a8:	d0e6      	beq.n	5478 <z_impl_device_get_binding+0x8>
	for (dev = __device_start; dev != __device_end; dev++) {
    54aa:	3418      	adds	r4, #24
    54ac:	e7eb      	b.n	5486 <z_impl_device_get_binding+0x16>
		if (z_device_is_ready(dev) && (strcmp(name, dev->name) == 0)) {
    54ae:	6821      	ldr	r1, [r4, #0]
    54b0:	4628      	mov	r0, r5
    54b2:	f000 ffe6 	bl	6482 <strcmp>
    54b6:	2800      	cmp	r0, #0
    54b8:	d1ee      	bne.n	5498 <z_impl_device_get_binding+0x28>
    54ba:	e7dd      	b.n	5478 <z_impl_device_get_binding+0x8>
    54bc:	00008764 	.word	0x00008764
    54c0:	000087c4 	.word	0x000087c4

000054c4 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    54c4:	b573      	push	{r0, r1, r4, r5, r6, lr}
    54c6:	4604      	mov	r4, r0
    54c8:	460d      	mov	r5, r1
	__asm__ volatile(
    54ca:	f04f 0320 	mov.w	r3, #32
    54ce:	f3ef 8611 	mrs	r6, BASEPRI
    54d2:	f383 8812 	msr	BASEPRI_MAX, r3
    54d6:	f3bf 8f6f 	isb	sy
	switch (reason) {
    54da:	2804      	cmp	r0, #4
    54dc:	bf96      	itet	ls
    54de:	4b12      	ldrls	r3, [pc, #72]	; (5528 <z_fatal_error+0x64>)
    54e0:	4b12      	ldrhi	r3, [pc, #72]	; (552c <z_fatal_error+0x68>)
	return 0;
    54e2:	f853 3020 	ldrls.w	r3, [r3, r0, lsl #2]
			k_current_get() : NULL;

	/* twister looks for the "ZEPHYR FATAL ERROR" string, don't
	 * change it without also updating twister
	 */
	LOG_ERR(">>> ZEPHYR FATAL ERROR %d: %s on CPU %d", reason,
    54e6:	2200      	movs	r2, #0
    54e8:	9200      	str	r2, [sp, #0]
    54ea:	2145      	movs	r1, #69	; 0x45
    54ec:	4602      	mov	r2, r0
    54ee:	4810      	ldr	r0, [pc, #64]	; (5530 <z_fatal_error+0x6c>)
    54f0:	f000 fca5 	bl	5e3e <z_log_minimal_printk>
	 * an IRQ or exception was being handled, or thread context.
	 *
	 * See #17656
	 */
#if defined(CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION)
	if ((esf != NULL) && arch_is_in_nested_exception(esf)) {
    54f4:	b13d      	cbz	r5, 5506 <z_fatal_error+0x42>
 * @return true if execution state was in handler mode, before
 *              the current exception occurred, otherwise false.
 */
static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf)
{
	return (esf->basic.xpsr & IPSR_ISR_Msk) ? (true) : (false);
    54f6:	69eb      	ldr	r3, [r5, #28]
    54f8:	f3c3 0308 	ubfx	r3, r3, #0, #9
    54fc:	b11b      	cbz	r3, 5506 <z_fatal_error+0x42>
		LOG_ERR("Fault during interrupt handling\n");
    54fe:	480d      	ldr	r0, [pc, #52]	; (5534 <z_fatal_error+0x70>)
    5500:	2145      	movs	r1, #69	; 0x45
    5502:	f000 fc9c 	bl	5e3e <z_log_minimal_printk>
	}
#endif

	LOG_ERR("Current thread: %p (%s)", thread,
    5506:	4b0c      	ldr	r3, [pc, #48]	; (5538 <z_fatal_error+0x74>)
    5508:	480c      	ldr	r0, [pc, #48]	; (553c <z_fatal_error+0x78>)
    550a:	2200      	movs	r2, #0
    550c:	2145      	movs	r1, #69	; 0x45
    550e:	f000 fc96 	bl	5e3e <z_log_minimal_printk>
		log_strdup(thread_name_get(thread)));

	coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    5512:	4629      	mov	r1, r5
    5514:	4620      	mov	r0, r4
    5516:	f7fe fcd1 	bl	3ebc <k_sys_fatal_error_handler>
	__asm__ volatile(
    551a:	f386 8811 	msr	BASEPRI, r6
    551e:	f3bf 8f6f 	isb	sy
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    5522:	b002      	add	sp, #8
    5524:	bd70      	pop	{r4, r5, r6, pc}
    5526:	bf00      	nop
    5528:	00008c7c 	.word	0x00008c7c
    552c:	00009b32 	.word	0x00009b32
    5530:	00009b40 	.word	0x00009b40
    5534:	00009b6d 	.word	0x00009b6d
    5538:	00009b93 	.word	0x00009b93
    553c:	00009b9b 	.word	0x00009b9b

00005540 <bg_thread_main>:
 * This routine completes kernel initialization by invoking the remaining
 * init functions, then invokes application's main() routine.
 */
__boot_func
static void bg_thread_main(void *unused1, void *unused2, void *unused3)
{
    5540:	b508      	push	{r3, lr}
	 * may perform memory management tasks (except for z_phys_map() which
	 * is allowed at any time)
	 */
	z_mem_manage_init();
#endif /* CONFIG_MMU */
	z_sys_post_kernel = true;
    5542:	4b09      	ldr	r3, [pc, #36]	; (5568 <bg_thread_main+0x28>)
    5544:	2201      	movs	r2, #1

	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    5546:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
    5548:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    554a:	f7ff ff71 	bl	5430 <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    554e:	f000 f909 	bl	5764 <boot_banner>
	void z_cpp_init_static(void);
	z_cpp_init_static();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    5552:	2003      	movs	r0, #3
    5554:	f7ff ff6c 	bl	5430 <z_sys_init_run_level>
	z_mem_manage_boot_finish();
#endif /* CONFIG_MMU */

	extern void main(void);

	main();
    5558:	f7fa ff2e 	bl	3b8 <main>

	/* Mark nonessential since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    555c:	4a03      	ldr	r2, [pc, #12]	; (556c <bg_thread_main+0x2c>)
    555e:	7b13      	ldrb	r3, [r2, #12]
    5560:	f023 0301 	bic.w	r3, r3, #1
    5564:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    5566:	bd08      	pop	{r3, pc}
    5568:	2000354c 	.word	0x2000354c
    556c:	20000108 	.word	0x20000108

00005570 <z_bss_zero>:
{
    5570:	b508      	push	{r3, lr}
	z_early_memset(__bss_start, 0, __bss_end - __bss_start);
    5572:	4803      	ldr	r0, [pc, #12]	; (5580 <z_bss_zero+0x10>)
    5574:	4a03      	ldr	r2, [pc, #12]	; (5584 <z_bss_zero+0x14>)
    5576:	2100      	movs	r1, #0
    5578:	1a12      	subs	r2, r2, r0
    557a:	f003 f8b9 	bl	86f0 <z_early_memset>
}
    557e:	bd08      	pop	{r3, pc}
    5580:	200000e8 	.word	0x200000e8
    5584:	20003550 	.word	0x20003550

00005588 <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    5588:	b508      	push	{r3, lr}
 * pointer) register, and switched to automatically when taking an exception.
 *
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    558a:	4b19      	ldr	r3, [pc, #100]	; (55f0 <z_cstart+0x68>)
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    558c:	f383 8808 	msr	MSP, r3
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    5590:	4c18      	ldr	r4, [pc, #96]	; (55f4 <z_cstart+0x6c>)
    5592:	6963      	ldr	r3, [r4, #20]
    5594:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    5598:	6163      	str	r3, [r4, #20]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    559a:	2500      	movs	r5, #0
    559c:	23e0      	movs	r3, #224	; 0xe0
    559e:	f884 3022 	strb.w	r3, [r4, #34]	; 0x22
    55a2:	77e5      	strb	r5, [r4, #31]
    55a4:	7625      	strb	r5, [r4, #24]
    55a6:	7665      	strb	r5, [r4, #25]
    55a8:	76a5      	strb	r5, [r4, #26]
    55aa:	f884 5020 	strb.w	r5, [r4, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    55ae:	6a63      	ldr	r3, [r4, #36]	; 0x24
    55b0:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    55b4:	6263      	str	r3, [r4, #36]	; 0x24
    55b6:	f884 5023 	strb.w	r5, [r4, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    55ba:	f7fd fbcb 	bl	2d54 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    55be:	f7fd f8f1 	bl	27a4 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    55c2:	f04f 33ff 	mov.w	r3, #4294967295
    55c6:	62a3      	str	r3, [r4, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    55c8:	62e3      	str	r3, [r4, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    55ca:	f7fd fccb 	bl	2f64 <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    55ce:	f7fd fc4d 	bl	2e6c <z_arm_configure_static_mpu_regions>
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    55d2:	f003 f882 	bl	86da <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    55d6:	4628      	mov	r0, r5
    55d8:	f7ff ff2a 	bl	5430 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    55dc:	2001      	movs	r0, #1
    55de:	f7ff ff27 	bl	5430 <z_sys_init_run_level>
#else
#ifdef ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING
	/* Custom ARCH-specific routine to switch to main()
	 * in the case of no multi-threading.
	 */
	ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING(bg_thread_main,
    55e2:	4805      	ldr	r0, [pc, #20]	; (55f8 <z_cstart+0x70>)
    55e4:	462b      	mov	r3, r5
    55e6:	462a      	mov	r2, r5
    55e8:	4629      	mov	r1, r5
    55ea:	f7fd f9a3 	bl	2934 <z_arm_switch_to_main_no_multithreading>
    55ee:	bf00      	nop
    55f0:	200065a0 	.word	0x200065a0
    55f4:	e000ed00 	.word	0xe000ed00
    55f8:	00005541 	.word	0x00005541

000055fc <z_data_copy>:
 * @brief Copy the data section from ROM to RAM
 *
 * This routine copies the data section from ROM to RAM.
 */
void z_data_copy(void)
{
    55fc:	b508      	push	{r3, lr}
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
		       __data_region_end - __data_region_start);
    55fe:	4806      	ldr	r0, [pc, #24]	; (5618 <z_data_copy+0x1c>)
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
    5600:	4a06      	ldr	r2, [pc, #24]	; (561c <z_data_copy+0x20>)
    5602:	4907      	ldr	r1, [pc, #28]	; (5620 <z_data_copy+0x24>)
    5604:	1a12      	subs	r2, r2, r0
    5606:	f003 f875 	bl	86f4 <z_early_memcpy>
#else
	z_early_memcpy(&_app_smem_start, &_app_smem_rom_start,
		       _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    560a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_early_memcpy(&__ramfunc_start, &__ramfunc_load_start,
    560e:	4a05      	ldr	r2, [pc, #20]	; (5624 <z_data_copy+0x28>)
    5610:	4905      	ldr	r1, [pc, #20]	; (5628 <z_data_copy+0x2c>)
    5612:	4806      	ldr	r0, [pc, #24]	; (562c <z_data_copy+0x30>)
    5614:	f003 b86e 	b.w	86f4 <z_early_memcpy>
    5618:	20000000 	.word	0x20000000
    561c:	200000e4 	.word	0x200000e4
    5620:	00009c3c 	.word	0x00009c3c
    5624:	00000000 	.word	0x00000000
    5628:	00009c3c 	.word	0x00009c3c
    562c:	20000000 	.word	0x20000000

00005630 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    5630:	4b03      	ldr	r3, [pc, #12]	; (5640 <elapsed+0x10>)
    5632:	681b      	ldr	r3, [r3, #0]
    5634:	b90b      	cbnz	r3, 563a <elapsed+0xa>
    5636:	f7fe bc37 	b.w	3ea8 <sys_clock_elapsed>
}
    563a:	2000      	movs	r0, #0
    563c:	4770      	bx	lr
    563e:	bf00      	nop
    5640:	20001390 	.word	0x20001390

00005644 <next_timeout>:
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    5644:	4b0d      	ldr	r3, [pc, #52]	; (567c <next_timeout+0x38>)

static int32_t next_timeout(void)
{
    5646:	b510      	push	{r4, lr}
    5648:	681c      	ldr	r4, [r3, #0]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    564a:	429c      	cmp	r4, r3
    564c:	bf08      	it	eq
    564e:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    5650:	f7ff ffee 	bl	5630 <elapsed>
	int32_t ret;

	if ((to == NULL) ||
    5654:	b174      	cbz	r4, 5674 <next_timeout+0x30>
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
    5656:	e9d4 3204 	ldrd	r3, r2, [r4, #16]
    565a:	1a1b      	subs	r3, r3, r0
    565c:	eb62 70e0 	sbc.w	r0, r2, r0, asr #31
	if ((to == NULL) ||
    5660:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    5664:	f170 0200 	sbcs.w	r2, r0, #0
    5668:	da04      	bge.n	5674 <next_timeout+0x30>
		ret = MAX_WAIT;
	} else {
		ret = MAX(0, to->dticks - ticks_elapsed);
    566a:	2800      	cmp	r0, #0
    566c:	bfac      	ite	ge
    566e:	4618      	movge	r0, r3
    5670:	2000      	movlt	r0, #0
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    5672:	bd10      	pop	{r4, pc}
		ret = MAX_WAIT;
    5674:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
	return ret;
    5678:	e7fb      	b.n	5672 <next_timeout+0x2e>
    567a:	bf00      	nop
    567c:	200000cc 	.word	0x200000cc

00005680 <remove_timeout>:
{
    5680:	b530      	push	{r4, r5, lr}
 */

static inline sys_dnode_t *sys_dlist_peek_next_no_check(sys_dlist_t *list,
							sys_dnode_t *node)
{
	return (node == list->tail) ? NULL : node->next;
    5682:	6803      	ldr	r3, [r0, #0]
 */

static inline sys_dnode_t *sys_dlist_peek_next(sys_dlist_t *list,
					       sys_dnode_t *node)
{
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    5684:	b168      	cbz	r0, 56a2 <remove_timeout+0x22>
	return (node == list->tail) ? NULL : node->next;
    5686:	4a0a      	ldr	r2, [pc, #40]	; (56b0 <remove_timeout+0x30>)
    5688:	6852      	ldr	r2, [r2, #4]
    568a:	4290      	cmp	r0, r2
    568c:	d009      	beq.n	56a2 <remove_timeout+0x22>
	if (next(t) != NULL) {
    568e:	b143      	cbz	r3, 56a2 <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    5690:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    5694:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    5698:	1912      	adds	r2, r2, r4
    569a:	eb41 0105 	adc.w	r1, r1, r5
    569e:	e9c3 2104 	strd	r2, r1, [r3, #16]
 * @param node the node to remove
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
    56a2:	6842      	ldr	r2, [r0, #4]
	sys_dnode_t *const next = node->next;

	prev->next = next;
    56a4:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    56a6:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    56a8:	2300      	movs	r3, #0
	node->prev = NULL;
    56aa:	e9c0 3300 	strd	r3, r3, [r0]
}
    56ae:	bd30      	pop	{r4, r5, pc}
    56b0:	200000cc 	.word	0x200000cc

000056b4 <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    56b4:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	__asm__ volatile(
    56b8:	f04f 0320 	mov.w	r3, #32
    56bc:	f3ef 8411 	mrs	r4, BASEPRI
    56c0:	f383 8812 	msr	BASEPRI_MAX, r3
    56c4:	f3bf 8f6f 	isb	sy
		announce_remaining += ticks;
		k_spin_unlock(&timeout_lock, key);
		return;
	}

	announce_remaining = ticks;
    56c8:	4e23      	ldr	r6, [pc, #140]	; (5758 <sys_clock_announce+0xa4>)
	return list->head == list;
    56ca:	f8df 8090 	ldr.w	r8, [pc, #144]	; 575c <sys_clock_announce+0xa8>

	while (first() != NULL && first()->dticks <= announce_remaining) {
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    56ce:	4d24      	ldr	r5, [pc, #144]	; (5760 <sys_clock_announce+0xac>)
	announce_remaining = ticks;
    56d0:	6030      	str	r0, [r6, #0]
    56d2:	f8d8 0000 	ldr.w	r0, [r8]
	while (first() != NULL && first()->dticks <= announce_remaining) {
    56d6:	6832      	ldr	r2, [r6, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    56d8:	4540      	cmp	r0, r8
		curr_tick += dt;
    56da:	e9d5 1e00 	ldrd	r1, lr, [r5]
    56de:	ea4f 77e2 	mov.w	r7, r2, asr #31
    56e2:	d00b      	beq.n	56fc <sys_clock_announce+0x48>
	while (first() != NULL && first()->dticks <= announce_remaining) {
    56e4:	b150      	cbz	r0, 56fc <sys_clock_announce+0x48>
    56e6:	e9d0 3c04 	ldrd	r3, ip, [r0, #16]
    56ea:	429a      	cmp	r2, r3
    56ec:	eb77 090c 	sbcs.w	r9, r7, ip
    56f0:	da16      	bge.n	5720 <sys_clock_announce+0x6c>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    56f2:	1a9b      	subs	r3, r3, r2
    56f4:	eb6c 0c07 	sbc.w	ip, ip, r7
    56f8:	e9c0 3c04 	strd	r3, ip, [r0, #16]
	}

	curr_tick += announce_remaining;
    56fc:	1852      	adds	r2, r2, r1
    56fe:	eb4e 0707 	adc.w	r7, lr, r7
    5702:	e9c5 2700 	strd	r2, r7, [r5]
	announce_remaining = 0;
    5706:	2500      	movs	r5, #0
    5708:	6035      	str	r5, [r6, #0]

	sys_clock_set_timeout(next_timeout(), false);
    570a:	f7ff ff9b 	bl	5644 <next_timeout>
    570e:	4629      	mov	r1, r5
    5710:	f7fe fb98 	bl	3e44 <sys_clock_set_timeout>
	__asm__ volatile(
    5714:	f384 8811 	msr	BASEPRI, r4
    5718:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    571c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		curr_tick += dt;
    5720:	1859      	adds	r1, r3, r1
    5722:	eb4e 77e3 	adc.w	r7, lr, r3, asr #31
		announce_remaining -= dt;
    5726:	1ad3      	subs	r3, r2, r3
    5728:	6033      	str	r3, [r6, #0]
		t->dticks = 0;
    572a:	2200      	movs	r2, #0
    572c:	2300      	movs	r3, #0
    572e:	e9c0 2304 	strd	r2, r3, [r0, #16]
		curr_tick += dt;
    5732:	e9c5 1700 	strd	r1, r7, [r5]
		remove_timeout(t);
    5736:	f7ff ffa3 	bl	5680 <remove_timeout>
    573a:	f384 8811 	msr	BASEPRI, r4
    573e:	f3bf 8f6f 	isb	sy
		t->fn(t);
    5742:	6883      	ldr	r3, [r0, #8]
    5744:	4798      	blx	r3
	__asm__ volatile(
    5746:	f04f 0320 	mov.w	r3, #32
    574a:	f3ef 8411 	mrs	r4, BASEPRI
    574e:	f383 8812 	msr	BASEPRI_MAX, r3
    5752:	f3bf 8f6f 	isb	sy
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    5756:	e7bc      	b.n	56d2 <sys_clock_announce+0x1e>
    5758:	20001390 	.word	0x20001390
    575c:	200000cc 	.word	0x200000cc
    5760:	20000188 	.word	0x20000188

00005764 <boot_banner>:
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
    5764:	4a02      	ldr	r2, [pc, #8]	; (5770 <boot_banner+0xc>)
    5766:	4903      	ldr	r1, [pc, #12]	; (5774 <boot_banner+0x10>)
    5768:	4803      	ldr	r0, [pc, #12]	; (5778 <boot_banner+0x14>)
    576a:	f000 baaf 	b.w	5ccc <printk>
    576e:	bf00      	nop
    5770:	00009b92 	.word	0x00009b92
    5774:	00009c05 	.word	0x00009c05
    5778:	00009c12 	.word	0x00009c12

0000577c <flash_area_id_from_multi_image_slot>:
    switch (slot) {
    577c:	b129      	cbz	r1, 578a <flash_area_id_from_multi_image_slot+0xe>
    577e:	2901      	cmp	r1, #1
    5780:	bf14      	ite	ne
    5782:	f06f 0015 	mvnne.w	r0, #21
    5786:	2005      	moveq	r0, #5
    5788:	4770      	bx	lr
    case 0: return FLASH_AREA_IMAGE_PRIMARY(image_index);
    578a:	2002      	movs	r0, #2
}
    578c:	4770      	bx	lr

0000578e <flash_area_get_device_id>:

uint8_t flash_area_get_device_id(const struct flash_area *fa)
{
	(void)fa;
	return FLASH_DEVICE_ID;
}
    578e:	2000      	movs	r0, #0
    5790:	4770      	bx	lr

00005792 <bootutil_tlv_iter_begin>:
 *          -1 on errors
 */
int
bootutil_tlv_iter_begin(struct image_tlv_iter *it, const struct image_header *hdr,
                        const struct flash_area *fap, uint16_t type, bool prot)
{
    5792:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    5796:	460e      	mov	r6, r1
    5798:	4617      	mov	r7, r2
    579a:	4699      	mov	r9, r3
    uint32_t off_;
    struct image_tlv_info info;

    if (it == NULL || hdr == NULL || fap == NULL) {
    579c:	4604      	mov	r4, r0
    579e:	b928      	cbnz	r0, 57ac <bootutil_tlv_iter_begin+0x1a>
        return -1;
    57a0:	f04f 38ff 	mov.w	r8, #4294967295
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    // position on first TLV
    it->tlv_off = off_ + sizeof(info);
    return 0;
}
    57a4:	4640      	mov	r0, r8
    57a6:	b003      	add	sp, #12
    57a8:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    if (it == NULL || hdr == NULL || fap == NULL) {
    57ac:	2900      	cmp	r1, #0
    57ae:	d0f7      	beq.n	57a0 <bootutil_tlv_iter_begin+0xe>
    57b0:	2a00      	cmp	r2, #0
    57b2:	d0f5      	beq.n	57a0 <bootutil_tlv_iter_begin+0xe>
    off_ = BOOT_TLV_OFF(hdr);
    57b4:	68cb      	ldr	r3, [r1, #12]
    57b6:	890d      	ldrh	r5, [r1, #8]
    57b8:	441d      	add	r5, r3
    if (LOAD_IMAGE_DATA(hdr, fap, off_, &info, sizeof(info))) {
    57ba:	2304      	movs	r3, #4
    57bc:	eb0d 0203 	add.w	r2, sp, r3
    57c0:	4629      	mov	r1, r5
    57c2:	4638      	mov	r0, r7
    57c4:	f000 fb49 	bl	5e5a <flash_area_read>
    57c8:	4680      	mov	r8, r0
    57ca:	2800      	cmp	r0, #0
    57cc:	d1e8      	bne.n	57a0 <bootutil_tlv_iter_begin+0xe>
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    57ce:	f8bd 1004 	ldrh.w	r1, [sp, #4]
        if (hdr->ih_protect_tlv_size != info.it_tlv_tot) {
    57d2:	8973      	ldrh	r3, [r6, #10]
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    57d4:	f646 1208 	movw	r2, #26888	; 0x6908
    57d8:	4291      	cmp	r1, r2
    57da:	d123      	bne.n	5824 <bootutil_tlv_iter_begin+0x92>
        if (hdr->ih_protect_tlv_size != info.it_tlv_tot) {
    57dc:	f8bd 1006 	ldrh.w	r1, [sp, #6]
    57e0:	4299      	cmp	r1, r3
    57e2:	d1dd      	bne.n	57a0 <bootutil_tlv_iter_begin+0xe>
        if (LOAD_IMAGE_DATA(hdr, fap, off_ + info.it_tlv_tot,
    57e4:	2304      	movs	r3, #4
    57e6:	eb0d 0203 	add.w	r2, sp, r3
    57ea:	4429      	add	r1, r5
    57ec:	4638      	mov	r0, r7
    57ee:	f000 fb34 	bl	5e5a <flash_area_read>
    57f2:	2800      	cmp	r0, #0
    57f4:	d1d4      	bne.n	57a0 <bootutil_tlv_iter_begin+0xe>
    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
    57f6:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    57fa:	f646 1307 	movw	r3, #26887	; 0x6907
    57fe:	429a      	cmp	r2, r3
    5800:	d1ce      	bne.n	57a0 <bootutil_tlv_iter_begin+0xe>
    it->prot = prot;
    5802:	f89d 3028 	ldrb.w	r3, [sp, #40]	; 0x28
    5806:	72a3      	strb	r3, [r4, #10]
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    5808:	8973      	ldrh	r3, [r6, #10]
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    580a:	f8bd 2006 	ldrh.w	r2, [sp, #6]
    it->type = type;
    580e:	f8a4 9008 	strh.w	r9, [r4, #8]
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    5812:	442b      	add	r3, r5
    5814:	60e3      	str	r3, [r4, #12]
    it->tlv_off = off_ + sizeof(info);
    5816:	3504      	adds	r5, #4
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    5818:	4413      	add	r3, r2
    it->fap = fap;
    581a:	e9c4 6700 	strd	r6, r7, [r4]
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    581e:	6163      	str	r3, [r4, #20]
    it->tlv_off = off_ + sizeof(info);
    5820:	6125      	str	r5, [r4, #16]
    return 0;
    5822:	e7bf      	b.n	57a4 <bootutil_tlv_iter_begin+0x12>
    } else if (hdr->ih_protect_tlv_size != 0) {
    5824:	2b00      	cmp	r3, #0
    5826:	d0e6      	beq.n	57f6 <bootutil_tlv_iter_begin+0x64>
    5828:	e7ba      	b.n	57a0 <bootutil_tlv_iter_begin+0xe>

0000582a <bootutil_tlv_iter_next>:
 *          -1 on errors
 */
int
bootutil_tlv_iter_next(struct image_tlv_iter *it, uint32_t *off, uint16_t *len,
                       uint16_t *type)
{
    582a:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    582e:	460f      	mov	r7, r1
    5830:	4690      	mov	r8, r2
    5832:	461e      	mov	r6, r3
    struct image_tlv tlv;
    int rc;

    if (it == NULL || it->hdr == NULL || it->fap == NULL) {
    5834:	4604      	mov	r4, r0
    5836:	b920      	cbnz	r0, 5842 <bootutil_tlv_iter_next+0x18>
        return -1;
    5838:	f04f 30ff 	mov.w	r0, #4294967295

        it->tlv_off += sizeof(tlv) + tlv.it_len;
    }

    return 1;
}
    583c:	b003      	add	sp, #12
    583e:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    if (it == NULL || it->hdr == NULL || it->fap == NULL) {
    5842:	6803      	ldr	r3, [r0, #0]
    5844:	2b00      	cmp	r3, #0
    5846:	d0f7      	beq.n	5838 <bootutil_tlv_iter_next+0xe>
    5848:	6843      	ldr	r3, [r0, #4]
    584a:	2b00      	cmp	r3, #0
    584c:	d0f4      	beq.n	5838 <bootutil_tlv_iter_next+0xe>
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    584e:	f64f 79ff 	movw	r9, #65535	; 0xffff
    while (it->tlv_off < it->tlv_end) {
    5852:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    5856:	429a      	cmp	r2, r3
    5858:	d216      	bcs.n	5888 <bootutil_tlv_iter_next+0x5e>
        if (it->hdr->ih_protect_tlv_size > 0 && it->tlv_off == it->prot_end) {
    585a:	6823      	ldr	r3, [r4, #0]
    585c:	895b      	ldrh	r3, [r3, #10]
    585e:	b123      	cbz	r3, 586a <bootutil_tlv_iter_next+0x40>
    5860:	68e3      	ldr	r3, [r4, #12]
    5862:	4293      	cmp	r3, r2
            it->tlv_off += sizeof(struct image_tlv_info);
    5864:	bf04      	itt	eq
    5866:	3304      	addeq	r3, #4
    5868:	6123      	streq	r3, [r4, #16]
        rc = LOAD_IMAGE_DATA(it->hdr, it->fap, it->tlv_off, &tlv, sizeof tlv);
    586a:	2304      	movs	r3, #4
    586c:	6921      	ldr	r1, [r4, #16]
    586e:	6860      	ldr	r0, [r4, #4]
    5870:	eb0d 0203 	add.w	r2, sp, r3
    5874:	f000 faf1 	bl	5e5a <flash_area_read>
        if (rc) {
    5878:	2800      	cmp	r0, #0
    587a:	d1dd      	bne.n	5838 <bootutil_tlv_iter_next+0xe>
        if (it->prot && it->tlv_off >= it->prot_end) {
    587c:	7aa3      	ldrb	r3, [r4, #10]
    587e:	6925      	ldr	r5, [r4, #16]
    5880:	b123      	cbz	r3, 588c <bootutil_tlv_iter_next+0x62>
    5882:	68e3      	ldr	r3, [r4, #12]
    5884:	42ab      	cmp	r3, r5
    5886:	d801      	bhi.n	588c <bootutil_tlv_iter_next+0x62>
            return 1;
    5888:	2001      	movs	r0, #1
    588a:	e7d7      	b.n	583c <bootutil_tlv_iter_next+0x12>
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    588c:	8921      	ldrh	r1, [r4, #8]
        it->tlv_off += sizeof(tlv) + tlv.it_len;
    588e:	f8bd 2006 	ldrh.w	r2, [sp, #6]
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    5892:	4549      	cmp	r1, r9
    5894:	f102 0304 	add.w	r3, r2, #4
    5898:	d003      	beq.n	58a2 <bootutil_tlv_iter_next+0x78>
    589a:	f8bd c004 	ldrh.w	ip, [sp, #4]
    589e:	458c      	cmp	ip, r1
    58a0:	d10b      	bne.n	58ba <bootutil_tlv_iter_next+0x90>
            if (type != NULL) {
    58a2:	b116      	cbz	r6, 58aa <bootutil_tlv_iter_next+0x80>
                *type = tlv.it_type;
    58a4:	f8bd 1004 	ldrh.w	r1, [sp, #4]
    58a8:	8031      	strh	r1, [r6, #0]
            *off = it->tlv_off + sizeof(tlv);
    58aa:	3504      	adds	r5, #4
    58ac:	603d      	str	r5, [r7, #0]
            *len = tlv.it_len;
    58ae:	f8a8 2000 	strh.w	r2, [r8]
            it->tlv_off += sizeof(tlv) + tlv.it_len;
    58b2:	6922      	ldr	r2, [r4, #16]
    58b4:	4413      	add	r3, r2
    58b6:	6123      	str	r3, [r4, #16]
            return 0;
    58b8:	e7c0      	b.n	583c <bootutil_tlv_iter_next+0x12>
        it->tlv_off += sizeof(tlv) + tlv.it_len;
    58ba:	442b      	add	r3, r5
    58bc:	6123      	str	r3, [r4, #16]
    58be:	e7c8      	b.n	5852 <bootutil_tlv_iter_next+0x28>

000058c0 <boot_fih_memequal>:
    return memcmp(s1, s2, n);
    58c0:	f000 bdeb 	b.w	649a <memcmp>

000058c4 <boot_trailer_sz>:
    return BOOT_STATUS_MAX_ENTRIES * boot_status_entry_sz(min_write_sz);
    58c4:	f44f 73c0 	mov.w	r3, #384	; 0x180
    58c8:	4358      	muls	r0, r3
}
    58ca:	3030      	adds	r0, #48	; 0x30
    58cc:	4770      	bx	lr

000058ce <boot_status_entries>:
	return fa->fa_id;
    58ce:	780b      	ldrb	r3, [r1, #0]
    if (flash_area_get_id(fap) == FLASH_AREA_IMAGE_PRIMARY(image_index) ||
    58d0:	2b02      	cmp	r3, #2
    58d2:	d006      	beq.n	58e2 <boot_status_entries+0x14>
    return -1;
    58d4:	2b05      	cmp	r3, #5
    58d6:	bf0c      	ite	eq
    58d8:	f44f 70c0 	moveq.w	r0, #384	; 0x180
    58dc:	f04f 30ff 	movne.w	r0, #4294967295
    58e0:	4770      	bx	lr
        return BOOT_STATUS_STATE_COUNT * BOOT_STATUS_MAX_ENTRIES;
    58e2:	f44f 70c0 	mov.w	r0, #384	; 0x180
}
    58e6:	4770      	bx	lr

000058e8 <boot_status_off>:
{
    58e8:	b510      	push	{r4, lr}
    58ea:	4604      	mov	r4, r0
    elem_sz = flash_area_align(fap);
    58ec:	f000 fb04 	bl	5ef8 <flash_area_align>
    return flash_area_get_size(fap) - off_from_end;
    58f0:	68a3      	ldr	r3, [r4, #8]
}
    58f2:	f44f 72c0 	mov.w	r2, #384	; 0x180
    return flash_area_get_size(fap) - off_from_end;
    58f6:	3b30      	subs	r3, #48	; 0x30
}
    58f8:	fb02 3010 	mls	r0, r2, r0, r3
    58fc:	bd10      	pop	{r4, pc}

000058fe <boot_write_copy_done>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    58fe:	6881      	ldr	r1, [r0, #8]
    5900:	3918      	subs	r1, #24
    5902:	f021 0107 	bic.w	r1, r1, #7

    off = boot_copy_done_off(fap);
    BOOT_LOG_DBG("writing copy_done; fa_id=%d off=0x%lx (0x%lx)",
                 flash_area_get_id(fap), (unsigned long)off,
                 (unsigned long)(flash_area_get_off(fap) + off));
    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
    5906:	2201      	movs	r2, #1
    5908:	3908      	subs	r1, #8
    590a:	f001 ba59 	b.w	6dc0 <boot_write_trailer_flag>

0000590e <boot_write_swap_size>:
}

int
boot_write_swap_size(const struct flash_area *fap, uint32_t swap_size)
{
    590e:	b513      	push	{r0, r1, r4, lr}
    5910:	4604      	mov	r4, r0
    5912:	9101      	str	r1, [sp, #4]
    return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
    5914:	f001 f9f1 	bl	6cfa <boot_swap_info_off>

    off = boot_swap_size_off(fap);
    BOOT_LOG_DBG("writing swap_size; fa_id=%d off=0x%lx (0x%lx)",
                 flash_area_get_id(fap), (unsigned long)off,
                 (unsigned long)flash_area_get_off(fap) + off);
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_size, 4);
    5918:	2304      	movs	r3, #4
    591a:	f1a0 0108 	sub.w	r1, r0, #8
    591e:	eb0d 0203 	add.w	r2, sp, r3
    5922:	4620      	mov	r0, r4
    5924:	f001 fa20 	bl	6d68 <boot_write_trailer>
}
    5928:	b002      	add	sp, #8
    592a:	bd10      	pop	{r4, pc}

0000592c <boot_read_image_headers>:
{
    592c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    592e:	4613      	mov	r3, r2
{
    5930:	460f      	mov	r7, r1
    5932:	4616      	mov	r6, r2
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    5934:	2100      	movs	r1, #0
    5936:	4602      	mov	r2, r0
{
    5938:	4605      	mov	r5, r0
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    593a:	f7fb fa97 	bl	e6c <boot_read_image_header>
        if (rc != 0) {
    593e:	4604      	mov	r4, r0
    5940:	b950      	cbnz	r0, 5958 <boot_read_image_headers+0x2c>
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    5942:	4633      	mov	r3, r6
    5944:	f105 022c 	add.w	r2, r5, #44	; 0x2c
    5948:	2101      	movs	r1, #1
    594a:	4628      	mov	r0, r5
    594c:	f7fb fa8e 	bl	e6c <boot_read_image_header>
        if (rc != 0) {
    5950:	b110      	cbz	r0, 5958 <boot_read_image_headers+0x2c>
            if (i > 0 && !require_all) {
    5952:	2f00      	cmp	r7, #0
    5954:	bf18      	it	ne
    5956:	4604      	movne	r4, r0
}
    5958:	4620      	mov	r0, r4
    595a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

0000595c <boot_read_image_size.isra.0>:
boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
    595c:	b573      	push	{r0, r1, r4, r5, r6, lr}
    595e:	4605      	mov	r5, r0
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
    5960:	2000      	movs	r0, #0
boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
    5962:	460c      	mov	r4, r1
    5964:	4616      	mov	r6, r2
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
    5966:	f7ff ff09 	bl	577c <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
    596a:	4669      	mov	r1, sp
    596c:	b2c0      	uxtb	r0, r0
    596e:	f7fc f9ad 	bl	1ccc <flash_area_open>
    if (rc != 0) {
    5972:	bb30      	cbnz	r0, 59c2 <boot_read_image_size.isra.0+0x66>
    off = BOOT_TLV_OFF(boot_img_hdr(state, slot));
    5974:	212c      	movs	r1, #44	; 0x2c
    5976:	fb01 5404 	mla	r4, r1, r4, r5
    if (flash_area_read(fap, off, &info, sizeof(info))) {
    597a:	9800      	ldr	r0, [sp, #0]
    off = BOOT_TLV_OFF(boot_img_hdr(state, slot));
    597c:	8921      	ldrh	r1, [r4, #8]
    597e:	68e3      	ldr	r3, [r4, #12]
    5980:	18cd      	adds	r5, r1, r3
    if (flash_area_read(fap, off, &info, sizeof(info))) {
    5982:	2304      	movs	r3, #4
    5984:	eb0d 0203 	add.w	r2, sp, r3
    5988:	4629      	mov	r1, r5
    598a:	f000 fa66 	bl	5e5a <flash_area_read>
    598e:	b9c0      	cbnz	r0, 59c2 <boot_read_image_size.isra.0+0x66>
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    5990:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    protect_tlv_size = boot_img_hdr(state, slot)->ih_protect_tlv_size;
    5994:	8964      	ldrh	r4, [r4, #10]
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    5996:	f646 1308 	movw	r3, #26888	; 0x6908
    599a:	429a      	cmp	r2, r3
    599c:	d116      	bne.n	59cc <boot_read_image_size.isra.0+0x70>
        if (protect_tlv_size != info.it_tlv_tot) {
    599e:	f8bd 3006 	ldrh.w	r3, [sp, #6]
    59a2:	429c      	cmp	r4, r3
    59a4:	d10d      	bne.n	59c2 <boot_read_image_size.isra.0+0x66>
        if (flash_area_read(fap, off + info.it_tlv_tot, &info, sizeof(info))) {
    59a6:	2304      	movs	r3, #4
    59a8:	9800      	ldr	r0, [sp, #0]
    59aa:	eb0d 0203 	add.w	r2, sp, r3
    59ae:	1961      	adds	r1, r4, r5
    59b0:	f000 fa53 	bl	5e5a <flash_area_read>
    59b4:	b928      	cbnz	r0, 59c2 <boot_read_image_size.isra.0+0x66>
    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
    59b6:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    59ba:	f646 1307 	movw	r3, #26887	; 0x6907
    59be:	429a      	cmp	r2, r3
    59c0:	d007      	beq.n	59d2 <boot_read_image_size.isra.0+0x76>
    flash_area_close(fap);
    59c2:	9800      	ldr	r0, [sp, #0]
    59c4:	f000 fa48 	bl	5e58 <flash_area_close>
}
    59c8:	b002      	add	sp, #8
    59ca:	bd70      	pop	{r4, r5, r6, pc}
    } else if (protect_tlv_size != 0) {
    59cc:	2c00      	cmp	r4, #0
    59ce:	d0f2      	beq.n	59b6 <boot_read_image_size.isra.0+0x5a>
    59d0:	e7f7      	b.n	59c2 <boot_read_image_size.isra.0+0x66>
    *size = off + protect_tlv_size + info.it_tlv_tot;
    59d2:	f8bd 1006 	ldrh.w	r1, [sp, #6]
    59d6:	4421      	add	r1, r4
    59d8:	4429      	add	r1, r5
    59da:	6031      	str	r1, [r6, #0]
    rc = 0;
    59dc:	e7f1      	b.n	59c2 <boot_read_image_size.isra.0+0x66>

000059de <boot_read_sectors>:
{
    59de:	b537      	push	{r0, r1, r2, r4, r5, lr}
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    59e0:	6a42      	ldr	r2, [r0, #36]	; 0x24
{
    59e2:	4604      	mov	r4, r0
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    59e4:	2580      	movs	r5, #128	; 0x80
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    59e6:	a901      	add	r1, sp, #4
    59e8:	2002      	movs	r0, #2
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    59ea:	9501      	str	r5, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    59ec:	f7fc f98c 	bl	1d08 <flash_area_get_sectors>
    if (rc != 0) {
    59f0:	b958      	cbnz	r0, 5a0a <boot_read_sectors+0x2c>
    *out_num_sectors = num_sectors;
    59f2:	9b01      	ldr	r3, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    59f4:	6d22      	ldr	r2, [r4, #80]	; 0x50
    *out_num_sectors = num_sectors;
    59f6:	62a3      	str	r3, [r4, #40]	; 0x28
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    59f8:	a901      	add	r1, sp, #4
    59fa:	2005      	movs	r0, #5
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    59fc:	9501      	str	r5, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    59fe:	f7fc f983 	bl	1d08 <flash_area_get_sectors>
    if (rc != 0) {
    5a02:	4605      	mov	r5, r0
    5a04:	b128      	cbz	r0, 5a12 <boot_read_sectors+0x34>
        return BOOT_EFLASH_SEC;
    5a06:	2509      	movs	r5, #9
    5a08:	e000      	b.n	5a0c <boot_read_sectors+0x2e>
        return BOOT_EFLASH;
    5a0a:	2501      	movs	r5, #1
}
    5a0c:	4628      	mov	r0, r5
    5a0e:	b003      	add	sp, #12
    5a10:	bd30      	pop	{r4, r5, pc}
    *out_num_sectors = num_sectors;
    5a12:	9b01      	ldr	r3, [sp, #4]
    elem_sz = flash_area_align(BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT));
    5a14:	6a20      	ldr	r0, [r4, #32]
    *out_num_sectors = num_sectors;
    5a16:	6563      	str	r3, [r4, #84]	; 0x54
    elem_sz = flash_area_align(BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT));
    5a18:	f000 fa6e 	bl	5ef8 <flash_area_align>
    BOOT_WRITE_SZ(state) = boot_write_sz(state);
    5a1c:	65e0      	str	r0, [r4, #92]	; 0x5c
    return 0;
    5a1e:	e7f5      	b.n	5a0c <boot_read_sectors+0x2e>

00005a20 <boot_status_reset>:
    bs->idx = BOOT_STATUS_IDX_0;
    5a20:	2301      	movs	r3, #1
    5a22:	6003      	str	r3, [r0, #0]
    bs->state = BOOT_STATUS_STATE_0;
    5a24:	f103 2301 	add.w	r3, r3, #16777472	; 0x1000100
    5a28:	6043      	str	r3, [r0, #4]
    bs->swap_size = 0;
    5a2a:	2300      	movs	r3, #0
    bs->source = 0;
    5a2c:	e9c0 3302 	strd	r3, r3, [r0, #8]
}
    5a30:	4770      	bx	lr

00005a32 <boot_status_is_reset>:
            bs->idx == BOOT_STATUS_IDX_0 &&
    5a32:	7943      	ldrb	r3, [r0, #5]
    5a34:	2b01      	cmp	r3, #1
    5a36:	d107      	bne.n	5a48 <boot_status_is_reset+0x16>
    return (bs->op == BOOT_STATUS_OP_MOVE &&
    5a38:	6803      	ldr	r3, [r0, #0]
    5a3a:	2b01      	cmp	r3, #1
    5a3c:	d104      	bne.n	5a48 <boot_status_is_reset+0x16>
            bs->idx == BOOT_STATUS_IDX_0 &&
    5a3e:	7900      	ldrb	r0, [r0, #4]
    5a40:	1e43      	subs	r3, r0, #1
    5a42:	4258      	negs	r0, r3
    5a44:	4158      	adcs	r0, r3
    5a46:	4770      	bx	lr
    5a48:	2000      	movs	r0, #0
}
    5a4a:	4770      	bx	lr

00005a4c <boot_write_status>:
{
    5a4c:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
    5a4e:	4606      	mov	r6, r0
    5a50:	460d      	mov	r5, r1
    rc = flash_area_open(area_id, &fap);
    5a52:	2002      	movs	r0, #2
    5a54:	a901      	add	r1, sp, #4
    5a56:	f7fc f939 	bl	1ccc <flash_area_open>
    if (rc != 0) {
    5a5a:	bb38      	cbnz	r0, 5aac <boot_write_status+0x60>
    off = boot_status_off(fap) +
    5a5c:	9801      	ldr	r0, [sp, #4]
    5a5e:	f7ff ff43 	bl	58e8 <boot_status_off>
          boot_status_internal_off(bs, BOOT_WRITE_SZ(state));
    5a62:	6df1      	ldr	r1, [r6, #92]	; 0x5c
    off = boot_status_off(fap) +
    5a64:	4604      	mov	r4, r0
          boot_status_internal_off(bs, BOOT_WRITE_SZ(state));
    5a66:	4628      	mov	r0, r5
    5a68:	f000 f8e5 	bl	5c36 <boot_status_internal_off>
    off = boot_status_off(fap) +
    5a6c:	4404      	add	r4, r0
    align = flash_area_align(fap);
    5a6e:	9801      	ldr	r0, [sp, #4]
    5a70:	f000 fa42 	bl	5ef8 <flash_area_align>
    5a74:	4606      	mov	r6, r0
    erased_val = flash_area_erased_val(fap);
    5a76:	9801      	ldr	r0, [sp, #4]
    5a78:	f000 fa47 	bl	5f0a <flash_area_erased_val>
    memset(buf, erased_val, BOOT_MAX_ALIGN);
    5a7c:	2208      	movs	r2, #8
    erased_val = flash_area_erased_val(fap);
    5a7e:	4601      	mov	r1, r0
    memset(buf, erased_val, BOOT_MAX_ALIGN);
    5a80:	eb0d 0002 	add.w	r0, sp, r2
    5a84:	f000 fd3d 	bl	6502 <memset>
    buf[0] = bs->state;
    5a88:	792b      	ldrb	r3, [r5, #4]
    5a8a:	f88d 3008 	strb.w	r3, [sp, #8]
    rc = flash_area_write(fap, off, buf, align);
    5a8e:	4621      	mov	r1, r4
    5a90:	9801      	ldr	r0, [sp, #4]
    5a92:	4633      	mov	r3, r6
    5a94:	aa02      	add	r2, sp, #8
    5a96:	f000 f9fc 	bl	5e92 <flash_area_write>
    if (rc != 0) {
    5a9a:	1e04      	subs	r4, r0, #0
    flash_area_close(fap);
    5a9c:	9801      	ldr	r0, [sp, #4]
    if (rc != 0) {
    5a9e:	bf18      	it	ne
    5aa0:	2401      	movne	r4, #1
    flash_area_close(fap);
    5aa2:	f000 f9d9 	bl	5e58 <flash_area_close>
}
    5aa6:	4620      	mov	r0, r4
    5aa8:	b004      	add	sp, #16
    5aaa:	bd70      	pop	{r4, r5, r6, pc}
        return BOOT_EFLASH;
    5aac:	2401      	movs	r4, #1
    5aae:	e7fa      	b.n	5aa6 <boot_write_status+0x5a>

00005ab0 <boot_erase_region>:
    return flash_area_erase(fap, off, sz);
    5ab0:	f000 ba0b 	b.w	5eca <flash_area_erase>

00005ab4 <swap_erase_trailer_sectors>:

#if defined(MCUBOOT_SWAP_USING_SCRATCH) || defined(MCUBOOT_SWAP_USING_MOVE)
int
swap_erase_trailer_sectors(const struct boot_loader_state *state,
                           const struct flash_area *fap)
{
    5ab4:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    5ab8:	460e      	mov	r6, r1
    int rc;

    BOOT_LOG_DBG("erasing trailer; fa_id=%d", flash_area_get_id(fap));

    image_index = BOOT_CURR_IMG(state);
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    5aba:	2100      	movs	r1, #0
{
    5abc:	4607      	mov	r7, r0
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    5abe:	4608      	mov	r0, r1
    5ac0:	f7ff fe5c 	bl	577c <flash_area_id_from_multi_image_slot>
            BOOT_PRIMARY_SLOT);
    fa_id_secondary = flash_area_id_from_multi_image_slot(image_index,
    5ac4:	2101      	movs	r1, #1
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    5ac6:	4604      	mov	r4, r0
    fa_id_secondary = flash_area_id_from_multi_image_slot(image_index,
    5ac8:	2000      	movs	r0, #0
    5aca:	f7ff fe57 	bl	577c <flash_area_id_from_multi_image_slot>
            BOOT_SECONDARY_SLOT);

    if (flash_area_get_id(fap) == fa_id_primary) {
    5ace:	7833      	ldrb	r3, [r6, #0]
    5ad0:	429c      	cmp	r4, r3
    5ad2:	d021      	beq.n	5b18 <swap_erase_trailer_sectors+0x64>
        slot = BOOT_PRIMARY_SLOT;
    } else if (flash_area_get_id(fap) == fa_id_secondary) {
    5ad4:	4298      	cmp	r0, r3
    5ad6:	d121      	bne.n	5b1c <swap_erase_trailer_sectors+0x68>
        slot = BOOT_SECONDARY_SLOT;
    5ad8:	2501      	movs	r5, #1
    return BOOT_IMG(state, slot).num_sectors;
    5ada:	232c      	movs	r3, #44	; 0x2c
    5adc:	fb03 7505 	mla	r5, r3, r5, r7
        return BOOT_EFLASH;
    }

    /* delete starting from last sector and moving to beginning */
    sector = boot_img_num_sectors(state, slot) - 1;
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    5ae0:	6df8      	ldr	r0, [r7, #92]	; 0x5c
    sector = boot_img_num_sectors(state, slot) - 1;
    5ae2:	6aac      	ldr	r4, [r5, #40]	; 0x28
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    5ae4:	f7ff feee 	bl	58c4 <boot_trailer_sz>
    sector = boot_img_num_sectors(state, slot) - 1;
    5ae8:	3c01      	subs	r4, #1
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    5aea:	4607      	mov	r7, r0
    total_sz = 0;
    5aec:	f04f 0800 	mov.w	r8, #0
    return flash_sector_get_size(&BOOT_IMG(state, slot).sectors[sector]);
    5af0:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    5af2:	eb03 02c4 	add.w	r2, r3, r4, lsl #3
    return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -
    5af6:	f853 1034 	ldr.w	r1, [r3, r4, lsl #3]
	return fs->fs_size;
    5afa:	f8d2 9004 	ldr.w	r9, [r2, #4]
    5afe:	681b      	ldr	r3, [r3, #0]
    do {
        sz = boot_img_sector_size(state, slot, sector);
        off = boot_img_sector_off(state, slot, sector);
        rc = boot_erase_region(fap, off, sz);
    5b00:	464a      	mov	r2, r9
    5b02:	1ac9      	subs	r1, r1, r3
    5b04:	4630      	mov	r0, r6
        assert(rc == 0);

        sector--;
        total_sz += sz;
    5b06:	44c8      	add	r8, r9
        rc = boot_erase_region(fap, off, sz);
    5b08:	f7ff ffd2 	bl	5ab0 <boot_erase_region>
    } while (total_sz < trailer_sz);
    5b0c:	45b8      	cmp	r8, r7
        sector--;
    5b0e:	f104 34ff 	add.w	r4, r4, #4294967295
    } while (total_sz < trailer_sz);
    5b12:	d3ed      	bcc.n	5af0 <swap_erase_trailer_sectors+0x3c>

    return rc;
}
    5b14:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        slot = BOOT_PRIMARY_SLOT;
    5b18:	2500      	movs	r5, #0
    5b1a:	e7de      	b.n	5ada <swap_erase_trailer_sectors+0x26>
        return BOOT_EFLASH;
    5b1c:	2001      	movs	r0, #1
    5b1e:	e7f9      	b.n	5b14 <swap_erase_trailer_sectors+0x60>

00005b20 <swap_status_init>:

int
swap_status_init(const struct boot_loader_state *state,
                 const struct flash_area *fap,
                 const struct boot_status *bs)
{
    5b20:	b537      	push	{r0, r1, r2, r4, r5, lr}
    5b22:	4615      	mov	r5, r2
    5b24:	460c      	mov	r4, r1

    image_index = BOOT_CURR_IMG(state);

    BOOT_LOG_DBG("initializing status; fa_id=%d", flash_area_get_id(fap));

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    5b26:	2005      	movs	r0, #5
    5b28:	4669      	mov	r1, sp
    5b2a:	f001 f960 	bl	6dee <boot_read_swap_state_by_id>
            &swap_state);
    assert(rc == 0);

    if (bs->swap_type != BOOT_SWAP_TYPE_NONE) {
    5b2e:	79e9      	ldrb	r1, [r5, #7]
    5b30:	2901      	cmp	r1, #1
    5b32:	d003      	beq.n	5b3c <swap_status_init+0x1c>
        rc = boot_write_swap_info(fap, bs->swap_type, image_index);
    5b34:	2200      	movs	r2, #0
    5b36:	4620      	mov	r0, r4
    5b38:	f001 f96d 	bl	6e16 <boot_write_swap_info>
        assert(rc == 0);
    }

    if (swap_state.image_ok == BOOT_FLAG_SET) {
    5b3c:	f89d 3003 	ldrb.w	r3, [sp, #3]
    5b40:	2b01      	cmp	r3, #1
    5b42:	d102      	bne.n	5b4a <swap_status_init+0x2a>
        rc = boot_write_image_ok(fap);
    5b44:	4620      	mov	r0, r4
    5b46:	f001 f945 	bl	6dd4 <boot_write_image_ok>
        assert(rc == 0);
    }

    rc = boot_write_swap_size(fap, bs->swap_size);
    5b4a:	68a9      	ldr	r1, [r5, #8]
    5b4c:	4620      	mov	r0, r4
    5b4e:	f7ff fede 	bl	590e <boot_write_swap_size>

    rc = boot_write_enc_key(fap, 1, bs);
    assert(rc == 0);
#endif

    rc = boot_write_magic(fap);
    5b52:	4620      	mov	r0, r4
    5b54:	f7fe f9bc 	bl	3ed0 <boot_write_magic>
    assert(rc == 0);

    return 0;
}
    5b58:	2000      	movs	r0, #0
    5b5a:	b003      	add	sp, #12
    5b5c:	bd30      	pop	{r4, r5, pc}

00005b5e <swap_read_status>:

int
swap_read_status(struct boot_loader_state *state, struct boot_status *bs)
{
    5b5e:	b573      	push	{r0, r1, r4, r5, r6, lr}
    5b60:	460d      	mov	r5, r1
    5b62:	4606      	mov	r6, r0
    uint32_t off;
    uint8_t swap_info;
    int area_id;
    int rc;

    bs->source = swap_status_source(state);
    5b64:	f7fb fa6a 	bl	103c <swap_status_source>
    5b68:	4604      	mov	r4, r0
    5b6a:	60e8      	str	r0, [r5, #12]
    switch (bs->source) {
    5b6c:	b350      	cbz	r0, 5bc4 <swap_read_status+0x66>
    5b6e:	2802      	cmp	r0, #2
    5b70:	d12d      	bne.n	5bce <swap_read_status+0x70>
    default:
        assert(0);
        return BOOT_EBADARGS;
    }

    rc = flash_area_open(area_id, &fap);
    5b72:	a901      	add	r1, sp, #4
    5b74:	f7fc f8aa 	bl	1ccc <flash_area_open>
    if (rc != 0) {
    5b78:	bb58      	cbnz	r0, 5bd2 <swap_read_status+0x74>
        return BOOT_EFLASH;
    }

    rc = swap_read_status_bytes(fap, state, bs);
    5b7a:	9801      	ldr	r0, [sp, #4]
    5b7c:	462a      	mov	r2, r5
    5b7e:	4631      	mov	r1, r6
    5b80:	f7fb f9c2 	bl	f08 <swap_read_status_bytes>
    if (rc == 0) {
    5b84:	4604      	mov	r4, r0
    5b86:	b9d0      	cbnz	r0, 5bbe <swap_read_status+0x60>
        off = boot_swap_info_off(fap);
    5b88:	9801      	ldr	r0, [sp, #4]
    5b8a:	f001 f8b6 	bl	6cfa <boot_swap_info_off>
        rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    5b8e:	2301      	movs	r3, #1
        off = boot_swap_info_off(fap);
    5b90:	4601      	mov	r1, r0
        rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    5b92:	f10d 0203 	add.w	r2, sp, #3
    5b96:	9801      	ldr	r0, [sp, #4]
    5b98:	f000 f95f 	bl	5e5a <flash_area_read>
        if (rc != 0) {
    5b9c:	4604      	mov	r4, r0
    5b9e:	b9a0      	cbnz	r0, 5bca <swap_read_status+0x6c>
            rc = BOOT_EFLASH;
            goto done;
        }

        if (bootutil_buffer_is_erased(fap, &swap_info, sizeof swap_info)) {
    5ba0:	9801      	ldr	r0, [sp, #4]
    5ba2:	2201      	movs	r2, #1
    5ba4:	f10d 0103 	add.w	r1, sp, #3
    5ba8:	f001 f8bb 	bl	6d22 <bootutil_buffer_is_erased>
    5bac:	b110      	cbz	r0, 5bb4 <swap_read_status+0x56>
            BOOT_SET_SWAP_INFO(swap_info, 0, BOOT_SWAP_TYPE_NONE);
    5bae:	2301      	movs	r3, #1
    5bb0:	f88d 3003 	strb.w	r3, [sp, #3]
            rc = 0;
        }

        /* Extract the swap type info */
        bs->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    5bb4:	f89d 3003 	ldrb.w	r3, [sp, #3]
    5bb8:	f003 030f 	and.w	r3, r3, #15
    5bbc:	71eb      	strb	r3, [r5, #7]
    }

done:
    flash_area_close(fap);
    5bbe:	9801      	ldr	r0, [sp, #4]
    5bc0:	f000 f94a 	bl	5e58 <flash_area_close>

    return rc;
}
    5bc4:	4620      	mov	r0, r4
    5bc6:	b002      	add	sp, #8
    5bc8:	bd70      	pop	{r4, r5, r6, pc}
            rc = BOOT_EFLASH;
    5bca:	2401      	movs	r4, #1
    5bcc:	e7f7      	b.n	5bbe <swap_read_status+0x60>
    switch (bs->source) {
    5bce:	2407      	movs	r4, #7
    5bd0:	e7f8      	b.n	5bc4 <swap_read_status+0x66>
        return BOOT_EFLASH;
    5bd2:	2401      	movs	r4, #1
    5bd4:	e7f6      	b.n	5bc4 <swap_read_status+0x66>

00005bd6 <swap_set_copy_done>:

int
swap_set_copy_done(uint8_t image_index)
{
    5bd6:	b513      	push	{r0, r1, r4, lr}
    const struct flash_area *fap;
    int rc;

    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
    5bd8:	2002      	movs	r0, #2
    5bda:	a901      	add	r1, sp, #4
    5bdc:	f7fc f876 	bl	1ccc <flash_area_open>
            &fap);
    if (rc != 0) {
    5be0:	b948      	cbnz	r0, 5bf6 <swap_set_copy_done+0x20>
        return BOOT_EFLASH;
    }

    rc = boot_write_copy_done(fap);
    5be2:	9801      	ldr	r0, [sp, #4]
    5be4:	f7ff fe8b 	bl	58fe <boot_write_copy_done>
    5be8:	4604      	mov	r4, r0
    flash_area_close(fap);
    5bea:	9801      	ldr	r0, [sp, #4]
    5bec:	f000 f934 	bl	5e58 <flash_area_close>
    return rc;
}
    5bf0:	4620      	mov	r0, r4
    5bf2:	b002      	add	sp, #8
    5bf4:	bd10      	pop	{r4, pc}
        return BOOT_EFLASH;
    5bf6:	2401      	movs	r4, #1
    5bf8:	e7fa      	b.n	5bf0 <swap_set_copy_done+0x1a>

00005bfa <swap_set_image_ok>:

int
swap_set_image_ok(uint8_t image_index)
{
    5bfa:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    const struct flash_area *fap;
    struct boot_swap_state state;
    int rc;

    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
    5bfc:	2002      	movs	r0, #2
    5bfe:	a901      	add	r1, sp, #4
    5c00:	f7fc f864 	bl	1ccc <flash_area_open>
            &fap);
    if (rc != 0) {
    5c04:	b9a8      	cbnz	r0, 5c32 <swap_set_image_ok+0x38>
        return BOOT_EFLASH;
    }

    rc = boot_read_swap_state(fap, &state);
    5c06:	9801      	ldr	r0, [sp, #4]
    5c08:	a902      	add	r1, sp, #8
    5c0a:	f7fe f981 	bl	3f10 <boot_read_swap_state>
    if (rc != 0) {
    5c0e:	4604      	mov	r4, r0
    5c10:	b968      	cbnz	r0, 5c2e <swap_set_image_ok+0x34>
        rc = BOOT_EFLASH;
        goto out;
    }

    if (state.image_ok == BOOT_FLAG_UNSET) {
    5c12:	f89d 300b 	ldrb.w	r3, [sp, #11]
    5c16:	2b03      	cmp	r3, #3
    5c18:	d103      	bne.n	5c22 <swap_set_image_ok+0x28>
        rc = boot_write_image_ok(fap);
    5c1a:	9801      	ldr	r0, [sp, #4]
    5c1c:	f001 f8da 	bl	6dd4 <boot_write_image_ok>
    5c20:	4604      	mov	r4, r0
    }

out:
    flash_area_close(fap);
    5c22:	9801      	ldr	r0, [sp, #4]
    5c24:	f000 f918 	bl	5e58 <flash_area_close>
    return rc;
}
    5c28:	4620      	mov	r0, r4
    5c2a:	b004      	add	sp, #16
    5c2c:	bd10      	pop	{r4, pc}
        rc = BOOT_EFLASH;
    5c2e:	2401      	movs	r4, #1
    5c30:	e7f7      	b.n	5c22 <swap_set_image_ok+0x28>
        return BOOT_EFLASH;
    5c32:	2401      	movs	r4, #1
    5c34:	e7f8      	b.n	5c28 <swap_set_image_ok+0x2e>

00005c36 <boot_status_internal_off>:
{
    5c36:	b530      	push	{r4, r5, lr}
    idx_sz = elem_sz * ((bs->op == BOOT_STATUS_OP_MOVE) ?
    5c38:	7943      	ldrb	r3, [r0, #5]
           (bs->state - BOOT_STATUS_STATE_0) * elem_sz;
    5c3a:	7902      	ldrb	r2, [r0, #4]
            BOOT_STATUS_MOVE_STATE_COUNT : BOOT_STATUS_SWAP_STATE_COUNT);
    5c3c:	2b01      	cmp	r3, #1
    5c3e:	bf0c      	ite	eq
    5c40:	2301      	moveq	r3, #1
    5c42:	2302      	movne	r3, #2
    idx_sz = elem_sz * ((bs->op == BOOT_STATUS_OP_MOVE) ?
    5c44:	fb01 f403 	mul.w	r4, r1, r3
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    5c48:	6803      	ldr	r3, [r0, #0]
    5c4a:	f103 33ff 	add.w	r3, r3, #4294967295
           (bs->state - BOOT_STATUS_STATE_0) * elem_sz;
    5c4e:	f102 32ff 	add.w	r2, r2, #4294967295
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    5c52:	fb04 f303 	mul.w	r3, r4, r3
               0 : (BOOT_MAX_IMG_SECTORS * BOOT_STATUS_MOVE_STATE_COUNT * elem_sz)) +
    5c56:	bf14      	ite	ne
    5c58:	01cd      	lslne	r5, r1, #7
    5c5a:	2500      	moveq	r5, #0
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    5c5c:	fb01 3102 	mla	r1, r1, r2, r3
}
    5c60:	1948      	adds	r0, r1, r5
    5c62:	bd30      	pop	{r4, r5, pc}

00005c64 <crc16_itu_t>:
	return seed;
}

uint16_t crc16_itu_t(uint16_t seed, const uint8_t *src, size_t len)
{
	for (; len > 0; len--) {
    5c64:	440a      	add	r2, r1
    5c66:	428a      	cmp	r2, r1
    5c68:	d100      	bne.n	5c6c <crc16_itu_t+0x8>
		seed ^= seed << 12U;
		seed ^= (seed & 0xffU) << 5U;
	}

	return seed;
}
    5c6a:	4770      	bx	lr
		seed ^= *src++;
    5c6c:	f811 3b01 	ldrb.w	r3, [r1], #1
    5c70:	ba40      	rev16	r0, r0
    5c72:	b280      	uxth	r0, r0
    5c74:	4058      	eors	r0, r3
		seed ^= (seed & 0xffU) >> 4U;
    5c76:	f3c0 1303 	ubfx	r3, r0, #4, #4
    5c7a:	4058      	eors	r0, r3
		seed ^= seed << 12U;
    5c7c:	ea80 3000 	eor.w	r0, r0, r0, lsl #12
    5c80:	b283      	uxth	r3, r0
		seed ^= (seed & 0xffU) << 5U;
    5c82:	0158      	lsls	r0, r3, #5
    5c84:	f400 50ff 	and.w	r0, r0, #8160	; 0x1fe0
    5c88:	4058      	eors	r0, r3
	for (; len > 0; len--) {
    5c8a:	e7ec      	b.n	5c66 <crc16_itu_t+0x2>

00005c8c <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    5c8c:	4603      	mov	r3, r0
    5c8e:	b158      	cbz	r0, 5ca8 <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    5c90:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    5c92:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    5c96:	2a01      	cmp	r2, #1
    5c98:	d003      	beq.n	5ca2 <sys_notify_validate+0x16>
    5c9a:	2a03      	cmp	r2, #3
    5c9c:	d104      	bne.n	5ca8 <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    5c9e:	6802      	ldr	r2, [r0, #0]
    5ca0:	b112      	cbz	r2, 5ca8 <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    5ca2:	2000      	movs	r0, #0
    5ca4:	6098      	str	r0, [r3, #8]
    5ca6:	4770      	bx	lr
		return -EINVAL;
    5ca8:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    5cac:	4770      	bx	lr

00005cae <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    5cae:	6842      	ldr	r2, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    5cb0:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    5cb2:	f002 0203 	and.w	r2, r2, #3
	switch (method) {
    5cb6:	2a03      	cmp	r2, #3
    5cb8:	f04f 0200 	mov.w	r2, #0
{
    5cbc:	4603      	mov	r3, r0
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    5cbe:	bf0c      	ite	eq
    5cc0:	6800      	ldreq	r0, [r0, #0]
	sys_notify_generic_callback rv = NULL;
    5cc2:	4610      	movne	r0, r2
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    5cc4:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    5cc6:	4770      	bx	lr

00005cc8 <arch_printk_char_out>:
}
    5cc8:	2000      	movs	r0, #0
    5cca:	4770      	bx	lr

00005ccc <printk>:
 *
 * @param fmt formatted string to output
 */

void printk(const char *fmt, ...)
{
    5ccc:	b40f      	push	{r0, r1, r2, r3}
    5cce:	b507      	push	{r0, r1, r2, lr}
    5cd0:	a904      	add	r1, sp, #16
    5cd2:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    5cd6:	9101      	str	r1, [sp, #4]

	vprintk(fmt, ap);
    5cd8:	f7fb fcc8 	bl	166c <vprintk>

	va_end(ap);
}
    5cdc:	b003      	add	sp, #12
    5cde:	f85d eb04 	ldr.w	lr, [sp], #4
    5ce2:	b004      	add	sp, #16
    5ce4:	4770      	bx	lr

00005ce6 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5ce6:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    5ce8:	f013 0307 	ands.w	r3, r3, #7
    5cec:	d105      	bne.n	5cfa <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    5cee:	6803      	ldr	r3, [r0, #0]
		evt = EVT_START;
    5cf0:	2b00      	cmp	r3, #0
    5cf2:	bf0c      	ite	eq
    5cf4:	2000      	moveq	r0, #0
    5cf6:	2003      	movne	r0, #3
    5cf8:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    5cfa:	2b02      	cmp	r3, #2
    5cfc:	d105      	bne.n	5d0a <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    5cfe:	8b43      	ldrh	r3, [r0, #26]
		evt = EVT_STOP;
    5d00:	2b00      	cmp	r3, #0
    5d02:	bf14      	ite	ne
    5d04:	2000      	movne	r0, #0
    5d06:	2004      	moveq	r0, #4
    5d08:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    5d0a:	2b01      	cmp	r3, #1
    5d0c:	d105      	bne.n	5d1a <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    5d0e:	6803      	ldr	r3, [r0, #0]
		evt = EVT_RESET;
    5d10:	2b00      	cmp	r3, #0
    5d12:	bf0c      	ite	eq
    5d14:	2000      	moveq	r0, #0
    5d16:	2005      	movne	r0, #5
    5d18:	4770      	bx	lr
	int evt = EVT_NOP;
    5d1a:	2000      	movs	r0, #0
}
    5d1c:	4770      	bx	lr

00005d1e <notify_one>:
{
    5d1e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5d22:	460d      	mov	r5, r1
    5d24:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5d26:	4619      	mov	r1, r3
    5d28:	1d28      	adds	r0, r5, #4
{
    5d2a:	4690      	mov	r8, r2
    5d2c:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5d2e:	f7ff ffbe 	bl	5cae <sys_notify_finalize>
	if (cb) {
    5d32:	4604      	mov	r4, r0
    5d34:	b138      	cbz	r0, 5d46 <notify_one+0x28>
		cb(mgr, cli, state, res);
    5d36:	4633      	mov	r3, r6
    5d38:	4642      	mov	r2, r8
    5d3a:	4629      	mov	r1, r5
    5d3c:	4638      	mov	r0, r7
    5d3e:	46a4      	mov	ip, r4
}
    5d40:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    5d44:	4760      	bx	ip
}
    5d46:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005d4a <transition_complete>:
{
    5d4a:	b410      	push	{r4}
    5d4c:	f04f 0420 	mov.w	r4, #32
    5d50:	f3ef 8211 	mrs	r2, BASEPRI
    5d54:	f384 8812 	msr	BASEPRI_MAX, r4
    5d58:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    5d5c:	6141      	str	r1, [r0, #20]
}
    5d5e:	bc10      	pop	{r4}
	process_event(mgr, EVT_COMPLETE, key);
    5d60:	2101      	movs	r1, #1
    5d62:	f7fb bc91 	b.w	1688 <process_event>

00005d66 <validate_args>:
{
    5d66:	b510      	push	{r4, lr}
    5d68:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    5d6a:	b140      	cbz	r0, 5d7e <validate_args+0x18>
    5d6c:	b139      	cbz	r1, 5d7e <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
    5d6e:	1d08      	adds	r0, r1, #4
    5d70:	f7ff ff8c 	bl	5c8c <sys_notify_validate>
	if ((rv == 0)
    5d74:	b928      	cbnz	r0, 5d82 <validate_args+0x1c>
	    && ((cli->notify.flags
    5d76:	68a3      	ldr	r3, [r4, #8]
    5d78:	f033 0303 	bics.w	r3, r3, #3
    5d7c:	d001      	beq.n	5d82 <validate_args+0x1c>
		rv = -EINVAL;
    5d7e:	f06f 0015 	mvn.w	r0, #21
}
    5d82:	bd10      	pop	{r4, pc}

00005d84 <onoff_manager_init>:
{
    5d84:	b538      	push	{r3, r4, r5, lr}
    5d86:	460c      	mov	r4, r1
	if ((mgr == NULL)
    5d88:	4605      	mov	r5, r0
    5d8a:	b158      	cbz	r0, 5da4 <onoff_manager_init+0x20>
	    || (transitions == NULL)
    5d8c:	b151      	cbz	r1, 5da4 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    5d8e:	680b      	ldr	r3, [r1, #0]
    5d90:	b143      	cbz	r3, 5da4 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    5d92:	684b      	ldr	r3, [r1, #4]
    5d94:	b133      	cbz	r3, 5da4 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    5d96:	221c      	movs	r2, #28
    5d98:	2100      	movs	r1, #0
    5d9a:	f000 fbb2 	bl	6502 <memset>
    5d9e:	612c      	str	r4, [r5, #16]
	return 0;
    5da0:	2000      	movs	r0, #0
}
    5da2:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    5da4:	f06f 0015 	mvn.w	r0, #21
    5da8:	e7fb      	b.n	5da2 <onoff_manager_init+0x1e>

00005daa <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    5daa:	b570      	push	{r4, r5, r6, lr}
    5dac:	4604      	mov	r4, r0
    5dae:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    5db0:	f7ff ffd9 	bl	5d66 <validate_args>

	if (rv < 0) {
    5db4:	1e05      	subs	r5, r0, #0
    5db6:	db31      	blt.n	5e1c <onoff_request+0x72>
    5db8:	f04f 0320 	mov.w	r3, #32
    5dbc:	f3ef 8111 	mrs	r1, BASEPRI
    5dc0:	f383 8812 	msr	BASEPRI_MAX, r3
    5dc4:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    5dc8:	8b63      	ldrh	r3, [r4, #26]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5dca:	8b20      	ldrh	r0, [r4, #24]
	if (mgr->refs == SERVICE_REFS_MAX) {
    5dcc:	f64f 75ff 	movw	r5, #65535	; 0xffff
    5dd0:	42ab      	cmp	r3, r5
    5dd2:	f000 0207 	and.w	r2, r0, #7
    5dd6:	d02e      	beq.n	5e36 <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
    5dd8:	2a02      	cmp	r2, #2
    5dda:	d10e      	bne.n	5dfa <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
    5ddc:	3301      	adds	r3, #1
    5dde:	8363      	strh	r3, [r4, #26]
	rv = state;
    5de0:	4615      	mov	r5, r2
		notify = true;
    5de2:	2301      	movs	r3, #1
	__asm__ volatile(
    5de4:	f381 8811 	msr	BASEPRI, r1
    5de8:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    5dec:	b1b3      	cbz	r3, 5e1c <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
    5dee:	2300      	movs	r3, #0
    5df0:	4631      	mov	r1, r6
    5df2:	4620      	mov	r0, r4
    5df4:	f7ff ff93 	bl	5d1e <notify_one>
    5df8:	e010      	b.n	5e1c <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
    5dfa:	0783      	lsls	r3, r0, #30
    5dfc:	d001      	beq.n	5e02 <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
    5dfe:	2a06      	cmp	r2, #6
    5e00:	d10e      	bne.n	5e20 <onoff_request+0x76>
	parent->next = child;
    5e02:	2300      	movs	r3, #0
    5e04:	6033      	str	r3, [r6, #0]
	return list->tail;
    5e06:	6863      	ldr	r3, [r4, #4]
Z_GENLIST_APPEND(slist, snode)
    5e08:	b993      	cbnz	r3, 5e30 <onoff_request+0x86>
	list->head = node;
    5e0a:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
    5e0e:	4615      	mov	r5, r2
    5e10:	b962      	cbnz	r2, 5e2c <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
    5e12:	460a      	mov	r2, r1
    5e14:	4620      	mov	r0, r4
    5e16:	2102      	movs	r1, #2
    5e18:	f7fb fc36 	bl	1688 <process_event>
		}
	}

	return rv;
}
    5e1c:	4628      	mov	r0, r5
    5e1e:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
    5e20:	2a05      	cmp	r2, #5
    5e22:	bf0c      	ite	eq
    5e24:	f06f 0585 	mvneq.w	r5, #133	; 0x85
    5e28:	f06f 0504 	mvnne.w	r5, #4
    5e2c:	2300      	movs	r3, #0
    5e2e:	e7d9      	b.n	5de4 <onoff_request+0x3a>
	parent->next = child;
    5e30:	601e      	str	r6, [r3, #0]
	list->tail = node;
    5e32:	6066      	str	r6, [r4, #4]
}
    5e34:	e7eb      	b.n	5e0e <onoff_request+0x64>
		rv = -EAGAIN;
    5e36:	f06f 050a 	mvn.w	r5, #10
    5e3a:	e7f7      	b.n	5e2c <onoff_request+0x82>

00005e3c <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_META, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_LEGACY_INCLUDE_PATH, 1);

GEN_ABS_SYM_END
    5e3c:	4770      	bx	lr

00005e3e <z_log_minimal_printk>:
#include <sys/printk.h>

#define HEXDUMP_BYTES_IN_LINE 8U

void z_log_minimal_printk(const char *fmt, ...)
{
    5e3e:	b40f      	push	{r0, r1, r2, r3}
    5e40:	b507      	push	{r0, r1, r2, lr}
    5e42:	a904      	add	r1, sp, #16
    5e44:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    5e48:	9101      	str	r1, [sp, #4]
	vprintk(fmt, ap);
    5e4a:	f7fb fc0f 	bl	166c <vprintk>
	va_end(ap);
}
    5e4e:	b003      	add	sp, #12
    5e50:	f85d eb04 	ldr.w	lr, [sp], #4
    5e54:	b004      	add	sp, #16
    5e56:	4770      	bx	lr

00005e58 <flash_area_close>:

void flash_area_close(const struct flash_area *fa)
{
	/* nothing to do for now */
}
    5e58:	4770      	bx	lr

00005e5a <flash_area_read>:

int flash_area_read(const struct flash_area *fa, off_t off, void *dst,
		    size_t len)
{
    5e5a:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}


static inline bool is_in_flash_area_bounds(const struct flash_area *fa,
					   off_t off, size_t len)
{
	return (off >= 0) && ((off + len) <= fa->fa_size);
    5e5e:	1e0c      	subs	r4, r1, #0
    5e60:	4605      	mov	r5, r0
    5e62:	4617      	mov	r7, r2
    5e64:	461e      	mov	r6, r3
    5e66:	db10      	blt.n	5e8a <flash_area_read+0x30>
    5e68:	6882      	ldr	r2, [r0, #8]
    5e6a:	18e3      	adds	r3, r4, r3
    5e6c:	4293      	cmp	r3, r2
    5e6e:	d80c      	bhi.n	5e8a <flash_area_read+0x30>

	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	dev = device_get_binding(fa->fa_dev_name);
    5e70:	68c0      	ldr	r0, [r0, #12]
    5e72:	f7ff fafd 	bl	5470 <z_impl_device_get_binding>

	return flash_read(dev, fa->fa_off + off, dst, len);
    5e76:	6869      	ldr	r1, [r5, #4]
    5e78:	4421      	add	r1, r4
				    size_t len)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->read(dev, offset, data, len);
    5e7a:	6883      	ldr	r3, [r0, #8]
    5e7c:	681c      	ldr	r4, [r3, #0]
    5e7e:	463a      	mov	r2, r7
    5e80:	4633      	mov	r3, r6
    5e82:	46a4      	mov	ip, r4
}
    5e84:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    5e88:	4760      	bx	ip
    5e8a:	f06f 0015 	mvn.w	r0, #21
    5e8e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005e92 <flash_area_write>:

int flash_area_write(const struct flash_area *fa, off_t off, const void *src,
		     size_t len)
{
    5e92:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5e96:	1e0c      	subs	r4, r1, #0
    5e98:	4605      	mov	r5, r0
    5e9a:	4617      	mov	r7, r2
    5e9c:	461e      	mov	r6, r3
    5e9e:	db10      	blt.n	5ec2 <flash_area_write+0x30>
    5ea0:	6882      	ldr	r2, [r0, #8]
    5ea2:	18e3      	adds	r3, r4, r3
    5ea4:	4293      	cmp	r3, r2
    5ea6:	d80c      	bhi.n	5ec2 <flash_area_write+0x30>

	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	flash_dev = device_get_binding(fa->fa_dev_name);
    5ea8:	68c0      	ldr	r0, [r0, #12]
    5eaa:	f7ff fae1 	bl	5470 <z_impl_device_get_binding>

	rc = flash_write(flash_dev, fa->fa_off + off, (void *)src, len);
    5eae:	6869      	ldr	r1, [r5, #4]
    5eb0:	4421      	add	r1, r4
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;
	int rc;

	rc = api->write(dev, offset, data, len);
    5eb2:	6883      	ldr	r3, [r0, #8]
    5eb4:	685c      	ldr	r4, [r3, #4]
    5eb6:	463a      	mov	r2, r7
    5eb8:	4633      	mov	r3, r6
    5eba:	46a4      	mov	ip, r4

	return rc;
}
    5ebc:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    5ec0:	4760      	bx	ip
    5ec2:	f06f 0015 	mvn.w	r0, #21
    5ec6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005eca <flash_area_erase>:

int flash_area_erase(const struct flash_area *fa, off_t off, size_t len)
{
    5eca:	b570      	push	{r4, r5, r6, lr}
    5ecc:	1e0c      	subs	r4, r1, #0
    5ece:	4605      	mov	r5, r0
    5ed0:	4616      	mov	r6, r2
    5ed2:	db0e      	blt.n	5ef2 <flash_area_erase+0x28>
    5ed4:	18a3      	adds	r3, r4, r2
    5ed6:	6882      	ldr	r2, [r0, #8]
    5ed8:	4293      	cmp	r3, r2
    5eda:	d80a      	bhi.n	5ef2 <flash_area_erase+0x28>

	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	flash_dev = device_get_binding(fa->fa_dev_name);
    5edc:	68c0      	ldr	r0, [r0, #12]
    5ede:	f7ff fac7 	bl	5470 <z_impl_device_get_binding>

	rc = flash_erase(flash_dev, fa->fa_off + off, len);
    5ee2:	6869      	ldr	r1, [r5, #4]
    5ee4:	4421      	add	r1, r4
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;
	int rc;

	rc = api->erase(dev, offset, size);
    5ee6:	6883      	ldr	r3, [r0, #8]
    5ee8:	4632      	mov	r2, r6
    5eea:	689b      	ldr	r3, [r3, #8]

	return rc;
}
    5eec:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    5ef0:	4718      	bx	r3
    5ef2:	f06f 0015 	mvn.w	r0, #21
    5ef6:	bd70      	pop	{r4, r5, r6, pc}

00005ef8 <flash_area_align>:

uint32_t flash_area_align(const struct flash_area *fa)
{
    5ef8:	b508      	push	{r3, lr}
	const struct device *dev;

	dev = device_get_binding(fa->fa_dev_name);
    5efa:	68c0      	ldr	r0, [r0, #12]
    5efc:	f7ff fab8 	bl	5470 <z_impl_device_get_binding>
static inline size_t z_impl_flash_get_write_block_size(const struct device *dev)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->get_parameters(dev)->write_block_size;
    5f00:	6883      	ldr	r3, [r0, #8]
    5f02:	68db      	ldr	r3, [r3, #12]
    5f04:	4798      	blx	r3

	return flash_get_write_block_size(dev);
}
    5f06:	6800      	ldr	r0, [r0, #0]
    5f08:	bd08      	pop	{r3, pc}

00005f0a <flash_area_erased_val>:
{
	return device_get_binding(fa->fa_dev_name);
}

uint8_t flash_area_erased_val(const struct flash_area *fa)
{
    5f0a:	b508      	push	{r3, lr}
	const struct flash_parameters *param;

	param = flash_get_parameters(device_get_binding(fa->fa_dev_name));
    5f0c:	68c0      	ldr	r0, [r0, #12]
    5f0e:	f7ff faaf 	bl	5470 <z_impl_device_get_binding>
static inline const struct flash_parameters *z_impl_flash_get_parameters(const struct device *dev)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->get_parameters(dev);
    5f12:	6883      	ldr	r3, [r0, #8]
    5f14:	68db      	ldr	r3, [r3, #12]
    5f16:	4798      	blx	r3

	return param->erase_value;
}
    5f18:	7900      	ldrb	r0, [r0, #4]
    5f1a:	bd08      	pop	{r3, pc}

00005f1c <get_sectors_cb>:
{
    5f1c:	b570      	push	{r4, r5, r6, lr}
	if (info->start_offset < data->area_off) {
    5f1e:	6802      	ldr	r2, [r0, #0]
    5f20:	684c      	ldr	r4, [r1, #4]
    5f22:	42a2      	cmp	r2, r4
    5f24:	d316      	bcc.n	5f54 <get_sectors_cb+0x38>
	} else if (info->start_offset >= data->area_off + data->area_len) {
    5f26:	688b      	ldr	r3, [r1, #8]
    5f28:	4423      	add	r3, r4
    5f2a:	429a      	cmp	r2, r3
    5f2c:	d206      	bcs.n	5f3c <get_sectors_cb+0x20>
	} else if (data->ret_idx >= data->ret_len) {
    5f2e:	e9d1 3504 	ldrd	r3, r5, [r1, #16]
    5f32:	42ab      	cmp	r3, r5
    5f34:	d304      	bcc.n	5f40 <get_sectors_cb+0x24>
		data->status = -ENOMEM;
    5f36:	f06f 030b 	mvn.w	r3, #11
    5f3a:	618b      	str	r3, [r1, #24]
		*bail_value = false;
    5f3c:	2000      	movs	r0, #0
    5f3e:	e00a      	b.n	5f56 <get_sectors_cb+0x3a>
	ret[data->ret_idx].fs_off = info->start_offset - data->area_off;
    5f40:	68cd      	ldr	r5, [r1, #12]
    5f42:	1b12      	subs	r2, r2, r4
    5f44:	eb05 06c3 	add.w	r6, r5, r3, lsl #3
    5f48:	f845 2033 	str.w	r2, [r5, r3, lsl #3]
	ret[data->ret_idx].fs_size = info->size;
    5f4c:	6842      	ldr	r2, [r0, #4]
    5f4e:	6072      	str	r2, [r6, #4]
	data->ret_idx++;
    5f50:	3301      	adds	r3, #1
    5f52:	610b      	str	r3, [r1, #16]
		*bail_value = true;
    5f54:	2001      	movs	r0, #1
}
    5f56:	bd70      	pop	{r4, r5, r6, pc}

00005f58 <console_write>:
{
    5f58:	b570      	push	{r4, r5, r6, lr}
    5f5a:	4606      	mov	r6, r0
    5f5c:	460d      	mov	r5, r1
	for (i = 0; i < cnt; i++) {
    5f5e:	2400      	movs	r4, #0
    5f60:	42ac      	cmp	r4, r5
    5f62:	db00      	blt.n	5f66 <console_write+0xe>
}
    5f64:	bd70      	pop	{r4, r5, r6, pc}
		if (console_out((int)str[i]) == EOF) {
    5f66:	5d30      	ldrb	r0, [r6, r4]
    5f68:	f7fb ff58 	bl	1e1c <console_out>
    5f6c:	3001      	adds	r0, #1
    5f6e:	d0f9      	beq.n	5f64 <console_write+0xc>
	for (i = 0; i < cnt; i++) {
    5f70:	3401      	adds	r4, #1
    5f72:	e7f5      	b.n	5f60 <console_write+0x8>

00005f74 <u32toa>:
{
    5f74:	b5f0      	push	{r4, r5, r6, r7, lr}
    uint32_t d = 1;
    5f76:	2301      	movs	r3, #1
        d *= 10;
    5f78:	240a      	movs	r4, #10
    while (val / d >= 10) {
    5f7a:	fbb1 f2f3 	udiv	r2, r1, r3
    5f7e:	2a09      	cmp	r2, #9
    5f80:	d806      	bhi.n	5f90 <u32toa+0x1c>
    dst = tgt;
    5f82:	4602      	mov	r2, r0
    int n = 0;
    5f84:	2500      	movs	r5, #0
        d /= 10;
    5f86:	260a      	movs	r6, #10
    while (d) {
    5f88:	b923      	cbnz	r3, 5f94 <u32toa+0x20>
    *dst = '\0';
    5f8a:	7013      	strb	r3, [r2, #0]
}
    5f8c:	1a10      	subs	r0, r2, r0
    5f8e:	bdf0      	pop	{r4, r5, r6, r7, pc}
        d *= 10;
    5f90:	4363      	muls	r3, r4
    5f92:	e7f2      	b.n	5f7a <u32toa+0x6>
        dgt = val / d;
    5f94:	fbb1 f4f3 	udiv	r4, r1, r3
        d /= 10;
    5f98:	fbb3 fcf6 	udiv	ip, r3, r6
        val %= d;
    5f9c:	fb03 1714 	mls	r7, r3, r4, r1
        if (n || dgt > 0 || d == 0) {
    5fa0:	b91d      	cbnz	r5, 5faa <u32toa+0x36>
    5fa2:	4299      	cmp	r1, r3
    5fa4:	d201      	bcs.n	5faa <u32toa+0x36>
    5fa6:	2b09      	cmp	r3, #9
    5fa8:	d803      	bhi.n	5fb2 <u32toa+0x3e>
            *dst++ = dgt + '0';
    5faa:	3430      	adds	r4, #48	; 0x30
    5fac:	f802 4b01 	strb.w	r4, [r2], #1
            ++n;
    5fb0:	3501      	adds	r5, #1
            *dst++ = dgt + '0';
    5fb2:	4663      	mov	r3, ip
    5fb4:	4639      	mov	r1, r7
    5fb6:	e7e7      	b.n	5f88 <u32toa+0x14>

00005fb8 <value_extract>:
 *          CBOR values are always big-endian, so this function converts from
 *          big to little-endian if necessary (@ref CONFIG_BIG_ENDIAN).
 */
static bool value_extract(cbor_state_t *state,
		void *const result, uint32_t result_len)
{
    5fb8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    5fba:	4604      	mov	r4, r0
	cbor_trace();
	cbor_assert(result_len != 0, "0-length result not supported.\n");
	cbor_assert(result != NULL, NULL);

	FAIL_IF((state->elem_count == 0) \
    5fbc:	6880      	ldr	r0, [r0, #8]
{
    5fbe:	460d      	mov	r5, r1
    5fc0:	4617      	mov	r7, r2
	FAIL_IF((state->elem_count == 0) \
    5fc2:	b1a0      	cbz	r0, 5fee <value_extract+0x36>
    5fc4:	6823      	ldr	r3, [r4, #0]
    5fc6:	68e1      	ldr	r1, [r4, #12]
    5fc8:	428b      	cmp	r3, r1
    5fca:	d21d      	bcs.n	6008 <value_extract+0x50>
		|| (state->payload >= state->payload_end));

	uint8_t *u8_result  = (uint8_t *)result;
	uint8_t additional = ADDITIONAL(*state->payload);
    5fcc:	781e      	ldrb	r6, [r3, #0]

	state->payload_bak = state->payload;
    5fce:	6063      	str	r3, [r4, #4]
	(state->payload)++;
    5fd0:	3301      	adds	r3, #1
	uint8_t additional = ADDITIONAL(*state->payload);
    5fd2:	f006 061f 	and.w	r6, r6, #31
	(state->payload)++;
    5fd6:	6023      	str	r3, [r4, #0]

	memset(result, 0, result_len);
    5fd8:	2100      	movs	r1, #0
    5fda:	4628      	mov	r0, r5
    5fdc:	f000 fa91 	bl	6502 <memset>
	if (additional <= VALUE_IN_HEADER) {
    5fe0:	2e17      	cmp	r6, #23
    5fe2:	d805      	bhi.n	5ff0 <value_extract+0x38>
#ifdef CONFIG_BIG_ENDIAN
		u8_result[result_len - 1] = additional;
#else
		u8_result[0] = additional;
    5fe4:	702e      	strb	r6, [r5, #0]
#endif /* CONFIG_BIG_ENDIAN */

		(state->payload) += len;
	}

	(state->elem_count)--;
    5fe6:	68a3      	ldr	r3, [r4, #8]
    5fe8:	3b01      	subs	r3, #1
    5fea:	60a3      	str	r3, [r4, #8]
	return true;
    5fec:	2001      	movs	r0, #1
}
    5fee:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	if (24 <= additional && additional <= 27) {
    5ff0:	3e18      	subs	r6, #24
    5ff2:	b2f3      	uxtb	r3, r6
    5ff4:	2b03      	cmp	r3, #3
		FAIL_AND_DECR_IF(len > result_len);
    5ff6:	6822      	ldr	r2, [r4, #0]
	if (24 <= additional && additional <= 27) {
    5ff8:	d808      	bhi.n	600c <value_extract+0x54>
		return 1 << (additional - 24);
    5ffa:	2301      	movs	r3, #1
    5ffc:	fa03 f606 	lsl.w	r6, r3, r6
		FAIL_AND_DECR_IF(len > result_len);
    6000:	42b7      	cmp	r7, r6
    6002:	d204      	bcs.n	600e <value_extract+0x56>
		FAIL_AND_DECR_IF((state->payload + len)
    6004:	3a01      	subs	r2, #1
    6006:	6022      	str	r2, [r4, #0]
	FAIL_IF((state->elem_count == 0) \
    6008:	2000      	movs	r0, #0
    600a:	e7f0      	b.n	5fee <value_extract+0x36>
	return 0;
    600c:	2600      	movs	r6, #0
		FAIL_AND_DECR_IF((state->payload + len)
    600e:	68e1      	ldr	r1, [r4, #12]
    6010:	1993      	adds	r3, r2, r6
    6012:	4299      	cmp	r1, r3
    6014:	d3f6      	bcc.n	6004 <value_extract+0x4c>
    6016:	1e72      	subs	r2, r6, #1
    6018:	3d01      	subs	r5, #1
		for (uint32_t i = 0; i < len; i++) {
    601a:	1c51      	adds	r1, r2, #1
			u8_result[i] = (state->payload)[len - i - 1];
    601c:	6823      	ldr	r3, [r4, #0]
		for (uint32_t i = 0; i < len; i++) {
    601e:	d102      	bne.n	6026 <value_extract+0x6e>
		(state->payload) += len;
    6020:	441e      	add	r6, r3
    6022:	6026      	str	r6, [r4, #0]
    6024:	e7df      	b.n	5fe6 <value_extract+0x2e>
			u8_result[i] = (state->payload)[len - i - 1];
    6026:	5c9b      	ldrb	r3, [r3, r2]
    6028:	f805 3f01 	strb.w	r3, [r5, #1]!
		for (uint32_t i = 0; i < len; i++) {
    602c:	3a01      	subs	r2, #1
    602e:	e7f4      	b.n	601a <value_extract+0x62>

00006030 <uint32_decode>:
}


static bool uint32_decode(cbor_state_t *state, uint32_t *result)
{
	if (!value_extract(state, result, 4)) {
    6030:	2204      	movs	r2, #4
    6032:	f7ff bfc1 	b.w	5fb8 <value_extract>

00006036 <strx_start_decode>:
}


static bool strx_start_decode(cbor_state_t *state,
		cbor_string_type_t *result, cbor_major_type_t exp_major_type)
{
    6036:	b538      	push	{r3, r4, r5, lr}
	FAIL_IF(state->payload >= state->payload_end);
    6038:	6803      	ldr	r3, [r0, #0]
{
    603a:	460d      	mov	r5, r1
	FAIL_IF(state->payload >= state->payload_end);
    603c:	68c1      	ldr	r1, [r0, #12]
    603e:	428b      	cmp	r3, r1
{
    6040:	4604      	mov	r4, r0
	FAIL_IF(state->payload >= state->payload_end);
    6042:	d301      	bcc.n	6048 <strx_start_decode+0x12>

	if (result->len > (state->payload_end - state->payload)) {
		cbor_print("error: 0x%x > 0x%x\r\n",
		(uint32_t)result->len,
		(uint32_t)(state->payload_end - state->payload));
		FAIL_RESTORE();
    6044:	2000      	movs	r0, #0
	}

	result->value = state->payload;
	return true;
}
    6046:	bd38      	pop	{r3, r4, r5, pc}
	uint8_t major_type = MAJOR_TYPE(*state->payload);
    6048:	781b      	ldrb	r3, [r3, #0]
	if (major_type != exp_major_type) {
    604a:	ebb2 1f53 	cmp.w	r2, r3, lsr #5
    604e:	d1f9      	bne.n	6044 <strx_start_decode+0xe>
	if (!uint32_decode(state, &result->len)) {
    6050:	1d29      	adds	r1, r5, #4
    6052:	f7ff ffed 	bl	6030 <uint32_decode>
    6056:	2800      	cmp	r0, #0
    6058:	d0f4      	beq.n	6044 <strx_start_decode+0xe>
	if (result->len > (state->payload_end - state->payload)) {
    605a:	6822      	ldr	r2, [r4, #0]
    605c:	68e3      	ldr	r3, [r4, #12]
    605e:	6869      	ldr	r1, [r5, #4]
    6060:	1a9b      	subs	r3, r3, r2
    6062:	4299      	cmp	r1, r3
    6064:	d905      	bls.n	6072 <strx_start_decode+0x3c>
		FAIL_RESTORE();
    6066:	6863      	ldr	r3, [r4, #4]
    6068:	6023      	str	r3, [r4, #0]
    606a:	68a3      	ldr	r3, [r4, #8]
    606c:	3301      	adds	r3, #1
    606e:	60a3      	str	r3, [r4, #8]
    6070:	e7e8      	b.n	6044 <strx_start_decode+0xe>
	result->value = state->payload;
    6072:	602a      	str	r2, [r5, #0]
	return true;
    6074:	e7e7      	b.n	6046 <strx_start_decode+0x10>

00006076 <list_map_start_decode>:


static bool list_map_start_decode(cbor_state_t *state,
		cbor_major_type_t exp_major_type)
{
	FAIL_IF(state->payload >= state->payload_end);
    6076:	6803      	ldr	r3, [r0, #0]
    6078:	68c2      	ldr	r2, [r0, #12]
    607a:	4293      	cmp	r3, r2
{
    607c:	b513      	push	{r0, r1, r4, lr}
    607e:	4604      	mov	r4, r0
	FAIL_IF(state->payload >= state->payload_end);
    6080:	d213      	bcs.n	60aa <list_map_start_decode+0x34>
	uint8_t major_type = MAJOR_TYPE(*state->payload);
    6082:	781b      	ldrb	r3, [r3, #0]
	uint32_t new_elem_count;

	if (major_type != exp_major_type) {
    6084:	ebb1 1f53 	cmp.w	r1, r3, lsr #5
    6088:	d10f      	bne.n	60aa <list_map_start_decode+0x34>
		FAIL();
	}

	if (!uint32_decode(state, &new_elem_count)) {
    608a:	a901      	add	r1, sp, #4
    608c:	f7ff ffd0 	bl	6030 <uint32_decode>
    6090:	b148      	cbz	r0, 60a6 <list_map_start_decode+0x30>
		FAIL();
	}

	if (!new_backup(state, new_elem_count)) {
    6092:	9901      	ldr	r1, [sp, #4]
    6094:	4620      	mov	r0, r4
    6096:	f000 f95d 	bl	6354 <new_backup>
    609a:	b920      	cbnz	r0, 60a6 <list_map_start_decode+0x30>
		FAIL_RESTORE();
    609c:	6863      	ldr	r3, [r4, #4]
    609e:	6023      	str	r3, [r4, #0]
    60a0:	68a3      	ldr	r3, [r4, #8]
    60a2:	3301      	adds	r3, #1
    60a4:	60a3      	str	r3, [r4, #8]
	}

	return true;
}
    60a6:	b002      	add	sp, #8
    60a8:	bd10      	pop	{r4, pc}
	FAIL_IF(state->payload >= state->payload_end);
    60aa:	2000      	movs	r0, #0
    60ac:	e7fb      	b.n	60a6 <list_map_start_decode+0x30>

000060ae <intx32_decode>:
	FAIL_IF(state->payload >= state->payload_end);
    60ae:	6803      	ldr	r3, [r0, #0]
    60b0:	68c2      	ldr	r2, [r0, #12]
    60b2:	4293      	cmp	r3, r2
{
    60b4:	b573      	push	{r0, r1, r4, r5, r6, lr}
    60b6:	4604      	mov	r4, r0
    60b8:	460d      	mov	r5, r1
	FAIL_IF(state->payload >= state->payload_end);
    60ba:	d212      	bcs.n	60e2 <intx32_decode+0x34>
	uint8_t major_type = MAJOR_TYPE(*state->payload);
    60bc:	781b      	ldrb	r3, [r3, #0]
	if (major_type != CBOR_MAJOR_TYPE_PINT
    60be:	2b3f      	cmp	r3, #63	; 0x3f
	uint8_t major_type = MAJOR_TYPE(*state->payload);
    60c0:	ea4f 1653 	mov.w	r6, r3, lsr #5
	if (major_type != CBOR_MAJOR_TYPE_PINT
    60c4:	d80d      	bhi.n	60e2 <intx32_decode+0x34>
	if (!value_extract(state, &uint_result, 4)) {
    60c6:	2204      	movs	r2, #4
    60c8:	eb0d 0102 	add.w	r1, sp, r2
    60cc:	f7ff ff74 	bl	5fb8 <value_extract>
    60d0:	b168      	cbz	r0, 60ee <intx32_decode+0x40>
	if (uint_result >= (1 << (8*sizeof(uint_result)-1))) {
    60d2:	9b01      	ldr	r3, [sp, #4]
    60d4:	2b00      	cmp	r3, #0
    60d6:	da06      	bge.n	60e6 <intx32_decode+0x38>
		FAIL_RESTORE();
    60d8:	6863      	ldr	r3, [r4, #4]
    60da:	6023      	str	r3, [r4, #0]
    60dc:	68a3      	ldr	r3, [r4, #8]
    60de:	3301      	adds	r3, #1
    60e0:	60a3      	str	r3, [r4, #8]
	FAIL_IF(state->payload >= state->payload_end);
    60e2:	2000      	movs	r0, #0
    60e4:	e003      	b.n	60ee <intx32_decode+0x40>
	if (major_type == CBOR_MAJOR_TYPE_NINT) {
    60e6:	2e01      	cmp	r6, #1
		int_result = -1 - uint_result;
    60e8:	bf08      	it	eq
    60ea:	43db      	mvneq	r3, r3
	*result = int_result;
    60ec:	602b      	str	r3, [r5, #0]
}
    60ee:	b002      	add	sp, #8
    60f0:	bd70      	pop	{r4, r5, r6, pc}

000060f2 <strx_decode>:
{
    60f2:	b538      	push	{r3, r4, r5, lr}
    60f4:	4604      	mov	r4, r0
    60f6:	460d      	mov	r5, r1
	if (!strx_start_decode(state, result, exp_major_type)) {
    60f8:	f7ff ff9d 	bl	6036 <strx_start_decode>
    60fc:	b118      	cbz	r0, 6106 <strx_decode+0x14>
	(state->payload) += result->len;
    60fe:	6823      	ldr	r3, [r4, #0]
    6100:	686a      	ldr	r2, [r5, #4]
    6102:	4413      	add	r3, r2
    6104:	6023      	str	r3, [r4, #0]
}
    6106:	bd38      	pop	{r3, r4, r5, pc}

00006108 <strx_expect>:
{
    6108:	b573      	push	{r0, r1, r4, r5, r6, lr}
    610a:	460e      	mov	r6, r1
	if (!strx_decode(state, &tmp_result, exp_major_type)) {
    610c:	4669      	mov	r1, sp
{
    610e:	4604      	mov	r4, r0
	if (!strx_decode(state, &tmp_result, exp_major_type)) {
    6110:	f7ff ffef 	bl	60f2 <strx_decode>
    6114:	4605      	mov	r5, r0
    6116:	b148      	cbz	r0, 612c <strx_expect+0x24>
	if ((tmp_result.len != result->len)
    6118:	9a01      	ldr	r2, [sp, #4]
    611a:	6873      	ldr	r3, [r6, #4]
    611c:	429a      	cmp	r2, r3
    611e:	d008      	beq.n	6132 <strx_expect+0x2a>
		FAIL_RESTORE();
    6120:	6863      	ldr	r3, [r4, #4]
    6122:	6023      	str	r3, [r4, #0]
    6124:	68a3      	ldr	r3, [r4, #8]
    6126:	3301      	adds	r3, #1
    6128:	60a3      	str	r3, [r4, #8]
    612a:	2500      	movs	r5, #0
}
    612c:	4628      	mov	r0, r5
    612e:	b002      	add	sp, #8
    6130:	bd70      	pop	{r4, r5, r6, pc}
			|| memcmp(result->value, tmp_result.value, tmp_result.len)) {
    6132:	9900      	ldr	r1, [sp, #0]
    6134:	6830      	ldr	r0, [r6, #0]
    6136:	f000 f9b0 	bl	649a <memcmp>
    613a:	2800      	cmp	r0, #0
    613c:	d0f6      	beq.n	612c <strx_expect+0x24>
    613e:	e7ef      	b.n	6120 <strx_expect+0x18>

00006140 <bstrx_decode>:
	return strx_decode(state, result, CBOR_MAJOR_TYPE_BSTR);
    6140:	2202      	movs	r2, #2
    6142:	f7ff bfd6 	b.w	60f2 <strx_decode>

00006146 <tstrx_expect>:
	return strx_expect(state, result, CBOR_MAJOR_TYPE_TSTR);
    6146:	2203      	movs	r2, #3
    6148:	f7ff bfde 	b.w	6108 <strx_expect>

0000614c <map_start_decode>:
	return list_map_start_decode(state, CBOR_MAJOR_TYPE_LIST);
}


bool map_start_decode(cbor_state_t *state)
{
    614c:	b510      	push	{r4, lr}
	bool ret = list_map_start_decode(state, CBOR_MAJOR_TYPE_MAP);
    614e:	2105      	movs	r1, #5
{
    6150:	4604      	mov	r4, r0
	bool ret = list_map_start_decode(state, CBOR_MAJOR_TYPE_MAP);
    6152:	f7ff ff90 	bl	6076 <list_map_start_decode>

	if (ret) {
    6156:	b110      	cbz	r0, 615e <map_start_decode+0x12>
		state->elem_count *= 2;
    6158:	68a3      	ldr	r3, [r4, #8]
    615a:	005b      	lsls	r3, r3, #1
    615c:	60a3      	str	r3, [r4, #8]
	}
	return ret;
}
    615e:	bd10      	pop	{r4, pc}

00006160 <list_map_end_decode>:


bool list_map_end_decode(cbor_state_t *state)
{
	if (!restore_backup(state,
    6160:	2200      	movs	r2, #0
    6162:	2107      	movs	r1, #7
    6164:	f000 b90c 	b.w	6380 <restore_backup>

00006168 <map_end_decode>:
    6168:	f7ff bffa 	b.w	6160 <list_map_end_decode>

0000616c <multi_decode>:
		uint32_t *num_decode,
		cbor_decoder_t decoder,
		cbor_state_t *state,
		void *result,
		uint32_t result_len)
{
    616c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    6170:	e9dd 570c 	ldrd	r5, r7, [sp, #48]	; 0x30
    6174:	4682      	mov	sl, r0
    6176:	4688      	mov	r8, r1
    6178:	4616      	mov	r6, r2
    617a:	469b      	mov	fp, r3
	for (uint32_t i = 0; i < max_decode; i++) {
    617c:	2400      	movs	r4, #0
    617e:	4544      	cmp	r4, r8
    6180:	d102      	bne.n	6188 <multi_decode+0x1c>
			}
			return true;
		}
	}
	cbor_print("Found %zu elements.\n", max_decode);
	*num_decode = max_decode;
    6182:	6034      	str	r4, [r6, #0]
	return true;
    6184:	2001      	movs	r0, #1
    6186:	e013      	b.n	61b0 <multi_decode+0x44>
		uint8_t const *payload_bak = state->payload;
    6188:	682a      	ldr	r2, [r5, #0]
    618a:	9201      	str	r2, [sp, #4]
		if (!decoder(state,
    618c:	4639      	mov	r1, r7
    618e:	4628      	mov	r0, r5
		uint32_t elem_count_bak = state->elem_count;
    6190:	f8d5 9008 	ldr.w	r9, [r5, #8]
		if (!decoder(state,
    6194:	47d8      	blx	fp
    6196:	9b0e      	ldr	r3, [sp, #56]	; 0x38
    6198:	9a01      	ldr	r2, [sp, #4]
    619a:	441f      	add	r7, r3
    619c:	b958      	cbnz	r0, 61b6 <multi_decode+0x4a>
			if (i < min_decode) {
    619e:	4554      	cmp	r4, sl
			*num_decode = i;
    61a0:	6034      	str	r4, [r6, #0]
			if (i < min_decode) {
    61a2:	bf38      	it	cc
    61a4:	2000      	movcc	r0, #0
			state->payload = payload_bak;
    61a6:	602a      	str	r2, [r5, #0]
			state->elem_count = elem_count_bak;
    61a8:	f8c5 9008 	str.w	r9, [r5, #8]
			if (i < min_decode) {
    61ac:	bf28      	it	cs
    61ae:	2001      	movcs	r0, #1
}
    61b0:	b003      	add	sp, #12
    61b2:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	for (uint32_t i = 0; i < max_decode; i++) {
    61b6:	3401      	adds	r4, #1
    61b8:	e7e1      	b.n	617e <multi_decode+0x12>

000061ba <get_result_len>:
	return true;
}


static uint32_t get_result_len(const void *const input, uint32_t max_result_len)
{
    61ba:	b510      	push	{r4, lr}
    61bc:	4603      	mov	r3, r0
	uint8_t *u8_result  = (uint8_t *)input;
	size_t i;

	for (i = 0; i < max_result_len; i++) {
    61be:	2200      	movs	r2, #0
    61c0:	4408      	add	r0, r1
#ifdef CONFIG_BIG_ENDIAN
		size_t idx = i;
#else
		size_t idx = max_result_len - 1 - i;
#endif
		if (u8_result[idx] != 0) {
    61c2:	f810 4d01 	ldrb.w	r4, [r0, #-1]!
    61c6:	b914      	cbnz	r4, 61ce <get_result_len+0x14>
	for (i = 0; i < max_result_len; i++) {
    61c8:	3201      	adds	r2, #1
    61ca:	4291      	cmp	r1, r2
    61cc:	d1f9      	bne.n	61c2 <get_result_len+0x8>
			break;
		}
	}
	max_result_len -= i;
    61ce:	1a89      	subs	r1, r1, r2

	/* According to specification result length can be encoded on 1, 2, 4
	 * or 8 bytes.
	 */
	cbor_assert(max_result_len <= 8, "Up to 8 bytes can be used to encode length.\n");
	size_t encode_byte_cnt = 1;
    61d0:	2001      	movs	r0, #1
	max_result_len -= i;
    61d2:	2204      	movs	r2, #4

	for (size_t i = 0; i <= 3; i++) {
		if (max_result_len <= encode_byte_cnt) {
    61d4:	4281      	cmp	r1, r0
    61d6:	d904      	bls.n	61e2 <get_result_len+0x28>
	for (size_t i = 0; i <= 3; i++) {
    61d8:	3a01      	subs	r2, #1
			max_result_len = encode_byte_cnt;
			break;
		}

		encode_byte_cnt *= 2;
    61da:	ea4f 0040 	mov.w	r0, r0, lsl #1
	for (size_t i = 0; i <= 3; i++) {
    61de:	d1f9      	bne.n	61d4 <get_result_len+0x1a>
    61e0:	4608      	mov	r0, r1
	}

	if ((max_result_len == 1) && (u8_result[0] <= VALUE_IN_HEADER)) {
    61e2:	2801      	cmp	r0, #1
    61e4:	d104      	bne.n	61f0 <get_result_len+0x36>
    61e6:	7818      	ldrb	r0, [r3, #0]
    61e8:	2817      	cmp	r0, #23
    61ea:	bf94      	ite	ls
    61ec:	2000      	movls	r0, #0
    61ee:	2001      	movhi	r0, #1
		max_result_len = 0;
	}

	return max_result_len;
}
    61f0:	bd10      	pop	{r4, pc}

000061f2 <get_additional>:
	switch(len) {
    61f2:	2808      	cmp	r0, #8
    61f4:	d80f      	bhi.n	6216 <get_additional+0x24>
    61f6:	e8df f000 	tbb	[pc, r0]
    61fa:	0506      	.short	0x0506
    61fc:	0a0a0808 	.word	0x0a0a0808
    6200:	0a0a      	.short	0x0a0a
    6202:	0c          	.byte	0x0c
    6203:	00          	.byte	0x00
    6204:	2118      	movs	r1, #24
}
    6206:	4608      	mov	r0, r1
    6208:	4770      	bx	lr
		case 2: return 25;
    620a:	2119      	movs	r1, #25
    620c:	e7fb      	b.n	6206 <get_additional+0x14>
		case 4: return 26;
    620e:	211a      	movs	r1, #26
    6210:	e7f9      	b.n	6206 <get_additional+0x14>
		case 8: return 27;
    6212:	211b      	movs	r1, #27
    6214:	e7f7      	b.n	6206 <get_additional+0x14>
	return 0;
    6216:	2100      	movs	r1, #0
    6218:	e7f5      	b.n	6206 <get_additional+0x14>

0000621a <value_encode>:


static bool value_encode(cbor_state_t *state, cbor_major_type_t major_type,
		const void *const input, uint32_t max_result_len)
{
    621a:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    621e:	4604      	mov	r4, r0
    6220:	460f      	mov	r7, r1
	cbor_assert(max_result_len != 0, "0-length result not supported.\n");
	return value_encode_len(state, major_type, input,
    6222:	4610      	mov	r0, r2
    6224:	4619      	mov	r1, r3
{
    6226:	4616      	mov	r6, r2
	return value_encode_len(state, major_type, input,
    6228:	f7ff ffc7 	bl	61ba <get_result_len>
	if ((state->payload + 1 + result_len) > state->payload_end) {
    622c:	6822      	ldr	r2, [r4, #0]
    622e:	68e1      	ldr	r1, [r4, #12]
    6230:	1c43      	adds	r3, r0, #1
    6232:	4413      	add	r3, r2
    6234:	4299      	cmp	r1, r3
	return value_encode_len(state, major_type, input,
    6236:	4605      	mov	r5, r0
	if ((state->payload + 1 + result_len) > state->payload_end) {
    6238:	d31d      	bcc.n	6276 <value_encode+0x5c>
	if ((state->payload + 1) > state->payload_end) {
    623a:	f102 0801 	add.w	r8, r2, #1
    623e:	4541      	cmp	r1, r8
    6240:	d319      	bcc.n	6276 <value_encode+0x5c>
	if (!encode_header_byte(state, major_type,
    6242:	7831      	ldrb	r1, [r6, #0]
    6244:	f7ff ffd5 	bl	61f2 <get_additional>
	*(state->payload_mut++) = (major_type << 5) | (additional & 0x1F);
    6248:	f000 001f 	and.w	r0, r0, #31
    624c:	ea40 1147 	orr.w	r1, r0, r7, lsl #5
    6250:	f8c4 8000 	str.w	r8, [r4]
    6254:	1973      	adds	r3, r6, r5
    6256:	7011      	strb	r1, [r2, #0]
	for (; result_len > 0; result_len--) {
    6258:	42b3      	cmp	r3, r6
    625a:	d105      	bne.n	6268 <value_encode+0x4e>
	state->elem_count++;
    625c:	68a3      	ldr	r3, [r4, #8]
    625e:	3301      	adds	r3, #1
    6260:	60a3      	str	r3, [r4, #8]
	return true;
    6262:	2001      	movs	r0, #1
				get_result_len(input, max_result_len));
}
    6264:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		*(state->payload_mut++) = u8_result[result_len - 1];
    6268:	6822      	ldr	r2, [r4, #0]
    626a:	1c51      	adds	r1, r2, #1
    626c:	6021      	str	r1, [r4, #0]
    626e:	f813 1d01 	ldrb.w	r1, [r3, #-1]!
    6272:	7011      	strb	r1, [r2, #0]
	for (; result_len > 0; result_len--) {
    6274:	e7f0      	b.n	6258 <value_encode+0x3e>
		FAIL();
    6276:	2000      	movs	r0, #0
    6278:	e7f4      	b.n	6264 <value_encode+0x4a>

0000627a <uint32_encode>:
}


static bool uint32_encode(cbor_state_t *state, const uint32_t *input,
		cbor_major_type_t major_type)
{
    627a:	b410      	push	{r4}
    627c:	460c      	mov	r4, r1
	if (!value_encode(state, major_type, input, 4)) {
    627e:	2304      	movs	r3, #4
{
    6280:	4611      	mov	r1, r2
	if (!value_encode(state, major_type, input, 4)) {
    6282:	4622      	mov	r2, r4
		FAIL();
	}
	return true;
}
    6284:	bc10      	pop	{r4}
	if (!value_encode(state, major_type, input, 4)) {
    6286:	f7ff bfc8 	b.w	621a <value_encode>

0000628a <strx_encode>:
}


static bool strx_encode(cbor_state_t *state,
		const cbor_string_type_t *input, cbor_major_type_t major_type)
{
    628a:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	if (input->value && ((get_result_len(&input->len, sizeof(input->len))
    628c:	460e      	mov	r6, r1
{
    628e:	4604      	mov	r4, r0
	if (input->value && ((get_result_len(&input->len, sizeof(input->len))
    6290:	f856 3b04 	ldr.w	r3, [r6], #4
{
    6294:	460d      	mov	r5, r1
    6296:	4617      	mov	r7, r2
	if (input->value && ((get_result_len(&input->len, sizeof(input->len))
    6298:	b173      	cbz	r3, 62b8 <strx_encode+0x2e>
    629a:	2104      	movs	r1, #4
    629c:	4630      	mov	r0, r6
    629e:	f7ff ff8c 	bl	61ba <get_result_len>
			+ 1 + input->len + (size_t)state->payload)
    62a2:	686a      	ldr	r2, [r5, #4]
    62a4:	6823      	ldr	r3, [r4, #0]
    62a6:	3201      	adds	r2, #1
    62a8:	4413      	add	r3, r2
	if (input->value && ((get_result_len(&input->len, sizeof(input->len))
    62aa:	68e2      	ldr	r2, [r4, #12]
			+ 1 + input->len + (size_t)state->payload)
    62ac:	4403      	add	r3, r0
	if (input->value && ((get_result_len(&input->len, sizeof(input->len))
    62ae:	429a      	cmp	r2, r3
    62b0:	d202      	bcs.n	62b8 <strx_encode+0x2e>
	if (!strx_start_encode(state, input, major_type)) {
		FAIL();
    62b2:	2600      	movs	r6, #0
	if (state->payload_mut != input->value) {
		memmove(state->payload_mut, input->value, input->len);
	}
	state->payload += input->len;
	return true;
}
    62b4:	4630      	mov	r0, r6
    62b6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	if (!uint32_encode(state, &input->len, major_type)) {
    62b8:	4631      	mov	r1, r6
    62ba:	463a      	mov	r2, r7
    62bc:	4620      	mov	r0, r4
    62be:	f7ff ffdc 	bl	627a <uint32_encode>
    62c2:	4606      	mov	r6, r0
    62c4:	2800      	cmp	r0, #0
    62c6:	d0f4      	beq.n	62b2 <strx_encode+0x28>
	if (input->len > (state->payload_end - state->payload)) {
    62c8:	6820      	ldr	r0, [r4, #0]
    62ca:	68e3      	ldr	r3, [r4, #12]
    62cc:	686a      	ldr	r2, [r5, #4]
    62ce:	1a1b      	subs	r3, r3, r0
    62d0:	429a      	cmp	r2, r3
    62d2:	d8ee      	bhi.n	62b2 <strx_encode+0x28>
	if (state->payload_mut != input->value) {
    62d4:	6829      	ldr	r1, [r5, #0]
    62d6:	4288      	cmp	r0, r1
    62d8:	d001      	beq.n	62de <strx_encode+0x54>
		memmove(state->payload_mut, input->value, input->len);
    62da:	f000 f8ef 	bl	64bc <memmove>
	state->payload += input->len;
    62de:	6823      	ldr	r3, [r4, #0]
    62e0:	686a      	ldr	r2, [r5, #4]
    62e2:	4413      	add	r3, r2
    62e4:	6023      	str	r3, [r4, #0]
	return true;
    62e6:	e7e5      	b.n	62b4 <strx_encode+0x2a>

000062e8 <uintx32_put>:
{
    62e8:	b507      	push	{r0, r1, r2, lr}
	if (!uint32_encode(state, &input, CBOR_MAJOR_TYPE_PINT)) {
    62ea:	2200      	movs	r2, #0
{
    62ec:	9101      	str	r1, [sp, #4]
	if (!uint32_encode(state, &input, CBOR_MAJOR_TYPE_PINT)) {
    62ee:	a901      	add	r1, sp, #4
    62f0:	f7ff ffc3 	bl	627a <uint32_encode>
}
    62f4:	b003      	add	sp, #12
    62f6:	f85d fb04 	ldr.w	pc, [sp], #4

000062fa <tstrx_encode>:
}


bool tstrx_encode(cbor_state_t *state, const cbor_string_type_t *input)
{
	return strx_encode(state, input, CBOR_MAJOR_TYPE_TSTR);
    62fa:	2203      	movs	r2, #3
    62fc:	f7ff bfc5 	b.w	628a <strx_encode>

00006300 <list_start_encode>:
	if ((state->payload + 1) > state->payload_end) {
    6300:	6803      	ldr	r3, [r0, #0]
    6302:	68c1      	ldr	r1, [r0, #12]
    6304:	1c5a      	adds	r2, r3, #1
    6306:	428a      	cmp	r2, r1
	*(state->payload_mut++) = (major_type << 5) | (additional & 0x1F);
    6308:	bf9f      	itttt	ls
    630a:	6002      	strls	r2, [r0, #0]
    630c:	229f      	movls	r2, #159	; 0x9f
#else
	if (!encode_header_byte(state, major_type, 31)) {
		FAIL();
	}
#endif
	return true;
    630e:	2001      	movls	r0, #1
	*(state->payload_mut++) = (major_type << 5) | (additional & 0x1F);
    6310:	701a      	strbls	r2, [r3, #0]
		FAIL();
    6312:	bf88      	it	hi
    6314:	2000      	movhi	r0, #0


bool list_start_encode(cbor_state_t *state, uint32_t max_num)
{
	return list_map_start_encode(state, max_num, CBOR_MAJOR_TYPE_LIST);
}
    6316:	4770      	bx	lr

00006318 <map_start_encode>:
	if ((state->payload + 1) > state->payload_end) {
    6318:	6803      	ldr	r3, [r0, #0]
    631a:	68c1      	ldr	r1, [r0, #12]
    631c:	1c5a      	adds	r2, r3, #1
    631e:	428a      	cmp	r2, r1
	*(state->payload_mut++) = (major_type << 5) | (additional & 0x1F);
    6320:	bf9f      	itttt	ls
    6322:	6002      	strls	r2, [r0, #0]
    6324:	22bf      	movls	r2, #191	; 0xbf
	return true;
    6326:	2001      	movls	r0, #1
	*(state->payload_mut++) = (major_type << 5) | (additional & 0x1F);
    6328:	701a      	strbls	r2, [r3, #0]
		FAIL();
    632a:	bf88      	it	hi
    632c:	2000      	movhi	r0, #0


bool map_start_encode(cbor_state_t *state, uint32_t max_num)
{
	return list_map_start_encode(state, max_num, CBOR_MAJOR_TYPE_MAP);
}
    632e:	4770      	bx	lr

00006330 <list_map_end_encode>:
	if ((state->payload + 1) > state->payload_end) {
    6330:	6803      	ldr	r3, [r0, #0]
    6332:	68c1      	ldr	r1, [r0, #12]
    6334:	1c5a      	adds	r2, r3, #1
    6336:	428a      	cmp	r2, r1
	*(state->payload_mut++) = (major_type << 5) | (additional & 0x1F);
    6338:	bf9f      	itttt	ls
    633a:	6002      	strls	r2, [r0, #0]
    633c:	22ff      	movls	r2, #255	; 0xff
#else
	if (!encode_header_byte(state, CBOR_MAJOR_TYPE_PRIM, 31)) {
		FAIL();
	}
#endif
	return true;
    633e:	2001      	movls	r0, #1
	*(state->payload_mut++) = (major_type << 5) | (additional & 0x1F);
    6340:	701a      	strbls	r2, [r3, #0]
		FAIL();
    6342:	bf88      	it	hi
    6344:	2000      	movhi	r0, #0
}
    6346:	4770      	bx	lr

00006348 <list_end_encode>:


bool list_end_encode(cbor_state_t *state, uint32_t max_num)
{
	return list_map_end_encode(state, max_num, CBOR_MAJOR_TYPE_LIST);
    6348:	2204      	movs	r2, #4
    634a:	f7ff bff1 	b.w	6330 <list_map_end_encode>

0000634e <map_end_encode>:
}


bool map_end_encode(cbor_state_t *state, uint32_t max_num)
{
	return list_map_end_encode(state, max_num, CBOR_MAJOR_TYPE_MAP);
    634e:	2205      	movs	r2, #5
    6350:	f7ff bfee 	b.w	6330 <list_map_end_encode>

00006354 <new_backup>:
_Static_assert((sizeof(size_t) == sizeof(void *)),
	"This code needs size_t to be the same length as pointers.");

bool new_backup(cbor_state_t *state, uint32_t new_elem_count)
{
	if ((state->backups->current_backup + 1)
    6354:	6902      	ldr	r2, [r0, #16]
{
    6356:	b538      	push	{r3, r4, r5, lr}
	if ((state->backups->current_backup + 1)
    6358:	6853      	ldr	r3, [r2, #4]
{
    635a:	460d      	mov	r5, r1
	if ((state->backups->current_backup + 1)
    635c:	6891      	ldr	r1, [r2, #8]
    635e:	3301      	adds	r3, #1
    6360:	428b      	cmp	r3, r1
{
    6362:	4604      	mov	r4, r0
	if ((state->backups->current_backup + 1)
    6364:	d20a      	bcs.n	637c <new_backup+0x28>
		>= state->backups->num_backups) {
		FAIL();
	}

	uint32_t i = ++(state->backups->current_backup);
	memcpy(&state->backups->backup_list[i], state,
    6366:	6810      	ldr	r0, [r2, #0]
	uint32_t i = ++(state->backups->current_backup);
    6368:	6053      	str	r3, [r2, #4]
	memcpy(&state->backups->backup_list[i], state,
    636a:	2214      	movs	r2, #20
    636c:	4621      	mov	r1, r4
    636e:	fb02 0003 	mla	r0, r2, r3, r0
    6372:	f000 f8bb 	bl	64ec <memcpy>
		sizeof(cbor_state_t));

	state->elem_count = new_elem_count;
    6376:	60a5      	str	r5, [r4, #8]

	return true;
    6378:	2001      	movs	r0, #1
}
    637a:	bd38      	pop	{r3, r4, r5, pc}
		FAIL();
    637c:	2000      	movs	r0, #0
    637e:	e7fc      	b.n	637a <new_backup+0x26>

00006380 <restore_backup>:


bool restore_backup(cbor_state_t *state, uint32_t flags,
		uint32_t max_elem_count)
{
    6380:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6384:	4616      	mov	r6, r2
	const uint8_t *payload = state->payload;
	const uint32_t elem_count = state->elem_count;

	if (state->backups->current_backup == 0) {
    6386:	6902      	ldr	r2, [r0, #16]
    6388:	6853      	ldr	r3, [r2, #4]
{
    638a:	4604      	mov	r4, r0
    638c:	460d      	mov	r5, r1
	if (state->backups->current_backup == 0) {
    638e:	b913      	cbnz	r3, 6396 <restore_backup+0x16>
		FAIL();
    6390:	2000      	movs	r0, #0
	if (flags & FLAG_TRANSFER_PAYLOAD) {
		state->payload = payload;
	}

	return true;
}
    6392:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if (flags & FLAG_RESTORE) {
    6396:	07e9      	lsls	r1, r5, #31
	const uint8_t *payload = state->payload;
    6398:	6807      	ldr	r7, [r0, #0]
	const uint32_t elem_count = state->elem_count;
    639a:	f8d0 8008 	ldr.w	r8, [r0, #8]
	if (flags & FLAG_RESTORE) {
    639e:	d505      	bpl.n	63ac <restore_backup+0x2c>
		memcpy(state, &state->backups->backup_list[i],
    63a0:	6811      	ldr	r1, [r2, #0]
    63a2:	2214      	movs	r2, #20
    63a4:	fb02 1103 	mla	r1, r2, r3, r1
    63a8:	f000 f8a0 	bl	64ec <memcpy>
	if (flags & FLAG_DISCARD) {
    63ac:	07aa      	lsls	r2, r5, #30
		state->backups->current_backup--;
    63ae:	bf41      	itttt	mi
    63b0:	6922      	ldrmi	r2, [r4, #16]
    63b2:	6853      	ldrmi	r3, [r2, #4]
    63b4:	f103 33ff 	addmi.w	r3, r3, #4294967295
    63b8:	6053      	strmi	r3, [r2, #4]
	if (elem_count > max_elem_count) {
    63ba:	45b0      	cmp	r8, r6
    63bc:	d8e8      	bhi.n	6390 <restore_backup+0x10>
	if (flags & FLAG_TRANSFER_PAYLOAD) {
    63be:	076b      	lsls	r3, r5, #29
		state->payload = payload;
    63c0:	bf48      	it	mi
    63c2:	6027      	strmi	r7, [r4, #0]
	return true;
    63c4:	2001      	movs	r0, #1
    63c6:	e7e4      	b.n	6392 <restore_backup+0x12>

000063c8 <union_start_code>:


bool union_start_code(cbor_state_t *state)
{
	if (!new_backup(state, state->elem_count)) {
    63c8:	6881      	ldr	r1, [r0, #8]
    63ca:	f7ff bfc3 	b.w	6354 <new_backup>

000063ce <union_elem_code>:
}


bool union_elem_code(cbor_state_t *state)
{
	if (!restore_backup(state, FLAG_RESTORE, state->elem_count)) {
    63ce:	6882      	ldr	r2, [r0, #8]
    63d0:	2101      	movs	r1, #1
    63d2:	f7ff bfd5 	b.w	6380 <restore_backup>

000063d6 <union_end_code>:
	return true;
}

bool union_end_code(cbor_state_t *state)
{
	if (!restore_backup(state, FLAG_DISCARD, state->elem_count)) {
    63d6:	6882      	ldr	r2, [r0, #8]
    63d8:	2102      	movs	r1, #2
    63da:	f7ff bfd1 	b.w	6380 <restore_backup>

000063de <entry_function>:
}

bool entry_function(const uint8_t *payload, uint32_t payload_len,
		const void *struct_ptr, uint32_t *payload_len_out,
		cbor_encoder_t func, uint32_t elem_count, uint32_t num_backups)
{
    63de:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    63e2:	b088      	sub	sp, #32
    63e4:	af00      	add	r7, sp, #0
    63e6:	4605      	mov	r5, r0
    63e8:	6c38      	ldr	r0, [r7, #64]	; 0x40
		.backup_list = state_backups,
		.current_backup = 0,
		.num_backups = num_backups + 1,
	};

	state.backups = &backups;
    63ea:	61ff      	str	r7, [r7, #28]
	cbor_state_t state_backups[num_backups + 1];
    63ec:	2414      	movs	r4, #20
{
    63ee:	460e      	mov	r6, r1
	cbor_state_t state_backups[num_backups + 1];
    63f0:	fb00 4404 	mla	r4, r0, r4, r4
	cbor_state_t state = {
    63f4:	6bf9      	ldr	r1, [r7, #60]	; 0x3c
    63f6:	6179      	str	r1, [r7, #20]
	cbor_state_t state_backups[num_backups + 1];
    63f8:	3407      	adds	r4, #7
		.payload_end = payload + payload_len,
    63fa:	19a9      	adds	r1, r5, r6
{
    63fc:	4698      	mov	r8, r3
	cbor_state_t state = {
    63fe:	61b9      	str	r1, [r7, #24]
    6400:	2300      	movs	r3, #0
	cbor_state_t state_backups[num_backups + 1];
    6402:	1c41      	adds	r1, r0, #1
    6404:	f024 0407 	bic.w	r4, r4, #7
	cbor_state_backups_t backups = {
    6408:	e9c7 3101 	strd	r3, r1, [r7, #4]
	cbor_state_t state = {
    640c:	e9c7 5303 	strd	r5, r3, [r7, #12]
	cbor_state_t state_backups[num_backups + 1];
    6410:	ebad 0d04 	sub.w	sp, sp, r4

	bool result = func(&state, struct_ptr);
    6414:	6bbb      	ldr	r3, [r7, #56]	; 0x38
	cbor_state_backups_t backups = {
    6416:	f8c7 d000 	str.w	sp, [r7]
	bool result = func(&state, struct_ptr);
    641a:	4611      	mov	r1, r2
    641c:	f107 000c 	add.w	r0, r7, #12
    6420:	4798      	blx	r3

	if (result && (payload_len_out != NULL)) {
    6422:	b150      	cbz	r0, 643a <entry_function+0x5c>
    6424:	f1b8 0f00 	cmp.w	r8, #0
    6428:	d007      	beq.n	643a <entry_function+0x5c>
		*payload_len_out = MIN(payload_len,
    642a:	68fb      	ldr	r3, [r7, #12]
    642c:	1b5b      	subs	r3, r3, r5
    642e:	42b3      	cmp	r3, r6
    6430:	bf94      	ite	ls
    6432:	f8c8 3000 	strls.w	r3, [r8]
    6436:	f8c8 6000 	strhi.w	r6, [r8]
				(size_t)state.payload - (size_t)payload);
	}
	return result;
}
    643a:	3720      	adds	r7, #32
    643c:	46bd      	mov	sp, r7
    643e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00006442 <z_do_kernel_oops>:
 *   fault handler will executed instead of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    6442:	4601      	mov	r1, r0
	}

#endif /* CONFIG_USERSPACE */

#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	z_arm_fatal_error(reason, esf);
    6444:	6800      	ldr	r0, [r0, #0]
    6446:	f7fc b9cb 	b.w	27e0 <z_arm_fatal_error>

0000644a <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    644a:	2100      	movs	r1, #0
    644c:	2001      	movs	r0, #1
    644e:	f7fc b9c7 	b.w	27e0 <z_arm_fatal_error>

00006452 <z_arm_nmi>:
 * Simply call what is installed in 'static void(*handler)(void)'.
 *
 */

void z_arm_nmi(void)
{
    6452:	b508      	push	{r3, lr}
	handler();
    6454:	f7fc fa28 	bl	28a8 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    6458:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    645c:	f7fc ba96 	b.w	298c <z_arm_exc_exit>

00006460 <strcpy>:

char *strcpy(char *ZRESTRICT d, const char *ZRESTRICT s)
{
	char *dest = d;

	while (*s != '\0') {
    6460:	3901      	subs	r1, #1
    6462:	4603      	mov	r3, r0
    6464:	f811 2f01 	ldrb.w	r2, [r1, #1]!
    6468:	b90a      	cbnz	r2, 646e <strcpy+0xe>
		*d = *s;
		d++;
		s++;
	}

	*d = '\0';
    646a:	701a      	strb	r2, [r3, #0]

	return dest;
}
    646c:	4770      	bx	lr
		*d = *s;
    646e:	f803 2b01 	strb.w	r2, [r3], #1
		s++;
    6472:	e7f7      	b.n	6464 <strcpy+0x4>

00006474 <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    6474:	4603      	mov	r3, r0
	size_t n = 0;
    6476:	2000      	movs	r0, #0

	while (*s != '\0') {
    6478:	5c1a      	ldrb	r2, [r3, r0]
    647a:	b902      	cbnz	r2, 647e <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    647c:	4770      	bx	lr
		n++;
    647e:	3001      	adds	r0, #1
    6480:	e7fa      	b.n	6478 <strlen+0x4>

00006482 <strcmp>:
 * @return negative # if <s1> < <s2>, 0 if <s1> == <s2>, else positive #
 */

int strcmp(const char *s1, const char *s2)
{
	while ((*s1 == *s2) && (*s1 != '\0')) {
    6482:	1e43      	subs	r3, r0, #1
    6484:	3901      	subs	r1, #1
    6486:	f813 2f01 	ldrb.w	r2, [r3, #1]!
    648a:	f811 0f01 	ldrb.w	r0, [r1, #1]!
    648e:	4282      	cmp	r2, r0
    6490:	d101      	bne.n	6496 <strcmp+0x14>
    6492:	2a00      	cmp	r2, #0
    6494:	d1f7      	bne.n	6486 <strcmp+0x4>
		s1++;
		s2++;
	}

	return *s1 - *s2;
}
    6496:	1a10      	subs	r0, r2, r0
    6498:	4770      	bx	lr

0000649a <memcmp>:
 * @brief Compare two memory areas
 *
 * @return negative # if <m1> < <m2>, 0 if <m1> == <m2>, else positive #
 */
int memcmp(const void *m1, const void *m2, size_t n)
{
    649a:	b510      	push	{r4, lr}
    649c:	4603      	mov	r3, r0
	const char *c1 = m1;
	const char *c2 = m2;

	if (!n) {
    649e:	b15a      	cbz	r2, 64b8 <memcmp+0x1e>
    64a0:	3901      	subs	r1, #1
    64a2:	1884      	adds	r4, r0, r2
		return 0;
	}

	while ((--n > 0) && (*c1 == *c2)) {
    64a4:	f813 0b01 	ldrb.w	r0, [r3], #1
    64a8:	f811 2f01 	ldrb.w	r2, [r1, #1]!
    64ac:	42a3      	cmp	r3, r4
    64ae:	d001      	beq.n	64b4 <memcmp+0x1a>
    64b0:	4290      	cmp	r0, r2
    64b2:	d0f7      	beq.n	64a4 <memcmp+0xa>
		c1++;
		c2++;
	}

	return *c1 - *c2;
    64b4:	1a80      	subs	r0, r0, r2
}
    64b6:	bd10      	pop	{r4, pc}
		return 0;
    64b8:	4610      	mov	r0, r2
    64ba:	e7fc      	b.n	64b6 <memcmp+0x1c>

000064bc <memmove>:
void *memmove(void *d, const void *s, size_t n)
{
	char *dest = d;
	const char *src  = s;

	if ((size_t) (dest - src) < n) {
    64bc:	1a43      	subs	r3, r0, r1
    64be:	4293      	cmp	r3, r2
{
    64c0:	b510      	push	{r4, lr}
    64c2:	eb00 0302 	add.w	r3, r0, r2
	if ((size_t) (dest - src) < n) {
    64c6:	d308      	bcc.n	64da <memmove+0x1e>
    64c8:	3901      	subs	r1, #1
	char *dest = d;
    64ca:	4602      	mov	r2, r0
			n--;
			dest[n] = src[n];
		}
	} else {
		/* It is safe to perform a forward-copy */
		while (n > 0) {
    64cc:	429a      	cmp	r2, r3
    64ce:	d007      	beq.n	64e0 <memmove+0x24>
			*dest = *src;
    64d0:	f811 4f01 	ldrb.w	r4, [r1, #1]!
    64d4:	f802 4b01 	strb.w	r4, [r2], #1
			dest++;
			src++;
			n--;
    64d8:	e7f8      	b.n	64cc <memmove+0x10>
    64da:	440a      	add	r2, r1
		while (n > 0) {
    64dc:	428a      	cmp	r2, r1
    64de:	d100      	bne.n	64e2 <memmove+0x26>
		}
	}

	return d;
}
    64e0:	bd10      	pop	{r4, pc}
			dest[n] = src[n];
    64e2:	f812 4d01 	ldrb.w	r4, [r2, #-1]!
    64e6:	f803 4d01 	strb.w	r4, [r3, #-1]!
    64ea:	e7f7      	b.n	64dc <memmove+0x20>

000064ec <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n)
{
    64ec:	b510      	push	{r4, lr}
    64ee:	1e43      	subs	r3, r0, #1
    64f0:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
    64f2:	4291      	cmp	r1, r2
    64f4:	d100      	bne.n	64f8 <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    64f6:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
    64f8:	f811 4b01 	ldrb.w	r4, [r1], #1
    64fc:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    6500:	e7f7      	b.n	64f2 <memcpy+0x6>

00006502 <memset>:
void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
	unsigned char c_byte = (unsigned char)c;
    6502:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
    6504:	4402      	add	r2, r0
	unsigned char *d_byte = (unsigned char *)buf;
    6506:	4603      	mov	r3, r0
	while (n > 0) {
    6508:	4293      	cmp	r3, r2
    650a:	d100      	bne.n	650e <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    650c:	4770      	bx	lr
		*(d_byte++) = c_byte;
    650e:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    6512:	e7f9      	b.n	6508 <memset+0x6>

00006514 <_stdout_hook_default>:
}
    6514:	f04f 30ff 	mov.w	r0, #4294967295
    6518:	4770      	bx	lr

0000651a <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    651a:	6903      	ldr	r3, [r0, #16]
    651c:	b2c9      	uxtb	r1, r1
    651e:	220c      	movs	r2, #12
    6520:	fb01 3302 	mla	r3, r1, r2, r3
    6524:	6c18      	ldr	r0, [r3, #64]	; 0x40
}
    6526:	f000 0007 	and.w	r0, r0, #7
    652a:	4770      	bx	lr

0000652c <set_on_state>:
	__asm__ volatile(
    652c:	f04f 0320 	mov.w	r3, #32
    6530:	f3ef 8211 	mrs	r2, BASEPRI
    6534:	f383 8812 	msr	BASEPRI_MAX, r3
    6538:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    653c:	6803      	ldr	r3, [r0, #0]
    653e:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    6542:	f043 0302 	orr.w	r3, r3, #2
    6546:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    6548:	f382 8811 	msr	BASEPRI, r2
    654c:	f3bf 8f6f 	isb	sy
}
    6550:	4770      	bx	lr

00006552 <stop>:
{
    6552:	4603      	mov	r3, r0
    6554:	b570      	push	{r4, r5, r6, lr}
	struct nrf_clock_control_data *data = dev->data;
    6556:	6900      	ldr	r0, [r0, #16]
	return &data->subsys[type];
    6558:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    655a:	f04f 0420 	mov.w	r4, #32
    655e:	f3ef 8611 	mrs	r6, BASEPRI
    6562:	f384 8812 	msr	BASEPRI_MAX, r4
    6566:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    656a:	250c      	movs	r5, #12
    656c:	fb05 0401 	mla	r4, r5, r1, r0
    6570:	6c24      	ldr	r4, [r4, #64]	; 0x40
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    6572:	f014 04c0 	ands.w	r4, r4, #192	; 0xc0
    6576:	d001      	beq.n	657c <stop+0x2a>
    6578:	42a2      	cmp	r2, r4
    657a:	d111      	bne.n	65a0 <stop+0x4e>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    657c:	fb05 0001 	mla	r0, r5, r1, r0
    6580:	2201      	movs	r2, #1
    6582:	6402      	str	r2, [r0, #64]	; 0x40
	int err = 0;
    6584:	2000      	movs	r0, #0
	__asm__ volatile(
    6586:	f386 8811 	msr	BASEPRI, r6
    658a:	f3bf 8f6f 	isb	sy
	if (err < 0) {
    658e:	b930      	cbnz	r0, 659e <stop+0x4c>
	get_sub_config(dev, type)->stop();
    6590:	685b      	ldr	r3, [r3, #4]
    6592:	220c      	movs	r2, #12
    6594:	fb02 3101 	mla	r1, r2, r1, r3
    6598:	684b      	ldr	r3, [r1, #4]
    659a:	4798      	blx	r3
	return 0;
    659c:	2000      	movs	r0, #0
}
    659e:	bd70      	pop	{r4, r5, r6, pc}
		err = -EPERM;
    65a0:	f04f 30ff 	mov.w	r0, #4294967295
    65a4:	e7ef      	b.n	6586 <stop+0x34>

000065a6 <api_stop>:
	return stop(dev, subsys, CTX_API);
    65a6:	2280      	movs	r2, #128	; 0x80
    65a8:	f7ff bfd3 	b.w	6552 <stop>

000065ac <async_start>:
{
    65ac:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    65ae:	9f06      	ldr	r7, [sp, #24]
	struct nrf_clock_control_data *data = dev->data;
    65b0:	6904      	ldr	r4, [r0, #16]
{
    65b2:	4605      	mov	r5, r0
    65b4:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    65b6:	f04f 0020 	mov.w	r0, #32
    65ba:	f3ef 8c11 	mrs	ip, BASEPRI
    65be:	f380 8812 	msr	BASEPRI_MAX, r0
    65c2:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    65c6:	260c      	movs	r6, #12
    65c8:	fb06 4601 	mla	r6, r6, r1, r4
    65cc:	6c30      	ldr	r0, [r6, #64]	; 0x40
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    65ce:	f000 0e07 	and.w	lr, r0, #7
    65d2:	f1be 0f01 	cmp.w	lr, #1
    65d6:	d110      	bne.n	65fa <async_start+0x4e>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    65d8:	6437      	str	r7, [r6, #64]	; 0x40
	int err = 0;
    65da:	2600      	movs	r6, #0
	__asm__ volatile(
    65dc:	f38c 8811 	msr	BASEPRI, ip
    65e0:	f3bf 8f6f 	isb	sy
	if (err < 0) {
    65e4:	b93e      	cbnz	r6, 65f6 <async_start+0x4a>
	subdata->cb = cb;
    65e6:	200c      	movs	r0, #12
    65e8:	4341      	muls	r1, r0
    65ea:	440c      	add	r4, r1
	subdata->user_data = user_data;
    65ec:	e9c4 230e 	strd	r2, r3, [r4, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    65f0:	686b      	ldr	r3, [r5, #4]
    65f2:	585b      	ldr	r3, [r3, r1]
    65f4:	4798      	blx	r3
}
    65f6:	4630      	mov	r0, r6
    65f8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    65fa:	f000 00c0 	and.w	r0, r0, #192	; 0xc0
		err = -EALREADY;
    65fe:	4287      	cmp	r7, r0
    6600:	bf14      	ite	ne
    6602:	f04f 36ff 	movne.w	r6, #4294967295
    6606:	f06f 0677 	mvneq.w	r6, #119	; 0x77
    660a:	e7e7      	b.n	65dc <async_start+0x30>

0000660c <api_start>:
{
    660c:	b513      	push	{r0, r1, r4, lr}
	return async_start(dev, subsys, cb, user_data, CTX_API);
    660e:	2480      	movs	r4, #128	; 0x80
    6610:	9400      	str	r4, [sp, #0]
    6612:	f7ff ffcb 	bl	65ac <async_start>
}
    6616:	b002      	add	sp, #8
    6618:	bd10      	pop	{r4, pc}

0000661a <api_blocking_start>:
}
    661a:	f06f 0085 	mvn.w	r0, #133	; 0x85
    661e:	4770      	bx	lr

00006620 <onoff_started_callback>:
	return &data->mgr[type];
    6620:	6900      	ldr	r0, [r0, #16]
{
    6622:	b410      	push	{r4}
	return &data->mgr[type];
    6624:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    6626:	241c      	movs	r4, #28
    6628:	fb03 0004 	mla	r0, r3, r4, r0
    662c:	2100      	movs	r1, #0
}
    662e:	bc10      	pop	{r4}
	notify(mgr, 0);
    6630:	4710      	bx	r2

00006632 <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    6632:	2000      	movs	r0, #0
    6634:	f001 bfd9 	b.w	85ea <nrfx_clock_stop>

00006638 <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6638:	6843      	ldr	r3, [r0, #4]
    663a:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    663c:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    6640:	600b      	str	r3, [r1, #0]
}
    6642:	2000      	movs	r0, #0
    6644:	4770      	bx	lr

00006646 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6646:	6843      	ldr	r3, [r0, #4]
    6648:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
    664a:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
    664e:	4042      	eors	r2, r0
    6650:	400a      	ands	r2, r1
    6652:	4042      	eors	r2, r0
    p_reg->OUT = value;
    6654:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
}
    6658:	2000      	movs	r0, #0
    665a:	4770      	bx	lr

0000665c <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    665c:	6843      	ldr	r3, [r0, #4]
    665e:	685b      	ldr	r3, [r3, #4]
}
    6660:	2000      	movs	r0, #0
    p_reg->OUTSET = set_mask;
    6662:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
    6666:	4770      	bx	lr

00006668 <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6668:	6843      	ldr	r3, [r0, #4]
    666a:	685b      	ldr	r3, [r3, #4]
}
    666c:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    666e:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
    6672:	4770      	bx	lr

00006674 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6674:	6843      	ldr	r3, [r0, #4]
    6676:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    6678:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value ^ mask);
    667c:	404b      	eors	r3, r1
    p_reg->OUT = value;
    667e:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
}
    6682:	2000      	movs	r0, #0
    6684:	4770      	bx	lr

00006686 <gpio_nrfx_manage_callback>:
	return port->data;
    6686:	6903      	ldr	r3, [r0, #16]
	return list->head;
    6688:	6858      	ldr	r0, [r3, #4]
{
    668a:	b530      	push	{r4, r5, lr}
	if (!sys_slist_is_empty(callbacks)) {
    668c:	b158      	cbz	r0, 66a6 <gpio_nrfx_manage_callback+0x20>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    668e:	2400      	movs	r4, #0
    6690:	4281      	cmp	r1, r0
    6692:	d112      	bne.n	66ba <gpio_nrfx_manage_callback+0x34>
	return node->next;
    6694:	6808      	ldr	r0, [r1, #0]
	return list->tail;
    6696:	689d      	ldr	r5, [r3, #8]
Z_GENLIST_REMOVE(slist, snode)
    6698:	b954      	cbnz	r4, 66b0 <gpio_nrfx_manage_callback+0x2a>
    669a:	428d      	cmp	r5, r1
	list->head = node;
    669c:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    669e:	d100      	bne.n	66a2 <gpio_nrfx_manage_callback+0x1c>
	list->tail = node;
    66a0:	6098      	str	r0, [r3, #8]
	parent->next = child;
    66a2:	2000      	movs	r0, #0
    66a4:	6008      	str	r0, [r1, #0]
	if (set) {
    66a6:	b96a      	cbnz	r2, 66c4 <gpio_nrfx_manage_callback+0x3e>
	return 0;
    66a8:	2000      	movs	r0, #0
}
    66aa:	bd30      	pop	{r4, r5, pc}
    66ac:	4628      	mov	r0, r5
    66ae:	e7ef      	b.n	6690 <gpio_nrfx_manage_callback+0xa>
Z_GENLIST_REMOVE(slist, snode)
    66b0:	428d      	cmp	r5, r1
	parent->next = child;
    66b2:	6020      	str	r0, [r4, #0]
	list->tail = node;
    66b4:	bf08      	it	eq
    66b6:	609c      	streq	r4, [r3, #8]
}
    66b8:	e7f3      	b.n	66a2 <gpio_nrfx_manage_callback+0x1c>
	return node->next;
    66ba:	6805      	ldr	r5, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    66bc:	4604      	mov	r4, r0
    66be:	2d00      	cmp	r5, #0
    66c0:	d1f4      	bne.n	66ac <gpio_nrfx_manage_callback+0x26>
			if (!set) {
    66c2:	b13a      	cbz	r2, 66d4 <gpio_nrfx_manage_callback+0x4e>
Z_GENLIST_PREPEND(slist, snode)
    66c4:	6898      	ldr	r0, [r3, #8]
	parent->next = child;
    66c6:	685a      	ldr	r2, [r3, #4]
    66c8:	600a      	str	r2, [r1, #0]
	list->head = node;
    66ca:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    66cc:	2800      	cmp	r0, #0
    66ce:	d1eb      	bne.n	66a8 <gpio_nrfx_manage_callback+0x22>
	list->tail = node;
    66d0:	6099      	str	r1, [r3, #8]
}
    66d2:	e7ea      	b.n	66aa <gpio_nrfx_manage_callback+0x24>
				return -EINVAL;
    66d4:	f06f 0015 	mvn.w	r0, #21
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    66d8:	e7e7      	b.n	66aa <gpio_nrfx_manage_callback+0x24>

000066da <is_regular_addr_valid>:
{
    66da:	b538      	push	{r3, r4, r5, lr}
    66dc:	4605      	mov	r5, r0
    66de:	460c      	mov	r4, r1
	return is_within_bounds(addr, len, 0, nrfx_nvmc_flash_size_get());
    66e0:	f001 ff93 	bl	860a <nrfx_nvmc_flash_size_get>
			(addr < (boundary_start + boundary_size)) &&
    66e4:	2d00      	cmp	r5, #0
    66e6:	db07      	blt.n	66f8 <is_regular_addr_valid+0x1e>
	return (addr >= boundary_start &&
    66e8:	42a8      	cmp	r0, r5
    66ea:	d905      	bls.n	66f8 <is_regular_addr_valid+0x1e>
			(len <= (boundary_start + boundary_size - addr)));
    66ec:	1b40      	subs	r0, r0, r5
			(addr < (boundary_start + boundary_size)) &&
    66ee:	4284      	cmp	r4, r0
    66f0:	bf8c      	ite	hi
    66f2:	2000      	movhi	r0, #0
    66f4:	2001      	movls	r0, #1
}
    66f6:	bd38      	pop	{r3, r4, r5, pc}
			(addr < (boundary_start + boundary_size)) &&
    66f8:	2000      	movs	r0, #0
    66fa:	e7fc      	b.n	66f6 <is_regular_addr_valid+0x1c>

000066fc <flash_get_page_info>:

#include <drivers/flash.h>

static int flash_get_page_info(const struct device *dev, off_t offs,
			       uint32_t index, struct flash_pages_info *info)
{
    66fc:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    6700:	461c      	mov	r4, r3
	const struct flash_driver_api *api = dev->api;
    6702:	6883      	ldr	r3, [r0, #8]
	const struct flash_pages_layout *layout;
	size_t layout_size;
	uint32_t index_jmp;

	info->start_offset = 0;
    6704:	f04f 0800 	mov.w	r8, #0
	info->index = 0U;

	api->page_layout(dev, &layout, &layout_size);
    6708:	691b      	ldr	r3, [r3, #16]
	info->start_offset = 0;
    670a:	f8c4 8000 	str.w	r8, [r4]
{
    670e:	460d      	mov	r5, r1
    6710:	4616      	mov	r6, r2
	info->index = 0U;
    6712:	f8c4 8008 	str.w	r8, [r4, #8]
	api->page_layout(dev, &layout, &layout_size);
    6716:	aa01      	add	r2, sp, #4
    6718:	4669      	mov	r1, sp
    671a:	4798      	blx	r3

	while (layout_size--) {
    671c:	e9dd 7c00 	ldrd	r7, ip, [sp]
    6720:	4640      	mov	r0, r8
		info->size = layout->pages_size;
    6722:	f107 0e04 	add.w	lr, r7, #4
	while (layout_size--) {
    6726:	4560      	cmp	r0, ip
    6728:	d104      	bne.n	6734 <flash_get_page_info+0x38>
		}

		layout++;
	}

	return -EINVAL; /* page at offs or idx doesn't exist */
    672a:	f06f 0015 	mvn.w	r0, #21
}
    672e:	b003      	add	sp, #12
    6730:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
		info->size = layout->pages_size;
    6734:	f85e 9030 	ldr.w	r9, [lr, r0, lsl #3]
			index_jmp = index - info->index;
    6738:	68a1      	ldr	r1, [r4, #8]
			index_jmp = (offs - info->start_offset) / info->size;
    673a:	6822      	ldr	r2, [r4, #0]
		info->size = layout->pages_size;
    673c:	f8c4 9004 	str.w	r9, [r4, #4]
		if (offs == 0) {
    6740:	b985      	cbnz	r5, 6764 <flash_get_page_info+0x68>
			index_jmp = index - info->index;
    6742:	1a73      	subs	r3, r6, r1
		index_jmp = MIN(index_jmp, layout->pages_count);
    6744:	f857 8030 	ldr.w	r8, [r7, r0, lsl #3]
    6748:	4543      	cmp	r3, r8
    674a:	bf28      	it	cs
    674c:	4643      	movcs	r3, r8
		info->start_offset += (index_jmp * info->size);
    674e:	fb03 2209 	mla	r2, r3, r9, r2
		info->index += index_jmp;
    6752:	4419      	add	r1, r3
		if (index_jmp < layout->pages_count) {
    6754:	4598      	cmp	r8, r3
		info->start_offset += (index_jmp * info->size);
    6756:	6022      	str	r2, [r4, #0]
		info->index += index_jmp;
    6758:	60a1      	str	r1, [r4, #8]
		if (index_jmp < layout->pages_count) {
    675a:	f100 0001 	add.w	r0, r0, #1
    675e:	d9e2      	bls.n	6726 <flash_get_page_info+0x2a>
			return 0;
    6760:	2000      	movs	r0, #0
    6762:	e7e4      	b.n	672e <flash_get_page_info+0x32>
			index_jmp = (offs - info->start_offset) / info->size;
    6764:	1aab      	subs	r3, r5, r2
    6766:	fbb3 f3f9 	udiv	r3, r3, r9
    676a:	e7eb      	b.n	6744 <flash_get_page_info+0x48>

0000676c <z_impl_flash_get_page_info_by_offs>:

int z_impl_flash_get_page_info_by_offs(const struct device *dev, off_t offs,
				       struct flash_pages_info *info)
{
    676c:	4613      	mov	r3, r2
	return flash_get_page_info(dev, offs, 0U, info);
    676e:	2200      	movs	r2, #0
    6770:	f7ff bfc4 	b.w	66fc <flash_get_page_info>

00006774 <flash_page_foreach>:
	return count;
}

void flash_page_foreach(const struct device *dev, flash_page_cb cb,
			void *data)
{
    6774:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	const struct flash_pages_layout *layout;
	struct flash_pages_info page_info;
	size_t block, num_blocks, page = 0, i;
	off_t off = 0;

	api->page_layout(dev, &layout, &num_blocks);
    6778:	6883      	ldr	r3, [r0, #8]
{
    677a:	b086      	sub	sp, #24
	api->page_layout(dev, &layout, &num_blocks);
    677c:	691b      	ldr	r3, [r3, #16]
{
    677e:	4688      	mov	r8, r1
    6780:	4691      	mov	r9, r2
	api->page_layout(dev, &layout, &num_blocks);
    6782:	a901      	add	r1, sp, #4
    6784:	aa02      	add	r2, sp, #8
    6786:	4798      	blx	r3
	off_t off = 0;
    6788:	2400      	movs	r4, #0
	size_t block, num_blocks, page = 0, i;
    678a:	46a2      	mov	sl, r4

	for (block = 0; block < num_blocks; block++) {
    678c:	4625      	mov	r5, r4
    678e:	9b02      	ldr	r3, [sp, #8]
    6790:	42ab      	cmp	r3, r5
    6792:	d802      	bhi.n	679a <flash_page_foreach+0x26>

			off += page_info.size;
			page++;
		}
	}
}
    6794:	b006      	add	sp, #24
    6796:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		const struct flash_pages_layout *l = &layout[block];
    679a:	9f01      	ldr	r7, [sp, #4]
    679c:	eb07 07c5 	add.w	r7, r7, r5, lsl #3
		for (i = 0; i < l->pages_count; i++) {
    67a0:	2600      	movs	r6, #0
		page_info.size = l->pages_size;
    67a2:	687b      	ldr	r3, [r7, #4]
    67a4:	9304      	str	r3, [sp, #16]
		for (i = 0; i < l->pages_count; i++) {
    67a6:	683a      	ldr	r2, [r7, #0]
    67a8:	42b2      	cmp	r2, r6
    67aa:	eb0a 0306 	add.w	r3, sl, r6
    67ae:	d802      	bhi.n	67b6 <flash_page_foreach+0x42>
	for (block = 0; block < num_blocks; block++) {
    67b0:	3501      	adds	r5, #1
    67b2:	469a      	mov	sl, r3
    67b4:	e7eb      	b.n	678e <flash_page_foreach+0x1a>
			if (!cb(&page_info, data)) {
    67b6:	4649      	mov	r1, r9
    67b8:	a803      	add	r0, sp, #12
			page_info.start_offset = off;
    67ba:	9403      	str	r4, [sp, #12]
			page_info.index = page;
    67bc:	9305      	str	r3, [sp, #20]
			if (!cb(&page_info, data)) {
    67be:	47c0      	blx	r8
    67c0:	2800      	cmp	r0, #0
    67c2:	d0e7      	beq.n	6794 <flash_page_foreach+0x20>
			off += page_info.size;
    67c4:	9b04      	ldr	r3, [sp, #16]
		for (i = 0; i < l->pages_count; i++) {
    67c6:	3601      	adds	r6, #1
			off += page_info.size;
    67c8:	441c      	add	r4, r3
		for (i = 0; i < l->pages_count; i++) {
    67ca:	e7ec      	b.n	67a6 <flash_page_foreach+0x32>

000067cc <uarte_nrfx_config_get>:
	*cfg = data->uart_config;
    67cc:	6902      	ldr	r2, [r0, #16]
{
    67ce:	460b      	mov	r3, r1
	*cfg = data->uart_config;
    67d0:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    67d4:	e883 0003 	stmia.w	r3, {r0, r1}
}
    67d8:	2000      	movs	r0, #0
    67da:	4770      	bx	lr

000067dc <uarte_nrfx_err_check>:
	return config->uarte_regs;
    67dc:	6843      	ldr	r3, [r0, #4]
    67de:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    67e0:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    67e4:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    67e8:	4770      	bx	lr

000067ea <uarte_nrfx_poll_in>:
	return config->uarte_regs;
    67ea:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = dev->data;
    67ec:	6902      	ldr	r2, [r0, #16]
	return config->uarte_regs;
    67ee:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    67f0:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    67f4:	b148      	cbz	r0, 680a <uarte_nrfx_poll_in+0x20>
	*c = data->rx_data;
    67f6:	7d52      	ldrb	r2, [r2, #21]
    67f8:	700a      	strb	r2, [r1, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    67fa:	2000      	movs	r0, #0
    67fc:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    6800:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6804:	2201      	movs	r2, #1
    6806:	601a      	str	r2, [r3, #0]
	return 0;
    6808:	4770      	bx	lr
		return -1;
    680a:	f04f 30ff 	mov.w	r0, #4294967295
}
    680e:	4770      	bx	lr

00006810 <uarte_nrfx_fifo_read>:
	if (size > 0 && nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    6810:	2a00      	cmp	r2, #0
{
    6812:	b510      	push	{r4, lr}
    6814:	4604      	mov	r4, r0
	if (size > 0 && nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    6816:	dd0f      	ble.n	6838 <uarte_nrfx_fifo_read+0x28>
	return config->uarte_regs;
    6818:	6843      	ldr	r3, [r0, #4]
    681a:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    681c:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (size > 0 && nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    6820:	b148      	cbz	r0, 6836 <uarte_nrfx_fifo_read+0x26>
	const struct uarte_nrfx_data *data = dev->data;
    6822:	6922      	ldr	r2, [r4, #16]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6824:	2000      	movs	r0, #0
    6826:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    682a:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
		rx_data[num_rx++] = (uint8_t)data->rx_data;
    682e:	7d52      	ldrb	r2, [r2, #21]
    6830:	700a      	strb	r2, [r1, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6832:	2001      	movs	r0, #1
    6834:	6018      	str	r0, [r3, #0]
}
    6836:	bd10      	pop	{r4, pc}
	int num_rx = 0;
    6838:	2000      	movs	r0, #0
    683a:	e7fc      	b.n	6836 <uarte_nrfx_fifo_read+0x26>

0000683c <uarte_nrfx_irq_tx_enable>:
	return config->uarte_regs;
    683c:	6843      	ldr	r3, [r0, #4]
	struct uarte_nrfx_data *data = dev->data;
    683e:	6901      	ldr	r1, [r0, #16]
	return config->uarte_regs;
    6840:	681a      	ldr	r2, [r3, #0]
	__asm__ volatile(
    6842:	f04f 0020 	mov.w	r0, #32
    6846:	f3ef 8311 	mrs	r3, BASEPRI
    684a:	f380 8812 	msr	BASEPRI_MAX, r0
    684e:	f3bf 8f6f 	isb	sy
	data->int_driven->disable_tx_irq = false;
    6852:	68c9      	ldr	r1, [r1, #12]
    6854:	2000      	movs	r0, #0
    6856:	7388      	strb	r0, [r1, #14]
    p_reg->INTENSET = mask;
    6858:	f44f 0180 	mov.w	r1, #4194304	; 0x400000
    685c:	f8c2 1304 	str.w	r1, [r2, #772]	; 0x304
	__asm__ volatile(
    6860:	f383 8811 	msr	BASEPRI, r3
    6864:	f3bf 8f6f 	isb	sy
}
    6868:	4770      	bx	lr

0000686a <uarte_nrfx_irq_tx_disable>:
	data->int_driven->disable_tx_irq = true;
    686a:	6903      	ldr	r3, [r0, #16]
    686c:	68db      	ldr	r3, [r3, #12]
    686e:	2201      	movs	r2, #1
    6870:	739a      	strb	r2, [r3, #14]
}
    6872:	4770      	bx	lr

00006874 <uarte_nrfx_irq_tx_ready_complete>:
	bool ready = !data->int_driven->disable_tx_irq &&
    6874:	6903      	ldr	r3, [r0, #16]
    6876:	68db      	ldr	r3, [r3, #12]
    6878:	7b9a      	ldrb	r2, [r3, #14]
		     nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) &&
    687a:	f002 01ff 	and.w	r1, r2, #255	; 0xff
    687e:	b962      	cbnz	r2, 689a <uarte_nrfx_irq_tx_ready_complete+0x26>
	return config->uarte_regs;
    6880:	6842      	ldr	r2, [r0, #4]
    6882:	6812      	ldr	r2, [r2, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6884:	f8d2 0158 	ldr.w	r0, [r2, #344]	; 0x158
	bool ready = !data->int_driven->disable_tx_irq &&
    6888:	b140      	cbz	r0, 689c <uarte_nrfx_irq_tx_ready_complete+0x28>
    return p_reg->INTENSET & mask;
    688a:	f8d2 0304 	ldr.w	r0, [r2, #772]	; 0x304
	if (ready) {
    688e:	f410 0080 	ands.w	r0, r0, #4194304	; 0x400000
    6892:	d003      	beq.n	689c <uarte_nrfx_irq_tx_ready_complete+0x28>
		data->int_driven->fifo_fill_lock = 0;
    6894:	6119      	str	r1, [r3, #16]
		     nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) &&
    6896:	2001      	movs	r0, #1
    6898:	4770      	bx	lr
    689a:	2000      	movs	r0, #0
}
    689c:	4770      	bx	lr

0000689e <uarte_nrfx_irq_rx_ready>:
	return config->uarte_regs;
    689e:	6843      	ldr	r3, [r0, #4]
    68a0:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    68a2:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
}
    68a6:	3800      	subs	r0, #0
    68a8:	bf18      	it	ne
    68aa:	2001      	movne	r0, #1
    68ac:	4770      	bx	lr

000068ae <uarte_nrfx_irq_rx_enable>:
	return config->uarte_regs;
    68ae:	6843      	ldr	r3, [r0, #4]
    68b0:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    68b2:	2210      	movs	r2, #16
    68b4:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    68b8:	4770      	bx	lr

000068ba <uarte_nrfx_irq_rx_disable>:
	return config->uarte_regs;
    68ba:	6843      	ldr	r3, [r0, #4]
    68bc:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    68be:	2210      	movs	r2, #16
    68c0:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
    68c4:	4770      	bx	lr

000068c6 <uarte_nrfx_irq_err_enable>:
	return config->uarte_regs;
    68c6:	6843      	ldr	r3, [r0, #4]
    68c8:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    68ca:	f44f 7200 	mov.w	r2, #512	; 0x200
    68ce:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    68d2:	4770      	bx	lr

000068d4 <uarte_nrfx_irq_err_disable>:
	return config->uarte_regs;
    68d4:	6843      	ldr	r3, [r0, #4]
    68d6:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    68d8:	f44f 7200 	mov.w	r2, #512	; 0x200
    68dc:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
    68e0:	4770      	bx	lr

000068e2 <uarte_nrfx_irq_update>:
}
    68e2:	2001      	movs	r0, #1
    68e4:	4770      	bx	lr

000068e6 <uarte_nrfx_irq_callback_set>:
	data->int_driven->cb = cb;
    68e6:	6903      	ldr	r3, [r0, #16]
    68e8:	68db      	ldr	r3, [r3, #12]
	data->int_driven->cb_data = cb_data;
    68ea:	e9c3 1200 	strd	r1, r2, [r3]
}
    68ee:	4770      	bx	lr

000068f0 <uarte_nrfx_irq_is_pending>:
{
    68f0:	b538      	push	{r3, r4, r5, lr}
	return config->uarte_regs;
    68f2:	6843      	ldr	r3, [r0, #4]
    68f4:	681d      	ldr	r5, [r3, #0]
    return p_reg->INTENSET & mask;
    68f6:	f8d5 3304 	ldr.w	r3, [r5, #772]	; 0x304
		||
    68fa:	025b      	lsls	r3, r3, #9
{
    68fc:	4604      	mov	r4, r0
		||
    68fe:	d405      	bmi.n	690c <uarte_nrfx_irq_is_pending+0x1c>
    6900:	f8d5 0304 	ldr.w	r0, [r5, #772]	; 0x304
    6904:	f010 0010 	ands.w	r0, r0, #16
    6908:	d106      	bne.n	6918 <uarte_nrfx_irq_is_pending+0x28>
}
    690a:	bd38      	pop	{r3, r4, r5, pc}
		 uarte_nrfx_irq_tx_ready_complete(dev))
    690c:	f7ff ffb2 	bl	6874 <uarte_nrfx_irq_tx_ready_complete>
					    NRF_UARTE_INT_TXSTOPPED_MASK) &&
    6910:	2800      	cmp	r0, #0
    6912:	d0f5      	beq.n	6900 <uarte_nrfx_irq_is_pending+0x10>
		||
    6914:	2001      	movs	r0, #1
    6916:	e7f8      	b.n	690a <uarte_nrfx_irq_is_pending+0x1a>
		 uarte_nrfx_irq_rx_ready(dev)));
    6918:	4620      	mov	r0, r4
    691a:	f7ff ffc0 	bl	689e <uarte_nrfx_irq_rx_ready>
					    NRF_UARTE_INT_ENDRX_MASK) &&
    691e:	3800      	subs	r0, #0
    6920:	bf18      	it	ne
    6922:	2001      	movne	r0, #1
    6924:	e7f1      	b.n	690a <uarte_nrfx_irq_is_pending+0x1a>

00006926 <tx_start.isra.0>:
	return config->uarte_regs;
    6926:	6803      	ldr	r3, [r0, #0]
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    6928:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    692c:	f8c3 2548 	str.w	r2, [r3, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6930:	2200      	movs	r2, #0
    6932:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    6936:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    693a:	f8c3 2158 	str.w	r2, [r3, #344]	; 0x158
    693e:	f8d3 2158 	ldr.w	r2, [r3, #344]	; 0x158
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    6942:	6842      	ldr	r2, [r0, #4]
    6944:	06d2      	lsls	r2, r2, #27
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    6946:	bf41      	itttt	mi
    6948:	2208      	movmi	r2, #8
    694a:	f8c3 2500 	strmi.w	r2, [r3, #1280]	; 0x500
    p_reg->INTENSET = mask;
    694e:	f44f 0280 	movmi.w	r2, #4194304	; 0x400000
    6952:	f8c3 2304 	strmi.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6956:	2201      	movs	r2, #1
    6958:	609a      	str	r2, [r3, #8]
}
    695a:	4770      	bx	lr

0000695c <is_tx_ready.isra.0>:
	return config->uarte_regs;
    695c:	6802      	ldr	r2, [r0, #0]
static bool is_tx_ready(const struct device *dev)
    695e:	4603      	mov	r3, r0
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6960:	f8d2 0158 	ldr.w	r0, [r2, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    6964:	b940      	cbnz	r0, 6978 <is_tx_ready.isra.0+0x1c>
	bool ppi_endtx = config->flags & UARTE_CFG_FLAG_PPI_ENDTX;
    6966:	685b      	ldr	r3, [r3, #4]
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    6968:	079b      	lsls	r3, r3, #30
    696a:	d406      	bmi.n	697a <is_tx_ready.isra.0+0x1e>
    696c:	f8d2 0120 	ldr.w	r0, [r2, #288]	; 0x120
    6970:	3800      	subs	r0, #0
    6972:	bf18      	it	ne
    6974:	2001      	movne	r0, #1
    6976:	4770      	bx	lr
    6978:	2001      	movs	r0, #1
}
    697a:	4770      	bx	lr

0000697c <uarte_nrfx_fifo_fill>:
{
    697c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	struct uarte_nrfx_data *data = dev->data;
    697e:	6906      	ldr	r6, [r0, #16]
	len = MIN(len, data->int_driven->tx_buff_size);
    6980:	68f3      	ldr	r3, [r6, #12]
    6982:	899c      	ldrh	r4, [r3, #12]
    6984:	f3bf 8f5b 	dmb	ish
    6988:	4294      	cmp	r4, r2
    698a:	bfa8      	it	ge
    698c:	4614      	movge	r4, r2
{
    698e:	4605      	mov	r5, r0
    6990:	3310      	adds	r3, #16
    6992:	2201      	movs	r2, #1
    6994:	e853 0f00 	ldrex	r0, [r3]
    6998:	2800      	cmp	r0, #0
    699a:	d103      	bne.n	69a4 <uarte_nrfx_fifo_fill+0x28>
    699c:	e843 2700 	strex	r7, r2, [r3]
    69a0:	2f00      	cmp	r7, #0
    69a2:	d1f7      	bne.n	6994 <uarte_nrfx_fifo_fill+0x18>
    69a4:	f3bf 8f5b 	dmb	ish
    69a8:	bf0c      	ite	eq
    69aa:	4613      	moveq	r3, r2
    69ac:	2300      	movne	r3, #0
	if (!atomic_cas(&data->int_driven->fifo_fill_lock, 0, 1)) {
    69ae:	d01d      	beq.n	69ec <uarte_nrfx_fifo_fill+0x70>
		return 0;
    69b0:	461c      	mov	r4, r3
}
    69b2:	4620      	mov	r0, r4
    69b4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		data->int_driven->tx_buffer[i] = tx_data[i];
    69b6:	68f2      	ldr	r2, [r6, #12]
    69b8:	5cc8      	ldrb	r0, [r1, r3]
    69ba:	6892      	ldr	r2, [r2, #8]
    69bc:	54d0      	strb	r0, [r2, r3]
	for (int i = 0; i < len; i++) {
    69be:	3301      	adds	r3, #1
    69c0:	42a3      	cmp	r3, r4
    69c2:	dbf8      	blt.n	69b6 <uarte_nrfx_fifo_fill+0x3a>
	__asm__ volatile(
    69c4:	f04f 0320 	mov.w	r3, #32
    69c8:	f3ef 8711 	mrs	r7, BASEPRI
    69cc:	f383 8812 	msr	BASEPRI_MAX, r3
    69d0:	f3bf 8f6f 	isb	sy
	if (!is_tx_ready(dev)) {
    69d4:	6868      	ldr	r0, [r5, #4]
    69d6:	f7ff ffc1 	bl	695c <is_tx_ready.isra.0>
    69da:	68f3      	ldr	r3, [r6, #12]
    69dc:	b940      	cbnz	r0, 69f0 <uarte_nrfx_fifo_fill+0x74>
		data->int_driven->fifo_fill_lock = 0;
    69de:	6118      	str	r0, [r3, #16]
		len = 0;
    69e0:	4604      	mov	r4, r0
	__asm__ volatile(
    69e2:	f387 8811 	msr	BASEPRI, r7
    69e6:	f3bf 8f6f 	isb	sy
	return len;
    69ea:	e7e2      	b.n	69b2 <uarte_nrfx_fifo_fill+0x36>
	for (int i = 0; i < len; i++) {
    69ec:	2300      	movs	r3, #0
    69ee:	e7e7      	b.n	69c0 <uarte_nrfx_fifo_fill+0x44>
		tx_start(dev, data->int_driven->tx_buffer, len);
    69f0:	6899      	ldr	r1, [r3, #8]
    69f2:	6868      	ldr	r0, [r5, #4]
    69f4:	4622      	mov	r2, r4
    69f6:	f7ff ff96 	bl	6926 <tx_start.isra.0>
    69fa:	e7f2      	b.n	69e2 <uarte_nrfx_fifo_fill+0x66>

000069fc <uarte_nrfx_isr_int>:
	const struct uarte_nrfx_config *config = dev->config;
    69fc:	6842      	ldr	r2, [r0, #4]
	return config->uarte_regs;
    69fe:	6813      	ldr	r3, [r2, #0]
    return p_reg->INTENSET & mask;
    6a00:	f8d3 1304 	ldr.w	r1, [r3, #772]	; 0x304
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
    6a04:	05c9      	lsls	r1, r1, #23
{
    6a06:	b410      	push	{r4}
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
    6a08:	d518      	bpl.n	6a3c <uarte_nrfx_isr_int+0x40>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6a0a:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    6a0e:	b1a9      	cbz	r1, 6a3c <uarte_nrfx_isr_int+0x40>
	__asm__ volatile(
    6a10:	f04f 0420 	mov.w	r4, #32
    6a14:	f3ef 8111 	mrs	r1, BASEPRI
    6a18:	f384 8812 	msr	BASEPRI_MAX, r4
    6a1c:	f3bf 8f6f 	isb	sy
    6a20:	f8d3 4120 	ldr.w	r4, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
    6a24:	b134      	cbz	r4, 6a34 <uarte_nrfx_isr_int+0x38>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6a26:	2400      	movs	r4, #0
    6a28:	f8c3 4120 	str.w	r4, [r3, #288]	; 0x120
    6a2c:	f8d3 4120 	ldr.w	r4, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6a30:	2401      	movs	r4, #1
    6a32:	60dc      	str	r4, [r3, #12]
	__asm__ volatile(
    6a34:	f381 8811 	msr	BASEPRI, r1
    6a38:	f3bf 8f6f 	isb	sy
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    6a3c:	6852      	ldr	r2, [r2, #4]
    6a3e:	06d2      	lsls	r2, r2, #27
    6a40:	d51a      	bpl.n	6a78 <uarte_nrfx_isr_int+0x7c>
	__asm__ volatile(
    6a42:	f04f 0220 	mov.w	r2, #32
    6a46:	f3ef 8111 	mrs	r1, BASEPRI
    6a4a:	f382 8812 	msr	BASEPRI_MAX, r2
    6a4e:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6a52:	f8d3 2158 	ldr.w	r2, [r3, #344]	; 0x158
		if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
    6a56:	b112      	cbz	r2, 6a5e <uarte_nrfx_isr_int+0x62>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    6a58:	2200      	movs	r2, #0
    6a5a:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
		if (!data->int_driven || data->int_driven->fifo_fill_lock == 0)
    6a5e:	6902      	ldr	r2, [r0, #16]
    6a60:	68d2      	ldr	r2, [r2, #12]
    6a62:	b10a      	cbz	r2, 6a68 <uarte_nrfx_isr_int+0x6c>
    6a64:	6912      	ldr	r2, [r2, #16]
    6a66:	b91a      	cbnz	r2, 6a70 <uarte_nrfx_isr_int+0x74>
    p_reg->INTENCLR = mask;
    6a68:	f44f 0280 	mov.w	r2, #4194304	; 0x400000
    6a6c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
	__asm__ volatile(
    6a70:	f381 8811 	msr	BASEPRI, r1
    6a74:	f3bf 8f6f 	isb	sy
	if (!data->int_driven) {
    6a78:	6902      	ldr	r2, [r0, #16]
    6a7a:	68d2      	ldr	r2, [r2, #12]
    6a7c:	b15a      	cbz	r2, 6a96 <uarte_nrfx_isr_int+0x9a>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6a7e:	f8d3 1158 	ldr.w	r1, [r3, #344]	; 0x158
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
    6a82:	b151      	cbz	r1, 6a9a <uarte_nrfx_isr_int+0x9e>
		if (data->int_driven->disable_tx_irq) {
    6a84:	7b94      	ldrb	r4, [r2, #14]
		data->int_driven->fifo_fill_lock = 0;
    6a86:	2100      	movs	r1, #0
    6a88:	6111      	str	r1, [r2, #16]
		if (data->int_driven->disable_tx_irq) {
    6a8a:	b134      	cbz	r4, 6a9a <uarte_nrfx_isr_int+0x9e>
    p_reg->INTENCLR = mask;
    6a8c:	f44f 0080 	mov.w	r0, #4194304	; 0x400000
    6a90:	f8c3 0308 	str.w	r0, [r3, #776]	; 0x308
			data->int_driven->disable_tx_irq = false;
    6a94:	7391      	strb	r1, [r2, #14]
}
    6a96:	bc10      	pop	{r4}
    6a98:	4770      	bx	lr
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6a9a:	f8d3 1124 	ldr.w	r1, [r3, #292]	; 0x124
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ERROR)) {
    6a9e:	b121      	cbz	r1, 6aaa <uarte_nrfx_isr_int+0xae>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6aa0:	2100      	movs	r1, #0
    6aa2:	f8c3 1124 	str.w	r1, [r3, #292]	; 0x124
    6aa6:	f8d3 3124 	ldr.w	r3, [r3, #292]	; 0x124
	if (data->int_driven->cb) {
    6aaa:	6813      	ldr	r3, [r2, #0]
    6aac:	2b00      	cmp	r3, #0
    6aae:	d0f2      	beq.n	6a96 <uarte_nrfx_isr_int+0x9a>
		data->int_driven->cb(dev, data->int_driven->cb_data);
    6ab0:	6851      	ldr	r1, [r2, #4]
}
    6ab2:	bc10      	pop	{r4}
		data->int_driven->cb(dev, data->int_driven->cb_data);
    6ab4:	4718      	bx	r3

00006ab6 <pinctrl_lookup_state>:

#include <drivers/pinctrl.h>

int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
			 const struct pinctrl_state **state)
{
    6ab6:	b530      	push	{r4, r5, lr}
	*state = &config->states[0];
    6ab8:	6843      	ldr	r3, [r0, #4]
    6aba:	6013      	str	r3, [r2, #0]
	while (*state <= &config->states[config->state_cnt - 1U]) {
    6abc:	7a03      	ldrb	r3, [r0, #8]
    6abe:	f103 5300 	add.w	r3, r3, #536870912	; 0x20000000
    6ac2:	3b01      	subs	r3, #1
    6ac4:	00db      	lsls	r3, r3, #3
    6ac6:	6845      	ldr	r5, [r0, #4]
    6ac8:	6814      	ldr	r4, [r2, #0]
    6aca:	441d      	add	r5, r3
    6acc:	42ac      	cmp	r4, r5
    6ace:	d902      	bls.n	6ad6 <pinctrl_lookup_state+0x20>
		}

		(*state)++;
	}

	return -ENOENT;
    6ad0:	f06f 0001 	mvn.w	r0, #1
}
    6ad4:	bd30      	pop	{r4, r5, pc}
		if (id == (*state)->id) {
    6ad6:	7965      	ldrb	r5, [r4, #5]
    6ad8:	428d      	cmp	r5, r1
    6ada:	d002      	beq.n	6ae2 <pinctrl_lookup_state+0x2c>
		(*state)++;
    6adc:	3408      	adds	r4, #8
    6ade:	6014      	str	r4, [r2, #0]
    6ae0:	e7f1      	b.n	6ac6 <pinctrl_lookup_state+0x10>
			return 0;
    6ae2:	2000      	movs	r0, #0
    6ae4:	e7f6      	b.n	6ad4 <pinctrl_lookup_state+0x1e>

00006ae6 <nrf_gpio_pin_write>:
    *p_pin = pin_number & 0x1F;
    6ae6:	f000 031f 	and.w	r3, r0, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    6aea:	2001      	movs	r0, #1
    6aec:	4098      	lsls	r0, r3
    6aee:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    if (value == 0)
    6af2:	b911      	cbnz	r1, 6afa <nrf_gpio_pin_write+0x14>
    p_reg->OUTCLR = clr_mask;
    6af4:	f8c3 050c 	str.w	r0, [r3, #1292]	; 0x50c
}
    6af8:	4770      	bx	lr
    p_reg->OUTSET = set_mask;
    6afa:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
}
    6afe:	4770      	bx	lr

00006b00 <nrf_pin_configure>:
__unused static void nrf_pin_configure(pinctrl_soc_pin_t pin,
				       nrf_gpio_pin_dir_t dir,
				       nrf_gpio_pin_input_t input)
{
	/* force input direction and disconnected buffer for low power */
	if (NRF_GET_LP(pin) == NRF_LP_ENABLE) {
    6b00:	f400 5380 	and.w	r3, r0, #4096	; 0x1000
		dir = NRF_GPIO_PIN_DIR_INPUT;
		input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    6b04:	2b00      	cmp	r3, #0
{
    6b06:	b510      	push	{r4, lr}
    *p_pin = pin_number & 0x1F;
    6b08:	f000 031f 	and.w	r3, r0, #31
		input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    6b0c:	bf08      	it	eq
    6b0e:	4614      	moveq	r4, r2
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    6b10:	f3c0 1281 	ubfx	r2, r0, #6, #2
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    6b14:	f400 6070 	and.w	r0, r0, #3840	; 0xf00
    6b18:	bf18      	it	ne
    6b1a:	2100      	movne	r1, #0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    6b1c:	ea40 0282 	orr.w	r2, r0, r2, lsl #2
    6b20:	ea42 0201 	orr.w	r2, r2, r1
    6b24:	bf18      	it	ne
    6b26:	2401      	movne	r4, #1
    reg->PIN_CNF[pin_number] = cnf;
    6b28:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    6b2c:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    6b30:	ea42 0244 	orr.w	r2, r2, r4, lsl #1
    reg->PIN_CNF[pin_number] = cnf;
    6b34:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
	}

	nrf_gpio_cfg(NRF_GET_PIN(pin), dir, input, NRF_GET_PULL(pin),
		     NRF_GET_DRIVE(pin), NRF_GPIO_PIN_NOSENSE);
}
    6b38:	bd10      	pop	{r4, pc}

00006b3a <pinctrl_configure_pins>:

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
			   uintptr_t reg)
{
    6b3a:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6b3e:	4614      	mov	r4, r2
    6b40:	4680      	mov	r8, r0
    6b42:	eb00 0781 	add.w	r7, r0, r1, lsl #2
			break;
		case NRF_FUN_PWM_OUT3:
			NRF_PSEL_PWM(reg, OUT[3]) = NRF_GET_PIN(pins[i]);
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
					   NRF_GET_INVERT(pins[i]));
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    6b46:	2501      	movs	r5, #1
    p_reg->OUTCLR = clr_mask;
    6b48:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    6b4c:	45b8      	cmp	r8, r7
    6b4e:	d102      	bne.n	6b56 <pinctrl_configure_pins+0x1c>
		default:
			return -ENOTSUP;
		}
	}

	return 0;
    6b50:	2000      	movs	r0, #0
}
    6b52:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		switch (NRF_GET_FUN(pins[i])) {
    6b56:	f8d8 3000 	ldr.w	r3, [r8]
    6b5a:	0c1a      	lsrs	r2, r3, #16
    6b5c:	2a19      	cmp	r2, #25
    6b5e:	d875      	bhi.n	6c4c <pinctrl_configure_pins+0x112>
    6b60:	e8df f002 	tbb	[pc, r2]
    6b64:	49221b0d 	.word	0x49221b0d
    6b68:	74493c27 	.word	0x74493c27
    6b6c:	4e747474 	.word	0x4e747474
    6b70:	74747453 	.word	0x74747453
    6b74:	74747474 	.word	0x74747474
    6b78:	65587474 	.word	0x65587474
    6b7c:	6f6a      	.short	0x6f6a
			NRF_PSEL_UART(reg, TXD) = NRF_GET_PIN(pins[i]);
    6b7e:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6b82:	f8c4 350c 	str.w	r3, [r4, #1292]	; 0x50c
    *p_pin = pin_number & 0x1F;
    6b86:	f8d8 3000 	ldr.w	r3, [r8]
    6b8a:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    6b8e:	fa05 f303 	lsl.w	r3, r5, r3
    p_reg->OUTSET = set_mask;
    6b92:	f8c6 3508 	str.w	r3, [r6, #1288]	; 0x508
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    6b96:	2201      	movs	r2, #1
    6b98:	e004      	b.n	6ba4 <pinctrl_configure_pins+0x6a>
			NRF_PSEL_UART(reg, RXD) = NRF_GET_PIN(pins[i]);
    6b9a:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6b9e:	f8c4 3514 	str.w	r3, [r4, #1300]	; 0x514
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    6ba2:	2200      	movs	r2, #0
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    6ba4:	4611      	mov	r1, r2
    6ba6:	e012      	b.n	6bce <pinctrl_configure_pins+0x94>
			NRF_PSEL_UART(reg, RTS) = NRF_GET_PIN(pins[i]);
    6ba8:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6bac:	f8c4 3508 	str.w	r3, [r4, #1288]	; 0x508
    6bb0:	e7e9      	b.n	6b86 <pinctrl_configure_pins+0x4c>
			NRF_PSEL_SPIM(reg, SCK) = NRF_GET_PIN(pins[i]);
    6bb2:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6bb6:	f8c4 3508 	str.w	r3, [r4, #1288]	; 0x508
    *p_pin = pin_number & 0x1F;
    6bba:	f8d8 3000 	ldr.w	r3, [r8]
    6bbe:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    6bc2:	fa05 f303 	lsl.w	r3, r5, r3
    p_reg->OUTCLR = clr_mask;
    6bc6:	f8c6 350c 	str.w	r3, [r6, #1292]	; 0x50c
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    6bca:	2200      	movs	r2, #0
    6bcc:	2101      	movs	r1, #1
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    6bce:	f8d8 0000 	ldr.w	r0, [r8]
    6bd2:	f7ff ff95 	bl	6b00 <nrf_pin_configure>
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    6bd6:	f108 0804 	add.w	r8, r8, #4
    6bda:	e7b7      	b.n	6b4c <pinctrl_configure_pins+0x12>
			NRF_PSEL_SPIM(reg, MOSI) = NRF_GET_PIN(pins[i]);
    6bdc:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6be0:	f8c4 350c 	str.w	r3, [r4, #1292]	; 0x50c
    *p_pin = pin_number & 0x1F;
    6be4:	f8d8 3000 	ldr.w	r3, [r8]
    6be8:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    6bec:	fa05 f303 	lsl.w	r3, r5, r3
    p_reg->OUTCLR = clr_mask;
    6bf0:	f8c6 350c 	str.w	r3, [r6, #1292]	; 0x50c
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    6bf4:	e7cf      	b.n	6b96 <pinctrl_configure_pins+0x5c>
			NRF_PSEL_SPIM(reg, MISO) = NRF_GET_PIN(pins[i]);
    6bf6:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6bfa:	f8c4 3510 	str.w	r3, [r4, #1296]	; 0x510
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    6bfe:	e7d0      	b.n	6ba2 <pinctrl_configure_pins+0x68>
			NRF_PSEL_TWIM(reg, SCL) = NRF_GET_PIN(pins[i]);
    6c00:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6c04:	f8c4 3508 	str.w	r3, [r4, #1288]	; 0x508
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    6c08:	e7cb      	b.n	6ba2 <pinctrl_configure_pins+0x68>
			NRF_PSEL_TWIM(reg, SDA) = NRF_GET_PIN(pins[i]);
    6c0a:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6c0e:	f8c4 350c 	str.w	r3, [r4, #1292]	; 0x50c
    6c12:	e7c6      	b.n	6ba2 <pinctrl_configure_pins+0x68>
			NRF_PSEL_PWM(reg, OUT[0]) = NRF_GET_PIN(pins[i]);
    6c14:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6c18:	f8c4 3560 	str.w	r3, [r4, #1376]	; 0x560
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
    6c1c:	f8d8 0000 	ldr.w	r0, [r8]
    6c20:	f3c0 3140 	ubfx	r1, r0, #13, #1
    6c24:	f000 003f 	and.w	r0, r0, #63	; 0x3f
    6c28:	f7ff ff5d 	bl	6ae6 <nrf_gpio_pin_write>
    6c2c:	e7b3      	b.n	6b96 <pinctrl_configure_pins+0x5c>
			NRF_PSEL_PWM(reg, OUT[1]) = NRF_GET_PIN(pins[i]);
    6c2e:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6c32:	f8c4 3564 	str.w	r3, [r4, #1380]	; 0x564
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
    6c36:	e7f1      	b.n	6c1c <pinctrl_configure_pins+0xe2>
			NRF_PSEL_PWM(reg, OUT[2]) = NRF_GET_PIN(pins[i]);
    6c38:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6c3c:	f8c4 3568 	str.w	r3, [r4, #1384]	; 0x568
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
    6c40:	e7ec      	b.n	6c1c <pinctrl_configure_pins+0xe2>
			NRF_PSEL_PWM(reg, OUT[3]) = NRF_GET_PIN(pins[i]);
    6c42:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6c46:	f8c4 356c 	str.w	r3, [r4, #1388]	; 0x56c
    6c4a:	e7e7      	b.n	6c1c <pinctrl_configure_pins+0xe2>
		switch (NRF_GET_FUN(pins[i])) {
    6c4c:	f06f 0085 	mvn.w	r0, #133	; 0x85
    6c50:	e77f      	b.n	6b52 <pinctrl_configure_pins+0x18>

00006c52 <fprotect_area>:
#define ENABLE_IN_DEBUG false
#endif


int fprotect_area(uint32_t start, size_t length)
{
    6c52:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
}

NRF_STATIC_INLINE void nrf_bprot_nvm_protection_in_debug_set(NRF_BPROT_Type * p_reg,
                                                             bool             enable)
{
    p_reg->DISABLEINDEBUG =
    6c56:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    6c5a:	4604      	mov	r4, r0
    6c5c:	4688      	mov	r8, r1
    6c5e:	b085      	sub	sp, #20
    6c60:	2701      	movs	r7, #1
	uint32_t block_end   = (start + length) / BPROT_REGIONS_SIZE;
	uint32_t block_mask[BPROT_CONFIGS_NUM] = {0};

	BUILD_ASSERT(BPROT_REGIONS_SIZE == CONFIG_FPROTECT_BLOCK_SIZE);

	if ((start % BPROT_REGIONS_SIZE) ||
    6c62:	ea44 0408 	orr.w	r4, r4, r8
	uint32_t block_end   = (start + length) / BPROT_REGIONS_SIZE;
    6c66:	eb00 0901 	add.w	r9, r0, r1
    6c6a:	f8c3 7608 	str.w	r7, [r3, #1544]	; 0x608
	uint32_t block_start = start / BPROT_REGIONS_SIZE;
    6c6e:	0b05      	lsrs	r5, r0, #12
	uint32_t block_mask[BPROT_CONFIGS_NUM] = {0};
    6c70:	2210      	movs	r2, #16
    6c72:	2100      	movs	r1, #0
    6c74:	4668      	mov	r0, sp
	if ((start % BPROT_REGIONS_SIZE) ||
    6c76:	f3c4 040b 	ubfx	r4, r4, #0, #12
	uint32_t block_mask[BPROT_CONFIGS_NUM] = {0};
    6c7a:	f7ff fc42 	bl	6502 <memset>
	uint32_t block_end   = (start + length) / BPROT_REGIONS_SIZE;
    6c7e:	ea4f 3619 	mov.w	r6, r9, lsr #12
	if ((start % BPROT_REGIONS_SIZE) ||
    6c82:	b924      	cbnz	r4, 6c8e <fprotect_area+0x3c>
	    (length % BPROT_REGIONS_SIZE) ||
    6c84:	f5b9 2f01 	cmp.w	r9, #528384	; 0x81000
    6c88:	d201      	bcs.n	6c8e <fprotect_area+0x3c>
	    (block_end > BPROT_REGIONS_NUM) ||
    6c8a:	42b5      	cmp	r5, r6
    6c8c:	d910      	bls.n	6cb0 <fprotect_area+0x5e>
		/*
		 * start or length isn't aligned with a BPROT region,
		 * or attempting to protect an area that is invalid or outside
		 * flash.
		 */
		return -EINVAL;
    6c8e:	f06f 0015 	mvn.w	r0, #21
    6c92:	e01e      	b.n	6cd2 <fprotect_area+0x80>
	}

	for (uint32_t i = block_start; i < block_end; i++) {
		block_mask[i / BITS_PER_LONG] |= BIT(i % BITS_PER_LONG);
    6c94:	096a      	lsrs	r2, r5, #5
    6c96:	ab04      	add	r3, sp, #16
    6c98:	eb03 0282 	add.w	r2, r3, r2, lsl #2
    6c9c:	f005 031f 	and.w	r3, r5, #31
    6ca0:	f852 1c10 	ldr.w	r1, [r2, #-16]
    6ca4:	fa07 f303 	lsl.w	r3, r7, r3
    6ca8:	430b      	orrs	r3, r1
    6caa:	f842 3c10 	str.w	r3, [r2, #-16]
	for (uint32_t i = block_start; i < block_end; i++) {
    6cae:	3501      	adds	r5, #1
    6cb0:	42b5      	cmp	r5, r6
    6cb2:	d1ef      	bne.n	6c94 <fprotect_area+0x42>
            p_reg->CONFIG0 = block_mask;
    6cb4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    6cb8:	9a00      	ldr	r2, [sp, #0]
    6cba:	f8c3 2600 	str.w	r2, [r3, #1536]	; 0x600
	}

	for (uint32_t i = 0; i < BPROT_CONFIGS_NUM; i++) {
		PROTECT(NRF_BPROT, i, block_mask[i]);
    6cbe:	9a01      	ldr	r2, [sp, #4]
            p_reg->CONFIG1 = block_mask;
    6cc0:	f8c3 2604 	str.w	r2, [r3, #1540]	; 0x604
    6cc4:	9a02      	ldr	r2, [sp, #8]
            p_reg->CONFIG2 = block_mask;
    6cc6:	f8c3 2610 	str.w	r2, [r3, #1552]	; 0x610
    6cca:	9a03      	ldr	r2, [sp, #12]
            p_reg->CONFIG3 = block_mask;
    6ccc:	f8c3 2614 	str.w	r2, [r3, #1556]	; 0x614
	}

	return 0;
    6cd0:	2000      	movs	r0, #0
}
    6cd2:	b005      	add	sp, #20
    6cd4:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}

00006cd8 <bootutil_buffer_is_erased.part.0>:
bool bootutil_buffer_is_erased(const struct flash_area *area,
    6cd8:	b538      	push	{r3, r4, r5, lr}
    6cda:	460c      	mov	r4, r1
    6cdc:	4615      	mov	r5, r2
    6cde:	4425      	add	r5, r4
    erased_val = flash_area_erased_val(area);
    6ce0:	f7ff f913 	bl	5f0a <flash_area_erased_val>
    for (i = 0, u8b = (uint8_t *)buffer; i < len; i++) {
    6ce4:	4621      	mov	r1, r4
    6ce6:	42a9      	cmp	r1, r5
    6ce8:	d101      	bne.n	6cee <bootutil_buffer_is_erased.part.0+0x16>
    return true;
    6cea:	2001      	movs	r0, #1
}
    6cec:	bd38      	pop	{r3, r4, r5, pc}
        if (u8b[i] != erased_val) {
    6cee:	f811 3b01 	ldrb.w	r3, [r1], #1
    6cf2:	4298      	cmp	r0, r3
    6cf4:	d0f7      	beq.n	6ce6 <bootutil_buffer_is_erased.part.0+0xe>
            return false;
    6cf6:	2000      	movs	r0, #0
    6cf8:	e7f8      	b.n	6cec <bootutil_buffer_is_erased.part.0+0x14>

00006cfa <boot_swap_info_off>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    6cfa:	6880      	ldr	r0, [r0, #8]
    6cfc:	3818      	subs	r0, #24
    6cfe:	f020 0007 	bic.w	r0, r0, #7
}
    6d02:	3810      	subs	r0, #16
    6d04:	4770      	bx	lr

00006d06 <boot_magic_compatible_check>:
    switch (tbl_val) {
    6d06:	2804      	cmp	r0, #4
    6d08:	d009      	beq.n	6d1e <boot_magic_compatible_check+0x18>
    6d0a:	2805      	cmp	r0, #5
    6d0c:	d103      	bne.n	6d16 <boot_magic_compatible_check+0x10>
        return val != BOOT_MAGIC_GOOD;
    6d0e:	1e48      	subs	r0, r1, #1
    6d10:	bf18      	it	ne
    6d12:	2001      	movne	r0, #1
    6d14:	4770      	bx	lr
        return tbl_val == val;
    6d16:	1a43      	subs	r3, r0, r1
    6d18:	4258      	negs	r0, r3
    6d1a:	4158      	adcs	r0, r3
    6d1c:	4770      	bx	lr
    switch (tbl_val) {
    6d1e:	2001      	movs	r0, #1
}
    6d20:	4770      	bx	lr

00006d22 <bootutil_buffer_is_erased>:
    if (buffer == NULL || len == 0) {
    6d22:	b111      	cbz	r1, 6d2a <bootutil_buffer_is_erased+0x8>
    6d24:	b10a      	cbz	r2, 6d2a <bootutil_buffer_is_erased+0x8>
    6d26:	f7ff bfd7 	b.w	6cd8 <bootutil_buffer_is_erased.part.0>
}
    6d2a:	2000      	movs	r0, #0
    6d2c:	4770      	bx	lr

00006d2e <boot_read_flag>:
{
    6d2e:	b538      	push	{r3, r4, r5, lr}
    6d30:	460c      	mov	r4, r1
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    6d32:	2301      	movs	r3, #1
{
    6d34:	4611      	mov	r1, r2
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    6d36:	4622      	mov	r2, r4
{
    6d38:	4605      	mov	r5, r0
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    6d3a:	f7ff f88e 	bl	5e5a <flash_area_read>
    if (rc < 0) {
    6d3e:	2800      	cmp	r0, #0
    6d40:	db10      	blt.n	6d64 <boot_read_flag+0x36>
    if (bootutil_buffer_is_erased(fap, flag, sizeof *flag)) {
    6d42:	2201      	movs	r2, #1
    6d44:	4621      	mov	r1, r4
    6d46:	4628      	mov	r0, r5
    6d48:	f7ff ffeb 	bl	6d22 <bootutil_buffer_is_erased>
    6d4c:	b118      	cbz	r0, 6d56 <boot_read_flag+0x28>
        *flag = BOOT_FLAG_UNSET;
    6d4e:	2303      	movs	r3, #3
    6d50:	7023      	strb	r3, [r4, #0]
    return 0;
    6d52:	2000      	movs	r0, #0
}
    6d54:	bd38      	pop	{r3, r4, r5, pc}
    if (flag != BOOT_FLAG_SET) {
    6d56:	7823      	ldrb	r3, [r4, #0]
        return BOOT_FLAG_BAD;
    6d58:	2b01      	cmp	r3, #1
    6d5a:	bf0c      	ite	eq
    6d5c:	2301      	moveq	r3, #1
    6d5e:	2302      	movne	r3, #2
        *flag = boot_flag_decode(*flag);
    6d60:	7023      	strb	r3, [r4, #0]
    6d62:	e7f7      	b.n	6d54 <boot_read_flag+0x26>
        return BOOT_EFLASH;
    6d64:	2001      	movs	r0, #1
    6d66:	e7f5      	b.n	6d54 <boot_read_flag+0x26>

00006d68 <boot_write_trailer>:
{
    6d68:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    6d6c:	461d      	mov	r5, r3
    6d6e:	4606      	mov	r6, r0
    6d70:	460f      	mov	r7, r1
    6d72:	4690      	mov	r8, r2
    align = flash_area_align(fap);
    6d74:	f7ff f8c0 	bl	5ef8 <flash_area_align>
    align = ALIGN_UP(inlen, align);
    6d78:	1e6c      	subs	r4, r5, #1
    6d7a:	4404      	add	r4, r0
    6d7c:	4240      	negs	r0, r0
    6d7e:	4004      	ands	r4, r0
    if (align > BOOT_MAX_ALIGN) {
    6d80:	2c08      	cmp	r4, #8
    6d82:	d81a      	bhi.n	6dba <boot_write_trailer+0x52>
    erased_val = flash_area_erased_val(fap);
    6d84:	4630      	mov	r0, r6
    6d86:	f7ff f8c0 	bl	5f0a <flash_area_erased_val>
    memcpy(buf, inbuf, inlen);
    6d8a:	462a      	mov	r2, r5
    erased_val = flash_area_erased_val(fap);
    6d8c:	4681      	mov	r9, r0
    memcpy(buf, inbuf, inlen);
    6d8e:	4641      	mov	r1, r8
    6d90:	4668      	mov	r0, sp
    6d92:	f7ff fbab 	bl	64ec <memcpy>
    memset(&buf[inlen], erased_val, align - inlen);
    6d96:	1b62      	subs	r2, r4, r5
    6d98:	4649      	mov	r1, r9
    6d9a:	eb0d 0005 	add.w	r0, sp, r5
    6d9e:	f7ff fbb0 	bl	6502 <memset>
    rc = flash_area_write(fap, off, buf, align);
    6da2:	4623      	mov	r3, r4
    6da4:	466a      	mov	r2, sp
    6da6:	4639      	mov	r1, r7
    6da8:	4630      	mov	r0, r6
    6daa:	f7ff f872 	bl	5e92 <flash_area_write>
    if (rc != 0) {
    6dae:	3800      	subs	r0, #0
    6db0:	bf18      	it	ne
    6db2:	2001      	movne	r0, #1
}
    6db4:	b003      	add	sp, #12
    6db6:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
        return -1;
    6dba:	f04f 30ff 	mov.w	r0, #4294967295
    6dbe:	e7f9      	b.n	6db4 <boot_write_trailer+0x4c>

00006dc0 <boot_write_trailer_flag>:
{
    6dc0:	b507      	push	{r0, r1, r2, lr}
    return boot_write_trailer(fap, off, buf, 1);
    6dc2:	2301      	movs	r3, #1
    const uint8_t buf[1] = { flag_val };
    6dc4:	f88d 2004 	strb.w	r2, [sp, #4]
    return boot_write_trailer(fap, off, buf, 1);
    6dc8:	aa01      	add	r2, sp, #4
    6dca:	f7ff ffcd 	bl	6d68 <boot_write_trailer>
}
    6dce:	b003      	add	sp, #12
    6dd0:	f85d fb04 	ldr.w	pc, [sp], #4

00006dd4 <boot_write_image_ok>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    6dd4:	6881      	ldr	r1, [r0, #8]
    6dd6:	3918      	subs	r1, #24
    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
    6dd8:	2201      	movs	r2, #1
    6dda:	f021 0107 	bic.w	r1, r1, #7
    6dde:	f7ff bfef 	b.w	6dc0 <boot_write_trailer_flag>

00006de2 <boot_read_image_ok>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    6de2:	6882      	ldr	r2, [r0, #8]
    6de4:	3a18      	subs	r2, #24
    return boot_read_flag(fap, image_ok, boot_image_ok_off(fap));
    6de6:	f022 0207 	bic.w	r2, r2, #7
    6dea:	f7ff bfa0 	b.w	6d2e <boot_read_flag>

00006dee <boot_read_swap_state_by_id>:
{
    6dee:	b513      	push	{r0, r1, r4, lr}
    6df0:	460c      	mov	r4, r1
    rc = flash_area_open(flash_area_id, &fap);
    6df2:	b2c0      	uxtb	r0, r0
    6df4:	a901      	add	r1, sp, #4
    6df6:	f7fa ff69 	bl	1ccc <flash_area_open>
    if (rc != 0) {
    6dfa:	b950      	cbnz	r0, 6e12 <boot_read_swap_state_by_id+0x24>
    rc = boot_read_swap_state(fap, state);
    6dfc:	4621      	mov	r1, r4
    6dfe:	9801      	ldr	r0, [sp, #4]
    6e00:	f7fd f886 	bl	3f10 <boot_read_swap_state>
    6e04:	4604      	mov	r4, r0
    flash_area_close(fap);
    6e06:	9801      	ldr	r0, [sp, #4]
    6e08:	f7ff f826 	bl	5e58 <flash_area_close>
}
    6e0c:	4620      	mov	r0, r4
    6e0e:	b002      	add	sp, #8
    6e10:	bd10      	pop	{r4, pc}
        return BOOT_EFLASH;
    6e12:	2401      	movs	r4, #1
    6e14:	e7fa      	b.n	6e0c <boot_read_swap_state_by_id+0x1e>

00006e16 <boot_write_swap_info>:
{
    6e16:	b513      	push	{r0, r1, r4, lr}
    BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);
    6e18:	ea41 1102 	orr.w	r1, r1, r2, lsl #4
{
    6e1c:	4604      	mov	r4, r0
    BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);
    6e1e:	f88d 1007 	strb.w	r1, [sp, #7]
    off = boot_swap_info_off(fap);
    6e22:	f7ff ff6a 	bl	6cfa <boot_swap_info_off>
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
    6e26:	2301      	movs	r3, #1
    off = boot_swap_info_off(fap);
    6e28:	4601      	mov	r1, r0
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
    6e2a:	f10d 0207 	add.w	r2, sp, #7
    6e2e:	4620      	mov	r0, r4
    6e30:	f7ff ff9a 	bl	6d68 <boot_write_trailer>
}
    6e34:	b002      	add	sp, #8
    6e36:	bd10      	pop	{r4, pc}

00006e38 <_mbedtls_init>:
	ARG_UNUSED(device);

	init_heap();

	return 0;
}
    6e38:	2000      	movs	r0, #0
    6e3a:	4770      	bx	lr

00006e3c <mbedtls_asn1_get_len>:
 */
int mbedtls_asn1_get_len( unsigned char **p,
                  const unsigned char *end,
                  size_t *len )
{
    if( ( end - *p ) < 1 )
    6e3c:	6803      	ldr	r3, [r0, #0]
{
    6e3e:	b570      	push	{r4, r5, r6, lr}
    if( ( end - *p ) < 1 )
    6e40:	1acd      	subs	r5, r1, r3
    6e42:	2d00      	cmp	r5, #0
    6e44:	dd0d      	ble.n	6e62 <mbedtls_asn1_get_len+0x26>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    if( ( **p & 0x80 ) == 0 )
    6e46:	f993 6000 	ldrsb.w	r6, [r3]
    6e4a:	781c      	ldrb	r4, [r3, #0]
    6e4c:	2e00      	cmp	r6, #0
    6e4e:	db0b      	blt.n	6e68 <mbedtls_asn1_get_len+0x2c>
        *len = *(*p)++;
    6e50:	1c5c      	adds	r4, r3, #1
    6e52:	6004      	str	r4, [r0, #0]
    6e54:	781b      	ldrb	r3, [r3, #0]
    6e56:	6013      	str	r3, [r2, #0]
        default:
            return( MBEDTLS_ERR_ASN1_INVALID_LENGTH );
        }
    }

    if( *len > (size_t) ( end - *p ) )
    6e58:	6803      	ldr	r3, [r0, #0]
    6e5a:	1ac9      	subs	r1, r1, r3
    6e5c:	6813      	ldr	r3, [r2, #0]
    6e5e:	428b      	cmp	r3, r1
    6e60:	d932      	bls.n	6ec8 <mbedtls_asn1_get_len+0x8c>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    6e62:	f06f 005f 	mvn.w	r0, #95	; 0x5f

    return( 0 );
}
    6e66:	bd70      	pop	{r4, r5, r6, pc}
        switch( **p & 0x7F )
    6e68:	f004 047f 	and.w	r4, r4, #127	; 0x7f
    6e6c:	3c01      	subs	r4, #1
    6e6e:	2c03      	cmp	r4, #3
    6e70:	d827      	bhi.n	6ec2 <mbedtls_asn1_get_len+0x86>
    6e72:	e8df f004 	tbb	[pc, r4]
    6e76:	0902      	.short	0x0902
    6e78:	1e12      	.short	0x1e12
            if( ( end - *p ) < 2 )
    6e7a:	2d01      	cmp	r5, #1
    6e7c:	d0f1      	beq.n	6e62 <mbedtls_asn1_get_len+0x26>
            *len = (*p)[1];
    6e7e:	785c      	ldrb	r4, [r3, #1]
    6e80:	6014      	str	r4, [r2, #0]
            (*p) += 2;
    6e82:	3302      	adds	r3, #2
            (*p) += 5;
    6e84:	6003      	str	r3, [r0, #0]
            break;
    6e86:	e7e7      	b.n	6e58 <mbedtls_asn1_get_len+0x1c>
            if( ( end - *p ) < 3 )
    6e88:	2d02      	cmp	r5, #2
    6e8a:	ddea      	ble.n	6e62 <mbedtls_asn1_get_len+0x26>
            *len = ( (size_t)(*p)[1] << 8 ) | (*p)[2];
    6e8c:	f8b3 4001 	ldrh.w	r4, [r3, #1]
    6e90:	ba64      	rev16	r4, r4
    6e92:	b2a4      	uxth	r4, r4
    6e94:	6014      	str	r4, [r2, #0]
            (*p) += 3;
    6e96:	3303      	adds	r3, #3
    6e98:	e7f4      	b.n	6e84 <mbedtls_asn1_get_len+0x48>
            if( ( end - *p ) < 4 )
    6e9a:	2d03      	cmp	r5, #3
    6e9c:	dde1      	ble.n	6e62 <mbedtls_asn1_get_len+0x26>
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    6e9e:	789c      	ldrb	r4, [r3, #2]
            *len = ( (size_t)(*p)[1] << 16 ) |
    6ea0:	785d      	ldrb	r5, [r3, #1]
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    6ea2:	0224      	lsls	r4, r4, #8
            *len = ( (size_t)(*p)[1] << 16 ) |
    6ea4:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    6ea8:	78dd      	ldrb	r5, [r3, #3]
    6eaa:	432c      	orrs	r4, r5
            *len = ( (size_t)(*p)[1] << 16 ) |
    6eac:	6014      	str	r4, [r2, #0]
            (*p) += 4;
    6eae:	3304      	adds	r3, #4
    6eb0:	e7e8      	b.n	6e84 <mbedtls_asn1_get_len+0x48>
            if( ( end - *p ) < 5 )
    6eb2:	2d04      	cmp	r5, #4
    6eb4:	ddd5      	ble.n	6e62 <mbedtls_asn1_get_len+0x26>
            *len = ( (size_t)(*p)[1] << 24 ) | ( (size_t)(*p)[2] << 16 ) |
    6eb6:	f8d3 4001 	ldr.w	r4, [r3, #1]
    6eba:	ba24      	rev	r4, r4
    6ebc:	6014      	str	r4, [r2, #0]
            (*p) += 5;
    6ebe:	3305      	adds	r3, #5
    6ec0:	e7e0      	b.n	6e84 <mbedtls_asn1_get_len+0x48>
        switch( **p & 0x7F )
    6ec2:	f06f 0063 	mvn.w	r0, #99	; 0x63
    6ec6:	e7ce      	b.n	6e66 <mbedtls_asn1_get_len+0x2a>
    return( 0 );
    6ec8:	2000      	movs	r0, #0
    6eca:	e7cc      	b.n	6e66 <mbedtls_asn1_get_len+0x2a>

00006ecc <mbedtls_asn1_get_tag>:

int mbedtls_asn1_get_tag( unsigned char **p,
                  const unsigned char *end,
                  size_t *len, int tag )
{
    6ecc:	b470      	push	{r4, r5, r6}
    if( ( end - *p ) < 1 )
    6ece:	6804      	ldr	r4, [r0, #0]
    6ed0:	1b0e      	subs	r6, r1, r4
    6ed2:	2e00      	cmp	r6, #0
    6ed4:	dd07      	ble.n	6ee6 <mbedtls_asn1_get_tag+0x1a>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    if( **p != tag )
    6ed6:	7826      	ldrb	r6, [r4, #0]
    6ed8:	429e      	cmp	r6, r3
    6eda:	d108      	bne.n	6eee <mbedtls_asn1_get_tag+0x22>
        return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG );

    (*p)++;
    6edc:	3401      	adds	r4, #1
    6ede:	6004      	str	r4, [r0, #0]

    return( mbedtls_asn1_get_len( p, end, len ) );
}
    6ee0:	bc70      	pop	{r4, r5, r6}
    return( mbedtls_asn1_get_len( p, end, len ) );
    6ee2:	f7ff bfab 	b.w	6e3c <mbedtls_asn1_get_len>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    6ee6:	f06f 005f 	mvn.w	r0, #95	; 0x5f
}
    6eea:	bc70      	pop	{r4, r5, r6}
    6eec:	4770      	bx	lr
        return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG );
    6eee:	f06f 0061 	mvn.w	r0, #97	; 0x61
    6ef2:	e7fa      	b.n	6eea <mbedtls_asn1_get_tag+0x1e>

00006ef4 <mbedtls_asn1_get_mpi>:

#if defined(MBEDTLS_BIGNUM_C)
int mbedtls_asn1_get_mpi( unsigned char **p,
                  const unsigned char *end,
                  mbedtls_mpi *X )
{
    6ef4:	b537      	push	{r0, r1, r2, r4, r5, lr}
    int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;
    size_t len;

    if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_INTEGER ) ) != 0 )
    6ef6:	2302      	movs	r3, #2
{
    6ef8:	4615      	mov	r5, r2
    if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_INTEGER ) ) != 0 )
    6efa:	aa01      	add	r2, sp, #4
{
    6efc:	4604      	mov	r4, r0
    if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_INTEGER ) ) != 0 )
    6efe:	f7ff ffe5 	bl	6ecc <mbedtls_asn1_get_tag>
    6f02:	b940      	cbnz	r0, 6f16 <mbedtls_asn1_get_mpi+0x22>
        return( ret );

    ret = mbedtls_mpi_read_binary( X, *p, len );
    6f04:	9a01      	ldr	r2, [sp, #4]
    6f06:	6821      	ldr	r1, [r4, #0]
    6f08:	4628      	mov	r0, r5
    6f0a:	f000 fb59 	bl	75c0 <mbedtls_mpi_read_binary>

    *p += len;
    6f0e:	6823      	ldr	r3, [r4, #0]
    6f10:	9a01      	ldr	r2, [sp, #4]
    6f12:	4413      	add	r3, r2
    6f14:	6023      	str	r3, [r4, #0]

    return( ret );
}
    6f16:	b003      	add	sp, #12
    6f18:	bd30      	pop	{r4, r5, pc}

00006f1a <mpi_safe_cond_assign>:
 */
static void mpi_safe_cond_assign( size_t n,
                                  mbedtls_mpi_uint *dest,
                                  const mbedtls_mpi_uint *src,
                                  unsigned char assign )
{
    6f1a:	b5f0      	push	{r4, r5, r6, r7, lr}
    6f1c:	3904      	subs	r1, #4
#pragma warning( push )
#pragma warning( disable : 4146 )
#endif

    /* all-bits 1 if assign is 1, all-bits 0 if assign is 0 */
    const mbedtls_mpi_uint mask = -assign;
    6f1e:	425f      	negs	r7, r3

#if defined(_MSC_VER)
#pragma warning( pop )
#endif

    for( i = 0; i < n; i++ )
    6f20:	2500      	movs	r5, #0
        dest[i] = ( src[i] & mask ) | ( dest[i] & ~mask );
    6f22:	3b01      	subs	r3, #1
    for( i = 0; i < n; i++ )
    6f24:	4285      	cmp	r5, r0
    6f26:	d100      	bne.n	6f2a <mpi_safe_cond_assign+0x10>
}
    6f28:	bdf0      	pop	{r4, r5, r6, r7, pc}
        dest[i] = ( src[i] & mask ) | ( dest[i] & ~mask );
    6f2a:	f852 6025 	ldr.w	r6, [r2, r5, lsl #2]
    6f2e:	f851 4f04 	ldr.w	r4, [r1, #4]!
    6f32:	403e      	ands	r6, r7
    6f34:	401c      	ands	r4, r3
    6f36:	4334      	orrs	r4, r6
    6f38:	600c      	str	r4, [r1, #0]
    for( i = 0; i < n; i++ )
    6f3a:	3501      	adds	r5, #1
    6f3c:	e7f2      	b.n	6f24 <mpi_safe_cond_assign+0xa>

00006f3e <mpi_mul_hlp>:
#endif
void mpi_mul_hlp( size_t i,
                  const mbedtls_mpi_uint *s,
                  mbedtls_mpi_uint *d,
                  mbedtls_mpi_uint b )
{
    6f3e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
        MULADDC_INIT
        MULADDC_CORE
        MULADDC_STOP
    }
#else /* MULADDC_HUIT */
    for( ; i >= 16; i -= 16 )
    6f42:	4684      	mov	ip, r0
{
    6f44:	4688      	mov	r8, r1
    6f46:	460e      	mov	r6, r1
    6f48:	4614      	mov	r4, r2
    mbedtls_mpi_uint c = 0, t = 0;
    6f4a:	2500      	movs	r5, #0
    for( ; i >= 16; i -= 16 )
    6f4c:	f1bc 0f0f 	cmp.w	ip, #15
    6f50:	f106 0640 	add.w	r6, r6, #64	; 0x40
    6f54:	f104 0440 	add.w	r4, r4, #64	; 0x40
    6f58:	d878      	bhi.n	704c <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x4c>
    6f5a:	0907      	lsrs	r7, r0, #4
    6f5c:	f06f 060f 	mvn.w	r6, #15
    6f60:	fb06 0607 	mla	r6, r6, r7, r0
        MULADDC_CORE   MULADDC_CORE
        MULADDC_CORE   MULADDC_CORE
        MULADDC_STOP
    }

    for( ; i >= 8; i -= 8 )
    6f64:	2e07      	cmp	r6, #7
    6f66:	ea4f 1c87 	mov.w	ip, r7, lsl #6
    6f6a:	eb08 1487 	add.w	r4, r8, r7, lsl #6
    6f6e:	eb02 1087 	add.w	r0, r2, r7, lsl #6
    6f72:	d95d      	bls.n	7030 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x30>
    {
        MULADDC_INIT
        MULADDC_CORE   MULADDC_CORE
    6f74:	f858 700c 	ldr.w	r7, [r8, ip]
    6f78:	fba3 1707 	umull	r1, r7, r3, r7
    6f7c:	186d      	adds	r5, r5, r1
    6f7e:	f852 100c 	ldr.w	r1, [r2, ip]
    6f82:	f147 0700 	adc.w	r7, r7, #0
    6f86:	186d      	adds	r5, r5, r1
    6f88:	f842 500c 	str.w	r5, [r2, ip]
    6f8c:	6861      	ldr	r1, [r4, #4]
    6f8e:	f147 0200 	adc.w	r2, r7, #0
    6f92:	fba3 5101 	umull	r5, r1, r3, r1
    6f96:	1952      	adds	r2, r2, r5
    6f98:	6845      	ldr	r5, [r0, #4]
    6f9a:	f141 0100 	adc.w	r1, r1, #0
    6f9e:	1952      	adds	r2, r2, r5
    6fa0:	6042      	str	r2, [r0, #4]
        MULADDC_CORE   MULADDC_CORE
    6fa2:	68a2      	ldr	r2, [r4, #8]
        MULADDC_CORE   MULADDC_CORE
    6fa4:	f141 0100 	adc.w	r1, r1, #0
        MULADDC_CORE   MULADDC_CORE
    6fa8:	fba3 5202 	umull	r5, r2, r3, r2
    6fac:	1949      	adds	r1, r1, r5
    6fae:	6885      	ldr	r5, [r0, #8]
    6fb0:	f142 0200 	adc.w	r2, r2, #0
    6fb4:	1949      	adds	r1, r1, r5
    6fb6:	6081      	str	r1, [r0, #8]
    6fb8:	68e1      	ldr	r1, [r4, #12]
    6fba:	f142 0200 	adc.w	r2, r2, #0
    6fbe:	fba3 5101 	umull	r5, r1, r3, r1
    6fc2:	1952      	adds	r2, r2, r5
    6fc4:	68c5      	ldr	r5, [r0, #12]
    6fc6:	f141 0100 	adc.w	r1, r1, #0
    6fca:	1952      	adds	r2, r2, r5
    6fcc:	60c2      	str	r2, [r0, #12]

        MULADDC_CORE   MULADDC_CORE
    6fce:	6922      	ldr	r2, [r4, #16]
        MULADDC_CORE   MULADDC_CORE
    6fd0:	f141 0100 	adc.w	r1, r1, #0
        MULADDC_CORE   MULADDC_CORE
    6fd4:	fba3 5202 	umull	r5, r2, r3, r2
    6fd8:	1949      	adds	r1, r1, r5
    6fda:	6905      	ldr	r5, [r0, #16]
    6fdc:	f142 0200 	adc.w	r2, r2, #0
    6fe0:	1949      	adds	r1, r1, r5
    6fe2:	6101      	str	r1, [r0, #16]
    6fe4:	6961      	ldr	r1, [r4, #20]
    6fe6:	f142 0200 	adc.w	r2, r2, #0
    6fea:	fba3 5101 	umull	r5, r1, r3, r1
    6fee:	1952      	adds	r2, r2, r5
    6ff0:	6945      	ldr	r5, [r0, #20]
    6ff2:	f141 0100 	adc.w	r1, r1, #0
    6ff6:	1952      	adds	r2, r2, r5
    6ff8:	6142      	str	r2, [r0, #20]
        MULADDC_CORE   MULADDC_CORE
    6ffa:	69a2      	ldr	r2, [r4, #24]
        MULADDC_CORE   MULADDC_CORE
    6ffc:	f141 0100 	adc.w	r1, r1, #0
        MULADDC_CORE   MULADDC_CORE
    7000:	fba3 5202 	umull	r5, r2, r3, r2
    7004:	1949      	adds	r1, r1, r5
    7006:	6985      	ldr	r5, [r0, #24]
    7008:	f142 0200 	adc.w	r2, r2, #0
    700c:	1949      	adds	r1, r1, r5
    700e:	6181      	str	r1, [r0, #24]
    7010:	69e5      	ldr	r5, [r4, #28]
    7012:	f142 0200 	adc.w	r2, r2, #0
    7016:	fba3 5105 	umull	r5, r1, r3, r5
    701a:	1952      	adds	r2, r2, r5
    701c:	f141 0500 	adc.w	r5, r1, #0
    7020:	69c1      	ldr	r1, [r0, #28]
    7022:	1852      	adds	r2, r2, r1
    7024:	61c2      	str	r2, [r0, #28]
    7026:	f145 0500 	adc.w	r5, r5, #0
    for( ; i >= 8; i -= 8 )
    702a:	3e08      	subs	r6, #8
        MULADDC_CORE   MULADDC_CORE
    702c:	3020      	adds	r0, #32
    702e:	3420      	adds	r4, #32
    7030:	ea4f 0c86 	mov.w	ip, r6, lsl #2
    7034:	4607      	mov	r7, r0
    7036:	eb04 0686 	add.w	r6, r4, r6, lsl #2
        MULADDC_STOP
    }

    for( ; i > 0; i-- )
    703a:	42a6      	cmp	r6, r4
    703c:	f040 8105 	bne.w	724a <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x24a>
    7040:	4460      	add	r0, ip
    }
#endif /* MULADDC_HUIT */

    t++;

    while( c != 0 )
    7042:	2d00      	cmp	r5, #0
    7044:	f040 810f 	bne.w	7266 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x266>
    {
        *d += c; c = ( *d < c ); d++;
    }
}
    7048:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        MULADDC_CORE   MULADDC_CORE
    704c:	f856 7c40 	ldr.w	r7, [r6, #-64]
    7050:	f854 1c40 	ldr.w	r1, [r4, #-64]
    7054:	fba3 e707 	umull	lr, r7, r3, r7
    7058:	eb15 050e 	adds.w	r5, r5, lr
    705c:	f147 0700 	adc.w	r7, r7, #0
    7060:	194d      	adds	r5, r1, r5
    7062:	f844 5c40 	str.w	r5, [r4, #-64]
    7066:	f856 5c3c 	ldr.w	r5, [r6, #-60]
    706a:	f854 1c3c 	ldr.w	r1, [r4, #-60]
    706e:	fba3 e505 	umull	lr, r5, r3, r5
    7072:	f147 0700 	adc.w	r7, r7, #0
    7076:	eb17 070e 	adds.w	r7, r7, lr
    707a:	f145 0500 	adc.w	r5, r5, #0
    707e:	19cf      	adds	r7, r1, r7
    7080:	f844 7c3c 	str.w	r7, [r4, #-60]
        MULADDC_CORE   MULADDC_CORE
    7084:	f856 7c38 	ldr.w	r7, [r6, #-56]
        MULADDC_CORE   MULADDC_CORE
    7088:	f145 0500 	adc.w	r5, r5, #0
        MULADDC_CORE   MULADDC_CORE
    708c:	fba3 e707 	umull	lr, r7, r3, r7
    7090:	eb15 0e0e 	adds.w	lr, r5, lr
    7094:	f854 5c38 	ldr.w	r5, [r4, #-56]
    7098:	f147 0700 	adc.w	r7, r7, #0
    709c:	eb15 050e 	adds.w	r5, r5, lr
    70a0:	f844 5c38 	str.w	r5, [r4, #-56]
    70a4:	f856 5c34 	ldr.w	r5, [r6, #-52]
    70a8:	f147 0700 	adc.w	r7, r7, #0
    70ac:	fba3 e505 	umull	lr, r5, r3, r5
    70b0:	eb17 0e0e 	adds.w	lr, r7, lr
    70b4:	f854 7c34 	ldr.w	r7, [r4, #-52]
    70b8:	f145 0500 	adc.w	r5, r5, #0
    70bc:	eb17 070e 	adds.w	r7, r7, lr
    70c0:	f844 7c34 	str.w	r7, [r4, #-52]
        MULADDC_CORE   MULADDC_CORE
    70c4:	f856 7c30 	ldr.w	r7, [r6, #-48]
        MULADDC_CORE   MULADDC_CORE
    70c8:	f145 0500 	adc.w	r5, r5, #0
        MULADDC_CORE   MULADDC_CORE
    70cc:	fba3 e707 	umull	lr, r7, r3, r7
    70d0:	eb15 0e0e 	adds.w	lr, r5, lr
    70d4:	f854 5c30 	ldr.w	r5, [r4, #-48]
    70d8:	f147 0700 	adc.w	r7, r7, #0
    70dc:	eb15 050e 	adds.w	r5, r5, lr
    70e0:	f844 5c30 	str.w	r5, [r4, #-48]
    70e4:	f856 5c2c 	ldr.w	r5, [r6, #-44]
    70e8:	f147 0700 	adc.w	r7, r7, #0
    70ec:	fba3 e505 	umull	lr, r5, r3, r5
    70f0:	eb17 0e0e 	adds.w	lr, r7, lr
    70f4:	f854 7c2c 	ldr.w	r7, [r4, #-44]
    70f8:	f145 0500 	adc.w	r5, r5, #0
    70fc:	eb17 070e 	adds.w	r7, r7, lr
    7100:	f844 7c2c 	str.w	r7, [r4, #-44]
        MULADDC_CORE   MULADDC_CORE
    7104:	f856 7c28 	ldr.w	r7, [r6, #-40]
        MULADDC_CORE   MULADDC_CORE
    7108:	f145 0500 	adc.w	r5, r5, #0
        MULADDC_CORE   MULADDC_CORE
    710c:	fba3 e707 	umull	lr, r7, r3, r7
    7110:	eb15 0e0e 	adds.w	lr, r5, lr
    7114:	f854 5c28 	ldr.w	r5, [r4, #-40]
    7118:	f147 0700 	adc.w	r7, r7, #0
    711c:	eb15 050e 	adds.w	r5, r5, lr
    7120:	f844 5c28 	str.w	r5, [r4, #-40]
    7124:	f856 5c24 	ldr.w	r5, [r6, #-36]
    7128:	f147 0700 	adc.w	r7, r7, #0
    712c:	fba3 e505 	umull	lr, r5, r3, r5
    7130:	eb17 0e0e 	adds.w	lr, r7, lr
    7134:	f854 7c24 	ldr.w	r7, [r4, #-36]
    7138:	f145 0500 	adc.w	r5, r5, #0
    713c:	eb17 070e 	adds.w	r7, r7, lr
    7140:	f844 7c24 	str.w	r7, [r4, #-36]
        MULADDC_CORE   MULADDC_CORE
    7144:	f856 7c20 	ldr.w	r7, [r6, #-32]
        MULADDC_CORE   MULADDC_CORE
    7148:	f145 0500 	adc.w	r5, r5, #0
        MULADDC_CORE   MULADDC_CORE
    714c:	fba3 e707 	umull	lr, r7, r3, r7
    7150:	eb15 0e0e 	adds.w	lr, r5, lr
    7154:	f854 5c20 	ldr.w	r5, [r4, #-32]
    7158:	f147 0700 	adc.w	r7, r7, #0
    715c:	eb15 050e 	adds.w	r5, r5, lr
    7160:	f844 5c20 	str.w	r5, [r4, #-32]
    7164:	f856 5c1c 	ldr.w	r5, [r6, #-28]
    7168:	f147 0700 	adc.w	r7, r7, #0
    716c:	fba3 e505 	umull	lr, r5, r3, r5
    7170:	eb17 0e0e 	adds.w	lr, r7, lr
    7174:	f854 7c1c 	ldr.w	r7, [r4, #-28]
    7178:	f145 0500 	adc.w	r5, r5, #0
    717c:	eb17 070e 	adds.w	r7, r7, lr
    7180:	f844 7c1c 	str.w	r7, [r4, #-28]
        MULADDC_CORE   MULADDC_CORE
    7184:	f856 7c18 	ldr.w	r7, [r6, #-24]
        MULADDC_CORE   MULADDC_CORE
    7188:	f145 0500 	adc.w	r5, r5, #0
        MULADDC_CORE   MULADDC_CORE
    718c:	fba3 e707 	umull	lr, r7, r3, r7
    7190:	eb15 0e0e 	adds.w	lr, r5, lr
    7194:	f854 5c18 	ldr.w	r5, [r4, #-24]
    7198:	f147 0700 	adc.w	r7, r7, #0
    719c:	eb15 050e 	adds.w	r5, r5, lr
    71a0:	f844 5c18 	str.w	r5, [r4, #-24]
    71a4:	f856 5c14 	ldr.w	r5, [r6, #-20]
        MULADDC_CORE   MULADDC_CORE
    71a8:	f854 1c04 	ldr.w	r1, [r4, #-4]
        MULADDC_CORE   MULADDC_CORE
    71ac:	fba3 e505 	umull	lr, r5, r3, r5
    71b0:	f147 0700 	adc.w	r7, r7, #0
    71b4:	eb17 0e0e 	adds.w	lr, r7, lr
    71b8:	f854 7c14 	ldr.w	r7, [r4, #-20]
    71bc:	f145 0500 	adc.w	r5, r5, #0
    71c0:	eb17 070e 	adds.w	r7, r7, lr
    71c4:	f844 7c14 	str.w	r7, [r4, #-20]
        MULADDC_CORE   MULADDC_CORE
    71c8:	f856 7c10 	ldr.w	r7, [r6, #-16]
        MULADDC_CORE   MULADDC_CORE
    71cc:	f145 0500 	adc.w	r5, r5, #0
        MULADDC_CORE   MULADDC_CORE
    71d0:	fba3 e707 	umull	lr, r7, r3, r7
    71d4:	eb15 0e0e 	adds.w	lr, r5, lr
    71d8:	f854 5c10 	ldr.w	r5, [r4, #-16]
    71dc:	f147 0700 	adc.w	r7, r7, #0
    71e0:	eb15 050e 	adds.w	r5, r5, lr
    71e4:	f844 5c10 	str.w	r5, [r4, #-16]
    71e8:	f856 5c0c 	ldr.w	r5, [r6, #-12]
    71ec:	f147 0700 	adc.w	r7, r7, #0
    71f0:	fba3 e505 	umull	lr, r5, r3, r5
    71f4:	eb17 0e0e 	adds.w	lr, r7, lr
    71f8:	f854 7c0c 	ldr.w	r7, [r4, #-12]
    71fc:	f145 0500 	adc.w	r5, r5, #0
    7200:	eb17 070e 	adds.w	r7, r7, lr
    7204:	f844 7c0c 	str.w	r7, [r4, #-12]
        MULADDC_CORE   MULADDC_CORE
    7208:	f856 7c08 	ldr.w	r7, [r6, #-8]
        MULADDC_CORE   MULADDC_CORE
    720c:	f145 0500 	adc.w	r5, r5, #0
        MULADDC_CORE   MULADDC_CORE
    7210:	fba3 e707 	umull	lr, r7, r3, r7
    7214:	eb15 0e0e 	adds.w	lr, r5, lr
    7218:	f854 5c08 	ldr.w	r5, [r4, #-8]
    721c:	f147 0700 	adc.w	r7, r7, #0
    7220:	eb15 050e 	adds.w	r5, r5, lr
    7224:	f844 5c08 	str.w	r5, [r4, #-8]
    7228:	f856 5c04 	ldr.w	r5, [r6, #-4]
    722c:	f147 0700 	adc.w	r7, r7, #0
    7230:	fba3 5e05 	umull	r5, lr, r3, r5
    7234:	197f      	adds	r7, r7, r5
    7236:	f14e 0500 	adc.w	r5, lr, #0
    723a:	19cf      	adds	r7, r1, r7
    723c:	f145 0500 	adc.w	r5, r5, #0
    7240:	f844 7c04 	str.w	r7, [r4, #-4]
    for( ; i >= 16; i -= 16 )
    7244:	f1ac 0c10 	sub.w	ip, ip, #16
    7248:	e680      	b.n	6f4c <mpi_mul_hlp+0xe>
        MULADDC_CORE
    724a:	f854 2b04 	ldr.w	r2, [r4], #4
    724e:	fba3 2102 	umull	r2, r1, r3, r2
    7252:	18ad      	adds	r5, r5, r2
    7254:	f141 0200 	adc.w	r2, r1, #0
    7258:	6839      	ldr	r1, [r7, #0]
    725a:	1949      	adds	r1, r1, r5
    725c:	f847 1b04 	str.w	r1, [r7], #4
    7260:	f142 0500 	adc.w	r5, r2, #0
    for( ; i > 0; i-- )
    7264:	e6e9      	b.n	703a <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x3a>
        *d += c; c = ( *d < c ); d++;
    7266:	6803      	ldr	r3, [r0, #0]
    7268:	195b      	adds	r3, r3, r5
    726a:	f840 3b04 	str.w	r3, [r0], #4
    726e:	bf2c      	ite	cs
    7270:	2501      	movcs	r5, #1
    7272:	2500      	movcc	r5, #0
    7274:	e6e5      	b.n	7042 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x42>

00007276 <mpi_montmul>:
 *                      Note that unlike the usual convention in the library
 *                      for `const mbedtls_mpi*`, the content of T can change.
 */
static void mpi_montmul( mbedtls_mpi *A, const mbedtls_mpi *B, const mbedtls_mpi *N, mbedtls_mpi_uint mm,
                         const mbedtls_mpi *T )
{
    7276:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    727a:	b085      	sub	sp, #20
    727c:	4617      	mov	r7, r2
    727e:	9c0e      	ldr	r4, [sp, #56]	; 0x38
    7280:	9000      	str	r0, [sp, #0]
    size_t i, n, m;
    mbedtls_mpi_uint u0, u1, *d;

    memset( T->p, 0, T->n * ciL );
    7282:	6862      	ldr	r2, [r4, #4]
    7284:	68a0      	ldr	r0, [r4, #8]
{
    7286:	9303      	str	r3, [sp, #12]
    7288:	468a      	mov	sl, r1
    memset( T->p, 0, T->n * ciL );
    728a:	0092      	lsls	r2, r2, #2
    728c:	2100      	movs	r1, #0
    728e:	f7ff f938 	bl	6502 <memset>

    d = T->p;
    n = N->n;
    7292:	687d      	ldr	r5, [r7, #4]
    m = ( B->n < n ) ? B->n : n;
    7294:	f8da 3004 	ldr.w	r3, [sl, #4]
    d = T->p;
    7298:	68a6      	ldr	r6, [r4, #8]
    m = ( B->n < n ) ? B->n : n;
    729a:	42ab      	cmp	r3, r5
    729c:	bf28      	it	cs
    729e:	462b      	movcs	r3, r5
        u1 = ( d[0] + u0 * B->p[0] ) * mm;

        mpi_mul_hlp( m, B->p, d, u0 );
        mpi_mul_hlp( n, N->p, d, u1 );

        *d++ = u0; d[n + 1] = 0;
    72a0:	1c6c      	adds	r4, r5, #1
    m = ( B->n < n ) ? B->n : n;
    72a2:	9301      	str	r3, [sp, #4]
        *d++ = u0; d[n + 1] = 0;
    72a4:	00a4      	lsls	r4, r4, #2
    d = T->p;
    72a6:	46b1      	mov	r9, r6
    for( i = 0; i < n; i++ )
    72a8:	f04f 0800 	mov.w	r8, #0
        u0 = A->p[i];
    72ac:	9b00      	ldr	r3, [sp, #0]
    for( i = 0; i < n; i++ )
    72ae:	45a8      	cmp	r8, r5
        u0 = A->p[i];
    72b0:	6898      	ldr	r0, [r3, #8]
    for( i = 0; i < n; i++ )
    72b2:	d122      	bne.n	72fa <mpi_montmul+0x84>
    72b4:	3c04      	subs	r4, #4
    72b6:	eb06 0804 	add.w	r8, r6, r4
     * plus N. We now potentially subtract N, avoiding leaking whether the
     * subtraction is performed through side channels. */

    /* Copy the n least significant limbs of d to A, so that
     * A = d if d < N (recall that N has n limbs). */
    memcpy( A->p, d, n * ciL );
    72ba:	4622      	mov	r2, r4
    72bc:	4641      	mov	r1, r8
    72be:	f7ff f915 	bl	64ec <memcpy>
    /* If d >= N then we want to set A to d - N. To prevent timing attacks,
     * do the calculation without using conditional tests. */
    /* Set d to d0 + (2^biL)^n - N where d0 is the current value of d. */
    d[n] += 1;
    72c2:	f856 3014 	ldr.w	r3, [r6, r4, lsl #1]
    d[n] -= mpi_sub_hlp( n, d, d, N->p );
    72c6:	f8d7 e008 	ldr.w	lr, [r7, #8]
    d[n] += 1;
    72ca:	3301      	adds	r3, #1
    72cc:	f846 3014 	str.w	r3, [r6, r4, lsl #1]
    mbedtls_mpi_uint c = 0, t, z;
    72d0:	2300      	movs	r3, #0
    72d2:	f1a8 0004 	sub.w	r0, r8, #4
    for( i = 0; i < n; i++ )
    72d6:	461a      	mov	r2, r3
    72d8:	4295      	cmp	r5, r2
    72da:	d12d      	bne.n	7338 <mpi_montmul+0xc2>
    d[n] -= mpi_sub_hlp( n, d, d, N->p );
    72dc:	f856 2014 	ldr.w	r2, [r6, r4, lsl #1]
     * so d[n] == 0 and we want to keep A as it is.
     * If d0 >= N then d >= (2^biL)^n, and d <= (2^biL)^n + N < 2 * (2^biL)^n
     * so d[n] == 1 and we want to set A to the result of the subtraction
     * which is d - (2^biL)^n, i.e. the n least significant limbs of d.
     * This exactly corresponds to a conditional assignment. */
    mpi_safe_cond_assign( n, A->p, d, (unsigned char) d[n] );
    72e0:	9900      	ldr	r1, [sp, #0]
    d[n] -= mpi_sub_hlp( n, d, d, N->p );
    72e2:	1ad3      	subs	r3, r2, r3
    mpi_safe_cond_assign( n, A->p, d, (unsigned char) d[n] );
    72e4:	6889      	ldr	r1, [r1, #8]
    d[n] -= mpi_sub_hlp( n, d, d, N->p );
    72e6:	f846 3014 	str.w	r3, [r6, r4, lsl #1]
    mpi_safe_cond_assign( n, A->p, d, (unsigned char) d[n] );
    72ea:	4642      	mov	r2, r8
    72ec:	b2db      	uxtb	r3, r3
    72ee:	4628      	mov	r0, r5
}
    72f0:	b005      	add	sp, #20
    72f2:	e8bd 4ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    mpi_safe_cond_assign( n, A->p, d, (unsigned char) d[n] );
    72f6:	f7ff be10 	b.w	6f1a <mpi_safe_cond_assign>
        u1 = ( d[0] + u0 * B->p[0] ) * mm;
    72fa:	f8da 1008 	ldr.w	r1, [sl, #8]
        u0 = A->p[i];
    72fe:	f850 b028 	ldr.w	fp, [r0, r8, lsl #2]
        u1 = ( d[0] + u0 * B->p[0] ) * mm;
    7302:	f8d9 3000 	ldr.w	r3, [r9]
    7306:	6808      	ldr	r0, [r1, #0]
    7308:	9a03      	ldr	r2, [sp, #12]
    730a:	fb00 330b 	mla	r3, r0, fp, r3
    730e:	4353      	muls	r3, r2
        mpi_mul_hlp( m, B->p, d, u0 );
    7310:	9801      	ldr	r0, [sp, #4]
        u1 = ( d[0] + u0 * B->p[0] ) * mm;
    7312:	9302      	str	r3, [sp, #8]
        mpi_mul_hlp( m, B->p, d, u0 );
    7314:	464a      	mov	r2, r9
    7316:	465b      	mov	r3, fp
    7318:	f7ff fe11 	bl	6f3e <mpi_mul_hlp>
        mpi_mul_hlp( n, N->p, d, u1 );
    731c:	9b02      	ldr	r3, [sp, #8]
    731e:	68b9      	ldr	r1, [r7, #8]
    7320:	464a      	mov	r2, r9
    7322:	4628      	mov	r0, r5
    7324:	f7ff fe0b 	bl	6f3e <mpi_mul_hlp>
        *d++ = u0; d[n + 1] = 0;
    7328:	f849 bb04 	str.w	fp, [r9], #4
    732c:	2300      	movs	r3, #0
    732e:	f849 3004 	str.w	r3, [r9, r4]
    for( i = 0; i < n; i++ )
    7332:	f108 0801 	add.w	r8, r8, #1
    7336:	e7b9      	b.n	72ac <mpi_montmul+0x36>
        z = ( l[i] <  c );    t = l[i] - c;
    7338:	f850 cf04 	ldr.w	ip, [r0, #4]!
        c = ( t < r[i] ) + z; d[i] = t - r[i];
    733c:	f85e 7022 	ldr.w	r7, [lr, r2, lsl #2]
        z = ( l[i] <  c );    t = l[i] - c;
    7340:	ebac 0103 	sub.w	r1, ip, r3
        c = ( t < r[i] ) + z; d[i] = t - r[i];
    7344:	42b9      	cmp	r1, r7
    7346:	bf2c      	ite	cs
    7348:	f04f 0900 	movcs.w	r9, #0
    734c:	f04f 0901 	movcc.w	r9, #1
    7350:	1bc9      	subs	r1, r1, r7
    7352:	459c      	cmp	ip, r3
    7354:	bf2c      	ite	cs
    7356:	464b      	movcs	r3, r9
    7358:	f109 0301 	addcc.w	r3, r9, #1
    735c:	6001      	str	r1, [r0, #0]
    for( i = 0; i < n; i++ )
    735e:	3201      	adds	r2, #1
    7360:	e7ba      	b.n	72d8 <mpi_montmul+0x62>

00007362 <mpi_bigendian_to_host.part.0>:
static void mpi_bigendian_to_host( mbedtls_mpi_uint * const p, size_t limbs )
    7362:	b573      	push	{r0, r1, r4, r5, r6, lr}
    for( cur_limb_left = p, cur_limb_right = p + ( limbs - 1 );
    7364:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    7368:	3901      	subs	r1, #1
    736a:	eb00 0181 	add.w	r1, r0, r1, lsl #2
    736e:	4281      	cmp	r1, r0
    7370:	d201      	bcs.n	7376 <mpi_bigendian_to_host.part.0+0x14>
}
    7372:	b002      	add	sp, #8
    7374:	bd70      	pop	{r4, r5, r6, pc}
    return( mpi_uint_bigendian_to_host_c( x ) );
    7376:	6803      	ldr	r3, [r0, #0]
    7378:	9301      	str	r3, [sp, #4]
        tmp             = mpi_uint_bigendian_to_host( *cur_limb_left  );
    737a:	2304      	movs	r3, #4
    for( i = 0, x_ptr = (unsigned char*) &x; i < ciL; i++, x_ptr++ )
    737c:	eb0d 0203 	add.w	r2, sp, r3
    mbedtls_mpi_uint tmp = 0;
    7380:	2500      	movs	r5, #0
    7382:	4614      	mov	r4, r2
        tmp |= (mbedtls_mpi_uint) *x_ptr;
    7384:	f812 6b01 	ldrb.w	r6, [r2], #1
    for( i = 0, x_ptr = (unsigned char*) &x; i < ciL; i++, x_ptr++ )
    7388:	3b01      	subs	r3, #1
    738a:	f013 03ff 	ands.w	r3, r3, #255	; 0xff
        tmp |= (mbedtls_mpi_uint) *x_ptr;
    738e:	ea46 2505 	orr.w	r5, r6, r5, lsl #8
    for( i = 0, x_ptr = (unsigned char*) &x; i < ciL; i++, x_ptr++ )
    7392:	d1f7      	bne.n	7384 <mpi_bigendian_to_host.part.0+0x22>
    return( mpi_uint_bigendian_to_host_c( x ) );
    7394:	680a      	ldr	r2, [r1, #0]
    7396:	9201      	str	r2, [sp, #4]
        *cur_limb_left  = mpi_uint_bigendian_to_host( *cur_limb_right );
    7398:	2204      	movs	r2, #4
        tmp |= (mbedtls_mpi_uint) *x_ptr;
    739a:	f814 6b01 	ldrb.w	r6, [r4], #1
    for( i = 0, x_ptr = (unsigned char*) &x; i < ciL; i++, x_ptr++ )
    739e:	3a01      	subs	r2, #1
    73a0:	f012 02ff 	ands.w	r2, r2, #255	; 0xff
        tmp |= (mbedtls_mpi_uint) *x_ptr;
    73a4:	ea46 2303 	orr.w	r3, r6, r3, lsl #8
    for( i = 0, x_ptr = (unsigned char*) &x; i < ciL; i++, x_ptr++ )
    73a8:	d1f7      	bne.n	739a <mpi_bigendian_to_host.part.0+0x38>
        *cur_limb_left  = mpi_uint_bigendian_to_host( *cur_limb_right );
    73aa:	f840 3b04 	str.w	r3, [r0], #4
        *cur_limb_right = tmp;
    73ae:	f841 5904 	str.w	r5, [r1], #-4
         cur_limb_left++, cur_limb_right-- )
    73b2:	e7dc      	b.n	736e <mpi_bigendian_to_host.part.0+0xc>

000073b4 <mbedtls_mpi_init>:
    X->n = 0;
    73b4:	2300      	movs	r3, #0
    73b6:	2201      	movs	r2, #1
    73b8:	e9c0 2300 	strd	r2, r3, [r0]
    X->p = NULL;
    73bc:	6083      	str	r3, [r0, #8]
}
    73be:	4770      	bx	lr

000073c0 <mbedtls_mpi_free>:
{
    73c0:	b510      	push	{r4, lr}
    if( X == NULL )
    73c2:	4604      	mov	r4, r0
    73c4:	b168      	cbz	r0, 73e2 <mbedtls_mpi_free+0x22>
    if( X->p != NULL )
    73c6:	6880      	ldr	r0, [r0, #8]
    73c8:	b130      	cbz	r0, 73d8 <mbedtls_mpi_free+0x18>
    mbedtls_platform_zeroize( v, ciL * n );
    73ca:	6861      	ldr	r1, [r4, #4]
    73cc:	0089      	lsls	r1, r1, #2
    73ce:	f7fd f80d 	bl	43ec <mbedtls_platform_zeroize>
        mbedtls_free( X->p );
    73d2:	68a0      	ldr	r0, [r4, #8]
    73d4:	f7fc fffa 	bl	43cc <mbedtls_free>
    X->n = 0;
    73d8:	2300      	movs	r3, #0
    73da:	2201      	movs	r2, #1
    73dc:	e9c4 2300 	strd	r2, r3, [r4]
    X->p = NULL;
    73e0:	60a3      	str	r3, [r4, #8]
}
    73e2:	bd10      	pop	{r4, pc}

000073e4 <mbedtls_mpi_grow>:
    if( nblimbs > MBEDTLS_MPI_MAX_LIMBS )
    73e4:	f242 7310 	movw	r3, #10000	; 0x2710
    73e8:	4299      	cmp	r1, r3
{
    73ea:	b570      	push	{r4, r5, r6, lr}
    73ec:	4604      	mov	r4, r0
    73ee:	460d      	mov	r5, r1
    if( nblimbs > MBEDTLS_MPI_MAX_LIMBS )
    73f0:	d902      	bls.n	73f8 <mbedtls_mpi_grow+0x14>
        return( MBEDTLS_ERR_MPI_ALLOC_FAILED );
    73f2:	f06f 000f 	mvn.w	r0, #15
}
    73f6:	bd70      	pop	{r4, r5, r6, pc}
    if( X->n < nblimbs )
    73f8:	6843      	ldr	r3, [r0, #4]
    73fa:	428b      	cmp	r3, r1
    73fc:	d216      	bcs.n	742c <mbedtls_mpi_grow+0x48>
        if( ( p = (mbedtls_mpi_uint*)mbedtls_calloc( nblimbs, ciL ) ) == NULL )
    73fe:	2104      	movs	r1, #4
    7400:	4628      	mov	r0, r5
    7402:	f7fc ffdd 	bl	43c0 <mbedtls_calloc>
    7406:	4606      	mov	r6, r0
    7408:	2800      	cmp	r0, #0
    740a:	d0f2      	beq.n	73f2 <mbedtls_mpi_grow+0xe>
        if( X->p != NULL )
    740c:	68a1      	ldr	r1, [r4, #8]
    740e:	b159      	cbz	r1, 7428 <mbedtls_mpi_grow+0x44>
            memcpy( p, X->p, X->n * ciL );
    7410:	6862      	ldr	r2, [r4, #4]
    7412:	0092      	lsls	r2, r2, #2
    7414:	f7ff f86a 	bl	64ec <memcpy>
    mbedtls_platform_zeroize( v, ciL * n );
    7418:	6861      	ldr	r1, [r4, #4]
    741a:	68a0      	ldr	r0, [r4, #8]
    741c:	0089      	lsls	r1, r1, #2
    741e:	f7fc ffe5 	bl	43ec <mbedtls_platform_zeroize>
            mbedtls_free( X->p );
    7422:	68a0      	ldr	r0, [r4, #8]
    7424:	f7fc ffd2 	bl	43cc <mbedtls_free>
        X->p = p;
    7428:	e9c4 5601 	strd	r5, r6, [r4, #4]
    return( 0 );
    742c:	2000      	movs	r0, #0
    742e:	e7e2      	b.n	73f6 <mbedtls_mpi_grow+0x12>

00007430 <mbedtls_mpi_resize_clear>:
{
    7430:	b538      	push	{r3, r4, r5, lr}
    7432:	4604      	mov	r4, r0
    if( limbs == 0 )
    7434:	460d      	mov	r5, r1
    7436:	b919      	cbnz	r1, 7440 <mbedtls_mpi_resize_clear+0x10>
        mbedtls_mpi_free( X );
    7438:	f7ff ffc2 	bl	73c0 <mbedtls_mpi_free>
}
    743c:	2000      	movs	r0, #0
    743e:	bd38      	pop	{r3, r4, r5, pc}
    else if( X->n == limbs )
    7440:	6842      	ldr	r2, [r0, #4]
    7442:	428a      	cmp	r2, r1
    7444:	d107      	bne.n	7456 <mbedtls_mpi_resize_clear+0x26>
        memset( X->p, 0, limbs * ciL );
    7446:	6880      	ldr	r0, [r0, #8]
    7448:	0092      	lsls	r2, r2, #2
    744a:	2100      	movs	r1, #0
    744c:	f7ff f859 	bl	6502 <memset>
        X->s = 1;
    7450:	2301      	movs	r3, #1
    7452:	6023      	str	r3, [r4, #0]
        return( 0 );
    7454:	e7f2      	b.n	743c <mbedtls_mpi_resize_clear+0xc>
        mbedtls_mpi_free( X );
    7456:	f7ff ffb3 	bl	73c0 <mbedtls_mpi_free>
        return( mbedtls_mpi_grow( X, limbs ) );
    745a:	4629      	mov	r1, r5
    745c:	4620      	mov	r0, r4
}
    745e:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
        return( mbedtls_mpi_grow( X, limbs ) );
    7462:	f7ff bfbf 	b.w	73e4 <mbedtls_mpi_grow>

00007466 <mbedtls_mpi_copy>:
    if( X == Y )
    7466:	4288      	cmp	r0, r1
{
    7468:	b570      	push	{r4, r5, r6, lr}
    746a:	4605      	mov	r5, r0
    746c:	460e      	mov	r6, r1
    if( X == Y )
    746e:	d00a      	beq.n	7486 <mbedtls_mpi_copy+0x20>
    if( Y->n == 0 )
    7470:	684c      	ldr	r4, [r1, #4]
        if( X->n != 0 )
    7472:	6840      	ldr	r0, [r0, #4]
    if( Y->n == 0 )
    7474:	b96c      	cbnz	r4, 7492 <mbedtls_mpi_copy+0x2c>
        if( X->n != 0 )
    7476:	b1c8      	cbz	r0, 74ac <mbedtls_mpi_copy+0x46>
            X->s = 1;
    7478:	2301      	movs	r3, #1
            memset( X->p, 0, X->n * ciL );
    747a:	0082      	lsls	r2, r0, #2
            X->s = 1;
    747c:	602b      	str	r3, [r5, #0]
            memset( X->p, 0, X->n * ciL );
    747e:	68a8      	ldr	r0, [r5, #8]
    7480:	4621      	mov	r1, r4
    7482:	f7ff f83e 	bl	6502 <memset>
        return( 0 );
    7486:	2000      	movs	r0, #0
    7488:	e010      	b.n	74ac <mbedtls_mpi_copy+0x46>
        if( Y->p[i] != 0 )
    748a:	68b3      	ldr	r3, [r6, #8]
    748c:	f853 3024 	ldr.w	r3, [r3, r4, lsl #2]
    7490:	b913      	cbnz	r3, 7498 <mbedtls_mpi_copy+0x32>
    for( i = Y->n - 1; i > 0; i-- )
    7492:	3c01      	subs	r4, #1
    7494:	2c00      	cmp	r4, #0
    7496:	d1f8      	bne.n	748a <mbedtls_mpi_copy+0x24>
    i++;
    7498:	3401      	adds	r4, #1
    X->s = Y->s;
    749a:	6833      	ldr	r3, [r6, #0]
    749c:	602b      	str	r3, [r5, #0]
    if( X->n < i )
    749e:	4284      	cmp	r4, r0
    74a0:	d905      	bls.n	74ae <mbedtls_mpi_copy+0x48>
        MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, i ) );
    74a2:	4621      	mov	r1, r4
    74a4:	4628      	mov	r0, r5
    74a6:	f7ff ff9d 	bl	73e4 <mbedtls_mpi_grow>
    74aa:	b140      	cbz	r0, 74be <mbedtls_mpi_copy+0x58>
}
    74ac:	bd70      	pop	{r4, r5, r6, pc}
        memset( X->p + i, 0, ( X->n - i ) * ciL );
    74ae:	1b02      	subs	r2, r0, r4
    74b0:	68a8      	ldr	r0, [r5, #8]
    74b2:	0092      	lsls	r2, r2, #2
    74b4:	2100      	movs	r1, #0
    74b6:	eb00 0084 	add.w	r0, r0, r4, lsl #2
    74ba:	f7ff f822 	bl	6502 <memset>
    memcpy( X->p, Y->p, i * ciL );
    74be:	68b1      	ldr	r1, [r6, #8]
    74c0:	68a8      	ldr	r0, [r5, #8]
    74c2:	00a2      	lsls	r2, r4, #2
    74c4:	f7ff f812 	bl	64ec <memcpy>
    74c8:	e7dd      	b.n	7486 <mbedtls_mpi_copy+0x20>

000074ca <mbedtls_mpi_safe_cond_assign>:
{
    74ca:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    74cc:	460e      	mov	r6, r1
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, Y->n ) );
    74ce:	6849      	ldr	r1, [r1, #4]
{
    74d0:	4605      	mov	r5, r0
    74d2:	4614      	mov	r4, r2
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, Y->n ) );
    74d4:	f7ff ff86 	bl	73e4 <mbedtls_mpi_grow>
    74d8:	4607      	mov	r7, r0
    74da:	b9c0      	cbnz	r0, 750e <mbedtls_mpi_safe_cond_assign+0x44>
    assign = (assign | (unsigned char)-assign) >> (sizeof( assign ) * 8 - 1);
    74dc:	4263      	negs	r3, r4
    74de:	431c      	orrs	r4, r3
    unsigned ua = a + 1;
    74e0:	682b      	ldr	r3, [r5, #0]
    mpi_safe_cond_assign( Y->n, X->p, Y->p, assign );
    74e2:	68a9      	ldr	r1, [r5, #8]
    74e4:	6870      	ldr	r0, [r6, #4]
    unsigned ua = a + 1;
    74e6:	1c5a      	adds	r2, r3, #1
    unsigned ub = b + 1;
    74e8:	6833      	ldr	r3, [r6, #0]
    74ea:	3301      	adds	r3, #1
    assign = (assign | (unsigned char)-assign) >> (sizeof( assign ) * 8 - 1);
    74ec:	f3c4 14c0 	ubfx	r4, r4, #7, #1
    unsigned ur = ( ua & ~mask ) | ( ub & mask );
    74f0:	4053      	eors	r3, r2
    74f2:	ea03 0344 	and.w	r3, r3, r4, lsl #1
    74f6:	4053      	eors	r3, r2
    return( (int) ur - 1 );
    74f8:	3b01      	subs	r3, #1
    X->s = mpi_safe_cond_select_sign( X->s, Y->s, assign );
    74fa:	602b      	str	r3, [r5, #0]
    mpi_safe_cond_assign( Y->n, X->p, Y->p, assign );
    74fc:	68b2      	ldr	r2, [r6, #8]
    74fe:	4623      	mov	r3, r4
    7500:	f7ff fd0b 	bl	6f1a <mpi_safe_cond_assign>
    for( i = Y->n; i < X->n; i++ )
    7504:	6873      	ldr	r3, [r6, #4]
        X->p[i] &= ~limb_mask;
    7506:	3c01      	subs	r4, #1
    for( i = Y->n; i < X->n; i++ )
    7508:	686a      	ldr	r2, [r5, #4]
    750a:	429a      	cmp	r2, r3
    750c:	d801      	bhi.n	7512 <mbedtls_mpi_safe_cond_assign+0x48>
}
    750e:	4638      	mov	r0, r7
    7510:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        X->p[i] &= ~limb_mask;
    7512:	68a9      	ldr	r1, [r5, #8]
    7514:	f851 2023 	ldr.w	r2, [r1, r3, lsl #2]
    7518:	4022      	ands	r2, r4
    751a:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    for( i = Y->n; i < X->n; i++ )
    751e:	3301      	adds	r3, #1
    7520:	e7f2      	b.n	7508 <mbedtls_mpi_safe_cond_assign+0x3e>

00007522 <mbedtls_mpi_lset>:
{
    7522:	b570      	push	{r4, r5, r6, lr}
    7524:	460e      	mov	r6, r1
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, 1 ) );
    7526:	2101      	movs	r1, #1
{
    7528:	4604      	mov	r4, r0
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, 1 ) );
    752a:	f7ff ff5b 	bl	73e4 <mbedtls_mpi_grow>
    752e:	4605      	mov	r5, r0
    7530:	b988      	cbnz	r0, 7556 <mbedtls_mpi_lset+0x34>
    memset( X->p, 0, X->n * ciL );
    7532:	6862      	ldr	r2, [r4, #4]
    7534:	4601      	mov	r1, r0
    7536:	0092      	lsls	r2, r2, #2
    7538:	68a0      	ldr	r0, [r4, #8]
    753a:	f7fe ffe2 	bl	6502 <memset>
    X->p[0] = ( z < 0 ) ? -z : z;
    753e:	68a3      	ldr	r3, [r4, #8]
    7540:	ea86 72e6 	eor.w	r2, r6, r6, asr #31
    X->s    = ( z < 0 ) ? -1 : 1;
    7544:	2e00      	cmp	r6, #0
    X->p[0] = ( z < 0 ) ? -z : z;
    7546:	eba2 72e6 	sub.w	r2, r2, r6, asr #31
    754a:	601a      	str	r2, [r3, #0]
    X->s    = ( z < 0 ) ? -1 : 1;
    754c:	bfb4      	ite	lt
    754e:	f04f 33ff 	movlt.w	r3, #4294967295
    7552:	2301      	movge	r3, #1
    7554:	6023      	str	r3, [r4, #0]
}
    7556:	4628      	mov	r0, r5
    7558:	bd70      	pop	{r4, r5, r6, pc}

0000755a <mbedtls_mpi_get_bit>:
    if( X->n * biL <= pos )
    755a:	6843      	ldr	r3, [r0, #4]
    755c:	ebb1 1f43 	cmp.w	r1, r3, lsl #5
    return( ( X->p[pos / biL] >> ( pos % biL ) ) & 0x01 );
    7560:	bf3f      	itttt	cc
    7562:	094a      	lsrcc	r2, r1, #5
    7564:	6883      	ldrcc	r3, [r0, #8]
    7566:	f853 0022 	ldrcc.w	r0, [r3, r2, lsl #2]
    756a:	f001 011f 	andcc.w	r1, r1, #31
    756e:	bf3a      	itte	cc
    7570:	fa20 f101 	lsrcc.w	r1, r0, r1
    7574:	f001 0001 	andcc.w	r0, r1, #1
        return( 0 );
    7578:	2000      	movcs	r0, #0
}
    757a:	4770      	bx	lr

0000757c <mbedtls_mpi_bitlen>:
{
    757c:	4602      	mov	r2, r0
    if( X->n == 0 )
    757e:	6840      	ldr	r0, [r0, #4]
    7580:	b188      	cbz	r0, 75a6 <mbedtls_mpi_bitlen+0x2a>
        if( X->p[i] != 0 )
    7582:	6892      	ldr	r2, [r2, #8]
    for( i = X->n - 1; i > 0; i-- )
    7584:	1e43      	subs	r3, r0, #1
    7586:	b97b      	cbnz	r3, 75a8 <mbedtls_mpi_bitlen+0x2c>
    j = biL - mbedtls_clz( X->p[i] );
    7588:	f852 1023 	ldr.w	r1, [r2, r3, lsl #2]
    for( j = 0; j < biL; j++ )
    758c:	2000      	movs	r0, #0
    mbedtls_mpi_uint mask = (mbedtls_mpi_uint) 1 << (biL - 1);
    758e:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
        if( x & mask ) break;
    7592:	4211      	tst	r1, r2
    7594:	d104      	bne.n	75a0 <mbedtls_mpi_bitlen+0x24>
    for( j = 0; j < biL; j++ )
    7596:	3001      	adds	r0, #1
    7598:	2820      	cmp	r0, #32
        mask >>= 1;
    759a:	ea4f 0252 	mov.w	r2, r2, lsr #1
    for( j = 0; j < biL; j++ )
    759e:	d1f8      	bne.n	7592 <mbedtls_mpi_bitlen+0x16>
    return( ( i * biL ) + j );
    75a0:	3301      	adds	r3, #1
    75a2:	ebc0 1043 	rsb	r0, r0, r3, lsl #5
}
    75a6:	4770      	bx	lr
        if( X->p[i] != 0 )
    75a8:	f852 1023 	ldr.w	r1, [r2, r3, lsl #2]
    75ac:	2900      	cmp	r1, #0
    75ae:	d1eb      	bne.n	7588 <mbedtls_mpi_bitlen+0xc>
    for( i = X->n - 1; i > 0; i-- )
    75b0:	3b01      	subs	r3, #1
    75b2:	e7e8      	b.n	7586 <mbedtls_mpi_bitlen+0xa>

000075b4 <mbedtls_mpi_size>:
{
    75b4:	b508      	push	{r3, lr}
    return( ( mbedtls_mpi_bitlen( X ) + 7 ) >> 3 );
    75b6:	f7ff ffe1 	bl	757c <mbedtls_mpi_bitlen>
    75ba:	3007      	adds	r0, #7
}
    75bc:	08c0      	lsrs	r0, r0, #3
    75be:	bd08      	pop	{r3, pc}

000075c0 <mbedtls_mpi_read_binary>:
{
    75c0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    size_t const limbs    = CHARS_TO_LIMBS( buflen );
    75c4:	f012 0403 	ands.w	r4, r2, #3
    75c8:	bf18      	it	ne
    75ca:	2401      	movne	r4, #1
    75cc:	eb04 0492 	add.w	r4, r4, r2, lsr #2
{
    75d0:	4688      	mov	r8, r1
    MBEDTLS_MPI_CHK( mbedtls_mpi_resize_clear( X, limbs ) );
    75d2:	4621      	mov	r1, r4
{
    75d4:	4607      	mov	r7, r0
    75d6:	4615      	mov	r5, r2
    MBEDTLS_MPI_CHK( mbedtls_mpi_resize_clear( X, limbs ) );
    75d8:	f7ff ff2a 	bl	7430 <mbedtls_mpi_resize_clear>
    75dc:	4606      	mov	r6, r0
    75de:	b968      	cbnz	r0, 75fc <mbedtls_mpi_read_binary+0x3c>
    if( buflen != 0 )
    75e0:	b165      	cbz	r5, 75fc <mbedtls_mpi_read_binary+0x3c>
        memcpy( Xp + overhead, buf, buflen );
    75e2:	68bb      	ldr	r3, [r7, #8]
    size_t const overhead = ( limbs * ciL ) - buflen;
    75e4:	ebc5 0084 	rsb	r0, r5, r4, lsl #2
        memcpy( Xp + overhead, buf, buflen );
    75e8:	462a      	mov	r2, r5
    75ea:	4641      	mov	r1, r8
    75ec:	4418      	add	r0, r3
    75ee:	f7fe ff7d 	bl	64ec <memcpy>
    if( limbs == 0 )
    75f2:	b11c      	cbz	r4, 75fc <mbedtls_mpi_read_binary+0x3c>
    75f4:	68b8      	ldr	r0, [r7, #8]
    75f6:	4621      	mov	r1, r4
    75f8:	f7ff feb3 	bl	7362 <mpi_bigendian_to_host.part.0>
}
    75fc:	4630      	mov	r0, r6
    75fe:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00007602 <mbedtls_mpi_write_binary>:
{
    7602:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    7604:	4604      	mov	r4, r0
    7606:	4608      	mov	r0, r1
    stored_bytes = X->n * ciL;
    7608:	6863      	ldr	r3, [r4, #4]
    if( stored_bytes < buflen )
    760a:	ebb2 0f83 	cmp.w	r2, r3, lsl #2
    stored_bytes = X->n * ciL;
    760e:	ea4f 0583 	mov.w	r5, r3, lsl #2
    if( stored_bytes < buflen )
    7612:	d91b      	bls.n	764c <mbedtls_mpi_write_binary+0x4a>
        p = buf + buflen - stored_bytes;
    7614:	1b52      	subs	r2, r2, r5
    7616:	188e      	adds	r6, r1, r2
        memset( buf, 0, buflen - stored_bytes );
    7618:	2100      	movs	r1, #0
    761a:	f7fe ff72 	bl	6502 <memset>
        p = buf + buflen - stored_bytes;
    761e:	4630      	mov	r0, r6
    7620:	462a      	mov	r2, r5
    for( i = 0; i < bytes_to_copy; i++ )
    7622:	1881      	adds	r1, r0, r2
    7624:	2300      	movs	r3, #0
    7626:	429a      	cmp	r2, r3
    7628:	d112      	bne.n	7650 <mbedtls_mpi_write_binary+0x4e>
    return( 0 );
    762a:	2000      	movs	r0, #0
}
    762c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
            if( GET_BYTE( X, i ) != 0 )
    762e:	68a7      	ldr	r7, [r4, #8]
    7630:	f023 0c03 	bic.w	ip, r3, #3
    7634:	f003 0103 	and.w	r1, r3, #3
    7638:	00ce      	lsls	r6, r1, #3
    763a:	f857 100c 	ldr.w	r1, [r7, ip]
    763e:	40f1      	lsrs	r1, r6
    7640:	b2c9      	uxtb	r1, r1
    7642:	b989      	cbnz	r1, 7668 <mbedtls_mpi_write_binary+0x66>
        for( i = bytes_to_copy; i < stored_bytes; i++ )
    7644:	3301      	adds	r3, #1
    7646:	42ab      	cmp	r3, r5
    7648:	d1f1      	bne.n	762e <mbedtls_mpi_write_binary+0x2c>
    764a:	e7ea      	b.n	7622 <mbedtls_mpi_write_binary+0x20>
    764c:	4613      	mov	r3, r2
    764e:	e7fa      	b.n	7646 <mbedtls_mpi_write_binary+0x44>
        p[bytes_to_copy - i - 1] = GET_BYTE( X, i );
    7650:	68a7      	ldr	r7, [r4, #8]
    7652:	f023 0603 	bic.w	r6, r3, #3
    7656:	f003 0003 	and.w	r0, r3, #3
    765a:	00c5      	lsls	r5, r0, #3
    765c:	59b8      	ldr	r0, [r7, r6]
    765e:	40e8      	lsrs	r0, r5
    7660:	f801 0d01 	strb.w	r0, [r1, #-1]!
    for( i = 0; i < bytes_to_copy; i++ )
    7664:	3301      	adds	r3, #1
    7666:	e7de      	b.n	7626 <mbedtls_mpi_write_binary+0x24>
                return( MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL );
    7668:	f06f 0007 	mvn.w	r0, #7
    766c:	e7de      	b.n	762c <mbedtls_mpi_write_binary+0x2a>

0000766e <mbedtls_mpi_shift_l>:
{
    766e:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    7670:	4605      	mov	r5, r0
    7672:	460e      	mov	r6, r1
    v0 = count / (biL    );
    7674:	094c      	lsrs	r4, r1, #5
    t1 = count & (biL - 1);
    7676:	f001 071f 	and.w	r7, r1, #31
    i = mbedtls_mpi_bitlen( X ) + count;
    767a:	f7ff ff7f 	bl	757c <mbedtls_mpi_bitlen>
    if( X->n * biL < i )
    767e:	686b      	ldr	r3, [r5, #4]
    i = mbedtls_mpi_bitlen( X ) + count;
    7680:	4430      	add	r0, r6
    if( X->n * biL < i )
    7682:	ebb0 1f43 	cmp.w	r0, r3, lsl #5
    7686:	d805      	bhi.n	7694 <mbedtls_mpi_shift_l+0x26>
    if( v0 > 0 )
    7688:	2e1f      	cmp	r6, #31
    768a:	d80f      	bhi.n	76ac <mbedtls_mpi_shift_l+0x3e>
    if( t1 > 0 )
    768c:	2f00      	cmp	r7, #0
    768e:	d13c      	bne.n	770a <mbedtls_mpi_shift_l+0x9c>
    ret = 0;
    7690:	2000      	movs	r0, #0
    7692:	e00a      	b.n	76aa <mbedtls_mpi_shift_l+0x3c>
        MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, BITS_TO_LIMBS( i ) ) );
    7694:	f010 011f 	ands.w	r1, r0, #31
    7698:	bf18      	it	ne
    769a:	2101      	movne	r1, #1
    769c:	eb01 1150 	add.w	r1, r1, r0, lsr #5
    76a0:	4628      	mov	r0, r5
    76a2:	f7ff fe9f 	bl	73e4 <mbedtls_mpi_grow>
    76a6:	2800      	cmp	r0, #0
    76a8:	d0ee      	beq.n	7688 <mbedtls_mpi_shift_l+0x1a>
}
    76aa:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        for( i = X->n; i > v0; i-- )
    76ac:	686b      	ldr	r3, [r5, #4]
    76ae:	f06f 0003 	mvn.w	r0, #3
    76b2:	009a      	lsls	r2, r3, #2
    76b4:	4360      	muls	r0, r4
    76b6:	4619      	mov	r1, r3
    76b8:	42a1      	cmp	r1, r4
    76ba:	f1a2 0204 	sub.w	r2, r2, #4
    76be:	d80c      	bhi.n	76da <mbedtls_mpi_shift_l+0x6c>
    76c0:	1ae2      	subs	r2, r4, r3
    76c2:	429c      	cmp	r4, r3
    76c4:	bf88      	it	hi
    76c6:	2200      	movhi	r2, #0
    76c8:	4413      	add	r3, r2
    76ca:	009b      	lsls	r3, r3, #2
            X->p[i - 1] = 0;
    76cc:	2200      	movs	r2, #0
        for( ; i > 0; i-- )
    76ce:	3b04      	subs	r3, #4
    76d0:	1d19      	adds	r1, r3, #4
    76d2:	d0db      	beq.n	768c <mbedtls_mpi_shift_l+0x1e>
            X->p[i - 1] = 0;
    76d4:	68a9      	ldr	r1, [r5, #8]
    76d6:	50ca      	str	r2, [r1, r3]
        for( ; i > 0; i-- )
    76d8:	e7f9      	b.n	76ce <mbedtls_mpi_shift_l+0x60>
            X->p[i - 1] = X->p[i - v0 - 1];
    76da:	68ae      	ldr	r6, [r5, #8]
    76dc:	eb06 0c02 	add.w	ip, r6, r2
        for( i = X->n; i > v0; i-- )
    76e0:	3901      	subs	r1, #1
            X->p[i - 1] = X->p[i - v0 - 1];
    76e2:	f85c c000 	ldr.w	ip, [ip, r0]
    76e6:	f846 c002 	str.w	ip, [r6, r2]
        for( i = X->n; i > v0; i-- )
    76ea:	e7e5      	b.n	76b8 <mbedtls_mpi_shift_l+0x4a>
            r1 = X->p[i] >> (biL - t1);
    76ec:	68a8      	ldr	r0, [r5, #8]
    76ee:	f850 1024 	ldr.w	r1, [r0, r4, lsl #2]
            X->p[i] <<= t1;
    76f2:	fa01 f307 	lsl.w	r3, r1, r7
            X->p[i] |= r0;
    76f6:	4313      	orrs	r3, r2
    76f8:	f840 3024 	str.w	r3, [r0, r4, lsl #2]
            r0 = r1;
    76fc:	fa21 f206 	lsr.w	r2, r1, r6
        for( i = v0; i < X->n; i++ )
    7700:	3401      	adds	r4, #1
    7702:	686b      	ldr	r3, [r5, #4]
    7704:	42a3      	cmp	r3, r4
    7706:	d8f1      	bhi.n	76ec <mbedtls_mpi_shift_l+0x7e>
    7708:	e7c2      	b.n	7690 <mbedtls_mpi_shift_l+0x22>
    mbedtls_mpi_uint r0 = 0, r1;
    770a:	2200      	movs	r2, #0
            r1 = X->p[i] >> (biL - t1);
    770c:	f1c7 0620 	rsb	r6, r7, #32
    7710:	e7f7      	b.n	7702 <mbedtls_mpi_shift_l+0x94>

00007712 <mbedtls_mpi_shift_r>:
    if( v0 > X->n || ( v0 == X->n && v1 > 0 ) )
    7712:	6843      	ldr	r3, [r0, #4]
{
    7714:	b4f0      	push	{r4, r5, r6, r7}
    v0 = count /  biL;
    7716:	094c      	lsrs	r4, r1, #5
    if( v0 > X->n || ( v0 == X->n && v1 > 0 ) )
    7718:	42a3      	cmp	r3, r4
    v1 = count & (biL - 1);
    771a:	f001 021f 	and.w	r2, r1, #31
    if( v0 > X->n || ( v0 == X->n && v1 > 0 ) )
    771e:	d301      	bcc.n	7724 <mbedtls_mpi_shift_r+0x12>
    7720:	d104      	bne.n	772c <mbedtls_mpi_shift_r+0x1a>
    7722:	b36a      	cbz	r2, 7780 <mbedtls_mpi_shift_r+0x6e>
}
    7724:	bcf0      	pop	{r4, r5, r6, r7}
        return mbedtls_mpi_lset( X, 0 );
    7726:	2100      	movs	r1, #0
    7728:	f7ff befb 	b.w	7522 <mbedtls_mpi_lset>
    if( v0 > 0 )
    772c:	291f      	cmp	r1, #31
    772e:	d829      	bhi.n	7784 <mbedtls_mpi_shift_r+0x72>
    if( v1 > 0 )
    7730:	b9aa      	cbnz	r2, 775e <mbedtls_mpi_shift_r+0x4c>
}
    7732:	2000      	movs	r0, #0
    7734:	bcf0      	pop	{r4, r5, r6, r7}
    7736:	4770      	bx	lr
            X->p[i] = X->p[i + v0];
    7738:	6885      	ldr	r5, [r0, #8]
    773a:	586e      	ldr	r6, [r5, r1]
    773c:	f845 6023 	str.w	r6, [r5, r3, lsl #2]
        for( i = 0; i < X->n - v0; i++ )
    7740:	3104      	adds	r1, #4
    7742:	3301      	adds	r3, #1
    7744:	6845      	ldr	r5, [r0, #4]
    7746:	1b2d      	subs	r5, r5, r4
    7748:	429d      	cmp	r5, r3
    774a:	d8f5      	bhi.n	7738 <mbedtls_mpi_shift_r+0x26>
            X->p[i] = 0;
    774c:	2400      	movs	r4, #0
        for( ; i < X->n; i++ )
    774e:	6841      	ldr	r1, [r0, #4]
    7750:	4299      	cmp	r1, r3
    7752:	d9ed      	bls.n	7730 <mbedtls_mpi_shift_r+0x1e>
            X->p[i] = 0;
    7754:	6881      	ldr	r1, [r0, #8]
    7756:	f841 4023 	str.w	r4, [r1, r3, lsl #2]
        for( ; i < X->n; i++ )
    775a:	3301      	adds	r3, #1
    775c:	e7f7      	b.n	774e <mbedtls_mpi_shift_r+0x3c>
        for( i = X->n; i > 0; i-- )
    775e:	6843      	ldr	r3, [r0, #4]
    mbedtls_mpi_uint r0 = 0, r1;
    7760:	2400      	movs	r4, #0
            r1 = X->p[i - 1] << (biL - v1);
    7762:	f1c2 0720 	rsb	r7, r2, #32
        for( i = X->n; i > 0; i-- )
    7766:	3b01      	subs	r3, #1
    7768:	d3e3      	bcc.n	7732 <mbedtls_mpi_shift_r+0x20>
            r1 = X->p[i - 1] << (biL - v1);
    776a:	6886      	ldr	r6, [r0, #8]
    776c:	f856 5023 	ldr.w	r5, [r6, r3, lsl #2]
            X->p[i - 1] >>= v1;
    7770:	fa25 f102 	lsr.w	r1, r5, r2
            X->p[i - 1] |= r0;
    7774:	4321      	orrs	r1, r4
    7776:	f846 1023 	str.w	r1, [r6, r3, lsl #2]
            r0 = r1;
    777a:	fa05 f407 	lsl.w	r4, r5, r7
    777e:	e7f2      	b.n	7766 <mbedtls_mpi_shift_r+0x54>
    if( v0 > 0 )
    7780:	291f      	cmp	r1, #31
    7782:	d9d6      	bls.n	7732 <mbedtls_mpi_shift_r+0x20>
    7784:	00a1      	lsls	r1, r4, #2
{
    7786:	2300      	movs	r3, #0
    7788:	e7dc      	b.n	7744 <mbedtls_mpi_shift_r+0x32>

0000778a <mbedtls_mpi_cmp_abs>:
{
    778a:	b530      	push	{r4, r5, lr}
    for( i = X->n; i > 0; i-- )
    778c:	6843      	ldr	r3, [r0, #4]
    778e:	b92b      	cbnz	r3, 779c <mbedtls_mpi_cmp_abs+0x12>
    for( j = Y->n; j > 0; j-- )
    7790:	684a      	ldr	r2, [r1, #4]
    7792:	b962      	cbnz	r2, 77ae <mbedtls_mpi_cmp_abs+0x24>
    if( i == 0 && j == 0 )
    7794:	1e18      	subs	r0, r3, #0
    7796:	bf18      	it	ne
    7798:	2001      	movne	r0, #1
    779a:	e028      	b.n	77ee <mbedtls_mpi_cmp_abs+0x64>
        if( X->p[i - 1] != 0 )
    779c:	6882      	ldr	r2, [r0, #8]
    779e:	eb02 0283 	add.w	r2, r2, r3, lsl #2
    77a2:	f852 2c04 	ldr.w	r2, [r2, #-4]
    77a6:	2a00      	cmp	r2, #0
    77a8:	d1f2      	bne.n	7790 <mbedtls_mpi_cmp_abs+0x6>
    for( i = X->n; i > 0; i-- )
    77aa:	3b01      	subs	r3, #1
    77ac:	e7ef      	b.n	778e <mbedtls_mpi_cmp_abs+0x4>
        if( Y->p[j - 1] != 0 )
    77ae:	688c      	ldr	r4, [r1, #8]
    77b0:	eb04 0582 	add.w	r5, r4, r2, lsl #2
    77b4:	f855 5c04 	ldr.w	r5, [r5, #-4]
    77b8:	b935      	cbnz	r5, 77c8 <mbedtls_mpi_cmp_abs+0x3e>
    for( j = Y->n; j > 0; j-- )
    77ba:	3a01      	subs	r2, #1
    77bc:	e7e9      	b.n	7792 <mbedtls_mpi_cmp_abs+0x8>
    if( i > j ) return(  1 );
    77be:	2001      	movs	r0, #1
    77c0:	e015      	b.n	77ee <mbedtls_mpi_cmp_abs+0x64>
    if( j > i ) return( -1 );
    77c2:	f04f 30ff 	mov.w	r0, #4294967295
    77c6:	e012      	b.n	77ee <mbedtls_mpi_cmp_abs+0x64>
    if( i == 0 && j == 0 )
    77c8:	2b00      	cmp	r3, #0
    77ca:	d0fa      	beq.n	77c2 <mbedtls_mpi_cmp_abs+0x38>
    if( i > j ) return(  1 );
    77cc:	4293      	cmp	r3, r2
    77ce:	d8f6      	bhi.n	77be <mbedtls_mpi_cmp_abs+0x34>
    if( j > i ) return( -1 );
    77d0:	d3f7      	bcc.n	77c2 <mbedtls_mpi_cmp_abs+0x38>
    77d2:	3b01      	subs	r3, #1
        if( X->p[i - 1] > Y->p[i - 1] ) return(  1 );
    77d4:	6882      	ldr	r2, [r0, #8]
    77d6:	f852 1023 	ldr.w	r1, [r2, r3, lsl #2]
    77da:	f854 2023 	ldr.w	r2, [r4, r3, lsl #2]
    77de:	4291      	cmp	r1, r2
    77e0:	d8ed      	bhi.n	77be <mbedtls_mpi_cmp_abs+0x34>
        if( X->p[i - 1] < Y->p[i - 1] ) return( -1 );
    77e2:	f103 33ff 	add.w	r3, r3, #4294967295
    77e6:	d3ec      	bcc.n	77c2 <mbedtls_mpi_cmp_abs+0x38>
    for( ; i > 0; i-- )
    77e8:	1c5a      	adds	r2, r3, #1
    77ea:	d1f3      	bne.n	77d4 <mbedtls_mpi_cmp_abs+0x4a>
    return( 0 );
    77ec:	2000      	movs	r0, #0
}
    77ee:	bd30      	pop	{r4, r5, pc}

000077f0 <mbedtls_mpi_cmp_mpi>:
{
    77f0:	b530      	push	{r4, r5, lr}
    for( i = X->n; i > 0; i-- )
    77f2:	6843      	ldr	r3, [r0, #4]
{
    77f4:	4602      	mov	r2, r0
    for( i = X->n; i > 0; i-- )
    77f6:	b923      	cbnz	r3, 7802 <mbedtls_mpi_cmp_mpi+0x12>
    for( j = Y->n; j > 0; j-- )
    77f8:	6848      	ldr	r0, [r1, #4]
    77fa:	b958      	cbnz	r0, 7814 <mbedtls_mpi_cmp_mpi+0x24>
    if( i == 0 && j == 0 )
    77fc:	2b00      	cmp	r3, #0
    77fe:	d136      	bne.n	786e <mbedtls_mpi_cmp_mpi+0x7e>
    7800:	e02f      	b.n	7862 <mbedtls_mpi_cmp_mpi+0x72>
        if( X->p[i - 1] != 0 )
    7802:	6890      	ldr	r0, [r2, #8]
    7804:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    7808:	f850 0c04 	ldr.w	r0, [r0, #-4]
    780c:	2800      	cmp	r0, #0
    780e:	d1f3      	bne.n	77f8 <mbedtls_mpi_cmp_mpi+0x8>
    for( i = X->n; i > 0; i-- )
    7810:	3b01      	subs	r3, #1
    7812:	e7f0      	b.n	77f6 <mbedtls_mpi_cmp_mpi+0x6>
        if( Y->p[j - 1] != 0 )
    7814:	688c      	ldr	r4, [r1, #8]
    7816:	eb04 0580 	add.w	r5, r4, r0, lsl #2
    781a:	f855 5c04 	ldr.w	r5, [r5, #-4]
    781e:	bb15      	cbnz	r5, 7866 <mbedtls_mpi_cmp_mpi+0x76>
    for( j = Y->n; j > 0; j-- )
    7820:	3801      	subs	r0, #1
    7822:	e7ea      	b.n	77fa <mbedtls_mpi_cmp_mpi+0xa>
    if( j > i ) return( -Y->s );
    7824:	d202      	bcs.n	782c <mbedtls_mpi_cmp_mpi+0x3c>
    7826:	6808      	ldr	r0, [r1, #0]
        if( X->p[i - 1] < Y->p[i - 1] ) return( -X->s );
    7828:	4240      	negs	r0, r0
    782a:	e021      	b.n	7870 <mbedtls_mpi_cmp_mpi+0x80>
    if( X->s > 0 && Y->s < 0 ) return(  1 );
    782c:	6810      	ldr	r0, [r2, #0]
    if( j > i ) return( -Y->s );
    782e:	6809      	ldr	r1, [r1, #0]
    if( X->s > 0 && Y->s < 0 ) return(  1 );
    7830:	2800      	cmp	r0, #0
    7832:	dd03      	ble.n	783c <mbedtls_mpi_cmp_mpi+0x4c>
    7834:	2900      	cmp	r1, #0
    7836:	da07      	bge.n	7848 <mbedtls_mpi_cmp_mpi+0x58>
    7838:	2001      	movs	r0, #1
    783a:	e019      	b.n	7870 <mbedtls_mpi_cmp_mpi+0x80>
    if( Y->s > 0 && X->s < 0 ) return( -1 );
    783c:	2900      	cmp	r1, #0
    783e:	dd03      	ble.n	7848 <mbedtls_mpi_cmp_mpi+0x58>
    7840:	b110      	cbz	r0, 7848 <mbedtls_mpi_cmp_mpi+0x58>
    7842:	f04f 30ff 	mov.w	r0, #4294967295
    7846:	e013      	b.n	7870 <mbedtls_mpi_cmp_mpi+0x80>
    7848:	3b01      	subs	r3, #1
        if( X->p[i - 1] > Y->p[i - 1] ) return(  X->s );
    784a:	6891      	ldr	r1, [r2, #8]
    784c:	f851 5023 	ldr.w	r5, [r1, r3, lsl #2]
    7850:	f854 1023 	ldr.w	r1, [r4, r3, lsl #2]
    7854:	428d      	cmp	r5, r1
    7856:	d80b      	bhi.n	7870 <mbedtls_mpi_cmp_mpi+0x80>
        if( X->p[i - 1] < Y->p[i - 1] ) return( -X->s );
    7858:	f103 33ff 	add.w	r3, r3, #4294967295
    785c:	d3e4      	bcc.n	7828 <mbedtls_mpi_cmp_mpi+0x38>
    for( ; i > 0; i-- )
    785e:	1c59      	adds	r1, r3, #1
    7860:	d1f3      	bne.n	784a <mbedtls_mpi_cmp_mpi+0x5a>
    return( 0 );
    7862:	2000      	movs	r0, #0
    7864:	e004      	b.n	7870 <mbedtls_mpi_cmp_mpi+0x80>
    if( i == 0 && j == 0 )
    7866:	2b00      	cmp	r3, #0
    7868:	d0dd      	beq.n	7826 <mbedtls_mpi_cmp_mpi+0x36>
    if( i > j ) return(  X->s );
    786a:	4283      	cmp	r3, r0
    786c:	d9da      	bls.n	7824 <mbedtls_mpi_cmp_mpi+0x34>
    786e:	6810      	ldr	r0, [r2, #0]
}
    7870:	bd30      	pop	{r4, r5, pc}

00007872 <mbedtls_mpi_cmp_int>:
{
    7872:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    *p  = ( z < 0 ) ? -z : z;
    7874:	ea81 73e1 	eor.w	r3, r1, r1, asr #31
    7878:	eba3 73e1 	sub.w	r3, r3, r1, asr #31
    Y.s = ( z < 0 ) ? -1 : 1;
    787c:	2900      	cmp	r1, #0
    *p  = ( z < 0 ) ? -z : z;
    787e:	9300      	str	r3, [sp, #0]
    Y.s = ( z < 0 ) ? -1 : 1;
    7880:	bfb4      	ite	lt
    7882:	f04f 33ff 	movlt.w	r3, #4294967295
    7886:	2301      	movge	r3, #1
    7888:	9301      	str	r3, [sp, #4]
    return( mbedtls_mpi_cmp_mpi( X, &Y ) );
    788a:	a901      	add	r1, sp, #4
    Y.n = 1;
    788c:	2301      	movs	r3, #1
    788e:	9302      	str	r3, [sp, #8]
    Y.p = p;
    7890:	f8cd d00c 	str.w	sp, [sp, #12]
    return( mbedtls_mpi_cmp_mpi( X, &Y ) );
    7894:	f7ff ffac 	bl	77f0 <mbedtls_mpi_cmp_mpi>
}
    7898:	b005      	add	sp, #20
    789a:	f85d fb04 	ldr.w	pc, [sp], #4

0000789e <mbedtls_mpi_add_abs>:
    if( X == B )
    789e:	4290      	cmp	r0, r2
{
    78a0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    78a4:	4606      	mov	r6, r0
    78a6:	460f      	mov	r7, r1
    78a8:	4615      	mov	r5, r2
    if( X == B )
    78aa:	d002      	beq.n	78b2 <mbedtls_mpi_add_abs+0x14>
    if( X != A )
    78ac:	4288      	cmp	r0, r1
    78ae:	d129      	bne.n	7904 <mbedtls_mpi_add_abs+0x66>
{
    78b0:	462f      	mov	r7, r5
    X->s = 1;
    78b2:	2301      	movs	r3, #1
    for( j = B->n; j > 0; j-- )
    78b4:	687d      	ldr	r5, [r7, #4]
    X->s = 1;
    78b6:	6033      	str	r3, [r6, #0]
    for( j = B->n; j > 0; j-- )
    78b8:	bb65      	cbnz	r5, 7914 <mbedtls_mpi_add_abs+0x76>
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, j ) );
    78ba:	4629      	mov	r1, r5
    78bc:	4630      	mov	r0, r6
    78be:	f7ff fd91 	bl	73e4 <mbedtls_mpi_grow>
    78c2:	4604      	mov	r4, r0
    78c4:	bb18      	cbnz	r0, 790e <mbedtls_mpi_add_abs+0x70>
    o = B->p; p = X->p; c = 0;
    78c6:	68b3      	ldr	r3, [r6, #8]
    78c8:	68b9      	ldr	r1, [r7, #8]
    78ca:	469c      	mov	ip, r3
    78cc:	4607      	mov	r7, r0
    for( i = 0; i < j; i++, o++, p++ )
    78ce:	4285      	cmp	r5, r0
    78d0:	d129      	bne.n	7926 <mbedtls_mpi_add_abs+0x88>
    78d2:	eb03 0385 	add.w	r3, r3, r5, lsl #2
    while( c != 0 )
    78d6:	b1d7      	cbz	r7, 790e <mbedtls_mpi_add_abs+0x70>
        if( i >= X->n )
    78d8:	6872      	ldr	r2, [r6, #4]
    78da:	42aa      	cmp	r2, r5
    78dc:	f105 0801 	add.w	r8, r5, #1
    78e0:	d807      	bhi.n	78f2 <mbedtls_mpi_add_abs+0x54>
            MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, i + 1 ) );
    78e2:	4641      	mov	r1, r8
    78e4:	4630      	mov	r0, r6
    78e6:	f7ff fd7d 	bl	73e4 <mbedtls_mpi_grow>
    78ea:	bb68      	cbnz	r0, 7948 <mbedtls_mpi_add_abs+0xaa>
            p = X->p + i;
    78ec:	68b3      	ldr	r3, [r6, #8]
    78ee:	eb03 0385 	add.w	r3, r3, r5, lsl #2
        *p += c; c = ( *p < c ); i++; p++;
    78f2:	681a      	ldr	r2, [r3, #0]
    78f4:	19d2      	adds	r2, r2, r7
    78f6:	f843 2b04 	str.w	r2, [r3], #4
    78fa:	bf2c      	ite	cs
    78fc:	2701      	movcs	r7, #1
    78fe:	2700      	movcc	r7, #0
    7900:	4645      	mov	r5, r8
    7902:	e7e8      	b.n	78d6 <mbedtls_mpi_add_abs+0x38>
        MBEDTLS_MPI_CHK( mbedtls_mpi_copy( X, A ) );
    7904:	f7ff fdaf 	bl	7466 <mbedtls_mpi_copy>
    7908:	4604      	mov	r4, r0
    790a:	2800      	cmp	r0, #0
    790c:	d0d0      	beq.n	78b0 <mbedtls_mpi_add_abs+0x12>
}
    790e:	4620      	mov	r0, r4
    7910:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        if( B->p[j - 1] != 0 )
    7914:	68bb      	ldr	r3, [r7, #8]
    7916:	eb03 0385 	add.w	r3, r3, r5, lsl #2
    791a:	f853 3c04 	ldr.w	r3, [r3, #-4]
    791e:	2b00      	cmp	r3, #0
    7920:	d1cb      	bne.n	78ba <mbedtls_mpi_add_abs+0x1c>
    for( j = B->n; j > 0; j-- )
    7922:	3d01      	subs	r5, #1
    7924:	e7c8      	b.n	78b8 <mbedtls_mpi_add_abs+0x1a>
        *p +=  c; c  = ( *p <  c );
    7926:	f8dc 2000 	ldr.w	r2, [ip]
    792a:	19d2      	adds	r2, r2, r7
    792c:	f851 7020 	ldr.w	r7, [r1, r0, lsl #2]
    7930:	bf2c      	ite	cs
    7932:	f04f 0e01 	movcs.w	lr, #1
    7936:	f04f 0e00 	movcc.w	lr, #0
        *p += tmp; c += ( *p < tmp );
    793a:	19d2      	adds	r2, r2, r7
    793c:	f84c 2b04 	str.w	r2, [ip], #4
    7940:	f14e 0700 	adc.w	r7, lr, #0
    for( i = 0; i < j; i++, o++, p++ )
    7944:	3001      	adds	r0, #1
    7946:	e7c2      	b.n	78ce <mbedtls_mpi_add_abs+0x30>
    return( ret );
    7948:	4604      	mov	r4, r0
    794a:	e7e0      	b.n	790e <mbedtls_mpi_add_abs+0x70>

0000794c <mbedtls_mpi_sub_abs>:
{
    794c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    for( n = B->n; n > 0; n-- )
    7950:	6854      	ldr	r4, [r2, #4]
{
    7952:	4605      	mov	r5, r0
    7954:	460e      	mov	r6, r1
    7956:	4690      	mov	r8, r2
    for( n = B->n; n > 0; n-- )
    7958:	b93c      	cbnz	r4, 796a <mbedtls_mpi_sub_abs+0x1e>
    if( n > A->n )
    795a:	6871      	ldr	r1, [r6, #4]
    795c:	42a1      	cmp	r1, r4
    795e:	d20e      	bcs.n	797e <mbedtls_mpi_sub_abs+0x32>
        ret = MBEDTLS_ERR_MPI_NEGATIVE_VALUE;
    7960:	f06f 0709 	mvn.w	r7, #9
}
    7964:	4638      	mov	r0, r7
    7966:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        if( B->p[n - 1] != 0 )
    796a:	f8d8 3008 	ldr.w	r3, [r8, #8]
    796e:	eb03 0384 	add.w	r3, r3, r4, lsl #2
    7972:	f853 3c04 	ldr.w	r3, [r3, #-4]
    7976:	2b00      	cmp	r3, #0
    7978:	d1ef      	bne.n	795a <mbedtls_mpi_sub_abs+0xe>
    for( n = B->n; n > 0; n-- )
    797a:	3c01      	subs	r4, #1
    797c:	e7ec      	b.n	7958 <mbedtls_mpi_sub_abs+0xc>
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, A->n ) );
    797e:	4628      	mov	r0, r5
    7980:	f7ff fd30 	bl	73e4 <mbedtls_mpi_grow>
    7984:	4607      	mov	r7, r0
    7986:	2800      	cmp	r0, #0
    7988:	d1ec      	bne.n	7964 <mbedtls_mpi_sub_abs+0x18>
    if( A->n > n )
    798a:	6872      	ldr	r2, [r6, #4]
    798c:	42a2      	cmp	r2, r4
    798e:	d909      	bls.n	79a4 <mbedtls_mpi_sub_abs+0x58>
        memcpy( X->p + n, A->p + n, ( A->n - n ) * ciL );
    7990:	68b1      	ldr	r1, [r6, #8]
    7992:	68a8      	ldr	r0, [r5, #8]
    7994:	1b12      	subs	r2, r2, r4
    7996:	0092      	lsls	r2, r2, #2
    7998:	eb01 0184 	add.w	r1, r1, r4, lsl #2
    799c:	eb00 0084 	add.w	r0, r0, r4, lsl #2
    79a0:	f7fe fda4 	bl	64ec <memcpy>
    if( X->n > A->n )
    79a4:	686a      	ldr	r2, [r5, #4]
    79a6:	6870      	ldr	r0, [r6, #4]
    79a8:	4282      	cmp	r2, r0
    79aa:	d907      	bls.n	79bc <mbedtls_mpi_sub_abs+0x70>
        memset( X->p + A->n, 0, ( X->n - A->n ) * ciL );
    79ac:	68ab      	ldr	r3, [r5, #8]
    79ae:	1a12      	subs	r2, r2, r0
    79b0:	0092      	lsls	r2, r2, #2
    79b2:	2100      	movs	r1, #0
    79b4:	eb03 0080 	add.w	r0, r3, r0, lsl #2
    79b8:	f7fe fda3 	bl	6502 <memset>
    mbedtls_mpi_uint c = 0, t, z;
    79bc:	2200      	movs	r2, #0
    carry = mpi_sub_hlp( n, X->p, A->p, B->p );
    79be:	68a9      	ldr	r1, [r5, #8]
    79c0:	f8d6 e008 	ldr.w	lr, [r6, #8]
    79c4:	f8d8 8008 	ldr.w	r8, [r8, #8]
    for( i = 0; i < n; i++ )
    79c8:	4613      	mov	r3, r2
    79ca:	429c      	cmp	r4, r3
    79cc:	d111      	bne.n	79f2 <mbedtls_mpi_sub_abs+0xa6>
    if( carry != 0 )
    79ce:	b16a      	cbz	r2, 79ec <mbedtls_mpi_sub_abs+0xa0>
    79d0:	eb01 0384 	add.w	r3, r1, r4, lsl #2
            --X->p[n];
    79d4:	f04f 30ff 	mov.w	r0, #4294967295
        for( ; n < X->n && X->p[n] == 0; n++ )
    79d8:	686a      	ldr	r2, [r5, #4]
    79da:	42a2      	cmp	r2, r4
    79dc:	d923      	bls.n	7a26 <mbedtls_mpi_sub_abs+0xda>
    79de:	681a      	ldr	r2, [r3, #0]
    79e0:	b1ea      	cbz	r2, 7a1e <mbedtls_mpi_sub_abs+0xd2>
        --X->p[n];
    79e2:	f851 3024 	ldr.w	r3, [r1, r4, lsl #2]
    79e6:	3b01      	subs	r3, #1
    79e8:	f841 3024 	str.w	r3, [r1, r4, lsl #2]
    X->s = 1;
    79ec:	2301      	movs	r3, #1
    79ee:	602b      	str	r3, [r5, #0]
    return( ret );
    79f0:	e7b8      	b.n	7964 <mbedtls_mpi_sub_abs+0x18>
        z = ( l[i] <  c );    t = l[i] - c;
    79f2:	f85e c023 	ldr.w	ip, [lr, r3, lsl #2]
        c = ( t < r[i] ) + z; d[i] = t - r[i];
    79f6:	f858 6023 	ldr.w	r6, [r8, r3, lsl #2]
        z = ( l[i] <  c );    t = l[i] - c;
    79fa:	ebac 0002 	sub.w	r0, ip, r2
        c = ( t < r[i] ) + z; d[i] = t - r[i];
    79fe:	42b0      	cmp	r0, r6
    7a00:	bf2c      	ite	cs
    7a02:	f04f 0900 	movcs.w	r9, #0
    7a06:	f04f 0901 	movcc.w	r9, #1
    7a0a:	1b80      	subs	r0, r0, r6
    7a0c:	f841 0023 	str.w	r0, [r1, r3, lsl #2]
    7a10:	4594      	cmp	ip, r2
    7a12:	bf2c      	ite	cs
    7a14:	464a      	movcs	r2, r9
    7a16:	f109 0201 	addcc.w	r2, r9, #1
    for( i = 0; i < n; i++ )
    7a1a:	3301      	adds	r3, #1
    7a1c:	e7d5      	b.n	79ca <mbedtls_mpi_sub_abs+0x7e>
            --X->p[n];
    7a1e:	f843 0b04 	str.w	r0, [r3], #4
        for( ; n < X->n && X->p[n] == 0; n++ )
    7a22:	3401      	adds	r4, #1
    7a24:	e7d8      	b.n	79d8 <mbedtls_mpi_sub_abs+0x8c>
        if( n == X->n )
    7a26:	d1dc      	bne.n	79e2 <mbedtls_mpi_sub_abs+0x96>
    7a28:	e79a      	b.n	7960 <mbedtls_mpi_sub_abs+0x14>

00007a2a <mbedtls_mpi_add_mpi>:
{
    7a2a:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    s = A->s;
    7a2c:	680d      	ldr	r5, [r1, #0]
    if( A->s * B->s < 0 )
    7a2e:	6813      	ldr	r3, [r2, #0]
    7a30:	436b      	muls	r3, r5
{
    7a32:	4604      	mov	r4, r0
    7a34:	460f      	mov	r7, r1
    7a36:	4616      	mov	r6, r2
    if( A->s * B->s < 0 )
    7a38:	d516      	bpl.n	7a68 <mbedtls_mpi_add_mpi+0x3e>
        if( mbedtls_mpi_cmp_abs( A, B ) >= 0 )
    7a3a:	4611      	mov	r1, r2
    7a3c:	4638      	mov	r0, r7
    7a3e:	f7ff fea4 	bl	778a <mbedtls_mpi_cmp_abs>
    7a42:	2800      	cmp	r0, #0
    7a44:	db06      	blt.n	7a54 <mbedtls_mpi_add_mpi+0x2a>
            MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( X, A, B ) );
    7a46:	4632      	mov	r2, r6
    7a48:	4639      	mov	r1, r7
    7a4a:	4620      	mov	r0, r4
    7a4c:	f7ff ff7e 	bl	794c <mbedtls_mpi_sub_abs>
        MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( X, A, B ) );
    7a50:	b140      	cbz	r0, 7a64 <mbedtls_mpi_add_mpi+0x3a>
}
    7a52:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
            MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( X, B, A ) );
    7a54:	463a      	mov	r2, r7
    7a56:	4631      	mov	r1, r6
    7a58:	4620      	mov	r0, r4
    7a5a:	f7ff ff77 	bl	794c <mbedtls_mpi_sub_abs>
    7a5e:	2800      	cmp	r0, #0
    7a60:	d1f7      	bne.n	7a52 <mbedtls_mpi_add_mpi+0x28>
            X->s = -s;
    7a62:	426d      	negs	r5, r5
        X->s = s;
    7a64:	6025      	str	r5, [r4, #0]
    return( ret );
    7a66:	e7f4      	b.n	7a52 <mbedtls_mpi_add_mpi+0x28>
        MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( X, A, B ) );
    7a68:	f7ff ff19 	bl	789e <mbedtls_mpi_add_abs>
    7a6c:	e7f0      	b.n	7a50 <mbedtls_mpi_add_mpi+0x26>

00007a6e <mbedtls_mpi_sub_mpi>:
{
    7a6e:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    s = A->s;
    7a70:	680d      	ldr	r5, [r1, #0]
    if( A->s * B->s > 0 )
    7a72:	6813      	ldr	r3, [r2, #0]
    7a74:	436b      	muls	r3, r5
    7a76:	2b00      	cmp	r3, #0
{
    7a78:	4604      	mov	r4, r0
    7a7a:	460f      	mov	r7, r1
    7a7c:	4616      	mov	r6, r2
    if( A->s * B->s > 0 )
    7a7e:	dd16      	ble.n	7aae <mbedtls_mpi_sub_mpi+0x40>
        if( mbedtls_mpi_cmp_abs( A, B ) >= 0 )
    7a80:	4611      	mov	r1, r2
    7a82:	4638      	mov	r0, r7
    7a84:	f7ff fe81 	bl	778a <mbedtls_mpi_cmp_abs>
    7a88:	2800      	cmp	r0, #0
    7a8a:	db06      	blt.n	7a9a <mbedtls_mpi_sub_mpi+0x2c>
            MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( X, A, B ) );
    7a8c:	4632      	mov	r2, r6
    7a8e:	4639      	mov	r1, r7
    7a90:	4620      	mov	r0, r4
    7a92:	f7ff ff5b 	bl	794c <mbedtls_mpi_sub_abs>
        MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( X, A, B ) );
    7a96:	b140      	cbz	r0, 7aaa <mbedtls_mpi_sub_mpi+0x3c>
}
    7a98:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
            MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( X, B, A ) );
    7a9a:	463a      	mov	r2, r7
    7a9c:	4631      	mov	r1, r6
    7a9e:	4620      	mov	r0, r4
    7aa0:	f7ff ff54 	bl	794c <mbedtls_mpi_sub_abs>
    7aa4:	2800      	cmp	r0, #0
    7aa6:	d1f7      	bne.n	7a98 <mbedtls_mpi_sub_mpi+0x2a>
            X->s = -s;
    7aa8:	426d      	negs	r5, r5
        X->s = s;
    7aaa:	6025      	str	r5, [r4, #0]
    return( ret );
    7aac:	e7f4      	b.n	7a98 <mbedtls_mpi_sub_mpi+0x2a>
        MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( X, A, B ) );
    7aae:	f7ff fef6 	bl	789e <mbedtls_mpi_add_abs>
    7ab2:	e7f0      	b.n	7a96 <mbedtls_mpi_sub_mpi+0x28>

00007ab4 <mbedtls_mpi_mul_int>:
{
    7ab4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    size_t n = A->n;
    7ab8:	684e      	ldr	r6, [r1, #4]
{
    7aba:	4605      	mov	r5, r0
    7abc:	460f      	mov	r7, r1
    7abe:	4690      	mov	r8, r2
    while( n > 0 && A->p[n - 1] == 0 )
    7ac0:	b146      	cbz	r6, 7ad4 <mbedtls_mpi_mul_int+0x20>
    7ac2:	68bb      	ldr	r3, [r7, #8]
    7ac4:	eb03 0386 	add.w	r3, r3, r6, lsl #2
    7ac8:	f853 3c04 	ldr.w	r3, [r3, #-4]
    7acc:	b143      	cbz	r3, 7ae0 <mbedtls_mpi_mul_int+0x2c>
    if( b == 0 || n == 0 )
    7ace:	f1b8 0f00 	cmp.w	r8, #0
    7ad2:	d107      	bne.n	7ae4 <mbedtls_mpi_mul_int+0x30>
        return( mbedtls_mpi_lset( X, 0 ) );
    7ad4:	4628      	mov	r0, r5
    7ad6:	2100      	movs	r1, #0
}
    7ad8:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
        return( mbedtls_mpi_lset( X, 0 ) );
    7adc:	f7ff bd21 	b.w	7522 <mbedtls_mpi_lset>
        --n;
    7ae0:	3e01      	subs	r6, #1
    7ae2:	e7ed      	b.n	7ac0 <mbedtls_mpi_mul_int+0xc>
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, n + 1 ) );
    7ae4:	1c71      	adds	r1, r6, #1
    7ae6:	4628      	mov	r0, r5
    7ae8:	f7ff fc7c 	bl	73e4 <mbedtls_mpi_grow>
    7aec:	4604      	mov	r4, r0
    7aee:	b960      	cbnz	r0, 7b0a <mbedtls_mpi_mul_int+0x56>
    MBEDTLS_MPI_CHK( mbedtls_mpi_copy( X, A ) );
    7af0:	4639      	mov	r1, r7
    7af2:	4628      	mov	r0, r5
    7af4:	f7ff fcb7 	bl	7466 <mbedtls_mpi_copy>
    7af8:	4604      	mov	r4, r0
    7afa:	b930      	cbnz	r0, 7b0a <mbedtls_mpi_mul_int+0x56>
    mpi_mul_hlp( n, A->p, X->p, b - 1 );
    7afc:	68aa      	ldr	r2, [r5, #8]
    7afe:	68b9      	ldr	r1, [r7, #8]
    7b00:	f108 33ff 	add.w	r3, r8, #4294967295
    7b04:	4630      	mov	r0, r6
    7b06:	f7ff fa1a 	bl	6f3e <mpi_mul_hlp>
}
    7b0a:	4620      	mov	r0, r4
    7b0c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00007b10 <mbedtls_mpi_div_mpi>:
{
    7b10:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    7b14:	b099      	sub	sp, #100	; 0x64
    7b16:	4688      	mov	r8, r1
    7b18:	9000      	str	r0, [sp, #0]
    if( mbedtls_mpi_cmp_int( B, 0 ) == 0 )
    7b1a:	2100      	movs	r1, #0
    7b1c:	4618      	mov	r0, r3
{
    7b1e:	4616      	mov	r6, r2
    7b20:	9301      	str	r3, [sp, #4]
    if( mbedtls_mpi_cmp_int( B, 0 ) == 0 )
    7b22:	f7ff fea6 	bl	7872 <mbedtls_mpi_cmp_int>
    7b26:	2800      	cmp	r0, #0
    7b28:	f000 8194 	beq.w	7e54 <mbedtls_mpi_div_mpi+0x344>
    T2.n = sizeof( TP2 ) / sizeof( *TP2 );
    7b2c:	2303      	movs	r3, #3
    X->n = 0;
    7b2e:	2400      	movs	r4, #0
    7b30:	2501      	movs	r5, #1
    T2.n = sizeof( TP2 ) / sizeof( *TP2 );
    7b32:	9313      	str	r3, [sp, #76]	; 0x4c
    if( mbedtls_mpi_cmp_abs( A, B ) < 0 )
    7b34:	9901      	ldr	r1, [sp, #4]
    T2.s = 1;
    7b36:	9512      	str	r5, [sp, #72]	; 0x48
    T2.p = TP2;
    7b38:	ab15      	add	r3, sp, #84	; 0x54
    if( mbedtls_mpi_cmp_abs( A, B ) < 0 )
    7b3a:	4630      	mov	r0, r6
    X->n = 0;
    7b3c:	e9cd 5406 	strd	r5, r4, [sp, #24]
    X->s = 1;
    7b40:	e9cd 4508 	strd	r4, r5, [sp, #32]
    X->p = NULL;
    7b44:	e9cd 440a 	strd	r4, r4, [sp, #40]	; 0x28
    X->n = 0;
    7b48:	e9cd 540c 	strd	r5, r4, [sp, #48]	; 0x30
    X->s = 1;
    7b4c:	e9cd 450e 	strd	r4, r5, [sp, #56]	; 0x38
    X->p = NULL;
    7b50:	e9cd 4410 	strd	r4, r4, [sp, #64]	; 0x40
    T2.p = TP2;
    7b54:	9314      	str	r3, [sp, #80]	; 0x50
    if( mbedtls_mpi_cmp_abs( A, B ) < 0 )
    7b56:	f7ff fe18 	bl	778a <mbedtls_mpi_cmp_abs>
    7b5a:	42a0      	cmp	r0, r4
    7b5c:	da29      	bge.n	7bb2 <mbedtls_mpi_div_mpi+0xa2>
        if( Q != NULL ) MBEDTLS_MPI_CHK( mbedtls_mpi_lset( Q, 0 ) );
    7b5e:	9b00      	ldr	r3, [sp, #0]
    7b60:	b93b      	cbnz	r3, 7b72 <mbedtls_mpi_div_mpi+0x62>
        if( R != NULL ) MBEDTLS_MPI_CHK( mbedtls_mpi_copy( R, A ) );
    7b62:	f1b8 0f00 	cmp.w	r8, #0
    7b66:	d11c      	bne.n	7ba2 <mbedtls_mpi_div_mpi+0x92>
        return( 0 );
    7b68:	2400      	movs	r4, #0
}
    7b6a:	4620      	mov	r0, r4
    7b6c:	b019      	add	sp, #100	; 0x64
    7b6e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        if( Q != NULL ) MBEDTLS_MPI_CHK( mbedtls_mpi_lset( Q, 0 ) );
    7b72:	4621      	mov	r1, r4
    7b74:	9800      	ldr	r0, [sp, #0]
    7b76:	f7ff fcd4 	bl	7522 <mbedtls_mpi_lset>
    7b7a:	4604      	mov	r4, r0
    7b7c:	2800      	cmp	r0, #0
    7b7e:	d0f0      	beq.n	7b62 <mbedtls_mpi_div_mpi+0x52>
    mbedtls_mpi_free( &X ); mbedtls_mpi_free( &Y ); mbedtls_mpi_free( &Z );
    7b80:	a806      	add	r0, sp, #24
    7b82:	f7ff fc1d 	bl	73c0 <mbedtls_mpi_free>
    7b86:	a809      	add	r0, sp, #36	; 0x24
    7b88:	f7ff fc1a 	bl	73c0 <mbedtls_mpi_free>
    7b8c:	a80c      	add	r0, sp, #48	; 0x30
    7b8e:	f7ff fc17 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &T1 );
    7b92:	a80f      	add	r0, sp, #60	; 0x3c
    7b94:	f7ff fc14 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_platform_zeroize( TP2, sizeof( TP2 ) );
    7b98:	210c      	movs	r1, #12
    7b9a:	a815      	add	r0, sp, #84	; 0x54
    7b9c:	f7fc fc26 	bl	43ec <mbedtls_platform_zeroize>
    return( ret );
    7ba0:	e7e3      	b.n	7b6a <mbedtls_mpi_div_mpi+0x5a>
        if( R != NULL ) MBEDTLS_MPI_CHK( mbedtls_mpi_copy( R, A ) );
    7ba2:	4631      	mov	r1, r6
    7ba4:	4640      	mov	r0, r8
    7ba6:	f7ff fc5e 	bl	7466 <mbedtls_mpi_copy>
    7baa:	4604      	mov	r4, r0
    7bac:	2800      	cmp	r0, #0
    7bae:	d1e7      	bne.n	7b80 <mbedtls_mpi_div_mpi+0x70>
    7bb0:	e7da      	b.n	7b68 <mbedtls_mpi_div_mpi+0x58>
    MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &X, A ) );
    7bb2:	4631      	mov	r1, r6
    7bb4:	a806      	add	r0, sp, #24
    7bb6:	f7ff fc56 	bl	7466 <mbedtls_mpi_copy>
    7bba:	4604      	mov	r4, r0
    7bbc:	2800      	cmp	r0, #0
    7bbe:	d1df      	bne.n	7b80 <mbedtls_mpi_div_mpi+0x70>
    MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &Y, B ) );
    7bc0:	af09      	add	r7, sp, #36	; 0x24
    7bc2:	9901      	ldr	r1, [sp, #4]
    7bc4:	4638      	mov	r0, r7
    7bc6:	f7ff fc4e 	bl	7466 <mbedtls_mpi_copy>
    7bca:	4604      	mov	r4, r0
    7bcc:	2800      	cmp	r0, #0
    7bce:	d1d7      	bne.n	7b80 <mbedtls_mpi_div_mpi+0x70>
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &Z, A->n + 2 ) );
    7bd0:	6871      	ldr	r1, [r6, #4]
    X.s = Y.s = 1;
    7bd2:	9509      	str	r5, [sp, #36]	; 0x24
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &Z, A->n + 2 ) );
    7bd4:	3102      	adds	r1, #2
    7bd6:	a80c      	add	r0, sp, #48	; 0x30
    X.s = Y.s = 1;
    7bd8:	9506      	str	r5, [sp, #24]
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &Z, A->n + 2 ) );
    7bda:	f7ff fc03 	bl	73e4 <mbedtls_mpi_grow>
    7bde:	4604      	mov	r4, r0
    7be0:	2800      	cmp	r0, #0
    7be2:	d1cd      	bne.n	7b80 <mbedtls_mpi_div_mpi+0x70>
    MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &Z,  0 ) );
    7be4:	4601      	mov	r1, r0
    7be6:	a80c      	add	r0, sp, #48	; 0x30
    7be8:	f7ff fc9b 	bl	7522 <mbedtls_mpi_lset>
    7bec:	4604      	mov	r4, r0
    7bee:	2800      	cmp	r0, #0
    7bf0:	d1c6      	bne.n	7b80 <mbedtls_mpi_div_mpi+0x70>
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &T1, A->n + 2 ) );
    7bf2:	6871      	ldr	r1, [r6, #4]
    7bf4:	a80f      	add	r0, sp, #60	; 0x3c
    7bf6:	3102      	adds	r1, #2
    7bf8:	f7ff fbf4 	bl	73e4 <mbedtls_mpi_grow>
    7bfc:	4604      	mov	r4, r0
    7bfe:	2800      	cmp	r0, #0
    7c00:	d1be      	bne.n	7b80 <mbedtls_mpi_div_mpi+0x70>
    k = mbedtls_mpi_bitlen( &Y ) % biL;
    7c02:	4638      	mov	r0, r7
    7c04:	f7ff fcba 	bl	757c <mbedtls_mpi_bitlen>
    7c08:	f000 001f 	and.w	r0, r0, #31
    if( k < biL - 1 )
    7c0c:	281f      	cmp	r0, #31
    7c0e:	d073      	beq.n	7cf8 <mbedtls_mpi_div_mpi+0x1e8>
        k = biL - 1 - k;
    7c10:	f1c0 0a1f 	rsb	sl, r0, #31
        MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &X, k ) );
    7c14:	4651      	mov	r1, sl
    7c16:	a806      	add	r0, sp, #24
    7c18:	f7ff fd29 	bl	766e <mbedtls_mpi_shift_l>
    7c1c:	4604      	mov	r4, r0
    7c1e:	2800      	cmp	r0, #0
    7c20:	d1ae      	bne.n	7b80 <mbedtls_mpi_div_mpi+0x70>
        MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &Y, k ) );
    7c22:	4651      	mov	r1, sl
    7c24:	4638      	mov	r0, r7
    7c26:	f7ff fd22 	bl	766e <mbedtls_mpi_shift_l>
    7c2a:	4604      	mov	r4, r0
    7c2c:	2800      	cmp	r0, #0
    7c2e:	d1a7      	bne.n	7b80 <mbedtls_mpi_div_mpi+0x70>
    n = X.n - 1;
    7c30:	f8dd 901c 	ldr.w	r9, [sp, #28]
    t = Y.n - 1;
    7c34:	9d0a      	ldr	r5, [sp, #40]	; 0x28
    MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &Y, biL * ( n - t ) ) );
    7c36:	eba9 0305 	sub.w	r3, r9, r5
    7c3a:	ea4f 1b43 	mov.w	fp, r3, lsl #5
    7c3e:	4659      	mov	r1, fp
    7c40:	4638      	mov	r0, r7
    7c42:	9302      	str	r3, [sp, #8]
    7c44:	f7ff fd13 	bl	766e <mbedtls_mpi_shift_l>
    7c48:	4604      	mov	r4, r0
    7c4a:	2800      	cmp	r0, #0
    7c4c:	d198      	bne.n	7b80 <mbedtls_mpi_div_mpi+0x70>
        Z.p[n - t]++;
    7c4e:	9b02      	ldr	r3, [sp, #8]
    7c50:	009b      	lsls	r3, r3, #2
    while( mbedtls_mpi_cmp_mpi( &X, &Y ) >= 0 )
    7c52:	4639      	mov	r1, r7
    7c54:	a806      	add	r0, sp, #24
    7c56:	9302      	str	r3, [sp, #8]
    7c58:	f7ff fdca 	bl	77f0 <mbedtls_mpi_cmp_mpi>
    7c5c:	2800      	cmp	r0, #0
    7c5e:	9b02      	ldr	r3, [sp, #8]
    7c60:	da4c      	bge.n	7cfc <mbedtls_mpi_div_mpi+0x1ec>
    MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &Y, biL * ( n - t ) ) );
    7c62:	4659      	mov	r1, fp
    7c64:	4638      	mov	r0, r7
    7c66:	f7ff fd54 	bl	7712 <mbedtls_mpi_shift_r>
    7c6a:	4604      	mov	r4, r0
    7c6c:	2800      	cmp	r0, #0
    7c6e:	d187      	bne.n	7b80 <mbedtls_mpi_div_mpi+0x70>
    t = Y.n - 1;
    7c70:	1e6b      	subs	r3, r5, #1
    7c72:	9302      	str	r3, [sp, #8]
        if( X.p[i] >= Y.p[t] )
    7c74:	009b      	lsls	r3, r3, #2
    7c76:	9304      	str	r3, [sp, #16]
            T1.p[0] = ( t < 1 ) ? 0 : Y.p[t - 1];
    7c78:	f105 4380 	add.w	r3, r5, #1073741824	; 0x40000000
    7c7c:	3b02      	subs	r3, #2
    7c7e:	009b      	lsls	r3, r3, #2
    7c80:	9305      	str	r3, [sp, #20]
    7c82:	f109 4380 	add.w	r3, r9, #1073741824	; 0x40000000
    n = X.n - 1;
    7c86:	f109 37ff 	add.w	r7, r9, #4294967295
    7c8a:	3b01      	subs	r3, #1
    7c8c:	f109 4980 	add.w	r9, r9, #1073741824	; 0x40000000
    7c90:	1b5d      	subs	r5, r3, r5
    7c92:	f1a9 0902 	sub.w	r9, r9, #2
    7c96:	00ad      	lsls	r5, r5, #2
    7c98:	ea4f 0b89 	mov.w	fp, r9, lsl #2
    for( i = n; i > t ; i-- )
    7c9c:	9b02      	ldr	r3, [sp, #8]
    7c9e:	429f      	cmp	r7, r3
    7ca0:	d83b      	bhi.n	7d1a <mbedtls_mpi_div_mpi+0x20a>
    if( Q != NULL )
    7ca2:	9b00      	ldr	r3, [sp, #0]
    7ca4:	b153      	cbz	r3, 7cbc <mbedtls_mpi_div_mpi+0x1ac>
        MBEDTLS_MPI_CHK( mbedtls_mpi_copy( Q, &Z ) );
    7ca6:	a90c      	add	r1, sp, #48	; 0x30
    7ca8:	4618      	mov	r0, r3
    7caa:	f7ff fbdc 	bl	7466 <mbedtls_mpi_copy>
    7cae:	bb08      	cbnz	r0, 7cf4 <mbedtls_mpi_div_mpi+0x1e4>
        Q->s = A->s * B->s;
    7cb0:	9a01      	ldr	r2, [sp, #4]
    7cb2:	6833      	ldr	r3, [r6, #0]
    7cb4:	6812      	ldr	r2, [r2, #0]
    7cb6:	4353      	muls	r3, r2
    7cb8:	9a00      	ldr	r2, [sp, #0]
    7cba:	6013      	str	r3, [r2, #0]
    if( R != NULL )
    7cbc:	f1b8 0f00 	cmp.w	r8, #0
    7cc0:	f43f af5e 	beq.w	7b80 <mbedtls_mpi_div_mpi+0x70>
        MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &X, k ) );
    7cc4:	4651      	mov	r1, sl
    7cc6:	a806      	add	r0, sp, #24
    7cc8:	f7ff fd23 	bl	7712 <mbedtls_mpi_shift_r>
    7ccc:	b990      	cbnz	r0, 7cf4 <mbedtls_mpi_div_mpi+0x1e4>
        X.s = A->s;
    7cce:	6833      	ldr	r3, [r6, #0]
    7cd0:	9306      	str	r3, [sp, #24]
        MBEDTLS_MPI_CHK( mbedtls_mpi_copy( R, &X ) );
    7cd2:	a906      	add	r1, sp, #24
    7cd4:	4640      	mov	r0, r8
    7cd6:	f7ff fbc6 	bl	7466 <mbedtls_mpi_copy>
    7cda:	4601      	mov	r1, r0
    7cdc:	2800      	cmp	r0, #0
    7cde:	f040 80b7 	bne.w	7e50 <mbedtls_mpi_div_mpi+0x340>
        if( mbedtls_mpi_cmp_int( R, 0 ) == 0 )
    7ce2:	4640      	mov	r0, r8
    7ce4:	f7ff fdc5 	bl	7872 <mbedtls_mpi_cmp_int>
    7ce8:	2800      	cmp	r0, #0
    7cea:	f47f af49 	bne.w	7b80 <mbedtls_mpi_div_mpi+0x70>
            R->s = 1;
    7cee:	2301      	movs	r3, #1
    7cf0:	f8c8 3000 	str.w	r3, [r8]
    7cf4:	4604      	mov	r4, r0
    7cf6:	e743      	b.n	7b80 <mbedtls_mpi_div_mpi+0x70>
    else k = 0;
    7cf8:	46a2      	mov	sl, r4
    7cfa:	e799      	b.n	7c30 <mbedtls_mpi_div_mpi+0x120>
        Z.p[n - t]++;
    7cfc:	990e      	ldr	r1, [sp, #56]	; 0x38
    7cfe:	9302      	str	r3, [sp, #8]
    7d00:	58ca      	ldr	r2, [r1, r3]
    7d02:	3201      	adds	r2, #1
    7d04:	50ca      	str	r2, [r1, r3]
        MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &X, &X, &Y ) );
    7d06:	a906      	add	r1, sp, #24
    7d08:	463a      	mov	r2, r7
    7d0a:	4608      	mov	r0, r1
    7d0c:	f7ff feaf 	bl	7a6e <mbedtls_mpi_sub_mpi>
    7d10:	9b02      	ldr	r3, [sp, #8]
    7d12:	4604      	mov	r4, r0
    7d14:	2800      	cmp	r0, #0
    7d16:	d09c      	beq.n	7c52 <mbedtls_mpi_div_mpi+0x142>
    7d18:	e732      	b.n	7b80 <mbedtls_mpi_div_mpi+0x70>
        if( X.p[i] >= Y.p[t] )
    7d1a:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
    7d1c:	f8dd 9020 	ldr.w	r9, [sp, #32]
    7d20:	9a04      	ldr	r2, [sp, #16]
    7d22:	f859 1027 	ldr.w	r1, [r9, r7, lsl #2]
    7d26:	589a      	ldr	r2, [r3, r2]
            Z.p[i - t - 1] = ~0;
    7d28:	9b0e      	ldr	r3, [sp, #56]	; 0x38
        if( X.p[i] >= Y.p[t] )
    7d2a:	4291      	cmp	r1, r2
            Z.p[i - t - 1] = ~0;
    7d2c:	eb03 0005 	add.w	r0, r3, r5
    7d30:	9003      	str	r0, [sp, #12]
        if( X.p[i] >= Y.p[t] )
    7d32:	d376      	bcc.n	7e22 <mbedtls_mpi_div_mpi+0x312>
            Z.p[i - t - 1] = ~0;
    7d34:	f04f 32ff 	mov.w	r2, #4294967295
    7d38:	515a      	str	r2, [r3, r5]
        T2.p[0] = ( i < 2 ) ? 0 : X.p[i - 2];
    7d3a:	2f01      	cmp	r7, #1
    7d3c:	bf8a      	itet	hi
    7d3e:	eb09 030b 	addhi.w	r3, r9, fp
    7d42:	2300      	movls	r3, #0
    7d44:	f853 3c04 	ldrhi.w	r3, [r3, #-4]
    7d48:	9315      	str	r3, [sp, #84]	; 0x54
        T2.p[1] = ( i < 1 ) ? 0 : X.p[i - 1];
    7d4a:	2f00      	cmp	r7, #0
    7d4c:	d07c      	beq.n	7e48 <mbedtls_mpi_div_mpi+0x338>
    7d4e:	f859 300b 	ldr.w	r3, [r9, fp]
    7d52:	9316      	str	r3, [sp, #88]	; 0x58
        T2.p[2] = X.p[i];
    7d54:	00bb      	lsls	r3, r7, #2
        Z.p[i - t - 1]++;
    7d56:	9a03      	ldr	r2, [sp, #12]
        T2.p[2] = X.p[i];
    7d58:	f859 3003 	ldr.w	r3, [r9, r3]
    7d5c:	9317      	str	r3, [sp, #92]	; 0x5c
        Z.p[i - t - 1]++;
    7d5e:	9b03      	ldr	r3, [sp, #12]
    7d60:	681b      	ldr	r3, [r3, #0]
    7d62:	3301      	adds	r3, #1
    7d64:	6013      	str	r3, [r2, #0]
            Z.p[i - t - 1]--;
    7d66:	9a0e      	ldr	r2, [sp, #56]	; 0x38
    7d68:	5953      	ldr	r3, [r2, r5]
    7d6a:	3b01      	subs	r3, #1
    7d6c:	5153      	str	r3, [r2, r5]
            MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &T1, 0 ) );
    7d6e:	2100      	movs	r1, #0
    7d70:	a80f      	add	r0, sp, #60	; 0x3c
    7d72:	f7ff fbd6 	bl	7522 <mbedtls_mpi_lset>
    7d76:	2800      	cmp	r0, #0
    7d78:	d1bc      	bne.n	7cf4 <mbedtls_mpi_div_mpi+0x1e4>
            T1.p[0] = ( t < 1 ) ? 0 : Y.p[t - 1];
    7d7a:	9b02      	ldr	r3, [sp, #8]
    7d7c:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    7d7e:	2b00      	cmp	r3, #0
    7d80:	d064      	beq.n	7e4c <mbedtls_mpi_div_mpi+0x33c>
    7d82:	9b05      	ldr	r3, [sp, #20]
    7d84:	58d1      	ldr	r1, [r2, r3]
    7d86:	9b11      	ldr	r3, [sp, #68]	; 0x44
    7d88:	6019      	str	r1, [r3, #0]
            T1.p[1] = Y.p[t];
    7d8a:	9904      	ldr	r1, [sp, #16]
    7d8c:	5852      	ldr	r2, [r2, r1]
    7d8e:	605a      	str	r2, [r3, #4]
            MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &T1, &T1, Z.p[i - t - 1] ) );
    7d90:	9b0e      	ldr	r3, [sp, #56]	; 0x38
    7d92:	a90f      	add	r1, sp, #60	; 0x3c
    7d94:	595a      	ldr	r2, [r3, r5]
    7d96:	4608      	mov	r0, r1
    7d98:	f7ff fe8c 	bl	7ab4 <mbedtls_mpi_mul_int>
    7d9c:	2800      	cmp	r0, #0
    7d9e:	d1a9      	bne.n	7cf4 <mbedtls_mpi_div_mpi+0x1e4>
        while( mbedtls_mpi_cmp_mpi( &T1, &T2 ) > 0 );
    7da0:	a912      	add	r1, sp, #72	; 0x48
    7da2:	a80f      	add	r0, sp, #60	; 0x3c
    7da4:	f7ff fd24 	bl	77f0 <mbedtls_mpi_cmp_mpi>
    7da8:	2800      	cmp	r0, #0
    7daa:	dcdc      	bgt.n	7d66 <mbedtls_mpi_div_mpi+0x256>
        MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &T1, &Y, Z.p[i - t - 1] ) );
    7dac:	9b0e      	ldr	r3, [sp, #56]	; 0x38
    7dae:	a909      	add	r1, sp, #36	; 0x24
    7db0:	595a      	ldr	r2, [r3, r5]
    7db2:	a80f      	add	r0, sp, #60	; 0x3c
    7db4:	f7ff fe7e 	bl	7ab4 <mbedtls_mpi_mul_int>
    7db8:	2800      	cmp	r0, #0
    7dba:	d19b      	bne.n	7cf4 <mbedtls_mpi_div_mpi+0x1e4>
        MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &T1,  biL * ( i - t - 1 ) ) );
    7dbc:	ea4f 09c5 	mov.w	r9, r5, lsl #3
    7dc0:	4649      	mov	r1, r9
    7dc2:	a80f      	add	r0, sp, #60	; 0x3c
    7dc4:	f7ff fc53 	bl	766e <mbedtls_mpi_shift_l>
    7dc8:	2800      	cmp	r0, #0
    7dca:	d193      	bne.n	7cf4 <mbedtls_mpi_div_mpi+0x1e4>
        MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &X, &X, &T1 ) );
    7dcc:	a906      	add	r1, sp, #24
    7dce:	4608      	mov	r0, r1
    7dd0:	aa0f      	add	r2, sp, #60	; 0x3c
    7dd2:	f7ff fe4c 	bl	7a6e <mbedtls_mpi_sub_mpi>
    7dd6:	4601      	mov	r1, r0
    7dd8:	2800      	cmp	r0, #0
    7dda:	d139      	bne.n	7e50 <mbedtls_mpi_div_mpi+0x340>
        if( mbedtls_mpi_cmp_int( &X, 0 ) < 0 )
    7ddc:	a806      	add	r0, sp, #24
    7dde:	f7ff fd48 	bl	7872 <mbedtls_mpi_cmp_int>
    7de2:	2800      	cmp	r0, #0
    7de4:	da18      	bge.n	7e18 <mbedtls_mpi_div_mpi+0x308>
            MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &T1, &Y ) );
    7de6:	a909      	add	r1, sp, #36	; 0x24
    7de8:	a80f      	add	r0, sp, #60	; 0x3c
    7dea:	f7ff fb3c 	bl	7466 <mbedtls_mpi_copy>
    7dee:	2800      	cmp	r0, #0
    7df0:	d180      	bne.n	7cf4 <mbedtls_mpi_div_mpi+0x1e4>
            MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &T1, biL * ( i - t - 1 ) ) );
    7df2:	4649      	mov	r1, r9
    7df4:	a80f      	add	r0, sp, #60	; 0x3c
    7df6:	f7ff fc3a 	bl	766e <mbedtls_mpi_shift_l>
    7dfa:	2800      	cmp	r0, #0
    7dfc:	f47f af7a 	bne.w	7cf4 <mbedtls_mpi_div_mpi+0x1e4>
            MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &X, &X, &T1 ) );
    7e00:	a906      	add	r1, sp, #24
    7e02:	aa0f      	add	r2, sp, #60	; 0x3c
    7e04:	4608      	mov	r0, r1
    7e06:	f7ff fe10 	bl	7a2a <mbedtls_mpi_add_mpi>
    7e0a:	2800      	cmp	r0, #0
    7e0c:	f47f af72 	bne.w	7cf4 <mbedtls_mpi_div_mpi+0x1e4>
            Z.p[i - t - 1]--;
    7e10:	9a0e      	ldr	r2, [sp, #56]	; 0x38
    7e12:	5953      	ldr	r3, [r2, r5]
    7e14:	3b01      	subs	r3, #1
    7e16:	5153      	str	r3, [r2, r5]
    for( i = n; i > t ; i-- )
    7e18:	3f01      	subs	r7, #1
    7e1a:	3d04      	subs	r5, #4
    7e1c:	f1ab 0b04 	sub.w	fp, fp, #4
    7e20:	e73c      	b.n	7c9c <mbedtls_mpi_div_mpi+0x18c>
            Z.p[i - t - 1] = mbedtls_int_div_int( X.p[i], X.p[i - 1],
    7e22:	f859 000b 	ldr.w	r0, [r9, fp]
    if( 0 == d || u1 >= d )
    7e26:	b152      	cbz	r2, 7e3e <mbedtls_mpi_div_mpi+0x32e>
    dividend  = (mbedtls_t_udbl) u1 << biL;
    7e28:	2300      	movs	r3, #0
    quotient = dividend / d;
    7e2a:	f7f8 f957 	bl	dc <__aeabi_uldivmod>
    return (mbedtls_mpi_uint) quotient;
    7e2e:	f04f 33ff 	mov.w	r3, #4294967295
    7e32:	4283      	cmp	r3, r0
    7e34:	f04f 0300 	mov.w	r3, #0
    7e38:	418b      	sbcs	r3, r1
    7e3a:	4602      	mov	r2, r0
    7e3c:	d201      	bcs.n	7e42 <mbedtls_mpi_div_mpi+0x332>
        return ( ~0 );
    7e3e:	f04f 32ff 	mov.w	r2, #4294967295
            Z.p[i - t - 1] = mbedtls_int_div_int( X.p[i], X.p[i - 1],
    7e42:	9b03      	ldr	r3, [sp, #12]
    7e44:	601a      	str	r2, [r3, #0]
    7e46:	e778      	b.n	7d3a <mbedtls_mpi_div_mpi+0x22a>
        T2.p[1] = ( i < 1 ) ? 0 : X.p[i - 1];
    7e48:	463b      	mov	r3, r7
    7e4a:	e782      	b.n	7d52 <mbedtls_mpi_div_mpi+0x242>
            T1.p[0] = ( t < 1 ) ? 0 : Y.p[t - 1];
    7e4c:	9902      	ldr	r1, [sp, #8]
    7e4e:	e79a      	b.n	7d86 <mbedtls_mpi_div_mpi+0x276>
    7e50:	460c      	mov	r4, r1
    7e52:	e695      	b.n	7b80 <mbedtls_mpi_div_mpi+0x70>
        return( MBEDTLS_ERR_MPI_DIVISION_BY_ZERO );
    7e54:	f06f 040b 	mvn.w	r4, #11
    7e58:	e687      	b.n	7b6a <mbedtls_mpi_div_mpi+0x5a>

00007e5a <mbedtls_mpi_mod_mpi>:
{
    7e5a:	b570      	push	{r4, r5, r6, lr}
    7e5c:	4604      	mov	r4, r0
    7e5e:	460d      	mov	r5, r1
    if( mbedtls_mpi_cmp_int( B, 0 ) < 0 )
    7e60:	4610      	mov	r0, r2
    7e62:	2100      	movs	r1, #0
{
    7e64:	4616      	mov	r6, r2
    if( mbedtls_mpi_cmp_int( B, 0 ) < 0 )
    7e66:	f7ff fd04 	bl	7872 <mbedtls_mpi_cmp_int>
    7e6a:	2800      	cmp	r0, #0
    7e6c:	db24      	blt.n	7eb8 <mbedtls_mpi_mod_mpi+0x5e>
    MBEDTLS_MPI_CHK( mbedtls_mpi_div_mpi( NULL, R, A, B ) );
    7e6e:	462a      	mov	r2, r5
    7e70:	4633      	mov	r3, r6
    7e72:	4621      	mov	r1, r4
    7e74:	2000      	movs	r0, #0
    7e76:	f7ff fe4b 	bl	7b10 <mbedtls_mpi_div_mpi>
    7e7a:	4605      	mov	r5, r0
    7e7c:	b138      	cbz	r0, 7e8e <mbedtls_mpi_mod_mpi+0x34>
}
    7e7e:	4628      	mov	r0, r5
    7e80:	bd70      	pop	{r4, r5, r6, pc}
      MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( R, R, B ) );
    7e82:	4632      	mov	r2, r6
    7e84:	4621      	mov	r1, r4
    7e86:	4620      	mov	r0, r4
    7e88:	f7ff fdcf 	bl	7a2a <mbedtls_mpi_add_mpi>
    7e8c:	b990      	cbnz	r0, 7eb4 <mbedtls_mpi_mod_mpi+0x5a>
    while( mbedtls_mpi_cmp_int( R, 0 ) < 0 )
    7e8e:	2100      	movs	r1, #0
    7e90:	4620      	mov	r0, r4
    7e92:	f7ff fcee 	bl	7872 <mbedtls_mpi_cmp_int>
    7e96:	2800      	cmp	r0, #0
    7e98:	dbf3      	blt.n	7e82 <mbedtls_mpi_mod_mpi+0x28>
    while( mbedtls_mpi_cmp_mpi( R, B ) >= 0 )
    7e9a:	4631      	mov	r1, r6
    7e9c:	4620      	mov	r0, r4
    7e9e:	f7ff fca7 	bl	77f0 <mbedtls_mpi_cmp_mpi>
    7ea2:	2800      	cmp	r0, #0
    7ea4:	dbeb      	blt.n	7e7e <mbedtls_mpi_mod_mpi+0x24>
      MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( R, R, B ) );
    7ea6:	4632      	mov	r2, r6
    7ea8:	4621      	mov	r1, r4
    7eaa:	4620      	mov	r0, r4
    7eac:	f7ff fddf 	bl	7a6e <mbedtls_mpi_sub_mpi>
    7eb0:	2800      	cmp	r0, #0
    7eb2:	d0f2      	beq.n	7e9a <mbedtls_mpi_mod_mpi+0x40>
    7eb4:	4605      	mov	r5, r0
    7eb6:	e7e2      	b.n	7e7e <mbedtls_mpi_mod_mpi+0x24>
        return( MBEDTLS_ERR_MPI_NEGATIVE_VALUE );
    7eb8:	f06f 0509 	mvn.w	r5, #9
    7ebc:	e7df      	b.n	7e7e <mbedtls_mpi_mod_mpi+0x24>

00007ebe <mbedtls_mpi_exp_mod>:
 * Sliding-window exponentiation: X = A^E mod N  (HAC 14.85)
 */
int mbedtls_mpi_exp_mod( mbedtls_mpi *X, const mbedtls_mpi *A,
                         const mbedtls_mpi *E, const mbedtls_mpi *N,
                         mbedtls_mpi *_RR )
{
    7ebe:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    7ec2:	f5ad 7d5b 	sub.w	sp, sp, #876	; 0x36c
    7ec6:	4606      	mov	r6, r0
    7ec8:	4688      	mov	r8, r1
    MPI_VALIDATE_RET( X != NULL );
    MPI_VALIDATE_RET( A != NULL );
    MPI_VALIDATE_RET( E != NULL );
    MPI_VALIDATE_RET( N != NULL );

    if( mbedtls_mpi_cmp_int( N, 0 ) <= 0 || ( N->p[0] & 1 ) == 0 )
    7eca:	4618      	mov	r0, r3
    7ecc:	2100      	movs	r1, #0
{
    7ece:	9204      	str	r2, [sp, #16]
    7ed0:	461d      	mov	r5, r3
    if( mbedtls_mpi_cmp_int( N, 0 ) <= 0 || ( N->p[0] & 1 ) == 0 )
    7ed2:	f7ff fcce 	bl	7872 <mbedtls_mpi_cmp_int>
    7ed6:	2800      	cmp	r0, #0
    7ed8:	f340 8217 	ble.w	830a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x30a>
    7edc:	68ab      	ldr	r3, [r5, #8]
    7ede:	681c      	ldr	r4, [r3, #0]
    7ee0:	f014 0301 	ands.w	r3, r4, #1
    7ee4:	9307      	str	r3, [sp, #28]
    7ee6:	f000 8210 	beq.w	830a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x30a>
        return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA );

    if( mbedtls_mpi_cmp_int( E, 0 ) < 0 )
    7eea:	9804      	ldr	r0, [sp, #16]
    7eec:	2100      	movs	r1, #0
    7eee:	f7ff fcc0 	bl	7872 <mbedtls_mpi_cmp_int>
    7ef2:	2800      	cmp	r0, #0
    7ef4:	f2c0 8209 	blt.w	830a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x30a>
        return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA );

    if( mbedtls_mpi_bitlen( E ) > MBEDTLS_MPI_MAX_BITS ||
    7ef8:	9804      	ldr	r0, [sp, #16]
    7efa:	f7ff fb3f 	bl	757c <mbedtls_mpi_bitlen>
    7efe:	f5b0 6f00 	cmp.w	r0, #2048	; 0x800
    7f02:	f200 8202 	bhi.w	830a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x30a>
        mbedtls_mpi_bitlen( N ) > MBEDTLS_MPI_MAX_BITS )
    7f06:	4628      	mov	r0, r5
    7f08:	f7ff fb38 	bl	757c <mbedtls_mpi_bitlen>
    if( mbedtls_mpi_bitlen( E ) > MBEDTLS_MPI_MAX_BITS ||
    7f0c:	f5b0 6f00 	cmp.w	r0, #2048	; 0x800
    7f10:	f200 81fb 	bhi.w	830a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x30a>
    x += ( ( m0 + 2 ) & 4 ) << 1;
    7f14:	1ca7      	adds	r7, r4, #2
    7f16:	007f      	lsls	r7, r7, #1
    7f18:	f007 0708 	and.w	r7, r7, #8
    7f1c:	4427      	add	r7, r4
    7f1e:	2103      	movs	r1, #3
        x *= ( 2 - ( m0 * x ) );
    7f20:	fb07 f304 	mul.w	r3, r7, r4
    7f24:	f1c3 0302 	rsb	r3, r3, #2
    for( i = biL; i >= 8; i /= 2 )
    7f28:	3901      	subs	r1, #1
        x *= ( 2 - ( m0 * x ) );
    7f2a:	fb03 f707 	mul.w	r7, r3, r7
    for( i = biL; i >= 8; i /= 2 )
    7f2e:	d1f7      	bne.n	7f20 <mbedtls_mpi_exp_mod+0x62>
    X->s = 1;
    7f30:	2301      	movs	r3, #1
     */
    mpi_montg_init( &mm, N );
    mbedtls_mpi_init( &RR ); mbedtls_mpi_init( &T );
    mbedtls_mpi_init( &Apos );
    mbedtls_mpi_init( &WW );
    memset( W, 0, sizeof( W ) );
    7f32:	f44f 7240 	mov.w	r2, #768	; 0x300
    7f36:	a81a      	add	r0, sp, #104	; 0x68
    X->n = 0;
    7f38:	e9cd 310b 	strd	r3, r1, [sp, #44]	; 0x2c
    X->s = 1;
    7f3c:	e9cd 130d 	strd	r1, r3, [sp, #52]	; 0x34
    X->p = NULL;
    7f40:	e9cd 110f 	strd	r1, r1, [sp, #60]	; 0x3c
    X->n = 0;
    7f44:	e9cd 3114 	strd	r3, r1, [sp, #80]	; 0x50
    7f48:	e9cd 3111 	strd	r3, r1, [sp, #68]	; 0x44
    X->p = NULL;
    7f4c:	9116      	str	r1, [sp, #88]	; 0x58
    7f4e:	9113      	str	r1, [sp, #76]	; 0x4c
    memset( W, 0, sizeof( W ) );
    7f50:	f7fe fad7 	bl	6502 <memset>

    i = mbedtls_mpi_bitlen( E );
    7f54:	9804      	ldr	r0, [sp, #16]
    7f56:	f7ff fb11 	bl	757c <mbedtls_mpi_bitlen>

    wsize = ( i > 671 ) ? 6 : ( i > 239 ) ? 5 :
    7f5a:	f5b0 7f28 	cmp.w	r0, #672	; 0x2a0
    7f5e:	f080 80f8 	bcs.w	8152 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x152>
    7f62:	28ef      	cmp	r0, #239	; 0xef
    7f64:	f200 80f7 	bhi.w	8156 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x156>
    7f68:	284f      	cmp	r0, #79	; 0x4f
    7f6a:	f200 80f6 	bhi.w	815a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x15a>
    7f6e:	2817      	cmp	r0, #23
    7f70:	9b07      	ldr	r3, [sp, #28]
    7f72:	bf88      	it	hi
    7f74:	2303      	movhi	r3, #3
#if( MBEDTLS_MPI_WINDOW_SIZE < 6 )
    if( wsize > MBEDTLS_MPI_WINDOW_SIZE )
        wsize = MBEDTLS_MPI_WINDOW_SIZE;
#endif

    j = N->n + 1;
    7f76:	6869      	ldr	r1, [r5, #4]
    wsize = ( i > 671 ) ? 6 : ( i > 239 ) ? 5 :
    7f78:	9303      	str	r3, [sp, #12]
    j = N->n + 1;
    7f7a:	f101 0901 	add.w	r9, r1, #1
    /* All W[i] and X must have at least N->n limbs for the mpi_montmul()
     * and mpi_montred() calls later. Here we ensure that W[1] and X are
     * large enough, and later we'll grow other W[i] to the same length.
     * They must not be shrunk midway through this function!
     */
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, j ) );
    7f7e:	4649      	mov	r1, r9
    7f80:	4630      	mov	r0, r6
    7f82:	f7ff fa2f 	bl	73e4 <mbedtls_mpi_grow>
    7f86:	4604      	mov	r4, r0
    7f88:	2800      	cmp	r0, #0
    7f8a:	f040 80be 	bne.w	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[1],  j ) );
    7f8e:	4649      	mov	r1, r9
    7f90:	a81d      	add	r0, sp, #116	; 0x74
    7f92:	f7ff fa27 	bl	73e4 <mbedtls_mpi_grow>
    7f96:	4604      	mov	r4, r0
    7f98:	2800      	cmp	r0, #0
    7f9a:	f040 80b6 	bne.w	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
    MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &T, j * 2 ) );
    7f9e:	ea4f 0149 	mov.w	r1, r9, lsl #1
    7fa2:	a80e      	add	r0, sp, #56	; 0x38
    7fa4:	f7ff fa1e 	bl	73e4 <mbedtls_mpi_grow>
    7fa8:	4604      	mov	r4, r0
    7faa:	2800      	cmp	r0, #0
    7fac:	f040 80ad 	bne.w	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>

    /*
     * Compensate for negative A (and correct at the end)
     */
    neg = ( A->s == -1 );
    7fb0:	f8d8 3000 	ldr.w	r3, [r8]
    7fb4:	9306      	str	r3, [sp, #24]
    if( neg )
    7fb6:	3301      	adds	r3, #1
    7fb8:	d10b      	bne.n	7fd2 <mbedtls_mpi_exp_mod+0x114>
    {
        MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &Apos, A ) );
    7fba:	4641      	mov	r1, r8
    7fbc:	a814      	add	r0, sp, #80	; 0x50
    7fbe:	f7ff fa52 	bl	7466 <mbedtls_mpi_copy>
    7fc2:	4604      	mov	r4, r0
    7fc4:	2800      	cmp	r0, #0
    7fc6:	f040 80a0 	bne.w	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
        Apos.s = 1;
    7fca:	2301      	movs	r3, #1
    7fcc:	9314      	str	r3, [sp, #80]	; 0x50
        A = &Apos;
    7fce:	f10d 0850 	add.w	r8, sp, #80	; 0x50
    }

    /*
     * If 1st call, pre-compute R^2 mod N
     */
    if( _RR == NULL || _RR->p == NULL )
    7fd2:	9be4      	ldr	r3, [sp, #912]	; 0x390
    7fd4:	b11b      	cbz	r3, 7fde <mbedtls_mpi_exp_mod+0x120>
    7fd6:	689b      	ldr	r3, [r3, #8]
    7fd8:	2b00      	cmp	r3, #0
    7fda:	f040 80c0 	bne.w	815e <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x15e>
    {
        MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &RR, 1 ) );
    7fde:	2101      	movs	r1, #1
    7fe0:	a80b      	add	r0, sp, #44	; 0x2c
    7fe2:	f7ff fa9e 	bl	7522 <mbedtls_mpi_lset>
    7fe6:	4604      	mov	r4, r0
    7fe8:	2800      	cmp	r0, #0
    7fea:	f040 808e 	bne.w	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
        MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &RR, N->n * 2 * biL ) );
    7fee:	6869      	ldr	r1, [r5, #4]
    7ff0:	a80b      	add	r0, sp, #44	; 0x2c
    7ff2:	0189      	lsls	r1, r1, #6
    7ff4:	f7ff fb3b 	bl	766e <mbedtls_mpi_shift_l>
    7ff8:	4604      	mov	r4, r0
    7ffa:	2800      	cmp	r0, #0
    7ffc:	f040 8085 	bne.w	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
        MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &RR, &RR, N ) );
    8000:	a90b      	add	r1, sp, #44	; 0x2c
    8002:	462a      	mov	r2, r5
    8004:	4608      	mov	r0, r1
    8006:	f7ff ff28 	bl	7e5a <mbedtls_mpi_mod_mpi>
    800a:	4604      	mov	r4, r0
    800c:	2800      	cmp	r0, #0
    800e:	d17c      	bne.n	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>

        if( _RR != NULL )
    8010:	9be4      	ldr	r3, [sp, #912]	; 0x390
    8012:	b123      	cbz	r3, 801e <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x1e>
            memcpy( _RR, &RR, sizeof( mbedtls_mpi ) );
    8014:	220c      	movs	r2, #12
    8016:	a90b      	add	r1, sp, #44	; 0x2c
    8018:	4618      	mov	r0, r3
    }
    else
        memcpy( &RR, _RR, sizeof( mbedtls_mpi ) );
    801a:	f7fe fa67 	bl	64ec <memcpy>

    /*
     * W[1] = A * R^2 * R^-1 mod N = A * R mod N
     */
    if( mbedtls_mpi_cmp_mpi( A, N ) >= 0 )
    801e:	4629      	mov	r1, r5
    8020:	4640      	mov	r0, r8
    8022:	f7ff fbe5 	bl	77f0 <mbedtls_mpi_cmp_mpi>
    8026:	2800      	cmp	r0, #0
    8028:	f2c0 809d 	blt.w	8166 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x166>
    {
        MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &W[1], A, N ) );
    802c:	462a      	mov	r2, r5
    802e:	4641      	mov	r1, r8
    8030:	a81d      	add	r0, sp, #116	; 0x74
    8032:	f7ff ff12 	bl	7e5a <mbedtls_mpi_mod_mpi>
    8036:	4604      	mov	r4, r0
    8038:	2800      	cmp	r0, #0
    803a:	d166      	bne.n	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
        /* This should be a no-op because W[1] is already that large before
         * mbedtls_mpi_mod_mpi(), but it's necessary to avoid an overflow
         * in mpi_montmul() below, so let's make sure. */
        MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[1], N->n + 1 ) );
    803c:	6869      	ldr	r1, [r5, #4]
    803e:	a81d      	add	r0, sp, #116	; 0x74
    8040:	3101      	adds	r1, #1
    8042:	f7ff f9cf 	bl	73e4 <mbedtls_mpi_grow>
    8046:	4604      	mov	r4, r0
    8048:	2800      	cmp	r0, #0
    804a:	d15e      	bne.n	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
    *mm = ~x + 1;
    804c:	f1c7 0b00 	rsb	fp, r7, #0
    else
        MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &W[1], A ) );

    /* Note that this is safe because W[1] always has at least N->n limbs
     * (it grew above and was preserved by mbedtls_mpi_copy()). */
    mpi_montmul( &W[1], &RR, N, mm, &T );
    8050:	f10d 0938 	add.w	r9, sp, #56	; 0x38
    8054:	465b      	mov	r3, fp
    8056:	462a      	mov	r2, r5
    8058:	a90b      	add	r1, sp, #44	; 0x2c
    805a:	a81d      	add	r0, sp, #116	; 0x74
    805c:	f8cd 9000 	str.w	r9, [sp]
    8060:	f7ff f909 	bl	7276 <mpi_montmul>

    /*
     * X = R^2 * R^-1 mod N = R mod N
     */
    MBEDTLS_MPI_CHK( mbedtls_mpi_copy( X, &RR ) );
    8064:	a90b      	add	r1, sp, #44	; 0x2c
    8066:	4630      	mov	r0, r6
    8068:	f7ff f9fd 	bl	7466 <mbedtls_mpi_copy>
    806c:	4604      	mov	r4, r0
    806e:	2800      	cmp	r0, #0
    8070:	d14b      	bne.n	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
    mbedtls_mpi_uint z = 1;
    8072:	ab0a      	add	r3, sp, #40	; 0x28
    8074:	2701      	movs	r7, #1
    U.p = &z;
    8076:	9319      	str	r3, [sp, #100]	; 0x64
    mpi_montmul( A, &U, N, mm, T );
    8078:	f8cd 9000 	str.w	r9, [sp]
    807c:	465b      	mov	r3, fp
    807e:	462a      	mov	r2, r5
    8080:	a917      	add	r1, sp, #92	; 0x5c
    8082:	4630      	mov	r0, r6
    U.n = U.s = (int) z;
    8084:	e9cd 7717 	strd	r7, r7, [sp, #92]	; 0x5c
    mbedtls_mpi_uint z = 1;
    8088:	970a      	str	r7, [sp, #40]	; 0x28
    mpi_montmul( A, &U, N, mm, T );
    808a:	f7ff f8f4 	bl	7276 <mpi_montmul>
    mpi_montred( X, N, mm, &T );

    if( wsize > 1 )
    808e:	9b03      	ldr	r3, [sp, #12]
    8090:	42bb      	cmp	r3, r7
    8092:	d16d      	bne.n	8170 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x170>

            mpi_montmul( &W[i], &W[1], N, mm, &T );
        }
    }

    nblimbs = E->n;
    8094:	9b04      	ldr	r3, [sp, #16]
    bufsize = 0;
    nbits   = 0;
    wbits   = 0;
    state   = 0;
    8096:	f04f 0800 	mov.w	r8, #0
    nblimbs = E->n;
    809a:	f8d3 9004 	ldr.w	r9, [r3, #4]
    bufsize = 0;
    809e:	f8cd 8014 	str.w	r8, [sp, #20]
    nbits   = 0;
    80a2:	4647      	mov	r7, r8
    wbits   = 0;
    80a4:	46c2      	mov	sl, r8

    while( 1 )
    {
        if( bufsize == 0 )
    80a6:	9b05      	ldr	r3, [sp, #20]
    80a8:	2b00      	cmp	r3, #0
    80aa:	f040 80b3 	bne.w	8214 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x214>
        {
            if( nblimbs == 0 )
    80ae:	f1b9 0f00 	cmp.w	r9, #0
    80b2:	f040 80ab 	bne.w	820c <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x20c>
    {
        mpi_montmul( X, X, N, mm, &T );

        wbits <<= 1;

        if( ( wbits & ( one << wsize ) ) != 0 )
    80b6:	9a03      	ldr	r2, [sp, #12]
    80b8:	2301      	movs	r3, #1
    80ba:	4093      	lsls	r3, r2
    80bc:	9305      	str	r3, [sp, #20]
    80be:	f10d 0838 	add.w	r8, sp, #56	; 0x38
    for( i = 0; i < nbits; i++ )
    80c2:	45b9      	cmp	r9, r7
    80c4:	f040 80ff 	bne.w	82c6 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x2c6>
    mbedtls_mpi_uint z = 1;
    80c8:	2301      	movs	r3, #1
    80ca:	aa0a      	add	r2, sp, #40	; 0x28
    U.n = U.s = (int) z;
    80cc:	e9cd 3317 	strd	r3, r3, [sp, #92]	; 0x5c
    mbedtls_mpi_uint z = 1;
    80d0:	930a      	str	r3, [sp, #40]	; 0x28
    U.p = &z;
    80d2:	9219      	str	r2, [sp, #100]	; 0x64
    mpi_montmul( A, &U, N, mm, T );
    80d4:	465b      	mov	r3, fp
    80d6:	f8cd 8000 	str.w	r8, [sp]
    80da:	462a      	mov	r2, r5
    80dc:	a917      	add	r1, sp, #92	; 0x5c
    80de:	4630      	mov	r0, r6
    80e0:	f7ff f8c9 	bl	7276 <mpi_montmul>
    /*
     * X = A^E * R * R^-1 mod N = A^E mod N
     */
    mpi_montred( X, N, mm, &T );

    if( neg && E->n != 0 && ( E->p[0] & 1 ) != 0 )
    80e4:	9b06      	ldr	r3, [sp, #24]
    80e6:	3301      	adds	r3, #1
    80e8:	d10f      	bne.n	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
    80ea:	9b04      	ldr	r3, [sp, #16]
    80ec:	685b      	ldr	r3, [r3, #4]
    80ee:	b163      	cbz	r3, 810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
    80f0:	9b04      	ldr	r3, [sp, #16]
    80f2:	689b      	ldr	r3, [r3, #8]
    80f4:	681b      	ldr	r3, [r3, #0]
    80f6:	07db      	lsls	r3, r3, #31
    80f8:	d507      	bpl.n	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
    {
        X->s = -1;
    80fa:	9b06      	ldr	r3, [sp, #24]
    80fc:	6033      	str	r3, [r6, #0]
        MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( X, N, X ) );
    80fe:	4632      	mov	r2, r6
    8100:	4629      	mov	r1, r5
    8102:	4630      	mov	r0, r6
    8104:	f7ff fc91 	bl	7a2a <mbedtls_mpi_add_mpi>
    8108:	4604      	mov	r4, r0
    }

cleanup:

    for( i = ( one << ( wsize - 1 ) ); i < ( one << wsize ); i++ )
    810a:	9b03      	ldr	r3, [sp, #12]
    810c:	9a03      	ldr	r2, [sp, #12]
    810e:	1e5d      	subs	r5, r3, #1
    8110:	2301      	movs	r3, #1
    8112:	fa03 f505 	lsl.w	r5, r3, r5
    8116:	fa03 f602 	lsl.w	r6, r3, r2
        mbedtls_mpi_free( &W[i] );
    811a:	270c      	movs	r7, #12
    for( i = ( one << ( wsize - 1 ) ); i < ( one << wsize ); i++ )
    811c:	42ae      	cmp	r6, r5
    811e:	f200 80ed 	bhi.w	82fc <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x2fc>

    mbedtls_mpi_free( &W[1] ); mbedtls_mpi_free( &T ); mbedtls_mpi_free( &Apos );
    8122:	a81d      	add	r0, sp, #116	; 0x74
    8124:	f7ff f94c 	bl	73c0 <mbedtls_mpi_free>
    8128:	a80e      	add	r0, sp, #56	; 0x38
    812a:	f7ff f949 	bl	73c0 <mbedtls_mpi_free>
    812e:	a814      	add	r0, sp, #80	; 0x50
    8130:	f7ff f946 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &WW );
    8134:	a811      	add	r0, sp, #68	; 0x44
    8136:	f7ff f943 	bl	73c0 <mbedtls_mpi_free>

    if( _RR == NULL || _RR->p == NULL )
    813a:	9be4      	ldr	r3, [sp, #912]	; 0x390
    813c:	b10b      	cbz	r3, 8142 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x142>
    813e:	689b      	ldr	r3, [r3, #8]
    8140:	b913      	cbnz	r3, 8148 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x148>
        mbedtls_mpi_free( &RR );
    8142:	a80b      	add	r0, sp, #44	; 0x2c
    8144:	f7ff f93c 	bl	73c0 <mbedtls_mpi_free>

    return( ret );
}
    8148:	4620      	mov	r0, r4
    814a:	f50d 7d5b 	add.w	sp, sp, #876	; 0x36c
    814e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    wsize = ( i > 671 ) ? 6 : ( i > 239 ) ? 5 :
    8152:	2306      	movs	r3, #6
    8154:	e70f      	b.n	7f76 <mbedtls_mpi_exp_mod+0xb8>
    8156:	2305      	movs	r3, #5
    8158:	e70d      	b.n	7f76 <mbedtls_mpi_exp_mod+0xb8>
    815a:	2304      	movs	r3, #4
    815c:	e70b      	b.n	7f76 <mbedtls_mpi_exp_mod+0xb8>
        memcpy( &RR, _RR, sizeof( mbedtls_mpi ) );
    815e:	99e4      	ldr	r1, [sp, #912]	; 0x390
    8160:	220c      	movs	r2, #12
    8162:	a80b      	add	r0, sp, #44	; 0x2c
    8164:	e759      	b.n	801a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x1a>
        MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &W[1], A ) );
    8166:	4641      	mov	r1, r8
    8168:	a81d      	add	r0, sp, #116	; 0x74
    816a:	f7ff f97c 	bl	7466 <mbedtls_mpi_copy>
    816e:	e76a      	b.n	8046 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x46>
        j =  one << ( wsize - 1 );
    8170:	9b03      	ldr	r3, [sp, #12]
        MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[j], N->n + 1 ) );
    8172:	6869      	ldr	r1, [r5, #4]
        j =  one << ( wsize - 1 );
    8174:	f103 38ff 	add.w	r8, r3, #4294967295
    8178:	fa07 f308 	lsl.w	r3, r7, r8
        MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[j], N->n + 1 ) );
    817c:	270c      	movs	r7, #12
        j =  one << ( wsize - 1 );
    817e:	9305      	str	r3, [sp, #20]
        MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[j], N->n + 1 ) );
    8180:	fa07 f708 	lsl.w	r7, r7, r8
    8184:	ab1a      	add	r3, sp, #104	; 0x68
    8186:	441f      	add	r7, r3
    8188:	3101      	adds	r1, #1
    818a:	4638      	mov	r0, r7
    818c:	f7ff f92a 	bl	73e4 <mbedtls_mpi_grow>
    8190:	2800      	cmp	r0, #0
    8192:	d1b9      	bne.n	8108 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x108>
        MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &W[j], &W[1]    ) );
    8194:	a91d      	add	r1, sp, #116	; 0x74
    8196:	4638      	mov	r0, r7
    8198:	f7ff f965 	bl	7466 <mbedtls_mpi_copy>
    819c:	2800      	cmp	r0, #0
    819e:	d1b3      	bne.n	8108 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x108>
        for( i = 0; i < wsize - 1; i++ )
    81a0:	46a2      	mov	sl, r4
            mpi_montmul( &W[j], &W[j], N, mm, &T );
    81a2:	f8cd 9000 	str.w	r9, [sp]
    81a6:	465b      	mov	r3, fp
    81a8:	462a      	mov	r2, r5
    81aa:	4639      	mov	r1, r7
    81ac:	4638      	mov	r0, r7
        for( i = 0; i < wsize - 1; i++ )
    81ae:	f10a 0a01 	add.w	sl, sl, #1
            mpi_montmul( &W[j], &W[j], N, mm, &T );
    81b2:	f7ff f860 	bl	7276 <mpi_montmul>
        for( i = 0; i < wsize - 1; i++ )
    81b6:	45d0      	cmp	r8, sl
    81b8:	d8f3      	bhi.n	81a2 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x1a2>
        for( i = j + 1; i < ( one << wsize ); i++ )
    81ba:	9b05      	ldr	r3, [sp, #20]
    81bc:	f103 0801 	add.w	r8, r3, #1
    81c0:	9b03      	ldr	r3, [sp, #12]
    81c2:	f04f 0a01 	mov.w	sl, #1
    81c6:	fa0a fa03 	lsl.w	sl, sl, r3
    81ca:	45c2      	cmp	sl, r8
    81cc:	f67f af62 	bls.w	8094 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x94>
            MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[i], N->n + 1 ) );
    81d0:	6869      	ldr	r1, [r5, #4]
    81d2:	f107 090c 	add.w	r9, r7, #12
    81d6:	3101      	adds	r1, #1
    81d8:	4648      	mov	r0, r9
    81da:	f7ff f903 	bl	73e4 <mbedtls_mpi_grow>
    81de:	2800      	cmp	r0, #0
    81e0:	d192      	bne.n	8108 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x108>
            MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &W[i], &W[i - 1] ) );
    81e2:	4639      	mov	r1, r7
    81e4:	4648      	mov	r0, r9
    81e6:	f7ff f93e 	bl	7466 <mbedtls_mpi_copy>
    81ea:	2800      	cmp	r0, #0
    81ec:	d18c      	bne.n	8108 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x108>
            mpi_montmul( &W[i], &W[1], N, mm, &T );
    81ee:	ab0e      	add	r3, sp, #56	; 0x38
    81f0:	9300      	str	r3, [sp, #0]
    81f2:	462a      	mov	r2, r5
    81f4:	465b      	mov	r3, fp
    81f6:	a91d      	add	r1, sp, #116	; 0x74
    81f8:	4648      	mov	r0, r9
    81fa:	f7ff f83c 	bl	7276 <mpi_montmul>
        for( i = j + 1; i < ( one << wsize ); i++ )
    81fe:	f108 0801 	add.w	r8, r8, #1
    8202:	464f      	mov	r7, r9
    8204:	e7e1      	b.n	81ca <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x1ca>
        state = 2;
    8206:	f04f 0802 	mov.w	r8, #2
    820a:	e74c      	b.n	80a6 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0xa6>
            bufsize = sizeof( mbedtls_mpi_uint ) << 3;
    820c:	2320      	movs	r3, #32
            nblimbs--;
    820e:	f109 39ff 	add.w	r9, r9, #4294967295
            bufsize = sizeof( mbedtls_mpi_uint ) << 3;
    8212:	9305      	str	r3, [sp, #20]
        bufsize--;
    8214:	9b05      	ldr	r3, [sp, #20]
    8216:	3b01      	subs	r3, #1
    8218:	9305      	str	r3, [sp, #20]
        ei = (E->p[nblimbs] >> bufsize) & 1;
    821a:	9b04      	ldr	r3, [sp, #16]
    821c:	9a05      	ldr	r2, [sp, #20]
    821e:	689b      	ldr	r3, [r3, #8]
    8220:	f853 3029 	ldr.w	r3, [r3, r9, lsl #2]
    8224:	40d3      	lsrs	r3, r2
        if( ei == 0 && state == 0 )
    8226:	f013 0301 	ands.w	r3, r3, #1
    822a:	d10f      	bne.n	824c <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x24c>
    822c:	f1b8 0f00 	cmp.w	r8, #0
    8230:	f43f af39 	beq.w	80a6 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0xa6>
        if( ei == 0 && state == 1 )
    8234:	f1b8 0f01 	cmp.w	r8, #1
    8238:	d108      	bne.n	824c <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x24c>
            mpi_montmul( X, X, N, mm, &T );
    823a:	ab0e      	add	r3, sp, #56	; 0x38
    823c:	9300      	str	r3, [sp, #0]
    823e:	462a      	mov	r2, r5
    8240:	465b      	mov	r3, fp
    8242:	4631      	mov	r1, r6
    8244:	4630      	mov	r0, r6
    8246:	f7ff f816 	bl	7276 <mpi_montmul>
            continue;
    824a:	e72c      	b.n	80a6 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0xa6>
        wbits |= ( ei << ( wsize - nbits ) );
    824c:	9a03      	ldr	r2, [sp, #12]
        nbits++;
    824e:	3701      	adds	r7, #1
        wbits |= ( ei << ( wsize - nbits ) );
    8250:	1bd2      	subs	r2, r2, r7
    8252:	4093      	lsls	r3, r2
    8254:	ea4a 0a03 	orr.w	sl, sl, r3
        if( nbits == wsize )
    8258:	9b03      	ldr	r3, [sp, #12]
    825a:	42bb      	cmp	r3, r7
    825c:	d1d3      	bne.n	8206 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x206>
            for( i = 0; i < wsize; i++ )
    825e:	f04f 0800 	mov.w	r8, #0
                mpi_montmul( X, X, N, mm, &T );
    8262:	ab0e      	add	r3, sp, #56	; 0x38
    8264:	9300      	str	r3, [sp, #0]
    8266:	462a      	mov	r2, r5
    8268:	465b      	mov	r3, fp
    826a:	4631      	mov	r1, r6
    826c:	4630      	mov	r0, r6
            for( i = 0; i < wsize; i++ )
    826e:	f108 0801 	add.w	r8, r8, #1
                mpi_montmul( X, X, N, mm, &T );
    8272:	f7ff f800 	bl	7276 <mpi_montmul>
            for( i = 0; i < wsize; i++ )
    8276:	4547      	cmp	r7, r8
    8278:	d8f3      	bhi.n	8262 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x262>
            MBEDTLS_MPI_CHK( mpi_select( &WW, W, (size_t) 1 << wsize, wbits ) );
    827a:	2301      	movs	r3, #1
    827c:	40bb      	lsls	r3, r7
    827e:	9308      	str	r3, [sp, #32]
    for( size_t i = 0; i < T_size; i++ )
    8280:	a91a      	add	r1, sp, #104	; 0x68
    8282:	f04f 0800 	mov.w	r8, #0
    const size_t diff = x ^ y;
    8286:	ea8a 0308 	eor.w	r3, sl, r8
    const size_t diff_msb = ( diff | (size_t) -diff );
    828a:	425a      	negs	r2, r3
    828c:	431a      	orrs	r2, r3
        MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( R, &T[i],
    828e:	43d2      	mvns	r2, r2
    8290:	0fd2      	lsrs	r2, r2, #31
    8292:	a811      	add	r0, sp, #68	; 0x44
    8294:	9109      	str	r1, [sp, #36]	; 0x24
    8296:	f7ff f918 	bl	74ca <mbedtls_mpi_safe_cond_assign>
    829a:	4607      	mov	r7, r0
    829c:	bb60      	cbnz	r0, 82f8 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x2f8>
    for( size_t i = 0; i < T_size; i++ )
    829e:	9b08      	ldr	r3, [sp, #32]
    82a0:	9909      	ldr	r1, [sp, #36]	; 0x24
    82a2:	f108 0801 	add.w	r8, r8, #1
    82a6:	4543      	cmp	r3, r8
    82a8:	f101 010c 	add.w	r1, r1, #12
    82ac:	d1eb      	bne.n	8286 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x286>
            mpi_montmul( X, &WW, N, mm, &T );
    82ae:	ab0e      	add	r3, sp, #56	; 0x38
    82b0:	9300      	str	r3, [sp, #0]
    82b2:	462a      	mov	r2, r5
    82b4:	465b      	mov	r3, fp
    82b6:	a911      	add	r1, sp, #68	; 0x44
    82b8:	4630      	mov	r0, r6
    82ba:	f7fe ffdc 	bl	7276 <mpi_montmul>
            nbits = 0;
    82be:	46ba      	mov	sl, r7
            state--;
    82c0:	f8dd 801c 	ldr.w	r8, [sp, #28]
    82c4:	e6ef      	b.n	80a6 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0xa6>
        mpi_montmul( X, X, N, mm, &T );
    82c6:	465b      	mov	r3, fp
    82c8:	f8cd 8000 	str.w	r8, [sp]
    82cc:	462a      	mov	r2, r5
    82ce:	4631      	mov	r1, r6
    82d0:	4630      	mov	r0, r6
    82d2:	f7fe ffd0 	bl	7276 <mpi_montmul>
        if( ( wbits & ( one << wsize ) ) != 0 )
    82d6:	9b05      	ldr	r3, [sp, #20]
        wbits <<= 1;
    82d8:	ea4f 0a4a 	mov.w	sl, sl, lsl #1
        if( ( wbits & ( one << wsize ) ) != 0 )
    82dc:	ea13 0f0a 	tst.w	r3, sl
    82e0:	d007      	beq.n	82f2 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x2f2>
            mpi_montmul( X, &W[1], N, mm, &T );
    82e2:	f8cd 8000 	str.w	r8, [sp]
    82e6:	465b      	mov	r3, fp
    82e8:	462a      	mov	r2, r5
    82ea:	a91d      	add	r1, sp, #116	; 0x74
    82ec:	4630      	mov	r0, r6
    82ee:	f7fe ffc2 	bl	7276 <mpi_montmul>
    for( i = 0; i < nbits; i++ )
    82f2:	f109 0901 	add.w	r9, r9, #1
    82f6:	e6e4      	b.n	80c2 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0xc2>
    82f8:	4604      	mov	r4, r0
    82fa:	e706      	b.n	810a <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x10a>
        mbedtls_mpi_free( &W[i] );
    82fc:	ab1a      	add	r3, sp, #104	; 0x68
    82fe:	fb07 3005 	mla	r0, r7, r5, r3
    8302:	f7ff f85d 	bl	73c0 <mbedtls_mpi_free>
    for( i = ( one << ( wsize - 1 ) ); i < ( one << wsize ); i++ )
    8306:	3501      	adds	r5, #1
    8308:	e708      	b.n	811c <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x11c>
        return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA );
    830a:	f06f 0403 	mvn.w	r4, #3
    830e:	e71b      	b.n	8148 <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0x148>

00008310 <platform_calloc_uninit>:
}
    8310:	2000      	movs	r0, #0
    8312:	4770      	bx	lr

00008314 <platform_exit_uninit>:
 * Make dummy function to prevent NULL pointer dereferences
 */
static void platform_exit_uninit( int status )
{
    ((void) status);
}
    8314:	4770      	bx	lr

00008316 <platform_free_uninit>:
    8316:	4770      	bx	lr

00008318 <mbedtls_rsa_import>:
{
    8318:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    831c:	4605      	mov	r5, r0
    831e:	e9dd 7608 	ldrd	r7, r6, [sp, #32]
    8322:	4691      	mov	r9, r2
    8324:	4698      	mov	r8, r3
    if( ( N != NULL && ( ret = mbedtls_mpi_copy( &ctx->N, N ) ) != 0 ) ||
    8326:	460c      	mov	r4, r1
    8328:	b979      	cbnz	r1, 834a <mbedtls_rsa_import+0x32>
    832a:	f1b9 0f00 	cmp.w	r9, #0
    832e:	d115      	bne.n	835c <mbedtls_rsa_import+0x44>
        ( P != NULL && ( ret = mbedtls_mpi_copy( &ctx->P, P ) ) != 0 ) ||
    8330:	f1b8 0f00 	cmp.w	r8, #0
    8334:	d11a      	bne.n	836c <mbedtls_rsa_import+0x54>
        ( Q != NULL && ( ret = mbedtls_mpi_copy( &ctx->Q, Q ) ) != 0 ) ||
    8336:	bb0f      	cbnz	r7, 837c <mbedtls_rsa_import+0x64>
        ( D != NULL && ( ret = mbedtls_mpi_copy( &ctx->D, D ) ) != 0 ) ||
    8338:	bb46      	cbnz	r6, 838c <mbedtls_rsa_import+0x74>
    if( N != NULL )
    833a:	b37c      	cbz	r4, 839c <mbedtls_rsa_import+0x84>
        ctx->len = mbedtls_mpi_size( &ctx->N );
    833c:	f105 0008 	add.w	r0, r5, #8
    8340:	f7ff f938 	bl	75b4 <mbedtls_mpi_size>
    8344:	6068      	str	r0, [r5, #4]
    return( 0 );
    8346:	2000      	movs	r0, #0
    8348:	e006      	b.n	8358 <mbedtls_rsa_import+0x40>
    if( ( N != NULL && ( ret = mbedtls_mpi_copy( &ctx->N, N ) ) != 0 ) ||
    834a:	3008      	adds	r0, #8
    834c:	f7ff f88b 	bl	7466 <mbedtls_mpi_copy>
    8350:	2800      	cmp	r0, #0
    8352:	d0ea      	beq.n	832a <mbedtls_rsa_import+0x12>
    8354:	f5a0 4081 	sub.w	r0, r0, #16512	; 0x4080
}
    8358:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        ( P != NULL && ( ret = mbedtls_mpi_copy( &ctx->P, P ) ) != 0 ) ||
    835c:	4649      	mov	r1, r9
    835e:	f105 002c 	add.w	r0, r5, #44	; 0x2c
    8362:	f7ff f880 	bl	7466 <mbedtls_mpi_copy>
    8366:	2800      	cmp	r0, #0
    8368:	d0e2      	beq.n	8330 <mbedtls_rsa_import+0x18>
    836a:	e7f3      	b.n	8354 <mbedtls_rsa_import+0x3c>
        ( Q != NULL && ( ret = mbedtls_mpi_copy( &ctx->Q, Q ) ) != 0 ) ||
    836c:	4641      	mov	r1, r8
    836e:	f105 0038 	add.w	r0, r5, #56	; 0x38
    8372:	f7ff f878 	bl	7466 <mbedtls_mpi_copy>
    8376:	2800      	cmp	r0, #0
    8378:	d0dd      	beq.n	8336 <mbedtls_rsa_import+0x1e>
    837a:	e7eb      	b.n	8354 <mbedtls_rsa_import+0x3c>
        ( D != NULL && ( ret = mbedtls_mpi_copy( &ctx->D, D ) ) != 0 ) ||
    837c:	4639      	mov	r1, r7
    837e:	f105 0020 	add.w	r0, r5, #32
    8382:	f7ff f870 	bl	7466 <mbedtls_mpi_copy>
    8386:	2800      	cmp	r0, #0
    8388:	d0d6      	beq.n	8338 <mbedtls_rsa_import+0x20>
    838a:	e7e3      	b.n	8354 <mbedtls_rsa_import+0x3c>
        ( E != NULL && ( ret = mbedtls_mpi_copy( &ctx->E, E ) ) != 0 ) )
    838c:	4631      	mov	r1, r6
    838e:	f105 0014 	add.w	r0, r5, #20
    8392:	f7ff f868 	bl	7466 <mbedtls_mpi_copy>
    8396:	2800      	cmp	r0, #0
    8398:	d0cf      	beq.n	833a <mbedtls_rsa_import+0x22>
    839a:	e7db      	b.n	8354 <mbedtls_rsa_import+0x3c>
    return( 0 );
    839c:	4620      	mov	r0, r4
    839e:	e7db      	b.n	8358 <mbedtls_rsa_import+0x40>

000083a0 <mbedtls_rsa_init>:
{
    83a0:	b510      	push	{r4, lr}
    memset( ctx, 0, sizeof( mbedtls_rsa_context ) );
    83a2:	22ac      	movs	r2, #172	; 0xac
    83a4:	2100      	movs	r1, #0
{
    83a6:	4604      	mov	r4, r0
    memset( ctx, 0, sizeof( mbedtls_rsa_context ) );
    83a8:	f7fe f8ab 	bl	6502 <memset>
    ctx->padding = MBEDTLS_RSA_PKCS_V15;
    83ac:	2300      	movs	r3, #0
    ctx->hash_id = MBEDTLS_MD_NONE;
    83ae:	e9c4 3329 	strd	r3, r3, [r4, #164]	; 0xa4
}
    83b2:	bd10      	pop	{r4, pc}

000083b4 <mbedtls_rsa_free>:

/*
 * Free the components of an RSA key
 */
void mbedtls_rsa_free( mbedtls_rsa_context *ctx )
{
    83b4:	b510      	push	{r4, lr}
    if( ctx == NULL )
    83b6:	4604      	mov	r4, r0
    83b8:	b3a0      	cbz	r0, 8424 <mbedtls_rsa_free+0x70>
        return;

    mbedtls_mpi_free( &ctx->Vi );
    83ba:	308c      	adds	r0, #140	; 0x8c
    83bc:	f7ff f800 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &ctx->Vf );
    83c0:	f104 0098 	add.w	r0, r4, #152	; 0x98
    83c4:	f7fe fffc 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &ctx->RN );
    83c8:	f104 0068 	add.w	r0, r4, #104	; 0x68
    83cc:	f7fe fff8 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &ctx->D  );
    83d0:	f104 0020 	add.w	r0, r4, #32
    83d4:	f7fe fff4 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &ctx->Q  );
    83d8:	f104 0038 	add.w	r0, r4, #56	; 0x38
    83dc:	f7fe fff0 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &ctx->P  );
    83e0:	f104 002c 	add.w	r0, r4, #44	; 0x2c
    83e4:	f7fe ffec 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &ctx->E  );
    83e8:	f104 0014 	add.w	r0, r4, #20
    83ec:	f7fe ffe8 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &ctx->N  );
    83f0:	f104 0008 	add.w	r0, r4, #8
    83f4:	f7fe ffe4 	bl	73c0 <mbedtls_mpi_free>

#if !defined(MBEDTLS_RSA_NO_CRT)
    mbedtls_mpi_free( &ctx->RQ );
    83f8:	f104 0080 	add.w	r0, r4, #128	; 0x80
    83fc:	f7fe ffe0 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &ctx->RP );
    8400:	f104 0074 	add.w	r0, r4, #116	; 0x74
    8404:	f7fe ffdc 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &ctx->QP );
    8408:	f104 005c 	add.w	r0, r4, #92	; 0x5c
    840c:	f7fe ffd8 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &ctx->DQ );
    8410:	f104 0050 	add.w	r0, r4, #80	; 0x50
    8414:	f7fe ffd4 	bl	73c0 <mbedtls_mpi_free>
    mbedtls_mpi_free( &ctx->DP );
    8418:	f104 0044 	add.w	r0, r4, #68	; 0x44
    {
        mbedtls_mutex_free( &ctx->mutex );
        ctx->ver = 0;
    }
#endif
}
    841c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    mbedtls_mpi_free( &ctx->DP );
    8420:	f7fe bfce 	b.w	73c0 <mbedtls_mpi_free>
}
    8424:	bd10      	pop	{r4, pc}

00008426 <mbedtls_sha256_init>:
    memset( ctx, 0, sizeof( mbedtls_sha256_context ) );
    8426:	226c      	movs	r2, #108	; 0x6c
    8428:	2100      	movs	r1, #0
    842a:	f7fe b86a 	b.w	6502 <memset>

0000842e <mbedtls_sha256_update>:
 * SHA-256 process buffer
 */
int mbedtls_sha256_update( mbedtls_sha256_context *ctx,
                               const unsigned char *input,
                               size_t ilen )
{
    842e:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    8432:	4605      	mov	r5, r0
    8434:	460e      	mov	r6, r1
    uint32_t left;

    SHA256_VALIDATE_RET( ctx != NULL );
    SHA256_VALIDATE_RET( ilen == 0 || input != NULL );

    if( ilen == 0 )
    8436:	4614      	mov	r4, r2
    8438:	b912      	cbnz	r2, 8440 <mbedtls_sha256_update+0x12>
    }

    if( ilen > 0 )
        memcpy( (void *) (ctx->buffer + left), input, ilen );

    return( 0 );
    843a:	2000      	movs	r0, #0
}
    843c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    left = ctx->total[0] & 0x3F;
    8440:	6803      	ldr	r3, [r0, #0]
    8442:	f003 073f 	and.w	r7, r3, #63	; 0x3f
    ctx->total[0] += (uint32_t) ilen;
    8446:	18d3      	adds	r3, r2, r3
    8448:	6003      	str	r3, [r0, #0]
        ctx->total[1]++;
    844a:	bf22      	ittt	cs
    844c:	6843      	ldrcs	r3, [r0, #4]
    844e:	3301      	addcs	r3, #1
    8450:	6043      	strcs	r3, [r0, #4]
    if( left && ilen >= fill )
    8452:	b1a7      	cbz	r7, 847e <mbedtls_sha256_update+0x50>
    fill = 64 - left;
    8454:	f1c7 0940 	rsb	r9, r7, #64	; 0x40
    if( left && ilen >= fill )
    8458:	454a      	cmp	r2, r9
    845a:	d310      	bcc.n	847e <mbedtls_sha256_update+0x50>
        memcpy( (void *) (ctx->buffer + left), input, fill );
    845c:	f100 0828 	add.w	r8, r0, #40	; 0x28
    8460:	464a      	mov	r2, r9
    8462:	eb08 0007 	add.w	r0, r8, r7
    8466:	f7fe f841 	bl	64ec <memcpy>
        if( ( ret = mbedtls_internal_sha256_process( ctx, ctx->buffer ) ) != 0 )
    846a:	4641      	mov	r1, r8
    846c:	4628      	mov	r0, r5
    846e:	f7fc f8d7 	bl	4620 <mbedtls_internal_sha256_process>
    8472:	2800      	cmp	r0, #0
    8474:	d1e2      	bne.n	843c <mbedtls_sha256_update+0xe>
        ilen  -= fill;
    8476:	443c      	add	r4, r7
        input += fill;
    8478:	444e      	add	r6, r9
        ilen  -= fill;
    847a:	3c40      	subs	r4, #64	; 0x40
        left = 0;
    847c:	4607      	mov	r7, r0
    847e:	4426      	add	r6, r4
    8480:	e005      	b.n	848e <mbedtls_sha256_update+0x60>
        if( ( ret = mbedtls_internal_sha256_process( ctx, input ) ) != 0 )
    8482:	4628      	mov	r0, r5
    8484:	f7fc f8cc 	bl	4620 <mbedtls_internal_sha256_process>
    8488:	2800      	cmp	r0, #0
    848a:	d1d7      	bne.n	843c <mbedtls_sha256_update+0xe>
        ilen  -= 64;
    848c:	3c40      	subs	r4, #64	; 0x40
    while( ilen >= 64 )
    848e:	2c3f      	cmp	r4, #63	; 0x3f
    8490:	eba6 0104 	sub.w	r1, r6, r4
    8494:	d8f5      	bhi.n	8482 <mbedtls_sha256_update+0x54>
    if( ilen > 0 )
    8496:	2c00      	cmp	r4, #0
    8498:	d0cf      	beq.n	843a <mbedtls_sha256_update+0xc>
        memcpy( (void *) (ctx->buffer + left), input, ilen );
    849a:	f105 0028 	add.w	r0, r5, #40	; 0x28
    849e:	4622      	mov	r2, r4
    84a0:	4438      	add	r0, r7
    84a2:	f7fe f823 	bl	64ec <memcpy>
    84a6:	e7c8      	b.n	843a <mbedtls_sha256_update+0xc>

000084a8 <mbedtls_sha256_finish>:
    SHA256_VALIDATE_RET( (unsigned char *)output != NULL );

    /*
     * Add padding: 0x80 then 0x00 until 8 bytes remain for the length
     */
    used = ctx->total[0] & 0x3F;
    84a8:	6803      	ldr	r3, [r0, #0]
    84aa:	f003 033f 	and.w	r3, r3, #63	; 0x3f

    ctx->buffer[used++] = 0x80;
    84ae:	1c5a      	adds	r2, r3, #1
    84b0:	4403      	add	r3, r0
{
    84b2:	b570      	push	{r4, r5, r6, lr}

    if( used <= 56 )
    84b4:	2a38      	cmp	r2, #56	; 0x38
{
    84b6:	460d      	mov	r5, r1
    {
        /* Enough room for padding + length in current block */
        memset( ctx->buffer + used, 0, 56 - used );
    84b8:	f100 0628 	add.w	r6, r0, #40	; 0x28
    ctx->buffer[used++] = 0x80;
    84bc:	f04f 0180 	mov.w	r1, #128	; 0x80
{
    84c0:	4604      	mov	r4, r0
    ctx->buffer[used++] = 0x80;
    84c2:	f883 1028 	strb.w	r1, [r3, #40]	; 0x28
        memset( ctx->buffer + used, 0, 56 - used );
    84c6:	eb06 0002 	add.w	r0, r6, r2
    if( used <= 56 )
    84ca:	d861      	bhi.n	8590 <mbedtls_sha256_finish+0xe8>
        memset( ctx->buffer + used, 0, 56 - used );
    84cc:	f1c2 0238 	rsb	r2, r2, #56	; 0x38
    84d0:	2100      	movs	r1, #0
        memset( ctx->buffer + used, 0, 64 - used );

        if( ( ret = mbedtls_internal_sha256_process( ctx, ctx->buffer ) ) != 0 )
            return( ret );

        memset( ctx->buffer, 0, 56 );
    84d2:	f7fe f816 	bl	6502 <memset>

    /*
     * Add message length
     */
    high = ( ctx->total[0] >> 29 )
         | ( ctx->total[1] <<  3 );
    84d6:	e9d4 3100 	ldrd	r3, r1, [r4]
    high = ( ctx->total[0] >> 29 )
    84da:	0f5a      	lsrs	r2, r3, #29
    84dc:	ea42 02c1 	orr.w	r2, r2, r1, lsl #3
    low  = ( ctx->total[0] <<  3 );
    84e0:	00db      	lsls	r3, r3, #3
    84e2:	ba12      	rev	r2, r2
    84e4:	ba1b      	rev	r3, r3

    PUT_UINT32_BE( high, ctx->buffer, 56 );
    84e6:	6622      	str	r2, [r4, #96]	; 0x60
    PUT_UINT32_BE( low,  ctx->buffer, 60 );
    84e8:	6663      	str	r3, [r4, #100]	; 0x64

    if( ( ret = mbedtls_internal_sha256_process( ctx, ctx->buffer ) ) != 0 )
    84ea:	4631      	mov	r1, r6
    84ec:	4620      	mov	r0, r4
    84ee:	f7fc f897 	bl	4620 <mbedtls_internal_sha256_process>
    84f2:	2800      	cmp	r0, #0
    84f4:	d14b      	bne.n	858e <mbedtls_sha256_finish+0xe6>
        return( ret );

    /*
     * Output final state
     */
    PUT_UINT32_BE( ctx->state[0], output,  0 );
    84f6:	7ae3      	ldrb	r3, [r4, #11]
    84f8:	702b      	strb	r3, [r5, #0]
    84fa:	8963      	ldrh	r3, [r4, #10]
    84fc:	706b      	strb	r3, [r5, #1]
    84fe:	68a3      	ldr	r3, [r4, #8]
    8500:	0a1b      	lsrs	r3, r3, #8
    8502:	70ab      	strb	r3, [r5, #2]
    8504:	68a3      	ldr	r3, [r4, #8]
    8506:	70eb      	strb	r3, [r5, #3]
    PUT_UINT32_BE( ctx->state[1], output,  4 );
    8508:	7be3      	ldrb	r3, [r4, #15]
    850a:	712b      	strb	r3, [r5, #4]
    850c:	89e3      	ldrh	r3, [r4, #14]
    850e:	716b      	strb	r3, [r5, #5]
    8510:	68e3      	ldr	r3, [r4, #12]
    8512:	0a1b      	lsrs	r3, r3, #8
    8514:	71ab      	strb	r3, [r5, #6]
    8516:	68e3      	ldr	r3, [r4, #12]
    8518:	71eb      	strb	r3, [r5, #7]
    PUT_UINT32_BE( ctx->state[2], output,  8 );
    851a:	7ce3      	ldrb	r3, [r4, #19]
    851c:	722b      	strb	r3, [r5, #8]
    851e:	8a63      	ldrh	r3, [r4, #18]
    8520:	726b      	strb	r3, [r5, #9]
    8522:	6923      	ldr	r3, [r4, #16]
    8524:	0a1b      	lsrs	r3, r3, #8
    8526:	72ab      	strb	r3, [r5, #10]
    8528:	6923      	ldr	r3, [r4, #16]
    852a:	72eb      	strb	r3, [r5, #11]
    PUT_UINT32_BE( ctx->state[3], output, 12 );
    852c:	7de3      	ldrb	r3, [r4, #23]
    852e:	732b      	strb	r3, [r5, #12]
    8530:	8ae3      	ldrh	r3, [r4, #22]
    8532:	736b      	strb	r3, [r5, #13]
    8534:	6963      	ldr	r3, [r4, #20]
    8536:	0a1b      	lsrs	r3, r3, #8
    8538:	73ab      	strb	r3, [r5, #14]
    853a:	6963      	ldr	r3, [r4, #20]
    853c:	73eb      	strb	r3, [r5, #15]
    PUT_UINT32_BE( ctx->state[4], output, 16 );
    853e:	7ee3      	ldrb	r3, [r4, #27]
    8540:	742b      	strb	r3, [r5, #16]
    8542:	8b63      	ldrh	r3, [r4, #26]
    8544:	746b      	strb	r3, [r5, #17]
    8546:	69a3      	ldr	r3, [r4, #24]
    8548:	0a1b      	lsrs	r3, r3, #8
    854a:	74ab      	strb	r3, [r5, #18]
    854c:	69a3      	ldr	r3, [r4, #24]
    854e:	74eb      	strb	r3, [r5, #19]
    PUT_UINT32_BE( ctx->state[5], output, 20 );
    8550:	7fe3      	ldrb	r3, [r4, #31]
    8552:	752b      	strb	r3, [r5, #20]
    8554:	8be3      	ldrh	r3, [r4, #30]
    8556:	756b      	strb	r3, [r5, #21]
    8558:	69e3      	ldr	r3, [r4, #28]
    855a:	0a1b      	lsrs	r3, r3, #8
    855c:	75ab      	strb	r3, [r5, #22]
    855e:	69e3      	ldr	r3, [r4, #28]
    8560:	75eb      	strb	r3, [r5, #23]
    PUT_UINT32_BE( ctx->state[6], output, 24 );
    8562:	f894 3023 	ldrb.w	r3, [r4, #35]	; 0x23
    8566:	762b      	strb	r3, [r5, #24]
    8568:	8c63      	ldrh	r3, [r4, #34]	; 0x22
    856a:	766b      	strb	r3, [r5, #25]
    856c:	6a23      	ldr	r3, [r4, #32]
    856e:	0a1b      	lsrs	r3, r3, #8
    8570:	76ab      	strb	r3, [r5, #26]
    8572:	6a23      	ldr	r3, [r4, #32]
    8574:	76eb      	strb	r3, [r5, #27]

#if defined(MBEDTLS_SHA224_C)
    if( ctx->is224 == 0 )
    8576:	6ea3      	ldr	r3, [r4, #104]	; 0x68
    8578:	b94b      	cbnz	r3, 858e <mbedtls_sha256_finish+0xe6>
#endif
        PUT_UINT32_BE( ctx->state[7], output, 28 );
    857a:	f894 3027 	ldrb.w	r3, [r4, #39]	; 0x27
    857e:	772b      	strb	r3, [r5, #28]
    8580:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
    8582:	776b      	strb	r3, [r5, #29]
    8584:	6a63      	ldr	r3, [r4, #36]	; 0x24
    8586:	0a1b      	lsrs	r3, r3, #8
    8588:	77ab      	strb	r3, [r5, #30]
    858a:	6a63      	ldr	r3, [r4, #36]	; 0x24
    858c:	77eb      	strb	r3, [r5, #31]

    return( 0 );
}
    858e:	bd70      	pop	{r4, r5, r6, pc}
        memset( ctx->buffer + used, 0, 64 - used );
    8590:	2100      	movs	r1, #0
    8592:	f1c2 0240 	rsb	r2, r2, #64	; 0x40
    8596:	f7fd ffb4 	bl	6502 <memset>
        if( ( ret = mbedtls_internal_sha256_process( ctx, ctx->buffer ) ) != 0 )
    859a:	4631      	mov	r1, r6
    859c:	4620      	mov	r0, r4
    859e:	f7fc f83f 	bl	4620 <mbedtls_internal_sha256_process>
    85a2:	2800      	cmp	r0, #0
    85a4:	d1f3      	bne.n	858e <mbedtls_sha256_finish+0xe6>
        memset( ctx->buffer, 0, 56 );
    85a6:	4601      	mov	r1, r0
    85a8:	2238      	movs	r2, #56	; 0x38
    85aa:	4630      	mov	r0, r6
    85ac:	e791      	b.n	84d2 <mbedtls_sha256_finish+0x2a>

000085ae <nrf52_errata_108>:
            if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF)
    85ae:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    85b2:	f8d3 0130 	ldr.w	r0, [r3, #304]	; 0x130
    85b6:	1c42      	adds	r2, r0, #1
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    85b8:	bf04      	itt	eq
    85ba:	f04f 4370 	moveq.w	r3, #4026531840	; 0xf0000000
    85be:	f893 0fe0 	ldrbeq.w	r0, [r3, #4064]	; 0xfe0
}
    85c2:	1f83      	subs	r3, r0, #6
    85c4:	4258      	negs	r0, r3
    85c6:	4158      	adcs	r0, r3
    85c8:	4770      	bx	lr

000085ca <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    85ca:	4700      	bx	r0

000085cc <nrfx_busy_wait>:
    85cc:	f000 b89a 	b.w	8704 <z_impl_k_busy_wait>

000085d0 <nrfx_clock_enable>:
{
    85d0:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    85d2:	2000      	movs	r0, #0
    85d4:	f7fa f942 	bl	285c <arch_irq_is_enabled>
    85d8:	b908      	cbnz	r0, 85de <nrfx_clock_enable+0xe>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    85da:	f7fa f92f 	bl	283c <arch_irq_enable>
    p_reg->LFCLKSRC = (uint32_t)(source);
    85de:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    85e2:	2200      	movs	r2, #0
    85e4:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    85e8:	bd08      	pop	{r3, pc}

000085ea <nrfx_clock_stop>:
    clock_stop(domain);
    85ea:	f7fc ba6b 	b.w	4ac4 <clock_stop>

000085ee <nrf_gpio_cfg_sense_set>:
    *p_pin = pin_number & 0x1F;
    85ee:	f000 001f 	and.w	r0, r0, #31
    85f2:	0080      	lsls	r0, r0, #2
    85f4:	f100 40a0 	add.w	r0, r0, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number];
    85f8:	f8d0 3700 	ldr.w	r3, [r0, #1792]	; 0x700
    cnf &= ~to_update;
    85fc:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    8600:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
    reg->PIN_CNF[pin_number] = cnf;
    8604:	f8c0 3700 	str.w	r3, [r0, #1792]	; 0x700
}
    8608:	4770      	bx	lr

0000860a <nrfx_nvmc_flash_size_get>:
    860a:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    860e:	691a      	ldr	r2, [r3, #16]
NRF_STATIC_INLINE uint32_t nrf_ficr_codesize_get(NRF_FICR_Type const * p_reg)
{
#if defined(FICR_INFO_CODESIZE_CODESIZE_Msk)
    return p_reg->INFO.CODESIZE;
#else
    return p_reg->CODESIZE;
    8610:	6958      	ldr	r0, [r3, #20]
}

uint32_t nrfx_nvmc_flash_size_get(void)
{
    return flash_total_size_get();
}
    8612:	4350      	muls	r0, r2
    8614:	4770      	bx	lr

00008616 <nrfx_nvmc_flash_page_size_get>:
    return p_reg->CODEPAGESIZE;
    8616:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    861a:	6918      	ldr	r0, [r3, #16]

uint32_t nrfx_nvmc_flash_page_size_get(void)
{
    return flash_page_size_get();
}
    861c:	4770      	bx	lr

0000861e <nrfx_nvmc_flash_page_count_get>:
    return p_reg->CODESIZE;
    861e:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    8622:	6958      	ldr	r0, [r3, #20]

uint32_t nrfx_nvmc_flash_page_count_get(void)
{
    return flash_page_count_get();
}
    8624:	4770      	bx	lr

00008626 <_GetAvailWriteSpace>:
  RdOff = pRing->RdOff;
    8626:	6903      	ldr	r3, [r0, #16]
  WrOff = pRing->WrOff;
    8628:	68c2      	ldr	r2, [r0, #12]
  if (RdOff <= WrOff) {
    862a:	4293      	cmp	r3, r2
    r = pRing->SizeOfBuffer - 1u - WrOff + RdOff;
    862c:	bf9c      	itt	ls
    862e:	6880      	ldrls	r0, [r0, #8]
    8630:	181b      	addls	r3, r3, r0
    r = RdOff - WrOff - 1u;
    8632:	3b01      	subs	r3, #1
    8634:	1a98      	subs	r0, r3, r2
}
    8636:	4770      	bx	lr

00008638 <_WriteNoCheck>:
static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) {
    8638:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  Rem = pRing->SizeOfBuffer - WrOff;
    863c:	e9d0 9402 	ldrd	r9, r4, [r0, #8]
static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) {
    8640:	4605      	mov	r5, r0
  Rem = pRing->SizeOfBuffer - WrOff;
    8642:	eba9 0804 	sub.w	r8, r9, r4
    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
    8646:	6840      	ldr	r0, [r0, #4]
  if (Rem > NumBytes) {
    8648:	4590      	cmp	r8, r2
    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
    864a:	4420      	add	r0, r4
static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) {
    864c:	460f      	mov	r7, r1
    pRing->WrOff = WrOff + NumBytes;
    864e:	4414      	add	r4, r2
  if (Rem > NumBytes) {
    8650:	d906      	bls.n	8660 <_WriteNoCheck+0x28>
    SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce);
    8652:	f7fd ff4b 	bl	64ec <memcpy>
    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
    8656:	f3bf 8f5f 	dmb	sy
    pRing->WrOff = NumBytesAtOnce;
    865a:	60ec      	str	r4, [r5, #12]
}
    865c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce);
    8660:	4642      	mov	r2, r8
    NumBytesAtOnce = NumBytes - Rem;
    8662:	eba4 0409 	sub.w	r4, r4, r9
    SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce);
    8666:	f7fd ff41 	bl	64ec <memcpy>
    SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce);
    866a:	6868      	ldr	r0, [r5, #4]
    866c:	4622      	mov	r2, r4
    866e:	eb07 0108 	add.w	r1, r7, r8
    8672:	e7ee      	b.n	8652 <_WriteNoCheck+0x1a>

00008674 <_WriteBlocking>:
static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) {
    8674:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  WrOff = pRing->WrOff;
    8678:	68c5      	ldr	r5, [r0, #12]
static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) {
    867a:	4606      	mov	r6, r0
    867c:	4689      	mov	r9, r1
    867e:	4617      	mov	r7, r2
  NumBytesWritten = 0u;
    8680:	f04f 0800 	mov.w	r8, #0
    RdOff = pRing->RdOff;                         // May be changed by host (debug probe) in the meantime
    8684:	6934      	ldr	r4, [r6, #16]
      NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u);
    8686:	68b3      	ldr	r3, [r6, #8]
    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
    8688:	6870      	ldr	r0, [r6, #4]
    if (RdOff > WrOff) {
    868a:	42a5      	cmp	r5, r4
      NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u);
    868c:	bf28      	it	cs
    868e:	18e4      	addcs	r4, r4, r3
    8690:	3c01      	subs	r4, #1
    8692:	1b62      	subs	r2, r4, r5
    NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff));      // Number of bytes that can be written until buffer wrap-around
    8694:	1b5c      	subs	r4, r3, r5
    NumBytesToWrite = MIN(NumBytesToWrite, NumBytes);
    8696:	42bc      	cmp	r4, r7
    8698:	bf28      	it	cs
    869a:	463c      	movcs	r4, r7
    869c:	4294      	cmp	r4, r2
    869e:	bf28      	it	cs
    86a0:	4614      	movcs	r4, r2
    SEGGER_RTT_MEMCPY((void*)pDst, pBuffer, NumBytesToWrite);
    86a2:	4649      	mov	r1, r9
    86a4:	4622      	mov	r2, r4
    86a6:	4428      	add	r0, r5
    86a8:	f7fd ff20 	bl	64ec <memcpy>
    if (WrOff == pRing->SizeOfBuffer) {
    86ac:	68b3      	ldr	r3, [r6, #8]
    WrOff           += NumBytesToWrite;
    86ae:	4425      	add	r5, r4
    NumBytesWritten += NumBytesToWrite;
    86b0:	44a0      	add	r8, r4
    pBuffer         += NumBytesToWrite;
    86b2:	44a1      	add	r9, r4
    NumBytes        -= NumBytesToWrite;
    86b4:	1b3f      	subs	r7, r7, r4
      WrOff = 0u;
    86b6:	42ab      	cmp	r3, r5
    86b8:	bf08      	it	eq
    86ba:	2500      	moveq	r5, #0
    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
    86bc:	f3bf 8f5f 	dmb	sy
    pRing->WrOff = WrOff;
    86c0:	60f5      	str	r5, [r6, #12]
  } while (NumBytes);
    86c2:	2f00      	cmp	r7, #0
    86c4:	d1de      	bne.n	8684 <_WriteBlocking+0x10>
}
    86c6:	4640      	mov	r0, r8
    86c8:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

000086cc <SEGGER_RTT_Init>:
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
  _DoInit();
    86cc:	f7fc be4a 	b.w	5364 <_DoInit>

000086d0 <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(const struct device *unused)
{
    86d0:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	SEGGER_RTT_Init();
    86d2:	f7ff fffb 	bl	86cc <SEGGER_RTT_Init>

	return 0;
}
    86d6:	2000      	movs	r0, #0
    86d8:	bd08      	pop	{r3, pc}

000086da <z_device_state_init>:
}
    86da:	4770      	bx	lr

000086dc <z_device_is_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    86dc:	b138      	cbz	r0, 86ee <z_device_is_ready+0x12>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    86de:	68c3      	ldr	r3, [r0, #12]
    86e0:	8818      	ldrh	r0, [r3, #0]
    86e2:	f3c0 0008 	ubfx	r0, r0, #0, #9
    86e6:	f5a0 7380 	sub.w	r3, r0, #256	; 0x100
    86ea:	4258      	negs	r0, r3
    86ec:	4158      	adcs	r0, r3
}
    86ee:	4770      	bx	lr

000086f0 <z_early_memset>:
	(void) memset(dst, c, n);
    86f0:	f7fd bf07 	b.w	6502 <memset>

000086f4 <z_early_memcpy>:
	(void) memcpy(dst, src, n);
    86f4:	f7fd befa 	b.w	64ec <memcpy>

000086f8 <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    86f8:	f3ef 8005 	mrs	r0, IPSR
}

bool k_is_in_isr(void)
{
	return arch_is_in_isr();
}
    86fc:	3800      	subs	r0, #0
    86fe:	bf18      	it	ne
    8700:	2001      	movne	r0, #1
    8702:	4770      	bx	lr

00008704 <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    8704:	b108      	cbz	r0, 870a <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    8706:	f7fa bc91 	b.w	302c <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    870a:	4770      	bx	lr

0000870c <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    870c:	4770      	bx	lr
	...

00008710 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    8710:	f7fc b84c 	b.w	47ac <SystemInit>
