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Nordic Thingy:52 v2.1.0
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47 #ifndef __DRV_ACC_LIS3DH_TYPES_H__
48 #define __DRV_ACC_LIS3DH_TYPES_H__
143 #define STATUS_AUX 0x07
144 #define STATUS_AUX_TOR BIT_6
145 #define STATUS_AUX_TDA BIT_2
148 #define OUT_TEMP_L 0x0C
149 #define OUT_TEMP_H 0x0D
152 #define WHO_AM_I 0x0F
153 #define I_AM_LIS3DH 0x33
156 #define CTRL_REG0 0x1E
157 #define CTRL_REG0_SDO_PU_DISC BIT_7
158 #define CTRL_REG0_CORRECT_OPER BIT_4
161 #define TEMP_CFG_REG 0x1F
162 #define TEMP_CFG_REG_TEMP1_EN BIT_7
163 #define TEMP_CFG_REG_TEMP2_EN BIT_6
166 #define CTRL_REG1 0x20
167 #define CTRL_REG1_ODR_BITS_MASK 0xF0
168 #define CTRL_REG1_ODR_BIT BIT_4
169 #define CTRL_REG1_LPEN BIT_3
170 #define CTRL_REG1_ZEN BIT_2
171 #define CTRL_REG1_YEN BIT_1
172 #define CTRL_REG1_XEN BIT_0
175 #define CTRL_REG2 0x21
176 #define CTRL_REG2_HPM BIT_6
177 #define CTRL_REG2_HPCF BIT_4
178 #define CTRL_REG2_FDS BIT_3
179 #define CTRL_REG2_HPCLICK BIT_2
180 #define CTRL_REG2_HP_IA2 BIT_1
181 #define CTRL_REG2_HP_IA1 BIT_0
184 #define CTRL_REG3 0x22
185 #define CTRL_REG3_I1_CLICK BIT_7
186 #define CTRL_REG3_I1_IA1 BIT_6
187 #define CTRL_REG3_I1_IA2 BIT_5
188 #define CTRL_REG3_I1_ZYXDA BIT_4
189 #define CTRL_REG3_I1_WTM BIT_2
190 #define CTRL_REG3_I1_ORUN BIT_1
193 #define CTRL_REG4 0x23
194 #define CTRL_REG4_BDU BIT_7
195 #define CTRL_REG4_BLE BIT_6
196 #define CTRL_REG4_FS1 BIT_5
197 #define CTRL_REG4_FS0 BIT_4
198 #define CTRL_REG4_HR BIT_3
199 #define CTRL_REG4_ST BIT_1
200 #define CTRL_REG4_SIM BIT_0
203 #define CTRL_REG5 0x24
204 #define CTRL_REG5_BOOT BIT_7
205 #define CTRL_REG5_FIFO_EN BIT_6
206 #define CTRL_REG5_LIR_INT1 BIT_3
207 #define CTRL_REG5_D4D_INT1 BIT_2
208 #define CTRL_REG5_LIR_INT2 BIT_1
209 #define CTRL_REG5_D4D_INT2 BIT_0
212 #define CTRL_REG6 0x25
213 #define CTRL_REG_6_I2_CLICK BIT_7
214 #define CTRL_REG_6_I2_IA1 BIT_6
215 #define CTRL_REG_6_I2_IA2 BIT_5
216 #define CTRL_REG_6_I2_BOOT BIT_4
217 #define CTRL_REG_6_I2_ACT BIT_3
218 #define CTRL_REG_6_INT_POLARITY BIT_1
221 #define REFERENCE_REG 0x26
225 #define STATUS_REG 0x27
244 #define FIFO_CTRL_REG 0x2E
245 #define FIFO_CTRL_REG_FM1 BIT_7
246 #define FIFO_CTRL_REG_FM0 BIT_6
247 #define FIFO_CTRL_REG_TR BIT_5
248 #define FIFO_CTRL_REG_FTH4 BIT_4
249 #define FIFO_CTRL_REG_FTH3 BIT_3
250 #define FIFO_CTRL_REG_FTH2 BIT_2
251 #define FIFO_CTRL_REG_FTH1 BIT_1
252 #define FIFO_CTRL_REG_FTH0 BIT_0
254 #define FIFO_SRC_REG 0x2F
255 #define FIFO_SRC_REG_WTM BIT_7
256 #define FIFO_SRC_REG_OVRN_INFO BIT_6
257 #define FIFO_SRC_REG_EMPTY BIT_5
258 #define FIFO_SRC_REG_FSS4 BIT_4
259 #define FIFO_SRC_REG_FSS3 BIT_3
260 #define FIFO_SRC_REG_FSS2 BIT_2
261 #define FIFO_SRC_REG_FSS1 BIT_1
262 #define FIFO_SRC_REG_FSS0 BIT_0
265 #define INT1_CFG 0x30
266 #define INT1_CFG_ANDOR BIT_7
267 #define INT1_CFG_INT_6D BIT_6
268 #define INT1_CFG_ZHIE BIT_5
269 #define INT1_CFG_ZLIE BIT_4
270 #define INT1_CFG_YHIE BIT_3
271 #define INT1_CFG_YLIE BIT_2
272 #define INT1_CFG_XHIE BIT_1
273 #define INT1_CFG_XLIE BIT_0
275 #define INT1_SRC 0x31
276 #define INT1_SRC_IA BIT_6
277 #define INT1_SRC_ZH BIT_5
278 #define INT1_SRC_ZL BIT_4
279 #define INT1_SRC_YH BIT_3
280 #define INT1_SRC_YL BIT_2
281 #define INT1_SRC_XH BIT_1
282 #define INT1_SRC_XL BIT_0
284 #define INT1_THS 0x32
285 #define INT1_THS_THS6 BIT_6
286 #define INT1_THS_THS5 BIT_5
287 #define INT1_THS_THS4 BIT_4
288 #define INT1_THS_THS3 BIT_3
289 #define INT1_THS_THS2 BIT_2
290 #define INT1_THS_THS1 BIT_1
291 #define INT1_THS_THS0 BIT_0
293 #define INT1_DURATION 0x33
294 #define INT1_DURATION_D6 BIT_6
295 #define INT1_DURATION_D5 BIT_5
296 #define INT1_DURATION_D4 BIT_4
297 #define INT1_DURATION_D3 BIT_3
298 #define INT1_DURATION_D2 BIT_2
299 #define INT1_DURATION_D1 BIT_1
300 #define INT1_DURATION_D0 BIT_0
303 #define INT2_CFG 0x34
304 #define INT2_CFG_ANDOR BIT_7
305 #define INT2_CFG_INT_6D BIT_6
306 #define INT2_CFG_ZHIE BIT_5
307 #define INT2_CFG_ZLIE BIT_4
308 #define INT2_CFG_YHIE BIT_3
309 #define INT2_CFG_YLIE BIT_2
310 #define INT2_CFG_XHIE BIT_1
311 #define INT2_CFG_XLIE BIT_0
313 #define INT2_SRC 0x35
314 #define INT2_SRC_IA BIT_6
315 #define INT2_SRC_ZH BIT_5
316 #define INT2_SRC_ZL BIT_4
317 #define INT2_SRC_YH BIT_3
318 #define INT2_SRC_YL BIT_2
319 #define INT2_SRC_XH BIT_1
320 #define INT2_SRC_XL BIT_0
322 #define INT2_THS 0x36
323 #define INT2_THS_THS6 BIT_6
324 #define INT2_THS_THS5 BIT_5
325 #define INT2_THS_THS4 BIT_4
326 #define INT2_THS_THS3 BIT_3
327 #define INT2_THS_THS2 BIT_2
328 #define INT2_THS_THS1 BIT_1
329 #define INT2_THS_THS0 BIT_0
331 #define INT2_DURATION 0x37
332 #define INT2_DURATION_D6 BIT_6
333 #define INT2_DURATION_D5 BIT_5
334 #define INT2_DURATION_D4 BIT_4
335 #define INT2_DURATION_D3 BIT_3
336 #define INT2_DURATION_D2 BIT_2
337 #define INT2_DURATION_D1 BIT_1
338 #define INT2_DURATION_D0 BIT_0
341 #define CLICK_CFG 0x38
342 #define CLICK_CFG_ZD BIT_5
343 #define CLICK_CFG_ZS BIT_4
344 #define CLICK_CFG_YD BIT_3
345 #define CLICK_CFG_YS BIT_2
346 #define CLICK_CFG_XD BIT_1
347 #define CLICK_CFG_XS BIT_0
349 #define CLICK_SRC 0x39
350 #define CLICK_SRC_IA BIT_6
351 #define CLICK_SRC_DCLICK BIT_5
352 #define CLICK_SRC_SCLICK BIT_4
353 #define CLICK_SRC_SIGN BIT_3
354 #define CLICK_SRC_Z BIT_2
355 #define CLICK_SRC_Y BIT_1
356 #define CLICK_SRC_X BIT_0
358 #define CLICK_THS 0x3A
359 #define CLICK_THS_LIR_CLICK BIT_7
360 #define CLICK_THS_THS6 BIT_6
361 #define CLICK_THS_THS5 BIT_5
362 #define CLICK_THS_THS4 BIT_4
363 #define CLICK_THS_THS3 BIT_3
364 #define CLICK_THS_THS2 BIT_2
365 #define CLICK_THS_THS1 BIT_1
366 #define CLICK_THS_THS0 BIT_0
368 #define TIME_LIMIT 0x3B
369 #define TIME_LATENCY 0x3C
370 #define TIME_WINDOW 0x3D