
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_start>:
#include <syscalls/z_errno_mrsh.c>

#else
int *z_impl_z_errno(void)
{
	return &_current->errno_var;
   0:	20000f00 	.word	0x20000f00
}
   4:	000016ed 	.word	0x000016ed
   8:	00005e09 	.word	0x00005e09
   c:	000016a5 	.word	0x000016a5
  10:	000016a5 	.word	0x000016a5
  14:	000016a5 	.word	0x000016a5
  18:	000016a5 	.word	0x000016a5
	...
  2c:	00001331 	.word	0x00001331
  30:	000016a5 	.word	0x000016a5
  34:	00000000 	.word	0x00000000
  38:	000012d9 	.word	0x000012d9
  3c:	00006bbf 	.word	0x00006bbf

00000040 <_irq_vector_table>:
  40:	0000141d 0000141d 0000141d 0000141d     ................
  50:	0000141d 0000141d 0000141d 0000141d     ................
  60:	0000141d 0000141d 0000141d 0000141d     ................
  70:	0000141d 0000141d 0000141d 0000141d     ................
  80:	0000141d 0000141d 0000141d 0000141d     ................
  90:	0000141d 0000141d 0000141d 0000141d     ................
  a0:	0000141d 0000141d 0000141d 0000141d     ................
  b0:	0000141d 0000141d 0000141d 0000141d     ................
  c0:	0000141d 0000141d 0000141d 0000141d     ................
  d0:	0000141d 0000141d 0000141d 0000141d     ................
  e0:	0000141d 0000141d 0000141d 0000141d     ................
  f0:	0000141d 0000141d 0000141d 0000141d     ................

Disassembly of section text:

00000100 <__aeabi_uldivmod>:
     100:	b953      	cbnz	r3, 118 <__aeabi_uldivmod+0x18>
     102:	b94a      	cbnz	r2, 118 <__aeabi_uldivmod+0x18>
     104:	2900      	cmp	r1, #0
     106:	bf08      	it	eq
     108:	2800      	cmpeq	r0, #0
     10a:	bf1c      	itt	ne
     10c:	f04f 31ff 	movne.w	r1, #4294967295
     110:	f04f 30ff 	movne.w	r0, #4294967295
     114:	f000 b96c 	b.w	3f0 <__aeabi_idiv0>
     118:	f1ad 0c08 	sub.w	ip, sp, #8
     11c:	e96d ce04 	strd	ip, lr, [sp, #-16]!
     120:	f000 f806 	bl	130 <__udivmoddi4>
     124:	f8dd e004 	ldr.w	lr, [sp, #4]
     128:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     12c:	b004      	add	sp, #16
     12e:	4770      	bx	lr

00000130 <__udivmoddi4>:
     130:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     134:	9e08      	ldr	r6, [sp, #32]
     136:	460d      	mov	r5, r1
     138:	4604      	mov	r4, r0
     13a:	468e      	mov	lr, r1
     13c:	2b00      	cmp	r3, #0
     13e:	f040 8082 	bne.w	246 <CONFIG_FLASH_SIZE+0x46>
     142:	428a      	cmp	r2, r1
     144:	4617      	mov	r7, r2
     146:	d946      	bls.n	1d6 <__data_size+0x36>
     148:	fab2 f282 	clz	r2, r2
     14c:	b14a      	cbz	r2, 162 <CONFIG_IDLE_STACK_SIZE+0x22>
     14e:	f1c2 0120 	rsb	r1, r2, #32
     152:	fa05 f302 	lsl.w	r3, r5, r2
     156:	fa20 f101 	lsr.w	r1, r0, r1
     15a:	4097      	lsls	r7, r2
     15c:	ea41 0e03 	orr.w	lr, r1, r3
     160:	4094      	lsls	r4, r2
     162:	ea4f 4817 	mov.w	r8, r7, lsr #16
     166:	0c23      	lsrs	r3, r4, #16
     168:	fbbe fcf8 	udiv	ip, lr, r8
     16c:	b2b9      	uxth	r1, r7
     16e:	fb08 ee1c 	mls	lr, r8, ip, lr
     172:	ea43 430e 	orr.w	r3, r3, lr, lsl #16
     176:	fb0c f001 	mul.w	r0, ip, r1
     17a:	4298      	cmp	r0, r3
     17c:	d90a      	bls.n	194 <CONFIG_IDLE_STACK_SIZE+0x54>
     17e:	18fb      	adds	r3, r7, r3
     180:	f10c 35ff 	add.w	r5, ip, #4294967295
     184:	f080 8116 	bcs.w	3b4 <CONFIG_FLASH_SIZE+0x1b4>
     188:	4298      	cmp	r0, r3
     18a:	f240 8113 	bls.w	3b4 <CONFIG_FLASH_SIZE+0x1b4>
     18e:	f1ac 0c02 	sub.w	ip, ip, #2
     192:	443b      	add	r3, r7
     194:	1a1b      	subs	r3, r3, r0
     196:	b2a4      	uxth	r4, r4
     198:	fbb3 f0f8 	udiv	r0, r3, r8
     19c:	fb08 3310 	mls	r3, r8, r0, r3
     1a0:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     1a4:	fb00 f101 	mul.w	r1, r0, r1
     1a8:	42a1      	cmp	r1, r4
     1aa:	d909      	bls.n	1c0 <__data_size+0x20>
     1ac:	193c      	adds	r4, r7, r4
     1ae:	f100 33ff 	add.w	r3, r0, #4294967295
     1b2:	f080 8101 	bcs.w	3b8 <CONFIG_FLASH_SIZE+0x1b8>
     1b6:	42a1      	cmp	r1, r4
     1b8:	f240 80fe 	bls.w	3b8 <CONFIG_FLASH_SIZE+0x1b8>
     1bc:	3802      	subs	r0, #2
     1be:	443c      	add	r4, r7
     1c0:	1a64      	subs	r4, r4, r1
     1c2:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     1c6:	2100      	movs	r1, #0
     1c8:	b11e      	cbz	r6, 1d2 <__data_size+0x32>
     1ca:	40d4      	lsrs	r4, r2
     1cc:	2300      	movs	r3, #0
     1ce:	e9c6 4300 	strd	r4, r3, [r6]
     1d2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     1d6:	b902      	cbnz	r2, 1da <__data_size+0x3a>
     1d8:	deff      	udf	#255	; 0xff
     1da:	fab2 f282 	clz	r2, r2
     1de:	2a00      	cmp	r2, #0
     1e0:	d14f      	bne.n	282 <CONFIG_FLASH_SIZE+0x82>
     1e2:	1bcb      	subs	r3, r1, r7
     1e4:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     1e8:	fa1f f887 	uxth.w	r8, r7
     1ec:	2101      	movs	r1, #1
     1ee:	fbb3 fcfe 	udiv	ip, r3, lr
     1f2:	0c25      	lsrs	r5, r4, #16
     1f4:	fb0e 331c 	mls	r3, lr, ip, r3
     1f8:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     1fc:	fb08 f30c 	mul.w	r3, r8, ip
     200:	42ab      	cmp	r3, r5
     202:	d907      	bls.n	214 <CONFIG_FLASH_SIZE+0x14>
     204:	197d      	adds	r5, r7, r5
     206:	f10c 30ff 	add.w	r0, ip, #4294967295
     20a:	d202      	bcs.n	212 <CONFIG_FLASH_SIZE+0x12>
     20c:	42ab      	cmp	r3, r5
     20e:	f200 80e7 	bhi.w	3e0 <CONFIG_FLASH_SIZE+0x1e0>
     212:	4684      	mov	ip, r0
     214:	1aed      	subs	r5, r5, r3
     216:	b2a3      	uxth	r3, r4
     218:	fbb5 f0fe 	udiv	r0, r5, lr
     21c:	fb0e 5510 	mls	r5, lr, r0, r5
     220:	ea43 4405 	orr.w	r4, r3, r5, lsl #16
     224:	fb08 f800 	mul.w	r8, r8, r0
     228:	45a0      	cmp	r8, r4
     22a:	d907      	bls.n	23c <CONFIG_FLASH_SIZE+0x3c>
     22c:	193c      	adds	r4, r7, r4
     22e:	f100 33ff 	add.w	r3, r0, #4294967295
     232:	d202      	bcs.n	23a <CONFIG_FLASH_SIZE+0x3a>
     234:	45a0      	cmp	r8, r4
     236:	f200 80d7 	bhi.w	3e8 <CONFIG_FLASH_SIZE+0x1e8>
     23a:	4618      	mov	r0, r3
     23c:	eba4 0408 	sub.w	r4, r4, r8
     240:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     244:	e7c0      	b.n	1c8 <__data_size+0x28>
     246:	428b      	cmp	r3, r1
     248:	d908      	bls.n	25c <CONFIG_FLASH_SIZE+0x5c>
     24a:	2e00      	cmp	r6, #0
     24c:	f000 80af 	beq.w	3ae <CONFIG_FLASH_SIZE+0x1ae>
     250:	2100      	movs	r1, #0
     252:	e9c6 0500 	strd	r0, r5, [r6]
     256:	4608      	mov	r0, r1
     258:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     25c:	fab3 f183 	clz	r1, r3
     260:	2900      	cmp	r1, #0
     262:	d14b      	bne.n	2fc <CONFIG_FLASH_SIZE+0xfc>
     264:	42ab      	cmp	r3, r5
     266:	d302      	bcc.n	26e <CONFIG_FLASH_SIZE+0x6e>
     268:	4282      	cmp	r2, r0
     26a:	f200 80b7 	bhi.w	3dc <CONFIG_FLASH_SIZE+0x1dc>
     26e:	1a84      	subs	r4, r0, r2
     270:	eb65 0303 	sbc.w	r3, r5, r3
     274:	2001      	movs	r0, #1
     276:	469e      	mov	lr, r3
     278:	2e00      	cmp	r6, #0
     27a:	d0aa      	beq.n	1d2 <__data_size+0x32>
     27c:	e9c6 4e00 	strd	r4, lr, [r6]
     280:	e7a7      	b.n	1d2 <__data_size+0x32>
     282:	f1c2 0c20 	rsb	ip, r2, #32
     286:	fa01 f302 	lsl.w	r3, r1, r2
     28a:	4097      	lsls	r7, r2
     28c:	fa20 f00c 	lsr.w	r0, r0, ip
     290:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     294:	fa21 fc0c 	lsr.w	ip, r1, ip
     298:	4318      	orrs	r0, r3
     29a:	fbbc f1fe 	udiv	r1, ip, lr
     29e:	0c05      	lsrs	r5, r0, #16
     2a0:	fb0e cc11 	mls	ip, lr, r1, ip
     2a4:	fa1f f887 	uxth.w	r8, r7
     2a8:	ea45 450c 	orr.w	r5, r5, ip, lsl #16
     2ac:	fb01 f308 	mul.w	r3, r1, r8
     2b0:	42ab      	cmp	r3, r5
     2b2:	fa04 f402 	lsl.w	r4, r4, r2
     2b6:	d909      	bls.n	2cc <CONFIG_FLASH_SIZE+0xcc>
     2b8:	197d      	adds	r5, r7, r5
     2ba:	f101 3cff 	add.w	ip, r1, #4294967295
     2be:	f080 808b 	bcs.w	3d8 <CONFIG_FLASH_SIZE+0x1d8>
     2c2:	42ab      	cmp	r3, r5
     2c4:	f240 8088 	bls.w	3d8 <CONFIG_FLASH_SIZE+0x1d8>
     2c8:	3902      	subs	r1, #2
     2ca:	443d      	add	r5, r7
     2cc:	1aeb      	subs	r3, r5, r3
     2ce:	b285      	uxth	r5, r0
     2d0:	fbb3 f0fe 	udiv	r0, r3, lr
     2d4:	fb0e 3310 	mls	r3, lr, r0, r3
     2d8:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     2dc:	fb00 f308 	mul.w	r3, r0, r8
     2e0:	42ab      	cmp	r3, r5
     2e2:	d907      	bls.n	2f4 <CONFIG_FLASH_SIZE+0xf4>
     2e4:	197d      	adds	r5, r7, r5
     2e6:	f100 3cff 	add.w	ip, r0, #4294967295
     2ea:	d271      	bcs.n	3d0 <CONFIG_FLASH_SIZE+0x1d0>
     2ec:	42ab      	cmp	r3, r5
     2ee:	d96f      	bls.n	3d0 <CONFIG_FLASH_SIZE+0x1d0>
     2f0:	3802      	subs	r0, #2
     2f2:	443d      	add	r5, r7
     2f4:	1aeb      	subs	r3, r5, r3
     2f6:	ea40 4101 	orr.w	r1, r0, r1, lsl #16
     2fa:	e778      	b.n	1ee <__data_size+0x4e>
     2fc:	f1c1 0c20 	rsb	ip, r1, #32
     300:	408b      	lsls	r3, r1
     302:	fa22 f70c 	lsr.w	r7, r2, ip
     306:	431f      	orrs	r7, r3
     308:	fa20 f40c 	lsr.w	r4, r0, ip
     30c:	fa05 f301 	lsl.w	r3, r5, r1
     310:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     314:	fa25 f50c 	lsr.w	r5, r5, ip
     318:	431c      	orrs	r4, r3
     31a:	0c23      	lsrs	r3, r4, #16
     31c:	fbb5 f9fe 	udiv	r9, r5, lr
     320:	fa1f f887 	uxth.w	r8, r7
     324:	fb0e 5519 	mls	r5, lr, r9, r5
     328:	ea43 4505 	orr.w	r5, r3, r5, lsl #16
     32c:	fb09 fa08 	mul.w	sl, r9, r8
     330:	45aa      	cmp	sl, r5
     332:	fa02 f201 	lsl.w	r2, r2, r1
     336:	fa00 f301 	lsl.w	r3, r0, r1
     33a:	d908      	bls.n	34e <CONFIG_FLASH_SIZE+0x14e>
     33c:	197d      	adds	r5, r7, r5
     33e:	f109 30ff 	add.w	r0, r9, #4294967295
     342:	d247      	bcs.n	3d4 <CONFIG_FLASH_SIZE+0x1d4>
     344:	45aa      	cmp	sl, r5
     346:	d945      	bls.n	3d4 <CONFIG_FLASH_SIZE+0x1d4>
     348:	f1a9 0902 	sub.w	r9, r9, #2
     34c:	443d      	add	r5, r7
     34e:	eba5 050a 	sub.w	r5, r5, sl
     352:	b2a4      	uxth	r4, r4
     354:	fbb5 f0fe 	udiv	r0, r5, lr
     358:	fb0e 5510 	mls	r5, lr, r0, r5
     35c:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
     360:	fb00 f808 	mul.w	r8, r0, r8
     364:	45a0      	cmp	r8, r4
     366:	d907      	bls.n	378 <CONFIG_FLASH_SIZE+0x178>
     368:	193c      	adds	r4, r7, r4
     36a:	f100 35ff 	add.w	r5, r0, #4294967295
     36e:	d22d      	bcs.n	3cc <CONFIG_FLASH_SIZE+0x1cc>
     370:	45a0      	cmp	r8, r4
     372:	d92b      	bls.n	3cc <CONFIG_FLASH_SIZE+0x1cc>
     374:	3802      	subs	r0, #2
     376:	443c      	add	r4, r7
     378:	ea40 4009 	orr.w	r0, r0, r9, lsl #16
     37c:	eba4 0408 	sub.w	r4, r4, r8
     380:	fba0 8902 	umull	r8, r9, r0, r2
     384:	454c      	cmp	r4, r9
     386:	46c6      	mov	lr, r8
     388:	464d      	mov	r5, r9
     38a:	d319      	bcc.n	3c0 <CONFIG_FLASH_SIZE+0x1c0>
     38c:	d016      	beq.n	3bc <CONFIG_FLASH_SIZE+0x1bc>
     38e:	b15e      	cbz	r6, 3a8 <CONFIG_FLASH_SIZE+0x1a8>
     390:	ebb3 020e 	subs.w	r2, r3, lr
     394:	eb64 0405 	sbc.w	r4, r4, r5
     398:	fa04 fc0c 	lsl.w	ip, r4, ip
     39c:	40ca      	lsrs	r2, r1
     39e:	ea4c 0202 	orr.w	r2, ip, r2
     3a2:	40cc      	lsrs	r4, r1
     3a4:	e9c6 2400 	strd	r2, r4, [r6]
     3a8:	2100      	movs	r1, #0
     3aa:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     3ae:	4631      	mov	r1, r6
     3b0:	4630      	mov	r0, r6
     3b2:	e70e      	b.n	1d2 <__data_size+0x32>
     3b4:	46ac      	mov	ip, r5
     3b6:	e6ed      	b.n	194 <CONFIG_IDLE_STACK_SIZE+0x54>
     3b8:	4618      	mov	r0, r3
     3ba:	e701      	b.n	1c0 <__data_size+0x20>
     3bc:	4543      	cmp	r3, r8
     3be:	d2e6      	bcs.n	38e <CONFIG_FLASH_SIZE+0x18e>
     3c0:	ebb8 0e02 	subs.w	lr, r8, r2
     3c4:	eb69 0507 	sbc.w	r5, r9, r7
     3c8:	3801      	subs	r0, #1
     3ca:	e7e0      	b.n	38e <CONFIG_FLASH_SIZE+0x18e>
     3cc:	4628      	mov	r0, r5
     3ce:	e7d3      	b.n	378 <CONFIG_FLASH_SIZE+0x178>
     3d0:	4660      	mov	r0, ip
     3d2:	e78f      	b.n	2f4 <CONFIG_FLASH_SIZE+0xf4>
     3d4:	4681      	mov	r9, r0
     3d6:	e7ba      	b.n	34e <CONFIG_FLASH_SIZE+0x14e>
     3d8:	4661      	mov	r1, ip
     3da:	e777      	b.n	2cc <CONFIG_FLASH_SIZE+0xcc>
     3dc:	4608      	mov	r0, r1
     3de:	e74b      	b.n	278 <CONFIG_FLASH_SIZE+0x78>
     3e0:	f1ac 0c02 	sub.w	ip, ip, #2
     3e4:	443d      	add	r5, r7
     3e6:	e715      	b.n	214 <CONFIG_FLASH_SIZE+0x14>
     3e8:	3802      	subs	r0, #2
     3ea:	443c      	add	r4, r7
     3ec:	e726      	b.n	23c <CONFIG_FLASH_SIZE+0x3c>
     3ee:	bf00      	nop

000003f0 <__aeabi_idiv0>:
     3f0:	4770      	bx	lr
     3f2:	bf00      	nop

000003f4 <main>:

#define STACKSIZE 1024
#define PRIORITY 99

void main(void)
{
     3f4:	b5f0      	push	{r4, r5, r6, r7, lr}
     3f6:	b09b      	sub	sp, #108	; 0x6c
	struct k_poll_signal async_sig = K_POLL_SIGNAL_INITIALIZER(async_sig);
     3f8:	ae16      	add	r6, sp, #88	; 0x58
     3fa:	9616      	str	r6, [sp, #88]	; 0x58
     3fc:	9617      	str	r6, [sp, #92]	; 0x5c
     3fe:	2400      	movs	r4, #0
     400:	9418      	str	r4, [sp, #96]	; 0x60
     402:	9419      	str	r4, [sp, #100]	; 0x64
	uint8_t data = 40, val =0, sz = 9;
     404:	2328      	movs	r3, #40	; 0x28
     406:	f88d 3057 	strb.w	r3, [sp, #87]	; 0x57
     40a:	f88d 4056 	strb.w	r4, [sp, #86]	; 0x56
	    struct spi_buf bufs = {
     40e:	f10d 0357 	add.w	r3, sp, #87	; 0x57
     412:	9313      	str	r3, [sp, #76]	; 0x4c
     414:	2701      	movs	r7, #1
     416:	9714      	str	r7, [sp, #80]	; 0x50
            .buf = &data,
            .len = sizeof(data)
    };
    struct spi_buf_set tx = {
     418:	ab13      	add	r3, sp, #76	; 0x4c
     41a:	9311      	str	r3, [sp, #68]	; 0x44
        .buffers = &bufs
    };

    tx.count = 1;
     41c:	9712      	str	r7, [sp, #72]	; 0x48

	struct spi_buf rbufs = {
     41e:	f10d 0356 	add.w	r3, sp, #86	; 0x56
     422:	930f      	str	r3, [sp, #60]	; 0x3c
     424:	9710      	str	r7, [sp, #64]	; 0x40
            .buf = &val,
            .len = sizeof(val)
    };
    struct spi_buf_set rx = {
     426:	940e      	str	r4, [sp, #56]	; 0x38
     428:	ab0f      	add	r3, sp, #60	; 0x3c
     42a:	930d      	str	r3, [sp, #52]	; 0x34
		/* coverity[OVERRUN] */
		return (const struct device *) arch_syscall_invoke1(*(uintptr_t *)&name, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
     42c:	481c      	ldr	r0, [pc, #112]	; (4a0 <CONFIG_MAIN_STACK_SIZE+0xa0>)
     42e:	f003 fe69 	bl	4104 <z_impl_device_get_binding>
        .buffers = &rbufs
    };
	struct spi_config spi_cfg;
	struct spi_cs_control cs_ctrl;

	cs_ctrl.gpio_dev = device_get_binding("GPIO_0");
     432:	9007      	str	r0, [sp, #28]
    cs_ctrl.gpio_pin = 11;
     434:	230b      	movs	r3, #11
     436:	f88d 3024 	strb.w	r3, [sp, #36]	; 0x24
    cs_ctrl.delay = 0;
     43a:	9408      	str	r4, [sp, #32]

	spi_cfg.operation = SPI_WORD_SET(8) | SPI_OP_MODE_MASTER | SPI_LINES_SINGLE; 
     43c:	f44f 7380 	mov.w	r3, #256	; 0x100
     440:	f8ad 302c 	strh.w	r3, [sp, #44]	; 0x2c
    spi_cfg.frequency = 1000000;
     444:	4b17      	ldr	r3, [pc, #92]	; (4a4 <CONFIG_MAIN_STACK_SIZE+0xa4>)
     446:	930a      	str	r3, [sp, #40]	; 0x28
	spi_cfg.cs = &cs_ctrl;
     448:	ab07      	add	r3, sp, #28
     44a:	930c      	str	r3, [sp, #48]	; 0x30
     44c:	4816      	ldr	r0, [pc, #88]	; (4a8 <CONFIG_MAIN_STACK_SIZE+0xa8>)
     44e:	f003 fe59 	bl	4104 <z_impl_device_get_binding>
     452:	4605      	mov	r5, r0

	const struct device * sp;
	sp = device_get_binding("SPI_0");

			data++;
     454:	f89d 1057 	ldrb.w	r1, [sp, #87]	; 0x57
     458:	4439      	add	r1, r7
     45a:	b2c9      	uxtb	r1, r1
     45c:	f88d 1057 	strb.w	r1, [sp, #87]	; 0x57
			struct k_poll_event  async_evt =
     460:	9402      	str	r4, [sp, #8]
     462:	9403      	str	r4, [sp, #12]
     464:	9404      	str	r4, [sp, #16]
     466:	9405      	str	r4, [sp, #20]
     468:	f88d 7015 	strb.w	r7, [sp, #21]
     46c:	9606      	str	r6, [sp, #24]
		K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_SIGNAL,
					 K_POLL_MODE_NOTIFY_ONLY,
					 &async_sig);

			printk("transmitted data: %u \n", data);
     46e:	480f      	ldr	r0, [pc, #60]	; (4ac <CONFIG_MAIN_STACK_SIZE+0xac>)
     470:	f005 faa4 	bl	59bc <printk>
				       const struct spi_config *config,
				       const struct spi_buf_set *tx_bufs,
				       const struct spi_buf_set *rx_bufs,
				       struct k_poll_signal *async)
{
	const struct spi_driver_api *api =
     474:	68ab      	ldr	r3, [r5, #8]
		(const struct spi_driver_api *)dev->api;

	return api->transceive_async(dev, config, tx_bufs, rx_bufs, async);
     476:	685c      	ldr	r4, [r3, #4]
     478:	9600      	str	r6, [sp, #0]
     47a:	ab0d      	add	r3, sp, #52	; 0x34
     47c:	aa11      	add	r2, sp, #68	; 0x44
     47e:	a90a      	add	r1, sp, #40	; 0x28
     480:	4628      	mov	r0, r5
     482:	47a0      	blx	r4
		/* coverity[OVERRUN] */
		return (int) arch_syscall_invoke4(*(uintptr_t *)&events, *(uintptr_t *)&num_events, parm0.split.lo, parm0.split.hi, K_SYSCALL_K_POLL);
	}
#endif
	compiler_barrier();
	return z_impl_k_poll(events, num_events, timeout);
     484:	f44f 4200 	mov.w	r2, #32768	; 0x8000
     488:	2300      	movs	r3, #0
     48a:	210a      	movs	r1, #10
     48c:	a802      	add	r0, sp, #8
     48e:	f004 fdf1 	bl	5074 <z_impl_k_poll>
			int error = spi_transceive_async(sp,&spi_cfg,&tx, &rx,&async_sig);
			int ret = k_poll(&async_evt, 10, K_MSEC(1000));
			printk("received data: %u \n", val);
     492:	f89d 1056 	ldrb.w	r1, [sp, #86]	; 0x56
     496:	4806      	ldr	r0, [pc, #24]	; (4b0 <CONFIG_MAIN_STACK_SIZE+0xb0>)
     498:	f005 fa90 	bl	59bc <printk>
     49c:	b01b      	add	sp, #108	; 0x6c
     49e:	bdf0      	pop	{r4, r5, r6, r7, pc}
     4a0:	00007758 	.word	0x00007758
     4a4:	000f4240 	.word	0x000f4240
     4a8:	00007760 	.word	0x00007760
     4ac:	00007768 	.word	0x00007768
     4b0:	00007780 	.word	0x00007780

000004b4 <char_out>:
struct out_context {
	int count;
};

static int char_out(int c, void *ctx_p)
{
     4b4:	b508      	push	{r3, lr}
	struct out_context *ctx = ctx_p;

	ctx->count++;
     4b6:	680b      	ldr	r3, [r1, #0]
     4b8:	3301      	adds	r3, #1
     4ba:	600b      	str	r3, [r1, #0]
	return _char_out(c);
     4bc:	4b01      	ldr	r3, [pc, #4]	; (4c4 <char_out+0x10>)
     4be:	681b      	ldr	r3, [r3, #0]
     4c0:	4798      	blx	r3
}
     4c2:	bd08      	pop	{r3, pc}
     4c4:	20000000 	.word	0x20000000

000004c8 <__printk_hook_install>:
	_char_out = fn;
     4c8:	4b01      	ldr	r3, [pc, #4]	; (4d0 <__printk_hook_install+0x8>)
     4ca:	6018      	str	r0, [r3, #0]
}
     4cc:	4770      	bx	lr
     4ce:	bf00      	nop
     4d0:	20000000 	.word	0x20000000

000004d4 <vprintk>:
#endif
	}
}
#else
void vprintk(const char *fmt, va_list ap)
{
     4d4:	b500      	push	{lr}
     4d6:	b083      	sub	sp, #12
     4d8:	4602      	mov	r2, r0
     4da:	460b      	mov	r3, r1
	struct out_context ctx = { 0 };
     4dc:	2100      	movs	r1, #0
     4de:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
	k_spinlock_key_t key = k_spin_lock(&lock);
#endif

	cbvprintf(char_out, &ctx, fmt, ap);
     4e0:	a901      	add	r1, sp, #4
     4e2:	4803      	ldr	r0, [pc, #12]	; (4f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x8>)
     4e4:	f000 f8c8 	bl	678 <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
	k_spin_unlock(&lock, key);
#endif
}
     4e8:	b003      	add	sp, #12
     4ea:	f85d fb04 	ldr.w	pc, [sp], #4
     4ee:	bf00      	nop
     4f0:	000004b5 	.word	0x000004b5

000004f4 <vsnprintk>:

	return ret;
}

int vsnprintk(char *str, size_t size, const char *fmt, va_list ap)
{
     4f4:	b510      	push	{r4, lr}
     4f6:	b084      	sub	sp, #16
     4f8:	4604      	mov	r4, r0
	struct str_context ctx = { str, size, 0 };
     4fa:	9001      	str	r0, [sp, #4]
     4fc:	9102      	str	r1, [sp, #8]
     4fe:	2100      	movs	r1, #0
     500:	9103      	str	r1, [sp, #12]

	cbvprintf(str_out, &ctx, fmt, ap);
     502:	a901      	add	r1, sp, #4
     504:	4805      	ldr	r0, [pc, #20]	; (51c <vsnprintk+0x28>)
     506:	f000 f8b7 	bl	678 <cbvprintf>

	if (ctx.count < ctx.max) {
     50a:	9b03      	ldr	r3, [sp, #12]
     50c:	9a02      	ldr	r2, [sp, #8]
     50e:	4293      	cmp	r3, r2
     510:	da01      	bge.n	516 <vsnprintk+0x22>
		str[ctx.count] = '\0';
     512:	2200      	movs	r2, #0
     514:	54e2      	strb	r2, [r4, r3]
	}

	return ctx.count;
}
     516:	9803      	ldr	r0, [sp, #12]
     518:	b004      	add	sp, #16
     51a:	bd10      	pop	{r4, pc}
     51c:	0000598d 	.word	0x0000598d

00000520 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     520:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
     524:	b083      	sub	sp, #12
     526:	4604      	mov	r4, r0
     528:	4608      	mov	r0, r1
     52a:	4615      	mov	r5, r2
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     52c:	8b23      	ldrh	r3, [r4, #24]
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     52e:	f013 0f08 	tst.w	r3, #8
     532:	d105      	bne.n	540 <process_event+0x20>
     534:	f003 0607 	and.w	r6, r3, #7
 *
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
     538:	2300      	movs	r3, #0
     53a:	9300      	str	r3, [sp, #0]
	list->tail = NULL;
     53c:	9301      	str	r3, [sp, #4]
}
     53e:	e069      	b.n	614 <process_event+0xf4>
		if (evt == EVT_COMPLETE) {
     540:	2901      	cmp	r1, #1
     542:	d009      	beq.n	558 <process_event+0x38>
			mgr->flags |= ONOFF_FLAG_COMPLETE;
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
     544:	f043 0320 	orr.w	r3, r3, #32
     548:	8323      	strh	r3, [r4, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     54a:	f385 8811 	msr	BASEPRI, r5
     54e:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     552:	b003      	add	sp, #12
     554:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     558:	f043 0310 	orr.w	r3, r3, #16
     55c:	8323      	strh	r3, [r4, #24]
     55e:	e7f4      	b.n	54a <process_event+0x2a>
			evt = process_recheck(mgr);
     560:	4620      	mov	r0, r4
     562:	f005 fa6e 	bl	5a42 <process_recheck>
     566:	e057      	b.n	618 <process_event+0xf8>
			res = mgr->last_res;
     568:	f8d4 9014 	ldr.w	r9, [r4, #20]
			process_complete(mgr, &clients, res);
     56c:	464a      	mov	r2, r9
     56e:	4669      	mov	r1, sp
     570:	4620      	mov	r0, r4
     572:	f005 fa7f 	bl	5a74 <process_complete>
		onoff_transition_fn transit = NULL;
     576:	2700      	movs	r7, #0
     578:	e05a      	b.n	630 <process_event+0x110>
			transit = mgr->transitions->start;
     57a:	6923      	ldr	r3, [r4, #16]
     57c:	681f      	ldr	r7, [r3, #0]
			set_state(mgr, ONOFF_STATE_TO_ON);
     57e:	2106      	movs	r1, #6
     580:	4620      	mov	r0, r4
     582:	f005 fa37 	bl	59f4 <set_state>
		res = 0;
     586:	f04f 0900 	mov.w	r9, #0
     58a:	e051      	b.n	630 <process_event+0x110>
			transit = mgr->transitions->stop;
     58c:	6923      	ldr	r3, [r4, #16]
     58e:	685f      	ldr	r7, [r3, #4]
			set_state(mgr, ONOFF_STATE_TO_OFF);
     590:	2104      	movs	r1, #4
     592:	4620      	mov	r0, r4
     594:	f005 fa2e 	bl	59f4 <set_state>
		res = 0;
     598:	f04f 0900 	mov.w	r9, #0
     59c:	e048      	b.n	630 <process_event+0x110>
			transit = mgr->transitions->reset;
     59e:	6923      	ldr	r3, [r4, #16]
     5a0:	689f      	ldr	r7, [r3, #8]
			set_state(mgr, ONOFF_STATE_RESETTING);
     5a2:	2105      	movs	r1, #5
     5a4:	4620      	mov	r0, r4
     5a6:	f005 fa25 	bl	59f4 <set_state>
		res = 0;
     5aa:	f04f 0900 	mov.w	r9, #0
     5ae:	e03f      	b.n	630 <process_event+0x110>
				   && !sys_slist_is_empty(&mgr->monitors);
     5b0:	2200      	movs	r2, #0
     5b2:	e046      	b.n	642 <process_event+0x122>
     5b4:	2200      	movs	r2, #0
     5b6:	e044      	b.n	642 <process_event+0x122>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     5b8:	f043 0308 	orr.w	r3, r3, #8
			mgr->flags = flags;
     5bc:	8323      	strh	r3, [r4, #24]
     5be:	f385 8811 	msr	BASEPRI, r5
     5c2:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
     5c6:	2900      	cmp	r1, #0
     5c8:	d144      	bne.n	654 <process_event+0x134>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     5ca:	9b00      	ldr	r3, [sp, #0]
			if (!sys_slist_is_empty(&clients)) {
     5cc:	b12b      	cbz	r3, 5da <process_event+0xba>
				notify_all(mgr, &clients, state, res);
     5ce:	464b      	mov	r3, r9
     5d0:	4642      	mov	r2, r8
     5d2:	4669      	mov	r1, sp
     5d4:	4620      	mov	r0, r4
     5d6:	f005 fac3 	bl	5b60 <notify_all>
			if (transit != NULL) {
     5da:	b117      	cbz	r7, 5e2 <process_event+0xc2>
				transit(mgr, transition_complete);
     5dc:	4925      	ldr	r1, [pc, #148]	; (674 <process_event+0x154>)
     5de:	4620      	mov	r0, r4
     5e0:	47b8      	blx	r7
	__asm__ volatile(
     5e2:	f04f 0320 	mov.w	r3, #32
     5e6:	f3ef 8511 	mrs	r5, BASEPRI
     5ea:	f383 8812 	msr	BASEPRI_MAX, r3
     5ee:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     5f2:	8b23      	ldrh	r3, [r4, #24]
     5f4:	f023 0308 	bic.w	r3, r3, #8
     5f8:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     5fa:	8b23      	ldrh	r3, [r4, #24]
     5fc:	f013 0f10 	tst.w	r3, #16
     600:	d02e      	beq.n	660 <process_event+0x140>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     602:	f023 0310 	bic.w	r3, r3, #16
     606:	8323      	strh	r3, [r4, #24]
			evt = EVT_COMPLETE;
     608:	2001      	movs	r0, #1
		state = mgr->flags & ONOFF_STATE_MASK;
     60a:	8b26      	ldrh	r6, [r4, #24]
     60c:	f006 0607 	and.w	r6, r6, #7
	} while (evt != EVT_NOP);
     610:	2800      	cmp	r0, #0
     612:	d09a      	beq.n	54a <process_event+0x2a>
		if (evt == EVT_RECHECK) {
     614:	2802      	cmp	r0, #2
     616:	d0a3      	beq.n	560 <process_event+0x40>
		if (evt == EVT_NOP) {
     618:	2800      	cmp	r0, #0
     61a:	d096      	beq.n	54a <process_event+0x2a>
		if (evt == EVT_COMPLETE) {
     61c:	2801      	cmp	r0, #1
     61e:	d0a3      	beq.n	568 <process_event+0x48>
		} else if (evt == EVT_START) {
     620:	2803      	cmp	r0, #3
     622:	d0aa      	beq.n	57a <process_event+0x5a>
		} else if (evt == EVT_STOP) {
     624:	2804      	cmp	r0, #4
     626:	d0b1      	beq.n	58c <process_event+0x6c>
		} else if (evt == EVT_RESET) {
     628:	2805      	cmp	r0, #5
     62a:	d0b8      	beq.n	59e <process_event+0x7e>
		onoff_transition_fn transit = NULL;
     62c:	2700      	movs	r7, #0
		res = 0;
     62e:	46b9      	mov	r9, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     630:	8b23      	ldrh	r3, [r4, #24]
     632:	f003 0807 	and.w	r8, r3, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     636:	45b0      	cmp	r8, r6
     638:	d0ba      	beq.n	5b0 <process_event+0x90>
     63a:	68a2      	ldr	r2, [r4, #8]
     63c:	2a00      	cmp	r2, #0
     63e:	d0b9      	beq.n	5b4 <process_event+0x94>
     640:	2201      	movs	r2, #1
		if (do_monitors
     642:	4611      	mov	r1, r2
     644:	2a00      	cmp	r2, #0
     646:	d1b7      	bne.n	5b8 <process_event+0x98>
     648:	9a00      	ldr	r2, [sp, #0]
		    || !sys_slist_is_empty(&clients)
     64a:	2a00      	cmp	r2, #0
     64c:	d1b4      	bne.n	5b8 <process_event+0x98>
		    || (transit != NULL)) {
     64e:	2f00      	cmp	r7, #0
     650:	d1b2      	bne.n	5b8 <process_event+0x98>
     652:	e7d2      	b.n	5fa <process_event+0xda>
				notify_monitors(mgr, state, res);
     654:	464a      	mov	r2, r9
     656:	4641      	mov	r1, r8
     658:	4620      	mov	r0, r4
     65a:	f005 f9d3 	bl	5a04 <notify_monitors>
     65e:	e7b4      	b.n	5ca <process_event+0xaa>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     660:	f013 0f20 	tst.w	r3, #32
     664:	d004      	beq.n	670 <process_event+0x150>
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     666:	f023 0320 	bic.w	r3, r3, #32
     66a:	8323      	strh	r3, [r4, #24]
			evt = EVT_RECHECK;
     66c:	2002      	movs	r0, #2
     66e:	e7cc      	b.n	60a <process_event+0xea>
		evt = EVT_NOP;
     670:	2000      	movs	r0, #0
     672:	e7ca      	b.n	60a <process_event+0xea>
     674:	00005b8f 	.word	0x00005b8f

00000678 <cbvprintf>:

	return (int)count;
}

int cbvprintf(cbprintf_cb out, void *ctx, const char *fp, va_list ap)
{
     678:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     67c:	b093      	sub	sp, #76	; 0x4c
     67e:	4606      	mov	r6, r0
     680:	460d      	mov	r5, r1
     682:	4692      	mov	sl, r2
     684:	9303      	str	r3, [sp, #12]
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
     686:	2400      	movs	r4, #0
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
     688:	f89a 0000 	ldrb.w	r0, [sl]
     68c:	2800      	cmp	r0, #0
     68e:	f000 84d6 	beq.w	103e <CONFIG_FPROTECT_BLOCK_SIZE+0x3e>
		if (*fp != '%') {
     692:	2825      	cmp	r0, #37	; 0x25
     694:	d008      	beq.n	6a8 <cbvprintf+0x30>
			OUTC(*fp++);
     696:	f10a 0a01 	add.w	sl, sl, #1
     69a:	4629      	mov	r1, r5
     69c:	47b0      	blx	r6
     69e:	2800      	cmp	r0, #0
     6a0:	f2c0 84ce 	blt.w	1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>
     6a4:	3401      	adds	r4, #1
			continue;
     6a6:	e7ef      	b.n	688 <cbvprintf+0x10>
		 * mitigate LLVM code generation bug.
		 */
		struct {
			union argument_value value;
			struct conversion conv;
		} state = {
     6a8:	2300      	movs	r3, #0
     6aa:	9306      	str	r3, [sp, #24]
     6ac:	9307      	str	r3, [sp, #28]
     6ae:	930b      	str	r3, [sp, #44]	; 0x2c
	*conv = (struct conversion) {
     6b0:	9308      	str	r3, [sp, #32]
     6b2:	9309      	str	r3, [sp, #36]	; 0x24
     6b4:	930a      	str	r3, [sp, #40]	; 0x28
	++sp;
     6b6:	f10a 0801 	add.w	r8, sl, #1
	if (*sp == '%') {
     6ba:	f89a 3001 	ldrb.w	r3, [sl, #1]
     6be:	2b25      	cmp	r3, #37	; 0x25
     6c0:	d001      	beq.n	6c6 <cbvprintf+0x4e>
	bool loop = true;
     6c2:	2701      	movs	r7, #1
     6c4:	e02c      	b.n	720 <cbvprintf+0xa8>
		conv->specifier = *sp++;
     6c6:	f10a 0802 	add.w	r8, sl, #2
     6ca:	f88d 3023 	strb.w	r3, [sp, #35]	; 0x23
		return sp;
     6ce:	e1a8      	b.n	a22 <CONFIG_ISR_STACK_SIZE+0x222>
			conv->flag_dash = true;
     6d0:	f89d 3020 	ldrb.w	r3, [sp, #32]
     6d4:	f043 0304 	orr.w	r3, r3, #4
     6d8:	f88d 3020 	strb.w	r3, [sp, #32]
		if (loop) {
     6dc:	b1ff      	cbz	r7, 71e <cbvprintf+0xa6>
			++sp;
     6de:	f108 0801 	add.w	r8, r8, #1
     6e2:	e01c      	b.n	71e <cbvprintf+0xa6>
			conv->flag_plus = true;
     6e4:	f89d 3020 	ldrb.w	r3, [sp, #32]
     6e8:	f043 0308 	orr.w	r3, r3, #8
     6ec:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     6f0:	e7f4      	b.n	6dc <cbvprintf+0x64>
			conv->flag_space = true;
     6f2:	f89d 3020 	ldrb.w	r3, [sp, #32]
     6f6:	f043 0310 	orr.w	r3, r3, #16
     6fa:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     6fe:	e7ed      	b.n	6dc <cbvprintf+0x64>
			conv->flag_hash = true;
     700:	f89d 3020 	ldrb.w	r3, [sp, #32]
     704:	f043 0320 	orr.w	r3, r3, #32
     708:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     70c:	e7e6      	b.n	6dc <cbvprintf+0x64>
			conv->flag_zero = true;
     70e:	f89d 3020 	ldrb.w	r3, [sp, #32]
     712:	f043 0340 	orr.w	r3, r3, #64	; 0x40
     716:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     71a:	e7df      	b.n	6dc <cbvprintf+0x64>
		switch (*sp) {
     71c:	2700      	movs	r7, #0
	} while (loop);
     71e:	b34f      	cbz	r7, 774 <cbvprintf+0xfc>
		switch (*sp) {
     720:	f898 3000 	ldrb.w	r3, [r8]
     724:	3b20      	subs	r3, #32
     726:	2b10      	cmp	r3, #16
     728:	d8f8      	bhi.n	71c <cbvprintf+0xa4>
     72a:	a201      	add	r2, pc, #4	; (adr r2, 730 <cbvprintf+0xb8>)
     72c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
     730:	000006f3 	.word	0x000006f3
     734:	0000071d 	.word	0x0000071d
     738:	0000071d 	.word	0x0000071d
     73c:	00000701 	.word	0x00000701
     740:	0000071d 	.word	0x0000071d
     744:	0000071d 	.word	0x0000071d
     748:	0000071d 	.word	0x0000071d
     74c:	0000071d 	.word	0x0000071d
     750:	0000071d 	.word	0x0000071d
     754:	0000071d 	.word	0x0000071d
     758:	0000071d 	.word	0x0000071d
     75c:	000006e5 	.word	0x000006e5
     760:	0000071d 	.word	0x0000071d
     764:	000006d1 	.word	0x000006d1
     768:	0000071d 	.word	0x0000071d
     76c:	0000071d 	.word	0x0000071d
     770:	0000070f 	.word	0x0000070f
	if (conv->flag_zero && conv->flag_dash) {
     774:	f89d 3020 	ldrb.w	r3, [sp, #32]
     778:	f003 0344 	and.w	r3, r3, #68	; 0x44
     77c:	2b44      	cmp	r3, #68	; 0x44
     77e:	d06d      	beq.n	85c <CONFIG_ISR_STACK_SIZE+0x5c>
	sp = extract_width(conv, sp);
     780:	f8cd 8014 	str.w	r8, [sp, #20]
	conv->width_present = true;
     784:	f89d 3020 	ldrb.w	r3, [sp, #32]
     788:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     78c:	f88d 3020 	strb.w	r3, [sp, #32]
	if (*sp == '*') {
     790:	f898 3000 	ldrb.w	r3, [r8]
     794:	2b2a      	cmp	r3, #42	; 0x2a
     796:	d068      	beq.n	86a <CONFIG_ISR_STACK_SIZE+0x6a>
	size_t width = extract_decimal(&sp);
     798:	a805      	add	r0, sp, #20
     79a:	f005 fa88 	bl	5cae <extract_decimal>
	if (sp != wp) {
     79e:	9b05      	ldr	r3, [sp, #20]
     7a0:	4598      	cmp	r8, r3
     7a2:	d012      	beq.n	7ca <cbvprintf+0x152>
		conv->width_present = true;
     7a4:	f89d 3020 	ldrb.w	r3, [sp, #32]
     7a8:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     7ac:	f88d 3020 	strb.w	r3, [sp, #32]
		conv->width_value = width;
     7b0:	9009      	str	r0, [sp, #36]	; 0x24
		conv->unsupported |= ((conv->width_value < 0)
     7b2:	f3c3 0340 	ubfx	r3, r3, #1, #1
				      || (width != (size_t)conv->width_value));
     7b6:	2800      	cmp	r0, #0
     7b8:	db60      	blt.n	87c <CONFIG_ISR_STACK_SIZE+0x7c>
     7ba:	2200      	movs	r2, #0
		conv->unsupported |= ((conv->width_value < 0)
     7bc:	4313      	orrs	r3, r2
     7be:	f89d 2020 	ldrb.w	r2, [sp, #32]
     7c2:	f363 0241 	bfi	r2, r3, #1, #1
     7c6:	f88d 2020 	strb.w	r2, [sp, #32]
	return sp;
     7ca:	9b05      	ldr	r3, [sp, #20]
	sp = extract_prec(conv, sp);
     7cc:	9305      	str	r3, [sp, #20]
	conv->prec_present = (*sp == '.');
     7ce:	781b      	ldrb	r3, [r3, #0]
     7d0:	2b2e      	cmp	r3, #46	; 0x2e
     7d2:	bf14      	ite	ne
     7d4:	2300      	movne	r3, #0
     7d6:	2301      	moveq	r3, #1
     7d8:	f89d 2021 	ldrb.w	r2, [sp, #33]	; 0x21
     7dc:	f363 0241 	bfi	r2, r3, #1, #1
     7e0:	f88d 2021 	strb.w	r2, [sp, #33]	; 0x21
	if (!conv->prec_present) {
     7e4:	2b00      	cmp	r3, #0
     7e6:	d04b      	beq.n	880 <CONFIG_ISR_STACK_SIZE+0x80>
	++sp;
     7e8:	9b05      	ldr	r3, [sp, #20]
     7ea:	1c5a      	adds	r2, r3, #1
     7ec:	9205      	str	r2, [sp, #20]
	if (*sp == '*') {
     7ee:	785b      	ldrb	r3, [r3, #1]
     7f0:	2b2a      	cmp	r3, #42	; 0x2a
     7f2:	d048      	beq.n	886 <CONFIG_ISR_STACK_SIZE+0x86>
	size_t prec = extract_decimal(&sp);
     7f4:	a805      	add	r0, sp, #20
     7f6:	f005 fa5a 	bl	5cae <extract_decimal>
	conv->prec_value = prec;
     7fa:	900a      	str	r0, [sp, #40]	; 0x28
	conv->unsupported |= ((conv->prec_value < 0)
     7fc:	f89d 3020 	ldrb.w	r3, [sp, #32]
     800:	f3c3 0340 	ubfx	r3, r3, #1, #1
			      || (prec != (size_t)conv->prec_value));
     804:	2800      	cmp	r0, #0
     806:	db47      	blt.n	898 <CONFIG_ISR_STACK_SIZE+0x98>
     808:	2200      	movs	r2, #0
	conv->unsupported |= ((conv->prec_value < 0)
     80a:	4313      	orrs	r3, r2
     80c:	f89d 2020 	ldrb.w	r2, [sp, #32]
     810:	f363 0241 	bfi	r2, r3, #1, #1
     814:	f88d 2020 	strb.w	r2, [sp, #32]
	return sp;
     818:	f8dd 8014 	ldr.w	r8, [sp, #20]
	switch (*sp) {
     81c:	f898 3000 	ldrb.w	r3, [r8]
     820:	3b4c      	subs	r3, #76	; 0x4c
     822:	2b2e      	cmp	r3, #46	; 0x2e
     824:	f200 80dc 	bhi.w	9e0 <CONFIG_ISR_STACK_SIZE+0x1e0>
     828:	e8df f003 	tbb	[pc, r3]
     82c:	dadadaca 	.word	0xdadadaca
     830:	dadadada 	.word	0xdadadada
     834:	dadadada 	.word	0xdadadada
     838:	dadadada 	.word	0xdadadada
     83c:	dadadada 	.word	0xdadadada
     840:	dadadada 	.word	0xdadadada
     844:	dadadada 	.word	0xdadadada
     848:	da6ada38 	.word	0xda6ada38
     84c:	dadada51 	.word	0xdadada51
     850:	dadadada 	.word	0xdadadada
     854:	dadadac0 	.word	0xdadadac0
     858:	dada      	.short	0xdada
     85a:	b6          	.byte	0xb6
     85b:	00          	.byte	0x00
		conv->flag_zero = false;
     85c:	f89d 3020 	ldrb.w	r3, [sp, #32]
     860:	f36f 1386 	bfc	r3, #6, #1
     864:	f88d 3020 	strb.w	r3, [sp, #32]
     868:	e78a      	b.n	780 <cbvprintf+0x108>
		conv->width_star = true;
     86a:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     86e:	f043 0301 	orr.w	r3, r3, #1
     872:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		return ++sp;
     876:	4643      	mov	r3, r8
     878:	3301      	adds	r3, #1
     87a:	e7a7      	b.n	7cc <cbvprintf+0x154>
				      || (width != (size_t)conv->width_value));
     87c:	2201      	movs	r2, #1
     87e:	e79d      	b.n	7bc <cbvprintf+0x144>
		return sp;
     880:	f8dd 8014 	ldr.w	r8, [sp, #20]
     884:	e7ca      	b.n	81c <CONFIG_ISR_STACK_SIZE+0x1c>
		conv->prec_star = true;
     886:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     88a:	f043 0304 	orr.w	r3, r3, #4
     88e:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		return ++sp;
     892:	f102 0801 	add.w	r8, r2, #1
     896:	e7c1      	b.n	81c <CONFIG_ISR_STACK_SIZE+0x1c>
			      || (prec != (size_t)conv->prec_value));
     898:	2201      	movs	r2, #1
     89a:	e7b6      	b.n	80a <CONFIG_ISR_STACK_SIZE+0xa>
		if (*++sp == 'h') {
     89c:	f108 0201 	add.w	r2, r8, #1
     8a0:	f898 3001 	ldrb.w	r3, [r8, #1]
     8a4:	2b68      	cmp	r3, #104	; 0x68
     8a6:	d008      	beq.n	8ba <CONFIG_ISR_STACK_SIZE+0xba>
			conv->length_mod = LENGTH_H;
     8a8:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     8ac:	2102      	movs	r1, #2
     8ae:	f361 03c6 	bfi	r3, r1, #3, #4
     8b2:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		if (*++sp == 'h') {
     8b6:	4690      	mov	r8, r2
     8b8:	e02b      	b.n	912 <CONFIG_ISR_STACK_SIZE+0x112>
			conv->length_mod = LENGTH_HH;
     8ba:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     8be:	2201      	movs	r2, #1
     8c0:	f362 03c6 	bfi	r3, r2, #3, #4
     8c4:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
			++sp;
     8c8:	f108 0802 	add.w	r8, r8, #2
     8cc:	e021      	b.n	912 <CONFIG_ISR_STACK_SIZE+0x112>
		if (*++sp == 'l') {
     8ce:	f108 0201 	add.w	r2, r8, #1
     8d2:	f898 3001 	ldrb.w	r3, [r8, #1]
     8d6:	2b6c      	cmp	r3, #108	; 0x6c
     8d8:	d008      	beq.n	8ec <CONFIG_ISR_STACK_SIZE+0xec>
			conv->length_mod = LENGTH_L;
     8da:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     8de:	2103      	movs	r1, #3
     8e0:	f361 03c6 	bfi	r3, r1, #3, #4
     8e4:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		if (*++sp == 'l') {
     8e8:	4690      	mov	r8, r2
     8ea:	e012      	b.n	912 <CONFIG_ISR_STACK_SIZE+0x112>
			conv->length_mod = LENGTH_LL;
     8ec:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     8f0:	2204      	movs	r2, #4
     8f2:	f362 03c6 	bfi	r3, r2, #3, #4
     8f6:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
			++sp;
     8fa:	f108 0802 	add.w	r8, r8, #2
     8fe:	e008      	b.n	912 <CONFIG_ISR_STACK_SIZE+0x112>
		conv->length_mod = LENGTH_J;
     900:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     904:	2205      	movs	r2, #5
     906:	f362 03c6 	bfi	r3, r2, #3, #4
     90a:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     90e:	f108 0801 	add.w	r8, r8, #1
	conv->specifier = *sp++;
     912:	f818 3b01 	ldrb.w	r3, [r8], #1
     916:	f88d 3023 	strb.w	r3, [sp, #35]	; 0x23
	switch (conv->specifier) {
     91a:	f1a3 0241 	sub.w	r2, r3, #65	; 0x41
     91e:	2a37      	cmp	r2, #55	; 0x37
     920:	f200 8150 	bhi.w	bc4 <CONFIG_ISR_STACK_SIZE+0x3c4>
     924:	e8df f012 	tbh	[pc, r2, lsl #1]
     928:	014e0126 	.word	0x014e0126
     92c:	014e014e 	.word	0x014e014e
     930:	01260126 	.word	0x01260126
     934:	014e0126 	.word	0x014e0126
     938:	014e014e 	.word	0x014e014e
     93c:	014e014e 	.word	0x014e014e
     940:	014e014e 	.word	0x014e014e
     944:	014e014e 	.word	0x014e014e
     948:	014e014e 	.word	0x014e014e
     94c:	014e014e 	.word	0x014e014e
     950:	014e014e 	.word	0x014e014e
     954:	0113014e 	.word	0x0113014e
     958:	014e014e 	.word	0x014e014e
     95c:	014e014e 	.word	0x014e014e
     960:	014e014e 	.word	0x014e014e
     964:	014e014e 	.word	0x014e014e
     968:	014e0126 	.word	0x014e0126
     96c:	00630113 	.word	0x00630113
     970:	01260126 	.word	0x01260126
     974:	014e0126 	.word	0x014e0126
     978:	014e0063 	.word	0x014e0063
     97c:	014e014e 	.word	0x014e014e
     980:	012f014e 	.word	0x012f014e
     984:	013f0113 	.word	0x013f0113
     988:	014e014e 	.word	0x014e014e
     98c:	014e013f 	.word	0x014e013f
     990:	014e0113 	.word	0x014e0113
     994:	0113014e 	.word	0x0113014e
		conv->length_mod = LENGTH_Z;
     998:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     99c:	2206      	movs	r2, #6
     99e:	f362 03c6 	bfi	r3, r2, #3, #4
     9a2:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     9a6:	f108 0801 	add.w	r8, r8, #1
		break;
     9aa:	e7b2      	b.n	912 <CONFIG_ISR_STACK_SIZE+0x112>
		conv->length_mod = LENGTH_T;
     9ac:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     9b0:	2207      	movs	r2, #7
     9b2:	f362 03c6 	bfi	r3, r2, #3, #4
     9b6:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     9ba:	f108 0801 	add.w	r8, r8, #1
		break;
     9be:	e7a8      	b.n	912 <CONFIG_ISR_STACK_SIZE+0x112>
		conv->length_mod = LENGTH_UPPER_L;
     9c0:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     9c4:	2208      	movs	r2, #8
     9c6:	f362 03c6 	bfi	r3, r2, #3, #4
     9ca:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     9ce:	f108 0801 	add.w	r8, r8, #1
		conv->unsupported = true;
     9d2:	f89d 3020 	ldrb.w	r3, [sp, #32]
     9d6:	f043 0302 	orr.w	r3, r3, #2
     9da:	f88d 3020 	strb.w	r3, [sp, #32]
		break;
     9de:	e798      	b.n	912 <CONFIG_ISR_STACK_SIZE+0x112>
		conv->length_mod = LENGTH_NONE;
     9e0:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     9e4:	f36f 03c6 	bfc	r3, #3, #4
     9e8:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		break;
     9ec:	e791      	b.n	912 <CONFIG_ISR_STACK_SIZE+0x112>
		conv->specifier_cat = SPECIFIER_SINT;
     9ee:	f89d 2022 	ldrb.w	r2, [sp, #34]	; 0x22
     9f2:	2101      	movs	r1, #1
     9f4:	f361 0202 	bfi	r2, r1, #0, #3
     9f8:	f88d 2022 	strb.w	r2, [sp, #34]	; 0x22
		if (conv->length_mod == LENGTH_UPPER_L) {
     9fc:	f89d 2021 	ldrb.w	r2, [sp, #33]	; 0x21
     a00:	f002 0278 	and.w	r2, r2, #120	; 0x78
     a04:	2a40      	cmp	r2, #64	; 0x40
     a06:	f000 80aa 	beq.w	b5e <CONFIG_ISR_STACK_SIZE+0x35e>
		if (conv->specifier == 'c') {
     a0a:	2b63      	cmp	r3, #99	; 0x63
     a0c:	f000 80ae 	beq.w	b6c <CONFIG_ISR_STACK_SIZE+0x36c>
	conv->unsupported |= unsupported;
     a10:	f89d 3020 	ldrb.w	r3, [sp, #32]
     a14:	f3c3 0240 	ubfx	r2, r3, #1, #1
     a18:	4317      	orrs	r7, r2
     a1a:	f367 0341 	bfi	r3, r7, #1, #1
     a1e:	f88d 3020 	strb.w	r3, [sp, #32]
		fp = extract_conversion(conv, sp);

		/* If dynamic width is specified, process it,
		 * otherwise set width if present.
		 */
		if (conv->width_star) {
     a22:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     a26:	f013 0f01 	tst.w	r3, #1
     a2a:	f000 80da 	beq.w	be2 <CONFIG_ISR_STACK_SIZE+0x3e2>
			width = va_arg(ap, int);
     a2e:	9b03      	ldr	r3, [sp, #12]
     a30:	1d1a      	adds	r2, r3, #4
     a32:	9203      	str	r2, [sp, #12]
     a34:	681f      	ldr	r7, [r3, #0]

			if (width < 0) {
     a36:	2f00      	cmp	r7, #0
     a38:	f2c0 80cb 	blt.w	bd2 <CONFIG_ISR_STACK_SIZE+0x3d2>

		/* If dynamic precision is specified, process it, otherwise
		 * set precision if present.  For floating point where
		 * precision is not present use 6.
		 */
		if (conv->prec_star) {
     a3c:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     a40:	f013 0f04 	tst.w	r3, #4
     a44:	f000 80df 	beq.w	c06 <CONFIG_ISR_STACK_SIZE+0x406>
			int arg = va_arg(ap, int);
     a48:	9b03      	ldr	r3, [sp, #12]
     a4a:	1d1a      	adds	r2, r3, #4
     a4c:	9203      	str	r2, [sp, #12]
     a4e:	f8d3 b000 	ldr.w	fp, [r3]

			if (arg < 0) {
     a52:	f1bb 0f00 	cmp.w	fp, #0
     a56:	f2c0 80cd 	blt.w	bf4 <CONFIG_ISR_STACK_SIZE+0x3f4>
		}

		/* Reuse width and precision memory in conv for value
		 * padding counts.
		 */
		conv->pad0_value = 0;
     a5a:	2300      	movs	r3, #0
     a5c:	9309      	str	r3, [sp, #36]	; 0x24
		conv->pad0_pre_exp = 0;
     a5e:	930a      	str	r3, [sp, #40]	; 0x28
		 * This can't be extracted to a helper function because
		 * passing a pointer to va_list doesn't work on x86_64.  See
		 * https://stackoverflow.com/a/8048892.
		 */
		enum specifier_cat_enum specifier_cat
			= (enum specifier_cat_enum)conv->specifier_cat;
     a60:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     a64:	f003 0307 	and.w	r3, r3, #7
		enum length_mod_enum length_mod
			= (enum length_mod_enum)conv->length_mod;
     a68:	f89d 1021 	ldrb.w	r1, [sp, #33]	; 0x21
     a6c:	f3c1 01c3 	ubfx	r1, r1, #3, #4
		/* Extract the value based on the argument category and length.
		 *
		 * Note that the length modifier doesn't affect the value of a
		 * pointer argument.
		 */
		if (specifier_cat == SPECIFIER_SINT) {
     a70:	2b01      	cmp	r3, #1
     a72:	f000 80d1 	beq.w	c18 <CONFIG_ISR_STACK_SIZE+0x418>
			if (length_mod == LENGTH_HH) {
				value->sint = (char)value->sint;
			} else if (length_mod == LENGTH_H) {
				value->sint = (short)value->sint;
			}
		} else if (specifier_cat == SPECIFIER_UINT) {
     a76:	2b02      	cmp	r3, #2
     a78:	f000 8116 	beq.w	ca8 <CONFIG_ISR_STACK_SIZE+0x4a8>
			if (length_mod == LENGTH_HH) {
				value->uint = (unsigned char)value->uint;
			} else if (length_mod == LENGTH_H) {
				value->uint = (unsigned short)value->uint;
			}
		} else if (specifier_cat == SPECIFIER_FP) {
     a7c:	2b04      	cmp	r3, #4
     a7e:	f000 8167 	beq.w	d50 <CONFIG_ISR_STACK_SIZE+0x550>
			if (length_mod == LENGTH_UPPER_L) {
				value->ldbl = va_arg(ap, long double);
			} else {
				value->dbl = va_arg(ap, double);
			}
		} else if (specifier_cat == SPECIFIER_PTR) {
     a82:	2b03      	cmp	r3, #3
     a84:	f000 817e 	beq.w	d84 <CONFIG_ISR_STACK_SIZE+0x584>
		/* We've now consumed all arguments related to this
		 * specification.  If the conversion is invalid, or is
		 * something we don't support, then output the original
		 * specification and move on.
		 */
		if (conv->invalid || conv->unsupported) {
     a88:	f89d 9020 	ldrb.w	r9, [sp, #32]
     a8c:	f019 0303 	ands.w	r3, r9, #3
     a90:	9302      	str	r3, [sp, #8]
     a92:	f040 817d 	bne.w	d90 <CONFIG_ISR_STACK_SIZE+0x590>
		}

		/* Do formatting, either into the buffer or
		 * referencing external data.
		 */
		switch (conv->specifier) {
     a96:	f89d 3023 	ldrb.w	r3, [sp, #35]	; 0x23
     a9a:	3b25      	subs	r3, #37	; 0x25
     a9c:	2b53      	cmp	r3, #83	; 0x53
     a9e:	f200 8233 	bhi.w	f08 <CONFIG_ISR_STACK_SIZE+0x708>
     aa2:	e8df f013 	tbh	[pc, r3, lsl #1]
     aa6:	0181      	.short	0x0181
     aa8:	02310231 	.word	0x02310231
     aac:	02310231 	.word	0x02310231
     ab0:	02310231 	.word	0x02310231
     ab4:	02310231 	.word	0x02310231
     ab8:	02310231 	.word	0x02310231
     abc:	02310231 	.word	0x02310231
     ac0:	02310231 	.word	0x02310231
     ac4:	02310231 	.word	0x02310231
     ac8:	02310231 	.word	0x02310231
     acc:	02310231 	.word	0x02310231
     ad0:	02310231 	.word	0x02310231
     ad4:	02310231 	.word	0x02310231
     ad8:	02310231 	.word	0x02310231
     adc:	02310231 	.word	0x02310231
     ae0:	02310231 	.word	0x02310231
     ae4:	02310231 	.word	0x02310231
     ae8:	02310231 	.word	0x02310231
     aec:	02310231 	.word	0x02310231
     af0:	02310231 	.word	0x02310231
     af4:	02310231 	.word	0x02310231
     af8:	02310231 	.word	0x02310231
     afc:	02310231 	.word	0x02310231
     b00:	02310231 	.word	0x02310231
     b04:	02310231 	.word	0x02310231
     b08:	02310231 	.word	0x02310231
     b0c:	023101c7 	.word	0x023101c7
     b10:	02310231 	.word	0x02310231
     b14:	02310231 	.word	0x02310231
     b18:	02310231 	.word	0x02310231
     b1c:	02310231 	.word	0x02310231
     b20:	01a10231 	.word	0x01a10231
     b24:	023101ab 	.word	0x023101ab
     b28:	02310231 	.word	0x02310231
     b2c:	01ab0231 	.word	0x01ab0231
     b30:	02310231 	.word	0x02310231
     b34:	02310231 	.word	0x02310231
     b38:	01c70208 	.word	0x01c70208
     b3c:	023101ea 	.word	0x023101ea
     b40:	018f0231 	.word	0x018f0231
     b44:	01c70231 	.word	0x01c70231
     b48:	02310231 	.word	0x02310231
     b4c:	01c7      	.short	0x01c7
		conv->specifier_cat = SPECIFIER_UINT;
     b4e:	f89d 2022 	ldrb.w	r2, [sp, #34]	; 0x22
     b52:	2102      	movs	r1, #2
     b54:	f361 0202 	bfi	r2, r1, #0, #3
     b58:	f88d 2022 	strb.w	r2, [sp, #34]	; 0x22
     b5c:	e74e      	b.n	9fc <CONFIG_ISR_STACK_SIZE+0x1fc>
			conv->invalid = true;
     b5e:	f89d 1020 	ldrb.w	r1, [sp, #32]
     b62:	f041 0101 	orr.w	r1, r1, #1
     b66:	f88d 1020 	strb.w	r1, [sp, #32]
     b6a:	e74e      	b.n	a0a <CONFIG_ISR_STACK_SIZE+0x20a>
			unsupported = (conv->length_mod != LENGTH_NONE);
     b6c:	1e17      	subs	r7, r2, #0
     b6e:	bf18      	it	ne
     b70:	2701      	movne	r7, #1
     b72:	e74d      	b.n	a10 <CONFIG_ISR_STACK_SIZE+0x210>
		conv->specifier_cat = SPECIFIER_FP;
     b74:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     b78:	2204      	movs	r2, #4
     b7a:	f362 0302 	bfi	r3, r2, #0, #3
     b7e:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
			unsupported = true;
     b82:	2701      	movs	r7, #1
			break;
     b84:	e744      	b.n	a10 <CONFIG_ISR_STACK_SIZE+0x210>
		conv->specifier_cat = SPECIFIER_PTR;
     b86:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     b8a:	2203      	movs	r2, #3
     b8c:	f362 0302 	bfi	r3, r2, #0, #3
     b90:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
		if (conv->length_mod == LENGTH_UPPER_L) {
     b94:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     b98:	f003 0378 	and.w	r3, r3, #120	; 0x78
     b9c:	2b40      	cmp	r3, #64	; 0x40
     b9e:	f47f af37 	bne.w	a10 <CONFIG_ISR_STACK_SIZE+0x210>
			unsupported = true;
     ba2:	2701      	movs	r7, #1
     ba4:	e734      	b.n	a10 <CONFIG_ISR_STACK_SIZE+0x210>
		conv->specifier_cat = SPECIFIER_PTR;
     ba6:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     baa:	2203      	movs	r2, #3
     bac:	f362 0302 	bfi	r3, r2, #0, #3
     bb0:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
		if (conv->length_mod != LENGTH_NONE) {
     bb4:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     bb8:	f013 0f78 	tst.w	r3, #120	; 0x78
     bbc:	f43f af28 	beq.w	a10 <CONFIG_ISR_STACK_SIZE+0x210>
			unsupported = true;
     bc0:	2701      	movs	r7, #1
     bc2:	e725      	b.n	a10 <CONFIG_ISR_STACK_SIZE+0x210>
		conv->invalid = true;
     bc4:	f89d 3020 	ldrb.w	r3, [sp, #32]
     bc8:	f043 0301 	orr.w	r3, r3, #1
     bcc:	f88d 3020 	strb.w	r3, [sp, #32]
		break;
     bd0:	e71e      	b.n	a10 <CONFIG_ISR_STACK_SIZE+0x210>
				conv->flag_dash = true;
     bd2:	f89d 3020 	ldrb.w	r3, [sp, #32]
     bd6:	f043 0304 	orr.w	r3, r3, #4
     bda:	f88d 3020 	strb.w	r3, [sp, #32]
				width = -width;
     bde:	427f      	negs	r7, r7
     be0:	e72c      	b.n	a3c <CONFIG_ISR_STACK_SIZE+0x23c>
		} else if (conv->width_present) {
     be2:	f99d 3020 	ldrsb.w	r3, [sp, #32]
     be6:	2b00      	cmp	r3, #0
     be8:	db02      	blt.n	bf0 <CONFIG_ISR_STACK_SIZE+0x3f0>
		int width = -1;
     bea:	f04f 37ff 	mov.w	r7, #4294967295
     bee:	e725      	b.n	a3c <CONFIG_ISR_STACK_SIZE+0x23c>
			width = conv->width_value;
     bf0:	9f09      	ldr	r7, [sp, #36]	; 0x24
     bf2:	e723      	b.n	a3c <CONFIG_ISR_STACK_SIZE+0x23c>
				conv->prec_present = false;
     bf4:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     bf8:	f36f 0341 	bfc	r3, #1, #1
     bfc:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		int precision = -1;
     c00:	f04f 3bff 	mov.w	fp, #4294967295
     c04:	e729      	b.n	a5a <CONFIG_ISR_STACK_SIZE+0x25a>
		} else if (conv->prec_present) {
     c06:	f013 0f02 	tst.w	r3, #2
     c0a:	d002      	beq.n	c12 <CONFIG_ISR_STACK_SIZE+0x412>
			precision = conv->prec_value;
     c0c:	f8dd b028 	ldr.w	fp, [sp, #40]	; 0x28
     c10:	e723      	b.n	a5a <CONFIG_ISR_STACK_SIZE+0x25a>
		int precision = -1;
     c12:	f04f 3bff 	mov.w	fp, #4294967295
     c16:	e720      	b.n	a5a <CONFIG_ISR_STACK_SIZE+0x25a>
			switch (length_mod) {
     c18:	1ecb      	subs	r3, r1, #3
     c1a:	2b04      	cmp	r3, #4
     c1c:	d804      	bhi.n	c28 <CONFIG_ISR_STACK_SIZE+0x428>
     c1e:	e8df f003 	tbb	[pc, r3]
     c22:	1d0b      	.short	0x1d0b
     c24:	3529      	.short	0x3529
     c26:	35          	.byte	0x35
     c27:	00          	.byte	0x00
				value->sint = va_arg(ap, int);
     c28:	9b03      	ldr	r3, [sp, #12]
     c2a:	1d1a      	adds	r2, r3, #4
     c2c:	9203      	str	r2, [sp, #12]
     c2e:	681a      	ldr	r2, [r3, #0]
     c30:	17d3      	asrs	r3, r2, #31
     c32:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     c36:	e006      	b.n	c46 <CONFIG_ISR_STACK_SIZE+0x446>
					value->sint = va_arg(ap, long);
     c38:	9b03      	ldr	r3, [sp, #12]
     c3a:	1d1a      	adds	r2, r3, #4
     c3c:	9203      	str	r2, [sp, #12]
     c3e:	681a      	ldr	r2, [r3, #0]
     c40:	17d3      	asrs	r3, r2, #31
     c42:	e9cd 2306 	strd	r2, r3, [sp, #24]
			if (length_mod == LENGTH_HH) {
     c46:	2901      	cmp	r1, #1
     c48:	d028      	beq.n	c9c <CONFIG_ISR_STACK_SIZE+0x49c>
			} else if (length_mod == LENGTH_H) {
     c4a:	2902      	cmp	r1, #2
     c4c:	f47f af1c 	bne.w	a88 <CONFIG_ISR_STACK_SIZE+0x288>
				value->sint = (short)value->sint;
     c50:	f9bd 2018 	ldrsh.w	r2, [sp, #24]
     c54:	17d3      	asrs	r3, r2, #31
     c56:	e9cd 2306 	strd	r2, r3, [sp, #24]
     c5a:	e715      	b.n	a88 <CONFIG_ISR_STACK_SIZE+0x288>
					(sint_value_type)va_arg(ap, long long);
     c5c:	9b03      	ldr	r3, [sp, #12]
     c5e:	3307      	adds	r3, #7
     c60:	f023 0307 	bic.w	r3, r3, #7
     c64:	f103 0208 	add.w	r2, r3, #8
     c68:	9203      	str	r2, [sp, #12]
     c6a:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->sint =
     c6e:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     c72:	e7e8      	b.n	c46 <CONFIG_ISR_STACK_SIZE+0x446>
					(sint_value_type)va_arg(ap, intmax_t);
     c74:	9b03      	ldr	r3, [sp, #12]
     c76:	3307      	adds	r3, #7
     c78:	f023 0307 	bic.w	r3, r3, #7
     c7c:	f103 0208 	add.w	r2, r3, #8
     c80:	9203      	str	r2, [sp, #12]
     c82:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->sint =
     c86:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     c8a:	e7dc      	b.n	c46 <CONFIG_ISR_STACK_SIZE+0x446>
					(sint_value_type)va_arg(ap, ptrdiff_t);
     c8c:	9b03      	ldr	r3, [sp, #12]
     c8e:	1d1a      	adds	r2, r3, #4
     c90:	9203      	str	r2, [sp, #12]
     c92:	681a      	ldr	r2, [r3, #0]
     c94:	17d3      	asrs	r3, r2, #31
				value->sint =
     c96:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     c9a:	e7d4      	b.n	c46 <CONFIG_ISR_STACK_SIZE+0x446>
				value->sint = (char)value->sint;
     c9c:	f89d 3018 	ldrb.w	r3, [sp, #24]
     ca0:	9306      	str	r3, [sp, #24]
     ca2:	2300      	movs	r3, #0
     ca4:	9307      	str	r3, [sp, #28]
     ca6:	e6ef      	b.n	a88 <CONFIG_ISR_STACK_SIZE+0x288>
			switch (length_mod) {
     ca8:	1ecb      	subs	r3, r1, #3
     caa:	2b04      	cmp	r3, #4
     cac:	d804      	bhi.n	cb8 <CONFIG_ISR_STACK_SIZE+0x4b8>
     cae:	e8df f003 	tbb	[pc, r3]
     cb2:	1f0b      	.short	0x1f0b
     cb4:	4135      	.short	0x4135
     cb6:	41          	.byte	0x41
     cb7:	00          	.byte	0x00
				value->uint = va_arg(ap, unsigned int);
     cb8:	9b03      	ldr	r3, [sp, #12]
     cba:	1d1a      	adds	r2, r3, #4
     cbc:	9203      	str	r2, [sp, #12]
     cbe:	681b      	ldr	r3, [r3, #0]
     cc0:	9306      	str	r3, [sp, #24]
     cc2:	2300      	movs	r3, #0
     cc4:	9307      	str	r3, [sp, #28]
				break;
     cc6:	e01e      	b.n	d06 <CONFIG_ISR_STACK_SIZE+0x506>
				    && (conv->specifier == 'c')) {
     cc8:	f89d 3023 	ldrb.w	r3, [sp, #35]	; 0x23
				if ((!WCHAR_IS_SIGNED)
     ccc:	2b63      	cmp	r3, #99	; 0x63
     cce:	d007      	beq.n	ce0 <CONFIG_ISR_STACK_SIZE+0x4e0>
					value->uint = va_arg(ap, unsigned long);
     cd0:	9b03      	ldr	r3, [sp, #12]
     cd2:	1d1a      	adds	r2, r3, #4
     cd4:	9203      	str	r2, [sp, #12]
     cd6:	681b      	ldr	r3, [r3, #0]
     cd8:	9306      	str	r3, [sp, #24]
     cda:	2300      	movs	r3, #0
     cdc:	9307      	str	r3, [sp, #28]
     cde:	e012      	b.n	d06 <CONFIG_ISR_STACK_SIZE+0x506>
					value->uint = (wchar_t)va_arg(ap,
     ce0:	9b03      	ldr	r3, [sp, #12]
     ce2:	1d1a      	adds	r2, r3, #4
     ce4:	9203      	str	r2, [sp, #12]
     ce6:	681b      	ldr	r3, [r3, #0]
     ce8:	9306      	str	r3, [sp, #24]
     cea:	2300      	movs	r3, #0
     cec:	9307      	str	r3, [sp, #28]
     cee:	e00a      	b.n	d06 <CONFIG_ISR_STACK_SIZE+0x506>
					(uint_value_type)va_arg(ap,
     cf0:	9b03      	ldr	r3, [sp, #12]
     cf2:	3307      	adds	r3, #7
     cf4:	f023 0307 	bic.w	r3, r3, #7
     cf8:	f103 0208 	add.w	r2, r3, #8
     cfc:	9203      	str	r2, [sp, #12]
     cfe:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->uint =
     d02:	e9cd 2306 	strd	r2, r3, [sp, #24]
			if (length_mod == LENGTH_HH) {
     d06:	2901      	cmp	r1, #1
     d08:	d01c      	beq.n	d44 <CONFIG_ISR_STACK_SIZE+0x544>
			} else if (length_mod == LENGTH_H) {
     d0a:	2902      	cmp	r1, #2
     d0c:	f47f aebc 	bne.w	a88 <CONFIG_ISR_STACK_SIZE+0x288>
				value->uint = (unsigned short)value->uint;
     d10:	f8bd 3018 	ldrh.w	r3, [sp, #24]
     d14:	9306      	str	r3, [sp, #24]
     d16:	2300      	movs	r3, #0
     d18:	9307      	str	r3, [sp, #28]
     d1a:	e6b5      	b.n	a88 <CONFIG_ISR_STACK_SIZE+0x288>
					(uint_value_type)va_arg(ap,
     d1c:	9b03      	ldr	r3, [sp, #12]
     d1e:	3307      	adds	r3, #7
     d20:	f023 0307 	bic.w	r3, r3, #7
     d24:	f103 0208 	add.w	r2, r3, #8
     d28:	9203      	str	r2, [sp, #12]
     d2a:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->uint =
     d2e:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     d32:	e7e8      	b.n	d06 <CONFIG_ISR_STACK_SIZE+0x506>
					(uint_value_type)va_arg(ap, size_t);
     d34:	9b03      	ldr	r3, [sp, #12]
     d36:	1d1a      	adds	r2, r3, #4
     d38:	9203      	str	r2, [sp, #12]
     d3a:	681b      	ldr	r3, [r3, #0]
				value->uint =
     d3c:	9306      	str	r3, [sp, #24]
     d3e:	2300      	movs	r3, #0
     d40:	9307      	str	r3, [sp, #28]
				break;
     d42:	e7e0      	b.n	d06 <CONFIG_ISR_STACK_SIZE+0x506>
				value->uint = (unsigned char)value->uint;
     d44:	f89d 3018 	ldrb.w	r3, [sp, #24]
     d48:	9306      	str	r3, [sp, #24]
     d4a:	2300      	movs	r3, #0
     d4c:	9307      	str	r3, [sp, #28]
     d4e:	e69b      	b.n	a88 <CONFIG_ISR_STACK_SIZE+0x288>
			if (length_mod == LENGTH_UPPER_L) {
     d50:	2908      	cmp	r1, #8
     d52:	d00b      	beq.n	d6c <CONFIG_ISR_STACK_SIZE+0x56c>
				value->dbl = va_arg(ap, double);
     d54:	9b03      	ldr	r3, [sp, #12]
     d56:	3307      	adds	r3, #7
     d58:	f023 0307 	bic.w	r3, r3, #7
     d5c:	f103 0208 	add.w	r2, r3, #8
     d60:	9203      	str	r2, [sp, #12]
     d62:	e9d3 2300 	ldrd	r2, r3, [r3]
     d66:	e9cd 2306 	strd	r2, r3, [sp, #24]
     d6a:	e68d      	b.n	a88 <CONFIG_ISR_STACK_SIZE+0x288>
				value->ldbl = va_arg(ap, long double);
     d6c:	9b03      	ldr	r3, [sp, #12]
     d6e:	3307      	adds	r3, #7
     d70:	f023 0307 	bic.w	r3, r3, #7
     d74:	f103 0208 	add.w	r2, r3, #8
     d78:	9203      	str	r2, [sp, #12]
     d7a:	e9d3 2300 	ldrd	r2, r3, [r3]
     d7e:	e9cd 2306 	strd	r2, r3, [sp, #24]
     d82:	e681      	b.n	a88 <CONFIG_ISR_STACK_SIZE+0x288>
			value->ptr = va_arg(ap, void *);
     d84:	9b03      	ldr	r3, [sp, #12]
     d86:	1d1a      	adds	r2, r3, #4
     d88:	9203      	str	r2, [sp, #12]
     d8a:	681b      	ldr	r3, [r3, #0]
     d8c:	9306      	str	r3, [sp, #24]
     d8e:	e67b      	b.n	a88 <CONFIG_ISR_STACK_SIZE+0x288>
			OUTS(sp, fp);
     d90:	4643      	mov	r3, r8
     d92:	4652      	mov	r2, sl
     d94:	4629      	mov	r1, r5
     d96:	4630      	mov	r0, r6
     d98:	f005 f806 	bl	5da8 <outs>
     d9c:	2800      	cmp	r0, #0
     d9e:	f2c0 814f 	blt.w	1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>
     da2:	4404      	add	r4, r0
		fp = extract_conversion(conv, sp);
     da4:	46c2      	mov	sl, r8
			continue;
     da6:	e46f      	b.n	688 <cbvprintf+0x10>
		case '%':
			OUTC('%');
     da8:	4629      	mov	r1, r5
     daa:	2025      	movs	r0, #37	; 0x25
     dac:	47b0      	blx	r6
     dae:	2800      	cmp	r0, #0
     db0:	f2c0 8146 	blt.w	1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>
     db4:	3401      	adds	r4, #1
		char sign = 0;
     db6:	f8dd 9008 	ldr.w	r9, [sp, #8]
		const char *bpe = buf + sizeof(buf);
     dba:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
		const char *bps = NULL;
     dbe:	f04f 0a00 	mov.w	sl, #0
			break;
     dc2:	e0a7      	b.n	f14 <CONFIG_ISR_STACK_SIZE+0x714>
		case 's': {
			bps = (const char *)value->ptr;
     dc4:	f8dd a018 	ldr.w	sl, [sp, #24]

			size_t len;

			if (precision >= 0) {
     dc8:	f1bb 0f00 	cmp.w	fp, #0
     dcc:	db08      	blt.n	de0 <CONFIG_ISR_STACK_SIZE+0x5e0>
				len = strnlen(bps, precision);
     dce:	4659      	mov	r1, fp
     dd0:	4650      	mov	r0, sl
     dd2:	f005 f8dd 	bl	5f90 <strnlen>
			} else {
				len = strlen(bps);
			}

			bpe = bps + len;
     dd6:	eb0a 0b00 	add.w	fp, sl, r0
		char sign = 0;
     dda:	f8dd 9008 	ldr.w	r9, [sp, #8]
			precision = -1;

			break;
     dde:	e099      	b.n	f14 <CONFIG_ISR_STACK_SIZE+0x714>
				len = strlen(bps);
     de0:	4650      	mov	r0, sl
     de2:	f005 f8cd 	bl	5f80 <strlen>
     de6:	e7f6      	b.n	dd6 <CONFIG_ISR_STACK_SIZE+0x5d6>
		}
		case 'c':
			bps = buf;
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     de8:	9b06      	ldr	r3, [sp, #24]
     dea:	f88d 3030 	strb.w	r3, [sp, #48]	; 0x30
		char sign = 0;
     dee:	f8dd 9008 	ldr.w	r9, [sp, #8]
			bpe = buf + 1;
     df2:	f10d 0b31 	add.w	fp, sp, #49	; 0x31
			bps = buf;
     df6:	f10d 0a30 	add.w	sl, sp, #48	; 0x30
			break;
     dfa:	e08b      	b.n	f14 <CONFIG_ISR_STACK_SIZE+0x714>
		case 'd':
		case 'i':
			if (conv->flag_plus) {
     dfc:	f019 0f08 	tst.w	r9, #8
     e00:	d105      	bne.n	e0e <CONFIG_ISR_STACK_SIZE+0x60e>
				sign = '+';
			} else if (conv->flag_space) {
     e02:	f019 0910 	ands.w	r9, r9, #16
     e06:	d004      	beq.n	e12 <CONFIG_ISR_STACK_SIZE+0x612>
				sign = ' ';
     e08:	f04f 0920 	mov.w	r9, #32
     e0c:	e001      	b.n	e12 <CONFIG_ISR_STACK_SIZE+0x612>
				sign = '+';
     e0e:	f04f 092b 	mov.w	r9, #43	; 0x2b

			/* sint/uint overlay in the union, and so
			 * can't appear in read and write operations
			 * in the same statement.
			 */
			sint = value->sint;
     e12:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
			if (sint < 0) {
     e16:	2a00      	cmp	r2, #0
     e18:	f173 0100 	sbcs.w	r1, r3, #0
     e1c:	db02      	blt.n	e24 <CONFIG_ISR_STACK_SIZE+0x624>
				sign = '-';
				value->uint = (uint_value_type)-sint;
			} else {
				value->uint = (uint_value_type)sint;
     e1e:	e9cd 2306 	strd	r2, r3, [sp, #24]
     e22:	e009      	b.n	e38 <CONFIG_ISR_STACK_SIZE+0x638>
				value->uint = (uint_value_type)-sint;
     e24:	4252      	negs	r2, r2
     e26:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
     e2a:	e9cd 2306 	strd	r2, r3, [sp, #24]
				sign = '-';
     e2e:	f04f 092d 	mov.w	r9, #45	; 0x2d
     e32:	e001      	b.n	e38 <CONFIG_ISR_STACK_SIZE+0x638>
		switch (conv->specifier) {
     e34:	f8dd 9008 	ldr.w	r9, [sp, #8]
			__fallthrough;
		case 'o':
		case 'u':
		case 'x':
		case 'X':
			bps = encode_uint(value->uint, conv, buf, bpe);
     e38:	f10d 0346 	add.w	r3, sp, #70	; 0x46
     e3c:	9300      	str	r3, [sp, #0]
     e3e:	ab0c      	add	r3, sp, #48	; 0x30
     e40:	aa08      	add	r2, sp, #32
     e42:	e9dd 0106 	ldrd	r0, r1, [sp, #24]
     e46:	f004 ff45 	bl	5cd4 <encode_uint>
     e4a:	4682      	mov	sl, r0
			/* Update pad0 values based on precision and converted
			 * length.  Note that a non-empty sign is not in the
			 * converted sequence, but it does not affect the
			 * padding size.
			 */
			if (precision >= 0) {
     e4c:	f1bb 0f00 	cmp.w	fp, #0
     e50:	f2c0 8090 	blt.w	f74 <CONFIG_ISR_STACK_SIZE+0x774>
				size_t len = bpe - bps;
     e54:	f10d 0346 	add.w	r3, sp, #70	; 0x46
     e58:	eba3 030a 	sub.w	r3, r3, sl

				/* Zero-padding flag is ignored for integer
				 * conversions with precision.
				 */
				conv->flag_zero = false;
     e5c:	f89d 2020 	ldrb.w	r2, [sp, #32]
     e60:	f36f 1286 	bfc	r2, #6, #1
     e64:	f88d 2020 	strb.w	r2, [sp, #32]

				/* Set pad0_value to satisfy precision */
				if (len < (size_t)precision) {
     e68:	459b      	cmp	fp, r3
     e6a:	f240 8086 	bls.w	f7a <CONFIG_ISR_STACK_SIZE+0x77a>
					conv->pad0_value = precision - (int)len;
     e6e:	ebab 0303 	sub.w	r3, fp, r3
     e72:	9309      	str	r3, [sp, #36]	; 0x24
		const char *bpe = buf + sizeof(buf);
     e74:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
     e78:	e04c      	b.n	f14 <CONFIG_ISR_STACK_SIZE+0x714>
		case 'p':
			/* Implementation-defined: null is "(nil)", non-null
			 * has 0x prefix followed by significant address hex
			 * digits, no leading zeros.
			 */
			if (value->ptr != NULL) {
     e7a:	9806      	ldr	r0, [sp, #24]
     e7c:	b930      	cbnz	r0, e8c <CONFIG_ISR_STACK_SIZE+0x68c>
		char sign = 0;
     e7e:	f8dd 9008 	ldr.w	r9, [sp, #8]

				goto prec_int_pad0;
			}

			bps = "(nil)";
			bpe = bps + 5;
     e82:	f8df b1c4 	ldr.w	fp, [pc, #452]	; 1048 <CONFIG_FPROTECT_BLOCK_SIZE+0x48>
			bps = "(nil)";
     e86:	f1ab 0a05 	sub.w	sl, fp, #5
     e8a:	e043      	b.n	f14 <CONFIG_ISR_STACK_SIZE+0x714>
				bps = encode_uint((uintptr_t)value->ptr, conv,
     e8c:	f10d 0346 	add.w	r3, sp, #70	; 0x46
     e90:	9300      	str	r3, [sp, #0]
     e92:	ab0c      	add	r3, sp, #48	; 0x30
     e94:	aa08      	add	r2, sp, #32
     e96:	2100      	movs	r1, #0
     e98:	f004 ff1c 	bl	5cd4 <encode_uint>
     e9c:	4682      	mov	sl, r0
				conv->altform_0c = true;
     e9e:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     ea2:	f043 0310 	orr.w	r3, r3, #16
     ea6:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
				conv->specifier = 'x';
     eaa:	2378      	movs	r3, #120	; 0x78
     eac:	f88d 3023 	strb.w	r3, [sp, #35]	; 0x23
		char sign = 0;
     eb0:	f8dd 9008 	ldr.w	r9, [sp, #8]
				goto prec_int_pad0;
     eb4:	e7ca      	b.n	e4c <CONFIG_ISR_STACK_SIZE+0x64c>

			break;
		case 'n':
			if (IS_ENABLED(CONFIG_CBPRINTF_N_SPECIFIER)) {
				store_count(conv, value->ptr, count);
     eb6:	9a06      	ldr	r2, [sp, #24]
	switch ((enum length_mod_enum)conv->length_mod) {
     eb8:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     ebc:	f3c3 03c3 	ubfx	r3, r3, #3, #4
     ec0:	2b07      	cmp	r3, #7
     ec2:	d806      	bhi.n	ed2 <CONFIG_ISR_STACK_SIZE+0x6d2>
     ec4:	e8df f003 	tbb	[pc, r3]
     ec8:	100e0c04 	.word	0x100e0c04
     ecc:	1e1c1712 	.word	0x1e1c1712
		*(int *)dp = count;
     ed0:	6014      	str	r4, [r2, #0]
		char sign = 0;
     ed2:	f8dd 9008 	ldr.w	r9, [sp, #8]
		const char *bpe = buf + sizeof(buf);
     ed6:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
		const char *bps = NULL;
     eda:	f04f 0a00 	mov.w	sl, #0
}
     ede:	e019      	b.n	f14 <CONFIG_ISR_STACK_SIZE+0x714>
		*(signed char *)dp = (signed char)count;
     ee0:	7014      	strb	r4, [r2, #0]
		break;
     ee2:	e7f6      	b.n	ed2 <CONFIG_ISR_STACK_SIZE+0x6d2>
		*(short *)dp = (short)count;
     ee4:	8014      	strh	r4, [r2, #0]
		break;
     ee6:	e7f4      	b.n	ed2 <CONFIG_ISR_STACK_SIZE+0x6d2>
		*(long *)dp = (long)count;
     ee8:	6014      	str	r4, [r2, #0]
		break;
     eea:	e7f2      	b.n	ed2 <CONFIG_ISR_STACK_SIZE+0x6d2>
		*(long long *)dp = (long long)count;
     eec:	4620      	mov	r0, r4
     eee:	17e1      	asrs	r1, r4, #31
     ef0:	e9c2 0100 	strd	r0, r1, [r2]
		break;
     ef4:	e7ed      	b.n	ed2 <CONFIG_ISR_STACK_SIZE+0x6d2>
		*(intmax_t *)dp = (intmax_t)count;
     ef6:	4620      	mov	r0, r4
     ef8:	17e1      	asrs	r1, r4, #31
     efa:	e9c2 0100 	strd	r0, r1, [r2]
		break;
     efe:	e7e8      	b.n	ed2 <CONFIG_ISR_STACK_SIZE+0x6d2>
		*(size_t *)dp = (size_t)count;
     f00:	6014      	str	r4, [r2, #0]
		break;
     f02:	e7e6      	b.n	ed2 <CONFIG_ISR_STACK_SIZE+0x6d2>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
     f04:	6014      	str	r4, [r2, #0]
		break;
     f06:	e7e4      	b.n	ed2 <CONFIG_ISR_STACK_SIZE+0x6d2>
		switch (conv->specifier) {
     f08:	f8dd 9008 	ldr.w	r9, [sp, #8]
     f0c:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
     f10:	f04f 0a00 	mov.w	sl, #0
		}

		/* If we don't have a converted value to emit, move
		 * on.
		 */
		if (bps == NULL) {
     f14:	f1ba 0f00 	cmp.w	sl, #0
     f18:	f000 808e 	beq.w	1038 <CONFIG_FPROTECT_BLOCK_SIZE+0x38>
		 *   * any exponent content from the converted value
		 * * for non-FP:
		 *   * any pad0_prefix
		 *   * the converted value
		 */
		size_t nj_len = (bpe - bps);
     f1c:	ebab 020a 	sub.w	r2, fp, sl
		int pad_len = 0;

		if (sign != 0) {
     f20:	f1b9 0f00 	cmp.w	r9, #0
     f24:	d000      	beq.n	f28 <CONFIG_ISR_STACK_SIZE+0x728>
			nj_len += 1U;
     f26:	3201      	adds	r2, #1
		}

		if (conv->altform_0c) {
     f28:	f89d 1022 	ldrb.w	r1, [sp, #34]	; 0x22
     f2c:	f011 0f10 	tst.w	r1, #16
     f30:	d026      	beq.n	f80 <CONFIG_ISR_STACK_SIZE+0x780>
			nj_len += 2U;
     f32:	3202      	adds	r2, #2
		} else if (conv->altform_0) {
			nj_len += 1U;
		}

		nj_len += conv->pad0_value;
     f34:	9b09      	ldr	r3, [sp, #36]	; 0x24
     f36:	4413      	add	r3, r2
		if (conv->pad_fp) {
     f38:	f011 0f40 	tst.w	r1, #64	; 0x40
     f3c:	d001      	beq.n	f42 <CONFIG_ISR_STACK_SIZE+0x742>
			nj_len += conv->pad0_pre_exp;
     f3e:	9a0a      	ldr	r2, [sp, #40]	; 0x28
     f40:	4413      	add	r3, r2
		 * result in no padding.
		 *
		 * If a non-negative padding width is present and we're doing
		 * right-justification, emit the padding now.
		 */
		if (width > 0) {
     f42:	2f00      	cmp	r7, #0
     f44:	dd32      	ble.n	fac <CONFIG_ISR_STACK_SIZE+0x7ac>
			width -= (int)nj_len;
     f46:	1aff      	subs	r7, r7, r3

			if (!conv->flag_dash) {
     f48:	f89d 3020 	ldrb.w	r3, [sp, #32]
     f4c:	f013 0f04 	tst.w	r3, #4
     f50:	d12c      	bne.n	fac <CONFIG_ISR_STACK_SIZE+0x7ac>
				char pad = ' ';

				/* If we're zero-padding we have to emit the
				 * sign first.
				 */
				if (conv->flag_zero) {
     f52:	f013 0f40 	tst.w	r3, #64	; 0x40
     f56:	d018      	beq.n	f8a <CONFIG_ISR_STACK_SIZE+0x78a>
					if (sign != 0) {
     f58:	f1b9 0f00 	cmp.w	r9, #0
     f5c:	d018      	beq.n	f90 <CONFIG_ISR_STACK_SIZE+0x790>
						OUTC(sign);
     f5e:	4629      	mov	r1, r5
     f60:	4648      	mov	r0, r9
     f62:	47b0      	blx	r6
     f64:	2800      	cmp	r0, #0
     f66:	db6b      	blt.n	1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>
     f68:	3401      	adds	r4, #1
						sign = 0;
     f6a:	f8dd 9008 	ldr.w	r9, [sp, #8]
					}
					pad = '0';
     f6e:	2330      	movs	r3, #48	; 0x30
     f70:	9302      	str	r3, [sp, #8]
     f72:	e00f      	b.n	f94 <CONFIG_ISR_STACK_SIZE+0x794>
		const char *bpe = buf + sizeof(buf);
     f74:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
     f78:	e7cc      	b.n	f14 <CONFIG_ISR_STACK_SIZE+0x714>
     f7a:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
     f7e:	e7c9      	b.n	f14 <CONFIG_ISR_STACK_SIZE+0x714>
		} else if (conv->altform_0) {
     f80:	f011 0f08 	tst.w	r1, #8
     f84:	d0d6      	beq.n	f34 <CONFIG_ISR_STACK_SIZE+0x734>
			nj_len += 1U;
     f86:	3201      	adds	r2, #1
     f88:	e7d4      	b.n	f34 <CONFIG_ISR_STACK_SIZE+0x734>
				char pad = ' ';
     f8a:	2320      	movs	r3, #32
     f8c:	9302      	str	r3, [sp, #8]
     f8e:	e001      	b.n	f94 <CONFIG_ISR_STACK_SIZE+0x794>
					pad = '0';
     f90:	2330      	movs	r3, #48	; 0x30
     f92:	9302      	str	r3, [sp, #8]
     f94:	463b      	mov	r3, r7
				}

				while (width-- > 0) {
     f96:	1e5f      	subs	r7, r3, #1
     f98:	2b00      	cmp	r3, #0
     f9a:	dd07      	ble.n	fac <CONFIG_ISR_STACK_SIZE+0x7ac>
					OUTC(pad);
     f9c:	4629      	mov	r1, r5
     f9e:	9802      	ldr	r0, [sp, #8]
     fa0:	47b0      	blx	r6
     fa2:	2800      	cmp	r0, #0
     fa4:	db4c      	blt.n	1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>
     fa6:	3401      	adds	r4, #1
				while (width-- > 0) {
     fa8:	463b      	mov	r3, r7
     faa:	e7f4      	b.n	f96 <CONFIG_ISR_STACK_SIZE+0x796>
		}

		/* If we have a sign that hasn't been emitted, now's the
		 * time....
		 */
		if (sign != 0) {
     fac:	f1b9 0f00 	cmp.w	r9, #0
     fb0:	d005      	beq.n	fbe <CONFIG_ISR_STACK_SIZE+0x7be>
			OUTC(sign);
     fb2:	4629      	mov	r1, r5
     fb4:	4648      	mov	r0, r9
     fb6:	47b0      	blx	r6
     fb8:	2800      	cmp	r0, #0
     fba:	db41      	blt.n	1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>
     fbc:	3401      	adds	r4, #1
				OUTC('0');
			}

			OUTS(cp, bpe);
		} else {
			if (conv->altform_0c | conv->altform_0) {
     fbe:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     fc2:	f3c3 1200 	ubfx	r2, r3, #4, #1
     fc6:	f3c3 03c0 	ubfx	r3, r3, #3, #1
     fca:	4313      	orrs	r3, r2
     fcc:	d005      	beq.n	fda <CONFIG_ISR_STACK_SIZE+0x7da>
				OUTC('0');
     fce:	4629      	mov	r1, r5
     fd0:	2030      	movs	r0, #48	; 0x30
     fd2:	47b0      	blx	r6
     fd4:	2800      	cmp	r0, #0
     fd6:	db33      	blt.n	1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>
     fd8:	3401      	adds	r4, #1
			}

			if (conv->altform_0c) {
     fda:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     fde:	f013 0f10 	tst.w	r3, #16
     fe2:	d006      	beq.n	ff2 <CONFIG_ISR_STACK_SIZE+0x7f2>
				OUTC(conv->specifier);
     fe4:	4629      	mov	r1, r5
     fe6:	f89d 0023 	ldrb.w	r0, [sp, #35]	; 0x23
     fea:	47b0      	blx	r6
     fec:	2800      	cmp	r0, #0
     fee:	db27      	blt.n	1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>
     ff0:	3401      	adds	r4, #1
			}

			pad_len = conv->pad0_value;
     ff2:	9b09      	ldr	r3, [sp, #36]	; 0x24
			while (pad_len-- > 0) {
     ff4:	f103 39ff 	add.w	r9, r3, #4294967295
     ff8:	2b00      	cmp	r3, #0
     ffa:	dd07      	ble.n	100c <CONFIG_FPROTECT_BLOCK_SIZE+0xc>
				OUTC('0');
     ffc:	4629      	mov	r1, r5
     ffe:	2030      	movs	r0, #48	; 0x30
    1000:	47b0      	blx	r6
    1002:	2800      	cmp	r0, #0
    1004:	db1c      	blt.n	1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>
    1006:	3401      	adds	r4, #1
			while (pad_len-- > 0) {
    1008:	464b      	mov	r3, r9
    100a:	e7f3      	b.n	ff4 <CONFIG_ISR_STACK_SIZE+0x7f4>
			}

			OUTS(bps, bpe);
    100c:	465b      	mov	r3, fp
    100e:	4652      	mov	r2, sl
    1010:	4629      	mov	r1, r5
    1012:	4630      	mov	r0, r6
    1014:	f004 fec8 	bl	5da8 <outs>
    1018:	2800      	cmp	r0, #0
    101a:	db11      	blt.n	1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>
    101c:	4404      	add	r4, r0
		}

		/* Finish left justification */
		while (width > 0) {
    101e:	2f00      	cmp	r7, #0
    1020:	dd07      	ble.n	1032 <CONFIG_FPROTECT_BLOCK_SIZE+0x32>
			OUTC(' ');
    1022:	4629      	mov	r1, r5
    1024:	2020      	movs	r0, #32
    1026:	47b0      	blx	r6
    1028:	2800      	cmp	r0, #0
    102a:	db09      	blt.n	1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>
    102c:	3401      	adds	r4, #1
			--width;
    102e:	3f01      	subs	r7, #1
    1030:	e7f5      	b.n	101e <CONFIG_FPROTECT_BLOCK_SIZE+0x1e>
		fp = extract_conversion(conv, sp);
    1032:	46c2      	mov	sl, r8
    1034:	f7ff bb28 	b.w	688 <cbvprintf+0x10>
    1038:	46c2      	mov	sl, r8
    103a:	f7ff bb25 	b.w	688 <cbvprintf+0x10>
		}
	}

	return count;
    103e:	4620      	mov	r0, r4
#undef OUTS
#undef OUTC
}
    1040:	b013      	add	sp, #76	; 0x4c
    1042:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    1046:	bf00      	nop
    1048:	00007799 	.word	0x00007799

0000104c <pm_system_resume>:
	 * and it may schedule another thread.
	 *
	 * Call pm_idle_exit_notification_disable() if this
	 * notification is not required.
	 */
	if (!post_ops_done) {
    104c:	4b1b      	ldr	r3, [pc, #108]	; (10bc <pm_system_resume+0x70>)
    104e:	681b      	ldr	r3, [r3, #0]
    1050:	2b00      	cmp	r3, #0
    1052:	d132      	bne.n	10ba <pm_system_resume+0x6e>
{
    1054:	b530      	push	{r4, r5, lr}
    1056:	b085      	sub	sp, #20
		post_ops_done = 1;
    1058:	4b18      	ldr	r3, [pc, #96]	; (10bc <pm_system_resume+0x70>)
    105a:	2201      	movs	r2, #1
    105c:	601a      	str	r2, [r3, #0]
		exit_pos_ops(z_power_state);
    105e:	4b18      	ldr	r3, [pc, #96]	; (10c0 <pm_system_resume+0x74>)
    1060:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
    1064:	ab04      	add	r3, sp, #16
    1066:	e903 0007 	stmdb	r3, {r0, r1, r2}
	if (pm_power_state_exit_post_ops != NULL) {
    106a:	4b16      	ldr	r3, [pc, #88]	; (10c4 <pm_system_resume+0x78>)
    106c:	b163      	cbz	r3, 1088 <pm_system_resume+0x3c>
		pm_power_state_exit_post_ops(info);
    106e:	f004 fffa 	bl	6066 <pm_power_state_exit_post_ops>
    1072:	f04f 0320 	mov.w	r3, #32
    1076:	f3ef 8511 	mrs	r5, BASEPRI
    107a:	f383 8812 	msr	BASEPRI_MAX, r3
    107e:	f3bf 8f6f 	isb	sy
    1082:	4b11      	ldr	r3, [pc, #68]	; (10c8 <pm_system_resume+0x7c>)
    1084:	681c      	ldr	r4, [r3, #0]
    1086:	e00a      	b.n	109e <pm_system_resume+0x52>
	__asm__ volatile(
    1088:	2300      	movs	r3, #0
    108a:	f383 8811 	msr	BASEPRI, r3
    108e:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    1092:	e7ee      	b.n	1072 <pm_system_resume+0x26>
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    1094:	4623      	mov	r3, r4
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next(sys_snode_t *node);

Z_GENLIST_PEEK_NEXT(slist, snode)
    1096:	b10c      	cbz	r4, 109c <pm_system_resume+0x50>
	return node->next;
    1098:	6823      	ldr	r3, [r4, #0]
    109a:	b143      	cbz	r3, 10ae <pm_system_resume+0x62>
{
    109c:	461c      	mov	r4, r3
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    109e:	b134      	cbz	r4, 10ae <pm_system_resume+0x62>
			callback = notifier->state_exit;
    10a0:	68a3      	ldr	r3, [r4, #8]
		if (callback) {
    10a2:	2b00      	cmp	r3, #0
    10a4:	d0f6      	beq.n	1094 <pm_system_resume+0x48>
			callback(z_power_state.state);
    10a6:	4a06      	ldr	r2, [pc, #24]	; (10c0 <pm_system_resume+0x74>)
    10a8:	7810      	ldrb	r0, [r2, #0]
    10aa:	4798      	blx	r3
    10ac:	e7f2      	b.n	1094 <pm_system_resume+0x48>
	__asm__ volatile(
    10ae:	f385 8811 	msr	BASEPRI, r5
    10b2:	f3bf 8f6f 	isb	sy
		pm_state_notify(false);
	}
}
    10b6:	b005      	add	sp, #20
    10b8:	bd30      	pop	{r4, r5, pc}
    10ba:	4770      	bx	lr
    10bc:	20000004 	.word	0x20000004
    10c0:	20000440 	.word	0x20000440
    10c4:	00006067 	.word	0x00006067
    10c8:	20000438 	.word	0x20000438

000010cc <pm_system_suspend>:
	return PM_STATE_ACTIVE;
}
#endif

enum pm_state pm_system_suspend(int32_t ticks)
{
    10cc:	b570      	push	{r4, r5, r6, lr}
    10ce:	b088      	sub	sp, #32
    10d0:	4606      	mov	r6, r0
	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);
	z_power_state = pm_policy_next_state(ticks);
    10d2:	4c2a      	ldr	r4, [pc, #168]	; (117c <pm_system_suspend+0xb0>)
    10d4:	466d      	mov	r5, sp
    10d6:	4601      	mov	r1, r0
    10d8:	4628      	mov	r0, r5
    10da:	f004 fe80 	bl	5dde <pm_policy_next_state>
    10de:	e895 0007 	ldmia.w	r5, {r0, r1, r2}
    10e2:	e884 0007 	stmia.w	r4, {r0, r1, r2}
	if (z_power_state.state == PM_STATE_ACTIVE) {
    10e6:	7820      	ldrb	r0, [r4, #0]
    10e8:	2800      	cmp	r0, #0
    10ea:	d045      	beq.n	1178 <pm_system_suspend+0xac>
		LOG_DBG("No PM operations done.");
		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks, z_power_state.state);
		return z_power_state.state;
	}
	post_ops_done = 0;
    10ec:	4b24      	ldr	r3, [pc, #144]	; (1180 <pm_system_suspend+0xb4>)
    10ee:	2200      	movs	r2, #0
    10f0:	601a      	str	r2, [r3, #0]

	if (ticks != K_TICKS_FOREVER) {
    10f2:	f1b6 3fff 	cmp.w	r6, #4294967295
    10f6:	d10c      	bne.n	1112 <pm_system_suspend+0x46>
	 * state. We don't want to be scheduled out yet, first we need
	 * to send a notification about leaving the idle state. So,
	 * we lock the scheduler here and unlock just after we have
	 * sent the notification in pm_system_resume().
	 */
	k_sched_lock();
    10f8:	f003 fafe 	bl	46f8 <k_sched_lock>
	__asm__ volatile(
    10fc:	f04f 0320 	mov.w	r3, #32
    1100:	f3ef 8511 	mrs	r5, BASEPRI
    1104:	f383 8812 	msr	BASEPRI_MAX, r3
    1108:	f3bf 8f6f 	isb	sy
	return list->head;
    110c:	4b1d      	ldr	r3, [pc, #116]	; (1184 <pm_system_suspend+0xb8>)
    110e:	681c      	ldr	r4, [r3, #0]
    1110:	e016      	b.n	1140 <pm_system_suspend+0x74>
		     k_us_to_ticks_ceil32(z_power_state.exit_latency_us), true);
    1112:	68a3      	ldr	r3, [r4, #8]
		} else {
			return t * ((uint64_t)to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    1114:	0c59      	lsrs	r1, r3, #17
    1116:	03d8      	lsls	r0, r3, #15
    1118:	4c1b      	ldr	r4, [pc, #108]	; (1188 <pm_system_suspend+0xbc>)
    111a:	4a1c      	ldr	r2, [pc, #112]	; (118c <pm_system_suspend+0xc0>)
    111c:	2300      	movs	r3, #0
    111e:	1900      	adds	r0, r0, r4
    1120:	f04f 0400 	mov.w	r4, #0
    1124:	eb44 0101 	adc.w	r1, r4, r1
    1128:	f7fe ffea 	bl	100 <__aeabi_uldivmod>
		z_set_timeout_expiry(ticks -
    112c:	2101      	movs	r1, #1
    112e:	1a30      	subs	r0, r6, r0
    1130:	f006 f890 	bl	7254 <z_set_timeout_expiry>
    1134:	e7e0      	b.n	10f8 <pm_system_suspend+0x2c>
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    1136:	4623      	mov	r3, r4
Z_GENLIST_PEEK_NEXT(slist, snode)
    1138:	b10c      	cbz	r4, 113e <pm_system_suspend+0x72>
	return node->next;
    113a:	6823      	ldr	r3, [r4, #0]
    113c:	b143      	cbz	r3, 1150 <pm_system_suspend+0x84>
{
    113e:	461c      	mov	r4, r3
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    1140:	b134      	cbz	r4, 1150 <pm_system_suspend+0x84>
			callback = notifier->state_entry;
    1142:	6863      	ldr	r3, [r4, #4]
		if (callback) {
    1144:	2b00      	cmp	r3, #0
    1146:	d0f6      	beq.n	1136 <pm_system_suspend+0x6a>
			callback(z_power_state.state);
    1148:	4a0c      	ldr	r2, [pc, #48]	; (117c <pm_system_suspend+0xb0>)
    114a:	7810      	ldrb	r0, [r2, #0]
    114c:	4798      	blx	r3
    114e:	e7f2      	b.n	1136 <pm_system_suspend+0x6a>
	__asm__ volatile(
    1150:	f385 8811 	msr	BASEPRI, r5
    1154:	f3bf 8f6f 	isb	sy
	pm_debug_start_timer();
	/* Enter power state */
	pm_state_notify(true);
	pm_state_set(z_power_state);
    1158:	4b08      	ldr	r3, [pc, #32]	; (117c <pm_system_suspend+0xb0>)
    115a:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
    115e:	ab08      	add	r3, sp, #32
    1160:	e903 0007 	stmdb	r3, {r0, r1, r2}
	if (pm_power_state_set != NULL) {
    1164:	4b0a      	ldr	r3, [pc, #40]	; (1190 <pm_system_suspend+0xc4>)
    1166:	b10b      	cbz	r3, 116c <pm_system_suspend+0xa0>
		pm_power_state_set(info);
    1168:	f004 ff6a 	bl	6040 <pm_power_state_set>
		/* Turn on peripherals and restore device states as necessary */
		pm_resume_devices();
	}
#endif
	pm_log_debug_info(z_power_state.state);
	pm_system_resume();
    116c:	f7ff ff6e 	bl	104c <pm_system_resume>
	k_sched_unlock();
    1170:	f003 fc60 	bl	4a34 <k_sched_unlock>
	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks, z_power_state.state);
	return z_power_state.state;
    1174:	4b01      	ldr	r3, [pc, #4]	; (117c <pm_system_suspend+0xb0>)
    1176:	7818      	ldrb	r0, [r3, #0]
}
    1178:	b008      	add	sp, #32
    117a:	bd70      	pop	{r4, r5, r6, pc}
    117c:	20000440 	.word	0x20000440
    1180:	20000004 	.word	0x20000004
    1184:	20000438 	.word	0x20000438
    1188:	000f423f 	.word	0x000f423f
    118c:	000f4240 	.word	0x000f4240
    1190:	00006041 	.word	0x00006041

00001194 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    1194:	4901      	ldr	r1, [pc, #4]	; (119c <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    1196:	2210      	movs	r2, #16
	str	r2, [r1]
    1198:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    119a:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    119c:	e000ed10 	.word	0xe000ed10

000011a0 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    11a0:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    11a2:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    11a4:	f380 8811 	msr	BASEPRI, r0
	isb
    11a8:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    11ac:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    11b0:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    11b2:	b662      	cpsie	i
	isb
    11b4:	f3bf 8f6f 	isb	sy

	bx	lr
    11b8:	4770      	bx	lr
    11ba:	bf00      	nop

000011bc <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    11bc:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    11be:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    11c0:	f381 8811 	msr	BASEPRI, r1

	wfe
    11c4:	bf20      	wfe

	msr	BASEPRI, r0
    11c6:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    11ca:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    11cc:	4770      	bx	lr
    11ce:	bf00      	nop

000011d0 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    11d0:	b243      	sxtb	r3, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    11d2:	2b00      	cmp	r3, #0
    11d4:	db08      	blt.n	11e8 <arch_irq_enable+0x18>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    11d6:	f000 001f 	and.w	r0, r0, #31
    11da:	095b      	lsrs	r3, r3, #5
    11dc:	2201      	movs	r2, #1
    11de:	fa02 f000 	lsl.w	r0, r2, r0
    11e2:	4a02      	ldr	r2, [pc, #8]	; (11ec <arch_irq_enable+0x1c>)
    11e4:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    11e8:	4770      	bx	lr
    11ea:	bf00      	nop
    11ec:	e000e100 	.word	0xe000e100

000011f0 <arch_irq_disable>:

void arch_irq_disable(unsigned int irq)
{
	NVIC_DisableIRQ((IRQn_Type)irq);
    11f0:	b243      	sxtb	r3, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    11f2:	2b00      	cmp	r3, #0
    11f4:	db0d      	blt.n	1212 <arch_irq_disable+0x22>
  {
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    11f6:	f000 001f 	and.w	r0, r0, #31
    11fa:	095b      	lsrs	r3, r3, #5
    11fc:	2201      	movs	r2, #1
    11fe:	fa02 f000 	lsl.w	r0, r2, r0
    1202:	3320      	adds	r3, #32
    1204:	4a03      	ldr	r2, [pc, #12]	; (1214 <arch_irq_disable+0x24>)
    1206:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    120a:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    120e:	f3bf 8f6f 	isb	sy
}
    1212:	4770      	bx	lr
    1214:	e000e100 	.word	0xe000e100

00001218 <arch_irq_is_enabled>:

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    1218:	0942      	lsrs	r2, r0, #5
    121a:	4b05      	ldr	r3, [pc, #20]	; (1230 <arch_irq_is_enabled+0x18>)
    121c:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    1220:	f000 001f 	and.w	r0, r0, #31
    1224:	2301      	movs	r3, #1
    1226:	fa03 f000 	lsl.w	r0, r3, r0
}
    122a:	4010      	ands	r0, r2
    122c:	4770      	bx	lr
    122e:	bf00      	nop
    1230:	e000e100 	.word	0xe000e100

00001234 <z_arm_irq_priority_set>:
	 * via flags
	 */
	if (IS_ENABLED(CONFIG_ZERO_LATENCY_IRQS) && (flags & IRQ_ZERO_LATENCY)) {
		prio = _EXC_ZERO_LATENCY_IRQS_PRIO;
	} else {
		prio += _IRQ_PRIO_OFFSET;
    1234:	3101      	adds	r1, #1
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    1236:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    1238:	2b00      	cmp	r3, #0
    123a:	db08      	blt.n	124e <z_arm_irq_priority_set+0x1a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    123c:	0149      	lsls	r1, r1, #5
    123e:	b2c9      	uxtb	r1, r1
    1240:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    1244:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    1248:	f883 1300 	strb.w	r1, [r3, #768]	; 0x300
    124c:	4770      	bx	lr
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    124e:	f000 000f 	and.w	r0, r0, #15
    1252:	0149      	lsls	r1, r1, #5
    1254:	b2c9      	uxtb	r1, r1
    1256:	4b01      	ldr	r3, [pc, #4]	; (125c <z_arm_irq_priority_set+0x28>)
    1258:	5419      	strb	r1, [r3, r0]
}
    125a:	4770      	bx	lr
    125c:	e000ed14 	.word	0xe000ed14

00001260 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    1260:	bf30      	wfi
    b z_SysNmiOnReset
    1262:	f7ff bffd 	b.w	1260 <z_SysNmiOnReset>
    1266:	bf00      	nop

00001268 <z_arm_prep_c>:
 * This routine prepares for the execution of and runs C code.
 *
 * @return N/A
 */
void z_arm_prep_c(void)
{
    1268:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    126a:	4b0b      	ldr	r3, [pc, #44]	; (1298 <z_arm_prep_c+0x30>)
    126c:	4a0b      	ldr	r2, [pc, #44]	; (129c <z_arm_prep_c+0x34>)
    126e:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    1272:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    1274:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1278:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    127c:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    1280:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    1284:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    1288:	f003 f814 	bl	42b4 <z_bss_zero>
	z_data_copy();
    128c:	f003 fd64 	bl	4d58 <z_data_copy>
#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    1290:	f000 fa12 	bl	16b8 <z_arm_interrupt_init>
	z_cstart();
    1294:	f003 f81a 	bl	42cc <z_cstart>
    1298:	e000ed00 	.word	0xe000ed00
    129c:	00000000 	.word	0x00000000

000012a0 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    12a0:	4a0a      	ldr	r2, [pc, #40]	; (12cc <arch_swap+0x2c>)
    12a2:	6893      	ldr	r3, [r2, #8]
    12a4:	f8c3 00ac 	str.w	r0, [r3, #172]	; 0xac
	_current->arch.swap_return_value = _k_neg_eagain;
    12a8:	4909      	ldr	r1, [pc, #36]	; (12d0 <arch_swap+0x30>)
    12aa:	6809      	ldr	r1, [r1, #0]
    12ac:	f8c3 10b0 	str.w	r1, [r3, #176]	; 0xb0

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    12b0:	4908      	ldr	r1, [pc, #32]	; (12d4 <arch_swap+0x34>)
    12b2:	684b      	ldr	r3, [r1, #4]
    12b4:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    12b8:	604b      	str	r3, [r1, #4]
    12ba:	2300      	movs	r3, #0
    12bc:	f383 8811 	msr	BASEPRI, r3
    12c0:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    12c4:	6893      	ldr	r3, [r2, #8]
}
    12c6:	f8d3 00b0 	ldr.w	r0, [r3, #176]	; 0xb0
    12ca:	4770      	bx	lr
    12cc:	20000a9c 	.word	0x20000a9c
    12d0:	00007964 	.word	0x00007964
    12d4:	e000ed00 	.word	0xe000ed00

000012d8 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    12d8:	4913      	ldr	r1, [pc, #76]	; (1328 <z_arm_pendsv+0x50>)
    ldr r2, [r1, #_kernel_offset_to_current]
    12da:	688a      	ldr	r2, [r1, #8]
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    12dc:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    12e0:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    12e2:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    12e6:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    12ea:	2020      	movs	r0, #32
    msr BASEPRI_MAX, r0
    12ec:	f380 8812 	msr	BASEPRI_MAX, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    12f0:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    12f4:	4f0d      	ldr	r7, [pc, #52]	; (132c <z_arm_pendsv+0x54>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    12f6:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    12fa:	69ca      	ldr	r2, [r1, #28]

    str r2, [r1, #_kernel_offset_to_current]
    12fc:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    12fe:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    1300:	f8d2 00ac 	ldr.w	r0, [r2, #172]	; 0xac
    movs r3, #0
    1304:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    1306:	f8c2 30ac 	str.w	r3, [r2, #172]	; 0xac
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    130a:	f380 8811 	msr	BASEPRI, r0
    isb
#endif

#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
    /* Re-program dynamic memory map */
    push {r2,lr}
    130e:	b504      	push	{r2, lr}
    mov r0, r2 /* _current thread */
    1310:	4610      	mov	r0, r2
    bl z_arm_configure_dynamic_mpu_regions
    1312:	f000 fa73 	bl	17fc <z_arm_configure_dynamic_mpu_regions>
    pop {r2,lr}
    1316:	e8bd 4004 	ldmia.w	sp!, {r2, lr}
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    131a:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    131e:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    1322:	f38c 8809 	msr	PSP, ip

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    1326:	4770      	bx	lr
    ldr r1, =_kernel
    1328:	20000a9c 	.word	0x20000a9c
    ldr v4, =_SCS_ICSR
    132c:	e000ed04 	.word	0xe000ed04

00001330 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    1330:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    1334:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    1336:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    133a:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    133e:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    1340:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    1344:	2902      	cmp	r1, #2
    beq _oops
    1346:	d0ff      	beq.n	1348 <_oops>

00001348 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    1348:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    134a:	f004 fd51 	bl	5df0 <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    134e:	bd01      	pop	{r0, pc}

00001350 <arch_new_thread>:
 * of the ESF.
 */
void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
		     char *stack_ptr, k_thread_entry_t entry,
		     void *p1, void *p2, void *p3)
{
    1350:	b410      	push	{r4}
		thread->stack_info.size -= FP_GUARD_EXTRA_SIZE;
	}
#endif /* FP_GUARD_EXTRA_SIZE */
#endif /* CONFIG_MPU_STACK_GUARD */

	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    1352:	f1a2 0420 	sub.w	r4, r2, #32
		iframe->pc = (uint32_t)arch_user_mode_enter;
	} else {
		iframe->pc = (uint32_t)z_thread_entry;
	}
#else
	iframe->pc = (uint32_t)z_thread_entry;
    1356:	490d      	ldr	r1, [pc, #52]	; (138c <arch_new_thread+0x3c>)
#endif

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
    1358:	f021 0101 	bic.w	r1, r1, #1
    135c:	f842 1c08 	str.w	r1, [r2, #-8]
#endif
	iframe->a1 = (uint32_t)entry;
    1360:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    1364:	9b01      	ldr	r3, [sp, #4]
    1366:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->a3 = (uint32_t)p2;
    136a:	9b02      	ldr	r3, [sp, #8]
    136c:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    1370:	9b03      	ldr	r3, [sp, #12]
    1372:	f842 3c14 	str.w	r3, [r2, #-20]

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    1376:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    137a:	f842 3c04 	str.w	r3, [r2, #-4]
#if defined(CONFIG_COMPILER_ISA_THUMB2)
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
    137e:	6504      	str	r4, [r0, #80]	; 0x50
	thread->arch.basepri = 0;
    1380:	2300      	movs	r3, #0
    1382:	f8c0 30ac 	str.w	r3, [r0, #172]	; 0xac
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    1386:	bc10      	pop	{r4}
    1388:	4770      	bx	lr
    138a:	bf00      	nop
    138c:	00005c9b 	.word	0x00005c9b

00001390 <z_check_thread_stack_fail>:
 *         thread stack corruption, otherwise return 0.
 */
uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp)
{
#if defined(CONFIG_MULTITHREADING)
	const struct k_thread *thread = _current;
    1390:	4b16      	ldr	r3, [pc, #88]	; (13ec <z_check_thread_stack_fail+0x5c>)
    1392:	689a      	ldr	r2, [r3, #8]

	if (thread == NULL) {
    1394:	b1da      	cbz	r2, 13ce <z_check_thread_stack_fail+0x3e>
			return thread->stack_info.start;
		}
	}
#else /* CONFIG_USERSPACE */
#if defined(CONFIG_MULTITHREADING)
	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
    1396:	f110 0f16 	cmn.w	r0, #22
    139a:	d01a      	beq.n	13d2 <z_check_thread_stack_fail+0x42>
{
    139c:	b410      	push	{r4}
	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
    139e:	f8d2 309c 	ldr.w	r3, [r2, #156]	; 0x9c
    13a2:	f1a3 0420 	sub.w	r4, r3, #32
    13a6:	4284      	cmp	r4, r0
    13a8:	d805      	bhi.n	13b6 <z_check_thread_stack_fail+0x26>
    13aa:	4283      	cmp	r3, r0
    13ac:	d908      	bls.n	13c0 <z_check_thread_stack_fail+0x30>
    13ae:	428b      	cmp	r3, r1
    13b0:	d808      	bhi.n	13c4 <z_check_thread_stack_fail+0x34>
    13b2:	2100      	movs	r1, #0
    13b4:	e000      	b.n	13b8 <z_check_thread_stack_fail+0x28>
    13b6:	2100      	movs	r1, #0
    13b8:	b931      	cbnz	r1, 13c8 <z_check_thread_stack_fail+0x38>
		return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack);
	}
#endif
#endif /* CONFIG_USERSPACE */

	return 0;
    13ba:	2000      	movs	r0, #0
}
    13bc:	bc10      	pop	{r4}
    13be:	4770      	bx	lr
	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
    13c0:	2100      	movs	r1, #0
    13c2:	e7f9      	b.n	13b8 <z_check_thread_stack_fail+0x28>
    13c4:	2101      	movs	r1, #1
    13c6:	e7f7      	b.n	13b8 <z_check_thread_stack_fail+0x28>
		return thread->stack_info.start;
    13c8:	f8d2 009c 	ldr.w	r0, [r2, #156]	; 0x9c
    13cc:	e7f6      	b.n	13bc <z_check_thread_stack_fail+0x2c>
		return 0;
    13ce:	2000      	movs	r0, #0
    13d0:	4770      	bx	lr
	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
    13d2:	f8d2 309c 	ldr.w	r3, [r2, #156]	; 0x9c
    13d6:	428b      	cmp	r3, r1
    13d8:	bf94      	ite	ls
    13da:	2100      	movls	r1, #0
    13dc:	2101      	movhi	r1, #1
    13de:	b909      	cbnz	r1, 13e4 <z_check_thread_stack_fail+0x54>
	return 0;
    13e0:	2000      	movs	r0, #0
}
    13e2:	4770      	bx	lr
		return thread->stack_info.start;
    13e4:	f8d2 009c 	ldr.w	r0, [r2, #156]	; 0x9c
    13e8:	4770      	bx	lr
    13ea:	bf00      	nop
    13ec:	20000a9c 	.word	0x20000a9c

000013f0 <arch_switch_to_main_thread>:
#endif /* CONFIG_FPU */
}

void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
    13f0:	b508      	push	{r3, lr}
    13f2:	460d      	mov	r5, r1
    13f4:	4614      	mov	r4, r2
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    13f6:	4b08      	ldr	r3, [pc, #32]	; (1418 <arch_switch_to_main_thread+0x28>)
    13f8:	6098      	str	r0, [r3, #8]
#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
	/*
	 * If stack protection is enabled, make sure to set it
	 * before jumping to thread entry function
	 */
	z_arm_configure_dynamic_mpu_regions(main_thread);
    13fa:	f000 f9ff 	bl	17fc <z_arm_configure_dynamic_mpu_regions>

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    13fe:	4620      	mov	r0, r4
    1400:	f385 8809 	msr	PSP, r5
    1404:	2100      	movs	r1, #0
    1406:	b663      	cpsie	if
    1408:	f381 8811 	msr	BASEPRI, r1
    140c:	f3bf 8f6f 	isb	sy
    1410:	2200      	movs	r2, #0
    1412:	2300      	movs	r3, #0
    1414:	f004 fc41 	bl	5c9a <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    1418:	20000a9c 	.word	0x20000a9c

0000141c <_isr_wrapper>:
 * @return N/A
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    141c:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    141e:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    1420:	4a0b      	ldr	r2, [pc, #44]	; (1450 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    1422:	6990      	ldr	r0, [r2, #24]
	cmp r0, #0
    1424:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    1426:	bf1e      	ittt	ne
	movne	r1, #0
    1428:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    142a:	6191      	strne	r1, [r2, #24]
		blne	z_pm_save_idle_exit
    142c:	f005 fd63 	blne	6ef6 <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    1430:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    1432:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    1436:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    143a:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    143e:	4905      	ldr	r1, [pc, #20]	; (1454 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    1440:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    1442:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    1444:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    1446:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    144a:	4903      	ldr	r1, [pc, #12]	; (1458 <_isr_wrapper+0x3c>)
	bx r1
    144c:	4708      	bx	r1
    144e:	0000      	.short	0x0000
	ldr r2, =_kernel
    1450:	20000a9c 	.word	0x20000a9c
	ldr r1, =_sw_isr_table
    1454:	00007550 	.word	0x00007550
	ldr r1, =z_arm_int_exit
    1458:	0000145d 	.word	0x0000145d

0000145c <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    145c:	4b04      	ldr	r3, [pc, #16]	; (1470 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    145e:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    1460:	69d8      	ldr	r0, [r3, #28]
	cmp r0, r1
    1462:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    1464:	d003      	beq.n	146e <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    1466:	4903      	ldr	r1, [pc, #12]	; (1474 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    1468:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    146c:	600a      	str	r2, [r1, #0]

0000146e <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    146e:	4770      	bx	lr
	ldr r3, =_kernel
    1470:	20000a9c 	.word	0x20000a9c
	ldr r1, =_SCS_ICSR
    1474:	e000ed04 	.word	0xe000ed04

00001478 <bus_fault>:
 * See z_arm_fault_dump() for example.
 *
 * @return N/A
 */
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
{
    1478:	b510      	push	{r4, lr}
    147a:	4614      	mov	r4, r2
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    147c:	4b12      	ldr	r3, [pc, #72]	; (14c8 <bus_fault+0x50>)
    147e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error");
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    1480:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    1482:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    1484:	f413 7f00 	tst.w	r3, #512	; 0x200
    1488:	d00b      	beq.n	14a2 <bus_fault+0x2a>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
    148a:	4b0f      	ldr	r3, [pc, #60]	; (14c8 <bus_fault+0x50>)
    148c:	6b9a      	ldr	r2, [r3, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    148e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    1490:	f413 4f00 	tst.w	r3, #32768	; 0x8000
    1494:	d005      	beq.n	14a2 <bus_fault+0x2a>
			PR_EXC("  BFAR Address: 0x%x", bfar);
			if (from_hard_fault != 0) {
    1496:	b121      	cbz	r1, 14a2 <bus_fault+0x2a>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    1498:	4a0b      	ldr	r2, [pc, #44]	; (14c8 <bus_fault+0x50>)
    149a:	6a93      	ldr	r3, [r2, #40]	; 0x28
    149c:	f423 4300 	bic.w	r3, r3, #32768	; 0x8000
    14a0:	6293      	str	r3, [r2, #40]	; 0x28
			}
		}
	}
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    14a2:	4b09      	ldr	r3, [pc, #36]	; (14c8 <bus_fault+0x50>)
    14a4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Imprecise data bus error");
	}
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    14a6:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    14a8:	f413 7f80 	tst.w	r3, #256	; 0x100
    14ac:	d101      	bne.n	14b2 <bus_fault+0x3a>
		PR_FAULT_INFO("  Instruction bus error");
#if !defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	}
#else
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    14ae:	4b06      	ldr	r3, [pc, #24]	; (14c8 <bus_fault+0x50>)
    14b0:	6a9b      	ldr	r3, [r3, #40]	; 0x28
		SYSMPU->CESR &= ~sperr;
	}
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    14b2:	4a05      	ldr	r2, [pc, #20]	; (14c8 <bus_fault+0x50>)
    14b4:	6a93      	ldr	r3, [r2, #40]	; 0x28
    14b6:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    14ba:	6293      	str	r3, [r2, #40]	; 0x28

	*recoverable = memory_fault_recoverable(esf, true);
    14bc:	2101      	movs	r1, #1
    14be:	f004 fca9 	bl	5e14 <memory_fault_recoverable>
    14c2:	7020      	strb	r0, [r4, #0]

	return reason;
}
    14c4:	2000      	movs	r0, #0
    14c6:	bd10      	pop	{r4, pc}
    14c8:	e000ed00 	.word	0xe000ed00

000014cc <usage_fault>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    14cc:	4b07      	ldr	r3, [pc, #28]	; (14ec <usage_fault+0x20>)
    14ce:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    14d0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    14d2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    14d4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    14d6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    14d8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    14da:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    14dc:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    14e0:	ea6f 4212 	mvn.w	r2, r2, lsr #16
    14e4:	629a      	str	r2, [r3, #40]	; 0x28

	return reason;
}
    14e6:	2000      	movs	r0, #0
    14e8:	4770      	bx	lr
    14ea:	bf00      	nop
    14ec:	e000ed00 	.word	0xe000ed00

000014f0 <mem_manage_fault>:
{
    14f0:	b570      	push	{r4, r5, r6, lr}
    14f2:	4605      	mov	r5, r0
    14f4:	4616      	mov	r6, r2
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    14f6:	4b20      	ldr	r3, [pc, #128]	; (1578 <mem_manage_fault+0x88>)
    14f8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    14fa:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    14fc:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    14fe:	f013 0f02 	tst.w	r3, #2
    1502:	d00c      	beq.n	151e <mem_manage_fault+0x2e>
		uint32_t temp = SCB->MMFAR;
    1504:	4b1c      	ldr	r3, [pc, #112]	; (1578 <mem_manage_fault+0x88>)
    1506:	6b58      	ldr	r0, [r3, #52]	; 0x34
		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    1508:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    150a:	f013 0f80 	tst.w	r3, #128	; 0x80
    150e:	d025      	beq.n	155c <mem_manage_fault+0x6c>
			if (from_hard_fault != 0) {
    1510:	b139      	cbz	r1, 1522 <mem_manage_fault+0x32>
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    1512:	4a19      	ldr	r2, [pc, #100]	; (1578 <mem_manage_fault+0x88>)
    1514:	6a93      	ldr	r3, [r2, #40]	; 0x28
    1516:	f023 0380 	bic.w	r3, r3, #128	; 0x80
    151a:	6293      	str	r3, [r2, #40]	; 0x28
    151c:	e001      	b.n	1522 <mem_manage_fault+0x32>
	uint32_t mmfar = -EINVAL;
    151e:	f06f 0015 	mvn.w	r0, #21
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    1522:	4b15      	ldr	r3, [pc, #84]	; (1578 <mem_manage_fault+0x88>)
    1524:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    1526:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1528:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    152a:	f013 0f10 	tst.w	r3, #16
    152e:	d104      	bne.n	153a <mem_manage_fault+0x4a>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    1530:	4b11      	ldr	r3, [pc, #68]	; (1578 <mem_manage_fault+0x88>)
    1532:	6a9c      	ldr	r4, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1534:	f014 0402 	ands.w	r4, r4, #2
    1538:	d004      	beq.n	1544 <mem_manage_fault+0x54>
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
    153a:	4b0f      	ldr	r3, [pc, #60]	; (1578 <mem_manage_fault+0x88>)
    153c:	685c      	ldr	r4, [r3, #4]
    153e:	f414 6400 	ands.w	r4, r4, #2048	; 0x800
    1542:	d10e      	bne.n	1562 <mem_manage_fault+0x72>
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    1544:	4a0c      	ldr	r2, [pc, #48]	; (1578 <mem_manage_fault+0x88>)
    1546:	6a93      	ldr	r3, [r2, #40]	; 0x28
    1548:	f043 03ff 	orr.w	r3, r3, #255	; 0xff
    154c:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    154e:	2101      	movs	r1, #1
    1550:	4628      	mov	r0, r5
    1552:	f004 fc5f 	bl	5e14 <memory_fault_recoverable>
    1556:	7030      	strb	r0, [r6, #0]
}
    1558:	4620      	mov	r0, r4
    155a:	bd70      	pop	{r4, r5, r6, pc}
	uint32_t mmfar = -EINVAL;
    155c:	f06f 0015 	mvn.w	r0, #21
    1560:	e7df      	b.n	1522 <mem_manage_fault+0x32>
			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
    1562:	4629      	mov	r1, r5
    1564:	f7ff ff14 	bl	1390 <z_check_thread_stack_fail>
			if (min_stack_ptr) {
    1568:	4604      	mov	r4, r0
    156a:	2800      	cmp	r0, #0
    156c:	d0ea      	beq.n	1544 <mem_manage_fault+0x54>
  \details Assigns the given value to the Process Stack Pointer (PSP).
  \param [in]    topOfProcStack  Process Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
{
  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
    156e:	f380 8809 	msr	PSP, r0
				reason = K_ERR_STACK_CHK_FAIL;
    1572:	2402      	movs	r4, #2
    1574:	e7e6      	b.n	1544 <mem_manage_fault+0x54>
    1576:	bf00      	nop
    1578:	e000ed00 	.word	0xe000ed00

0000157c <hard_fault>:
 * See z_arm_fault_dump() for example.
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t hard_fault(z_arch_esf_t *esf, bool *recoverable)
{
    157c:	b510      	push	{r4, lr}
    157e:	4604      	mov	r4, r0
		reason = esf->basic.r0;
	}

	*recoverable = memory_fault_recoverable(esf, true);
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	*recoverable = false;
    1580:	2300      	movs	r3, #0
    1582:	700b      	strb	r3, [r1, #0]

	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    1584:	4b1b      	ldr	r3, [pc, #108]	; (15f4 <hard_fault+0x78>)
    1586:	6ad8      	ldr	r0, [r3, #44]	; 0x2c
    1588:	f010 0002 	ands.w	r0, r0, #2
    158c:	d12d      	bne.n	15ea <hard_fault+0x6e>
		PR_EXC("  Bus fault on vector table read");
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    158e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    1590:	2b00      	cmp	r3, #0
    1592:	db2b      	blt.n	15ec <hard_fault+0x70>
		PR_EXC("  Debug event");
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    1594:	4b17      	ldr	r3, [pc, #92]	; (15f4 <hard_fault+0x78>)
    1596:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    1598:	f013 4380 	ands.w	r3, r3, #1073741824	; 0x40000000
    159c:	d027      	beq.n	15ee <hard_fault+0x72>
	uint16_t *ret_addr = (uint16_t *)esf->basic.pc;
    159e:	69a3      	ldr	r3, [r4, #24]
	uint16_t fault_insn = *(ret_addr - 1);
    15a0:	f833 2c02 	ldrh.w	r2, [r3, #-2]
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    15a4:	f64d 7302 	movw	r3, #57090	; 0xdf02
    15a8:	429a      	cmp	r2, r3
    15aa:	d010      	beq.n	15ce <hard_fault+0x52>
		PR_EXC("  Fault escalation (see below)");
		if (z_arm_is_synchronous_svc(esf)) {
			PR_EXC("ARCH_EXCEPT with reason %x\n", esf->basic.r0);
			reason = esf->basic.r0;
		} else if (SCB_MMFSR != 0) {
    15ac:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    15b0:	f603 6326 	addw	r3, r3, #3622	; 0xe26
    15b4:	781b      	ldrb	r3, [r3, #0]
    15b6:	b963      	cbnz	r3, 15d2 <hard_fault+0x56>
			reason = mem_manage_fault(esf, 1, recoverable);
		} else if (SCB_BFSR != 0) {
    15b8:	4b0f      	ldr	r3, [pc, #60]	; (15f8 <hard_fault+0x7c>)
    15ba:	781b      	ldrb	r3, [r3, #0]
    15bc:	b97b      	cbnz	r3, 15de <hard_fault+0x62>
			reason = bus_fault(esf, 1, recoverable);
		} else if (SCB_UFSR != 0) {
    15be:	4b0f      	ldr	r3, [pc, #60]	; (15fc <hard_fault+0x80>)
    15c0:	881b      	ldrh	r3, [r3, #0]
    15c2:	b29b      	uxth	r3, r3
    15c4:	b193      	cbz	r3, 15ec <hard_fault+0x70>
			reason = usage_fault(esf);
    15c6:	4620      	mov	r0, r4
    15c8:	f7ff ff80 	bl	14cc <usage_fault>
    15cc:	e00e      	b.n	15ec <hard_fault+0x70>
			reason = esf->basic.r0;
    15ce:	6820      	ldr	r0, [r4, #0]
    15d0:	e00c      	b.n	15ec <hard_fault+0x70>
			reason = mem_manage_fault(esf, 1, recoverable);
    15d2:	460a      	mov	r2, r1
    15d4:	2101      	movs	r1, #1
    15d6:	4620      	mov	r0, r4
    15d8:	f7ff ff8a 	bl	14f0 <mem_manage_fault>
    15dc:	e006      	b.n	15ec <hard_fault+0x70>
			reason = bus_fault(esf, 1, recoverable);
    15de:	460a      	mov	r2, r1
    15e0:	2101      	movs	r1, #1
    15e2:	4620      	mov	r0, r4
    15e4:	f7ff ff48 	bl	1478 <bus_fault>
    15e8:	e000      	b.n	15ec <hard_fault+0x70>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    15ea:	2000      	movs	r0, #0
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	return reason;
}
    15ec:	bd10      	pop	{r4, pc}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    15ee:	4618      	mov	r0, r3
	return reason;
    15f0:	e7fc      	b.n	15ec <hard_fault+0x70>
    15f2:	bf00      	nop
    15f4:	e000ed00 	.word	0xe000ed00
    15f8:	e000ed29 	.word	0xe000ed29
    15fc:	e000ed2a 	.word	0xe000ed2a

00001600 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    1600:	b570      	push	{r4, r5, r6, lr}
    1602:	b08a      	sub	sp, #40	; 0x28
    1604:	460c      	mov	r4, r1
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    1606:	4b22      	ldr	r3, [pc, #136]	; (1690 <z_arm_fault+0x90>)
    1608:	6859      	ldr	r1, [r3, #4]
    160a:	f3c1 0108 	ubfx	r1, r1, #0, #9
    160e:	2300      	movs	r3, #0
    1610:	f383 8811 	msr	BASEPRI, r3
    1614:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    1618:	f002 437f 	and.w	r3, r2, #4278190080	; 0xff000000
    161c:	f1b3 4f7f 	cmp.w	r3, #4278190080	; 0xff000000
    1620:	d115      	bne.n	164e <z_arm_fault+0x4e>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    1622:	f002 030c 	and.w	r3, r2, #12
    1626:	2b08      	cmp	r3, #8
    1628:	d014      	beq.n	1654 <z_arm_fault+0x54>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    162a:	f012 0f08 	tst.w	r2, #8
    162e:	d00b      	beq.n	1648 <z_arm_fault+0x48>
	*nested_exc = false;
    1630:	2600      	movs	r6, #0

#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
    1632:	f10d 0227 	add.w	r2, sp, #39	; 0x27
    1636:	4620      	mov	r0, r4
    1638:	f004 fbf1 	bl	5e1e <fault_handle>
    163c:	4605      	mov	r5, r0
	if (recoverable) {
    163e:	f89d 3027 	ldrb.w	r3, [sp, #39]	; 0x27
    1642:	b153      	cbz	r3, 165a <z_arm_fault+0x5a>
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
	}

	z_arm_fatal_error(reason, &esf_copy);
}
    1644:	b00a      	add	sp, #40	; 0x28
    1646:	bd70      	pop	{r4, r5, r6, pc}
			ptr_esf = (z_arch_esf_t *)msp;
    1648:	4604      	mov	r4, r0
			*nested_exc = true;
    164a:	2601      	movs	r6, #1
    164c:	e7f1      	b.n	1632 <z_arm_fault+0x32>
	*nested_exc = false;
    164e:	2600      	movs	r6, #0
		return NULL;
    1650:	4634      	mov	r4, r6
    1652:	e7ee      	b.n	1632 <z_arm_fault+0x32>
	*nested_exc = false;
    1654:	2600      	movs	r6, #0
		return NULL;
    1656:	4634      	mov	r4, r6
    1658:	e7eb      	b.n	1632 <z_arm_fault+0x32>
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    165a:	2220      	movs	r2, #32
    165c:	4621      	mov	r1, r4
    165e:	a801      	add	r0, sp, #4
    1660:	f004 fcaa 	bl	5fb8 <memcpy>
	if (nested_exc) {
    1664:	b14e      	cbz	r6, 167a <z_arm_fault+0x7a>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    1666:	9b08      	ldr	r3, [sp, #32]
    1668:	f3c3 0208 	ubfx	r2, r3, #0, #9
    166c:	b95a      	cbnz	r2, 1686 <z_arm_fault+0x86>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    166e:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    1672:	ea6f 2343 	mvn.w	r3, r3, lsl #9
    1676:	9308      	str	r3, [sp, #32]
    1678:	e005      	b.n	1686 <z_arm_fault+0x86>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    167a:	9b08      	ldr	r3, [sp, #32]
    167c:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    1680:	f023 0301 	bic.w	r3, r3, #1
    1684:	9308      	str	r3, [sp, #32]
	z_arm_fatal_error(reason, &esf_copy);
    1686:	a901      	add	r1, sp, #4
    1688:	4628      	mov	r0, r5
    168a:	f004 fbad 	bl	5de8 <z_arm_fatal_error>
    168e:	e7d9      	b.n	1644 <z_arm_fault+0x44>
    1690:	e000ed00 	.word	0xe000ed00

00001694 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    1694:	4a02      	ldr	r2, [pc, #8]	; (16a0 <z_arm_fault_init+0xc>)
    1696:	6953      	ldr	r3, [r2, #20]
    1698:	f043 0310 	orr.w	r3, r3, #16
    169c:	6153      	str	r3, [r2, #20]
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
}
    169e:	4770      	bx	lr
    16a0:	e000ed00 	.word	0xe000ed00

000016a4 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    16a4:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    16a8:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    16ac:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    16ae:	4672      	mov	r2, lr
	bl z_arm_fault
    16b0:	f7ff ffa6 	bl	1600 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    16b4:	bd01      	pop	{r0, pc}
    16b6:	bf00      	nop

000016b8 <z_arm_interrupt_init>:
 * @return N/A
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    16b8:	2200      	movs	r2, #0

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    16ba:	e006      	b.n	16ca <z_arm_interrupt_init+0x12>
    16bc:	f002 010f 	and.w	r1, r2, #15
    16c0:	4b09      	ldr	r3, [pc, #36]	; (16e8 <z_arm_interrupt_init+0x30>)
    16c2:	440b      	add	r3, r1
    16c4:	2120      	movs	r1, #32
    16c6:	7619      	strb	r1, [r3, #24]
    16c8:	3201      	adds	r2, #1
    16ca:	2a2f      	cmp	r2, #47	; 0x2f
    16cc:	dc0a      	bgt.n	16e4 <z_arm_interrupt_init+0x2c>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
    16ce:	b253      	sxtb	r3, r2
  if ((int32_t)(IRQn) >= 0)
    16d0:	2b00      	cmp	r3, #0
    16d2:	dbf3      	blt.n	16bc <z_arm_interrupt_init+0x4>
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    16d4:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    16d8:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    16dc:	2120      	movs	r1, #32
    16de:	f883 1300 	strb.w	r1, [r3, #768]	; 0x300
    16e2:	e7f1      	b.n	16c8 <z_arm_interrupt_init+0x10>
	}
}
    16e4:	4770      	bx	lr
    16e6:	bf00      	nop
    16e8:	e000ecfc 	.word	0xe000ecfc

000016ec <__start>:
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    16ec:	2000      	movs	r0, #0
    msr CONTROL, r0
    16ee:	f380 8814 	msr	CONTROL, r0
    isb
    16f2:	f3bf 8f6f 	isb	sy
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    16f6:	f005 fe85 	bl	7404 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    16fa:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    16fc:	490d      	ldr	r1, [pc, #52]	; (1734 <__start+0x48>)
    str r0, [r1]
    16fe:	6008      	str	r0, [r1, #0]
    dsb
    1700:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    1704:	480c      	ldr	r0, [pc, #48]	; (1738 <__start+0x4c>)
    msr msp, r0
    1706:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    170a:	f000 f829 	bl	1760 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    170e:	2020      	movs	r0, #32
    msr BASEPRI, r0
    1710:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    1714:	4809      	ldr	r0, [pc, #36]	; (173c <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    1716:	f44f 6102 	mov.w	r1, #2080	; 0x820
    adds r0, r0, r1
    171a:	1840      	adds	r0, r0, r1
    msr PSP, r0
    171c:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    1720:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    1724:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    1726:	4308      	orrs	r0, r1
    msr CONTROL, r0
    1728:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    172c:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    1730:	f7ff fd9a 	bl	1268 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    1734:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    1738:	20000f00 	.word	0x20000f00
    ldr r0, =z_interrupt_stacks
    173c:	20001080 	.word	0x20001080

00001740 <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    1740:	4b06      	ldr	r3, [pc, #24]	; (175c <z_arm_clear_arm_mpu_config+0x1c>)
    1742:	6818      	ldr	r0, [r3, #0]
	int num_regions =
    1744:	f3c0 2007 	ubfx	r0, r0, #8, #8

	for (i = 0; i < num_regions; i++) {
    1748:	2300      	movs	r3, #0
    174a:	4283      	cmp	r3, r0
    174c:	da05      	bge.n	175a <z_arm_clear_arm_mpu_config+0x1a>
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
    174e:	4a03      	ldr	r2, [pc, #12]	; (175c <z_arm_clear_arm_mpu_config+0x1c>)
    1750:	6093      	str	r3, [r2, #8]
  MPU->RASR = 0U;
    1752:	2100      	movs	r1, #0
    1754:	6111      	str	r1, [r2, #16]
    1756:	3301      	adds	r3, #1
    1758:	e7f7      	b.n	174a <z_arm_clear_arm_mpu_config+0xa>
		ARM_MPU_ClrRegion(i);
	}
}
    175a:	4770      	bx	lr
    175c:	e000ed90 	.word	0xe000ed90

00001760 <z_arm_init_arch_hw_at_boot>:
 * components and core registers.
 *
 * @return N/A
 */
void z_arm_init_arch_hw_at_boot(void)
{
    1760:	b510      	push	{r4, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    1762:	b672      	cpsid	i
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    1764:	2400      	movs	r4, #0
    1766:	f384 8813 	msr	FAULTMASK, r4

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    176a:	f7ff ffe9 	bl	1740 <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    176e:	4623      	mov	r3, r4
    1770:	e008      	b.n	1784 <z_arm_init_arch_hw_at_boot+0x24>
		NVIC->ICER[i] = 0xFFFFFFFF;
    1772:	f103 0120 	add.w	r1, r3, #32
    1776:	4a0e      	ldr	r2, [pc, #56]	; (17b0 <z_arm_init_arch_hw_at_boot+0x50>)
    1778:	f04f 30ff 	mov.w	r0, #4294967295
    177c:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    1780:	3301      	adds	r3, #1
    1782:	b2db      	uxtb	r3, r3
    1784:	2b07      	cmp	r3, #7
    1786:	d9f4      	bls.n	1772 <z_arm_init_arch_hw_at_boot+0x12>
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    1788:	2300      	movs	r3, #0
    178a:	e008      	b.n	179e <z_arm_init_arch_hw_at_boot+0x3e>
		NVIC->ICPR[i] = 0xFFFFFFFF;
    178c:	f103 0160 	add.w	r1, r3, #96	; 0x60
    1790:	4a07      	ldr	r2, [pc, #28]	; (17b0 <z_arm_init_arch_hw_at_boot+0x50>)
    1792:	f04f 30ff 	mov.w	r0, #4294967295
    1796:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    179a:	3301      	adds	r3, #1
    179c:	b2db      	uxtb	r3, r3
    179e:	2b07      	cmp	r3, #7
    17a0:	d9f4      	bls.n	178c <z_arm_init_arch_hw_at_boot+0x2c>
  __ASM volatile ("cpsie i" : : : "memory");
    17a2:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    17a4:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    17a8:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    17ac:	bd10      	pop	{r4, pc}
    17ae:	bf00      	nop
    17b0:	e000e100 	.word	0xe000e100

000017b4 <z_impl_k_thread_abort>:
#include <kswap.h>
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
    17b4:	b508      	push	{r3, lr}
	if (_current == thread) {
    17b6:	4b08      	ldr	r3, [pc, #32]	; (17d8 <z_impl_k_thread_abort+0x24>)
    17b8:	689b      	ldr	r3, [r3, #8]
    17ba:	4283      	cmp	r3, r0
    17bc:	d002      	beq.n	17c4 <z_impl_k_thread_abort+0x10>
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
		}
	}

	z_thread_abort(thread);
    17be:	f003 fa91 	bl	4ce4 <z_thread_abort>
}
    17c2:	bd08      	pop	{r3, pc}
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    17c4:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    17c8:	2b00      	cmp	r3, #0
    17ca:	d0f8      	beq.n	17be <z_impl_k_thread_abort+0xa>
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    17cc:	4a03      	ldr	r2, [pc, #12]	; (17dc <z_impl_k_thread_abort+0x28>)
    17ce:	6853      	ldr	r3, [r2, #4]
    17d0:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    17d4:	6053      	str	r3, [r2, #4]
    17d6:	e7f2      	b.n	17be <z_impl_k_thread_abort+0xa>
    17d8:	20000a9c 	.word	0x20000a9c
    17dc:	e000ed00 	.word	0xe000ed00

000017e0 <z_arm_configure_static_mpu_regions>:
 *
 * For some MPU architectures, such as the unmodified ARMv8-M MPU,
 * the function must execute with MPU enabled.
 */
void z_arm_configure_static_mpu_regions(void)
{
    17e0:	b508      	push	{r3, lr}
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    17e2:	4b03      	ldr	r3, [pc, #12]	; (17f0 <z_arm_configure_static_mpu_regions+0x10>)
    17e4:	4a03      	ldr	r2, [pc, #12]	; (17f4 <z_arm_configure_static_mpu_regions+0x14>)
    17e6:	2101      	movs	r1, #1
    17e8:	4803      	ldr	r0, [pc, #12]	; (17f8 <z_arm_configure_static_mpu_regions+0x18>)
    17ea:	f004 fb9e 	bl	5f2a <arm_core_mpu_configure_static_mpu_regions>
	};

	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
		ARRAY_SIZE(dyn_region_areas));
#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */
}
    17ee:	bd08      	pop	{r3, pc}
    17f0:	20020000 	.word	0x20020000
    17f4:	20000000 	.word	0x20000000
    17f8:	0000779c 	.word	0x0000779c

000017fc <z_arm_configure_dynamic_mpu_regions>:
 *
 * This function is not inherently thread-safe, but the memory domain
 * spinlock needs to be held anyway.
 */
void z_arm_configure_dynamic_mpu_regions(struct k_thread *thread)
{
    17fc:	b508      	push	{r3, lr}
#endif /* CONFIG_USERSPACE */
	{
		/* A supervisor thread only has the normal thread stack to
		 * protect with a stack guard.
		 */
		guard_start = thread->stack_info.start - guard_size;
    17fe:	f8d0 309c 	ldr.w	r3, [r0, #156]	; 0x9c
    1802:	3b20      	subs	r3, #32
	}

	__ASSERT(region_num < _MAX_DYNAMIC_MPU_REGIONS_NUM,
		"Out-of-bounds error for dynamic region map.");

	dynamic_regions[region_num].start = guard_start;
    1804:	4804      	ldr	r0, [pc, #16]	; (1818 <z_arm_configure_dynamic_mpu_regions+0x1c>)
    1806:	6003      	str	r3, [r0, #0]
	dynamic_regions[region_num].size = guard_size;
    1808:	2320      	movs	r3, #32
    180a:	6043      	str	r3, [r0, #4]
	dynamic_regions[region_num].attr = K_MEM_PARTITION_P_RO_U_NA;
    180c:	4b03      	ldr	r3, [pc, #12]	; (181c <z_arm_configure_dynamic_mpu_regions+0x20>)
    180e:	6083      	str	r3, [r0, #8]

	region_num++;
#endif /* CONFIG_MPU_STACK_GUARD */

	/* Configure the dynamic MPU regions */
	arm_core_mpu_configure_dynamic_mpu_regions(dynamic_regions,
    1810:	2101      	movs	r1, #1
    1812:	f004 fb8e 	bl	5f32 <arm_core_mpu_configure_dynamic_mpu_regions>
						   region_num);
}
    1816:	bd08      	pop	{r3, pc}
    1818:	2000044c 	.word	0x2000044c
    181c:	150b0000 	.word	0x150b0000

00001820 <region_init>:
#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */
}

static inline void set_region_number(uint32_t index)
{
	MPU->RNR = index;
    1820:	4a06      	ldr	r2, [pc, #24]	; (183c <region_init+0x1c>)
    1822:	6090      	str	r0, [r2, #8]

	set_region_base_address(region_conf->base & MPU_RBAR_ADDR_Msk);
	set_region_attributes(region_conf->attr.rasr);
	set_region_size(region_conf->size | MPU_RASR_ENABLE_Msk);
#else
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    1824:	680b      	ldr	r3, [r1, #0]
    1826:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    182a:	4303      	orrs	r3, r0
    182c:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    1830:	60d3      	str	r3, [r2, #12]
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    1832:	688b      	ldr	r3, [r1, #8]
    1834:	f043 0301 	orr.w	r3, r3, #1
    1838:	6113      	str	r3, [r2, #16]
	LOG_DBG("[%d] 0x%08x 0x%08x",
		index, region_conf->base, region_conf->attr.rasr);
#endif
}
    183a:	4770      	bx	lr
    183c:	e000ed90 	.word	0xe000ed90

00001840 <mpu_configure_static_mpu_regions>:
 */
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
    1840:	b510      	push	{r4, lr}
	int mpu_reg_index = static_regions_num;
    1842:	4c03      	ldr	r4, [pc, #12]	; (1850 <mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    1844:	2301      	movs	r3, #1
    1846:	7822      	ldrb	r2, [r4, #0]
    1848:	f004 fb47 	bl	5eda <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    184c:	7020      	strb	r0, [r4, #0]

	return mpu_reg_index;
}
    184e:	bd10      	pop	{r4, pc}
    1850:	20000ae0 	.word	0x20000ae0

00001854 <mpu_configure_dynamic_mpu_regions>:
 * If the dynamic MPU regions configuration has not been successfully
 * performed, the error signal is propagated to the caller of the function.
 */
static int mpu_configure_dynamic_mpu_regions(const struct z_arm_mpu_partition
	dynamic_regions[], uint8_t regions_num)
{
    1854:	b508      	push	{r3, lr}

	/* In ARMv7-M architecture the dynamic regions are
	 * programmed on top of existing SRAM region configuration.
	 */

	mpu_reg_index = mpu_configure_regions(dynamic_regions,
    1856:	2300      	movs	r3, #0
    1858:	4a08      	ldr	r2, [pc, #32]	; (187c <mpu_configure_dynamic_mpu_regions+0x28>)
    185a:	7812      	ldrb	r2, [r2, #0]
    185c:	f004 fb3d 	bl	5eda <mpu_configure_regions>
		regions_num, mpu_reg_index, false);

	if (mpu_reg_index != -EINVAL) {
    1860:	f110 0f16 	cmn.w	r0, #22
    1864:	d008      	beq.n	1878 <mpu_configure_dynamic_mpu_regions+0x24>

		/* Disable the non-programmed MPU regions. */
		for (int i = mpu_reg_index; i < get_num_regions(); i++) {
    1866:	4603      	mov	r3, r0
    1868:	2b07      	cmp	r3, #7
    186a:	dc05      	bgt.n	1878 <mpu_configure_dynamic_mpu_regions+0x24>
  MPU->RNR = rnr;
    186c:	4a04      	ldr	r2, [pc, #16]	; (1880 <mpu_configure_dynamic_mpu_regions+0x2c>)
    186e:	6093      	str	r3, [r2, #8]
  MPU->RASR = 0U;
    1870:	2100      	movs	r1, #0
    1872:	6111      	str	r1, [r2, #16]
    1874:	3301      	adds	r3, #1
    1876:	e7f7      	b.n	1868 <mpu_configure_dynamic_mpu_regions+0x14>
			ARM_MPU_ClrRegion(i);
		}
	}

	return mpu_reg_index;
}
    1878:	bd08      	pop	{r3, pc}
    187a:	bf00      	nop
    187c:	20000ae0 	.word	0x20000ae0
    1880:	e000ed90 	.word	0xe000ed90

00001884 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    1884:	4b03      	ldr	r3, [pc, #12]	; (1894 <arm_core_mpu_enable+0x10>)
    1886:	2205      	movs	r2, #5
    1888:	605a      	str	r2, [r3, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    188a:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    188e:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    1892:	4770      	bx	lr
    1894:	e000ed90 	.word	0xe000ed90

00001898 <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    1898:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    189c:	4b01      	ldr	r3, [pc, #4]	; (18a4 <arm_core_mpu_disable+0xc>)
    189e:	2200      	movs	r2, #0
    18a0:	605a      	str	r2, [r3, #4]
}
    18a2:	4770      	bx	lr
    18a4:	e000ed90 	.word	0xe000ed90

000018a8 <z_arm_mpu_init>:
 *
 * This function provides the default configuration mechanism for the Memory
 * Protection Unit (MPU).
 */
int z_arm_mpu_init(void)
{
    18a8:	b538      	push	{r3, r4, r5, lr}
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    18aa:	4b0e      	ldr	r3, [pc, #56]	; (18e4 <z_arm_mpu_init+0x3c>)
    18ac:	681d      	ldr	r5, [r3, #0]
    18ae:	2d08      	cmp	r5, #8
    18b0:	d815      	bhi.n	18de <z_arm_mpu_init+0x36>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    18b2:	f7ff fff1 	bl	1898 <arm_core_mpu_disable>

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    18b6:	2400      	movs	r4, #0
    18b8:	42a5      	cmp	r5, r4
    18ba:	d90a      	bls.n	18d2 <z_arm_mpu_init+0x2a>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
    18bc:	4b09      	ldr	r3, [pc, #36]	; (18e4 <z_arm_mpu_init+0x3c>)
    18be:	6859      	ldr	r1, [r3, #4]
    18c0:	eb04 0244 	add.w	r2, r4, r4, lsl #1
    18c4:	0093      	lsls	r3, r2, #2
    18c6:	4419      	add	r1, r3
    18c8:	4620      	mov	r0, r4
    18ca:	f7ff ffa9 	bl	1820 <region_init>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    18ce:	3401      	adds	r4, #1
    18d0:	e7f2      	b.n	18b8 <z_arm_mpu_init+0x10>
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    18d2:	4b05      	ldr	r3, [pc, #20]	; (18e8 <z_arm_mpu_init+0x40>)
    18d4:	701d      	strb	r5, [r3, #0]


	arm_core_mpu_enable();
    18d6:	f7ff ffd5 	bl	1884 <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    18da:	2000      	movs	r0, #0
}
    18dc:	bd38      	pop	{r3, r4, r5, pc}
		return -1;
    18de:	f04f 30ff 	mov.w	r0, #4294967295
    18e2:	e7fb      	b.n	18dc <z_arm_mpu_init+0x34>
    18e4:	000077b8 	.word	0x000077b8
    18e8:	20000ae0 	.word	0x20000ae0

000018ec <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
    18ec:	4b01      	ldr	r3, [pc, #4]	; (18f4 <__stdout_hook_install+0x8>)
    18ee:	6018      	str	r0, [r3, #0]
}
    18f0:	4770      	bx	lr
    18f2:	bf00      	nop
    18f4:	20000008 	.word	0x20000008

000018f8 <nordicsemi_nrf52_init>:
	__asm__ volatile(
    18f8:	f04f 0320 	mov.w	r3, #32
    18fc:	f3ef 8211 	mrs	r2, BASEPRI
    1900:	f383 8812 	msr	BASEPRI_MAX, r3
    1904:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    1908:	2301      	movs	r3, #1
    190a:	4906      	ldr	r1, [pc, #24]	; (1924 <nordicsemi_nrf52_init+0x2c>)
    190c:	f8c1 3540 	str.w	r3, [r1, #1344]	; 0x540
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    1910:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    1914:	f8c1 3578 	str.w	r3, [r1, #1400]	; 0x578
	__asm__ volatile(
    1918:	f382 8811 	msr	BASEPRI, r2
    191c:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    1920:	2000      	movs	r0, #0
    1922:	4770      	bx	lr
    1924:	4001e000 	.word	0x4001e000

00001928 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    1928:	b130      	cbz	r0, 1938 <arch_busy_wait+0x10>

void arch_busy_wait(uint32_t time_us)
{
    192a:	b508      	push	{r3, lr}
    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    192c:	0180      	lsls	r0, r0, #6
    192e:	4b03      	ldr	r3, [pc, #12]	; (193c <arch_busy_wait+0x14>)
    1930:	f043 0301 	orr.w	r3, r3, #1
    1934:	4798      	blx	r3
	nrfx_coredep_delay_us(time_us);
}
    1936:	bd08      	pop	{r3, pc}
    1938:	4770      	bx	lr
    193a:	bf00      	nop
    193c:	00007750 	.word	0x00007750

00001940 <get_hf_flags>:
static uint32_t *get_hf_flags(void)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;

	return &data->subsys[CLOCK_CONTROL_NRF_TYPE_HFCLK].flags;
}
    1940:	4800      	ldr	r0, [pc, #0]	; (1944 <get_hf_flags+0x4>)
    1942:	4770      	bx	lr
    1944:	200004a8 	.word	0x200004a8

00001948 <get_subsys>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    1948:	4b03      	ldr	r3, [pc, #12]	; (1958 <get_subsys+0x10>)
    194a:	1ac0      	subs	r0, r0, r3
    194c:	1080      	asrs	r0, r0, #2

	return (clock_control_subsys_t)offset;
}
    194e:	4b03      	ldr	r3, [pc, #12]	; (195c <get_subsys+0x14>)
    1950:	fb03 f000 	mul.w	r0, r3, r0
    1954:	4770      	bx	lr
    1956:	bf00      	nop
    1958:	20000468 	.word	0x20000468
    195c:	b6db6db7 	.word	0xb6db6db7

00001960 <onoff_stop>:

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    1960:	b538      	push	{r3, r4, r5, lr}
    1962:	4605      	mov	r5, r0
    1964:	460c      	mov	r4, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    1966:	f7ff ffef 	bl	1948 <get_subsys>
    196a:	4601      	mov	r1, r0
    196c:	2240      	movs	r2, #64	; 0x40
    196e:	4803      	ldr	r0, [pc, #12]	; (197c <onoff_stop+0x1c>)
    1970:	f004 fbfb 	bl	616a <stop>
    1974:	4601      	mov	r1, r0
	notify(mgr, res);
    1976:	4628      	mov	r0, r5
    1978:	47a0      	blx	r4
}
    197a:	bd38      	pop	{r3, r4, r5, pc}
    197c:	00007478 	.word	0x00007478

00001980 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    1980:	b530      	push	{r4, r5, lr}
    1982:	b083      	sub	sp, #12
    1984:	4605      	mov	r5, r0
    1986:	460c      	mov	r4, r1
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1988:	f7ff ffde 	bl	1948 <get_subsys>
    198c:	4601      	mov	r1, r0
    198e:	2340      	movs	r3, #64	; 0x40
    1990:	9300      	str	r3, [sp, #0]
    1992:	4623      	mov	r3, r4
    1994:	4a05      	ldr	r2, [pc, #20]	; (19ac <onoff_start+0x2c>)
    1996:	4806      	ldr	r0, [pc, #24]	; (19b0 <onoff_start+0x30>)
    1998:	f004 fc01 	bl	619e <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    199c:	1e01      	subs	r1, r0, #0
    199e:	db01      	blt.n	19a4 <onoff_start+0x24>
		notify(mgr, err);
	}
}
    19a0:	b003      	add	sp, #12
    19a2:	bd30      	pop	{r4, r5, pc}
		notify(mgr, err);
    19a4:	4628      	mov	r0, r5
    19a6:	47a0      	blx	r4
}
    19a8:	e7fa      	b.n	19a0 <onoff_start+0x20>
    19aa:	bf00      	nop
    19ac:	000061e7 	.word	0x000061e7
    19b0:	00007478 	.word	0x00007478

000019b4 <clock_event_handler>:
		__ASSERT_NO_MSG(false);
	}
}

static void clock_event_handler(nrfx_clock_evt_type_t event)
{
    19b4:	b508      	push	{r3, lr}
	const struct device *dev = CLOCK_DEVICE;

	switch (event) {
    19b6:	b110      	cbz	r0, 19be <clock_event_handler+0xa>
    19b8:	2801      	cmp	r0, #1
    19ba:	d00d      	beq.n	19d8 <clock_event_handler+0x24>
		break;
	default:
		__ASSERT_NO_MSG(0);
		break;
	}
}
    19bc:	bd08      	pop	{r3, pc}
				get_sub_data(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK);
    19be:	2100      	movs	r1, #0
    19c0:	4808      	ldr	r0, [pc, #32]	; (19e4 <clock_event_handler+0x30>)
    19c2:	f004 fb5b 	bl	607c <get_sub_data>
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    19c6:	6883      	ldr	r3, [r0, #8]
    19c8:	f013 0f07 	tst.w	r3, #7
    19cc:	d1f6      	bne.n	19bc <clock_event_handler+0x8>
			clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK);
    19ce:	2100      	movs	r1, #0
    19d0:	4804      	ldr	r0, [pc, #16]	; (19e4 <clock_event_handler+0x30>)
    19d2:	f004 fbb8 	bl	6146 <clkstarted_handle>
    19d6:	e7f1      	b.n	19bc <clock_event_handler+0x8>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    19d8:	2101      	movs	r1, #1
    19da:	4802      	ldr	r0, [pc, #8]	; (19e4 <clock_event_handler+0x30>)
    19dc:	f004 fbb3 	bl	6146 <clkstarted_handle>
}
    19e0:	e7ec      	b.n	19bc <clock_event_handler+0x8>
    19e2:	bf00      	nop
    19e4:	00007478 	.word	0x00007478

000019e8 <generic_hfclk_start>:
{
    19e8:	b510      	push	{r4, lr}
	__asm__ volatile(
    19ea:	f04f 0320 	mov.w	r3, #32
    19ee:	f3ef 8411 	mrs	r4, BASEPRI
    19f2:	f383 8812 	msr	BASEPRI_MAX, r3
    19f6:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    19fa:	4a13      	ldr	r2, [pc, #76]	; (1a48 <generic_hfclk_start+0x60>)
    19fc:	6813      	ldr	r3, [r2, #0]
    19fe:	f043 0302 	orr.w	r3, r3, #2
    1a02:	6013      	str	r3, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    1a04:	f013 0f01 	tst.w	r3, #1
    1a08:	d108      	bne.n	1a1c <generic_hfclk_start+0x34>
	bool already_started = false;
    1a0a:	2300      	movs	r3, #0
	__asm__ volatile(
    1a0c:	f384 8811 	msr	BASEPRI, r4
    1a10:	f3bf 8f6f 	isb	sy
	if (already_started) {
    1a14:	b99b      	cbnz	r3, 1a3e <generic_hfclk_start+0x56>
	hfclk_start();
    1a16:	f004 fbee 	bl	61f6 <hfclk_start>
}
    1a1a:	bd10      	pop	{r4, pc}
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    1a1c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1a20:	f8d3 240c 	ldr.w	r2, [r3, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    1a24:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    1a28:	f012 0f01 	tst.w	r2, #1
    1a2c:	d101      	bne.n	1a32 <generic_hfclk_start+0x4a>
	bool already_started = false;
    1a2e:	2300      	movs	r3, #0
    1a30:	e7ec      	b.n	1a0c <generic_hfclk_start+0x24>
			set_on_state(get_hf_flags());
    1a32:	f7ff ff85 	bl	1940 <get_hf_flags>
    1a36:	f004 fb73 	bl	6120 <set_on_state>
			already_started = true;
    1a3a:	2301      	movs	r3, #1
    1a3c:	e7e6      	b.n	1a0c <generic_hfclk_start+0x24>
		clkstarted_handle(CLOCK_DEVICE,
    1a3e:	2100      	movs	r1, #0
    1a40:	4802      	ldr	r0, [pc, #8]	; (1a4c <generic_hfclk_start+0x64>)
    1a42:	f004 fb80 	bl	6146 <clkstarted_handle>
		return;
    1a46:	e7e8      	b.n	1a1a <generic_hfclk_start+0x32>
    1a48:	200004b8 	.word	0x200004b8
    1a4c:	00007478 	.word	0x00007478

00001a50 <generic_hfclk_stop>:
{
    1a50:	b508      	push	{r3, lr}
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    1a52:	4b0a      	ldr	r3, [pc, #40]	; (1a7c <generic_hfclk_stop+0x2c>)
    1a54:	f3bf 8f5b 	dmb	ish
    1a58:	e853 2f00 	ldrex	r2, [r3]
    1a5c:	f022 0102 	bic.w	r1, r2, #2
    1a60:	e843 1000 	strex	r0, r1, [r3]
    1a64:	2800      	cmp	r0, #0
    1a66:	d1f7      	bne.n	1a58 <generic_hfclk_stop+0x8>
    1a68:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    1a6c:	f012 0f01 	tst.w	r2, #1
    1a70:	d000      	beq.n	1a74 <generic_hfclk_stop+0x24>
}
    1a72:	bd08      	pop	{r3, pc}
	hfclk_stop();
    1a74:	f004 fbc9 	bl	620a <hfclk_stop>
    1a78:	e7fb      	b.n	1a72 <generic_hfclk_stop+0x22>
    1a7a:	bf00      	nop
    1a7c:	200004b8 	.word	0x200004b8

00001a80 <api_blocking_start>:
{
    1a80:	b500      	push	{lr}
    1a82:	b087      	sub	sp, #28
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1a84:	f8cd d000 	str.w	sp, [sp]
    1a88:	f8cd d004 	str.w	sp, [sp, #4]
    1a8c:	2300      	movs	r3, #0
    1a8e:	9302      	str	r3, [sp, #8]
    1a90:	2301      	movs	r3, #1
    1a92:	9303      	str	r3, [sp, #12]
    1a94:	ab04      	add	r3, sp, #16
    1a96:	9304      	str	r3, [sp, #16]
    1a98:	9305      	str	r3, [sp, #20]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1a9a:	466b      	mov	r3, sp
    1a9c:	4a06      	ldr	r2, [pc, #24]	; (1ab8 <api_blocking_start+0x38>)
    1a9e:	f004 fb9a 	bl	61d6 <api_start>
	if (err < 0) {
    1aa2:	2800      	cmp	r0, #0
    1aa4:	db05      	blt.n	1ab2 <api_blocking_start+0x32>
	return z_impl_k_sem_take(sem, timeout);
    1aa6:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    1aaa:	2300      	movs	r3, #0
    1aac:	4668      	mov	r0, sp
    1aae:	f002 fd7b 	bl	45a8 <z_impl_k_sem_take>
}
    1ab2:	b007      	add	sp, #28
    1ab4:	f85d fb04 	ldr.w	pc, [sp], #4
    1ab8:	0000621f 	.word	0x0000621f

00001abc <clk_init>:
#endif /* NRF_CLOCK_HAS_HFCLKAUDIO */
#endif
}

static int clk_init(const struct device *dev)
{
    1abc:	b570      	push	{r4, r5, r6, lr}
    1abe:	4606      	mov	r6, r0
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1ac0:	2200      	movs	r2, #0
    1ac2:	2101      	movs	r1, #1
    1ac4:	4610      	mov	r0, r2
    1ac6:	f7ff fbb5 	bl	1234 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);
	irq_enable(DT_INST_IRQN(0));
    1aca:	2000      	movs	r0, #0
    1acc:	f7ff fb80 	bl	11d0 <arch_irq_enable>

	nrfx_err = nrfx_clock_init(clock_event_handler);
    1ad0:	4811      	ldr	r0, [pc, #68]	; (1b18 <clk_init+0x5c>)
    1ad2:	f001 fbd3 	bl	327c <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    1ad6:	4b11      	ldr	r3, [pc, #68]	; (1b1c <clk_init+0x60>)
    1ad8:	4298      	cmp	r0, r3
    1ada:	d11a      	bne.n	1b12 <clk_init+0x56>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    1adc:	f005 f8ed 	bl	6cba <nrfx_clock_enable>

	for (enum clock_control_nrf_type i = 0;
    1ae0:	2400      	movs	r4, #0
    1ae2:	e003      	b.n	1aec <clk_init+0x30>
					 &transitions);
		if (err < 0) {
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1ae4:	2301      	movs	r3, #1
    1ae6:	60ab      	str	r3, [r5, #8]
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
    1ae8:	441c      	add	r4, r3
    1aea:	b2e4      	uxtb	r4, r4
	for (enum clock_control_nrf_type i = 0;
    1aec:	2c01      	cmp	r4, #1
    1aee:	d80e      	bhi.n	1b0e <clk_init+0x52>
						get_sub_data(dev, i);
    1af0:	4621      	mov	r1, r4
    1af2:	4630      	mov	r0, r6
    1af4:	f004 fac2 	bl	607c <get_sub_data>
    1af8:	4605      	mov	r5, r0
		err = onoff_manager_init(get_onoff_manager(dev, i),
    1afa:	4621      	mov	r1, r4
    1afc:	4630      	mov	r0, r6
    1afe:	f004 fac8 	bl	6092 <get_onoff_manager>
    1b02:	4907      	ldr	r1, [pc, #28]	; (1b20 <clk_init+0x64>)
    1b04:	f004 f851 	bl	5baa <onoff_manager_init>
		if (err < 0) {
    1b08:	2800      	cmp	r0, #0
    1b0a:	daeb      	bge.n	1ae4 <clk_init+0x28>
    1b0c:	e000      	b.n	1b10 <clk_init+0x54>
	}

	return 0;
    1b0e:	2000      	movs	r0, #0
}
    1b10:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    1b12:	f06f 0004 	mvn.w	r0, #4
    1b16:	e7fb      	b.n	1b10 <clk_init+0x54>
    1b18:	000019b5 	.word	0x000019b5
    1b1c:	0bad0000 	.word	0x0bad0000
    1b20:	00007804 	.word	0x00007804

00001b24 <lfclk_spinwait>:
{
    1b24:	b570      	push	{r4, r5, r6, lr}
    1b26:	4605      	mov	r5, r0
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    1b28:	2801      	cmp	r0, #1
    1b2a:	d107      	bne.n	1b3c <lfclk_spinwait+0x18>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    1b2c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1b30:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
    1b34:	f003 0303 	and.w	r3, r3, #3
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    1b38:	2b01      	cmp	r3, #1
    1b3a:	d058      	beq.n	1bee <lfclk_spinwait+0xca>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    1b3c:	f005 f9a4 	bl	6e88 <k_is_in_isr>
    1b40:	b928      	cbnz	r0, 1b4e <lfclk_spinwait+0x2a>
 */
static inline bool k_is_pre_kernel(void)
{
	extern bool z_sys_post_kernel; /* in init.c */

	return !z_sys_post_kernel;
    1b42:	4b2e      	ldr	r3, [pc, #184]	; (1bfc <lfclk_spinwait+0xd8>)
    1b44:	781b      	ldrb	r3, [r3, #0]
    1b46:	2b00      	cmp	r3, #0
    1b48:	d041      	beq.n	1bce <lfclk_spinwait+0xaa>
    1b4a:	2300      	movs	r3, #0
    1b4c:	e000      	b.n	1b50 <lfclk_spinwait+0x2c>
    1b4e:	2301      	movs	r3, #1
	int key = isr_mode ? irq_lock() : 0;
    1b50:	461c      	mov	r4, r3
    1b52:	2b00      	cmp	r3, #0
    1b54:	d03d      	beq.n	1bd2 <lfclk_spinwait+0xae>
	__asm__ volatile(
    1b56:	f04f 0320 	mov.w	r3, #32
    1b5a:	f3ef 8611 	mrs	r6, BASEPRI
    1b5e:	f383 8812 	msr	BASEPRI_MAX, r3
    1b62:	f3bf 8f6f 	isb	sy
	if (!isr_mode) {
    1b66:	b924      	cbnz	r4, 1b72 <lfclk_spinwait+0x4e>
    p_reg->INTENCLR = mask;
    1b68:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1b6c:	2202      	movs	r2, #2
    1b6e:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    1b72:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    1b76:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    1b7a:	f003 0303 	and.w	r3, r3, #3
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    1b7e:	f8d2 2418 	ldr.w	r2, [r2, #1048]	; 0x418
    1b82:	f412 3f80 	tst.w	r2, #65536	; 0x10000
    1b86:	d12b      	bne.n	1be0 <lfclk_spinwait+0xbc>
    return false;
    1b88:	2200      	movs	r2, #0
	while (!(nrfx_clock_is_running(d, (void *)&type)
    1b8a:	b11a      	cbz	r2, 1b94 <lfclk_spinwait+0x70>
    1b8c:	2b01      	cmp	r3, #1
    1b8e:	d029      	beq.n	1be4 <lfclk_spinwait+0xc0>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    1b90:	2d01      	cmp	r5, #1
    1b92:	d027      	beq.n	1be4 <lfclk_spinwait+0xc0>
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    1b94:	b1fc      	cbz	r4, 1bd6 <lfclk_spinwait+0xb2>
 *
 * @return N/A
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    1b96:	4630      	mov	r0, r6
    1b98:	f7ff fb10 	bl	11bc <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    1b9c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1ba0:	f8d3 3518 	ldr.w	r3, [r3, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    1ba4:	2b00      	cmp	r3, #0
    1ba6:	d1e4      	bne.n	1b72 <lfclk_spinwait+0x4e>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    1ba8:	4b15      	ldr	r3, [pc, #84]	; (1c00 <lfclk_spinwait+0xdc>)
    1baa:	681b      	ldr	r3, [r3, #0]
		    && nrf_clock_event_check(NRF_CLOCK,
    1bac:	2b00      	cmp	r3, #0
    1bae:	d0e0      	beq.n	1b72 <lfclk_spinwait+0x4e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    1bb0:	4b13      	ldr	r3, [pc, #76]	; (1c00 <lfclk_spinwait+0xdc>)
    1bb2:	2200      	movs	r2, #0
    1bb4:	601a      	str	r2, [r3, #0]
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    1bb6:	681b      	ldr	r3, [r3, #0]
    p_reg->LFCLKSRC = (uint32_t)(source);
    1bb8:	2301      	movs	r3, #1
    1bba:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    1bbe:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1bc2:	4a10      	ldr	r2, [pc, #64]	; (1c04 <lfclk_spinwait+0xe0>)
    1bc4:	f8c2 3180 	str.w	r3, [r2, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    1bc8:	4a0f      	ldr	r2, [pc, #60]	; (1c08 <lfclk_spinwait+0xe4>)
    1bca:	6013      	str	r3, [r2, #0]
}
    1bcc:	e7d1      	b.n	1b72 <lfclk_spinwait+0x4e>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    1bce:	2301      	movs	r3, #1
    1bd0:	e7be      	b.n	1b50 <lfclk_spinwait+0x2c>
	int key = isr_mode ? irq_lock() : 0;
    1bd2:	2600      	movs	r6, #0
    1bd4:	e7c7      	b.n	1b66 <lfclk_spinwait+0x42>
	return z_impl_k_sleep(timeout);
    1bd6:	2021      	movs	r0, #33	; 0x21
    1bd8:	2100      	movs	r1, #0
    1bda:	f003 f841 	bl	4c60 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    1bde:	e7dd      	b.n	1b9c <lfclk_spinwait+0x78>
                return true;
    1be0:	2201      	movs	r2, #1
    1be2:	e7d2      	b.n	1b8a <lfclk_spinwait+0x66>
	if (isr_mode) {
    1be4:	b124      	cbz	r4, 1bf0 <lfclk_spinwait+0xcc>
	__asm__ volatile(
    1be6:	f386 8811 	msr	BASEPRI, r6
    1bea:	f3bf 8f6f 	isb	sy
}
    1bee:	bd70      	pop	{r4, r5, r6, pc}
    p_reg->INTENSET = mask;
    1bf0:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1bf4:	2202      	movs	r2, #2
    1bf6:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    1bfa:	e7f8      	b.n	1bee <lfclk_spinwait+0xca>
    1bfc:	20000ae2 	.word	0x20000ae2
    1c00:	40000104 	.word	0x40000104
    1c04:	e000e100 	.word	0xe000e100
    1c08:	40000008 	.word	0x40000008

00001c0c <z_nrf_clock_control_lf_on>:
{
    1c0c:	b510      	push	{r4, lr}
    1c0e:	4604      	mov	r4, r0
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    1c10:	4b10      	ldr	r3, [pc, #64]	; (1c54 <z_nrf_clock_control_lf_on+0x48>)
    1c12:	2101      	movs	r1, #1
    1c14:	f3bf 8f5b 	dmb	ish
    1c18:	e853 2f00 	ldrex	r2, [r3]
    1c1c:	e843 1000 	strex	r0, r1, [r3]
    1c20:	2800      	cmp	r0, #0
    1c22:	d1f9      	bne.n	1c18 <z_nrf_clock_control_lf_on+0xc>
    1c24:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    1c28:	b11a      	cbz	r2, 1c32 <z_nrf_clock_control_lf_on+0x26>
	switch (start_mode) {
    1c2a:	1e63      	subs	r3, r4, #1
    1c2c:	2b01      	cmp	r3, #1
    1c2e:	d90c      	bls.n	1c4a <z_nrf_clock_control_lf_on+0x3e>
}
    1c30:	bd10      	pop	{r4, pc}
				get_onoff_manager(CLOCK_DEVICE,
    1c32:	4809      	ldr	r0, [pc, #36]	; (1c58 <z_nrf_clock_control_lf_on+0x4c>)
    1c34:	f004 fa2d 	bl	6092 <get_onoff_manager>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    1c38:	4908      	ldr	r1, [pc, #32]	; (1c5c <z_nrf_clock_control_lf_on+0x50>)
    1c3a:	2300      	movs	r3, #0
    1c3c:	604b      	str	r3, [r1, #4]
    1c3e:	60cb      	str	r3, [r1, #12]
    1c40:	2301      	movs	r3, #1
    1c42:	608b      	str	r3, [r1, #8]
		err = onoff_request(mgr, &cli);
    1c44:	f003 ffcd 	bl	5be2 <onoff_request>
    1c48:	e7ef      	b.n	1c2a <z_nrf_clock_control_lf_on+0x1e>
		lfclk_spinwait(start_mode);
    1c4a:	4620      	mov	r0, r4
    1c4c:	f7ff ff6a 	bl	1b24 <lfclk_spinwait>
		break;
    1c50:	e7ee      	b.n	1c30 <z_nrf_clock_control_lf_on+0x24>
    1c52:	bf00      	nop
    1c54:	200004bc 	.word	0x200004bc
    1c58:	00007478 	.word	0x00007478
    1c5c:	20000458 	.word	0x20000458

00001c60 <console_out>:
 *
 * @return The character passed as input.
 */

static int console_out(int c)
{
    1c60:	b510      	push	{r4, lr}
    1c62:	4604      	mov	r4, r0
		return c;
	}

#endif  /* CONFIG_UART_CONSOLE_DEBUG_SERVER_HOOKS */

	if ('\n' == c) {
    1c64:	280a      	cmp	r0, #10
    1c66:	d007      	beq.n	1c78 <console_out+0x18>
		uart_poll_out(uart_console_dev, '\r');
	}
	uart_poll_out(uart_console_dev, c);
    1c68:	4b07      	ldr	r3, [pc, #28]	; (1c88 <console_out+0x28>)
    1c6a:	6818      	ldr	r0, [r3, #0]
    1c6c:	b2e1      	uxtb	r1, r4
				      unsigned char out_char);

static inline void z_impl_uart_poll_out(const struct device *dev,
						unsigned char out_char)
{
	const struct uart_driver_api *api =
    1c6e:	6883      	ldr	r3, [r0, #8]
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    1c70:	685b      	ldr	r3, [r3, #4]
    1c72:	4798      	blx	r3

	return c;
}
    1c74:	4620      	mov	r0, r4
    1c76:	bd10      	pop	{r4, pc}
		uart_poll_out(uart_console_dev, '\r');
    1c78:	4b03      	ldr	r3, [pc, #12]	; (1c88 <console_out+0x28>)
    1c7a:	6818      	ldr	r0, [r3, #0]
	const struct uart_driver_api *api =
    1c7c:	6883      	ldr	r3, [r0, #8]
	api->poll_out(dev, out_char);
    1c7e:	685b      	ldr	r3, [r3, #4]
    1c80:	210d      	movs	r1, #13
    1c82:	4798      	blx	r3
		return;
	}
#endif
	compiler_barrier();
	z_impl_uart_poll_out(dev, out_char);
}
    1c84:	e7f0      	b.n	1c68 <console_out+0x8>
    1c86:	bf00      	nop
    1c88:	200004c0 	.word	0x200004c0

00001c8c <uart_console_hook_install>:
 *
 * @return N/A
 */

static void uart_console_hook_install(void)
{
    1c8c:	b510      	push	{r4, lr}
	__stdout_hook_install(console_out);
    1c8e:	4c04      	ldr	r4, [pc, #16]	; (1ca0 <uart_console_hook_install+0x14>)
    1c90:	4620      	mov	r0, r4
    1c92:	f7ff fe2b 	bl	18ec <__stdout_hook_install>
	__printk_hook_install(console_out);
    1c96:	4620      	mov	r0, r4
    1c98:	f7fe fc16 	bl	4c8 <__printk_hook_install>
}
    1c9c:	bd10      	pop	{r4, pc}
    1c9e:	bf00      	nop
    1ca0:	00001c61 	.word	0x00001c61

00001ca4 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    1ca4:	b508      	push	{r3, lr}

	ARG_UNUSED(arg);

	/* Claim console device */
	uart_console_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console));
    1ca6:	4806      	ldr	r0, [pc, #24]	; (1cc0 <uart_console_init+0x1c>)
    1ca8:	4b06      	ldr	r3, [pc, #24]	; (1cc4 <uart_console_init+0x20>)
    1caa:	6018      	str	r0, [r3, #0]
 *
 * @return a non-positive integer as documented in device_usable_check().
 */
static inline int z_device_usable_check(const struct device *dev)
{
	return z_device_ready(dev) ? 0 : -ENODEV;
    1cac:	f005 f8a7 	bl	6dfe <z_device_ready>
    1cb0:	b118      	cbz	r0, 1cba <uart_console_init+0x16>
	if (!device_is_ready(uart_console_dev)) {
		return -ENODEV;
	}

	uart_console_hook_install();
    1cb2:	f7ff ffeb 	bl	1c8c <uart_console_hook_install>

	return 0;
    1cb6:	2000      	movs	r0, #0
}
    1cb8:	bd08      	pop	{r3, pc}
		return -ENODEV;
    1cba:	f06f 0012 	mvn.w	r0, #18
    1cbe:	e7fb      	b.n	1cb8 <uart_console_init+0x14>
    1cc0:	000074a8 	.word	0x000074a8
    1cc4:	200004c0 	.word	0x200004c0

00001cc8 <gpio_nrfx_config>:
	return res;
}

static int gpio_nrfx_config(const struct device *port,
			    gpio_pin_t pin, gpio_flags_t flags)
{
    1cc8:	b4f0      	push	{r4, r5, r6, r7}
	return port->config;
    1cca:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    1ccc:	685f      	ldr	r7, [r3, #4]
	nrf_gpio_pin_pull_t pull;
	nrf_gpio_pin_drive_t drive;
	nrf_gpio_pin_dir_t dir;
	nrf_gpio_pin_input_t input;

	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1cce:	4b37      	ldr	r3, [pc, #220]	; (1dac <gpio_nrfx_config+0xe4>)
    1cd0:	4013      	ands	r3, r2
    1cd2:	4c37      	ldr	r4, [pc, #220]	; (1db0 <gpio_nrfx_config+0xe8>)
    1cd4:	42a3      	cmp	r3, r4
    1cd6:	d027      	beq.n	1d28 <gpio_nrfx_config+0x60>
    1cd8:	d812      	bhi.n	1d00 <gpio_nrfx_config+0x38>
    1cda:	2b06      	cmp	r3, #6
    1cdc:	d026      	beq.n	1d2c <gpio_nrfx_config+0x64>
    1cde:	d904      	bls.n	1cea <gpio_nrfx_config+0x22>
    1ce0:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    1ce4:	d109      	bne.n	1cfa <gpio_nrfx_config+0x32>
	case GPIO_DS_DFLT_LOW | GPIO_OPEN_DRAIN:
		drive = NRF_GPIO_PIN_S0D1;
		break;

	case GPIO_DS_ALT_LOW | GPIO_DS_DFLT_HIGH:
		drive = NRF_GPIO_PIN_H0S1;
    1ce6:	2401      	movs	r4, #1
    1ce8:	e016      	b.n	1d18 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1cea:	b30b      	cbz	r3, 1d30 <gpio_nrfx_config+0x68>
    1cec:	2b02      	cmp	r3, #2
    1cee:	d101      	bne.n	1cf4 <gpio_nrfx_config+0x2c>
	case GPIO_DS_ALT_LOW | GPIO_OPEN_DRAIN:
		drive = NRF_GPIO_PIN_H0D1;
		break;

	case GPIO_DS_DFLT_HIGH | GPIO_OPEN_SOURCE:
		drive = NRF_GPIO_PIN_D0S1;
    1cf0:	2404      	movs	r4, #4
    1cf2:	e011      	b.n	1d18 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1cf4:	f06f 0015 	mvn.w	r0, #21
    1cf8:	e046      	b.n	1d88 <gpio_nrfx_config+0xc0>
    1cfa:	f06f 0015 	mvn.w	r0, #21
    1cfe:	e043      	b.n	1d88 <gpio_nrfx_config+0xc0>
    1d00:	4c2c      	ldr	r4, [pc, #176]	; (1db4 <gpio_nrfx_config+0xec>)
    1d02:	42a3      	cmp	r3, r4
    1d04:	d016      	beq.n	1d34 <gpio_nrfx_config+0x6c>
    1d06:	f5b3 0fa0 	cmp.w	r3, #5242880	; 0x500000
    1d0a:	d101      	bne.n	1d10 <gpio_nrfx_config+0x48>
		drive = NRF_GPIO_PIN_H0H1;
    1d0c:	2403      	movs	r4, #3
    1d0e:	e003      	b.n	1d18 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1d10:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
    1d14:	d146      	bne.n	1da4 <gpio_nrfx_config+0xdc>
		drive = NRF_GPIO_PIN_S0H1;
    1d16:	2402      	movs	r4, #2

	default:
		return -EINVAL;
	}

	if ((flags & GPIO_PULL_UP) != 0) {
    1d18:	f012 0f10 	tst.w	r2, #16
    1d1c:	d10c      	bne.n	1d38 <gpio_nrfx_config+0x70>
		pull = NRF_GPIO_PIN_PULLUP;
	} else if ((flags & GPIO_PULL_DOWN) != 0) {
    1d1e:	f012 0f20 	tst.w	r2, #32
    1d22:	d033      	beq.n	1d8c <gpio_nrfx_config+0xc4>
		pull = NRF_GPIO_PIN_PULLDOWN;
    1d24:	2501      	movs	r5, #1
    1d26:	e008      	b.n	1d3a <gpio_nrfx_config+0x72>
		drive = NRF_GPIO_PIN_H0D1;
    1d28:	2407      	movs	r4, #7
    1d2a:	e7f5      	b.n	1d18 <gpio_nrfx_config+0x50>
		drive = NRF_GPIO_PIN_S0D1;
    1d2c:	2406      	movs	r4, #6
    1d2e:	e7f3      	b.n	1d18 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1d30:	2400      	movs	r4, #0
    1d32:	e7f1      	b.n	1d18 <gpio_nrfx_config+0x50>
		drive = NRF_GPIO_PIN_D0H1;
    1d34:	2405      	movs	r4, #5
    1d36:	e7ef      	b.n	1d18 <gpio_nrfx_config+0x50>
		pull = NRF_GPIO_PIN_PULLUP;
    1d38:	2503      	movs	r5, #3
	} else {
		pull = NRF_GPIO_PIN_NOPULL;
	}

	dir = ((flags & GPIO_OUTPUT) != 0)
    1d3a:	f3c2 2340 	ubfx	r3, r2, #9, #1
	      ? NRF_GPIO_PIN_DIR_OUTPUT
	      : NRF_GPIO_PIN_DIR_INPUT;

	input = ((flags & GPIO_INPUT) != 0)
		? NRF_GPIO_PIN_INPUT_CONNECT
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
    1d3e:	f412 7f80 	tst.w	r2, #256	; 0x100
    1d42:	bf0c      	ite	eq
    1d44:	2601      	moveq	r6, #1
    1d46:	2600      	movne	r6, #0

	if ((flags & GPIO_OUTPUT) != 0) {
    1d48:	f412 7f00 	tst.w	r2, #512	; 0x200
    1d4c:	d006      	beq.n	1d5c <gpio_nrfx_config+0x94>
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
    1d4e:	f412 6f00 	tst.w	r2, #2048	; 0x800
    1d52:	d01d      	beq.n	1d90 <gpio_nrfx_config+0xc8>
			nrf_gpio_port_out_set(reg, BIT(pin));
    1d54:	2201      	movs	r2, #1
    1d56:	408a      	lsls	r2, r1
}


NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
{
    p_reg->OUTSET = set_mask;
    1d58:	f8c7 2508 	str.w	r2, [r7, #1288]	; 0x508
	return port->config;
    1d5c:	6842      	ldr	r2, [r0, #4]
		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
			nrf_gpio_port_out_clear(reg, BIT(pin));
		}
	}

	nrf_gpio_cfg(NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin),
    1d5e:	7a12      	ldrb	r2, [r2, #8]
    1d60:	f001 011f 	and.w	r1, r1, #31
    1d64:	ea41 1242 	orr.w	r2, r1, r2, lsl #5
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;

    return pin_number >> 5;
    1d68:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    1d6a:	2a01      	cmp	r2, #1
    1d6c:	d018      	beq.n	1da0 <gpio_nrfx_config+0xd8>
        case 0: return NRF_P0;
    1d6e:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    1d72:	ea43 0346 	orr.w	r3, r3, r6, lsl #1
           ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) |
    1d76:	ea43 0385 	orr.w	r3, r3, r5, lsl #2
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    1d7a:	ea43 2304 	orr.w	r3, r3, r4, lsl #8
    reg->PIN_CNF[pin_number] = cnf;
    1d7e:	f501 71e0 	add.w	r1, r1, #448	; 0x1c0
    1d82:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
		     dir, input, pull, drive, NRF_GPIO_PIN_NOSENSE);

	return 0;
    1d86:	2000      	movs	r0, #0
}
    1d88:	bcf0      	pop	{r4, r5, r6, r7}
    1d8a:	4770      	bx	lr
		pull = NRF_GPIO_PIN_NOPULL;
    1d8c:	2500      	movs	r5, #0
    1d8e:	e7d4      	b.n	1d3a <gpio_nrfx_config+0x72>
		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
    1d90:	f412 6f80 	tst.w	r2, #1024	; 0x400
    1d94:	d0e2      	beq.n	1d5c <gpio_nrfx_config+0x94>
			nrf_gpio_port_out_clear(reg, BIT(pin));
    1d96:	2201      	movs	r2, #1
    1d98:	408a      	lsls	r2, r1
    p_reg->OUTCLR = clr_mask;
    1d9a:	f8c7 250c 	str.w	r2, [r7, #1292]	; 0x50c
}
    1d9e:	e7dd      	b.n	1d5c <gpio_nrfx_config+0x94>
        case 1: return NRF_P1;
    1da0:	4a05      	ldr	r2, [pc, #20]	; (1db8 <gpio_nrfx_config+0xf0>)
    1da2:	e7e6      	b.n	1d72 <gpio_nrfx_config+0xaa>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1da4:	f06f 0015 	mvn.w	r0, #21
    1da8:	e7ee      	b.n	1d88 <gpio_nrfx_config+0xc0>
    1daa:	bf00      	nop
    1dac:	00f00006 	.word	0x00f00006
    1db0:	00100006 	.word	0x00100006
    1db4:	00400002 	.word	0x00400002
    1db8:	50000300 	.word	0x50000300

00001dbc <cfg_level_pins>:
	 */
	return out;
}

static void cfg_level_pins(const struct device *port)
{
    1dbc:	b4f0      	push	{r4, r5, r6, r7}
	return port->data;
    1dbe:	6905      	ldr	r5, [r0, #16]
	return port->config;
    1dc0:	6846      	ldr	r6, [r0, #4]
	uint32_t out = data->pin_int_en;
    1dc2:	68e9      	ldr	r1, [r5, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    1dc4:	696a      	ldr	r2, [r5, #20]
    1dc6:	69ab      	ldr	r3, [r5, #24]
    1dc8:	4313      	orrs	r3, r2
    1dca:	ea21 0103 	bic.w	r1, r1, r3
	const struct gpio_nrfx_data *data = get_port_data(port);
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
	uint32_t pin = 0U;
	uint32_t bit = 1U << pin;
    1dce:	2301      	movs	r3, #1
	uint32_t pin = 0U;
    1dd0:	2000      	movs	r0, #0
	uint32_t level_pins = get_level_pins(port);

	/* Configure sense detection on all pins that use it. */
	while (level_pins) {
    1dd2:	e011      	b.n	1df8 <cfg_level_pins+0x3c>
		return NRF_GPIO_PIN_SENSE_HIGH;
    1dd4:	f04f 0c02 	mov.w	ip, #2
    1dd8:	e01d      	b.n	1e16 <cfg_level_pins+0x5a>
    1dda:	4f14      	ldr	r7, [pc, #80]	; (1e2c <cfg_level_pins+0x70>)
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    1ddc:	f504 74e0 	add.w	r4, r4, #448	; 0x1c0
    1de0:	f857 2024 	ldr.w	r2, [r7, r4, lsl #2]
    1de4:	f422 3240 	bic.w	r2, r2, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    1de8:	ea42 420c 	orr.w	r2, r2, ip, lsl #16
    1dec:	f847 2024 	str.w	r2, [r7, r4, lsl #2]
		if (level_pins & bit) {
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
			uint32_t sense = sense_for_pin(data, pin);

			nrf_gpio_cfg_sense_set(abs_pin, sense);
			level_pins &= ~bit;
    1df0:	ea21 0103 	bic.w	r1, r1, r3
		}
		++pin;
    1df4:	3001      	adds	r0, #1
		bit <<= 1;
    1df6:	005b      	lsls	r3, r3, #1
	while (level_pins) {
    1df8:	b1a9      	cbz	r1, 1e26 <cfg_level_pins+0x6a>
		if (level_pins & bit) {
    1dfa:	420b      	tst	r3, r1
    1dfc:	d0fa      	beq.n	1df4 <cfg_level_pins+0x38>
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    1dfe:	7a34      	ldrb	r4, [r6, #8]
    1e00:	f000 021f 	and.w	r2, r0, #31
    1e04:	ea42 1244 	orr.w	r2, r2, r4, lsl #5
	if ((BIT(pin) & data->int_active_level) != 0U) {
    1e08:	692c      	ldr	r4, [r5, #16]
    1e0a:	40c4      	lsrs	r4, r0
    1e0c:	f014 0f01 	tst.w	r4, #1
    1e10:	d1e0      	bne.n	1dd4 <cfg_level_pins+0x18>
	return NRF_GPIO_PIN_SENSE_LOW;
    1e12:	f04f 0c03 	mov.w	ip, #3
    *p_pin = pin_number & 0x1F;
    1e16:	f002 041f 	and.w	r4, r2, #31
    return pin_number >> 5;
    1e1a:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    1e1c:	2a01      	cmp	r2, #1
    1e1e:	d0dc      	beq.n	1dda <cfg_level_pins+0x1e>
        case 0: return NRF_P0;
    1e20:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    1e24:	e7da      	b.n	1ddc <cfg_level_pins+0x20>
	}
}
    1e26:	bcf0      	pop	{r4, r5, r6, r7}
    1e28:	4770      	bx	lr
    1e2a:	bf00      	nop
    1e2c:	50000300 	.word	0x50000300

00001e30 <check_level_trigger_pins>:
 *
 * @return Bitmask where 1 marks pin as trigger source.
 */
static uint32_t check_level_trigger_pins(const struct device *port,
					 uint32_t *sense_levels)
{
    1e30:	b5f0      	push	{r4, r5, r6, r7, lr}
    1e32:	468c      	mov	ip, r1
	return port->data;
    1e34:	6903      	ldr	r3, [r0, #16]
	return port->config;
    1e36:	6841      	ldr	r1, [r0, #4]
	uint32_t out = data->pin_int_en;
    1e38:	68df      	ldr	r7, [r3, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    1e3a:	695a      	ldr	r2, [r3, #20]
    1e3c:	6998      	ldr	r0, [r3, #24]
    1e3e:	4302      	orrs	r2, r0
    1e40:	ea27 0702 	bic.w	r7, r7, r2
	struct gpio_nrfx_data *data = get_port_data(port);
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
	uint32_t level_pins = get_level_pins(port);
	uint32_t port_in = nrf_gpio_port_in_read(cfg->port);
    1e44:	684a      	ldr	r2, [r1, #4]
    return p_reg->IN;
    1e46:	f8d2 2510 	ldr.w	r2, [r2, #1296]	; 0x510

	/* Extract which pins have logic level same as interrupt trigger level.
	 */
	uint32_t pin_states = ~(port_in ^ data->int_active_level);
    1e4a:	6918      	ldr	r0, [r3, #16]
    1e4c:	4050      	eors	r0, r2

	/* Discard pins that aren't configured for level. */
	uint32_t out = pin_states & level_pins;
    1e4e:	ea27 0000 	bic.w	r0, r7, r0
	uint32_t pin = 0U;
	uint32_t bit = 1U << pin;

	uint32_t port_latch = 0;

	uint32_t check_pins = level_pins;
    1e52:	463c      	mov	r4, r7
	uint32_t bit = 1U << pin;
    1e54:	2301      	movs	r3, #1
	uint32_t pin = 0U;
    1e56:	2500      	movs	r5, #0
#if IS_ENABLED(CONFIG_GPIO_NRF_INT_EDGE_USING_SENSE)
	/* Read LATCH, which will tell us which pin has changed its state. */
	port_latch = cfg->port->LATCH;
#endif

	while (check_pins) {
    1e58:	e015      	b.n	1e86 <check_level_trigger_pins+0x56>
        case 1: return NRF_P1;
    1e5a:	f8df e074 	ldr.w	lr, [pc, #116]	; 1ed0 <check_level_trigger_pins+0xa0>
    1e5e:	e025      	b.n	1eac <check_level_trigger_pins+0x7c>
    *p_pin = pin_number & 0x1F;
    1e60:	f002 061f 	and.w	r6, r2, #31
    return pin_number >> 5;
    1e64:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    1e66:	2a01      	cmp	r2, #1
    1e68:	d02e      	beq.n	1ec8 <check_level_trigger_pins+0x98>
        case 0: return NRF_P0;
    1e6a:	f04f 4ea0 	mov.w	lr, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    1e6e:	f506 72e0 	add.w	r2, r6, #448	; 0x1c0
    1e72:	f85e 6022 	ldr.w	r6, [lr, r2, lsl #2]
    1e76:	f426 3640 	bic.w	r6, r6, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    1e7a:	f84e 6022 	str.w	r6, [lr, r2, lsl #2]
					*sense_levels |= bit;
				}
			}

			nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
			check_pins &= ~bit;
    1e7e:	ea24 0403 	bic.w	r4, r4, r3
		}
		++pin;
    1e82:	3501      	adds	r5, #1
		bit <<= 1;
    1e84:	005b      	lsls	r3, r3, #1
	while (check_pins) {
    1e86:	b314      	cbz	r4, 1ece <check_level_trigger_pins+0x9e>
		if (check_pins & bit) {
    1e88:	4223      	tst	r3, r4
    1e8a:	d0fa      	beq.n	1e82 <check_level_trigger_pins+0x52>
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    1e8c:	7a0e      	ldrb	r6, [r1, #8]
    1e8e:	f005 021f 	and.w	r2, r5, #31
    1e92:	ea42 1246 	orr.w	r2, r2, r6, lsl #5
			if (!(level_pins & bit)) {
    1e96:	423b      	tst	r3, r7
    1e98:	d1e2      	bne.n	1e60 <check_level_trigger_pins+0x30>
    *p_pin = pin_number & 0x1F;
    1e9a:	f002 061f 	and.w	r6, r2, #31
    return pin_number >> 5;
    1e9e:	ea4f 1e52 	mov.w	lr, r2, lsr #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    1ea2:	f1be 0f01 	cmp.w	lr, #1
    1ea6:	d0d8      	beq.n	1e5a <check_level_trigger_pins+0x2a>
        case 0: return NRF_P0;
    1ea8:	f04f 4ea0 	mov.w	lr, #1342177280	; 0x50000000
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    1eac:	f506 76e0 	add.w	r6, r6, #448	; 0x1c0
    1eb0:	f85e 6026 	ldr.w	r6, [lr, r6, lsl #2]
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    1eb4:	f3c6 4601 	ubfx	r6, r6, #16, #2
				if (high) {
    1eb8:	2e02      	cmp	r6, #2
    1eba:	d1d1      	bne.n	1e60 <check_level_trigger_pins+0x30>
					*sense_levels |= bit;
    1ebc:	f8dc 6000 	ldr.w	r6, [ip]
    1ec0:	431e      	orrs	r6, r3
    1ec2:	f8cc 6000 	str.w	r6, [ip]
    1ec6:	e7cb      	b.n	1e60 <check_level_trigger_pins+0x30>
        case 1: return NRF_P1;
    1ec8:	f8df e004 	ldr.w	lr, [pc, #4]	; 1ed0 <check_level_trigger_pins+0xa0>
    1ecc:	e7cf      	b.n	1e6e <check_level_trigger_pins+0x3e>
	 */
	cfg->port->LATCH = port_latch;
#endif

	return out;
}
    1ece:	bdf0      	pop	{r4, r5, r6, r7, pc}
    1ed0:	50000300 	.word	0x50000300

00001ed4 <gpiote_pin_cleanup>:
{
    1ed4:	b510      	push	{r4, lr}
    p_reg->INTENCLR = mask;
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask)
{
    return p_reg->INTENSET & mask;
    1ed6:	4b14      	ldr	r3, [pc, #80]	; (1f28 <gpiote_pin_cleanup+0x54>)
    1ed8:	f8d3 4304 	ldr.w	r4, [r3, #772]	; 0x304
    1edc:	b2e4      	uxtb	r4, r4
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    1ede:	2300      	movs	r3, #0
    1ee0:	e000      	b.n	1ee4 <gpiote_pin_cleanup+0x10>
    1ee2:	3301      	adds	r3, #1
    1ee4:	2b07      	cmp	r3, #7
    1ee6:	d81d      	bhi.n	1f24 <gpiote_pin_cleanup+0x50>
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
{
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    1ee8:	f503 72a2 	add.w	r2, r3, #324	; 0x144
    1eec:	490e      	ldr	r1, [pc, #56]	; (1f28 <gpiote_pin_cleanup+0x54>)
    1eee:	f851 2022 	ldr.w	r2, [r1, r2, lsl #2]
    1ef2:	f3c2 2205 	ubfx	r2, r2, #8, #6
		if ((nrf_gpiote_event_pin_get(NRF_GPIOTE, i) == abs_pin)
    1ef6:	4290      	cmp	r0, r2
    1ef8:	d1f3      	bne.n	1ee2 <gpiote_pin_cleanup+0xe>
		    && (intenset & BIT(i))) {
    1efa:	fa24 f203 	lsr.w	r2, r4, r3
    1efe:	f012 0f01 	tst.w	r2, #1
    1f02:	d0ee      	beq.n	1ee2 <gpiote_pin_cleanup+0xe>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
    1f04:	460a      	mov	r2, r1
    1f06:	f503 70a2 	add.w	r0, r3, #324	; 0x144
    1f0a:	f851 1020 	ldr.w	r1, [r1, r0, lsl #2]
    1f0e:	f021 0101 	bic.w	r1, r1, #1
    1f12:	f842 1020 	str.w	r1, [r2, r0, lsl #2]
			nrf_gpiote_int_disable(NRF_GPIOTE, BIT(i));
    1f16:	2101      	movs	r1, #1
    1f18:	4099      	lsls	r1, r3
    p_reg->INTENCLR = mask;
    1f1a:	f8c2 1308 	str.w	r1, [r2, #776]	; 0x308
			nrfx_gpiote_channel_free(i);
    1f1e:	b2d8      	uxtb	r0, r3
    1f20:	f001 fad6 	bl	34d0 <nrfx_gpiote_channel_free>
}
    1f24:	bd10      	pop	{r4, pc}
    1f26:	bf00      	nop
    1f28:	40006000 	.word	0x40006000

00001f2c <gpiote_channel_alloc>:
{
    1f2c:	b570      	push	{r4, r5, r6, lr}
    1f2e:	b082      	sub	sp, #8
    1f30:	4604      	mov	r4, r0
    1f32:	460d      	mov	r5, r1
	if (nrfx_gpiote_channel_alloc(&channel) != NRFX_SUCCESS) {
    1f34:	f10d 0007 	add.w	r0, sp, #7
    1f38:	f001 fae6 	bl	3508 <nrfx_gpiote_channel_alloc>
    1f3c:	4b1c      	ldr	r3, [pc, #112]	; (1fb0 <gpiote_channel_alloc+0x84>)
    1f3e:	4298      	cmp	r0, r3
    1f40:	d132      	bne.n	1fa8 <gpiote_channel_alloc+0x7c>
	nrf_gpiote_event_t evt = offsetof(NRF_GPIOTE_Type, EVENTS_IN[channel]);
    1f42:	f89d 3007 	ldrb.w	r3, [sp, #7]
    1f46:	f103 0240 	add.w	r2, r3, #64	; 0x40
    1f4a:	0092      	lsls	r2, r2, #2
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    1f4c:	4e19      	ldr	r6, [pc, #100]	; (1fb4 <gpiote_channel_alloc+0x88>)
    1f4e:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    1f52:	f856 1023 	ldr.w	r1, [r6, r3, lsl #2]
    1f56:	f421 314f 	bic.w	r1, r1, #211968	; 0x33c00
    1f5a:	f421 7140 	bic.w	r1, r1, #768	; 0x300
    1f5e:	f846 1023 	str.w	r1, [r6, r3, lsl #2]
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    1f62:	f856 1023 	ldr.w	r1, [r6, r3, lsl #2]
    1f66:	0224      	lsls	r4, r4, #8
    1f68:	f404 547c 	and.w	r4, r4, #16128	; 0x3f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
    1f6c:	042d      	lsls	r5, r5, #16
    1f6e:	f405 3540 	and.w	r5, r5, #196608	; 0x30000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    1f72:	432c      	orrs	r4, r5
    1f74:	430c      	orrs	r4, r1
    1f76:	f846 4023 	str.w	r4, [r6, r3, lsl #2]
    return ((uint32_t)p_reg + event);
    1f7a:	f102 4380 	add.w	r3, r2, #1073741824	; 0x40000000
    1f7e:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    1f82:	2000      	movs	r0, #0
    1f84:	6018      	str	r0, [r3, #0]
    1f86:	681b      	ldr	r3, [r3, #0]
	nrf_gpiote_event_enable(NRF_GPIOTE, channel);
    1f88:	f89d 1007 	ldrb.w	r1, [sp, #7]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    1f8c:	f501 73a2 	add.w	r3, r1, #324	; 0x144
    1f90:	f856 2023 	ldr.w	r2, [r6, r3, lsl #2]
    1f94:	f042 0201 	orr.w	r2, r2, #1
    1f98:	f846 2023 	str.w	r2, [r6, r3, lsl #2]
	nrf_gpiote_int_enable(NRF_GPIOTE, BIT(channel));
    1f9c:	2301      	movs	r3, #1
    1f9e:	408b      	lsls	r3, r1
    p_reg->INTENSET = mask;
    1fa0:	f8c6 3304 	str.w	r3, [r6, #772]	; 0x304
}
    1fa4:	b002      	add	sp, #8
    1fa6:	bd70      	pop	{r4, r5, r6, pc}
		return -ENODEV;
    1fa8:	f06f 0012 	mvn.w	r0, #18
    1fac:	e7fa      	b.n	1fa4 <gpiote_channel_alloc+0x78>
    1fae:	bf00      	nop
    1fb0:	0bad0000 	.word	0x0bad0000
    1fb4:	40006000 	.word	0x40006000

00001fb8 <gpiote_pin_int_cfg>:
{
    1fb8:	b570      	push	{r4, r5, r6, lr}
    1fba:	460d      	mov	r5, r1
	return port->data;
    1fbc:	6906      	ldr	r6, [r0, #16]
	return port->config;
    1fbe:	6843      	ldr	r3, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    1fc0:	7a1b      	ldrb	r3, [r3, #8]
    1fc2:	f001 041f 	and.w	r4, r1, #31
    1fc6:	ea44 1443 	orr.w	r4, r4, r3, lsl #5
	gpiote_pin_cleanup(abs_pin);
    1fca:	4620      	mov	r0, r4
    1fcc:	f7ff ff82 	bl	1ed4 <gpiote_pin_cleanup>
    *p_pin = pin_number & 0x1F;
    1fd0:	f004 001f 	and.w	r0, r4, #31
    return pin_number >> 5;
    1fd4:	0963      	lsrs	r3, r4, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    1fd6:	2b01      	cmp	r3, #1
    1fd8:	d020      	beq.n	201c <gpiote_pin_int_cfg+0x64>
        case 0: return NRF_P0;
    1fda:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    1fde:	f500 71e0 	add.w	r1, r0, #448	; 0x1c0
    1fe2:	f852 3021 	ldr.w	r3, [r2, r1, lsl #2]
    1fe6:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    1fea:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
	if (data->pin_int_en & BIT(pin)) {
    1fee:	68f3      	ldr	r3, [r6, #12]
    1ff0:	40eb      	lsrs	r3, r5
    1ff2:	f013 0f01 	tst.w	r3, #1
    1ff6:	d02f      	beq.n	2058 <gpiote_pin_int_cfg+0xa0>
		if (data->trig_edge & BIT(pin)) {
    1ff8:	6973      	ldr	r3, [r6, #20]
    1ffa:	40eb      	lsrs	r3, r5
    1ffc:	f013 0f01 	tst.w	r3, #1
    2000:	d015      	beq.n	202e <gpiote_pin_int_cfg+0x76>
				if (data->double_edge & BIT(pin)) {
    2002:	69b3      	ldr	r3, [r6, #24]
    2004:	40eb      	lsrs	r3, r5
    2006:	f013 0f01 	tst.w	r3, #1
    200a:	d109      	bne.n	2020 <gpiote_pin_int_cfg+0x68>
				} else if ((data->int_active_level & BIT(pin)) != 0U) {
    200c:	6931      	ldr	r1, [r6, #16]
    200e:	fa21 f505 	lsr.w	r5, r1, r5
    2012:	f015 0f01 	tst.w	r5, #1
    2016:	d008      	beq.n	202a <gpiote_pin_int_cfg+0x72>
					pol = NRF_GPIOTE_POLARITY_LOTOHI;
    2018:	2101      	movs	r1, #1
    201a:	e002      	b.n	2022 <gpiote_pin_int_cfg+0x6a>
        case 1: return NRF_P1;
    201c:	4a0f      	ldr	r2, [pc, #60]	; (205c <gpiote_pin_int_cfg+0xa4>)
    201e:	e7de      	b.n	1fde <gpiote_pin_int_cfg+0x26>
					pol = NRF_GPIOTE_POLARITY_TOGGLE;
    2020:	2103      	movs	r1, #3
				res = gpiote_channel_alloc(abs_pin, pol);
    2022:	4620      	mov	r0, r4
    2024:	f7ff ff82 	bl	1f2c <gpiote_channel_alloc>
    2028:	e017      	b.n	205a <gpiote_pin_int_cfg+0xa2>
					pol = NRF_GPIOTE_POLARITY_HITOLO;
    202a:	2102      	movs	r1, #2
    202c:	e7f9      	b.n	2022 <gpiote_pin_int_cfg+0x6a>
	if ((BIT(pin) & data->int_active_level) != 0U) {
    202e:	6931      	ldr	r1, [r6, #16]
    2030:	fa21 f505 	lsr.w	r5, r1, r5
    2034:	f015 0f01 	tst.w	r5, #1
    2038:	d10c      	bne.n	2054 <gpiote_pin_int_cfg+0x9c>
	return NRF_GPIO_PIN_SENSE_LOW;
    203a:	2103      	movs	r1, #3
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    203c:	f500 70e0 	add.w	r0, r0, #448	; 0x1c0
    2040:	f852 3020 	ldr.w	r3, [r2, r0, lsl #2]
    2044:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    2048:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
    204c:	f842 3020 	str.w	r3, [r2, r0, lsl #2]
	int res = 0;
    2050:	2000      	movs	r0, #0
}
    2052:	e002      	b.n	205a <gpiote_pin_int_cfg+0xa2>
		return NRF_GPIO_PIN_SENSE_HIGH;
    2054:	2102      	movs	r1, #2
    2056:	e7f1      	b.n	203c <gpiote_pin_int_cfg+0x84>
	int res = 0;
    2058:	2000      	movs	r0, #0
}
    205a:	bd70      	pop	{r4, r5, r6, pc}
    205c:	50000300 	.word	0x50000300

00002060 <gpio_nrfx_pin_interrupt_configure>:
{
    2060:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	return port->data;
    2062:	6904      	ldr	r4, [r0, #16]
	return port->config;
    2064:	6845      	ldr	r5, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    2066:	7a2e      	ldrb	r6, [r5, #8]
    2068:	f001 051f 	and.w	r5, r1, #31
    206c:	ea45 1546 	orr.w	r5, r5, r6, lsl #5
	if (!IS_ENABLED(CONFIG_GPIO_NRF_INT_EDGE_USING_SENSE) &&
    2070:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    2074:	d025      	beq.n	20c2 <gpio_nrfx_pin_interrupt_configure+0x62>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    2076:	f5b2 5f00 	cmp.w	r2, #8192	; 0x2000
    207a:	d035      	beq.n	20e8 <gpio_nrfx_pin_interrupt_configure+0x88>
    207c:	68e5      	ldr	r5, [r4, #12]
    207e:	2601      	movs	r6, #1
    2080:	408e      	lsls	r6, r1
    2082:	4335      	orrs	r5, r6
    2084:	60e5      	str	r5, [r4, #12]
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    2086:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    208a:	d033      	beq.n	20f4 <gpio_nrfx_pin_interrupt_configure+0x94>
    208c:	6962      	ldr	r2, [r4, #20]
    208e:	2501      	movs	r5, #1
    2090:	408d      	lsls	r5, r1
    2092:	ea22 0205 	bic.w	r2, r2, r5
    2096:	6162      	str	r2, [r4, #20]
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
    2098:	f5b3 2fc0 	cmp.w	r3, #393216	; 0x60000
    209c:	d02f      	beq.n	20fe <gpio_nrfx_pin_interrupt_configure+0x9e>
    209e:	69a2      	ldr	r2, [r4, #24]
    20a0:	2501      	movs	r5, #1
    20a2:	408d      	lsls	r5, r1
    20a4:	ea22 0205 	bic.w	r2, r2, r5
    20a8:	61a2      	str	r2, [r4, #24]
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    20aa:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
    20ae:	d02b      	beq.n	2108 <gpio_nrfx_pin_interrupt_configure+0xa8>
    20b0:	6923      	ldr	r3, [r4, #16]
    20b2:	2201      	movs	r2, #1
    20b4:	408a      	lsls	r2, r1
    20b6:	ea23 0302 	bic.w	r3, r3, r2
    20ba:	6123      	str	r3, [r4, #16]
	return gpiote_pin_int_cfg(port, pin);
    20bc:	f7ff ff7c 	bl	1fb8 <gpiote_pin_int_cfg>
}
    20c0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    *p_pin = pin_number & 0x1F;
    20c2:	f005 061f 	and.w	r6, r5, #31
    return pin_number >> 5;
    20c6:	096d      	lsrs	r5, r5, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    20c8:	2d01      	cmp	r5, #1
    20ca:	d00b      	beq.n	20e4 <gpio_nrfx_pin_interrupt_configure+0x84>
        case 0: return NRF_P0;
    20cc:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    20d0:	f506 75e0 	add.w	r5, r6, #448	; 0x1c0
    20d4:	f857 5025 	ldr.w	r5, [r7, r5, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    20d8:	f015 0f01 	tst.w	r5, #1
    20dc:	d0cb      	beq.n	2076 <gpio_nrfx_pin_interrupt_configure+0x16>
		return -ENOTSUP;
    20de:	f06f 0085 	mvn.w	r0, #133	; 0x85
    20e2:	e7ed      	b.n	20c0 <gpio_nrfx_pin_interrupt_configure+0x60>
        case 1: return NRF_P1;
    20e4:	4f0b      	ldr	r7, [pc, #44]	; (2114 <gpio_nrfx_pin_interrupt_configure+0xb4>)
    20e6:	e7f3      	b.n	20d0 <gpio_nrfx_pin_interrupt_configure+0x70>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    20e8:	68e5      	ldr	r5, [r4, #12]
    20ea:	2601      	movs	r6, #1
    20ec:	408e      	lsls	r6, r1
    20ee:	ea25 0506 	bic.w	r5, r5, r6
    20f2:	e7c7      	b.n	2084 <gpio_nrfx_pin_interrupt_configure+0x24>
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    20f4:	6962      	ldr	r2, [r4, #20]
    20f6:	2501      	movs	r5, #1
    20f8:	408d      	lsls	r5, r1
    20fa:	432a      	orrs	r2, r5
    20fc:	e7cb      	b.n	2096 <gpio_nrfx_pin_interrupt_configure+0x36>
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
    20fe:	69a2      	ldr	r2, [r4, #24]
    2100:	2501      	movs	r5, #1
    2102:	408d      	lsls	r5, r1
    2104:	432a      	orrs	r2, r5
    2106:	e7cf      	b.n	20a8 <gpio_nrfx_pin_interrupt_configure+0x48>
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    2108:	6923      	ldr	r3, [r4, #16]
    210a:	2201      	movs	r2, #1
    210c:	408a      	lsls	r2, r1
    210e:	4313      	orrs	r3, r2
    2110:	e7d3      	b.n	20ba <gpio_nrfx_pin_interrupt_configure+0x5a>
    2112:	bf00      	nop
    2114:	50000300 	.word	0x50000300

00002118 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    2118:	b508      	push	{r3, lr}
	static bool gpio_initialized;

	if (!gpio_initialized) {
    211a:	4b0b      	ldr	r3, [pc, #44]	; (2148 <gpio_nrfx_init+0x30>)
    211c:	781b      	ldrb	r3, [r3, #0]
    211e:	b10b      	cbz	r3, 2124 <gpio_nrfx_init+0xc>
		irq_enable(DT_IRQN(GPIOTE_NODE));
		nrf_gpiote_int_enable(NRF_GPIOTE, NRF_GPIOTE_INT_PORT_MASK);
	}

	return 0;
}
    2120:	2000      	movs	r0, #0
    2122:	bd08      	pop	{r3, pc}
		gpio_initialized = true;
    2124:	4b08      	ldr	r3, [pc, #32]	; (2148 <gpio_nrfx_init+0x30>)
    2126:	2201      	movs	r2, #1
    2128:	701a      	strb	r2, [r3, #0]
		IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    212a:	2200      	movs	r2, #0
    212c:	2105      	movs	r1, #5
    212e:	2006      	movs	r0, #6
    2130:	f7ff f880 	bl	1234 <z_arm_irq_priority_set>
		irq_enable(DT_IRQN(GPIOTE_NODE));
    2134:	2006      	movs	r0, #6
    2136:	f7ff f84b 	bl	11d0 <arch_irq_enable>
    213a:	4b04      	ldr	r3, [pc, #16]	; (214c <gpio_nrfx_init+0x34>)
    213c:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    2140:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    2144:	e7ec      	b.n	2120 <gpio_nrfx_init+0x8>
    2146:	bf00      	nop
    2148:	20000ae1 	.word	0x20000ae1
    214c:	40006000 	.word	0x40006000

00002150 <gpiote_event_handler>:
{
    2150:	b570      	push	{r4, r5, r6, lr}
    2152:	b084      	sub	sp, #16
	uint32_t fired_triggers[GPIO_COUNT] = {0};
    2154:	2300      	movs	r3, #0
    2156:	9302      	str	r3, [sp, #8]
    2158:	9303      	str	r3, [sp, #12]
	uint32_t sense_levels[GPIO_COUNT] = {0};
    215a:	9300      	str	r3, [sp, #0]
    215c:	9301      	str	r3, [sp, #4]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    215e:	4b46      	ldr	r3, [pc, #280]	; (2278 <gpiote_event_handler+0x128>)
    2160:	681c      	ldr	r4, [r3, #0]
	if (port_event) {
    2162:	b90c      	cbnz	r4, 2168 <gpiote_event_handler+0x18>
{
    2164:	2100      	movs	r1, #0
    2166:	e011      	b.n	218c <gpiote_event_handler+0x3c>
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(0)),
    2168:	4d44      	ldr	r5, [pc, #272]	; (227c <gpiote_event_handler+0x12c>)
    216a:	4669      	mov	r1, sp
    216c:	4628      	mov	r0, r5
    216e:	f7ff fe5f 	bl	1e30 <check_level_trigger_pins>
		fired_triggers[0] =
    2172:	9002      	str	r0, [sp, #8]
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(1)),
    2174:	a901      	add	r1, sp, #4
    2176:	f105 0018 	add.w	r0, r5, #24
    217a:	f7ff fe59 	bl	1e30 <check_level_trigger_pins>
		fired_triggers[1] =
    217e:	9003      	str	r0, [sp, #12]
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2180:	4b3d      	ldr	r3, [pc, #244]	; (2278 <gpiote_event_handler+0x128>)
    2182:	2200      	movs	r2, #0
    2184:	601a      	str	r2, [r3, #0]
    2186:	681b      	ldr	r3, [r3, #0]
}
    2188:	e7ec      	b.n	2164 <gpiote_event_handler+0x14>
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    218a:	3101      	adds	r1, #1
    218c:	2907      	cmp	r1, #7
    218e:	d82d      	bhi.n	21ec <gpiote_event_handler+0x9c>
		nrf_gpiote_event_t evt =
    2190:	f101 0340 	add.w	r3, r1, #64	; 0x40
    2194:	009b      	lsls	r3, r3, #2
    2196:	b29a      	uxth	r2, r3
		if (nrf_gpiote_int_enable_check(NRF_GPIOTE, BIT(i)) &&
    2198:	2301      	movs	r3, #1
    219a:	408b      	lsls	r3, r1
    return p_reg->INTENSET & mask;
    219c:	4838      	ldr	r0, [pc, #224]	; (2280 <gpiote_event_handler+0x130>)
    219e:	f8d0 0304 	ldr.w	r0, [r0, #772]	; 0x304
    21a2:	4203      	tst	r3, r0
    21a4:	d0f1      	beq.n	218a <gpiote_event_handler+0x3a>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    21a6:	f102 4380 	add.w	r3, r2, #1073741824	; 0x40000000
    21aa:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    21ae:	681b      	ldr	r3, [r3, #0]
    21b0:	2b00      	cmp	r3, #0
    21b2:	d0ea      	beq.n	218a <gpiote_event_handler+0x3a>
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    21b4:	f501 73a2 	add.w	r3, r1, #324	; 0x144
    21b8:	4831      	ldr	r0, [pc, #196]	; (2280 <gpiote_event_handler+0x130>)
    21ba:	f850 0023 	ldr.w	r0, [r0, r3, lsl #2]
			fired_triggers[abs_pin / 32U] |= BIT(abs_pin % 32);
    21be:	f3c0 3340 	ubfx	r3, r0, #13, #1
    21c2:	f3c0 2004 	ubfx	r0, r0, #8, #5
    21c6:	2501      	movs	r5, #1
    21c8:	fa05 f000 	lsl.w	r0, r5, r0
    21cc:	ad04      	add	r5, sp, #16
    21ce:	eb05 0383 	add.w	r3, r5, r3, lsl #2
    21d2:	f853 5c08 	ldr.w	r5, [r3, #-8]
    21d6:	4305      	orrs	r5, r0
    21d8:	f843 5c08 	str.w	r5, [r3, #-8]
    return ((uint32_t)p_reg + event);
    21dc:	f102 4380 	add.w	r3, r2, #1073741824	; 0x40000000
    21e0:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    21e4:	2200      	movs	r2, #0
    21e6:	601a      	str	r2, [r3, #0]
    21e8:	681b      	ldr	r3, [r3, #0]
}
    21ea:	e7ce      	b.n	218a <gpiote_event_handler+0x3a>
	if (fired_triggers[0]) {
    21ec:	9e02      	ldr	r6, [sp, #8]
    21ee:	b92e      	cbnz	r6, 21fc <gpiote_event_handler+0xac>
	if (fired_triggers[1]) {
    21f0:	9e03      	ldr	r6, [sp, #12]
    21f2:	b9ee      	cbnz	r6, 2230 <gpiote_event_handler+0xe0>
	if (port_event) {
    21f4:	2c00      	cmp	r4, #0
    21f6:	d135      	bne.n	2264 <gpiote_event_handler+0x114>
}
    21f8:	b004      	add	sp, #16
    21fa:	bd70      	pop	{r4, r5, r6, pc}
	return list->head;
    21fc:	4b21      	ldr	r3, [pc, #132]	; (2284 <gpiote_event_handler+0x134>)
    21fe:	6859      	ldr	r1, [r3, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    2200:	b119      	cbz	r1, 220a <gpiote_event_handler+0xba>
    2202:	460d      	mov	r5, r1
Z_GENLIST_PEEK_NEXT(slist, snode)
    2204:	b149      	cbz	r1, 221a <gpiote_event_handler+0xca>
	return node->next;
    2206:	680d      	ldr	r5, [r1, #0]
    2208:	e007      	b.n	221a <gpiote_event_handler+0xca>
    220a:	460d      	mov	r5, r1
    220c:	e005      	b.n	221a <gpiote_event_handler+0xca>
    220e:	b16d      	cbz	r5, 222c <gpiote_event_handler+0xdc>
    2210:	462b      	mov	r3, r5
Z_GENLIST_PEEK_NEXT(slist, snode)
    2212:	b105      	cbz	r5, 2216 <gpiote_event_handler+0xc6>
	return node->next;
    2214:	682b      	ldr	r3, [r5, #0]
    2216:	4629      	mov	r1, r5
    2218:	461d      	mov	r5, r3
    221a:	2900      	cmp	r1, #0
    221c:	d0e8      	beq.n	21f0 <gpiote_event_handler+0xa0>
		if (cb->pin_mask & pins) {
    221e:	688a      	ldr	r2, [r1, #8]
    2220:	4032      	ands	r2, r6
    2222:	d0f4      	beq.n	220e <gpiote_event_handler+0xbe>
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    2224:	684b      	ldr	r3, [r1, #4]
    2226:	4815      	ldr	r0, [pc, #84]	; (227c <gpiote_event_handler+0x12c>)
    2228:	4798      	blx	r3
    222a:	e7f0      	b.n	220e <gpiote_event_handler+0xbe>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    222c:	462b      	mov	r3, r5
    222e:	e7f2      	b.n	2216 <gpiote_event_handler+0xc6>
	return list->head;
    2230:	4b15      	ldr	r3, [pc, #84]	; (2288 <gpiote_event_handler+0x138>)
    2232:	6859      	ldr	r1, [r3, #4]
    2234:	b119      	cbz	r1, 223e <gpiote_event_handler+0xee>
    2236:	460d      	mov	r5, r1
Z_GENLIST_PEEK_NEXT(slist, snode)
    2238:	b149      	cbz	r1, 224e <gpiote_event_handler+0xfe>
	return node->next;
    223a:	680d      	ldr	r5, [r1, #0]
    223c:	e007      	b.n	224e <gpiote_event_handler+0xfe>
    223e:	460d      	mov	r5, r1
    2240:	e005      	b.n	224e <gpiote_event_handler+0xfe>
    2242:	b16d      	cbz	r5, 2260 <gpiote_event_handler+0x110>
    2244:	462b      	mov	r3, r5
Z_GENLIST_PEEK_NEXT(slist, snode)
    2246:	b105      	cbz	r5, 224a <gpiote_event_handler+0xfa>
	return node->next;
    2248:	682b      	ldr	r3, [r5, #0]
    224a:	4629      	mov	r1, r5
    224c:	461d      	mov	r5, r3
    224e:	2900      	cmp	r1, #0
    2250:	d0d0      	beq.n	21f4 <gpiote_event_handler+0xa4>
		if (cb->pin_mask & pins) {
    2252:	688a      	ldr	r2, [r1, #8]
    2254:	4032      	ands	r2, r6
    2256:	d0f4      	beq.n	2242 <gpiote_event_handler+0xf2>
			cb->handler(port, cb, cb->pin_mask & pins);
    2258:	684b      	ldr	r3, [r1, #4]
    225a:	480c      	ldr	r0, [pc, #48]	; (228c <gpiote_event_handler+0x13c>)
    225c:	4798      	blx	r3
    225e:	e7f0      	b.n	2242 <gpiote_event_handler+0xf2>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    2260:	462b      	mov	r3, r5
    2262:	e7f2      	b.n	224a <gpiote_event_handler+0xfa>
		cfg_level_pins(DEVICE_DT_GET(GPIO(0)));
    2264:	4c05      	ldr	r4, [pc, #20]	; (227c <gpiote_event_handler+0x12c>)
    2266:	4620      	mov	r0, r4
    2268:	f7ff fda8 	bl	1dbc <cfg_level_pins>
		cfg_level_pins(DEVICE_DT_GET(GPIO(1)));
    226c:	f104 0018 	add.w	r0, r4, #24
    2270:	f7ff fda4 	bl	1dbc <cfg_level_pins>
}
    2274:	e7c0      	b.n	21f8 <gpiote_event_handler+0xa8>
    2276:	bf00      	nop
    2278:	4000617c 	.word	0x4000617c
    227c:	000074d8 	.word	0x000074d8
    2280:	40006000 	.word	0x40006000
    2284:	200004c4 	.word	0x200004c4
    2288:	200004e0 	.word	0x200004e0
    228c:	000074f0 	.word	0x000074f0

00002290 <configure>:
	}
}

static int configure(const struct device *dev,
		     const struct spi_config *spi_cfg)
{
    2290:	b5f0      	push	{r4, r5, r6, r7, lr}
    2292:	b085      	sub	sp, #20
    2294:	460c      	mov	r4, r1
	return dev->data;
    2296:	6905      	ldr	r5, [r0, #16]
	return dev->config;
    2298:	6846      	ldr	r6, [r0, #4]
	const struct spi_nrfx_config *dev_config = get_dev_config(dev);
	struct spi_context *ctx = &dev_data->ctx;
	nrfx_spi_config_t config;
	nrfx_err_t result;

	if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) {
    229a:	f895 706d 	ldrb.w	r7, [r5, #109]	; 0x6d
    229e:	b11f      	cbz	r7, 22a8 <configure+0x18>
	._ctx_name.sync = Z_SEM_INITIALIZER(_data._ctx_name.sync, 0, 1)

static inline bool spi_context_configured(struct spi_context *ctx,
					  const struct spi_config *config)
{
	return !!(ctx->config == config);
    22a0:	682b      	ldr	r3, [r5, #0]
    22a2:	428b      	cmp	r3, r1
    22a4:	f000 80a2 	beq.w	23ec <configure+0x15c>
		/* Already configured. No need to do it again. */
		return 0;
	}

	if (SPI_OP_MODE_GET(spi_cfg->operation) != SPI_OP_MODE_MASTER) {
    22a8:	88a3      	ldrh	r3, [r4, #4]
    22aa:	f013 0f01 	tst.w	r3, #1
    22ae:	f040 809f 	bne.w	23f0 <configure+0x160>
		LOG_ERR("Slave mode is not supported on %s", dev->name);
		return -EINVAL;
	}

	if (spi_cfg->operation & SPI_MODE_LOOP) {
    22b2:	f013 0f08 	tst.w	r3, #8
    22b6:	f040 809e 	bne.w	23f6 <configure+0x166>
		LOG_ERR("Loopback mode is not supported");
		return -EINVAL;
	}

	if ((spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
    22ba:	f413 5fc0 	tst.w	r3, #6144	; 0x1800
    22be:	f040 809d 	bne.w	23fc <configure+0x16c>
		LOG_ERR("Only single line mode is supported");
		return -EINVAL;
	}

	if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
    22c2:	f3c3 1345 	ubfx	r3, r3, #5, #6
    22c6:	2b08      	cmp	r3, #8
    22c8:	f040 809b 	bne.w	2402 <configure+0x172>
		LOG_ERR("Word sizes other than 8 bits are not supported");
		return -EINVAL;
	}

	if (spi_cfg->frequency < 125000) {
    22cc:	6822      	ldr	r2, [r4, #0]
    22ce:	4b51      	ldr	r3, [pc, #324]	; (2414 <configure+0x184>)
    22d0:	429a      	cmp	r2, r3
    22d2:	f240 8099 	bls.w	2408 <configure+0x178>
		LOG_ERR("Frequencies lower than 125 kHz are not supported");
		return -EINVAL;
	}

	config = dev_config->def_config;
    22d6:	f106 0308 	add.w	r3, r6, #8
    22da:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    22dc:	f10d 0c10 	add.w	ip, sp, #16
    22e0:	e90c 000f 	stmdb	ip, {r0, r1, r2, r3}

	config.frequency = get_nrf_spi_frequency(spi_cfg->frequency);
    22e4:	6823      	ldr	r3, [r4, #0]
	if (frequency < 250000) {
    22e6:	4a4c      	ldr	r2, [pc, #304]	; (2418 <configure+0x188>)
    22e8:	4293      	cmp	r3, r2
    22ea:	d953      	bls.n	2394 <configure+0x104>
	} else if (frequency < 500000) {
    22ec:	4a4b      	ldr	r2, [pc, #300]	; (241c <configure+0x18c>)
    22ee:	4293      	cmp	r3, r2
    22f0:	d953      	bls.n	239a <configure+0x10a>
	} else if (frequency < 1000000) {
    22f2:	4a4b      	ldr	r2, [pc, #300]	; (2420 <configure+0x190>)
    22f4:	4293      	cmp	r3, r2
    22f6:	d953      	bls.n	23a0 <configure+0x110>
	} else if (frequency < 2000000) {
    22f8:	4a4a      	ldr	r2, [pc, #296]	; (2424 <configure+0x194>)
    22fa:	4293      	cmp	r3, r2
    22fc:	d953      	bls.n	23a6 <configure+0x116>
	} else if (frequency < 4000000) {
    22fe:	4a4a      	ldr	r2, [pc, #296]	; (2428 <configure+0x198>)
    2300:	4293      	cmp	r3, r2
    2302:	d953      	bls.n	23ac <configure+0x11c>
	} else if (frequency < 8000000) {
    2304:	4a49      	ldr	r2, [pc, #292]	; (242c <configure+0x19c>)
    2306:	4293      	cmp	r3, r2
    2308:	d253      	bcs.n	23b2 <configure+0x122>
		return NRF_SPI_FREQ_4M;
    230a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
	config.frequency = get_nrf_spi_frequency(spi_cfg->frequency);
    230e:	9302      	str	r3, [sp, #8]
	config.mode      = get_nrf_spi_mode(spi_cfg->operation);
    2310:	88a3      	ldrh	r3, [r4, #4]
	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
    2312:	f013 0f02 	tst.w	r3, #2
    2316:	d04f      	beq.n	23b8 <configure+0x128>
		if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
    2318:	f013 0f04 	tst.w	r3, #4
    231c:	d051      	beq.n	23c2 <configure+0x132>
			return NRF_SPI_MODE_3;
    231e:	2303      	movs	r3, #3
	config.mode      = get_nrf_spi_mode(spi_cfg->operation);
    2320:	f88d 300c 	strb.w	r3, [sp, #12]
	config.bit_order = get_nrf_spi_bit_order(spi_cfg->operation);
    2324:	88a3      	ldrh	r3, [r4, #4]
	if (operation & SPI_TRANSFER_LSB) {
    2326:	f013 0f10 	tst.w	r3, #16
    232a:	d04e      	beq.n	23ca <configure+0x13a>
		return NRF_SPI_BIT_ORDER_LSB_FIRST;
    232c:	2301      	movs	r3, #1
	config.bit_order = get_nrf_spi_bit_order(spi_cfg->operation);
    232e:	f88d 300d 	strb.w	r3, [sp, #13]

	if (dev_data->initialized) {
    2332:	2f00      	cmp	r7, #0
    2334:	d14b      	bne.n	23ce <configure+0x13e>
		nrfx_spi_uninit(&dev_config->spi);
		dev_data->initialized = false;
	}

	result = nrfx_spi_init(&dev_config->spi, &config,
    2336:	462b      	mov	r3, r5
    2338:	4a3d      	ldr	r2, [pc, #244]	; (2430 <configure+0x1a0>)
    233a:	4669      	mov	r1, sp
    233c:	4630      	mov	r0, r6
    233e:	f001 f9cf 	bl	36e0 <nrfx_spi_init>
			       event_handler, dev_data);
	if (result != NRFX_SUCCESS) {
    2342:	4b3c      	ldr	r3, [pc, #240]	; (2434 <configure+0x1a4>)
    2344:	4298      	cmp	r0, r3
    2346:	d162      	bne.n	240e <configure+0x17e>
		LOG_ERR("Failed to initialize nrfx driver: %08x", result);
		return -EIO;
	}

	dev_data->initialized = true;
    2348:	2301      	movs	r3, #1
    234a:	f885 306d 	strb.w	r3, [r5, #109]	; 0x6d

	ctx->config = spi_cfg;
    234e:	602c      	str	r4, [r5, #0]
	return GPIO_ACTIVE_LOW;
}

static inline void spi_context_cs_configure(struct spi_context *ctx)
{
	if (ctx->config->cs && ctx->config->cs->gpio_dev) {
    2350:	68a3      	ldr	r3, [r4, #8]
    2352:	b1e3      	cbz	r3, 238e <configure+0xfe>
    2354:	6818      	ldr	r0, [r3, #0]
    2356:	b1d0      	cbz	r0, 238e <configure+0xfe>
		/* Validate CS active levels are equivalent */
		__ASSERT(spi_context_cs_active_level(ctx) ==
			 (ctx->config->cs->gpio_dt_flags & GPIO_ACTIVE_LOW),
			 "Devicetree and spi_context CS levels are not equal");
		gpio_pin_configure(ctx->config->cs->gpio_dev,
    2358:	7a19      	ldrb	r1, [r3, #8]
				   ctx->config->cs->gpio_pin,
				   ctx->config->cs->gpio_dt_flags |
    235a:	7a5b      	ldrb	r3, [r3, #9]
		gpio_pin_configure(ctx->config->cs->gpio_dev,
    235c:	f443 53b0 	orr.w	r3, r3, #5632	; 0x1600

static inline int z_impl_gpio_pin_configure(const struct device *port,
					    gpio_pin_t pin,
					    gpio_flags_t flags)
{
	const struct gpio_driver_api *api =
    2360:	6885      	ldr	r5, [r0, #8]
		(const struct gpio_driver_api *)port->api;
	const struct gpio_driver_config *const cfg =
		(const struct gpio_driver_config *)port->config;
	struct gpio_driver_data *data =
    2362:	6904      	ldr	r4, [r0, #16]
	__ASSERT((flags & (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH))
		 != (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH),
		 "Output cannot be initialized low and high");

	if (((flags & GPIO_OUTPUT_INIT_LOGICAL) != 0)
	    && ((flags & (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH)) != 0)
    2364:	f413 6f40 	tst.w	r3, #3072	; 0xc00
    2368:	d004      	beq.n	2374 <configure+0xe4>
	    && ((flags & GPIO_ACTIVE_LOW) != 0)) {
    236a:	f013 0f01 	tst.w	r3, #1
    236e:	d001      	beq.n	2374 <configure+0xe4>
		flags ^= GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH;
    2370:	f483 6340 	eor.w	r3, r3, #3072	; 0xc00
	}

	flags &= ~GPIO_OUTPUT_INIT_LOGICAL;
    2374:	f423 5280 	bic.w	r2, r3, #4096	; 0x1000

	(void)cfg;
	__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
		 "Unsupported pin");

	if ((flags & GPIO_ACTIVE_LOW) != 0) {
    2378:	f013 0f01 	tst.w	r3, #1
    237c:	d02e      	beq.n	23dc <configure+0x14c>
		data->invert |= (gpio_port_pins_t)BIT(pin);
    237e:	2301      	movs	r3, #1
    2380:	fa03 f601 	lsl.w	r6, r3, r1
    2384:	6823      	ldr	r3, [r4, #0]
    2386:	4333      	orrs	r3, r6
    2388:	6023      	str	r3, [r4, #0]
	} else {
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
	}

	return api->pin_configure(port, pin, flags);
    238a:	682b      	ldr	r3, [r5, #0]
    238c:	4798      	blx	r3
	spi_context_cs_configure(ctx);

	return 0;
    238e:	2000      	movs	r0, #0
}
    2390:	b005      	add	sp, #20
    2392:	bdf0      	pop	{r4, r5, r6, r7, pc}
		return NRF_SPI_FREQ_125K;
    2394:	f04f 7300 	mov.w	r3, #33554432	; 0x2000000
    2398:	e7b9      	b.n	230e <configure+0x7e>
		return NRF_SPI_FREQ_250K;
    239a:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    239e:	e7b6      	b.n	230e <configure+0x7e>
		return NRF_SPI_FREQ_500K;
    23a0:	f04f 6300 	mov.w	r3, #134217728	; 0x8000000
    23a4:	e7b3      	b.n	230e <configure+0x7e>
		return NRF_SPI_FREQ_1M;
    23a6:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    23aa:	e7b0      	b.n	230e <configure+0x7e>
		return NRF_SPI_FREQ_2M;
    23ac:	f04f 5300 	mov.w	r3, #536870912	; 0x20000000
    23b0:	e7ad      	b.n	230e <configure+0x7e>
		return NRF_SPI_FREQ_8M;
    23b2:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
    23b6:	e7aa      	b.n	230e <configure+0x7e>
		if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
    23b8:	f013 0f04 	tst.w	r3, #4
    23bc:	d003      	beq.n	23c6 <configure+0x136>
			return NRF_SPI_MODE_1;
    23be:	2301      	movs	r3, #1
    23c0:	e7ae      	b.n	2320 <configure+0x90>
			return NRF_SPI_MODE_2;
    23c2:	2302      	movs	r3, #2
    23c4:	e7ac      	b.n	2320 <configure+0x90>
			return NRF_SPI_MODE_0;
    23c6:	2300      	movs	r3, #0
    23c8:	e7aa      	b.n	2320 <configure+0x90>
		return NRF_SPI_BIT_ORDER_MSB_FIRST;
    23ca:	2300      	movs	r3, #0
    23cc:	e7af      	b.n	232e <configure+0x9e>
		nrfx_spi_uninit(&dev_config->spi);
    23ce:	4630      	mov	r0, r6
    23d0:	f001 fa70 	bl	38b4 <nrfx_spi_uninit>
		dev_data->initialized = false;
    23d4:	2300      	movs	r3, #0
    23d6:	f885 306d 	strb.w	r3, [r5, #109]	; 0x6d
    23da:	e7ac      	b.n	2336 <configure+0xa6>
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
    23dc:	2301      	movs	r3, #1
    23de:	fa03 f601 	lsl.w	r6, r3, r1
    23e2:	6823      	ldr	r3, [r4, #0]
    23e4:	ea23 0306 	bic.w	r3, r3, r6
    23e8:	6023      	str	r3, [r4, #0]
    23ea:	e7ce      	b.n	238a <configure+0xfa>
		return 0;
    23ec:	2000      	movs	r0, #0
    23ee:	e7cf      	b.n	2390 <configure+0x100>
		return -EINVAL;
    23f0:	f06f 0015 	mvn.w	r0, #21
    23f4:	e7cc      	b.n	2390 <configure+0x100>
		return -EINVAL;
    23f6:	f06f 0015 	mvn.w	r0, #21
    23fa:	e7c9      	b.n	2390 <configure+0x100>
		return -EINVAL;
    23fc:	f06f 0015 	mvn.w	r0, #21
    2400:	e7c6      	b.n	2390 <configure+0x100>
		return -EINVAL;
    2402:	f06f 0015 	mvn.w	r0, #21
    2406:	e7c3      	b.n	2390 <configure+0x100>
		return -EINVAL;
    2408:	f06f 0015 	mvn.w	r0, #21
    240c:	e7c0      	b.n	2390 <configure+0x100>
		return -EIO;
    240e:	f06f 0004 	mvn.w	r0, #4
    2412:	e7bd      	b.n	2390 <configure+0x100>
    2414:	0001e847 	.word	0x0001e847
    2418:	0003d08f 	.word	0x0003d08f
    241c:	0007a11f 	.word	0x0007a11f
    2420:	000f423f 	.word	0x000f423f
    2424:	001e847f 	.word	0x001e847f
    2428:	003d08ff 	.word	0x003d08ff
    242c:	007a1200 	.word	0x007a1200
    2430:	0000642d 	.word	0x0000642d
    2434:	0bad0000 	.word	0x0bad0000

00002438 <transfer_next_chunk>:

static void transfer_next_chunk(const struct device *dev)
{
    2438:	b530      	push	{r4, r5, lr}
    243a:	b085      	sub	sp, #20
	return dev->data;
    243c:	6904      	ldr	r4, [r0, #16]
 * directions have a continuous buffer, i.e. the maximum SPI transfer that
 * can be done with DMA that handles only non-scattered buffers.
 */
static inline size_t spi_context_max_continuous_chunk(struct spi_context *ctx)
{
	if (!ctx->tx_len) {
    243e:	6da2      	ldr	r2, [r4, #88]	; 0x58
    2440:	2a00      	cmp	r2, #0
    2442:	d057      	beq.n	24f4 <transfer_next_chunk+0xbc>
		return ctx->rx_len;
	} else if (!ctx->rx_len) {
    2444:	6e23      	ldr	r3, [r4, #96]	; 0x60
    2446:	2b00      	cmp	r3, #0
    2448:	d056      	beq.n	24f8 <transfer_next_chunk+0xc0>
		return ctx->tx_len;
	}

	return MIN(ctx->tx_len, ctx->rx_len);
    244a:	4293      	cmp	r3, r2
    244c:	bf28      	it	cs
    244e:	4613      	movcs	r3, r2
	struct spi_context *ctx = &dev_data->ctx;
	int error = 0;

	size_t chunk_len = spi_context_max_continuous_chunk(ctx);

	if (chunk_len > 0) {
    2450:	2b00      	cmp	r3, #0
    2452:	d05d      	beq.n	2510 <transfer_next_chunk+0xd8>
		nrfx_spi_xfer_desc_t xfer;
		nrfx_err_t result;

		dev_data->chunk_len = chunk_len;
    2454:	66a3      	str	r3, [r4, #104]	; 0x68

		xfer.p_tx_buffer = ctx->tx_buf;
    2456:	6d61      	ldr	r1, [r4, #84]	; 0x54
    2458:	9100      	str	r1, [sp, #0]
	return !!(ctx->tx_buf && ctx->tx_len);
    245a:	2900      	cmp	r1, #0
    245c:	d04e      	beq.n	24fc <transfer_next_chunk+0xc4>
    245e:	2a00      	cmp	r2, #0
    2460:	d14e      	bne.n	2500 <transfer_next_chunk+0xc8>
		xfer.tx_length   = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
    2462:	2a00      	cmp	r2, #0
    2464:	d04e      	beq.n	2504 <transfer_next_chunk+0xcc>
    2466:	461a      	mov	r2, r3
    2468:	9201      	str	r2, [sp, #4]
		xfer.p_rx_buffer = ctx->rx_buf;
    246a:	6de2      	ldr	r2, [r4, #92]	; 0x5c
    246c:	9202      	str	r2, [sp, #8]
	return !!(ctx->rx_buf && ctx->rx_len);
    246e:	2a00      	cmp	r2, #0
    2470:	d04a      	beq.n	2508 <transfer_next_chunk+0xd0>
    2472:	6e22      	ldr	r2, [r4, #96]	; 0x60
    2474:	2a00      	cmp	r2, #0
    2476:	d149      	bne.n	250c <transfer_next_chunk+0xd4>
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    2478:	b902      	cbnz	r2, 247c <transfer_next_chunk+0x44>
    247a:	2300      	movs	r3, #0
    247c:	9303      	str	r3, [sp, #12]
		result = nrfx_spi_xfer(&get_dev_config(dev)->spi, &xfer, 0);
    247e:	2200      	movs	r2, #0
    2480:	4669      	mov	r1, sp
    2482:	6840      	ldr	r0, [r0, #4]
    2484:	f001 fa82 	bl	398c <nrfx_spi_xfer>
		if (result == NRFX_SUCCESS) {
    2488:	4b2d      	ldr	r3, [pc, #180]	; (2540 <transfer_next_chunk+0x108>)
    248a:	4298      	cmp	r0, r3
    248c:	d030      	beq.n	24f0 <transfer_next_chunk+0xb8>
			return;
		}

		error = -EIO;
    248e:	f06f 0504 	mvn.w	r5, #4
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio_dev) {
    2492:	6823      	ldr	r3, [r4, #0]
    2494:	b1e3      	cbz	r3, 24d0 <transfer_next_chunk+0x98>
    2496:	689a      	ldr	r2, [r3, #8]
    2498:	b1d2      	cbz	r2, 24d0 <transfer_next_chunk+0x98>
    249a:	6811      	ldr	r1, [r2, #0]
    249c:	b1c1      	cbz	r1, 24d0 <transfer_next_chunk+0x98>
			    ctx->config->operation & SPI_HOLD_ON_CS) {
    249e:	889b      	ldrh	r3, [r3, #4]
			if (!force_off &&
    24a0:	f413 5f00 	tst.w	r3, #8192	; 0x2000
    24a4:	d114      	bne.n	24d0 <transfer_next_chunk+0x98>
			k_busy_wait(ctx->config->cs->delay);
    24a6:	6850      	ldr	r0, [r2, #4]
	z_impl_k_busy_wait(usec_to_wait);
    24a8:	f004 ff03 	bl	72b2 <z_impl_k_busy_wait>
			gpio_pin_set(ctx->config->cs->gpio_dev,
    24ac:	6823      	ldr	r3, [r4, #0]
    24ae:	689b      	ldr	r3, [r3, #8]
    24b0:	6818      	ldr	r0, [r3, #0]
    24b2:	7a19      	ldrb	r1, [r3, #8]
static inline int gpio_pin_set(const struct device *port, gpio_pin_t pin,
			       int value)
{
	const struct gpio_driver_config *const cfg =
		(const struct gpio_driver_config *)port->config;
	const struct gpio_driver_data *const data =
    24b4:	6903      	ldr	r3, [r0, #16]

	(void)cfg;
	__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
		 "Unsupported pin");

	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    24b6:	681a      	ldr	r2, [r3, #0]
    24b8:	2301      	movs	r3, #1
    24ba:	408b      	lsls	r3, r1
    24bc:	421a      	tst	r2, r3
    24be:	d129      	bne.n	2514 <transfer_next_chunk+0xdc>
    24c0:	2300      	movs	r3, #0
	if (value != 0)	{
    24c2:	b34b      	cbz	r3, 2518 <transfer_next_chunk+0xe0>
		ret = gpio_port_set_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    24c4:	2301      	movs	r3, #1
    24c6:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    24ca:	6883      	ldr	r3, [r0, #8]
	return api->port_set_bits_raw(port, pins);
    24cc:	68db      	ldr	r3, [r3, #12]
    24ce:	4798      	blx	r3
	if (!ctx->asynchronous) {
    24d0:	f894 3040 	ldrb.w	r3, [r4, #64]	; 0x40
    24d4:	b33b      	cbz	r3, 2526 <transfer_next_chunk+0xee>
		if (ctx->signal) {
    24d6:	6be0      	ldr	r0, [r4, #60]	; 0x3c
    24d8:	b110      	cbz	r0, 24e0 <transfer_next_chunk+0xa8>
		/* coverity[OVERRUN] */
		return (int) arch_syscall_invoke2(*(uintptr_t *)&sig, *(uintptr_t *)&result, K_SYSCALL_K_POLL_SIGNAL_RAISE);
	}
#endif
	compiler_barrier();
	return z_impl_k_poll_signal_raise(sig, result);
    24da:	4629      	mov	r1, r5
    24dc:	f003 f86c 	bl	55b8 <z_impl_k_poll_signal_raise>
		if (!(ctx->config->operation & SPI_LOCK_ON)) {
    24e0:	6823      	ldr	r3, [r4, #0]
    24e2:	889b      	ldrh	r3, [r3, #4]
    24e4:	f413 4f80 	tst.w	r3, #16384	; 0x4000
    24e8:	d023      	beq.n	2532 <transfer_next_chunk+0xfa>
	spi_context_cs_control(ctx, false);

	LOG_DBG("Transaction finished with status %d", error);

	spi_context_complete(ctx, error);
	dev_data->busy = false;
    24ea:	2300      	movs	r3, #0
    24ec:	f884 306c 	strb.w	r3, [r4, #108]	; 0x6c
}
    24f0:	b005      	add	sp, #20
    24f2:	bd30      	pop	{r4, r5, pc}
		return ctx->rx_len;
    24f4:	6e23      	ldr	r3, [r4, #96]	; 0x60
    24f6:	e7ab      	b.n	2450 <transfer_next_chunk+0x18>
		return ctx->tx_len;
    24f8:	4613      	mov	r3, r2
    24fa:	e7a9      	b.n	2450 <transfer_next_chunk+0x18>
	return !!(ctx->tx_buf && ctx->tx_len);
    24fc:	2200      	movs	r2, #0
    24fe:	e7b0      	b.n	2462 <transfer_next_chunk+0x2a>
    2500:	2201      	movs	r2, #1
    2502:	e7ae      	b.n	2462 <transfer_next_chunk+0x2a>
		xfer.tx_length   = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
    2504:	2200      	movs	r2, #0
    2506:	e7af      	b.n	2468 <transfer_next_chunk+0x30>
	return !!(ctx->rx_buf && ctx->rx_len);
    2508:	2200      	movs	r2, #0
    250a:	e7b5      	b.n	2478 <transfer_next_chunk+0x40>
    250c:	2201      	movs	r2, #1
    250e:	e7b3      	b.n	2478 <transfer_next_chunk+0x40>
	int error = 0;
    2510:	2500      	movs	r5, #0
    2512:	e7be      	b.n	2492 <transfer_next_chunk+0x5a>
		value = (value != 0) ? 0 : 1;
    2514:	2301      	movs	r3, #1
    2516:	e7d4      	b.n	24c2 <transfer_next_chunk+0x8a>
		ret = gpio_port_clear_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    2518:	2301      	movs	r3, #1
    251a:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    251e:	6883      	ldr	r3, [r0, #8]
	return api->port_clear_bits_raw(port, pins);
    2520:	691b      	ldr	r3, [r3, #16]
    2522:	4798      	blx	r3
	return ret;
    2524:	e7d4      	b.n	24d0 <transfer_next_chunk+0x98>
		ctx->sync_status = status;
    2526:	63a5      	str	r5, [r4, #56]	; 0x38
		k_sem_give(&ctx->sync);
    2528:	f104 0020 	add.w	r0, r4, #32
	z_impl_k_sem_give(sem);
    252c:	f002 f814 	bl	4558 <z_impl_k_sem_give>
}
    2530:	e7db      	b.n	24ea <transfer_next_chunk+0xb2>
			ctx->owner = NULL;
    2532:	2300      	movs	r3, #0
    2534:	6063      	str	r3, [r4, #4]
			k_sem_give(&ctx->lock);
    2536:	f104 0008 	add.w	r0, r4, #8
	z_impl_k_sem_give(sem);
    253a:	f002 f80d 	bl	4558 <z_impl_k_sem_give>
}
    253e:	e7d4      	b.n	24ea <transfer_next_chunk+0xb2>
    2540:	0bad0000 	.word	0x0bad0000

00002544 <configure>:
	}
}

static int configure(const struct device *dev,
		     const struct spi_config *spi_cfg)
{
    2544:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    2548:	b086      	sub	sp, #24
    254a:	460c      	mov	r4, r1
	return dev->data;
    254c:	6907      	ldr	r7, [r0, #16]
	return dev->config;
    254e:	f8d0 8004 	ldr.w	r8, [r0, #4]
	struct spi_nrfx_data *dev_data = get_dev_data(dev);
	const struct spi_nrfx_config *dev_config = get_dev_config(dev);
	struct spi_context *ctx = &dev_data->ctx;
	uint32_t max_freq = dev_config->max_freq;
    2552:	f8d8 e00c 	ldr.w	lr, [r8, #12]
	nrfx_spim_config_t config;
	nrfx_err_t result;

	if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) {
    2556:	f897 c06d 	ldrb.w	ip, [r7, #109]	; 0x6d
    255a:	f1bc 0f00 	cmp.w	ip, #0
    255e:	d003      	beq.n	2568 <configure+0x24>
	return !!(ctx->config == config);
    2560:	683b      	ldr	r3, [r7, #0]
    2562:	428b      	cmp	r3, r1
    2564:	f000 80b3 	beq.w	26ce <configure+0x18a>
		/* Already configured. No need to do it again. */
		return 0;
	}

	if (SPI_OP_MODE_GET(spi_cfg->operation) != SPI_OP_MODE_MASTER) {
    2568:	88a3      	ldrh	r3, [r4, #4]
    256a:	f013 0f01 	tst.w	r3, #1
    256e:	f040 80b0 	bne.w	26d2 <configure+0x18e>
		LOG_ERR("Slave mode is not supported on %s", dev->name);
		return -EINVAL;
	}

	if (spi_cfg->operation & SPI_MODE_LOOP) {
    2572:	f013 0f08 	tst.w	r3, #8
    2576:	f040 80af 	bne.w	26d8 <configure+0x194>
		LOG_ERR("Loopback mode is not supported");
		return -EINVAL;
	}

	if ((spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
    257a:	f413 5fc0 	tst.w	r3, #6144	; 0x1800
    257e:	f040 80ae 	bne.w	26de <configure+0x19a>
		LOG_ERR("Only single line mode is supported");
		return -EINVAL;
	}

	if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
    2582:	f3c3 1345 	ubfx	r3, r3, #5, #6
    2586:	2b08      	cmp	r3, #8
    2588:	f040 80ac 	bne.w	26e4 <configure+0x1a0>
		LOG_ERR("Word sizes other than 8 bits are not supported");
		return -EINVAL;
	}

	if (spi_cfg->frequency < 125000) {
    258c:	6822      	ldr	r2, [r4, #0]
    258e:	4b5a      	ldr	r3, [pc, #360]	; (26f8 <configure+0x1b4>)
    2590:	429a      	cmp	r2, r3
    2592:	f240 80aa 	bls.w	26ea <configure+0x1a6>
	    nrf_clock_hfclk_div_get(NRF_CLOCK) != NRF_CLOCK_HFCLK_DIV_1) {
		max_freq = 16000000;
	}
#endif

	config = dev_config->def_config;
    2596:	ad01      	add	r5, sp, #4
    2598:	f108 0610 	add.w	r6, r8, #16
    259c:	ce0f      	ldmia	r6!, {r0, r1, r2, r3}
    259e:	c50f      	stmia	r5!, {r0, r1, r2, r3}
    25a0:	6833      	ldr	r3, [r6, #0]
    25a2:	602b      	str	r3, [r5, #0]

	/* Limit the frequency to that supported by the SPIM instance. */
	config.frequency = get_nrf_spim_frequency(MIN(spi_cfg->frequency,
    25a4:	6823      	ldr	r3, [r4, #0]
    25a6:	4573      	cmp	r3, lr
    25a8:	bf28      	it	cs
    25aa:	4673      	movcs	r3, lr
	if (frequency < 250000) {
    25ac:	4a53      	ldr	r2, [pc, #332]	; (26fc <configure+0x1b8>)
    25ae:	4293      	cmp	r3, r2
    25b0:	d917      	bls.n	25e2 <configure+0x9e>
	} else if (frequency < 500000) {
    25b2:	4a53      	ldr	r2, [pc, #332]	; (2700 <configure+0x1bc>)
    25b4:	4293      	cmp	r3, r2
    25b6:	d95b      	bls.n	2670 <configure+0x12c>
	} else if (frequency < 1000000) {
    25b8:	4a52      	ldr	r2, [pc, #328]	; (2704 <configure+0x1c0>)
    25ba:	4293      	cmp	r3, r2
    25bc:	d95b      	bls.n	2676 <configure+0x132>
	} else if (frequency < 2000000) {
    25be:	4a52      	ldr	r2, [pc, #328]	; (2708 <configure+0x1c4>)
    25c0:	4293      	cmp	r3, r2
    25c2:	d95b      	bls.n	267c <configure+0x138>
	} else if (frequency < 4000000) {
    25c4:	4a51      	ldr	r2, [pc, #324]	; (270c <configure+0x1c8>)
    25c6:	4293      	cmp	r3, r2
    25c8:	d95b      	bls.n	2682 <configure+0x13e>
	} else if (frequency < 8000000) {
    25ca:	4a51      	ldr	r2, [pc, #324]	; (2710 <configure+0x1cc>)
    25cc:	4293      	cmp	r3, r2
    25ce:	d35b      	bcc.n	2688 <configure+0x144>
	} else if (frequency < 16000000) {
    25d0:	4a50      	ldr	r2, [pc, #320]	; (2714 <configure+0x1d0>)
    25d2:	4293      	cmp	r3, r2
    25d4:	d35b      	bcc.n	268e <configure+0x14a>
	} else if (frequency < 32000000) {
    25d6:	4a50      	ldr	r2, [pc, #320]	; (2718 <configure+0x1d4>)
    25d8:	4293      	cmp	r3, r2
    25da:	d25b      	bcs.n	2694 <configure+0x150>
		return NRF_SPIM_FREQ_16M;
    25dc:	f04f 6320 	mov.w	r3, #167772160	; 0xa000000
    25e0:	e001      	b.n	25e6 <configure+0xa2>
		return NRF_SPIM_FREQ_125K;
    25e2:	f04f 7300 	mov.w	r3, #33554432	; 0x2000000
	config.frequency = get_nrf_spim_frequency(MIN(spi_cfg->frequency,
    25e6:	9303      	str	r3, [sp, #12]
						      max_freq));
	config.mode      = get_nrf_spim_mode(spi_cfg->operation);
    25e8:	88a3      	ldrh	r3, [r4, #4]
	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
    25ea:	f013 0f02 	tst.w	r3, #2
    25ee:	d054      	beq.n	269a <configure+0x156>
		if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
    25f0:	f013 0f04 	tst.w	r3, #4
    25f4:	d056      	beq.n	26a4 <configure+0x160>
			return NRF_SPIM_MODE_3;
    25f6:	2303      	movs	r3, #3
	config.mode      = get_nrf_spim_mode(spi_cfg->operation);
    25f8:	f88d 3010 	strb.w	r3, [sp, #16]
	config.bit_order = get_nrf_spim_bit_order(spi_cfg->operation);
    25fc:	88a3      	ldrh	r3, [r4, #4]
	if (operation & SPI_TRANSFER_LSB) {
    25fe:	f013 0f10 	tst.w	r3, #16
    2602:	d053      	beq.n	26ac <configure+0x168>
		return NRF_SPIM_BIT_ORDER_LSB_FIRST;
    2604:	2301      	movs	r3, #1
	config.bit_order = get_nrf_spim_bit_order(spi_cfg->operation);
    2606:	f88d 3011 	strb.w	r3, [sp, #17]

	if (dev_data->initialized) {
    260a:	f1bc 0f00 	cmp.w	ip, #0
    260e:	d14f      	bne.n	26b0 <configure+0x16c>
		nrfx_spim_uninit(&dev_config->spim);
		dev_data->initialized = false;
	}

	result = nrfx_spim_init(&dev_config->spim, &config,
    2610:	463b      	mov	r3, r7
    2612:	4a42      	ldr	r2, [pc, #264]	; (271c <configure+0x1d8>)
    2614:	a901      	add	r1, sp, #4
    2616:	4640      	mov	r0, r8
    2618:	f001 fad6 	bl	3bc8 <nrfx_spim_init>
				event_handler, dev_data);
	if (result != NRFX_SUCCESS) {
    261c:	4b40      	ldr	r3, [pc, #256]	; (2720 <configure+0x1dc>)
    261e:	4298      	cmp	r0, r3
    2620:	d166      	bne.n	26f0 <configure+0x1ac>
		LOG_ERR("Failed to initialize nrfx driver: %08x", result);
		return -EIO;
	}

	dev_data->initialized = true;
    2622:	2301      	movs	r3, #1
    2624:	f887 306d 	strb.w	r3, [r7, #109]	; 0x6d

	ctx->config = spi_cfg;
    2628:	603c      	str	r4, [r7, #0]
	if (ctx->config->cs && ctx->config->cs->gpio_dev) {
    262a:	68a3      	ldr	r3, [r4, #8]
    262c:	b1e3      	cbz	r3, 2668 <configure+0x124>
    262e:	6818      	ldr	r0, [r3, #0]
    2630:	b1d0      	cbz	r0, 2668 <configure+0x124>
		gpio_pin_configure(ctx->config->cs->gpio_dev,
    2632:	7a19      	ldrb	r1, [r3, #8]
				   ctx->config->cs->gpio_dt_flags |
    2634:	7a5b      	ldrb	r3, [r3, #9]
		gpio_pin_configure(ctx->config->cs->gpio_dev,
    2636:	f443 53b0 	orr.w	r3, r3, #5632	; 0x1600
	const struct gpio_driver_api *api =
    263a:	6885      	ldr	r5, [r0, #8]
	struct gpio_driver_data *data =
    263c:	6904      	ldr	r4, [r0, #16]
	    && ((flags & (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH)) != 0)
    263e:	f413 6f40 	tst.w	r3, #3072	; 0xc00
    2642:	d004      	beq.n	264e <configure+0x10a>
	    && ((flags & GPIO_ACTIVE_LOW) != 0)) {
    2644:	f013 0f01 	tst.w	r3, #1
    2648:	d001      	beq.n	264e <configure+0x10a>
		flags ^= GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH;
    264a:	f483 6340 	eor.w	r3, r3, #3072	; 0xc00
	flags &= ~GPIO_OUTPUT_INIT_LOGICAL;
    264e:	f423 5280 	bic.w	r2, r3, #4096	; 0x1000
	if ((flags & GPIO_ACTIVE_LOW) != 0) {
    2652:	f013 0f01 	tst.w	r3, #1
    2656:	d032      	beq.n	26be <configure+0x17a>
		data->invert |= (gpio_port_pins_t)BIT(pin);
    2658:	2301      	movs	r3, #1
    265a:	fa03 f601 	lsl.w	r6, r3, r1
    265e:	6823      	ldr	r3, [r4, #0]
    2660:	4333      	orrs	r3, r6
    2662:	6023      	str	r3, [r4, #0]
	return api->pin_configure(port, pin, flags);
    2664:	682b      	ldr	r3, [r5, #0]
    2666:	4798      	blx	r3
	spi_context_cs_configure(ctx);

	return 0;
    2668:	2000      	movs	r0, #0
}
    266a:	b006      	add	sp, #24
    266c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		return NRF_SPIM_FREQ_250K;
    2670:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    2674:	e7b7      	b.n	25e6 <configure+0xa2>
		return NRF_SPIM_FREQ_500K;
    2676:	f04f 6300 	mov.w	r3, #134217728	; 0x8000000
    267a:	e7b4      	b.n	25e6 <configure+0xa2>
		return NRF_SPIM_FREQ_1M;
    267c:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    2680:	e7b1      	b.n	25e6 <configure+0xa2>
		return NRF_SPIM_FREQ_2M;
    2682:	f04f 5300 	mov.w	r3, #536870912	; 0x20000000
    2686:	e7ae      	b.n	25e6 <configure+0xa2>
		return NRF_SPIM_FREQ_4M;
    2688:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    268c:	e7ab      	b.n	25e6 <configure+0xa2>
		return NRF_SPIM_FREQ_8M;
    268e:	f04f 4300 	mov.w	r3, #2147483648	; 0x80000000
    2692:	e7a8      	b.n	25e6 <configure+0xa2>
		return NRF_SPIM_FREQ_32M;
    2694:	f04f 53a0 	mov.w	r3, #335544320	; 0x14000000
    2698:	e7a5      	b.n	25e6 <configure+0xa2>
		if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
    269a:	f013 0f04 	tst.w	r3, #4
    269e:	d003      	beq.n	26a8 <configure+0x164>
			return NRF_SPIM_MODE_1;
    26a0:	2301      	movs	r3, #1
    26a2:	e7a9      	b.n	25f8 <configure+0xb4>
			return NRF_SPIM_MODE_2;
    26a4:	2302      	movs	r3, #2
    26a6:	e7a7      	b.n	25f8 <configure+0xb4>
			return NRF_SPIM_MODE_0;
    26a8:	2300      	movs	r3, #0
    26aa:	e7a5      	b.n	25f8 <configure+0xb4>
		return NRF_SPIM_BIT_ORDER_MSB_FIRST;
    26ac:	2300      	movs	r3, #0
    26ae:	e7aa      	b.n	2606 <configure+0xc2>
		nrfx_spim_uninit(&dev_config->spim);
    26b0:	4640      	mov	r0, r8
    26b2:	f001 fc03 	bl	3ebc <nrfx_spim_uninit>
		dev_data->initialized = false;
    26b6:	2300      	movs	r3, #0
    26b8:	f887 306d 	strb.w	r3, [r7, #109]	; 0x6d
    26bc:	e7a8      	b.n	2610 <configure+0xcc>
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
    26be:	2301      	movs	r3, #1
    26c0:	fa03 f601 	lsl.w	r6, r3, r1
    26c4:	6823      	ldr	r3, [r4, #0]
    26c6:	ea23 0306 	bic.w	r3, r3, r6
    26ca:	6023      	str	r3, [r4, #0]
    26cc:	e7ca      	b.n	2664 <configure+0x120>
		return 0;
    26ce:	2000      	movs	r0, #0
    26d0:	e7cb      	b.n	266a <configure+0x126>
		return -EINVAL;
    26d2:	f06f 0015 	mvn.w	r0, #21
    26d6:	e7c8      	b.n	266a <configure+0x126>
		return -EINVAL;
    26d8:	f06f 0015 	mvn.w	r0, #21
    26dc:	e7c5      	b.n	266a <configure+0x126>
		return -EINVAL;
    26de:	f06f 0015 	mvn.w	r0, #21
    26e2:	e7c2      	b.n	266a <configure+0x126>
		return -EINVAL;
    26e4:	f06f 0015 	mvn.w	r0, #21
    26e8:	e7bf      	b.n	266a <configure+0x126>
		return -EINVAL;
    26ea:	f06f 0015 	mvn.w	r0, #21
    26ee:	e7bc      	b.n	266a <configure+0x126>
		return -EIO;
    26f0:	f06f 0004 	mvn.w	r0, #4
    26f4:	e7b9      	b.n	266a <configure+0x126>
    26f6:	bf00      	nop
    26f8:	0001e847 	.word	0x0001e847
    26fc:	0003d08f 	.word	0x0003d08f
    2700:	0007a11f 	.word	0x0007a11f
    2704:	000f423f 	.word	0x000f423f
    2708:	001e847f 	.word	0x001e847f
    270c:	003d08ff 	.word	0x003d08ff
    2710:	007a1200 	.word	0x007a1200
    2714:	00f42400 	.word	0x00f42400
    2718:	01e84800 	.word	0x01e84800
    271c:	00006715 	.word	0x00006715
    2720:	0bad0000 	.word	0x0bad0000

00002724 <transfer_next_chunk>:

static void transfer_next_chunk(const struct device *dev)
{
    2724:	b5f0      	push	{r4, r5, r6, r7, lr}
    2726:	b085      	sub	sp, #20
	return dev->data;
    2728:	6904      	ldr	r4, [r0, #16]
	return dev->config;
    272a:	6846      	ldr	r6, [r0, #4]
	if (!ctx->tx_len) {
    272c:	6da3      	ldr	r3, [r4, #88]	; 0x58
    272e:	2b00      	cmp	r3, #0
    2730:	d071      	beq.n	2816 <transfer_next_chunk+0xf2>
	} else if (!ctx->rx_len) {
    2732:	6e25      	ldr	r5, [r4, #96]	; 0x60
    2734:	2d00      	cmp	r5, #0
    2736:	d070      	beq.n	281a <transfer_next_chunk+0xf6>
	return MIN(ctx->tx_len, ctx->rx_len);
    2738:	429d      	cmp	r5, r3
    273a:	bf28      	it	cs
    273c:	461d      	movcs	r5, r3
	struct spi_context *ctx = &dev_data->ctx;
	int error = 0;

	size_t chunk_len = spi_context_max_continuous_chunk(ctx);

	if (chunk_len > 0) {
    273e:	2d00      	cmp	r5, #0
    2740:	d07b      	beq.n	283a <transfer_next_chunk+0x116>
		nrfx_spim_xfer_desc_t xfer;
		nrfx_err_t result;
		const uint8_t *tx_buf = ctx->tx_buf;
    2742:	6d61      	ldr	r1, [r4, #84]	; 0x54
	return !!(ctx->tx_buf && ctx->tx_len);
    2744:	2900      	cmp	r1, #0
    2746:	d06a      	beq.n	281e <transfer_next_chunk+0xfa>
    2748:	2b00      	cmp	r3, #0
    274a:	d16a      	bne.n	2822 <transfer_next_chunk+0xfe>
#if (CONFIG_SPI_NRFX_RAM_BUFFER_SIZE > 0)
		if (spi_context_tx_buf_on(ctx) && !nrfx_is_in_ram(tx_buf)) {
    274c:	b173      	cbz	r3, 276c <transfer_next_chunk+0x48>

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrfx_is_in_ram(void const * p_object)
{
    return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u);
    274e:	f001 4360 	and.w	r3, r1, #3758096384	; 0xe0000000
    2752:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
    2756:	d009      	beq.n	276c <transfer_next_chunk+0x48>
			if (chunk_len > sizeof(dev_data->buffer)) {
    2758:	2d08      	cmp	r5, #8
    275a:	d900      	bls.n	275e <transfer_next_chunk+0x3a>
				chunk_len = sizeof(dev_data->buffer);
    275c:	2508      	movs	r5, #8
			}

			memcpy(dev_data->buffer, tx_buf, chunk_len);
    275e:	f104 076e 	add.w	r7, r4, #110	; 0x6e
    2762:	462a      	mov	r2, r5
    2764:	4638      	mov	r0, r7
    2766:	f003 fc27 	bl	5fb8 <memcpy>
			tx_buf = dev_data->buffer;
    276a:	4639      	mov	r1, r7
		}
#endif
		if (chunk_len > dev_config->max_chunk_len) {
    276c:	68b3      	ldr	r3, [r6, #8]
    276e:	42ab      	cmp	r3, r5
    2770:	d300      	bcc.n	2774 <transfer_next_chunk+0x50>
    2772:	462b      	mov	r3, r5
			chunk_len = dev_config->max_chunk_len;
		}

		dev_data->chunk_len = chunk_len;
    2774:	66a3      	str	r3, [r4, #104]	; 0x68

		xfer.p_tx_buffer = tx_buf;
    2776:	9100      	str	r1, [sp, #0]
    2778:	6d62      	ldr	r2, [r4, #84]	; 0x54
    277a:	2a00      	cmp	r2, #0
    277c:	d053      	beq.n	2826 <transfer_next_chunk+0x102>
    277e:	6da2      	ldr	r2, [r4, #88]	; 0x58
    2780:	2a00      	cmp	r2, #0
    2782:	d152      	bne.n	282a <transfer_next_chunk+0x106>
		xfer.tx_length   = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
    2784:	2a00      	cmp	r2, #0
    2786:	d052      	beq.n	282e <transfer_next_chunk+0x10a>
    2788:	461a      	mov	r2, r3
    278a:	9201      	str	r2, [sp, #4]
		xfer.p_rx_buffer = ctx->rx_buf;
    278c:	6de2      	ldr	r2, [r4, #92]	; 0x5c
    278e:	9202      	str	r2, [sp, #8]
	return !!(ctx->rx_buf && ctx->rx_len);
    2790:	2a00      	cmp	r2, #0
    2792:	d04e      	beq.n	2832 <transfer_next_chunk+0x10e>
    2794:	6e22      	ldr	r2, [r4, #96]	; 0x60
    2796:	2a00      	cmp	r2, #0
    2798:	d14d      	bne.n	2836 <transfer_next_chunk+0x112>
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    279a:	b902      	cbnz	r2, 279e <transfer_next_chunk+0x7a>
    279c:	2300      	movs	r3, #0
    279e:	9303      	str	r3, [sp, #12]
			LOG_WRN("Transaction aborted since it would trigger nRF52832 PAN 58");
			error = -EIO;
		}

		if (!error) {
			result = nrfx_spim_xfer(&dev_config->spim, &xfer, 0);
    27a0:	2200      	movs	r2, #0
    27a2:	4669      	mov	r1, sp
    27a4:	4630      	mov	r0, r6
    27a6:	f001 fbdf 	bl	3f68 <nrfx_spim_xfer>
			if (result == NRFX_SUCCESS) {
    27aa:	4b30      	ldr	r3, [pc, #192]	; (286c <transfer_next_chunk+0x148>)
    27ac:	4298      	cmp	r0, r3
    27ae:	d030      	beq.n	2812 <transfer_next_chunk+0xee>
				return;
			}
			error = -EIO;
    27b0:	f06f 0504 	mvn.w	r5, #4
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio_dev) {
    27b4:	6823      	ldr	r3, [r4, #0]
    27b6:	b1e3      	cbz	r3, 27f2 <transfer_next_chunk+0xce>
    27b8:	689a      	ldr	r2, [r3, #8]
    27ba:	b1d2      	cbz	r2, 27f2 <transfer_next_chunk+0xce>
    27bc:	6811      	ldr	r1, [r2, #0]
    27be:	b1c1      	cbz	r1, 27f2 <transfer_next_chunk+0xce>
			    ctx->config->operation & SPI_HOLD_ON_CS) {
    27c0:	889b      	ldrh	r3, [r3, #4]
			if (!force_off &&
    27c2:	f413 5f00 	tst.w	r3, #8192	; 0x2000
    27c6:	d114      	bne.n	27f2 <transfer_next_chunk+0xce>
			k_busy_wait(ctx->config->cs->delay);
    27c8:	6850      	ldr	r0, [r2, #4]
	z_impl_k_busy_wait(usec_to_wait);
    27ca:	f004 fd72 	bl	72b2 <z_impl_k_busy_wait>
			gpio_pin_set(ctx->config->cs->gpio_dev,
    27ce:	6823      	ldr	r3, [r4, #0]
    27d0:	689b      	ldr	r3, [r3, #8]
    27d2:	6818      	ldr	r0, [r3, #0]
    27d4:	7a19      	ldrb	r1, [r3, #8]
	const struct gpio_driver_data *const data =
    27d6:	6903      	ldr	r3, [r0, #16]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    27d8:	681a      	ldr	r2, [r3, #0]
    27da:	2301      	movs	r3, #1
    27dc:	408b      	lsls	r3, r1
    27de:	421a      	tst	r2, r3
    27e0:	d12d      	bne.n	283e <transfer_next_chunk+0x11a>
    27e2:	2300      	movs	r3, #0
	if (value != 0)	{
    27e4:	b36b      	cbz	r3, 2842 <transfer_next_chunk+0x11e>
		ret = gpio_port_set_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    27e6:	2301      	movs	r3, #1
    27e8:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    27ec:	6883      	ldr	r3, [r0, #8]
	return api->port_set_bits_raw(port, pins);
    27ee:	68db      	ldr	r3, [r3, #12]
    27f0:	4798      	blx	r3
	if (!ctx->asynchronous) {
    27f2:	f894 3040 	ldrb.w	r3, [r4, #64]	; 0x40
    27f6:	b35b      	cbz	r3, 2850 <transfer_next_chunk+0x12c>
		if (ctx->signal) {
    27f8:	6be0      	ldr	r0, [r4, #60]	; 0x3c
    27fa:	b110      	cbz	r0, 2802 <transfer_next_chunk+0xde>
	return z_impl_k_poll_signal_raise(sig, result);
    27fc:	4629      	mov	r1, r5
    27fe:	f002 fedb 	bl	55b8 <z_impl_k_poll_signal_raise>
		if (!(ctx->config->operation & SPI_LOCK_ON)) {
    2802:	6823      	ldr	r3, [r4, #0]
    2804:	889b      	ldrh	r3, [r3, #4]
    2806:	f413 4f80 	tst.w	r3, #16384	; 0x4000
    280a:	d027      	beq.n	285c <transfer_next_chunk+0x138>
	spi_context_cs_control(ctx, false);

	LOG_DBG("Transaction finished with status %d", error);

	spi_context_complete(ctx, error);
	dev_data->busy = false;
    280c:	2300      	movs	r3, #0
    280e:	f884 306c 	strb.w	r3, [r4, #108]	; 0x6c
}
    2812:	b005      	add	sp, #20
    2814:	bdf0      	pop	{r4, r5, r6, r7, pc}
		return ctx->rx_len;
    2816:	6e25      	ldr	r5, [r4, #96]	; 0x60
    2818:	e791      	b.n	273e <transfer_next_chunk+0x1a>
		return ctx->tx_len;
    281a:	461d      	mov	r5, r3
    281c:	e78f      	b.n	273e <transfer_next_chunk+0x1a>
	return !!(ctx->tx_buf && ctx->tx_len);
    281e:	2300      	movs	r3, #0
    2820:	e794      	b.n	274c <transfer_next_chunk+0x28>
    2822:	2301      	movs	r3, #1
    2824:	e792      	b.n	274c <transfer_next_chunk+0x28>
    2826:	2200      	movs	r2, #0
    2828:	e7ac      	b.n	2784 <transfer_next_chunk+0x60>
    282a:	2201      	movs	r2, #1
    282c:	e7aa      	b.n	2784 <transfer_next_chunk+0x60>
		xfer.tx_length   = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
    282e:	2200      	movs	r2, #0
    2830:	e7ab      	b.n	278a <transfer_next_chunk+0x66>
	return !!(ctx->rx_buf && ctx->rx_len);
    2832:	2200      	movs	r2, #0
    2834:	e7b1      	b.n	279a <transfer_next_chunk+0x76>
    2836:	2201      	movs	r2, #1
    2838:	e7af      	b.n	279a <transfer_next_chunk+0x76>
	int error = 0;
    283a:	2500      	movs	r5, #0
    283c:	e7ba      	b.n	27b4 <transfer_next_chunk+0x90>
		value = (value != 0) ? 0 : 1;
    283e:	2301      	movs	r3, #1
    2840:	e7d0      	b.n	27e4 <transfer_next_chunk+0xc0>
		ret = gpio_port_clear_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    2842:	2301      	movs	r3, #1
    2844:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    2848:	6883      	ldr	r3, [r0, #8]
	return api->port_clear_bits_raw(port, pins);
    284a:	691b      	ldr	r3, [r3, #16]
    284c:	4798      	blx	r3
	return ret;
    284e:	e7d0      	b.n	27f2 <transfer_next_chunk+0xce>
		ctx->sync_status = status;
    2850:	63a5      	str	r5, [r4, #56]	; 0x38
		k_sem_give(&ctx->sync);
    2852:	f104 0020 	add.w	r0, r4, #32
	z_impl_k_sem_give(sem);
    2856:	f001 fe7f 	bl	4558 <z_impl_k_sem_give>
}
    285a:	e7d7      	b.n	280c <transfer_next_chunk+0xe8>
			ctx->owner = NULL;
    285c:	2300      	movs	r3, #0
    285e:	6063      	str	r3, [r4, #4]
			k_sem_give(&ctx->lock);
    2860:	f104 0008 	add.w	r0, r4, #8
	z_impl_k_sem_give(sem);
    2864:	f001 fe78 	bl	4558 <z_impl_k_sem_give>
}
    2868:	e7d0      	b.n	280c <transfer_next_chunk+0xe8>
    286a:	bf00      	nop
    286c:	0bad0000 	.word	0x0bad0000

00002870 <baudrate_set>:
	return dev->data;
}

static inline const struct uarte_nrfx_config *get_dev_config(const struct device *dev)
{
	return dev->config;
    2870:	6843      	ldr	r3, [r0, #4]

static inline NRF_UARTE_Type *get_uarte_instance(const struct device *dev)
{
	const struct uarte_nrfx_config *config = get_dev_config(dev);

	return config->uarte_regs;
    2872:	681a      	ldr	r2, [r3, #0]
static int baudrate_set(const struct device *dev, uint32_t baudrate)
{
	nrf_uarte_baudrate_t nrf_baudrate; /* calculated baudrate divisor */
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);

	switch (baudrate) {
    2874:	f5b1 4f16 	cmp.w	r1, #38400	; 0x9600
    2878:	d06f      	beq.n	295a <baudrate_set+0xea>
    287a:	d83a      	bhi.n	28f2 <baudrate_set+0x82>
    287c:	f5b1 5f16 	cmp.w	r1, #9600	; 0x2580
    2880:	d06e      	beq.n	2960 <baudrate_set+0xf0>
    2882:	d90a      	bls.n	289a <baudrate_set+0x2a>
    2884:	f5b1 4fe1 	cmp.w	r1, #28800	; 0x7080
    2888:	d075      	beq.n	2976 <baudrate_set+0x106>
    288a:	d924      	bls.n	28d6 <baudrate_set+0x66>
    288c:	f647 2312 	movw	r3, #31250	; 0x7a12
    2890:	4299      	cmp	r1, r3
    2892:	d12b      	bne.n	28ec <baudrate_set+0x7c>
		break;
	case 28800:
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
		break;
	case 31250:
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    2894:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    2898:	e013      	b.n	28c2 <baudrate_set+0x52>
	switch (baudrate) {
    289a:	f5b1 6f96 	cmp.w	r1, #1200	; 0x4b0
    289e:	d061      	beq.n	2964 <baudrate_set+0xf4>
    28a0:	d907      	bls.n	28b2 <baudrate_set+0x42>
    28a2:	f5b1 6f16 	cmp.w	r1, #2400	; 0x960
    28a6:	d063      	beq.n	2970 <baudrate_set+0x100>
    28a8:	f5b1 5f96 	cmp.w	r1, #4800	; 0x12c0
    28ac:	d110      	bne.n	28d0 <baudrate_set+0x60>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    28ae:	4b3c      	ldr	r3, [pc, #240]	; (29a0 <baudrate_set+0x130>)
    28b0:	e007      	b.n	28c2 <baudrate_set+0x52>
	switch (baudrate) {
    28b2:	f5b1 7f96 	cmp.w	r1, #300	; 0x12c
    28b6:	d058      	beq.n	296a <baudrate_set+0xfa>
    28b8:	f5b1 7f16 	cmp.w	r1, #600	; 0x258
    28bc:	d105      	bne.n	28ca <baudrate_set+0x5a>
		nrf_baudrate = 0x00027000;
    28be:	f44f 331c 	mov.w	r3, #159744	; 0x27000
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    28c2:	f8c2 3524 	str.w	r3, [r2, #1316]	; 0x524
		return -EINVAL;
	}

	nrf_uarte_baudrate_set(uarte, nrf_baudrate);

	return 0;
    28c6:	2000      	movs	r0, #0
    28c8:	4770      	bx	lr
	switch (baudrate) {
    28ca:	f06f 0015 	mvn.w	r0, #21
    28ce:	4770      	bx	lr
    28d0:	f06f 0015 	mvn.w	r0, #21
    28d4:	4770      	bx	lr
    28d6:	f5b1 5f61 	cmp.w	r1, #14400	; 0x3840
    28da:	d04e      	beq.n	297a <baudrate_set+0x10a>
    28dc:	f5b1 4f96 	cmp.w	r1, #19200	; 0x4b00
    28e0:	d101      	bne.n	28e6 <baudrate_set+0x76>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    28e2:	4b30      	ldr	r3, [pc, #192]	; (29a4 <baudrate_set+0x134>)
    28e4:	e7ed      	b.n	28c2 <baudrate_set+0x52>
	switch (baudrate) {
    28e6:	f06f 0015 	mvn.w	r0, #21
    28ea:	4770      	bx	lr
    28ec:	f06f 0015 	mvn.w	r0, #21
    28f0:	4770      	bx	lr
    28f2:	f5b1 3f61 	cmp.w	r1, #230400	; 0x38400
    28f6:	d042      	beq.n	297e <baudrate_set+0x10e>
    28f8:	d909      	bls.n	290e <baudrate_set+0x9e>
    28fa:	f5b1 2f61 	cmp.w	r1, #921600	; 0xe1000
    28fe:	d046      	beq.n	298e <baudrate_set+0x11e>
    2900:	d91f      	bls.n	2942 <baudrate_set+0xd2>
    2902:	4b29      	ldr	r3, [pc, #164]	; (29a8 <baudrate_set+0x138>)
    2904:	4299      	cmp	r1, r3
    2906:	d148      	bne.n	299a <baudrate_set+0x12a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    2908:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    290c:	e7d9      	b.n	28c2 <baudrate_set+0x52>
	switch (baudrate) {
    290e:	f5b1 3f96 	cmp.w	r1, #76800	; 0x12c00
    2912:	d037      	beq.n	2984 <baudrate_set+0x114>
    2914:	d905      	bls.n	2922 <baudrate_set+0xb2>
    2916:	f5b1 3fe1 	cmp.w	r1, #115200	; 0x1c200
    291a:	d10f      	bne.n	293c <baudrate_set+0xcc>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    291c:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    2920:	e7cf      	b.n	28c2 <baudrate_set+0x52>
	switch (baudrate) {
    2922:	f64d 23c0 	movw	r3, #56000	; 0xdac0
    2926:	4299      	cmp	r1, r3
    2928:	d02e      	beq.n	2988 <baudrate_set+0x118>
    292a:	f5b1 4f61 	cmp.w	r1, #57600	; 0xe100
    292e:	d102      	bne.n	2936 <baudrate_set+0xc6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    2930:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    2934:	e7c5      	b.n	28c2 <baudrate_set+0x52>
	switch (baudrate) {
    2936:	f06f 0015 	mvn.w	r0, #21
    293a:	4770      	bx	lr
    293c:	f06f 0015 	mvn.w	r0, #21
    2940:	4770      	bx	lr
    2942:	4b1a      	ldr	r3, [pc, #104]	; (29ac <baudrate_set+0x13c>)
    2944:	4299      	cmp	r1, r3
    2946:	d025      	beq.n	2994 <baudrate_set+0x124>
    2948:	f5b1 2fe1 	cmp.w	r1, #460800	; 0x70800
    294c:	d102      	bne.n	2954 <baudrate_set+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    294e:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    2952:	e7b6      	b.n	28c2 <baudrate_set+0x52>
	switch (baudrate) {
    2954:	f06f 0015 	mvn.w	r0, #21
    2958:	4770      	bx	lr
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    295a:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    295e:	e7b0      	b.n	28c2 <baudrate_set+0x52>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    2960:	4b13      	ldr	r3, [pc, #76]	; (29b0 <baudrate_set+0x140>)
    2962:	e7ae      	b.n	28c2 <baudrate_set+0x52>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    2964:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    2968:	e7ab      	b.n	28c2 <baudrate_set+0x52>
	switch (baudrate) {
    296a:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    296e:	e7a8      	b.n	28c2 <baudrate_set+0x52>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    2970:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    2974:	e7a5      	b.n	28c2 <baudrate_set+0x52>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    2976:	4b0f      	ldr	r3, [pc, #60]	; (29b4 <baudrate_set+0x144>)
    2978:	e7a3      	b.n	28c2 <baudrate_set+0x52>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    297a:	4b0f      	ldr	r3, [pc, #60]	; (29b8 <baudrate_set+0x148>)
    297c:	e7a1      	b.n	28c2 <baudrate_set+0x52>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    297e:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    2982:	e79e      	b.n	28c2 <baudrate_set+0x52>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    2984:	4b0d      	ldr	r3, [pc, #52]	; (29bc <baudrate_set+0x14c>)
    2986:	e79c      	b.n	28c2 <baudrate_set+0x52>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    2988:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    298c:	e799      	b.n	28c2 <baudrate_set+0x52>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    298e:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    2992:	e796      	b.n	28c2 <baudrate_set+0x52>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    2994:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    2998:	e793      	b.n	28c2 <baudrate_set+0x52>
	switch (baudrate) {
    299a:	f06f 0015 	mvn.w	r0, #21
}
    299e:	4770      	bx	lr
    29a0:	0013b000 	.word	0x0013b000
    29a4:	004ea000 	.word	0x004ea000
    29a8:	000f4240 	.word	0x000f4240
    29ac:	0003d090 	.word	0x0003d090
    29b0:	00275000 	.word	0x00275000
    29b4:	0075c000 	.word	0x0075c000
    29b8:	003af000 	.word	0x003af000
    29bc:	013a9000 	.word	0x013a9000

000029c0 <uarte_nrfx_poll_out>:
 *
 * @param dev UARTE device struct
 * @param c Character to send
 */
static void uarte_nrfx_poll_out(const struct device *dev, unsigned char c)
{
    29c0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    29c4:	4605      	mov	r5, r0
    29c6:	460f      	mov	r7, r1
	return dev->data;
    29c8:	f8d0 8010 	ldr.w	r8, [r0, #16]
	struct uarte_nrfx_data *data = get_dev_data(dev);
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    29cc:	f004 fa5c 	bl	6e88 <k_is_in_isr>
    29d0:	b920      	cbnz	r0, 29dc <uarte_nrfx_poll_out+0x1c>
	return !z_sys_post_kernel;
    29d2:	4b16      	ldr	r3, [pc, #88]	; (2a2c <uarte_nrfx_poll_out+0x6c>)
    29d4:	781b      	ldrb	r3, [r3, #0]
    29d6:	b1ab      	cbz	r3, 2a04 <uarte_nrfx_poll_out+0x44>
    29d8:	2300      	movs	r3, #0
    29da:	e000      	b.n	29de <uarte_nrfx_poll_out+0x1e>
    29dc:	2301      	movs	r3, #1
	int key;

	if (isr_mode) {
    29de:	b19b      	cbz	r3, 2a08 <uarte_nrfx_poll_out+0x48>
	__asm__ volatile(
    29e0:	f04f 0320 	mov.w	r3, #32
    29e4:	f3ef 8411 	mrs	r4, BASEPRI
    29e8:	f383 8812 	msr	BASEPRI_MAX, r3
    29ec:	f3bf 8f6f 	isb	sy
		while (1) {
			key = irq_lock();
    29f0:	4626      	mov	r6, r4
			if (is_tx_ready(dev)) {
    29f2:	4628      	mov	r0, r5
    29f4:	f004 f84f 	bl	6a96 <is_tx_ready>
    29f8:	b950      	cbnz	r0, 2a10 <uarte_nrfx_poll_out+0x50>
	__asm__ volatile(
    29fa:	f384 8811 	msr	BASEPRI, r4
    29fe:	f3bf 8f6f 	isb	sy
}
    2a02:	e7ed      	b.n	29e0 <uarte_nrfx_poll_out+0x20>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    2a04:	2301      	movs	r3, #1
    2a06:	e7ea      	b.n	29de <uarte_nrfx_poll_out+0x1e>
			}

			irq_unlock(key);
		}
	} else {
		key = wait_tx_ready(dev);
    2a08:	4628      	mov	r0, r5
    2a0a:	f004 f893 	bl	6b34 <wait_tx_ready>
    2a0e:	4606      	mov	r6, r0
	}

	data->char_out = c;
    2a10:	4641      	mov	r1, r8
    2a12:	f801 7f10 	strb.w	r7, [r1, #16]!
	tx_start(dev, &data->char_out, 1);
    2a16:	2201      	movs	r2, #1
    2a18:	4628      	mov	r0, r5
    2a1a:	f004 f856 	bl	6aca <tx_start>
	__asm__ volatile(
    2a1e:	f386 8811 	msr	BASEPRI, r6
    2a22:	f3bf 8f6f 	isb	sy

	irq_unlock(key);
}
    2a26:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    2a2a:	bf00      	nop
    2a2c:	20000ae2 	.word	0x20000ae2

00002a30 <endtx_stoptx_ppi_init>:
#endif /* UARTE_INTERRUPT_DRIVEN */
};

static int endtx_stoptx_ppi_init(NRF_UARTE_Type *uarte,
				 struct uarte_nrfx_data *data)
{
    2a30:	b538      	push	{r3, r4, r5, lr}
    2a32:	4604      	mov	r4, r0
    2a34:	460d      	mov	r5, r1
	nrfx_err_t ret;

	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    2a36:	f101 0012 	add.w	r0, r1, #18
    2a3a:	f000 fdb3 	bl	35a4 <nrfx_ppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    2a3e:	4b0c      	ldr	r3, [pc, #48]	; (2a70 <endtx_stoptx_ppi_init+0x40>)
    2a40:	4298      	cmp	r0, r3
    2a42:	d111      	bne.n	2a68 <endtx_stoptx_ppi_init+0x38>
		LOG_ERR("Failed to allocate PPI Channel");
		return -EIO;
	}

	nrfx_gppi_channel_endpoints_setup(data->ppi_ch_endtx,
    2a44:	7cab      	ldrb	r3, [r5, #18]
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    2a46:	f504 7190 	add.w	r1, r4, #288	; 0x120
    return (uint32_t)p_reg + (uint32_t)task;
    2a4a:	340c      	adds	r4, #12
NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type *    p_reg,
                                                      nrf_ppi_channel_t channel,
                                                      uint32_t          eep,
                                                      uint32_t          tep)
{
    p_reg->CH[(uint32_t) channel].EEP = eep;
    2a4c:	4a09      	ldr	r2, [pc, #36]	; (2a74 <endtx_stoptx_ppi_init+0x44>)
    2a4e:	33a2      	adds	r3, #162	; 0xa2
    2a50:	f842 1033 	str.w	r1, [r2, r3, lsl #3]
    p_reg->CH[(uint32_t) channel].TEP = tep;
    2a54:	eb02 03c3 	add.w	r3, r2, r3, lsl #3
    2a58:	605c      	str	r4, [r3, #4]
		nrf_uarte_event_address_get(uarte, NRF_UARTE_EVENT_ENDTX),
		nrf_uarte_task_address_get(uarte, NRF_UARTE_TASK_STOPTX));
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    2a5a:	7ca9      	ldrb	r1, [r5, #18]
    2a5c:	2301      	movs	r3, #1
    2a5e:	408b      	lsls	r3, r1
    p_reg->CHENSET = mask;
    2a60:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504

	return 0;
    2a64:	2000      	movs	r0, #0
}
    2a66:	bd38      	pop	{r3, r4, r5, pc}
		return -EIO;
    2a68:	f06f 0004 	mvn.w	r0, #4
    2a6c:	e7fb      	b.n	2a66 <endtx_stoptx_ppi_init+0x36>
    2a6e:	bf00      	nop
    2a70:	0bad0000 	.word	0x0bad0000
    2a74:	4001f000 	.word	0x4001f000

00002a78 <uarte_instance_init>:

static int uarte_instance_init(const struct device *dev,
			       uint8_t interrupts_active)
{
    2a78:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	return dev->config;
    2a7a:	6844      	ldr	r4, [r0, #4]
	return config->uarte_regs;
    2a7c:	6825      	ldr	r5, [r4, #0]
	return dev->data;
    2a7e:	6906      	ldr	r6, [r0, #16]
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    2a80:	2300      	movs	r3, #0
    2a82:	f8c5 3500 	str.w	r3, [r5, #1280]	; 0x500
	struct uarte_nrfx_data *data = get_dev_data(dev);
	const struct uarte_nrfx_config *cfg = get_dev_config(dev);

	nrf_uarte_disable(uarte);

	data->dev = dev;
    2a86:	6030      	str	r0, [r6, #0]

	nrf_gpio_pin_write(cfg->pseltxd, 1);
    2a88:	68a3      	ldr	r3, [r4, #8]
    *p_pin = pin_number & 0x1F;
    2a8a:	f003 011f 	and.w	r1, r3, #31
    return pin_number >> 5;
    2a8e:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    2a90:	2b01      	cmp	r3, #1
    2a92:	f000 8097 	beq.w	2bc4 <uarte_instance_init+0x14c>
        case 0: return NRF_P0;
    2a96:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2a9a:	2301      	movs	r3, #1
    2a9c:	408b      	lsls	r3, r1
    p_reg->OUTSET = set_mask;
    2a9e:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
	nrf_gpio_cfg_output(cfg->pseltxd);
    2aa2:	68a3      	ldr	r3, [r4, #8]
    *p_pin = pin_number & 0x1F;
    2aa4:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    2aa8:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    2aaa:	2b01      	cmp	r3, #1
    2aac:	f000 808c 	beq.w	2bc8 <uarte_instance_init+0x150>
        case 0: return NRF_P0;
    2ab0:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    2ab4:	f502 73e0 	add.w	r3, r2, #448	; 0x1c0
    2ab8:	2203      	movs	r2, #3
    2aba:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

	if (cfg->pselrxd !=  NRF_UARTE_PSEL_DISCONNECTED) {
    2abe:	68e3      	ldr	r3, [r4, #12]
    2ac0:	f1b3 3fff 	cmp.w	r3, #4294967295
    2ac4:	d00c      	beq.n	2ae0 <uarte_instance_init+0x68>
		nrf_gpio_cfg_input(cfg->pselrxd, cfg->rxd_pull);
    2ac6:	7e21      	ldrb	r1, [r4, #24]
    *p_pin = pin_number & 0x1F;
    2ac8:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    2acc:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    2ace:	2b01      	cmp	r3, #1
    2ad0:	d07c      	beq.n	2bcc <uarte_instance_init+0x154>
        case 0: return NRF_P0;
    2ad2:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    2ad6:	0089      	lsls	r1, r1, #2
    reg->PIN_CNF[pin_number] = cnf;
    2ad8:	f502 73e0 	add.w	r3, r2, #448	; 0x1c0
    2adc:	f847 1023 	str.w	r1, [r7, r3, lsl #2]
	}

	nrf_uarte_txrx_pins_set(uarte, cfg->pseltxd, cfg->pselrxd);
    2ae0:	68a2      	ldr	r2, [r4, #8]
    2ae2:	68e3      	ldr	r3, [r4, #12]
    p_reg->PSEL.TXD = pseltxd;
    2ae4:	f8c5 250c 	str.w	r2, [r5, #1292]	; 0x50c
    p_reg->PSEL.RXD = pselrxd;
    2ae8:	f8c5 3514 	str.w	r3, [r5, #1300]	; 0x514

	if (cfg->pselcts != NRF_UARTE_PSEL_DISCONNECTED) {
    2aec:	6923      	ldr	r3, [r4, #16]
    2aee:	f1b3 3fff 	cmp.w	r3, #4294967295
    2af2:	d00c      	beq.n	2b0e <uarte_instance_init+0x96>
		nrf_gpio_cfg_input(cfg->pselcts, cfg->cts_pull);
    2af4:	7e61      	ldrb	r1, [r4, #25]
    *p_pin = pin_number & 0x1F;
    2af6:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    2afa:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    2afc:	2b01      	cmp	r3, #1
    2afe:	d067      	beq.n	2bd0 <uarte_instance_init+0x158>
        case 0: return NRF_P0;
    2b00:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    2b04:	0089      	lsls	r1, r1, #2
    reg->PIN_CNF[pin_number] = cnf;
    2b06:	f502 73e0 	add.w	r3, r2, #448	; 0x1c0
    2b0a:	f847 1023 	str.w	r1, [r7, r3, lsl #2]
	}

	if (cfg->pselrts != NRF_UARTE_PSEL_DISCONNECTED) {
    2b0e:	6963      	ldr	r3, [r4, #20]
    2b10:	f1b3 3fff 	cmp.w	r3, #4294967295
    2b14:	d017      	beq.n	2b46 <uarte_instance_init+0xce>
    *p_pin = pin_number & 0x1F;
    2b16:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    2b1a:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    2b1c:	2b01      	cmp	r3, #1
    2b1e:	d059      	beq.n	2bd4 <uarte_instance_init+0x15c>
        case 0: return NRF_P0;
    2b20:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2b24:	2301      	movs	r3, #1
    2b26:	4093      	lsls	r3, r2
    p_reg->OUTSET = set_mask;
    2b28:	f8c1 3508 	str.w	r3, [r1, #1288]	; 0x508
		nrf_gpio_pin_write(cfg->pselrts, 1);
		nrf_gpio_cfg_output(cfg->pselrts);
    2b2c:	6963      	ldr	r3, [r4, #20]
    *p_pin = pin_number & 0x1F;
    2b2e:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    2b32:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    2b34:	2b01      	cmp	r3, #1
    2b36:	d04f      	beq.n	2bd8 <uarte_instance_init+0x160>
        case 0: return NRF_P0;
    2b38:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    2b3c:	f502 73e0 	add.w	r3, r2, #448	; 0x1c0
    2b40:	2203      	movs	r2, #3
    2b42:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
	}

	nrf_uarte_hwfc_pins_set(uarte, cfg->pselrts, cfg->pselcts);
    2b46:	6962      	ldr	r2, [r4, #20]
    2b48:	6923      	ldr	r3, [r4, #16]
    p_reg->PSEL.RTS = pselrts;
    2b4a:	f8c5 2508 	str.w	r2, [r5, #1288]	; 0x508
    p_reg->PSEL.CTS = pselcts;
    2b4e:	f8c5 3510 	str.w	r3, [r5, #1296]	; 0x510
	return dev->data;
    2b52:	6901      	ldr	r1, [r0, #16]

	err = uarte_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
    2b54:	3104      	adds	r1, #4
    2b56:	f003 ff22 	bl	699e <uarte_nrfx_configure>
	if (err) {
    2b5a:	4607      	mov	r7, r0
    2b5c:	bb80      	cbnz	r0, 2bc0 <uarte_instance_init+0x148>
		return err;
	}

	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
	    cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX) {
    2b5e:	6863      	ldr	r3, [r4, #4]
	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
    2b60:	f013 0f08 	tst.w	r3, #8
    2b64:	d13a      	bne.n	2bdc <uarte_instance_init+0x164>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    2b66:	2308      	movs	r3, #8
    2b68:	f8c5 3500 	str.w	r3, [r5, #1280]	; 0x500
#endif
	{
		/* Enable receiver and transmitter */
		nrf_uarte_enable(uarte);

		if (cfg->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
    2b6c:	68e3      	ldr	r3, [r4, #12]
    2b6e:	f1b3 3fff 	cmp.w	r3, #4294967295
    2b72:	d00c      	beq.n	2b8e <uarte_instance_init+0x116>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2b74:	2300      	movs	r3, #0
    2b76:	f8c5 3110 	str.w	r3, [r5, #272]	; 0x110
    2b7a:	f8d5 3110 	ldr.w	r3, [r5, #272]	; 0x110
			nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);

			nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
    2b7e:	f106 0311 	add.w	r3, r6, #17

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    2b82:	f8c5 3534 	str.w	r3, [r5, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    2b86:	2301      	movs	r3, #1
    2b88:	f8c5 3538 	str.w	r3, [r5, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2b8c:	602b      	str	r3, [r5, #0]
			nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTRX);
		}
	}

	if (!(cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX)) {
    2b8e:	6863      	ldr	r3, [r4, #4]
    2b90:	f013 0f08 	tst.w	r3, #8
    2b94:	d103      	bne.n	2b9e <uarte_instance_init+0x126>
    p_reg->INTENSET = mask;
    2b96:	f44f 7380 	mov.w	r3, #256	; 0x100
    2b9a:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
		nrf_uarte_int_enable(uarte, NRF_UARTE_INT_ENDTX_MASK);
	}

	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    2b9e:	6863      	ldr	r3, [r4, #4]
    2ba0:	f013 0f10 	tst.w	r3, #16
    2ba4:	d003      	beq.n	2bae <uarte_instance_init+0x136>
    2ba6:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
    2baa:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304

	/* Set TXSTOPPED event by requesting fake (zero-length) transfer.
	 * Pointer to RAM variable (data->tx_buffer) is set because otherwise
	 * such operation may result in HardFault or RAM corruption.
	 */
	nrf_uarte_tx_buffer_set(uarte, &data->char_out, 0);
    2bae:	3610      	adds	r6, #16
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    2bb0:	f8c5 6544 	str.w	r6, [r5, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    2bb4:	2300      	movs	r3, #0
    2bb6:	f8c5 3548 	str.w	r3, [r5, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2bba:	2301      	movs	r3, #1
    2bbc:	60ab      	str	r3, [r5, #8]
    2bbe:	60eb      	str	r3, [r5, #12]

	/* switch off transmitter to save an energy */
	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPTX);

	return 0;
}
    2bc0:	4638      	mov	r0, r7
    2bc2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        case 1: return NRF_P1;
    2bc4:	4a09      	ldr	r2, [pc, #36]	; (2bec <uarte_instance_init+0x174>)
    2bc6:	e768      	b.n	2a9a <uarte_instance_init+0x22>
    2bc8:	4908      	ldr	r1, [pc, #32]	; (2bec <uarte_instance_init+0x174>)
    2bca:	e773      	b.n	2ab4 <uarte_instance_init+0x3c>
    2bcc:	4f07      	ldr	r7, [pc, #28]	; (2bec <uarte_instance_init+0x174>)
    2bce:	e782      	b.n	2ad6 <uarte_instance_init+0x5e>
    2bd0:	4f06      	ldr	r7, [pc, #24]	; (2bec <uarte_instance_init+0x174>)
    2bd2:	e797      	b.n	2b04 <uarte_instance_init+0x8c>
    2bd4:	4905      	ldr	r1, [pc, #20]	; (2bec <uarte_instance_init+0x174>)
    2bd6:	e7a5      	b.n	2b24 <uarte_instance_init+0xac>
    2bd8:	4904      	ldr	r1, [pc, #16]	; (2bec <uarte_instance_init+0x174>)
    2bda:	e7af      	b.n	2b3c <uarte_instance_init+0xc4>
		err = endtx_stoptx_ppi_init(uarte, data);
    2bdc:	4631      	mov	r1, r6
    2bde:	4628      	mov	r0, r5
    2be0:	f7ff ff26 	bl	2a30 <endtx_stoptx_ppi_init>
		if (err < 0) {
    2be4:	2800      	cmp	r0, #0
    2be6:	dabe      	bge.n	2b66 <uarte_instance_init+0xee>
			return err;
    2be8:	4607      	mov	r7, r0
    2bea:	e7e9      	b.n	2bc0 <uarte_instance_init+0x148>
    2bec:	50000300 	.word	0x50000300

00002bf0 <set_comparator>:
	return (a - b) & COUNTER_MAX;
}

static void set_comparator(int32_t chan, uint32_t cyc)
{
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    2bf0:	f021 417f 	bic.w	r1, r1, #4278190080	; 0xff000000

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE  void nrf_rtc_cc_set(NRF_RTC_Type * p_reg, uint32_t ch, uint32_t cc_val)
{
    p_reg->CC[ch] = cc_val;
    2bf4:	f500 70a8 	add.w	r0, r0, #336	; 0x150
    2bf8:	4b01      	ldr	r3, [pc, #4]	; (2c00 <set_comparator+0x10>)
    2bfa:	f843 1020 	str.w	r1, [r3, r0, lsl #2]
}
    2bfe:	4770      	bx	lr
    2c00:	40011000 	.word	0x40011000

00002c04 <get_comparator>:
}

NRF_STATIC_INLINE  uint32_t nrf_rtc_cc_get(NRF_RTC_Type const * p_reg, uint32_t ch)
{
    return p_reg->CC[ch];
    2c04:	f500 70a8 	add.w	r0, r0, #336	; 0x150
    2c08:	4b01      	ldr	r3, [pc, #4]	; (2c10 <get_comparator+0xc>)
    2c0a:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]

static uint32_t get_comparator(int32_t chan)
{
	return nrf_rtc_cc_get(RTC, chan);
}
    2c0e:	4770      	bx	lr
    2c10:	40011000 	.word	0x40011000

00002c14 <event_enable>:
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
}

static void event_enable(int32_t chan)
{
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2c14:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    2c18:	4083      	lsls	r3, r0
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
    2c1a:	4a02      	ldr	r2, [pc, #8]	; (2c24 <event_enable+0x10>)
    2c1c:	f8c2 3344 	str.w	r3, [r2, #836]	; 0x344
}
    2c20:	4770      	bx	lr
    2c22:	bf00      	nop
    2c24:	40011000 	.word	0x40011000

00002c28 <event_disable>:

static void event_disable(int32_t chan)
{
	nrf_rtc_event_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2c28:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    2c2c:	4083      	lsls	r3, r0
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    2c2e:	4a02      	ldr	r2, [pc, #8]	; (2c38 <event_disable+0x10>)
    2c30:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
}
    2c34:	4770      	bx	lr
    2c36:	bf00      	nop
    2c38:	40011000 	.word	0x40011000

00002c3c <counter>:
     return p_reg->COUNTER;
    2c3c:	4b01      	ldr	r3, [pc, #4]	; (2c44 <counter+0x8>)
    2c3e:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504

static uint32_t counter(void)
{
	return nrf_rtc_counter_get(RTC);
}
    2c42:	4770      	bx	lr
    2c44:	40011000 	.word	0x40011000

00002c48 <compare_int_lock>:
	__ASSERT_NO_MSG(chan < CHAN_COUNT);
	return nrf_rtc_event_address_get(RTC, nrf_rtc_compare_event_get(chan));
}

static bool compare_int_lock(int32_t chan)
{
    2c48:	b510      	push	{r4, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    2c4a:	2301      	movs	r3, #1
    2c4c:	4083      	lsls	r3, r0
    2c4e:	43dc      	mvns	r4, r3
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    2c50:	4a10      	ldr	r2, [pc, #64]	; (2c94 <compare_int_lock+0x4c>)
    2c52:	f3bf 8f5b 	dmb	ish
    2c56:	e852 1f00 	ldrex	r1, [r2]
    2c5a:	ea01 0c04 	and.w	ip, r1, r4
    2c5e:	e842 ce00 	strex	lr, ip, [r2]
    2c62:	f1be 0f00 	cmp.w	lr, #0
    2c66:	d1f6      	bne.n	2c56 <compare_int_lock+0xe>
    2c68:	f3bf 8f5b 	dmb	ish

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2c6c:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    2c70:	fa02 f000 	lsl.w	r0, r2, r0
    p_reg->INTENCLR = mask;
    2c74:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    2c78:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
    2c7c:	f8c2 0308 	str.w	r0, [r2, #776]	; 0x308
    2c80:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2c84:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    2c88:	420b      	tst	r3, r1
}
    2c8a:	bf14      	ite	ne
    2c8c:	2001      	movne	r0, #1
    2c8e:	2000      	moveq	r0, #0
    2c90:	bd10      	pop	{r4, pc}
    2c92:	bf00      	nop
    2c94:	20000500 	.word	0x20000500

00002c98 <channel_processing_check_and_clear>:
		event_enable(chan);
	}
}

static bool channel_processing_check_and_clear(int32_t chan)
{
    2c98:	b570      	push	{r4, r5, r6, lr}
    2c9a:	4604      	mov	r4, r0
	bool result = false;

	uint32_t mcu_critical_state = full_int_lock();
    2c9c:	f003 ffa4 	bl	6be8 <full_int_lock>
    2ca0:	4605      	mov	r5, r0

	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    2ca2:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    2ca6:	40a3      	lsls	r3, r4
    return p_reg->INTENSET & mask;
    2ca8:	4a17      	ldr	r2, [pc, #92]	; (2d08 <channel_processing_check_and_clear+0x70>)
    2caa:	f8d2 2304 	ldr.w	r2, [r2, #772]	; 0x304
    2cae:	4213      	tst	r3, r2
    2cb0:	d105      	bne.n	2cbe <channel_processing_check_and_clear+0x26>
	bool result = false;
    2cb2:	2600      	movs	r6, #0
		if (result) {
			event_clear(chan);
		}
	}

	full_int_unlock(mcu_critical_state);
    2cb4:	4628      	mov	r0, r5
    2cb6:	f003 ffa0 	bl	6bfa <full_int_unlock>

	return result;
}
    2cba:	4630      	mov	r0, r6
    2cbc:	bd70      	pop	{r4, r5, r6, pc}
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    2cbe:	2301      	movs	r3, #1
    2cc0:	40a3      	lsls	r3, r4
    2cc2:	43db      	mvns	r3, r3
    2cc4:	4a11      	ldr	r2, [pc, #68]	; (2d0c <channel_processing_check_and_clear+0x74>)
    2cc6:	f3bf 8f5b 	dmb	ish
    2cca:	e852 1f00 	ldrex	r1, [r2]
    2cce:	ea01 0003 	and.w	r0, r1, r3
    2cd2:	e842 0600 	strex	r6, r0, [r2]
    2cd6:	2e00      	cmp	r6, #0
    2cd8:	d1f7      	bne.n	2cca <channel_processing_check_and_clear+0x32>
    2cda:	f3bf 8f5b 	dmb	ish
    2cde:	b959      	cbnz	r1, 2cf8 <channel_processing_check_and_clear+0x60>
			 nrf_rtc_event_check(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    2ce0:	f104 0350 	add.w	r3, r4, #80	; 0x50
    2ce4:	009b      	lsls	r3, r3, #2
    2ce6:	b29b      	uxth	r3, r3
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2ce8:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    2cec:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    2cf0:	681b      	ldr	r3, [r3, #0]
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    2cf2:	b113      	cbz	r3, 2cfa <channel_processing_check_and_clear+0x62>
    2cf4:	2301      	movs	r3, #1
    2cf6:	e000      	b.n	2cfa <channel_processing_check_and_clear+0x62>
    2cf8:	2301      	movs	r3, #1
		if (result) {
    2cfa:	461e      	mov	r6, r3
    2cfc:	2b00      	cmp	r3, #0
    2cfe:	d0d9      	beq.n	2cb4 <channel_processing_check_and_clear+0x1c>
			event_clear(chan);
    2d00:	4620      	mov	r0, r4
    2d02:	f003 ff62 	bl	6bca <event_clear>
    2d06:	e7d5      	b.n	2cb4 <channel_processing_check_and_clear+0x1c>
    2d08:	40011000 	.word	0x40011000
    2d0c:	200004fc 	.word	0x200004fc

00002d10 <compare_int_unlock>:
	if (key) {
    2d10:	b901      	cbnz	r1, 2d14 <compare_int_unlock+0x4>
}
    2d12:	4770      	bx	lr
		atomic_or(&int_mask, BIT(chan));
    2d14:	2301      	movs	r3, #1
    2d16:	4083      	lsls	r3, r0
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    2d18:	4a11      	ldr	r2, [pc, #68]	; (2d60 <compare_int_unlock+0x50>)
    2d1a:	f3bf 8f5b 	dmb	ish
    2d1e:	e852 1f00 	ldrex	r1, [r2]
    2d22:	4319      	orrs	r1, r3
    2d24:	e842 1c00 	strex	ip, r1, [r2]
    2d28:	f1bc 0f00 	cmp.w	ip, #0
    2d2c:	d1f7      	bne.n	2d1e <compare_int_unlock+0xe>
    2d2e:	f3bf 8f5b 	dmb	ish
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2d32:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    2d36:	4083      	lsls	r3, r0
    p_reg->INTENSET = mask;
    2d38:	4a0a      	ldr	r2, [pc, #40]	; (2d64 <compare_int_unlock+0x54>)
    2d3a:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    2d3e:	f3bf 8f5b 	dmb	ish
    2d42:	4b09      	ldr	r3, [pc, #36]	; (2d68 <compare_int_unlock+0x58>)
    2d44:	681b      	ldr	r3, [r3, #0]
    2d46:	f3bf 8f5b 	dmb	ish
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    2d4a:	fa23 f000 	lsr.w	r0, r3, r0
    2d4e:	f010 0f01 	tst.w	r0, #1
    2d52:	d0de      	beq.n	2d12 <compare_int_unlock+0x2>
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2d54:	4b05      	ldr	r3, [pc, #20]	; (2d6c <compare_int_unlock+0x5c>)
    2d56:	f44f 3200 	mov.w	r2, #131072	; 0x20000
    2d5a:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
}
    2d5e:	e7d8      	b.n	2d12 <compare_int_unlock+0x2>
    2d60:	20000500 	.word	0x20000500
    2d64:	40011000 	.word	0x40011000
    2d68:	200004fc 	.word	0x200004fc
    2d6c:	e000e100 	.word	0xe000e100

00002d70 <sys_clock_timeout_handler>:
{
    2d70:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2d72:	4607      	mov	r7, r0
    2d74:	4614      	mov	r4, r2
    2d76:	461e      	mov	r6, r3
	uint32_t cc_value = absolute_time_to_cc(expire_time);
    2d78:	4610      	mov	r0, r2
    2d7a:	4619      	mov	r1, r3
    2d7c:	f003 ff31 	bl	6be2 <absolute_time_to_cc>
    2d80:	4605      	mov	r5, r0
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2d82:	4b15      	ldr	r3, [pc, #84]	; (2dd8 <sys_clock_timeout_handler+0x68>)
    2d84:	681a      	ldr	r2, [r3, #0]
    2d86:	1aa0      	subs	r0, r4, r2
	last_count += dticks * CYC_PER_TICK;
    2d88:	601c      	str	r4, [r3, #0]
    2d8a:	605e      	str	r6, [r3, #4]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    2d8c:	f5a5 1300 	sub.w	r3, r5, #2097152	; 0x200000
	if (in_anchor_range(cc_value)) {
    2d90:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    2d94:	d308      	bcc.n	2da8 <sys_clock_timeout_handler+0x38>
	return false;
    2d96:	2400      	movs	r4, #0
	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    2d98:	f002 f8ea 	bl	4f70 <sys_clock_announce>
	if (cc_value == get_comparator(chan)) {
    2d9c:	4638      	mov	r0, r7
    2d9e:	f7ff ff31 	bl	2c04 <get_comparator>
    2da2:	42a8      	cmp	r0, r5
    2da4:	d00c      	beq.n	2dc0 <sys_clock_timeout_handler+0x50>
}
    2da6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    2da8:	4b0c      	ldr	r3, [pc, #48]	; (2ddc <sys_clock_timeout_handler+0x6c>)
    2daa:	6819      	ldr	r1, [r3, #0]
    2dac:	0a0b      	lsrs	r3, r1, #8
    2dae:	060a      	lsls	r2, r1, #24
    2db0:	1952      	adds	r2, r2, r5
    2db2:	f143 0300 	adc.w	r3, r3, #0
    2db6:	490a      	ldr	r1, [pc, #40]	; (2de0 <sys_clock_timeout_handler+0x70>)
    2db8:	e9c1 2300 	strd	r2, r3, [r1]
		return true;
    2dbc:	2401      	movs	r4, #1
    2dbe:	e7eb      	b.n	2d98 <sys_clock_timeout_handler+0x28>
		if (!anchor_updated) {
    2dc0:	b11c      	cbz	r4, 2dca <sys_clock_timeout_handler+0x5a>
		event_enable(chan);
    2dc2:	4638      	mov	r0, r7
    2dc4:	f7ff ff26 	bl	2c14 <event_enable>
}
    2dc8:	e7ed      	b.n	2da6 <sys_clock_timeout_handler+0x36>
			set_comparator(chan, COUNTER_HALF_SPAN);
    2dca:	f44f 0100 	mov.w	r1, #8388608	; 0x800000
    2dce:	4638      	mov	r0, r7
    2dd0:	f7ff ff0e 	bl	2bf0 <set_comparator>
    2dd4:	e7f5      	b.n	2dc2 <sys_clock_timeout_handler+0x52>
    2dd6:	bf00      	nop
    2dd8:	200001e0 	.word	0x200001e0
    2ddc:	20000504 	.word	0x20000504
    2de0:	200001c8 	.word	0x200001c8

00002de4 <z_nrf_rtc_timer_read>:
{
    2de4:	b538      	push	{r3, r4, r5, lr}
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    2de6:	4b0d      	ldr	r3, [pc, #52]	; (2e1c <z_nrf_rtc_timer_read+0x38>)
    2de8:	681b      	ldr	r3, [r3, #0]
    2dea:	0a1d      	lsrs	r5, r3, #8
    2dec:	061c      	lsls	r4, r3, #24
  __ASM volatile ("dmb 0xF":::"memory");
    2dee:	f3bf 8f5f 	dmb	sy
	uint32_t cntr = counter();
    2df2:	f7ff ff23 	bl	2c3c <counter>
    2df6:	4603      	mov	r3, r0
	val += cntr;
    2df8:	1820      	adds	r0, r4, r0
    2dfa:	f145 0100 	adc.w	r1, r5, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    2dfe:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    2e02:	d20a      	bcs.n	2e1a <z_nrf_rtc_timer_read+0x36>
		if (val < anchor) {
    2e04:	4b06      	ldr	r3, [pc, #24]	; (2e20 <z_nrf_rtc_timer_read+0x3c>)
    2e06:	e9d3 2300 	ldrd	r2, r3, [r3]
    2e0a:	4299      	cmp	r1, r3
    2e0c:	bf08      	it	eq
    2e0e:	4290      	cmpeq	r0, r2
    2e10:	d203      	bcs.n	2e1a <z_nrf_rtc_timer_read+0x36>
			val += COUNTER_SPAN;
    2e12:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    2e16:	f141 0100 	adc.w	r1, r1, #0
}
    2e1a:	bd38      	pop	{r3, r4, r5, pc}
    2e1c:	20000504 	.word	0x20000504
    2e20:	200001c8 	.word	0x200001c8

00002e24 <compare_set_nolocks>:
{
    2e24:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    2e28:	4606      	mov	r6, r0
    2e2a:	4614      	mov	r4, r2
    2e2c:	461d      	mov	r5, r3
	uint32_t cc_value = absolute_time_to_cc(target_time);
    2e2e:	4610      	mov	r0, r2
    2e30:	4619      	mov	r1, r3
    2e32:	f003 fed6 	bl	6be2 <absolute_time_to_cc>
    2e36:	4607      	mov	r7, r0
	uint64_t curr_time = z_nrf_rtc_timer_read();
    2e38:	f7ff ffd4 	bl	2de4 <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    2e3c:	42a9      	cmp	r1, r5
    2e3e:	bf08      	it	eq
    2e40:	42a0      	cmpeq	r0, r4
    2e42:	d21e      	bcs.n	2e82 <compare_set_nolocks+0x5e>
		if (target_time - curr_time > COUNTER_SPAN) {
    2e44:	ebb4 0800 	subs.w	r8, r4, r0
    2e48:	eb65 0901 	sbc.w	r9, r5, r1
    2e4c:	f04f 7280 	mov.w	r2, #16777216	; 0x1000000
    2e50:	2300      	movs	r3, #0
    2e52:	454b      	cmp	r3, r9
    2e54:	bf08      	it	eq
    2e56:	4542      	cmpeq	r2, r8
    2e58:	d32e      	bcc.n	2eb8 <compare_set_nolocks+0x94>
		if (target_time != cc_data[chan].target_time) {
    2e5a:	4b19      	ldr	r3, [pc, #100]	; (2ec0 <compare_set_nolocks+0x9c>)
    2e5c:	eb03 1306 	add.w	r3, r3, r6, lsl #4
    2e60:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
    2e64:	42ab      	cmp	r3, r5
    2e66:	bf08      	it	eq
    2e68:	42a2      	cmpeq	r2, r4
    2e6a:	d018      	beq.n	2e9e <compare_set_nolocks+0x7a>
			uint32_t cc_set = set_absolute_alarm(chan, cc_value);
    2e6c:	4639      	mov	r1, r7
    2e6e:	4630      	mov	r0, r6
    2e70:	f003 fec8 	bl	6c04 <set_absolute_alarm>
			target_time += counter_sub(cc_set, cc_value);
    2e74:	4639      	mov	r1, r7
    2e76:	f003 fea4 	bl	6bc2 <counter_sub>
    2e7a:	1824      	adds	r4, r4, r0
    2e7c:	f145 0500 	adc.w	r5, r5, #0
    2e80:	e00d      	b.n	2e9e <compare_set_nolocks+0x7a>
		atomic_or(&force_isr_mask, BIT(chan));
    2e82:	2301      	movs	r3, #1
    2e84:	40b3      	lsls	r3, r6
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    2e86:	4a0f      	ldr	r2, [pc, #60]	; (2ec4 <compare_set_nolocks+0xa0>)
    2e88:	f3bf 8f5b 	dmb	ish
    2e8c:	e852 1f00 	ldrex	r1, [r2]
    2e90:	4319      	orrs	r1, r3
    2e92:	e842 1000 	strex	r0, r1, [r2]
    2e96:	2800      	cmp	r0, #0
    2e98:	d1f8      	bne.n	2e8c <compare_set_nolocks+0x68>
    2e9a:	f3bf 8f5b 	dmb	ish
	cc_data[chan].target_time = target_time;
    2e9e:	4b08      	ldr	r3, [pc, #32]	; (2ec0 <compare_set_nolocks+0x9c>)
    2ea0:	0132      	lsls	r2, r6, #4
    2ea2:	eb03 1606 	add.w	r6, r3, r6, lsl #4
    2ea6:	e9c6 4502 	strd	r4, r5, [r6, #8]
	cc_data[chan].callback = handler;
    2eaa:	9908      	ldr	r1, [sp, #32]
    2eac:	5099      	str	r1, [r3, r2]
	cc_data[chan].user_context = user_data;
    2eae:	9b09      	ldr	r3, [sp, #36]	; 0x24
    2eb0:	6073      	str	r3, [r6, #4]
	return ret;
    2eb2:	2000      	movs	r0, #0
}
    2eb4:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			return -EINVAL;
    2eb8:	f06f 0015 	mvn.w	r0, #21
    2ebc:	e7fa      	b.n	2eb4 <compare_set_nolocks+0x90>
    2ebe:	bf00      	nop
    2ec0:	200001d0 	.word	0x200001d0
    2ec4:	200004fc 	.word	0x200004fc

00002ec8 <process_channel>:

static void process_channel(int32_t chan)
{
    2ec8:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    2ecc:	b082      	sub	sp, #8
    2ece:	4604      	mov	r4, r0
	if (channel_processing_check_and_clear(chan)) {
    2ed0:	f7ff fee2 	bl	2c98 <channel_processing_check_and_clear>
    2ed4:	b910      	cbnz	r0, 2edc <process_channel+0x14>

		if (handler) {
			handler(chan, expire_time, user_context);
		}
	}
}
    2ed6:	b002      	add	sp, #8
    2ed8:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		curr_time = z_nrf_rtc_timer_read();
    2edc:	f7ff ff82 	bl	2de4 <z_nrf_rtc_timer_read>
    2ee0:	4606      	mov	r6, r0
    2ee2:	460f      	mov	r7, r1
		mcu_critical_state = full_int_lock();
    2ee4:	f003 fe80 	bl	6be8 <full_int_lock>
    2ee8:	4682      	mov	sl, r0
		expire_time = cc_data[chan].target_time;
    2eea:	4b13      	ldr	r3, [pc, #76]	; (2f38 <process_channel+0x70>)
    2eec:	eb03 1304 	add.w	r3, r3, r4, lsl #4
    2ef0:	e9d3 8902 	ldrd	r8, r9, [r3, #8]
		if (curr_time >= expire_time) {
    2ef4:	454f      	cmp	r7, r9
    2ef6:	bf08      	it	eq
    2ef8:	4546      	cmpeq	r6, r8
    2efa:	d20b      	bcs.n	2f14 <process_channel+0x4c>
		z_nrf_rtc_timer_compare_handler_t handler = NULL;
    2efc:	2600      	movs	r6, #0
		full_int_unlock(mcu_critical_state);
    2efe:	4650      	mov	r0, sl
    2f00:	f003 fe7b 	bl	6bfa <full_int_unlock>
		if (handler) {
    2f04:	2e00      	cmp	r6, #0
    2f06:	d0e6      	beq.n	2ed6 <process_channel+0xe>
			handler(chan, expire_time, user_context);
    2f08:	9500      	str	r5, [sp, #0]
    2f0a:	4642      	mov	r2, r8
    2f0c:	464b      	mov	r3, r9
    2f0e:	4620      	mov	r0, r4
    2f10:	47b0      	blx	r6
}
    2f12:	e7e0      	b.n	2ed6 <process_channel+0xe>
			handler = cc_data[chan].callback;
    2f14:	4a08      	ldr	r2, [pc, #32]	; (2f38 <process_channel+0x70>)
    2f16:	0123      	lsls	r3, r4, #4
    2f18:	eb02 1104 	add.w	r1, r2, r4, lsl #4
    2f1c:	58d6      	ldr	r6, [r2, r3]
			user_context = cc_data[chan].user_context;
    2f1e:	684d      	ldr	r5, [r1, #4]
			cc_data[chan].callback = NULL;
    2f20:	2000      	movs	r0, #0
    2f22:	50d0      	str	r0, [r2, r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    2f24:	f04f 32ff 	mov.w	r2, #4294967295
    2f28:	f04f 33ff 	mov.w	r3, #4294967295
    2f2c:	e9c1 2302 	strd	r2, r3, [r1, #8]
			event_disable(chan);
    2f30:	4620      	mov	r0, r4
    2f32:	f7ff fe79 	bl	2c28 <event_disable>
    2f36:	e7e2      	b.n	2efe <process_channel+0x36>
    2f38:	200001d0 	.word	0x200001d0

00002f3c <rtc_nrf_isr>:
 * probably better abstract that at some point (e.g. query and reset
 * it by pointer at runtime, maybe?) so we don't have this leaky
 * symbol.
 */
void rtc_nrf_isr(const void *arg)
{
    2f3c:	b510      	push	{r4, lr}
    return p_reg->INTENSET & mask;
    2f3e:	4b0d      	ldr	r3, [pc, #52]	; (2f74 <rtc_nrf_isr+0x38>)
    2f40:	f8d3 3304 	ldr.w	r3, [r3, #772]	; 0x304
	ARG_UNUSED(arg);

	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    2f44:	f013 0f02 	tst.w	r3, #2
    2f48:	d00a      	beq.n	2f60 <rtc_nrf_isr+0x24>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2f4a:	4b0b      	ldr	r3, [pc, #44]	; (2f78 <rtc_nrf_isr+0x3c>)
    2f4c:	681b      	ldr	r3, [r3, #0]
    2f4e:	b13b      	cbz	r3, 2f60 <rtc_nrf_isr+0x24>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2f50:	4b09      	ldr	r3, [pc, #36]	; (2f78 <rtc_nrf_isr+0x3c>)
    2f52:	2200      	movs	r2, #0
    2f54:	601a      	str	r2, [r3, #0]
    2f56:	681b      	ldr	r3, [r3, #0]
	    nrf_rtc_event_check(RTC, NRF_RTC_EVENT_OVERFLOW)) {
		nrf_rtc_event_clear(RTC, NRF_RTC_EVENT_OVERFLOW);
		overflow_cnt++;
    2f58:	4a08      	ldr	r2, [pc, #32]	; (2f7c <rtc_nrf_isr+0x40>)
    2f5a:	6813      	ldr	r3, [r2, #0]
    2f5c:	3301      	adds	r3, #1
    2f5e:	6013      	str	r3, [r2, #0]
{
    2f60:	2400      	movs	r4, #0
	}

	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    2f62:	2c00      	cmp	r4, #0
    2f64:	dd00      	ble.n	2f68 <rtc_nrf_isr+0x2c>
		process_channel(chan);
	}
}
    2f66:	bd10      	pop	{r4, pc}
		process_channel(chan);
    2f68:	4620      	mov	r0, r4
    2f6a:	f7ff ffad 	bl	2ec8 <process_channel>
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    2f6e:	3401      	adds	r4, #1
    2f70:	e7f7      	b.n	2f62 <rtc_nrf_isr+0x26>
    2f72:	bf00      	nop
    2f74:	40011000 	.word	0x40011000
    2f78:	40011104 	.word	0x40011104
    2f7c:	20000504 	.word	0x20000504

00002f80 <sys_clock_driver_init>:

	atomic_or(&alloc_mask, BIT(chan));
}

int sys_clock_driver_init(const struct device *dev)
{
    2f80:	b530      	push	{r4, r5, lr}
    2f82:	b083      	sub	sp, #12
    p_reg->PRESCALER = val;
    2f84:	2300      	movs	r3, #0
    2f86:	4a1f      	ldr	r2, [pc, #124]	; (3004 <sys_clock_driver_init+0x84>)
    2f88:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			CLOCK_CONTROL_NRF_LF_START_AVAILABLE :
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    2f8c:	2b00      	cmp	r3, #0
    2f8e:	dd27      	ble.n	2fe0 <sys_clock_driver_init+0x60>
    p_reg->INTENSET = mask;
    2f90:	4c1c      	ldr	r4, [pc, #112]	; (3004 <sys_clock_driver_init+0x84>)
    2f92:	2502      	movs	r5, #2
    2f94:	f8c4 5304 	str.w	r5, [r4, #772]	; 0x304
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2f98:	4b1b      	ldr	r3, [pc, #108]	; (3008 <sys_clock_driver_init+0x88>)
    2f9a:	f44f 3200 	mov.w	r2, #131072	; 0x20000
    2f9e:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    2fa2:	2200      	movs	r2, #0
    2fa4:	2101      	movs	r1, #1
    2fa6:	2011      	movs	r0, #17
    2fa8:	f7fe f944 	bl	1234 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    2fac:	2011      	movs	r0, #17
    2fae:	f7fe f90f 	bl	11d0 <arch_irq_enable>
    2fb2:	f8c4 5304 	str.w	r5, [r4, #772]	; 0x304
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    2fb6:	2301      	movs	r3, #1
    2fb8:	4a14      	ldr	r2, [pc, #80]	; (300c <sys_clock_driver_init+0x8c>)
    2fba:	6013      	str	r3, [r2, #0]
    2fbc:	6023      	str	r3, [r4, #0]

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    2fbe:	4a14      	ldr	r2, [pc, #80]	; (3010 <sys_clock_driver_init+0x90>)
    2fc0:	6013      	str	r3, [r2, #0]

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
				(COUNTER_HALF_SPAN - 1) :
				(counter() + CYC_PER_TICK);

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    2fc2:	2400      	movs	r4, #0
    2fc4:	9401      	str	r4, [sp, #4]
    2fc6:	4b13      	ldr	r3, [pc, #76]	; (3014 <sys_clock_driver_init+0x94>)
    2fc8:	9300      	str	r3, [sp, #0]
    2fca:	4a13      	ldr	r2, [pc, #76]	; (3018 <sys_clock_driver_init+0x98>)
    2fcc:	2300      	movs	r3, #0
    2fce:	4620      	mov	r0, r4
    2fd0:	f003 fe53 	bl	6c7a <compare_set>

	z_nrf_clock_control_lf_on(mode);
    2fd4:	4628      	mov	r0, r5
    2fd6:	f7fe fe19 	bl	1c0c <z_nrf_clock_control_lf_on>

	return 0;
}
    2fda:	4620      	mov	r0, r4
    2fdc:	b003      	add	sp, #12
    2fde:	bd30      	pop	{r4, r5, pc}
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    2fe0:	4a0e      	ldr	r2, [pc, #56]	; (301c <sys_clock_driver_init+0x9c>)
    2fe2:	eb02 1203 	add.w	r2, r2, r3, lsl #4
    2fe6:	f04f 30ff 	mov.w	r0, #4294967295
    2fea:	f04f 31ff 	mov.w	r1, #4294967295
    2fee:	e9c2 0102 	strd	r0, r1, [r2, #8]
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2ff2:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    2ff6:	409a      	lsls	r2, r3
    p_reg->INTENSET = mask;
    2ff8:	4902      	ldr	r1, [pc, #8]	; (3004 <sys_clock_driver_init+0x84>)
    2ffa:	f8c1 2304 	str.w	r2, [r1, #772]	; 0x304
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    2ffe:	3301      	adds	r3, #1
    3000:	e7c4      	b.n	2f8c <sys_clock_driver_init+0xc>
    3002:	bf00      	nop
    3004:	40011000 	.word	0x40011000
    3008:	e000e100 	.word	0xe000e100
    300c:	40011008 	.word	0x40011008
    3010:	20000500 	.word	0x20000500
    3014:	00002d71 	.word	0x00002d71
    3018:	007fffff 	.word	0x007fffff
    301c:	200001d0 	.word	0x200001d0

00003020 <sys_clock_set_timeout>:

void sys_clock_set_timeout(int32_t ticks, bool idle)
{
    3020:	b510      	push	{r4, lr}
    3022:	b082      	sub	sp, #8

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return;
	}

	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    3024:	f1b0 3fff 	cmp.w	r0, #4294967295
    3028:	d007      	beq.n	303a <sys_clock_set_timeout+0x1a>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    302a:	1e44      	subs	r4, r0, #1
    302c:	2c00      	cmp	r4, #0
    302e:	dd07      	ble.n	3040 <sys_clock_set_timeout+0x20>
    3030:	4b11      	ldr	r3, [pc, #68]	; (3078 <sys_clock_set_timeout+0x58>)
    3032:	429c      	cmp	r4, r3
    3034:	dd05      	ble.n	3042 <sys_clock_set_timeout+0x22>
    3036:	4c11      	ldr	r4, [pc, #68]	; (307c <sys_clock_set_timeout+0x5c>)
    3038:	e003      	b.n	3042 <sys_clock_set_timeout+0x22>
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    303a:	f500 0000 	add.w	r0, r0, #8388608	; 0x800000
    303e:	e7f4      	b.n	302a <sys_clock_set_timeout+0xa>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    3040:	2400      	movs	r4, #0

	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    3042:	f7ff fecf 	bl	2de4 <z_nrf_rtc_timer_read>
    3046:	4b0e      	ldr	r3, [pc, #56]	; (3080 <sys_clock_set_timeout+0x60>)
    3048:	e9d3 2300 	ldrd	r2, r3, [r3]
    304c:	1a80      	subs	r0, r0, r2
	/* If we haven't announced for more than half the 24-bit wrap
	 * duration, then force an announce to avoid loss of a wrap
	 * event.  This can happen if new timeouts keep being set
	 * before the existing one triggers the interrupt.
	 */
	if (unannounced >= COUNTER_HALF_SPAN) {
    304e:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    3052:	d300      	bcc.n	3056 <sys_clock_set_timeout+0x36>
		ticks = 0;
    3054:	2400      	movs	r4, #0
	}

	/* Get the cycles from last_count to the tick boundary after
	 * the requested ticks have passed starting now.
	 */
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    3056:	4404      	add	r4, r0
    3058:	3401      	adds	r4, #1
	cyc = (cyc / CYC_PER_TICK) * CYC_PER_TICK;

	/* Due to elapsed time the calculation above might produce a
	 * duration that laps the counter.  Don't let it.
	 */
	if (cyc > MAX_CYCLES) {
    305a:	f5b4 0f00 	cmp.w	r4, #8388608	; 0x800000
    305e:	d300      	bcc.n	3062 <sys_clock_set_timeout+0x42>
		cyc = MAX_CYCLES;
    3060:	4c06      	ldr	r4, [pc, #24]	; (307c <sys_clock_set_timeout+0x5c>)
	}

	uint64_t target_time = cyc + last_count;

	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    3062:	2000      	movs	r0, #0
    3064:	9001      	str	r0, [sp, #4]
    3066:	4907      	ldr	r1, [pc, #28]	; (3084 <sys_clock_set_timeout+0x64>)
    3068:	9100      	str	r1, [sp, #0]
    306a:	1912      	adds	r2, r2, r4
    306c:	f143 0300 	adc.w	r3, r3, #0
    3070:	f003 fe03 	bl	6c7a <compare_set>
}
    3074:	b002      	add	sp, #8
    3076:	bd10      	pop	{r4, pc}
    3078:	007ffffe 	.word	0x007ffffe
    307c:	007fffff 	.word	0x007fffff
    3080:	200001e0 	.word	0x200001e0
    3084:	00002d71 	.word	0x00002d71

00003088 <sys_clock_elapsed>:

uint32_t sys_clock_elapsed(void)
{
    3088:	b508      	push	{r3, lr}
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return 0;
	}

	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    308a:	f7ff feab 	bl	2de4 <z_nrf_rtc_timer_read>
    308e:	4b02      	ldr	r3, [pc, #8]	; (3098 <sys_clock_elapsed+0x10>)
    3090:	681b      	ldr	r3, [r3, #0]
}
    3092:	1ac0      	subs	r0, r0, r3
    3094:	bd08      	pop	{r3, pc}
    3096:	bf00      	nop
    3098:	200001e0 	.word	0x200001e0

0000309c <nrf52_errata_36>:
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    309c:	4b03      	ldr	r3, [pc, #12]	; (30ac <nrf52_errata_36+0x10>)
    309e:	681b      	ldr	r3, [r3, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    30a0:	2b0d      	cmp	r3, #13
    30a2:	d001      	beq.n	30a8 <nrf52_errata_36+0xc>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    30a4:	2000      	movs	r0, #0
    30a6:	4770      	bx	lr
                        return true;
    30a8:	2001      	movs	r0, #1
    #endif
}
    30aa:	4770      	bx	lr
    30ac:	10000130 	.word	0x10000130

000030b0 <nrf52_errata_66>:
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    30b0:	4b03      	ldr	r3, [pc, #12]	; (30c0 <nrf52_errata_66+0x10>)
    30b2:	681b      	ldr	r3, [r3, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    30b4:	2b0d      	cmp	r3, #13
    30b6:	d001      	beq.n	30bc <nrf52_errata_66+0xc>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    30b8:	2000      	movs	r0, #0
    30ba:	4770      	bx	lr
                        return true;
    30bc:	2001      	movs	r0, #1
    #endif
}
    30be:	4770      	bx	lr
    30c0:	10000130 	.word	0x10000130

000030c4 <nrf52_errata_136>:
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    30c4:	4b03      	ldr	r3, [pc, #12]	; (30d4 <nrf52_errata_136+0x10>)
    30c6:	681b      	ldr	r3, [r3, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    30c8:	2b0d      	cmp	r3, #13
    30ca:	d001      	beq.n	30d0 <nrf52_errata_136+0xc>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    30cc:	2000      	movs	r0, #0
    30ce:	4770      	bx	lr
                        return true;
    30d0:	2001      	movs	r0, #1
    #endif
}
    30d2:	4770      	bx	lr
    30d4:	10000130 	.word	0x10000130

000030d8 <nrf52_errata_249>:
        #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    30d8:	4b06      	ldr	r3, [pc, #24]	; (30f4 <nrf52_errata_249+0x1c>)
    30da:	681b      	ldr	r3, [r3, #0]
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    30dc:	4a06      	ldr	r2, [pc, #24]	; (30f8 <nrf52_errata_249+0x20>)
    30de:	6812      	ldr	r2, [r2, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    30e0:	2b0d      	cmp	r3, #13
    30e2:	d001      	beq.n	30e8 <nrf52_errata_249+0x10>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    30e4:	2000      	movs	r0, #0
    30e6:	4770      	bx	lr
                switch(var2)
    30e8:	2a01      	cmp	r2, #1
    30ea:	d801      	bhi.n	30f0 <nrf52_errata_249+0x18>
    30ec:	2000      	movs	r0, #0
    30ee:	4770      	bx	lr
                        return true;
    30f0:	2001      	movs	r0, #1
    #endif
}
    30f2:	4770      	bx	lr
    30f4:	10000130 	.word	0x10000130
    30f8:	10000134 	.word	0x10000134

000030fc <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    30fc:	4b02      	ldr	r3, [pc, #8]	; (3108 <nvmc_wait+0xc>)
    30fe:	f8d3 3400 	ldr.w	r3, [r3, #1024]	; 0x400
    3102:	2b00      	cmp	r3, #0
    3104:	d0fa      	beq.n	30fc <nvmc_wait>
}
    3106:	4770      	bx	lr
    3108:	4001e000 	.word	0x4001e000

0000310c <nvmc_config>:

/*  Configure the NVMC to "mode".
    Mode must be an enumerator of field NVMC_CONFIG_WEN */
void nvmc_config(uint32_t mode)
{
    310c:	b508      	push	{r3, lr}
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    310e:	4b03      	ldr	r3, [pc, #12]	; (311c <nvmc_config+0x10>)
    3110:	f8c3 0504 	str.w	r0, [r3, #1284]	; 0x504
    nvmc_wait();
    3114:	f7ff fff2 	bl	30fc <nvmc_wait>
}
    3118:	bd08      	pop	{r3, pc}
    311a:	bf00      	nop
    311c:	4001e000 	.word	0x4001e000

00003120 <SystemCoreClockUpdate>:

void SystemCoreClockUpdate(void)
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    3120:	4b01      	ldr	r3, [pc, #4]	; (3128 <SystemCoreClockUpdate+0x8>)
    3122:	4a02      	ldr	r2, [pc, #8]	; (312c <SystemCoreClockUpdate+0xc>)
    3124:	601a      	str	r2, [r3, #0]
}
    3126:	4770      	bx	lr
    3128:	2000018c 	.word	0x2000018c
    312c:	03d09000 	.word	0x03d09000

00003130 <SystemInit>:

void SystemInit(void)
{
    3130:	b538      	push	{r3, r4, r5, lr}
    #endif

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
    3132:	f7ff ffb3 	bl	309c <nrf52_errata_36>
    3136:	b140      	cbz	r0, 314a <SystemInit+0x1a>
            NRF_CLOCK->EVENTS_DONE = 0;
    3138:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    313c:	2200      	movs	r2, #0
    313e:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    3142:	f8c3 2110 	str.w	r2, [r3, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    3146:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    #endif

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
    314a:	f7ff ffb1 	bl	30b0 <nrf52_errata_66>
    314e:	2800      	cmp	r0, #0
    3150:	d046      	beq.n	31e0 <SystemInit+0xb0>
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    3152:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
    3156:	f8d2 1404 	ldr.w	r1, [r2, #1028]	; 0x404
    315a:	4b45      	ldr	r3, [pc, #276]	; (3270 <SystemInit+0x140>)
    315c:	f8c3 1520 	str.w	r1, [r3, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    3160:	f8d2 1408 	ldr.w	r1, [r2, #1032]	; 0x408
    3164:	f8c3 1524 	str.w	r1, [r3, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    3168:	f8d2 140c 	ldr.w	r1, [r2, #1036]	; 0x40c
    316c:	f8c3 1528 	str.w	r1, [r3, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    3170:	f8d2 1410 	ldr.w	r1, [r2, #1040]	; 0x410
    3174:	f8c3 152c 	str.w	r1, [r3, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    3178:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
    317c:	f8c3 1530 	str.w	r1, [r3, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    3180:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    3184:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    3188:	f8d2 141c 	ldr.w	r1, [r2, #1052]	; 0x41c
    318c:	f8c3 1540 	str.w	r1, [r3, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    3190:	f8d2 1420 	ldr.w	r1, [r2, #1056]	; 0x420
    3194:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    3198:	f8d2 1424 	ldr.w	r1, [r2, #1060]	; 0x424
    319c:	f8c3 1548 	str.w	r1, [r3, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    31a0:	f8d2 1428 	ldr.w	r1, [r2, #1064]	; 0x428
    31a4:	f8c3 154c 	str.w	r1, [r3, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    31a8:	f8d2 142c 	ldr.w	r1, [r2, #1068]	; 0x42c
    31ac:	f8c3 1550 	str.w	r1, [r3, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    31b0:	f8d2 1430 	ldr.w	r1, [r2, #1072]	; 0x430
    31b4:	f8c3 1554 	str.w	r1, [r3, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    31b8:	f8d2 1434 	ldr.w	r1, [r2, #1076]	; 0x434
    31bc:	f8c3 1560 	str.w	r1, [r3, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    31c0:	f8d2 1438 	ldr.w	r1, [r2, #1080]	; 0x438
    31c4:	f8c3 1564 	str.w	r1, [r3, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    31c8:	f8d2 143c 	ldr.w	r1, [r2, #1084]	; 0x43c
    31cc:	f8c3 1568 	str.w	r1, [r3, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    31d0:	f8d2 1440 	ldr.w	r1, [r2, #1088]	; 0x440
    31d4:	f8c3 156c 	str.w	r1, [r3, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    31d8:	f8d2 2444 	ldr.w	r2, [r2, #1092]	; 0x444
    31dc:	f8c3 2570 	str.w	r2, [r3, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
    31e0:	f7ff ff70 	bl	30c4 <nrf52_errata_136>
    31e4:	b160      	cbz	r0, 3200 <SystemInit+0xd0>
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    31e6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    31ea:	f8d3 3400 	ldr.w	r3, [r3, #1024]	; 0x400
    31ee:	f013 0f01 	tst.w	r3, #1
    31f2:	d005      	beq.n	3200 <SystemInit+0xd0>
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    31f4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    31f8:	f06f 0201 	mvn.w	r2, #1
    31fc:	f8c3 2400 	str.w	r2, [r3, #1024]	; 0x400
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_errata_249())
    3200:	f7ff ff6a 	bl	30d8 <nrf52_errata_249>
    3204:	b138      	cbz	r0, 3216 <SystemInit+0xe6>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    3206:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    320a:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    320e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3212:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    3216:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    321a:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
    321e:	2b00      	cmp	r3, #0
    3220:	db08      	blt.n	3234 <SystemInit+0x104>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    3222:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    3226:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    322a:	2b00      	cmp	r3, #0
    322c:	db02      	blt.n	3234 <SystemInit+0x104>
            nvmc_config(NVMC_CONFIG_WEN_Ren);
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
    322e:	f7ff ff77 	bl	3120 <SystemCoreClockUpdate>
}
    3232:	bd38      	pop	{r3, r4, r5, pc}
            nvmc_config(NVMC_CONFIG_WEN_Wen);
    3234:	2001      	movs	r0, #1
    3236:	f7ff ff69 	bl	310c <nvmc_config>
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    323a:	f04f 2410 	mov.w	r4, #268439552	; 0x10001000
    323e:	2512      	movs	r5, #18
    3240:	f8c4 5200 	str.w	r5, [r4, #512]	; 0x200
            nvmc_wait();
    3244:	f7ff ff5a 	bl	30fc <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    3248:	f8c4 5204 	str.w	r5, [r4, #516]	; 0x204
            nvmc_wait();
    324c:	f7ff ff56 	bl	30fc <nvmc_wait>
            nvmc_config(NVMC_CONFIG_WEN_Ren);
    3250:	2000      	movs	r0, #0
    3252:	f7ff ff5b 	bl	310c <nvmc_config>
  __ASM volatile ("dsb 0xF":::"memory");
    3256:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    325a:	4906      	ldr	r1, [pc, #24]	; (3274 <SystemInit+0x144>)
    325c:	68ca      	ldr	r2, [r1, #12]
    325e:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    3262:	4b05      	ldr	r3, [pc, #20]	; (3278 <SystemInit+0x148>)
    3264:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    3266:	60cb      	str	r3, [r1, #12]
    3268:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    326c:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    326e:	e7fd      	b.n	326c <SystemInit+0x13c>
    3270:	4000c000 	.word	0x4000c000
    3274:	e000ed00 	.word	0xe000ed00
    3278:	05fa0004 	.word	0x05fa0004

0000327c <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    327c:	4b05      	ldr	r3, [pc, #20]	; (3294 <nrfx_clock_init+0x18>)
    327e:	791b      	ldrb	r3, [r3, #4]
    3280:	b92b      	cbnz	r3, 328e <nrfx_clock_init+0x12>
    else
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
    3282:	4b04      	ldr	r3, [pc, #16]	; (3294 <nrfx_clock_init+0x18>)
    3284:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    3286:	2201      	movs	r2, #1
    3288:	711a      	strb	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    328a:	4803      	ldr	r0, [pc, #12]	; (3298 <nrfx_clock_init+0x1c>)
    328c:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    328e:	4803      	ldr	r0, [pc, #12]	; (329c <nrfx_clock_init+0x20>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    3290:	4770      	bx	lr
    3292:	bf00      	nop
    3294:	20000508 	.word	0x20000508
    3298:	0bad0000 	.word	0x0bad0000
    329c:	0bad000c 	.word	0x0bad000c

000032a0 <nrfx_clock_start>:
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    32a0:	b110      	cbz	r0, 32a8 <nrfx_clock_start+0x8>
    32a2:	2801      	cmp	r0, #1
    32a4:	d025      	beq.n	32f2 <nrfx_clock_start+0x52>
    32a6:	4770      	bx	lr
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    32a8:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    32ac:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    32b0:	f003 0303 	and.w	r3, r3, #3
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    32b4:	f8d2 2418 	ldr.w	r2, [r2, #1048]	; 0x418
    32b8:	f412 3f80 	tst.w	r2, #65536	; 0x10000
    32bc:	d111      	bne.n	32e2 <nrfx_clock_start+0x42>
    p_reg->LFCLKSRC = (uint32_t)(source);
    32be:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    32c2:	2200      	movs	r2, #0
    32c4:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    32c8:	4b0f      	ldr	r3, [pc, #60]	; (3308 <nrfx_clock_start+0x68>)
    32ca:	2200      	movs	r2, #0
    32cc:	601a      	str	r2, [r3, #0]
    32ce:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    32d0:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    32d4:	2202      	movs	r2, #2
    32d6:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    32da:	3308      	adds	r3, #8
    32dc:	2201      	movs	r2, #1
    32de:	601a      	str	r2, [r3, #0]
}
    32e0:	4770      	bx	lr
    {
        case NRF_CLOCK_DOMAIN_LFCLK:
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
            {
                nrf_clock_lfclk_t lfclksrc;
                if (nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc) &&
    32e2:	2b01      	cmp	r3, #1
    32e4:	d1eb      	bne.n	32be <nrfx_clock_start+0x1e>
    p_reg->LFCLKSRC = (uint32_t)(source);
    32e6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    32ea:	2201      	movs	r2, #1
    32ec:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    32f0:	e7ea      	b.n	32c8 <nrfx_clock_start+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    32f2:	4b06      	ldr	r3, [pc, #24]	; (330c <nrfx_clock_start+0x6c>)
    32f4:	2200      	movs	r2, #0
    32f6:	601a      	str	r2, [r3, #0]
    32f8:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    32fa:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    32fe:	2201      	movs	r2, #1
    3300:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3304:	601a      	str	r2, [r3, #0]
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    3306:	4770      	bx	lr
    3308:	40000104 	.word	0x40000104
    330c:	40000100 	.word	0x40000100

00003310 <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
    3310:	b530      	push	{r4, r5, lr}
    3312:	b083      	sub	sp, #12
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    3314:	4604      	mov	r4, r0
    3316:	b118      	cbz	r0, 3320 <nrfx_clock_stop+0x10>
    3318:	2801      	cmp	r0, #1
    331a:	d013      	beq.n	3344 <nrfx_clock_stop+0x34>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    331c:	b003      	add	sp, #12
    331e:	bd30      	pop	{r4, r5, pc}
    p_reg->INTENCLR = mask;
    3320:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3324:	2202      	movs	r2, #2
    3326:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    332a:	f503 7382 	add.w	r3, r3, #260	; 0x104
    332e:	2200      	movs	r2, #0
    3330:	601a      	str	r2, [r3, #0]
    3332:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3334:	4b37      	ldr	r3, [pc, #220]	; (3414 <nrfx_clock_stop+0x104>)
    3336:	2201      	movs	r2, #1
    3338:	601a      	str	r2, [r3, #0]
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    333a:	2c01      	cmp	r4, #1
    333c:	d00f      	beq.n	335e <nrfx_clock_stop+0x4e>
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    333e:	f242 7510 	movw	r5, #10000	; 0x2710
    3342:	e053      	b.n	33ec <nrfx_clock_stop+0xdc>
    p_reg->INTENCLR = mask;
    3344:	2301      	movs	r3, #1
    3346:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    334a:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    334e:	f502 7280 	add.w	r2, r2, #256	; 0x100
    3352:	2100      	movs	r1, #0
    3354:	6011      	str	r1, [r2, #0]
    3356:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3358:	4a2f      	ldr	r2, [pc, #188]	; (3418 <nrfx_clock_stop+0x108>)
    335a:	6013      	str	r3, [r2, #0]
}
    335c:	e7ed      	b.n	333a <nrfx_clock_stop+0x2a>
        nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    335e:	2301      	movs	r3, #1
    3360:	f88d 3007 	strb.w	r3, [sp, #7]
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
    3364:	f242 7510 	movw	r5, #10000	; 0x2710
    3368:	e018      	b.n	339c <nrfx_clock_stop+0x8c>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    336a:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    336e:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    3372:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    3376:	f8cd 3007 	str.w	r3, [sp, #7]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    337a:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
    337e:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    3382:	d120      	bne.n	33c6 <nrfx_clock_stop+0xb6>
    return false;
    3384:	2300      	movs	r3, #0
    3386:	2b00      	cmp	r3, #0
    3388:	d0c8      	beq.n	331c <nrfx_clock_stop+0xc>
    338a:	f89d 3007 	ldrb.w	r3, [sp, #7]
    338e:	2b01      	cmp	r3, #1
    3390:	d1c4      	bne.n	331c <nrfx_clock_stop+0xc>
    3392:	2001      	movs	r0, #1
    3394:	f003 fc8d 	bl	6cb2 <nrfx_busy_wait>
    3398:	3d01      	subs	r5, #1
    339a:	d0bf      	beq.n	331c <nrfx_clock_stop+0xc>
    switch (domain)
    339c:	2c00      	cmp	r4, #0
    339e:	d0e4      	beq.n	336a <nrfx_clock_stop+0x5a>
    33a0:	2c01      	cmp	r4, #1
    33a2:	d001      	beq.n	33a8 <nrfx_clock_stop+0x98>
    33a4:	2300      	movs	r3, #0
    33a6:	e7ee      	b.n	3386 <nrfx_clock_stop+0x76>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    33a8:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    33ac:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
    33b0:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    33b4:	f88d 3007 	strb.w	r3, [sp, #7]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    33b8:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
    33bc:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    33c0:	d103      	bne.n	33ca <nrfx_clock_stop+0xba>
    return false;
    33c2:	2300      	movs	r3, #0
    33c4:	e7df      	b.n	3386 <nrfx_clock_stop+0x76>
                return true;
    33c6:	2301      	movs	r3, #1
    33c8:	e7dd      	b.n	3386 <nrfx_clock_stop+0x76>
                return true;
    33ca:	2301      	movs	r3, #1
    33cc:	e7db      	b.n	3386 <nrfx_clock_stop+0x76>
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    33ce:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    33d2:	f8d3 3418 	ldr.w	r3, [r3, #1048]	; 0x418
    33d6:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    33da:	d116      	bne.n	340a <nrfx_clock_stop+0xfa>
    return false;
    33dc:	2300      	movs	r3, #0
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    33de:	2b00      	cmp	r3, #0
    33e0:	d09c      	beq.n	331c <nrfx_clock_stop+0xc>
    33e2:	2001      	movs	r0, #1
    33e4:	f003 fc65 	bl	6cb2 <nrfx_busy_wait>
    33e8:	3d01      	subs	r5, #1
    33ea:	d097      	beq.n	331c <nrfx_clock_stop+0xc>
    switch (domain)
    33ec:	2c00      	cmp	r4, #0
    33ee:	d0ee      	beq.n	33ce <nrfx_clock_stop+0xbe>
    33f0:	2c01      	cmp	r4, #1
    33f2:	d001      	beq.n	33f8 <nrfx_clock_stop+0xe8>
    33f4:	2300      	movs	r3, #0
    33f6:	e7f2      	b.n	33de <nrfx_clock_stop+0xce>
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    33f8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    33fc:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
    3400:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    3404:	d103      	bne.n	340e <nrfx_clock_stop+0xfe>
    return false;
    3406:	2300      	movs	r3, #0
    3408:	e7e9      	b.n	33de <nrfx_clock_stop+0xce>
                return true;
    340a:	2301      	movs	r3, #1
    340c:	e7e7      	b.n	33de <nrfx_clock_stop+0xce>
                return true;
    340e:	2301      	movs	r3, #1
    3410:	e7e5      	b.n	33de <nrfx_clock_stop+0xce>
    3412:	bf00      	nop
    3414:	4000000c 	.word	0x4000000c
    3418:	40000004 	.word	0x40000004

0000341c <nrfx_power_clock_irq_handler>:
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    341c:	b508      	push	{r3, lr}
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    341e:	4b18      	ldr	r3, [pc, #96]	; (3480 <nrfx_power_clock_irq_handler+0x64>)
    3420:	681b      	ldr	r3, [r3, #0]
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    3422:	b15b      	cbz	r3, 343c <nrfx_power_clock_irq_handler+0x20>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3424:	4b16      	ldr	r3, [pc, #88]	; (3480 <nrfx_power_clock_irq_handler+0x64>)
    3426:	2000      	movs	r0, #0
    3428:	6018      	str	r0, [r3, #0]
    342a:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    342c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3430:	2201      	movs	r2, #1
    3432:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    3436:	4b13      	ldr	r3, [pc, #76]	; (3484 <nrfx_power_clock_irq_handler+0x68>)
    3438:	681b      	ldr	r3, [r3, #0]
    343a:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    343c:	4b12      	ldr	r3, [pc, #72]	; (3488 <nrfx_power_clock_irq_handler+0x6c>)
    343e:	681b      	ldr	r3, [r3, #0]
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    3440:	b19b      	cbz	r3, 346a <nrfx_power_clock_irq_handler+0x4e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3442:	4b11      	ldr	r3, [pc, #68]	; (3488 <nrfx_power_clock_irq_handler+0x6c>)
    3444:	2200      	movs	r2, #0
    3446:	601a      	str	r2, [r3, #0]
    3448:	681b      	ldr	r3, [r3, #0]
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    344a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    344e:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    3452:	f8d3 3418 	ldr.w	r3, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    3456:	f012 0f03 	tst.w	r2, #3
    345a:	d107      	bne.n	346c <nrfx_power_clock_irq_handler+0x50>
    p_reg->LFCLKSRC = (uint32_t)(source);
    345c:	2301      	movs	r3, #1
    345e:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    3462:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3466:	3208      	adds	r2, #8
    3468:	6013      	str	r3, [r2, #0]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    346a:	bd08      	pop	{r3, pc}
    p_reg->INTENCLR = mask;
    346c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3470:	2202      	movs	r2, #2
    3472:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    3476:	4b03      	ldr	r3, [pc, #12]	; (3484 <nrfx_power_clock_irq_handler+0x68>)
    3478:	681b      	ldr	r3, [r3, #0]
    347a:	2001      	movs	r0, #1
    347c:	4798      	blx	r3
}
    347e:	e7f4      	b.n	346a <nrfx_power_clock_irq_handler+0x4e>
    3480:	40000100 	.word	0x40000100
    3484:	20000508 	.word	0x20000508
    3488:	40000104 	.word	0x40000104

0000348c <is_allocated_channel>:
    NRFX_LOG_INFO("Uninitialized.");
}

static bool is_allocated_channel(uint8_t index)
{
    return m_cb.allocated_channels_mask & (1UL << index);
    348c:	4b04      	ldr	r3, [pc, #16]	; (34a0 <is_allocated_channel+0x14>)
    348e:	6d9a      	ldr	r2, [r3, #88]	; 0x58
    3490:	2301      	movs	r3, #1
    3492:	4083      	lsls	r3, r0
    3494:	421a      	tst	r2, r3
}
    3496:	bf14      	ite	ne
    3498:	2001      	movne	r0, #1
    349a:	2000      	moveq	r0, #0
    349c:	4770      	bx	lr
    349e:	bf00      	nop
    34a0:	20000510 	.word	0x20000510

000034a4 <channel_allocated_set>:
    return NRFX_GPIOTE_APP_CHANNELS_MASK & (1UL << index);
}

static void channel_allocated_set(uint8_t index)
{
    m_cb.allocated_channels_mask |= (1UL << index);
    34a4:	2301      	movs	r3, #1
    34a6:	fa03 f000 	lsl.w	r0, r3, r0
    34aa:	4a02      	ldr	r2, [pc, #8]	; (34b4 <channel_allocated_set+0x10>)
    34ac:	6d93      	ldr	r3, [r2, #88]	; 0x58
    34ae:	4303      	orrs	r3, r0
    34b0:	6593      	str	r3, [r2, #88]	; 0x58
}
    34b2:	4770      	bx	lr
    34b4:	20000510 	.word	0x20000510

000034b8 <channel_allocated_clr>:

static void channel_allocated_clr(uint8_t index)
{
    m_cb.allocated_channels_mask &= ~(1UL << index);
    34b8:	2301      	movs	r3, #1
    34ba:	fa03 f000 	lsl.w	r0, r3, r0
    34be:	4a03      	ldr	r2, [pc, #12]	; (34cc <channel_allocated_clr+0x14>)
    34c0:	6d93      	ldr	r3, [r2, #88]	; 0x58
    34c2:	ea23 0300 	bic.w	r3, r3, r0
    34c6:	6593      	str	r3, [r2, #88]	; 0x58
}
    34c8:	4770      	bx	lr
    34ca:	bf00      	nop
    34cc:	20000510 	.word	0x20000510

000034d0 <nrfx_gpiote_channel_free>:

nrfx_err_t nrfx_gpiote_channel_free(uint8_t channel)
{
    34d0:	b538      	push	{r3, r4, r5, lr}
    34d2:	4604      	mov	r4, r0
    nrfx_err_t err_code = NRFX_SUCCESS;

    if (!is_app_channel(channel))
    34d4:	f003 fbfa 	bl	6ccc <is_app_channel>
    34d8:	b908      	cbnz	r0, 34de <nrfx_gpiote_channel_free+0xe>
    {
        err_code = NRFX_ERROR_INVALID_PARAM;
    34da:	4809      	ldr	r0, [pc, #36]	; (3500 <nrfx_gpiote_channel_free+0x30>)
        NRFX_CRITICAL_SECTION_EXIT();
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    34dc:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    34de:	f04f 0320 	mov.w	r3, #32
    34e2:	f3ef 8511 	mrs	r5, BASEPRI
    34e6:	f383 8812 	msr	BASEPRI_MAX, r3
    34ea:	f3bf 8f6f 	isb	sy
        channel_allocated_clr(channel);
    34ee:	4620      	mov	r0, r4
    34f0:	f7ff ffe2 	bl	34b8 <channel_allocated_clr>
	__asm__ volatile(
    34f4:	f385 8811 	msr	BASEPRI, r5
    34f8:	f3bf 8f6f 	isb	sy
    nrfx_err_t err_code = NRFX_SUCCESS;
    34fc:	4801      	ldr	r0, [pc, #4]	; (3504 <nrfx_gpiote_channel_free+0x34>)
}
    34fe:	e7ed      	b.n	34dc <nrfx_gpiote_channel_free+0xc>
    3500:	0bad0004 	.word	0x0bad0004
    3504:	0bad0000 	.word	0x0bad0000

00003508 <nrfx_gpiote_channel_alloc>:

nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel)
{
    3508:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    350c:	4680      	mov	r8, r0
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    uint32_t mask = NRFX_GPIOTE_APP_CHANNELS_MASK;

    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    350e:	2400      	movs	r4, #0
    uint32_t mask = NRFX_GPIOTE_APP_CHANNELS_MASK;
    3510:	25ff      	movs	r5, #255	; 0xff
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    3512:	4f17      	ldr	r7, [pc, #92]	; (3570 <nrfx_gpiote_channel_alloc+0x68>)
    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    3514:	e013      	b.n	353e <nrfx_gpiote_channel_alloc+0x36>
    {
        NRFX_CRITICAL_SECTION_ENTER();
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
        {
            channel_allocated_set(ch_idx);
    3516:	4620      	mov	r0, r4
    3518:	f7ff ffc4 	bl	34a4 <channel_allocated_set>
            *p_channel = ch_idx;
    351c:	f888 4000 	strb.w	r4, [r8]
            err_code = NRFX_SUCCESS;
    3520:	4f14      	ldr	r7, [pc, #80]	; (3574 <nrfx_gpiote_channel_alloc+0x6c>)
	__asm__ volatile(
    3522:	f386 8811 	msr	BASEPRI, r6
    3526:	f3bf 8f6f 	isb	sy
        }
        NRFX_CRITICAL_SECTION_EXIT();

        if (err_code == NRFX_SUCCESS)
    352a:	4b12      	ldr	r3, [pc, #72]	; (3574 <nrfx_gpiote_channel_alloc+0x6c>)
    352c:	429f      	cmp	r7, r3
    352e:	d01b      	beq.n	3568 <nrfx_gpiote_channel_alloc+0x60>
        {
            NRFX_LOG_INFO("Allocated channel: %d.", ch_idx);
            break;
        }

        mask &= ~(1UL << ch_idx);
    3530:	2301      	movs	r3, #1
    3532:	fa03 f309 	lsl.w	r3, r3, r9
    3536:	ea25 0503 	bic.w	r5, r5, r3
    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    353a:	3401      	adds	r4, #1
    353c:	b2e4      	uxtb	r4, r4
    353e:	b19d      	cbz	r5, 3568 <nrfx_gpiote_channel_alloc+0x60>
	__asm__ volatile(
    3540:	f04f 0320 	mov.w	r3, #32
    3544:	f3ef 8611 	mrs	r6, BASEPRI
    3548:	f383 8812 	msr	BASEPRI_MAX, r3
    354c:	f3bf 8f6f 	isb	sy
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
    3550:	46a1      	mov	r9, r4
    3552:	fa25 f304 	lsr.w	r3, r5, r4
    3556:	f013 0f01 	tst.w	r3, #1
    355a:	d0e2      	beq.n	3522 <nrfx_gpiote_channel_alloc+0x1a>
    355c:	4620      	mov	r0, r4
    355e:	f7ff ff95 	bl	348c <is_allocated_channel>
    3562:	2800      	cmp	r0, #0
    3564:	d1dd      	bne.n	3522 <nrfx_gpiote_channel_alloc+0x1a>
    3566:	e7d6      	b.n	3516 <nrfx_gpiote_channel_alloc+0xe>
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    3568:	4638      	mov	r0, r7
    356a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    356e:	bf00      	nop
    3570:	0bad0002 	.word	0x0bad0002
    3574:	0bad0000 	.word	0x0bad0000

00003578 <is_allocated_channel>:
NRFX_STATIC_INLINE uint32_t nrfx_ppi_task_addr_group_disable_get(nrf_ppi_channel_group_t group);

#ifndef NRFX_DECLARE_ONLY
NRFX_STATIC_INLINE uint32_t nrfx_ppi_channel_to_mask(nrf_ppi_channel_t channel)
{
    return (1uL << (uint32_t) channel);
    3578:	2301      	movs	r3, #1
    357a:	4083      	lsls	r3, r0
 * @retval true  The channel is allocated.
 * @retval false The channel is not allocated.
 */
static bool is_allocated_channel(nrf_ppi_channel_t channel)
{
    return ((m_channels_allocated & nrfx_ppi_channel_to_mask(channel)) != 0);
    357c:	4a03      	ldr	r2, [pc, #12]	; (358c <is_allocated_channel+0x14>)
    357e:	6812      	ldr	r2, [r2, #0]
    3580:	4213      	tst	r3, r2
}
    3582:	bf14      	ite	ne
    3584:	2001      	movne	r0, #1
    3586:	2000      	moveq	r0, #0
    3588:	4770      	bx	lr
    358a:	bf00      	nop
    358c:	2000056c 	.word	0x2000056c

00003590 <channel_allocated_set>:
    3590:	2301      	movs	r3, #1
    3592:	fa03 f000 	lsl.w	r0, r3, r0
 *
 * @param[in] channel_num Specifies the channel to set the "allocated" indication.
 */
static void channel_allocated_set(nrf_ppi_channel_t channel)
{
    m_channels_allocated |= nrfx_ppi_channel_to_mask(channel);
    3596:	4a02      	ldr	r2, [pc, #8]	; (35a0 <channel_allocated_set+0x10>)
    3598:	6813      	ldr	r3, [r2, #0]
    359a:	4303      	orrs	r3, r0
    359c:	6013      	str	r3, [r2, #0]
}
    359e:	4770      	bx	lr
    35a0:	2000056c 	.word	0x2000056c

000035a4 <nrfx_ppi_channel_alloc>:
    group_allocated_clr_all();
}


nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel)
{
    35a4:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    35a8:	4681      	mov	r9, r0
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    uint32_t mask = NRFX_PPI_PROG_APP_CHANNELS_MASK;

    for (uint8_t ch_idx = NRF_PPI_CHANNEL0; mask != 0; ch_idx++)
    35aa:	2400      	movs	r4, #0
    uint32_t mask = NRFX_PPI_PROG_APP_CHANNELS_MASK;
    35ac:	4e15      	ldr	r6, [pc, #84]	; (3604 <nrfx_ppi_channel_alloc+0x60>)
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    35ae:	f8df 805c 	ldr.w	r8, [pc, #92]	; 360c <nrfx_ppi_channel_alloc+0x68>
    for (uint8_t ch_idx = NRF_PPI_CHANNEL0; mask != 0; ch_idx++)
    35b2:	e011      	b.n	35d8 <nrfx_ppi_channel_alloc+0x34>
    {
        nrf_ppi_channel_t channel = (nrf_ppi_channel_t)ch_idx;
        NRFX_CRITICAL_SECTION_ENTER();
        if ((mask & nrfx_ppi_channel_to_mask(channel)) && (!is_allocated_channel(channel)))
        {
            channel_allocated_set(channel);
    35b4:	4620      	mov	r0, r4
    35b6:	f7ff ffeb 	bl	3590 <channel_allocated_set>
            *p_channel = channel;
    35ba:	f889 4000 	strb.w	r4, [r9]
            err_code   = NRFX_SUCCESS;
    35be:	f8df 8048 	ldr.w	r8, [pc, #72]	; 3608 <nrfx_ppi_channel_alloc+0x64>
	__asm__ volatile(
    35c2:	f387 8811 	msr	BASEPRI, r7
    35c6:	f3bf 8f6f 	isb	sy
        }
        NRFX_CRITICAL_SECTION_EXIT();
        if (err_code == NRFX_SUCCESS)
    35ca:	4b0f      	ldr	r3, [pc, #60]	; (3608 <nrfx_ppi_channel_alloc+0x64>)
    35cc:	4598      	cmp	r8, r3
    35ce:	d016      	beq.n	35fe <nrfx_ppi_channel_alloc+0x5a>
        {
            NRFX_LOG_INFO("Allocated channel: %d.", channel);
            break;
        }
        mask &= ~nrfx_ppi_channel_to_mask(channel);
    35d0:	ea26 0605 	bic.w	r6, r6, r5
    for (uint8_t ch_idx = NRF_PPI_CHANNEL0; mask != 0; ch_idx++)
    35d4:	3401      	adds	r4, #1
    35d6:	b2e4      	uxtb	r4, r4
    35d8:	b18e      	cbz	r6, 35fe <nrfx_ppi_channel_alloc+0x5a>
	__asm__ volatile(
    35da:	f04f 0320 	mov.w	r3, #32
    35de:	f3ef 8711 	mrs	r7, BASEPRI
    35e2:	f383 8812 	msr	BASEPRI_MAX, r3
    35e6:	f3bf 8f6f 	isb	sy
    35ea:	2501      	movs	r5, #1
    35ec:	40a5      	lsls	r5, r4
        if ((mask & nrfx_ppi_channel_to_mask(channel)) && (!is_allocated_channel(channel)))
    35ee:	4235      	tst	r5, r6
    35f0:	d0e7      	beq.n	35c2 <nrfx_ppi_channel_alloc+0x1e>
    35f2:	4620      	mov	r0, r4
    35f4:	f7ff ffc0 	bl	3578 <is_allocated_channel>
    35f8:	2800      	cmp	r0, #0
    35fa:	d1e2      	bne.n	35c2 <nrfx_ppi_channel_alloc+0x1e>
    35fc:	e7da      	b.n	35b4 <nrfx_ppi_channel_alloc+0x10>
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    35fe:	4640      	mov	r0, r8
    3600:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    3604:	000fffff 	.word	0x000fffff
    3608:	0bad0000 	.word	0x0bad0000
    360c:	0bad0002 	.word	0x0bad0002

00003610 <finish_transfer>:

    p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
}

static void finish_transfer(spi_control_block_t * p_cb)
{
    3610:	b508      	push	{r3, lr}
    3612:	4603      	mov	r3, r0
    // If Slave Select signal is used, this is the time to deactivate it.
    if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    3614:	7f82      	ldrb	r2, [r0, #30]
    3616:	2aff      	cmp	r2, #255	; 0xff
    3618:	d00a      	beq.n	3630 <finish_transfer+0x20>
    *p_pin = pin_number & 0x1F;
    361a:	f002 011f 	and.w	r1, r2, #31
    return pin_number >> 5;
    361e:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3620:	2a01      	cmp	r2, #1
    3622:	d00e      	beq.n	3642 <finish_transfer+0x32>
        case 0: return NRF_P0;
    3624:	f04f 40a0 	mov.w	r0, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    3628:	2201      	movs	r2, #1
    362a:	408a      	lsls	r2, r1
    p_reg->OUTSET = set_mask;
    362c:	f8c0 2508 	str.w	r2, [r0, #1288]	; 0x508
        nrf_gpio_pin_set(p_cb->ss_pin);
    }

    // By clearing this flag before calling the handler we allow subsequent
    // transfers to be started directly from the handler function.
    p_cb->transfer_in_progress = false;
    3630:	2200      	movs	r2, #0
    3632:	775a      	strb	r2, [r3, #29]

    p_cb->evt.type = NRFX_SPI_EVENT_DONE;
    3634:	721a      	strb	r2, [r3, #8]
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    3636:	4618      	mov	r0, r3
    3638:	f850 2b08 	ldr.w	r2, [r0], #8
    363c:	6859      	ldr	r1, [r3, #4]
    363e:	4790      	blx	r2
}
    3640:	bd08      	pop	{r3, pc}
        case 1: return NRF_P1;
    3642:	4801      	ldr	r0, [pc, #4]	; (3648 <finish_transfer+0x38>)
    3644:	e7f0      	b.n	3628 <finish_transfer+0x18>
    3646:	bf00      	nop
    3648:	50000300 	.word	0x50000300

0000364c <spi_xfer>:
}

static void spi_xfer(NRF_SPI_Type               * p_spi,
                     spi_control_block_t        * p_cb,
                     nrfx_spi_xfer_desc_t const * p_xfer_desc)
{
    364c:	b538      	push	{r3, r4, r5, lr}
    364e:	4604      	mov	r4, r0
    3650:	460d      	mov	r5, r1
    p_cb->bytes_transferred = 0;
    3652:	2300      	movs	r3, #0
    3654:	620b      	str	r3, [r1, #32]
}

NRF_STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg,
                                           uint32_t       mask)
{
    p_reg->INTENCLR = mask;
    3656:	2104      	movs	r1, #4
    3658:	f8c0 1308 	str.w	r1, [r0, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    365c:	f8c0 3108 	str.w	r3, [r0, #264]	; 0x108
    3660:	f8d0 3108 	ldr.w	r3, [r0, #264]	; 0x108

    // Start the transfer by writing some byte to the TXD register;
    // if TX buffer is not empty, take the first byte from this buffer,
    // otherwise - use over-run character.
    nrf_spi_txd_set(p_spi,
        (p_xfer_desc->tx_length > 0 ? p_xfer_desc->p_tx_buffer[0] : p_cb->orc));
    3664:	6853      	ldr	r3, [r2, #4]
    nrf_spi_txd_set(p_spi,
    3666:	b183      	cbz	r3, 368a <spi_xfer+0x3e>
        (p_xfer_desc->tx_length > 0 ? p_xfer_desc->p_tx_buffer[0] : p_cb->orc));
    3668:	6813      	ldr	r3, [r2, #0]
    nrf_spi_txd_set(p_spi,
    366a:	781b      	ldrb	r3, [r3, #0]
#endif
}

NRF_STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data)
{
    p_reg->TXD = data;
    366c:	f8c4 351c 	str.w	r3, [r4, #1308]	; 0x51c

    // TXD register is double buffered, so next byte to be transmitted can
    // be written immediately, if needed, i.e. if TX or RX transfer is to
    // be more that 1 byte long. Again - if there is something more in TX
    // buffer send it, otherwise use over-run character.
    if (p_xfer_desc->tx_length > 1)
    3670:	6853      	ldr	r3, [r2, #4]
    3672:	2b01      	cmp	r3, #1
    3674:	d90b      	bls.n	368e <spi_xfer+0x42>
    {
        nrf_spi_txd_set(p_spi, p_xfer_desc->p_tx_buffer[1]);
    3676:	6813      	ldr	r3, [r2, #0]
    3678:	785b      	ldrb	r3, [r3, #1]
    367a:	f8c4 351c 	str.w	r3, [r4, #1308]	; 0x51c
    // For blocking mode (user handler not provided) wait here for READY
    // events (indicating that the byte from TXD register was transmitted
    // and a new incoming byte was moved to the RXD register) and continue
    // transaction until all requested bytes are transferred.
    // In non-blocking mode - IRQ service routine will do this stuff.
    if (p_cb->handler)
    367e:	682b      	ldr	r3, [r5, #0]
    3680:	b163      	cbz	r3, 369c <spi_xfer+0x50>
    p_reg->INTENSET = mask;
    3682:	2304      	movs	r3, #4
    3684:	f8c4 3304 	str.w	r3, [r4, #772]	; 0x304
        if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
        {
            nrf_gpio_pin_set(p_cb->ss_pin);
        }
    }
}
    3688:	bd38      	pop	{r3, r4, r5, pc}
    nrf_spi_txd_set(p_spi,
    368a:	7feb      	ldrb	r3, [r5, #31]
    368c:	e7ee      	b.n	366c <spi_xfer+0x20>
    else if (p_xfer_desc->rx_length > 1)
    368e:	68d3      	ldr	r3, [r2, #12]
    3690:	2b01      	cmp	r3, #1
    3692:	d9f4      	bls.n	367e <spi_xfer+0x32>
        nrf_spi_txd_set(p_spi, p_cb->orc);
    3694:	7feb      	ldrb	r3, [r5, #31]
    p_reg->TXD = data;
    3696:	f8c4 351c 	str.w	r3, [r4, #1308]	; 0x51c
}
    369a:	e7f0      	b.n	367e <spi_xfer+0x32>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    369c:	f8d4 3108 	ldr.w	r3, [r4, #264]	; 0x108
            while (!nrf_spi_event_check(p_spi, NRF_SPI_EVENT_READY)) {}
    36a0:	2b00      	cmp	r3, #0
    36a2:	d0fb      	beq.n	369c <spi_xfer+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    36a4:	2300      	movs	r3, #0
    36a6:	f8c4 3108 	str.w	r3, [r4, #264]	; 0x108
    36aa:	f8d4 3108 	ldr.w	r3, [r4, #264]	; 0x108
        } while (transfer_byte(p_spi, p_cb));
    36ae:	4629      	mov	r1, r5
    36b0:	4620      	mov	r0, r4
    36b2:	f003 fb13 	bl	6cdc <transfer_byte>
    36b6:	2800      	cmp	r0, #0
    36b8:	d1f0      	bne.n	369c <spi_xfer+0x50>
        if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    36ba:	7fab      	ldrb	r3, [r5, #30]
    36bc:	2bff      	cmp	r3, #255	; 0xff
    36be:	d0e3      	beq.n	3688 <spi_xfer+0x3c>
    *p_pin = pin_number & 0x1F;
    36c0:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    36c4:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    36c6:	2b01      	cmp	r3, #1
    36c8:	d006      	beq.n	36d8 <spi_xfer+0x8c>
        case 0: return NRF_P0;
    36ca:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    36ce:	2301      	movs	r3, #1
    36d0:	4093      	lsls	r3, r2
    p_reg->OUTSET = set_mask;
    36d2:	f8c1 3508 	str.w	r3, [r1, #1288]	; 0x508
}
    36d6:	e7d7      	b.n	3688 <spi_xfer+0x3c>
        case 1: return NRF_P1;
    36d8:	4900      	ldr	r1, [pc, #0]	; (36dc <spi_xfer+0x90>)
    36da:	e7f8      	b.n	36ce <spi_xfer+0x82>
    36dc:	50000300 	.word	0x50000300

000036e0 <nrfx_spi_init>:
{
    36e0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    36e2:	7904      	ldrb	r4, [r0, #4]
    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    36e4:	eb04 0684 	add.w	r6, r4, r4, lsl #2
    36e8:	4d6e      	ldr	r5, [pc, #440]	; (38a4 <nrfx_spi_init+0x1c4>)
    36ea:	eb05 05c6 	add.w	r5, r5, r6, lsl #3
    36ee:	7f2d      	ldrb	r5, [r5, #28]
    36f0:	2d00      	cmp	r5, #0
    36f2:	f040 80d5 	bne.w	38a0 <nrfx_spi_init+0x1c0>
    p_cb->handler = handler;
    36f6:	4d6b      	ldr	r5, [pc, #428]	; (38a4 <nrfx_spi_init+0x1c4>)
    36f8:	eb05 07c6 	add.w	r7, r5, r6, lsl #3
    36fc:	f845 2036 	str.w	r2, [r5, r6, lsl #3]
    p_cb->p_context = p_context;
    3700:	607b      	str	r3, [r7, #4]
    if (p_config->mode <= NRF_SPI_MODE_1)
    3702:	7b0b      	ldrb	r3, [r1, #12]
    3704:	2b01      	cmp	r3, #1
    3706:	f240 809f 	bls.w	3848 <nrfx_spi_init+0x168>
        nrf_gpio_pin_set(p_config->sck_pin);
    370a:	780b      	ldrb	r3, [r1, #0]
    *p_pin = pin_number & 0x1F;
    370c:	f003 061f 	and.w	r6, r3, #31
    return pin_number >> 5;
    3710:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3712:	2b01      	cmp	r3, #1
    3714:	f000 80a7 	beq.w	3866 <nrfx_spi_init+0x186>
        case 0: return NRF_P0;
    3718:	f04f 45a0 	mov.w	r5, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    371c:	2301      	movs	r3, #1
    371e:	40b3      	lsls	r3, r6
    p_reg->OUTSET = set_mask;
    3720:	f8c5 3508 	str.w	r3, [r5, #1288]	; 0x508
    nrf_gpio_cfg(p_config->sck_pin,
    3724:	780b      	ldrb	r3, [r1, #0]
    *p_pin = pin_number & 0x1F;
    3726:	f003 051f 	and.w	r5, r3, #31
    return pin_number >> 5;
    372a:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    372c:	2b01      	cmp	r3, #1
    372e:	f000 809c 	beq.w	386a <nrfx_spi_init+0x18a>
        case 0: return NRF_P0;
    3732:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    3736:	f505 73e0 	add.w	r3, r5, #448	; 0x1c0
    373a:	2501      	movs	r5, #1
    373c:	f846 5023 	str.w	r5, [r6, r3, lsl #2]
    if (p_config->mosi_pin != NRFX_SPI_PIN_NOT_USED)
    3740:	784b      	ldrb	r3, [r1, #1]
    3742:	2bff      	cmp	r3, #255	; 0xff
    3744:	f000 8095 	beq.w	3872 <nrfx_spi_init+0x192>
        mosi_pin = p_config->mosi_pin;
    3748:	461d      	mov	r5, r3
    *p_pin = pin_number & 0x1F;
    374a:	f003 061f 	and.w	r6, r3, #31
    return pin_number >> 5;
    374e:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3750:	2b01      	cmp	r3, #1
    3752:	f000 808c 	beq.w	386e <nrfx_spi_init+0x18e>
        case 0: return NRF_P0;
    3756:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    375a:	2301      	movs	r3, #1
    375c:	40b3      	lsls	r3, r6
    p_reg->OUTCLR = clr_mask;
    375e:	f8c7 350c 	str.w	r3, [r7, #1292]	; 0x50c
    reg->PIN_CNF[pin_number] = cnf;
    3762:	f506 76e0 	add.w	r6, r6, #448	; 0x1c0
    3766:	2303      	movs	r3, #3
    3768:	f847 3026 	str.w	r3, [r7, r6, lsl #2]
    if (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED)
    376c:	788b      	ldrb	r3, [r1, #2]
    376e:	2bff      	cmp	r3, #255	; 0xff
    3770:	f000 8085 	beq.w	387e <nrfx_spi_init+0x19e>
        miso_pin = p_config->miso_pin;
    3774:	461e      	mov	r6, r3
        nrf_gpio_cfg_input(miso_pin, p_config->miso_pull);
    3776:	f891 c00e 	ldrb.w	ip, [r1, #14]
    *p_pin = pin_number & 0x1F;
    377a:	f003 071f 	and.w	r7, r3, #31
    return pin_number >> 5;
    377e:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3780:	2b01      	cmp	r3, #1
    3782:	d079      	beq.n	3878 <nrfx_spi_init+0x198>
        case 0: return NRF_P0;
    3784:	f04f 4ea0 	mov.w	lr, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    3788:	ea4f 0c8c 	mov.w	ip, ip, lsl #2
    reg->PIN_CNF[pin_number] = cnf;
    378c:	f507 73e0 	add.w	r3, r7, #448	; 0x1c0
    3790:	f84e c023 	str.w	ip, [lr, r3, lsl #2]
    if (p_config->ss_pin != NRFX_SPI_PIN_NOT_USED)
    3794:	78cb      	ldrb	r3, [r1, #3]
    3796:	2bff      	cmp	r3, #255	; 0xff
    3798:	d018      	beq.n	37cc <nrfx_spi_init+0xec>
    *p_pin = pin_number & 0x1F;
    379a:	f003 0c1f 	and.w	ip, r3, #31
    return pin_number >> 5;
    379e:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    37a0:	2b01      	cmp	r3, #1
    37a2:	d06f      	beq.n	3884 <nrfx_spi_init+0x1a4>
        case 0: return NRF_P0;
    37a4:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    37a8:	2301      	movs	r3, #1
    37aa:	fa03 f30c 	lsl.w	r3, r3, ip
    p_reg->OUTSET = set_mask;
    37ae:	f8c7 3508 	str.w	r3, [r7, #1288]	; 0x508
        nrf_gpio_cfg_output(p_config->ss_pin);
    37b2:	78cb      	ldrb	r3, [r1, #3]
    *p_pin = pin_number & 0x1F;
    37b4:	f003 071f 	and.w	r7, r3, #31
    return pin_number >> 5;
    37b8:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    37ba:	2b01      	cmp	r3, #1
    37bc:	d064      	beq.n	3888 <nrfx_spi_init+0x1a8>
        case 0: return NRF_P0;
    37be:	f04f 4ca0 	mov.w	ip, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    37c2:	f507 73e0 	add.w	r3, r7, #448	; 0x1c0
    37c6:	2703      	movs	r7, #3
    37c8:	f84c 7023 	str.w	r7, [ip, r3, lsl #2]
    m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin;
    37cc:	7903      	ldrb	r3, [r0, #4]
    37ce:	f891 c003 	ldrb.w	ip, [r1, #3]
    37d2:	eb03 0383 	add.w	r3, r3, r3, lsl #2
    37d6:	4f33      	ldr	r7, [pc, #204]	; (38a4 <nrfx_spi_init+0x1c4>)
    37d8:	eb07 03c3 	add.w	r3, r7, r3, lsl #3
    37dc:	f883 c01e 	strb.w	ip, [r3, #30]
    NRF_SPI_Type * p_spi = p_instance->p_reg;
    37e0:	6803      	ldr	r3, [r0, #0]
    nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin);
    37e2:	780f      	ldrb	r7, [r1, #0]
    p_reg->PSEL.SCK = sck_pin;
    37e4:	f8c3 7508 	str.w	r7, [r3, #1288]	; 0x508
    p_reg->PSEL.MOSI = mosi_pin;
    37e8:	f8c3 550c 	str.w	r5, [r3, #1292]	; 0x50c
    p_reg->PSEL.MISO = miso_pin;
    37ec:	f8c3 6510 	str.w	r6, [r3, #1296]	; 0x510
    nrf_spi_frequency_set(p_spi, p_config->frequency);
    37f0:	688d      	ldr	r5, [r1, #8]
}

NRF_STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type *      p_reg,
                                             nrf_spi_frequency_t frequency)
{
    p_reg->FREQUENCY = (uint32_t)frequency;
    37f2:	f8c3 5524 	str.w	r5, [r3, #1316]	; 0x524
    nrf_spi_configure(p_spi, p_config->mode, p_config->bit_order);
    37f6:	7b0e      	ldrb	r6, [r1, #12]
    37f8:	7b4d      	ldrb	r5, [r1, #13]
NRF_STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type *      p_reg,
                                         nrf_spi_mode_t      spi_mode,
                                         nrf_spi_bit_order_t spi_bit_order)
{
    uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ?
        SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst);
    37fa:	3d00      	subs	r5, #0
    37fc:	bf18      	it	ne
    37fe:	2501      	movne	r5, #1
    switch (spi_mode)
    3800:	2e02      	cmp	r6, #2
    3802:	d047      	beq.n	3894 <nrfx_spi_init+0x1b4>
    3804:	2e03      	cmp	r6, #3
    3806:	d048      	beq.n	389a <nrfx_spi_init+0x1ba>
    3808:	2e01      	cmp	r6, #1
    380a:	d040      	beq.n	388e <nrfx_spi_init+0x1ae>
    case NRF_SPI_MODE_3:
        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
                  (SPI_CONFIG_CPHA_Trailing   << SPI_CONFIG_CPHA_Pos);
        break;
    }
    p_reg->CONFIG = config;
    380c:	f8c3 5554 	str.w	r5, [r3, #1364]	; 0x554
    m_cb[p_instance->drv_inst_idx].orc = p_config->orc;
    3810:	7905      	ldrb	r5, [r0, #4]
    3812:	794e      	ldrb	r6, [r1, #5]
    3814:	eb05 0585 	add.w	r5, r5, r5, lsl #2
    3818:	4922      	ldr	r1, [pc, #136]	; (38a4 <nrfx_spi_init+0x1c4>)
    381a:	eb01 05c5 	add.w	r5, r1, r5, lsl #3
    381e:	77ee      	strb	r6, [r5, #31]
    p_reg->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
    3820:	2101      	movs	r1, #1
    3822:	f8c3 1500 	str.w	r1, [r3, #1280]	; 0x500
    if (p_cb->handler)
    3826:	b122      	cbz	r2, 3832 <nrfx_spi_init+0x152>
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg));
    3828:	6800      	ldr	r0, [r0, #0]
    382a:	f340 3007 	sbfx	r0, r0, #12, #8
    382e:	f7fd fccf 	bl	11d0 <arch_irq_enable>
    p_cb->transfer_in_progress = false;
    3832:	4b1c      	ldr	r3, [pc, #112]	; (38a4 <nrfx_spi_init+0x1c4>)
    3834:	eb04 0284 	add.w	r2, r4, r4, lsl #2
    3838:	eb03 02c2 	add.w	r2, r3, r2, lsl #3
    383c:	2100      	movs	r1, #0
    383e:	7751      	strb	r1, [r2, #29]
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    3840:	2301      	movs	r3, #1
    3842:	7713      	strb	r3, [r2, #28]
    return err_code;
    3844:	4818      	ldr	r0, [pc, #96]	; (38a8 <nrfx_spi_init+0x1c8>)
}
    3846:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        nrf_gpio_pin_clear(p_config->sck_pin);
    3848:	780b      	ldrb	r3, [r1, #0]
    *p_pin = pin_number & 0x1F;
    384a:	f003 061f 	and.w	r6, r3, #31
    return pin_number >> 5;
    384e:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3850:	2b01      	cmp	r3, #1
    3852:	d006      	beq.n	3862 <nrfx_spi_init+0x182>
        case 0: return NRF_P0;
    3854:	f04f 45a0 	mov.w	r5, #1342177280	; 0x50000000
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    3858:	2301      	movs	r3, #1
    385a:	40b3      	lsls	r3, r6
    p_reg->OUTCLR = clr_mask;
    385c:	f8c5 350c 	str.w	r3, [r5, #1292]	; 0x50c
}
    3860:	e760      	b.n	3724 <nrfx_spi_init+0x44>
        case 1: return NRF_P1;
    3862:	4d12      	ldr	r5, [pc, #72]	; (38ac <nrfx_spi_init+0x1cc>)
    3864:	e7f8      	b.n	3858 <nrfx_spi_init+0x178>
    3866:	4d11      	ldr	r5, [pc, #68]	; (38ac <nrfx_spi_init+0x1cc>)
    3868:	e758      	b.n	371c <nrfx_spi_init+0x3c>
    386a:	4e10      	ldr	r6, [pc, #64]	; (38ac <nrfx_spi_init+0x1cc>)
    386c:	e763      	b.n	3736 <nrfx_spi_init+0x56>
    386e:	4f0f      	ldr	r7, [pc, #60]	; (38ac <nrfx_spi_init+0x1cc>)
    3870:	e773      	b.n	375a <nrfx_spi_init+0x7a>
        mosi_pin = NRF_SPI_PIN_NOT_CONNECTED;
    3872:	f04f 35ff 	mov.w	r5, #4294967295
    3876:	e779      	b.n	376c <nrfx_spi_init+0x8c>
    3878:	f8df e030 	ldr.w	lr, [pc, #48]	; 38ac <nrfx_spi_init+0x1cc>
    387c:	e784      	b.n	3788 <nrfx_spi_init+0xa8>
        miso_pin = NRF_SPI_PIN_NOT_CONNECTED;
    387e:	f04f 36ff 	mov.w	r6, #4294967295
    3882:	e787      	b.n	3794 <nrfx_spi_init+0xb4>
    3884:	4f09      	ldr	r7, [pc, #36]	; (38ac <nrfx_spi_init+0x1cc>)
    3886:	e78f      	b.n	37a8 <nrfx_spi_init+0xc8>
    3888:	f8df c020 	ldr.w	ip, [pc, #32]	; 38ac <nrfx_spi_init+0x1cc>
    388c:	e799      	b.n	37c2 <nrfx_spi_init+0xe2>
        config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
    388e:	f045 0502 	orr.w	r5, r5, #2
        break;
    3892:	e7bb      	b.n	380c <nrfx_spi_init+0x12c>
        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
    3894:	f045 0504 	orr.w	r5, r5, #4
        break;
    3898:	e7b8      	b.n	380c <nrfx_spi_init+0x12c>
        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
    389a:	f045 0506 	orr.w	r5, r5, #6
        break;
    389e:	e7b5      	b.n	380c <nrfx_spi_init+0x12c>
        return err_code;
    38a0:	4803      	ldr	r0, [pc, #12]	; (38b0 <nrfx_spi_init+0x1d0>)
    38a2:	e7d0      	b.n	3846 <nrfx_spi_init+0x166>
    38a4:	20000570 	.word	0x20000570
    38a8:	0bad0000 	.word	0x0bad0000
    38ac:	50000300 	.word	0x50000300
    38b0:	0bad0005 	.word	0x0bad0005

000038b4 <nrfx_spi_uninit>:
{
    38b4:	b538      	push	{r3, r4, r5, lr}
    spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    38b6:	7904      	ldrb	r4, [r0, #4]
    NRF_SPI_Type * p_spi = p_instance->p_reg;
    38b8:	6805      	ldr	r5, [r0, #0]
    if (p_cb->handler)
    38ba:	eb04 0284 	add.w	r2, r4, r4, lsl #2
    38be:	4b31      	ldr	r3, [pc, #196]	; (3984 <nrfx_spi_uninit+0xd0>)
    38c0:	f853 3032 	ldr.w	r3, [r3, r2, lsl #3]
    38c4:	b133      	cbz	r3, 38d4 <nrfx_spi_uninit+0x20>
        NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg));
    38c6:	f345 3007 	sbfx	r0, r5, #12, #8
    38ca:	f7fd fc91 	bl	11f0 <arch_irq_disable>
    p_reg->INTENCLR = mask;
    38ce:	2304      	movs	r3, #4
    38d0:	f8c5 3308 	str.w	r3, [r5, #776]	; 0x308
    p_reg->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
    38d4:	2300      	movs	r3, #0
    38d6:	f8c5 3500 	str.w	r3, [r5, #1280]	; 0x500
    return p_reg->PSEL.SCK;
    38da:	f8d5 3508 	ldr.w	r3, [r5, #1288]	; 0x508
    *p_pin = pin_number & 0x1F;
    38de:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    38e2:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    38e4:	2b01      	cmp	r3, #1
    38e6:	d044      	beq.n	3972 <nrfx_spi_uninit+0xbe>
        case 0: return NRF_P0;
    38e8:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    38ec:	f502 73e0 	add.w	r3, r2, #448	; 0x1c0
    38f0:	2202      	movs	r2, #2
    38f2:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    return p_reg->PSEL.MISO;
    38f6:	f8d5 3510 	ldr.w	r3, [r5, #1296]	; 0x510
    if (miso_pin != NRF_SPI_PIN_NOT_CONNECTED)
    38fa:	f1b3 3fff 	cmp.w	r3, #4294967295
    38fe:	d00b      	beq.n	3918 <nrfx_spi_uninit+0x64>
    *p_pin = pin_number & 0x1F;
    3900:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    3904:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3906:	2b01      	cmp	r3, #1
    3908:	d035      	beq.n	3976 <nrfx_spi_uninit+0xc2>
        case 0: return NRF_P0;
    390a:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    390e:	f502 73e0 	add.w	r3, r2, #448	; 0x1c0
    3912:	2202      	movs	r2, #2
    3914:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    return p_reg->PSEL.MOSI;
    3918:	f8d5 350c 	ldr.w	r3, [r5, #1292]	; 0x50c
    if (mosi_pin != NRF_SPI_PIN_NOT_CONNECTED)
    391c:	f1b3 3fff 	cmp.w	r3, #4294967295
    3920:	d00b      	beq.n	393a <nrfx_spi_uninit+0x86>
    *p_pin = pin_number & 0x1F;
    3922:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    3926:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3928:	2b01      	cmp	r3, #1
    392a:	d026      	beq.n	397a <nrfx_spi_uninit+0xc6>
        case 0: return NRF_P0;
    392c:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    3930:	f502 73e0 	add.w	r3, r2, #448	; 0x1c0
    3934:	2202      	movs	r2, #2
    3936:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    393a:	eb04 0384 	add.w	r3, r4, r4, lsl #2
    393e:	4a11      	ldr	r2, [pc, #68]	; (3984 <nrfx_spi_uninit+0xd0>)
    3940:	eb02 03c3 	add.w	r3, r2, r3, lsl #3
    3944:	7f9b      	ldrb	r3, [r3, #30]
    3946:	2bff      	cmp	r3, #255	; 0xff
    3948:	d00b      	beq.n	3962 <nrfx_spi_uninit+0xae>
    *p_pin = pin_number & 0x1F;
    394a:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    394e:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3950:	2b01      	cmp	r3, #1
    3952:	d014      	beq.n	397e <nrfx_spi_uninit+0xca>
        case 0: return NRF_P0;
    3954:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    3958:	f502 73e0 	add.w	r3, r2, #448	; 0x1c0
    395c:	2202      	movs	r2, #2
    395e:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
    3962:	eb04 0484 	add.w	r4, r4, r4, lsl #2
    3966:	4b07      	ldr	r3, [pc, #28]	; (3984 <nrfx_spi_uninit+0xd0>)
    3968:	eb03 04c4 	add.w	r4, r3, r4, lsl #3
    396c:	2300      	movs	r3, #0
    396e:	7723      	strb	r3, [r4, #28]
}
    3970:	bd38      	pop	{r3, r4, r5, pc}
        case 1: return NRF_P1;
    3972:	4905      	ldr	r1, [pc, #20]	; (3988 <nrfx_spi_uninit+0xd4>)
    3974:	e7ba      	b.n	38ec <nrfx_spi_uninit+0x38>
    3976:	4904      	ldr	r1, [pc, #16]	; (3988 <nrfx_spi_uninit+0xd4>)
    3978:	e7c9      	b.n	390e <nrfx_spi_uninit+0x5a>
    397a:	4903      	ldr	r1, [pc, #12]	; (3988 <nrfx_spi_uninit+0xd4>)
    397c:	e7d8      	b.n	3930 <nrfx_spi_uninit+0x7c>
    397e:	4902      	ldr	r1, [pc, #8]	; (3988 <nrfx_spi_uninit+0xd4>)
    3980:	e7ea      	b.n	3958 <nrfx_spi_uninit+0xa4>
    3982:	bf00      	nop
    3984:	20000570 	.word	0x20000570
    3988:	50000300 	.word	0x50000300

0000398c <nrfx_spi_xfer>:

nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const *           p_instance,
                         nrfx_spi_xfer_desc_t const * p_xfer_desc,
                         uint32_t                     flags)
{
    398c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    3990:	7904      	ldrb	r4, [r0, #4]
    3992:	eb04 0384 	add.w	r3, r4, r4, lsl #2
    3996:	4f23      	ldr	r7, [pc, #140]	; (3a24 <nrfx_spi_xfer+0x98>)
    3998:	eb07 07c3 	add.w	r7, r7, r3, lsl #3
    NRFX_ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0);
    NRFX_ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0);

    nrfx_err_t err_code = NRFX_SUCCESS;

    if (p_cb->transfer_in_progress)
    399c:	7f7b      	ldrb	r3, [r7, #29]
    399e:	2b00      	cmp	r3, #0
    39a0:	d13d      	bne.n	3a1e <nrfx_spi_xfer+0x92>
    39a2:	4606      	mov	r6, r0
    39a4:	460d      	mov	r5, r1
    39a6:	4696      	mov	lr, r2
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
    else
    {
        if (p_cb->handler)
    39a8:	eb04 0384 	add.w	r3, r4, r4, lsl #2
    39ac:	4a1d      	ldr	r2, [pc, #116]	; (3a24 <nrfx_spi_xfer+0x98>)
    39ae:	f852 3033 	ldr.w	r3, [r2, r3, lsl #3]
    39b2:	b10b      	cbz	r3, 39b8 <nrfx_spi_xfer+0x2c>
        {
            p_cb->transfer_in_progress = true;
    39b4:	2201      	movs	r2, #1
    39b6:	777a      	strb	r2, [r7, #29]
        }
    }

    p_cb->evt.xfer_desc = *p_xfer_desc;
    39b8:	eb04 0c84 	add.w	ip, r4, r4, lsl #2
    39bc:	4b19      	ldr	r3, [pc, #100]	; (3a24 <nrfx_spi_xfer+0x98>)
    39be:	eb03 0ccc 	add.w	ip, r3, ip, lsl #3
    39c2:	f10c 080c 	add.w	r8, ip, #12
    39c6:	e895 000f 	ldmia.w	r5, {r0, r1, r2, r3}
    39ca:	e888 000f 	stmia.w	r8, {r0, r1, r2, r3}
    p_cb->abort = false;
    39ce:	2300      	movs	r3, #0
    39d0:	f88c 3024 	strb.w	r3, [ip, #36]	; 0x24

    if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
    39d4:	f89c 301e 	ldrb.w	r3, [ip, #30]
    39d8:	2bff      	cmp	r3, #255	; 0xff
    39da:	d00a      	beq.n	39f2 <nrfx_spi_xfer+0x66>
    *p_pin = pin_number & 0x1F;
    39dc:	f003 011f 	and.w	r1, r3, #31
    return pin_number >> 5;
    39e0:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    39e2:	2b01      	cmp	r3, #1
    39e4:	d012      	beq.n	3a0c <nrfx_spi_xfer+0x80>
        case 0: return NRF_P0;
    39e6:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    39ea:	2301      	movs	r3, #1
    39ec:	408b      	lsls	r3, r1
    p_reg->OUTCLR = clr_mask;
    39ee:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
    {
        nrf_gpio_pin_clear(p_cb->ss_pin);
    }
    if (flags)
    39f2:	f1be 0f00 	cmp.w	lr, #0
    39f6:	d00b      	beq.n	3a10 <nrfx_spi_xfer+0x84>
    {
        p_cb->transfer_in_progress = false;
    39f8:	eb04 0484 	add.w	r4, r4, r4, lsl #2
    39fc:	4b09      	ldr	r3, [pc, #36]	; (3a24 <nrfx_spi_xfer+0x98>)
    39fe:	eb03 04c4 	add.w	r4, r3, r4, lsl #3
    3a02:	2300      	movs	r3, #0
    3a04:	7763      	strb	r3, [r4, #29]
        err_code = NRFX_ERROR_NOT_SUPPORTED;
    3a06:	4808      	ldr	r0, [pc, #32]	; (3a28 <nrfx_spi_xfer+0x9c>)
    }
    NRFX_LOG_INFO("Function: %s, error code: %s.",
                  __func__,
                  NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    3a08:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        case 1: return NRF_P1;
    3a0c:	4a07      	ldr	r2, [pc, #28]	; (3a2c <nrfx_spi_xfer+0xa0>)
    3a0e:	e7ec      	b.n	39ea <nrfx_spi_xfer+0x5e>
        spi_xfer(p_instance->p_reg, p_cb, p_xfer_desc);
    3a10:	462a      	mov	r2, r5
    3a12:	4639      	mov	r1, r7
    3a14:	6830      	ldr	r0, [r6, #0]
    3a16:	f7ff fe19 	bl	364c <spi_xfer>
    nrfx_err_t err_code = NRFX_SUCCESS;
    3a1a:	4805      	ldr	r0, [pc, #20]	; (3a30 <nrfx_spi_xfer+0xa4>)
    3a1c:	e7f4      	b.n	3a08 <nrfx_spi_xfer+0x7c>
        return err_code;
    3a1e:	4805      	ldr	r0, [pc, #20]	; (3a34 <nrfx_spi_xfer+0xa8>)
    3a20:	e7f2      	b.n	3a08 <nrfx_spi_xfer+0x7c>
    3a22:	bf00      	nop
    3a24:	20000570 	.word	0x20000570
    3a28:	0bad0003 	.word	0x0bad0003
    3a2c:	50000300 	.word	0x50000300
    3a30:	0bad0000 	.word	0x0bad0000
    3a34:	0bad000b 	.word	0x0bad000b

00003a38 <nrfx_spi_0_irq_handler>:
    }
}

#if NRFX_CHECK(NRFX_SPI0_ENABLED)
void nrfx_spi_0_irq_handler(void)
{
    3a38:	b508      	push	{r3, lr}
    irq_handler(NRF_SPI0, &m_cb[NRFX_SPI0_INST_IDX]);
    3a3a:	4902      	ldr	r1, [pc, #8]	; (3a44 <nrfx_spi_0_irq_handler+0xc>)
    3a3c:	4802      	ldr	r0, [pc, #8]	; (3a48 <nrfx_spi_0_irq_handler+0x10>)
    3a3e:	f003 f988 	bl	6d52 <irq_handler>
}
    3a42:	bd08      	pop	{r3, pc}
    3a44:	20000570 	.word	0x20000570
    3a48:	40003000 	.word	0x40003000

00003a4c <nrfx_spi_1_irq_handler>:
#endif

#if NRFX_CHECK(NRFX_SPI1_ENABLED)
void nrfx_spi_1_irq_handler(void)
{
    3a4c:	b508      	push	{r3, lr}
    irq_handler(NRF_SPI1, &m_cb[NRFX_SPI1_INST_IDX]);
    3a4e:	4903      	ldr	r1, [pc, #12]	; (3a5c <nrfx_spi_1_irq_handler+0x10>)
    3a50:	f04f 2040 	mov.w	r0, #1073758208	; 0x40004000
    3a54:	f003 f97d 	bl	6d52 <irq_handler>
}
    3a58:	bd08      	pop	{r3, pc}
    3a5a:	bf00      	nop
    3a5c:	20000598 	.word	0x20000598

00003a60 <spim_pin_uninit>:
    return err_code;
}

static void spim_pin_uninit(uint32_t pin)
{
    if (pin == NRF_SPIM_PIN_NOT_CONNECTED)
    3a60:	f1b0 3fff 	cmp.w	r0, #4294967295
    3a64:	d00b      	beq.n	3a7e <spim_pin_uninit+0x1e>
    *p_pin = pin_number & 0x1F;
    3a66:	f000 031f 	and.w	r3, r0, #31
    return pin_number >> 5;
    3a6a:	0940      	lsrs	r0, r0, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3a6c:	2801      	cmp	r0, #1
    3a6e:	d007      	beq.n	3a80 <spim_pin_uninit+0x20>
        case 0: return NRF_P0;
    3a70:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    3a74:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    3a78:	2202      	movs	r2, #2
    3a7a:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    {
        return;
    }

    nrf_gpio_cfg_default(pin);
}
    3a7e:	4770      	bx	lr
        case 1: return NRF_P1;
    3a80:	4900      	ldr	r1, [pc, #0]	; (3a84 <spim_pin_uninit+0x24>)
    3a82:	e7f7      	b.n	3a74 <spim_pin_uninit+0x14>
    3a84:	50000300 	.word	0x50000300

00003a88 <finish_transfer>:
    return nrfx_spim_xfer(p_instance, p_xfer_desc, 0);
}
#endif

static void finish_transfer(spim_control_block_t * p_cb)
{
    3a88:	b508      	push	{r3, lr}
    3a8a:	4603      	mov	r3, r0
    // If Slave Select signal is used, this is the time to deactivate it.
    if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    3a8c:	f890 2020 	ldrb.w	r2, [r0, #32]
    3a90:	2aff      	cmp	r2, #255	; 0xff
    3a92:	d00e      	beq.n	3ab2 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x1a>
    {
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
        if (!p_cb->use_hw_ss)
    3a94:	7f81      	ldrb	r1, [r0, #30]
    3a96:	b961      	cbnz	r1, 3ab2 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x1a>
#endif
        {
            if (p_cb->ss_active_high)
    3a98:	7fc1      	ldrb	r1, [r0, #31]
    3a9a:	b1a9      	cbz	r1, 3ac8 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x30>
    *p_pin = pin_number & 0x1F;
    3a9c:	f002 011f 	and.w	r1, r2, #31
    return pin_number >> 5;
    3aa0:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3aa2:	2a01      	cmp	r2, #1
    3aa4:	d00e      	beq.n	3ac4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x2c>
        case 0: return NRF_P0;
    3aa6:	f04f 40a0 	mov.w	r0, #1342177280	; 0x50000000
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    3aaa:	2201      	movs	r2, #1
    3aac:	408a      	lsls	r2, r1
    p_reg->OUTCLR = clr_mask;
    3aae:	f8c0 250c 	str.w	r2, [r0, #1292]	; 0x50c
        }
    }

    // By clearing this flag before calling the handler we allow subsequent
    // transfers to be started directly from the handler function.
    p_cb->transfer_in_progress = false;
    3ab2:	2200      	movs	r2, #0
    3ab4:	775a      	strb	r2, [r3, #29]

    p_cb->evt.type = NRFX_SPIM_EVENT_DONE;
    3ab6:	721a      	strb	r2, [r3, #8]
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    3ab8:	4618      	mov	r0, r3
    3aba:	f850 2b08 	ldr.w	r2, [r0], #8
    3abe:	6859      	ldr	r1, [r3, #4]
    3ac0:	4790      	blx	r2
}
    3ac2:	bd08      	pop	{r3, pc}
        case 1: return NRF_P1;
    3ac4:	4807      	ldr	r0, [pc, #28]	; (3ae4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x4c>)
    3ac6:	e7f0      	b.n	3aaa <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x12>
    *p_pin = pin_number & 0x1F;
    3ac8:	f002 011f 	and.w	r1, r2, #31
    return pin_number >> 5;
    3acc:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3ace:	2a01      	cmp	r2, #1
    3ad0:	d006      	beq.n	3ae0 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x48>
        case 0: return NRF_P0;
    3ad2:	f04f 40a0 	mov.w	r0, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    3ad6:	2201      	movs	r2, #1
    3ad8:	408a      	lsls	r2, r1
    p_reg->OUTSET = set_mask;
    3ada:	f8c0 2508 	str.w	r2, [r0, #1288]	; 0x508
}
    3ade:	e7e8      	b.n	3ab2 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x1a>
        case 1: return NRF_P1;
    3ae0:	4800      	ldr	r0, [pc, #0]	; (3ae4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x4c>)
    3ae2:	e7f8      	b.n	3ad6 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x3e>
    3ae4:	50000300 	.word	0x50000300

00003ae8 <spim_xfer>:

static nrfx_err_t spim_xfer(NRF_SPIM_Type               * p_spim,
                            spim_control_block_t        * p_cb,
                            nrfx_spim_xfer_desc_t const * p_xfer_desc,
                            uint32_t                      flags)
{
    3ae8:	b570      	push	{r4, r5, r6, lr}
    3aea:	4604      	mov	r4, r0
    3aec:	460d      	mov	r5, r1
    3aee:	461e      	mov	r6, r3
    nrfx_err_t err_code;
    // EasyDMA requires that transfer buffers are placed in Data RAM region;
    // signal error if they are not.
    if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) ||
    3af0:	6813      	ldr	r3, [r2, #0]
    3af2:	b123      	cbz	r3, 3afe <spim_xfer+0x16>
    3af4:	f003 4160 	and.w	r1, r3, #3758096384	; 0xe0000000
    3af8:	f1b1 5f00 	cmp.w	r1, #536870912	; 0x20000000
    3afc:	d106      	bne.n	3b0c <spim_xfer+0x24>
        (p_xfer_desc->p_rx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_rx_buffer)))
    3afe:	6891      	ldr	r1, [r2, #8]
    if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) ||
    3b00:	b141      	cbz	r1, 3b14 <spim_xfer+0x2c>
    3b02:	f001 4160 	and.w	r1, r1, #3758096384	; 0xe0000000
        (p_xfer_desc->p_rx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_rx_buffer)))
    3b06:	f1b1 5f00 	cmp.w	r1, #536870912	; 0x20000000
    3b0a:	d003      	beq.n	3b14 <spim_xfer+0x2c>
    {
        p_cb->transfer_in_progress = false;
    3b0c:	2300      	movs	r3, #0
    3b0e:	776b      	strb	r3, [r5, #29]
        err_code = NRFX_ERROR_INVALID_ADDR;
        NRFX_LOG_WARNING("Function: %s, error code: %s.",
                         __func__,
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    3b10:	482a      	ldr	r0, [pc, #168]	; (3bbc <spim_xfer+0xd4>)
        spim_int_enable(p_spim, !(flags & NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER));
    }
    err_code = NRFX_SUCCESS;
    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    3b12:	bd70      	pop	{r4, r5, r6, pc}
    nrf_spim_tx_buffer_set(p_spim, p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length);
    3b14:	6851      	ldr	r1, [r2, #4]

NRF_STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
                                              uint8_t const * p_buffer,
                                              size_t          length)
{
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    3b16:	f8c4 3544 	str.w	r3, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    3b1a:	f8c4 1548 	str.w	r1, [r4, #1352]	; 0x548
    nrf_spim_rx_buffer_set(p_spim, p_xfer_desc->p_rx_buffer, p_xfer_desc->rx_length);
    3b1e:	6891      	ldr	r1, [r2, #8]
    3b20:	68d3      	ldr	r3, [r2, #12]

NRF_STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
                                              uint8_t * p_buffer,
                                              size_t    length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    3b22:	f8c4 1534 	str.w	r1, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    3b26:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3b2a:	2300      	movs	r3, #0
    3b2c:	f8c4 3118 	str.w	r3, [r4, #280]	; 0x118
    3b30:	f8d4 3118 	ldr.w	r3, [r4, #280]	; 0x118
    spim_list_enable_handle(p_spim, flags);
    3b34:	4631      	mov	r1, r6
    3b36:	4620      	mov	r0, r4
    3b38:	f003 f923 	bl	6d82 <spim_list_enable_handle>
    if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER))
    3b3c:	f016 0208 	ands.w	r2, r6, #8
    3b40:	d101      	bne.n	3b46 <spim_xfer+0x5e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3b42:	2301      	movs	r3, #1
    3b44:	6123      	str	r3, [r4, #16]
    if (!p_cb->handler)
    3b46:	682b      	ldr	r3, [r5, #0]
    3b48:	b14b      	cbz	r3, 3b5e <spim_xfer+0x76>
        spim_int_enable(p_spim, !(flags & NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER));
    3b4a:	f016 0f04 	tst.w	r6, #4
    3b4e:	bf0c      	ite	eq
    3b50:	2101      	moveq	r1, #1
    3b52:	2100      	movne	r1, #0
    3b54:	4620      	mov	r0, r4
    3b56:	f003 f90b 	bl	6d70 <spim_int_enable>
    return err_code;
    3b5a:	4819      	ldr	r0, [pc, #100]	; (3bc0 <spim_xfer+0xd8>)
    3b5c:	e7d9      	b.n	3b12 <spim_xfer+0x2a>
        if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER))
    3b5e:	b91a      	cbnz	r2, 3b68 <spim_xfer+0x80>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3b60:	f8d4 3118 	ldr.w	r3, [r4, #280]	; 0x118
            while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END))
    3b64:	2b00      	cmp	r3, #0
    3b66:	d0fb      	beq.n	3b60 <spim_xfer+0x78>
        if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    3b68:	f895 3020 	ldrb.w	r3, [r5, #32]
    3b6c:	2bff      	cmp	r3, #255	; 0xff
    3b6e:	d021      	beq.n	3bb4 <spim_xfer+0xcc>
            if (!p_cb->use_hw_ss)
    3b70:	7faa      	ldrb	r2, [r5, #30]
    3b72:	bb0a      	cbnz	r2, 3bb8 <spim_xfer+0xd0>
                if (p_cb->ss_active_high)
    3b74:	7fea      	ldrb	r2, [r5, #31]
    3b76:	b172      	cbz	r2, 3b96 <spim_xfer+0xae>
    *p_pin = pin_number & 0x1F;
    3b78:	f003 011f 	and.w	r1, r3, #31
    return pin_number >> 5;
    3b7c:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3b7e:	2b01      	cmp	r3, #1
    3b80:	d007      	beq.n	3b92 <spim_xfer+0xaa>
        case 0: return NRF_P0;
    3b82:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    3b86:	2301      	movs	r3, #1
    3b88:	408b      	lsls	r3, r1
    p_reg->OUTCLR = clr_mask;
    3b8a:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
    return err_code;
    3b8e:	480c      	ldr	r0, [pc, #48]	; (3bc0 <spim_xfer+0xd8>)
}
    3b90:	e7bf      	b.n	3b12 <spim_xfer+0x2a>
        case 1: return NRF_P1;
    3b92:	4a0c      	ldr	r2, [pc, #48]	; (3bc4 <spim_xfer+0xdc>)
    3b94:	e7f7      	b.n	3b86 <spim_xfer+0x9e>
    *p_pin = pin_number & 0x1F;
    3b96:	f003 011f 	and.w	r1, r3, #31
    return pin_number >> 5;
    3b9a:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3b9c:	2b01      	cmp	r3, #1
    3b9e:	d007      	beq.n	3bb0 <spim_xfer+0xc8>
        case 0: return NRF_P0;
    3ba0:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    3ba4:	2301      	movs	r3, #1
    3ba6:	408b      	lsls	r3, r1
    p_reg->OUTSET = set_mask;
    3ba8:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
    3bac:	4804      	ldr	r0, [pc, #16]	; (3bc0 <spim_xfer+0xd8>)
}
    3bae:	e7b0      	b.n	3b12 <spim_xfer+0x2a>
        case 1: return NRF_P1;
    3bb0:	4a04      	ldr	r2, [pc, #16]	; (3bc4 <spim_xfer+0xdc>)
    3bb2:	e7f7      	b.n	3ba4 <spim_xfer+0xbc>
    3bb4:	4802      	ldr	r0, [pc, #8]	; (3bc0 <spim_xfer+0xd8>)
    3bb6:	e7ac      	b.n	3b12 <spim_xfer+0x2a>
    3bb8:	4801      	ldr	r0, [pc, #4]	; (3bc0 <spim_xfer+0xd8>)
    3bba:	e7aa      	b.n	3b12 <spim_xfer+0x2a>
    3bbc:	0bad000a 	.word	0x0bad000a
    3bc0:	0bad0000 	.word	0x0bad0000
    3bc4:	50000300 	.word	0x50000300

00003bc8 <nrfx_spim_init>:
{
    3bc8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    3bcc:	7904      	ldrb	r4, [r0, #4]
    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    3bce:	eb04 07c4 	add.w	r7, r4, r4, lsl #3
    3bd2:	4db5      	ldr	r5, [pc, #724]	; (3ea8 <nrfx_spim_init+0x2e0>)
    3bd4:	eb05 0587 	add.w	r5, r5, r7, lsl #2
    3bd8:	7f2d      	ldrb	r5, [r5, #28]
    3bda:	2d00      	cmp	r5, #0
    3bdc:	f040 8160 	bne.w	3ea0 <nrfx_spim_init+0x2d8>
    3be0:	4626      	mov	r6, r4
    if (
    3be2:	2c00      	cmp	r4, #0
    3be4:	f040 815e 	bne.w	3ea4 <nrfx_spim_init+0x2dc>
        (!SPIM_SUPPORTED_FREQ_VALIDATE(p_instance->drv_inst_idx, p_config->frequency)) ||
    3be8:	688d      	ldr	r5, [r1, #8]
    3bea:	f1b5 6f20 	cmp.w	r5, #167772160	; 0xa000000
    3bee:	f000 8105 	beq.w	3dfc <nrfx_spim_init+0x234>
    3bf2:	f1b5 5fa0 	cmp.w	r5, #335544320	; 0x14000000
    3bf6:	f000 8101 	beq.w	3dfc <nrfx_spim_init+0x234>
    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg;
    3bfa:	6805      	ldr	r5, [r0, #0]
    p_cb->handler = handler;
    3bfc:	4faa      	ldr	r7, [pc, #680]	; (3ea8 <nrfx_spim_init+0x2e0>)
    3bfe:	eb06 0cc6 	add.w	ip, r6, r6, lsl #3
    3c02:	eb07 0e8c 	add.w	lr, r7, ip, lsl #2
    3c06:	f847 202c 	str.w	r2, [r7, ip, lsl #2]
    p_cb->p_context = p_context;
    3c0a:	f8ce 3004 	str.w	r3, [lr, #4]
    if (p_config->mode <= NRF_SPIM_MODE_1)
    3c0e:	7b0b      	ldrb	r3, [r1, #12]
    3c10:	2b01      	cmp	r3, #1
    3c12:	f240 80fd 	bls.w	3e10 <nrfx_spim_init+0x248>
        nrf_gpio_pin_set(p_config->sck_pin);
    3c16:	780b      	ldrb	r3, [r1, #0]
    *p_pin = pin_number & 0x1F;
    3c18:	f003 0c1f 	and.w	ip, r3, #31
    return pin_number >> 5;
    3c1c:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3c1e:	2b01      	cmp	r3, #1
    3c20:	f000 8106 	beq.w	3e30 <nrfx_spim_init+0x268>
        case 0: return NRF_P0;
    3c24:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    3c28:	2301      	movs	r3, #1
    3c2a:	fa03 f30c 	lsl.w	r3, r3, ip
    p_reg->OUTSET = set_mask;
    3c2e:	f8c7 3508 	str.w	r3, [r7, #1288]	; 0x508
    pin_drive = (p_config->frequency == NRF_SPIM_FREQ_32M) ? NRF_GPIO_PIN_H0H1 : NRF_GPIO_PIN_S0S1;
    3c32:	688b      	ldr	r3, [r1, #8]
    3c34:	f1b3 5fa0 	cmp.w	r3, #335544320	; 0x14000000
    3c38:	f000 80fc 	beq.w	3e34 <nrfx_spim_init+0x26c>
    nrf_gpio_cfg(p_config->sck_pin,
    3c3c:	780b      	ldrb	r3, [r1, #0]
    *p_pin = pin_number & 0x1F;
    3c3e:	f003 071f 	and.w	r7, r3, #31
    return pin_number >> 5;
    3c42:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3c44:	2b01      	cmp	r3, #1
    3c46:	f000 80f7 	beq.w	3e38 <nrfx_spim_init+0x270>
        case 0: return NRF_P0;
    3c4a:	f04f 4ea0 	mov.w	lr, #1342177280	; 0x50000000
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    3c4e:	0224      	lsls	r4, r4, #8
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    3c50:	f044 0c01 	orr.w	ip, r4, #1
    reg->PIN_CNF[pin_number] = cnf;
    3c54:	f507 73e0 	add.w	r3, r7, #448	; 0x1c0
    3c58:	f84e c023 	str.w	ip, [lr, r3, lsl #2]
    if (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED)
    3c5c:	784b      	ldrb	r3, [r1, #1]
    3c5e:	2bff      	cmp	r3, #255	; 0xff
    3c60:	f000 80f0 	beq.w	3e44 <nrfx_spim_init+0x27c>
        mosi_pin = p_config->mosi_pin;
    3c64:	461f      	mov	r7, r3
    *p_pin = pin_number & 0x1F;
    3c66:	f003 0c1f 	and.w	ip, r3, #31
    return pin_number >> 5;
    3c6a:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3c6c:	2b01      	cmp	r3, #1
    3c6e:	f000 80e6 	beq.w	3e3e <nrfx_spim_init+0x276>
        case 0: return NRF_P0;
    3c72:	f04f 4ea0 	mov.w	lr, #1342177280	; 0x50000000
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    3c76:	2301      	movs	r3, #1
    3c78:	fa03 f30c 	lsl.w	r3, r3, ip
    p_reg->OUTCLR = clr_mask;
    3c7c:	f8ce 350c 	str.w	r3, [lr, #1292]	; 0x50c
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    3c80:	f044 0303 	orr.w	r3, r4, #3
    reg->PIN_CNF[pin_number] = cnf;
    3c84:	f50c 7ce0 	add.w	ip, ip, #448	; 0x1c0
    3c88:	f84e 302c 	str.w	r3, [lr, ip, lsl #2]
    if (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED)
    3c8c:	788b      	ldrb	r3, [r1, #2]
    3c8e:	2bff      	cmp	r3, #255	; 0xff
    3c90:	f000 80de 	beq.w	3e50 <nrfx_spim_init+0x288>
        miso_pin = p_config->miso_pin;
    3c94:	469c      	mov	ip, r3
        nrf_gpio_cfg(miso_pin,
    3c96:	f891 800e 	ldrb.w	r8, [r1, #14]
    *p_pin = pin_number & 0x1F;
    3c9a:	f003 0e1f 	and.w	lr, r3, #31
    return pin_number >> 5;
    3c9e:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3ca0:	2b01      	cmp	r3, #1
    3ca2:	f000 80d2 	beq.w	3e4a <nrfx_spim_init+0x282>
        case 0: return NRF_P0;
    3ca6:	f04f 49a0 	mov.w	r9, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    3caa:	ea44 0888 	orr.w	r8, r4, r8, lsl #2
    reg->PIN_CNF[pin_number] = cnf;
    3cae:	f50e 73e0 	add.w	r3, lr, #448	; 0x1c0
    3cb2:	f849 8023 	str.w	r8, [r9, r3, lsl #2]
    p_cb->ss_pin = p_config->ss_pin;
    3cb6:	78cb      	ldrb	r3, [r1, #3]
    3cb8:	eb06 0ec6 	add.w	lr, r6, r6, lsl #3
    3cbc:	f8df 81e8 	ldr.w	r8, [pc, #488]	; 3ea8 <nrfx_spim_init+0x2e0>
    3cc0:	eb08 0e8e 	add.w	lr, r8, lr, lsl #2
    3cc4:	f88e 3020 	strb.w	r3, [lr, #32]
    if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    3cc8:	2bff      	cmp	r3, #255	; 0xff
    3cca:	d03f      	beq.n	3d4c <nrfx_spim_init+0x184>
        if (p_config->ss_active_high)
    3ccc:	f891 e004 	ldrb.w	lr, [r1, #4]
    3cd0:	f1be 0f00 	cmp.w	lr, #0
    3cd4:	f000 80c2 	beq.w	3e5c <nrfx_spim_init+0x294>
    *p_pin = pin_number & 0x1F;
    3cd8:	f003 0e1f 	and.w	lr, r3, #31
    return pin_number >> 5;
    3cdc:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3cde:	2b01      	cmp	r3, #1
    3ce0:	f000 80b9 	beq.w	3e56 <nrfx_spim_init+0x28e>
        case 0: return NRF_P0;
    3ce4:	f04f 48a0 	mov.w	r8, #1342177280	; 0x50000000
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    3ce8:	2301      	movs	r3, #1
    3cea:	fa03 f30e 	lsl.w	r3, r3, lr
    p_reg->OUTCLR = clr_mask;
    3cee:	f8c8 350c 	str.w	r3, [r8, #1292]	; 0x50c
        nrf_gpio_cfg(p_config->ss_pin,
    3cf2:	78cb      	ldrb	r3, [r1, #3]
    *p_pin = pin_number & 0x1F;
    3cf4:	f003 0e1f 	and.w	lr, r3, #31
    return pin_number >> 5;
    3cf8:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3cfa:	2b01      	cmp	r3, #1
    3cfc:	f000 80be 	beq.w	3e7c <nrfx_spim_init+0x2b4>
        case 0: return NRF_P0;
    3d00:	f04f 49a0 	mov.w	r9, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    3d04:	f044 0803 	orr.w	r8, r4, #3
    reg->PIN_CNF[pin_number] = cnf;
    3d08:	f50e 73e0 	add.w	r3, lr, #448	; 0x1c0
    3d0c:	f849 8023 	str.w	r8, [r9, r3, lsl #2]
        if (p_config->use_hw_ss)
    3d10:	7c4b      	ldrb	r3, [r1, #17]
    3d12:	b193      	cbz	r3, 3d3a <nrfx_spim_init+0x172>
            p_cb->use_hw_ss = p_config->use_hw_ss;
    3d14:	eb06 0ec6 	add.w	lr, r6, r6, lsl #3
    3d18:	f8df 818c 	ldr.w	r8, [pc, #396]	; 3ea8 <nrfx_spim_init+0x2e0>
    3d1c:	eb08 0e8e 	add.w	lr, r8, lr, lsl #2
    3d20:	f88e 301e 	strb.w	r3, [lr, #30]
                                   p_config->ss_pin,
    3d24:	f891 8003 	ldrb.w	r8, [r1, #3]
                                   (p_config->ss_active_high == true ?
    3d28:	f891 e004 	ldrb.w	lr, [r1, #4]
                                   p_config->ss_duration);
    3d2c:	7c8b      	ldrb	r3, [r1, #18]
    p_reg->PSEL.CSN = pin;
    3d2e:	f8c5 8514 	str.w	r8, [r5, #1300]	; 0x514
    p_reg->CSNPOL = polarity;
    3d32:	f8c5 e568 	str.w	lr, [r5, #1384]	; 0x568
    p_reg->IFTIMING.CSNDUR = duration;
    3d36:	f8c5 3564 	str.w	r3, [r5, #1380]	; 0x564
        p_cb->ss_active_high = p_config->ss_active_high;
    3d3a:	f891 8004 	ldrb.w	r8, [r1, #4]
    3d3e:	eb06 0ec6 	add.w	lr, r6, r6, lsl #3
    3d42:	4b59      	ldr	r3, [pc, #356]	; (3ea8 <nrfx_spim_init+0x2e0>)
    3d44:	eb03 038e 	add.w	r3, r3, lr, lsl #2
    3d48:	f883 801f 	strb.w	r8, [r3, #31]
    if (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED)
    3d4c:	7bcb      	ldrb	r3, [r1, #15]
    3d4e:	2bff      	cmp	r3, #255	; 0xff
    3d50:	d01e      	beq.n	3d90 <nrfx_spim_init+0x1c8>
    *p_pin = pin_number & 0x1F;
    3d52:	f003 081f 	and.w	r8, r3, #31
    return pin_number >> 5;
    3d56:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3d58:	2b01      	cmp	r3, #1
    3d5a:	f000 8092 	beq.w	3e82 <nrfx_spim_init+0x2ba>
        case 0: return NRF_P0;
    3d5e:	f04f 4ea0 	mov.w	lr, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    3d62:	2301      	movs	r3, #1
    3d64:	fa03 f308 	lsl.w	r3, r3, r8
    p_reg->OUTSET = set_mask;
    3d68:	f8ce 3508 	str.w	r3, [lr, #1288]	; 0x508
        nrf_gpio_cfg(p_config->dcx_pin,
    3d6c:	7bcb      	ldrb	r3, [r1, #15]
    *p_pin = pin_number & 0x1F;
    3d6e:	f003 0e1f 	and.w	lr, r3, #31
    return pin_number >> 5;
    3d72:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3d74:	2b01      	cmp	r3, #1
    3d76:	f000 8087 	beq.w	3e88 <nrfx_spim_init+0x2c0>
        case 0: return NRF_P0;
    3d7a:	f04f 48a0 	mov.w	r8, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    3d7e:	f044 0403 	orr.w	r4, r4, #3
    reg->PIN_CNF[pin_number] = cnf;
    3d82:	f50e 73e0 	add.w	r3, lr, #448	; 0x1c0
    3d86:	f848 4023 	str.w	r4, [r8, r3, lsl #2]
        nrf_spim_dcx_pin_set(p_spim, p_config->dcx_pin);
    3d8a:	7bcb      	ldrb	r3, [r1, #15]
    p_reg->PSELDCX = dcx_pin;
    3d8c:	f8c5 356c 	str.w	r3, [r5, #1388]	; 0x56c
    nrf_spim_iftiming_set(p_spim, p_config->rx_delay);
    3d90:	7c0b      	ldrb	r3, [r1, #16]
    p_reg->IFTIMING.RXDELAY = rxdelay;
    3d92:	f8c5 3560 	str.w	r3, [r5, #1376]	; 0x560
    nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin);
    3d96:	780b      	ldrb	r3, [r1, #0]
    p_reg->PSEL.SCK  = sck_pin;
    3d98:	f8c5 3508 	str.w	r3, [r5, #1288]	; 0x508
    p_reg->PSEL.MOSI = mosi_pin;
    3d9c:	f8c5 750c 	str.w	r7, [r5, #1292]	; 0x50c
    p_reg->PSEL.MISO = miso_pin;
    3da0:	f8c5 c510 	str.w	ip, [r5, #1296]	; 0x510
    nrf_spim_frequency_set(p_spim, p_config->frequency);
    3da4:	688b      	ldr	r3, [r1, #8]
    p_reg->FREQUENCY = (uint32_t)frequency;
    3da6:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
    nrf_spim_configure(p_spim, p_config->mode, p_config->bit_order);
    3daa:	7b0c      	ldrb	r4, [r1, #12]
    3dac:	7b4b      	ldrb	r3, [r1, #13]
NRF_STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type *      p_reg,
                                          nrf_spim_mode_t      spi_mode,
                                          nrf_spim_bit_order_t spi_bit_order)
{
    uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
        SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
    3dae:	3b00      	subs	r3, #0
    3db0:	bf18      	it	ne
    3db2:	2301      	movne	r3, #1
    switch (spi_mode)
    3db4:	2c02      	cmp	r4, #2
    3db6:	d06d      	beq.n	3e94 <nrfx_spim_init+0x2cc>
    3db8:	2c03      	cmp	r4, #3
    3dba:	d06e      	beq.n	3e9a <nrfx_spim_init+0x2d2>
    3dbc:	2c01      	cmp	r4, #1
    3dbe:	d066      	beq.n	3e8e <nrfx_spim_init+0x2c6>
    case NRF_SPIM_MODE_3:
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
                  (SPIM_CONFIG_CPHA_Trailing   << SPIM_CONFIG_CPHA_Pos);
        break;
    }
    p_reg->CONFIG = config;
    3dc0:	f8c5 3554 	str.w	r3, [r5, #1364]	; 0x554
    nrf_spim_orc_set(p_spim, p_config->orc);
    3dc4:	798b      	ldrb	r3, [r1, #6]
}

NRF_STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
                                        uint8_t         orc)
{
    p_reg->ORC = orc;
    3dc6:	f8c5 35c0 	str.w	r3, [r5, #1472]	; 0x5c0
    p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
    3dca:	2307      	movs	r3, #7
    3dcc:	f8c5 3500 	str.w	r3, [r5, #1280]	; 0x500
    if (p_cb->handler)
    3dd0:	b122      	cbz	r2, 3ddc <nrfx_spim_init+0x214>
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg));
    3dd2:	6800      	ldr	r0, [r0, #0]
    3dd4:	f340 3007 	sbfx	r0, r0, #12, #8
    3dd8:	f7fd f9fa 	bl	11d0 <arch_irq_enable>
    p_cb->transfer_in_progress = false;
    3ddc:	4a32      	ldr	r2, [pc, #200]	; (3ea8 <nrfx_spim_init+0x2e0>)
    3dde:	eb06 03c6 	add.w	r3, r6, r6, lsl #3
    3de2:	eb02 0383 	add.w	r3, r2, r3, lsl #2
    3de6:	2100      	movs	r1, #0
    3de8:	7759      	strb	r1, [r3, #29]
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    3dea:	eb06 03c6 	add.w	r3, r6, r6, lsl #3
    3dee:	eb02 0383 	add.w	r3, r2, r3, lsl #2
    3df2:	2201      	movs	r2, #1
    3df4:	771a      	strb	r2, [r3, #28]
    return err_code;
    3df6:	482d      	ldr	r0, [pc, #180]	; (3eac <nrfx_spim_init+0x2e4>)
}
    3df8:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        (!SPIM_SUPPORTED_FREQ_VALIDATE(p_instance->drv_inst_idx, p_config->frequency)) ||
    3dfc:	f1b5 6f20 	cmp.w	r5, #167772160	; 0xa000000
    3e00:	f43f aefb 	beq.w	3bfa <nrfx_spim_init+0x32>
    3e04:	f1b5 5fa0 	cmp.w	r5, #335544320	; 0x14000000
    3e08:	f43f aef7 	beq.w	3bfa <nrfx_spim_init+0x32>
        return err_code;
    3e0c:	4828      	ldr	r0, [pc, #160]	; (3eb0 <nrfx_spim_init+0x2e8>)
    3e0e:	e7f3      	b.n	3df8 <nrfx_spim_init+0x230>
        nrf_gpio_pin_clear(p_config->sck_pin);
    3e10:	780b      	ldrb	r3, [r1, #0]
    *p_pin = pin_number & 0x1F;
    3e12:	f003 071f 	and.w	r7, r3, #31
    return pin_number >> 5;
    3e16:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3e18:	2b01      	cmp	r3, #1
    3e1a:	d006      	beq.n	3e2a <nrfx_spim_init+0x262>
        case 0: return NRF_P0;
    3e1c:	f04f 4ca0 	mov.w	ip, #1342177280	; 0x50000000
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    3e20:	2301      	movs	r3, #1
    3e22:	40bb      	lsls	r3, r7
    p_reg->OUTCLR = clr_mask;
    3e24:	f8cc 350c 	str.w	r3, [ip, #1292]	; 0x50c
}
    3e28:	e703      	b.n	3c32 <nrfx_spim_init+0x6a>
        case 1: return NRF_P1;
    3e2a:	f8df c088 	ldr.w	ip, [pc, #136]	; 3eb4 <nrfx_spim_init+0x2ec>
    3e2e:	e7f7      	b.n	3e20 <nrfx_spim_init+0x258>
    3e30:	4f20      	ldr	r7, [pc, #128]	; (3eb4 <nrfx_spim_init+0x2ec>)
    3e32:	e6f9      	b.n	3c28 <nrfx_spim_init+0x60>
    pin_drive = (p_config->frequency == NRF_SPIM_FREQ_32M) ? NRF_GPIO_PIN_H0H1 : NRF_GPIO_PIN_S0S1;
    3e34:	2403      	movs	r4, #3
    3e36:	e701      	b.n	3c3c <nrfx_spim_init+0x74>
    3e38:	f8df e078 	ldr.w	lr, [pc, #120]	; 3eb4 <nrfx_spim_init+0x2ec>
    3e3c:	e707      	b.n	3c4e <nrfx_spim_init+0x86>
    3e3e:	f8df e074 	ldr.w	lr, [pc, #116]	; 3eb4 <nrfx_spim_init+0x2ec>
    3e42:	e718      	b.n	3c76 <nrfx_spim_init+0xae>
        mosi_pin = NRF_SPIM_PIN_NOT_CONNECTED;
    3e44:	f04f 37ff 	mov.w	r7, #4294967295
    3e48:	e720      	b.n	3c8c <nrfx_spim_init+0xc4>
    3e4a:	f8df 9068 	ldr.w	r9, [pc, #104]	; 3eb4 <nrfx_spim_init+0x2ec>
    3e4e:	e72c      	b.n	3caa <nrfx_spim_init+0xe2>
        miso_pin = NRF_SPIM_PIN_NOT_CONNECTED;
    3e50:	f04f 3cff 	mov.w	ip, #4294967295
    3e54:	e72f      	b.n	3cb6 <nrfx_spim_init+0xee>
    3e56:	f8df 805c 	ldr.w	r8, [pc, #92]	; 3eb4 <nrfx_spim_init+0x2ec>
    3e5a:	e745      	b.n	3ce8 <nrfx_spim_init+0x120>
    *p_pin = pin_number & 0x1F;
    3e5c:	f003 0e1f 	and.w	lr, r3, #31
    return pin_number >> 5;
    3e60:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3e62:	2b01      	cmp	r3, #1
    3e64:	d007      	beq.n	3e76 <nrfx_spim_init+0x2ae>
        case 0: return NRF_P0;
    3e66:	f04f 48a0 	mov.w	r8, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    3e6a:	2301      	movs	r3, #1
    3e6c:	fa03 f30e 	lsl.w	r3, r3, lr
    p_reg->OUTSET = set_mask;
    3e70:	f8c8 3508 	str.w	r3, [r8, #1288]	; 0x508
}
    3e74:	e73d      	b.n	3cf2 <nrfx_spim_init+0x12a>
        case 1: return NRF_P1;
    3e76:	f8df 803c 	ldr.w	r8, [pc, #60]	; 3eb4 <nrfx_spim_init+0x2ec>
    3e7a:	e7f6      	b.n	3e6a <nrfx_spim_init+0x2a2>
    3e7c:	f8df 9034 	ldr.w	r9, [pc, #52]	; 3eb4 <nrfx_spim_init+0x2ec>
    3e80:	e740      	b.n	3d04 <nrfx_spim_init+0x13c>
    3e82:	f8df e030 	ldr.w	lr, [pc, #48]	; 3eb4 <nrfx_spim_init+0x2ec>
    3e86:	e76c      	b.n	3d62 <nrfx_spim_init+0x19a>
    3e88:	f8df 8028 	ldr.w	r8, [pc, #40]	; 3eb4 <nrfx_spim_init+0x2ec>
    3e8c:	e777      	b.n	3d7e <nrfx_spim_init+0x1b6>
        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
    3e8e:	f043 0302 	orr.w	r3, r3, #2
        break;
    3e92:	e795      	b.n	3dc0 <nrfx_spim_init+0x1f8>
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
    3e94:	f043 0304 	orr.w	r3, r3, #4
        break;
    3e98:	e792      	b.n	3dc0 <nrfx_spim_init+0x1f8>
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
    3e9a:	f043 0306 	orr.w	r3, r3, #6
        break;
    3e9e:	e78f      	b.n	3dc0 <nrfx_spim_init+0x1f8>
        return err_code;
    3ea0:	4805      	ldr	r0, [pc, #20]	; (3eb8 <nrfx_spim_init+0x2f0>)
    3ea2:	e7a9      	b.n	3df8 <nrfx_spim_init+0x230>
        return err_code;
    3ea4:	4802      	ldr	r0, [pc, #8]	; (3eb0 <nrfx_spim_init+0x2e8>)
    3ea6:	e7a7      	b.n	3df8 <nrfx_spim_init+0x230>
    3ea8:	200005c0 	.word	0x200005c0
    3eac:	0bad0000 	.word	0x0bad0000
    3eb0:	0bad0003 	.word	0x0bad0003
    3eb4:	50000300 	.word	0x50000300
    3eb8:	0bad0005 	.word	0x0bad0005

00003ebc <nrfx_spim_uninit>:
{
    3ebc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3ebe:	4606      	mov	r6, r0
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    3ec0:	7904      	ldrb	r4, [r0, #4]
    3ec2:	4b26      	ldr	r3, [pc, #152]	; (3f5c <nrfx_spim_uninit+0xa0>)
    3ec4:	eb04 02c4 	add.w	r2, r4, r4, lsl #3
    3ec8:	eb03 0782 	add.w	r7, r3, r2, lsl #2
    NRF_SPIM_Type * p_spim = p_instance->p_reg;
    3ecc:	6805      	ldr	r5, [r0, #0]
    if (p_cb->handler)
    3ece:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    3ed2:	b143      	cbz	r3, 3ee6 <nrfx_spim_uninit+0x2a>
        NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg));
    3ed4:	f345 3007 	sbfx	r0, r5, #12, #8
    3ed8:	f7fd f98a 	bl	11f0 <arch_irq_disable>
    p_reg->INTENCLR = mask;
    3edc:	4b20      	ldr	r3, [pc, #128]	; (3f60 <nrfx_spim_uninit+0xa4>)
    3ede:	f8c5 3308 	str.w	r3, [r5, #776]	; 0x308
        if (p_cb->transfer_in_progress)
    3ee2:	7f7b      	ldrb	r3, [r7, #29]
    3ee4:	bb6b      	cbnz	r3, 3f42 <nrfx_spim_uninit+0x86>
    p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
    3ee6:	2300      	movs	r3, #0
    3ee8:	f8c5 3500 	str.w	r3, [r5, #1280]	; 0x500
    return p_reg->PSEL.SCK;
    3eec:	f8d5 0508 	ldr.w	r0, [r5, #1288]	; 0x508
    spim_pin_uninit(nrf_spim_sck_pin_get(p_spim));
    3ef0:	f7ff fdb6 	bl	3a60 <spim_pin_uninit>
    return p_reg->PSEL.MISO;
    3ef4:	f8d5 0510 	ldr.w	r0, [r5, #1296]	; 0x510
    spim_pin_uninit(nrf_spim_miso_pin_get(p_spim));
    3ef8:	f7ff fdb2 	bl	3a60 <spim_pin_uninit>
    return p_reg->PSEL.MOSI;
    3efc:	f8d5 050c 	ldr.w	r0, [r5, #1292]	; 0x50c
    spim_pin_uninit(nrf_spim_mosi_pin_get(p_spim));
    3f00:	f7ff fdae 	bl	3a60 <spim_pin_uninit>
    if (SPIM_DCX_PRESENT_VALIDATE(p_instance->drv_inst_idx))
    3f04:	7933      	ldrb	r3, [r6, #4]
    3f06:	b30b      	cbz	r3, 3f4c <nrfx_spim_uninit+0x90>
    if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    3f08:	eb04 03c4 	add.w	r3, r4, r4, lsl #3
    3f0c:	4a13      	ldr	r2, [pc, #76]	; (3f5c <nrfx_spim_uninit+0xa0>)
    3f0e:	eb02 0383 	add.w	r3, r2, r3, lsl #2
    3f12:	f893 3020 	ldrb.w	r3, [r3, #32]
    3f16:	2bff      	cmp	r3, #255	; 0xff
    3f18:	d00b      	beq.n	3f32 <nrfx_spim_uninit+0x76>
    *p_pin = pin_number & 0x1F;
    3f1a:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    3f1e:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3f20:	2b01      	cmp	r3, #1
    3f22:	d018      	beq.n	3f56 <nrfx_spim_uninit+0x9a>
        case 0: return NRF_P0;
    3f24:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    3f28:	f502 73e0 	add.w	r3, r2, #448	; 0x1c0
    3f2c:	2202      	movs	r2, #2
    3f2e:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
    3f32:	eb04 04c4 	add.w	r4, r4, r4, lsl #3
    3f36:	4b09      	ldr	r3, [pc, #36]	; (3f5c <nrfx_spim_uninit+0xa0>)
    3f38:	eb03 0484 	add.w	r4, r3, r4, lsl #2
    3f3c:	2300      	movs	r3, #0
    3f3e:	7723      	strb	r3, [r4, #28]
}
    3f40:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
            spim_abort(p_spim, p_cb);
    3f42:	4639      	mov	r1, r7
    3f44:	4628      	mov	r0, r5
    3f46:	f002 ff40 	bl	6dca <spim_abort>
    3f4a:	e7cc      	b.n	3ee6 <nrfx_spim_uninit+0x2a>
    return p_reg->PSELDCX;
    3f4c:	f8d5 056c 	ldr.w	r0, [r5, #1388]	; 0x56c
        spim_pin_uninit(nrf_spim_dcx_pin_get(p_spim));
    3f50:	f7ff fd86 	bl	3a60 <spim_pin_uninit>
    3f54:	e7d8      	b.n	3f08 <nrfx_spim_uninit+0x4c>
        case 1: return NRF_P1;
    3f56:	4903      	ldr	r1, [pc, #12]	; (3f64 <nrfx_spim_uninit+0xa8>)
    3f58:	e7e6      	b.n	3f28 <nrfx_spim_uninit+0x6c>
    3f5a:	bf00      	nop
    3f5c:	200005c0 	.word	0x200005c0
    3f60:	00080152 	.word	0x00080152
    3f64:	50000300 	.word	0x50000300

00003f68 <nrfx_spim_xfer>:

nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const *           p_instance,
                          nrfx_spim_xfer_desc_t const * p_xfer_desc,
                          uint32_t                      flags)
{
    3f68:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    3f6c:	7904      	ldrb	r4, [r0, #4]
    3f6e:	eb04 03c4 	add.w	r3, r4, r4, lsl #3
    3f72:	4f27      	ldr	r7, [pc, #156]	; (4010 <nrfx_spim_xfer+0xa8>)
    3f74:	eb07 0783 	add.w	r7, r7, r3, lsl #2
    NRFX_ASSERT(!(flags & NRFX_SPIM_FLAG_HOLD_XFER) ||
                (p_cb->ss_pin == NRFX_SPIM_PIN_NOT_USED));

    nrfx_err_t err_code = NRFX_SUCCESS;

    if (p_cb->transfer_in_progress)
    3f78:	7f7b      	ldrb	r3, [r7, #29]
    3f7a:	2b00      	cmp	r3, #0
    3f7c:	d145      	bne.n	400a <nrfx_spim_xfer+0xa2>
    3f7e:	4606      	mov	r6, r0
    3f80:	460d      	mov	r5, r1
    3f82:	4694      	mov	ip, r2
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
    else
    {
        if (p_cb->handler && !(flags & (NRFX_SPIM_FLAG_REPEATED_XFER |
    3f84:	eb04 03c4 	add.w	r3, r4, r4, lsl #3
    3f88:	4a21      	ldr	r2, [pc, #132]	; (4010 <nrfx_spim_xfer+0xa8>)
    3f8a:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
    3f8e:	b123      	cbz	r3, 3f9a <nrfx_spim_xfer+0x32>
    3f90:	f01c 0f14 	tst.w	ip, #20
    3f94:	d101      	bne.n	3f9a <nrfx_spim_xfer+0x32>
                                        NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER)))
        {
            p_cb->transfer_in_progress = true;
    3f96:	2201      	movs	r2, #1
    3f98:	777a      	strb	r2, [r7, #29]
        }
    }

    p_cb->evt.xfer_desc = *p_xfer_desc;
    3f9a:	eb04 0ec4 	add.w	lr, r4, r4, lsl #3
    3f9e:	4b1c      	ldr	r3, [pc, #112]	; (4010 <nrfx_spim_xfer+0xa8>)
    3fa0:	eb03 0e8e 	add.w	lr, r3, lr, lsl #2
    3fa4:	f10e 080c 	add.w	r8, lr, #12
    3fa8:	e895 000f 	ldmia.w	r5, {r0, r1, r2, r3}
    3fac:	e888 000f 	stmia.w	r8, {r0, r1, r2, r3}

    if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    3fb0:	f89e 3020 	ldrb.w	r3, [lr, #32]
    3fb4:	2bff      	cmp	r3, #255	; 0xff
    3fb6:	d010      	beq.n	3fda <nrfx_spim_xfer+0x72>
    {
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
        if (!p_cb->use_hw_ss)
    3fb8:	f89e 201e 	ldrb.w	r2, [lr, #30]
    3fbc:	b96a      	cbnz	r2, 3fda <nrfx_spim_xfer+0x72>
#endif
        {
            if (p_cb->ss_active_high)
    3fbe:	f89e 201f 	ldrb.w	r2, [lr, #31]
    3fc2:	b1a2      	cbz	r2, 3fee <nrfx_spim_xfer+0x86>
    *p_pin = pin_number & 0x1F;
    3fc4:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    3fc8:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3fca:	2b01      	cmp	r3, #1
    3fcc:	d00d      	beq.n	3fea <nrfx_spim_xfer+0x82>
        case 0: return NRF_P0;
    3fce:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    3fd2:	2301      	movs	r3, #1
    3fd4:	4093      	lsls	r3, r2
    p_reg->OUTSET = set_mask;
    3fd6:	f8c1 3508 	str.w	r3, [r1, #1288]	; 0x508
                nrf_gpio_pin_clear(p_cb->ss_pin);
            }
        }
    }

    return spim_xfer(p_instance->p_reg, p_cb,  p_xfer_desc, flags);
    3fda:	4663      	mov	r3, ip
    3fdc:	462a      	mov	r2, r5
    3fde:	4639      	mov	r1, r7
    3fe0:	6830      	ldr	r0, [r6, #0]
    3fe2:	f7ff fd81 	bl	3ae8 <spim_xfer>
}
    3fe6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        case 1: return NRF_P1;
    3fea:	490a      	ldr	r1, [pc, #40]	; (4014 <nrfx_spim_xfer+0xac>)
    3fec:	e7f1      	b.n	3fd2 <nrfx_spim_xfer+0x6a>
    *p_pin = pin_number & 0x1F;
    3fee:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    3ff2:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3ff4:	2b01      	cmp	r3, #1
    3ff6:	d006      	beq.n	4006 <nrfx_spim_xfer+0x9e>
        case 0: return NRF_P0;
    3ff8:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    3ffc:	2301      	movs	r3, #1
    3ffe:	4093      	lsls	r3, r2
    p_reg->OUTCLR = clr_mask;
    4000:	f8c1 350c 	str.w	r3, [r1, #1292]	; 0x50c
}
    4004:	e7e9      	b.n	3fda <nrfx_spim_xfer+0x72>
        case 1: return NRF_P1;
    4006:	4903      	ldr	r1, [pc, #12]	; (4014 <nrfx_spim_xfer+0xac>)
    4008:	e7f8      	b.n	3ffc <nrfx_spim_xfer+0x94>
        return err_code;
    400a:	4803      	ldr	r0, [pc, #12]	; (4018 <nrfx_spim_xfer+0xb0>)
    400c:	e7eb      	b.n	3fe6 <nrfx_spim_xfer+0x7e>
    400e:	bf00      	nop
    4010:	200005c0 	.word	0x200005c0
    4014:	50000300 	.word	0x50000300
    4018:	0bad000b 	.word	0x0bad000b

0000401c <nrfx_spim_3_irq_handler>:
}
#endif

#if NRFX_CHECK(NRFX_SPIM3_ENABLED)
void nrfx_spim_3_irq_handler(void)
{
    401c:	b508      	push	{r3, lr}
    irq_handler(NRF_SPIM3, &m_cb[NRFX_SPIM3_INST_IDX]);
    401e:	4902      	ldr	r1, [pc, #8]	; (4028 <nrfx_spim_3_irq_handler+0xc>)
    4020:	4802      	ldr	r0, [pc, #8]	; (402c <nrfx_spim_3_irq_handler+0x10>)
    4022:	f002 fec3 	bl	6dac <irq_handler>
}
    4026:	bd08      	pop	{r3, pc}
    4028:	200005c0 	.word	0x200005c0
    402c:	4002f000 	.word	0x4002f000

00004030 <_DoInit>:
                      _DoInit();                                                                     \
                    }                                                                                \
                  } while (0);                                                                       \
                }

static void _DoInit(void) {
    4030:	b510      	push	{r4, lr}
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    4032:	4c14      	ldr	r4, [pc, #80]	; (4084 <_DoInit+0x54>)
    4034:	2303      	movs	r3, #3
    4036:	6123      	str	r3, [r4, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    4038:	6163      	str	r3, [r4, #20]
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    403a:	4a13      	ldr	r2, [pc, #76]	; (4088 <_DoInit+0x58>)
    403c:	61a2      	str	r2, [r4, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    403e:	4b13      	ldr	r3, [pc, #76]	; (408c <_DoInit+0x5c>)
    4040:	61e3      	str	r3, [r4, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    4042:	f44f 6380 	mov.w	r3, #1024	; 0x400
    4046:	6223      	str	r3, [r4, #32]
  p->aUp[0].RdOff         = 0u;
    4048:	2300      	movs	r3, #0
    404a:	62a3      	str	r3, [r4, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    404c:	6263      	str	r3, [r4, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    404e:	62e3      	str	r3, [r4, #44]	; 0x2c
  //
  // Initialize down buffer 0
  //
  p->aDown[0].sName         = "Terminal";
    4050:	6622      	str	r2, [r4, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    4052:	4a0f      	ldr	r2, [pc, #60]	; (4090 <_DoInit+0x60>)
    4054:	6662      	str	r2, [r4, #100]	; 0x64
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    4056:	2210      	movs	r2, #16
    4058:	66a2      	str	r2, [r4, #104]	; 0x68
  p->aDown[0].RdOff         = 0u;
    405a:	6723      	str	r3, [r4, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    405c:	66e3      	str	r3, [r4, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    405e:	6763      	str	r3, [r4, #116]	; 0x74
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    4060:	490c      	ldr	r1, [pc, #48]	; (4094 <_DoInit+0x64>)
    4062:	1de0      	adds	r0, r4, #7
    4064:	f001 ff69 	bl	5f3a <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    4068:	f3bf 8f5f 	dmb	sy
  STRCPY((char*)&p->acID[0], "SEGGER");
    406c:	490a      	ldr	r1, [pc, #40]	; (4098 <_DoInit+0x68>)
    406e:	4620      	mov	r0, r4
    4070:	f001 ff63 	bl	5f3a <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    4074:	f3bf 8f5f 	dmb	sy
  p->acID[6] = ' ';
    4078:	2320      	movs	r3, #32
    407a:	71a3      	strb	r3, [r4, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    407c:	f3bf 8f5f 	dmb	sy
}
    4080:	bd10      	pop	{r4, pc}
    4082:	bf00      	nop
    4084:	200005e4 	.word	0x200005e4
    4088:	00007938 	.word	0x00007938
    408c:	2000069c 	.word	0x2000069c
    4090:	2000068c 	.word	0x2000068c
    4094:	00007944 	.word	0x00007944
    4098:	00007948 	.word	0x00007948

0000409c <z_device_state_init>:
 * The state object is always zero-initialized, but this may not be
 * sufficient.
 */
void z_device_state_init(void)
{
	const struct device *dev = __device_start;
    409c:	4b03      	ldr	r3, [pc, #12]	; (40ac <z_device_state_init+0x10>)

	while (dev < __device_end) {
    409e:	4a04      	ldr	r2, [pc, #16]	; (40b0 <z_device_state_init+0x14>)
    40a0:	4293      	cmp	r3, r2
    40a2:	d201      	bcs.n	40a8 <z_device_state_init+0xc>
		z_object_init(dev);
		++dev;
    40a4:	3318      	adds	r3, #24
    40a6:	e7fa      	b.n	409e <z_device_state_init+0x2>
	}
}
    40a8:	4770      	bx	lr
    40aa:	bf00      	nop
    40ac:	00007478 	.word	0x00007478
    40b0:	00007550 	.word	0x00007550

000040b4 <z_sys_init_run_level>:
 * off and the next one begins.
 *
 * @param level init level to run.
 */
void z_sys_init_run_level(int32_t level)
{
    40b4:	b570      	push	{r4, r5, r6, lr}
    40b6:	4606      	mov	r6, r0
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    40b8:	4b11      	ldr	r3, [pc, #68]	; (4100 <z_sys_init_run_level+0x4c>)
    40ba:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    40be:	e009      	b.n	40d4 <z_sys_init_run_level+0x20>
			/* Mark device initialized.  If initialization
			 * failed, record the error condition.
			 */
			if (rc != 0) {
				if (rc < 0) {
					rc = -rc;
    40c0:	4240      	negs	r0, r0
    40c2:	e017      	b.n	40f4 <z_sys_init_run_level+0x40>
				}
				if (rc > UINT8_MAX) {
					rc = UINT8_MAX;
				}
				dev->state->init_res = rc;
    40c4:	68eb      	ldr	r3, [r5, #12]
    40c6:	7018      	strb	r0, [r3, #0]
			}
			dev->state->initialized = true;
    40c8:	68ea      	ldr	r2, [r5, #12]
    40ca:	7853      	ldrb	r3, [r2, #1]
    40cc:	f043 0301 	orr.w	r3, r3, #1
    40d0:	7053      	strb	r3, [r2, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    40d2:	3408      	adds	r4, #8
    40d4:	1c73      	adds	r3, r6, #1
    40d6:	4a0a      	ldr	r2, [pc, #40]	; (4100 <z_sys_init_run_level+0x4c>)
    40d8:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
    40dc:	42a3      	cmp	r3, r4
    40de:	d90d      	bls.n	40fc <z_sys_init_run_level+0x48>
		const struct device *dev = entry->dev;
    40e0:	6865      	ldr	r5, [r4, #4]
		int rc = entry->init(dev);
    40e2:	6823      	ldr	r3, [r4, #0]
    40e4:	4628      	mov	r0, r5
    40e6:	4798      	blx	r3
		if (dev != NULL) {
    40e8:	2d00      	cmp	r5, #0
    40ea:	d0f2      	beq.n	40d2 <z_sys_init_run_level+0x1e>
			if (rc != 0) {
    40ec:	2800      	cmp	r0, #0
    40ee:	d0eb      	beq.n	40c8 <z_sys_init_run_level+0x14>
				if (rc < 0) {
    40f0:	2800      	cmp	r0, #0
    40f2:	dbe5      	blt.n	40c0 <z_sys_init_run_level+0xc>
				if (rc > UINT8_MAX) {
    40f4:	28ff      	cmp	r0, #255	; 0xff
    40f6:	dde5      	ble.n	40c4 <z_sys_init_run_level+0x10>
					rc = UINT8_MAX;
    40f8:	20ff      	movs	r0, #255	; 0xff
    40fa:	e7e3      	b.n	40c4 <z_sys_init_run_level+0x10>
		}
	}
}
    40fc:	bd70      	pop	{r4, r5, r6, pc}
    40fe:	bf00      	nop
    4100:	00007950 	.word	0x00007950

00004104 <z_impl_device_get_binding>:

const struct device *z_impl_device_get_binding(const char *name)
{
    4104:	b538      	push	{r3, r4, r5, lr}
	const struct device *dev;

	/* A null string identifies no device.  So does an empty
	 * string.
	 */
	if ((name == NULL) || (name[0] == '\0')) {
    4106:	4605      	mov	r5, r0
    4108:	b328      	cbz	r0, 4156 <z_impl_device_get_binding+0x52>
    410a:	7803      	ldrb	r3, [r0, #0]
    410c:	b32b      	cbz	r3, 415a <z_impl_device_get_binding+0x56>
	/* Split the search into two loops: in the common scenario, where
	 * device names are stored in ROM (and are referenced by the user
	 * with CONFIG_* macros), only cheap pointer comparisons will be
	 * performed. Reserve string comparisons for a fallback.
	 */
	for (dev = __device_start; dev != __device_end; dev++) {
    410e:	4c14      	ldr	r4, [pc, #80]	; (4160 <z_impl_device_get_binding+0x5c>)
    4110:	e000      	b.n	4114 <z_impl_device_get_binding+0x10>
    4112:	3418      	adds	r4, #24
    4114:	4b13      	ldr	r3, [pc, #76]	; (4164 <z_impl_device_get_binding+0x60>)
    4116:	429c      	cmp	r4, r3
    4118:	d008      	beq.n	412c <z_impl_device_get_binding+0x28>
		if (z_device_ready(dev) && (dev->name == name)) {
    411a:	4620      	mov	r0, r4
    411c:	f002 fe6f 	bl	6dfe <z_device_ready>
    4120:	2800      	cmp	r0, #0
    4122:	d0f6      	beq.n	4112 <z_impl_device_get_binding+0xe>
    4124:	6823      	ldr	r3, [r4, #0]
    4126:	42ab      	cmp	r3, r5
    4128:	d1f3      	bne.n	4112 <z_impl_device_get_binding+0xe>
    412a:	e012      	b.n	4152 <z_impl_device_get_binding+0x4e>
			return dev;
		}
	}

	for (dev = __device_start; dev != __device_end; dev++) {
    412c:	4c0c      	ldr	r4, [pc, #48]	; (4160 <z_impl_device_get_binding+0x5c>)
    412e:	e000      	b.n	4132 <z_impl_device_get_binding+0x2e>
    4130:	3418      	adds	r4, #24
    4132:	4b0c      	ldr	r3, [pc, #48]	; (4164 <z_impl_device_get_binding+0x60>)
    4134:	429c      	cmp	r4, r3
    4136:	d00b      	beq.n	4150 <z_impl_device_get_binding+0x4c>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    4138:	4620      	mov	r0, r4
    413a:	f002 fe60 	bl	6dfe <z_device_ready>
    413e:	2800      	cmp	r0, #0
    4140:	d0f6      	beq.n	4130 <z_impl_device_get_binding+0x2c>
    4142:	6821      	ldr	r1, [r4, #0]
    4144:	4628      	mov	r0, r5
    4146:	f001 ff2d 	bl	5fa4 <strcmp>
    414a:	2800      	cmp	r0, #0
    414c:	d1f0      	bne.n	4130 <z_impl_device_get_binding+0x2c>
    414e:	e000      	b.n	4152 <z_impl_device_get_binding+0x4e>
			return dev;
		}
	}

	return NULL;
    4150:	2400      	movs	r4, #0
}
    4152:	4620      	mov	r0, r4
    4154:	bd38      	pop	{r3, r4, r5, pc}
		return NULL;
    4156:	4604      	mov	r4, r0
    4158:	e7fb      	b.n	4152 <z_impl_device_get_binding+0x4e>
    415a:	2400      	movs	r4, #0
    415c:	e7f9      	b.n	4152 <z_impl_device_get_binding+0x4e>
    415e:	bf00      	nop
    4160:	00007478 	.word	0x00007478
    4164:	00007550 	.word	0x00007550

00004168 <init_idle_thread>:
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */

#if defined(CONFIG_MULTITHREADING)
__boot_func
static void init_idle_thread(int i)
{
    4168:	b5f0      	push	{r4, r5, r6, r7, lr}
    416a:	b089      	sub	sp, #36	; 0x24
    416c:	4604      	mov	r4, r0
	struct k_thread *thread = &z_idle_threads[i];
    416e:	4b15      	ldr	r3, [pc, #84]	; (41c4 <init_idle_thread+0x5c>)
    4170:	25b8      	movs	r5, #184	; 0xb8
    4172:	fb05 3500 	mla	r5, r5, r0, r3
	k_thread_stack_t *stack = z_idle_stacks[i];
    4176:	4b14      	ldr	r3, [pc, #80]	; (41c8 <init_idle_thread+0x60>)
    4178:	f44f 76b0 	mov.w	r6, #352	; 0x160
    417c:	fb06 3600 	mla	r6, r6, r0, r3

#ifdef CONFIG_THREAD_NAME
	char tname[8];

	snprintk(tname, 8, "idle %02d", i);
    4180:	af06      	add	r7, sp, #24
    4182:	4603      	mov	r3, r0
    4184:	4a11      	ldr	r2, [pc, #68]	; (41cc <init_idle_thread+0x64>)
    4186:	2108      	movs	r1, #8
    4188:	4638      	mov	r0, r7
    418a:	f001 fc25 	bl	59d8 <snprintk>
#else
	char *tname = NULL;
#endif /* CONFIG_THREAD_NAME */

	z_setup_new_thread(thread, stack,
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    418e:	eb04 0444 	add.w	r4, r4, r4, lsl #1
    4192:	480f      	ldr	r0, [pc, #60]	; (41d0 <init_idle_thread+0x68>)
    4194:	eb00 04c4 	add.w	r4, r0, r4, lsl #3
	z_setup_new_thread(thread, stack,
    4198:	9705      	str	r7, [sp, #20]
    419a:	2301      	movs	r3, #1
    419c:	9304      	str	r3, [sp, #16]
    419e:	230f      	movs	r3, #15
    41a0:	9303      	str	r3, [sp, #12]
    41a2:	2300      	movs	r3, #0
    41a4:	9302      	str	r3, [sp, #8]
    41a6:	9301      	str	r3, [sp, #4]
    41a8:	9400      	str	r4, [sp, #0]
    41aa:	4b0a      	ldr	r3, [pc, #40]	; (41d4 <init_idle_thread+0x6c>)
    41ac:	f44f 72a0 	mov.w	r2, #320	; 0x140
    41b0:	4631      	mov	r1, r6
    41b2:	4628      	mov	r0, r5
    41b4:	f000 f910 	bl	43d8 <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    41b8:	7b6b      	ldrb	r3, [r5, #13]
    41ba:	f023 0304 	bic.w	r3, r3, #4
    41be:	736b      	strb	r3, [r5, #13]
	z_mark_thread_as_started(thread);

#ifdef CONFIG_SMP
	thread->base.is_idle = 1U;
#endif
}
    41c0:	b009      	add	sp, #36	; 0x24
    41c2:	bdf0      	pop	{r4, r5, r6, r7, pc}
    41c4:	200001e8 	.word	0x200001e8
    41c8:	20000f20 	.word	0x20000f20
    41cc:	00007968 	.word	0x00007968
    41d0:	20000a9c 	.word	0x20000a9c
    41d4:	00006f03 	.word	0x00006f03

000041d8 <prepare_multithreading>:
 *
 * @return initial stack pointer for the main thread
 */
__boot_func
static char *prepare_multithreading(void)
{
    41d8:	b570      	push	{r4, r5, r6, lr}
    41da:	b086      	sub	sp, #24
	char *stack_ptr;

	/* _kernel.ready_q is all zeroes */
	z_sched_init();
    41dc:	f000 fc9e 	bl	4b1c <z_sched_init>
	 * - the main thread will be the one to run first
	 * - no other thread is initialized yet and thus their priority fields
	 *   contain garbage, which would prevent the cache loading algorithm
	 *   to work as intended
	 */
	_kernel.ready_q.cache = &z_main_thread;
    41e0:	4d1b      	ldr	r5, [pc, #108]	; (4250 <prepare_multithreading+0x78>)
    41e2:	4b1c      	ldr	r3, [pc, #112]	; (4254 <prepare_multithreading+0x7c>)
    41e4:	61dd      	str	r5, [r3, #28]
#endif
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    41e6:	4b1c      	ldr	r3, [pc, #112]	; (4258 <prepare_multithreading+0x80>)
    41e8:	9305      	str	r3, [sp, #20]
    41ea:	2301      	movs	r3, #1
    41ec:	9304      	str	r3, [sp, #16]
    41ee:	2400      	movs	r4, #0
    41f0:	9403      	str	r4, [sp, #12]
    41f2:	9402      	str	r4, [sp, #8]
    41f4:	9401      	str	r4, [sp, #4]
    41f6:	9400      	str	r4, [sp, #0]
    41f8:	4b18      	ldr	r3, [pc, #96]	; (425c <prepare_multithreading+0x84>)
    41fa:	f44f 6280 	mov.w	r2, #1024	; 0x400
    41fe:	4918      	ldr	r1, [pc, #96]	; (4260 <prepare_multithreading+0x88>)
    4200:	4628      	mov	r0, r5
    4202:	f000 f8e9 	bl	43d8 <z_setup_new_thread>
    4206:	4606      	mov	r6, r0
    4208:	7b6b      	ldrb	r3, [r5, #13]
    420a:	f023 0304 	bic.w	r3, r3, #4
    420e:	736b      	strb	r3, [r5, #13]
				       CONFIG_MAIN_STACK_SIZE, bg_thread_main,
				       NULL, NULL, NULL,
				       CONFIG_MAIN_THREAD_PRIORITY,
				       K_ESSENTIAL, "main");
	z_mark_thread_as_started(&z_main_thread);
	z_ready_thread(&z_main_thread);
    4210:	4628      	mov	r0, r5
    4212:	f002 fed7 	bl	6fc4 <z_ready_thread>

	for (int i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
    4216:	2c00      	cmp	r4, #0
    4218:	dd02      	ble.n	4220 <prepare_multithreading+0x48>
			(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[i]) +
			 K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[i]));
	}

	return stack_ptr;
}
    421a:	4630      	mov	r0, r6
    421c:	b006      	add	sp, #24
    421e:	bd70      	pop	{r4, r5, r6, pc}
		init_idle_thread(i);
    4220:	4620      	mov	r0, r4
    4222:	f7ff ffa1 	bl	4168 <init_idle_thread>
		_kernel.cpus[i].idle_thread = &z_idle_threads[i];
    4226:	4b0f      	ldr	r3, [pc, #60]	; (4264 <prepare_multithreading+0x8c>)
    4228:	22b8      	movs	r2, #184	; 0xb8
    422a:	fb02 3204 	mla	r2, r2, r4, r3
    422e:	eb04 0144 	add.w	r1, r4, r4, lsl #1
    4232:	4b08      	ldr	r3, [pc, #32]	; (4254 <prepare_multithreading+0x7c>)
    4234:	eb03 03c1 	add.w	r3, r3, r1, lsl #3
    4238:	60da      	str	r2, [r3, #12]
		_kernel.cpus[i].id = i;
    423a:	751c      	strb	r4, [r3, #20]
			(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[i]) +
    423c:	eb04 1184 	add.w	r1, r4, r4, lsl #6
    4240:	4a09      	ldr	r2, [pc, #36]	; (4268 <prepare_multithreading+0x90>)
    4242:	eb02 1241 	add.w	r2, r2, r1, lsl #5
    4246:	f502 6202 	add.w	r2, r2, #2080	; 0x820
		_kernel.cpus[i].irq_stack =
    424a:	605a      	str	r2, [r3, #4]
	for (int i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
    424c:	3401      	adds	r4, #1
    424e:	e7e2      	b.n	4216 <prepare_multithreading+0x3e>
    4250:	200002a0 	.word	0x200002a0
    4254:	20000a9c 	.word	0x20000a9c
    4258:	00007974 	.word	0x00007974
    425c:	0000426d 	.word	0x0000426d
    4260:	20000b00 	.word	0x20000b00
    4264:	200001e8 	.word	0x200001e8
    4268:	20001080 	.word	0x20001080

0000426c <bg_thread_main>:
{
    426c:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    426e:	4b0a      	ldr	r3, [pc, #40]	; (4298 <bg_thread_main+0x2c>)
    4270:	2201      	movs	r2, #1
    4272:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    4274:	2002      	movs	r0, #2
    4276:	f7ff ff1d 	bl	40b4 <z_sys_init_run_level>
	boot_banner();
    427a:	f001 f9c7 	bl	560c <boot_banner>
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    427e:	2003      	movs	r0, #3
    4280:	f7ff ff18 	bl	40b4 <z_sys_init_run_level>
	z_init_static_threads();
    4284:	f000 f90c 	bl	44a0 <z_init_static_threads>
	main();
    4288:	f7fc f8b4 	bl	3f4 <main>
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    428c:	4a03      	ldr	r2, [pc, #12]	; (429c <bg_thread_main+0x30>)
    428e:	7b13      	ldrb	r3, [r2, #12]
    4290:	f023 0301 	bic.w	r3, r3, #1
    4294:	7313      	strb	r3, [r2, #12]
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    4296:	bd08      	pop	{r3, pc}
    4298:	20000ae2 	.word	0x20000ae2
    429c:	200002a0 	.word	0x200002a0

000042a0 <switch_to_main_thread>:

__boot_func
static FUNC_NORETURN void switch_to_main_thread(char *stack_ptr)
{
    42a0:	b508      	push	{r3, lr}
    42a2:	4601      	mov	r1, r0
#ifdef CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    42a4:	4a01      	ldr	r2, [pc, #4]	; (42ac <switch_to_main_thread+0xc>)
    42a6:	4802      	ldr	r0, [pc, #8]	; (42b0 <switch_to_main_thread+0x10>)
    42a8:	f7fd f8a2 	bl	13f0 <arch_switch_to_main_thread>
	 * current fake thread is not on a wait queue or ready queue, so it
	 * will never be rescheduled in.
	 */
	z_swap_unlocked();
#endif
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    42ac:	0000426d 	.word	0x0000426d
    42b0:	200002a0 	.word	0x200002a0

000042b4 <z_bss_zero>:
{
    42b4:	b508      	push	{r3, lr}
	(void)memset(__bss_start, 0, __bss_end - __bss_start);
    42b6:	4803      	ldr	r0, [pc, #12]	; (42c4 <z_bss_zero+0x10>)
    42b8:	4a03      	ldr	r2, [pc, #12]	; (42c8 <z_bss_zero+0x14>)
    42ba:	1a12      	subs	r2, r2, r0
    42bc:	2100      	movs	r1, #0
    42be:	f001 fe9f 	bl	6000 <memset>
}
    42c2:	bd08      	pop	{r3, pc}
    42c4:	200001c8 	.word	0x200001c8
    42c8:	20000ae4 	.word	0x20000ae4

000042cc <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    42cc:	b500      	push	{lr}
    42ce:	b0af      	sub	sp, #188	; 0xbc
 *
 * @return N/A
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    42d0:	4b1c      	ldr	r3, [pc, #112]	; (4344 <z_cstart+0x78>)
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    42d2:	f383 8808 	msr	MSP, r3
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    42d6:	4c1c      	ldr	r4, [pc, #112]	; (4348 <z_cstart+0x7c>)
    42d8:	6963      	ldr	r3, [r4, #20]
    42da:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    42de:	6163      	str	r3, [r4, #20]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    42e0:	23e0      	movs	r3, #224	; 0xe0
    42e2:	f884 3022 	strb.w	r3, [r4, #34]	; 0x22
    42e6:	2500      	movs	r5, #0
    42e8:	77e5      	strb	r5, [r4, #31]
    42ea:	7625      	strb	r5, [r4, #24]
    42ec:	7665      	strb	r5, [r4, #25]
    42ee:	76a5      	strb	r5, [r4, #26]
    42f0:	f884 5020 	strb.w	r5, [r4, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    42f4:	6a63      	ldr	r3, [r4, #36]	; 0x24
    42f6:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    42fa:	6263      	str	r3, [r4, #36]	; 0x24
    42fc:	f884 5023 	strb.w	r5, [r4, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    4300:	f7fd f9c8 	bl	1694 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    4304:	f7fc ff46 	bl	1194 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    4308:	f04f 33ff 	mov.w	r3, #4294967295
    430c:	62a3      	str	r3, [r4, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    430e:	62e3      	str	r3, [r4, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    4310:	f7fd faca 	bl	18a8 <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    4314:	f7fd fa64 	bl	17e0 <z_arm_configure_static_mpu_regions>
 *
 * The memory of the dummy thread can be completely uninitialized.
 */
static inline void z_dummy_thread_init(struct k_thread *dummy_thread)
{
	dummy_thread->base.thread_state = _THREAD_DUMMY;
    4318:	2401      	movs	r4, #1
    431a:	f88d 400d 	strb.w	r4, [sp, #13]
#ifdef CONFIG_SCHED_CPU_MASK
	dummy_thread->base.cpu_mask = -1;
#endif
	dummy_thread->base.user_options = K_ESSENTIAL;
    431e:	f88d 400c 	strb.w	r4, [sp, #12]
#ifdef CONFIG_THREAD_STACK_INFO
	dummy_thread->stack_info.start = 0U;
    4322:	9527      	str	r5, [sp, #156]	; 0x9c
	dummy_thread->stack_info.size = 0U;
    4324:	9528      	str	r5, [sp, #160]	; 0xa0
#endif
#ifdef CONFIG_USERSPACE
	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
#endif

	_current_cpu->current = dummy_thread;
    4326:	4b09      	ldr	r3, [pc, #36]	; (434c <z_cstart+0x80>)
    4328:	f8c3 d008 	str.w	sp, [r3, #8]
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    432c:	f7ff feb6 	bl	409c <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    4330:	4628      	mov	r0, r5
    4332:	f7ff febf 	bl	40b4 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    4336:	4620      	mov	r0, r4
    4338:	f7ff febc 	bl	40b4 <z_sys_init_run_level>
	timing_init();
	timing_start();
#endif

#ifdef CONFIG_MULTITHREADING
	switch_to_main_thread(prepare_multithreading());
    433c:	f7ff ff4c 	bl	41d8 <prepare_multithreading>
    4340:	f7ff ffae 	bl	42a0 <switch_to_main_thread>
    4344:	200018a0 	.word	0x200018a0
    4348:	e000ed00 	.word	0xe000ed00
    434c:	20000a9c 	.word	0x20000a9c

00004350 <z_thread_monitor_exit>:
    4350:	f04f 0320 	mov.w	r3, #32
    4354:	f3ef 8111 	mrs	r1, BASEPRI
    4358:	f383 8812 	msr	BASEPRI_MAX, r3
    435c:	f3bf 8f6f 	isb	sy
 */
void z_thread_monitor_exit(struct k_thread *thread)
{
	k_spinlock_key_t key = k_spin_lock(&z_thread_monitor_lock);

	if (thread == _kernel.threads) {
    4360:	4b0a      	ldr	r3, [pc, #40]	; (438c <z_thread_monitor_exit+0x3c>)
    4362:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    4364:	4283      	cmp	r3, r0
    4366:	d104      	bne.n	4372 <z_thread_monitor_exit+0x22>
		_kernel.threads = _kernel.threads->next_thread;
    4368:	6f5a      	ldr	r2, [r3, #116]	; 0x74
    436a:	4b08      	ldr	r3, [pc, #32]	; (438c <z_thread_monitor_exit+0x3c>)
    436c:	629a      	str	r2, [r3, #40]	; 0x28
    436e:	e007      	b.n	4380 <z_thread_monitor_exit+0x30>
		struct k_thread *prev_thread;

		prev_thread = _kernel.threads;
		while ((prev_thread != NULL) &&
			(thread != prev_thread->next_thread)) {
			prev_thread = prev_thread->next_thread;
    4370:	4613      	mov	r3, r2
		while ((prev_thread != NULL) &&
    4372:	b113      	cbz	r3, 437a <z_thread_monitor_exit+0x2a>
			(thread != prev_thread->next_thread)) {
    4374:	6f5a      	ldr	r2, [r3, #116]	; 0x74
		while ((prev_thread != NULL) &&
    4376:	4282      	cmp	r2, r0
    4378:	d1fa      	bne.n	4370 <z_thread_monitor_exit+0x20>
		}
		if (prev_thread != NULL) {
    437a:	b10b      	cbz	r3, 4380 <z_thread_monitor_exit+0x30>
			prev_thread->next_thread = thread->next_thread;
    437c:	6f42      	ldr	r2, [r0, #116]	; 0x74
    437e:	675a      	str	r2, [r3, #116]	; 0x74
	__asm__ volatile(
    4380:	f381 8811 	msr	BASEPRI, r1
    4384:	f3bf 8f6f 	isb	sy
		}
	}

	k_spin_unlock(&z_thread_monitor_lock, key);
}
    4388:	4770      	bx	lr
    438a:	bf00      	nop
    438c:	20000a9c 	.word	0x20000a9c

00004390 <z_impl_k_thread_name_set>:
#endif

int z_impl_k_thread_name_set(struct k_thread *thread, const char *value)
{
    4390:	b510      	push	{r4, lr}
#ifdef CONFIG_THREAD_NAME
	if (thread == NULL) {
    4392:	4604      	mov	r4, r0
    4394:	b140      	cbz	r0, 43a8 <z_impl_k_thread_name_set+0x18>
		thread = _current;
	}

	strncpy(thread->name, value, CONFIG_THREAD_MAX_NAME_LEN);
    4396:	2220      	movs	r2, #32
    4398:	f104 0078 	add.w	r0, r4, #120	; 0x78
    439c:	f001 fdd6 	bl	5f4c <strncpy>
	thread->name[CONFIG_THREAD_MAX_NAME_LEN - 1] = '\0';
    43a0:	2000      	movs	r0, #0
    43a2:	f884 0097 	strb.w	r0, [r4, #151]	; 0x97

	SYS_PORT_TRACING_OBJ_FUNC(k_thread, name_set, thread, -ENOSYS);

	return -ENOSYS;
#endif /* CONFIG_THREAD_NAME */
}
    43a6:	bd10      	pop	{r4, pc}
		thread = _current;
    43a8:	4b01      	ldr	r3, [pc, #4]	; (43b0 <z_impl_k_thread_name_set+0x20>)
    43aa:	689c      	ldr	r4, [r3, #8]
    43ac:	e7f3      	b.n	4396 <z_impl_k_thread_name_set+0x6>
    43ae:	bf00      	nop
    43b0:	20000a9c 	.word	0x20000a9c

000043b4 <schedule_new_thread>:
#endif
#endif

#ifdef CONFIG_MULTITHREADING
static void schedule_new_thread(struct k_thread *thread, k_timeout_t delay)
{
    43b4:	b538      	push	{r3, r4, r5, lr}
    43b6:	4614      	mov	r4, r2
    43b8:	461d      	mov	r5, r3
#ifdef CONFIG_SYS_CLOCK_EXISTS
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    43ba:	ea54 0305 	orrs.w	r3, r4, r5
    43be:	d102      	bne.n	43c6 <schedule_new_thread+0x12>
	z_impl_k_thread_start(thread);
    43c0:	f002 fd68 	bl	6e94 <z_impl_k_thread_start>
	}
#else
	ARG_UNUSED(delay);
	k_thread_start(thread);
#endif
}
    43c4:	bd38      	pop	{r3, r4, r5, pc}

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    43c6:	462b      	mov	r3, r5
    43c8:	4902      	ldr	r1, [pc, #8]	; (43d4 <schedule_new_thread+0x20>)
    43ca:	3018      	adds	r0, #24
    43cc:	f000 fd26 	bl	4e1c <z_add_timeout>
    43d0:	e7f8      	b.n	43c4 <schedule_new_thread+0x10>
    43d2:	bf00      	nop
    43d4:	00006ffd 	.word	0x00006ffd

000043d8 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    43d8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    43dc:	b085      	sub	sp, #20
    43de:	4604      	mov	r4, r0
    43e0:	460f      	mov	r7, r1
    43e2:	4615      	mov	r5, r2
    43e4:	461e      	mov	r6, r3
    43e6:	f8dd a038 	ldr.w	sl, [sp, #56]	; 0x38
    43ea:	f8dd 903c 	ldr.w	r9, [sp, #60]	; 0x3c
    43ee:	f8dd 8040 	ldr.w	r8, [sp, #64]	; 0x40
    43f2:	f8dd b04c 	ldr.w	fp, [sp, #76]	; 0x4c
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    43f6:	f100 0358 	add.w	r3, r0, #88	; 0x58
 * @return N/A
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
    43fa:	6583      	str	r3, [r0, #88]	; 0x58
	list->tail = (sys_dnode_t *)list;
    43fc:	65c3      	str	r3, [r0, #92]	; 0x5c
	k_object_access_grant(new_thread, new_thread);
#endif
	z_waitq_init(&new_thread->join_queue);

	/* Initialize various struct k_thread members */
	z_init_thread_base(&new_thread->base, prio, _THREAD_PRESTART, options);
    43fe:	9b12      	ldr	r3, [sp, #72]	; 0x48
    4400:	2204      	movs	r2, #4
    4402:	9911      	ldr	r1, [sp, #68]	; 0x44
    4404:	f002 fd4a 	bl	6e9c <z_init_thread_base>
	stack_ptr = setup_thread_stack(new_thread, stack, stack_size);
    4408:	462a      	mov	r2, r5
    440a:	4639      	mov	r1, r7
    440c:	4620      	mov	r0, r4
    440e:	f002 fd29 	bl	6e64 <setup_thread_stack>
    4412:	4605      	mov	r5, r0
	 */
	__ASSERT_NO_MSG(arch_mem_coherent(new_thread));
	__ASSERT_NO_MSG(!arch_mem_coherent(stack));
#endif

	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    4414:	f8cd 8008 	str.w	r8, [sp, #8]
    4418:	f8cd 9004 	str.w	r9, [sp, #4]
    441c:	f8cd a000 	str.w	sl, [sp]
    4420:	4633      	mov	r3, r6
    4422:	4602      	mov	r2, r0
    4424:	4639      	mov	r1, r7
    4426:	4620      	mov	r0, r4
    4428:	f7fc ff92 	bl	1350 <arch_new_thread>

	/* static threads overwrite it afterwards with real value */
	new_thread->init_data = NULL;
    442c:	2300      	movs	r3, #0
    442e:	6563      	str	r3, [r4, #84]	; 0x54
#ifdef CONFIG_THREAD_CUSTOM_DATA
	/* Initialize custom data field (value is opaque to kernel) */
	new_thread->custom_data = NULL;
#endif
#ifdef CONFIG_THREAD_MONITOR
	new_thread->entry.pEntry = entry;
    4430:	6666      	str	r6, [r4, #100]	; 0x64
	new_thread->entry.parameter1 = p1;
    4432:	f8c4 a068 	str.w	sl, [r4, #104]	; 0x68
	new_thread->entry.parameter2 = p2;
    4436:	f8c4 906c 	str.w	r9, [r4, #108]	; 0x6c
	new_thread->entry.parameter3 = p3;
    443a:	f8c4 8070 	str.w	r8, [r4, #112]	; 0x70
	__asm__ volatile(
    443e:	f04f 0320 	mov.w	r3, #32
    4442:	f3ef 8211 	mrs	r2, BASEPRI
    4446:	f383 8812 	msr	BASEPRI_MAX, r3
    444a:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&z_thread_monitor_lock);

	new_thread->next_thread = _kernel.threads;
    444e:	4b13      	ldr	r3, [pc, #76]	; (449c <z_setup_new_thread+0xc4>)
    4450:	6a99      	ldr	r1, [r3, #40]	; 0x28
    4452:	6761      	str	r1, [r4, #116]	; 0x74
	_kernel.threads = new_thread;
    4454:	629c      	str	r4, [r3, #40]	; 0x28
	__asm__ volatile(
    4456:	f382 8811 	msr	BASEPRI, r2
    445a:	f3bf 8f6f 	isb	sy
	k_spin_unlock(&z_thread_monitor_lock, key);
#endif
#ifdef CONFIG_THREAD_NAME
	if (name != NULL) {
    445e:	f1bb 0f00 	cmp.w	fp, #0
    4462:	d013      	beq.n	448c <z_setup_new_thread+0xb4>
		strncpy(new_thread->name, name,
    4464:	221f      	movs	r2, #31
    4466:	4659      	mov	r1, fp
    4468:	f104 0078 	add.w	r0, r4, #120	; 0x78
    446c:	f001 fd6e 	bl	5f4c <strncpy>
			CONFIG_THREAD_MAX_NAME_LEN - 1);
		/* Ensure NULL termination, truncate if longer */
		new_thread->name[CONFIG_THREAD_MAX_NAME_LEN - 1] = '\0';
    4470:	2300      	movs	r3, #0
    4472:	f884 3097 	strb.w	r3, [r4, #151]	; 0x97
#ifdef CONFIG_SCHED_CPU_MASK
	new_thread->base.cpu_mask = -1;
#endif
#ifdef CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN
	/* _current may be null if the dummy thread is not used */
	if (!_current) {
    4476:	4b09      	ldr	r3, [pc, #36]	; (449c <z_setup_new_thread+0xc4>)
    4478:	689b      	ldr	r3, [r3, #8]
    447a:	b15b      	cbz	r3, 4494 <z_setup_new_thread+0xbc>
	}
#endif
#ifdef CONFIG_SCHED_DEADLINE
	new_thread->base.prio_deadline = 0;
#endif
	new_thread->resource_pool = _current->resource_pool;
    447c:	f8d3 30a8 	ldr.w	r3, [r3, #168]	; 0xa8
    4480:	f8c4 30a8 	str.w	r3, [r4, #168]	; 0xa8
#ifdef CONFIG_THREAD_RUNTIME_STATS
	memset(&new_thread->rt_stats, 0, sizeof(new_thread->rt_stats));
#endif

	return stack_ptr;
}
    4484:	4628      	mov	r0, r5
    4486:	b005      	add	sp, #20
    4488:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		new_thread->name[0] = '\0';
    448c:	2300      	movs	r3, #0
    448e:	f884 3078 	strb.w	r3, [r4, #120]	; 0x78
    4492:	e7f0      	b.n	4476 <z_setup_new_thread+0x9e>
		new_thread->resource_pool = NULL;
    4494:	f8c4 30a8 	str.w	r3, [r4, #168]	; 0xa8
		return stack_ptr;
    4498:	e7f4      	b.n	4484 <z_setup_new_thread+0xac>
    449a:	bf00      	nop
    449c:	20000a9c 	.word	0x20000a9c

000044a0 <z_init_static_threads>:
	}
}
#endif /* CONFIG_USERSPACE */

void z_init_static_threads(void)
{
    44a0:	e92d 4370 	stmdb	sp!, {r4, r5, r6, r8, r9, lr}
    44a4:	b086      	sub	sp, #24
	_FOREACH_STATIC_THREAD(thread_data) {
    44a6:	4c23      	ldr	r4, [pc, #140]	; (4534 <z_init_static_threads+0x94>)
    44a8:	4b23      	ldr	r3, [pc, #140]	; (4538 <z_init_static_threads+0x98>)
    44aa:	429c      	cmp	r4, r3
    44ac:	d215      	bcs.n	44da <z_init_static_threads+0x3a>
		z_setup_new_thread(
    44ae:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    44b0:	9305      	str	r3, [sp, #20]
    44b2:	6a23      	ldr	r3, [r4, #32]
    44b4:	9304      	str	r3, [sp, #16]
    44b6:	69e3      	ldr	r3, [r4, #28]
    44b8:	9303      	str	r3, [sp, #12]
    44ba:	69a3      	ldr	r3, [r4, #24]
    44bc:	9302      	str	r3, [sp, #8]
    44be:	6963      	ldr	r3, [r4, #20]
    44c0:	9301      	str	r3, [sp, #4]
    44c2:	6923      	ldr	r3, [r4, #16]
    44c4:	9300      	str	r3, [sp, #0]
    44c6:	68e3      	ldr	r3, [r4, #12]
    44c8:	68a2      	ldr	r2, [r4, #8]
    44ca:	6861      	ldr	r1, [r4, #4]
    44cc:	6820      	ldr	r0, [r4, #0]
    44ce:	f7ff ff83 	bl	43d8 <z_setup_new_thread>
			thread_data->init_p3,
			thread_data->init_prio,
			thread_data->init_options,
			thread_data->init_name);

		thread_data->init_thread->init_data = thread_data;
    44d2:	6823      	ldr	r3, [r4, #0]
    44d4:	655c      	str	r4, [r3, #84]	; 0x54
	_FOREACH_STATIC_THREAD(thread_data) {
    44d6:	3430      	adds	r4, #48	; 0x30
    44d8:	e7e6      	b.n	44a8 <z_init_static_threads+0x8>
	 * until they are all started.
	 *
	 * Note that static threads defined using the legacy API have a
	 * delay of K_FOREVER.
	 */
	k_sched_lock();
    44da:	f000 f90d 	bl	46f8 <k_sched_lock>
	_FOREACH_STATIC_THREAD(thread_data) {
    44de:	4c15      	ldr	r4, [pc, #84]	; (4534 <z_init_static_threads+0x94>)
    44e0:	e01b      	b.n	451a <z_init_static_threads+0x7a>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
			schedule_new_thread(thread_data->init_thread,
    44e2:	6826      	ldr	r6, [r4, #0]
					    K_MSEC(thread_data->init_delay));
    44e4:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    44e8:	ea4f 79e3 	mov.w	r9, r3, asr #31
		} else {
			return (t * to_hz + off) / from_hz;
    44ec:	ea4f 31c9 	mov.w	r1, r9, lsl #15
    44f0:	ea41 4153 	orr.w	r1, r1, r3, lsr #17
    44f4:	03d8      	lsls	r0, r3, #15
    44f6:	f240 35e7 	movw	r5, #999	; 0x3e7
    44fa:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    44fe:	2300      	movs	r3, #0
    4500:	1940      	adds	r0, r0, r5
    4502:	f04f 0500 	mov.w	r5, #0
    4506:	eb45 0101 	adc.w	r1, r5, r1
    450a:	f7fb fdf9 	bl	100 <__aeabi_uldivmod>
    450e:	4602      	mov	r2, r0
    4510:	460b      	mov	r3, r1
			schedule_new_thread(thread_data->init_thread,
    4512:	4630      	mov	r0, r6
    4514:	f7ff ff4e 	bl	43b4 <schedule_new_thread>
	_FOREACH_STATIC_THREAD(thread_data) {
    4518:	3430      	adds	r4, #48	; 0x30
    451a:	4b07      	ldr	r3, [pc, #28]	; (4538 <z_init_static_threads+0x98>)
    451c:	429c      	cmp	r4, r3
    451e:	d204      	bcs.n	452a <z_init_static_threads+0x8a>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    4520:	6a63      	ldr	r3, [r4, #36]	; 0x24
    4522:	f1b3 3fff 	cmp.w	r3, #4294967295
    4526:	d0f7      	beq.n	4518 <z_init_static_threads+0x78>
    4528:	e7db      	b.n	44e2 <z_init_static_threads+0x42>
		}
	}
	k_sched_unlock();
    452a:	f000 fa83 	bl	4a34 <k_sched_unlock>
}
    452e:	b006      	add	sp, #24
    4530:	e8bd 8370 	ldmia.w	sp!, {r4, r5, r6, r8, r9, pc}
    4534:	200001c4 	.word	0x200001c4
    4538:	200001c4 	.word	0x200001c4

0000453c <pm_save_idle>:
 *
 * Sets the kernel data structure idle field to either a positive value or
 * K_FOREVER.
 */
static void pm_save_idle(void)
{
    453c:	b508      	push	{r3, lr}
#ifdef CONFIG_PM
	int32_t ticks = z_get_next_timeout_expiry();
    453e:	f002 fe73 	bl	7228 <z_get_next_timeout_expiry>
	_kernel.idle = ticks;
    4542:	4b04      	ldr	r3, [pc, #16]	; (4554 <pm_save_idle+0x18>)
    4544:	6198      	str	r0, [r3, #24]
	 * before exiting. This is because the kernel does not do its own idle
	 * processing in those cases i.e. skips k_cpu_idle(). The kernel's
	 * idle processing re-enables interrupts which is essential for
	 * the kernel's scheduling logic.
	 */
	if (pm_system_suspend(ticks) == PM_STATE_ACTIVE) {
    4546:	f7fc fdc1 	bl	10cc <pm_system_suspend>
    454a:	b100      	cbz	r0, 454e <pm_save_idle+0x12>
		k_cpu_idle();
	}
#endif
}
    454c:	bd08      	pop	{r3, pc}
	arch_cpu_idle();
    454e:	f7fc fe27 	bl	11a0 <arch_cpu_idle>
    4552:	e7fb      	b.n	454c <pm_save_idle+0x10>
    4554:	20000a9c 	.word	0x20000a9c

00004558 <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    4558:	b538      	push	{r3, r4, r5, lr}
    455a:	4604      	mov	r4, r0
	__asm__ volatile(
    455c:	f04f 0320 	mov.w	r3, #32
    4560:	f3ef 8511 	mrs	r5, BASEPRI
    4564:	f383 8812 	msr	BASEPRI_MAX, r3
    4568:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    456c:	f002 fdc5 	bl	70fa <z_unpend_first_thread>

	if (thread != NULL) {
    4570:	b148      	cbz	r0, 4586 <z_impl_k_sem_give+0x2e>
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    4572:	2200      	movs	r2, #0
    4574:	f8c0 20b0 	str.w	r2, [r0, #176]	; 0xb0
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    4578:	f002 fd24 	bl	6fc4 <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    457c:	4629      	mov	r1, r5
    457e:	4809      	ldr	r0, [pc, #36]	; (45a4 <z_impl_k_sem_give+0x4c>)
    4580:	f000 f89e 	bl	46c0 <z_reschedule>

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    4584:	bd38      	pop	{r3, r4, r5, pc}
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    4586:	68a3      	ldr	r3, [r4, #8]
    4588:	68e2      	ldr	r2, [r4, #12]
    458a:	4293      	cmp	r3, r2
    458c:	d008      	beq.n	45a0 <z_impl_k_sem_give+0x48>
    458e:	2201      	movs	r2, #1
    4590:	4413      	add	r3, r2
    4592:	60a3      	str	r3, [r4, #8]
	z_handle_obj_poll_events(&sem->poll_events, K_POLL_STATE_SEM_AVAILABLE);
    4594:	2102      	movs	r1, #2
    4596:	f104 0010 	add.w	r0, r4, #16
    459a:	f002 ff02 	bl	73a2 <z_handle_obj_poll_events>
}
    459e:	e7ed      	b.n	457c <z_impl_k_sem_give+0x24>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    45a0:	2200      	movs	r2, #0
    45a2:	e7f5      	b.n	4590 <z_impl_k_sem_give+0x38>
    45a4:	20000ac8 	.word	0x20000ac8

000045a8 <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    45a8:	b530      	push	{r4, r5, lr}
    45aa:	b083      	sub	sp, #12
    45ac:	461d      	mov	r5, r3
    45ae:	f04f 0320 	mov.w	r3, #32
    45b2:	f3ef 8111 	mrs	r1, BASEPRI
    45b6:	f383 8812 	msr	BASEPRI_MAX, r3
    45ba:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    45be:	6883      	ldr	r3, [r0, #8]
    45c0:	b143      	cbz	r3, 45d4 <z_impl_k_sem_take+0x2c>
		sem->count--;
    45c2:	3b01      	subs	r3, #1
    45c4:	6083      	str	r3, [r0, #8]
	__asm__ volatile(
    45c6:	f381 8811 	msr	BASEPRI, r1
    45ca:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    45ce:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    45d0:	b003      	add	sp, #12
    45d2:	bd30      	pop	{r4, r5, pc}
    45d4:	4614      	mov	r4, r2
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    45d6:	ea54 0305 	orrs.w	r3, r4, r5
    45da:	d006      	beq.n	45ea <z_impl_k_sem_take+0x42>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    45dc:	e9cd 4500 	strd	r4, r5, [sp]
    45e0:	4602      	mov	r2, r0
    45e2:	4805      	ldr	r0, [pc, #20]	; (45f8 <z_impl_k_sem_take+0x50>)
    45e4:	f000 f9d0 	bl	4988 <z_pend_curr>
	return ret;
    45e8:	e7f2      	b.n	45d0 <z_impl_k_sem_take+0x28>
    45ea:	f381 8811 	msr	BASEPRI, r1
    45ee:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    45f2:	f06f 000f 	mvn.w	r0, #15
    45f6:	e7eb      	b.n	45d0 <z_impl_k_sem_take+0x28>
    45f8:	20000ac8 	.word	0x20000ac8

000045fc <add_thread_timeout>:
		z_priq_wait_add(&wait_q->waitq, thread);
	}
}

static void add_thread_timeout(struct k_thread *thread, k_timeout_t timeout)
{
    45fc:	b538      	push	{r3, r4, r5, lr}
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    45fe:	f1b3 3fff 	cmp.w	r3, #4294967295
    4602:	bf08      	it	eq
    4604:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    4608:	d100      	bne.n	460c <add_thread_timeout+0x10>
		z_add_thread_timeout(thread, timeout);
	}
}
    460a:	bd38      	pop	{r3, r4, r5, pc}
    460c:	4902      	ldr	r1, [pc, #8]	; (4618 <add_thread_timeout+0x1c>)
    460e:	3018      	adds	r0, #24
    4610:	f000 fc04 	bl	4e1c <z_add_timeout>
    4614:	e7f9      	b.n	460a <add_thread_timeout+0xe>
    4616:	bf00      	nop
    4618:	00006ffd 	.word	0x00006ffd

0000461c <z_reset_time_slice>:
{
    461c:	b508      	push	{r3, lr}
	if (slice_time != 0) {
    461e:	4b08      	ldr	r3, [pc, #32]	; (4640 <z_reset_time_slice+0x24>)
    4620:	681b      	ldr	r3, [r3, #0]
    4622:	b903      	cbnz	r3, 4626 <z_reset_time_slice+0xa>
}
    4624:	bd08      	pop	{r3, pc}
		_current_cpu->slice_ticks = slice_time + sys_clock_elapsed();
    4626:	f7fe fd2f 	bl	3088 <sys_clock_elapsed>
    462a:	4603      	mov	r3, r0
    462c:	4a04      	ldr	r2, [pc, #16]	; (4640 <z_reset_time_slice+0x24>)
    462e:	6810      	ldr	r0, [r2, #0]
    4630:	4403      	add	r3, r0
    4632:	4a04      	ldr	r2, [pc, #16]	; (4644 <z_reset_time_slice+0x28>)
    4634:	6113      	str	r3, [r2, #16]
		z_set_timeout_expiry(slice_time, false);
    4636:	2100      	movs	r1, #0
    4638:	f002 fe0c 	bl	7254 <z_set_timeout_expiry>
}
    463c:	e7f2      	b.n	4624 <z_reset_time_slice+0x8>
    463e:	bf00      	nop
    4640:	20000ad0 	.word	0x20000ad0
    4644:	20000a9c 	.word	0x20000a9c

00004648 <k_sched_time_slice_set>:
{
    4648:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    464c:	4606      	mov	r6, r0
    464e:	4688      	mov	r8, r1
	LOCKED(&sched_spinlock) {
    4650:	2300      	movs	r3, #0
	__asm__ volatile(
    4652:	f04f 0220 	mov.w	r2, #32
    4656:	f3ef 8711 	mrs	r7, BASEPRI
    465a:	f382 8812 	msr	BASEPRI_MAX, r2
    465e:	f3bf 8f6f 	isb	sy
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    4662:	e009      	b.n	4678 <k_sched_time_slice_set+0x30>
		slice_max_prio = prio;
    4664:	4b13      	ldr	r3, [pc, #76]	; (46b4 <k_sched_time_slice_set+0x6c>)
    4666:	f8c3 8000 	str.w	r8, [r3]
		z_reset_time_slice();
    466a:	f7ff ffd7 	bl	461c <z_reset_time_slice>
	__asm__ volatile(
    466e:	f387 8811 	msr	BASEPRI, r7
    4672:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    4676:	2301      	movs	r3, #1
    4678:	b9cb      	cbnz	r3, 46ae <k_sched_time_slice_set+0x66>
		_current_cpu->slice_ticks = 0;
    467a:	2300      	movs	r3, #0
    467c:	4a0e      	ldr	r2, [pc, #56]	; (46b8 <k_sched_time_slice_set+0x70>)
    467e:	6113      	str	r3, [r2, #16]
			return (uint32_t)((t * to_hz + off) / from_hz);
    4680:	0c75      	lsrs	r5, r6, #17
    4682:	03f4      	lsls	r4, r6, #15
    4684:	f240 30e7 	movw	r0, #999	; 0x3e7
    4688:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    468c:	2300      	movs	r3, #0
    468e:	1820      	adds	r0, r4, r0
    4690:	f04f 0100 	mov.w	r1, #0
    4694:	eb45 0101 	adc.w	r1, r5, r1
    4698:	f7fb fd32 	bl	100 <__aeabi_uldivmod>
		slice_time = k_ms_to_ticks_ceil32(slice);
    469c:	4b07      	ldr	r3, [pc, #28]	; (46bc <k_sched_time_slice_set+0x74>)
    469e:	6018      	str	r0, [r3, #0]
		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && slice > 0) {
    46a0:	2e00      	cmp	r6, #0
    46a2:	dddf      	ble.n	4664 <k_sched_time_slice_set+0x1c>
			slice_time = MAX(2, slice_time);
    46a4:	2802      	cmp	r0, #2
    46a6:	bfb8      	it	lt
    46a8:	2002      	movlt	r0, #2
    46aa:	6018      	str	r0, [r3, #0]
    46ac:	e7da      	b.n	4664 <k_sched_time_slice_set+0x1c>
}
    46ae:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    46b2:	bf00      	nop
    46b4:	20000acc 	.word	0x20000acc
    46b8:	20000a9c 	.word	0x20000a9c
    46bc:	20000ad0 	.word	0x20000ad0

000046c0 <z_reschedule>:
	return new_thread != _current;
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
    46c0:	b508      	push	{r3, lr}
	if (resched(key.key) && need_swap()) {
    46c2:	4608      	mov	r0, r1
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    46c4:	b921      	cbnz	r1, 46d0 <z_reschedule+0x10>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    46c6:	f3ef 8305 	mrs	r3, IPSR
    46ca:	b913      	cbnz	r3, 46d2 <z_reschedule+0x12>
    46cc:	2101      	movs	r1, #1
    46ce:	e000      	b.n	46d2 <z_reschedule+0x12>
    46d0:	2100      	movs	r1, #0
	if (resched(key.key) && need_swap()) {
    46d2:	f011 0f01 	tst.w	r1, #1
    46d6:	d007      	beq.n	46e8 <z_reschedule+0x28>
	new_thread = _kernel.ready_q.cache;
    46d8:	4b06      	ldr	r3, [pc, #24]	; (46f4 <z_reschedule+0x34>)
    46da:	69da      	ldr	r2, [r3, #28]
	return new_thread != _current;
    46dc:	689b      	ldr	r3, [r3, #8]
	if (resched(key.key) && need_swap()) {
    46de:	429a      	cmp	r2, r3
    46e0:	d002      	beq.n	46e8 <z_reschedule+0x28>
	ret = arch_swap(key);
    46e2:	f7fc fddd 	bl	12a0 <arch_swap>
		z_swap(lock, key);
    46e6:	e003      	b.n	46f0 <z_reschedule+0x30>
    46e8:	f380 8811 	msr	BASEPRI, r0
    46ec:	f3bf 8f6f 	isb	sy
	} else {
		k_spin_unlock(lock, key);
	}
}
    46f0:	bd08      	pop	{r3, pc}
    46f2:	bf00      	nop
    46f4:	20000a9c 	.word	0x20000a9c

000046f8 <k_sched_lock>:
	}
}

void k_sched_lock(void)
{
	LOCKED(&sched_spinlock) {
    46f8:	2300      	movs	r3, #0
	__asm__ volatile(
    46fa:	f04f 0220 	mov.w	r2, #32
    46fe:	f3ef 8111 	mrs	r1, BASEPRI
    4702:	f382 8812 	msr	BASEPRI_MAX, r2
    4706:	f3bf 8f6f 	isb	sy
    470a:	b953      	cbnz	r3, 4722 <k_sched_lock+0x2a>
static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1U, "");

	--_current->base.sched_locked;
    470c:	4b05      	ldr	r3, [pc, #20]	; (4724 <k_sched_lock+0x2c>)
    470e:	689a      	ldr	r2, [r3, #8]
    4710:	7bd3      	ldrb	r3, [r2, #15]
    4712:	3b01      	subs	r3, #1
    4714:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    4716:	f381 8811 	msr	BASEPRI, r1
    471a:	f3bf 8f6f 	isb	sy
    471e:	2301      	movs	r3, #1
    4720:	e7f3      	b.n	470a <k_sched_lock+0x12>
		SYS_PORT_TRACING_FUNC(k_thread, sched_lock);

		z_sched_lock();
	}
}
    4722:	4770      	bx	lr
    4724:	20000a9c 	.word	0x20000a9c

00004728 <update_cache>:
{
    4728:	b538      	push	{r3, r4, r5, lr}
    472a:	4604      	mov	r4, r0
	thread = _priq_run_best(&_kernel.ready_q.runq);
    472c:	480f      	ldr	r0, [pc, #60]	; (476c <update_cache+0x44>)
    472e:	f002 fc42 	bl	6fb6 <z_priq_dumb_best>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    4732:	4605      	mov	r5, r0
    4734:	b170      	cbz	r0, 4754 <update_cache+0x2c>
	if (preempt_ok != 0) {
    4736:	b984      	cbnz	r4, 475a <update_cache+0x32>
	if (z_is_thread_prevented_from_running(_current)) {
    4738:	4b0d      	ldr	r3, [pc, #52]	; (4770 <update_cache+0x48>)
    473a:	689b      	ldr	r3, [r3, #8]
	uint8_t state = thread->base.thread_state;
    473c:	7b5a      	ldrb	r2, [r3, #13]
    473e:	f012 0f1f 	tst.w	r2, #31
    4742:	d10a      	bne.n	475a <update_cache+0x32>
 * @return true if node is linked into a list, false if it is not
 */

static inline bool sys_dnode_is_linked(const sys_dnode_t *node)
{
	return node->next != NULL;
    4744:	69aa      	ldr	r2, [r5, #24]
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    4746:	b942      	cbnz	r2, 475a <update_cache+0x32>
	return thread->base.preempt <= _PREEMPT_THRESHOLD;
    4748:	89da      	ldrh	r2, [r3, #14]
	if (is_preempt(_current) || is_metairq(thread)) {
    474a:	2a7f      	cmp	r2, #127	; 0x7f
    474c:	d905      	bls.n	475a <update_cache+0x32>
		_kernel.ready_q.cache = _current;
    474e:	4a08      	ldr	r2, [pc, #32]	; (4770 <update_cache+0x48>)
    4750:	61d3      	str	r3, [r2, #28]
    4752:	e00a      	b.n	476a <update_cache+0x42>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    4754:	4b06      	ldr	r3, [pc, #24]	; (4770 <update_cache+0x48>)
    4756:	68dd      	ldr	r5, [r3, #12]
    4758:	e7ed      	b.n	4736 <update_cache+0xe>
		if (thread != _current) {
    475a:	4b05      	ldr	r3, [pc, #20]	; (4770 <update_cache+0x48>)
    475c:	689b      	ldr	r3, [r3, #8]
    475e:	42ab      	cmp	r3, r5
    4760:	d001      	beq.n	4766 <update_cache+0x3e>
			z_reset_time_slice();
    4762:	f7ff ff5b 	bl	461c <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    4766:	4b02      	ldr	r3, [pc, #8]	; (4770 <update_cache+0x48>)
    4768:	61dd      	str	r5, [r3, #28]
}
    476a:	bd38      	pop	{r3, r4, r5, pc}
    476c:	20000abc 	.word	0x20000abc
    4770:	20000a9c 	.word	0x20000a9c

00004774 <move_thread_to_end_of_prio_q>:
{
    4774:	b538      	push	{r3, r4, r5, lr}
    4776:	4605      	mov	r5, r0
	return (thread->base.thread_state & state) != 0U;
    4778:	7b42      	ldrb	r2, [r0, #13]
	if (z_is_thread_queued(thread)) {
    477a:	f990 300d 	ldrsb.w	r3, [r0, #13]
    477e:	2b00      	cmp	r3, #0
    4780:	db28      	blt.n	47d4 <move_thread_to_end_of_prio_q+0x60>
	thread->base.thread_state |= _THREAD_QUEUED;
    4782:	7b6b      	ldrb	r3, [r5, #13]
    4784:	f063 037f 	orn	r3, r3, #127	; 0x7f
    4788:	736b      	strb	r3, [r5, #13]
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    478a:	4b1a      	ldr	r3, [pc, #104]	; (47f4 <move_thread_to_end_of_prio_q+0x80>)
    478c:	f853 4f20 	ldr.w	r4, [r3, #32]!
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4790:	429c      	cmp	r4, r3
    4792:	d02d      	beq.n	47f0 <move_thread_to_end_of_prio_q+0x7c>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4794:	b16c      	cbz	r4, 47b2 <move_thread_to_end_of_prio_q+0x3e>
		if (z_sched_prio_cmp(thread, t) > 0) {
    4796:	4621      	mov	r1, r4
    4798:	4628      	mov	r0, r5
    479a:	f002 fbc2 	bl	6f22 <z_sched_prio_cmp>
    479e:	2800      	cmp	r0, #0
    47a0:	dc20      	bgt.n	47e4 <move_thread_to_end_of_prio_q+0x70>
 */

static inline sys_dnode_t *sys_dlist_peek_next(sys_dlist_t *list,
					       sys_dnode_t *node)
{
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    47a2:	b134      	cbz	r4, 47b2 <move_thread_to_end_of_prio_q+0x3e>
	return (node == list->tail) ? NULL : node->next;
    47a4:	4b13      	ldr	r3, [pc, #76]	; (47f4 <move_thread_to_end_of_prio_q+0x80>)
    47a6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    47a8:	429c      	cmp	r4, r3
    47aa:	d002      	beq.n	47b2 <move_thread_to_end_of_prio_q+0x3e>
    47ac:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    47ae:	2c00      	cmp	r4, #0
    47b0:	d1f0      	bne.n	4794 <move_thread_to_end_of_prio_q+0x20>
 * @return N/A
 */

static inline void sys_dlist_append(sys_dlist_t *list, sys_dnode_t *node)
{
	sys_dnode_t *const tail = list->tail;
    47b2:	4b10      	ldr	r3, [pc, #64]	; (47f4 <move_thread_to_end_of_prio_q+0x80>)
    47b4:	6a5a      	ldr	r2, [r3, #36]	; 0x24

	node->next = list;
    47b6:	f103 0120 	add.w	r1, r3, #32
    47ba:	6029      	str	r1, [r5, #0]
	node->prev = tail;
    47bc:	606a      	str	r2, [r5, #4]

	tail->next = node;
    47be:	6015      	str	r5, [r2, #0]
	list->tail = node;
    47c0:	625d      	str	r5, [r3, #36]	; 0x24
	update_cache(thread == _current);
    47c2:	4b0c      	ldr	r3, [pc, #48]	; (47f4 <move_thread_to_end_of_prio_q+0x80>)
    47c4:	6898      	ldr	r0, [r3, #8]
    47c6:	42a8      	cmp	r0, r5
    47c8:	bf14      	ite	ne
    47ca:	2000      	movne	r0, #0
    47cc:	2001      	moveq	r0, #1
    47ce:	f7ff ffab 	bl	4728 <update_cache>
}
    47d2:	bd38      	pop	{r3, r4, r5, pc}
	thread->base.thread_state &= ~_THREAD_QUEUED;
    47d4:	f002 027f 	and.w	r2, r2, #127	; 0x7f
    47d8:	7342      	strb	r2, [r0, #13]
		_priq_run_remove(pq, thread);
    47da:	4601      	mov	r1, r0
    47dc:	4806      	ldr	r0, [pc, #24]	; (47f8 <move_thread_to_end_of_prio_q+0x84>)
    47de:	f002 fbbf 	bl	6f60 <z_priq_dumb_remove>
}
    47e2:	e7ce      	b.n	4782 <move_thread_to_end_of_prio_q+0xe>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    47e4:	6863      	ldr	r3, [r4, #4]

	node->prev = prev;
    47e6:	606b      	str	r3, [r5, #4]
	node->next = successor;
    47e8:	602c      	str	r4, [r5, #0]
	prev->next = node;
    47ea:	601d      	str	r5, [r3, #0]
	successor->prev = node;
    47ec:	6065      	str	r5, [r4, #4]
}
    47ee:	e7e8      	b.n	47c2 <move_thread_to_end_of_prio_q+0x4e>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    47f0:	2400      	movs	r4, #0
    47f2:	e7cf      	b.n	4794 <move_thread_to_end_of_prio_q+0x20>
    47f4:	20000a9c 	.word	0x20000a9c
    47f8:	20000abc 	.word	0x20000abc

000047fc <z_time_slice>:
{
    47fc:	b510      	push	{r4, lr}
	__asm__ volatile(
    47fe:	f04f 0320 	mov.w	r3, #32
    4802:	f3ef 8411 	mrs	r4, BASEPRI
    4806:	f383 8812 	msr	BASEPRI_MAX, r3
    480a:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    480e:	4b1c      	ldr	r3, [pc, #112]	; (4880 <z_time_slice+0x84>)
    4810:	689b      	ldr	r3, [r3, #8]
    4812:	4a1c      	ldr	r2, [pc, #112]	; (4884 <z_time_slice+0x88>)
    4814:	6812      	ldr	r2, [r2, #0]
    4816:	4293      	cmp	r3, r2
    4818:	d01d      	beq.n	4856 <z_time_slice+0x5a>
	pending_current = NULL;
    481a:	4a1a      	ldr	r2, [pc, #104]	; (4884 <z_time_slice+0x88>)
    481c:	2100      	movs	r1, #0
    481e:	6011      	str	r1, [r2, #0]
	if (slice_time && sliceable(_current)) {
    4820:	4a19      	ldr	r2, [pc, #100]	; (4888 <z_time_slice+0x8c>)
    4822:	6812      	ldr	r2, [r2, #0]
    4824:	b322      	cbz	r2, 4870 <z_time_slice+0x74>
	return thread->base.preempt <= _PREEMPT_THRESHOLD;
    4826:	89da      	ldrh	r2, [r3, #14]
		&& !z_is_idle_thread_object(thread);
    4828:	2a7f      	cmp	r2, #127	; 0x7f
    482a:	d821      	bhi.n	4870 <z_time_slice+0x74>
	uint8_t state = thread->base.thread_state;
    482c:	7b5a      	ldrb	r2, [r3, #13]
		&& !z_is_thread_prevented_from_running(thread)
    482e:	f012 0f1f 	tst.w	r2, #31
    4832:	d11d      	bne.n	4870 <z_time_slice+0x74>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    4834:	f993 100e 	ldrsb.w	r1, [r3, #14]
    4838:	4a14      	ldr	r2, [pc, #80]	; (488c <z_time_slice+0x90>)
    483a:	6812      	ldr	r2, [r2, #0]
    483c:	4291      	cmp	r1, r2
    483e:	db17      	blt.n	4870 <z_time_slice+0x74>
		&& !z_is_idle_thread_object(thread);
    4840:	4a13      	ldr	r2, [pc, #76]	; (4890 <z_time_slice+0x94>)
    4842:	4293      	cmp	r3, r2
    4844:	d014      	beq.n	4870 <z_time_slice+0x74>
		if (ticks >= _current_cpu->slice_ticks) {
    4846:	4a0e      	ldr	r2, [pc, #56]	; (4880 <z_time_slice+0x84>)
    4848:	6912      	ldr	r2, [r2, #16]
    484a:	4282      	cmp	r2, r0
    484c:	dd0a      	ble.n	4864 <z_time_slice+0x68>
			_current_cpu->slice_ticks -= ticks;
    484e:	1a10      	subs	r0, r2, r0
    4850:	4b0b      	ldr	r3, [pc, #44]	; (4880 <z_time_slice+0x84>)
    4852:	6118      	str	r0, [r3, #16]
    4854:	e00f      	b.n	4876 <z_time_slice+0x7a>
		z_reset_time_slice();
    4856:	f7ff fee1 	bl	461c <z_reset_time_slice>
	__asm__ volatile(
    485a:	f384 8811 	msr	BASEPRI, r4
    485e:	f3bf 8f6f 	isb	sy
		return;
    4862:	e00c      	b.n	487e <z_time_slice+0x82>
			move_thread_to_end_of_prio_q(_current);
    4864:	4618      	mov	r0, r3
    4866:	f7ff ff85 	bl	4774 <move_thread_to_end_of_prio_q>
			z_reset_time_slice();
    486a:	f7ff fed7 	bl	461c <z_reset_time_slice>
    486e:	e002      	b.n	4876 <z_time_slice+0x7a>
		_current_cpu->slice_ticks = 0;
    4870:	4b03      	ldr	r3, [pc, #12]	; (4880 <z_time_slice+0x84>)
    4872:	2200      	movs	r2, #0
    4874:	611a      	str	r2, [r3, #16]
    4876:	f384 8811 	msr	BASEPRI, r4
    487a:	f3bf 8f6f 	isb	sy
}
    487e:	bd10      	pop	{r4, pc}
    4880:	20000a9c 	.word	0x20000a9c
    4884:	20000ac8 	.word	0x20000ac8
    4888:	20000ad0 	.word	0x20000ad0
    488c:	20000acc 	.word	0x20000acc
    4890:	200001e8 	.word	0x200001e8

00004894 <ready_thread>:
{
    4894:	b538      	push	{r3, r4, r5, lr}
	return (thread->base.thread_state & state) != 0U;
    4896:	7b43      	ldrb	r3, [r0, #13]
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    4898:	f990 200d 	ldrsb.w	r2, [r0, #13]
    489c:	2a00      	cmp	r2, #0
    489e:	db2d      	blt.n	48fc <ready_thread+0x68>
    48a0:	4604      	mov	r4, r0
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    48a2:	f013 0f1f 	tst.w	r3, #31
    48a6:	d105      	bne.n	48b4 <ready_thread+0x20>
	return node->next != NULL;
    48a8:	6982      	ldr	r2, [r0, #24]
    48aa:	b10a      	cbz	r2, 48b0 <ready_thread+0x1c>
    48ac:	2200      	movs	r2, #0
    48ae:	e002      	b.n	48b6 <ready_thread+0x22>
    48b0:	2201      	movs	r2, #1
    48b2:	e000      	b.n	48b6 <ready_thread+0x22>
    48b4:	2200      	movs	r2, #0
    48b6:	b30a      	cbz	r2, 48fc <ready_thread+0x68>
	thread->base.thread_state |= _THREAD_QUEUED;
    48b8:	f063 037f 	orn	r3, r3, #127	; 0x7f
    48bc:	7363      	strb	r3, [r4, #13]
	return list->head == list;
    48be:	4b14      	ldr	r3, [pc, #80]	; (4910 <ready_thread+0x7c>)
    48c0:	f853 5f20 	ldr.w	r5, [r3, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    48c4:	429d      	cmp	r5, r3
    48c6:	d020      	beq.n	490a <ready_thread+0x76>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    48c8:	b16d      	cbz	r5, 48e6 <ready_thread+0x52>
		if (z_sched_prio_cmp(thread, t) > 0) {
    48ca:	4629      	mov	r1, r5
    48cc:	4620      	mov	r0, r4
    48ce:	f002 fb28 	bl	6f22 <z_sched_prio_cmp>
    48d2:	2800      	cmp	r0, #0
    48d4:	dc13      	bgt.n	48fe <ready_thread+0x6a>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    48d6:	b135      	cbz	r5, 48e6 <ready_thread+0x52>
	return (node == list->tail) ? NULL : node->next;
    48d8:	4b0d      	ldr	r3, [pc, #52]	; (4910 <ready_thread+0x7c>)
    48da:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    48dc:	429d      	cmp	r5, r3
    48de:	d002      	beq.n	48e6 <ready_thread+0x52>
    48e0:	682d      	ldr	r5, [r5, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    48e2:	2d00      	cmp	r5, #0
    48e4:	d1f0      	bne.n	48c8 <ready_thread+0x34>
	sys_dnode_t *const tail = list->tail;
    48e6:	4b0a      	ldr	r3, [pc, #40]	; (4910 <ready_thread+0x7c>)
    48e8:	6a5a      	ldr	r2, [r3, #36]	; 0x24
	node->next = list;
    48ea:	f103 0120 	add.w	r1, r3, #32
    48ee:	6021      	str	r1, [r4, #0]
	node->prev = tail;
    48f0:	6062      	str	r2, [r4, #4]
	tail->next = node;
    48f2:	6014      	str	r4, [r2, #0]
	list->tail = node;
    48f4:	625c      	str	r4, [r3, #36]	; 0x24
		update_cache(0);
    48f6:	2000      	movs	r0, #0
    48f8:	f7ff ff16 	bl	4728 <update_cache>
}
    48fc:	bd38      	pop	{r3, r4, r5, pc}
	sys_dnode_t *const prev = successor->prev;
    48fe:	686b      	ldr	r3, [r5, #4]
	node->prev = prev;
    4900:	6063      	str	r3, [r4, #4]
	node->next = successor;
    4902:	6025      	str	r5, [r4, #0]
	prev->next = node;
    4904:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    4906:	606c      	str	r4, [r5, #4]
}
    4908:	e7f5      	b.n	48f6 <ready_thread+0x62>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    490a:	2500      	movs	r5, #0
    490c:	e7dc      	b.n	48c8 <ready_thread+0x34>
    490e:	bf00      	nop
    4910:	20000a9c 	.word	0x20000a9c

00004914 <z_sched_start>:
{
    4914:	b510      	push	{r4, lr}
	__asm__ volatile(
    4916:	f04f 0320 	mov.w	r3, #32
    491a:	f3ef 8411 	mrs	r4, BASEPRI
    491e:	f383 8812 	msr	BASEPRI_MAX, r3
    4922:	f3bf 8f6f 	isb	sy
	return (thread->base.thread_state & _THREAD_PRESTART) == 0U;
    4926:	7b43      	ldrb	r3, [r0, #13]
	if (z_has_thread_started(thread)) {
    4928:	f013 0f04 	tst.w	r3, #4
    492c:	d104      	bne.n	4938 <z_sched_start+0x24>
	__asm__ volatile(
    492e:	f384 8811 	msr	BASEPRI, r4
    4932:	f3bf 8f6f 	isb	sy
}
    4936:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    4938:	f023 0304 	bic.w	r3, r3, #4
    493c:	7343      	strb	r3, [r0, #13]
	ready_thread(thread);
    493e:	f7ff ffa9 	bl	4894 <ready_thread>
	z_reschedule(&sched_spinlock, key);
    4942:	4621      	mov	r1, r4
    4944:	4801      	ldr	r0, [pc, #4]	; (494c <z_sched_start+0x38>)
    4946:	f7ff febb 	bl	46c0 <z_reschedule>
    494a:	e7f4      	b.n	4936 <z_sched_start+0x22>
    494c:	20000acc 	.word	0x20000acc

00004950 <unready_thread>:
{
    4950:	b510      	push	{r4, lr}
    4952:	4604      	mov	r4, r0
	return (thread->base.thread_state & state) != 0U;
    4954:	7b42      	ldrb	r2, [r0, #13]
	if (z_is_thread_queued(thread)) {
    4956:	f990 300d 	ldrsb.w	r3, [r0, #13]
    495a:	2b00      	cmp	r3, #0
    495c:	db08      	blt.n	4970 <unready_thread+0x20>
	update_cache(thread == _current);
    495e:	4b08      	ldr	r3, [pc, #32]	; (4980 <unready_thread+0x30>)
    4960:	6898      	ldr	r0, [r3, #8]
    4962:	42a0      	cmp	r0, r4
    4964:	bf14      	ite	ne
    4966:	2000      	movne	r0, #0
    4968:	2001      	moveq	r0, #1
    496a:	f7ff fedd 	bl	4728 <update_cache>
}
    496e:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_QUEUED;
    4970:	f002 027f 	and.w	r2, r2, #127	; 0x7f
    4974:	7342      	strb	r2, [r0, #13]
		_priq_run_remove(pq, thread);
    4976:	4601      	mov	r1, r0
    4978:	4802      	ldr	r0, [pc, #8]	; (4984 <unready_thread+0x34>)
    497a:	f002 faf1 	bl	6f60 <z_priq_dumb_remove>
}
    497e:	e7ee      	b.n	495e <unready_thread+0xe>
    4980:	20000a9c 	.word	0x20000a9c
    4984:	20000abc 	.word	0x20000abc

00004988 <z_pend_curr>:
{
    4988:	b510      	push	{r4, lr}
    498a:	460c      	mov	r4, r1
    498c:	4611      	mov	r1, r2
	pending_current = _current;
    498e:	4b06      	ldr	r3, [pc, #24]	; (49a8 <z_pend_curr+0x20>)
    4990:	6898      	ldr	r0, [r3, #8]
    4992:	4b06      	ldr	r3, [pc, #24]	; (49ac <z_pend_curr+0x24>)
    4994:	6018      	str	r0, [r3, #0]
	pend(_current, wait_q, timeout);
    4996:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    499a:	f002 fb8d 	bl	70b8 <pend>
    499e:	4620      	mov	r0, r4
    49a0:	f7fc fc7e 	bl	12a0 <arch_swap>
}
    49a4:	bd10      	pop	{r4, pc}
    49a6:	bf00      	nop
    49a8:	20000a9c 	.word	0x20000a9c
    49ac:	20000ac8 	.word	0x20000ac8

000049b0 <z_impl_k_thread_suspend>:
{
    49b0:	b538      	push	{r3, r4, r5, lr}
    49b2:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    49b4:	3018      	adds	r0, #24
    49b6:	f002 fc19 	bl	71ec <z_abort_timeout>
	LOCKED(&sched_spinlock) {
    49ba:	2300      	movs	r3, #0
	__asm__ volatile(
    49bc:	f04f 0220 	mov.w	r2, #32
    49c0:	f3ef 8511 	mrs	r5, BASEPRI
    49c4:	f382 8812 	msr	BASEPRI_MAX, r2
    49c8:	f3bf 8f6f 	isb	sy
    49cc:	e010      	b.n	49f0 <z_impl_k_thread_suspend+0x40>
	thread->base.thread_state |= _THREAD_SUSPENDED;
    49ce:	7b63      	ldrb	r3, [r4, #13]
    49d0:	f043 0310 	orr.w	r3, r3, #16
    49d4:	7363      	strb	r3, [r4, #13]
		update_cache(thread == _current);
    49d6:	4b15      	ldr	r3, [pc, #84]	; (4a2c <z_impl_k_thread_suspend+0x7c>)
    49d8:	6898      	ldr	r0, [r3, #8]
    49da:	42a0      	cmp	r0, r4
    49dc:	bf14      	ite	ne
    49de:	2000      	movne	r0, #0
    49e0:	2001      	moveq	r0, #1
    49e2:	f7ff fea1 	bl	4728 <update_cache>
	__asm__ volatile(
    49e6:	f385 8811 	msr	BASEPRI, r5
    49ea:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    49ee:	2301      	movs	r3, #1
    49f0:	b963      	cbnz	r3, 4a0c <z_impl_k_thread_suspend+0x5c>
	return (thread->base.thread_state & state) != 0U;
    49f2:	7b62      	ldrb	r2, [r4, #13]
		if (z_is_thread_queued(thread)) {
    49f4:	f994 300d 	ldrsb.w	r3, [r4, #13]
    49f8:	2b00      	cmp	r3, #0
    49fa:	dae8      	bge.n	49ce <z_impl_k_thread_suspend+0x1e>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    49fc:	f002 027f 	and.w	r2, r2, #127	; 0x7f
    4a00:	7362      	strb	r2, [r4, #13]
		_priq_run_remove(pq, thread);
    4a02:	4621      	mov	r1, r4
    4a04:	480a      	ldr	r0, [pc, #40]	; (4a30 <z_impl_k_thread_suspend+0x80>)
    4a06:	f002 faab 	bl	6f60 <z_priq_dumb_remove>
}
    4a0a:	e7e0      	b.n	49ce <z_impl_k_thread_suspend+0x1e>
	if (thread == _current) {
    4a0c:	4b07      	ldr	r3, [pc, #28]	; (4a2c <z_impl_k_thread_suspend+0x7c>)
    4a0e:	689b      	ldr	r3, [r3, #8]
    4a10:	42a3      	cmp	r3, r4
    4a12:	d000      	beq.n	4a16 <z_impl_k_thread_suspend+0x66>
}
    4a14:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    4a16:	f04f 0320 	mov.w	r3, #32
    4a1a:	f3ef 8011 	mrs	r0, BASEPRI
    4a1e:	f383 8812 	msr	BASEPRI_MAX, r3
    4a22:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    4a26:	f002 fa86 	bl	6f36 <z_reschedule_irqlock>
    4a2a:	e7f3      	b.n	4a14 <z_impl_k_thread_suspend+0x64>
    4a2c:	20000a9c 	.word	0x20000a9c
    4a30:	20000abc 	.word	0x20000abc

00004a34 <k_sched_unlock>:

void k_sched_unlock(void)
{
    4a34:	b510      	push	{r4, lr}
	LOCKED(&sched_spinlock) {
    4a36:	2300      	movs	r3, #0
    4a38:	f04f 0220 	mov.w	r2, #32
    4a3c:	f3ef 8411 	mrs	r4, BASEPRI
    4a40:	f382 8812 	msr	BASEPRI_MAX, r2
    4a44:	f3bf 8f6f 	isb	sy
    4a48:	b96b      	cbnz	r3, 4a66 <k_sched_unlock+0x32>
		__ASSERT(_current->base.sched_locked != 0U, "");
		__ASSERT(!arch_is_in_isr(), "");

		++_current->base.sched_locked;
    4a4a:	4b0c      	ldr	r3, [pc, #48]	; (4a7c <k_sched_unlock+0x48>)
    4a4c:	689a      	ldr	r2, [r3, #8]
    4a4e:	7bd3      	ldrb	r3, [r2, #15]
    4a50:	3301      	adds	r3, #1
    4a52:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    4a54:	2000      	movs	r0, #0
    4a56:	f7ff fe67 	bl	4728 <update_cache>
	__asm__ volatile(
    4a5a:	f384 8811 	msr	BASEPRI, r4
    4a5e:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    4a62:	2301      	movs	r3, #1
    4a64:	e7f0      	b.n	4a48 <k_sched_unlock+0x14>
	__asm__ volatile(
    4a66:	f04f 0320 	mov.w	r3, #32
    4a6a:	f3ef 8011 	mrs	r0, BASEPRI
    4a6e:	f383 8812 	msr	BASEPRI_MAX, r3
    4a72:	f3bf 8f6f 	isb	sy
    4a76:	f002 fa5e 	bl	6f36 <z_reschedule_irqlock>
		_current, _current->base.sched_locked);

	SYS_PORT_TRACING_FUNC(k_thread, sched_unlock);

	z_reschedule_unlocked();
}
    4a7a:	bd10      	pop	{r4, pc}
    4a7c:	20000a9c 	.word	0x20000a9c

00004a80 <end_thread>:
#ifdef CONFIG_CMSIS_RTOS_V1
extern void z_thread_cmsis_status_mask_clear(struct k_thread *thread);
#endif

static void end_thread(struct k_thread *thread)
{
    4a80:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	/* We hold the lock, and the thread is known not to be running
	 * anywhere.
	 */
	if ((thread->base.thread_state & _THREAD_DEAD) == 0U) {
    4a82:	7b43      	ldrb	r3, [r0, #13]
    4a84:	f013 0f08 	tst.w	r3, #8
    4a88:	d145      	bne.n	4b16 <end_thread+0x96>
    4a8a:	4605      	mov	r5, r0
		thread->base.thread_state |= _THREAD_DEAD;
    4a8c:	f043 0308 	orr.w	r3, r3, #8
		thread->base.thread_state &= ~_THREAD_ABORTING;
    4a90:	f003 03df 	and.w	r3, r3, #223	; 0xdf
    4a94:	7343      	strb	r3, [r0, #13]
		if (z_is_thread_queued(thread)) {
    4a96:	f013 0f80 	tst.w	r3, #128	; 0x80
    4a9a:	d114      	bne.n	4ac6 <end_thread+0x46>
			dequeue_thread(&_kernel.ready_q.runq, thread);
		}
		if (thread->base.pended_on != NULL) {
    4a9c:	68ab      	ldr	r3, [r5, #8]
    4a9e:	b15b      	cbz	r3, 4ab8 <end_thread+0x38>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    4aa0:	4628      	mov	r0, r5
    4aa2:	f002 fa3c 	bl	6f1e <pended_on_thread>
    4aa6:	4629      	mov	r1, r5
    4aa8:	f002 fa5a 	bl	6f60 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    4aac:	7b6b      	ldrb	r3, [r5, #13]
    4aae:	f023 0302 	bic.w	r3, r3, #2
    4ab2:	736b      	strb	r3, [r5, #13]
	thread->base.pended_on = NULL;
    4ab4:	2300      	movs	r3, #0
    4ab6:	60ab      	str	r3, [r5, #8]
    4ab8:	f105 0018 	add.w	r0, r5, #24
    4abc:	f002 fb96 	bl	71ec <z_abort_timeout>
			unpend_thread_no_timeout(thread);
		}
		(void)z_abort_thread_timeout(thread);
		unpend_all(&thread->join_queue);
    4ac0:	f105 0758 	add.w	r7, r5, #88	; 0x58
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    4ac4:	e01c      	b.n	4b00 <end_thread+0x80>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    4ac6:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    4aca:	7343      	strb	r3, [r0, #13]
		_priq_run_remove(pq, thread);
    4acc:	4601      	mov	r1, r0
    4ace:	4812      	ldr	r0, [pc, #72]	; (4b18 <end_thread+0x98>)
    4ad0:	f002 fa46 	bl	6f60 <z_priq_dumb_remove>
}
    4ad4:	e7e2      	b.n	4a9c <end_thread+0x1c>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    4ad6:	4620      	mov	r0, r4
    4ad8:	f002 fa21 	bl	6f1e <pended_on_thread>
    4adc:	4621      	mov	r1, r4
    4ade:	f002 fa3f 	bl	6f60 <z_priq_dumb_remove>
    4ae2:	7b63      	ldrb	r3, [r4, #13]
    4ae4:	f023 0302 	bic.w	r3, r3, #2
    4ae8:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    4aea:	2600      	movs	r6, #0
    4aec:	60a6      	str	r6, [r4, #8]
    4aee:	f104 0018 	add.w	r0, r4, #24
    4af2:	f002 fb7b 	bl	71ec <z_abort_timeout>
    4af6:	f8c4 60b0 	str.w	r6, [r4, #176]	; 0xb0
		ready_thread(thread);
    4afa:	4620      	mov	r0, r4
    4afc:	f7ff feca 	bl	4894 <ready_thread>
	return list->head == list;
    4b00:	683c      	ldr	r4, [r7, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4b02:	42bc      	cmp	r4, r7
    4b04:	d001      	beq.n	4b0a <end_thread+0x8a>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    4b06:	2c00      	cmp	r4, #0
    4b08:	d1e5      	bne.n	4ad6 <end_thread+0x56>
		update_cache(1);
    4b0a:	2001      	movs	r0, #1
    4b0c:	f7ff fe0c 	bl	4728 <update_cache>

		SYS_PORT_TRACING_FUNC(k_thread, sched_abort, thread);

		z_thread_monitor_exit(thread);
    4b10:	4628      	mov	r0, r5
    4b12:	f7ff fc1d 	bl	4350 <z_thread_monitor_exit>
		z_thread_perms_all_clear(thread);
		z_object_uninit(thread->stack_obj);
		z_object_uninit(thread);
#endif
	}
}
    4b16:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    4b18:	20000abc 	.word	0x20000abc

00004b1c <z_sched_init>:
{
    4b1c:	b508      	push	{r3, lr}
	list->head = (sys_dnode_t *)list;
    4b1e:	4b05      	ldr	r3, [pc, #20]	; (4b34 <z_sched_init+0x18>)
    4b20:	f103 0220 	add.w	r2, r3, #32
    4b24:	621a      	str	r2, [r3, #32]
	list->tail = (sys_dnode_t *)list;
    4b26:	625a      	str	r2, [r3, #36]	; 0x24
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    4b28:	2100      	movs	r1, #0
    4b2a:	4608      	mov	r0, r1
    4b2c:	f7ff fd8c 	bl	4648 <k_sched_time_slice_set>
}
    4b30:	bd08      	pop	{r3, pc}
    4b32:	bf00      	nop
    4b34:	20000a9c 	.word	0x20000a9c

00004b38 <z_impl_k_yield>:
{
    4b38:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4b3a:	f04f 0320 	mov.w	r3, #32
    4b3e:	f3ef 8611 	mrs	r6, BASEPRI
    4b42:	f383 8812 	msr	BASEPRI_MAX, r3
    4b46:	f3bf 8f6f 	isb	sy
		dequeue_thread(&_kernel.ready_q.runq,
    4b4a:	4c1c      	ldr	r4, [pc, #112]	; (4bbc <z_impl_k_yield+0x84>)
    4b4c:	68a1      	ldr	r1, [r4, #8]
	thread->base.thread_state &= ~_THREAD_QUEUED;
    4b4e:	7b4b      	ldrb	r3, [r1, #13]
    4b50:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    4b54:	734b      	strb	r3, [r1, #13]
		_priq_run_remove(pq, thread);
    4b56:	f104 0720 	add.w	r7, r4, #32
    4b5a:	4638      	mov	r0, r7
    4b5c:	f002 fa00 	bl	6f60 <z_priq_dumb_remove>
	queue_thread(&_kernel.ready_q.runq, _current);
    4b60:	68a5      	ldr	r5, [r4, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    4b62:	7b6b      	ldrb	r3, [r5, #13]
    4b64:	f063 037f 	orn	r3, r3, #127	; 0x7f
    4b68:	736b      	strb	r3, [r5, #13]
	return list->head == list;
    4b6a:	6a24      	ldr	r4, [r4, #32]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4b6c:	42bc      	cmp	r4, r7
    4b6e:	d023      	beq.n	4bb8 <z_impl_k_yield+0x80>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4b70:	b16c      	cbz	r4, 4b8e <z_impl_k_yield+0x56>
		if (z_sched_prio_cmp(thread, t) > 0) {
    4b72:	4621      	mov	r1, r4
    4b74:	4628      	mov	r0, r5
    4b76:	f002 f9d4 	bl	6f22 <z_sched_prio_cmp>
    4b7a:	2800      	cmp	r0, #0
    4b7c:	dc16      	bgt.n	4bac <z_impl_k_yield+0x74>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    4b7e:	b134      	cbz	r4, 4b8e <z_impl_k_yield+0x56>
	return (node == list->tail) ? NULL : node->next;
    4b80:	4b0e      	ldr	r3, [pc, #56]	; (4bbc <z_impl_k_yield+0x84>)
    4b82:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    4b84:	429c      	cmp	r4, r3
    4b86:	d002      	beq.n	4b8e <z_impl_k_yield+0x56>
    4b88:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4b8a:	2c00      	cmp	r4, #0
    4b8c:	d1f0      	bne.n	4b70 <z_impl_k_yield+0x38>
	sys_dnode_t *const tail = list->tail;
    4b8e:	4b0b      	ldr	r3, [pc, #44]	; (4bbc <z_impl_k_yield+0x84>)
    4b90:	6a5a      	ldr	r2, [r3, #36]	; 0x24
	node->next = list;
    4b92:	f103 0120 	add.w	r1, r3, #32
    4b96:	6029      	str	r1, [r5, #0]
	node->prev = tail;
    4b98:	606a      	str	r2, [r5, #4]
	tail->next = node;
    4b9a:	6015      	str	r5, [r2, #0]
	list->tail = node;
    4b9c:	625d      	str	r5, [r3, #36]	; 0x24
	update_cache(1);
    4b9e:	2001      	movs	r0, #1
    4ba0:	f7ff fdc2 	bl	4728 <update_cache>
    4ba4:	4630      	mov	r0, r6
    4ba6:	f7fc fb7b 	bl	12a0 <arch_swap>
}
    4baa:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	sys_dnode_t *const prev = successor->prev;
    4bac:	6863      	ldr	r3, [r4, #4]
	node->prev = prev;
    4bae:	606b      	str	r3, [r5, #4]
	node->next = successor;
    4bb0:	602c      	str	r4, [r5, #0]
	prev->next = node;
    4bb2:	601d      	str	r5, [r3, #0]
	successor->prev = node;
    4bb4:	6065      	str	r5, [r4, #4]
}
    4bb6:	e7f2      	b.n	4b9e <z_impl_k_yield+0x66>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4bb8:	2400      	movs	r4, #0
    4bba:	e7d9      	b.n	4b70 <z_impl_k_yield+0x38>
    4bbc:	20000a9c 	.word	0x20000a9c

00004bc0 <z_tick_sleep>:
{
    4bc0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4bc4:	4604      	mov	r4, r0
    4bc6:	460d      	mov	r5, r1
	if (ticks == 0) {
    4bc8:	ea54 0105 	orrs.w	r1, r4, r5
    4bcc:	d037      	beq.n	4c3e <z_tick_sleep+0x7e>
	if (Z_TICK_ABS(ticks) <= 0) {
    4bce:	f06f 0101 	mvn.w	r1, #1
    4bd2:	1a0a      	subs	r2, r1, r0
    4bd4:	f04f 31ff 	mov.w	r1, #4294967295
    4bd8:	eb61 0305 	sbc.w	r3, r1, r5
    4bdc:	2a01      	cmp	r2, #1
    4bde:	f173 0300 	sbcs.w	r3, r3, #0
    4be2:	db30      	blt.n	4c46 <z_tick_sleep+0x86>
		expected_wakeup_ticks = Z_TICK_ABS(ticks);
    4be4:	f06f 0601 	mvn.w	r6, #1
    4be8:	1a36      	subs	r6, r6, r0
    4bea:	f04f 0320 	mov.w	r3, #32
    4bee:	f3ef 8811 	mrs	r8, BASEPRI
    4bf2:	f383 8812 	msr	BASEPRI_MAX, r3
    4bf6:	f3bf 8f6f 	isb	sy
	pending_current = _current;
    4bfa:	4f16      	ldr	r7, [pc, #88]	; (4c54 <z_tick_sleep+0x94>)
    4bfc:	68b8      	ldr	r0, [r7, #8]
    4bfe:	4b16      	ldr	r3, [pc, #88]	; (4c58 <z_tick_sleep+0x98>)
    4c00:	6018      	str	r0, [r3, #0]
	unready_thread(_current);
    4c02:	f7ff fea5 	bl	4950 <unready_thread>
	z_add_thread_timeout(_current, timeout);
    4c06:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    4c08:	4622      	mov	r2, r4
    4c0a:	462b      	mov	r3, r5
    4c0c:	4913      	ldr	r1, [pc, #76]	; (4c5c <z_tick_sleep+0x9c>)
    4c0e:	3018      	adds	r0, #24
    4c10:	f000 f904 	bl	4e1c <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    4c14:	68ba      	ldr	r2, [r7, #8]
	thread->base.thread_state |= _THREAD_SUSPENDED;
    4c16:	7b53      	ldrb	r3, [r2, #13]
    4c18:	f043 0310 	orr.w	r3, r3, #16
    4c1c:	7353      	strb	r3, [r2, #13]
    4c1e:	4640      	mov	r0, r8
    4c20:	f7fc fb3e 	bl	12a0 <arch_swap>
	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    4c24:	2500      	movs	r5, #0
    4c26:	f002 fb40 	bl	72aa <sys_clock_tick_get_32>
    4c2a:	1a34      	subs	r4, r6, r0
    4c2c:	f165 0500 	sbc.w	r5, r5, #0
	if (ticks > 0) {
    4c30:	2c01      	cmp	r4, #1
    4c32:	f175 0300 	sbcs.w	r3, r5, #0
    4c36:	da0a      	bge.n	4c4e <z_tick_sleep+0x8e>
	return 0;
    4c38:	2000      	movs	r0, #0
}
    4c3a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	z_impl_k_yield();
    4c3e:	f7ff ff7b 	bl	4b38 <z_impl_k_yield>
		return 0;
    4c42:	2000      	movs	r0, #0
    4c44:	e7f9      	b.n	4c3a <z_tick_sleep+0x7a>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    4c46:	f002 fb30 	bl	72aa <sys_clock_tick_get_32>
    4c4a:	1906      	adds	r6, r0, r4
    4c4c:	e7cd      	b.n	4bea <z_tick_sleep+0x2a>
		return ticks;
    4c4e:	4620      	mov	r0, r4
    4c50:	e7f3      	b.n	4c3a <z_tick_sleep+0x7a>
    4c52:	bf00      	nop
    4c54:	20000a9c 	.word	0x20000a9c
    4c58:	20000ac8 	.word	0x20000ac8
    4c5c:	00006ffd 	.word	0x00006ffd

00004c60 <z_impl_k_sleep>:
{
    4c60:	b538      	push	{r3, r4, r5, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    4c62:	f1b1 3fff 	cmp.w	r1, #4294967295
    4c66:	bf08      	it	eq
    4c68:	f1b0 3fff 	cmpeq.w	r0, #4294967295
    4c6c:	d01a      	beq.n	4ca4 <z_impl_k_sleep+0x44>
	ticks = z_tick_sleep(ticks);
    4c6e:	f7ff ffa7 	bl	4bc0 <z_tick_sleep>
	int32_t ret = k_ticks_to_ms_floor64(ticks);
    4c72:	4604      	mov	r4, r0
    4c74:	17c5      	asrs	r5, r0, #31
			return (t * to_hz + off) / from_hz;
    4c76:	0169      	lsls	r1, r5, #5
    4c78:	0143      	lsls	r3, r0, #5
    4c7a:	ea41 62d0 	orr.w	r2, r1, r0, lsr #27
    4c7e:	1a18      	subs	r0, r3, r0
    4c80:	eb62 0305 	sbc.w	r3, r2, r5
    4c84:	009a      	lsls	r2, r3, #2
    4c86:	ea42 7290 	orr.w	r2, r2, r0, lsr #30
    4c8a:	0081      	lsls	r1, r0, #2
    4c8c:	4613      	mov	r3, r2
    4c8e:	1908      	adds	r0, r1, r4
    4c90:	eb45 0303 	adc.w	r3, r5, r3
    4c94:	00da      	lsls	r2, r3, #3
    4c96:	ea42 7250 	orr.w	r2, r2, r0, lsr #29
    4c9a:	00c1      	lsls	r1, r0, #3
    4c9c:	0bc8      	lsrs	r0, r1, #15
    4c9e:	ea40 4042 	orr.w	r0, r0, r2, lsl #17
}
    4ca2:	bd38      	pop	{r3, r4, r5, pc}
		k_thread_suspend(_current);
    4ca4:	4b03      	ldr	r3, [pc, #12]	; (4cb4 <z_impl_k_sleep+0x54>)
    4ca6:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    4ca8:	f7ff fe82 	bl	49b0 <z_impl_k_thread_suspend>
		return (int32_t) K_TICKS_FOREVER;
    4cac:	f04f 30ff 	mov.w	r0, #4294967295
    4cb0:	e7f7      	b.n	4ca2 <z_impl_k_sleep+0x42>
    4cb2:	bf00      	nop
    4cb4:	20000a9c 	.word	0x20000a9c

00004cb8 <z_impl_z_current_get>:
}
    4cb8:	4b01      	ldr	r3, [pc, #4]	; (4cc0 <z_impl_z_current_get+0x8>)
    4cba:	6898      	ldr	r0, [r3, #8]
    4cbc:	4770      	bx	lr
    4cbe:	bf00      	nop
    4cc0:	20000a9c 	.word	0x20000a9c

00004cc4 <z_impl_k_is_preempt_thread>:
    4cc4:	f3ef 8305 	mrs	r3, IPSR
	return !arch_is_in_isr() && is_preempt(_current);
    4cc8:	b933      	cbnz	r3, 4cd8 <z_impl_k_is_preempt_thread+0x14>
    4cca:	4b05      	ldr	r3, [pc, #20]	; (4ce0 <z_impl_k_is_preempt_thread+0x1c>)
    4ccc:	689b      	ldr	r3, [r3, #8]
	return thread->base.preempt <= _PREEMPT_THRESHOLD;
    4cce:	89db      	ldrh	r3, [r3, #14]
	return !arch_is_in_isr() && is_preempt(_current);
    4cd0:	2b7f      	cmp	r3, #127	; 0x7f
    4cd2:	d803      	bhi.n	4cdc <z_impl_k_is_preempt_thread+0x18>
    4cd4:	2001      	movs	r0, #1
    4cd6:	4770      	bx	lr
    4cd8:	2000      	movs	r0, #0
    4cda:	4770      	bx	lr
    4cdc:	2000      	movs	r0, #0
}
    4cde:	4770      	bx	lr
    4ce0:	20000a9c 	.word	0x20000a9c

00004ce4 <z_thread_abort>:

void z_thread_abort(struct k_thread *thread)
{
    4ce4:	b538      	push	{r3, r4, r5, lr}
    4ce6:	f04f 0320 	mov.w	r3, #32
    4cea:	f3ef 8511 	mrs	r5, BASEPRI
    4cee:	f383 8812 	msr	BASEPRI_MAX, r3
    4cf2:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    4cf6:	7b43      	ldrb	r3, [r0, #13]
    4cf8:	f013 0f08 	tst.w	r3, #8
    4cfc:	d004      	beq.n	4d08 <z_thread_abort+0x24>
	__asm__ volatile(
    4cfe:	f385 8811 	msr	BASEPRI, r5
    4d02:	f3bf 8f6f 	isb	sy
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
	}
	k_spin_unlock(&sched_spinlock, key);
}
    4d06:	bd38      	pop	{r3, r4, r5, pc}
    4d08:	4604      	mov	r4, r0
	end_thread(thread);
    4d0a:	f7ff feb9 	bl	4a80 <end_thread>
	if (thread == _current && !arch_is_in_isr()) {
    4d0e:	4b08      	ldr	r3, [pc, #32]	; (4d30 <z_thread_abort+0x4c>)
    4d10:	689b      	ldr	r3, [r3, #8]
    4d12:	42a3      	cmp	r3, r4
    4d14:	d004      	beq.n	4d20 <z_thread_abort+0x3c>
    4d16:	f385 8811 	msr	BASEPRI, r5
    4d1a:	f3bf 8f6f 	isb	sy
    4d1e:	e7f2      	b.n	4d06 <z_thread_abort+0x22>
    4d20:	f3ef 8305 	mrs	r3, IPSR
    4d24:	2b00      	cmp	r3, #0
    4d26:	d1f6      	bne.n	4d16 <z_thread_abort+0x32>
    4d28:	4628      	mov	r0, r5
    4d2a:	f7fc fab9 	bl	12a0 <arch_swap>
	return ret;
    4d2e:	e7f2      	b.n	4d16 <z_thread_abort+0x32>
    4d30:	20000a9c 	.word	0x20000a9c

00004d34 <z_sched_wait>:
	return ret;
}

int z_sched_wait(struct k_spinlock *lock, k_spinlock_key_t key,
		 _wait_q_t *wait_q, k_timeout_t timeout, void **data)
{
    4d34:	b5d0      	push	{r4, r6, r7, lr}
    4d36:	b082      	sub	sp, #8
    4d38:	9c08      	ldr	r4, [sp, #32]
	int ret = z_pend_curr(lock, key, wait_q, timeout);
    4d3a:	e9dd 6706 	ldrd	r6, r7, [sp, #24]
    4d3e:	e9cd 6700 	strd	r6, r7, [sp]
    4d42:	f7ff fe21 	bl	4988 <z_pend_curr>

	if (data != NULL) {
    4d46:	b11c      	cbz	r4, 4d50 <z_sched_wait+0x1c>
		*data = _current->base.swap_data;
    4d48:	4b02      	ldr	r3, [pc, #8]	; (4d54 <z_sched_wait+0x20>)
    4d4a:	689b      	ldr	r3, [r3, #8]
    4d4c:	695b      	ldr	r3, [r3, #20]
    4d4e:	6023      	str	r3, [r4, #0]
	}
	return ret;
}
    4d50:	b002      	add	sp, #8
    4d52:	bdd0      	pop	{r4, r6, r7, pc}
    4d54:	20000a9c 	.word	0x20000a9c

00004d58 <z_data_copy>:
 * This routine copies the data section from ROM to RAM.
 *
 * @return N/A
 */
void z_data_copy(void)
{
    4d58:	b508      	push	{r3, lr}
	(void)memcpy(&__data_region_start, &__data_region_load_start,
		 __data_region_end - __data_region_start);
    4d5a:	4806      	ldr	r0, [pc, #24]	; (4d74 <z_data_copy+0x1c>)
	(void)memcpy(&__data_region_start, &__data_region_load_start,
    4d5c:	4a06      	ldr	r2, [pc, #24]	; (4d78 <z_data_copy+0x20>)
    4d5e:	1a12      	subs	r2, r2, r0
    4d60:	4906      	ldr	r1, [pc, #24]	; (4d7c <z_data_copy+0x24>)
    4d62:	f001 f929 	bl	5fb8 <memcpy>
#ifdef CONFIG_ARCH_HAS_RAMFUNC_SUPPORT
	(void)memcpy(&__ramfunc_start, &__ramfunc_load_start,
    4d66:	4a06      	ldr	r2, [pc, #24]	; (4d80 <z_data_copy+0x28>)
    4d68:	4906      	ldr	r1, [pc, #24]	; (4d84 <z_data_copy+0x2c>)
    4d6a:	4807      	ldr	r0, [pc, #28]	; (4d88 <z_data_copy+0x30>)
    4d6c:	f001 f924 	bl	5fb8 <memcpy>
#else
	(void)memcpy(&_app_smem_start, &_app_smem_rom_start,
		 _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    4d70:	bd08      	pop	{r3, pc}
    4d72:	bf00      	nop
    4d74:	20000000 	.word	0x20000000
    4d78:	200001c4 	.word	0x200001c4
    4d7c:	000079bc 	.word	0x000079bc
    4d80:	00000000 	.word	0x00000000
    4d84:	000079bc 	.word	0x000079bc
    4d88:	20000000 	.word	0x20000000

00004d8c <first>:
	return list->head == list;
    4d8c:	4b03      	ldr	r3, [pc, #12]	; (4d9c <first+0x10>)
    4d8e:	6818      	ldr	r0, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4d90:	4298      	cmp	r0, r3
    4d92:	d000      	beq.n	4d96 <first+0xa>
static struct _timeout *first(void)
{
	sys_dnode_t *t = sys_dlist_peek_head(&timeout_list);

	return t == NULL ? NULL : CONTAINER_OF(t, struct _timeout, node);
}
    4d94:	4770      	bx	lr
    4d96:	2000      	movs	r0, #0
	return t == NULL ? NULL : CONTAINER_OF(t, struct _timeout, node);
    4d98:	e7fc      	b.n	4d94 <first+0x8>
    4d9a:	bf00      	nop
    4d9c:	20000190 	.word	0x20000190

00004da0 <next>:
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    4da0:	b130      	cbz	r0, 4db0 <next+0x10>
	return (node == list->tail) ? NULL : node->next;
    4da2:	4a04      	ldr	r2, [pc, #16]	; (4db4 <next+0x14>)
    4da4:	6852      	ldr	r2, [r2, #4]
    4da6:	4290      	cmp	r0, r2
    4da8:	d001      	beq.n	4dae <next+0xe>
    4daa:	6800      	ldr	r0, [r0, #0]
    4dac:	4770      	bx	lr
    4dae:	2000      	movs	r0, #0
static struct _timeout *next(struct _timeout *t)
{
	sys_dnode_t *n = sys_dlist_peek_next(&timeout_list, &t->node);

	return n == NULL ? NULL : CONTAINER_OF(n, struct _timeout, node);
}
    4db0:	4770      	bx	lr
    4db2:	bf00      	nop
    4db4:	20000190 	.word	0x20000190

00004db8 <elapsed>:

	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
    4db8:	b508      	push	{r3, lr}
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    4dba:	4b04      	ldr	r3, [pc, #16]	; (4dcc <elapsed+0x14>)
    4dbc:	681b      	ldr	r3, [r3, #0]
    4dbe:	b10b      	cbz	r3, 4dc4 <elapsed+0xc>
    4dc0:	2000      	movs	r0, #0
}
    4dc2:	bd08      	pop	{r3, pc}
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    4dc4:	f7fe f960 	bl	3088 <sys_clock_elapsed>
    4dc8:	e7fb      	b.n	4dc2 <elapsed+0xa>
    4dca:	bf00      	nop
    4dcc:	20000ad4 	.word	0x20000ad4

00004dd0 <next_timeout>:

static int32_t next_timeout(void)
{
    4dd0:	b510      	push	{r4, lr}
	struct _timeout *to = first();
    4dd2:	f7ff ffdb 	bl	4d8c <first>
    4dd6:	4604      	mov	r4, r0
	int32_t ticks_elapsed = elapsed();
    4dd8:	f7ff ffee 	bl	4db8 <elapsed>
	int32_t ret = to == NULL ? MAX_WAIT
    4ddc:	b18c      	cbz	r4, 4e02 <next_timeout+0x32>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    4dde:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    4de2:	1a12      	subs	r2, r2, r0
    4de4:	eb63 73e0 	sbc.w	r3, r3, r0, asr #31
	int32_t ret = to == NULL ? MAX_WAIT
    4de8:	2a01      	cmp	r2, #1
    4dea:	f173 0100 	sbcs.w	r1, r3, #0
    4dee:	db11      	blt.n	4e14 <next_timeout+0x44>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    4df0:	4610      	mov	r0, r2
    4df2:	f1b2 4f00 	cmp.w	r2, #2147483648	; 0x80000000
    4df6:	f173 0300 	sbcs.w	r3, r3, #0
    4dfa:	db04      	blt.n	4e06 <next_timeout+0x36>
    4dfc:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    4e00:	e001      	b.n	4e06 <next_timeout+0x36>
	int32_t ret = to == NULL ? MAX_WAIT
    4e02:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    4e06:	4b04      	ldr	r3, [pc, #16]	; (4e18 <next_timeout+0x48>)
    4e08:	691b      	ldr	r3, [r3, #16]
    4e0a:	b113      	cbz	r3, 4e12 <next_timeout+0x42>
    4e0c:	4283      	cmp	r3, r0
    4e0e:	da00      	bge.n	4e12 <next_timeout+0x42>
		ret = _current_cpu->slice_ticks;
    4e10:	4618      	mov	r0, r3
	}
#endif
	return ret;
}
    4e12:	bd10      	pop	{r4, pc}
	int32_t ret = to == NULL ? MAX_WAIT
    4e14:	2000      	movs	r0, #0
    4e16:	e7f6      	b.n	4e06 <next_timeout+0x36>
    4e18:	20000a9c 	.word	0x20000a9c

00004e1c <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
    4e1c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4e20:	b083      	sub	sp, #12
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    4e22:	f1b3 3fff 	cmp.w	r3, #4294967295
    4e26:	bf08      	it	eq
    4e28:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    4e2c:	f000 8096 	beq.w	4f5c <z_add_timeout+0x140>
    4e30:	4682      	mov	sl, r0
    4e32:	4614      	mov	r4, r2
    4e34:	461d      	mov	r5, r3
#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    4e36:	6081      	str	r1, [r0, #8]

	LOCKED(&timeout_lock) {
    4e38:	2300      	movs	r3, #0
	__asm__ volatile(
    4e3a:	f04f 0220 	mov.w	r2, #32
    4e3e:	f3ef 8b11 	mrs	fp, BASEPRI
    4e42:	f382 8812 	msr	BASEPRI_MAX, r2
    4e46:	f3bf 8f6f 	isb	sy
    4e4a:	e02e      	b.n	4eaa <z_add_timeout+0x8e>

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
		    Z_TICK_ABS(timeout.ticks) >= 0) {
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;

			to->dticks = MAX(1, ticks);
    4e4c:	2201      	movs	r2, #1
    4e4e:	2300      	movs	r3, #0
    4e50:	e04b      	b.n	4eea <z_add_timeout+0xce>
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
    4e52:	f7ff ffb1 	bl	4db8 <elapsed>
    4e56:	1822      	adds	r2, r4, r0
    4e58:	eb45 73e0 	adc.w	r3, r5, r0, asr #31
    4e5c:	3201      	adds	r2, #1
    4e5e:	f143 0300 	adc.w	r3, r3, #0
    4e62:	f8ca 2010 	str.w	r2, [sl, #16]
    4e66:	f8ca 3014 	str.w	r3, [sl, #20]
    4e6a:	e042      	b.n	4ef2 <z_add_timeout+0xd6>
		}

		for (t = first(); t != NULL; t = next(t)) {
			if (t->dticks > to->dticks) {
				t->dticks -= to->dticks;
    4e6c:	9b00      	ldr	r3, [sp, #0]
    4e6e:	1ac2      	subs	r2, r0, r3
    4e70:	9b01      	ldr	r3, [sp, #4]
    4e72:	eb61 0303 	sbc.w	r3, r1, r3
    4e76:	f8cc 2010 	str.w	r2, [ip, #16]
    4e7a:	f8cc 3014 	str.w	r3, [ip, #20]
	sys_dnode_t *const prev = successor->prev;
    4e7e:	f8dc 3004 	ldr.w	r3, [ip, #4]
	node->prev = prev;
    4e82:	f8ca 3004 	str.w	r3, [sl, #4]
	node->next = successor;
    4e86:	f8ca c000 	str.w	ip, [sl]
	prev->next = node;
    4e8a:	f8c3 a000 	str.w	sl, [r3]
	successor->prev = node;
    4e8e:	f8cc a004 	str.w	sl, [ip, #4]
				break;
			}
			to->dticks -= t->dticks;
		}

		if (t == NULL) {
    4e92:	f1bc 0f00 	cmp.w	ip, #0
    4e96:	d049      	beq.n	4f2c <z_add_timeout+0x110>
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    4e98:	f7ff ff78 	bl	4d8c <first>
    4e9c:	4582      	cmp	sl, r0
    4e9e:	d050      	beq.n	4f42 <z_add_timeout+0x126>
	__asm__ volatile(
    4ea0:	f38b 8811 	msr	BASEPRI, fp
    4ea4:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    4ea8:	2301      	movs	r3, #1
    4eaa:	2b00      	cmp	r3, #0
    4eac:	d156      	bne.n	4f5c <z_add_timeout+0x140>
		    Z_TICK_ABS(timeout.ticks) >= 0) {
    4eae:	f06f 0301 	mvn.w	r3, #1
    4eb2:	ebb3 0804 	subs.w	r8, r3, r4
    4eb6:	f04f 30ff 	mov.w	r0, #4294967295
    4eba:	eb60 0905 	sbc.w	r9, r0, r5
		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    4ebe:	f1b8 0f00 	cmp.w	r8, #0
    4ec2:	f179 0300 	sbcs.w	r3, r9, #0
    4ec6:	dbc4      	blt.n	4e52 <z_add_timeout+0x36>
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    4ec8:	4a26      	ldr	r2, [pc, #152]	; (4f64 <z_add_timeout+0x148>)
    4eca:	6813      	ldr	r3, [r2, #0]
    4ecc:	6852      	ldr	r2, [r2, #4]
    4ece:	18e3      	adds	r3, r4, r3
    4ed0:	eb45 0202 	adc.w	r2, r5, r2
    4ed4:	f06f 0101 	mvn.w	r1, #1
    4ed8:	1ace      	subs	r6, r1, r3
    4eda:	eb60 0702 	sbc.w	r7, r0, r2
			to->dticks = MAX(1, ticks);
    4ede:	4632      	mov	r2, r6
    4ee0:	463b      	mov	r3, r7
    4ee2:	2e01      	cmp	r6, #1
    4ee4:	f177 0100 	sbcs.w	r1, r7, #0
    4ee8:	dbb0      	blt.n	4e4c <z_add_timeout+0x30>
    4eea:	f8ca 2010 	str.w	r2, [sl, #16]
    4eee:	f8ca 3014 	str.w	r3, [sl, #20]
		for (t = first(); t != NULL; t = next(t)) {
    4ef2:	f7ff ff4b 	bl	4d8c <first>
    4ef6:	4684      	mov	ip, r0
    4ef8:	f1bc 0f00 	cmp.w	ip, #0
    4efc:	d0c9      	beq.n	4e92 <z_add_timeout+0x76>
			if (t->dticks > to->dticks) {
    4efe:	e9dc 0104 	ldrd	r0, r1, [ip, #16]
    4f02:	e9da 2304 	ldrd	r2, r3, [sl, #16]
    4f06:	e9cd 2300 	strd	r2, r3, [sp]
    4f0a:	4282      	cmp	r2, r0
    4f0c:	418b      	sbcs	r3, r1
    4f0e:	dbad      	blt.n	4e6c <z_add_timeout+0x50>
			to->dticks -= t->dticks;
    4f10:	9b00      	ldr	r3, [sp, #0]
    4f12:	1a1a      	subs	r2, r3, r0
    4f14:	9b01      	ldr	r3, [sp, #4]
    4f16:	eb63 0301 	sbc.w	r3, r3, r1
    4f1a:	f8ca 2010 	str.w	r2, [sl, #16]
    4f1e:	f8ca 3014 	str.w	r3, [sl, #20]
		for (t = first(); t != NULL; t = next(t)) {
    4f22:	4660      	mov	r0, ip
    4f24:	f7ff ff3c 	bl	4da0 <next>
    4f28:	4684      	mov	ip, r0
    4f2a:	e7e5      	b.n	4ef8 <z_add_timeout+0xdc>
	sys_dnode_t *const tail = list->tail;
    4f2c:	4b0e      	ldr	r3, [pc, #56]	; (4f68 <z_add_timeout+0x14c>)
    4f2e:	685a      	ldr	r2, [r3, #4]
	node->next = list;
    4f30:	f8ca 3000 	str.w	r3, [sl]
	node->prev = tail;
    4f34:	f8ca 2004 	str.w	r2, [sl, #4]
	tail->next = node;
    4f38:	f8c2 a000 	str.w	sl, [r2]
	list->tail = node;
    4f3c:	f8c3 a004 	str.w	sl, [r3, #4]
}
    4f40:	e7aa      	b.n	4e98 <z_add_timeout+0x7c>
			 * last announcement, and slice_ticks is based
			 * on that. It means that the time remaining for
			 * the next announcement can be less than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    4f42:	f7ff ff45 	bl	4dd0 <next_timeout>

			if (next_time == 0 ||
    4f46:	4603      	mov	r3, r0
    4f48:	b118      	cbz	r0, 4f52 <z_add_timeout+0x136>
			    _current_cpu->slice_ticks != next_time) {
    4f4a:	4a08      	ldr	r2, [pc, #32]	; (4f6c <z_add_timeout+0x150>)
    4f4c:	6912      	ldr	r2, [r2, #16]
			if (next_time == 0 ||
    4f4e:	4282      	cmp	r2, r0
    4f50:	d0a6      	beq.n	4ea0 <z_add_timeout+0x84>
				sys_clock_set_timeout(next_time, false);
    4f52:	2100      	movs	r1, #0
    4f54:	4618      	mov	r0, r3
    4f56:	f7fe f863 	bl	3020 <sys_clock_set_timeout>
    4f5a:	e7a1      	b.n	4ea0 <z_add_timeout+0x84>
#else
			sys_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    4f5c:	b003      	add	sp, #12
    4f5e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    4f62:	bf00      	nop
    4f64:	20000358 	.word	0x20000358
    4f68:	20000190 	.word	0x20000190
    4f6c:	20000a9c 	.word	0x20000a9c

00004f70 <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    4f70:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4f72:	4604      	mov	r4, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    4f74:	f7ff fc42 	bl	47fc <z_time_slice>
	__asm__ volatile(
    4f78:	f04f 0320 	mov.w	r3, #32
    4f7c:	f3ef 8511 	mrs	r5, BASEPRI
    4f80:	f383 8812 	msr	BASEPRI_MAX, r3
    4f84:	f3bf 8f6f 	isb	sy
#endif

	k_spinlock_key_t key = k_spin_lock(&timeout_lock);

	announce_remaining = ticks;
    4f88:	4b28      	ldr	r3, [pc, #160]	; (502c <sys_clock_announce+0xbc>)
    4f8a:	601c      	str	r4, [r3, #0]

	while (first() != NULL && first()->dticks <= announce_remaining) {
    4f8c:	f7ff fefe 	bl	4d8c <first>
    4f90:	4604      	mov	r4, r0
    4f92:	b350      	cbz	r0, 4fea <sys_clock_announce+0x7a>
    4f94:	e9d0 6704 	ldrd	r6, r7, [r0, #16]
    4f98:	4b24      	ldr	r3, [pc, #144]	; (502c <sys_clock_announce+0xbc>)
    4f9a:	681b      	ldr	r3, [r3, #0]
    4f9c:	17d9      	asrs	r1, r3, #31
    4f9e:	42b3      	cmp	r3, r6
    4fa0:	eb71 0207 	sbcs.w	r2, r1, r7
    4fa4:	db21      	blt.n	4fea <sys_clock_announce+0x7a>
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    4fa6:	4a22      	ldr	r2, [pc, #136]	; (5030 <sys_clock_announce+0xc0>)
    4fa8:	e9d2 0100 	ldrd	r0, r1, [r2]
    4fac:	1980      	adds	r0, r0, r6
    4fae:	eb41 71e6 	adc.w	r1, r1, r6, asr #31
    4fb2:	e9c2 0100 	strd	r0, r1, [r2]
		announce_remaining -= dt;
    4fb6:	1b9b      	subs	r3, r3, r6
    4fb8:	4a1c      	ldr	r2, [pc, #112]	; (502c <sys_clock_announce+0xbc>)
    4fba:	6013      	str	r3, [r2, #0]
		t->dticks = 0;
    4fbc:	2200      	movs	r2, #0
    4fbe:	2300      	movs	r3, #0
    4fc0:	e9c4 2304 	strd	r2, r3, [r4, #16]
		remove_timeout(t);
    4fc4:	4620      	mov	r0, r4
    4fc6:	f002 f8fa 	bl	71be <remove_timeout>
	__asm__ volatile(
    4fca:	f385 8811 	msr	BASEPRI, r5
    4fce:	f3bf 8f6f 	isb	sy

		k_spin_unlock(&timeout_lock, key);
		t->fn(t);
    4fd2:	68a3      	ldr	r3, [r4, #8]
    4fd4:	4620      	mov	r0, r4
    4fd6:	4798      	blx	r3
	__asm__ volatile(
    4fd8:	f04f 0320 	mov.w	r3, #32
    4fdc:	f3ef 8511 	mrs	r5, BASEPRI
    4fe0:	f383 8812 	msr	BASEPRI_MAX, r3
    4fe4:	f3bf 8f6f 	isb	sy
    4fe8:	e7d0      	b.n	4f8c <sys_clock_announce+0x1c>
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
    4fea:	b144      	cbz	r4, 4ffe <sys_clock_announce+0x8e>
		first()->dticks -= announce_remaining;
    4fec:	4b0f      	ldr	r3, [pc, #60]	; (502c <sys_clock_announce+0xbc>)
    4fee:	6819      	ldr	r1, [r3, #0]
    4ff0:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    4ff4:	1a52      	subs	r2, r2, r1
    4ff6:	eb63 73e1 	sbc.w	r3, r3, r1, asr #31
    4ffa:	e9c4 2304 	strd	r2, r3, [r4, #16]
	}

	curr_tick += announce_remaining;
    4ffe:	480c      	ldr	r0, [pc, #48]	; (5030 <sys_clock_announce+0xc0>)
    5000:	490a      	ldr	r1, [pc, #40]	; (502c <sys_clock_announce+0xbc>)
    5002:	680c      	ldr	r4, [r1, #0]
    5004:	e9d0 2300 	ldrd	r2, r3, [r0]
    5008:	1912      	adds	r2, r2, r4
    500a:	eb43 73e4 	adc.w	r3, r3, r4, asr #31
    500e:	e9c0 2300 	strd	r2, r3, [r0]
	announce_remaining = 0;
    5012:	2400      	movs	r4, #0
    5014:	600c      	str	r4, [r1, #0]

	sys_clock_set_timeout(next_timeout(), false);
    5016:	f7ff fedb 	bl	4dd0 <next_timeout>
    501a:	4621      	mov	r1, r4
    501c:	f7fe f800 	bl	3020 <sys_clock_set_timeout>
	__asm__ volatile(
    5020:	f385 8811 	msr	BASEPRI, r5
    5024:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    5028:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    502a:	bf00      	nop
    502c:	20000ad4 	.word	0x20000ad4
    5030:	20000358 	.word	0x20000358

00005034 <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    5034:	b510      	push	{r4, lr}
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
    5036:	2100      	movs	r1, #0
	__asm__ volatile(
    5038:	f04f 0320 	mov.w	r3, #32
    503c:	f3ef 8411 	mrs	r4, BASEPRI
    5040:	f383 8812 	msr	BASEPRI_MAX, r3
    5044:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;
    5048:	2200      	movs	r2, #0
    504a:	2300      	movs	r3, #0
	LOCKED(&timeout_lock) {
    504c:	b969      	cbnz	r1, 506a <sys_clock_tick_get+0x36>
		t = curr_tick + sys_clock_elapsed();
    504e:	f7fe f81b 	bl	3088 <sys_clock_elapsed>
    5052:	4b07      	ldr	r3, [pc, #28]	; (5070 <sys_clock_tick_get+0x3c>)
    5054:	e9d3 2300 	ldrd	r2, r3, [r3]
    5058:	1812      	adds	r2, r2, r0
    505a:	f143 0300 	adc.w	r3, r3, #0
	__asm__ volatile(
    505e:	f384 8811 	msr	BASEPRI, r4
    5062:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    5066:	2101      	movs	r1, #1
    5068:	e7f0      	b.n	504c <sys_clock_tick_get+0x18>
	}
	return t;
}
    506a:	4610      	mov	r0, r2
    506c:	4619      	mov	r1, r3
    506e:	bd10      	pop	{r4, pc}
    5070:	20000358 	.word	0x20000358

00005074 <z_impl_k_poll>:
	return 0;
}

int z_impl_k_poll(struct k_poll_event *events, int num_events,
		  k_timeout_t timeout)
{
    5074:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    5078:	b08d      	sub	sp, #52	; 0x34
    507a:	4605      	mov	r5, r0
    507c:	9107      	str	r1, [sp, #28]
    507e:	9202      	str	r2, [sp, #8]
    5080:	9303      	str	r3, [sp, #12]
	int events_registered;
	k_spinlock_key_t key;
	struct z_poller *poller = &_current->poller;
    5082:	4ba4      	ldr	r3, [pc, #656]	; (5314 <z_impl_k_poll+0x2a0>)
    5084:	f8d3 9008 	ldr.w	r9, [r3, #8]
    5088:	f109 0760 	add.w	r7, r9, #96	; 0x60

	poller->is_polling = true;
    508c:	2301      	movs	r3, #1
    508e:	f889 3060 	strb.w	r3, [r9, #96]	; 0x60
	poller->mode = MODE_POLL;
    5092:	f889 3061 	strb.w	r3, [r9, #97]	; 0x61
	__ASSERT(events != NULL, "NULL events\n");
	__ASSERT(num_events >= 0, "<0 events\n");

	SYS_PORT_TRACING_FUNC_ENTER(k_poll_api, poll, events);

	events_registered = register_events(events, num_events, poller,
    5096:	e9dd 1202 	ldrd	r1, r2, [sp, #8]
    509a:	4613      	mov	r3, r2
    509c:	430b      	orrs	r3, r1
    509e:	bf0c      	ite	eq
    50a0:	2301      	moveq	r3, #1
    50a2:	2300      	movne	r3, #0
    50a4:	9306      	str	r3, [sp, #24]
	for (int ii = 0; ii < num_events; ii++) {
    50a6:	2600      	movs	r6, #0
	int events_registered = 0;
    50a8:	46b3      	mov	fp, r6
	for (int ii = 0; ii < num_events; ii++) {
    50aa:	e02e      	b.n	510a <z_impl_k_poll+0x96>
		if (k_sem_count_get(event->sem) > 0U) {
    50ac:	6923      	ldr	r3, [r4, #16]
	return sem->count;
    50ae:	689b      	ldr	r3, [r3, #8]
    50b0:	b1c3      	cbz	r3, 50e4 <z_impl_k_poll+0x70>
			*state = K_POLL_STATE_SEM_AVAILABLE;
    50b2:	2302      	movs	r3, #2
    50b4:	9305      	str	r3, [sp, #20]
			return true;
    50b6:	2301      	movs	r3, #1
    50b8:	e014      	b.n	50e4 <z_impl_k_poll+0x70>
		if (!k_queue_is_empty(event->queue)) {
    50ba:	6923      	ldr	r3, [r4, #16]
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_sfnode_t *sys_sflist_peek_head(sys_sflist_t *list)
{
	return list->head;
    50bc:	681b      	ldr	r3, [r3, #0]
    50be:	b18b      	cbz	r3, 50e4 <z_impl_k_poll+0x70>
			*state = K_POLL_STATE_FIFO_DATA_AVAILABLE;
    50c0:	2304      	movs	r3, #4
    50c2:	9305      	str	r3, [sp, #20]
			return true;
    50c4:	2301      	movs	r3, #1
    50c6:	e00d      	b.n	50e4 <z_impl_k_poll+0x70>
		if (event->signal->signaled != 0U) {
    50c8:	6923      	ldr	r3, [r4, #16]
    50ca:	689b      	ldr	r3, [r3, #8]
    50cc:	b153      	cbz	r3, 50e4 <z_impl_k_poll+0x70>
			*state = K_POLL_STATE_SIGNALED;
    50ce:	2301      	movs	r3, #1
    50d0:	9305      	str	r3, [sp, #20]
    50d2:	e007      	b.n	50e4 <z_impl_k_poll+0x70>
		if (event->msgq->used_msgs > 0) {
    50d4:	6923      	ldr	r3, [r4, #16]
    50d6:	6a1b      	ldr	r3, [r3, #32]
    50d8:	b123      	cbz	r3, 50e4 <z_impl_k_poll+0x70>
			*state = K_POLL_STATE_MSGQ_DATA_AVAILABLE;
    50da:	2310      	movs	r3, #16
    50dc:	9305      	str	r3, [sp, #20]
			return true;
    50de:	2301      	movs	r3, #1
    50e0:	e000      	b.n	50e4 <z_impl_k_poll+0x70>
	switch (event->type) {
    50e2:	2300      	movs	r3, #0
		if (is_condition_met(&events[ii], &state)) {
    50e4:	2b00      	cmp	r3, #0
    50e6:	d03d      	beq.n	5164 <z_impl_k_poll+0xf0>
	event->poller = NULL;
    50e8:	2100      	movs	r1, #0
    50ea:	60a1      	str	r1, [r4, #8]
	event->state |= state;
    50ec:	68e3      	ldr	r3, [r4, #12]
    50ee:	f3c3 3245 	ubfx	r2, r3, #13, #6
    50f2:	9805      	ldr	r0, [sp, #20]
    50f4:	4302      	orrs	r2, r0
    50f6:	f362 3352 	bfi	r3, r2, #13, #6
    50fa:	60e3      	str	r3, [r4, #12]
			poller->is_polling = false;
    50fc:	7039      	strb	r1, [r7, #0]
    50fe:	9b08      	ldr	r3, [sp, #32]
    5100:	f383 8811 	msr	BASEPRI, r3
    5104:	f3bf 8f6f 	isb	sy
	for (int ii = 0; ii < num_events; ii++) {
    5108:	3601      	adds	r6, #1
    510a:	9b07      	ldr	r3, [sp, #28]
    510c:	42b3      	cmp	r3, r6
    510e:	f340 81bf 	ble.w	5490 <z_impl_k_poll+0x41c>
	__asm__ volatile(
    5112:	f04f 0320 	mov.w	r3, #32
    5116:	f3ef 8211 	mrs	r2, BASEPRI
    511a:	f383 8812 	msr	BASEPRI_MAX, r3
    511e:	f3bf 8f6f 	isb	sy
    5122:	9208      	str	r2, [sp, #32]
		if (is_condition_met(&events[ii], &state)) {
    5124:	eb06 0486 	add.w	r4, r6, r6, lsl #2
    5128:	00a3      	lsls	r3, r4, #2
    512a:	9309      	str	r3, [sp, #36]	; 0x24
    512c:	eb05 0484 	add.w	r4, r5, r4, lsl #2
	switch (event->type) {
    5130:	7b63      	ldrb	r3, [r4, #13]
    5132:	f003 031f 	and.w	r3, r3, #31
    5136:	3b01      	subs	r3, #1
    5138:	2b07      	cmp	r3, #7
    513a:	d8d2      	bhi.n	50e2 <z_impl_k_poll+0x6e>
    513c:	a201      	add	r2, pc, #4	; (adr r2, 5144 <z_impl_k_poll+0xd0>)
    513e:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
    5142:	bf00      	nop
    5144:	000050c9 	.word	0x000050c9
    5148:	000050ad 	.word	0x000050ad
    514c:	000050e3 	.word	0x000050e3
    5150:	000050bb 	.word	0x000050bb
    5154:	000050e3 	.word	0x000050e3
    5158:	000050e3 	.word	0x000050e3
    515c:	000050e3 	.word	0x000050e3
    5160:	000050d5 	.word	0x000050d5
		} else if (!just_check && poller->is_polling) {
    5164:	9b06      	ldr	r3, [sp, #24]
    5166:	2b00      	cmp	r3, #0
    5168:	d1c9      	bne.n	50fe <z_impl_k_poll+0x8a>
    516a:	783b      	ldrb	r3, [r7, #0]
    516c:	2b00      	cmp	r3, #0
    516e:	d0c6      	beq.n	50fe <z_impl_k_poll+0x8a>
	switch (event->type) {
    5170:	7b63      	ldrb	r3, [r4, #13]
    5172:	f003 031f 	and.w	r3, r3, #31
    5176:	3b01      	subs	r3, #1
    5178:	2b07      	cmp	r3, #7
    517a:	d846      	bhi.n	520a <z_impl_k_poll+0x196>
    517c:	e8df f013 	tbh	[pc, r3, lsl #1]
    5180:	000800cc 	.word	0x000800cc
    5184:	006a0045 	.word	0x006a0045
    5188:	00450045 	.word	0x00450045
    518c:	01290045 	.word	0x01290045
		add_event(&event->sem->poll_events, event, poller);
    5190:	f8d4 a010 	ldr.w	sl, [r4, #16]
    5194:	f10a 0810 	add.w	r8, sl, #16
	return list->head == list;
    5198:	f8da 3010 	ldr.w	r3, [sl, #16]
	return sys_dlist_is_empty(list) ? NULL : list->tail;
    519c:	4598      	cmp	r8, r3
    519e:	d02b      	beq.n	51f8 <z_impl_k_poll+0x184>
    51a0:	f8d8 3004 	ldr.w	r3, [r8, #4]
	if ((pending == NULL) ||
    51a4:	b343      	cbz	r3, 51f8 <z_impl_k_poll+0x184>
		(z_sched_prio_cmp(poller_thread(pending->poller),
    51a6:	6898      	ldr	r0, [r3, #8]
    51a8:	f002 f889 	bl	72be <poller_thread>
    51ac:	900b      	str	r0, [sp, #44]	; 0x2c
    51ae:	4638      	mov	r0, r7
    51b0:	f002 f885 	bl	72be <poller_thread>
    51b4:	4601      	mov	r1, r0
    51b6:	900a      	str	r0, [sp, #40]	; 0x28
    51b8:	980b      	ldr	r0, [sp, #44]	; 0x2c
    51ba:	f001 feb2 	bl	6f22 <z_sched_prio_cmp>
	if ((pending == NULL) ||
    51be:	2800      	cmp	r0, #0
    51c0:	dc1a      	bgt.n	51f8 <z_impl_k_poll+0x184>
	return list->head == list;
    51c2:	f8da a010 	ldr.w	sl, [sl, #16]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    51c6:	45d0      	cmp	r8, sl
    51c8:	d02f      	beq.n	522a <z_impl_k_poll+0x1b6>
    51ca:	4653      	mov	r3, sl
    51cc:	46a2      	mov	sl, r4
    51ce:	461c      	mov	r4, r3
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    51d0:	b38c      	cbz	r4, 5236 <z_impl_k_poll+0x1c2>
		if (z_sched_prio_cmp(poller_thread(poller),
    51d2:	68a0      	ldr	r0, [r4, #8]
    51d4:	f002 f873 	bl	72be <poller_thread>
    51d8:	4601      	mov	r1, r0
    51da:	980a      	ldr	r0, [sp, #40]	; 0x28
    51dc:	f001 fea1 	bl	6f22 <z_sched_prio_cmp>
    51e0:	2800      	cmp	r0, #0
    51e2:	dc16      	bgt.n	5212 <z_impl_k_poll+0x19e>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    51e4:	b34c      	cbz	r4, 523a <z_impl_k_poll+0x1c6>
	return (node == list->tail) ? NULL : node->next;
    51e6:	f8d8 3004 	ldr.w	r3, [r8, #4]
    51ea:	429c      	cmp	r4, r3
    51ec:	d030      	beq.n	5250 <z_impl_k_poll+0x1dc>
    51ee:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    51f0:	2c00      	cmp	r4, #0
    51f2:	d1ed      	bne.n	51d0 <z_impl_k_poll+0x15c>
    51f4:	4654      	mov	r4, sl
    51f6:	e021      	b.n	523c <z_impl_k_poll+0x1c8>
	sys_dnode_t *const tail = list->tail;
    51f8:	f8d8 3004 	ldr.w	r3, [r8, #4]
	node->next = list;
    51fc:	9a09      	ldr	r2, [sp, #36]	; 0x24
    51fe:	f845 8002 	str.w	r8, [r5, r2]
	node->prev = tail;
    5202:	6063      	str	r3, [r4, #4]
	tail->next = node;
    5204:	601c      	str	r4, [r3, #0]
	list->tail = node;
    5206:	f8c8 4004 	str.w	r4, [r8, #4]
	event->poller = poller;
    520a:	60a7      	str	r7, [r4, #8]
			events_registered += 1;
    520c:	f10b 0b01 	add.w	fp, fp, #1
    5210:	e775      	b.n	50fe <z_impl_k_poll+0x8a>
    5212:	4623      	mov	r3, r4
    5214:	4654      	mov	r4, sl
    5216:	469a      	mov	sl, r3
	sys_dnode_t *const prev = successor->prev;
    5218:	685b      	ldr	r3, [r3, #4]
	node->prev = prev;
    521a:	6063      	str	r3, [r4, #4]
	node->next = successor;
    521c:	9a09      	ldr	r2, [sp, #36]	; 0x24
    521e:	f845 a002 	str.w	sl, [r5, r2]
	prev->next = node;
    5222:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    5224:	f8ca 4004 	str.w	r4, [sl, #4]
			return;
    5228:	e7ef      	b.n	520a <z_impl_k_poll+0x196>
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    522a:	f04f 0a00 	mov.w	sl, #0
    522e:	4653      	mov	r3, sl
    5230:	46a2      	mov	sl, r4
    5232:	461c      	mov	r4, r3
    5234:	e7cc      	b.n	51d0 <z_impl_k_poll+0x15c>
    5236:	4654      	mov	r4, sl
    5238:	e000      	b.n	523c <z_impl_k_poll+0x1c8>
    523a:	4654      	mov	r4, sl
	sys_dnode_t *const tail = list->tail;
    523c:	f8d8 3004 	ldr.w	r3, [r8, #4]
	node->next = list;
    5240:	9a09      	ldr	r2, [sp, #36]	; 0x24
    5242:	f845 8002 	str.w	r8, [r5, r2]
	node->prev = tail;
    5246:	6063      	str	r3, [r4, #4]
	tail->next = node;
    5248:	601c      	str	r4, [r3, #0]
	list->tail = node;
    524a:	f8c8 4004 	str.w	r4, [r8, #4]
}
    524e:	e7dc      	b.n	520a <z_impl_k_poll+0x196>
    5250:	4654      	mov	r4, sl
    5252:	e7f3      	b.n	523c <z_impl_k_poll+0x1c8>
		add_event(&event->queue->poll_events, event, poller);
    5254:	f8d4 a010 	ldr.w	sl, [r4, #16]
    5258:	f10a 0810 	add.w	r8, sl, #16
	return list->head == list;
    525c:	f8da 3010 	ldr.w	r3, [sl, #16]
	return sys_dlist_is_empty(list) ? NULL : list->tail;
    5260:	4598      	cmp	r8, r3
    5262:	d02b      	beq.n	52bc <z_impl_k_poll+0x248>
    5264:	f8d8 3004 	ldr.w	r3, [r8, #4]
	if ((pending == NULL) ||
    5268:	b343      	cbz	r3, 52bc <z_impl_k_poll+0x248>
		(z_sched_prio_cmp(poller_thread(pending->poller),
    526a:	6898      	ldr	r0, [r3, #8]
    526c:	f002 f827 	bl	72be <poller_thread>
    5270:	900b      	str	r0, [sp, #44]	; 0x2c
    5272:	4638      	mov	r0, r7
    5274:	f002 f823 	bl	72be <poller_thread>
    5278:	4601      	mov	r1, r0
    527a:	900a      	str	r0, [sp, #40]	; 0x28
    527c:	980b      	ldr	r0, [sp, #44]	; 0x2c
    527e:	f001 fe50 	bl	6f22 <z_sched_prio_cmp>
	if ((pending == NULL) ||
    5282:	2800      	cmp	r0, #0
    5284:	dc1a      	bgt.n	52bc <z_impl_k_poll+0x248>
	return list->head == list;
    5286:	f8da a010 	ldr.w	sl, [sl, #16]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    528a:	45d0      	cmp	r8, sl
    528c:	d02c      	beq.n	52e8 <z_impl_k_poll+0x274>
    528e:	4653      	mov	r3, sl
    5290:	46a2      	mov	sl, r4
    5292:	461c      	mov	r4, r3
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    5294:	b374      	cbz	r4, 52f4 <z_impl_k_poll+0x280>
		if (z_sched_prio_cmp(poller_thread(poller),
    5296:	68a0      	ldr	r0, [r4, #8]
    5298:	f002 f811 	bl	72be <poller_thread>
    529c:	4601      	mov	r1, r0
    529e:	980a      	ldr	r0, [sp, #40]	; 0x28
    52a0:	f001 fe3f 	bl	6f22 <z_sched_prio_cmp>
    52a4:	2800      	cmp	r0, #0
    52a6:	dc13      	bgt.n	52d0 <z_impl_k_poll+0x25c>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    52a8:	b334      	cbz	r4, 52f8 <z_impl_k_poll+0x284>
	return (node == list->tail) ? NULL : node->next;
    52aa:	f8d8 3004 	ldr.w	r3, [r8, #4]
    52ae:	429c      	cmp	r4, r3
    52b0:	d02d      	beq.n	530e <z_impl_k_poll+0x29a>
    52b2:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    52b4:	2c00      	cmp	r4, #0
    52b6:	d1ed      	bne.n	5294 <z_impl_k_poll+0x220>
    52b8:	4654      	mov	r4, sl
    52ba:	e01e      	b.n	52fa <z_impl_k_poll+0x286>
	sys_dnode_t *const tail = list->tail;
    52bc:	f8d8 3004 	ldr.w	r3, [r8, #4]
	node->next = list;
    52c0:	9a09      	ldr	r2, [sp, #36]	; 0x24
    52c2:	f845 8002 	str.w	r8, [r5, r2]
	node->prev = tail;
    52c6:	6063      	str	r3, [r4, #4]
	tail->next = node;
    52c8:	601c      	str	r4, [r3, #0]
	list->tail = node;
    52ca:	f8c8 4004 	str.w	r4, [r8, #4]
		return;
    52ce:	e79c      	b.n	520a <z_impl_k_poll+0x196>
    52d0:	4623      	mov	r3, r4
    52d2:	4654      	mov	r4, sl
    52d4:	469a      	mov	sl, r3
	sys_dnode_t *const prev = successor->prev;
    52d6:	685b      	ldr	r3, [r3, #4]
	node->prev = prev;
    52d8:	6063      	str	r3, [r4, #4]
	node->next = successor;
    52da:	9a09      	ldr	r2, [sp, #36]	; 0x24
    52dc:	f845 a002 	str.w	sl, [r5, r2]
	prev->next = node;
    52e0:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    52e2:	f8ca 4004 	str.w	r4, [sl, #4]
			return;
    52e6:	e790      	b.n	520a <z_impl_k_poll+0x196>
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    52e8:	f04f 0a00 	mov.w	sl, #0
    52ec:	4653      	mov	r3, sl
    52ee:	46a2      	mov	sl, r4
    52f0:	461c      	mov	r4, r3
    52f2:	e7cf      	b.n	5294 <z_impl_k_poll+0x220>
    52f4:	4654      	mov	r4, sl
    52f6:	e000      	b.n	52fa <z_impl_k_poll+0x286>
    52f8:	4654      	mov	r4, sl
	sys_dnode_t *const tail = list->tail;
    52fa:	f8d8 3004 	ldr.w	r3, [r8, #4]
	node->next = list;
    52fe:	9a09      	ldr	r2, [sp, #36]	; 0x24
    5300:	f845 8002 	str.w	r8, [r5, r2]
	node->prev = tail;
    5304:	6063      	str	r3, [r4, #4]
	tail->next = node;
    5306:	601c      	str	r4, [r3, #0]
	list->tail = node;
    5308:	f8c8 4004 	str.w	r4, [r8, #4]
}
    530c:	e77d      	b.n	520a <z_impl_k_poll+0x196>
    530e:	4654      	mov	r4, sl
    5310:	e7f3      	b.n	52fa <z_impl_k_poll+0x286>
    5312:	bf00      	nop
    5314:	20000a9c 	.word	0x20000a9c
		add_event(&event->signal->poll_events, event, poller);
    5318:	f8d4 8010 	ldr.w	r8, [r4, #16]
	return list->head == list;
    531c:	f8d8 3000 	ldr.w	r3, [r8]
	return sys_dlist_is_empty(list) ? NULL : list->tail;
    5320:	4598      	cmp	r8, r3
    5322:	d02b      	beq.n	537c <z_impl_k_poll+0x308>
    5324:	f8d8 3004 	ldr.w	r3, [r8, #4]
	if ((pending == NULL) ||
    5328:	b343      	cbz	r3, 537c <z_impl_k_poll+0x308>
		(z_sched_prio_cmp(poller_thread(pending->poller),
    532a:	6898      	ldr	r0, [r3, #8]
    532c:	f001 ffc7 	bl	72be <poller_thread>
    5330:	4682      	mov	sl, r0
    5332:	4638      	mov	r0, r7
    5334:	f001 ffc3 	bl	72be <poller_thread>
    5338:	4601      	mov	r1, r0
    533a:	900a      	str	r0, [sp, #40]	; 0x28
    533c:	4650      	mov	r0, sl
    533e:	f001 fdf0 	bl	6f22 <z_sched_prio_cmp>
	if ((pending == NULL) ||
    5342:	2800      	cmp	r0, #0
    5344:	dc1a      	bgt.n	537c <z_impl_k_poll+0x308>
	return list->head == list;
    5346:	f8d8 a000 	ldr.w	sl, [r8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    534a:	45d0      	cmp	r8, sl
    534c:	d02c      	beq.n	53a8 <z_impl_k_poll+0x334>
    534e:	4653      	mov	r3, sl
    5350:	46a2      	mov	sl, r4
    5352:	461c      	mov	r4, r3
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    5354:	b374      	cbz	r4, 53b4 <z_impl_k_poll+0x340>
		if (z_sched_prio_cmp(poller_thread(poller),
    5356:	68a0      	ldr	r0, [r4, #8]
    5358:	f001 ffb1 	bl	72be <poller_thread>
    535c:	4601      	mov	r1, r0
    535e:	980a      	ldr	r0, [sp, #40]	; 0x28
    5360:	f001 fddf 	bl	6f22 <z_sched_prio_cmp>
    5364:	2800      	cmp	r0, #0
    5366:	dc13      	bgt.n	5390 <z_impl_k_poll+0x31c>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    5368:	b334      	cbz	r4, 53b8 <z_impl_k_poll+0x344>
	return (node == list->tail) ? NULL : node->next;
    536a:	f8d8 3004 	ldr.w	r3, [r8, #4]
    536e:	429c      	cmp	r4, r3
    5370:	d02d      	beq.n	53ce <z_impl_k_poll+0x35a>
    5372:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    5374:	2c00      	cmp	r4, #0
    5376:	d1ed      	bne.n	5354 <z_impl_k_poll+0x2e0>
    5378:	4654      	mov	r4, sl
    537a:	e01e      	b.n	53ba <z_impl_k_poll+0x346>
	sys_dnode_t *const tail = list->tail;
    537c:	f8d8 3004 	ldr.w	r3, [r8, #4]
	node->next = list;
    5380:	9a09      	ldr	r2, [sp, #36]	; 0x24
    5382:	f845 8002 	str.w	r8, [r5, r2]
	node->prev = tail;
    5386:	6063      	str	r3, [r4, #4]
	tail->next = node;
    5388:	601c      	str	r4, [r3, #0]
	list->tail = node;
    538a:	f8c8 4004 	str.w	r4, [r8, #4]
		return;
    538e:	e73c      	b.n	520a <z_impl_k_poll+0x196>
    5390:	4623      	mov	r3, r4
    5392:	4654      	mov	r4, sl
    5394:	469a      	mov	sl, r3
	sys_dnode_t *const prev = successor->prev;
    5396:	685b      	ldr	r3, [r3, #4]
	node->prev = prev;
    5398:	6063      	str	r3, [r4, #4]
	node->next = successor;
    539a:	9a09      	ldr	r2, [sp, #36]	; 0x24
    539c:	f845 a002 	str.w	sl, [r5, r2]
	prev->next = node;
    53a0:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    53a2:	f8ca 4004 	str.w	r4, [sl, #4]
			return;
    53a6:	e730      	b.n	520a <z_impl_k_poll+0x196>
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    53a8:	f04f 0a00 	mov.w	sl, #0
    53ac:	4653      	mov	r3, sl
    53ae:	46a2      	mov	sl, r4
    53b0:	461c      	mov	r4, r3
    53b2:	e7cf      	b.n	5354 <z_impl_k_poll+0x2e0>
    53b4:	4654      	mov	r4, sl
    53b6:	e000      	b.n	53ba <z_impl_k_poll+0x346>
    53b8:	4654      	mov	r4, sl
	sys_dnode_t *const tail = list->tail;
    53ba:	f8d8 3004 	ldr.w	r3, [r8, #4]
	node->next = list;
    53be:	9a09      	ldr	r2, [sp, #36]	; 0x24
    53c0:	f845 8002 	str.w	r8, [r5, r2]
	node->prev = tail;
    53c4:	6063      	str	r3, [r4, #4]
	tail->next = node;
    53c6:	601c      	str	r4, [r3, #0]
	list->tail = node;
    53c8:	f8c8 4004 	str.w	r4, [r8, #4]
}
    53cc:	e71d      	b.n	520a <z_impl_k_poll+0x196>
    53ce:	4654      	mov	r4, sl
    53d0:	e7f3      	b.n	53ba <z_impl_k_poll+0x346>
		add_event(&event->msgq->poll_events, event, poller);
    53d2:	f8d4 a010 	ldr.w	sl, [r4, #16]
    53d6:	f10a 0824 	add.w	r8, sl, #36	; 0x24
	return list->head == list;
    53da:	f8da 3024 	ldr.w	r3, [sl, #36]	; 0x24
	return sys_dlist_is_empty(list) ? NULL : list->tail;
    53de:	4598      	cmp	r8, r3
    53e0:	d02b      	beq.n	543a <z_impl_k_poll+0x3c6>
    53e2:	f8d8 3004 	ldr.w	r3, [r8, #4]
	if ((pending == NULL) ||
    53e6:	b343      	cbz	r3, 543a <z_impl_k_poll+0x3c6>
		(z_sched_prio_cmp(poller_thread(pending->poller),
    53e8:	6898      	ldr	r0, [r3, #8]
    53ea:	f001 ff68 	bl	72be <poller_thread>
    53ee:	900b      	str	r0, [sp, #44]	; 0x2c
    53f0:	4638      	mov	r0, r7
    53f2:	f001 ff64 	bl	72be <poller_thread>
    53f6:	4601      	mov	r1, r0
    53f8:	900a      	str	r0, [sp, #40]	; 0x28
    53fa:	980b      	ldr	r0, [sp, #44]	; 0x2c
    53fc:	f001 fd91 	bl	6f22 <z_sched_prio_cmp>
	if ((pending == NULL) ||
    5400:	2800      	cmp	r0, #0
    5402:	dc1a      	bgt.n	543a <z_impl_k_poll+0x3c6>
	return list->head == list;
    5404:	f8da a024 	ldr.w	sl, [sl, #36]	; 0x24
	return sys_dlist_is_empty(list) ? NULL : list->head;
    5408:	45d0      	cmp	r8, sl
    540a:	d02c      	beq.n	5466 <z_impl_k_poll+0x3f2>
    540c:	4653      	mov	r3, sl
    540e:	46a2      	mov	sl, r4
    5410:	461c      	mov	r4, r3
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    5412:	b374      	cbz	r4, 5472 <z_impl_k_poll+0x3fe>
		if (z_sched_prio_cmp(poller_thread(poller),
    5414:	68a0      	ldr	r0, [r4, #8]
    5416:	f001 ff52 	bl	72be <poller_thread>
    541a:	4601      	mov	r1, r0
    541c:	980a      	ldr	r0, [sp, #40]	; 0x28
    541e:	f001 fd80 	bl	6f22 <z_sched_prio_cmp>
    5422:	2800      	cmp	r0, #0
    5424:	dc13      	bgt.n	544e <z_impl_k_poll+0x3da>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    5426:	b334      	cbz	r4, 5476 <z_impl_k_poll+0x402>
	return (node == list->tail) ? NULL : node->next;
    5428:	f8d8 3004 	ldr.w	r3, [r8, #4]
    542c:	429c      	cmp	r4, r3
    542e:	d02d      	beq.n	548c <z_impl_k_poll+0x418>
    5430:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    5432:	2c00      	cmp	r4, #0
    5434:	d1ed      	bne.n	5412 <z_impl_k_poll+0x39e>
    5436:	4654      	mov	r4, sl
    5438:	e01e      	b.n	5478 <z_impl_k_poll+0x404>
	sys_dnode_t *const tail = list->tail;
    543a:	f8d8 3004 	ldr.w	r3, [r8, #4]
	node->next = list;
    543e:	9a09      	ldr	r2, [sp, #36]	; 0x24
    5440:	f845 8002 	str.w	r8, [r5, r2]
	node->prev = tail;
    5444:	6063      	str	r3, [r4, #4]
	tail->next = node;
    5446:	601c      	str	r4, [r3, #0]
	list->tail = node;
    5448:	f8c8 4004 	str.w	r4, [r8, #4]
		return;
    544c:	e6dd      	b.n	520a <z_impl_k_poll+0x196>
    544e:	4623      	mov	r3, r4
    5450:	4654      	mov	r4, sl
    5452:	469a      	mov	sl, r3
	sys_dnode_t *const prev = successor->prev;
    5454:	685b      	ldr	r3, [r3, #4]
	node->prev = prev;
    5456:	6063      	str	r3, [r4, #4]
	node->next = successor;
    5458:	9a09      	ldr	r2, [sp, #36]	; 0x24
    545a:	f845 a002 	str.w	sl, [r5, r2]
	prev->next = node;
    545e:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    5460:	f8ca 4004 	str.w	r4, [sl, #4]
			return;
    5464:	e6d1      	b.n	520a <z_impl_k_poll+0x196>
	SYS_DLIST_FOR_EACH_CONTAINER(events, pending, _node) {
    5466:	f04f 0a00 	mov.w	sl, #0
    546a:	4653      	mov	r3, sl
    546c:	46a2      	mov	sl, r4
    546e:	461c      	mov	r4, r3
    5470:	e7cf      	b.n	5412 <z_impl_k_poll+0x39e>
    5472:	4654      	mov	r4, sl
    5474:	e000      	b.n	5478 <z_impl_k_poll+0x404>
    5476:	4654      	mov	r4, sl
	sys_dnode_t *const tail = list->tail;
    5478:	f8d8 3004 	ldr.w	r3, [r8, #4]
	node->next = list;
    547c:	9a09      	ldr	r2, [sp, #36]	; 0x24
    547e:	f845 8002 	str.w	r8, [r5, r2]
	node->prev = tail;
    5482:	6063      	str	r3, [r4, #4]
	tail->next = node;
    5484:	601c      	str	r4, [r3, #0]
	list->tail = node;
    5486:	f8c8 4004 	str.w	r4, [r8, #4]
}
    548a:	e6be      	b.n	520a <z_impl_k_poll+0x196>
    548c:	4654      	mov	r4, sl
    548e:	e7f3      	b.n	5478 <z_impl_k_poll+0x404>
    5490:	f04f 0320 	mov.w	r3, #32
    5494:	f3ef 8111 	mrs	r1, BASEPRI
    5498:	f383 8812 	msr	BASEPRI_MAX, r3
    549c:	f3bf 8f6f 	isb	sy
	/*
	 * If we're not polling anymore, it means that at least one event
	 * condition is met, either when looping through the events here or
	 * because one of the events registered has had its state changed.
	 */
	if (!poller->is_polling) {
    54a0:	f899 3060 	ldrb.w	r3, [r9, #96]	; 0x60
    54a4:	b1cb      	cbz	r3, 54da <z_impl_k_poll+0x466>
		SYS_PORT_TRACING_FUNC_EXIT(k_poll_api, poll, events, 0);

		return 0;
	}

	poller->is_polling = false;
    54a6:	2300      	movs	r3, #0
    54a8:	f889 3060 	strb.w	r3, [r9, #96]	; 0x60

	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    54ac:	e9dd 3402 	ldrd	r3, r4, [sp, #8]
    54b0:	4323      	orrs	r3, r4
    54b2:	d045      	beq.n	5540 <z_impl_k_poll+0x4cc>
		return -EAGAIN;
	}

	static _wait_q_t wait_q = Z_WAIT_Q_INIT(&wait_q);

	int swap_rc = z_pend_curr(&lock, key, &wait_q, timeout);
    54b4:	e9dd 3402 	ldrd	r3, r4, [sp, #8]
    54b8:	e9cd 3400 	strd	r3, r4, [sp]
    54bc:	4a3c      	ldr	r2, [pc, #240]	; (55b0 <z_impl_k_poll+0x53c>)
    54be:	483d      	ldr	r0, [pc, #244]	; (55b4 <z_impl_k_poll+0x540>)
    54c0:	f7ff fa62 	bl	4988 <z_pend_curr>
    54c4:	f04f 0320 	mov.w	r3, #32
    54c8:	f3ef 8c11 	mrs	ip, BASEPRI
    54cc:	f383 8812 	msr	BASEPRI_MAX, r3
    54d0:	f3bf 8f6f 	isb	sy
    54d4:	4661      	mov	r1, ip
	while (num_events--) {
    54d6:	465b      	mov	r3, fp
    54d8:	e04e      	b.n	5578 <z_impl_k_poll+0x504>
		clear_event_registrations(events, events_registered, key);
    54da:	4608      	mov	r0, r1
	while (num_events--) {
    54dc:	465b      	mov	r3, fp
    54de:	e014      	b.n	550a <z_impl_k_poll+0x496>
	return node->next != NULL;
    54e0:	59aa      	ldr	r2, [r5, r6]
	if (remove_event && sys_dnode_is_linked(&event->_node)) {
    54e2:	b12a      	cbz	r2, 54f0 <z_impl_k_poll+0x47c>
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
    54e4:	685c      	ldr	r4, [r3, #4]
	sys_dnode_t *const next = node->next;

	prev->next = next;
    54e6:	6022      	str	r2, [r4, #0]
	next->prev = prev;
    54e8:	6054      	str	r4, [r2, #4]
	node->next = NULL;
    54ea:	2200      	movs	r2, #0
    54ec:	51aa      	str	r2, [r5, r6]
	node->prev = NULL;
    54ee:	605a      	str	r2, [r3, #4]
	__asm__ volatile(
    54f0:	f380 8811 	msr	BASEPRI, r0
    54f4:	f3bf 8f6f 	isb	sy
	__asm__ volatile(
    54f8:	f04f 0320 	mov.w	r3, #32
    54fc:	f3ef 8011 	mrs	r0, BASEPRI
    5500:	f383 8812 	msr	BASEPRI_MAX, r3
    5504:	f3bf 8f6f 	isb	sy
	while (num_events--) {
    5508:	463b      	mov	r3, r7
    550a:	1e5f      	subs	r7, r3, #1
    550c:	b193      	cbz	r3, 5534 <z_impl_k_poll+0x4c0>
		clear_event_registration(&events[num_events]);
    550e:	eb07 0387 	add.w	r3, r7, r7, lsl #2
    5512:	009e      	lsls	r6, r3, #2
    5514:	eb05 0383 	add.w	r3, r5, r3, lsl #2
	event->poller = NULL;
    5518:	2200      	movs	r2, #0
    551a:	609a      	str	r2, [r3, #8]
	switch (event->type) {
    551c:	7b5a      	ldrb	r2, [r3, #13]
    551e:	f002 021f 	and.w	r2, r2, #31
    5522:	2a08      	cmp	r2, #8
    5524:	d8e4      	bhi.n	54f0 <z_impl_k_poll+0x47c>
    5526:	2401      	movs	r4, #1
    5528:	fa04 f202 	lsl.w	r2, r4, r2
    552c:	f412 7f8b 	tst.w	r2, #278	; 0x116
    5530:	d0de      	beq.n	54f0 <z_impl_k_poll+0x47c>
    5532:	e7d5      	b.n	54e0 <z_impl_k_poll+0x46c>
	__asm__ volatile(
    5534:	f381 8811 	msr	BASEPRI, r1
    5538:	f3bf 8f6f 	isb	sy
		return 0;
    553c:	4618      	mov	r0, r3
    553e:	e034      	b.n	55aa <z_impl_k_poll+0x536>
    5540:	f381 8811 	msr	BASEPRI, r1
    5544:	f3bf 8f6f 	isb	sy
		return -EAGAIN;
    5548:	f06f 000a 	mvn.w	r0, #10
    554c:	e02d      	b.n	55aa <z_impl_k_poll+0x536>
	return node->next != NULL;
    554e:	59ea      	ldr	r2, [r5, r7]
	if (remove_event && sys_dnode_is_linked(&event->_node)) {
    5550:	b12a      	cbz	r2, 555e <z_impl_k_poll+0x4ea>
	sys_dnode_t *const prev = node->prev;
    5552:	685e      	ldr	r6, [r3, #4]
	prev->next = next;
    5554:	6032      	str	r2, [r6, #0]
	next->prev = prev;
    5556:	6056      	str	r6, [r2, #4]
	node->next = NULL;
    5558:	2200      	movs	r2, #0
    555a:	51ea      	str	r2, [r5, r7]
	node->prev = NULL;
    555c:	605a      	str	r2, [r3, #4]
    555e:	f381 8811 	msr	BASEPRI, r1
    5562:	f3bf 8f6f 	isb	sy
	__asm__ volatile(
    5566:	f04f 0320 	mov.w	r3, #32
    556a:	f3ef 8111 	mrs	r1, BASEPRI
    556e:	f383 8812 	msr	BASEPRI_MAX, r3
    5572:	f3bf 8f6f 	isb	sy
	while (num_events--) {
    5576:	4623      	mov	r3, r4
    5578:	1e5c      	subs	r4, r3, #1
    557a:	b193      	cbz	r3, 55a2 <z_impl_k_poll+0x52e>
		clear_event_registration(&events[num_events]);
    557c:	eb04 0384 	add.w	r3, r4, r4, lsl #2
    5580:	009f      	lsls	r7, r3, #2
    5582:	eb05 0383 	add.w	r3, r5, r3, lsl #2
	event->poller = NULL;
    5586:	2200      	movs	r2, #0
    5588:	609a      	str	r2, [r3, #8]
	switch (event->type) {
    558a:	7b5a      	ldrb	r2, [r3, #13]
    558c:	f002 021f 	and.w	r2, r2, #31
    5590:	2a08      	cmp	r2, #8
    5592:	d8e4      	bhi.n	555e <z_impl_k_poll+0x4ea>
    5594:	2601      	movs	r6, #1
    5596:	fa06 f202 	lsl.w	r2, r6, r2
    559a:	f412 7f8b 	tst.w	r2, #278	; 0x116
    559e:	d0de      	beq.n	555e <z_impl_k_poll+0x4ea>
    55a0:	e7d5      	b.n	554e <z_impl_k_poll+0x4da>
	__asm__ volatile(
    55a2:	f38c 8811 	msr	BASEPRI, ip
    55a6:	f3bf 8f6f 	isb	sy
	k_spin_unlock(&lock, key);

	SYS_PORT_TRACING_FUNC_EXIT(k_poll_api, poll, events, swap_rc);

	return swap_rc;
}
    55aa:	b00d      	add	sp, #52	; 0x34
    55ac:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    55b0:	20000198 	.word	0x20000198
    55b4:	20000ad8 	.word	0x20000ad8

000055b8 <z_impl_k_poll_signal_raise>:
}
#include <syscalls/k_poll_signal_check_mrsh.c>
#endif

int z_impl_k_poll_signal_raise(struct k_poll_signal *sig, int result)
{
    55b8:	b538      	push	{r3, r4, r5, lr}
    55ba:	4603      	mov	r3, r0
	__asm__ volatile(
    55bc:	f04f 0220 	mov.w	r2, #32
    55c0:	f3ef 8511 	mrs	r5, BASEPRI
    55c4:	f382 8812 	msr	BASEPRI_MAX, r2
    55c8:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_poll_event *poll_event;

	sig->result = result;
    55cc:	60c1      	str	r1, [r0, #12]
	sig->signaled = 1U;
    55ce:	2201      	movs	r2, #1
    55d0:	6082      	str	r2, [r0, #8]
	return list->head == list;
    55d2:	6800      	ldr	r0, [r0, #0]

static inline sys_dnode_t *sys_dlist_get(sys_dlist_t *list)
{
	sys_dnode_t *node = NULL;

	if (!sys_dlist_is_empty(list)) {
    55d4:	4283      	cmp	r3, r0
    55d6:	d011      	beq.n	55fc <z_impl_k_poll_signal_raise+0x44>
	sys_dnode_t *const prev = node->prev;
    55d8:	6842      	ldr	r2, [r0, #4]
	sys_dnode_t *const next = node->next;
    55da:	6803      	ldr	r3, [r0, #0]
	prev->next = next;
    55dc:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    55de:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    55e0:	2300      	movs	r3, #0
    55e2:	6003      	str	r3, [r0, #0]
	node->prev = NULL;
    55e4:	6043      	str	r3, [r0, #4]

	poll_event = (struct k_poll_event *)sys_dlist_get(&sig->poll_events);
	if (poll_event == NULL) {
    55e6:	b148      	cbz	r0, 55fc <z_impl_k_poll_signal_raise+0x44>
		SYS_PORT_TRACING_FUNC(k_poll_api, signal_raise, sig, 0);

		return 0;
	}

	int rc = signal_poll_event(poll_event, K_POLL_STATE_SIGNALED);
    55e8:	2101      	movs	r1, #1
    55ea:	f001 feb8 	bl	735e <signal_poll_event>
    55ee:	4604      	mov	r4, r0

	SYS_PORT_TRACING_FUNC(k_poll_api, signal_raise, sig, rc);

	z_reschedule(&lock, key);
    55f0:	4629      	mov	r1, r5
    55f2:	4805      	ldr	r0, [pc, #20]	; (5608 <z_impl_k_poll_signal_raise+0x50>)
    55f4:	f7ff f864 	bl	46c0 <z_reschedule>
	return rc;
}
    55f8:	4620      	mov	r0, r4
    55fa:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    55fc:	f385 8811 	msr	BASEPRI, r5
    5600:	f3bf 8f6f 	isb	sy
		return 0;
    5604:	2400      	movs	r4, #0
    5606:	e7f7      	b.n	55f8 <z_impl_k_poll_signal_raise+0x40>
    5608:	20000ad8 	.word	0x20000ad8

0000560c <boot_banner>:
#define BOOT_DELAY_BANNER ""
#endif

#if defined(CONFIG_BOOT_DELAY) || CONFIG_BOOT_DELAY > 0
void boot_banner(void)
{
    560c:	b508      	push	{r3, lr}
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
    560e:	4a03      	ldr	r2, [pc, #12]	; (561c <boot_banner+0x10>)
    5610:	4903      	ldr	r1, [pc, #12]	; (5620 <boot_banner+0x14>)
    5612:	4804      	ldr	r0, [pc, #16]	; (5624 <boot_banner+0x18>)
    5614:	f000 f9d2 	bl	59bc <printk>
#else
	printk("*** Booting Zephyr OS version %s %s ***\n",
	       KERNEL_VERSION_STRING, BOOT_DELAY_BANNER);
#endif
#endif
}
    5618:	bd08      	pop	{r3, pc}
    561a:	bf00      	nop
    561c:	00007940 	.word	0x00007940
    5620:	0000797c 	.word	0x0000797c
    5624:	00007988 	.word	0x00007988

00005628 <k_sys_work_q_init>:
			     CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE);

struct k_work_q k_sys_work_q;

static int k_sys_work_q_init(const struct device *dev)
{
    5628:	b510      	push	{r4, lr}
    562a:	b084      	sub	sp, #16
	ARG_UNUSED(dev);
	struct k_work_queue_config cfg = {
    562c:	4b08      	ldr	r3, [pc, #32]	; (5650 <k_sys_work_q_init+0x28>)
    562e:	9302      	str	r3, [sp, #8]
    5630:	2400      	movs	r4, #0
    5632:	f88d 400c 	strb.w	r4, [sp, #12]
		.name = "sysworkq",
		.no_yield = IS_ENABLED(CONFIG_SYSTEM_WORKQUEUE_NO_YIELD),
	};

	k_work_queue_start(&k_sys_work_q,
    5636:	ab02      	add	r3, sp, #8
    5638:	9300      	str	r3, [sp, #0]
    563a:	f04f 33ff 	mov.w	r3, #4294967295
    563e:	f44f 6280 	mov.w	r2, #1024	; 0x400
    5642:	4904      	ldr	r1, [pc, #16]	; (5654 <k_sys_work_q_init+0x2c>)
    5644:	4804      	ldr	r0, [pc, #16]	; (5658 <k_sys_work_q_init+0x30>)
    5646:	f000 f929 	bl	589c <k_work_queue_start>
			    sys_work_q_stack,
			    K_KERNEL_STACK_SIZEOF(sys_work_q_stack),
			    CONFIG_SYSTEM_WORKQUEUE_PRIORITY, &cfg);
	return 0;
}
    564a:	4620      	mov	r0, r4
    564c:	b004      	add	sp, #16
    564e:	bd10      	pop	{r4, pc}
    5650:	000079b0 	.word	0x000079b0
    5654:	200018a0 	.word	0x200018a0
    5658:	20000360 	.word	0x20000360

0000565c <submit_to_queue_locked>:
 * @retval -EINVAL if no queue is provided
 * @retval -ENODEV if the queue is not started
 */
static int submit_to_queue_locked(struct k_work *work,
				  struct k_work_q **queuep)
{
    565c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    565e:	460d      	mov	r5, r1
	return (*flagp & BIT(bit)) != 0U;
    5660:	68c3      	ldr	r3, [r0, #12]
	int ret = 0;

	if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
    5662:	f013 0f02 	tst.w	r3, #2
    5666:	d15b      	bne.n	5720 <submit_to_queue_locked+0xc4>
    5668:	4604      	mov	r4, r0
		/* Disallowed */
		ret = -EBUSY;
	} else if (!flag_test(&work->flags, K_WORK_QUEUED_BIT)) {
    566a:	f013 0f04 	tst.w	r3, #4
    566e:	d15c      	bne.n	572a <submit_to_queue_locked+0xce>
		/* Not currently queued */
		ret = 1;

		/* If no queue specified resubmit to last queue.
		 */
		if (*queuep == NULL) {
    5670:	680b      	ldr	r3, [r1, #0]
    5672:	2b00      	cmp	r3, #0
    5674:	d037      	beq.n	56e6 <submit_to_queue_locked+0x8a>
	return (*flagp & BIT(bit)) != 0U;
    5676:	68e3      	ldr	r3, [r4, #12]

		/* If the work is currently running we have to use the
		 * queue it's running on to prevent handler
		 * re-entrancy.
		 */
		if (flag_test(&work->flags, K_WORK_RUNNING_BIT)) {
    5678:	f013 0f01 	tst.w	r3, #1
    567c:	d036      	beq.n	56ec <submit_to_queue_locked+0x90>
			__ASSERT_NO_MSG(work->queue != NULL);
			*queuep = work->queue;
    567e:	68a3      	ldr	r3, [r4, #8]
    5680:	602b      	str	r3, [r5, #0]
			ret = 2;
    5682:	2702      	movs	r7, #2
		}

		int rc = queue_submit_locked(*queuep, work);
    5684:	682e      	ldr	r6, [r5, #0]
	if (queue == NULL) {
    5686:	2e00      	cmp	r6, #0
    5688:	d03e      	beq.n	5708 <submit_to_queue_locked+0xac>
	bool chained = (_current == &queue->thread) && !k_is_in_isr();
    568a:	4b29      	ldr	r3, [pc, #164]	; (5730 <submit_to_queue_locked+0xd4>)
    568c:	689b      	ldr	r3, [r3, #8]
    568e:	42b3      	cmp	r3, r6
    5690:	d02e      	beq.n	56f0 <submit_to_queue_locked+0x94>
    5692:	2300      	movs	r3, #0
    5694:	461a      	mov	r2, r3
	return (*flagp & BIT(bit)) != 0U;
    5696:	f8d6 30d0 	ldr.w	r3, [r6, #208]	; 0xd0
    569a:	f3c3 0180 	ubfx	r1, r3, #2, #1
    569e:	f3c3 00c0 	ubfx	r0, r3, #3, #1
	if (!flag_test(&queue->flags, K_WORK_QUEUE_STARTED_BIT)) {
    56a2:	f013 0f01 	tst.w	r3, #1
    56a6:	d032      	beq.n	570e <submit_to_queue_locked+0xb2>
	} else if (draining && !chained) {
    56a8:	b101      	cbz	r1, 56ac <submit_to_queue_locked+0x50>
    56aa:	b39a      	cbz	r2, 5714 <submit_to_queue_locked+0xb8>
	} else if (plugged && !draining) {
    56ac:	b100      	cbz	r0, 56b0 <submit_to_queue_locked+0x54>
    56ae:	b3a1      	cbz	r1, 571a <submit_to_queue_locked+0xbe>
	parent->next = child;
    56b0:	2300      	movs	r3, #0
    56b2:	6023      	str	r3, [r4, #0]
	return list->tail;
    56b4:	f8d6 30bc 	ldr.w	r3, [r6, #188]	; 0xbc
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
				    sys_snode_t *node);

Z_GENLIST_APPEND(slist, snode)
    56b8:	b30b      	cbz	r3, 56fe <submit_to_queue_locked+0xa2>
	parent->next = child;
    56ba:	601c      	str	r4, [r3, #0]
	list->tail = node;
    56bc:	f8c6 40bc 	str.w	r4, [r6, #188]	; 0xbc
		rv = z_sched_wake(&queue->notifyq, 0, NULL);
    56c0:	2200      	movs	r2, #0
    56c2:	4611      	mov	r1, r2
    56c4:	f106 00c0 	add.w	r0, r6, #192	; 0xc0
    56c8:	f001 fd42 	bl	7150 <z_sched_wake>
		ret = 1;
    56cc:	2001      	movs	r0, #1

		if (rc < 0) {
    56ce:	2800      	cmp	r0, #0
    56d0:	db06      	blt.n	56e0 <submit_to_queue_locked+0x84>
	*flagp |= BIT(bit);
    56d2:	68e3      	ldr	r3, [r4, #12]
    56d4:	f043 0304 	orr.w	r3, r3, #4
    56d8:	60e3      	str	r3, [r4, #12]
			ret = rc;
		} else {
			flag_set(&work->flags, K_WORK_QUEUED_BIT);
			work->queue = *queuep;
    56da:	682b      	ldr	r3, [r5, #0]
    56dc:	60a3      	str	r3, [r4, #8]
    56de:	4638      	mov	r0, r7
		}
	} else {
		/* Already queued, do nothing. */
	}

	if (ret <= 0) {
    56e0:	2800      	cmp	r0, #0
    56e2:	dc21      	bgt.n	5728 <submit_to_queue_locked+0xcc>
    56e4:	e01e      	b.n	5724 <submit_to_queue_locked+0xc8>
			*queuep = work->queue;
    56e6:	6883      	ldr	r3, [r0, #8]
    56e8:	600b      	str	r3, [r1, #0]
    56ea:	e7c4      	b.n	5676 <submit_to_queue_locked+0x1a>
		ret = 1;
    56ec:	2701      	movs	r7, #1
    56ee:	e7c9      	b.n	5684 <submit_to_queue_locked+0x28>
	bool chained = (_current == &queue->thread) && !k_is_in_isr();
    56f0:	f001 fbca 	bl	6e88 <k_is_in_isr>
    56f4:	b908      	cbnz	r0, 56fa <submit_to_queue_locked+0x9e>
    56f6:	2301      	movs	r3, #1
    56f8:	e7cc      	b.n	5694 <submit_to_queue_locked+0x38>
    56fa:	2300      	movs	r3, #0
    56fc:	e7ca      	b.n	5694 <submit_to_queue_locked+0x38>
    56fe:	f8c6 40bc 	str.w	r4, [r6, #188]	; 0xbc
	list->head = node;
    5702:	f8c6 40b8 	str.w	r4, [r6, #184]	; 0xb8
}
    5706:	e7db      	b.n	56c0 <submit_to_queue_locked+0x64>
		return -EINVAL;
    5708:	f06f 0015 	mvn.w	r0, #21
    570c:	e7df      	b.n	56ce <submit_to_queue_locked+0x72>
		ret = -ENODEV;
    570e:	f06f 0012 	mvn.w	r0, #18
    5712:	e7dc      	b.n	56ce <submit_to_queue_locked+0x72>
		ret = -EBUSY;
    5714:	f06f 000f 	mvn.w	r0, #15
    5718:	e7d9      	b.n	56ce <submit_to_queue_locked+0x72>
		ret = -EBUSY;
    571a:	f06f 000f 	mvn.w	r0, #15
    571e:	e7d6      	b.n	56ce <submit_to_queue_locked+0x72>
		ret = -EBUSY;
    5720:	f06f 000f 	mvn.w	r0, #15
		*queuep = NULL;
    5724:	2300      	movs	r3, #0
    5726:	602b      	str	r3, [r5, #0]
	}

	return ret;
}
    5728:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	int ret = 0;
    572a:	2000      	movs	r0, #0
    572c:	e7fa      	b.n	5724 <submit_to_queue_locked+0xc8>
    572e:	bf00      	nop
    5730:	20000a9c 	.word	0x20000a9c

00005734 <finalize_cancel_locked>:
{
    5734:	b570      	push	{r4, r5, r6, lr}
    5736:	4605      	mov	r5, r0
	*flagp &= ~BIT(bit);
    5738:	68c3      	ldr	r3, [r0, #12]
    573a:	f023 0302 	bic.w	r3, r3, #2
    573e:	60c3      	str	r3, [r0, #12]
	return list->head;
    5740:	4b19      	ldr	r3, [pc, #100]	; (57a8 <finalize_cancel_locked+0x74>)
    5742:	6818      	ldr	r0, [r3, #0]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&pending_cancels, wc, tmp, node) {
    5744:	b1e8      	cbz	r0, 5782 <finalize_cancel_locked+0x4e>
    5746:	4604      	mov	r4, r0
Z_GENLIST_PEEK_NEXT(slist, snode)
    5748:	b100      	cbz	r0, 574c <finalize_cancel_locked+0x18>
	return node->next;
    574a:	6804      	ldr	r4, [r0, #0]
    574c:	2600      	movs	r6, #0
    574e:	e01d      	b.n	578c <finalize_cancel_locked+0x58>
 */
static inline void sys_slist_remove(sys_slist_t *list,
				    sys_snode_t *prev_node,
				    sys_snode_t *node);

Z_GENLIST_REMOVE(slist, snode)
    5750:	b15e      	cbz	r6, 576a <finalize_cancel_locked+0x36>
	return node->next;
    5752:	6803      	ldr	r3, [r0, #0]
	parent->next = child;
    5754:	6033      	str	r3, [r6, #0]
	return list->tail;
    5756:	4b14      	ldr	r3, [pc, #80]	; (57a8 <finalize_cancel_locked+0x74>)
    5758:	685b      	ldr	r3, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    575a:	4298      	cmp	r0, r3
    575c:	d00e      	beq.n	577c <finalize_cancel_locked+0x48>
	parent->next = child;
    575e:	2300      	movs	r3, #0
    5760:	f840 3b08 	str.w	r3, [r0], #8
	z_impl_k_sem_give(sem);
    5764:	f7fe fef8 	bl	4558 <z_impl_k_sem_give>
}
    5768:	e015      	b.n	5796 <finalize_cancel_locked+0x62>
	return node->next;
    576a:	6802      	ldr	r2, [r0, #0]
	list->head = node;
    576c:	4b0e      	ldr	r3, [pc, #56]	; (57a8 <finalize_cancel_locked+0x74>)
    576e:	601a      	str	r2, [r3, #0]
	return list->tail;
    5770:	685b      	ldr	r3, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    5772:	4298      	cmp	r0, r3
    5774:	d1f3      	bne.n	575e <finalize_cancel_locked+0x2a>
	list->tail = node;
    5776:	4b0c      	ldr	r3, [pc, #48]	; (57a8 <finalize_cancel_locked+0x74>)
    5778:	605a      	str	r2, [r3, #4]
}
    577a:	e7f0      	b.n	575e <finalize_cancel_locked+0x2a>
	list->tail = node;
    577c:	4b0a      	ldr	r3, [pc, #40]	; (57a8 <finalize_cancel_locked+0x74>)
    577e:	605e      	str	r6, [r3, #4]
}
    5780:	e7ed      	b.n	575e <finalize_cancel_locked+0x2a>
    5782:	4604      	mov	r4, r0
    5784:	e7e2      	b.n	574c <finalize_cancel_locked+0x18>
    5786:	4623      	mov	r3, r4
    5788:	4620      	mov	r0, r4
    578a:	461c      	mov	r4, r3
    578c:	b150      	cbz	r0, 57a4 <finalize_cancel_locked+0x70>
		if (wc->work == work) {
    578e:	6843      	ldr	r3, [r0, #4]
    5790:	42ab      	cmp	r3, r5
    5792:	d0dd      	beq.n	5750 <finalize_cancel_locked+0x1c>
			prev = &wc->node;
    5794:	4606      	mov	r6, r0
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&pending_cancels, wc, tmp, node) {
    5796:	2c00      	cmp	r4, #0
    5798:	d0f5      	beq.n	5786 <finalize_cancel_locked+0x52>
    579a:	4623      	mov	r3, r4
Z_GENLIST_PEEK_NEXT(slist, snode)
    579c:	2c00      	cmp	r4, #0
    579e:	d0f3      	beq.n	5788 <finalize_cancel_locked+0x54>
	return node->next;
    57a0:	6823      	ldr	r3, [r4, #0]
    57a2:	e7f1      	b.n	5788 <finalize_cancel_locked+0x54>
}
    57a4:	bd70      	pop	{r4, r5, r6, pc}
    57a6:	bf00      	nop
    57a8:	20000ad8 	.word	0x20000ad8

000057ac <work_queue_main>:
/* Loop executed by a work queue thread.
 *
 * @param workq_ptr pointer to the work queue structure
 */
static void work_queue_main(void *workq_ptr, void *p2, void *p3)
{
    57ac:	b5f0      	push	{r4, r5, r6, r7, lr}
    57ae:	b085      	sub	sp, #20
    57b0:	4605      	mov	r5, r0
	struct k_work_q *queue = (struct k_work_q *)workq_ptr;
    57b2:	e016      	b.n	57e2 <work_queue_main+0x36>
	return (*flagp & BIT(bit)) != 0U;
    57b4:	f8d5 30d0 	ldr.w	r3, [r5, #208]	; 0xd0
	*flagp &= ~BIT(bit);
    57b8:	f023 0204 	bic.w	r2, r3, #4
    57bc:	f8c5 20d0 	str.w	r2, [r5, #208]	; 0xd0
			 * which should never happen, even line 'if (work != NULL)'
			 * ensures that.
			 * This means that if node is not NULL, then work will not be NULL.
			 */
			handler = work->handler;
		} else if (flag_test_and_clear(&queue->flags,
    57c0:	f013 0f04 	tst.w	r3, #4
    57c4:	d158      	bne.n	5878 <work_queue_main+0xcc>
			 * the lock, and we didn't find work nor got asked to
			 * stop.  Just go to sleep: when something happens the
			 * work thread will be woken and we can check again.
			 */

			(void)z_sched_wait(&lock, key, &queue->notifyq,
    57c6:	2300      	movs	r3, #0
    57c8:	9302      	str	r3, [sp, #8]
    57ca:	f04f 32ff 	mov.w	r2, #4294967295
    57ce:	f04f 33ff 	mov.w	r3, #4294967295
    57d2:	e9cd 2300 	strd	r2, r3, [sp]
    57d6:	f105 02c0 	add.w	r2, r5, #192	; 0xc0
    57da:	4631      	mov	r1, r6
    57dc:	482e      	ldr	r0, [pc, #184]	; (5898 <work_queue_main+0xec>)
    57de:	f7ff faa9 	bl	4d34 <z_sched_wait>
	__asm__ volatile(
    57e2:	f04f 0320 	mov.w	r3, #32
    57e6:	f3ef 8611 	mrs	r6, BASEPRI
    57ea:	f383 8812 	msr	BASEPRI_MAX, r3
    57ee:	f3bf 8f6f 	isb	sy
	return list->head;
    57f2:	f8d5 40b8 	ldr.w	r4, [r5, #184]	; 0xb8
Z_GENLIST_GET(slist, snode)
    57f6:	2c00      	cmp	r4, #0
    57f8:	d0dc      	beq.n	57b4 <work_queue_main+0x8>
	return node->next;
    57fa:	6823      	ldr	r3, [r4, #0]
	list->head = node;
    57fc:	f8c5 30b8 	str.w	r3, [r5, #184]	; 0xb8
	return list->tail;
    5800:	f8d5 20bc 	ldr.w	r2, [r5, #188]	; 0xbc
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    5804:	4294      	cmp	r4, r2
    5806:	d034      	beq.n	5872 <work_queue_main+0xc6>
	*flagp |= BIT(bit);
    5808:	f8d5 30d0 	ldr.w	r3, [r5, #208]	; 0xd0
    580c:	f043 0302 	orr.w	r3, r3, #2
    5810:	f8c5 30d0 	str.w	r3, [r5, #208]	; 0xd0
    5814:	68e3      	ldr	r3, [r4, #12]
    5816:	f043 0301 	orr.w	r3, r3, #1
	*flagp &= ~BIT(bit);
    581a:	f023 0304 	bic.w	r3, r3, #4
    581e:	60e3      	str	r3, [r4, #12]
			handler = work->handler;
    5820:	6863      	ldr	r3, [r4, #4]
		if (work == NULL) {
    5822:	2c00      	cmp	r4, #0
    5824:	d0cf      	beq.n	57c6 <work_queue_main+0x1a>
	__asm__ volatile(
    5826:	f386 8811 	msr	BASEPRI, r6
    582a:	f3bf 8f6f 	isb	sy

		if (work != NULL) {
			bool yield;

			__ASSERT_NO_MSG(handler != NULL);
			handler(work);
    582e:	4620      	mov	r0, r4
    5830:	4798      	blx	r3
	__asm__ volatile(
    5832:	f04f 0320 	mov.w	r3, #32
    5836:	f3ef 8611 	mrs	r6, BASEPRI
    583a:	f383 8812 	msr	BASEPRI_MAX, r3
    583e:	f3bf 8f6f 	isb	sy
	*flagp &= ~BIT(bit);
    5842:	68e3      	ldr	r3, [r4, #12]
    5844:	f023 0301 	bic.w	r3, r3, #1
    5848:	60e3      	str	r3, [r4, #12]
			 * starving other threads.
			 */
			key = k_spin_lock(&lock);

			flag_clear(&work->flags, K_WORK_RUNNING_BIT);
			if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
    584a:	f013 0f02 	tst.w	r3, #2
    584e:	d11e      	bne.n	588e <work_queue_main+0xe2>
	*flagp &= ~BIT(bit);
    5850:	f8d5 30d0 	ldr.w	r3, [r5, #208]	; 0xd0
    5854:	f023 0302 	bic.w	r3, r3, #2
    5858:	f8c5 30d0 	str.w	r3, [r5, #208]	; 0xd0
	return (*flagp & BIT(bit)) != 0U;
    585c:	f3c3 2300 	ubfx	r3, r3, #8, #1
	__asm__ volatile(
    5860:	f386 8811 	msr	BASEPRI, r6
    5864:	f3bf 8f6f 	isb	sy
			k_spin_unlock(&lock, key);

			/* Optionally yield to prevent the work queue from
			 * starving other threads.
			 */
			if (yield) {
    5868:	2b00      	cmp	r3, #0
    586a:	d1ba      	bne.n	57e2 <work_queue_main+0x36>
	z_impl_k_yield();
    586c:	f7ff f964 	bl	4b38 <z_impl_k_yield>
}
    5870:	e7b7      	b.n	57e2 <work_queue_main+0x36>
	list->tail = node;
    5872:	f8c5 30bc 	str.w	r3, [r5, #188]	; 0xbc
}
    5876:	e7c7      	b.n	5808 <work_queue_main+0x5c>
			(void)z_sched_wake_all(&queue->drainq, 1, NULL);
    5878:	f105 07c8 	add.w	r7, r5, #200	; 0xc8
static inline bool z_sched_wake_all(_wait_q_t *wait_q, int swap_retval,
				    void *swap_data)
{
	bool woken = false;

	while (z_sched_wake(wait_q, swap_retval, swap_data)) {
    587c:	2200      	movs	r2, #0
    587e:	2101      	movs	r1, #1
    5880:	4638      	mov	r0, r7
    5882:	f001 fc65 	bl	7150 <z_sched_wake>
    5886:	2800      	cmp	r0, #0
    5888:	d1f8      	bne.n	587c <work_queue_main+0xd0>
		k_work_handler_t handler = NULL;
    588a:	2300      	movs	r3, #0
    588c:	e7c9      	b.n	5822 <work_queue_main+0x76>
				finalize_cancel_locked(work);
    588e:	4620      	mov	r0, r4
    5890:	f7ff ff50 	bl	5734 <finalize_cancel_locked>
    5894:	e7dc      	b.n	5850 <work_queue_main+0xa4>
    5896:	bf00      	nop
    5898:	20000ad8 	.word	0x20000ad8

0000589c <k_work_queue_start>:
void k_work_queue_start(struct k_work_q *queue,
			k_thread_stack_t *stack,
			size_t stack_size,
			int prio,
			const struct k_work_queue_config *cfg)
{
    589c:	b5f0      	push	{r4, r5, r6, r7, lr}
    589e:	b089      	sub	sp, #36	; 0x24
    58a0:	4604      	mov	r4, r0
    58a2:	9d0e      	ldr	r5, [sp, #56]	; 0x38
	list->head = NULL;
    58a4:	2000      	movs	r0, #0
    58a6:	f8c4 00b8 	str.w	r0, [r4, #184]	; 0xb8
	list->tail = NULL;
    58aa:	f8c4 00bc 	str.w	r0, [r4, #188]	; 0xbc
    58ae:	f104 00c0 	add.w	r0, r4, #192	; 0xc0
	list->head = (sys_dnode_t *)list;
    58b2:	f8c4 00c0 	str.w	r0, [r4, #192]	; 0xc0
	list->tail = (sys_dnode_t *)list;
    58b6:	f8c4 00c4 	str.w	r0, [r4, #196]	; 0xc4
    58ba:	f104 00c8 	add.w	r0, r4, #200	; 0xc8
	list->head = (sys_dnode_t *)list;
    58be:	f8c4 00c8 	str.w	r0, [r4, #200]	; 0xc8
	list->tail = (sys_dnode_t *)list;
    58c2:	f8c4 00cc 	str.w	r0, [r4, #204]	; 0xcc

	sys_slist_init(&queue->pending);
	z_waitq_init(&queue->notifyq);
	z_waitq_init(&queue->drainq);

	if ((cfg != NULL) && cfg->no_yield) {
    58c6:	b1fd      	cbz	r5, 5908 <k_work_queue_start+0x6c>
    58c8:	7928      	ldrb	r0, [r5, #4]
    58ca:	b9f8      	cbnz	r0, 590c <k_work_queue_start+0x70>
	uint32_t flags = K_WORK_QUEUE_STARTED;
    58cc:	2001      	movs	r0, #1
	*flagp = flags;
    58ce:	f8c4 00d0 	str.w	r0, [r4, #208]	; 0xd0
	return z_impl_k_thread_create(new_thread, stack, stack_size, entry, p1, p2, p3, prio, options, delay);
    58d2:	f04f 36ff 	mov.w	r6, #4294967295
    58d6:	f04f 37ff 	mov.w	r7, #4294967295
    58da:	e9cd 6706 	strd	r6, r7, [sp, #24]
    58de:	2000      	movs	r0, #0
    58e0:	9004      	str	r0, [sp, #16]
    58e2:	9303      	str	r3, [sp, #12]
    58e4:	9002      	str	r0, [sp, #8]
    58e6:	9001      	str	r0, [sp, #4]
    58e8:	9400      	str	r4, [sp, #0]
    58ea:	4b0a      	ldr	r3, [pc, #40]	; (5914 <k_work_queue_start+0x78>)
    58ec:	4620      	mov	r0, r4
    58ee:	f001 fae0 	bl	6eb2 <z_impl_k_thread_create>

	(void)k_thread_create(&queue->thread, stack, stack_size,
			      work_queue_main, queue, NULL, NULL,
			      prio, 0, K_FOREVER);

	if ((cfg != NULL) && (cfg->name != NULL)) {
    58f2:	b125      	cbz	r5, 58fe <k_work_queue_start+0x62>
    58f4:	6829      	ldr	r1, [r5, #0]
    58f6:	b111      	cbz	r1, 58fe <k_work_queue_start+0x62>
	return z_impl_k_thread_name_set(thread, str);
    58f8:	4620      	mov	r0, r4
    58fa:	f7fe fd49 	bl	4390 <z_impl_k_thread_name_set>
	z_impl_k_thread_start(thread);
    58fe:	4620      	mov	r0, r4
    5900:	f001 fac8 	bl	6e94 <z_impl_k_thread_start>
	}

	k_thread_start(&queue->thread);

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_work_queue, start, queue);
}
    5904:	b009      	add	sp, #36	; 0x24
    5906:	bdf0      	pop	{r4, r5, r6, r7, pc}
	uint32_t flags = K_WORK_QUEUE_STARTED;
    5908:	2001      	movs	r0, #1
    590a:	e7e0      	b.n	58ce <k_work_queue_start+0x32>
		flags |= K_WORK_QUEUE_NO_YIELD;
    590c:	f240 1001 	movw	r0, #257	; 0x101
    5910:	e7dd      	b.n	58ce <k_work_queue_start+0x32>
    5912:	bf00      	nop
    5914:	000057ad 	.word	0x000057ad

00005918 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    5918:	4602      	mov	r2, r0
    591a:	b1b0      	cbz	r0, 594a <sys_notify_validate+0x32>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    591c:	6843      	ldr	r3, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    591e:	f003 0303 	and.w	r3, r3, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    5922:	2b02      	cmp	r3, #2
    5924:	d00b      	beq.n	593e <sys_notify_validate+0x26>
    5926:	2b03      	cmp	r3, #3
    5928:	d004      	beq.n	5934 <sys_notify_validate+0x1c>
    592a:	2b01      	cmp	r3, #1
    592c:	d004      	beq.n	5938 <sys_notify_validate+0x20>
    592e:	f06f 0015 	mvn.w	r0, #21
    5932:	4770      	bx	lr
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    5934:	6803      	ldr	r3, [r0, #0]
    5936:	b15b      	cbz	r3, 5950 <sys_notify_validate+0x38>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    5938:	2000      	movs	r0, #0
    593a:	6090      	str	r0, [r2, #8]
    593c:	4770      	bx	lr
		if (notify->method.signal == NULL) {
    593e:	6803      	ldr	r3, [r0, #0]
    5940:	2b00      	cmp	r3, #0
    5942:	d1f9      	bne.n	5938 <sys_notify_validate+0x20>
			rv = -EINVAL;
    5944:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    5948:	4770      	bx	lr
		return -EINVAL;
    594a:	f06f 0015 	mvn.w	r0, #21
    594e:	4770      	bx	lr
			rv = -EINVAL;
    5950:	f06f 0015 	mvn.w	r0, #21
    5954:	4770      	bx	lr

00005956 <sys_notify_finalize>:

sys_notify_generic_callback sys_notify_finalize(struct sys_notify *notify,
						    int res)
{
    5956:	b510      	push	{r4, lr}
    5958:	4603      	mov	r3, r0
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    595a:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    595c:	f002 0203 	and.w	r2, r2, #3
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    5960:	6081      	str	r1, [r0, #8]
	switch (method) {
    5962:	2a02      	cmp	r2, #2
    5964:	d004      	beq.n	5970 <sys_notify_finalize+0x1a>
    5966:	2a03      	cmp	r2, #3
    5968:	d105      	bne.n	5976 <sys_notify_finalize+0x20>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    596a:	6804      	ldr	r4, [r0, #0]
	struct k_poll_signal *sig = NULL;
    596c:	2000      	movs	r0, #0
		break;
    596e:	e004      	b.n	597a <sys_notify_finalize+0x24>
	case SYS_NOTIFY_METHOD_SIGNAL:
		sig = notify->method.signal;
    5970:	6800      	ldr	r0, [r0, #0]
	sys_notify_generic_callback rv = NULL;
    5972:	2400      	movs	r4, #0
		break;
    5974:	e001      	b.n	597a <sys_notify_finalize+0x24>
	switch (method) {
    5976:	2400      	movs	r4, #0
    5978:	4620      	mov	r0, r4
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    597a:	2200      	movs	r2, #0
    597c:	605a      	str	r2, [r3, #4]

	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
    597e:	b108      	cbz	r0, 5984 <sys_notify_finalize+0x2e>
	return z_impl_k_poll_signal_raise(sig, result);
    5980:	f7ff fe1a 	bl	55b8 <z_impl_k_poll_signal_raise>
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    5984:	4620      	mov	r0, r4
    5986:	bd10      	pop	{r4, pc}

00005988 <arch_printk_char_out>:
}
    5988:	2000      	movs	r0, #0
    598a:	4770      	bx	lr

0000598c <str_out>:
{
    598c:	b410      	push	{r4}
	if (ctx->str == NULL || ctx->count >= ctx->max) {
    598e:	680c      	ldr	r4, [r1, #0]
    5990:	b154      	cbz	r4, 59a8 <str_out+0x1c>
    5992:	688a      	ldr	r2, [r1, #8]
    5994:	684b      	ldr	r3, [r1, #4]
    5996:	429a      	cmp	r2, r3
    5998:	da06      	bge.n	59a8 <str_out+0x1c>
	if (ctx->count == ctx->max - 1) {
    599a:	3b01      	subs	r3, #1
    599c:	429a      	cmp	r2, r3
    599e:	d008      	beq.n	59b2 <str_out+0x26>
		ctx->str[ctx->count++] = c;
    59a0:	1c53      	adds	r3, r2, #1
    59a2:	608b      	str	r3, [r1, #8]
    59a4:	54a0      	strb	r0, [r4, r2]
    59a6:	e002      	b.n	59ae <str_out+0x22>
		ctx->count++;
    59a8:	688b      	ldr	r3, [r1, #8]
    59aa:	3301      	adds	r3, #1
    59ac:	608b      	str	r3, [r1, #8]
}
    59ae:	bc10      	pop	{r4}
    59b0:	4770      	bx	lr
		ctx->str[ctx->count++] = '\0';
    59b2:	1c53      	adds	r3, r2, #1
    59b4:	608b      	str	r3, [r1, #8]
    59b6:	2300      	movs	r3, #0
    59b8:	54a3      	strb	r3, [r4, r2]
    59ba:	e7f8      	b.n	59ae <str_out+0x22>

000059bc <printk>:
{
    59bc:	b40f      	push	{r0, r1, r2, r3}
    59be:	b500      	push	{lr}
    59c0:	b083      	sub	sp, #12
    59c2:	a904      	add	r1, sp, #16
    59c4:	f851 0b04 	ldr.w	r0, [r1], #4
	va_start(ap, fmt);
    59c8:	9101      	str	r1, [sp, #4]
		vprintk(fmt, ap);
    59ca:	f7fa fd83 	bl	4d4 <vprintk>
}
    59ce:	b003      	add	sp, #12
    59d0:	f85d eb04 	ldr.w	lr, [sp], #4
    59d4:	b004      	add	sp, #16
    59d6:	4770      	bx	lr

000059d8 <snprintk>:
{
    59d8:	b40c      	push	{r2, r3}
    59da:	b500      	push	{lr}
    59dc:	b083      	sub	sp, #12
    59de:	ab04      	add	r3, sp, #16
    59e0:	f853 2b04 	ldr.w	r2, [r3], #4
	va_start(ap, fmt);
    59e4:	9301      	str	r3, [sp, #4]
	ret = vsnprintk(str, size, fmt, ap);
    59e6:	f7fa fd85 	bl	4f4 <vsnprintk>
}
    59ea:	b003      	add	sp, #12
    59ec:	f85d eb04 	ldr.w	lr, [sp], #4
    59f0:	b002      	add	sp, #8
    59f2:	4770      	bx	lr

000059f4 <set_state>:
	mgr->flags = (state & ONOFF_STATE_MASK)
    59f4:	f001 0307 	and.w	r3, r1, #7
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    59f8:	8b01      	ldrh	r1, [r0, #24]
    59fa:	f021 0107 	bic.w	r1, r1, #7
    59fe:	4319      	orrs	r1, r3
	mgr->flags = (state & ONOFF_STATE_MASK)
    5a00:	8301      	strh	r1, [r0, #24]
}
    5a02:	4770      	bx	lr

00005a04 <notify_monitors>:
{
    5a04:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5a08:	4606      	mov	r6, r0
    5a0a:	460f      	mov	r7, r1
    5a0c:	4690      	mov	r8, r2
	return list->head;
    5a0e:	6881      	ldr	r1, [r0, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    5a10:	b119      	cbz	r1, 5a1a <notify_monitors+0x16>
    5a12:	460c      	mov	r4, r1
Z_GENLIST_PEEK_NEXT(slist, snode)
    5a14:	b131      	cbz	r1, 5a24 <notify_monitors+0x20>
	return node->next;
    5a16:	680c      	ldr	r4, [r1, #0]
    5a18:	e004      	b.n	5a24 <notify_monitors+0x20>
    5a1a:	460c      	mov	r4, r1
    5a1c:	e002      	b.n	5a24 <notify_monitors+0x20>
    5a1e:	4623      	mov	r3, r4
    5a20:	4621      	mov	r1, r4
    5a22:	461c      	mov	r4, r3
    5a24:	b159      	cbz	r1, 5a3e <notify_monitors+0x3a>
		mon->callback(mgr, mon, state, res);
    5a26:	684d      	ldr	r5, [r1, #4]
    5a28:	4643      	mov	r3, r8
    5a2a:	463a      	mov	r2, r7
    5a2c:	4630      	mov	r0, r6
    5a2e:	47a8      	blx	r5
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    5a30:	2c00      	cmp	r4, #0
    5a32:	d0f4      	beq.n	5a1e <notify_monitors+0x1a>
    5a34:	4623      	mov	r3, r4
Z_GENLIST_PEEK_NEXT(slist, snode)
    5a36:	2c00      	cmp	r4, #0
    5a38:	d0f2      	beq.n	5a20 <notify_monitors+0x1c>
	return node->next;
    5a3a:	6823      	ldr	r3, [r4, #0]
    5a3c:	e7f0      	b.n	5a20 <notify_monitors+0x1c>
}
    5a3e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005a42 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5a42:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    5a44:	f013 0307 	ands.w	r3, r3, #7
    5a48:	d103      	bne.n	5a52 <process_recheck+0x10>
	return list->head;
    5a4a:	6802      	ldr	r2, [r0, #0]
	    && !sys_slist_is_empty(&mgr->clients)) {
    5a4c:	b10a      	cbz	r2, 5a52 <process_recheck+0x10>
		evt = EVT_START;
    5a4e:	2003      	movs	r0, #3
    5a50:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    5a52:	2b02      	cmp	r3, #2
    5a54:	d003      	beq.n	5a5e <process_recheck+0x1c>
	} else if ((state == ONOFF_STATE_ERROR)
    5a56:	2b01      	cmp	r3, #1
    5a58:	d006      	beq.n	5a68 <process_recheck+0x26>
	int evt = EVT_NOP;
    5a5a:	2000      	movs	r0, #0
    5a5c:	4770      	bx	lr
		   && (mgr->refs == 0U)) {
    5a5e:	8b42      	ldrh	r2, [r0, #26]
    5a60:	2a00      	cmp	r2, #0
    5a62:	d1f8      	bne.n	5a56 <process_recheck+0x14>
		evt = EVT_STOP;
    5a64:	2004      	movs	r0, #4
    5a66:	4770      	bx	lr
    5a68:	6803      	ldr	r3, [r0, #0]
		   && !sys_slist_is_empty(&mgr->clients)) {
    5a6a:	b10b      	cbz	r3, 5a70 <process_recheck+0x2e>
		evt = EVT_RESET;
    5a6c:	2005      	movs	r0, #5
}
    5a6e:	4770      	bx	lr
	int evt = EVT_NOP;
    5a70:	2000      	movs	r0, #0
    5a72:	4770      	bx	lr

00005a74 <process_complete>:
{
    5a74:	b538      	push	{r3, r4, r5, lr}
    5a76:	4604      	mov	r4, r0
    5a78:	460d      	mov	r5, r1
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5a7a:	8b03      	ldrh	r3, [r0, #24]
	if (res < 0) {
    5a7c:	2a00      	cmp	r2, #0
    5a7e:	db07      	blt.n	5a90 <process_complete+0x1c>
    5a80:	f003 0307 	and.w	r3, r3, #7
		   || (state == ONOFF_STATE_RESETTING)) {
    5a84:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
    5a86:	2a01      	cmp	r2, #1
    5a88:	d90e      	bls.n	5aa8 <process_complete+0x34>
	} else if (state == ONOFF_STATE_TO_OFF) {
    5a8a:	2b04      	cmp	r3, #4
    5a8c:	d032      	beq.n	5af4 <process_complete+0x80>
}
    5a8e:	bd38      	pop	{r3, r4, r5, pc}
		*clients = mgr->clients;
    5a90:	e9d0 0100 	ldrd	r0, r1, [r0]
    5a94:	e885 0003 	stmia.w	r5, {r0, r1}
	list->head = NULL;
    5a98:	2300      	movs	r3, #0
    5a9a:	6023      	str	r3, [r4, #0]
	list->tail = NULL;
    5a9c:	6063      	str	r3, [r4, #4]
		set_state(mgr, ONOFF_STATE_ERROR);
    5a9e:	2101      	movs	r1, #1
    5aa0:	4620      	mov	r0, r4
    5aa2:	f7ff ffa7 	bl	59f4 <set_state>
    5aa6:	e7f2      	b.n	5a8e <process_complete+0x1a>
		*clients = mgr->clients;
    5aa8:	e9d0 0100 	ldrd	r0, r1, [r0]
    5aac:	e885 0003 	stmia.w	r5, {r0, r1}
	list->head = NULL;
    5ab0:	2200      	movs	r2, #0
    5ab2:	6022      	str	r2, [r4, #0]
	list->tail = NULL;
    5ab4:	6062      	str	r2, [r4, #4]
		if (state == ONOFF_STATE_TO_ON) {
    5ab6:	2b06      	cmp	r3, #6
    5ab8:	d117      	bne.n	5aea <process_complete+0x76>
	return list->head;
    5aba:	682b      	ldr	r3, [r5, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    5abc:	b13b      	cbz	r3, 5ace <process_complete+0x5a>
				mgr->refs += 1U;
    5abe:	8b62      	ldrh	r2, [r4, #26]
    5ac0:	3201      	adds	r2, #1
    5ac2:	8362      	strh	r2, [r4, #26]
Z_GENLIST_PEEK_NEXT(slist, snode)
    5ac4:	2b00      	cmp	r3, #0
    5ac6:	d0f9      	beq.n	5abc <process_complete+0x48>
	return node->next;
    5ac8:	681b      	ldr	r3, [r3, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    5aca:	2b00      	cmp	r3, #0
    5acc:	d1f6      	bne.n	5abc <process_complete+0x48>
			set_state(mgr, ONOFF_STATE_ON);
    5ace:	2102      	movs	r1, #2
    5ad0:	4620      	mov	r0, r4
    5ad2:	f7ff ff8f 	bl	59f4 <set_state>
		if (process_recheck(mgr) != EVT_NOP) {
    5ad6:	4620      	mov	r0, r4
    5ad8:	f7ff ffb3 	bl	5a42 <process_recheck>
    5adc:	2800      	cmp	r0, #0
    5ade:	d0d6      	beq.n	5a8e <process_complete+0x1a>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    5ae0:	8b23      	ldrh	r3, [r4, #24]
    5ae2:	f043 0320 	orr.w	r3, r3, #32
    5ae6:	8323      	strh	r3, [r4, #24]
    5ae8:	e7d1      	b.n	5a8e <process_complete+0x1a>
			set_state(mgr, ONOFF_STATE_OFF);
    5aea:	2100      	movs	r1, #0
    5aec:	4620      	mov	r0, r4
    5aee:	f7ff ff81 	bl	59f4 <set_state>
    5af2:	e7f0      	b.n	5ad6 <process_complete+0x62>
		set_state(mgr, ONOFF_STATE_OFF);
    5af4:	2100      	movs	r1, #0
    5af6:	f7ff ff7d 	bl	59f4 <set_state>
		if (process_recheck(mgr) != EVT_NOP) {
    5afa:	4620      	mov	r0, r4
    5afc:	f7ff ffa1 	bl	5a42 <process_recheck>
    5b00:	2800      	cmp	r0, #0
    5b02:	d0c4      	beq.n	5a8e <process_complete+0x1a>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    5b04:	8b23      	ldrh	r3, [r4, #24]
    5b06:	f043 0320 	orr.w	r3, r3, #32
    5b0a:	8323      	strh	r3, [r4, #24]
}
    5b0c:	e7bf      	b.n	5a8e <process_complete+0x1a>

00005b0e <validate_args>:
	if ((mgr == NULL) || (cli == NULL)) {
    5b0e:	b158      	cbz	r0, 5b28 <validate_args+0x1a>
{
    5b10:	b510      	push	{r4, lr}
    5b12:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    5b14:	b159      	cbz	r1, 5b2e <validate_args+0x20>
	int rv = sys_notify_validate(&cli->notify);
    5b16:	1d08      	adds	r0, r1, #4
    5b18:	f7ff fefe 	bl	5918 <sys_notify_validate>
	if ((rv == 0)
    5b1c:	b918      	cbnz	r0, 5b26 <validate_args+0x18>
	    && ((cli->notify.flags
    5b1e:	68a3      	ldr	r3, [r4, #8]
    5b20:	f033 0303 	bics.w	r3, r3, #3
    5b24:	d106      	bne.n	5b34 <validate_args+0x26>
}
    5b26:	bd10      	pop	{r4, pc}
		return -EINVAL;
    5b28:	f06f 0015 	mvn.w	r0, #21
}
    5b2c:	4770      	bx	lr
		return -EINVAL;
    5b2e:	f06f 0015 	mvn.w	r0, #21
    5b32:	e7f8      	b.n	5b26 <validate_args+0x18>
		rv = -EINVAL;
    5b34:	f06f 0015 	mvn.w	r0, #21
    5b38:	e7f5      	b.n	5b26 <validate_args+0x18>

00005b3a <notify_one>:
{
    5b3a:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5b3e:	4607      	mov	r7, r0
    5b40:	460c      	mov	r4, r1
    5b42:	4616      	mov	r6, r2
    5b44:	461d      	mov	r5, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5b46:	4619      	mov	r1, r3
    5b48:	1d20      	adds	r0, r4, #4
    5b4a:	f7ff ff04 	bl	5956 <sys_notify_finalize>
	if (cb) {
    5b4e:	b128      	cbz	r0, 5b5c <notify_one+0x22>
    5b50:	4680      	mov	r8, r0
		cb(mgr, cli, state, res);
    5b52:	462b      	mov	r3, r5
    5b54:	4632      	mov	r2, r6
    5b56:	4621      	mov	r1, r4
    5b58:	4638      	mov	r0, r7
    5b5a:	47c0      	blx	r8
}
    5b5c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005b60 <notify_all>:
{
    5b60:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    5b64:	4681      	mov	r9, r0
    5b66:	460c      	mov	r4, r1
    5b68:	4690      	mov	r8, r2
    5b6a:	461f      	mov	r7, r3
	while (!sys_slist_is_empty(list)) {
    5b6c:	e005      	b.n	5b7a <notify_all+0x1a>
	list->tail = node;
    5b6e:	6065      	str	r5, [r4, #4]
		notify_one(mgr, cli, state, res);
    5b70:	463b      	mov	r3, r7
    5b72:	4642      	mov	r2, r8
    5b74:	4648      	mov	r0, r9
    5b76:	f7ff ffe0 	bl	5b3a <notify_one>
	return list->head;
    5b7a:	6821      	ldr	r1, [r4, #0]
	while (!sys_slist_is_empty(list)) {
    5b7c:	b129      	cbz	r1, 5b8a <notify_all+0x2a>
	return node->next;
    5b7e:	680d      	ldr	r5, [r1, #0]
	list->head = node;
    5b80:	6025      	str	r5, [r4, #0]
	return list->tail;
    5b82:	6866      	ldr	r6, [r4, #4]
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    5b84:	428e      	cmp	r6, r1
    5b86:	d1f3      	bne.n	5b70 <notify_all+0x10>
    5b88:	e7f1      	b.n	5b6e <notify_all+0xe>
}
    5b8a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

00005b8e <transition_complete>:
{
    5b8e:	b510      	push	{r4, lr}
	__asm__ volatile(
    5b90:	f04f 0420 	mov.w	r4, #32
    5b94:	f3ef 8211 	mrs	r2, BASEPRI
    5b98:	f384 8812 	msr	BASEPRI_MAX, r4
    5b9c:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    5ba0:	6141      	str	r1, [r0, #20]
	process_event(mgr, EVT_COMPLETE, key);
    5ba2:	2101      	movs	r1, #1
    5ba4:	f7fa fcbc 	bl	520 <process_event>
}
    5ba8:	bd10      	pop	{r4, pc}

00005baa <onoff_manager_init>:
	if ((mgr == NULL)
    5baa:	4603      	mov	r3, r0
    5bac:	b168      	cbz	r0, 5bca <onoff_manager_init+0x20>
	    || (transitions == NULL)
    5bae:	b179      	cbz	r1, 5bd0 <onoff_manager_init+0x26>
	    || (transitions->start == NULL)
    5bb0:	680a      	ldr	r2, [r1, #0]
    5bb2:	b182      	cbz	r2, 5bd6 <onoff_manager_init+0x2c>
	    || (transitions->stop == NULL)) {
    5bb4:	684a      	ldr	r2, [r1, #4]
    5bb6:	b18a      	cbz	r2, 5bdc <onoff_manager_init+0x32>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    5bb8:	2000      	movs	r0, #0
    5bba:	6018      	str	r0, [r3, #0]
    5bbc:	6058      	str	r0, [r3, #4]
    5bbe:	6098      	str	r0, [r3, #8]
    5bc0:	60d8      	str	r0, [r3, #12]
    5bc2:	6158      	str	r0, [r3, #20]
    5bc4:	6198      	str	r0, [r3, #24]
    5bc6:	6119      	str	r1, [r3, #16]
	return 0;
    5bc8:	4770      	bx	lr
		return -EINVAL;
    5bca:	f06f 0015 	mvn.w	r0, #21
    5bce:	4770      	bx	lr
    5bd0:	f06f 0015 	mvn.w	r0, #21
    5bd4:	4770      	bx	lr
    5bd6:	f06f 0015 	mvn.w	r0, #21
    5bda:	4770      	bx	lr
    5bdc:	f06f 0015 	mvn.w	r0, #21
}
    5be0:	4770      	bx	lr

00005be2 <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    5be2:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    5be4:	4604      	mov	r4, r0
    5be6:	460f      	mov	r7, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    5be8:	f7ff ff91 	bl	5b0e <validate_args>

	if (rv < 0) {
    5bec:	1e06      	subs	r6, r0, #0
    5bee:	db37      	blt.n	5c60 <onoff_request+0x7e>
    5bf0:	f04f 0320 	mov.w	r3, #32
    5bf4:	f3ef 8211 	mrs	r2, BASEPRI
    5bf8:	f383 8812 	msr	BASEPRI_MAX, r3
    5bfc:	f3bf 8f6f 	isb	sy
		return rv;
	}

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5c00:	8b25      	ldrh	r5, [r4, #24]
    5c02:	f005 0507 	and.w	r5, r5, #7

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    5c06:	8b63      	ldrh	r3, [r4, #26]
    5c08:	f64f 71ff 	movw	r1, #65535	; 0xffff
    5c0c:	428b      	cmp	r3, r1
    5c0e:	d02f      	beq.n	5c70 <onoff_request+0x8e>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
    5c10:	462e      	mov	r6, r5
	if (state == ONOFF_STATE_ON) {
    5c12:	2d02      	cmp	r5, #2
    5c14:	d00c      	beq.n	5c30 <onoff_request+0x4e>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
	} else if ((state == ONOFF_STATE_OFF)
    5c16:	b18d      	cbz	r5, 5c3c <onoff_request+0x5a>
		   || (state == ONOFF_STATE_TO_OFF)
    5c18:	2d04      	cmp	r5, #4
    5c1a:	d00f      	beq.n	5c3c <onoff_request+0x5a>
		   || (state == ONOFF_STATE_TO_ON)) {
    5c1c:	2d06      	cmp	r5, #6
    5c1e:	d00d      	beq.n	5c3c <onoff_request+0x5a>
		/* Start if OFF, queue client */
		start = (state == ONOFF_STATE_OFF);
		add_client = true;
	} else if (state == ONOFF_STATE_RESETTING) {
    5c20:	2d05      	cmp	r5, #5
    5c22:	d01f      	beq.n	5c64 <onoff_request+0x82>
		rv = -ENOTSUP;
	} else {
		__ASSERT_NO_MSG(state == ONOFF_STATE_ERROR);
		rv = -EIO;
    5c24:	f06f 0604 	mvn.w	r6, #4
	bool notify = false;            /* do client notification */
    5c28:	2100      	movs	r1, #0
	bool start = false;             /* trigger a start transition */
    5c2a:	460b      	mov	r3, r1
	bool add_client = false;        /* add client to pending list */
    5c2c:	4608      	mov	r0, r1
    5c2e:	e00a      	b.n	5c46 <onoff_request+0x64>
		mgr->refs += 1U;
    5c30:	3301      	adds	r3, #1
    5c32:	8363      	strh	r3, [r4, #26]
		notify = true;
    5c34:	2101      	movs	r1, #1
	bool start = false;             /* trigger a start transition */
    5c36:	2300      	movs	r3, #0
	bool add_client = false;        /* add client to pending list */
    5c38:	4618      	mov	r0, r3
    5c3a:	e004      	b.n	5c46 <onoff_request+0x64>
		start = (state == ONOFF_STATE_OFF);
    5c3c:	fab5 f385 	clz	r3, r5
    5c40:	095b      	lsrs	r3, r3, #5
	bool notify = false;            /* do client notification */
    5c42:	2100      	movs	r1, #0
		add_client = true;
    5c44:	2001      	movs	r0, #1
	}

out:
	if (add_client) {
    5c46:	b128      	cbz	r0, 5c54 <onoff_request+0x72>
	parent->next = child;
    5c48:	2000      	movs	r0, #0
    5c4a:	6038      	str	r0, [r7, #0]
	return list->tail;
    5c4c:	6860      	ldr	r0, [r4, #4]
Z_GENLIST_APPEND(slist, snode)
    5c4e:	b1a8      	cbz	r0, 5c7c <onoff_request+0x9a>
	parent->next = child;
    5c50:	6007      	str	r7, [r0, #0]
	list->tail = node;
    5c52:	6067      	str	r7, [r4, #4]
		sys_slist_append(&mgr->clients, &cli->node);
	}

	if (start) {
    5c54:	b9ab      	cbnz	r3, 5c82 <onoff_request+0xa0>
	__asm__ volatile(
    5c56:	f382 8811 	msr	BASEPRI, r2
    5c5a:	f3bf 8f6f 	isb	sy
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    5c5e:	b9a9      	cbnz	r1, 5c8c <onoff_request+0xaa>
			notify_one(mgr, cli, state, 0);
		}
	}

	return rv;
}
    5c60:	4630      	mov	r0, r6
    5c62:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		rv = -ENOTSUP;
    5c64:	f06f 0685 	mvn.w	r6, #133	; 0x85
	bool notify = false;            /* do client notification */
    5c68:	2100      	movs	r1, #0
	bool start = false;             /* trigger a start transition */
    5c6a:	460b      	mov	r3, r1
	bool add_client = false;        /* add client to pending list */
    5c6c:	4608      	mov	r0, r1
    5c6e:	e7ea      	b.n	5c46 <onoff_request+0x64>
		rv = -EAGAIN;
    5c70:	f06f 060a 	mvn.w	r6, #10
	bool notify = false;            /* do client notification */
    5c74:	2100      	movs	r1, #0
	bool start = false;             /* trigger a start transition */
    5c76:	460b      	mov	r3, r1
	bool add_client = false;        /* add client to pending list */
    5c78:	4608      	mov	r0, r1
    5c7a:	e7e4      	b.n	5c46 <onoff_request+0x64>
    5c7c:	6067      	str	r7, [r4, #4]
	list->head = node;
    5c7e:	6027      	str	r7, [r4, #0]
}
    5c80:	e7e8      	b.n	5c54 <onoff_request+0x72>
		process_event(mgr, EVT_RECHECK, key);
    5c82:	2102      	movs	r1, #2
    5c84:	4620      	mov	r0, r4
    5c86:	f7fa fc4b 	bl	520 <process_event>
    5c8a:	e7e9      	b.n	5c60 <onoff_request+0x7e>
			notify_one(mgr, cli, state, 0);
    5c8c:	2300      	movs	r3, #0
    5c8e:	462a      	mov	r2, r5
    5c90:	4639      	mov	r1, r7
    5c92:	4620      	mov	r0, r4
    5c94:	f7ff ff51 	bl	5b3a <notify_one>
    5c98:	e7e2      	b.n	5c60 <onoff_request+0x7e>

00005c9a <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    5c9a:	b508      	push	{r3, lr}
    5c9c:	4604      	mov	r4, r0
    5c9e:	4608      	mov	r0, r1
    5ca0:	4611      	mov	r1, r2
#ifdef CONFIG_THREAD_LOCAL_STORAGE
	z_tls_current = z_current_get();
#endif
	entry(p1, p2, p3);
    5ca2:	461a      	mov	r2, r3
    5ca4:	47a0      	blx	r4
	return z_impl_z_current_get();
    5ca6:	f7ff f807 	bl	4cb8 <z_impl_z_current_get>
	z_impl_k_thread_abort(thread);
    5caa:	f7fb fd83 	bl	17b4 <z_impl_k_thread_abort>

00005cae <extract_decimal>:
{
    5cae:	b410      	push	{r4}
    5cb0:	4604      	mov	r4, r0
	const char *sp = *str;
    5cb2:	6802      	ldr	r2, [r0, #0]
	size_t val = 0;
    5cb4:	2000      	movs	r0, #0
	while (isdigit((int)(unsigned char)*sp)) {
    5cb6:	7813      	ldrb	r3, [r2, #0]
			(((unsigned)c) <= (unsigned)'~'));
}

static inline int isdigit(int a)
{
	return (int)(((unsigned)(a)-(unsigned)'0') < 10U);
    5cb8:	f1a3 0130 	sub.w	r1, r3, #48	; 0x30
    5cbc:	2909      	cmp	r1, #9
    5cbe:	d806      	bhi.n	5cce <extract_decimal+0x20>
		val = 10U * val + *sp++ - '0';
    5cc0:	eb00 0080 	add.w	r0, r0, r0, lsl #2
    5cc4:	3201      	adds	r2, #1
    5cc6:	eb03 0040 	add.w	r0, r3, r0, lsl #1
    5cca:	3830      	subs	r0, #48	; 0x30
    5ccc:	e7f3      	b.n	5cb6 <extract_decimal+0x8>
	*str = sp;
    5cce:	6022      	str	r2, [r4, #0]
}
    5cd0:	bc10      	pop	{r4}
    5cd2:	4770      	bx	lr

00005cd4 <encode_uint>:
{
    5cd4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    5cd8:	b083      	sub	sp, #12
    5cda:	4604      	mov	r4, r0
    5cdc:	460d      	mov	r5, r1
    5cde:	9201      	str	r2, [sp, #4]
    5ce0:	469a      	mov	sl, r3
    5ce2:	f8dd 8030 	ldr.w	r8, [sp, #48]	; 0x30
	bool upcase = isupper((int)conv->specifier);
    5ce6:	78d3      	ldrb	r3, [r2, #3]
	return (int)(((unsigned)(a)-(unsigned)'A') < 26U);
    5ce8:	f1a3 0b41 	sub.w	fp, r3, #65	; 0x41
	switch (specifier) {
    5cec:	2b6f      	cmp	r3, #111	; 0x6f
    5cee:	d00f      	beq.n	5d10 <encode_uint+0x3c>
    5cf0:	d906      	bls.n	5d00 <encode_uint+0x2c>
    5cf2:	2b70      	cmp	r3, #112	; 0x70
    5cf4:	d00f      	beq.n	5d16 <encode_uint+0x42>
    5cf6:	2b78      	cmp	r3, #120	; 0x78
    5cf8:	d110      	bne.n	5d1c <encode_uint+0x48>
		return 16;
    5cfa:	f04f 0910 	mov.w	r9, #16
    5cfe:	e026      	b.n	5d4e <encode_uint+0x7a>
	switch (specifier) {
    5d00:	2b58      	cmp	r3, #88	; 0x58
    5d02:	d002      	beq.n	5d0a <encode_uint+0x36>
    5d04:	f04f 090a 	mov.w	r9, #10
    5d08:	e021      	b.n	5d4e <encode_uint+0x7a>
		return 16;
    5d0a:	f04f 0910 	mov.w	r9, #16
    5d0e:	e01e      	b.n	5d4e <encode_uint+0x7a>
		return 8;
    5d10:	f04f 0908 	mov.w	r9, #8
    5d14:	e01b      	b.n	5d4e <encode_uint+0x7a>
		return 16;
    5d16:	f04f 0910 	mov.w	r9, #16
    5d1a:	e018      	b.n	5d4e <encode_uint+0x7a>
	switch (specifier) {
    5d1c:	f04f 090a 	mov.w	r9, #10
	char *bp = bps + (bpe - bps);
    5d20:	e015      	b.n	5d4e <encode_uint+0x7a>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5d22:	f1bb 0f19 	cmp.w	fp, #25
    5d26:	d820      	bhi.n	5d6a <encode_uint+0x96>
			: upcase ? ('A' + lsv - 10) : ('a' + lsv - 10);
    5d28:	b2d2      	uxtb	r2, r2
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5d2a:	3237      	adds	r2, #55	; 0x37
    5d2c:	b2d2      	uxtb	r2, r2
    5d2e:	f808 2d01 	strb.w	r2, [r8, #-1]!
		value /= radix;
    5d32:	4632      	mov	r2, r6
    5d34:	463b      	mov	r3, r7
    5d36:	4620      	mov	r0, r4
    5d38:	4629      	mov	r1, r5
    5d3a:	f7fa f9e1 	bl	100 <__aeabi_uldivmod>
	} while ((value != 0) && (bps < bp));
    5d3e:	42bd      	cmp	r5, r7
    5d40:	bf08      	it	eq
    5d42:	42b4      	cmpeq	r4, r6
    5d44:	d315      	bcc.n	5d72 <encode_uint+0x9e>
    5d46:	45d0      	cmp	r8, sl
    5d48:	d913      	bls.n	5d72 <encode_uint+0x9e>
		value /= radix;
    5d4a:	4604      	mov	r4, r0
    5d4c:	460d      	mov	r5, r1
		unsigned int lsv = (unsigned int)(value % radix);
    5d4e:	464e      	mov	r6, r9
    5d50:	2700      	movs	r7, #0
    5d52:	464a      	mov	r2, r9
    5d54:	463b      	mov	r3, r7
    5d56:	4620      	mov	r0, r4
    5d58:	4629      	mov	r1, r5
    5d5a:	f7fa f9d1 	bl	100 <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5d5e:	2a09      	cmp	r2, #9
    5d60:	d8df      	bhi.n	5d22 <encode_uint+0x4e>
    5d62:	b2d2      	uxtb	r2, r2
    5d64:	3230      	adds	r2, #48	; 0x30
    5d66:	b2d2      	uxtb	r2, r2
    5d68:	e7e1      	b.n	5d2e <encode_uint+0x5a>
			: upcase ? ('A' + lsv - 10) : ('a' + lsv - 10);
    5d6a:	b2d2      	uxtb	r2, r2
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5d6c:	3257      	adds	r2, #87	; 0x57
    5d6e:	b2d2      	uxtb	r2, r2
    5d70:	e7dd      	b.n	5d2e <encode_uint+0x5a>
	if (conv->flag_hash) {
    5d72:	9b01      	ldr	r3, [sp, #4]
    5d74:	781b      	ldrb	r3, [r3, #0]
    5d76:	f013 0f20 	tst.w	r3, #32
    5d7a:	d005      	beq.n	5d88 <encode_uint+0xb4>
		if (radix == 8) {
    5d7c:	f1b9 0f08 	cmp.w	r9, #8
    5d80:	d006      	beq.n	5d90 <encode_uint+0xbc>
		} else if (radix == 16) {
    5d82:	f1b9 0f10 	cmp.w	r9, #16
    5d86:	d009      	beq.n	5d9c <encode_uint+0xc8>
}
    5d88:	4640      	mov	r0, r8
    5d8a:	b003      	add	sp, #12
    5d8c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			conv->altform_0 = true;
    5d90:	9a01      	ldr	r2, [sp, #4]
    5d92:	7893      	ldrb	r3, [r2, #2]
    5d94:	f043 0308 	orr.w	r3, r3, #8
    5d98:	7093      	strb	r3, [r2, #2]
    5d9a:	e7f5      	b.n	5d88 <encode_uint+0xb4>
			conv->altform_0c = true;
    5d9c:	9a01      	ldr	r2, [sp, #4]
    5d9e:	7893      	ldrb	r3, [r2, #2]
    5da0:	f043 0310 	orr.w	r3, r3, #16
    5da4:	7093      	strb	r3, [r2, #2]
    5da6:	e7ef      	b.n	5d88 <encode_uint+0xb4>

00005da8 <outs>:
{
    5da8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5dac:	4607      	mov	r7, r0
    5dae:	460e      	mov	r6, r1
    5db0:	4614      	mov	r4, r2
    5db2:	4698      	mov	r8, r3
	size_t count = 0;
    5db4:	2500      	movs	r5, #0
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    5db6:	e006      	b.n	5dc6 <outs+0x1e>
		int rc = out((int)*sp++, ctx);
    5db8:	4631      	mov	r1, r6
    5dba:	f814 0b01 	ldrb.w	r0, [r4], #1
    5dbe:	47b8      	blx	r7
		if (rc < 0) {
    5dc0:	2800      	cmp	r0, #0
    5dc2:	db09      	blt.n	5dd8 <outs+0x30>
		++count;
    5dc4:	3501      	adds	r5, #1
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    5dc6:	4544      	cmp	r4, r8
    5dc8:	d3f6      	bcc.n	5db8 <outs+0x10>
    5dca:	f1b8 0f00 	cmp.w	r8, #0
    5dce:	d102      	bne.n	5dd6 <outs+0x2e>
    5dd0:	7823      	ldrb	r3, [r4, #0]
    5dd2:	2b00      	cmp	r3, #0
    5dd4:	d1f0      	bne.n	5db8 <outs+0x10>
	return (int)count;
    5dd6:	4628      	mov	r0, r5
}
    5dd8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005ddc <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_DISASSEMBLY, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_PRINT_MEMORY_USAGE, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    5ddc:	4770      	bx	lr

00005dde <pm_policy_next_state>:
			return pm_min_residency[i];
		}
	}

	LOG_DBG("No suitable power state found!");
	return (struct pm_state_info){PM_STATE_ACTIVE, 0, 0};
    5dde:	2200      	movs	r2, #0
    5de0:	6002      	str	r2, [r0, #0]
    5de2:	6042      	str	r2, [r0, #4]
    5de4:	6082      	str	r2, [r0, #8]
}
    5de6:	4770      	bx	lr

00005de8 <z_arm_fatal_error>:
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
		esf->basic.pc);
}

void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    5de8:	b508      	push	{r3, lr}

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    5dea:	f001 f821 	bl	6e30 <z_fatal_error>
}
    5dee:	bd08      	pop	{r3, pc}

00005df0 <z_do_kernel_oops>:
 *   fault handler will executed insted of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    5df0:	b508      	push	{r3, lr}
    5df2:	4601      	mov	r1, r0
	}

#endif /* CONFIG_USERSPACE */

#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	z_arm_fatal_error(reason, esf);
    5df4:	6800      	ldr	r0, [r0, #0]
    5df6:	f7ff fff7 	bl	5de8 <z_arm_fatal_error>

	memcpy(&esf_copy, esf, offsetof(z_arch_esf_t, extra_info));
	esf_copy.extra_info = (struct __extra_esf_info) { 0 };
	z_arm_fatal_error(reason, &esf_copy);
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
}
    5dfa:	bd08      	pop	{r3, pc}

00005dfc <z_irq_spurious>:
 * called.
 *
 * @return N/A
 */
void z_irq_spurious(const void *unused)
{
    5dfc:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    5dfe:	2100      	movs	r1, #0
    5e00:	2001      	movs	r0, #1
    5e02:	f7ff fff1 	bl	5de8 <z_arm_fatal_error>
}
    5e06:	bd08      	pop	{r3, pc}

00005e08 <z_arm_nmi>:
 *
 * @return N/A
 */

void z_arm_nmi(void)
{
    5e08:	b508      	push	{r3, lr}
	handler();
    5e0a:	f7fb fa29 	bl	1260 <z_SysNmiOnReset>
	z_arm_int_exit();
    5e0e:	f7fb fb25 	bl	145c <z_arm_exc_exit>
}
    5e12:	bd08      	pop	{r3, pc}

00005e14 <memory_fault_recoverable>:
}
    5e14:	2000      	movs	r0, #0
    5e16:	4770      	bx	lr

00005e18 <debug_monitor>:
	*recoverable = false;
    5e18:	2300      	movs	r3, #0
    5e1a:	700b      	strb	r3, [r1, #0]
}
    5e1c:	4770      	bx	lr

00005e1e <fault_handle>:
{
    5e1e:	b508      	push	{r3, lr}
	*recoverable = false;
    5e20:	2300      	movs	r3, #0
    5e22:	7013      	strb	r3, [r2, #0]
	switch (fault) {
    5e24:	1ecb      	subs	r3, r1, #3
    5e26:	2b09      	cmp	r3, #9
    5e28:	d81a      	bhi.n	5e60 <fault_handle+0x42>
    5e2a:	e8df f003 	tbb	[pc, r3]
    5e2e:	0905      	.short	0x0905
    5e30:	1919110d 	.word	0x1919110d
    5e34:	14191919 	.word	0x14191919
		reason = hard_fault(esf, recoverable);
    5e38:	4611      	mov	r1, r2
    5e3a:	f7fb fb9f 	bl	157c <hard_fault>
		break;
    5e3e:	e010      	b.n	5e62 <fault_handle+0x44>
		reason = mem_manage_fault(esf, 0, recoverable);
    5e40:	2100      	movs	r1, #0
    5e42:	f7fb fb55 	bl	14f0 <mem_manage_fault>
		break;
    5e46:	e00c      	b.n	5e62 <fault_handle+0x44>
		reason = bus_fault(esf, 0, recoverable);
    5e48:	2100      	movs	r1, #0
    5e4a:	f7fb fb15 	bl	1478 <bus_fault>
		break;
    5e4e:	e008      	b.n	5e62 <fault_handle+0x44>
		reason = usage_fault(esf);
    5e50:	f7fb fb3c 	bl	14cc <usage_fault>
		break;
    5e54:	e005      	b.n	5e62 <fault_handle+0x44>
		debug_monitor(esf, recoverable);
    5e56:	4611      	mov	r1, r2
    5e58:	f7ff ffde 	bl	5e18 <debug_monitor>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    5e5c:	2000      	movs	r0, #0
		break;
    5e5e:	e000      	b.n	5e62 <fault_handle+0x44>
	*recoverable = false;
    5e60:	2000      	movs	r0, #0
}
    5e62:	bd08      	pop	{r3, pc}

00005e64 <mpu_partition_is_valid>:
		((part->size & (part->size - 1U)) == 0U)
    5e64:	6843      	ldr	r3, [r0, #4]
    5e66:	1e5a      	subs	r2, r3, #1
		&&
    5e68:	4213      	tst	r3, r2
    5e6a:	d106      	bne.n	5e7a <mpu_partition_is_valid+0x16>
		&&
    5e6c:	2b1f      	cmp	r3, #31
    5e6e:	d906      	bls.n	5e7e <mpu_partition_is_valid+0x1a>
		((part->start & (part->size - 1U)) == 0U);
    5e70:	6803      	ldr	r3, [r0, #0]
		&&
    5e72:	421a      	tst	r2, r3
    5e74:	d005      	beq.n	5e82 <mpu_partition_is_valid+0x1e>
    5e76:	2000      	movs	r0, #0
    5e78:	4770      	bx	lr
    5e7a:	2000      	movs	r0, #0
    5e7c:	4770      	bx	lr
    5e7e:	2000      	movs	r0, #0
    5e80:	4770      	bx	lr
    5e82:	2001      	movs	r0, #1
}
    5e84:	4770      	bx	lr

00005e86 <region_allocate_and_init>:
	if (index > (get_num_regions() - 1U)) {
    5e86:	2807      	cmp	r0, #7
    5e88:	d805      	bhi.n	5e96 <region_allocate_and_init+0x10>
{
    5e8a:	b510      	push	{r4, lr}
    5e8c:	4604      	mov	r4, r0
	region_init(index, region_conf);
    5e8e:	f7fb fcc7 	bl	1820 <region_init>
	return index;
    5e92:	4620      	mov	r0, r4
}
    5e94:	bd10      	pop	{r4, pc}
		return -EINVAL;
    5e96:	f06f 0015 	mvn.w	r0, #21
}
    5e9a:	4770      	bx	lr

00005e9c <mpu_configure_region>:
{
    5e9c:	b500      	push	{lr}
    5e9e:	b085      	sub	sp, #20
	region_conf.base = new_region->start;
    5ea0:	680b      	ldr	r3, [r1, #0]
    5ea2:	9301      	str	r3, [sp, #4]
	get_region_attr_from_mpu_partition_info(&region_conf.attr,
    5ea4:	684b      	ldr	r3, [r1, #4]
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    5ea6:	688a      	ldr	r2, [r1, #8]
	if (size <= 32U) {
    5ea8:	2b20      	cmp	r3, #32
    5eaa:	d912      	bls.n	5ed2 <mpu_configure_region+0x36>
	if (size > (1UL << 31)) {
    5eac:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    5eb0:	d811      	bhi.n	5ed6 <mpu_configure_region+0x3a>
	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    5eb2:	3b01      	subs	r3, #1
    5eb4:	fab3 f383 	clz	r3, r3
    5eb8:	f1c3 031f 	rsb	r3, r3, #31
    5ebc:	005b      	lsls	r3, r3, #1
    5ebe:	f003 033e 	and.w	r3, r3, #62	; 0x3e
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    5ec2:	4313      	orrs	r3, r2
    5ec4:	9303      	str	r3, [sp, #12]
	return region_allocate_and_init(index,
    5ec6:	a901      	add	r1, sp, #4
    5ec8:	f7ff ffdd 	bl	5e86 <region_allocate_and_init>
}
    5ecc:	b005      	add	sp, #20
    5ece:	f85d fb04 	ldr.w	pc, [sp], #4
		return REGION_32B;
    5ed2:	2308      	movs	r3, #8
    5ed4:	e7f5      	b.n	5ec2 <mpu_configure_region+0x26>
		return REGION_4G;
    5ed6:	233e      	movs	r3, #62	; 0x3e
    5ed8:	e7f3      	b.n	5ec2 <mpu_configure_region+0x26>

00005eda <mpu_configure_regions>:
{
    5eda:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    5ede:	4680      	mov	r8, r0
    5ee0:	460f      	mov	r7, r1
    5ee2:	4699      	mov	r9, r3
	int reg_index = start_reg_index;
    5ee4:	4616      	mov	r6, r2
	for (i = 0; i < regions_num; i++) {
    5ee6:	2500      	movs	r5, #0
    5ee8:	e009      	b.n	5efe <mpu_configure_regions+0x24>
		reg_index = mpu_configure_region(reg_index, &regions[i]);
    5eea:	4621      	mov	r1, r4
    5eec:	b2f0      	uxtb	r0, r6
    5eee:	f7ff ffd5 	bl	5e9c <mpu_configure_region>
    5ef2:	4606      	mov	r6, r0
		if (reg_index == -EINVAL) {
    5ef4:	f110 0f16 	cmn.w	r0, #22
    5ef8:	d014      	beq.n	5f24 <mpu_configure_regions+0x4a>
		reg_index++;
    5efa:	3601      	adds	r6, #1
	for (i = 0; i < regions_num; i++) {
    5efc:	3501      	adds	r5, #1
    5efe:	42bd      	cmp	r5, r7
    5f00:	da10      	bge.n	5f24 <mpu_configure_regions+0x4a>
		if (regions[i].size == 0U) {
    5f02:	eb05 0445 	add.w	r4, r5, r5, lsl #1
    5f06:	eb08 0484 	add.w	r4, r8, r4, lsl #2
    5f0a:	6862      	ldr	r2, [r4, #4]
    5f0c:	2a00      	cmp	r2, #0
    5f0e:	d0f5      	beq.n	5efc <mpu_configure_regions+0x22>
		if (do_sanity_check &&
    5f10:	f1b9 0f00 	cmp.w	r9, #0
    5f14:	d0e9      	beq.n	5eea <mpu_configure_regions+0x10>
				(!mpu_partition_is_valid(&regions[i]))) {
    5f16:	4620      	mov	r0, r4
    5f18:	f7ff ffa4 	bl	5e64 <mpu_partition_is_valid>
		if (do_sanity_check &&
    5f1c:	2800      	cmp	r0, #0
    5f1e:	d1e4      	bne.n	5eea <mpu_configure_regions+0x10>
			return -EINVAL;
    5f20:	f06f 0615 	mvn.w	r6, #21
}
    5f24:	4630      	mov	r0, r6
    5f26:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

00005f2a <arm_core_mpu_configure_static_mpu_regions>:
{
    5f2a:	b508      	push	{r3, lr}
	if (mpu_configure_static_mpu_regions(static_regions, regions_num,
    5f2c:	f7fb fc88 	bl	1840 <mpu_configure_static_mpu_regions>
}
    5f30:	bd08      	pop	{r3, pc}

00005f32 <arm_core_mpu_configure_dynamic_mpu_regions>:
{
    5f32:	b508      	push	{r3, lr}
	if (mpu_configure_dynamic_mpu_regions(dynamic_regions, regions_num)
    5f34:	f7fb fc8e 	bl	1854 <mpu_configure_dynamic_mpu_regions>
}
    5f38:	bd08      	pop	{r3, pc}

00005f3a <strcpy>:

char *strcpy(char *_MLIBC_RESTRICT d, const char *_MLIBC_RESTRICT s)
{
	char *dest = d;

	while (*s != '\0') {
    5f3a:	4602      	mov	r2, r0
    5f3c:	780b      	ldrb	r3, [r1, #0]
    5f3e:	b11b      	cbz	r3, 5f48 <strcpy+0xe>
		*d = *s;
    5f40:	f802 3b01 	strb.w	r3, [r2], #1
		d++;
		s++;
    5f44:	3101      	adds	r1, #1
    5f46:	e7f9      	b.n	5f3c <strcpy+0x2>
	}

	*d = '\0';
    5f48:	7013      	strb	r3, [r2, #0]

	return dest;
}
    5f4a:	4770      	bx	lr

00005f4c <strncpy>:

char *strncpy(char *_MLIBC_RESTRICT d, const char *_MLIBC_RESTRICT s, size_t n)
{
	char *dest = d;

	while ((n > 0) && *s != '\0') {
    5f4c:	4603      	mov	r3, r0
    5f4e:	b1a2      	cbz	r2, 5f7a <strncpy+0x2e>
{
    5f50:	b410      	push	{r4}
	while ((n > 0) && *s != '\0') {
    5f52:	780c      	ldrb	r4, [r1, #0]
    5f54:	b12c      	cbz	r4, 5f62 <strncpy+0x16>
		*d = *s;
    5f56:	f803 4b01 	strb.w	r4, [r3], #1
		s++;
    5f5a:	3101      	adds	r1, #1
		d++;
		n--;
    5f5c:	3a01      	subs	r2, #1
	while ((n > 0) && *s != '\0') {
    5f5e:	2a00      	cmp	r2, #0
    5f60:	d1f7      	bne.n	5f52 <strncpy+0x6>
	}

	while (n > 0) {
    5f62:	b122      	cbz	r2, 5f6e <strncpy+0x22>
		*d = '\0';
    5f64:	2100      	movs	r1, #0
    5f66:	f803 1b01 	strb.w	r1, [r3], #1
		d++;
		n--;
    5f6a:	3a01      	subs	r2, #1
    5f6c:	e7f9      	b.n	5f62 <strncpy+0x16>
	}

	return dest;
}
    5f6e:	bc10      	pop	{r4}
    5f70:	4770      	bx	lr
		*d = '\0';
    5f72:	2100      	movs	r1, #0
    5f74:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    5f78:	3a01      	subs	r2, #1
	while (n > 0) {
    5f7a:	2a00      	cmp	r2, #0
    5f7c:	d1f9      	bne.n	5f72 <strncpy+0x26>
    5f7e:	4770      	bx	lr

00005f80 <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    5f80:	4603      	mov	r3, r0
	size_t n = 0;
    5f82:	2000      	movs	r0, #0

	while (*s != '\0') {
    5f84:	781a      	ldrb	r2, [r3, #0]
    5f86:	b112      	cbz	r2, 5f8e <strlen+0xe>
		s++;
    5f88:	3301      	adds	r3, #1
		n++;
    5f8a:	3001      	adds	r0, #1
    5f8c:	e7fa      	b.n	5f84 <strlen+0x4>
	}

	return n;
}
    5f8e:	4770      	bx	lr

00005f90 <strnlen>:
 *
 * @return number of bytes in fixed-size string <s>
 */

size_t strnlen(const char *s, size_t maxlen)
{
    5f90:	4603      	mov	r3, r0
	size_t n = 0;
    5f92:	2000      	movs	r0, #0

	while (*s != '\0' && n < maxlen) {
    5f94:	781a      	ldrb	r2, [r3, #0]
    5f96:	b122      	cbz	r2, 5fa2 <strnlen+0x12>
    5f98:	4288      	cmp	r0, r1
    5f9a:	d202      	bcs.n	5fa2 <strnlen+0x12>
		s++;
    5f9c:	3301      	adds	r3, #1
		n++;
    5f9e:	3001      	adds	r0, #1
    5fa0:	e7f8      	b.n	5f94 <strnlen+0x4>
	}

	return n;
}
    5fa2:	4770      	bx	lr

00005fa4 <strcmp>:
 * @return negative # if <s1> < <s2>, 0 if <s1> == <s2>, else positive #
 */

int strcmp(const char *s1, const char *s2)
{
	while ((*s1 == *s2) && (*s1 != '\0')) {
    5fa4:	7803      	ldrb	r3, [r0, #0]
    5fa6:	780a      	ldrb	r2, [r1, #0]
    5fa8:	4293      	cmp	r3, r2
    5faa:	d103      	bne.n	5fb4 <strcmp+0x10>
    5fac:	b113      	cbz	r3, 5fb4 <strcmp+0x10>
		s1++;
    5fae:	3001      	adds	r0, #1
		s2++;
    5fb0:	3101      	adds	r1, #1
    5fb2:	e7f7      	b.n	5fa4 <strcmp>
	}

	return *s1 - *s2;
}
    5fb4:	1a98      	subs	r0, r3, r2
    5fb6:	4770      	bx	lr

00005fb8 <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *_MLIBC_RESTRICT d, const void *_MLIBC_RESTRICT s, size_t n)
{
    5fb8:	b410      	push	{r4}
	const unsigned char *s_byte = (const unsigned char *)s;

#if !defined(CONFIG_MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE)
	const uintptr_t mask = sizeof(mem_word_t) - 1;

	if ((((uintptr_t)d ^ (uintptr_t)s_byte) & mask) == 0) {
    5fba:	ea80 0301 	eor.w	r3, r0, r1
    5fbe:	f013 0f03 	tst.w	r3, #3
    5fc2:	d001      	beq.n	5fc8 <memcpy+0x10>
	unsigned char *d_byte = (unsigned char *)d;
    5fc4:	4603      	mov	r3, r0
    5fc6:	e017      	b.n	5ff8 <memcpy+0x40>
    5fc8:	4603      	mov	r3, r0

		/* do byte-sized copying until word-aligned or finished */

		while (((uintptr_t)d_byte) & mask) {
    5fca:	f013 0f03 	tst.w	r3, #3
    5fce:	d00b      	beq.n	5fe8 <memcpy+0x30>
			if (n == 0) {
    5fd0:	b1a2      	cbz	r2, 5ffc <memcpy+0x44>
				return d;
			}
			*(d_byte++) = *(s_byte++);
    5fd2:	f811 4b01 	ldrb.w	r4, [r1], #1
    5fd6:	f803 4b01 	strb.w	r4, [r3], #1
			n--;
    5fda:	3a01      	subs	r2, #1
    5fdc:	e7f5      	b.n	5fca <memcpy+0x12>

		mem_word_t *d_word = (mem_word_t *)d_byte;
		const mem_word_t *s_word = (const mem_word_t *)s_byte;

		while (n >= sizeof(mem_word_t)) {
			*(d_word++) = *(s_word++);
    5fde:	f851 4b04 	ldr.w	r4, [r1], #4
    5fe2:	f843 4b04 	str.w	r4, [r3], #4
			n -= sizeof(mem_word_t);
    5fe6:	3a04      	subs	r2, #4
		while (n >= sizeof(mem_word_t)) {
    5fe8:	2a03      	cmp	r2, #3
    5fea:	d8f8      	bhi.n	5fde <memcpy+0x26>
    5fec:	e004      	b.n	5ff8 <memcpy+0x40>
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
		*(d_byte++) = *(s_byte++);
    5fee:	f811 4b01 	ldrb.w	r4, [r1], #1
    5ff2:	f803 4b01 	strb.w	r4, [r3], #1
		n--;
    5ff6:	3a01      	subs	r2, #1
	while (n > 0) {
    5ff8:	2a00      	cmp	r2, #0
    5ffa:	d1f8      	bne.n	5fee <memcpy+0x36>
	}

	return d;
}
    5ffc:	bc10      	pop	{r4}
    5ffe:	4770      	bx	lr

00006000 <memset>:
 *
 * @return pointer to start of buffer
 */

void *memset(void *buf, int c, size_t n)
{
    6000:	b410      	push	{r4}
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
	unsigned char c_byte = (unsigned char)c;
    6002:	b2cc      	uxtb	r4, r1
	unsigned char *d_byte = (unsigned char *)buf;
    6004:	4603      	mov	r3, r0

#if !defined(CONFIG_MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE)
	while (((uintptr_t)d_byte) & (sizeof(mem_word_t) - 1)) {
    6006:	f013 0f03 	tst.w	r3, #3
    600a:	d004      	beq.n	6016 <memset+0x16>
		if (n == 0) {
    600c:	b19a      	cbz	r2, 6036 <memset+0x36>
			return buf;
		}
		*(d_byte++) = c_byte;
    600e:	f803 4b01 	strb.w	r4, [r3], #1
		n--;
    6012:	3a01      	subs	r2, #1
    6014:	e7f7      	b.n	6006 <memset+0x6>
	}

	/* do word-sized initialization as long as possible */

	mem_word_t *d_word = (mem_word_t *)d_byte;
	mem_word_t c_word = (mem_word_t)c_byte;
    6016:	b2c9      	uxtb	r1, r1

	c_word |= c_word << 8;
    6018:	ea41 2101 	orr.w	r1, r1, r1, lsl #8
	c_word |= c_word << 16;
    601c:	ea41 4101 	orr.w	r1, r1, r1, lsl #16
#if Z_MEM_WORD_T_WIDTH > 32
	c_word |= c_word << 32;
#endif

	while (n >= sizeof(mem_word_t)) {
    6020:	2a03      	cmp	r2, #3
    6022:	d906      	bls.n	6032 <memset+0x32>
		*(d_word++) = c_word;
    6024:	f843 1b04 	str.w	r1, [r3], #4
		n -= sizeof(mem_word_t);
    6028:	3a04      	subs	r2, #4
    602a:	e7f9      	b.n	6020 <memset+0x20>

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
		*(d_byte++) = c_byte;
    602c:	f803 4b01 	strb.w	r4, [r3], #1
		n--;
    6030:	3a01      	subs	r2, #1
	while (n > 0) {
    6032:	2a00      	cmp	r2, #0
    6034:	d1fa      	bne.n	602c <memset+0x2c>
	}

	return buf;
}
    6036:	bc10      	pop	{r4}
    6038:	4770      	bx	lr

0000603a <_stdout_hook_default>:
}
    603a:	f04f 30ff 	mov.w	r0, #4294967295
    603e:	4770      	bx	lr

00006040 <pm_power_state_set>:
#include <logging/log.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);

/* Invoke Low Power/System Off specific Tasks */
__weak void pm_power_state_set(struct pm_state_info info)
{
    6040:	b084      	sub	sp, #16
    6042:	ab04      	add	r3, sp, #16
    6044:	e903 0007 	stmdb	r3, {r0, r1, r2}
	switch (info.state) {
    6048:	f89d 3004 	ldrb.w	r3, [sp, #4]
    604c:	2b06      	cmp	r3, #6
    604e:	d001      	beq.n	6054 <pm_power_state_set+0x14>
		break;
	default:
		LOG_DBG("Unsupported power state %u", info.state);
		break;
	}
}
    6050:	b004      	add	sp, #16
    6052:	4770      	bx	lr
    p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
    6054:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    6058:	2201      	movs	r2, #1
    605a:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  __ASM volatile ("dsb 0xF":::"memory");
    605e:	f3bf 8f4f 	dsb	sy
        __WFE();
    6062:	bf20      	wfe
    while (true)
    6064:	e7fd      	b.n	6062 <pm_power_state_set+0x22>

00006066 <pm_power_state_exit_post_ops>:

/* Handle SOC specific activity after Low Power Mode Exit */
__weak void pm_power_state_exit_post_ops(struct pm_state_info info)
{
    6066:	b084      	sub	sp, #16
    6068:	ab04      	add	r3, sp, #16
    606a:	e903 0007 	stmdb	r3, {r0, r1, r2}
    606e:	2300      	movs	r3, #0
    6070:	f383 8811 	msr	BASEPRI, r3
    6074:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
    6078:	b004      	add	sp, #16
    607a:	4770      	bx	lr

0000607c <get_sub_data>:
	struct nrf_clock_control_data *data = dev->data;
    607c:	6900      	ldr	r0, [r0, #16]
	return &data->subsys[type];
    607e:	eb01 0141 	add.w	r1, r1, r1, lsl #1
    6082:	0089      	lsls	r1, r1, #2
    6084:	3138      	adds	r1, #56	; 0x38
}
    6086:	4408      	add	r0, r1
    6088:	4770      	bx	lr

0000608a <get_sub_config>:
	const struct nrf_clock_control_config *config =
    608a:	6840      	ldr	r0, [r0, #4]
}
    608c:	eb00 00c1 	add.w	r0, r0, r1, lsl #3
    6090:	4770      	bx	lr

00006092 <get_onoff_manager>:
	struct nrf_clock_control_data *data = dev->data;
    6092:	6900      	ldr	r0, [r0, #16]
	return &data->mgr[type];
    6094:	ebc1 01c1 	rsb	r1, r1, r1, lsl #3
}
    6098:	eb00 0081 	add.w	r0, r0, r1, lsl #2
    609c:	4770      	bx	lr

0000609e <get_status>:
{
    609e:	b508      	push	{r3, lr}
	return GET_STATUS(get_sub_data(dev, type)->flags);
    60a0:	b2c9      	uxtb	r1, r1
    60a2:	f7ff ffeb 	bl	607c <get_sub_data>
    60a6:	6880      	ldr	r0, [r0, #8]
}
    60a8:	f000 0007 	and.w	r0, r0, #7
    60ac:	bd08      	pop	{r3, pc}

000060ae <set_off_state>:
	__asm__ volatile(
    60ae:	f04f 0320 	mov.w	r3, #32
    60b2:	f3ef 8211 	mrs	r2, BASEPRI
    60b6:	f383 8812 	msr	BASEPRI_MAX, r3
    60ba:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    60be:	6803      	ldr	r3, [r0, #0]
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    60c0:	f013 03c0 	ands.w	r3, r3, #192	; 0xc0
    60c4:	d001      	beq.n	60ca <set_off_state+0x1c>
    60c6:	428b      	cmp	r3, r1
    60c8:	d107      	bne.n	60da <set_off_state+0x2c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    60ca:	2301      	movs	r3, #1
    60cc:	6003      	str	r3, [r0, #0]
	int err = 0;
    60ce:	2000      	movs	r0, #0
	__asm__ volatile(
    60d0:	f382 8811 	msr	BASEPRI, r2
    60d4:	f3bf 8f6f 	isb	sy
}
    60d8:	4770      	bx	lr
		err = -EPERM;
    60da:	f04f 30ff 	mov.w	r0, #4294967295
    60de:	e7f7      	b.n	60d0 <set_off_state+0x22>

000060e0 <set_starting_state>:
{
    60e0:	b410      	push	{r4}
	__asm__ volatile(
    60e2:	f04f 0320 	mov.w	r3, #32
    60e6:	f3ef 8211 	mrs	r2, BASEPRI
    60ea:	f383 8812 	msr	BASEPRI_MAX, r3
    60ee:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    60f2:	6803      	ldr	r3, [r0, #0]
    60f4:	f003 04c0 	and.w	r4, r3, #192	; 0xc0
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    60f8:	f003 0307 	and.w	r3, r3, #7
    60fc:	2b01      	cmp	r3, #1
    60fe:	d009      	beq.n	6114 <set_starting_state+0x34>
	} else if (current_ctx != ctx) {
    6100:	428c      	cmp	r4, r1
    6102:	d00a      	beq.n	611a <set_starting_state+0x3a>
		err = -EPERM;
    6104:	f04f 30ff 	mov.w	r0, #4294967295
	__asm__ volatile(
    6108:	f382 8811 	msr	BASEPRI, r2
    610c:	f3bf 8f6f 	isb	sy
}
    6110:	bc10      	pop	{r4}
    6112:	4770      	bx	lr
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    6114:	6001      	str	r1, [r0, #0]
	int err = 0;
    6116:	2000      	movs	r0, #0
    6118:	e7f6      	b.n	6108 <set_starting_state+0x28>
		err = -EALREADY;
    611a:	f06f 0077 	mvn.w	r0, #119	; 0x77
    611e:	e7f3      	b.n	6108 <set_starting_state+0x28>

00006120 <set_on_state>:
	__asm__ volatile(
    6120:	f04f 0320 	mov.w	r3, #32
    6124:	f3ef 8211 	mrs	r2, BASEPRI
    6128:	f383 8812 	msr	BASEPRI_MAX, r3
    612c:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    6130:	6803      	ldr	r3, [r0, #0]
    6132:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    6136:	f043 0302 	orr.w	r3, r3, #2
    613a:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    613c:	f382 8811 	msr	BASEPRI, r2
    6140:	f3bf 8f6f 	isb	sy
}
    6144:	4770      	bx	lr

00006146 <clkstarted_handle>:
{
    6146:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6148:	4606      	mov	r6, r0
    614a:	460c      	mov	r4, r1
	struct nrf_clock_control_sub_data *sub_data = get_sub_data(dev, type);
    614c:	f7ff ff96 	bl	607c <get_sub_data>
	clock_control_cb_t callback = sub_data->cb;
    6150:	6805      	ldr	r5, [r0, #0]
	void *user_data = sub_data->user_data;
    6152:	6847      	ldr	r7, [r0, #4]
	sub_data->cb = NULL;
    6154:	2300      	movs	r3, #0
    6156:	f840 3b08 	str.w	r3, [r0], #8
	set_on_state(&sub_data->flags);
    615a:	f7ff ffe1 	bl	6120 <set_on_state>
	if (callback) {
    615e:	b11d      	cbz	r5, 6168 <clkstarted_handle+0x22>
		callback(dev, (clock_control_subsys_t)type, user_data);
    6160:	463a      	mov	r2, r7
    6162:	4621      	mov	r1, r4
    6164:	4630      	mov	r0, r6
    6166:	47a8      	blx	r5
}
    6168:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

0000616a <stop>:
{
    616a:	b570      	push	{r4, r5, r6, lr}
    616c:	4606      	mov	r6, r0
    616e:	4615      	mov	r5, r2
	enum clock_control_nrf_type type = (enum clock_control_nrf_type)subsys;
    6170:	b2cc      	uxtb	r4, r1
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    6172:	4621      	mov	r1, r4
    6174:	f7ff ff82 	bl	607c <get_sub_data>
	err = set_off_state(&subdata->flags, ctx);
    6178:	4629      	mov	r1, r5
    617a:	3008      	adds	r0, #8
    617c:	f7ff ff97 	bl	60ae <set_off_state>
	if (err < 0) {
    6180:	2800      	cmp	r0, #0
    6182:	db06      	blt.n	6192 <stop+0x28>
	get_sub_config(dev, type)->stop();
    6184:	4621      	mov	r1, r4
    6186:	4630      	mov	r0, r6
    6188:	f7ff ff7f 	bl	608a <get_sub_config>
    618c:	6843      	ldr	r3, [r0, #4]
    618e:	4798      	blx	r3
	return 0;
    6190:	2000      	movs	r0, #0
}
    6192:	bd70      	pop	{r4, r5, r6, pc}

00006194 <api_stop>:
{
    6194:	b508      	push	{r3, lr}
	return stop(dev, subsys, CTX_API);
    6196:	2280      	movs	r2, #128	; 0x80
    6198:	f7ff ffe7 	bl	616a <stop>
}
    619c:	bd08      	pop	{r3, pc}

0000619e <async_start>:
{
    619e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    61a2:	4606      	mov	r6, r0
    61a4:	4690      	mov	r8, r2
    61a6:	461f      	mov	r7, r3
	enum clock_control_nrf_type type = (enum clock_control_nrf_type)subsys;
    61a8:	b2cd      	uxtb	r5, r1
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    61aa:	4629      	mov	r1, r5
    61ac:	f7ff ff66 	bl	607c <get_sub_data>
    61b0:	4604      	mov	r4, r0
	err = set_starting_state(&subdata->flags, ctx);
    61b2:	9906      	ldr	r1, [sp, #24]
    61b4:	3008      	adds	r0, #8
    61b6:	f7ff ff93 	bl	60e0 <set_starting_state>
	if (err < 0) {
    61ba:	2800      	cmp	r0, #0
    61bc:	db09      	blt.n	61d2 <async_start+0x34>
	subdata->cb = cb;
    61be:	f8c4 8000 	str.w	r8, [r4]
	subdata->user_data = user_data;
    61c2:	6067      	str	r7, [r4, #4]
	 get_sub_config(dev, type)->start();
    61c4:	4629      	mov	r1, r5
    61c6:	4630      	mov	r0, r6
    61c8:	f7ff ff5f 	bl	608a <get_sub_config>
    61cc:	6803      	ldr	r3, [r0, #0]
    61ce:	4798      	blx	r3
	return 0;
    61d0:	2000      	movs	r0, #0
}
    61d2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

000061d6 <api_start>:
{
    61d6:	b510      	push	{r4, lr}
    61d8:	b082      	sub	sp, #8
	return async_start(dev, subsys, cb, user_data, CTX_API);
    61da:	2480      	movs	r4, #128	; 0x80
    61dc:	9400      	str	r4, [sp, #0]
    61de:	f7ff ffde 	bl	619e <async_start>
}
    61e2:	b002      	add	sp, #8
    61e4:	bd10      	pop	{r4, pc}

000061e6 <onoff_started_callback>:
{
    61e6:	b510      	push	{r4, lr}
    61e8:	4614      	mov	r4, r2
	struct onoff_manager *mgr = get_onoff_manager(dev, type);
    61ea:	b2c9      	uxtb	r1, r1
    61ec:	f7ff ff51 	bl	6092 <get_onoff_manager>
	notify(mgr, 0);
    61f0:	2100      	movs	r1, #0
    61f2:	47a0      	blx	r4
}
    61f4:	bd10      	pop	{r4, pc}

000061f6 <hfclk_start>:
{
    61f6:	b508      	push	{r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    61f8:	2001      	movs	r0, #1
    61fa:	f7fd f851 	bl	32a0 <nrfx_clock_start>
}
    61fe:	bd08      	pop	{r3, pc}

00006200 <lfclk_start>:
{
    6200:	b508      	push	{r3, lr}
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    6202:	2000      	movs	r0, #0
    6204:	f7fd f84c 	bl	32a0 <nrfx_clock_start>
}
    6208:	bd08      	pop	{r3, pc}

0000620a <hfclk_stop>:
{
    620a:	b508      	push	{r3, lr}
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    620c:	2001      	movs	r0, #1
    620e:	f7fd f87f 	bl	3310 <nrfx_clock_stop>
}
    6212:	bd08      	pop	{r3, pc}

00006214 <lfclk_stop>:
{
    6214:	b508      	push	{r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    6216:	2000      	movs	r0, #0
    6218:	f7fd f87a 	bl	3310 <nrfx_clock_stop>
}
    621c:	bd08      	pop	{r3, pc}

0000621e <blocking_start_callback>:
{
    621e:	b508      	push	{r3, lr}
    6220:	4610      	mov	r0, r2
	z_impl_k_sem_give(sem);
    6222:	f7fe f999 	bl	4558 <z_impl_k_sem_give>
}
    6226:	bd08      	pop	{r3, pc}

00006228 <gpio_nrfx_port_get_raw>:
	return port->config;
    6228:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    622a:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    622c:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    6230:	600b      	str	r3, [r1, #0]
}
    6232:	2000      	movs	r0, #0
    6234:	4770      	bx	lr

00006236 <gpio_nrfx_port_set_masked_raw>:
	return port->config;
    6236:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6238:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
    623a:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
    623e:	4042      	eors	r2, r0
    6240:	400a      	ands	r2, r1
    6242:	4042      	eors	r2, r0
    p_reg->OUT = value;
    6244:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
}
    6248:	2000      	movs	r0, #0
    624a:	4770      	bx	lr

0000624c <gpio_nrfx_port_set_bits_raw>:
	return port->config;
    624c:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    624e:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTSET = set_mask;
    6250:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
}
    6254:	2000      	movs	r0, #0
    6256:	4770      	bx	lr

00006258 <gpio_nrfx_port_clear_bits_raw>:
	return port->config;
    6258:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    625a:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTCLR = clr_mask;
    625c:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
}
    6260:	2000      	movs	r0, #0
    6262:	4770      	bx	lr

00006264 <gpio_nrfx_port_toggle_bits>:
	return port->config;
    6264:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6266:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    6268:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value ^ mask);
    626c:	404b      	eors	r3, r1
    p_reg->OUT = value;
    626e:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
}
    6272:	2000      	movs	r0, #0
    6274:	4770      	bx	lr

00006276 <gpio_nrfx_manage_callback>:
{
    6276:	b470      	push	{r4, r5, r6}
	return port->data;
    6278:	6900      	ldr	r0, [r0, #16]
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    627a:	1d05      	adds	r5, r0, #4
	return list->head;
    627c:	6843      	ldr	r3, [r0, #4]
	if (!sys_slist_is_empty(callbacks)) {
    627e:	b1db      	cbz	r3, 62b8 <gpio_nrfx_manage_callback+0x42>
		if (!sys_slist_find_and_remove(callbacks, &callback->node)) {
    6280:	460e      	mov	r6, r1
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    6282:	2400      	movs	r4, #0
    6284:	e00a      	b.n	629c <gpio_nrfx_manage_callback+0x26>
	return node->next;
    6286:	680b      	ldr	r3, [r1, #0]
	list->head = node;
    6288:	6043      	str	r3, [r0, #4]
	return list->tail;
    628a:	686c      	ldr	r4, [r5, #4]
Z_GENLIST_REMOVE(slist, snode)
    628c:	42a1      	cmp	r1, r4
    628e:	d10f      	bne.n	62b0 <gpio_nrfx_manage_callback+0x3a>
	list->tail = node;
    6290:	606b      	str	r3, [r5, #4]
}
    6292:	e00d      	b.n	62b0 <gpio_nrfx_manage_callback+0x3a>
	list->tail = node;
    6294:	606c      	str	r4, [r5, #4]
}
    6296:	e00b      	b.n	62b0 <gpio_nrfx_manage_callback+0x3a>
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    6298:	461c      	mov	r4, r3
    629a:	681b      	ldr	r3, [r3, #0]
    629c:	b15b      	cbz	r3, 62b6 <gpio_nrfx_manage_callback+0x40>
    629e:	429e      	cmp	r6, r3
    62a0:	d1fa      	bne.n	6298 <gpio_nrfx_manage_callback+0x22>
Z_GENLIST_REMOVE(slist, snode)
    62a2:	2c00      	cmp	r4, #0
    62a4:	d0ef      	beq.n	6286 <gpio_nrfx_manage_callback+0x10>
	return node->next;
    62a6:	680b      	ldr	r3, [r1, #0]
	parent->next = child;
    62a8:	6023      	str	r3, [r4, #0]
	return list->tail;
    62aa:	686b      	ldr	r3, [r5, #4]
Z_GENLIST_REMOVE(slist, snode)
    62ac:	4299      	cmp	r1, r3
    62ae:	d0f1      	beq.n	6294 <gpio_nrfx_manage_callback+0x1e>
	parent->next = child;
    62b0:	2300      	movs	r3, #0
    62b2:	600b      	str	r3, [r1, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    62b4:	e000      	b.n	62b8 <gpio_nrfx_manage_callback+0x42>
			if (!set) {
    62b6:	b152      	cbz	r2, 62ce <gpio_nrfx_manage_callback+0x58>
	if (set) {
    62b8:	b162      	cbz	r2, 62d4 <gpio_nrfx_manage_callback+0x5e>
	return list->head;
    62ba:	6843      	ldr	r3, [r0, #4]
	parent->next = child;
    62bc:	600b      	str	r3, [r1, #0]
	list->head = node;
    62be:	6041      	str	r1, [r0, #4]
	return list->tail;
    62c0:	686b      	ldr	r3, [r5, #4]
Z_GENLIST_PREPEND(slist, snode)
    62c2:	b10b      	cbz	r3, 62c8 <gpio_nrfx_manage_callback+0x52>
	return 0;
    62c4:	2000      	movs	r0, #0
    62c6:	e006      	b.n	62d6 <gpio_nrfx_manage_callback+0x60>
	list->tail = node;
    62c8:	6069      	str	r1, [r5, #4]
    62ca:	2000      	movs	r0, #0
}
    62cc:	e003      	b.n	62d6 <gpio_nrfx_manage_callback+0x60>
				return -EINVAL;
    62ce:	f06f 0015 	mvn.w	r0, #21
    62d2:	e000      	b.n	62d6 <gpio_nrfx_manage_callback+0x60>
	return 0;
    62d4:	2000      	movs	r0, #0
}
    62d6:	bc70      	pop	{r4, r5, r6}
    62d8:	4770      	bx	lr

000062da <spi_1_init>:
#ifdef CONFIG_SPI_0_NRF_SPI
SPI_NRFX_SPI_DEVICE(0);
#endif

#ifdef CONFIG_SPI_1_NRF_SPI
SPI_NRFX_SPI_DEVICE(1);
    62da:	b510      	push	{r4, lr}
    62dc:	4604      	mov	r4, r0
    62de:	2200      	movs	r2, #0
    62e0:	2101      	movs	r1, #1
    62e2:	2004      	movs	r0, #4
    62e4:	f7fa ffa6 	bl	1234 <z_arm_irq_priority_set>
	return dev->data;
    62e8:	6924      	ldr	r4, [r4, #16]
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio_dev) {
    62ea:	6823      	ldr	r3, [r4, #0]
    62ec:	b1c3      	cbz	r3, 6320 <spi_1_init+0x46>
    62ee:	689b      	ldr	r3, [r3, #8]
    62f0:	b1b3      	cbz	r3, 6320 <spi_1_init+0x46>
    62f2:	681a      	ldr	r2, [r3, #0]
    62f4:	b1a2      	cbz	r2, 6320 <spi_1_init+0x46>
			k_busy_wait(ctx->config->cs->delay);
    62f6:	6858      	ldr	r0, [r3, #4]
	z_impl_k_busy_wait(usec_to_wait);
    62f8:	f000 ffdb 	bl	72b2 <z_impl_k_busy_wait>
			gpio_pin_set(ctx->config->cs->gpio_dev,
    62fc:	6823      	ldr	r3, [r4, #0]
    62fe:	689b      	ldr	r3, [r3, #8]
    6300:	6818      	ldr	r0, [r3, #0]
    6302:	7a19      	ldrb	r1, [r3, #8]
	const struct gpio_driver_data *const data =
    6304:	6903      	ldr	r3, [r0, #16]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    6306:	681a      	ldr	r2, [r3, #0]
    6308:	2301      	movs	r3, #1
    630a:	408b      	lsls	r3, r1
    630c:	421a      	tst	r2, r3
    630e:	d10b      	bne.n	6328 <spi_1_init+0x4e>
    6310:	2300      	movs	r3, #0
	if (value != 0)	{
    6312:	b15b      	cbz	r3, 632c <spi_1_init+0x52>
		ret = gpio_port_set_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    6314:	2301      	movs	r3, #1
    6316:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    631a:	6883      	ldr	r3, [r0, #8]
	return api->port_set_bits_raw(port, pins);
    631c:	68db      	ldr	r3, [r3, #12]
    631e:	4798      	blx	r3
    6320:	6923      	ldr	r3, [r4, #16]
	if (!k_sem_count_get(&ctx->lock)) {
    6322:	b153      	cbz	r3, 633a <spi_1_init+0x60>
SPI_NRFX_SPI_DEVICE(1);
    6324:	2000      	movs	r0, #0
    6326:	bd10      	pop	{r4, pc}
		value = (value != 0) ? 0 : 1;
    6328:	2301      	movs	r3, #1
    632a:	e7f2      	b.n	6312 <spi_1_init+0x38>
		ret = gpio_port_clear_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    632c:	2301      	movs	r3, #1
    632e:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    6332:	6883      	ldr	r3, [r0, #8]
	return api->port_clear_bits_raw(port, pins);
    6334:	691b      	ldr	r3, [r3, #16]
    6336:	4798      	blx	r3
	return ret;
    6338:	e7f2      	b.n	6320 <spi_1_init+0x46>
		ctx->owner = NULL;
    633a:	6063      	str	r3, [r4, #4]
		k_sem_give(&ctx->lock);
    633c:	f104 0008 	add.w	r0, r4, #8
	z_impl_k_sem_give(sem);
    6340:	f7fe f90a 	bl	4558 <z_impl_k_sem_give>
}
    6344:	e7ee      	b.n	6324 <spi_1_init+0x4a>

00006346 <spi_0_init>:
SPI_NRFX_SPI_DEVICE(0);
    6346:	b510      	push	{r4, lr}
    6348:	4604      	mov	r4, r0
    634a:	2200      	movs	r2, #0
    634c:	2101      	movs	r1, #1
    634e:	2003      	movs	r0, #3
    6350:	f7fa ff70 	bl	1234 <z_arm_irq_priority_set>
	return dev->data;
    6354:	6924      	ldr	r4, [r4, #16]
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio_dev) {
    6356:	6823      	ldr	r3, [r4, #0]
    6358:	b1c3      	cbz	r3, 638c <spi_0_init+0x46>
    635a:	689b      	ldr	r3, [r3, #8]
    635c:	b1b3      	cbz	r3, 638c <spi_0_init+0x46>
    635e:	681a      	ldr	r2, [r3, #0]
    6360:	b1a2      	cbz	r2, 638c <spi_0_init+0x46>
			k_busy_wait(ctx->config->cs->delay);
    6362:	6858      	ldr	r0, [r3, #4]
	z_impl_k_busy_wait(usec_to_wait);
    6364:	f000 ffa5 	bl	72b2 <z_impl_k_busy_wait>
			gpio_pin_set(ctx->config->cs->gpio_dev,
    6368:	6823      	ldr	r3, [r4, #0]
    636a:	689b      	ldr	r3, [r3, #8]
    636c:	6818      	ldr	r0, [r3, #0]
    636e:	7a19      	ldrb	r1, [r3, #8]
	const struct gpio_driver_data *const data =
    6370:	6903      	ldr	r3, [r0, #16]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    6372:	681a      	ldr	r2, [r3, #0]
    6374:	2301      	movs	r3, #1
    6376:	408b      	lsls	r3, r1
    6378:	421a      	tst	r2, r3
    637a:	d10b      	bne.n	6394 <spi_0_init+0x4e>
    637c:	2300      	movs	r3, #0
	if (value != 0)	{
    637e:	b15b      	cbz	r3, 6398 <spi_0_init+0x52>
		ret = gpio_port_set_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    6380:	2301      	movs	r3, #1
    6382:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    6386:	6883      	ldr	r3, [r0, #8]
	return api->port_set_bits_raw(port, pins);
    6388:	68db      	ldr	r3, [r3, #12]
    638a:	4798      	blx	r3
    638c:	6923      	ldr	r3, [r4, #16]
	if (!k_sem_count_get(&ctx->lock)) {
    638e:	b153      	cbz	r3, 63a6 <spi_0_init+0x60>
SPI_NRFX_SPI_DEVICE(0);
    6390:	2000      	movs	r0, #0
    6392:	bd10      	pop	{r4, pc}
		value = (value != 0) ? 0 : 1;
    6394:	2301      	movs	r3, #1
    6396:	e7f2      	b.n	637e <spi_0_init+0x38>
		ret = gpio_port_clear_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    6398:	2301      	movs	r3, #1
    639a:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    639e:	6883      	ldr	r3, [r0, #8]
	return api->port_clear_bits_raw(port, pins);
    63a0:	691b      	ldr	r3, [r3, #16]
    63a2:	4798      	blx	r3
	return ret;
    63a4:	e7f2      	b.n	638c <spi_0_init+0x46>
		ctx->owner = NULL;
    63a6:	6063      	str	r3, [r4, #4]
		k_sem_give(&ctx->lock);
    63a8:	f104 0008 	add.w	r0, r4, #8
	z_impl_k_sem_give(sem);
    63ac:	f7fe f8d4 	bl	4558 <z_impl_k_sem_give>
}
    63b0:	e7ee      	b.n	6390 <spi_0_init+0x4a>

000063b2 <spi_nrfx_release>:
{
    63b2:	b510      	push	{r4, lr}
	return dev->data;
    63b4:	6904      	ldr	r4, [r0, #16]
	return !!(ctx->config == config);
    63b6:	6823      	ldr	r3, [r4, #0]
	if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
    63b8:	428b      	cmp	r3, r1
    63ba:	d131      	bne.n	6420 <spi_nrfx_release+0x6e>
	if (dev_data->busy) {
    63bc:	f894 306c 	ldrb.w	r3, [r4, #108]	; 0x6c
    63c0:	2b00      	cmp	r3, #0
    63c2:	d130      	bne.n	6426 <spi_nrfx_release+0x74>
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio_dev) {
    63c4:	6823      	ldr	r3, [r4, #0]
    63c6:	b1c3      	cbz	r3, 63fa <spi_nrfx_release+0x48>
    63c8:	689b      	ldr	r3, [r3, #8]
    63ca:	b1b3      	cbz	r3, 63fa <spi_nrfx_release+0x48>
    63cc:	681a      	ldr	r2, [r3, #0]
    63ce:	b1a2      	cbz	r2, 63fa <spi_nrfx_release+0x48>
			k_busy_wait(ctx->config->cs->delay);
    63d0:	6858      	ldr	r0, [r3, #4]
	z_impl_k_busy_wait(usec_to_wait);
    63d2:	f000 ff6e 	bl	72b2 <z_impl_k_busy_wait>
			gpio_pin_set(ctx->config->cs->gpio_dev,
    63d6:	6823      	ldr	r3, [r4, #0]
    63d8:	689b      	ldr	r3, [r3, #8]
    63da:	6818      	ldr	r0, [r3, #0]
    63dc:	7a19      	ldrb	r1, [r3, #8]
	const struct gpio_driver_data *const data =
    63de:	6903      	ldr	r3, [r0, #16]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    63e0:	681a      	ldr	r2, [r3, #0]
    63e2:	2301      	movs	r3, #1
    63e4:	408b      	lsls	r3, r1
    63e6:	421a      	tst	r2, r3
    63e8:	d10b      	bne.n	6402 <spi_nrfx_release+0x50>
    63ea:	2300      	movs	r3, #0
	if (value != 0)	{
    63ec:	b15b      	cbz	r3, 6406 <spi_nrfx_release+0x54>
		ret = gpio_port_set_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    63ee:	2301      	movs	r3, #1
    63f0:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    63f4:	6883      	ldr	r3, [r0, #8]
	return api->port_set_bits_raw(port, pins);
    63f6:	68db      	ldr	r3, [r3, #12]
    63f8:	4798      	blx	r3
    63fa:	6923      	ldr	r3, [r4, #16]
	if (!k_sem_count_get(&ctx->lock)) {
    63fc:	b153      	cbz	r3, 6414 <spi_nrfx_release+0x62>
	return 0;
    63fe:	2000      	movs	r0, #0
}
    6400:	bd10      	pop	{r4, pc}
		value = (value != 0) ? 0 : 1;
    6402:	2301      	movs	r3, #1
    6404:	e7f2      	b.n	63ec <spi_nrfx_release+0x3a>
		ret = gpio_port_clear_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    6406:	2301      	movs	r3, #1
    6408:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    640c:	6883      	ldr	r3, [r0, #8]
	return api->port_clear_bits_raw(port, pins);
    640e:	691b      	ldr	r3, [r3, #16]
    6410:	4798      	blx	r3
	return ret;
    6412:	e7f2      	b.n	63fa <spi_nrfx_release+0x48>
		ctx->owner = NULL;
    6414:	6063      	str	r3, [r4, #4]
		k_sem_give(&ctx->lock);
    6416:	f104 0008 	add.w	r0, r4, #8
	z_impl_k_sem_give(sem);
    641a:	f7fe f89d 	bl	4558 <z_impl_k_sem_give>
}
    641e:	e7ee      	b.n	63fe <spi_nrfx_release+0x4c>
		return -EINVAL;
    6420:	f06f 0015 	mvn.w	r0, #21
    6424:	e7ec      	b.n	6400 <spi_nrfx_release+0x4e>
		return -EBUSY;
    6426:	f06f 000f 	mvn.w	r0, #15
    642a:	e7e9      	b.n	6400 <spi_nrfx_release+0x4e>

0000642c <event_handler>:
{
    642c:	b508      	push	{r3, lr}
	if (p_event->type == NRFX_SPI_EVENT_DONE) {
    642e:	7803      	ldrb	r3, [r0, #0]
    6430:	2b00      	cmp	r3, #0
    6432:	d139      	bne.n	64a8 <event_handler+0x7c>
		spi_context_update_tx(&dev_data->ctx, 1, dev_data->chunk_len);
    6434:	6e8a      	ldr	r2, [r1, #104]	; 0x68
	if (!ctx->tx_len) {
    6436:	6d8b      	ldr	r3, [r1, #88]	; 0x58
    6438:	b1c3      	cbz	r3, 646c <event_handler+0x40>
	if (len > ctx->tx_len) {
    643a:	429a      	cmp	r2, r3
    643c:	d816      	bhi.n	646c <event_handler+0x40>
	ctx->tx_len -= len;
    643e:	1a9b      	subs	r3, r3, r2
    6440:	658b      	str	r3, [r1, #88]	; 0x58
	if (!ctx->tx_len) {
    6442:	b97b      	cbnz	r3, 6464 <event_handler+0x38>
		ctx->tx_count--;
    6444:	6c8b      	ldr	r3, [r1, #72]	; 0x48
    6446:	3b01      	subs	r3, #1
    6448:	648b      	str	r3, [r1, #72]	; 0x48
		if (ctx->tx_count) {
    644a:	b143      	cbz	r3, 645e <event_handler+0x32>
			ctx->current_tx++;
    644c:	6c4b      	ldr	r3, [r1, #68]	; 0x44
    644e:	f103 0008 	add.w	r0, r3, #8
    6452:	6448      	str	r0, [r1, #68]	; 0x44
			ctx->tx_buf = (const uint8_t *)ctx->current_tx->buf;
    6454:	6898      	ldr	r0, [r3, #8]
    6456:	6548      	str	r0, [r1, #84]	; 0x54
			ctx->tx_len = ctx->current_tx->len / dfs;
    6458:	68db      	ldr	r3, [r3, #12]
    645a:	658b      	str	r3, [r1, #88]	; 0x58
    645c:	e006      	b.n	646c <event_handler+0x40>
			ctx->tx_buf = NULL;
    645e:	2300      	movs	r3, #0
    6460:	654b      	str	r3, [r1, #84]	; 0x54
    6462:	e003      	b.n	646c <event_handler+0x40>
	} else if (ctx->tx_buf) {
    6464:	6d4b      	ldr	r3, [r1, #84]	; 0x54
    6466:	b10b      	cbz	r3, 646c <event_handler+0x40>
		ctx->tx_buf += dfs * len;
    6468:	4413      	add	r3, r2
    646a:	654b      	str	r3, [r1, #84]	; 0x54
	if (!ctx->rx_len) {
    646c:	6e0b      	ldr	r3, [r1, #96]	; 0x60
    646e:	b1c3      	cbz	r3, 64a2 <event_handler+0x76>
	if (len > ctx->rx_len) {
    6470:	429a      	cmp	r2, r3
    6472:	d816      	bhi.n	64a2 <event_handler+0x76>
	ctx->rx_len -= len;
    6474:	1a9b      	subs	r3, r3, r2
    6476:	660b      	str	r3, [r1, #96]	; 0x60
	if (!ctx->rx_len) {
    6478:	b97b      	cbnz	r3, 649a <event_handler+0x6e>
		ctx->rx_count--;
    647a:	6d0b      	ldr	r3, [r1, #80]	; 0x50
    647c:	3b01      	subs	r3, #1
    647e:	650b      	str	r3, [r1, #80]	; 0x50
		if (ctx->rx_count) {
    6480:	b143      	cbz	r3, 6494 <event_handler+0x68>
			ctx->current_rx++;
    6482:	6ccb      	ldr	r3, [r1, #76]	; 0x4c
    6484:	f103 0208 	add.w	r2, r3, #8
    6488:	64ca      	str	r2, [r1, #76]	; 0x4c
			ctx->rx_buf = (uint8_t *)ctx->current_rx->buf;
    648a:	689a      	ldr	r2, [r3, #8]
    648c:	65ca      	str	r2, [r1, #92]	; 0x5c
			ctx->rx_len = ctx->current_rx->len / dfs;
    648e:	68db      	ldr	r3, [r3, #12]
    6490:	660b      	str	r3, [r1, #96]	; 0x60
    6492:	e006      	b.n	64a2 <event_handler+0x76>
			ctx->rx_buf = NULL;
    6494:	2300      	movs	r3, #0
    6496:	65cb      	str	r3, [r1, #92]	; 0x5c
    6498:	e003      	b.n	64a2 <event_handler+0x76>
	} else if (ctx->rx_buf) {
    649a:	6dcb      	ldr	r3, [r1, #92]	; 0x5c
    649c:	b10b      	cbz	r3, 64a2 <event_handler+0x76>
		ctx->rx_buf += dfs * len;
    649e:	441a      	add	r2, r3
    64a0:	65ca      	str	r2, [r1, #92]	; 0x5c
		transfer_next_chunk(dev_data->dev);
    64a2:	6e48      	ldr	r0, [r1, #100]	; 0x64
    64a4:	f7fb ffc8 	bl	2438 <transfer_next_chunk>
}
    64a8:	bd08      	pop	{r3, pc}

000064aa <transceive>:
{
    64aa:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    64ae:	4606      	mov	r6, r0
    64b0:	460d      	mov	r5, r1
    64b2:	4690      	mov	r8, r2
    64b4:	461f      	mov	r7, r3
	return dev->data;
    64b6:	6904      	ldr	r4, [r0, #16]
	if ((spi_cfg->operation & SPI_LOCK_ON) &&
    64b8:	888b      	ldrh	r3, [r1, #4]
    64ba:	f413 4f80 	tst.w	r3, #16384	; 0x4000
    64be:	d004      	beq.n	64ca <transceive+0x20>
    64c0:	6923      	ldr	r3, [r4, #16]
    64c2:	b913      	cbnz	r3, 64ca <transceive+0x20>
		(ctx->owner == spi_cfg)) {
    64c4:	6863      	ldr	r3, [r4, #4]
		(k_sem_count_get(&ctx->lock) == 0) &&
    64c6:	4299      	cmp	r1, r3
    64c8:	d00e      	beq.n	64e8 <transceive+0x3e>
	k_sem_take(&ctx->lock, K_FOREVER);
    64ca:	f104 0008 	add.w	r0, r4, #8
	return z_impl_k_sem_take(sem, timeout);
    64ce:	f04f 32ff 	mov.w	r2, #4294967295
    64d2:	f04f 33ff 	mov.w	r3, #4294967295
    64d6:	f7fe f867 	bl	45a8 <z_impl_k_sem_take>
	ctx->owner = spi_cfg;
    64da:	6065      	str	r5, [r4, #4]
	ctx->asynchronous = asynchronous;
    64dc:	f89d 3018 	ldrb.w	r3, [sp, #24]
    64e0:	f884 3040 	strb.w	r3, [r4, #64]	; 0x40
	ctx->signal = signal;
    64e4:	9b07      	ldr	r3, [sp, #28]
    64e6:	63e3      	str	r3, [r4, #60]	; 0x3c
	error = configure(dev, spi_cfg);
    64e8:	4629      	mov	r1, r5
    64ea:	4630      	mov	r0, r6
    64ec:	f7fb fed0 	bl	2290 <configure>
	if (error == 0) {
    64f0:	4605      	mov	r5, r0
    64f2:	b168      	cbz	r0, 6510 <transceive+0x66>
	if (!ctx->asynchronous || (status < 0)) {
    64f4:	f894 3040 	ldrb.w	r3, [r4, #64]	; 0x40
    64f8:	b10b      	cbz	r3, 64fe <transceive+0x54>
    64fa:	2d00      	cmp	r5, #0
    64fc:	da05      	bge.n	650a <transceive+0x60>
		ctx->owner = NULL;
    64fe:	2300      	movs	r3, #0
    6500:	6063      	str	r3, [r4, #4]
		k_sem_give(&ctx->lock);
    6502:	f104 0008 	add.w	r0, r4, #8
	z_impl_k_sem_give(sem);
    6506:	f7fe f827 	bl	4558 <z_impl_k_sem_give>
}
    650a:	4628      	mov	r0, r5
    650c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		dev_data->busy = true;
    6510:	2301      	movs	r3, #1
    6512:	f884 306c 	strb.w	r3, [r4, #108]	; 0x6c
	if (tx_bufs) {
    6516:	f1b8 0f00 	cmp.w	r8, #0
    651a:	d05d      	beq.n	65d8 <transceive+0x12e>
		ctx->current_tx = tx_bufs->buffers;
    651c:	f8d8 3000 	ldr.w	r3, [r8]
    6520:	6463      	str	r3, [r4, #68]	; 0x44
		ctx->tx_count = tx_bufs->count;
    6522:	f8d8 2004 	ldr.w	r2, [r8, #4]
    6526:	64a2      	str	r2, [r4, #72]	; 0x48
		ctx->tx_buf = (const uint8_t *)ctx->current_tx->buf;
    6528:	681a      	ldr	r2, [r3, #0]
    652a:	6562      	str	r2, [r4, #84]	; 0x54
		ctx->tx_len = ctx->current_tx->len / dfs;
    652c:	685b      	ldr	r3, [r3, #4]
    652e:	65a3      	str	r3, [r4, #88]	; 0x58
	if (rx_bufs) {
    6530:	2f00      	cmp	r7, #0
    6532:	d057      	beq.n	65e4 <transceive+0x13a>
		ctx->current_rx = rx_bufs->buffers;
    6534:	683b      	ldr	r3, [r7, #0]
    6536:	64e3      	str	r3, [r4, #76]	; 0x4c
		ctx->rx_count = rx_bufs->count;
    6538:	687a      	ldr	r2, [r7, #4]
    653a:	6522      	str	r2, [r4, #80]	; 0x50
		ctx->rx_buf = (uint8_t *)ctx->current_rx->buf;
    653c:	681a      	ldr	r2, [r3, #0]
    653e:	65e2      	str	r2, [r4, #92]	; 0x5c
		ctx->rx_len = ctx->current_rx->len / dfs;
    6540:	685b      	ldr	r3, [r3, #4]
    6542:	6623      	str	r3, [r4, #96]	; 0x60
	ctx->sync_status = 0;
    6544:	2300      	movs	r3, #0
    6546:	63a3      	str	r3, [r4, #56]	; 0x38
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio_dev) {
    6548:	6823      	ldr	r3, [r4, #0]
    654a:	b1c3      	cbz	r3, 657e <transceive+0xd4>
    654c:	689b      	ldr	r3, [r3, #8]
    654e:	b1b3      	cbz	r3, 657e <transceive+0xd4>
    6550:	6818      	ldr	r0, [r3, #0]
    6552:	b1a0      	cbz	r0, 657e <transceive+0xd4>
			gpio_pin_set(ctx->config->cs->gpio_dev,
    6554:	7a19      	ldrb	r1, [r3, #8]
	const struct gpio_driver_data *const data =
    6556:	6903      	ldr	r3, [r0, #16]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    6558:	681a      	ldr	r2, [r3, #0]
    655a:	2301      	movs	r3, #1
    655c:	408b      	lsls	r3, r1
    655e:	421a      	tst	r2, r3
    6560:	d146      	bne.n	65f0 <transceive+0x146>
    6562:	2301      	movs	r3, #1
	if (value != 0)	{
    6564:	2b00      	cmp	r3, #0
    6566:	d045      	beq.n	65f4 <transceive+0x14a>
		ret = gpio_port_set_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    6568:	2301      	movs	r3, #1
    656a:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    656e:	6883      	ldr	r3, [r0, #8]
	return api->port_set_bits_raw(port, pins);
    6570:	68db      	ldr	r3, [r3, #12]
    6572:	4798      	blx	r3
			k_busy_wait(ctx->config->cs->delay);
    6574:	6823      	ldr	r3, [r4, #0]
    6576:	689b      	ldr	r3, [r3, #8]
    6578:	6858      	ldr	r0, [r3, #4]
	z_impl_k_busy_wait(usec_to_wait);
    657a:	f000 fe9a 	bl	72b2 <z_impl_k_busy_wait>
		transfer_next_chunk(dev);
    657e:	4630      	mov	r0, r6
    6580:	f7fb ff5a 	bl	2438 <transfer_next_chunk>
	timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    6584:	6e23      	ldr	r3, [r4, #96]	; 0x60
    6586:	6da2      	ldr	r2, [r4, #88]	; 0x58
    6588:	429a      	cmp	r2, r3
    658a:	bf38      	it	cc
    658c:	461a      	movcc	r2, r3
    658e:	f44f 53fa 	mov.w	r3, #8000	; 0x1f40
    6592:	fb03 f302 	mul.w	r3, r3, r2
		     ctx->config->frequency;
    6596:	6822      	ldr	r2, [r4, #0]
    6598:	6812      	ldr	r2, [r2, #0]
	timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    659a:	fbb3 f3f2 	udiv	r3, r3, r2
	timeout_ms += CONFIG_SPI_COMPLETION_TIMEOUT_TOLERANCE;
    659e:	33c8      	adds	r3, #200	; 0xc8
	if (!ctx->asynchronous) {
    65a0:	f894 2040 	ldrb.w	r2, [r4, #64]	; 0x40
    65a4:	2a00      	cmp	r2, #0
    65a6:	d1a5      	bne.n	64f4 <transceive+0x4a>
		if (k_sem_take(&ctx->sync, K_MSEC(timeout_ms))) {
    65a8:	f104 0620 	add.w	r6, r4, #32
    65ac:	0c59      	lsrs	r1, r3, #17
    65ae:	03dd      	lsls	r5, r3, #15
    65b0:	f240 30e7 	movw	r0, #999	; 0x3e7
    65b4:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    65b8:	2300      	movs	r3, #0
    65ba:	1828      	adds	r0, r5, r0
    65bc:	f04f 0500 	mov.w	r5, #0
    65c0:	eb45 0101 	adc.w	r1, r5, r1
    65c4:	f7f9 fd9c 	bl	100 <__aeabi_uldivmod>
    65c8:	4602      	mov	r2, r0
    65ca:	460b      	mov	r3, r1
	return z_impl_k_sem_take(sem, timeout);
    65cc:	4630      	mov	r0, r6
    65ce:	f7fd ffeb 	bl	45a8 <z_impl_k_sem_take>
    65d2:	b9b0      	cbnz	r0, 6602 <transceive+0x158>
		status = ctx->sync_status;
    65d4:	6ba5      	ldr	r5, [r4, #56]	; 0x38
    65d6:	e78d      	b.n	64f4 <transceive+0x4a>
		ctx->current_tx = NULL;
    65d8:	2300      	movs	r3, #0
    65da:	6463      	str	r3, [r4, #68]	; 0x44
		ctx->tx_count = 0;
    65dc:	64a3      	str	r3, [r4, #72]	; 0x48
		ctx->tx_buf = NULL;
    65de:	6563      	str	r3, [r4, #84]	; 0x54
		ctx->tx_len = 0;
    65e0:	65a3      	str	r3, [r4, #88]	; 0x58
    65e2:	e7a5      	b.n	6530 <transceive+0x86>
		ctx->current_rx = NULL;
    65e4:	2300      	movs	r3, #0
    65e6:	64e3      	str	r3, [r4, #76]	; 0x4c
		ctx->rx_count = 0;
    65e8:	6523      	str	r3, [r4, #80]	; 0x50
		ctx->rx_buf = NULL;
    65ea:	65e3      	str	r3, [r4, #92]	; 0x5c
		ctx->rx_len = 0;
    65ec:	6623      	str	r3, [r4, #96]	; 0x60
    65ee:	e7a9      	b.n	6544 <transceive+0x9a>
		value = (value != 0) ? 0 : 1;
    65f0:	462b      	mov	r3, r5
    65f2:	e7b7      	b.n	6564 <transceive+0xba>
		ret = gpio_port_clear_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    65f4:	2301      	movs	r3, #1
    65f6:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    65fa:	6883      	ldr	r3, [r0, #8]
	return api->port_clear_bits_raw(port, pins);
    65fc:	691b      	ldr	r3, [r3, #16]
    65fe:	4798      	blx	r3
    6600:	e7b8      	b.n	6574 <transceive+0xca>
			return -ETIMEDOUT;
    6602:	f06f 0573 	mvn.w	r5, #115	; 0x73
    6606:	e775      	b.n	64f4 <transceive+0x4a>

00006608 <spi_nrfx_transceive_async>:
{
    6608:	b510      	push	{r4, lr}
    660a:	b082      	sub	sp, #8
	return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, async);
    660c:	9c04      	ldr	r4, [sp, #16]
    660e:	9401      	str	r4, [sp, #4]
    6610:	2401      	movs	r4, #1
    6612:	9400      	str	r4, [sp, #0]
    6614:	f7ff ff49 	bl	64aa <transceive>
}
    6618:	b002      	add	sp, #8
    661a:	bd10      	pop	{r4, pc}

0000661c <spi_nrfx_transceive>:
{
    661c:	b510      	push	{r4, lr}
    661e:	b082      	sub	sp, #8
	return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL);
    6620:	2400      	movs	r4, #0
    6622:	9401      	str	r4, [sp, #4]
    6624:	9400      	str	r4, [sp, #0]
    6626:	f7ff ff40 	bl	64aa <transceive>
}
    662a:	b002      	add	sp, #8
    662c:	bd10      	pop	{r4, pc}

0000662e <spi_3_init>:
#ifdef CONFIG_SPI_2_NRF_SPIM
SPI_NRFX_SPIM_DEVICE(2);
#endif

#ifdef CONFIG_SPI_3_NRF_SPIM
SPI_NRFX_SPIM_DEVICE(3);
    662e:	b510      	push	{r4, lr}
    6630:	4604      	mov	r4, r0
    6632:	2200      	movs	r2, #0
    6634:	2101      	movs	r1, #1
    6636:	202f      	movs	r0, #47	; 0x2f
    6638:	f7fa fdfc 	bl	1234 <z_arm_irq_priority_set>
	return dev->data;
    663c:	6924      	ldr	r4, [r4, #16]
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio_dev) {
    663e:	6823      	ldr	r3, [r4, #0]
    6640:	b1c3      	cbz	r3, 6674 <spi_3_init+0x46>
    6642:	689b      	ldr	r3, [r3, #8]
    6644:	b1b3      	cbz	r3, 6674 <spi_3_init+0x46>
    6646:	681a      	ldr	r2, [r3, #0]
    6648:	b1a2      	cbz	r2, 6674 <spi_3_init+0x46>
			k_busy_wait(ctx->config->cs->delay);
    664a:	6858      	ldr	r0, [r3, #4]
	z_impl_k_busy_wait(usec_to_wait);
    664c:	f000 fe31 	bl	72b2 <z_impl_k_busy_wait>
			gpio_pin_set(ctx->config->cs->gpio_dev,
    6650:	6823      	ldr	r3, [r4, #0]
    6652:	689b      	ldr	r3, [r3, #8]
    6654:	6818      	ldr	r0, [r3, #0]
    6656:	7a19      	ldrb	r1, [r3, #8]
	const struct gpio_driver_data *const data =
    6658:	6903      	ldr	r3, [r0, #16]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    665a:	681a      	ldr	r2, [r3, #0]
    665c:	2301      	movs	r3, #1
    665e:	408b      	lsls	r3, r1
    6660:	421a      	tst	r2, r3
    6662:	d10b      	bne.n	667c <spi_3_init+0x4e>
    6664:	2300      	movs	r3, #0
	if (value != 0)	{
    6666:	b15b      	cbz	r3, 6680 <spi_3_init+0x52>
		ret = gpio_port_set_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    6668:	2301      	movs	r3, #1
    666a:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    666e:	6883      	ldr	r3, [r0, #8]
	return api->port_set_bits_raw(port, pins);
    6670:	68db      	ldr	r3, [r3, #12]
    6672:	4798      	blx	r3
    6674:	6923      	ldr	r3, [r4, #16]
	if (!k_sem_count_get(&ctx->lock)) {
    6676:	b153      	cbz	r3, 668e <spi_3_init+0x60>
SPI_NRFX_SPIM_DEVICE(3);
    6678:	2000      	movs	r0, #0
    667a:	bd10      	pop	{r4, pc}
		value = (value != 0) ? 0 : 1;
    667c:	2301      	movs	r3, #1
    667e:	e7f2      	b.n	6666 <spi_3_init+0x38>
		ret = gpio_port_clear_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    6680:	2301      	movs	r3, #1
    6682:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    6686:	6883      	ldr	r3, [r0, #8]
	return api->port_clear_bits_raw(port, pins);
    6688:	691b      	ldr	r3, [r3, #16]
    668a:	4798      	blx	r3
	return ret;
    668c:	e7f2      	b.n	6674 <spi_3_init+0x46>
		ctx->owner = NULL;
    668e:	6063      	str	r3, [r4, #4]
		k_sem_give(&ctx->lock);
    6690:	f104 0008 	add.w	r0, r4, #8
	z_impl_k_sem_give(sem);
    6694:	f7fd ff60 	bl	4558 <z_impl_k_sem_give>
}
    6698:	e7ee      	b.n	6678 <spi_3_init+0x4a>

0000669a <spi_nrfx_release>:
{
    669a:	b510      	push	{r4, lr}
	return dev->data;
    669c:	6904      	ldr	r4, [r0, #16]
	return !!(ctx->config == config);
    669e:	6823      	ldr	r3, [r4, #0]
	if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
    66a0:	428b      	cmp	r3, r1
    66a2:	d131      	bne.n	6708 <spi_nrfx_release+0x6e>
	if (dev_data->busy) {
    66a4:	f894 306c 	ldrb.w	r3, [r4, #108]	; 0x6c
    66a8:	2b00      	cmp	r3, #0
    66aa:	d130      	bne.n	670e <spi_nrfx_release+0x74>
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio_dev) {
    66ac:	6823      	ldr	r3, [r4, #0]
    66ae:	b1c3      	cbz	r3, 66e2 <spi_nrfx_release+0x48>
    66b0:	689b      	ldr	r3, [r3, #8]
    66b2:	b1b3      	cbz	r3, 66e2 <spi_nrfx_release+0x48>
    66b4:	681a      	ldr	r2, [r3, #0]
    66b6:	b1a2      	cbz	r2, 66e2 <spi_nrfx_release+0x48>
			k_busy_wait(ctx->config->cs->delay);
    66b8:	6858      	ldr	r0, [r3, #4]
	z_impl_k_busy_wait(usec_to_wait);
    66ba:	f000 fdfa 	bl	72b2 <z_impl_k_busy_wait>
			gpio_pin_set(ctx->config->cs->gpio_dev,
    66be:	6823      	ldr	r3, [r4, #0]
    66c0:	689b      	ldr	r3, [r3, #8]
    66c2:	6818      	ldr	r0, [r3, #0]
    66c4:	7a19      	ldrb	r1, [r3, #8]
	const struct gpio_driver_data *const data =
    66c6:	6903      	ldr	r3, [r0, #16]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    66c8:	681a      	ldr	r2, [r3, #0]
    66ca:	2301      	movs	r3, #1
    66cc:	408b      	lsls	r3, r1
    66ce:	421a      	tst	r2, r3
    66d0:	d10b      	bne.n	66ea <spi_nrfx_release+0x50>
    66d2:	2300      	movs	r3, #0
	if (value != 0)	{
    66d4:	b15b      	cbz	r3, 66ee <spi_nrfx_release+0x54>
		ret = gpio_port_set_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    66d6:	2301      	movs	r3, #1
    66d8:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    66dc:	6883      	ldr	r3, [r0, #8]
	return api->port_set_bits_raw(port, pins);
    66de:	68db      	ldr	r3, [r3, #12]
    66e0:	4798      	blx	r3
    66e2:	6923      	ldr	r3, [r4, #16]
	if (!k_sem_count_get(&ctx->lock)) {
    66e4:	b153      	cbz	r3, 66fc <spi_nrfx_release+0x62>
	return 0;
    66e6:	2000      	movs	r0, #0
}
    66e8:	bd10      	pop	{r4, pc}
		value = (value != 0) ? 0 : 1;
    66ea:	2301      	movs	r3, #1
    66ec:	e7f2      	b.n	66d4 <spi_nrfx_release+0x3a>
		ret = gpio_port_clear_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    66ee:	2301      	movs	r3, #1
    66f0:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    66f4:	6883      	ldr	r3, [r0, #8]
	return api->port_clear_bits_raw(port, pins);
    66f6:	691b      	ldr	r3, [r3, #16]
    66f8:	4798      	blx	r3
	return ret;
    66fa:	e7f2      	b.n	66e2 <spi_nrfx_release+0x48>
		ctx->owner = NULL;
    66fc:	6063      	str	r3, [r4, #4]
		k_sem_give(&ctx->lock);
    66fe:	f104 0008 	add.w	r0, r4, #8
	z_impl_k_sem_give(sem);
    6702:	f7fd ff29 	bl	4558 <z_impl_k_sem_give>
}
    6706:	e7ee      	b.n	66e6 <spi_nrfx_release+0x4c>
		return -EINVAL;
    6708:	f06f 0015 	mvn.w	r0, #21
    670c:	e7ec      	b.n	66e8 <spi_nrfx_release+0x4e>
		return -EBUSY;
    670e:	f06f 000f 	mvn.w	r0, #15
    6712:	e7e9      	b.n	66e8 <spi_nrfx_release+0x4e>

00006714 <event_handler>:
{
    6714:	b508      	push	{r3, lr}
	if (p_event->type == NRFX_SPIM_EVENT_DONE) {
    6716:	7803      	ldrb	r3, [r0, #0]
    6718:	2b00      	cmp	r3, #0
    671a:	d139      	bne.n	6790 <event_handler+0x7c>
		spi_context_update_tx(&dev_data->ctx, 1, dev_data->chunk_len);
    671c:	6e8a      	ldr	r2, [r1, #104]	; 0x68
	if (!ctx->tx_len) {
    671e:	6d8b      	ldr	r3, [r1, #88]	; 0x58
    6720:	b1c3      	cbz	r3, 6754 <event_handler+0x40>
	if (len > ctx->tx_len) {
    6722:	429a      	cmp	r2, r3
    6724:	d816      	bhi.n	6754 <event_handler+0x40>
	ctx->tx_len -= len;
    6726:	1a9b      	subs	r3, r3, r2
    6728:	658b      	str	r3, [r1, #88]	; 0x58
	if (!ctx->tx_len) {
    672a:	b97b      	cbnz	r3, 674c <event_handler+0x38>
		ctx->tx_count--;
    672c:	6c8b      	ldr	r3, [r1, #72]	; 0x48
    672e:	3b01      	subs	r3, #1
    6730:	648b      	str	r3, [r1, #72]	; 0x48
		if (ctx->tx_count) {
    6732:	b143      	cbz	r3, 6746 <event_handler+0x32>
			ctx->current_tx++;
    6734:	6c4b      	ldr	r3, [r1, #68]	; 0x44
    6736:	f103 0008 	add.w	r0, r3, #8
    673a:	6448      	str	r0, [r1, #68]	; 0x44
			ctx->tx_buf = (const uint8_t *)ctx->current_tx->buf;
    673c:	6898      	ldr	r0, [r3, #8]
    673e:	6548      	str	r0, [r1, #84]	; 0x54
			ctx->tx_len = ctx->current_tx->len / dfs;
    6740:	68db      	ldr	r3, [r3, #12]
    6742:	658b      	str	r3, [r1, #88]	; 0x58
    6744:	e006      	b.n	6754 <event_handler+0x40>
			ctx->tx_buf = NULL;
    6746:	2300      	movs	r3, #0
    6748:	654b      	str	r3, [r1, #84]	; 0x54
    674a:	e003      	b.n	6754 <event_handler+0x40>
	} else if (ctx->tx_buf) {
    674c:	6d4b      	ldr	r3, [r1, #84]	; 0x54
    674e:	b10b      	cbz	r3, 6754 <event_handler+0x40>
		ctx->tx_buf += dfs * len;
    6750:	4413      	add	r3, r2
    6752:	654b      	str	r3, [r1, #84]	; 0x54
	if (!ctx->rx_len) {
    6754:	6e0b      	ldr	r3, [r1, #96]	; 0x60
    6756:	b1c3      	cbz	r3, 678a <event_handler+0x76>
	if (len > ctx->rx_len) {
    6758:	429a      	cmp	r2, r3
    675a:	d816      	bhi.n	678a <event_handler+0x76>
	ctx->rx_len -= len;
    675c:	1a9b      	subs	r3, r3, r2
    675e:	660b      	str	r3, [r1, #96]	; 0x60
	if (!ctx->rx_len) {
    6760:	b97b      	cbnz	r3, 6782 <event_handler+0x6e>
		ctx->rx_count--;
    6762:	6d0b      	ldr	r3, [r1, #80]	; 0x50
    6764:	3b01      	subs	r3, #1
    6766:	650b      	str	r3, [r1, #80]	; 0x50
		if (ctx->rx_count) {
    6768:	b143      	cbz	r3, 677c <event_handler+0x68>
			ctx->current_rx++;
    676a:	6ccb      	ldr	r3, [r1, #76]	; 0x4c
    676c:	f103 0208 	add.w	r2, r3, #8
    6770:	64ca      	str	r2, [r1, #76]	; 0x4c
			ctx->rx_buf = (uint8_t *)ctx->current_rx->buf;
    6772:	689a      	ldr	r2, [r3, #8]
    6774:	65ca      	str	r2, [r1, #92]	; 0x5c
			ctx->rx_len = ctx->current_rx->len / dfs;
    6776:	68db      	ldr	r3, [r3, #12]
    6778:	660b      	str	r3, [r1, #96]	; 0x60
    677a:	e006      	b.n	678a <event_handler+0x76>
			ctx->rx_buf = NULL;
    677c:	2300      	movs	r3, #0
    677e:	65cb      	str	r3, [r1, #92]	; 0x5c
    6780:	e003      	b.n	678a <event_handler+0x76>
	} else if (ctx->rx_buf) {
    6782:	6dcb      	ldr	r3, [r1, #92]	; 0x5c
    6784:	b10b      	cbz	r3, 678a <event_handler+0x76>
		ctx->rx_buf += dfs * len;
    6786:	441a      	add	r2, r3
    6788:	65ca      	str	r2, [r1, #92]	; 0x5c
		transfer_next_chunk(dev_data->dev);
    678a:	6e48      	ldr	r0, [r1, #100]	; 0x64
    678c:	f7fb ffca 	bl	2724 <transfer_next_chunk>
}
    6790:	bd08      	pop	{r3, pc}

00006792 <transceive>:
{
    6792:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6796:	4606      	mov	r6, r0
    6798:	460d      	mov	r5, r1
    679a:	4690      	mov	r8, r2
    679c:	461f      	mov	r7, r3
	return dev->data;
    679e:	6904      	ldr	r4, [r0, #16]
	if ((spi_cfg->operation & SPI_LOCK_ON) &&
    67a0:	888b      	ldrh	r3, [r1, #4]
    67a2:	f413 4f80 	tst.w	r3, #16384	; 0x4000
    67a6:	d004      	beq.n	67b2 <transceive+0x20>
    67a8:	6923      	ldr	r3, [r4, #16]
    67aa:	b913      	cbnz	r3, 67b2 <transceive+0x20>
		(ctx->owner == spi_cfg)) {
    67ac:	6863      	ldr	r3, [r4, #4]
		(k_sem_count_get(&ctx->lock) == 0) &&
    67ae:	4299      	cmp	r1, r3
    67b0:	d00e      	beq.n	67d0 <transceive+0x3e>
	k_sem_take(&ctx->lock, K_FOREVER);
    67b2:	f104 0008 	add.w	r0, r4, #8
	return z_impl_k_sem_take(sem, timeout);
    67b6:	f04f 32ff 	mov.w	r2, #4294967295
    67ba:	f04f 33ff 	mov.w	r3, #4294967295
    67be:	f7fd fef3 	bl	45a8 <z_impl_k_sem_take>
	ctx->owner = spi_cfg;
    67c2:	6065      	str	r5, [r4, #4]
	ctx->asynchronous = asynchronous;
    67c4:	f89d 3018 	ldrb.w	r3, [sp, #24]
    67c8:	f884 3040 	strb.w	r3, [r4, #64]	; 0x40
	ctx->signal = signal;
    67cc:	9b07      	ldr	r3, [sp, #28]
    67ce:	63e3      	str	r3, [r4, #60]	; 0x3c
	error = configure(dev, spi_cfg);
    67d0:	4629      	mov	r1, r5
    67d2:	4630      	mov	r0, r6
    67d4:	f7fb feb6 	bl	2544 <configure>
	if (error == 0) {
    67d8:	4605      	mov	r5, r0
    67da:	b168      	cbz	r0, 67f8 <transceive+0x66>
	if (!ctx->asynchronous || (status < 0)) {
    67dc:	f894 3040 	ldrb.w	r3, [r4, #64]	; 0x40
    67e0:	b10b      	cbz	r3, 67e6 <transceive+0x54>
    67e2:	2d00      	cmp	r5, #0
    67e4:	da05      	bge.n	67f2 <transceive+0x60>
		ctx->owner = NULL;
    67e6:	2300      	movs	r3, #0
    67e8:	6063      	str	r3, [r4, #4]
		k_sem_give(&ctx->lock);
    67ea:	f104 0008 	add.w	r0, r4, #8
	z_impl_k_sem_give(sem);
    67ee:	f7fd feb3 	bl	4558 <z_impl_k_sem_give>
}
    67f2:	4628      	mov	r0, r5
    67f4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		dev_data->busy = true;
    67f8:	2301      	movs	r3, #1
    67fa:	f884 306c 	strb.w	r3, [r4, #108]	; 0x6c
	if (tx_bufs) {
    67fe:	f1b8 0f00 	cmp.w	r8, #0
    6802:	d05d      	beq.n	68c0 <transceive+0x12e>
		ctx->current_tx = tx_bufs->buffers;
    6804:	f8d8 3000 	ldr.w	r3, [r8]
    6808:	6463      	str	r3, [r4, #68]	; 0x44
		ctx->tx_count = tx_bufs->count;
    680a:	f8d8 2004 	ldr.w	r2, [r8, #4]
    680e:	64a2      	str	r2, [r4, #72]	; 0x48
		ctx->tx_buf = (const uint8_t *)ctx->current_tx->buf;
    6810:	681a      	ldr	r2, [r3, #0]
    6812:	6562      	str	r2, [r4, #84]	; 0x54
		ctx->tx_len = ctx->current_tx->len / dfs;
    6814:	685b      	ldr	r3, [r3, #4]
    6816:	65a3      	str	r3, [r4, #88]	; 0x58
	if (rx_bufs) {
    6818:	2f00      	cmp	r7, #0
    681a:	d057      	beq.n	68cc <transceive+0x13a>
		ctx->current_rx = rx_bufs->buffers;
    681c:	683b      	ldr	r3, [r7, #0]
    681e:	64e3      	str	r3, [r4, #76]	; 0x4c
		ctx->rx_count = rx_bufs->count;
    6820:	687a      	ldr	r2, [r7, #4]
    6822:	6522      	str	r2, [r4, #80]	; 0x50
		ctx->rx_buf = (uint8_t *)ctx->current_rx->buf;
    6824:	681a      	ldr	r2, [r3, #0]
    6826:	65e2      	str	r2, [r4, #92]	; 0x5c
		ctx->rx_len = ctx->current_rx->len / dfs;
    6828:	685b      	ldr	r3, [r3, #4]
    682a:	6623      	str	r3, [r4, #96]	; 0x60
	ctx->sync_status = 0;
    682c:	2300      	movs	r3, #0
    682e:	63a3      	str	r3, [r4, #56]	; 0x38
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio_dev) {
    6830:	6823      	ldr	r3, [r4, #0]
    6832:	b1c3      	cbz	r3, 6866 <transceive+0xd4>
    6834:	689b      	ldr	r3, [r3, #8]
    6836:	b1b3      	cbz	r3, 6866 <transceive+0xd4>
    6838:	6818      	ldr	r0, [r3, #0]
    683a:	b1a0      	cbz	r0, 6866 <transceive+0xd4>
			gpio_pin_set(ctx->config->cs->gpio_dev,
    683c:	7a19      	ldrb	r1, [r3, #8]
	const struct gpio_driver_data *const data =
    683e:	6903      	ldr	r3, [r0, #16]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    6840:	681a      	ldr	r2, [r3, #0]
    6842:	2301      	movs	r3, #1
    6844:	408b      	lsls	r3, r1
    6846:	421a      	tst	r2, r3
    6848:	d146      	bne.n	68d8 <transceive+0x146>
    684a:	2301      	movs	r3, #1
	if (value != 0)	{
    684c:	2b00      	cmp	r3, #0
    684e:	d045      	beq.n	68dc <transceive+0x14a>
		ret = gpio_port_set_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    6850:	2301      	movs	r3, #1
    6852:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    6856:	6883      	ldr	r3, [r0, #8]
	return api->port_set_bits_raw(port, pins);
    6858:	68db      	ldr	r3, [r3, #12]
    685a:	4798      	blx	r3
			k_busy_wait(ctx->config->cs->delay);
    685c:	6823      	ldr	r3, [r4, #0]
    685e:	689b      	ldr	r3, [r3, #8]
    6860:	6858      	ldr	r0, [r3, #4]
	z_impl_k_busy_wait(usec_to_wait);
    6862:	f000 fd26 	bl	72b2 <z_impl_k_busy_wait>
		transfer_next_chunk(dev);
    6866:	4630      	mov	r0, r6
    6868:	f7fb ff5c 	bl	2724 <transfer_next_chunk>
	timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    686c:	6e23      	ldr	r3, [r4, #96]	; 0x60
    686e:	6da2      	ldr	r2, [r4, #88]	; 0x58
    6870:	429a      	cmp	r2, r3
    6872:	bf38      	it	cc
    6874:	461a      	movcc	r2, r3
    6876:	f44f 53fa 	mov.w	r3, #8000	; 0x1f40
    687a:	fb03 f302 	mul.w	r3, r3, r2
		     ctx->config->frequency;
    687e:	6822      	ldr	r2, [r4, #0]
    6880:	6812      	ldr	r2, [r2, #0]
	timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    6882:	fbb3 f3f2 	udiv	r3, r3, r2
	timeout_ms += CONFIG_SPI_COMPLETION_TIMEOUT_TOLERANCE;
    6886:	33c8      	adds	r3, #200	; 0xc8
	if (!ctx->asynchronous) {
    6888:	f894 2040 	ldrb.w	r2, [r4, #64]	; 0x40
    688c:	2a00      	cmp	r2, #0
    688e:	d1a5      	bne.n	67dc <transceive+0x4a>
		if (k_sem_take(&ctx->sync, K_MSEC(timeout_ms))) {
    6890:	f104 0620 	add.w	r6, r4, #32
    6894:	0c59      	lsrs	r1, r3, #17
    6896:	03dd      	lsls	r5, r3, #15
    6898:	f240 30e7 	movw	r0, #999	; 0x3e7
    689c:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    68a0:	2300      	movs	r3, #0
    68a2:	1828      	adds	r0, r5, r0
    68a4:	f04f 0500 	mov.w	r5, #0
    68a8:	eb45 0101 	adc.w	r1, r5, r1
    68ac:	f7f9 fc28 	bl	100 <__aeabi_uldivmod>
    68b0:	4602      	mov	r2, r0
    68b2:	460b      	mov	r3, r1
	return z_impl_k_sem_take(sem, timeout);
    68b4:	4630      	mov	r0, r6
    68b6:	f7fd fe77 	bl	45a8 <z_impl_k_sem_take>
    68ba:	b9b0      	cbnz	r0, 68ea <transceive+0x158>
		status = ctx->sync_status;
    68bc:	6ba5      	ldr	r5, [r4, #56]	; 0x38
    68be:	e78d      	b.n	67dc <transceive+0x4a>
		ctx->current_tx = NULL;
    68c0:	2300      	movs	r3, #0
    68c2:	6463      	str	r3, [r4, #68]	; 0x44
		ctx->tx_count = 0;
    68c4:	64a3      	str	r3, [r4, #72]	; 0x48
		ctx->tx_buf = NULL;
    68c6:	6563      	str	r3, [r4, #84]	; 0x54
		ctx->tx_len = 0;
    68c8:	65a3      	str	r3, [r4, #88]	; 0x58
    68ca:	e7a5      	b.n	6818 <transceive+0x86>
		ctx->current_rx = NULL;
    68cc:	2300      	movs	r3, #0
    68ce:	64e3      	str	r3, [r4, #76]	; 0x4c
		ctx->rx_count = 0;
    68d0:	6523      	str	r3, [r4, #80]	; 0x50
		ctx->rx_buf = NULL;
    68d2:	65e3      	str	r3, [r4, #92]	; 0x5c
		ctx->rx_len = 0;
    68d4:	6623      	str	r3, [r4, #96]	; 0x60
    68d6:	e7a9      	b.n	682c <transceive+0x9a>
		value = (value != 0) ? 0 : 1;
    68d8:	462b      	mov	r3, r5
    68da:	e7b7      	b.n	684c <transceive+0xba>
		ret = gpio_port_clear_bits_raw(port, (gpio_port_pins_t)BIT(pin));
    68dc:	2301      	movs	r3, #1
    68de:	fa03 f101 	lsl.w	r1, r3, r1
	const struct gpio_driver_api *api =
    68e2:	6883      	ldr	r3, [r0, #8]
	return api->port_clear_bits_raw(port, pins);
    68e4:	691b      	ldr	r3, [r3, #16]
    68e6:	4798      	blx	r3
    68e8:	e7b8      	b.n	685c <transceive+0xca>
			return -ETIMEDOUT;
    68ea:	f06f 0573 	mvn.w	r5, #115	; 0x73
    68ee:	e775      	b.n	67dc <transceive+0x4a>

000068f0 <spi_nrfx_transceive_async>:
{
    68f0:	b510      	push	{r4, lr}
    68f2:	b082      	sub	sp, #8
	return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, async);
    68f4:	9c04      	ldr	r4, [sp, #16]
    68f6:	9401      	str	r4, [sp, #4]
    68f8:	2401      	movs	r4, #1
    68fa:	9400      	str	r4, [sp, #0]
    68fc:	f7ff ff49 	bl	6792 <transceive>
}
    6900:	b002      	add	sp, #8
    6902:	bd10      	pop	{r4, pc}

00006904 <spi_nrfx_transceive>:
{
    6904:	b510      	push	{r4, lr}
    6906:	b082      	sub	sp, #8
	return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL);
    6908:	2400      	movs	r4, #0
    690a:	9401      	str	r4, [sp, #4]
    690c:	9400      	str	r4, [sp, #0]
    690e:	f7ff ff40 	bl	6792 <transceive>
}
    6912:	b002      	add	sp, #8
    6914:	bd10      	pop	{r4, pc}

00006916 <endtx_isr>:
	return dev->config;
    6916:	6843      	ldr	r3, [r0, #4]
	return config->uarte_regs;
    6918:	681b      	ldr	r3, [r3, #0]
	__asm__ volatile(
    691a:	f04f 0120 	mov.w	r1, #32
    691e:	f3ef 8211 	mrs	r2, BASEPRI
    6922:	f381 8812 	msr	BASEPRI_MAX, r1
    6926:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    692a:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
    692e:	b131      	cbz	r1, 693e <endtx_isr+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6930:	2100      	movs	r1, #0
    6932:	f8c3 1120 	str.w	r1, [r3, #288]	; 0x120
    6936:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    693a:	2101      	movs	r1, #1
    693c:	60d9      	str	r1, [r3, #12]
	__asm__ volatile(
    693e:	f382 8811 	msr	BASEPRI, r2
    6942:	f3bf 8f6f 	isb	sy
}
    6946:	4770      	bx	lr

00006948 <uarte_nrfx_isr_int>:
{
    6948:	b538      	push	{r3, r4, r5, lr}
    694a:	4604      	mov	r4, r0
	return dev->config;
    694c:	6843      	ldr	r3, [r0, #4]
	return config->uarte_regs;
    694e:	681d      	ldr	r5, [r3, #0]
    return p_reg->INTENSET & mask;
    6950:	f8d5 3304 	ldr.w	r3, [r5, #772]	; 0x304
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
    6954:	f413 7f80 	tst.w	r3, #256	; 0x100
    6958:	d002      	beq.n	6960 <uarte_nrfx_isr_int+0x18>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    695a:	f8d5 3120 	ldr.w	r3, [r5, #288]	; 0x120
    695e:	b9db      	cbnz	r3, 6998 <uarte_nrfx_isr_int+0x50>
	return dev->config;
    6960:	6863      	ldr	r3, [r4, #4]
	if (get_dev_config(dev)->flags & UARTE_CFG_FLAG_LOW_POWER) {
    6962:	685b      	ldr	r3, [r3, #4]
    6964:	f013 0f10 	tst.w	r3, #16
    6968:	d015      	beq.n	6996 <uarte_nrfx_isr_int+0x4e>
	__asm__ volatile(
    696a:	f04f 0220 	mov.w	r2, #32
    696e:	f3ef 8311 	mrs	r3, BASEPRI
    6972:	f382 8812 	msr	BASEPRI_MAX, r2
    6976:	f3bf 8f6f 	isb	sy
    697a:	f8d5 2158 	ldr.w	r2, [r5, #344]	; 0x158
		if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
    697e:	b112      	cbz	r2, 6986 <uarte_nrfx_isr_int+0x3e>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    6980:	2200      	movs	r2, #0
    6982:	f8c5 2500 	str.w	r2, [r5, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    6986:	f44f 0280 	mov.w	r2, #4194304	; 0x400000
    698a:	f8c5 2308 	str.w	r2, [r5, #776]	; 0x308
	__asm__ volatile(
    698e:	f383 8811 	msr	BASEPRI, r3
    6992:	f3bf 8f6f 	isb	sy
}
    6996:	bd38      	pop	{r3, r4, r5, pc}
		endtx_isr(dev);
    6998:	f7ff ffbd 	bl	6916 <endtx_isr>
    699c:	e7e0      	b.n	6960 <uarte_nrfx_isr_int+0x18>

0000699e <uarte_nrfx_configure>:
{
    699e:	b530      	push	{r4, r5, lr}
    69a0:	b083      	sub	sp, #12
    69a2:	4605      	mov	r5, r0
    69a4:	460c      	mov	r4, r1
	switch (cfg->stop_bits) {
    69a6:	794b      	ldrb	r3, [r1, #5]
    69a8:	2b01      	cmp	r3, #1
    69aa:	d006      	beq.n	69ba <uarte_nrfx_configure+0x1c>
    69ac:	2b03      	cmp	r3, #3
    69ae:	d011      	beq.n	69d4 <uarte_nrfx_configure+0x36>
    69b0:	f06f 0285 	mvn.w	r2, #133	; 0x85
}
    69b4:	4610      	mov	r0, r2
    69b6:	b003      	add	sp, #12
    69b8:	bd30      	pop	{r4, r5, pc}
		uarte_cfg.stop = NRF_UARTE_STOP_ONE;
    69ba:	2300      	movs	r3, #0
    69bc:	f88d 3002 	strb.w	r3, [sp, #2]
	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    69c0:	79a3      	ldrb	r3, [r4, #6]
    69c2:	2b03      	cmp	r3, #3
    69c4:	d14f      	bne.n	6a66 <uarte_nrfx_configure+0xc8>
	switch (cfg->flow_ctrl) {
    69c6:	79e3      	ldrb	r3, [r4, #7]
    69c8:	b143      	cbz	r3, 69dc <uarte_nrfx_configure+0x3e>
    69ca:	2b01      	cmp	r3, #1
    69cc:	d015      	beq.n	69fa <uarte_nrfx_configure+0x5c>
    69ce:	f06f 0285 	mvn.w	r2, #133	; 0x85
    69d2:	e7ef      	b.n	69b4 <uarte_nrfx_configure+0x16>
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
    69d4:	2310      	movs	r3, #16
    69d6:	f88d 3002 	strb.w	r3, [sp, #2]
		break;
    69da:	e7f1      	b.n	69c0 <uarte_nrfx_configure+0x22>
		uarte_cfg.hwfc = NRF_UARTE_HWFC_DISABLED;
    69dc:	2300      	movs	r3, #0
    69de:	f88d 3000 	strb.w	r3, [sp]
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
    69e2:	2300      	movs	r3, #0
    69e4:	f8ad 3004 	strh.w	r3, [sp, #4]
	switch (cfg->parity) {
    69e8:	7923      	ldrb	r3, [r4, #4]
    69ea:	2b01      	cmp	r3, #1
    69ec:	d033      	beq.n	6a56 <uarte_nrfx_configure+0xb8>
    69ee:	2b02      	cmp	r3, #2
    69f0:	d02d      	beq.n	6a4e <uarte_nrfx_configure+0xb0>
    69f2:	b173      	cbz	r3, 6a12 <uarte_nrfx_configure+0x74>
    69f4:	f06f 0285 	mvn.w	r2, #133	; 0x85
    69f8:	e7dc      	b.n	69b4 <uarte_nrfx_configure+0x16>
	return dev->config;
    69fa:	686b      	ldr	r3, [r5, #4]
		if (IS_HWFC_PINS_USED(get_dev_config(dev)->flags)) {
    69fc:	685b      	ldr	r3, [r3, #4]
    69fe:	f003 0201 	and.w	r2, r3, #1
    6a02:	f003 0302 	and.w	r3, r3, #2
    6a06:	4313      	orrs	r3, r2
    6a08:	d030      	beq.n	6a6c <uarte_nrfx_configure+0xce>
			uarte_cfg.hwfc = NRF_UARTE_HWFC_ENABLED;
    6a0a:	2301      	movs	r3, #1
    6a0c:	f88d 3000 	strb.w	r3, [sp]
		break;
    6a10:	e7e7      	b.n	69e2 <uarte_nrfx_configure+0x44>
		uarte_cfg.parity = NRF_UARTE_PARITY_EXCLUDED;
    6a12:	f88d 3001 	strb.w	r3, [sp, #1]
	if (baudrate_set(dev, cfg->baudrate) != 0) {
    6a16:	6821      	ldr	r1, [r4, #0]
    6a18:	4628      	mov	r0, r5
    6a1a:	f7fb ff29 	bl	2870 <baudrate_set>
    6a1e:	4602      	mov	r2, r0
    6a20:	bb38      	cbnz	r0, 6a72 <uarte_nrfx_configure+0xd4>
	return dev->config;
    6a22:	686b      	ldr	r3, [r5, #4]
	return config->uarte_regs;
    6a24:	6819      	ldr	r1, [r3, #0]
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    6a26:	f89d 3001 	ldrb.w	r3, [sp, #1]
                    | (uint32_t)p_cfg->stop
    6a2a:	f89d 0002 	ldrb.w	r0, [sp, #2]
    6a2e:	4303      	orrs	r3, r0
                    | (uint32_t)p_cfg->paritytype
    6a30:	f8bd 0004 	ldrh.w	r0, [sp, #4]
    6a34:	4303      	orrs	r3, r0
                    | (uint32_t)p_cfg->hwfc;
    6a36:	f89d 0000 	ldrb.w	r0, [sp]
    6a3a:	4303      	orrs	r3, r0
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    6a3c:	f8c1 356c 	str.w	r3, [r1, #1388]	; 0x56c
	return dev->data;
    6a40:	692b      	ldr	r3, [r5, #16]
	get_dev_data(dev)->uart_config = *cfg;
    6a42:	3304      	adds	r3, #4
    6a44:	e894 0003 	ldmia.w	r4, {r0, r1}
    6a48:	e883 0003 	stmia.w	r3, {r0, r1}
	return 0;
    6a4c:	e7b2      	b.n	69b4 <uarte_nrfx_configure+0x16>
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
    6a4e:	230e      	movs	r3, #14
    6a50:	f88d 3001 	strb.w	r3, [sp, #1]
		break;
    6a54:	e7df      	b.n	6a16 <uarte_nrfx_configure+0x78>
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
    6a56:	230e      	movs	r3, #14
    6a58:	f88d 3001 	strb.w	r3, [sp, #1]
		uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_ODD;
    6a5c:	f44f 7380 	mov.w	r3, #256	; 0x100
    6a60:	f8ad 3004 	strh.w	r3, [sp, #4]
		break;
    6a64:	e7d7      	b.n	6a16 <uarte_nrfx_configure+0x78>
		return -ENOTSUP;
    6a66:	f06f 0285 	mvn.w	r2, #133	; 0x85
    6a6a:	e7a3      	b.n	69b4 <uarte_nrfx_configure+0x16>
			return -ENOTSUP;
    6a6c:	f06f 0285 	mvn.w	r2, #133	; 0x85
    6a70:	e7a0      	b.n	69b4 <uarte_nrfx_configure+0x16>
		return -ENOTSUP;
    6a72:	f06f 0285 	mvn.w	r2, #133	; 0x85
    6a76:	e79d      	b.n	69b4 <uarte_nrfx_configure+0x16>

00006a78 <uarte_nrfx_config_get>:
{
    6a78:	460b      	mov	r3, r1
	return dev->data;
    6a7a:	6902      	ldr	r2, [r0, #16]
	*cfg = get_dev_data(dev)->uart_config;
    6a7c:	6891      	ldr	r1, [r2, #8]
    6a7e:	6850      	ldr	r0, [r2, #4]
    6a80:	e883 0003 	stmia.w	r3, {r0, r1}
}
    6a84:	2000      	movs	r0, #0
    6a86:	4770      	bx	lr

00006a88 <uarte_nrfx_err_check>:
	return dev->config;
    6a88:	6843      	ldr	r3, [r0, #4]
	return config->uarte_regs;
    6a8a:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    6a8c:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    6a90:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    6a94:	4770      	bx	lr

00006a96 <is_tx_ready>:
	return dev->config;
    6a96:	6843      	ldr	r3, [r0, #4]
	return config->uarte_regs;
    6a98:	681a      	ldr	r2, [r3, #0]
	bool ppi_endtx = get_dev_config(dev)->flags & UARTE_CFG_FLAG_PPI_ENDTX;
    6a9a:	685b      	ldr	r3, [r3, #4]
    6a9c:	f003 0308 	and.w	r3, r3, #8
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6aa0:	f8d2 1158 	ldr.w	r1, [r2, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    6aa4:	b929      	cbnz	r1, 6ab2 <is_tx_ready+0x1c>
    6aa6:	b933      	cbnz	r3, 6ab6 <is_tx_ready+0x20>
    6aa8:	f8d2 3120 	ldr.w	r3, [r2, #288]	; 0x120
    6aac:	b92b      	cbnz	r3, 6aba <is_tx_ready+0x24>
    6aae:	2000      	movs	r0, #0
    6ab0:	4770      	bx	lr
    6ab2:	2001      	movs	r0, #1
    6ab4:	4770      	bx	lr
    6ab6:	2000      	movs	r0, #0
    6ab8:	4770      	bx	lr
    6aba:	2001      	movs	r0, #1
}
    6abc:	4770      	bx	lr

00006abe <uarte_enable>:
	return dev->config;
    6abe:	6843      	ldr	r3, [r0, #4]
	return config->uarte_regs;
    6ac0:	681b      	ldr	r3, [r3, #0]
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    6ac2:	2208      	movs	r2, #8
    6ac4:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
}
    6ac8:	4770      	bx	lr

00006aca <tx_start>:
{
    6aca:	b510      	push	{r4, lr}
	return dev->config;
    6acc:	6843      	ldr	r3, [r0, #4]
	return config->uarte_regs;
    6ace:	681c      	ldr	r4, [r3, #0]
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    6ad0:	f8c4 1544 	str.w	r1, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    6ad4:	f8c4 2548 	str.w	r2, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6ad8:	2300      	movs	r3, #0
    6ada:	f8c4 3120 	str.w	r3, [r4, #288]	; 0x120
    6ade:	f8d4 2120 	ldr.w	r2, [r4, #288]	; 0x120
    6ae2:	f8c4 3158 	str.w	r3, [r4, #344]	; 0x158
    6ae6:	f8d4 3158 	ldr.w	r3, [r4, #344]	; 0x158
	return dev->config;
    6aea:	6843      	ldr	r3, [r0, #4]
	if (get_dev_config(dev)->flags & UARTE_CFG_FLAG_LOW_POWER) {
    6aec:	685b      	ldr	r3, [r3, #4]
    6aee:	f013 0f10 	tst.w	r3, #16
    6af2:	d102      	bne.n	6afa <tx_start+0x30>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6af4:	2301      	movs	r3, #1
    6af6:	60a3      	str	r3, [r4, #8]
}
    6af8:	bd10      	pop	{r4, pc}
		uarte_enable(dev, UARTE_LOW_POWER_TX);
    6afa:	2101      	movs	r1, #1
    6afc:	f7ff ffdf 	bl	6abe <uarte_enable>
    p_reg->INTENSET = mask;
    6b00:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
    6b04:	f8c4 3304 	str.w	r3, [r4, #772]	; 0x304
}
    6b08:	e7f4      	b.n	6af4 <tx_start+0x2a>

00006b0a <uarte_nrfx_poll_in>:
{
    6b0a:	b410      	push	{r4}
	return dev->data;
    6b0c:	6904      	ldr	r4, [r0, #16]
	return dev->config;
    6b0e:	6843      	ldr	r3, [r0, #4]
	return config->uarte_regs;
    6b10:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6b12:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    6b16:	b152      	cbz	r2, 6b2e <uarte_nrfx_poll_in+0x24>
	*c = data->rx_data;
    6b18:	7c62      	ldrb	r2, [r4, #17]
    6b1a:	700a      	strb	r2, [r1, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6b1c:	2000      	movs	r0, #0
    6b1e:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    6b22:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6b26:	2201      	movs	r2, #1
    6b28:	601a      	str	r2, [r3, #0]
}
    6b2a:	bc10      	pop	{r4}
    6b2c:	4770      	bx	lr
		return -1;
    6b2e:	f04f 30ff 	mov.w	r0, #4294967295
    6b32:	e7fa      	b.n	6b2a <uarte_nrfx_poll_in+0x20>

00006b34 <wait_tx_ready>:
{
    6b34:	b570      	push	{r4, r5, r6, lr}
    6b36:	4606      	mov	r6, r0
    6b38:	e014      	b.n	6b64 <wait_tx_ready+0x30>
		if (res) {
    6b3a:	b17d      	cbz	r5, 6b5c <wait_tx_ready+0x28>
	__asm__ volatile(
    6b3c:	f04f 0320 	mov.w	r3, #32
    6b40:	f3ef 8411 	mrs	r4, BASEPRI
    6b44:	f383 8812 	msr	BASEPRI_MAX, r3
    6b48:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    6b4c:	4630      	mov	r0, r6
    6b4e:	f7ff ffa2 	bl	6a96 <is_tx_ready>
    6b52:	b9a0      	cbnz	r0, 6b7e <wait_tx_ready+0x4a>
	__asm__ volatile(
    6b54:	f384 8811 	msr	BASEPRI, r4
    6b58:	f3bf 8f6f 	isb	sy
	return z_impl_k_sleep(timeout);
    6b5c:	2021      	movs	r0, #33	; 0x21
    6b5e:	2100      	movs	r1, #0
    6b60:	f7fe f87e 	bl	4c60 <z_impl_k_sleep>
		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    6b64:	2464      	movs	r4, #100	; 0x64
    6b66:	4630      	mov	r0, r6
    6b68:	f7ff ff95 	bl	6a96 <is_tx_ready>
    6b6c:	4605      	mov	r5, r0
    6b6e:	2800      	cmp	r0, #0
    6b70:	d1e3      	bne.n	6b3a <wait_tx_ready+0x6>
    6b72:	2001      	movs	r0, #1
    6b74:	f000 f89d 	bl	6cb2 <nrfx_busy_wait>
    6b78:	3c01      	subs	r4, #1
    6b7a:	d1f4      	bne.n	6b66 <wait_tx_ready+0x32>
    6b7c:	e7dd      	b.n	6b3a <wait_tx_ready+0x6>
}
    6b7e:	4620      	mov	r0, r4
    6b80:	bd70      	pop	{r4, r5, r6, pc}

00006b82 <uarte_0_init>:
				.tx_buffer = uarte##idx##_tx_buffer,	       \
				.tx_buff_size = sizeof(uarte##idx##_tx_buffer),\
			};))

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
    6b82:	b510      	push	{r4, lr}
    6b84:	4604      	mov	r4, r0
    6b86:	2200      	movs	r2, #0
    6b88:	2101      	movs	r1, #1
    6b8a:	2002      	movs	r0, #2
    6b8c:	f7fa fb52 	bl	1234 <z_arm_irq_priority_set>
    6b90:	2002      	movs	r0, #2
    6b92:	f7fa fb1d 	bl	11d0 <arch_irq_enable>
    6b96:	2100      	movs	r1, #0
    6b98:	4620      	mov	r0, r4
    6b9a:	f7fb ff6d 	bl	2a78 <uarte_instance_init>
    6b9e:	bd10      	pop	{r4, pc}

00006ba0 <uarte_1_init>:
#endif

#ifdef CONFIG_UART_1_NRF_UARTE
UART_NRF_UARTE_DEVICE(1);
    6ba0:	b510      	push	{r4, lr}
    6ba2:	4604      	mov	r4, r0
    6ba4:	2200      	movs	r2, #0
    6ba6:	2101      	movs	r1, #1
    6ba8:	2028      	movs	r0, #40	; 0x28
    6baa:	f7fa fb43 	bl	1234 <z_arm_irq_priority_set>
    6bae:	2028      	movs	r0, #40	; 0x28
    6bb0:	f7fa fb0e 	bl	11d0 <arch_irq_enable>
    6bb4:	2100      	movs	r1, #0
    6bb6:	4620      	mov	r0, r4
    6bb8:	f7fb ff5e 	bl	2a78 <uarte_instance_init>
    6bbc:	bd10      	pop	{r4, pc}

00006bbe <sys_clock_isr>:
/* Weak-linked noop defaults for optional driver interfaces*/

void __weak sys_clock_isr(void *arg)
{
	__ASSERT_NO_MSG(false);
}
    6bbe:	4770      	bx	lr

00006bc0 <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
    6bc0:	4770      	bx	lr

00006bc2 <counter_sub>:
	return (a - b) & COUNTER_MAX;
    6bc2:	1a40      	subs	r0, r0, r1
}
    6bc4:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
    6bc8:	4770      	bx	lr

00006bca <event_clear>:
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    6bca:	f100 0350 	add.w	r3, r0, #80	; 0x50
    6bce:	009b      	lsls	r3, r3, #2
    6bd0:	b29b      	uxth	r3, r3
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    6bd2:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    6bd6:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    6bda:	2200      	movs	r2, #0
    6bdc:	601a      	str	r2, [r3, #0]
    6bde:	681b      	ldr	r3, [r3, #0]
}
    6be0:	4770      	bx	lr

00006be2 <absolute_time_to_cc>:
}
    6be2:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
    6be6:	4770      	bx	lr

00006be8 <full_int_lock>:
	__asm__ volatile(
    6be8:	f04f 0320 	mov.w	r3, #32
    6bec:	f3ef 8011 	mrs	r0, BASEPRI
    6bf0:	f383 8812 	msr	BASEPRI_MAX, r3
    6bf4:	f3bf 8f6f 	isb	sy
}
    6bf8:	4770      	bx	lr

00006bfa <full_int_unlock>:
	__asm__ volatile(
    6bfa:	f380 8811 	msr	BASEPRI, r0
    6bfe:	f3bf 8f6f 	isb	sy
}
    6c02:	4770      	bx	lr

00006c04 <set_absolute_alarm>:
{
    6c04:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6c06:	4606      	mov	r6, r0
	uint32_t cc_val = abs_val & COUNTER_MAX;
    6c08:	f021 457f 	bic.w	r5, r1, #4278190080	; 0xff000000
	uint32_t prev_cc = get_comparator(chan);
    6c0c:	f7fb fffa 	bl	2c04 <get_comparator>
    6c10:	4607      	mov	r7, r0
    6c12:	e019      	b.n	6c48 <set_absolute_alarm+0x44>
	z_impl_k_busy_wait(usec_to_wait);
    6c14:	2013      	movs	r0, #19
    6c16:	f000 fb4c 	bl	72b2 <z_impl_k_busy_wait>
}
    6c1a:	e022      	b.n	6c62 <set_absolute_alarm+0x5e>
		event_clear(chan);
    6c1c:	4630      	mov	r0, r6
    6c1e:	f7ff ffd4 	bl	6bca <event_clear>
		event_enable(chan);
    6c22:	4630      	mov	r0, r6
    6c24:	f7fb fff6 	bl	2c14 <event_enable>
		set_comparator(chan, cc_val);
    6c28:	4629      	mov	r1, r5
    6c2a:	4630      	mov	r0, r6
    6c2c:	f7fb ffe0 	bl	2bf0 <set_comparator>
		now2 = counter();
    6c30:	f7fc f804 	bl	2c3c <counter>
		 (counter_sub(cc_val, now2 + 2) > COUNTER_HALF_SPAN));
    6c34:	4284      	cmp	r4, r0
    6c36:	d01e      	beq.n	6c76 <set_absolute_alarm+0x72>
    6c38:	1c81      	adds	r1, r0, #2
    6c3a:	4628      	mov	r0, r5
    6c3c:	f7ff ffc1 	bl	6bc2 <counter_sub>
	} while ((now2 != now) &&
    6c40:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    6c44:	d917      	bls.n	6c76 <set_absolute_alarm+0x72>
		prev_cc = cc_val;
    6c46:	462f      	mov	r7, r5
		now = counter();
    6c48:	f7fb fff8 	bl	2c3c <counter>
    6c4c:	4604      	mov	r4, r0
		set_comparator(chan, now);
    6c4e:	4601      	mov	r1, r0
    6c50:	4630      	mov	r0, r6
    6c52:	f7fb ffcd 	bl	2bf0 <set_comparator>
		if (counter_sub(prev_cc, now) == 1) {
    6c56:	4621      	mov	r1, r4
    6c58:	4638      	mov	r0, r7
    6c5a:	f7ff ffb2 	bl	6bc2 <counter_sub>
    6c5e:	2801      	cmp	r0, #1
    6c60:	d0d8      	beq.n	6c14 <set_absolute_alarm+0x10>
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    6c62:	1ca7      	adds	r7, r4, #2
    6c64:	4639      	mov	r1, r7
    6c66:	4628      	mov	r0, r5
    6c68:	f7ff ffab 	bl	6bc2 <counter_sub>
    6c6c:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    6c70:	d9d4      	bls.n	6c1c <set_absolute_alarm+0x18>
			cc_val = now + 2;
    6c72:	463d      	mov	r5, r7
    6c74:	e7d2      	b.n	6c1c <set_absolute_alarm+0x18>
}
    6c76:	4628      	mov	r0, r5
    6c78:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00006c7a <compare_set>:
{
    6c7a:	b5f0      	push	{r4, r5, r6, r7, lr}
    6c7c:	b083      	sub	sp, #12
    6c7e:	4604      	mov	r4, r0
    6c80:	4617      	mov	r7, r2
    6c82:	461d      	mov	r5, r3
	key = compare_int_lock(chan);
    6c84:	f7fb ffe0 	bl	2c48 <compare_int_lock>
    6c88:	4606      	mov	r6, r0
	int ret = compare_set_nolocks(chan, target_time, handler, user_data);
    6c8a:	9b09      	ldr	r3, [sp, #36]	; 0x24
    6c8c:	9301      	str	r3, [sp, #4]
    6c8e:	9b08      	ldr	r3, [sp, #32]
    6c90:	9300      	str	r3, [sp, #0]
    6c92:	463a      	mov	r2, r7
    6c94:	462b      	mov	r3, r5
    6c96:	4620      	mov	r0, r4
    6c98:	f7fc f8c4 	bl	2e24 <compare_set_nolocks>
    6c9c:	4605      	mov	r5, r0
	compare_int_unlock(chan, key);
    6c9e:	4631      	mov	r1, r6
    6ca0:	4620      	mov	r0, r4
    6ca2:	f7fc f835 	bl	2d10 <compare_int_unlock>
}
    6ca6:	4628      	mov	r0, r5
    6ca8:	b003      	add	sp, #12
    6caa:	bdf0      	pop	{r4, r5, r6, r7, pc}

00006cac <nrfx_isr>:

#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
    6cac:	b508      	push	{r3, lr}
	((nrfx_irq_handler_t)irq_handler)();
    6cae:	4780      	blx	r0
}
    6cb0:	bd08      	pop	{r3, pc}

00006cb2 <nrfx_busy_wait>:

void nrfx_busy_wait(uint32_t usec_to_wait)
{
    6cb2:	b508      	push	{r3, lr}
	z_impl_k_busy_wait(usec_to_wait);
    6cb4:	f000 fafd 	bl	72b2 <z_impl_k_busy_wait>
	k_busy_wait(usec_to_wait);
}
    6cb8:	bd08      	pop	{r3, pc}

00006cba <nrfx_clock_enable>:
{
    6cba:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    6cbc:	2000      	movs	r0, #0
    6cbe:	f7fa faab 	bl	1218 <arch_irq_is_enabled>
    6cc2:	b100      	cbz	r0, 6cc6 <nrfx_clock_enable+0xc>
}
    6cc4:	bd08      	pop	{r3, pc}
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    6cc6:	f7fa fa83 	bl	11d0 <arch_irq_enable>
    6cca:	e7fb      	b.n	6cc4 <nrfx_clock_enable+0xa>

00006ccc <is_app_channel>:
    return NRFX_GPIOTE_APP_CHANNELS_MASK & (1UL << index);
    6ccc:	2301      	movs	r3, #1
    6cce:	4083      	lsls	r3, r0
    6cd0:	f013 0fff 	tst.w	r3, #255	; 0xff
}
    6cd4:	bf14      	ite	ne
    6cd6:	2001      	movne	r0, #1
    6cd8:	2000      	moveq	r0, #0
    6cda:	4770      	bx	lr

00006cdc <transfer_byte>:
{
    6cdc:	b430      	push	{r4, r5}
    6cde:	b082      	sub	sp, #8
    return p_reg->RXD;
    6ce0:	f8d0 3518 	ldr.w	r3, [r0, #1304]	; 0x518
    6ce4:	b2db      	uxtb	r3, r3
    volatile uint8_t rx_data = nrf_spi_rxd_get(p_spi);
    6ce6:	f88d 3007 	strb.w	r3, [sp, #7]
    if (p_cb->bytes_transferred < p_cb->evt.xfer_desc.rx_length)
    6cea:	6a0b      	ldr	r3, [r1, #32]
    6cec:	698a      	ldr	r2, [r1, #24]
    6cee:	4293      	cmp	r3, r2
    6cf0:	d203      	bcs.n	6cfa <transfer_byte+0x1e>
        p_cb->evt.xfer_desc.p_rx_buffer[p_cb->bytes_transferred] = rx_data;
    6cf2:	694a      	ldr	r2, [r1, #20]
    6cf4:	f89d 4007 	ldrb.w	r4, [sp, #7]
    6cf8:	54d4      	strb	r4, [r2, r3]
    ++p_cb->bytes_transferred;
    6cfa:	6a0b      	ldr	r3, [r1, #32]
    6cfc:	3301      	adds	r3, #1
    6cfe:	620b      	str	r3, [r1, #32]
    size_t bytes_used = p_cb->bytes_transferred + 1;
    6d00:	1c5a      	adds	r2, r3, #1
    if (p_cb->abort)
    6d02:	f891 4024 	ldrb.w	r4, [r1, #36]	; 0x24
    6d06:	b13c      	cbz	r4, 6d18 <transfer_byte+0x3c>
        if (bytes_used < p_cb->evt.xfer_desc.tx_length)
    6d08:	690c      	ldr	r4, [r1, #16]
    6d0a:	4294      	cmp	r4, r2
    6d0c:	d900      	bls.n	6d10 <transfer_byte+0x34>
            p_cb->evt.xfer_desc.tx_length = bytes_used;
    6d0e:	610a      	str	r2, [r1, #16]
        if (bytes_used < p_cb->evt.xfer_desc.rx_length)
    6d10:	698c      	ldr	r4, [r1, #24]
    6d12:	4294      	cmp	r4, r2
    6d14:	d900      	bls.n	6d18 <transfer_byte+0x3c>
            p_cb->evt.xfer_desc.rx_length = bytes_used;
    6d16:	618a      	str	r2, [r1, #24]
    if (bytes_used < p_cb->evt.xfer_desc.tx_length)
    6d18:	690c      	ldr	r4, [r1, #16]
    6d1a:	4294      	cmp	r4, r2
    6d1c:	d808      	bhi.n	6d30 <transfer_byte+0x54>
    else if (bytes_used < p_cb->evt.xfer_desc.rx_length)
    6d1e:	698d      	ldr	r5, [r1, #24]
    6d20:	4295      	cmp	r5, r2
    6d22:	d80d      	bhi.n	6d40 <transfer_byte+0x64>
    return (p_cb->bytes_transferred < p_cb->evt.xfer_desc.tx_length ||
    6d24:	42a3      	cmp	r3, r4
    6d26:	d310      	bcc.n	6d4a <transfer_byte+0x6e>
    6d28:	42ab      	cmp	r3, r5
    6d2a:	d210      	bcs.n	6d4e <transfer_byte+0x72>
    6d2c:	2001      	movs	r0, #1
    6d2e:	e004      	b.n	6d3a <transfer_byte+0x5e>
        nrf_spi_txd_set(p_spi, p_cb->evt.xfer_desc.p_tx_buffer[bytes_used]);
    6d30:	68cb      	ldr	r3, [r1, #12]
    6d32:	5c9b      	ldrb	r3, [r3, r2]
    p_reg->TXD = data;
    6d34:	f8c0 351c 	str.w	r3, [r0, #1308]	; 0x51c
        return true;
    6d38:	2001      	movs	r0, #1
}
    6d3a:	b002      	add	sp, #8
    6d3c:	bc30      	pop	{r4, r5}
    6d3e:	4770      	bx	lr
        nrf_spi_txd_set(p_spi, p_cb->orc);
    6d40:	7fcb      	ldrb	r3, [r1, #31]
    6d42:	f8c0 351c 	str.w	r3, [r0, #1308]	; 0x51c
        return true;
    6d46:	2001      	movs	r0, #1
    6d48:	e7f7      	b.n	6d3a <transfer_byte+0x5e>
    return (p_cb->bytes_transferred < p_cb->evt.xfer_desc.tx_length ||
    6d4a:	2001      	movs	r0, #1
    6d4c:	e7f5      	b.n	6d3a <transfer_byte+0x5e>
    6d4e:	2000      	movs	r0, #0
    6d50:	e7f3      	b.n	6d3a <transfer_byte+0x5e>

00006d52 <irq_handler>:
{
    6d52:	b510      	push	{r4, lr}
    6d54:	460c      	mov	r4, r1
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6d56:	2200      	movs	r2, #0
    6d58:	f8c0 2108 	str.w	r2, [r0, #264]	; 0x108
    6d5c:	f8d0 3108 	ldr.w	r3, [r0, #264]	; 0x108
    if (!transfer_byte(p_spi, p_cb))
    6d60:	f7ff ffbc 	bl	6cdc <transfer_byte>
    6d64:	b100      	cbz	r0, 6d68 <irq_handler+0x16>
}
    6d66:	bd10      	pop	{r4, pc}
        finish_transfer(p_cb);
    6d68:	4620      	mov	r0, r4
    6d6a:	f7fc fc51 	bl	3610 <finish_transfer>
}
    6d6e:	e7fa      	b.n	6d66 <irq_handler+0x14>

00006d70 <spim_int_enable>:
    if (!enable)
    6d70:	b919      	cbnz	r1, 6d7a <spim_int_enable+0xa>
    p_reg->INTENCLR = mask;
    6d72:	2340      	movs	r3, #64	; 0x40
    6d74:	f8c0 3308 	str.w	r3, [r0, #776]	; 0x308
}
    6d78:	4770      	bx	lr
    p_reg->INTENSET = mask;
    6d7a:	2340      	movs	r3, #64	; 0x40
    6d7c:	f8c0 3304 	str.w	r3, [r0, #772]	; 0x304
}
    6d80:	4770      	bx	lr

00006d82 <spim_list_enable_handle>:
    if (NRFX_SPIM_FLAG_TX_POSTINC & flags)
    6d82:	f011 0f01 	tst.w	r1, #1
    6d86:	d009      	beq.n	6d9c <spim_list_enable_handle+0x1a>
}


NRF_STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)
{
    p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_ArrayList << SPIM_TXD_LIST_LIST_Pos;
    6d88:	2301      	movs	r3, #1
    6d8a:	f8c0 3550 	str.w	r3, [r0, #1360]	; 0x550
    if (NRFX_SPIM_FLAG_RX_POSTINC & flags)
    6d8e:	f011 0f02 	tst.w	r1, #2
    6d92:	d007      	beq.n	6da4 <spim_list_enable_handle+0x22>
    p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_Disabled << SPIM_TXD_LIST_LIST_Pos;
}

NRF_STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)
{
    p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_ArrayList << SPIM_RXD_LIST_LIST_Pos;
    6d94:	2301      	movs	r3, #1
    6d96:	f8c0 3540 	str.w	r3, [r0, #1344]	; 0x540
}
    6d9a:	4770      	bx	lr
    p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_Disabled << SPIM_TXD_LIST_LIST_Pos;
    6d9c:	2300      	movs	r3, #0
    6d9e:	f8c0 3550 	str.w	r3, [r0, #1360]	; 0x550
}
    6da2:	e7f4      	b.n	6d8e <spim_list_enable_handle+0xc>

NRF_STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)
{
    p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_Disabled << SPIM_RXD_LIST_LIST_Pos;
    6da4:	2300      	movs	r3, #0
    6da6:	f8c0 3540 	str.w	r3, [r0, #1344]	; 0x540
}
    6daa:	4770      	bx	lr

00006dac <irq_handler>:
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6dac:	f8d0 2118 	ldr.w	r2, [r0, #280]	; 0x118
    if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END))
    6db0:	b902      	cbnz	r2, 6db4 <irq_handler+0x8>
    6db2:	4770      	bx	lr
{
    6db4:	b508      	push	{r3, lr}
    6db6:	4603      	mov	r3, r0
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6db8:	2200      	movs	r2, #0
    6dba:	f8c0 2118 	str.w	r2, [r0, #280]	; 0x118
    6dbe:	f8d3 3118 	ldr.w	r3, [r3, #280]	; 0x118
        finish_transfer(p_cb);
    6dc2:	4608      	mov	r0, r1
    6dc4:	f7fc fe60 	bl	3a88 <finish_transfer>
}
    6dc8:	bd08      	pop	{r3, pc}

00006dca <spim_abort>:
{
    6dca:	b570      	push	{r4, r5, r6, lr}
    6dcc:	4605      	mov	r5, r0
    6dce:	460e      	mov	r6, r1
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6dd0:	2301      	movs	r3, #1
    6dd2:	6143      	str	r3, [r0, #20]
    NRFX_WAIT_FOR(nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED), 100, 1, stopped);
    6dd4:	2464      	movs	r4, #100	; 0x64
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6dd6:	f8d5 3104 	ldr.w	r3, [r5, #260]	; 0x104
    6dda:	b923      	cbnz	r3, 6de6 <spim_abort+0x1c>
    6ddc:	2001      	movs	r0, #1
    6dde:	f7ff ff68 	bl	6cb2 <nrfx_busy_wait>
    6de2:	3c01      	subs	r4, #1
    6de4:	d1f7      	bne.n	6dd6 <spim_abort+0xc>
    p_cb->transfer_in_progress = false;
    6de6:	2300      	movs	r3, #0
    6de8:	7773      	strb	r3, [r6, #29]
}
    6dea:	bd70      	pop	{r4, r5, r6, pc}

00006dec <SEGGER_RTT_Init>:
*  Function description
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
    6dec:	b508      	push	{r3, lr}
  _DoInit();
    6dee:	f7fd f91f 	bl	4030 <_DoInit>
}
    6df2:	bd08      	pop	{r3, pc}

00006df4 <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(const struct device *unused)
{
    6df4:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	SEGGER_RTT_Init();
    6df6:	f7ff fff9 	bl	6dec <SEGGER_RTT_Init>

	return 0;
}
    6dfa:	2000      	movs	r0, #0
    6dfc:	bd08      	pop	{r3, pc}

00006dfe <z_device_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    6dfe:	b148      	cbz	r0, 6e14 <z_device_ready+0x16>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    6e00:	68c3      	ldr	r3, [r0, #12]
    6e02:	8818      	ldrh	r0, [r3, #0]
    6e04:	f3c0 0008 	ubfx	r0, r0, #0, #9
    6e08:	f5b0 7f80 	cmp.w	r0, #256	; 0x100
    6e0c:	bf14      	ite	ne
    6e0e:	2000      	movne	r0, #0
    6e10:	2001      	moveq	r0, #1
    6e12:	4770      	bx	lr
		return false;
    6e14:	2000      	movs	r0, #0
}
    6e16:	4770      	bx	lr

00006e18 <arch_system_halt>:
	__asm__ volatile(
    6e18:	f04f 0220 	mov.w	r2, #32
    6e1c:	f3ef 8311 	mrs	r3, BASEPRI
    6e20:	f382 8812 	msr	BASEPRI_MAX, r2
    6e24:	f3bf 8f6f 	isb	sy
	/* TODO: What's the best way to totally halt the system if SMP
	 * is enabled?
	 */

	(void)arch_irq_lock();
	for (;;) {
    6e28:	e7fe      	b.n	6e28 <arch_system_halt+0x10>

00006e2a <k_sys_fatal_error_handler>:
/* LCOV_EXCL_STOP */

/* LCOV_EXCL_START */
__weak void k_sys_fatal_error_handler(unsigned int reason,
				      const z_arch_esf_t *esf)
{
    6e2a:	b508      	push	{r3, lr}
	ARG_UNUSED(esf);

	LOG_PANIC();
	LOG_ERR("Halting system");
	arch_system_halt(reason);
    6e2c:	f7ff fff4 	bl	6e18 <arch_system_halt>

00006e30 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    6e30:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6e32:	4605      	mov	r5, r0
    6e34:	460e      	mov	r6, r1
    6e36:	f04f 0320 	mov.w	r3, #32
    6e3a:	f3ef 8711 	mrs	r7, BASEPRI
    6e3e:	f383 8812 	msr	BASEPRI_MAX, r3
    6e42:	f3bf 8f6f 	isb	sy
	return z_impl_z_current_get();
    6e46:	f7fd ff37 	bl	4cb8 <z_impl_z_current_get>
    6e4a:	4604      	mov	r4, r0
	LOG_ERR("Current thread: %p (%s)", thread,
		log_strdup(thread_name_get(thread)));

	coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    6e4c:	4631      	mov	r1, r6
    6e4e:	4628      	mov	r0, r5
    6e50:	f7ff ffeb 	bl	6e2a <k_sys_fatal_error_handler>
	__asm__ volatile(
    6e54:	f387 8811 	msr	BASEPRI, r7
    6e58:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    6e5c:	4620      	mov	r0, r4
    6e5e:	f7fa fca9 	bl	17b4 <z_impl_k_thread_abort>
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    6e62:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00006e64 <setup_thread_stack>:
{
    6e64:	b410      	push	{r4}
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    6e66:	3207      	adds	r2, #7
    6e68:	f022 0207 	bic.w	r2, r2, #7
    6e6c:	f102 0320 	add.w	r3, r2, #32

/** @} */

static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym)
{
	return (char *)sym + K_KERNEL_STACK_RESERVED;
    6e70:	f101 0420 	add.w	r4, r1, #32
	new_thread->stack_info.start = (uintptr_t)stack_buf_start;
    6e74:	f8c0 409c 	str.w	r4, [r0, #156]	; 0x9c
	new_thread->stack_info.size = stack_buf_size;
    6e78:	f8c0 20a0 	str.w	r2, [r0, #160]	; 0xa0
	new_thread->stack_info.delta = delta;
    6e7c:	2200      	movs	r2, #0
    6e7e:	f8c0 20a4 	str.w	r2, [r0, #164]	; 0xa4
}
    6e82:	18c8      	adds	r0, r1, r3
    6e84:	bc10      	pop	{r4}
    6e86:	4770      	bx	lr

00006e88 <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    6e88:	f3ef 8005 	mrs	r0, IPSR
}
    6e8c:	3800      	subs	r0, #0
    6e8e:	bf18      	it	ne
    6e90:	2001      	movne	r0, #1
    6e92:	4770      	bx	lr

00006e94 <z_impl_k_thread_start>:
{
    6e94:	b508      	push	{r3, lr}
	z_sched_start(thread);
    6e96:	f7fd fd3d 	bl	4914 <z_sched_start>
}
    6e9a:	bd08      	pop	{r3, pc}

00006e9c <z_init_thread_base>:
#endif

void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
    6e9c:	b410      	push	{r4}
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
    6e9e:	2400      	movs	r4, #0
    6ea0:	6084      	str	r4, [r0, #8]
	thread_base->user_options = (uint8_t)options;
    6ea2:	7303      	strb	r3, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    6ea4:	7342      	strb	r2, [r0, #13]

	thread_base->prio = priority;
    6ea6:	7381      	strb	r1, [r0, #14]

	thread_base->sched_locked = 0U;
    6ea8:	73c4      	strb	r4, [r0, #15]
	node->next = NULL;
    6eaa:	6184      	str	r4, [r0, #24]
	node->prev = NULL;
    6eac:	61c4      	str	r4, [r0, #28]
#endif

	/* swap_data does not need to be initialized */

	z_init_thread_timeout(thread_base);
}
    6eae:	bc10      	pop	{r4}
    6eb0:	4770      	bx	lr

00006eb2 <z_impl_k_thread_create>:
{
    6eb2:	b5f0      	push	{r4, r5, r6, r7, lr}
    6eb4:	b087      	sub	sp, #28
    6eb6:	4604      	mov	r4, r0
    6eb8:	e9dd 6712 	ldrd	r6, r7, [sp, #72]	; 0x48
	z_setup_new_thread(new_thread, stack, stack_size, entry, p1, p2, p3,
    6ebc:	2500      	movs	r5, #0
    6ebe:	9505      	str	r5, [sp, #20]
    6ec0:	9d10      	ldr	r5, [sp, #64]	; 0x40
    6ec2:	9504      	str	r5, [sp, #16]
    6ec4:	9d0f      	ldr	r5, [sp, #60]	; 0x3c
    6ec6:	9503      	str	r5, [sp, #12]
    6ec8:	9d0e      	ldr	r5, [sp, #56]	; 0x38
    6eca:	9502      	str	r5, [sp, #8]
    6ecc:	9d0d      	ldr	r5, [sp, #52]	; 0x34
    6ece:	9501      	str	r5, [sp, #4]
    6ed0:	9d0c      	ldr	r5, [sp, #48]	; 0x30
    6ed2:	9500      	str	r5, [sp, #0]
    6ed4:	f7fd fa80 	bl	43d8 <z_setup_new_thread>
	if (!K_TIMEOUT_EQ(delay, K_FOREVER)) {
    6ed8:	f1b7 3fff 	cmp.w	r7, #4294967295
    6edc:	bf08      	it	eq
    6ede:	f1b6 3fff 	cmpeq.w	r6, #4294967295
    6ee2:	d102      	bne.n	6eea <z_impl_k_thread_create+0x38>
}
    6ee4:	4620      	mov	r0, r4
    6ee6:	b007      	add	sp, #28
    6ee8:	bdf0      	pop	{r4, r5, r6, r7, pc}
		schedule_new_thread(new_thread, delay);
    6eea:	4632      	mov	r2, r6
    6eec:	463b      	mov	r3, r7
    6eee:	4620      	mov	r0, r4
    6ef0:	f7fd fa60 	bl	43b4 <schedule_new_thread>
    6ef4:	e7f6      	b.n	6ee4 <z_impl_k_thread_create+0x32>

00006ef6 <z_pm_save_idle_exit>:

void z_pm_save_idle_exit(int32_t ticks)
{
    6ef6:	b508      	push	{r3, lr}
	/* Some CPU low power states require notification at the ISR
	 * to allow any operations that needs to be done before kernel
	 * switches task or processes nested interrupts.
	 * This can be simply ignored if not required.
	 */
	pm_system_resume();
    6ef8:	f7fa f8a8 	bl	104c <pm_system_resume>
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
    6efc:	f7ff fe60 	bl	6bc0 <sys_clock_idle_exit>
}
    6f00:	bd08      	pop	{r3, pc}

00006f02 <idle>:

void idle(void *unused1, void *unused2, void *unused3)
{
    6f02:	b508      	push	{r3, lr}
	__asm__ volatile(
    6f04:	f04f 0220 	mov.w	r2, #32
    6f08:	f3ef 8311 	mrs	r3, BASEPRI
    6f0c:	f382 8812 	msr	BASEPRI_MAX, r2
    6f10:	f3bf 8f6f 	isb	sy
		 * higher level construct.
		 */
		(void) arch_irq_lock();

		if (IS_ENABLED(CONFIG_PM)) {
			pm_save_idle();
    6f14:	f7fd fb12 	bl	453c <pm_save_idle>
    6f18:	e7f4      	b.n	6f04 <idle+0x2>

00006f1a <thread_active_elsewhere>:
}
    6f1a:	2000      	movs	r0, #0
    6f1c:	4770      	bx	lr

00006f1e <pended_on_thread>:
}
    6f1e:	6880      	ldr	r0, [r0, #8]
    6f20:	4770      	bx	lr

00006f22 <z_sched_prio_cmp>:
	int32_t b1 = thread_1->base.prio;
    6f22:	f990 300e 	ldrsb.w	r3, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    6f26:	f991 000e 	ldrsb.w	r0, [r1, #14]
	if (b1 != b2) {
    6f2a:	4283      	cmp	r3, r0
    6f2c:	d001      	beq.n	6f32 <z_sched_prio_cmp+0x10>
		return b2 - b1;
    6f2e:	1ac0      	subs	r0, r0, r3
    6f30:	4770      	bx	lr
	return 0;
    6f32:	2000      	movs	r0, #0
}
    6f34:	4770      	bx	lr

00006f36 <z_reschedule_irqlock>:
{
    6f36:	b508      	push	{r3, lr}
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    6f38:	4603      	mov	r3, r0
    6f3a:	b920      	cbnz	r0, 6f46 <z_reschedule_irqlock+0x10>
    6f3c:	f3ef 8205 	mrs	r2, IPSR
    6f40:	b942      	cbnz	r2, 6f54 <z_reschedule_irqlock+0x1e>
    6f42:	2201      	movs	r2, #1
    6f44:	e000      	b.n	6f48 <z_reschedule_irqlock+0x12>
    6f46:	2200      	movs	r2, #0
	if (resched(key)) {
    6f48:	b932      	cbnz	r2, 6f58 <z_reschedule_irqlock+0x22>
	__asm__ volatile(
    6f4a:	f383 8811 	msr	BASEPRI, r3
    6f4e:	f3bf 8f6f 	isb	sy
}
    6f52:	bd08      	pop	{r3, pc}
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    6f54:	2200      	movs	r2, #0
    6f56:	e7f7      	b.n	6f48 <z_reschedule_irqlock+0x12>
	ret = arch_swap(key);
    6f58:	4618      	mov	r0, r3
    6f5a:	f7fa f9a1 	bl	12a0 <arch_swap>
	return ret;
    6f5e:	e7f8      	b.n	6f52 <z_reschedule_irqlock+0x1c>

00006f60 <z_priq_dumb_remove>:
	sys_dnode_t *const prev = node->prev;
    6f60:	684a      	ldr	r2, [r1, #4]
	sys_dnode_t *const next = node->next;
    6f62:	680b      	ldr	r3, [r1, #0]
	prev->next = next;
    6f64:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    6f66:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    6f68:	2300      	movs	r3, #0
    6f6a:	600b      	str	r3, [r1, #0]
	node->prev = NULL;
    6f6c:	604b      	str	r3, [r1, #4]
}
    6f6e:	4770      	bx	lr

00006f70 <z_unpend_thread>:
{
    6f70:	b538      	push	{r3, r4, r5, lr}
    6f72:	4604      	mov	r4, r0
	LOCKED(&sched_spinlock) {
    6f74:	2300      	movs	r3, #0
	__asm__ volatile(
    6f76:	f04f 0220 	mov.w	r2, #32
    6f7a:	f3ef 8511 	mrs	r5, BASEPRI
    6f7e:	f382 8812 	msr	BASEPRI_MAX, r2
    6f82:	f3bf 8f6f 	isb	sy
    6f86:	b98b      	cbnz	r3, 6fac <z_unpend_thread+0x3c>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    6f88:	4620      	mov	r0, r4
    6f8a:	f7ff ffc8 	bl	6f1e <pended_on_thread>
    6f8e:	4621      	mov	r1, r4
    6f90:	f7ff ffe6 	bl	6f60 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    6f94:	7b63      	ldrb	r3, [r4, #13]
    6f96:	f023 0302 	bic.w	r3, r3, #2
    6f9a:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    6f9c:	2300      	movs	r3, #0
    6f9e:	60a3      	str	r3, [r4, #8]
	__asm__ volatile(
    6fa0:	f385 8811 	msr	BASEPRI, r5
    6fa4:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    6fa8:	2301      	movs	r3, #1
    6faa:	e7ec      	b.n	6f86 <z_unpend_thread+0x16>
	return z_abort_timeout(&thread->base.timeout);
    6fac:	f104 0018 	add.w	r0, r4, #24
    6fb0:	f000 f91c 	bl	71ec <z_abort_timeout>
}
    6fb4:	bd38      	pop	{r3, r4, r5, pc}

00006fb6 <z_priq_dumb_best>:
{
    6fb6:	4603      	mov	r3, r0
	return list->head == list;
    6fb8:	6800      	ldr	r0, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    6fba:	4283      	cmp	r3, r0
    6fbc:	d000      	beq.n	6fc0 <z_priq_dumb_best+0xa>
}
    6fbe:	4770      	bx	lr
	struct k_thread *thread = NULL;
    6fc0:	2000      	movs	r0, #0
	return thread;
    6fc2:	e7fc      	b.n	6fbe <z_priq_dumb_best+0x8>

00006fc4 <z_ready_thread>:
{
    6fc4:	b538      	push	{r3, r4, r5, lr}
    6fc6:	4604      	mov	r4, r0
	LOCKED(&sched_spinlock) {
    6fc8:	2300      	movs	r3, #0
	__asm__ volatile(
    6fca:	f04f 0220 	mov.w	r2, #32
    6fce:	f3ef 8511 	mrs	r5, BASEPRI
    6fd2:	f382 8812 	msr	BASEPRI_MAX, r2
    6fd6:	f3bf 8f6f 	isb	sy
    6fda:	e007      	b.n	6fec <z_ready_thread+0x28>
			ready_thread(thread);
    6fdc:	4620      	mov	r0, r4
    6fde:	f7fd fc59 	bl	4894 <ready_thread>
	__asm__ volatile(
    6fe2:	f385 8811 	msr	BASEPRI, r5
    6fe6:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    6fea:	2301      	movs	r3, #1
    6fec:	b92b      	cbnz	r3, 6ffa <z_ready_thread+0x36>
		if (!thread_active_elsewhere(thread)) {
    6fee:	4620      	mov	r0, r4
    6ff0:	f7ff ff93 	bl	6f1a <thread_active_elsewhere>
    6ff4:	2800      	cmp	r0, #0
    6ff6:	d1f4      	bne.n	6fe2 <z_ready_thread+0x1e>
    6ff8:	e7f0      	b.n	6fdc <z_ready_thread+0x18>
}
    6ffa:	bd38      	pop	{r3, r4, r5, pc}

00006ffc <z_thread_timeout>:
{
    6ffc:	b570      	push	{r4, r5, r6, lr}
    6ffe:	4604      	mov	r4, r0
	struct k_thread *thread = CONTAINER_OF(timeout,
    7000:	f1a0 0518 	sub.w	r5, r0, #24
	LOCKED(&sched_spinlock) {
    7004:	2300      	movs	r3, #0
	__asm__ volatile(
    7006:	f04f 0220 	mov.w	r2, #32
    700a:	f3ef 8611 	mrs	r6, BASEPRI
    700e:	f382 8812 	msr	BASEPRI_MAX, r2
    7012:	f3bf 8f6f 	isb	sy
    7016:	e019      	b.n	704c <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x4c>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    7018:	4628      	mov	r0, r5
    701a:	f7ff ff80 	bl	6f1e <pended_on_thread>
    701e:	4629      	mov	r1, r5
    7020:	f7ff ff9e 	bl	6f60 <z_priq_dumb_remove>
    7024:	7b6b      	ldrb	r3, [r5, #13]
    7026:	f023 0302 	bic.w	r3, r3, #2
    702a:	736b      	strb	r3, [r5, #13]
	thread->base.pended_on = NULL;
    702c:	2300      	movs	r3, #0
    702e:	60ab      	str	r3, [r5, #8]
	thread->base.thread_state &= ~_THREAD_PRESTART;
    7030:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    7034:	f003 03eb 	and.w	r3, r3, #235	; 0xeb
    7038:	f804 3c0b 	strb.w	r3, [r4, #-11]
			ready_thread(thread);
    703c:	4628      	mov	r0, r5
    703e:	f7fd fc29 	bl	4894 <ready_thread>
	__asm__ volatile(
    7042:	f386 8811 	msr	BASEPRI, r6
    7046:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    704a:	2301      	movs	r3, #1
    704c:	b94b      	cbnz	r3, 7062 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x62>
		bool killed = ((thread->base.thread_state & _THREAD_DEAD) ||
    704e:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
		if (!killed) {
    7052:	f013 0f28 	tst.w	r3, #40	; 0x28
    7056:	d1f4      	bne.n	7042 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x42>
			if (thread->base.pended_on != NULL) {
    7058:	f854 3c10 	ldr.w	r3, [r4, #-16]
    705c:	2b00      	cmp	r3, #0
    705e:	d1db      	bne.n	7018 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x18>
    7060:	e7e6      	b.n	7030 <CONFIG_PM_PARTITION_SIZE_B0_IMAGE+0x30>
}
    7062:	bd70      	pop	{r4, r5, r6, pc}

00007064 <add_to_waitq_locked>:
{
    7064:	b570      	push	{r4, r5, r6, lr}
    7066:	4605      	mov	r5, r0
    7068:	460e      	mov	r6, r1
	unready_thread(thread);
    706a:	f7fd fc71 	bl	4950 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    706e:	7b6b      	ldrb	r3, [r5, #13]
    7070:	f043 0302 	orr.w	r3, r3, #2
    7074:	736b      	strb	r3, [r5, #13]
	if (wait_q != NULL) {
    7076:	b1b6      	cbz	r6, 70a6 <add_to_waitq_locked+0x42>
		thread->base.pended_on = wait_q;
    7078:	60ae      	str	r6, [r5, #8]
	return list->head == list;
    707a:	6834      	ldr	r4, [r6, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    707c:	42a6      	cmp	r6, r4
    707e:	d019      	beq.n	70b4 <add_to_waitq_locked+0x50>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    7080:	b164      	cbz	r4, 709c <add_to_waitq_locked+0x38>
		if (z_sched_prio_cmp(thread, t) > 0) {
    7082:	4621      	mov	r1, r4
    7084:	4628      	mov	r0, r5
    7086:	f7ff ff4c 	bl	6f22 <z_sched_prio_cmp>
    708a:	2800      	cmp	r0, #0
    708c:	dc0c      	bgt.n	70a8 <add_to_waitq_locked+0x44>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    708e:	b12c      	cbz	r4, 709c <add_to_waitq_locked+0x38>
	return (node == list->tail) ? NULL : node->next;
    7090:	6873      	ldr	r3, [r6, #4]
    7092:	429c      	cmp	r4, r3
    7094:	d002      	beq.n	709c <add_to_waitq_locked+0x38>
    7096:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    7098:	2c00      	cmp	r4, #0
    709a:	d1f1      	bne.n	7080 <add_to_waitq_locked+0x1c>
	sys_dnode_t *const tail = list->tail;
    709c:	6873      	ldr	r3, [r6, #4]
	node->next = list;
    709e:	602e      	str	r6, [r5, #0]
	node->prev = tail;
    70a0:	606b      	str	r3, [r5, #4]
	tail->next = node;
    70a2:	601d      	str	r5, [r3, #0]
	list->tail = node;
    70a4:	6075      	str	r5, [r6, #4]
}
    70a6:	bd70      	pop	{r4, r5, r6, pc}
	sys_dnode_t *const prev = successor->prev;
    70a8:	6863      	ldr	r3, [r4, #4]
	node->prev = prev;
    70aa:	606b      	str	r3, [r5, #4]
	node->next = successor;
    70ac:	602c      	str	r4, [r5, #0]
	prev->next = node;
    70ae:	601d      	str	r5, [r3, #0]
	successor->prev = node;
    70b0:	6065      	str	r5, [r4, #4]
}
    70b2:	e7f8      	b.n	70a6 <add_to_waitq_locked+0x42>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    70b4:	2400      	movs	r4, #0
    70b6:	e7e3      	b.n	7080 <add_to_waitq_locked+0x1c>

000070b8 <pend>:
{
    70b8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    70bc:	4605      	mov	r5, r0
    70be:	460f      	mov	r7, r1
    70c0:	4691      	mov	r9, r2
    70c2:	4698      	mov	r8, r3
	LOCKED(&sched_spinlock) {
    70c4:	2400      	movs	r4, #0
	__asm__ volatile(
    70c6:	f04f 0320 	mov.w	r3, #32
    70ca:	f3ef 8611 	mrs	r6, BASEPRI
    70ce:	f383 8812 	msr	BASEPRI_MAX, r3
    70d2:	f3bf 8f6f 	isb	sy
    70d6:	b94c      	cbnz	r4, 70ec <pend+0x34>
		add_to_waitq_locked(thread, wait_q);
    70d8:	4639      	mov	r1, r7
    70da:	4628      	mov	r0, r5
    70dc:	f7ff ffc2 	bl	7064 <add_to_waitq_locked>
	__asm__ volatile(
    70e0:	f386 8811 	msr	BASEPRI, r6
    70e4:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    70e8:	2401      	movs	r4, #1
    70ea:	e7f4      	b.n	70d6 <pend+0x1e>
	add_thread_timeout(thread, timeout);
    70ec:	464a      	mov	r2, r9
    70ee:	4643      	mov	r3, r8
    70f0:	4628      	mov	r0, r5
    70f2:	f7fd fa83 	bl	45fc <add_thread_timeout>
}
    70f6:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

000070fa <z_unpend_first_thread>:
{
    70fa:	b570      	push	{r4, r5, r6, lr}
    70fc:	4606      	mov	r6, r0
	LOCKED(&sched_spinlock) {
    70fe:	2300      	movs	r3, #0
	__asm__ volatile(
    7100:	f04f 0220 	mov.w	r2, #32
    7104:	f3ef 8511 	mrs	r5, BASEPRI
    7108:	f382 8812 	msr	BASEPRI_MAX, r2
    710c:	f3bf 8f6f 	isb	sy
	struct k_thread *thread = NULL;
    7110:	461c      	mov	r4, r3
    7112:	e013      	b.n	713c <z_unpend_first_thread+0x42>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    7114:	f7ff ff03 	bl	6f1e <pended_on_thread>
    7118:	4621      	mov	r1, r4
    711a:	f7ff ff21 	bl	6f60 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    711e:	7b63      	ldrb	r3, [r4, #13]
    7120:	f023 0302 	bic.w	r3, r3, #2
    7124:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    7126:	2300      	movs	r3, #0
    7128:	60a3      	str	r3, [r4, #8]
    712a:	f104 0018 	add.w	r0, r4, #24
    712e:	f000 f85d 	bl	71ec <z_abort_timeout>
	__asm__ volatile(
    7132:	f385 8811 	msr	BASEPRI, r5
    7136:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    713a:	2301      	movs	r3, #1
    713c:	b933      	cbnz	r3, 714c <z_unpend_first_thread+0x52>
		thread = _priq_wait_best(&wait_q->waitq);
    713e:	4630      	mov	r0, r6
    7140:	f7ff ff39 	bl	6fb6 <z_priq_dumb_best>
		if (thread != NULL) {
    7144:	4604      	mov	r4, r0
    7146:	2800      	cmp	r0, #0
    7148:	d1e4      	bne.n	7114 <z_unpend_first_thread+0x1a>
    714a:	e7f2      	b.n	7132 <z_unpend_first_thread+0x38>
}
    714c:	4620      	mov	r0, r4
    714e:	bd70      	pop	{r4, r5, r6, pc}

00007150 <z_sched_wake>:
{
    7150:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    7154:	4606      	mov	r6, r0
    7156:	4688      	mov	r8, r1
    7158:	4617      	mov	r7, r2
	LOCKED(&sched_spinlock) {
    715a:	2300      	movs	r3, #0
	__asm__ volatile(
    715c:	f04f 0220 	mov.w	r2, #32
    7160:	f3ef 8511 	mrs	r5, BASEPRI
    7164:	f382 8812 	msr	BASEPRI_MAX, r2
    7168:	f3bf 8f6f 	isb	sy
	bool ret = false;
    716c:	4699      	mov	r9, r3
    716e:	e01b      	b.n	71a8 <z_sched_wake+0x58>
    7170:	f8c0 80b0 	str.w	r8, [r0, #176]	; 0xb0
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    7174:	6147      	str	r7, [r0, #20]
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    7176:	f7ff fed2 	bl	6f1e <pended_on_thread>
    717a:	4621      	mov	r1, r4
    717c:	f7ff fef0 	bl	6f60 <z_priq_dumb_remove>
    7180:	7b63      	ldrb	r3, [r4, #13]
    7182:	f023 0302 	bic.w	r3, r3, #2
    7186:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    7188:	2300      	movs	r3, #0
    718a:	60a3      	str	r3, [r4, #8]
    718c:	f104 0018 	add.w	r0, r4, #24
    7190:	f000 f82c 	bl	71ec <z_abort_timeout>
			ready_thread(thread);
    7194:	4620      	mov	r0, r4
    7196:	f7fd fb7d 	bl	4894 <ready_thread>
			ret = true;
    719a:	f04f 0901 	mov.w	r9, #1
	__asm__ volatile(
    719e:	f385 8811 	msr	BASEPRI, r5
    71a2:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    71a6:	2301      	movs	r3, #1
    71a8:	b933      	cbnz	r3, 71b8 <z_sched_wake+0x68>
		thread = _priq_wait_best(&wait_q->waitq);
    71aa:	4630      	mov	r0, r6
    71ac:	f7ff ff03 	bl	6fb6 <z_priq_dumb_best>
		if (thread != NULL) {
    71b0:	4604      	mov	r4, r0
    71b2:	2800      	cmp	r0, #0
    71b4:	d1dc      	bne.n	7170 <z_sched_wake+0x20>
    71b6:	e7f2      	b.n	719e <z_sched_wake+0x4e>
}
    71b8:	4648      	mov	r0, r9
    71ba:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

000071be <remove_timeout>:
{
    71be:	b538      	push	{r3, r4, r5, lr}
    71c0:	4604      	mov	r4, r0
	if (next(t) != NULL) {
    71c2:	f7fd fded 	bl	4da0 <next>
    71c6:	b148      	cbz	r0, 71dc <remove_timeout+0x1e>
    71c8:	4602      	mov	r2, r0
		next(t)->dticks += t->dticks;
    71ca:	6920      	ldr	r0, [r4, #16]
    71cc:	6965      	ldr	r5, [r4, #20]
    71ce:	6913      	ldr	r3, [r2, #16]
    71d0:	6951      	ldr	r1, [r2, #20]
    71d2:	181b      	adds	r3, r3, r0
    71d4:	eb45 0101 	adc.w	r1, r5, r1
    71d8:	6113      	str	r3, [r2, #16]
    71da:	6151      	str	r1, [r2, #20]
	sys_dnode_t *const prev = node->prev;
    71dc:	6862      	ldr	r2, [r4, #4]
	sys_dnode_t *const next = node->next;
    71de:	6823      	ldr	r3, [r4, #0]
	prev->next = next;
    71e0:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    71e2:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    71e4:	2300      	movs	r3, #0
    71e6:	6023      	str	r3, [r4, #0]
	node->prev = NULL;
    71e8:	6063      	str	r3, [r4, #4]
}
    71ea:	bd38      	pop	{r3, r4, r5, pc}

000071ec <z_abort_timeout>:
{
    71ec:	b570      	push	{r4, r5, r6, lr}
    71ee:	4604      	mov	r4, r0
	LOCKED(&timeout_lock) {
    71f0:	2300      	movs	r3, #0
	__asm__ volatile(
    71f2:	f04f 0220 	mov.w	r2, #32
    71f6:	f3ef 8611 	mrs	r6, BASEPRI
    71fa:	f382 8812 	msr	BASEPRI_MAX, r2
    71fe:	f3bf 8f6f 	isb	sy
	int ret = -EINVAL;
    7202:	f06f 0015 	mvn.w	r0, #21
    7206:	e008      	b.n	721a <z_abort_timeout+0x2e>
			remove_timeout(to);
    7208:	4620      	mov	r0, r4
    720a:	f7ff ffd8 	bl	71be <remove_timeout>
			ret = 0;
    720e:	4628      	mov	r0, r5
	__asm__ volatile(
    7210:	f386 8811 	msr	BASEPRI, r6
    7214:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    7218:	2301      	movs	r3, #1
    721a:	461d      	mov	r5, r3
    721c:	b91b      	cbnz	r3, 7226 <z_abort_timeout+0x3a>
	return node->next != NULL;
    721e:	6823      	ldr	r3, [r4, #0]
		if (sys_dnode_is_linked(&to->node)) {
    7220:	2b00      	cmp	r3, #0
    7222:	d1f1      	bne.n	7208 <z_abort_timeout+0x1c>
    7224:	e7f4      	b.n	7210 <z_abort_timeout+0x24>
}
    7226:	bd70      	pop	{r4, r5, r6, pc}

00007228 <z_get_next_timeout_expiry>:
{
    7228:	b510      	push	{r4, lr}
	LOCKED(&timeout_lock) {
    722a:	2300      	movs	r3, #0
	__asm__ volatile(
    722c:	f04f 0220 	mov.w	r2, #32
    7230:	f3ef 8411 	mrs	r4, BASEPRI
    7234:	f382 8812 	msr	BASEPRI_MAX, r2
    7238:	f3bf 8f6f 	isb	sy
	int32_t ret = (int32_t) K_TICKS_FOREVER;
    723c:	f04f 30ff 	mov.w	r0, #4294967295
	LOCKED(&timeout_lock) {
    7240:	b93b      	cbnz	r3, 7252 <z_get_next_timeout_expiry+0x2a>
		ret = next_timeout();
    7242:	f7fd fdc5 	bl	4dd0 <next_timeout>
	__asm__ volatile(
    7246:	f384 8811 	msr	BASEPRI, r4
    724a:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    724e:	2301      	movs	r3, #1
    7250:	e7f6      	b.n	7240 <z_get_next_timeout_expiry+0x18>
}
    7252:	bd10      	pop	{r4, pc}

00007254 <z_set_timeout_expiry>:
{
    7254:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    7256:	4606      	mov	r6, r0
    7258:	460f      	mov	r7, r1
	LOCKED(&timeout_lock) {
    725a:	2300      	movs	r3, #0
	__asm__ volatile(
    725c:	f04f 0220 	mov.w	r2, #32
    7260:	f3ef 8511 	mrs	r5, BASEPRI
    7264:	f382 8812 	msr	BASEPRI_MAX, r2
    7268:	f3bf 8f6f 	isb	sy
    726c:	e00a      	b.n	7284 <z_set_timeout_expiry+0x30>
			      || (ticks <= next_to);
    726e:	2401      	movs	r4, #1
		bool sooner = (next_to == K_TICKS_FOREVER)
    7270:	f004 0401 	and.w	r4, r4, #1
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
    7274:	2801      	cmp	r0, #1
    7276:	dd00      	ble.n	727a <z_set_timeout_expiry+0x26>
    7278:	b97c      	cbnz	r4, 729a <z_set_timeout_expiry+0x46>
	__asm__ volatile(
    727a:	f385 8811 	msr	BASEPRI, r5
    727e:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    7282:	2301      	movs	r3, #1
    7284:	461c      	mov	r4, r3
    7286:	b97b      	cbnz	r3, 72a8 <z_set_timeout_expiry+0x54>
		int next_to = next_timeout();
    7288:	f7fd fda2 	bl	4dd0 <next_timeout>
			      || (ticks <= next_to);
    728c:	f1b0 3fff 	cmp.w	r0, #4294967295
    7290:	d0ed      	beq.n	726e <z_set_timeout_expiry+0x1a>
    7292:	42b0      	cmp	r0, r6
    7294:	dbec      	blt.n	7270 <z_set_timeout_expiry+0x1c>
    7296:	2401      	movs	r4, #1
    7298:	e7ea      	b.n	7270 <z_set_timeout_expiry+0x1c>
			sys_clock_set_timeout(MIN(ticks, next_to), is_idle);
    729a:	4639      	mov	r1, r7
    729c:	42b0      	cmp	r0, r6
    729e:	bfa8      	it	ge
    72a0:	4630      	movge	r0, r6
    72a2:	f7fb febd 	bl	3020 <sys_clock_set_timeout>
    72a6:	e7e8      	b.n	727a <z_set_timeout_expiry+0x26>
}
    72a8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

000072aa <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
    72aa:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
    72ac:	f7fd fec2 	bl	5034 <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    72b0:	bd08      	pop	{r3, pc}

000072b2 <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    72b2:	b900      	cbnz	r0, 72b6 <z_impl_k_busy_wait+0x4>
    72b4:	4770      	bx	lr
{
    72b6:	b508      	push	{r3, lr}
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    72b8:	f7fa fb36 	bl	1928 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    72bc:	bd08      	pop	{r3, pc}

000072be <poller_thread>:
	return p ? CONTAINER_OF(p, struct k_thread, poller) : NULL;
    72be:	b108      	cbz	r0, 72c4 <poller_thread+0x6>
    72c0:	3860      	subs	r0, #96	; 0x60
    72c2:	4770      	bx	lr
}
    72c4:	4770      	bx	lr

000072c6 <signal_poller>:
{
    72c6:	b538      	push	{r3, r4, r5, lr}
    72c8:	460d      	mov	r5, r1
	struct k_thread *thread = poller_thread(event->poller);
    72ca:	6880      	ldr	r0, [r0, #8]
    72cc:	f7ff fff7 	bl	72be <poller_thread>
	return (thread->base.thread_state & _THREAD_PENDING) != 0U;
    72d0:	7b43      	ldrb	r3, [r0, #13]
	if (!z_is_thread_pending(thread)) {
    72d2:	f013 0f02 	tst.w	r3, #2
    72d6:	d028      	beq.n	732a <signal_poller+0x64>
    72d8:	4604      	mov	r4, r0
	return thread->base.timeout.dticks == _EXPIRED;
    72da:	e9d0 230a 	ldrd	r2, r3, [r0, #40]	; 0x28
	if (z_is_thread_timeout_expired(thread)) {
    72de:	f06f 0001 	mvn.w	r0, #1
    72e2:	f04f 31ff 	mov.w	r1, #4294967295
    72e6:	428b      	cmp	r3, r1
    72e8:	bf08      	it	eq
    72ea:	4282      	cmpeq	r2, r0
    72ec:	d01f      	beq.n	732e <signal_poller+0x68>
	z_unpend_thread(thread);
    72ee:	4620      	mov	r0, r4
    72f0:	f7ff fe3e 	bl	6f70 <z_unpend_thread>
	arch_thread_return_value_set(thread,
    72f4:	2d08      	cmp	r5, #8
    72f6:	d00a      	beq.n	730e <signal_poller+0x48>
    72f8:	2300      	movs	r3, #0
    72fa:	f8c4 30b0 	str.w	r3, [r4, #176]	; 0xb0
	uint8_t state = thread->base.thread_state;
    72fe:	7b63      	ldrb	r3, [r4, #13]
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    7300:	f013 0f1f 	tst.w	r3, #31
    7304:	d108      	bne.n	7318 <signal_poller+0x52>
    7306:	69a3      	ldr	r3, [r4, #24]
    7308:	b123      	cbz	r3, 7314 <signal_poller+0x4e>
    730a:	2300      	movs	r3, #0
    730c:	e005      	b.n	731a <signal_poller+0x54>
    730e:	f06f 0303 	mvn.w	r3, #3
    7312:	e7f2      	b.n	72fa <signal_poller+0x34>
    7314:	2301      	movs	r3, #1
    7316:	e000      	b.n	731a <signal_poller+0x54>
    7318:	2300      	movs	r3, #0
	if (!z_is_thread_ready(thread)) {
    731a:	b90b      	cbnz	r3, 7320 <signal_poller+0x5a>
		return 0;
    731c:	2000      	movs	r0, #0
    731e:	e005      	b.n	732c <signal_poller+0x66>
	z_ready_thread(thread);
    7320:	4620      	mov	r0, r4
    7322:	f7ff fe4f 	bl	6fc4 <z_ready_thread>
	return 0;
    7326:	2000      	movs	r0, #0
    7328:	e000      	b.n	732c <signal_poller+0x66>
		return 0;
    732a:	2000      	movs	r0, #0
}
    732c:	bd38      	pop	{r3, r4, r5, pc}
		return -EAGAIN;
    732e:	f06f 000a 	mvn.w	r0, #10
    7332:	e7fb      	b.n	732c <signal_poller+0x66>

00007334 <signal_triggered_work>:
	twork->poll_result = -EAGAIN;
	k_work_submit_to_queue(twork->workq, &twork->work);
}

static int signal_triggered_work(struct k_poll_event *event, uint32_t status)
{
    7334:	b570      	push	{r4, r5, r6, lr}
	struct z_poller *poller = event->poller;
    7336:	6884      	ldr	r4, [r0, #8]
	struct k_work_poll *twork =
		CONTAINER_OF(poller, struct k_work_poll, poller);

	if (poller->is_polling && twork->workq != NULL) {
    7338:	7823      	ldrb	r3, [r4, #0]
    733a:	b173      	cbz	r3, 735a <signal_triggered_work+0x26>
    733c:	f854 5c04 	ldr.w	r5, [r4, #-4]
    7340:	b15d      	cbz	r5, 735a <signal_triggered_work+0x26>
		struct k_work_q *work_q = twork->workq;

		z_abort_timeout(&twork->timeout);
    7342:	f1a4 0614 	sub.w	r6, r4, #20
    7346:	f104 0014 	add.w	r0, r4, #20
    734a:	f7ff ff4f 	bl	71ec <z_abort_timeout>
		twork->poll_result = 0;
    734e:	2300      	movs	r3, #0
    7350:	62e3      	str	r3, [r4, #44]	; 0x2c
		k_work_submit_to_queue(work_q, &twork->work);
    7352:	4631      	mov	r1, r6
    7354:	4628      	mov	r0, r5
    7356:	f000 f834 	bl	73c2 <k_work_submit_to_queue>
	}

	return 0;
}
    735a:	2000      	movs	r0, #0
    735c:	bd70      	pop	{r4, r5, r6, pc}

0000735e <signal_poll_event>:
{
    735e:	b570      	push	{r4, r5, r6, lr}
    7360:	4604      	mov	r4, r0
    7362:	460d      	mov	r5, r1
	struct z_poller *poller = event->poller;
    7364:	6886      	ldr	r6, [r0, #8]
	if (poller != NULL) {
    7366:	b1d6      	cbz	r6, 739e <signal_poll_event+0x40>
		if (poller->mode == MODE_POLL) {
    7368:	7873      	ldrb	r3, [r6, #1]
    736a:	2b01      	cmp	r3, #1
    736c:	d00d      	beq.n	738a <signal_poll_event+0x2c>
		} else if (poller->mode == MODE_TRIGGERED) {
    736e:	2b02      	cmp	r3, #2
    7370:	d012      	beq.n	7398 <signal_poll_event+0x3a>
		poller->is_polling = false;
    7372:	2000      	movs	r0, #0
    7374:	7030      	strb	r0, [r6, #0]
	event->poller = NULL;
    7376:	2300      	movs	r3, #0
    7378:	60a3      	str	r3, [r4, #8]
	event->state |= state;
    737a:	68e3      	ldr	r3, [r4, #12]
    737c:	f3c3 3145 	ubfx	r1, r3, #13, #6
    7380:	430d      	orrs	r5, r1
    7382:	f365 3352 	bfi	r3, r5, #13, #6
    7386:	60e3      	str	r3, [r4, #12]
}
    7388:	bd70      	pop	{r4, r5, r6, pc}
			retcode = signal_poller(event, state);
    738a:	f7ff ff9c 	bl	72c6 <signal_poller>
		poller->is_polling = false;
    738e:	2300      	movs	r3, #0
    7390:	7033      	strb	r3, [r6, #0]
		if (retcode < 0) {
    7392:	4298      	cmp	r0, r3
    7394:	daef      	bge.n	7376 <signal_poll_event+0x18>
    7396:	e7f7      	b.n	7388 <signal_poll_event+0x2a>
			retcode = signal_triggered_work(event, state);
    7398:	f7ff ffcc 	bl	7334 <signal_triggered_work>
    739c:	e7f7      	b.n	738e <signal_poll_event+0x30>
	int retcode = 0;
    739e:	2000      	movs	r0, #0
    73a0:	e7e9      	b.n	7376 <signal_poll_event+0x18>

000073a2 <z_handle_obj_poll_events>:
{
    73a2:	b508      	push	{r3, lr}
    73a4:	4603      	mov	r3, r0
	return list->head == list;
    73a6:	6800      	ldr	r0, [r0, #0]
	if (!sys_dlist_is_empty(list)) {
    73a8:	4283      	cmp	r3, r0
    73aa:	d009      	beq.n	73c0 <z_handle_obj_poll_events+0x1e>
	sys_dnode_t *const prev = node->prev;
    73ac:	6842      	ldr	r2, [r0, #4]
	sys_dnode_t *const next = node->next;
    73ae:	6803      	ldr	r3, [r0, #0]
	prev->next = next;
    73b0:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    73b2:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    73b4:	2300      	movs	r3, #0
    73b6:	6003      	str	r3, [r0, #0]
	node->prev = NULL;
    73b8:	6043      	str	r3, [r0, #4]
	if (poll_event != NULL) {
    73ba:	b108      	cbz	r0, 73c0 <z_handle_obj_poll_events+0x1e>
		(void) signal_poll_event(poll_event, state);
    73bc:	f7ff ffcf 	bl	735e <signal_poll_event>
}
    73c0:	bd08      	pop	{r3, pc}

000073c2 <k_work_submit_to_queue>:
{
    73c2:	b530      	push	{r4, r5, lr}
    73c4:	b083      	sub	sp, #12
    73c6:	9001      	str	r0, [sp, #4]
    73c8:	4608      	mov	r0, r1
	__asm__ volatile(
    73ca:	f04f 0320 	mov.w	r3, #32
    73ce:	f3ef 8511 	mrs	r5, BASEPRI
    73d2:	f383 8812 	msr	BASEPRI_MAX, r3
    73d6:	f3bf 8f6f 	isb	sy
	int ret = submit_to_queue_locked(work, &queue);
    73da:	a901      	add	r1, sp, #4
    73dc:	f7fe f93e 	bl	565c <submit_to_queue_locked>
    73e0:	4604      	mov	r4, r0
	__asm__ volatile(
    73e2:	f385 8811 	msr	BASEPRI, r5
    73e6:	f3bf 8f6f 	isb	sy
	if ((ret > 0) && (k_is_preempt_thread() != 0)) {
    73ea:	2800      	cmp	r0, #0
    73ec:	dc02      	bgt.n	73f4 <k_work_submit_to_queue+0x32>
}
    73ee:	4620      	mov	r0, r4
    73f0:	b003      	add	sp, #12
    73f2:	bd30      	pop	{r4, r5, pc}
	return z_impl_k_is_preempt_thread();
    73f4:	f7fd fc66 	bl	4cc4 <z_impl_k_is_preempt_thread>
	if ((ret > 0) && (k_is_preempt_thread() != 0)) {
    73f8:	2800      	cmp	r0, #0
    73fa:	d0f8      	beq.n	73ee <k_work_submit_to_queue+0x2c>
	z_impl_k_yield();
    73fc:	f7fd fb9c 	bl	4b38 <z_impl_k_yield>
	return ret;
    7400:	e7f5      	b.n	73ee <k_work_submit_to_queue+0x2c>

00007402 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    7402:	4770      	bx	lr

00007404 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    7404:	f7fb be94 	b.w	3130 <SystemInit>
