
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_start>:
#include <syscalls/z_errno_mrsh.c>

#else
int *z_impl_z_errno(void)
{
	return &_current->errno_var;
   0:	20000d58 	.word	0x20000d58
}
   4:	00001ba9 	.word	0x00001ba9
   8:	00004eb7 	.word	0x00004eb7
   c:	00001bfd 	.word	0x00001bfd
  10:	00001bfd 	.word	0x00001bfd
  14:	00001bfd 	.word	0x00001bfd
  18:	00001bfd 	.word	0x00001bfd
	...
  2c:	00001a05 	.word	0x00001a05
  30:	00001bfd 	.word	0x00001bfd
  34:	00000000 	.word	0x00000000
  38:	000019bd 	.word	0x000019bd
  3c:	00004dff 	.word	0x00004dff

00000040 <_irq_vector_table>:
  40:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...
  50:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...
  60:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...
  70:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...
  80:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...
  90:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...
  a0:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...
  b0:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...
  c0:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...
  d0:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...
  e0:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...
  f0:	00001b69 00001b69 00001b69 00001b69     i...i...i...i...

Disassembly of section text:

00000100 <__aeabi_uldivmod>:
     100:	b953      	cbnz	r3, 118 <__aeabi_uldivmod+0x18>
     102:	b94a      	cbnz	r2, 118 <__aeabi_uldivmod+0x18>
     104:	2900      	cmp	r1, #0
     106:	bf08      	it	eq
     108:	2800      	cmpeq	r0, #0
     10a:	bf1c      	itt	ne
     10c:	f04f 31ff 	movne.w	r1, #4294967295
     110:	f04f 30ff 	movne.w	r0, #4294967295
     114:	f000 b96c 	b.w	3f0 <__aeabi_idiv0>
     118:	f1ad 0c08 	sub.w	ip, sp, #8
     11c:	e96d ce04 	strd	ip, lr, [sp, #-16]!
     120:	f000 f806 	bl	130 <__udivmoddi4>
     124:	f8dd e004 	ldr.w	lr, [sp, #4]
     128:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     12c:	b004      	add	sp, #16
     12e:	4770      	bx	lr

00000130 <__udivmoddi4>:
     130:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     134:	9e08      	ldr	r6, [sp, #32]
     136:	460d      	mov	r5, r1
     138:	4604      	mov	r4, r0
     13a:	468e      	mov	lr, r1
     13c:	2b00      	cmp	r3, #0
     13e:	f040 8082 	bne.w	246 <CONFIG_FLASH_SIZE+0x46>
     142:	428a      	cmp	r2, r1
     144:	4617      	mov	r7, r2
     146:	d946      	bls.n	1d6 <CONFIG_IDLE_STACK_SIZE+0x96>
     148:	fab2 f282 	clz	r2, r2
     14c:	b14a      	cbz	r2, 162 <CONFIG_IDLE_STACK_SIZE+0x22>
     14e:	f1c2 0120 	rsb	r1, r2, #32
     152:	fa05 f302 	lsl.w	r3, r5, r2
     156:	fa20 f101 	lsr.w	r1, r0, r1
     15a:	4097      	lsls	r7, r2
     15c:	ea41 0e03 	orr.w	lr, r1, r3
     160:	4094      	lsls	r4, r2
     162:	ea4f 4817 	mov.w	r8, r7, lsr #16
     166:	0c23      	lsrs	r3, r4, #16
     168:	fbbe fcf8 	udiv	ip, lr, r8
     16c:	b2b9      	uxth	r1, r7
     16e:	fb08 ee1c 	mls	lr, r8, ip, lr
     172:	ea43 430e 	orr.w	r3, r3, lr, lsl #16
     176:	fb0c f001 	mul.w	r0, ip, r1
     17a:	4298      	cmp	r0, r3
     17c:	d90a      	bls.n	194 <CONFIG_IDLE_STACK_SIZE+0x54>
     17e:	18fb      	adds	r3, r7, r3
     180:	f10c 35ff 	add.w	r5, ip, #4294967295
     184:	f080 8116 	bcs.w	3b4 <CONFIG_FLASH_SIZE+0x1b4>
     188:	4298      	cmp	r0, r3
     18a:	f240 8113 	bls.w	3b4 <CONFIG_FLASH_SIZE+0x1b4>
     18e:	f1ac 0c02 	sub.w	ip, ip, #2
     192:	443b      	add	r3, r7
     194:	1a1b      	subs	r3, r3, r0
     196:	b2a4      	uxth	r4, r4
     198:	fbb3 f0f8 	udiv	r0, r3, r8
     19c:	fb08 3310 	mls	r3, r8, r0, r3
     1a0:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     1a4:	fb00 f101 	mul.w	r1, r0, r1
     1a8:	42a1      	cmp	r1, r4
     1aa:	d909      	bls.n	1c0 <CONFIG_IDLE_STACK_SIZE+0x80>
     1ac:	193c      	adds	r4, r7, r4
     1ae:	f100 33ff 	add.w	r3, r0, #4294967295
     1b2:	f080 8101 	bcs.w	3b8 <CONFIG_FLASH_SIZE+0x1b8>
     1b6:	42a1      	cmp	r1, r4
     1b8:	f240 80fe 	bls.w	3b8 <CONFIG_FLASH_SIZE+0x1b8>
     1bc:	3802      	subs	r0, #2
     1be:	443c      	add	r4, r7
     1c0:	1a64      	subs	r4, r4, r1
     1c2:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     1c6:	2100      	movs	r1, #0
     1c8:	b11e      	cbz	r6, 1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     1ca:	40d4      	lsrs	r4, r2
     1cc:	2300      	movs	r3, #0
     1ce:	e9c6 4300 	strd	r4, r3, [r6]
     1d2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     1d6:	b902      	cbnz	r2, 1da <CONFIG_IDLE_STACK_SIZE+0x9a>
     1d8:	deff      	udf	#255	; 0xff
     1da:	fab2 f282 	clz	r2, r2
     1de:	2a00      	cmp	r2, #0
     1e0:	d14f      	bne.n	282 <CONFIG_FLASH_SIZE+0x82>
     1e2:	1bcb      	subs	r3, r1, r7
     1e4:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     1e8:	fa1f f887 	uxth.w	r8, r7
     1ec:	2101      	movs	r1, #1
     1ee:	fbb3 fcfe 	udiv	ip, r3, lr
     1f2:	0c25      	lsrs	r5, r4, #16
     1f4:	fb0e 331c 	mls	r3, lr, ip, r3
     1f8:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     1fc:	fb08 f30c 	mul.w	r3, r8, ip
     200:	42ab      	cmp	r3, r5
     202:	d907      	bls.n	214 <CONFIG_FLASH_SIZE+0x14>
     204:	197d      	adds	r5, r7, r5
     206:	f10c 30ff 	add.w	r0, ip, #4294967295
     20a:	d202      	bcs.n	212 <CONFIG_FLASH_SIZE+0x12>
     20c:	42ab      	cmp	r3, r5
     20e:	f200 80e7 	bhi.w	3e0 <CONFIG_FLASH_SIZE+0x1e0>
     212:	4684      	mov	ip, r0
     214:	1aed      	subs	r5, r5, r3
     216:	b2a3      	uxth	r3, r4
     218:	fbb5 f0fe 	udiv	r0, r5, lr
     21c:	fb0e 5510 	mls	r5, lr, r0, r5
     220:	ea43 4405 	orr.w	r4, r3, r5, lsl #16
     224:	fb08 f800 	mul.w	r8, r8, r0
     228:	45a0      	cmp	r8, r4
     22a:	d907      	bls.n	23c <CONFIG_FLASH_SIZE+0x3c>
     22c:	193c      	adds	r4, r7, r4
     22e:	f100 33ff 	add.w	r3, r0, #4294967295
     232:	d202      	bcs.n	23a <CONFIG_FLASH_SIZE+0x3a>
     234:	45a0      	cmp	r8, r4
     236:	f200 80d7 	bhi.w	3e8 <CONFIG_FLASH_SIZE+0x1e8>
     23a:	4618      	mov	r0, r3
     23c:	eba4 0408 	sub.w	r4, r4, r8
     240:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     244:	e7c0      	b.n	1c8 <CONFIG_IDLE_STACK_SIZE+0x88>
     246:	428b      	cmp	r3, r1
     248:	d908      	bls.n	25c <CONFIG_FLASH_SIZE+0x5c>
     24a:	2e00      	cmp	r6, #0
     24c:	f000 80af 	beq.w	3ae <CONFIG_FLASH_SIZE+0x1ae>
     250:	2100      	movs	r1, #0
     252:	e9c6 0500 	strd	r0, r5, [r6]
     256:	4608      	mov	r0, r1
     258:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     25c:	fab3 f183 	clz	r1, r3
     260:	2900      	cmp	r1, #0
     262:	d14b      	bne.n	2fc <CONFIG_FLASH_SIZE+0xfc>
     264:	42ab      	cmp	r3, r5
     266:	d302      	bcc.n	26e <CONFIG_FLASH_SIZE+0x6e>
     268:	4282      	cmp	r2, r0
     26a:	f200 80b7 	bhi.w	3dc <CONFIG_FLASH_SIZE+0x1dc>
     26e:	1a84      	subs	r4, r0, r2
     270:	eb65 0303 	sbc.w	r3, r5, r3
     274:	2001      	movs	r0, #1
     276:	469e      	mov	lr, r3
     278:	2e00      	cmp	r6, #0
     27a:	d0aa      	beq.n	1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     27c:	e9c6 4e00 	strd	r4, lr, [r6]
     280:	e7a7      	b.n	1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     282:	f1c2 0c20 	rsb	ip, r2, #32
     286:	fa01 f302 	lsl.w	r3, r1, r2
     28a:	4097      	lsls	r7, r2
     28c:	fa20 f00c 	lsr.w	r0, r0, ip
     290:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     294:	fa21 fc0c 	lsr.w	ip, r1, ip
     298:	4318      	orrs	r0, r3
     29a:	fbbc f1fe 	udiv	r1, ip, lr
     29e:	0c05      	lsrs	r5, r0, #16
     2a0:	fb0e cc11 	mls	ip, lr, r1, ip
     2a4:	fa1f f887 	uxth.w	r8, r7
     2a8:	ea45 450c 	orr.w	r5, r5, ip, lsl #16
     2ac:	fb01 f308 	mul.w	r3, r1, r8
     2b0:	42ab      	cmp	r3, r5
     2b2:	fa04 f402 	lsl.w	r4, r4, r2
     2b6:	d909      	bls.n	2cc <CONFIG_FLASH_SIZE+0xcc>
     2b8:	197d      	adds	r5, r7, r5
     2ba:	f101 3cff 	add.w	ip, r1, #4294967295
     2be:	f080 808b 	bcs.w	3d8 <CONFIG_FLASH_SIZE+0x1d8>
     2c2:	42ab      	cmp	r3, r5
     2c4:	f240 8088 	bls.w	3d8 <CONFIG_FLASH_SIZE+0x1d8>
     2c8:	3902      	subs	r1, #2
     2ca:	443d      	add	r5, r7
     2cc:	1aeb      	subs	r3, r5, r3
     2ce:	b285      	uxth	r5, r0
     2d0:	fbb3 f0fe 	udiv	r0, r3, lr
     2d4:	fb0e 3310 	mls	r3, lr, r0, r3
     2d8:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     2dc:	fb00 f308 	mul.w	r3, r0, r8
     2e0:	42ab      	cmp	r3, r5
     2e2:	d907      	bls.n	2f4 <CONFIG_FLASH_SIZE+0xf4>
     2e4:	197d      	adds	r5, r7, r5
     2e6:	f100 3cff 	add.w	ip, r0, #4294967295
     2ea:	d271      	bcs.n	3d0 <CONFIG_FLASH_SIZE+0x1d0>
     2ec:	42ab      	cmp	r3, r5
     2ee:	d96f      	bls.n	3d0 <CONFIG_FLASH_SIZE+0x1d0>
     2f0:	3802      	subs	r0, #2
     2f2:	443d      	add	r5, r7
     2f4:	1aeb      	subs	r3, r5, r3
     2f6:	ea40 4101 	orr.w	r1, r0, r1, lsl #16
     2fa:	e778      	b.n	1ee <CONFIG_IDLE_STACK_SIZE+0xae>
     2fc:	f1c1 0c20 	rsb	ip, r1, #32
     300:	408b      	lsls	r3, r1
     302:	fa22 f70c 	lsr.w	r7, r2, ip
     306:	431f      	orrs	r7, r3
     308:	fa20 f40c 	lsr.w	r4, r0, ip
     30c:	fa05 f301 	lsl.w	r3, r5, r1
     310:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     314:	fa25 f50c 	lsr.w	r5, r5, ip
     318:	431c      	orrs	r4, r3
     31a:	0c23      	lsrs	r3, r4, #16
     31c:	fbb5 f9fe 	udiv	r9, r5, lr
     320:	fa1f f887 	uxth.w	r8, r7
     324:	fb0e 5519 	mls	r5, lr, r9, r5
     328:	ea43 4505 	orr.w	r5, r3, r5, lsl #16
     32c:	fb09 fa08 	mul.w	sl, r9, r8
     330:	45aa      	cmp	sl, r5
     332:	fa02 f201 	lsl.w	r2, r2, r1
     336:	fa00 f301 	lsl.w	r3, r0, r1
     33a:	d908      	bls.n	34e <CONFIG_FLASH_SIZE+0x14e>
     33c:	197d      	adds	r5, r7, r5
     33e:	f109 30ff 	add.w	r0, r9, #4294967295
     342:	d247      	bcs.n	3d4 <CONFIG_FLASH_SIZE+0x1d4>
     344:	45aa      	cmp	sl, r5
     346:	d945      	bls.n	3d4 <CONFIG_FLASH_SIZE+0x1d4>
     348:	f1a9 0902 	sub.w	r9, r9, #2
     34c:	443d      	add	r5, r7
     34e:	eba5 050a 	sub.w	r5, r5, sl
     352:	b2a4      	uxth	r4, r4
     354:	fbb5 f0fe 	udiv	r0, r5, lr
     358:	fb0e 5510 	mls	r5, lr, r0, r5
     35c:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
     360:	fb00 f808 	mul.w	r8, r0, r8
     364:	45a0      	cmp	r8, r4
     366:	d907      	bls.n	378 <CONFIG_FLASH_SIZE+0x178>
     368:	193c      	adds	r4, r7, r4
     36a:	f100 35ff 	add.w	r5, r0, #4294967295
     36e:	d22d      	bcs.n	3cc <CONFIG_FLASH_SIZE+0x1cc>
     370:	45a0      	cmp	r8, r4
     372:	d92b      	bls.n	3cc <CONFIG_FLASH_SIZE+0x1cc>
     374:	3802      	subs	r0, #2
     376:	443c      	add	r4, r7
     378:	ea40 4009 	orr.w	r0, r0, r9, lsl #16
     37c:	eba4 0408 	sub.w	r4, r4, r8
     380:	fba0 8902 	umull	r8, r9, r0, r2
     384:	454c      	cmp	r4, r9
     386:	46c6      	mov	lr, r8
     388:	464d      	mov	r5, r9
     38a:	d319      	bcc.n	3c0 <CONFIG_FLASH_SIZE+0x1c0>
     38c:	d016      	beq.n	3bc <CONFIG_FLASH_SIZE+0x1bc>
     38e:	b15e      	cbz	r6, 3a8 <CONFIG_FLASH_SIZE+0x1a8>
     390:	ebb3 020e 	subs.w	r2, r3, lr
     394:	eb64 0405 	sbc.w	r4, r4, r5
     398:	fa04 fc0c 	lsl.w	ip, r4, ip
     39c:	40ca      	lsrs	r2, r1
     39e:	ea4c 0202 	orr.w	r2, ip, r2
     3a2:	40cc      	lsrs	r4, r1
     3a4:	e9c6 2400 	strd	r2, r4, [r6]
     3a8:	2100      	movs	r1, #0
     3aa:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     3ae:	4631      	mov	r1, r6
     3b0:	4630      	mov	r0, r6
     3b2:	e70e      	b.n	1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     3b4:	46ac      	mov	ip, r5
     3b6:	e6ed      	b.n	194 <CONFIG_IDLE_STACK_SIZE+0x54>
     3b8:	4618      	mov	r0, r3
     3ba:	e701      	b.n	1c0 <CONFIG_IDLE_STACK_SIZE+0x80>
     3bc:	4543      	cmp	r3, r8
     3be:	d2e6      	bcs.n	38e <CONFIG_FLASH_SIZE+0x18e>
     3c0:	ebb8 0e02 	subs.w	lr, r8, r2
     3c4:	eb69 0507 	sbc.w	r5, r9, r7
     3c8:	3801      	subs	r0, #1
     3ca:	e7e0      	b.n	38e <CONFIG_FLASH_SIZE+0x18e>
     3cc:	4628      	mov	r0, r5
     3ce:	e7d3      	b.n	378 <CONFIG_FLASH_SIZE+0x178>
     3d0:	4660      	mov	r0, ip
     3d2:	e78f      	b.n	2f4 <CONFIG_FLASH_SIZE+0xf4>
     3d4:	4681      	mov	r9, r0
     3d6:	e7ba      	b.n	34e <CONFIG_FLASH_SIZE+0x14e>
     3d8:	4661      	mov	r1, ip
     3da:	e777      	b.n	2cc <CONFIG_FLASH_SIZE+0xcc>
     3dc:	4608      	mov	r0, r1
     3de:	e74b      	b.n	278 <CONFIG_FLASH_SIZE+0x78>
     3e0:	f1ac 0c02 	sub.w	ip, ip, #2
     3e4:	443d      	add	r5, r7
     3e6:	e715      	b.n	214 <CONFIG_FLASH_SIZE+0x14>
     3e8:	3802      	subs	r0, #2
     3ea:	443c      	add	r4, r7
     3ec:	e726      	b.n	23c <CONFIG_FLASH_SIZE+0x3c>
     3ee:	bf00      	nop

000003f0 <__aeabi_idiv0>:
     3f0:	4770      	bx	lr
     3f2:	bf00      	nop

000003f4 <strcmp>:
     3f4:	f810 2b01 	ldrb.w	r2, [r0], #1
     3f8:	f811 3b01 	ldrb.w	r3, [r1], #1
     3fc:	2a01      	cmp	r2, #1
     3fe:	bf28      	it	cs
     400:	429a      	cmpcs	r2, r3
     402:	d0f7      	beq.n	3f4 <strcmp>
     404:	1ad0      	subs	r0, r2, r3
     406:	4770      	bx	lr

00000408 <strlen>:
     408:	4603      	mov	r3, r0
     40a:	f813 2b01 	ldrb.w	r2, [r3], #1
     40e:	2a00      	cmp	r2, #0
     410:	d1fb      	bne.n	40a <strlen+0x2>
     412:	1a18      	subs	r0, r3, r0
     414:	3801      	subs	r0, #1
     416:	4770      	bx	lr

00000418 <main>:
#include <zephyr.h>
#include <sys/printk.h>
#include "my_class.h"

void main(void)
{
     418:	b510      	push	{r4, lr}
     41a:	b084      	sub	sp, #16
	printk("Hello World! %s\n", CONFIG_BOARD);
     41c:	4916      	ldr	r1, [pc, #88]	; (478 <main+0x60>)
     41e:	4817      	ldr	r0, [pc, #92]	; (47c <main+0x64>)
     420:	f004 fa51 	bl	48c6 <printk>

	MyClass myObject(5);
     424:	2105      	movs	r1, #5
     426:	4668      	mov	r0, sp
     428:	f004 fa00 	bl	482c <_ZN7MyClassC1Ei>
	MyClass* pObj = new MyClass(10);
     42c:	2010      	movs	r0, #16
     42e:	f005 f96a 	bl	5706 <_Znwj>
     432:	4604      	mov	r4, r0
     434:	b110      	cbz	r0, 43c <main+0x24>
     436:	210a      	movs	r1, #10
     438:	f004 f9f8 	bl	482c <_ZN7MyClassC1Ei>
	printk("Number is: %i\n", myObject.getNumber());
     43c:	4668      	mov	r0, sp
     43e:	f004 fa12 	bl	4866 <_ZN7MyClass9getNumberEv>
     442:	4601      	mov	r1, r0
     444:	480e      	ldr	r0, [pc, #56]	; (480 <main+0x68>)
     446:	f004 fa3e 	bl	48c6 <printk>
	myObject.addToNumber(5);
     44a:	2105      	movs	r1, #5
     44c:	4668      	mov	r0, sp
     44e:	f004 f9fa 	bl	4846 <_ZN7MyClass11addToNumberEi>
	printk("Number is now: %i\n", myObject.getNumber());
     452:	4668      	mov	r0, sp
     454:	f004 fa07 	bl	4866 <_ZN7MyClass9getNumberEv>
     458:	4601      	mov	r1, r0
     45a:	480a      	ldr	r0, [pc, #40]	; (484 <main+0x6c>)
     45c:	f004 fa33 	bl	48c6 <printk>
	delete pObj;
     460:	b12c      	cbz	r4, 46e <main+0x56>
     462:	4620      	mov	r0, r4
     464:	f004 fa01 	bl	486a <_ZN7MyClassD1Ev>
     468:	4620      	mov	r0, r4
     46a:	f005 f94a 	bl	5702 <_ZdlPv>
	MyClass myObject(5);
     46e:	4668      	mov	r0, sp
     470:	f004 f9fb 	bl	486a <_ZN7MyClassD1Ev>
}
     474:	b004      	add	sp, #16
     476:	bd10      	pop	{r4, pc}
     478:	00005a98 	.word	0x00005a98
     47c:	00005aa4 	.word	0x00005aa4
     480:	00005ab8 	.word	0x00005ab8
     484:	00005ac8 	.word	0x00005ac8

00000488 <char_out>:
struct out_context {
	int count;
};

static int char_out(int c, void *ctx_p)
{
     488:	b508      	push	{r3, lr}
	struct out_context *ctx = ctx_p;

	ctx->count++;
     48a:	680b      	ldr	r3, [r1, #0]
     48c:	3301      	adds	r3, #1
     48e:	600b      	str	r3, [r1, #0]
	return _char_out(c);
     490:	4b01      	ldr	r3, [pc, #4]	; (498 <char_out+0x10>)
     492:	681b      	ldr	r3, [r3, #0]
     494:	4798      	blx	r3
}
     496:	bd08      	pop	{r3, pc}
     498:	20000000 	.word	0x20000000

0000049c <__printk_hook_install>:
	_char_out = fn;
     49c:	4b01      	ldr	r3, [pc, #4]	; (4a4 <__printk_hook_install+0x8>)
     49e:	6018      	str	r0, [r3, #0]
}
     4a0:	4770      	bx	lr
     4a2:	bf00      	nop
     4a4:	20000000 	.word	0x20000000

000004a8 <vprintk>:
#endif
	}
}
#else
void vprintk(const char *fmt, va_list ap)
{
     4a8:	b500      	push	{lr}
     4aa:	b083      	sub	sp, #12
     4ac:	4602      	mov	r2, r0
     4ae:	460b      	mov	r3, r1
	struct out_context ctx = { 0 };
     4b0:	2100      	movs	r1, #0
     4b2:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
	k_spinlock_key_t key = k_spin_lock(&lock);
#endif

	cbvprintf(char_out, &ctx, fmt, ap);
     4b4:	a901      	add	r1, sp, #4
     4b6:	4803      	ldr	r0, [pc, #12]	; (4c4 <vprintk+0x1c>)
     4b8:	f000 f938 	bl	72c <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
	k_spin_unlock(&lock, key);
#endif
}
     4bc:	b003      	add	sp, #12
     4be:	f85d fb04 	ldr.w	pc, [sp], #4
     4c2:	bf00      	nop
     4c4:	00000489 	.word	0x00000489

000004c8 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     4c8:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
     4cc:	b083      	sub	sp, #12
     4ce:	4604      	mov	r4, r0
     4d0:	4608      	mov	r0, r1
     4d2:	4615      	mov	r5, r2
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     4d4:	8ba3      	ldrh	r3, [r4, #28]
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     4d6:	f013 0f08 	tst.w	r3, #8
     4da:	d105      	bne.n	4e8 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE>
     4dc:	f003 0607 	and.w	r6, r3, #7
 *
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
     4e0:	2300      	movs	r3, #0
     4e2:	9300      	str	r3, [sp, #0]
	list->tail = NULL;
     4e4:	9301      	str	r3, [sp, #4]
}
     4e6:	e069      	b.n	5bc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xd4>
		if (evt == EVT_COMPLETE) {
     4e8:	2901      	cmp	r1, #1
     4ea:	d009      	beq.n	500 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x18>
			mgr->flags |= ONOFF_FLAG_COMPLETE;
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
     4ec:	f043 0320 	orr.w	r3, r3, #32
     4f0:	83a3      	strh	r3, [r4, #28]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     4f2:	f385 8811 	msr	BASEPRI, r5
     4f6:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     4fa:	b003      	add	sp, #12
     4fc:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     500:	f043 0310 	orr.w	r3, r3, #16
     504:	83a3      	strh	r3, [r4, #28]
     506:	e7f4      	b.n	4f2 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa>
			evt = process_recheck(mgr);
     508:	4620      	mov	r0, r4
     50a:	f004 fa11 	bl	4930 <process_recheck>
     50e:	e057      	b.n	5c0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xd8>
			res = mgr->last_res;
     510:	f8d4 9018 	ldr.w	r9, [r4, #24]
			process_complete(mgr, &clients, res);
     514:	464a      	mov	r2, r9
     516:	4669      	mov	r1, sp
     518:	4620      	mov	r0, r4
     51a:	f004 fa22 	bl	4962 <process_complete>
		onoff_transition_fn transit = NULL;
     51e:	2700      	movs	r7, #0
     520:	e05a      	b.n	5d8 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xf0>
			transit = mgr->transitions->start;
     522:	6923      	ldr	r3, [r4, #16]
     524:	681f      	ldr	r7, [r3, #0]
			set_state(mgr, ONOFF_STATE_TO_ON);
     526:	2106      	movs	r1, #6
     528:	4620      	mov	r0, r4
     52a:	f004 f9da 	bl	48e2 <set_state>
		res = 0;
     52e:	f04f 0900 	mov.w	r9, #0
     532:	e051      	b.n	5d8 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xf0>
			transit = mgr->transitions->stop;
     534:	6923      	ldr	r3, [r4, #16]
     536:	685f      	ldr	r7, [r3, #4]
			set_state(mgr, ONOFF_STATE_TO_OFF);
     538:	2104      	movs	r1, #4
     53a:	4620      	mov	r0, r4
     53c:	f004 f9d1 	bl	48e2 <set_state>
		res = 0;
     540:	f04f 0900 	mov.w	r9, #0
     544:	e048      	b.n	5d8 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xf0>
			transit = mgr->transitions->reset;
     546:	6923      	ldr	r3, [r4, #16]
     548:	689f      	ldr	r7, [r3, #8]
			set_state(mgr, ONOFF_STATE_RESETTING);
     54a:	2105      	movs	r1, #5
     54c:	4620      	mov	r0, r4
     54e:	f004 f9c8 	bl	48e2 <set_state>
		res = 0;
     552:	f04f 0900 	mov.w	r9, #0
     556:	e03f      	b.n	5d8 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xf0>
				   && !sys_slist_is_empty(&mgr->monitors);
     558:	2200      	movs	r2, #0
     55a:	e046      	b.n	5ea <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x102>
     55c:	2200      	movs	r2, #0
     55e:	e044      	b.n	5ea <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x102>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     560:	f043 0308 	orr.w	r3, r3, #8
			mgr->flags = flags;
     564:	83a3      	strh	r3, [r4, #28]
     566:	f385 8811 	msr	BASEPRI, r5
     56a:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
     56e:	2900      	cmp	r1, #0
     570:	d144      	bne.n	5fc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x114>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     572:	9b00      	ldr	r3, [sp, #0]
			if (!sys_slist_is_empty(&clients)) {
     574:	b12b      	cbz	r3, 582 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x9a>
				notify_all(mgr, &clients, state, res);
     576:	464b      	mov	r3, r9
     578:	4642      	mov	r2, r8
     57a:	4669      	mov	r1, sp
     57c:	4620      	mov	r0, r4
     57e:	f004 fa66 	bl	4a4e <notify_all>
			if (transit != NULL) {
     582:	b117      	cbz	r7, 58a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa2>
				transit(mgr, transition_complete);
     584:	4925      	ldr	r1, [pc, #148]	; (61c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x134>)
     586:	4620      	mov	r0, r4
     588:	47b8      	blx	r7
	__asm__ volatile(
     58a:	f04f 0320 	mov.w	r3, #32
     58e:	f3ef 8511 	mrs	r5, BASEPRI
     592:	f383 8811 	msr	BASEPRI, r3
     596:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     59a:	8ba3      	ldrh	r3, [r4, #28]
     59c:	f023 0308 	bic.w	r3, r3, #8
     5a0:	83a3      	strh	r3, [r4, #28]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     5a2:	8ba3      	ldrh	r3, [r4, #28]
     5a4:	f013 0f10 	tst.w	r3, #16
     5a8:	d02e      	beq.n	608 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x120>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     5aa:	f023 0310 	bic.w	r3, r3, #16
     5ae:	83a3      	strh	r3, [r4, #28]
			evt = EVT_COMPLETE;
     5b0:	2001      	movs	r0, #1
		state = mgr->flags & ONOFF_STATE_MASK;
     5b2:	8ba6      	ldrh	r6, [r4, #28]
     5b4:	f006 0607 	and.w	r6, r6, #7
	} while (evt != EVT_NOP);
     5b8:	2800      	cmp	r0, #0
     5ba:	d09a      	beq.n	4f2 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa>
		if (evt == EVT_RECHECK) {
     5bc:	2802      	cmp	r0, #2
     5be:	d0a3      	beq.n	508 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x20>
		if (evt == EVT_NOP) {
     5c0:	2800      	cmp	r0, #0
     5c2:	d096      	beq.n	4f2 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa>
		if (evt == EVT_COMPLETE) {
     5c4:	2801      	cmp	r0, #1
     5c6:	d0a3      	beq.n	510 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x28>
		} else if (evt == EVT_START) {
     5c8:	2803      	cmp	r0, #3
     5ca:	d0aa      	beq.n	522 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x3a>
		} else if (evt == EVT_STOP) {
     5cc:	2804      	cmp	r0, #4
     5ce:	d0b1      	beq.n	534 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x4c>
		} else if (evt == EVT_RESET) {
     5d0:	2805      	cmp	r0, #5
     5d2:	d0b8      	beq.n	546 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x5e>
		onoff_transition_fn transit = NULL;
     5d4:	2700      	movs	r7, #0
		res = 0;
     5d6:	46b9      	mov	r9, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     5d8:	8ba3      	ldrh	r3, [r4, #28]
     5da:	f003 0807 	and.w	r8, r3, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     5de:	45b0      	cmp	r8, r6
     5e0:	d0ba      	beq.n	558 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x70>
     5e2:	68a2      	ldr	r2, [r4, #8]
     5e4:	2a00      	cmp	r2, #0
     5e6:	d0b9      	beq.n	55c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x74>
     5e8:	2201      	movs	r2, #1
		if (do_monitors
     5ea:	4611      	mov	r1, r2
     5ec:	2a00      	cmp	r2, #0
     5ee:	d1b7      	bne.n	560 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x78>
     5f0:	9a00      	ldr	r2, [sp, #0]
		    || !sys_slist_is_empty(&clients)
     5f2:	2a00      	cmp	r2, #0
     5f4:	d1b4      	bne.n	560 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x78>
		    || (transit != NULL)) {
     5f6:	2f00      	cmp	r7, #0
     5f8:	d1b2      	bne.n	560 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x78>
     5fa:	e7d2      	b.n	5a2 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xba>
				notify_monitors(mgr, state, res);
     5fc:	464a      	mov	r2, r9
     5fe:	4641      	mov	r1, r8
     600:	4620      	mov	r0, r4
     602:	f004 f976 	bl	48f2 <notify_monitors>
     606:	e7b4      	b.n	572 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x8a>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     608:	f013 0f20 	tst.w	r3, #32
     60c:	d004      	beq.n	618 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x130>
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     60e:	f023 0320 	bic.w	r3, r3, #32
     612:	83a3      	strh	r3, [r4, #28]
			evt = EVT_RECHECK;
     614:	2002      	movs	r0, #2
     616:	e7cc      	b.n	5b2 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xca>
		evt = EVT_NOP;
     618:	2000      	movs	r0, #0
     61a:	e7ca      	b.n	5b2 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xca>
     61c:	00004a7d 	.word	0x00004a7d

00000620 <extract_decimal>:
 * the referenced text.
 *
 * @return the decoded integer value.
 */
static size_t extract_decimal(const char **str)
{
     620:	b410      	push	{r4}
     622:	4604      	mov	r4, r0
	const char *sp = *str;
     624:	6802      	ldr	r2, [r0, #0]
	size_t val = 0;
     626:	2000      	movs	r0, #0

	while (isdigit((int)(unsigned char)*sp)) {
     628:	7813      	ldrb	r3, [r2, #0]
     62a:	4907      	ldr	r1, [pc, #28]	; (648 <extract_decimal+0x28>)
     62c:	5c59      	ldrb	r1, [r3, r1]
     62e:	f011 0f04 	tst.w	r1, #4
     632:	d006      	beq.n	642 <extract_decimal+0x22>
		val = 10U * val + *sp++ - '0';
     634:	eb00 0080 	add.w	r0, r0, r0, lsl #2
     638:	3201      	adds	r2, #1
     63a:	eb03 0040 	add.w	r0, r3, r0, lsl #1
     63e:	3830      	subs	r0, #48	; 0x30
     640:	e7f2      	b.n	628 <extract_decimal+0x8>
	}
	*str = sp;
     642:	6022      	str	r2, [r4, #0]
	return val;
}
     644:	bc10      	pop	{r4}
     646:	4770      	bx	lr
     648:	00005c6a 	.word	0x00005c6a

0000064c <encode_uint>:
 */
static char *encode_uint(uint_value_type value,
			 struct conversion *conv,
			 char *bps,
			 const char *bpe)
{
     64c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     650:	b083      	sub	sp, #12
     652:	4604      	mov	r4, r0
     654:	460d      	mov	r5, r1
     656:	9201      	str	r2, [sp, #4]
     658:	469a      	mov	sl, r3
     65a:	f8dd 8030 	ldr.w	r8, [sp, #48]	; 0x30
	bool upcase = isupper((int)conv->specifier);
     65e:	78d3      	ldrb	r3, [r2, #3]
     660:	4a31      	ldr	r2, [pc, #196]	; (728 <encode_uint+0xdc>)
     662:	f813 b002 	ldrb.w	fp, [r3, r2]
     666:	f00b 0b03 	and.w	fp, fp, #3
	switch (specifier) {
     66a:	2b6f      	cmp	r3, #111	; 0x6f
     66c:	d00f      	beq.n	68e <encode_uint+0x42>
     66e:	d906      	bls.n	67e <encode_uint+0x32>
     670:	2b70      	cmp	r3, #112	; 0x70
     672:	d00f      	beq.n	694 <encode_uint+0x48>
     674:	2b78      	cmp	r3, #120	; 0x78
     676:	d110      	bne.n	69a <encode_uint+0x4e>
		return 16;
     678:	f04f 0910 	mov.w	r9, #16
     67c:	e023      	b.n	6c6 <encode_uint+0x7a>
	switch (specifier) {
     67e:	2b58      	cmp	r3, #88	; 0x58
     680:	d002      	beq.n	688 <encode_uint+0x3c>
     682:	f04f 090a 	mov.w	r9, #10
     686:	e01e      	b.n	6c6 <encode_uint+0x7a>
		return 16;
     688:	f04f 0910 	mov.w	r9, #16
     68c:	e01b      	b.n	6c6 <encode_uint+0x7a>
		return 8;
     68e:	f04f 0908 	mov.w	r9, #8
     692:	e018      	b.n	6c6 <encode_uint+0x7a>
		return 16;
     694:	f04f 0910 	mov.w	r9, #16
     698:	e015      	b.n	6c6 <encode_uint+0x7a>
	switch (specifier) {
     69a:	f04f 090a 	mov.w	r9, #10
	const unsigned int radix = conversion_radix(conv->specifier);
	char *bp = bps + (bpe - bps);
     69e:	e012      	b.n	6c6 <encode_uint+0x7a>

	do {
		unsigned int lsv = (unsigned int)(value % radix);

		*--bp = (lsv <= 9) ? ('0' + lsv)
     6a0:	b2d2      	uxtb	r2, r2
     6a2:	3230      	adds	r2, #48	; 0x30
     6a4:	b2d2      	uxtb	r2, r2
     6a6:	f808 2d01 	strb.w	r2, [r8, #-1]!
			: upcase ? ('A' + lsv - 10) : ('a' + lsv - 10);
		value /= radix;
     6aa:	4632      	mov	r2, r6
     6ac:	463b      	mov	r3, r7
     6ae:	4620      	mov	r0, r4
     6b0:	4629      	mov	r1, r5
     6b2:	f7ff fd25 	bl	100 <__aeabi_uldivmod>
	} while ((value != 0) && (bps < bp));
     6b6:	42bd      	cmp	r5, r7
     6b8:	bf08      	it	eq
     6ba:	42b4      	cmpeq	r4, r6
     6bc:	d318      	bcc.n	6f0 <encode_uint+0xa4>
     6be:	45d0      	cmp	r8, sl
     6c0:	d916      	bls.n	6f0 <encode_uint+0xa4>
		value /= radix;
     6c2:	4604      	mov	r4, r0
     6c4:	460d      	mov	r5, r1
		unsigned int lsv = (unsigned int)(value % radix);
     6c6:	464e      	mov	r6, r9
     6c8:	2700      	movs	r7, #0
     6ca:	464a      	mov	r2, r9
     6cc:	463b      	mov	r3, r7
     6ce:	4620      	mov	r0, r4
     6d0:	4629      	mov	r1, r5
     6d2:	f7ff fd15 	bl	100 <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
     6d6:	2a09      	cmp	r2, #9
     6d8:	d9e2      	bls.n	6a0 <encode_uint+0x54>
     6da:	f1bb 0f01 	cmp.w	fp, #1
     6de:	d003      	beq.n	6e8 <encode_uint+0x9c>
			: upcase ? ('A' + lsv - 10) : ('a' + lsv - 10);
     6e0:	b2d2      	uxtb	r2, r2
		*--bp = (lsv <= 9) ? ('0' + lsv)
     6e2:	3257      	adds	r2, #87	; 0x57
     6e4:	b2d2      	uxtb	r2, r2
     6e6:	e7de      	b.n	6a6 <encode_uint+0x5a>
			: upcase ? ('A' + lsv - 10) : ('a' + lsv - 10);
     6e8:	b2d2      	uxtb	r2, r2
		*--bp = (lsv <= 9) ? ('0' + lsv)
     6ea:	3237      	adds	r2, #55	; 0x37
     6ec:	b2d2      	uxtb	r2, r2
     6ee:	e7da      	b.n	6a6 <encode_uint+0x5a>

	/* Record required alternate forms.  This can be determined
	 * from the radix without re-checking specifier.
	 */
	if (conv->flag_hash) {
     6f0:	9b01      	ldr	r3, [sp, #4]
     6f2:	781b      	ldrb	r3, [r3, #0]
     6f4:	f013 0f20 	tst.w	r3, #32
     6f8:	d005      	beq.n	706 <encode_uint+0xba>
		if (radix == 8) {
     6fa:	f1b9 0f08 	cmp.w	r9, #8
     6fe:	d006      	beq.n	70e <encode_uint+0xc2>
			conv->altform_0 = true;
		} else if (radix == 16) {
     700:	f1b9 0f10 	cmp.w	r9, #16
     704:	d009      	beq.n	71a <encode_uint+0xce>
			;
		}
	}

	return bp;
}
     706:	4640      	mov	r0, r8
     708:	b003      	add	sp, #12
     70a:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			conv->altform_0 = true;
     70e:	9a01      	ldr	r2, [sp, #4]
     710:	7893      	ldrb	r3, [r2, #2]
     712:	f043 0308 	orr.w	r3, r3, #8
     716:	7093      	strb	r3, [r2, #2]
     718:	e7f5      	b.n	706 <encode_uint+0xba>
			conv->altform_0c = true;
     71a:	9a01      	ldr	r2, [sp, #4]
     71c:	7893      	ldrb	r3, [r2, #2]
     71e:	f043 0310 	orr.w	r3, r3, #16
     722:	7093      	strb	r3, [r2, #2]
     724:	e7ef      	b.n	706 <encode_uint+0xba>
     726:	bf00      	nop
     728:	00005c6a 	.word	0x00005c6a

0000072c <cbvprintf>:

	return (int)count;
}

int cbvprintf(cbprintf_cb out, void *ctx, const char *fp, va_list ap)
{
     72c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     730:	b093      	sub	sp, #76	; 0x4c
     732:	4606      	mov	r6, r0
     734:	460d      	mov	r5, r1
     736:	4692      	mov	sl, r2
     738:	9303      	str	r3, [sp, #12]
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
     73a:	2400      	movs	r4, #0
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
     73c:	f89a 0000 	ldrb.w	r0, [sl]
     740:	2800      	cmp	r0, #0
     742:	f000 84d6 	beq.w	10f2 <CONFIG_FPROTECT_BLOCK_SIZE+0xf2>
		if (*fp != '%') {
     746:	2825      	cmp	r0, #37	; 0x25
     748:	d008      	beq.n	75c <cbvprintf+0x30>
			OUTC(*fp++);
     74a:	f10a 0a01 	add.w	sl, sl, #1
     74e:	4629      	mov	r1, r5
     750:	47b0      	blx	r6
     752:	2800      	cmp	r0, #0
     754:	f2c0 84ce 	blt.w	10f4 <CONFIG_FPROTECT_BLOCK_SIZE+0xf4>
     758:	3401      	adds	r4, #1
			continue;
     75a:	e7ef      	b.n	73c <cbvprintf+0x10>
		 * mitigate LLVM code generation bug.
		 */
		struct {
			union argument_value value;
			struct conversion conv;
		} state = {
     75c:	2300      	movs	r3, #0
     75e:	9306      	str	r3, [sp, #24]
     760:	9307      	str	r3, [sp, #28]
     762:	930b      	str	r3, [sp, #44]	; 0x2c
	*conv = (struct conversion) {
     764:	9308      	str	r3, [sp, #32]
     766:	9309      	str	r3, [sp, #36]	; 0x24
     768:	930a      	str	r3, [sp, #40]	; 0x28
	++sp;
     76a:	f10a 0801 	add.w	r8, sl, #1
	if (*sp == '%') {
     76e:	f89a 3001 	ldrb.w	r3, [sl, #1]
     772:	2b25      	cmp	r3, #37	; 0x25
     774:	d001      	beq.n	77a <cbvprintf+0x4e>
	bool loop = true;
     776:	2701      	movs	r7, #1
     778:	e02c      	b.n	7d4 <cbvprintf+0xa8>
		conv->specifier = *sp++;
     77a:	f10a 0802 	add.w	r8, sl, #2
     77e:	f88d 3023 	strb.w	r3, [sp, #35]	; 0x23
		return sp;
     782:	e1a8      	b.n	ad6 <CONFIG_ISR_STACK_SIZE+0x2d6>
			conv->flag_dash = true;
     784:	f89d 3020 	ldrb.w	r3, [sp, #32]
     788:	f043 0304 	orr.w	r3, r3, #4
     78c:	f88d 3020 	strb.w	r3, [sp, #32]
		if (loop) {
     790:	b1ff      	cbz	r7, 7d2 <cbvprintf+0xa6>
			++sp;
     792:	f108 0801 	add.w	r8, r8, #1
     796:	e01c      	b.n	7d2 <cbvprintf+0xa6>
			conv->flag_plus = true;
     798:	f89d 3020 	ldrb.w	r3, [sp, #32]
     79c:	f043 0308 	orr.w	r3, r3, #8
     7a0:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     7a4:	e7f4      	b.n	790 <cbvprintf+0x64>
			conv->flag_space = true;
     7a6:	f89d 3020 	ldrb.w	r3, [sp, #32]
     7aa:	f043 0310 	orr.w	r3, r3, #16
     7ae:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     7b2:	e7ed      	b.n	790 <cbvprintf+0x64>
			conv->flag_hash = true;
     7b4:	f89d 3020 	ldrb.w	r3, [sp, #32]
     7b8:	f043 0320 	orr.w	r3, r3, #32
     7bc:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     7c0:	e7e6      	b.n	790 <cbvprintf+0x64>
			conv->flag_zero = true;
     7c2:	f89d 3020 	ldrb.w	r3, [sp, #32]
     7c6:	f043 0340 	orr.w	r3, r3, #64	; 0x40
     7ca:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     7ce:	e7df      	b.n	790 <cbvprintf+0x64>
		switch (*sp) {
     7d0:	2700      	movs	r7, #0
	} while (loop);
     7d2:	b34f      	cbz	r7, 828 <CONFIG_ISR_STACK_SIZE+0x28>
		switch (*sp) {
     7d4:	f898 3000 	ldrb.w	r3, [r8]
     7d8:	3b20      	subs	r3, #32
     7da:	2b10      	cmp	r3, #16
     7dc:	d8f8      	bhi.n	7d0 <cbvprintf+0xa4>
     7de:	a201      	add	r2, pc, #4	; (adr r2, 7e4 <cbvprintf+0xb8>)
     7e0:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
     7e4:	000007a7 	.word	0x000007a7
     7e8:	000007d1 	.word	0x000007d1
     7ec:	000007d1 	.word	0x000007d1
     7f0:	000007b5 	.word	0x000007b5
     7f4:	000007d1 	.word	0x000007d1
     7f8:	000007d1 	.word	0x000007d1
     7fc:	000007d1 	.word	0x000007d1
     800:	000007d1 	.word	0x000007d1
     804:	000007d1 	.word	0x000007d1
     808:	000007d1 	.word	0x000007d1
     80c:	000007d1 	.word	0x000007d1
     810:	00000799 	.word	0x00000799
     814:	000007d1 	.word	0x000007d1
     818:	00000785 	.word	0x00000785
     81c:	000007d1 	.word	0x000007d1
     820:	000007d1 	.word	0x000007d1
     824:	000007c3 	.word	0x000007c3
	if (conv->flag_zero && conv->flag_dash) {
     828:	f89d 3020 	ldrb.w	r3, [sp, #32]
     82c:	f003 0344 	and.w	r3, r3, #68	; 0x44
     830:	2b44      	cmp	r3, #68	; 0x44
     832:	d06d      	beq.n	910 <CONFIG_ISR_STACK_SIZE+0x110>
	sp = extract_width(conv, sp);
     834:	f8cd 8014 	str.w	r8, [sp, #20]
	conv->width_present = true;
     838:	f89d 3020 	ldrb.w	r3, [sp, #32]
     83c:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     840:	f88d 3020 	strb.w	r3, [sp, #32]
	if (*sp == '*') {
     844:	f898 3000 	ldrb.w	r3, [r8]
     848:	2b2a      	cmp	r3, #42	; 0x2a
     84a:	d068      	beq.n	91e <CONFIG_ISR_STACK_SIZE+0x11e>
	size_t width = extract_decimal(&sp);
     84c:	a805      	add	r0, sp, #20
     84e:	f7ff fee7 	bl	620 <extract_decimal>
	if (sp != wp) {
     852:	9b05      	ldr	r3, [sp, #20]
     854:	4598      	cmp	r8, r3
     856:	d012      	beq.n	87e <CONFIG_ISR_STACK_SIZE+0x7e>
		conv->width_present = true;
     858:	f89d 3020 	ldrb.w	r3, [sp, #32]
     85c:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     860:	f88d 3020 	strb.w	r3, [sp, #32]
		conv->width_value = width;
     864:	9009      	str	r0, [sp, #36]	; 0x24
		conv->unsupported |= ((conv->width_value < 0)
     866:	f3c3 0340 	ubfx	r3, r3, #1, #1
				      || (width != (size_t)conv->width_value));
     86a:	2800      	cmp	r0, #0
     86c:	db60      	blt.n	930 <CONFIG_ISR_STACK_SIZE+0x130>
     86e:	2200      	movs	r2, #0
		conv->unsupported |= ((conv->width_value < 0)
     870:	4313      	orrs	r3, r2
     872:	f89d 2020 	ldrb.w	r2, [sp, #32]
     876:	f363 0241 	bfi	r2, r3, #1, #1
     87a:	f88d 2020 	strb.w	r2, [sp, #32]
	return sp;
     87e:	9b05      	ldr	r3, [sp, #20]
	sp = extract_prec(conv, sp);
     880:	9305      	str	r3, [sp, #20]
	conv->prec_present = (*sp == '.');
     882:	781b      	ldrb	r3, [r3, #0]
     884:	2b2e      	cmp	r3, #46	; 0x2e
     886:	bf14      	ite	ne
     888:	2300      	movne	r3, #0
     88a:	2301      	moveq	r3, #1
     88c:	f89d 2021 	ldrb.w	r2, [sp, #33]	; 0x21
     890:	f363 0241 	bfi	r2, r3, #1, #1
     894:	f88d 2021 	strb.w	r2, [sp, #33]	; 0x21
	if (!conv->prec_present) {
     898:	2b00      	cmp	r3, #0
     89a:	d04b      	beq.n	934 <CONFIG_ISR_STACK_SIZE+0x134>
	++sp;
     89c:	9b05      	ldr	r3, [sp, #20]
     89e:	1c5a      	adds	r2, r3, #1
     8a0:	9205      	str	r2, [sp, #20]
	if (*sp == '*') {
     8a2:	785b      	ldrb	r3, [r3, #1]
     8a4:	2b2a      	cmp	r3, #42	; 0x2a
     8a6:	d048      	beq.n	93a <CONFIG_ISR_STACK_SIZE+0x13a>
	size_t prec = extract_decimal(&sp);
     8a8:	a805      	add	r0, sp, #20
     8aa:	f7ff feb9 	bl	620 <extract_decimal>
	conv->prec_value = prec;
     8ae:	900a      	str	r0, [sp, #40]	; 0x28
	conv->unsupported |= ((conv->prec_value < 0)
     8b0:	f89d 3020 	ldrb.w	r3, [sp, #32]
     8b4:	f3c3 0340 	ubfx	r3, r3, #1, #1
			      || (prec != (size_t)conv->prec_value));
     8b8:	2800      	cmp	r0, #0
     8ba:	db47      	blt.n	94c <CONFIG_ISR_STACK_SIZE+0x14c>
     8bc:	2200      	movs	r2, #0
	conv->unsupported |= ((conv->prec_value < 0)
     8be:	4313      	orrs	r3, r2
     8c0:	f89d 2020 	ldrb.w	r2, [sp, #32]
     8c4:	f363 0241 	bfi	r2, r3, #1, #1
     8c8:	f88d 2020 	strb.w	r2, [sp, #32]
	return sp;
     8cc:	f8dd 8014 	ldr.w	r8, [sp, #20]
	switch (*sp) {
     8d0:	f898 3000 	ldrb.w	r3, [r8]
     8d4:	3b4c      	subs	r3, #76	; 0x4c
     8d6:	2b2e      	cmp	r3, #46	; 0x2e
     8d8:	f200 80dc 	bhi.w	a94 <CONFIG_ISR_STACK_SIZE+0x294>
     8dc:	e8df f003 	tbb	[pc, r3]
     8e0:	dadadaca 	.word	0xdadadaca
     8e4:	dadadada 	.word	0xdadadada
     8e8:	dadadada 	.word	0xdadadada
     8ec:	dadadada 	.word	0xdadadada
     8f0:	dadadada 	.word	0xdadadada
     8f4:	dadadada 	.word	0xdadadada
     8f8:	dadadada 	.word	0xdadadada
     8fc:	da6ada38 	.word	0xda6ada38
     900:	dadada51 	.word	0xdadada51
     904:	dadadada 	.word	0xdadadada
     908:	dadadac0 	.word	0xdadadac0
     90c:	dada      	.short	0xdada
     90e:	b6          	.byte	0xb6
     90f:	00          	.byte	0x00
		conv->flag_zero = false;
     910:	f89d 3020 	ldrb.w	r3, [sp, #32]
     914:	f36f 1386 	bfc	r3, #6, #1
     918:	f88d 3020 	strb.w	r3, [sp, #32]
     91c:	e78a      	b.n	834 <CONFIG_ISR_STACK_SIZE+0x34>
		conv->width_star = true;
     91e:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     922:	f043 0301 	orr.w	r3, r3, #1
     926:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		return ++sp;
     92a:	4643      	mov	r3, r8
     92c:	3301      	adds	r3, #1
     92e:	e7a7      	b.n	880 <CONFIG_ISR_STACK_SIZE+0x80>
				      || (width != (size_t)conv->width_value));
     930:	2201      	movs	r2, #1
     932:	e79d      	b.n	870 <CONFIG_ISR_STACK_SIZE+0x70>
		return sp;
     934:	f8dd 8014 	ldr.w	r8, [sp, #20]
     938:	e7ca      	b.n	8d0 <CONFIG_ISR_STACK_SIZE+0xd0>
		conv->prec_star = true;
     93a:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     93e:	f043 0304 	orr.w	r3, r3, #4
     942:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		return ++sp;
     946:	f102 0801 	add.w	r8, r2, #1
     94a:	e7c1      	b.n	8d0 <CONFIG_ISR_STACK_SIZE+0xd0>
			      || (prec != (size_t)conv->prec_value));
     94c:	2201      	movs	r2, #1
     94e:	e7b6      	b.n	8be <CONFIG_ISR_STACK_SIZE+0xbe>
		if (*++sp == 'h') {
     950:	f108 0201 	add.w	r2, r8, #1
     954:	f898 3001 	ldrb.w	r3, [r8, #1]
     958:	2b68      	cmp	r3, #104	; 0x68
     95a:	d008      	beq.n	96e <CONFIG_ISR_STACK_SIZE+0x16e>
			conv->length_mod = LENGTH_H;
     95c:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     960:	2102      	movs	r1, #2
     962:	f361 03c6 	bfi	r3, r1, #3, #4
     966:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		if (*++sp == 'h') {
     96a:	4690      	mov	r8, r2
     96c:	e02b      	b.n	9c6 <CONFIG_ISR_STACK_SIZE+0x1c6>
			conv->length_mod = LENGTH_HH;
     96e:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     972:	2201      	movs	r2, #1
     974:	f362 03c6 	bfi	r3, r2, #3, #4
     978:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
			++sp;
     97c:	f108 0802 	add.w	r8, r8, #2
     980:	e021      	b.n	9c6 <CONFIG_ISR_STACK_SIZE+0x1c6>
		if (*++sp == 'l') {
     982:	f108 0201 	add.w	r2, r8, #1
     986:	f898 3001 	ldrb.w	r3, [r8, #1]
     98a:	2b6c      	cmp	r3, #108	; 0x6c
     98c:	d008      	beq.n	9a0 <CONFIG_ISR_STACK_SIZE+0x1a0>
			conv->length_mod = LENGTH_L;
     98e:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     992:	2103      	movs	r1, #3
     994:	f361 03c6 	bfi	r3, r1, #3, #4
     998:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		if (*++sp == 'l') {
     99c:	4690      	mov	r8, r2
     99e:	e012      	b.n	9c6 <CONFIG_ISR_STACK_SIZE+0x1c6>
			conv->length_mod = LENGTH_LL;
     9a0:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     9a4:	2204      	movs	r2, #4
     9a6:	f362 03c6 	bfi	r3, r2, #3, #4
     9aa:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
			++sp;
     9ae:	f108 0802 	add.w	r8, r8, #2
     9b2:	e008      	b.n	9c6 <CONFIG_ISR_STACK_SIZE+0x1c6>
		conv->length_mod = LENGTH_J;
     9b4:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     9b8:	2205      	movs	r2, #5
     9ba:	f362 03c6 	bfi	r3, r2, #3, #4
     9be:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     9c2:	f108 0801 	add.w	r8, r8, #1
	conv->specifier = *sp++;
     9c6:	f818 3b01 	ldrb.w	r3, [r8], #1
     9ca:	f88d 3023 	strb.w	r3, [sp, #35]	; 0x23
	switch (conv->specifier) {
     9ce:	f1a3 0241 	sub.w	r2, r3, #65	; 0x41
     9d2:	2a37      	cmp	r2, #55	; 0x37
     9d4:	f200 8150 	bhi.w	c78 <CONFIG_ISR_STACK_SIZE+0x478>
     9d8:	e8df f012 	tbh	[pc, r2, lsl #1]
     9dc:	014e0126 	.word	0x014e0126
     9e0:	014e014e 	.word	0x014e014e
     9e4:	01260126 	.word	0x01260126
     9e8:	014e0126 	.word	0x014e0126
     9ec:	014e014e 	.word	0x014e014e
     9f0:	014e014e 	.word	0x014e014e
     9f4:	014e014e 	.word	0x014e014e
     9f8:	014e014e 	.word	0x014e014e
     9fc:	014e014e 	.word	0x014e014e
     a00:	014e014e 	.word	0x014e014e
     a04:	014e014e 	.word	0x014e014e
     a08:	0113014e 	.word	0x0113014e
     a0c:	014e014e 	.word	0x014e014e
     a10:	014e014e 	.word	0x014e014e
     a14:	014e014e 	.word	0x014e014e
     a18:	014e014e 	.word	0x014e014e
     a1c:	014e0126 	.word	0x014e0126
     a20:	00630113 	.word	0x00630113
     a24:	01260126 	.word	0x01260126
     a28:	014e0126 	.word	0x014e0126
     a2c:	014e0063 	.word	0x014e0063
     a30:	014e014e 	.word	0x014e014e
     a34:	012f014e 	.word	0x012f014e
     a38:	013f0113 	.word	0x013f0113
     a3c:	014e014e 	.word	0x014e014e
     a40:	014e013f 	.word	0x014e013f
     a44:	014e0113 	.word	0x014e0113
     a48:	0113014e 	.word	0x0113014e
		conv->length_mod = LENGTH_Z;
     a4c:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     a50:	2206      	movs	r2, #6
     a52:	f362 03c6 	bfi	r3, r2, #3, #4
     a56:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     a5a:	f108 0801 	add.w	r8, r8, #1
		break;
     a5e:	e7b2      	b.n	9c6 <CONFIG_ISR_STACK_SIZE+0x1c6>
		conv->length_mod = LENGTH_T;
     a60:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     a64:	2207      	movs	r2, #7
     a66:	f362 03c6 	bfi	r3, r2, #3, #4
     a6a:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     a6e:	f108 0801 	add.w	r8, r8, #1
		break;
     a72:	e7a8      	b.n	9c6 <CONFIG_ISR_STACK_SIZE+0x1c6>
		conv->length_mod = LENGTH_UPPER_L;
     a74:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     a78:	2208      	movs	r2, #8
     a7a:	f362 03c6 	bfi	r3, r2, #3, #4
     a7e:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     a82:	f108 0801 	add.w	r8, r8, #1
		conv->unsupported = true;
     a86:	f89d 3020 	ldrb.w	r3, [sp, #32]
     a8a:	f043 0302 	orr.w	r3, r3, #2
     a8e:	f88d 3020 	strb.w	r3, [sp, #32]
		break;
     a92:	e798      	b.n	9c6 <CONFIG_ISR_STACK_SIZE+0x1c6>
		conv->length_mod = LENGTH_NONE;
     a94:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     a98:	f36f 03c6 	bfc	r3, #3, #4
     a9c:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		break;
     aa0:	e791      	b.n	9c6 <CONFIG_ISR_STACK_SIZE+0x1c6>
		conv->specifier_cat = SPECIFIER_SINT;
     aa2:	f89d 2022 	ldrb.w	r2, [sp, #34]	; 0x22
     aa6:	2101      	movs	r1, #1
     aa8:	f361 0202 	bfi	r2, r1, #0, #3
     aac:	f88d 2022 	strb.w	r2, [sp, #34]	; 0x22
		if (conv->length_mod == LENGTH_UPPER_L) {
     ab0:	f89d 2021 	ldrb.w	r2, [sp, #33]	; 0x21
     ab4:	f002 0278 	and.w	r2, r2, #120	; 0x78
     ab8:	2a40      	cmp	r2, #64	; 0x40
     aba:	f000 80aa 	beq.w	c12 <CONFIG_ISR_STACK_SIZE+0x412>
		if (conv->specifier == 'c') {
     abe:	2b63      	cmp	r3, #99	; 0x63
     ac0:	f000 80ae 	beq.w	c20 <CONFIG_ISR_STACK_SIZE+0x420>
	conv->unsupported |= unsupported;
     ac4:	f89d 3020 	ldrb.w	r3, [sp, #32]
     ac8:	f3c3 0240 	ubfx	r2, r3, #1, #1
     acc:	4317      	orrs	r7, r2
     ace:	f367 0341 	bfi	r3, r7, #1, #1
     ad2:	f88d 3020 	strb.w	r3, [sp, #32]
		fp = extract_conversion(conv, sp);

		/* If dynamic width is specified, process it,
		 * otherwise set width if present.
		 */
		if (conv->width_star) {
     ad6:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     ada:	f013 0f01 	tst.w	r3, #1
     ade:	f000 80da 	beq.w	c96 <CONFIG_ISR_STACK_SIZE+0x496>
			width = va_arg(ap, int);
     ae2:	9b03      	ldr	r3, [sp, #12]
     ae4:	1d1a      	adds	r2, r3, #4
     ae6:	9203      	str	r2, [sp, #12]
     ae8:	681f      	ldr	r7, [r3, #0]

			if (width < 0) {
     aea:	2f00      	cmp	r7, #0
     aec:	f2c0 80cb 	blt.w	c86 <CONFIG_ISR_STACK_SIZE+0x486>

		/* If dynamic precision is specified, process it, otherwise
		 * set precision if present.  For floating point where
		 * precision is not present use 6.
		 */
		if (conv->prec_star) {
     af0:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     af4:	f013 0f04 	tst.w	r3, #4
     af8:	f000 80df 	beq.w	cba <CONFIG_ISR_STACK_SIZE+0x4ba>
			int arg = va_arg(ap, int);
     afc:	9b03      	ldr	r3, [sp, #12]
     afe:	1d1a      	adds	r2, r3, #4
     b00:	9203      	str	r2, [sp, #12]
     b02:	f8d3 b000 	ldr.w	fp, [r3]

			if (arg < 0) {
     b06:	f1bb 0f00 	cmp.w	fp, #0
     b0a:	f2c0 80cd 	blt.w	ca8 <CONFIG_ISR_STACK_SIZE+0x4a8>
		}

		/* Reuse width and precision memory in conv for value
		 * padding counts.
		 */
		conv->pad0_value = 0;
     b0e:	2300      	movs	r3, #0
     b10:	9309      	str	r3, [sp, #36]	; 0x24
		conv->pad0_pre_exp = 0;
     b12:	930a      	str	r3, [sp, #40]	; 0x28
		 * This can't be extracted to a helper function because
		 * passing a pointer to va_list doesn't work on x86_64.  See
		 * https://stackoverflow.com/a/8048892.
		 */
		enum specifier_cat_enum specifier_cat
			= (enum specifier_cat_enum)conv->specifier_cat;
     b14:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     b18:	f003 0307 	and.w	r3, r3, #7
		enum length_mod_enum length_mod
			= (enum length_mod_enum)conv->length_mod;
     b1c:	f89d 1021 	ldrb.w	r1, [sp, #33]	; 0x21
     b20:	f3c1 01c3 	ubfx	r1, r1, #3, #4
		/* Extract the value based on the argument category and length.
		 *
		 * Note that the length modifier doesn't affect the value of a
		 * pointer argument.
		 */
		if (specifier_cat == SPECIFIER_SINT) {
     b24:	2b01      	cmp	r3, #1
     b26:	f000 80d1 	beq.w	ccc <CONFIG_ISR_STACK_SIZE+0x4cc>
			if (length_mod == LENGTH_HH) {
				value->sint = (char)value->sint;
			} else if (length_mod == LENGTH_H) {
				value->sint = (short)value->sint;
			}
		} else if (specifier_cat == SPECIFIER_UINT) {
     b2a:	2b02      	cmp	r3, #2
     b2c:	f000 8116 	beq.w	d5c <CONFIG_ISR_STACK_SIZE+0x55c>
			if (length_mod == LENGTH_HH) {
				value->uint = (unsigned char)value->uint;
			} else if (length_mod == LENGTH_H) {
				value->uint = (unsigned short)value->uint;
			}
		} else if (specifier_cat == SPECIFIER_FP) {
     b30:	2b04      	cmp	r3, #4
     b32:	f000 8167 	beq.w	e04 <CONFIG_ISR_STACK_SIZE+0x604>
			if (length_mod == LENGTH_UPPER_L) {
				value->ldbl = va_arg(ap, long double);
			} else {
				value->dbl = va_arg(ap, double);
			}
		} else if (specifier_cat == SPECIFIER_PTR) {
     b36:	2b03      	cmp	r3, #3
     b38:	f000 817e 	beq.w	e38 <CONFIG_ISR_STACK_SIZE+0x638>
		/* We've now consumed all arguments related to this
		 * specification.  If the conversion is invalid, or is
		 * something we don't support, then output the original
		 * specification and move on.
		 */
		if (conv->invalid || conv->unsupported) {
     b3c:	f89d 9020 	ldrb.w	r9, [sp, #32]
     b40:	f019 0303 	ands.w	r3, r9, #3
     b44:	9302      	str	r3, [sp, #8]
     b46:	f040 817d 	bne.w	e44 <CONFIG_ISR_STACK_SIZE+0x644>
		}

		/* Do formatting, either into the buffer or
		 * referencing external data.
		 */
		switch (conv->specifier) {
     b4a:	f89d 3023 	ldrb.w	r3, [sp, #35]	; 0x23
     b4e:	3b25      	subs	r3, #37	; 0x25
     b50:	2b53      	cmp	r3, #83	; 0x53
     b52:	f200 8233 	bhi.w	fbc <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x1c>
     b56:	e8df f013 	tbh	[pc, r3, lsl #1]
     b5a:	0181      	.short	0x0181
     b5c:	02310231 	.word	0x02310231
     b60:	02310231 	.word	0x02310231
     b64:	02310231 	.word	0x02310231
     b68:	02310231 	.word	0x02310231
     b6c:	02310231 	.word	0x02310231
     b70:	02310231 	.word	0x02310231
     b74:	02310231 	.word	0x02310231
     b78:	02310231 	.word	0x02310231
     b7c:	02310231 	.word	0x02310231
     b80:	02310231 	.word	0x02310231
     b84:	02310231 	.word	0x02310231
     b88:	02310231 	.word	0x02310231
     b8c:	02310231 	.word	0x02310231
     b90:	02310231 	.word	0x02310231
     b94:	02310231 	.word	0x02310231
     b98:	02310231 	.word	0x02310231
     b9c:	02310231 	.word	0x02310231
     ba0:	02310231 	.word	0x02310231
     ba4:	02310231 	.word	0x02310231
     ba8:	02310231 	.word	0x02310231
     bac:	02310231 	.word	0x02310231
     bb0:	02310231 	.word	0x02310231
     bb4:	02310231 	.word	0x02310231
     bb8:	02310231 	.word	0x02310231
     bbc:	02310231 	.word	0x02310231
     bc0:	023101c7 	.word	0x023101c7
     bc4:	02310231 	.word	0x02310231
     bc8:	02310231 	.word	0x02310231
     bcc:	02310231 	.word	0x02310231
     bd0:	02310231 	.word	0x02310231
     bd4:	01a10231 	.word	0x01a10231
     bd8:	023101ab 	.word	0x023101ab
     bdc:	02310231 	.word	0x02310231
     be0:	01ab0231 	.word	0x01ab0231
     be4:	02310231 	.word	0x02310231
     be8:	02310231 	.word	0x02310231
     bec:	01c70208 	.word	0x01c70208
     bf0:	023101ea 	.word	0x023101ea
     bf4:	018f0231 	.word	0x018f0231
     bf8:	01c70231 	.word	0x01c70231
     bfc:	02310231 	.word	0x02310231
     c00:	01c7      	.short	0x01c7
		conv->specifier_cat = SPECIFIER_UINT;
     c02:	f89d 2022 	ldrb.w	r2, [sp, #34]	; 0x22
     c06:	2102      	movs	r1, #2
     c08:	f361 0202 	bfi	r2, r1, #0, #3
     c0c:	f88d 2022 	strb.w	r2, [sp, #34]	; 0x22
     c10:	e74e      	b.n	ab0 <CONFIG_ISR_STACK_SIZE+0x2b0>
			conv->invalid = true;
     c12:	f89d 1020 	ldrb.w	r1, [sp, #32]
     c16:	f041 0101 	orr.w	r1, r1, #1
     c1a:	f88d 1020 	strb.w	r1, [sp, #32]
     c1e:	e74e      	b.n	abe <CONFIG_ISR_STACK_SIZE+0x2be>
			unsupported = (conv->length_mod != LENGTH_NONE);
     c20:	1e17      	subs	r7, r2, #0
     c22:	bf18      	it	ne
     c24:	2701      	movne	r7, #1
     c26:	e74d      	b.n	ac4 <CONFIG_ISR_STACK_SIZE+0x2c4>
		conv->specifier_cat = SPECIFIER_FP;
     c28:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     c2c:	2204      	movs	r2, #4
     c2e:	f362 0302 	bfi	r3, r2, #0, #3
     c32:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
			unsupported = true;
     c36:	2701      	movs	r7, #1
			break;
     c38:	e744      	b.n	ac4 <CONFIG_ISR_STACK_SIZE+0x2c4>
		conv->specifier_cat = SPECIFIER_PTR;
     c3a:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     c3e:	2203      	movs	r2, #3
     c40:	f362 0302 	bfi	r3, r2, #0, #3
     c44:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
		if (conv->length_mod == LENGTH_UPPER_L) {
     c48:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     c4c:	f003 0378 	and.w	r3, r3, #120	; 0x78
     c50:	2b40      	cmp	r3, #64	; 0x40
     c52:	f47f af37 	bne.w	ac4 <CONFIG_ISR_STACK_SIZE+0x2c4>
			unsupported = true;
     c56:	2701      	movs	r7, #1
     c58:	e734      	b.n	ac4 <CONFIG_ISR_STACK_SIZE+0x2c4>
		conv->specifier_cat = SPECIFIER_PTR;
     c5a:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     c5e:	2203      	movs	r2, #3
     c60:	f362 0302 	bfi	r3, r2, #0, #3
     c64:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
		if (conv->length_mod != LENGTH_NONE) {
     c68:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     c6c:	f013 0f78 	tst.w	r3, #120	; 0x78
     c70:	f43f af28 	beq.w	ac4 <CONFIG_ISR_STACK_SIZE+0x2c4>
			unsupported = true;
     c74:	2701      	movs	r7, #1
     c76:	e725      	b.n	ac4 <CONFIG_ISR_STACK_SIZE+0x2c4>
		conv->invalid = true;
     c78:	f89d 3020 	ldrb.w	r3, [sp, #32]
     c7c:	f043 0301 	orr.w	r3, r3, #1
     c80:	f88d 3020 	strb.w	r3, [sp, #32]
		break;
     c84:	e71e      	b.n	ac4 <CONFIG_ISR_STACK_SIZE+0x2c4>
				conv->flag_dash = true;
     c86:	f89d 3020 	ldrb.w	r3, [sp, #32]
     c8a:	f043 0304 	orr.w	r3, r3, #4
     c8e:	f88d 3020 	strb.w	r3, [sp, #32]
				width = -width;
     c92:	427f      	negs	r7, r7
     c94:	e72c      	b.n	af0 <CONFIG_ISR_STACK_SIZE+0x2f0>
		} else if (conv->width_present) {
     c96:	f99d 3020 	ldrsb.w	r3, [sp, #32]
     c9a:	2b00      	cmp	r3, #0
     c9c:	db02      	blt.n	ca4 <CONFIG_ISR_STACK_SIZE+0x4a4>
		int width = -1;
     c9e:	f04f 37ff 	mov.w	r7, #4294967295
     ca2:	e725      	b.n	af0 <CONFIG_ISR_STACK_SIZE+0x2f0>
			width = conv->width_value;
     ca4:	9f09      	ldr	r7, [sp, #36]	; 0x24
     ca6:	e723      	b.n	af0 <CONFIG_ISR_STACK_SIZE+0x2f0>
				conv->prec_present = false;
     ca8:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     cac:	f36f 0341 	bfc	r3, #1, #1
     cb0:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		int precision = -1;
     cb4:	f04f 3bff 	mov.w	fp, #4294967295
     cb8:	e729      	b.n	b0e <CONFIG_ISR_STACK_SIZE+0x30e>
		} else if (conv->prec_present) {
     cba:	f013 0f02 	tst.w	r3, #2
     cbe:	d002      	beq.n	cc6 <CONFIG_ISR_STACK_SIZE+0x4c6>
			precision = conv->prec_value;
     cc0:	f8dd b028 	ldr.w	fp, [sp, #40]	; 0x28
     cc4:	e723      	b.n	b0e <CONFIG_ISR_STACK_SIZE+0x30e>
		int precision = -1;
     cc6:	f04f 3bff 	mov.w	fp, #4294967295
     cca:	e720      	b.n	b0e <CONFIG_ISR_STACK_SIZE+0x30e>
			switch (length_mod) {
     ccc:	1ecb      	subs	r3, r1, #3
     cce:	2b04      	cmp	r3, #4
     cd0:	d804      	bhi.n	cdc <CONFIG_ISR_STACK_SIZE+0x4dc>
     cd2:	e8df f003 	tbb	[pc, r3]
     cd6:	1d0b      	.short	0x1d0b
     cd8:	3529      	.short	0x3529
     cda:	35          	.byte	0x35
     cdb:	00          	.byte	0x00
				value->sint = va_arg(ap, int);
     cdc:	9b03      	ldr	r3, [sp, #12]
     cde:	1d1a      	adds	r2, r3, #4
     ce0:	9203      	str	r2, [sp, #12]
     ce2:	681a      	ldr	r2, [r3, #0]
     ce4:	17d3      	asrs	r3, r2, #31
     ce6:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     cea:	e006      	b.n	cfa <CONFIG_ISR_STACK_SIZE+0x4fa>
					value->sint = va_arg(ap, long);
     cec:	9b03      	ldr	r3, [sp, #12]
     cee:	1d1a      	adds	r2, r3, #4
     cf0:	9203      	str	r2, [sp, #12]
     cf2:	681a      	ldr	r2, [r3, #0]
     cf4:	17d3      	asrs	r3, r2, #31
     cf6:	e9cd 2306 	strd	r2, r3, [sp, #24]
			if (length_mod == LENGTH_HH) {
     cfa:	2901      	cmp	r1, #1
     cfc:	d028      	beq.n	d50 <CONFIG_ISR_STACK_SIZE+0x550>
			} else if (length_mod == LENGTH_H) {
     cfe:	2902      	cmp	r1, #2
     d00:	f47f af1c 	bne.w	b3c <CONFIG_ISR_STACK_SIZE+0x33c>
				value->sint = (short)value->sint;
     d04:	f9bd 2018 	ldrsh.w	r2, [sp, #24]
     d08:	17d3      	asrs	r3, r2, #31
     d0a:	e9cd 2306 	strd	r2, r3, [sp, #24]
     d0e:	e715      	b.n	b3c <CONFIG_ISR_STACK_SIZE+0x33c>
					(sint_value_type)va_arg(ap, long long);
     d10:	9b03      	ldr	r3, [sp, #12]
     d12:	3307      	adds	r3, #7
     d14:	f023 0307 	bic.w	r3, r3, #7
     d18:	f103 0208 	add.w	r2, r3, #8
     d1c:	9203      	str	r2, [sp, #12]
     d1e:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->sint =
     d22:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     d26:	e7e8      	b.n	cfa <CONFIG_ISR_STACK_SIZE+0x4fa>
					(sint_value_type)va_arg(ap, intmax_t);
     d28:	9b03      	ldr	r3, [sp, #12]
     d2a:	3307      	adds	r3, #7
     d2c:	f023 0307 	bic.w	r3, r3, #7
     d30:	f103 0208 	add.w	r2, r3, #8
     d34:	9203      	str	r2, [sp, #12]
     d36:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->sint =
     d3a:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     d3e:	e7dc      	b.n	cfa <CONFIG_ISR_STACK_SIZE+0x4fa>
					(sint_value_type)va_arg(ap, ptrdiff_t);
     d40:	9b03      	ldr	r3, [sp, #12]
     d42:	1d1a      	adds	r2, r3, #4
     d44:	9203      	str	r2, [sp, #12]
     d46:	681a      	ldr	r2, [r3, #0]
     d48:	17d3      	asrs	r3, r2, #31
				value->sint =
     d4a:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     d4e:	e7d4      	b.n	cfa <CONFIG_ISR_STACK_SIZE+0x4fa>
				value->sint = (char)value->sint;
     d50:	f89d 3018 	ldrb.w	r3, [sp, #24]
     d54:	9306      	str	r3, [sp, #24]
     d56:	2300      	movs	r3, #0
     d58:	9307      	str	r3, [sp, #28]
     d5a:	e6ef      	b.n	b3c <CONFIG_ISR_STACK_SIZE+0x33c>
			switch (length_mod) {
     d5c:	1ecb      	subs	r3, r1, #3
     d5e:	2b04      	cmp	r3, #4
     d60:	d804      	bhi.n	d6c <CONFIG_ISR_STACK_SIZE+0x56c>
     d62:	e8df f003 	tbb	[pc, r3]
     d66:	1f0b      	.short	0x1f0b
     d68:	4135      	.short	0x4135
     d6a:	41          	.byte	0x41
     d6b:	00          	.byte	0x00
				value->uint = va_arg(ap, unsigned int);
     d6c:	9b03      	ldr	r3, [sp, #12]
     d6e:	1d1a      	adds	r2, r3, #4
     d70:	9203      	str	r2, [sp, #12]
     d72:	681b      	ldr	r3, [r3, #0]
     d74:	9306      	str	r3, [sp, #24]
     d76:	2300      	movs	r3, #0
     d78:	9307      	str	r3, [sp, #28]
				break;
     d7a:	e01e      	b.n	dba <CONFIG_ISR_STACK_SIZE+0x5ba>
				    && (conv->specifier == 'c')) {
     d7c:	f89d 3023 	ldrb.w	r3, [sp, #35]	; 0x23
				if ((!WCHAR_IS_SIGNED)
     d80:	2b63      	cmp	r3, #99	; 0x63
     d82:	d007      	beq.n	d94 <CONFIG_ISR_STACK_SIZE+0x594>
					value->uint = va_arg(ap, unsigned long);
     d84:	9b03      	ldr	r3, [sp, #12]
     d86:	1d1a      	adds	r2, r3, #4
     d88:	9203      	str	r2, [sp, #12]
     d8a:	681b      	ldr	r3, [r3, #0]
     d8c:	9306      	str	r3, [sp, #24]
     d8e:	2300      	movs	r3, #0
     d90:	9307      	str	r3, [sp, #28]
     d92:	e012      	b.n	dba <CONFIG_ISR_STACK_SIZE+0x5ba>
					value->uint = (wchar_t)va_arg(ap,
     d94:	9b03      	ldr	r3, [sp, #12]
     d96:	1d1a      	adds	r2, r3, #4
     d98:	9203      	str	r2, [sp, #12]
     d9a:	681b      	ldr	r3, [r3, #0]
     d9c:	9306      	str	r3, [sp, #24]
     d9e:	2300      	movs	r3, #0
     da0:	9307      	str	r3, [sp, #28]
     da2:	e00a      	b.n	dba <CONFIG_ISR_STACK_SIZE+0x5ba>
					(uint_value_type)va_arg(ap,
     da4:	9b03      	ldr	r3, [sp, #12]
     da6:	3307      	adds	r3, #7
     da8:	f023 0307 	bic.w	r3, r3, #7
     dac:	f103 0208 	add.w	r2, r3, #8
     db0:	9203      	str	r2, [sp, #12]
     db2:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->uint =
     db6:	e9cd 2306 	strd	r2, r3, [sp, #24]
			if (length_mod == LENGTH_HH) {
     dba:	2901      	cmp	r1, #1
     dbc:	d01c      	beq.n	df8 <CONFIG_ISR_STACK_SIZE+0x5f8>
			} else if (length_mod == LENGTH_H) {
     dbe:	2902      	cmp	r1, #2
     dc0:	f47f aebc 	bne.w	b3c <CONFIG_ISR_STACK_SIZE+0x33c>
				value->uint = (unsigned short)value->uint;
     dc4:	f8bd 3018 	ldrh.w	r3, [sp, #24]
     dc8:	9306      	str	r3, [sp, #24]
     dca:	2300      	movs	r3, #0
     dcc:	9307      	str	r3, [sp, #28]
     dce:	e6b5      	b.n	b3c <CONFIG_ISR_STACK_SIZE+0x33c>
					(uint_value_type)va_arg(ap,
     dd0:	9b03      	ldr	r3, [sp, #12]
     dd2:	3307      	adds	r3, #7
     dd4:	f023 0307 	bic.w	r3, r3, #7
     dd8:	f103 0208 	add.w	r2, r3, #8
     ddc:	9203      	str	r2, [sp, #12]
     dde:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->uint =
     de2:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     de6:	e7e8      	b.n	dba <CONFIG_ISR_STACK_SIZE+0x5ba>
					(uint_value_type)va_arg(ap, size_t);
     de8:	9b03      	ldr	r3, [sp, #12]
     dea:	1d1a      	adds	r2, r3, #4
     dec:	9203      	str	r2, [sp, #12]
     dee:	681b      	ldr	r3, [r3, #0]
				value->uint =
     df0:	9306      	str	r3, [sp, #24]
     df2:	2300      	movs	r3, #0
     df4:	9307      	str	r3, [sp, #28]
				break;
     df6:	e7e0      	b.n	dba <CONFIG_ISR_STACK_SIZE+0x5ba>
				value->uint = (unsigned char)value->uint;
     df8:	f89d 3018 	ldrb.w	r3, [sp, #24]
     dfc:	9306      	str	r3, [sp, #24]
     dfe:	2300      	movs	r3, #0
     e00:	9307      	str	r3, [sp, #28]
     e02:	e69b      	b.n	b3c <CONFIG_ISR_STACK_SIZE+0x33c>
			if (length_mod == LENGTH_UPPER_L) {
     e04:	2908      	cmp	r1, #8
     e06:	d00b      	beq.n	e20 <CONFIG_ISR_STACK_SIZE+0x620>
				value->dbl = va_arg(ap, double);
     e08:	9b03      	ldr	r3, [sp, #12]
     e0a:	3307      	adds	r3, #7
     e0c:	f023 0307 	bic.w	r3, r3, #7
     e10:	f103 0208 	add.w	r2, r3, #8
     e14:	9203      	str	r2, [sp, #12]
     e16:	e9d3 2300 	ldrd	r2, r3, [r3]
     e1a:	e9cd 2306 	strd	r2, r3, [sp, #24]
     e1e:	e68d      	b.n	b3c <CONFIG_ISR_STACK_SIZE+0x33c>
				value->ldbl = va_arg(ap, long double);
     e20:	9b03      	ldr	r3, [sp, #12]
     e22:	3307      	adds	r3, #7
     e24:	f023 0307 	bic.w	r3, r3, #7
     e28:	f103 0208 	add.w	r2, r3, #8
     e2c:	9203      	str	r2, [sp, #12]
     e2e:	e9d3 2300 	ldrd	r2, r3, [r3]
     e32:	e9cd 2306 	strd	r2, r3, [sp, #24]
     e36:	e681      	b.n	b3c <CONFIG_ISR_STACK_SIZE+0x33c>
			value->ptr = va_arg(ap, void *);
     e38:	9b03      	ldr	r3, [sp, #12]
     e3a:	1d1a      	adds	r2, r3, #4
     e3c:	9203      	str	r2, [sp, #12]
     e3e:	681b      	ldr	r3, [r3, #0]
     e40:	9306      	str	r3, [sp, #24]
     e42:	e67b      	b.n	b3c <CONFIG_ISR_STACK_SIZE+0x33c>
			OUTS(sp, fp);
     e44:	4643      	mov	r3, r8
     e46:	4652      	mov	r2, sl
     e48:	4629      	mov	r1, r5
     e4a:	4630      	mov	r0, r6
     e4c:	f003 fecc 	bl	4be8 <outs>
     e50:	2800      	cmp	r0, #0
     e52:	f2c0 814f 	blt.w	10f4 <CONFIG_FPROTECT_BLOCK_SIZE+0xf4>
     e56:	4404      	add	r4, r0
		fp = extract_conversion(conv, sp);
     e58:	46c2      	mov	sl, r8
			continue;
     e5a:	e46f      	b.n	73c <cbvprintf+0x10>
		case '%':
			OUTC('%');
     e5c:	4629      	mov	r1, r5
     e5e:	2025      	movs	r0, #37	; 0x25
     e60:	47b0      	blx	r6
     e62:	2800      	cmp	r0, #0
     e64:	f2c0 8146 	blt.w	10f4 <CONFIG_FPROTECT_BLOCK_SIZE+0xf4>
     e68:	3401      	adds	r4, #1
		char sign = 0;
     e6a:	f8dd 9008 	ldr.w	r9, [sp, #8]
		const char *bpe = buf + sizeof(buf);
     e6e:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
		const char *bps = NULL;
     e72:	f04f 0a00 	mov.w	sl, #0
			break;
     e76:	e0a7      	b.n	fc8 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x28>
		case 's': {
			bps = (const char *)value->ptr;
     e78:	f8dd a018 	ldr.w	sl, [sp, #24]

			size_t len;

			if (precision >= 0) {
     e7c:	f1bb 0f00 	cmp.w	fp, #0
     e80:	db08      	blt.n	e94 <CONFIG_ISR_STACK_SIZE+0x694>
				len = strnlen(bps, precision);
     e82:	4659      	mov	r1, fp
     e84:	4650      	mov	r0, sl
     e86:	f004 fc9a 	bl	57be <strnlen>
			} else {
				len = strlen(bps);
			}

			bpe = bps + len;
     e8a:	eb0a 0b00 	add.w	fp, sl, r0
		char sign = 0;
     e8e:	f8dd 9008 	ldr.w	r9, [sp, #8]
			precision = -1;

			break;
     e92:	e099      	b.n	fc8 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x28>
				len = strlen(bps);
     e94:	4650      	mov	r0, sl
     e96:	f7ff fab7 	bl	408 <strlen>
     e9a:	e7f6      	b.n	e8a <CONFIG_ISR_STACK_SIZE+0x68a>
		}
		case 'c':
			bps = buf;
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     e9c:	9b06      	ldr	r3, [sp, #24]
     e9e:	f88d 3030 	strb.w	r3, [sp, #48]	; 0x30
		char sign = 0;
     ea2:	f8dd 9008 	ldr.w	r9, [sp, #8]
			bpe = buf + 1;
     ea6:	f10d 0b31 	add.w	fp, sp, #49	; 0x31
			bps = buf;
     eaa:	f10d 0a30 	add.w	sl, sp, #48	; 0x30
			break;
     eae:	e08b      	b.n	fc8 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x28>
		case 'd':
		case 'i':
			if (conv->flag_plus) {
     eb0:	f019 0f08 	tst.w	r9, #8
     eb4:	d105      	bne.n	ec2 <CONFIG_ISR_STACK_SIZE+0x6c2>
				sign = '+';
			} else if (conv->flag_space) {
     eb6:	f019 0910 	ands.w	r9, r9, #16
     eba:	d004      	beq.n	ec6 <CONFIG_ISR_STACK_SIZE+0x6c6>
				sign = ' ';
     ebc:	f04f 0920 	mov.w	r9, #32
     ec0:	e001      	b.n	ec6 <CONFIG_ISR_STACK_SIZE+0x6c6>
				sign = '+';
     ec2:	f04f 092b 	mov.w	r9, #43	; 0x2b

			/* sint/uint overlay in the union, and so
			 * can't appear in read and write operations
			 * in the same statement.
			 */
			sint = value->sint;
     ec6:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
			if (sint < 0) {
     eca:	2a00      	cmp	r2, #0
     ecc:	f173 0100 	sbcs.w	r1, r3, #0
     ed0:	db02      	blt.n	ed8 <CONFIG_ISR_STACK_SIZE+0x6d8>
				sign = '-';
				value->uint = (uint_value_type)-sint;
			} else {
				value->uint = (uint_value_type)sint;
     ed2:	e9cd 2306 	strd	r2, r3, [sp, #24]
     ed6:	e009      	b.n	eec <CONFIG_ISR_STACK_SIZE+0x6ec>
				value->uint = (uint_value_type)-sint;
     ed8:	4252      	negs	r2, r2
     eda:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
     ede:	e9cd 2306 	strd	r2, r3, [sp, #24]
				sign = '-';
     ee2:	f04f 092d 	mov.w	r9, #45	; 0x2d
     ee6:	e001      	b.n	eec <CONFIG_ISR_STACK_SIZE+0x6ec>
		switch (conv->specifier) {
     ee8:	f8dd 9008 	ldr.w	r9, [sp, #8]
			__fallthrough;
		case 'o':
		case 'u':
		case 'x':
		case 'X':
			bps = encode_uint(value->uint, conv, buf, bpe);
     eec:	f10d 0346 	add.w	r3, sp, #70	; 0x46
     ef0:	9300      	str	r3, [sp, #0]
     ef2:	ab0c      	add	r3, sp, #48	; 0x30
     ef4:	aa08      	add	r2, sp, #32
     ef6:	e9dd 0106 	ldrd	r0, r1, [sp, #24]
     efa:	f7ff fba7 	bl	64c <encode_uint>
     efe:	4682      	mov	sl, r0
			/* Update pad0 values based on precision and converted
			 * length.  Note that a non-empty sign is not in the
			 * converted sequence, but it does not affect the
			 * padding size.
			 */
			if (precision >= 0) {
     f00:	f1bb 0f00 	cmp.w	fp, #0
     f04:	f2c0 8090 	blt.w	1028 <CONFIG_FPROTECT_BLOCK_SIZE+0x28>
				size_t len = bpe - bps;
     f08:	f10d 0346 	add.w	r3, sp, #70	; 0x46
     f0c:	eba3 030a 	sub.w	r3, r3, sl

				/* Zero-padding flag is ignored for integer
				 * conversions with precision.
				 */
				conv->flag_zero = false;
     f10:	f89d 2020 	ldrb.w	r2, [sp, #32]
     f14:	f36f 1286 	bfc	r2, #6, #1
     f18:	f88d 2020 	strb.w	r2, [sp, #32]

				/* Set pad0_value to satisfy precision */
				if (len < (size_t)precision) {
     f1c:	459b      	cmp	fp, r3
     f1e:	f240 8086 	bls.w	102e <CONFIG_FPROTECT_BLOCK_SIZE+0x2e>
					conv->pad0_value = precision - (int)len;
     f22:	ebab 0303 	sub.w	r3, fp, r3
     f26:	9309      	str	r3, [sp, #36]	; 0x24
		const char *bpe = buf + sizeof(buf);
     f28:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
     f2c:	e04c      	b.n	fc8 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x28>
		case 'p':
			/* Implementation-defined: null is "(nil)", non-null
			 * has 0x prefix followed by significant address hex
			 * digits, no leading zeros.
			 */
			if (value->ptr != NULL) {
     f2e:	9806      	ldr	r0, [sp, #24]
     f30:	b930      	cbnz	r0, f40 <CONFIG_ISR_STACK_SIZE+0x740>
		char sign = 0;
     f32:	f8dd 9008 	ldr.w	r9, [sp, #8]

				goto prec_int_pad0;
			}

			bps = "(nil)";
			bpe = bps + 5;
     f36:	f8df b1c4 	ldr.w	fp, [pc, #452]	; 10fc <CONFIG_FPROTECT_BLOCK_SIZE+0xfc>
			bps = "(nil)";
     f3a:	f1ab 0a05 	sub.w	sl, fp, #5
     f3e:	e043      	b.n	fc8 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x28>
				bps = encode_uint((uintptr_t)value->ptr, conv,
     f40:	f10d 0346 	add.w	r3, sp, #70	; 0x46
     f44:	9300      	str	r3, [sp, #0]
     f46:	ab0c      	add	r3, sp, #48	; 0x30
     f48:	aa08      	add	r2, sp, #32
     f4a:	2100      	movs	r1, #0
     f4c:	f7ff fb7e 	bl	64c <encode_uint>
     f50:	4682      	mov	sl, r0
				conv->altform_0c = true;
     f52:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     f56:	f043 0310 	orr.w	r3, r3, #16
     f5a:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
				conv->specifier = 'x';
     f5e:	2378      	movs	r3, #120	; 0x78
     f60:	f88d 3023 	strb.w	r3, [sp, #35]	; 0x23
		char sign = 0;
     f64:	f8dd 9008 	ldr.w	r9, [sp, #8]
				goto prec_int_pad0;
     f68:	e7ca      	b.n	f00 <CONFIG_ISR_STACK_SIZE+0x700>

			break;
		case 'n':
			if (IS_ENABLED(CONFIG_CBPRINTF_N_SPECIFIER)) {
				store_count(conv, value->ptr, count);
     f6a:	9a06      	ldr	r2, [sp, #24]
	switch ((enum length_mod_enum)conv->length_mod) {
     f6c:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     f70:	f3c3 03c3 	ubfx	r3, r3, #3, #4
     f74:	2b07      	cmp	r3, #7
     f76:	d806      	bhi.n	f86 <CONFIG_ISR_STACK_SIZE+0x786>
     f78:	e8df f003 	tbb	[pc, r3]
     f7c:	100e0c04 	.word	0x100e0c04
     f80:	1e1c1712 	.word	0x1e1c1712
		*(int *)dp = count;
     f84:	6014      	str	r4, [r2, #0]
		char sign = 0;
     f86:	f8dd 9008 	ldr.w	r9, [sp, #8]
		const char *bpe = buf + sizeof(buf);
     f8a:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
		const char *bps = NULL;
     f8e:	f04f 0a00 	mov.w	sl, #0
}
     f92:	e019      	b.n	fc8 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x28>
		*(signed char *)dp = (signed char)count;
     f94:	7014      	strb	r4, [r2, #0]
		break;
     f96:	e7f6      	b.n	f86 <CONFIG_ISR_STACK_SIZE+0x786>
		*(short *)dp = (short)count;
     f98:	8014      	strh	r4, [r2, #0]
		break;
     f9a:	e7f4      	b.n	f86 <CONFIG_ISR_STACK_SIZE+0x786>
		*(long *)dp = (long)count;
     f9c:	6014      	str	r4, [r2, #0]
		break;
     f9e:	e7f2      	b.n	f86 <CONFIG_ISR_STACK_SIZE+0x786>
		*(long long *)dp = (long long)count;
     fa0:	4620      	mov	r0, r4
     fa2:	17e1      	asrs	r1, r4, #31
     fa4:	e9c2 0100 	strd	r0, r1, [r2]
		break;
     fa8:	e7ed      	b.n	f86 <CONFIG_ISR_STACK_SIZE+0x786>
		*(intmax_t *)dp = (intmax_t)count;
     faa:	4620      	mov	r0, r4
     fac:	17e1      	asrs	r1, r4, #31
     fae:	e9c2 0100 	strd	r0, r1, [r2]
		break;
     fb2:	e7e8      	b.n	f86 <CONFIG_ISR_STACK_SIZE+0x786>
		*(size_t *)dp = (size_t)count;
     fb4:	6014      	str	r4, [r2, #0]
		break;
     fb6:	e7e6      	b.n	f86 <CONFIG_ISR_STACK_SIZE+0x786>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
     fb8:	6014      	str	r4, [r2, #0]
		break;
     fba:	e7e4      	b.n	f86 <CONFIG_ISR_STACK_SIZE+0x786>
		switch (conv->specifier) {
     fbc:	f8dd 9008 	ldr.w	r9, [sp, #8]
     fc0:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
     fc4:	f04f 0a00 	mov.w	sl, #0
		}

		/* If we don't have a converted value to emit, move
		 * on.
		 */
		if (bps == NULL) {
     fc8:	f1ba 0f00 	cmp.w	sl, #0
     fcc:	f000 808e 	beq.w	10ec <CONFIG_FPROTECT_BLOCK_SIZE+0xec>
		 *   * any exponent content from the converted value
		 * * for non-FP:
		 *   * any pad0_prefix
		 *   * the converted value
		 */
		size_t nj_len = (bpe - bps);
     fd0:	ebab 020a 	sub.w	r2, fp, sl
		int pad_len = 0;

		if (sign != 0) {
     fd4:	f1b9 0f00 	cmp.w	r9, #0
     fd8:	d000      	beq.n	fdc <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x3c>
			nj_len += 1U;
     fda:	3201      	adds	r2, #1
		}

		if (conv->altform_0c) {
     fdc:	f89d 1022 	ldrb.w	r1, [sp, #34]	; 0x22
     fe0:	f011 0f10 	tst.w	r1, #16
     fe4:	d026      	beq.n	1034 <CONFIG_FPROTECT_BLOCK_SIZE+0x34>
			nj_len += 2U;
     fe6:	3202      	adds	r2, #2
		} else if (conv->altform_0) {
			nj_len += 1U;
		}

		nj_len += conv->pad0_value;
     fe8:	9b09      	ldr	r3, [sp, #36]	; 0x24
     fea:	4413      	add	r3, r2
		if (conv->pad_fp) {
     fec:	f011 0f40 	tst.w	r1, #64	; 0x40
     ff0:	d001      	beq.n	ff6 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x56>
			nj_len += conv->pad0_pre_exp;
     ff2:	9a0a      	ldr	r2, [sp, #40]	; 0x28
     ff4:	4413      	add	r3, r2
		 * result in no padding.
		 *
		 * If a non-negative padding width is present and we're doing
		 * right-justification, emit the padding now.
		 */
		if (width > 0) {
     ff6:	2f00      	cmp	r7, #0
     ff8:	dd32      	ble.n	1060 <CONFIG_FPROTECT_BLOCK_SIZE+0x60>
			width -= (int)nj_len;
     ffa:	1aff      	subs	r7, r7, r3

			if (!conv->flag_dash) {
     ffc:	f89d 3020 	ldrb.w	r3, [sp, #32]
    1000:	f013 0f04 	tst.w	r3, #4
    1004:	d12c      	bne.n	1060 <CONFIG_FPROTECT_BLOCK_SIZE+0x60>
				char pad = ' ';

				/* If we're zero-padding we have to emit the
				 * sign first.
				 */
				if (conv->flag_zero) {
    1006:	f013 0f40 	tst.w	r3, #64	; 0x40
    100a:	d018      	beq.n	103e <CONFIG_FPROTECT_BLOCK_SIZE+0x3e>
					if (sign != 0) {
    100c:	f1b9 0f00 	cmp.w	r9, #0
    1010:	d018      	beq.n	1044 <CONFIG_FPROTECT_BLOCK_SIZE+0x44>
						OUTC(sign);
    1012:	4629      	mov	r1, r5
    1014:	4648      	mov	r0, r9
    1016:	47b0      	blx	r6
    1018:	2800      	cmp	r0, #0
    101a:	db6b      	blt.n	10f4 <CONFIG_FPROTECT_BLOCK_SIZE+0xf4>
    101c:	3401      	adds	r4, #1
						sign = 0;
    101e:	f8dd 9008 	ldr.w	r9, [sp, #8]
					}
					pad = '0';
    1022:	2330      	movs	r3, #48	; 0x30
    1024:	9302      	str	r3, [sp, #8]
    1026:	e00f      	b.n	1048 <CONFIG_FPROTECT_BLOCK_SIZE+0x48>
		const char *bpe = buf + sizeof(buf);
    1028:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
    102c:	e7cc      	b.n	fc8 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x28>
    102e:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
    1032:	e7c9      	b.n	fc8 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x28>
		} else if (conv->altform_0) {
    1034:	f011 0f08 	tst.w	r1, #8
    1038:	d0d6      	beq.n	fe8 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x48>
			nj_len += 1U;
    103a:	3201      	adds	r2, #1
    103c:	e7d4      	b.n	fe8 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x48>
				char pad = ' ';
    103e:	2320      	movs	r3, #32
    1040:	9302      	str	r3, [sp, #8]
    1042:	e001      	b.n	1048 <CONFIG_FPROTECT_BLOCK_SIZE+0x48>
					pad = '0';
    1044:	2330      	movs	r3, #48	; 0x30
    1046:	9302      	str	r3, [sp, #8]
    1048:	463b      	mov	r3, r7
				}

				while (width-- > 0) {
    104a:	1e5f      	subs	r7, r3, #1
    104c:	2b00      	cmp	r3, #0
    104e:	dd07      	ble.n	1060 <CONFIG_FPROTECT_BLOCK_SIZE+0x60>
					OUTC(pad);
    1050:	4629      	mov	r1, r5
    1052:	9802      	ldr	r0, [sp, #8]
    1054:	47b0      	blx	r6
    1056:	2800      	cmp	r0, #0
    1058:	db4c      	blt.n	10f4 <CONFIG_FPROTECT_BLOCK_SIZE+0xf4>
    105a:	3401      	adds	r4, #1
				while (width-- > 0) {
    105c:	463b      	mov	r3, r7
    105e:	e7f4      	b.n	104a <CONFIG_FPROTECT_BLOCK_SIZE+0x4a>
		}

		/* If we have a sign that hasn't been emitted, now's the
		 * time....
		 */
		if (sign != 0) {
    1060:	f1b9 0f00 	cmp.w	r9, #0
    1064:	d005      	beq.n	1072 <CONFIG_FPROTECT_BLOCK_SIZE+0x72>
			OUTC(sign);
    1066:	4629      	mov	r1, r5
    1068:	4648      	mov	r0, r9
    106a:	47b0      	blx	r6
    106c:	2800      	cmp	r0, #0
    106e:	db41      	blt.n	10f4 <CONFIG_FPROTECT_BLOCK_SIZE+0xf4>
    1070:	3401      	adds	r4, #1
				OUTC('0');
			}

			OUTS(cp, bpe);
		} else {
			if (conv->altform_0c | conv->altform_0) {
    1072:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
    1076:	f3c3 1200 	ubfx	r2, r3, #4, #1
    107a:	f3c3 03c0 	ubfx	r3, r3, #3, #1
    107e:	4313      	orrs	r3, r2
    1080:	d005      	beq.n	108e <CONFIG_FPROTECT_BLOCK_SIZE+0x8e>
				OUTC('0');
    1082:	4629      	mov	r1, r5
    1084:	2030      	movs	r0, #48	; 0x30
    1086:	47b0      	blx	r6
    1088:	2800      	cmp	r0, #0
    108a:	db33      	blt.n	10f4 <CONFIG_FPROTECT_BLOCK_SIZE+0xf4>
    108c:	3401      	adds	r4, #1
			}

			if (conv->altform_0c) {
    108e:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
    1092:	f013 0f10 	tst.w	r3, #16
    1096:	d006      	beq.n	10a6 <CONFIG_FPROTECT_BLOCK_SIZE+0xa6>
				OUTC(conv->specifier);
    1098:	4629      	mov	r1, r5
    109a:	f89d 0023 	ldrb.w	r0, [sp, #35]	; 0x23
    109e:	47b0      	blx	r6
    10a0:	2800      	cmp	r0, #0
    10a2:	db27      	blt.n	10f4 <CONFIG_FPROTECT_BLOCK_SIZE+0xf4>
    10a4:	3401      	adds	r4, #1
			}

			pad_len = conv->pad0_value;
    10a6:	9b09      	ldr	r3, [sp, #36]	; 0x24
			while (pad_len-- > 0) {
    10a8:	f103 39ff 	add.w	r9, r3, #4294967295
    10ac:	2b00      	cmp	r3, #0
    10ae:	dd07      	ble.n	10c0 <CONFIG_FPROTECT_BLOCK_SIZE+0xc0>
				OUTC('0');
    10b0:	4629      	mov	r1, r5
    10b2:	2030      	movs	r0, #48	; 0x30
    10b4:	47b0      	blx	r6
    10b6:	2800      	cmp	r0, #0
    10b8:	db1c      	blt.n	10f4 <CONFIG_FPROTECT_BLOCK_SIZE+0xf4>
    10ba:	3401      	adds	r4, #1
			while (pad_len-- > 0) {
    10bc:	464b      	mov	r3, r9
    10be:	e7f3      	b.n	10a8 <CONFIG_FPROTECT_BLOCK_SIZE+0xa8>
			}

			OUTS(bps, bpe);
    10c0:	465b      	mov	r3, fp
    10c2:	4652      	mov	r2, sl
    10c4:	4629      	mov	r1, r5
    10c6:	4630      	mov	r0, r6
    10c8:	f003 fd8e 	bl	4be8 <outs>
    10cc:	2800      	cmp	r0, #0
    10ce:	db11      	blt.n	10f4 <CONFIG_FPROTECT_BLOCK_SIZE+0xf4>
    10d0:	4404      	add	r4, r0
		}

		/* Finish left justification */
		while (width > 0) {
    10d2:	2f00      	cmp	r7, #0
    10d4:	dd07      	ble.n	10e6 <CONFIG_FPROTECT_BLOCK_SIZE+0xe6>
			OUTC(' ');
    10d6:	4629      	mov	r1, r5
    10d8:	2020      	movs	r0, #32
    10da:	47b0      	blx	r6
    10dc:	2800      	cmp	r0, #0
    10de:	db09      	blt.n	10f4 <CONFIG_FPROTECT_BLOCK_SIZE+0xf4>
    10e0:	3401      	adds	r4, #1
			--width;
    10e2:	3f01      	subs	r7, #1
    10e4:	e7f5      	b.n	10d2 <CONFIG_FPROTECT_BLOCK_SIZE+0xd2>
		fp = extract_conversion(conv, sp);
    10e6:	46c2      	mov	sl, r8
    10e8:	f7ff bb28 	b.w	73c <cbvprintf+0x10>
    10ec:	46c2      	mov	sl, r8
    10ee:	f7ff bb25 	b.w	73c <cbvprintf+0x10>
		}
	}

	return count;
    10f2:	4620      	mov	r0, r4
#undef OUTS
#undef OUTC
}
    10f4:	b013      	add	sp, #76	; 0x4c
    10f6:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    10fa:	bf00      	nop
    10fc:	00005ae1 	.word	0x00005ae1

00001100 <__do_init_array_aux>:
 * @brief Execute initialization routines referenced in .init_array section
 *
 * @return N/A
 */
void __do_init_array_aux(void)
{
    1100:	b510      	push	{r4, lr}
	for (func_ptr *func = __init_array_start;
    1102:	4c04      	ldr	r4, [pc, #16]	; (1114 <__do_init_array_aux+0x14>)
    1104:	4b04      	ldr	r3, [pc, #16]	; (1118 <__do_init_array_aux+0x18>)
    1106:	429c      	cmp	r4, r3
    1108:	d203      	bcs.n	1112 <__do_init_array_aux+0x12>
		func < __init_array_end;
		func++) {
		(*func)();
    110a:	f854 3b04 	ldr.w	r3, [r4], #4
    110e:	4798      	blx	r3
		func++) {
    1110:	e7f8      	b.n	1104 <__do_init_array_aux+0x4>
	}
}
    1112:	bd10      	pop	{r4, pc}
    1114:	00005a5c 	.word	0x00005a5c
    1118:	00005a5c 	.word	0x00005a5c

0000111c <__do_global_ctors_aux>:
 */
void __do_global_ctors_aux(void)
{
	unsigned int nCtors;

	nCtors = (unsigned long)__CTOR_LIST__[0];
    111c:	4b06      	ldr	r3, [pc, #24]	; (1138 <__do_global_ctors_aux+0x1c>)
    111e:	681b      	ldr	r3, [r3, #0]

	while (nCtors >= 1U) {
    1120:	b14b      	cbz	r3, 1136 <__do_global_ctors_aux+0x1a>
{
    1122:	b510      	push	{r4, lr}
		__CTOR_LIST__[nCtors--]();
    1124:	1e5c      	subs	r4, r3, #1
    1126:	4a04      	ldr	r2, [pc, #16]	; (1138 <__do_global_ctors_aux+0x1c>)
    1128:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
    112c:	4798      	blx	r3
    112e:	4623      	mov	r3, r4
	while (nCtors >= 1U) {
    1130:	2c00      	cmp	r4, #0
    1132:	d1f7      	bne.n	1124 <__do_global_ctors_aux+0x8>
	}
}
    1134:	bd10      	pop	{r4, pc}
    1136:	4770      	bx	lr
    1138:	00005a54 	.word	0x00005a54

0000113c <pm_system_resume>:
	 * and it may schedule another thread.
	 *
	 * Call pm_idle_exit_notification_disable() if this
	 * notification is not required.
	 */
	if (!post_ops_done) {
    113c:	4b1b      	ldr	r3, [pc, #108]	; (11ac <pm_system_resume+0x70>)
    113e:	681b      	ldr	r3, [r3, #0]
    1140:	2b00      	cmp	r3, #0
    1142:	d132      	bne.n	11aa <pm_system_resume+0x6e>
{
    1144:	b530      	push	{r4, r5, lr}
    1146:	b085      	sub	sp, #20
		post_ops_done = 1;
    1148:	4b18      	ldr	r3, [pc, #96]	; (11ac <pm_system_resume+0x70>)
    114a:	2201      	movs	r2, #1
    114c:	601a      	str	r2, [r3, #0]
		exit_pos_ops(z_power_state);
    114e:	4b18      	ldr	r3, [pc, #96]	; (11b0 <pm_system_resume+0x74>)
    1150:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
    1154:	ab04      	add	r3, sp, #16
    1156:	e903 0007 	stmdb	r3, {r0, r1, r2}
	if (pm_power_state_exit_post_ops != NULL) {
    115a:	4b16      	ldr	r3, [pc, #88]	; (11b4 <pm_system_resume+0x78>)
    115c:	b163      	cbz	r3, 1178 <pm_system_resume+0x3c>
		pm_power_state_exit_post_ops(info);
    115e:	f003 ff61 	bl	5024 <pm_power_state_exit_post_ops>
    1162:	f04f 0320 	mov.w	r3, #32
    1166:	f3ef 8511 	mrs	r5, BASEPRI
    116a:	f383 8811 	msr	BASEPRI, r3
    116e:	f3bf 8f6f 	isb	sy
    1172:	4b11      	ldr	r3, [pc, #68]	; (11b8 <pm_system_resume+0x7c>)
    1174:	681c      	ldr	r4, [r3, #0]
    1176:	e00a      	b.n	118e <pm_system_resume+0x52>
	__asm__ volatile(
    1178:	2300      	movs	r3, #0
    117a:	f383 8811 	msr	BASEPRI, r3
    117e:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    1182:	e7ee      	b.n	1162 <pm_system_resume+0x26>
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    1184:	4623      	mov	r3, r4
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next(sys_snode_t *node);

Z_GENLIST_PEEK_NEXT(slist, snode)
    1186:	b10c      	cbz	r4, 118c <pm_system_resume+0x50>
	return node->next;
    1188:	6823      	ldr	r3, [r4, #0]
    118a:	b143      	cbz	r3, 119e <pm_system_resume+0x62>
{
    118c:	461c      	mov	r4, r3
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    118e:	b134      	cbz	r4, 119e <pm_system_resume+0x62>
			callback = notifier->state_exit;
    1190:	68a3      	ldr	r3, [r4, #8]
		if (callback) {
    1192:	2b00      	cmp	r3, #0
    1194:	d0f6      	beq.n	1184 <pm_system_resume+0x48>
			callback(z_power_state.state);
    1196:	4a06      	ldr	r2, [pc, #24]	; (11b0 <pm_system_resume+0x74>)
    1198:	7810      	ldrb	r0, [r2, #0]
    119a:	4798      	blx	r3
    119c:	e7f2      	b.n	1184 <pm_system_resume+0x48>
	__asm__ volatile(
    119e:	f385 8811 	msr	BASEPRI, r5
    11a2:	f3bf 8f6f 	isb	sy
		pm_state_notify(false);
	}
}
    11a6:	b005      	add	sp, #20
    11a8:	bd30      	pop	{r4, r5, pc}
    11aa:	4770      	bx	lr
    11ac:	20000004 	.word	0x20000004
    11b0:	20000290 	.word	0x20000290
    11b4:	00005025 	.word	0x00005025
    11b8:	20000288 	.word	0x20000288

000011bc <pm_system_suspend>:
	return PM_STATE_ACTIVE;
}
#endif

enum pm_state pm_system_suspend(int32_t ticks)
{
    11bc:	b570      	push	{r4, r5, r6, lr}
    11be:	b088      	sub	sp, #32
    11c0:	4606      	mov	r6, r0
	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);
	z_power_state = pm_policy_next_state(ticks);
    11c2:	4c2a      	ldr	r4, [pc, #168]	; (126c <pm_system_suspend+0xb0>)
    11c4:	466d      	mov	r5, sp
    11c6:	4601      	mov	r1, r0
    11c8:	4628      	mov	r0, r5
    11ca:	f003 fd28 	bl	4c1e <pm_policy_next_state>
    11ce:	e895 0007 	ldmia.w	r5, {r0, r1, r2}
    11d2:	e884 0007 	stmia.w	r4, {r0, r1, r2}
	if (z_power_state.state == PM_STATE_ACTIVE) {
    11d6:	7820      	ldrb	r0, [r4, #0]
    11d8:	2800      	cmp	r0, #0
    11da:	d045      	beq.n	1268 <pm_system_suspend+0xac>
		LOG_DBG("No PM operations done.");
		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks, z_power_state.state);
		return z_power_state.state;
	}
	post_ops_done = 0;
    11dc:	4b24      	ldr	r3, [pc, #144]	; (1270 <pm_system_suspend+0xb4>)
    11de:	2200      	movs	r2, #0
    11e0:	601a      	str	r2, [r3, #0]

	if (ticks != K_TICKS_FOREVER) {
    11e2:	f1b6 3fff 	cmp.w	r6, #4294967295
    11e6:	d10c      	bne.n	1202 <pm_system_suspend+0x46>
	 * state. We don't want to be scheduled out yet, first we need
	 * to send a notification about leaving the idle state. So,
	 * we lock the scheduler here and unlock just after we have
	 * sent the notification in pm_system_resume().
	 */
	k_sched_lock();
    11e8:	f002 fc5a 	bl	3aa0 <k_sched_lock>
	__asm__ volatile(
    11ec:	f04f 0320 	mov.w	r3, #32
    11f0:	f3ef 8511 	mrs	r5, BASEPRI
    11f4:	f383 8811 	msr	BASEPRI, r3
    11f8:	f3bf 8f6f 	isb	sy
	return list->head;
    11fc:	4b1d      	ldr	r3, [pc, #116]	; (1274 <pm_system_suspend+0xb8>)
    11fe:	681c      	ldr	r4, [r3, #0]
    1200:	e016      	b.n	1230 <pm_system_suspend+0x74>
		     k_us_to_ticks_ceil32(z_power_state.exit_latency_us), true);
    1202:	68a3      	ldr	r3, [r4, #8]
		} else {
			return t * ((uint64_t)to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    1204:	0c59      	lsrs	r1, r3, #17
    1206:	03d8      	lsls	r0, r3, #15
    1208:	4c1b      	ldr	r4, [pc, #108]	; (1278 <pm_system_suspend+0xbc>)
    120a:	4a1c      	ldr	r2, [pc, #112]	; (127c <pm_system_suspend+0xc0>)
    120c:	2300      	movs	r3, #0
    120e:	1900      	adds	r0, r0, r4
    1210:	f04f 0400 	mov.w	r4, #0
    1214:	eb44 0101 	adc.w	r1, r4, r1
    1218:	f7fe ff72 	bl	100 <__aeabi_uldivmod>
		z_set_timeout_expiry(ticks -
    121c:	2101      	movs	r1, #1
    121e:	1a30      	subs	r0, r6, r0
    1220:	f004 fa1e 	bl	5660 <z_set_timeout_expiry>
    1224:	e7e0      	b.n	11e8 <pm_system_suspend+0x2c>
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    1226:	4623      	mov	r3, r4
Z_GENLIST_PEEK_NEXT(slist, snode)
    1228:	b10c      	cbz	r4, 122e <pm_system_suspend+0x72>
	return node->next;
    122a:	6823      	ldr	r3, [r4, #0]
    122c:	b143      	cbz	r3, 1240 <pm_system_suspend+0x84>
{
    122e:	461c      	mov	r4, r3
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    1230:	b134      	cbz	r4, 1240 <pm_system_suspend+0x84>
			callback = notifier->state_entry;
    1232:	6863      	ldr	r3, [r4, #4]
		if (callback) {
    1234:	2b00      	cmp	r3, #0
    1236:	d0f6      	beq.n	1226 <pm_system_suspend+0x6a>
			callback(z_power_state.state);
    1238:	4a0c      	ldr	r2, [pc, #48]	; (126c <pm_system_suspend+0xb0>)
    123a:	7810      	ldrb	r0, [r2, #0]
    123c:	4798      	blx	r3
    123e:	e7f2      	b.n	1226 <pm_system_suspend+0x6a>
	__asm__ volatile(
    1240:	f385 8811 	msr	BASEPRI, r5
    1244:	f3bf 8f6f 	isb	sy
	pm_debug_start_timer();
	/* Enter power state */
	pm_state_notify(true);
	pm_state_set(z_power_state);
    1248:	4b08      	ldr	r3, [pc, #32]	; (126c <pm_system_suspend+0xb0>)
    124a:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
    124e:	ab08      	add	r3, sp, #32
    1250:	e903 0007 	stmdb	r3, {r0, r1, r2}
	if (pm_power_state_set != NULL) {
    1254:	4b0a      	ldr	r3, [pc, #40]	; (1280 <pm_system_suspend+0xc4>)
    1256:	b10b      	cbz	r3, 125c <pm_system_suspend+0xa0>
		pm_power_state_set(info);
    1258:	f003 fed1 	bl	4ffe <pm_power_state_set>
		/* Turn on peripherals and restore device states as necessary */
		pm_resume_devices();
	}
#endif
	pm_log_debug_info(z_power_state.state);
	pm_system_resume();
    125c:	f7ff ff6e 	bl	113c <pm_system_resume>
	k_sched_unlock();
    1260:	f002 fcce 	bl	3c00 <k_sched_unlock>
	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks, z_power_state.state);
	return z_power_state.state;
    1264:	4b01      	ldr	r3, [pc, #4]	; (126c <pm_system_suspend+0xb0>)
    1266:	7818      	ldrb	r0, [r3, #0]
}
    1268:	b008      	add	sp, #32
    126a:	bd70      	pop	{r4, r5, r6, pc}
    126c:	20000290 	.word	0x20000290
    1270:	20000004 	.word	0x20000004
    1274:	20000288 	.word	0x20000288
    1278:	000f423f 	.word	0x000f423f
    127c:	000f4240 	.word	0x000f4240
    1280:	00004fff 	.word	0x00004fff

00001284 <console_out>:
 *
 * @return The character passed as input.
 */

static int console_out(int c)
{
    1284:	b510      	push	{r4, lr}
    1286:	4604      	mov	r4, r0
		return c;
	}

#endif  /* CONFIG_UART_CONSOLE_DEBUG_SERVER_HOOKS */

	if ('\n' == c) {
    1288:	280a      	cmp	r0, #10
    128a:	d007      	beq.n	129c <console_out+0x18>
		uart_poll_out(uart_console_dev, '\r');
	}
	uart_poll_out(uart_console_dev, c);
    128c:	4b07      	ldr	r3, [pc, #28]	; (12ac <console_out+0x28>)
    128e:	6818      	ldr	r0, [r3, #0]
    1290:	b2e1      	uxtb	r1, r4
				      unsigned char out_char);

static inline void z_impl_uart_poll_out(const struct device *dev,
						unsigned char out_char)
{
	const struct uart_driver_api *api =
    1292:	6883      	ldr	r3, [r0, #8]
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    1294:	685b      	ldr	r3, [r3, #4]
    1296:	4798      	blx	r3

	return c;
}
    1298:	4620      	mov	r0, r4
    129a:	bd10      	pop	{r4, pc}
		uart_poll_out(uart_console_dev, '\r');
    129c:	4b03      	ldr	r3, [pc, #12]	; (12ac <console_out+0x28>)
    129e:	6818      	ldr	r0, [r3, #0]
	const struct uart_driver_api *api =
    12a0:	6883      	ldr	r3, [r0, #8]
	api->poll_out(dev, out_char);
    12a2:	685b      	ldr	r3, [r3, #4]
    12a4:	210d      	movs	r1, #13
    12a6:	4798      	blx	r3
		return;
	}
#endif
	compiler_barrier();
	z_impl_uart_poll_out(dev, out_char);
}
    12a8:	e7f0      	b.n	128c <console_out+0x8>
    12aa:	bf00      	nop
    12ac:	2000029c 	.word	0x2000029c

000012b0 <uart_console_hook_install>:
 *
 * @return N/A
 */

static void uart_console_hook_install(void)
{
    12b0:	b510      	push	{r4, lr}
	__stdout_hook_install(console_out);
    12b2:	4c04      	ldr	r4, [pc, #16]	; (12c4 <uart_console_hook_install+0x14>)
    12b4:	4620      	mov	r0, r4
    12b6:	f000 fe71 	bl	1f9c <__stdout_hook_install>
	__printk_hook_install(console_out);
    12ba:	4620      	mov	r0, r4
    12bc:	f7ff f8ee 	bl	49c <__printk_hook_install>
}
    12c0:	bd10      	pop	{r4, pc}
    12c2:	bf00      	nop
    12c4:	00001285 	.word	0x00001285

000012c8 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    12c8:	b508      	push	{r3, lr}
		/* coverity[OVERRUN] */
		return (const struct device *) arch_syscall_invoke1(*(uintptr_t *)&name, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
    12ca:	4804      	ldr	r0, [pc, #16]	; (12dc <uart_console_init+0x14>)
    12cc:	f001 ff32 	bl	3134 <z_impl_device_get_binding>

	ARG_UNUSED(arg);

	/* Claim console device */
	uart_console_dev = device_get_binding(CONFIG_UART_CONSOLE_ON_DEV_NAME);
    12d0:	4b03      	ldr	r3, [pc, #12]	; (12e0 <uart_console_init+0x18>)
    12d2:	6018      	str	r0, [r3, #0]

	uart_console_hook_install();
    12d4:	f7ff ffec 	bl	12b0 <uart_console_hook_install>

	return 0;
}
    12d8:	2000      	movs	r0, #0
    12da:	bd08      	pop	{r3, pc}
    12dc:	00005ae4 	.word	0x00005ae4
    12e0:	2000029c 	.word	0x2000029c

000012e4 <get_hf_flags>:
static uint32_t *get_hf_flags(void)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;

	return &data->subsys[CLOCK_CONTROL_NRF_TYPE_HFCLK].flags;
}
    12e4:	4800      	ldr	r0, [pc, #0]	; (12e8 <get_hf_flags+0x4>)
    12e6:	4770      	bx	lr
    12e8:	200002fc 	.word	0x200002fc

000012ec <get_subsys>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    12ec:	4b01      	ldr	r3, [pc, #4]	; (12f4 <get_subsys+0x8>)
    12ee:	1ac0      	subs	r0, r0, r3

	return (clock_control_subsys_t)offset;
}
    12f0:	1140      	asrs	r0, r0, #5
    12f2:	4770      	bx	lr
    12f4:	200002b4 	.word	0x200002b4

000012f8 <onoff_stop>:

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    12f8:	b538      	push	{r3, r4, r5, lr}
    12fa:	4605      	mov	r5, r0
    12fc:	460c      	mov	r4, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    12fe:	f7ff fff5 	bl	12ec <get_subsys>
    1302:	4601      	mov	r1, r0
    1304:	2240      	movs	r2, #64	; 0x40
    1306:	4803      	ldr	r0, [pc, #12]	; (1314 <onoff_stop+0x1c>)
    1308:	f003 fd03 	bl	4d12 <stop>
    130c:	4601      	mov	r1, r0
	notify(mgr, res);
    130e:	4628      	mov	r0, r5
    1310:	47a0      	blx	r4
}
    1312:	bd38      	pop	{r3, r4, r5, pc}
    1314:	00005844 	.word	0x00005844

00001318 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    1318:	b530      	push	{r4, r5, lr}
    131a:	b083      	sub	sp, #12
    131c:	4605      	mov	r5, r0
    131e:	460c      	mov	r4, r1
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1320:	f7ff ffe4 	bl	12ec <get_subsys>
    1324:	4601      	mov	r1, r0
    1326:	2340      	movs	r3, #64	; 0x40
    1328:	9300      	str	r3, [sp, #0]
    132a:	4623      	mov	r3, r4
    132c:	4a05      	ldr	r2, [pc, #20]	; (1344 <onoff_start+0x2c>)
    132e:	4806      	ldr	r0, [pc, #24]	; (1348 <onoff_start+0x30>)
    1330:	f003 fd09 	bl	4d46 <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    1334:	1e01      	subs	r1, r0, #0
    1336:	db01      	blt.n	133c <onoff_start+0x24>
		notify(mgr, err);
	}
}
    1338:	b003      	add	sp, #12
    133a:	bd30      	pop	{r4, r5, pc}
		notify(mgr, err);
    133c:	4628      	mov	r0, r5
    133e:	47a0      	blx	r4
}
    1340:	e7fa      	b.n	1338 <onoff_start+0x20>
    1342:	bf00      	nop
    1344:	00004d8f 	.word	0x00004d8f
    1348:	00005844 	.word	0x00005844

0000134c <generic_hfclk_start>:
{
    134c:	b510      	push	{r4, lr}
	__asm__ volatile(
    134e:	f04f 0320 	mov.w	r3, #32
    1352:	f3ef 8411 	mrs	r4, BASEPRI
    1356:	f383 8811 	msr	BASEPRI, r3
    135a:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    135e:	4a13      	ldr	r2, [pc, #76]	; (13ac <generic_hfclk_start+0x60>)
    1360:	6813      	ldr	r3, [r2, #0]
    1362:	f043 0302 	orr.w	r3, r3, #2
    1366:	6013      	str	r3, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    1368:	f013 0f01 	tst.w	r3, #1
    136c:	d108      	bne.n	1380 <generic_hfclk_start+0x34>
	bool already_started = false;
    136e:	2300      	movs	r3, #0
	__asm__ volatile(
    1370:	f384 8811 	msr	BASEPRI, r4
    1374:	f3bf 8f6f 	isb	sy
	if (already_started) {
    1378:	b99b      	cbnz	r3, 13a2 <generic_hfclk_start+0x56>
	hfclk_start();
    137a:	f003 fd10 	bl	4d9e <hfclk_start>
}
    137e:	bd10      	pop	{r4, pc}
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    1380:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1384:	f8d3 240c 	ldr.w	r2, [r3, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    1388:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    138c:	f012 0f01 	tst.w	r2, #1
    1390:	d101      	bne.n	1396 <generic_hfclk_start+0x4a>
	bool already_started = false;
    1392:	2300      	movs	r3, #0
    1394:	e7ec      	b.n	1370 <generic_hfclk_start+0x24>
			set_on_state(get_hf_flags());
    1396:	f7ff ffa5 	bl	12e4 <get_hf_flags>
    139a:	f003 fc95 	bl	4cc8 <set_on_state>
			already_started = true;
    139e:	2301      	movs	r3, #1
    13a0:	e7e6      	b.n	1370 <generic_hfclk_start+0x24>
		clkstarted_handle(CLOCK_DEVICE,
    13a2:	2100      	movs	r1, #0
    13a4:	4802      	ldr	r0, [pc, #8]	; (13b0 <generic_hfclk_start+0x64>)
    13a6:	f003 fca2 	bl	4cee <clkstarted_handle>
		return;
    13aa:	e7e8      	b.n	137e <generic_hfclk_start+0x32>
    13ac:	2000030c 	.word	0x2000030c
    13b0:	00005844 	.word	0x00005844

000013b4 <generic_hfclk_stop>:
{
    13b4:	b508      	push	{r3, lr}
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    13b6:	4b0a      	ldr	r3, [pc, #40]	; (13e0 <generic_hfclk_stop+0x2c>)
    13b8:	f3bf 8f5b 	dmb	ish
    13bc:	e853 2f00 	ldrex	r2, [r3]
    13c0:	f022 0102 	bic.w	r1, r2, #2
    13c4:	e843 1000 	strex	r0, r1, [r3]
    13c8:	2800      	cmp	r0, #0
    13ca:	d1f7      	bne.n	13bc <generic_hfclk_stop+0x8>
    13cc:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    13d0:	f012 0f01 	tst.w	r2, #1
    13d4:	d000      	beq.n	13d8 <generic_hfclk_stop+0x24>
}
    13d6:	bd08      	pop	{r3, pc}
	hfclk_stop();
    13d8:	f003 fceb 	bl	4db2 <hfclk_stop>
    13dc:	e7fb      	b.n	13d6 <generic_hfclk_stop+0x22>
    13de:	bf00      	nop
    13e0:	2000030c 	.word	0x2000030c

000013e4 <api_blocking_start>:
{
    13e4:	b500      	push	{lr}
    13e6:	b085      	sub	sp, #20
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    13e8:	f8cd d000 	str.w	sp, [sp]
    13ec:	f8cd d004 	str.w	sp, [sp, #4]
    13f0:	2300      	movs	r3, #0
    13f2:	9302      	str	r3, [sp, #8]
    13f4:	2301      	movs	r3, #1
    13f6:	9303      	str	r3, [sp, #12]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    13f8:	466b      	mov	r3, sp
    13fa:	4a07      	ldr	r2, [pc, #28]	; (1418 <api_blocking_start+0x34>)
    13fc:	f003 fcbf 	bl	4d7e <api_start>
	if (err < 0) {
    1400:	2800      	cmp	r0, #0
    1402:	db05      	blt.n	1410 <api_blocking_start+0x2c>
		/* coverity[OVERRUN] */
		return (int) arch_syscall_invoke3(*(uintptr_t *)&sem, parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    1404:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    1408:	2300      	movs	r3, #0
    140a:	4668      	mov	r0, sp
    140c:	f002 f93a 	bl	3684 <z_impl_k_sem_take>
}
    1410:	b005      	add	sp, #20
    1412:	f85d fb04 	ldr.w	pc, [sp], #4
    1416:	bf00      	nop
    1418:	00004dbd 	.word	0x00004dbd

0000141c <clk_init>:
#endif /* NRF_CLOCK_HAS_HFCLKAUDIO */
#endif
}

static int clk_init(const struct device *dev)
{
    141c:	b570      	push	{r4, r5, r6, lr}
    141e:	4605      	mov	r5, r0
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1420:	2200      	movs	r2, #0
    1422:	2101      	movs	r1, #1
    1424:	4610      	mov	r0, r2
    1426:	f000 fb1b 	bl	1a60 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);
	irq_enable(DT_INST_IRQN(0));
    142a:	2000      	movs	r0, #0
    142c:	f000 fafa 	bl	1a24 <arch_irq_enable>

	nrfx_err = nrfx_clock_init(clock_event_handler);
    1430:	4813      	ldr	r0, [pc, #76]	; (1480 <clk_init+0x64>)
    1432:	f001 fc59 	bl	2ce8 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    1436:	4b13      	ldr	r3, [pc, #76]	; (1484 <clk_init+0x68>)
    1438:	4298      	cmp	r0, r3
    143a:	d11d      	bne.n	1478 <clk_init+0x5c>

	if (IS_ENABLED(CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION) &&
	    !IS_ENABLED(CONFIG_CLOCK_CONTROL_NRF_FORCE_ALT)) {
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
    143c:	6928      	ldr	r0, [r5, #16]
    143e:	f000 f993 	bl	1768 <z_nrf_clock_calibration_init>
	}

	nrfx_clock_enable();
    1442:	f003 fe66 	bl	5112 <nrfx_clock_enable>

	for (enum clock_control_nrf_type i = 0;
    1446:	2400      	movs	r4, #0
    1448:	e003      	b.n	1452 <clk_init+0x36>
					 &transitions);
		if (err < 0) {
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    144a:	2301      	movs	r3, #1
    144c:	60b3      	str	r3, [r6, #8]
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
    144e:	441c      	add	r4, r3
    1450:	b2e4      	uxtb	r4, r4
	for (enum clock_control_nrf_type i = 0;
    1452:	2c01      	cmp	r4, #1
    1454:	d80e      	bhi.n	1474 <clk_init+0x58>
						get_sub_data(dev, i);
    1456:	4621      	mov	r1, r4
    1458:	4628      	mov	r0, r5
    145a:	f003 fbe5 	bl	4c28 <get_sub_data>
    145e:	4606      	mov	r6, r0
		err = onoff_manager_init(get_onoff_manager(dev, i),
    1460:	4621      	mov	r1, r4
    1462:	4628      	mov	r0, r5
    1464:	f003 fbeb 	bl	4c3e <get_onoff_manager>
    1468:	4907      	ldr	r1, [pc, #28]	; (1488 <clk_init+0x6c>)
    146a:	f003 fb15 	bl	4a98 <onoff_manager_init>
		if (err < 0) {
    146e:	2800      	cmp	r0, #0
    1470:	daeb      	bge.n	144a <clk_init+0x2e>
    1472:	e000      	b.n	1476 <clk_init+0x5a>
	}

	return 0;
    1474:	2000      	movs	r0, #0
}
    1476:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    1478:	f06f 0004 	mvn.w	r0, #4
    147c:	e7fb      	b.n	1476 <clk_init+0x5a>
    147e:	bf00      	nop
    1480:	0000148d 	.word	0x0000148d
    1484:	0bad0000 	.word	0x0bad0000
    1488:	00005b18 	.word	0x00005b18

0000148c <clock_event_handler>:
{
    148c:	b508      	push	{r3, lr}
	switch (event) {
    148e:	2801      	cmp	r0, #1
    1490:	d010      	beq.n	14b4 <clock_event_handler+0x28>
    1492:	2803      	cmp	r0, #3
    1494:	d015      	beq.n	14c2 <clock_event_handler+0x36>
    1496:	b100      	cbz	r0, 149a <clock_event_handler+0xe>
}
    1498:	bd08      	pop	{r3, pc}
				get_sub_data(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK);
    149a:	2100      	movs	r1, #0
    149c:	480a      	ldr	r0, [pc, #40]	; (14c8 <clock_event_handler+0x3c>)
    149e:	f003 fbc3 	bl	4c28 <get_sub_data>
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    14a2:	6883      	ldr	r3, [r0, #8]
    14a4:	f013 0f07 	tst.w	r3, #7
    14a8:	d1f6      	bne.n	1498 <clock_event_handler+0xc>
			clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK);
    14aa:	2100      	movs	r1, #0
    14ac:	4806      	ldr	r0, [pc, #24]	; (14c8 <clock_event_handler+0x3c>)
    14ae:	f003 fc1e 	bl	4cee <clkstarted_handle>
    14b2:	e7f1      	b.n	1498 <clock_event_handler+0xc>
			z_nrf_clock_calibration_lfclk_started();
    14b4:	f003 fc9f 	bl	4df6 <z_nrf_clock_calibration_lfclk_started>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    14b8:	2101      	movs	r1, #1
    14ba:	4803      	ldr	r0, [pc, #12]	; (14c8 <clock_event_handler+0x3c>)
    14bc:	f003 fc17 	bl	4cee <clkstarted_handle>
		break;
    14c0:	e7ea      	b.n	1498 <clock_event_handler+0xc>
			z_nrf_clock_calibration_done_handler();
    14c2:	f000 f967 	bl	1794 <z_nrf_clock_calibration_done_handler>
}
    14c6:	e7e7      	b.n	1498 <clock_event_handler+0xc>
    14c8:	00005844 	.word	0x00005844

000014cc <lfclk_spinwait>:
{
    14cc:	b570      	push	{r4, r5, r6, lr}
    14ce:	4605      	mov	r5, r0
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    14d0:	f003 fe6e 	bl	51b0 <k_is_in_isr>
    14d4:	b920      	cbnz	r0, 14e0 <lfclk_spinwait+0x14>
 */
static inline bool k_is_pre_kernel(void)
{
	extern bool z_sys_post_kernel; /* in init.c */

	return !z_sys_post_kernel;
    14d6:	4b21      	ldr	r3, [pc, #132]	; (155c <lfclk_spinwait+0x90>)
    14d8:	781b      	ldrb	r3, [r3, #0]
    14da:	b19b      	cbz	r3, 1504 <lfclk_spinwait+0x38>
    14dc:	2300      	movs	r3, #0
    14de:	e000      	b.n	14e2 <lfclk_spinwait+0x16>
    14e0:	2301      	movs	r3, #1
	int key = isr_mode ? irq_lock() : 0;
    14e2:	461c      	mov	r4, r3
    14e4:	b183      	cbz	r3, 1508 <lfclk_spinwait+0x3c>
	__asm__ volatile(
    14e6:	f04f 0320 	mov.w	r3, #32
    14ea:	f3ef 8611 	mrs	r6, BASEPRI
    14ee:	f383 8811 	msr	BASEPRI, r3
    14f2:	f3bf 8f6f 	isb	sy
	if (!isr_mode) {
    14f6:	b96c      	cbnz	r4, 1514 <lfclk_spinwait+0x48>
    p_reg->INTENCLR = mask;
    14f8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    14fc:	2202      	movs	r2, #2
    14fe:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
    1502:	e007      	b.n	1514 <lfclk_spinwait+0x48>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    1504:	2301      	movs	r3, #1
    1506:	e7ec      	b.n	14e2 <lfclk_spinwait+0x16>
	int key = isr_mode ? irq_lock() : 0;
    1508:	2600      	movs	r6, #0
    150a:	e7f4      	b.n	14f6 <lfclk_spinwait+0x2a>
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    150c:	b1cc      	cbz	r4, 1542 <lfclk_spinwait+0x76>
 *
 * @return N/A
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    150e:	4630      	mov	r0, r6
    1510:	f000 fb00 	bl	1b14 <arch_cpu_atomic_idle>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    1514:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    1518:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    151c:	f003 0303 	and.w	r3, r3, #3
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    1520:	f8d2 2418 	ldr.w	r2, [r2, #1048]	; 0x418
    1524:	f412 3f80 	tst.w	r2, #65536	; 0x10000
    1528:	d110      	bne.n	154c <lfclk_spinwait+0x80>
#endif
        default:
            NRFX_ASSERT(0);
            return false;
    }
    return false;
    152a:	2200      	movs	r2, #0
	while (!(nrfx_clock_is_running(d, (void *)&type)
    152c:	2a00      	cmp	r2, #0
    152e:	d0ed      	beq.n	150c <lfclk_spinwait+0x40>
    1530:	b10b      	cbz	r3, 1536 <lfclk_spinwait+0x6a>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    1532:	2d01      	cmp	r5, #1
    1534:	d1ea      	bne.n	150c <lfclk_spinwait+0x40>
	if (isr_mode) {
    1536:	b15c      	cbz	r4, 1550 <lfclk_spinwait+0x84>
	__asm__ volatile(
    1538:	f386 8811 	msr	BASEPRI, r6
    153c:	f3bf 8f6f 	isb	sy
}
    1540:	bd70      	pop	{r4, r5, r6, pc}
	return z_impl_k_sleep(timeout);
    1542:	2021      	movs	r0, #33	; 0x21
    1544:	2100      	movs	r1, #0
    1546:	f002 fdbb 	bl	40c0 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    154a:	e7e3      	b.n	1514 <lfclk_spinwait+0x48>
                return true;
    154c:	2201      	movs	r2, #1
    154e:	e7ed      	b.n	152c <lfclk_spinwait+0x60>
    p_reg->INTENSET = mask;
    1550:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1554:	2202      	movs	r2, #2
    1556:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    155a:	e7f1      	b.n	1540 <lfclk_spinwait+0x74>
    155c:	2000094d 	.word	0x2000094d

00001560 <z_nrf_clock_control_get_onoff>:
{
    1560:	b508      	push	{r3, lr}
	return get_onoff_manager(CLOCK_DEVICE,
    1562:	b2c1      	uxtb	r1, r0
    1564:	4801      	ldr	r0, [pc, #4]	; (156c <z_nrf_clock_control_get_onoff+0xc>)
    1566:	f003 fb6a 	bl	4c3e <get_onoff_manager>
}
    156a:	bd08      	pop	{r3, pc}
    156c:	00005844 	.word	0x00005844

00001570 <z_nrf_clock_control_lf_on>:
{
    1570:	b510      	push	{r4, lr}
    1572:	4604      	mov	r4, r0
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    1574:	4b10      	ldr	r3, [pc, #64]	; (15b8 <z_nrf_clock_control_lf_on+0x48>)
    1576:	2101      	movs	r1, #1
    1578:	f3bf 8f5b 	dmb	ish
    157c:	e853 2f00 	ldrex	r2, [r3]
    1580:	e843 1000 	strex	r0, r1, [r3]
    1584:	2800      	cmp	r0, #0
    1586:	d1f9      	bne.n	157c <z_nrf_clock_control_lf_on+0xc>
    1588:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    158c:	b11a      	cbz	r2, 1596 <z_nrf_clock_control_lf_on+0x26>
	switch (start_mode) {
    158e:	1e63      	subs	r3, r4, #1
    1590:	2b01      	cmp	r3, #1
    1592:	d90c      	bls.n	15ae <z_nrf_clock_control_lf_on+0x3e>
}
    1594:	bd10      	pop	{r4, pc}
				get_onoff_manager(CLOCK_DEVICE,
    1596:	4809      	ldr	r0, [pc, #36]	; (15bc <z_nrf_clock_control_lf_on+0x4c>)
    1598:	f003 fb51 	bl	4c3e <get_onoff_manager>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    159c:	4908      	ldr	r1, [pc, #32]	; (15c0 <z_nrf_clock_control_lf_on+0x50>)
    159e:	2300      	movs	r3, #0
    15a0:	604b      	str	r3, [r1, #4]
    15a2:	60cb      	str	r3, [r1, #12]
    15a4:	2301      	movs	r3, #1
    15a6:	608b      	str	r3, [r1, #8]
		err = onoff_request(mgr, &cli);
    15a8:	f003 fa92 	bl	4ad0 <onoff_request>
    15ac:	e7ef      	b.n	158e <z_nrf_clock_control_lf_on+0x1e>
		lfclk_spinwait(start_mode);
    15ae:	4620      	mov	r0, r4
    15b0:	f7ff ff8c 	bl	14cc <lfclk_spinwait>
		break;
    15b4:	e7ee      	b.n	1594 <z_nrf_clock_control_lf_on+0x24>
    15b6:	bf00      	nop
    15b8:	20000310 	.word	0x20000310
    15bc:	00005844 	.word	0x00005844
    15c0:	200002a4 	.word	0x200002a4

000015c4 <get_temperature>:
	return (int16_t)(4 * val->val1 + val->val2 / 250000);
}

/* Function reads from temperature sensor and converts to 0.25'C units. */
static int get_temperature(int16_t *tvp)
{
    15c4:	b510      	push	{r4, lr}
    15c6:	b082      	sub	sp, #8
    15c8:	4604      	mov	r4, r0
	struct sensor_value sensor_val;
	int rc = sensor_sample_fetch(temp_sensor);
    15ca:	4b0e      	ldr	r3, [pc, #56]	; (1604 <get_temperature+0x40>)
    15cc:	6818      	ldr	r0, [r3, #0]
 */
__syscall int sensor_sample_fetch(const struct device *dev);

static inline int z_impl_sensor_sample_fetch(const struct device *dev)
{
	const struct sensor_driver_api *api =
    15ce:	6883      	ldr	r3, [r0, #8]
		(const struct sensor_driver_api *)dev->api;

	return api->sample_fetch(dev, SENSOR_CHAN_ALL);
    15d0:	68db      	ldr	r3, [r3, #12]
    15d2:	2138      	movs	r1, #56	; 0x38
    15d4:	4798      	blx	r3

	if (rc == 0) {
    15d6:	b930      	cbnz	r0, 15e6 <get_temperature+0x22>
		rc = sensor_channel_get(temp_sensor, SENSOR_CHAN_DIE_TEMP,
    15d8:	4b0a      	ldr	r3, [pc, #40]	; (1604 <get_temperature+0x40>)
    15da:	6818      	ldr	r0, [r3, #0]

static inline int z_impl_sensor_channel_get(const struct device *dev,
					    enum sensor_channel chan,
					    struct sensor_value *val)
{
	const struct sensor_driver_api *api =
    15dc:	6883      	ldr	r3, [r0, #8]
		(const struct sensor_driver_api *)dev->api;

	return api->channel_get(dev, chan, val);
    15de:	691b      	ldr	r3, [r3, #16]
    15e0:	466a      	mov	r2, sp
    15e2:	210c      	movs	r1, #12
    15e4:	4798      	blx	r3
					&sensor_val);
	}
	if (rc == 0) {
    15e6:	b950      	cbnz	r0, 15fe <get_temperature+0x3a>
	return (int16_t)(4 * val->val1 + val->val2 / 250000);
    15e8:	9b01      	ldr	r3, [sp, #4]
    15ea:	4a07      	ldr	r2, [pc, #28]	; (1608 <get_temperature+0x44>)
    15ec:	fb82 1203 	smull	r1, r2, r2, r3
    15f0:	17db      	asrs	r3, r3, #31
    15f2:	ebc3 4322 	rsb	r3, r3, r2, asr #16
    15f6:	9a00      	ldr	r2, [sp, #0]
    15f8:	eb03 0382 	add.w	r3, r3, r2, lsl #2
		*tvp = sensor_value_to_temp_unit(&sensor_val);
    15fc:	8023      	strh	r3, [r4, #0]
	}
	return rc;
}
    15fe:	b002      	add	sp, #8
    1600:	bd10      	pop	{r4, pc}
    1602:	bf00      	nop
    1604:	2000032c 	.word	0x2000032c
    1608:	431bde83 	.word	0x431bde83

0000160c <hf_release>:
{
    160c:	b508      	push	{r3, lr}
	clk_release(&mgrs[CLOCK_CONTROL_NRF_TYPE_HFCLK]);
    160e:	4b02      	ldr	r3, [pc, #8]	; (1618 <hf_release+0xc>)
    1610:	6818      	ldr	r0, [r3, #0]
    1612:	f003 fbdf 	bl	4dd4 <clk_release>
}
    1616:	bd08      	pop	{r3, pc}
    1618:	20000328 	.word	0x20000328

0000161c <start_cycle>:
{
    161c:	b500      	push	{lr}
    161e:	b083      	sub	sp, #12
	z_impl_k_timer_start(timer, duration, period);
    1620:	2200      	movs	r2, #0
    1622:	2300      	movs	r3, #0
    1624:	e9cd 2300 	strd	r2, r3, [sp]
    1628:	f44f 3200 	mov.w	r2, #131072	; 0x20000
    162c:	2300      	movs	r3, #0
    162e:	4805      	ldr	r0, [pc, #20]	; (1644 <start_cycle+0x28>)
    1630:	f002 ff7a 	bl	4528 <z_impl_k_timer_start>
	hf_release();
    1634:	f7ff ffea 	bl	160c <hf_release>
	cal_process_in_progress = 0;
    1638:	4b03      	ldr	r3, [pc, #12]	; (1648 <start_cycle+0x2c>)
    163a:	2200      	movs	r2, #0
    163c:	601a      	str	r2, [r3, #0]
}
    163e:	b003      	add	sp, #12
    1640:	f85d fb04 	ldr.w	pc, [sp], #4
    1644:	200000a8 	.word	0x200000a8
    1648:	20000314 	.word	0x20000314

0000164c <start_hw_cal>:
{
    164c:	b508      	push	{r3, lr}
		*(volatile uint32_t *)0x40000C34 = 0x00000002;
    164e:	4b04      	ldr	r3, [pc, #16]	; (1660 <start_hw_cal+0x14>)
    1650:	2202      	movs	r2, #2
    1652:	601a      	str	r2, [r3, #0]
	nrfx_clock_calibration_start();
    1654:	f001 fc02 	bl	2e5c <nrfx_clock_calibration_start>
	calib_skip_cnt = CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP;
    1658:	4b02      	ldr	r3, [pc, #8]	; (1664 <start_hw_cal+0x18>)
    165a:	2201      	movs	r2, #1
    165c:	701a      	strb	r2, [r3, #0]
}
    165e:	bd08      	pop	{r3, pc}
    1660:	40000c34 	.word	0x40000c34
    1664:	2000094a 	.word	0x2000094a

00001668 <cal_hf_callback>:
{
    1668:	b508      	push	{r3, lr}
	if ((temp_sensor == NULL) || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    166a:	4b05      	ldr	r3, [pc, #20]	; (1680 <cal_hf_callback+0x18>)
    166c:	681b      	ldr	r3, [r3, #0]
    166e:	b11b      	cbz	r3, 1678 <cal_hf_callback+0x10>
		k_work_submit(&temp_measure_work);
    1670:	4804      	ldr	r0, [pc, #16]	; (1684 <cal_hf_callback+0x1c>)
    1672:	f002 f951 	bl	3918 <k_work_submit>
}
    1676:	bd08      	pop	{r3, pc}
		start_hw_cal();
    1678:	f7ff ffe8 	bl	164c <start_hw_cal>
    167c:	e7fb      	b.n	1676 <cal_hf_callback+0xe>
    167e:	bf00      	nop
    1680:	2000032c 	.word	0x2000032c
    1684:	20000008 	.word	0x20000008

00001688 <measure_temperature>:
/* Function determines if calibration should be performed based on temperature
 * measurement. Function is called from system work queue context. It is
 * reading temperature from TEMP sensor and compares with last measurement.
 */
static void measure_temperature(struct k_work *work)
{
    1688:	b500      	push	{lr}
    168a:	b083      	sub	sp, #12
	int16_t temperature = 0;
    168c:	2300      	movs	r3, #0
    168e:	f8ad 3006 	strh.w	r3, [sp, #6]
	int16_t diff = 0;
	bool started = false;
	int rc;

	rc = get_temperature(&temperature);
    1692:	f10d 0006 	add.w	r0, sp, #6
    1696:	f7ff ff95 	bl	15c4 <get_temperature>

	if (rc != 0) {
    169a:	b180      	cbz	r0, 16be <measure_temperature+0x36>
		/* Temperature read failed, force calibration. */
		calib_skip_cnt = 0;
    169c:	2000      	movs	r0, #0
    169e:	4b12      	ldr	r3, [pc, #72]	; (16e8 <measure_temperature+0x60>)
    16a0:	7018      	strb	r0, [r3, #0]
	} else {
		diff = abs(temperature - prev_temperature);
	}

	if ((calib_skip_cnt == 0) ||
    16a2:	4b11      	ldr	r3, [pc, #68]	; (16e8 <measure_temperature+0x60>)
    16a4:	781b      	ldrb	r3, [r3, #0]
    16a6:	b10b      	cbz	r3, 16ac <measure_temperature+0x24>
    16a8:	2801      	cmp	r0, #1
    16aa:	dd12      	ble.n	16d2 <measure_temperature+0x4a>
		(diff >= CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_TEMP_DIFF)) {
		prev_temperature = temperature;
    16ac:	4b0f      	ldr	r3, [pc, #60]	; (16ec <measure_temperature+0x64>)
    16ae:	f8bd 2006 	ldrh.w	r2, [sp, #6]
    16b2:	801a      	strh	r2, [r3, #0]
		started = true;
		start_hw_cal();
    16b4:	f7ff ffca 	bl	164c <start_hw_cal>
		start_cycle();
	}

	LOG_DBG("Calibration %s. Temperature diff: %d (in 0.25'C units).",
			started ? "started" : "skipped", diff);
}
    16b8:	b003      	add	sp, #12
    16ba:	f85d fb04 	ldr.w	pc, [sp], #4
		diff = abs(temperature - prev_temperature);
    16be:	f9bd 0006 	ldrsh.w	r0, [sp, #6]
    16c2:	4b0a      	ldr	r3, [pc, #40]	; (16ec <measure_temperature+0x64>)
    16c4:	f9b3 3000 	ldrsh.w	r3, [r3]
    16c8:	1ac0      	subs	r0, r0, r3
    16ca:	f004 f834 	bl	5736 <abs>
    16ce:	b200      	sxth	r0, r0
    16d0:	e7e7      	b.n	16a2 <measure_temperature+0x1a>
		calib_skip_cnt--;
    16d2:	3b01      	subs	r3, #1
    16d4:	4a04      	ldr	r2, [pc, #16]	; (16e8 <measure_temperature+0x60>)
    16d6:	7013      	strb	r3, [r2, #0]
		total_skips_cnt++;
    16d8:	4a05      	ldr	r2, [pc, #20]	; (16f0 <measure_temperature+0x68>)
    16da:	6813      	ldr	r3, [r2, #0]
    16dc:	3301      	adds	r3, #1
    16de:	6013      	str	r3, [r2, #0]
		start_cycle();
    16e0:	f7ff ff9c 	bl	161c <start_cycle>
}
    16e4:	e7e8      	b.n	16b8 <measure_temperature+0x30>
    16e6:	bf00      	nop
    16e8:	2000094a 	.word	0x2000094a
    16ec:	20000948 	.word	0x20000948
    16f0:	20000334 	.word	0x20000334

000016f4 <hf_request>:
{
    16f4:	b508      	push	{r3, lr}
	clk_request(&mgrs[CLOCK_CONTROL_NRF_TYPE_HFCLK], &cli, cal_hf_callback);
    16f6:	4a03      	ldr	r2, [pc, #12]	; (1704 <hf_request+0x10>)
    16f8:	4903      	ldr	r1, [pc, #12]	; (1708 <hf_request+0x14>)
    16fa:	4b04      	ldr	r3, [pc, #16]	; (170c <hf_request+0x18>)
    16fc:	6818      	ldr	r0, [r3, #0]
    16fe:	f003 fb6d 	bl	4ddc <clk_request>
}
    1702:	bd08      	pop	{r3, pc}
    1704:	00001669 	.word	0x00001669
    1708:	20000318 	.word	0x20000318
    170c:	20000328 	.word	0x20000328

00001710 <start_cal_process>:
{
    1710:	b508      	push	{r3, lr}
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    1712:	4b09      	ldr	r3, [pc, #36]	; (1738 <start_cal_process+0x28>)
    1714:	2201      	movs	r2, #1
    1716:	f3bf 8f5b 	dmb	ish
    171a:	e853 1f00 	ldrex	r1, [r3]
    171e:	2900      	cmp	r1, #0
    1720:	d103      	bne.n	172a <start_cal_process+0x1a>
    1722:	e843 2000 	strex	r0, r2, [r3]
    1726:	2800      	cmp	r0, #0
    1728:	d1f7      	bne.n	171a <start_cal_process+0xa>
    172a:	f3bf 8f5b 	dmb	ish
	if (atomic_cas(&cal_process_in_progress, 0, 1) == false) {
    172e:	d101      	bne.n	1734 <start_cal_process+0x24>
		hf_request();
    1730:	f7ff ffe0 	bl	16f4 <hf_request>
}
    1734:	bd08      	pop	{r3, pc}
    1736:	bf00      	nop
    1738:	20000314 	.word	0x20000314

0000173c <start_unconditional_cal_process>:

SYS_INIT(temp_sensor_init, APPLICATION, 0);
#endif /* CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP */

static void start_unconditional_cal_process(void)
{
    173c:	b508      	push	{r3, lr}
	calib_skip_cnt = 0;
    173e:	4b03      	ldr	r3, [pc, #12]	; (174c <start_unconditional_cal_process+0x10>)
    1740:	2200      	movs	r2, #0
    1742:	701a      	strb	r2, [r3, #0]
	start_cal_process();
    1744:	f7ff ffe4 	bl	1710 <start_cal_process>
}
    1748:	bd08      	pop	{r3, pc}
    174a:	bf00      	nop
    174c:	2000094a 	.word	0x2000094a

00001750 <temp_sensor_init>:
{
    1750:	b508      	push	{r3, lr}
    1752:	4803      	ldr	r0, [pc, #12]	; (1760 <temp_sensor_init+0x10>)
    1754:	f001 fcee 	bl	3134 <z_impl_device_get_binding>
	temp_sensor = temp_device();
    1758:	4b02      	ldr	r3, [pc, #8]	; (1764 <temp_sensor_init+0x14>)
    175a:	6018      	str	r0, [r3, #0]
}
    175c:	2000      	movs	r0, #0
    175e:	bd08      	pop	{r3, pc}
    1760:	00005b24 	.word	0x00005b24
    1764:	2000032c 	.word	0x2000032c

00001768 <z_nrf_clock_calibration_init>:
	mgrs = onoff_mgrs;
    1768:	4b03      	ldr	r3, [pc, #12]	; (1778 <z_nrf_clock_calibration_init+0x10>)
    176a:	6018      	str	r0, [r3, #0]
	total_cnt = 0;
    176c:	2300      	movs	r3, #0
    176e:	4a03      	ldr	r2, [pc, #12]	; (177c <z_nrf_clock_calibration_init+0x14>)
    1770:	6013      	str	r3, [r2, #0]
	total_skips_cnt = 0;
    1772:	4a03      	ldr	r2, [pc, #12]	; (1780 <z_nrf_clock_calibration_init+0x18>)
    1774:	6013      	str	r3, [r2, #0]
}
    1776:	4770      	bx	lr
    1778:	20000328 	.word	0x20000328
    177c:	20000330 	.word	0x20000330
    1780:	20000334 	.word	0x20000334

00001784 <z_nrf_clock_calibration_lfclk_stopped>:
{
	start_unconditional_cal_process();
}

void z_nrf_clock_calibration_lfclk_stopped(void)
{
    1784:	b508      	push	{r3, lr}
	z_impl_k_timer_stop(timer);
    1786:	4802      	ldr	r0, [pc, #8]	; (1790 <z_nrf_clock_calibration_lfclk_stopped+0xc>)
    1788:	f003 ff9f 	bl	56ca <z_impl_k_timer_stop>
	k_timer_stop(&backoff_timer);
	LOG_DBG("Calibration stopped");
}
    178c:	bd08      	pop	{r3, pc}
    178e:	bf00      	nop
    1790:	200000a8 	.word	0x200000a8

00001794 <z_nrf_clock_calibration_done_handler>:

void z_nrf_clock_calibration_done_handler(void)
{
    1794:	b508      	push	{r3, lr}
	total_cnt++;
    1796:	4a03      	ldr	r2, [pc, #12]	; (17a4 <z_nrf_clock_calibration_done_handler+0x10>)
    1798:	6813      	ldr	r3, [r2, #0]
    179a:	3301      	adds	r3, #1
    179c:	6013      	str	r3, [r2, #0]
	LOG_DBG("Calibration done.");

	start_cycle();
    179e:	f7ff ff3d 	bl	161c <start_cycle>
}
    17a2:	bd08      	pop	{r3, pc}
    17a4:	20000330 	.word	0x20000330

000017a8 <set_comparator>:
	return (a - b) & COUNTER_MAX;
}

static void set_comparator(int32_t chan, uint32_t cyc)
{
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    17a8:	f021 417f 	bic.w	r1, r1, #4278190080	; 0xff000000

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE  void nrf_rtc_cc_set(NRF_RTC_Type * p_reg, uint32_t ch, uint32_t cc_val)
{
    p_reg->CC[ch] = cc_val;
    17ac:	f500 70a8 	add.w	r0, r0, #336	; 0x150
    17b0:	4b01      	ldr	r3, [pc, #4]	; (17b8 <set_comparator+0x10>)
    17b2:	f843 1020 	str.w	r1, [r3, r0, lsl #2]
}
    17b6:	4770      	bx	lr
    17b8:	40011000 	.word	0x40011000

000017bc <get_comparator>:
}

NRF_STATIC_INLINE  uint32_t nrf_rtc_cc_get(NRF_RTC_Type const * p_reg, uint32_t ch)
{
    return p_reg->CC[ch];
    17bc:	f500 70a8 	add.w	r0, r0, #336	; 0x150
    17c0:	4b01      	ldr	r3, [pc, #4]	; (17c8 <get_comparator+0xc>)
    17c2:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]

static uint32_t get_comparator(int32_t chan)
{
	return nrf_rtc_cc_get(RTC, chan);
}
    17c6:	4770      	bx	lr
    17c8:	40011000 	.word	0x40011000

000017cc <event_enable>:
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
}

static void event_enable(int32_t chan)
{
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    17cc:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    17d0:	4083      	lsls	r3, r0
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
    17d2:	4a02      	ldr	r2, [pc, #8]	; (17dc <event_enable+0x10>)
    17d4:	f8c2 3344 	str.w	r3, [r2, #836]	; 0x344
}
    17d8:	4770      	bx	lr
    17da:	bf00      	nop
    17dc:	40011000 	.word	0x40011000

000017e0 <event_disable>:

static void event_disable(int32_t chan)
{
	nrf_rtc_event_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    17e0:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    17e4:	4083      	lsls	r3, r0
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    17e6:	4a02      	ldr	r2, [pc, #8]	; (17f0 <event_disable+0x10>)
    17e8:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
}
    17ec:	4770      	bx	lr
    17ee:	bf00      	nop
    17f0:	40011000 	.word	0x40011000

000017f4 <counter>:
     return p_reg->COUNTER;
    17f4:	4b01      	ldr	r3, [pc, #4]	; (17fc <counter+0x8>)
    17f6:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504

static uint32_t counter(void)
{
	return nrf_rtc_counter_get(RTC);
}
    17fa:	4770      	bx	lr
    17fc:	40011000 	.word	0x40011000

00001800 <rtc_nrf_isr>:
 * probably better abstract that at some point (e.g. query and reset
 * it by pointer at runtime, maybe?) so we don't have this leaky
 * symbol.
 */
void rtc_nrf_isr(const void *arg)
{
    1800:	b570      	push	{r4, r5, r6, lr}
	ARG_UNUSED(arg);

	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    1802:	2400      	movs	r4, #0
    1804:	2c00      	cmp	r4, #0
    1806:	dd00      	ble.n	180a <rtc_nrf_isr+0xa>
				handler(chan, cc_val,
					cc_data[chan].user_context);
			}
		}
	}
}
    1808:	bd70      	pop	{r4, r5, r6, pc}
		if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan)) &&
    180a:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    180e:	40a3      	lsls	r3, r4
    return p_reg->INTENSET & mask;
    1810:	4a19      	ldr	r2, [pc, #100]	; (1878 <rtc_nrf_isr+0x78>)
    1812:	f8d2 2304 	ldr.w	r2, [r2, #772]	; 0x304
    1816:	4213      	tst	r3, r2
    1818:	d009      	beq.n	182e <rtc_nrf_isr+0x2e>
		    nrf_rtc_event_check(RTC, RTC_CHANNEL_EVENT_ADDR(chan))) {
    181a:	f104 0350 	add.w	r3, r4, #80	; 0x50
    181e:	009b      	lsls	r3, r3, #2
    1820:	b29b      	uxth	r3, r3
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    1822:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    1826:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    182a:	681b      	ldr	r3, [r3, #0]
		if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan)) &&
    182c:	b90b      	cbnz	r3, 1832 <rtc_nrf_isr+0x32>
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    182e:	3401      	adds	r4, #1
    1830:	e7e8      	b.n	1804 <rtc_nrf_isr+0x4>
			event_clear(chan);
    1832:	4620      	mov	r0, r4
    1834:	f003 fae9 	bl	4e0a <event_clear>
			event_disable(chan);
    1838:	4620      	mov	r0, r4
    183a:	f7ff ffd1 	bl	17e0 <event_disable>
			cc_val = get_comparator(chan);
    183e:	4620      	mov	r0, r4
    1840:	f7ff ffbc 	bl	17bc <get_comparator>
    1844:	4605      	mov	r5, r0
			now = counter();
    1846:	f7ff ffd5 	bl	17f4 <counter>
    184a:	4606      	mov	r6, r0
			if (counter_sub(now, cc_val) > COUNTER_HALF_SPAN) {
    184c:	4629      	mov	r1, r5
    184e:	f003 fad8 	bl	4e02 <counter_sub>
    1852:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    1856:	d800      	bhi.n	185a <rtc_nrf_isr+0x5a>
			cc_val = get_comparator(chan);
    1858:	462e      	mov	r6, r5
			handler = cc_data[chan].callback;
    185a:	4b08      	ldr	r3, [pc, #32]	; (187c <rtc_nrf_isr+0x7c>)
    185c:	f853 5034 	ldr.w	r5, [r3, r4, lsl #3]
			cc_data[chan].callback = NULL;
    1860:	2200      	movs	r2, #0
    1862:	f843 2034 	str.w	r2, [r3, r4, lsl #3]
			if (handler) {
    1866:	2d00      	cmp	r5, #0
    1868:	d0e1      	beq.n	182e <rtc_nrf_isr+0x2e>
				handler(chan, cc_val,
    186a:	eb03 03c4 	add.w	r3, r3, r4, lsl #3
    186e:	685a      	ldr	r2, [r3, #4]
    1870:	4631      	mov	r1, r6
    1872:	4620      	mov	r0, r4
    1874:	47a8      	blx	r5
    1876:	e7da      	b.n	182e <rtc_nrf_isr+0x2e>
    1878:	40011000 	.word	0x40011000
    187c:	2000033c 	.word	0x2000033c

00001880 <compare_set>:
{
    1880:	b538      	push	{r3, r4, r5, lr}
	cc_data[chan].callback = handler;
    1882:	4c04      	ldr	r4, [pc, #16]	; (1894 <compare_set+0x14>)
    1884:	f844 2030 	str.w	r2, [r4, r0, lsl #3]
	cc_data[chan].user_context = user_data;
    1888:	eb04 04c0 	add.w	r4, r4, r0, lsl #3
    188c:	6063      	str	r3, [r4, #4]
	set_absolute_alarm(chan, cc_value);
    188e:	f003 fac8 	bl	4e22 <set_absolute_alarm>
}
    1892:	bd38      	pop	{r3, r4, r5, pc}
    1894:	2000033c 	.word	0x2000033c

00001898 <sys_clock_timeout_handler>:
{
    1898:	b538      	push	{r3, r4, r5, lr}
    189a:	4608      	mov	r0, r1
	uint32_t dticks = counter_sub(cc_value, last_count) / CYC_PER_TICK;
    189c:	4d04      	ldr	r5, [pc, #16]	; (18b0 <sys_clock_timeout_handler+0x18>)
    189e:	682c      	ldr	r4, [r5, #0]
    18a0:	4621      	mov	r1, r4
    18a2:	f003 faae 	bl	4e02 <counter_sub>
	last_count += dticks * CYC_PER_TICK;
    18a6:	4404      	add	r4, r0
    18a8:	602c      	str	r4, [r5, #0]
	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    18aa:	f002 fd91 	bl	43d0 <sys_clock_announce>
}
    18ae:	bd38      	pop	{r3, r4, r5, pc}
    18b0:	20000348 	.word	0x20000348

000018b4 <sys_clock_driver_init>:

	atomic_or(&alloc_mask, BIT(chan));
}

int sys_clock_driver_init(const struct device *dev)
{
    18b4:	b508      	push	{r3, lr}
    p_reg->PRESCALER = val;
    18b6:	2300      	movs	r3, #0
    18b8:	4a12      	ldr	r2, [pc, #72]	; (1904 <sys_clock_driver_init+0x50>)
    18ba:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			CLOCK_CONTROL_NRF_LF_START_AVAILABLE :
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    18be:	2b00      	cmp	r3, #0
    18c0:	dd18      	ble.n	18f4 <sys_clock_driver_init+0x40>
 */
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    18c2:	4b11      	ldr	r3, [pc, #68]	; (1908 <sys_clock_driver_init+0x54>)
    18c4:	f44f 3200 	mov.w	r2, #131072	; 0x20000
    18c8:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
	}

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    18cc:	2200      	movs	r2, #0
    18ce:	2101      	movs	r1, #1
    18d0:	2011      	movs	r0, #17
    18d2:	f000 f8c5 	bl	1a60 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    18d6:	2011      	movs	r0, #17
    18d8:	f000 f8a4 	bl	1a24 <arch_irq_enable>
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    18dc:	2301      	movs	r3, #1
    18de:	4a0b      	ldr	r2, [pc, #44]	; (190c <sys_clock_driver_init+0x58>)
    18e0:	6013      	str	r3, [r2, #0]
    18e2:	3a08      	subs	r2, #8
    18e4:	6013      	str	r3, [r2, #0]

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    18e6:	4a0a      	ldr	r2, [pc, #40]	; (1910 <sys_clock_driver_init+0x5c>)
    18e8:	6013      	str	r3, [r2, #0]
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		compare_set(0, counter() + CYC_PER_TICK,
			    sys_clock_timeout_handler, NULL);
	}

	z_nrf_clock_control_lf_on(mode);
    18ea:	2002      	movs	r0, #2
    18ec:	f7ff fe40 	bl	1570 <z_nrf_clock_control_lf_on>

	return 0;
}
    18f0:	2000      	movs	r0, #0
    18f2:	bd08      	pop	{r3, pc}
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    18f4:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    18f8:	409a      	lsls	r2, r3
    p_reg->INTENSET = mask;
    18fa:	4902      	ldr	r1, [pc, #8]	; (1904 <sys_clock_driver_init+0x50>)
    18fc:	f8c1 2304 	str.w	r2, [r1, #772]	; 0x304
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    1900:	3301      	adds	r3, #1
    1902:	e7dc      	b.n	18be <sys_clock_driver_init+0xa>
    1904:	40011000 	.word	0x40011000
    1908:	e000e100 	.word	0xe000e100
    190c:	40011008 	.word	0x40011008
    1910:	20000344 	.word	0x20000344

00001914 <sys_clock_set_timeout>:

void sys_clock_set_timeout(int32_t ticks, bool idle)
{
    1914:	b538      	push	{r3, r4, r5, lr}

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return;
	}

	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    1916:	f1b0 3fff 	cmp.w	r0, #4294967295
    191a:	d007      	beq.n	192c <sys_clock_set_timeout+0x18>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    191c:	1e44      	subs	r4, r0, #1
    191e:	2c00      	cmp	r4, #0
    1920:	dd07      	ble.n	1932 <sys_clock_set_timeout+0x1e>
    1922:	4b10      	ldr	r3, [pc, #64]	; (1964 <sys_clock_set_timeout+0x50>)
    1924:	429c      	cmp	r4, r3
    1926:	dd05      	ble.n	1934 <sys_clock_set_timeout+0x20>
    1928:	4c0f      	ldr	r4, [pc, #60]	; (1968 <sys_clock_set_timeout+0x54>)
    192a:	e003      	b.n	1934 <sys_clock_set_timeout+0x20>
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    192c:	f500 0000 	add.w	r0, r0, #8388608	; 0x800000
    1930:	e7f4      	b.n	191c <sys_clock_set_timeout+0x8>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    1932:	2400      	movs	r4, #0

	uint32_t unannounced = counter_sub(counter(), last_count);
    1934:	f7ff ff5e 	bl	17f4 <counter>
    1938:	4b0c      	ldr	r3, [pc, #48]	; (196c <sys_clock_set_timeout+0x58>)
    193a:	681d      	ldr	r5, [r3, #0]
    193c:	4629      	mov	r1, r5
    193e:	f003 fa60 	bl	4e02 <counter_sub>
	/* If we haven't announced for more than half the 24-bit wrap
	 * duration, then force an announce to avoid loss of a wrap
	 * event.  This can happen if new timeouts keep being set
	 * before the existing one triggers the interrupt.
	 */
	if (unannounced >= COUNTER_HALF_SPAN) {
    1942:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    1946:	d300      	bcc.n	194a <sys_clock_set_timeout+0x36>
		ticks = 0;
    1948:	2400      	movs	r4, #0
	}

	/* Get the cycles from last_count to the tick boundary after
	 * the requested ticks have passed starting now.
	 */
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    194a:	1821      	adds	r1, r4, r0
    194c:	3101      	adds	r1, #1
	cyc = (cyc / CYC_PER_TICK) * CYC_PER_TICK;

	/* Due to elapsed time the calculation above might produce a
	 * duration that laps the counter.  Don't let it.
	 */
	if (cyc > MAX_CYCLES) {
    194e:	f5b1 0f00 	cmp.w	r1, #8388608	; 0x800000
    1952:	d300      	bcc.n	1956 <sys_clock_set_timeout+0x42>
		cyc = MAX_CYCLES;
    1954:	4904      	ldr	r1, [pc, #16]	; (1968 <sys_clock_set_timeout+0x54>)
	}

	cyc += last_count;
	compare_set(0, cyc, sys_clock_timeout_handler, NULL);
    1956:	2300      	movs	r3, #0
    1958:	4a05      	ldr	r2, [pc, #20]	; (1970 <sys_clock_set_timeout+0x5c>)
    195a:	4429      	add	r1, r5
    195c:	4618      	mov	r0, r3
    195e:	f7ff ff8f 	bl	1880 <compare_set>
}
    1962:	bd38      	pop	{r3, r4, r5, pc}
    1964:	007ffffe 	.word	0x007ffffe
    1968:	007fffff 	.word	0x007fffff
    196c:	20000348 	.word	0x20000348
    1970:	00001899 	.word	0x00001899

00001974 <sys_clock_elapsed>:

uint32_t sys_clock_elapsed(void)
{
    1974:	b508      	push	{r3, lr}
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return 0;
	}

	return counter_sub(counter(), last_count) / CYC_PER_TICK;
    1976:	f7ff ff3d 	bl	17f4 <counter>
    197a:	4b02      	ldr	r3, [pc, #8]	; (1984 <sys_clock_elapsed+0x10>)
    197c:	6819      	ldr	r1, [r3, #0]
    197e:	f003 fa40 	bl	4e02 <counter_sub>
}
    1982:	bd08      	pop	{r3, pc}
    1984:	20000348 	.word	0x20000348

00001988 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    1988:	4a09      	ldr	r2, [pc, #36]	; (19b0 <arch_swap+0x28>)
    198a:	6893      	ldr	r3, [r2, #8]
    198c:	6758      	str	r0, [r3, #116]	; 0x74
	_current->arch.swap_return_value = _k_neg_eagain;
    198e:	4909      	ldr	r1, [pc, #36]	; (19b4 <arch_swap+0x2c>)
    1990:	6809      	ldr	r1, [r1, #0]
    1992:	6799      	str	r1, [r3, #120]	; 0x78

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    1994:	4908      	ldr	r1, [pc, #32]	; (19b8 <arch_swap+0x30>)
    1996:	684b      	ldr	r3, [r1, #4]
    1998:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    199c:	604b      	str	r3, [r1, #4]
    199e:	2300      	movs	r3, #0
    19a0:	f383 8811 	msr	BASEPRI, r3
    19a4:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    19a8:	6893      	ldr	r3, [r2, #8]
}
    19aa:	6f98      	ldr	r0, [r3, #120]	; 0x78
    19ac:	4770      	bx	lr
    19ae:	bf00      	nop
    19b0:	200008e4 	.word	0x200008e4
    19b4:	00005c1c 	.word	0x00005c1c
    19b8:	e000ed00 	.word	0xe000ed00

000019bc <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    19bc:	490f      	ldr	r1, [pc, #60]	; (19fc <z_arm_pendsv+0x40>)
    ldr r2, [r1, #_kernel_offset_to_current]
    19be:	688a      	ldr	r2, [r1, #8]
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    19c0:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    19c4:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    19c6:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    19ca:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    19ce:	2020      	movs	r0, #32
    msr BASEPRI, r0
    19d0:	f380 8811 	msr	BASEPRI, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    19d4:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    19d8:	4f09      	ldr	r7, [pc, #36]	; (1a00 <z_arm_pendsv+0x44>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    19da:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    19de:	6a4a      	ldr	r2, [r1, #36]	; 0x24

    str r2, [r1, #_kernel_offset_to_current]
    19e0:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    19e2:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    19e4:	6f50      	ldr	r0, [r2, #116]	; 0x74
    movs r3, #0
    19e6:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    19e8:	6753      	str	r3, [r2, #116]	; 0x74
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    19ea:	f380 8811 	msr	BASEPRI, r0
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    19ee:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    19f2:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    19f6:	f38c 8809 	msr	PSP, ip

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    19fa:	4770      	bx	lr
    ldr r1, =_kernel
    19fc:	200008e4 	.word	0x200008e4
    ldr v4, =_SCS_ICSR
    1a00:	e000ed04 	.word	0xe000ed04

00001a04 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #0x4    /* did we come from thread mode ? */
    1a04:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    1a08:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    1a0a:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    1a0e:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    1a12:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    1a14:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    1a18:	2902      	cmp	r1, #2
    beq _oops
    1a1a:	d0ff      	beq.n	1a1c <_oops>

00001a1c <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    1a1c:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    1a1e:	f003 fa44 	bl	4eaa <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    1a22:	bd01      	pop	{r0, pc}

00001a24 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    1a24:	b243      	sxtb	r3, r0
  if ((int32_t)(IRQn) >= 0)
    1a26:	2b00      	cmp	r3, #0
    1a28:	db08      	blt.n	1a3c <arch_irq_enable+0x18>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1a2a:	f000 001f 	and.w	r0, r0, #31
    1a2e:	095b      	lsrs	r3, r3, #5
    1a30:	2201      	movs	r2, #1
    1a32:	fa02 f000 	lsl.w	r0, r2, r0
    1a36:	4a02      	ldr	r2, [pc, #8]	; (1a40 <arch_irq_enable+0x1c>)
    1a38:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    1a3c:	4770      	bx	lr
    1a3e:	bf00      	nop
    1a40:	e000e100 	.word	0xe000e100

00001a44 <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    1a44:	0942      	lsrs	r2, r0, #5
    1a46:	4b05      	ldr	r3, [pc, #20]	; (1a5c <arch_irq_is_enabled+0x18>)
    1a48:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    1a4c:	f000 001f 	and.w	r0, r0, #31
    1a50:	2301      	movs	r3, #1
    1a52:	fa03 f000 	lsl.w	r0, r3, r0
}
    1a56:	4010      	ands	r0, r2
    1a58:	4770      	bx	lr
    1a5a:	bf00      	nop
    1a5c:	e000e100 	.word	0xe000e100

00001a60 <z_arm_irq_priority_set>:
	 * via flags
	 */
	if (IS_ENABLED(CONFIG_ZERO_LATENCY_IRQS) && (flags & IRQ_ZERO_LATENCY)) {
		prio = _EXC_ZERO_LATENCY_IRQS_PRIO;
	} else {
		prio += _IRQ_PRIO_OFFSET;
    1a60:	3101      	adds	r1, #1
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    1a62:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    1a64:	2b00      	cmp	r3, #0
    1a66:	db08      	blt.n	1a7a <z_arm_irq_priority_set+0x1a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1a68:	0149      	lsls	r1, r1, #5
    1a6a:	b2c9      	uxtb	r1, r1
    1a6c:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    1a70:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    1a74:	f883 1300 	strb.w	r1, [r3, #768]	; 0x300
    1a78:	4770      	bx	lr
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1a7a:	f000 000f 	and.w	r0, r0, #15
    1a7e:	0149      	lsls	r1, r1, #5
    1a80:	b2c9      	uxtb	r1, r1
    1a82:	4b01      	ldr	r3, [pc, #4]	; (1a88 <z_arm_irq_priority_set+0x28>)
    1a84:	5419      	strb	r1, [r3, r0]
}
    1a86:	4770      	bx	lr
    1a88:	e000ed14 	.word	0xe000ed14

00001a8c <arch_new_thread>:
 * of the ESF.
 */
void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
		     char *stack_ptr, k_thread_entry_t entry,
		     void *p1, void *p2, void *p3)
{
    1a8c:	b410      	push	{r4}
		thread->stack_info.size -= FP_GUARD_EXTRA_SIZE;
	}
#endif /* FP_GUARD_EXTRA_SIZE */
#endif /* CONFIG_MPU_STACK_GUARD */

	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    1a8e:	f1a2 0420 	sub.w	r4, r2, #32
		iframe->pc = (uint32_t)arch_user_mode_enter;
	} else {
		iframe->pc = (uint32_t)z_thread_entry;
	}
#else
	iframe->pc = (uint32_t)z_thread_entry;
    1a92:	490c      	ldr	r1, [pc, #48]	; (1ac4 <arch_new_thread+0x38>)
#endif

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
    1a94:	f021 0101 	bic.w	r1, r1, #1
    1a98:	f842 1c08 	str.w	r1, [r2, #-8]
#endif
	iframe->a1 = (uint32_t)entry;
    1a9c:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    1aa0:	9b01      	ldr	r3, [sp, #4]
    1aa2:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->a3 = (uint32_t)p2;
    1aa6:	9b02      	ldr	r3, [sp, #8]
    1aa8:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    1aac:	9b03      	ldr	r3, [sp, #12]
    1aae:	f842 3c14 	str.w	r3, [r2, #-20]

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    1ab2:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    1ab6:	f842 3c04 	str.w	r3, [r2, #-4]
#if defined(CONFIG_COMPILER_ISA_THUMB2)
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
    1aba:	6504      	str	r4, [r0, #80]	; 0x50
	thread->arch.basepri = 0;
    1abc:	2300      	movs	r3, #0
    1abe:	6743      	str	r3, [r0, #116]	; 0x74
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    1ac0:	bc10      	pop	{r4}
    1ac2:	4770      	bx	lr
    1ac4:	00004bd5 	.word	0x00004bd5

00001ac8 <arch_switch_to_main_thread>:
void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    1ac8:	4b07      	ldr	r3, [pc, #28]	; (1ae8 <arch_switch_to_main_thread+0x20>)
    1aca:	6098      	str	r0, [r3, #8]

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    1acc:	4610      	mov	r0, r2
    1ace:	f381 8809 	msr	PSP, r1
    1ad2:	2100      	movs	r1, #0
    1ad4:	b663      	cpsie	if
    1ad6:	f381 8811 	msr	BASEPRI, r1
    1ada:	f3bf 8f6f 	isb	sy
    1ade:	2200      	movs	r2, #0
    1ae0:	2300      	movs	r3, #0
    1ae2:	f003 f877 	bl	4bd4 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    1ae6:	bf00      	nop
    1ae8:	200008e4 	.word	0x200008e4

00001aec <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    1aec:	4901      	ldr	r1, [pc, #4]	; (1af4 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    1aee:	2210      	movs	r2, #16
	str	r2, [r1]
    1af0:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    1af2:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    1af4:	e000ed10 	.word	0xe000ed10

00001af8 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    1af8:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    1afa:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    1afc:	f380 8811 	msr	BASEPRI, r0
	isb
    1b00:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    1b04:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    1b08:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    1b0a:	b662      	cpsie	i
	isb
    1b0c:	f3bf 8f6f 	isb	sy

	bx	lr
    1b10:	4770      	bx	lr
    1b12:	bf00      	nop

00001b14 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    1b14:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    1b16:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    1b18:	f381 8811 	msr	BASEPRI, r1

	wfe
    1b1c:	bf20      	wfe

	msr	BASEPRI, r0
    1b1e:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    1b22:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    1b24:	4770      	bx	lr
    1b26:	bf00      	nop

00001b28 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    1b28:	bf30      	wfi
    b z_SysNmiOnReset
    1b2a:	f7ff bffd 	b.w	1b28 <z_SysNmiOnReset>
    1b2e:	bf00      	nop

00001b30 <z_arm_prep_c>:
 * This routine prepares for the execution of and runs C code.
 *
 * @return N/A
 */
void z_arm_prep_c(void)
{
    1b30:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1b32:	4b0b      	ldr	r3, [pc, #44]	; (1b60 <z_arm_prep_c+0x30>)
    1b34:	4a0b      	ldr	r2, [pc, #44]	; (1b64 <z_arm_prep_c+0x34>)
    1b36:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    1b3a:	609a      	str	r2, [r3, #8]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    1b3c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1b40:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    1b44:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    1b48:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    1b4c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    1b50:	f001 fba4 	bl	329c <z_bss_zero>
	z_data_copy();
    1b54:	f002 fb30 	bl	41b8 <z_data_copy>
#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    1b58:	f000 f994 	bl	1e84 <z_arm_interrupt_init>
	z_cstart();
    1b5c:	f001 fbc8 	bl	32f0 <z_cstart>
    1b60:	e000ed00 	.word	0xe000ed00
    1b64:	00000000 	.word	0x00000000

00001b68 <_isr_wrapper>:
 * @return N/A
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    1b68:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    1b6a:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    1b6c:	4a0b      	ldr	r2, [pc, #44]	; (1b9c <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    1b6e:	6a10      	ldr	r0, [r2, #32]
	cmp r0, #0
    1b70:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    1b72:	bf1e      	ittt	ne
	movne	r1, #0
    1b74:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    1b76:	6211      	strne	r1, [r2, #32]
		blne	z_pm_save_idle_exit
    1b78:	f003 fb54 	blne	5224 <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    1b7c:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    1b7e:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    1b82:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    1b86:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    1b8a:	4905      	ldr	r1, [pc, #20]	; (1ba0 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    1b8c:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    1b8e:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    1b90:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    1b92:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    1b96:	4903      	ldr	r1, [pc, #12]	; (1ba4 <_isr_wrapper+0x3c>)
	bx r1
    1b98:	4708      	bx	r1
    1b9a:	0000      	.short	0x0000
	ldr r2, =_kernel
    1b9c:	200008e4 	.word	0x200008e4
	ldr r1, =_sw_isr_table
    1ba0:	000058d4 	.word	0x000058d4
	ldr r1, =z_arm_int_exit
    1ba4:	00001df5 	.word	0x00001df5

00001ba8 <__start>:
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    1ba8:	2000      	movs	r0, #0
    msr CONTROL, r0
    1baa:	f380 8814 	msr	CONTROL, r0
    isb
    1bae:	f3bf 8f6f 	isb	sy
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_platform_init
    1bb2:	f003 fe11 	bl	57d8 <z_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    1bb6:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    1bb8:	490d      	ldr	r1, [pc, #52]	; (1bf0 <__start+0x48>)
    str r0, [r1]
    1bba:	6008      	str	r0, [r1, #0]
    dsb
    1bbc:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    1bc0:	480c      	ldr	r0, [pc, #48]	; (1bf4 <__start+0x4c>)
    msr msp, r0
    1bc2:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    1bc6:	f000 f933 	bl	1e30 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    1bca:	2020      	movs	r0, #32
    msr BASEPRI, r0
    1bcc:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    1bd0:	4809      	ldr	r0, [pc, #36]	; (1bf8 <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    1bd2:	f44f 6100 	mov.w	r1, #2048	; 0x800
    adds r0, r0, r1
    1bd6:	1840      	adds	r0, r0, r1
    msr PSP, r0
    1bd8:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    1bdc:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    1be0:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    1be2:	4308      	orrs	r0, r1
    msr CONTROL, r0
    1be4:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    1be8:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    1bec:	f7ff ffa0 	bl	1b30 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    1bf0:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    1bf4:	20000d58 	.word	0x20000d58
    ldr r0, =z_interrupt_stacks
    1bf8:	20000e98 	.word	0x20000e98

00001bfc <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    1bfc:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    1c00:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    1c04:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    1c06:	4672      	mov	r2, lr
	bl z_arm_fault
    1c08:	f000 f89c 	bl	1d44 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    1c0c:	bd01      	pop	{r0, pc}
    1c0e:	bf00      	nop

00001c10 <mem_manage_fault>:
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
			      bool *recoverable)
{
    1c10:	b510      	push	{r4, lr}
    1c12:	4614      	mov	r4, r2
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    1c14:	4b13      	ldr	r3, [pc, #76]	; (1c64 <mem_manage_fault+0x54>)
    1c16:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error (context area might be"
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    1c18:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    1c1a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    1c1c:	f013 0f02 	tst.w	r3, #2
    1c20:	d00b      	beq.n	1c3a <mem_manage_fault+0x2a>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		uint32_t temp = SCB->MMFAR;
    1c22:	4b10      	ldr	r3, [pc, #64]	; (1c64 <mem_manage_fault+0x54>)
    1c24:	6b5a      	ldr	r2, [r3, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    1c26:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    1c28:	f013 0f80 	tst.w	r3, #128	; 0x80
    1c2c:	d005      	beq.n	1c3a <mem_manage_fault+0x2a>
			mmfar = temp;
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
			if (from_hard_fault != 0) {
    1c2e:	b121      	cbz	r1, 1c3a <mem_manage_fault+0x2a>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    1c30:	4a0c      	ldr	r2, [pc, #48]	; (1c64 <mem_manage_fault+0x54>)
    1c32:	6a93      	ldr	r3, [r2, #40]	; 0x28
    1c34:	f023 0380 	bic.w	r3, r3, #128	; 0x80
    1c38:	6293      	str	r3, [r2, #40]	; 0x28
			}
		}
	}
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    1c3a:	4b0a      	ldr	r3, [pc, #40]	; (1c64 <mem_manage_fault+0x54>)
    1c3c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Instruction Access Violation");
	}
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    1c3e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	 * crossed into an area beyond the thread stack.]
	 *
	 * Data Access Violation errors may or may not be caused by
	 * thread stack overflows.
	 */
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1c40:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    1c42:	f013 0f10 	tst.w	r3, #16
    1c46:	d101      	bne.n	1c4c <mem_manage_fault+0x3c>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    1c48:	4b06      	ldr	r3, [pc, #24]	; (1c64 <mem_manage_fault+0x54>)
    1c4a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
		"without stack guard, user-mode or null-pointer detection\n");
#endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */
	}

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    1c4c:	4a05      	ldr	r2, [pc, #20]	; (1c64 <mem_manage_fault+0x54>)
    1c4e:	6a93      	ldr	r3, [r2, #40]	; 0x28
    1c50:	f043 03ff 	orr.w	r3, r3, #255	; 0xff
    1c54:	6293      	str	r3, [r2, #40]	; 0x28

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf, true);
    1c56:	2101      	movs	r1, #1
    1c58:	f003 f933 	bl	4ec2 <memory_fault_recoverable>
    1c5c:	7020      	strb	r0, [r4, #0]

	return reason;
}
    1c5e:	2000      	movs	r0, #0
    1c60:	bd10      	pop	{r4, pc}
    1c62:	bf00      	nop
    1c64:	e000ed00 	.word	0xe000ed00

00001c68 <bus_fault>:
 * See z_arm_fault_dump() for example.
 *
 * @return N/A
 */
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
{
    1c68:	b510      	push	{r4, lr}
    1c6a:	4614      	mov	r4, r2
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    1c6c:	4b12      	ldr	r3, [pc, #72]	; (1cb8 <bus_fault+0x50>)
    1c6e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error");
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    1c70:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    1c72:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    1c74:	f413 7f00 	tst.w	r3, #512	; 0x200
    1c78:	d00b      	beq.n	1c92 <bus_fault+0x2a>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
    1c7a:	4b0f      	ldr	r3, [pc, #60]	; (1cb8 <bus_fault+0x50>)
    1c7c:	6b9a      	ldr	r2, [r3, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    1c7e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    1c80:	f413 4f00 	tst.w	r3, #32768	; 0x8000
    1c84:	d005      	beq.n	1c92 <bus_fault+0x2a>
			PR_EXC("  BFAR Address: 0x%x", bfar);
			if (from_hard_fault != 0) {
    1c86:	b121      	cbz	r1, 1c92 <bus_fault+0x2a>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    1c88:	4a0b      	ldr	r2, [pc, #44]	; (1cb8 <bus_fault+0x50>)
    1c8a:	6a93      	ldr	r3, [r2, #40]	; 0x28
    1c8c:	f423 4300 	bic.w	r3, r3, #32768	; 0x8000
    1c90:	6293      	str	r3, [r2, #40]	; 0x28
			}
		}
	}
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    1c92:	4b09      	ldr	r3, [pc, #36]	; (1cb8 <bus_fault+0x50>)
    1c94:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Imprecise data bus error");
	}
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    1c96:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    1c98:	f413 7f80 	tst.w	r3, #256	; 0x100
    1c9c:	d101      	bne.n	1ca2 <bus_fault+0x3a>
		PR_FAULT_INFO("  Instruction bus error");
#if !defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	}
#else
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    1c9e:	4b06      	ldr	r3, [pc, #24]	; (1cb8 <bus_fault+0x50>)
    1ca0:	6a9b      	ldr	r3, [r3, #40]	; 0x28
		SYSMPU->CESR &= ~sperr;
	}
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    1ca2:	4a05      	ldr	r2, [pc, #20]	; (1cb8 <bus_fault+0x50>)
    1ca4:	6a93      	ldr	r3, [r2, #40]	; 0x28
    1ca6:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    1caa:	6293      	str	r3, [r2, #40]	; 0x28

	*recoverable = memory_fault_recoverable(esf, true);
    1cac:	2101      	movs	r1, #1
    1cae:	f003 f908 	bl	4ec2 <memory_fault_recoverable>
    1cb2:	7020      	strb	r0, [r4, #0]

	return reason;
}
    1cb4:	2000      	movs	r0, #0
    1cb6:	bd10      	pop	{r4, pc}
    1cb8:	e000ed00 	.word	0xe000ed00

00001cbc <usage_fault>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    1cbc:	4b07      	ldr	r3, [pc, #28]	; (1cdc <usage_fault+0x20>)
    1cbe:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    1cc0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    1cc2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    1cc4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    1cc6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    1cc8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    1cca:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1ccc:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    1cd0:	ea6f 4212 	mvn.w	r2, r2, lsr #16
    1cd4:	629a      	str	r2, [r3, #40]	; 0x28

	return reason;
}
    1cd6:	2000      	movs	r0, #0
    1cd8:	4770      	bx	lr
    1cda:	bf00      	nop
    1cdc:	e000ed00 	.word	0xe000ed00

00001ce0 <hard_fault>:
	}
#undef _SVC_OPCODE

	*recoverable = memory_fault_recoverable(esf, true);
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	*recoverable = false;
    1ce0:	2300      	movs	r3, #0
    1ce2:	700b      	strb	r3, [r1, #0]

	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    1ce4:	4b14      	ldr	r3, [pc, #80]	; (1d38 <hard_fault+0x58>)
    1ce6:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    1ce8:	f012 0202 	ands.w	r2, r2, #2
    1cec:	d121      	bne.n	1d32 <hard_fault+0x52>
{
    1cee:	b510      	push	{r4, lr}
    1cf0:	4604      	mov	r4, r0
		PR_EXC("  Bus fault on vector table read");
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    1cf2:	6ad8      	ldr	r0, [r3, #44]	; 0x2c
    1cf4:	f010 4080 	ands.w	r0, r0, #1073741824	; 0x40000000
    1cf8:	d010      	beq.n	1d1c <hard_fault+0x3c>
		PR_EXC("  Fault escalation (see below)");
		if (SCB_MMFSR != 0) {
    1cfa:	3328      	adds	r3, #40	; 0x28
    1cfc:	781b      	ldrb	r3, [r3, #0]
    1cfe:	b943      	cbnz	r3, 1d12 <hard_fault+0x32>
			reason = mem_manage_fault(esf, 1, recoverable);
		} else if (SCB_BFSR != 0) {
    1d00:	4b0e      	ldr	r3, [pc, #56]	; (1d3c <hard_fault+0x5c>)
    1d02:	781b      	ldrb	r3, [r3, #0]
    1d04:	b95b      	cbnz	r3, 1d1e <hard_fault+0x3e>
			reason = bus_fault(esf, 1, recoverable);
		} else if (SCB_UFSR != 0) {
    1d06:	4b0e      	ldr	r3, [pc, #56]	; (1d40 <hard_fault+0x60>)
    1d08:	881b      	ldrh	r3, [r3, #0]
    1d0a:	b29b      	uxth	r3, r3
    1d0c:	b96b      	cbnz	r3, 1d2a <hard_fault+0x4a>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    1d0e:	4610      	mov	r0, r2
	}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	return reason;
    1d10:	e004      	b.n	1d1c <hard_fault+0x3c>
			reason = mem_manage_fault(esf, 1, recoverable);
    1d12:	460a      	mov	r2, r1
    1d14:	2101      	movs	r1, #1
    1d16:	4620      	mov	r0, r4
    1d18:	f7ff ff7a 	bl	1c10 <mem_manage_fault>
}
    1d1c:	bd10      	pop	{r4, pc}
			reason = bus_fault(esf, 1, recoverable);
    1d1e:	460a      	mov	r2, r1
    1d20:	2101      	movs	r1, #1
    1d22:	4620      	mov	r0, r4
    1d24:	f7ff ffa0 	bl	1c68 <bus_fault>
    1d28:	e7f8      	b.n	1d1c <hard_fault+0x3c>
			reason = usage_fault(esf);
    1d2a:	4620      	mov	r0, r4
    1d2c:	f7ff ffc6 	bl	1cbc <usage_fault>
    1d30:	e7f4      	b.n	1d1c <hard_fault+0x3c>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    1d32:	2000      	movs	r0, #0
}
    1d34:	4770      	bx	lr
    1d36:	bf00      	nop
    1d38:	e000ed00 	.word	0xe000ed00
    1d3c:	e000ed29 	.word	0xe000ed29
    1d40:	e000ed2a 	.word	0xe000ed2a

00001d44 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    1d44:	b5f0      	push	{r4, r5, r6, r7, lr}
    1d46:	b08b      	sub	sp, #44	; 0x2c
    1d48:	460c      	mov	r4, r1
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    1d4a:	4b25      	ldr	r3, [pc, #148]	; (1de0 <z_arm_fault+0x9c>)
    1d4c:	6859      	ldr	r1, [r3, #4]
    1d4e:	f3c1 0108 	ubfx	r1, r1, #0, #9
    1d52:	2300      	movs	r3, #0
    1d54:	f383 8811 	msr	BASEPRI, r3
    1d58:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    1d5c:	f002 437f 	and.w	r3, r2, #4278190080	; 0xff000000
    1d60:	f1b3 4f7f 	cmp.w	r3, #4278190080	; 0xff000000
    1d64:	d115      	bne.n	1d92 <z_arm_fault+0x4e>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    1d66:	f002 030c 	and.w	r3, r2, #12
    1d6a:	2b08      	cmp	r3, #8
    1d6c:	d014      	beq.n	1d98 <z_arm_fault+0x54>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    1d6e:	f012 0f08 	tst.w	r2, #8
    1d72:	d00b      	beq.n	1d8c <z_arm_fault+0x48>
	*nested_exc = false;
    1d74:	2700      	movs	r7, #0

#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
    1d76:	f10d 0227 	add.w	r2, sp, #39	; 0x27
    1d7a:	4620      	mov	r0, r4
    1d7c:	f003 f8a6 	bl	4ecc <fault_handle>
    1d80:	4606      	mov	r6, r0
	if (recoverable) {
    1d82:	f89d 3027 	ldrb.w	r3, [sp, #39]	; 0x27
    1d86:	b153      	cbz	r3, 1d9e <z_arm_fault+0x5a>
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
	}

	z_arm_fatal_error(reason, &esf_copy);
}
    1d88:	b00b      	add	sp, #44	; 0x2c
    1d8a:	bdf0      	pop	{r4, r5, r6, r7, pc}
			ptr_esf = (z_arch_esf_t *)msp;
    1d8c:	4604      	mov	r4, r0
			*nested_exc = true;
    1d8e:	2701      	movs	r7, #1
    1d90:	e7f1      	b.n	1d76 <z_arm_fault+0x32>
	*nested_exc = false;
    1d92:	2700      	movs	r7, #0
		return NULL;
    1d94:	463c      	mov	r4, r7
    1d96:	e7ee      	b.n	1d76 <z_arm_fault+0x32>
	*nested_exc = false;
    1d98:	2700      	movs	r7, #0
		return NULL;
    1d9a:	463c      	mov	r4, r7
    1d9c:	e7eb      	b.n	1d76 <z_arm_fault+0x32>
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    1d9e:	ad01      	add	r5, sp, #4
    1da0:	6820      	ldr	r0, [r4, #0]
    1da2:	6861      	ldr	r1, [r4, #4]
    1da4:	68a2      	ldr	r2, [r4, #8]
    1da6:	68e3      	ldr	r3, [r4, #12]
    1da8:	c50f      	stmia	r5!, {r0, r1, r2, r3}
    1daa:	6920      	ldr	r0, [r4, #16]
    1dac:	6961      	ldr	r1, [r4, #20]
    1dae:	69a2      	ldr	r2, [r4, #24]
    1db0:	69e3      	ldr	r3, [r4, #28]
    1db2:	c50f      	stmia	r5!, {r0, r1, r2, r3}
	if (nested_exc) {
    1db4:	b14f      	cbz	r7, 1dca <z_arm_fault+0x86>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    1db6:	9b08      	ldr	r3, [sp, #32]
    1db8:	f3c3 0208 	ubfx	r2, r3, #0, #9
    1dbc:	b95a      	cbnz	r2, 1dd6 <z_arm_fault+0x92>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    1dbe:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    1dc2:	ea6f 2343 	mvn.w	r3, r3, lsl #9
    1dc6:	9308      	str	r3, [sp, #32]
    1dc8:	e005      	b.n	1dd6 <z_arm_fault+0x92>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    1dca:	9b08      	ldr	r3, [sp, #32]
    1dcc:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    1dd0:	f023 0301 	bic.w	r3, r3, #1
    1dd4:	9308      	str	r3, [sp, #32]
	z_arm_fatal_error(reason, &esf_copy);
    1dd6:	a901      	add	r1, sp, #4
    1dd8:	4630      	mov	r0, r6
    1dda:	f003 f862 	bl	4ea2 <z_arm_fatal_error>
    1dde:	e7d3      	b.n	1d88 <z_arm_fault+0x44>
    1de0:	e000ed00 	.word	0xe000ed00

00001de4 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    1de4:	4a02      	ldr	r2, [pc, #8]	; (1df0 <z_arm_fault_init+0xc>)
    1de6:	6953      	ldr	r3, [r2, #20]
    1de8:	f043 0310 	orr.w	r3, r3, #16
    1dec:	6153      	str	r3, [r2, #20]
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
}
    1dee:	4770      	bx	lr
    1df0:	e000ed00 	.word	0xe000ed00

00001df4 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    1df4:	4b04      	ldr	r3, [pc, #16]	; (1e08 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    1df6:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    1df8:	6a58      	ldr	r0, [r3, #36]	; 0x24
	cmp r0, r1
    1dfa:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    1dfc:	d003      	beq.n	1e06 <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    1dfe:	4903      	ldr	r1, [pc, #12]	; (1e0c <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    1e00:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    1e04:	600a      	str	r2, [r1, #0]

00001e06 <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    1e06:	4770      	bx	lr
	ldr r3, =_kernel
    1e08:	200008e4 	.word	0x200008e4
	ldr r1, =_SCS_ICSR
    1e0c:	e000ed04 	.word	0xe000ed04

00001e10 <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    1e10:	4b06      	ldr	r3, [pc, #24]	; (1e2c <z_arm_clear_arm_mpu_config+0x1c>)
    1e12:	6818      	ldr	r0, [r3, #0]
	int num_regions =
    1e14:	f3c0 2007 	ubfx	r0, r0, #8, #8

	for (i = 0; i < num_regions; i++) {
    1e18:	2300      	movs	r3, #0
    1e1a:	4283      	cmp	r3, r0
    1e1c:	da05      	bge.n	1e2a <z_arm_clear_arm_mpu_config+0x1a>
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
    1e1e:	4a03      	ldr	r2, [pc, #12]	; (1e2c <z_arm_clear_arm_mpu_config+0x1c>)
    1e20:	6093      	str	r3, [r2, #8]
  MPU->RASR = 0U;
    1e22:	2100      	movs	r1, #0
    1e24:	6111      	str	r1, [r2, #16]
    1e26:	3301      	adds	r3, #1
    1e28:	e7f7      	b.n	1e1a <z_arm_clear_arm_mpu_config+0xa>
		ARM_MPU_ClrRegion(i);
	}
}
    1e2a:	4770      	bx	lr
    1e2c:	e000ed90 	.word	0xe000ed90

00001e30 <z_arm_init_arch_hw_at_boot>:
 * components and core registers.
 *
 * @return N/A
 */
void z_arm_init_arch_hw_at_boot(void)
{
    1e30:	b510      	push	{r4, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    1e32:	b672      	cpsid	i
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    1e34:	2400      	movs	r4, #0
    1e36:	f384 8813 	msr	FAULTMASK, r4

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    1e3a:	f7ff ffe9 	bl	1e10 <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    1e3e:	4623      	mov	r3, r4
    1e40:	e008      	b.n	1e54 <z_arm_init_arch_hw_at_boot+0x24>
		NVIC->ICER[i] = 0xFFFFFFFF;
    1e42:	f103 0120 	add.w	r1, r3, #32
    1e46:	4a0e      	ldr	r2, [pc, #56]	; (1e80 <z_arm_init_arch_hw_at_boot+0x50>)
    1e48:	f04f 30ff 	mov.w	r0, #4294967295
    1e4c:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    1e50:	3301      	adds	r3, #1
    1e52:	b2db      	uxtb	r3, r3
    1e54:	2b07      	cmp	r3, #7
    1e56:	d9f4      	bls.n	1e42 <z_arm_init_arch_hw_at_boot+0x12>
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    1e58:	2300      	movs	r3, #0
    1e5a:	e008      	b.n	1e6e <z_arm_init_arch_hw_at_boot+0x3e>
		NVIC->ICPR[i] = 0xFFFFFFFF;
    1e5c:	f103 0160 	add.w	r1, r3, #96	; 0x60
    1e60:	4a07      	ldr	r2, [pc, #28]	; (1e80 <z_arm_init_arch_hw_at_boot+0x50>)
    1e62:	f04f 30ff 	mov.w	r0, #4294967295
    1e66:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    1e6a:	3301      	adds	r3, #1
    1e6c:	b2db      	uxtb	r3, r3
    1e6e:	2b07      	cmp	r3, #7
    1e70:	d9f4      	bls.n	1e5c <z_arm_init_arch_hw_at_boot+0x2c>
  __ASM volatile ("cpsie i" : : : "memory");
    1e72:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    1e74:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1e78:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    1e7c:	bd10      	pop	{r4, pc}
    1e7e:	bf00      	nop
    1e80:	e000e100 	.word	0xe000e100

00001e84 <z_arm_interrupt_init>:
 * @return N/A
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    1e84:	2200      	movs	r2, #0

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    1e86:	e006      	b.n	1e96 <z_arm_interrupt_init+0x12>
    1e88:	f002 010f 	and.w	r1, r2, #15
    1e8c:	4b09      	ldr	r3, [pc, #36]	; (1eb4 <z_arm_interrupt_init+0x30>)
    1e8e:	440b      	add	r3, r1
    1e90:	2120      	movs	r1, #32
    1e92:	7619      	strb	r1, [r3, #24]
    1e94:	3201      	adds	r2, #1
    1e96:	2a2f      	cmp	r2, #47	; 0x2f
    1e98:	dc0a      	bgt.n	1eb0 <z_arm_interrupt_init+0x2c>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
    1e9a:	b253      	sxtb	r3, r2
  if ((int32_t)(IRQn) >= 0)
    1e9c:	2b00      	cmp	r3, #0
    1e9e:	dbf3      	blt.n	1e88 <z_arm_interrupt_init+0x4>
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1ea0:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    1ea4:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    1ea8:	2120      	movs	r1, #32
    1eaa:	f883 1300 	strb.w	r1, [r3, #768]	; 0x300
    1eae:	e7f1      	b.n	1e94 <z_arm_interrupt_init+0x10>
	}
}
    1eb0:	4770      	bx	lr
    1eb2:	bf00      	nop
    1eb4:	e000ecfc 	.word	0xe000ecfc

00001eb8 <z_impl_k_thread_abort>:
#include <kswap.h>
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
    1eb8:	b508      	push	{r3, lr}
	if (_current == thread) {
    1eba:	4b08      	ldr	r3, [pc, #32]	; (1edc <z_impl_k_thread_abort+0x24>)
    1ebc:	689b      	ldr	r3, [r3, #8]
    1ebe:	4283      	cmp	r3, r0
    1ec0:	d002      	beq.n	1ec8 <z_impl_k_thread_abort+0x10>
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
		}
	}

	z_thread_abort(thread);
    1ec2:	f002 f93f 	bl	4144 <z_thread_abort>
}
    1ec6:	bd08      	pop	{r3, pc}
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    1ec8:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    1ecc:	2b00      	cmp	r3, #0
    1ece:	d0f8      	beq.n	1ec2 <z_impl_k_thread_abort+0xa>
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    1ed0:	4a03      	ldr	r2, [pc, #12]	; (1ee0 <z_impl_k_thread_abort+0x28>)
    1ed2:	6853      	ldr	r3, [r2, #4]
    1ed4:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    1ed8:	6053      	str	r3, [r2, #4]
    1eda:	e7f2      	b.n	1ec2 <z_impl_k_thread_abort+0xa>
    1edc:	200008e4 	.word	0x200008e4
    1ee0:	e000ed00 	.word	0xe000ed00

00001ee4 <z_arm_configure_static_mpu_regions>:
 *
 * For some MPU architectures, such as the unmodified ARMv8-M MPU,
 * the function must execute with MPU enabled.
 */
void z_arm_configure_static_mpu_regions(void)
{
    1ee4:	b508      	push	{r3, lr}
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    1ee6:	4b03      	ldr	r3, [pc, #12]	; (1ef4 <z_arm_configure_static_mpu_regions+0x10>)
    1ee8:	4a03      	ldr	r2, [pc, #12]	; (1ef8 <z_arm_configure_static_mpu_regions+0x14>)
    1eea:	2101      	movs	r1, #1
    1eec:	4803      	ldr	r0, [pc, #12]	; (1efc <z_arm_configure_static_mpu_regions+0x18>)
    1eee:	f003 f873 	bl	4fd8 <arm_core_mpu_configure_static_mpu_regions>
	};

	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
		ARRAY_SIZE(dyn_region_areas));
#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */
}
    1ef2:	bd08      	pop	{r3, pc}
    1ef4:	20020000 	.word	0x20020000
    1ef8:	20000000 	.word	0x20000000
    1efc:	00005b38 	.word	0x00005b38

00001f00 <region_init>:
 */
static void region_init(const uint32_t index,
	const struct arm_mpu_region *region_conf)
{
	/* Select the region you want to access */
	MPU->RNR = index;
    1f00:	4a06      	ldr	r2, [pc, #24]	; (1f1c <region_init+0x1c>)
    1f02:	6090      	str	r0, [r2, #8]
	/* Configure the region */
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    1f04:	680b      	ldr	r3, [r1, #0]
    1f06:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    1f0a:	4303      	orrs	r3, r0
    1f0c:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    1f10:	60d3      	str	r3, [r2, #12]
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    1f12:	688b      	ldr	r3, [r1, #8]
    1f14:	f043 0301 	orr.w	r3, r3, #1
    1f18:	6113      	str	r3, [r2, #16]
	LOG_DBG("[%d] 0x%08x 0x%08x",
		index, region_conf->base, region_conf->attr.rasr);
}
    1f1a:	4770      	bx	lr
    1f1c:	e000ed90 	.word	0xe000ed90

00001f20 <mpu_configure_static_mpu_regions>:
 */
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
    1f20:	b510      	push	{r4, lr}
	int mpu_reg_index = static_regions_num;
    1f22:	4c03      	ldr	r4, [pc, #12]	; (1f30 <mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    1f24:	2301      	movs	r3, #1
    1f26:	7822      	ldrb	r2, [r4, #0]
    1f28:	f003 f82e 	bl	4f88 <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    1f2c:	7020      	strb	r0, [r4, #0]

	return mpu_reg_index;
}
    1f2e:	bd10      	pop	{r4, pc}
    1f30:	2000094b 	.word	0x2000094b

00001f34 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    1f34:	4b03      	ldr	r3, [pc, #12]	; (1f44 <arm_core_mpu_enable+0x10>)
    1f36:	2205      	movs	r2, #5
    1f38:	605a      	str	r2, [r3, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    1f3a:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1f3e:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    1f42:	4770      	bx	lr
    1f44:	e000ed90 	.word	0xe000ed90

00001f48 <arm_core_mpu_disable>:
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
__STATIC_FORCEINLINE void __DMB(void)
{
  __ASM volatile ("dmb 0xF":::"memory");
    1f48:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    1f4c:	4b01      	ldr	r3, [pc, #4]	; (1f54 <arm_core_mpu_disable+0xc>)
    1f4e:	2200      	movs	r2, #0
    1f50:	605a      	str	r2, [r3, #4]
}
    1f52:	4770      	bx	lr
    1f54:	e000ed90 	.word	0xe000ed90

00001f58 <z_arm_mpu_init>:
 *
 * This function provides the default configuration mechanism for the Memory
 * Protection Unit (MPU).
 */
int z_arm_mpu_init(void)
{
    1f58:	b538      	push	{r3, r4, r5, lr}
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    1f5a:	4b0e      	ldr	r3, [pc, #56]	; (1f94 <z_arm_mpu_init+0x3c>)
    1f5c:	681d      	ldr	r5, [r3, #0]
    1f5e:	2d08      	cmp	r5, #8
    1f60:	d815      	bhi.n	1f8e <z_arm_mpu_init+0x36>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    1f62:	f7ff fff1 	bl	1f48 <arm_core_mpu_disable>

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1f66:	2400      	movs	r4, #0
    1f68:	42a5      	cmp	r5, r4
    1f6a:	d90a      	bls.n	1f82 <z_arm_mpu_init+0x2a>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
    1f6c:	4b09      	ldr	r3, [pc, #36]	; (1f94 <z_arm_mpu_init+0x3c>)
    1f6e:	6859      	ldr	r1, [r3, #4]
    1f70:	eb04 0244 	add.w	r2, r4, r4, lsl #1
    1f74:	0093      	lsls	r3, r2, #2
    1f76:	4419      	add	r1, r3
    1f78:	4620      	mov	r0, r4
    1f7a:	f7ff ffc1 	bl	1f00 <region_init>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1f7e:	3401      	adds	r4, #1
    1f80:	e7f2      	b.n	1f68 <z_arm_mpu_init+0x10>
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    1f82:	4b05      	ldr	r3, [pc, #20]	; (1f98 <z_arm_mpu_init+0x40>)
    1f84:	701d      	strb	r5, [r3, #0]


	arm_core_mpu_enable();
    1f86:	f7ff ffd5 	bl	1f34 <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    1f8a:	2000      	movs	r0, #0
}
    1f8c:	bd38      	pop	{r3, r4, r5, pc}
		return -1;
    1f8e:	f04f 30ff 	mov.w	r0, #4294967295
    1f92:	e7fb      	b.n	1f8c <z_arm_mpu_init+0x34>
    1f94:	00005b5c 	.word	0x00005b5c
    1f98:	2000094b 	.word	0x2000094b

00001f9c <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
    1f9c:	4b01      	ldr	r3, [pc, #4]	; (1fa4 <__stdout_hook_install+0x8>)
    1f9e:	6018      	str	r0, [r3, #0]
}
    1fa0:	4770      	bx	lr
    1fa2:	bf00      	nop
    1fa4:	20000018 	.word	0x20000018

00001fa8 <z_impl_zephyr_write_stdout>:
}
#include <syscalls/z_zephyr_read_stdin_mrsh.c>
#endif

int z_impl_zephyr_write_stdout(const void *buffer, int nbytes)
{
    1fa8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    1faa:	4605      	mov	r5, r0
    1fac:	460f      	mov	r7, r1
	const char *buf = buffer;
	int i;

	for (i = 0; i < nbytes; i++) {
    1fae:	2400      	movs	r4, #0
    1fb0:	e004      	b.n	1fbc <z_impl_zephyr_write_stdout+0x14>
		if (*(buf + i) == '\n') {
			_stdout_hook('\r');
		}
		_stdout_hook(*(buf + i));
    1fb2:	4b09      	ldr	r3, [pc, #36]	; (1fd8 <z_impl_zephyr_write_stdout+0x30>)
    1fb4:	681b      	ldr	r3, [r3, #0]
    1fb6:	7830      	ldrb	r0, [r6, #0]
    1fb8:	4798      	blx	r3
	for (i = 0; i < nbytes; i++) {
    1fba:	3401      	adds	r4, #1
    1fbc:	42bc      	cmp	r4, r7
    1fbe:	da08      	bge.n	1fd2 <z_impl_zephyr_write_stdout+0x2a>
		if (*(buf + i) == '\n') {
    1fc0:	192e      	adds	r6, r5, r4
    1fc2:	5d2b      	ldrb	r3, [r5, r4]
    1fc4:	2b0a      	cmp	r3, #10
    1fc6:	d1f4      	bne.n	1fb2 <z_impl_zephyr_write_stdout+0xa>
			_stdout_hook('\r');
    1fc8:	4b03      	ldr	r3, [pc, #12]	; (1fd8 <z_impl_zephyr_write_stdout+0x30>)
    1fca:	681b      	ldr	r3, [r3, #0]
    1fcc:	200d      	movs	r0, #13
    1fce:	4798      	blx	r3
    1fd0:	e7ef      	b.n	1fb2 <z_impl_zephyr_write_stdout+0xa>
	}
	return nbytes;
}
    1fd2:	4638      	mov	r0, r7
    1fd4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    1fd6:	bf00      	nop
    1fd8:	20000018 	.word	0x20000018

00001fdc <_exit>:
	return 0;
}
__weak FUNC_ALIAS(_fstat, fstat, int);

__weak void _exit(int status)
{
    1fdc:	b508      	push	{r3, lr}
	_write(1, "exit\n", 5);
    1fde:	2205      	movs	r2, #5
    1fe0:	4902      	ldr	r1, [pc, #8]	; (1fec <_exit+0x10>)
    1fe2:	2001      	movs	r0, #1
    1fe4:	f003 f801 	bl	4fea <_write>
	while (1) {
    1fe8:	e7fe      	b.n	1fe8 <_exit+0xc>
    1fea:	bf00      	nop
    1fec:	00005b44 	.word	0x00005b44

00001ff0 <_sbrk>:
		;
	}
}

void *_sbrk(intptr_t count)
{
    1ff0:	4602      	mov	r2, r0
	void *ret, *ptr;

	ptr = ((char *)HEAP_BASE) + heap_sz;
    1ff2:	4b08      	ldr	r3, [pc, #32]	; (2014 <_sbrk+0x24>)
    1ff4:	6819      	ldr	r1, [r3, #0]
    1ff6:	4b08      	ldr	r3, [pc, #32]	; (2018 <_sbrk+0x28>)
    1ff8:	18c8      	adds	r0, r1, r3

	if ((heap_sz + count) < MAX_HEAP_SIZE) {
    1ffa:	440a      	add	r2, r1
    1ffc:	f1c3 5300 	rsb	r3, r3, #536870912	; 0x20000000
    2000:	f503 3300 	add.w	r3, r3, #131072	; 0x20000
    2004:	429a      	cmp	r2, r3
    2006:	d202      	bcs.n	200e <_sbrk+0x1e>
		heap_sz += count;
    2008:	4b02      	ldr	r3, [pc, #8]	; (2014 <_sbrk+0x24>)
    200a:	601a      	str	r2, [r3, #0]
		ret = ptr;
    200c:	4770      	bx	lr
	} else {
		ret = (void *)-1;
    200e:	f04f 30ff 	mov.w	r0, #4294967295
	}

	return ret;
}
    2012:	4770      	bx	lr
    2014:	2000034c 	.word	0x2000034c
    2018:	20001a98 	.word	0x20001a98

0000201c <__malloc_lock>:
__weak FUNC_ALIAS(_sbrk, sbrk, void *);

static LIBC_DATA SYS_MUTEX_DEFINE(heap_mutex);

void __malloc_lock(struct _reent *reent)
{
    201c:	b508      	push	{r3, lr}
	return z_impl_k_mutex_lock(mutex, timeout);
    201e:	f04f 32ff 	mov.w	r2, #4294967295
    2022:	f04f 33ff 	mov.w	r3, #4294967295
    2026:	4802      	ldr	r0, [pc, #8]	; (2030 <__malloc_lock+0x14>)
    2028:	f001 fa3e 	bl	34a8 <z_impl_k_mutex_lock>
	sys_mutex_lock(&heap_mutex, K_FOREVER);
}
    202c:	bd08      	pop	{r3, pc}
    202e:	bf00      	nop
    2030:	2000001c 	.word	0x2000001c

00002034 <__malloc_unlock>:

void __malloc_unlock(struct _reent *reent)
{
    2034:	b508      	push	{r3, lr}
	return z_impl_k_mutex_unlock(mutex);
    2036:	4802      	ldr	r0, [pc, #8]	; (2040 <__malloc_unlock+0xc>)
    2038:	f001 fac0 	bl	35bc <z_impl_k_mutex_unlock>
	sys_mutex_unlock(&heap_mutex);
}
    203c:	bd08      	pop	{r3, pc}
    203e:	bf00      	nop
    2040:	2000001c 	.word	0x2000001c

00002044 <nordicsemi_nrf52_init>:
	__asm__ volatile(
    2044:	f04f 0320 	mov.w	r3, #32
    2048:	f3ef 8211 	mrs	r2, BASEPRI
    204c:	f383 8811 	msr	BASEPRI, r3
    2050:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    2054:	2301      	movs	r3, #1
    2056:	4906      	ldr	r1, [pc, #24]	; (2070 <nordicsemi_nrf52_init+0x2c>)
    2058:	f8c1 3540 	str.w	r3, [r1, #1344]	; 0x540
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    205c:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    2060:	f8c1 3578 	str.w	r3, [r1, #1400]	; 0x578
	__asm__ volatile(
    2064:	f382 8811 	msr	BASEPRI, r2
    2068:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    206c:	2000      	movs	r0, #0
    206e:	4770      	bx	lr
    2070:	4001e000 	.word	0x4001e000

00002074 <sys_arch_reboot>:
    *p_gpregret = val;
    2074:	b2c0      	uxtb	r0, r0
    2076:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    207a:	f8c3 051c 	str.w	r0, [r3, #1308]	; 0x51c
  __ASM volatile ("dsb 0xF":::"memory");
    207e:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2082:	4905      	ldr	r1, [pc, #20]	; (2098 <sys_arch_reboot+0x24>)
    2084:	68ca      	ldr	r2, [r1, #12]
    2086:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    208a:	4b04      	ldr	r3, [pc, #16]	; (209c <sys_arch_reboot+0x28>)
    208c:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    208e:	60cb      	str	r3, [r1, #12]
    2090:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    2094:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    2096:	e7fd      	b.n	2094 <sys_arch_reboot+0x20>
    2098:	e000ed00 	.word	0xe000ed00
    209c:	05fa0004 	.word	0x05fa0004

000020a0 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    20a0:	b130      	cbz	r0, 20b0 <arch_busy_wait+0x10>

void arch_busy_wait(uint32_t time_us)
{
    20a2:	b508      	push	{r3, lr}
    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    20a4:	0180      	lsls	r0, r0, #6
    20a6:	4b03      	ldr	r3, [pc, #12]	; (20b4 <arch_busy_wait+0x14>)
    20a8:	f043 0301 	orr.w	r3, r3, #1
    20ac:	4798      	blx	r3
	nrfx_coredep_delay_us(time_us);
}
    20ae:	bd08      	pop	{r3, pc}
    20b0:	4770      	bx	lr
    20b2:	bf00      	nop
    20b4:	00005a90 	.word	0x00005a90

000020b8 <gpio_nrfx_config>:
	return res;
}

static int gpio_nrfx_config(const struct device *port,
			    gpio_pin_t pin, gpio_flags_t flags)
{
    20b8:	b4f0      	push	{r4, r5, r6, r7}
	return port->config;
    20ba:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    20bc:	685f      	ldr	r7, [r3, #4]
	nrf_gpio_pin_pull_t pull;
	nrf_gpio_pin_drive_t drive;
	nrf_gpio_pin_dir_t dir;
	nrf_gpio_pin_input_t input;

	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    20be:	4b37      	ldr	r3, [pc, #220]	; (219c <gpio_nrfx_config+0xe4>)
    20c0:	4013      	ands	r3, r2
    20c2:	4c37      	ldr	r4, [pc, #220]	; (21a0 <gpio_nrfx_config+0xe8>)
    20c4:	42a3      	cmp	r3, r4
    20c6:	d027      	beq.n	2118 <gpio_nrfx_config+0x60>
    20c8:	d812      	bhi.n	20f0 <gpio_nrfx_config+0x38>
    20ca:	2b06      	cmp	r3, #6
    20cc:	d026      	beq.n	211c <gpio_nrfx_config+0x64>
    20ce:	d904      	bls.n	20da <gpio_nrfx_config+0x22>
    20d0:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    20d4:	d109      	bne.n	20ea <gpio_nrfx_config+0x32>
	case GPIO_DS_DFLT_LOW | GPIO_OPEN_DRAIN:
		drive = NRF_GPIO_PIN_S0D1;
		break;

	case GPIO_DS_ALT_LOW | GPIO_DS_DFLT_HIGH:
		drive = NRF_GPIO_PIN_H0S1;
    20d6:	2401      	movs	r4, #1
    20d8:	e016      	b.n	2108 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    20da:	b30b      	cbz	r3, 2120 <gpio_nrfx_config+0x68>
    20dc:	2b02      	cmp	r3, #2
    20de:	d101      	bne.n	20e4 <gpio_nrfx_config+0x2c>
	case GPIO_DS_ALT_LOW | GPIO_OPEN_DRAIN:
		drive = NRF_GPIO_PIN_H0D1;
		break;

	case GPIO_DS_DFLT_HIGH | GPIO_OPEN_SOURCE:
		drive = NRF_GPIO_PIN_D0S1;
    20e0:	2404      	movs	r4, #4
    20e2:	e011      	b.n	2108 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    20e4:	f06f 0015 	mvn.w	r0, #21
    20e8:	e046      	b.n	2178 <gpio_nrfx_config+0xc0>
    20ea:	f06f 0015 	mvn.w	r0, #21
    20ee:	e043      	b.n	2178 <gpio_nrfx_config+0xc0>
    20f0:	4c2c      	ldr	r4, [pc, #176]	; (21a4 <gpio_nrfx_config+0xec>)
    20f2:	42a3      	cmp	r3, r4
    20f4:	d016      	beq.n	2124 <gpio_nrfx_config+0x6c>
    20f6:	f5b3 0fa0 	cmp.w	r3, #5242880	; 0x500000
    20fa:	d101      	bne.n	2100 <gpio_nrfx_config+0x48>
		drive = NRF_GPIO_PIN_H0H1;
    20fc:	2403      	movs	r4, #3
    20fe:	e003      	b.n	2108 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    2100:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
    2104:	d146      	bne.n	2194 <gpio_nrfx_config+0xdc>
		drive = NRF_GPIO_PIN_S0H1;
    2106:	2402      	movs	r4, #2

	default:
		return -EINVAL;
	}

	if ((flags & GPIO_PULL_UP) != 0) {
    2108:	f012 0f10 	tst.w	r2, #16
    210c:	d10c      	bne.n	2128 <gpio_nrfx_config+0x70>
		pull = NRF_GPIO_PIN_PULLUP;
	} else if ((flags & GPIO_PULL_DOWN) != 0) {
    210e:	f012 0f20 	tst.w	r2, #32
    2112:	d033      	beq.n	217c <gpio_nrfx_config+0xc4>
		pull = NRF_GPIO_PIN_PULLDOWN;
    2114:	2501      	movs	r5, #1
    2116:	e008      	b.n	212a <gpio_nrfx_config+0x72>
		drive = NRF_GPIO_PIN_H0D1;
    2118:	2407      	movs	r4, #7
    211a:	e7f5      	b.n	2108 <gpio_nrfx_config+0x50>
		drive = NRF_GPIO_PIN_S0D1;
    211c:	2406      	movs	r4, #6
    211e:	e7f3      	b.n	2108 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    2120:	2400      	movs	r4, #0
    2122:	e7f1      	b.n	2108 <gpio_nrfx_config+0x50>
		drive = NRF_GPIO_PIN_D0H1;
    2124:	2405      	movs	r4, #5
    2126:	e7ef      	b.n	2108 <gpio_nrfx_config+0x50>
		pull = NRF_GPIO_PIN_PULLUP;
    2128:	2503      	movs	r5, #3
	} else {
		pull = NRF_GPIO_PIN_NOPULL;
	}

	dir = ((flags & GPIO_OUTPUT) != 0)
    212a:	f3c2 2340 	ubfx	r3, r2, #9, #1
	      ? NRF_GPIO_PIN_DIR_OUTPUT
	      : NRF_GPIO_PIN_DIR_INPUT;

	input = ((flags & GPIO_INPUT) != 0)
		? NRF_GPIO_PIN_INPUT_CONNECT
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
    212e:	f412 7f80 	tst.w	r2, #256	; 0x100
    2132:	bf0c      	ite	eq
    2134:	2601      	moveq	r6, #1
    2136:	2600      	movne	r6, #0

	if ((flags & GPIO_OUTPUT) != 0) {
    2138:	f412 7f00 	tst.w	r2, #512	; 0x200
    213c:	d006      	beq.n	214c <gpio_nrfx_config+0x94>
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
    213e:	f412 6f00 	tst.w	r2, #2048	; 0x800
    2142:	d01d      	beq.n	2180 <gpio_nrfx_config+0xc8>
			nrf_gpio_port_out_set(reg, BIT(pin));
    2144:	2201      	movs	r2, #1
    2146:	408a      	lsls	r2, r1
}


NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
{
    p_reg->OUTSET = set_mask;
    2148:	f8c7 2508 	str.w	r2, [r7, #1288]	; 0x508
	return port->config;
    214c:	6842      	ldr	r2, [r0, #4]
		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
			nrf_gpio_port_out_clear(reg, BIT(pin));
		}
	}

	nrf_gpio_cfg(NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin),
    214e:	7a12      	ldrb	r2, [r2, #8]
    2150:	f001 011f 	and.w	r1, r1, #31
    2154:	ea41 1242 	orr.w	r2, r1, r2, lsl #5
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;

    return pin_number >> 5;
    2158:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    215a:	2a01      	cmp	r2, #1
    215c:	d018      	beq.n	2190 <gpio_nrfx_config+0xd8>
        case 0: return NRF_P0;
    215e:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    2162:	ea43 0346 	orr.w	r3, r3, r6, lsl #1
           ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) |
    2166:	ea43 0385 	orr.w	r3, r3, r5, lsl #2
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    216a:	ea43 2304 	orr.w	r3, r3, r4, lsl #8
    reg->PIN_CNF[pin_number] = cnf;
    216e:	f501 71e0 	add.w	r1, r1, #448	; 0x1c0
    2172:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
		     dir, input, pull, drive, NRF_GPIO_PIN_NOSENSE);

	return 0;
    2176:	2000      	movs	r0, #0
}
    2178:	bcf0      	pop	{r4, r5, r6, r7}
    217a:	4770      	bx	lr
		pull = NRF_GPIO_PIN_NOPULL;
    217c:	2500      	movs	r5, #0
    217e:	e7d4      	b.n	212a <gpio_nrfx_config+0x72>
		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
    2180:	f412 6f80 	tst.w	r2, #1024	; 0x400
    2184:	d0e2      	beq.n	214c <gpio_nrfx_config+0x94>
			nrf_gpio_port_out_clear(reg, BIT(pin));
    2186:	2201      	movs	r2, #1
    2188:	408a      	lsls	r2, r1
    p_reg->OUTCLR = clr_mask;
    218a:	f8c7 250c 	str.w	r2, [r7, #1292]	; 0x50c
}
    218e:	e7dd      	b.n	214c <gpio_nrfx_config+0x94>
        case 1: return NRF_P1;
    2190:	4a05      	ldr	r2, [pc, #20]	; (21a8 <gpio_nrfx_config+0xf0>)
    2192:	e7e6      	b.n	2162 <gpio_nrfx_config+0xaa>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    2194:	f06f 0015 	mvn.w	r0, #21
    2198:	e7ee      	b.n	2178 <gpio_nrfx_config+0xc0>
    219a:	bf00      	nop
    219c:	00f00006 	.word	0x00f00006
    21a0:	00100006 	.word	0x00100006
    21a4:	00400002 	.word	0x00400002
    21a8:	50000300 	.word	0x50000300

000021ac <cfg_level_pins>:
	 */
	return out;
}

static void cfg_level_pins(const struct device *port)
{
    21ac:	b4f0      	push	{r4, r5, r6, r7}
	return port->data;
    21ae:	6905      	ldr	r5, [r0, #16]
	return port->config;
    21b0:	6846      	ldr	r6, [r0, #4]
	uint32_t out = data->pin_int_en;
    21b2:	68e9      	ldr	r1, [r5, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    21b4:	696a      	ldr	r2, [r5, #20]
    21b6:	69ab      	ldr	r3, [r5, #24]
    21b8:	4313      	orrs	r3, r2
    21ba:	ea21 0103 	bic.w	r1, r1, r3
	const struct gpio_nrfx_data *data = get_port_data(port);
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
	uint32_t pin = 0U;
	uint32_t bit = 1U << pin;
    21be:	2301      	movs	r3, #1
	uint32_t pin = 0U;
    21c0:	2000      	movs	r0, #0
	uint32_t level_pins = get_level_pins(port);

	/* Configure sense detection on all pins that use it. */
	while (level_pins) {
    21c2:	e011      	b.n	21e8 <cfg_level_pins+0x3c>
		return NRF_GPIO_PIN_SENSE_HIGH;
    21c4:	f04f 0c02 	mov.w	ip, #2
    21c8:	e01d      	b.n	2206 <cfg_level_pins+0x5a>
    21ca:	4f14      	ldr	r7, [pc, #80]	; (221c <cfg_level_pins+0x70>)
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    21cc:	f504 74e0 	add.w	r4, r4, #448	; 0x1c0
    21d0:	f857 2024 	ldr.w	r2, [r7, r4, lsl #2]
    21d4:	f422 3240 	bic.w	r2, r2, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    21d8:	ea42 420c 	orr.w	r2, r2, ip, lsl #16
    21dc:	f847 2024 	str.w	r2, [r7, r4, lsl #2]
		if (level_pins & bit) {
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
			uint32_t sense = sense_for_pin(data, pin);

			nrf_gpio_cfg_sense_set(abs_pin, sense);
			level_pins &= ~bit;
    21e0:	ea21 0103 	bic.w	r1, r1, r3
		}
		++pin;
    21e4:	3001      	adds	r0, #1
		bit <<= 1;
    21e6:	005b      	lsls	r3, r3, #1
	while (level_pins) {
    21e8:	b1a9      	cbz	r1, 2216 <cfg_level_pins+0x6a>
		if (level_pins & bit) {
    21ea:	420b      	tst	r3, r1
    21ec:	d0fa      	beq.n	21e4 <cfg_level_pins+0x38>
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    21ee:	7a34      	ldrb	r4, [r6, #8]
    21f0:	f000 021f 	and.w	r2, r0, #31
    21f4:	ea42 1244 	orr.w	r2, r2, r4, lsl #5
	if ((BIT(pin) & data->int_active_level) != 0U) {
    21f8:	692c      	ldr	r4, [r5, #16]
    21fa:	40c4      	lsrs	r4, r0
    21fc:	f014 0f01 	tst.w	r4, #1
    2200:	d1e0      	bne.n	21c4 <cfg_level_pins+0x18>
	return NRF_GPIO_PIN_SENSE_LOW;
    2202:	f04f 0c03 	mov.w	ip, #3
    *p_pin = pin_number & 0x1F;
    2206:	f002 041f 	and.w	r4, r2, #31
    return pin_number >> 5;
    220a:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    220c:	2a01      	cmp	r2, #1
    220e:	d0dc      	beq.n	21ca <cfg_level_pins+0x1e>
        case 0: return NRF_P0;
    2210:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    2214:	e7da      	b.n	21cc <cfg_level_pins+0x20>
	}
}
    2216:	bcf0      	pop	{r4, r5, r6, r7}
    2218:	4770      	bx	lr
    221a:	bf00      	nop
    221c:	50000300 	.word	0x50000300

00002220 <check_level_trigger_pins>:
 *
 * @return Bitmask where 1 marks pin as trigger source.
 */
static uint32_t check_level_trigger_pins(const struct device *port,
					 uint32_t *sense_levels)
{
    2220:	b5f0      	push	{r4, r5, r6, r7, lr}
    2222:	468c      	mov	ip, r1
	return port->data;
    2224:	6903      	ldr	r3, [r0, #16]
	return port->config;
    2226:	6841      	ldr	r1, [r0, #4]
	uint32_t out = data->pin_int_en;
    2228:	68df      	ldr	r7, [r3, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    222a:	695a      	ldr	r2, [r3, #20]
    222c:	6998      	ldr	r0, [r3, #24]
    222e:	4302      	orrs	r2, r0
    2230:	ea27 0702 	bic.w	r7, r7, r2
	struct gpio_nrfx_data *data = get_port_data(port);
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
	uint32_t level_pins = get_level_pins(port);
	uint32_t port_in = nrf_gpio_port_in_read(cfg->port);
    2234:	684a      	ldr	r2, [r1, #4]
    return p_reg->IN;
    2236:	f8d2 2510 	ldr.w	r2, [r2, #1296]	; 0x510

	/* Extract which pins have logic level same as interrupt trigger level.
	 */
	uint32_t pin_states = ~(port_in ^ data->int_active_level);
    223a:	6918      	ldr	r0, [r3, #16]
    223c:	4050      	eors	r0, r2

	/* Discard pins that aren't configured for level. */
	uint32_t out = pin_states & level_pins;
    223e:	ea27 0000 	bic.w	r0, r7, r0
	uint32_t pin = 0U;
	uint32_t bit = 1U << pin;

	uint32_t port_latch = 0;

	uint32_t check_pins = level_pins;
    2242:	463c      	mov	r4, r7
	uint32_t bit = 1U << pin;
    2244:	2301      	movs	r3, #1
	uint32_t pin = 0U;
    2246:	2500      	movs	r5, #0
#if IS_ENABLED(CONFIG_GPIO_NRF_INT_EDGE_USING_SENSE)
	/* Read LATCH, which will tell us which pin has changed its state. */
	port_latch = cfg->port->LATCH;
#endif

	while (check_pins) {
    2248:	e015      	b.n	2276 <check_level_trigger_pins+0x56>
        case 1: return NRF_P1;
    224a:	f8df e074 	ldr.w	lr, [pc, #116]	; 22c0 <check_level_trigger_pins+0xa0>
    224e:	e025      	b.n	229c <check_level_trigger_pins+0x7c>
    *p_pin = pin_number & 0x1F;
    2250:	f002 061f 	and.w	r6, r2, #31
    return pin_number >> 5;
    2254:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    2256:	2a01      	cmp	r2, #1
    2258:	d02e      	beq.n	22b8 <check_level_trigger_pins+0x98>
        case 0: return NRF_P0;
    225a:	f04f 4ea0 	mov.w	lr, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    225e:	f506 72e0 	add.w	r2, r6, #448	; 0x1c0
    2262:	f85e 6022 	ldr.w	r6, [lr, r2, lsl #2]
    2266:	f426 3640 	bic.w	r6, r6, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    226a:	f84e 6022 	str.w	r6, [lr, r2, lsl #2]
					*sense_levels |= bit;
				}
			}

			nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
			check_pins &= ~bit;
    226e:	ea24 0403 	bic.w	r4, r4, r3
		}
		++pin;
    2272:	3501      	adds	r5, #1
		bit <<= 1;
    2274:	005b      	lsls	r3, r3, #1
	while (check_pins) {
    2276:	b314      	cbz	r4, 22be <check_level_trigger_pins+0x9e>
		if (check_pins & bit) {
    2278:	4223      	tst	r3, r4
    227a:	d0fa      	beq.n	2272 <check_level_trigger_pins+0x52>
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    227c:	7a0e      	ldrb	r6, [r1, #8]
    227e:	f005 021f 	and.w	r2, r5, #31
    2282:	ea42 1246 	orr.w	r2, r2, r6, lsl #5
			if (!(level_pins & bit)) {
    2286:	423b      	tst	r3, r7
    2288:	d1e2      	bne.n	2250 <check_level_trigger_pins+0x30>
    *p_pin = pin_number & 0x1F;
    228a:	f002 061f 	and.w	r6, r2, #31
    return pin_number >> 5;
    228e:	ea4f 1e52 	mov.w	lr, r2, lsr #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    2292:	f1be 0f01 	cmp.w	lr, #1
    2296:	d0d8      	beq.n	224a <check_level_trigger_pins+0x2a>
        case 0: return NRF_P0;
    2298:	f04f 4ea0 	mov.w	lr, #1342177280	; 0x50000000
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    229c:	f506 76e0 	add.w	r6, r6, #448	; 0x1c0
    22a0:	f85e 6026 	ldr.w	r6, [lr, r6, lsl #2]
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    22a4:	f3c6 4601 	ubfx	r6, r6, #16, #2
				if (high) {
    22a8:	2e02      	cmp	r6, #2
    22aa:	d1d1      	bne.n	2250 <check_level_trigger_pins+0x30>
					*sense_levels |= bit;
    22ac:	f8dc 6000 	ldr.w	r6, [ip]
    22b0:	431e      	orrs	r6, r3
    22b2:	f8cc 6000 	str.w	r6, [ip]
    22b6:	e7cb      	b.n	2250 <check_level_trigger_pins+0x30>
        case 1: return NRF_P1;
    22b8:	f8df e004 	ldr.w	lr, [pc, #4]	; 22c0 <check_level_trigger_pins+0xa0>
    22bc:	e7cf      	b.n	225e <check_level_trigger_pins+0x3e>
	 */
	cfg->port->LATCH = port_latch;
#endif

	return out;
}
    22be:	bdf0      	pop	{r4, r5, r6, r7, pc}
    22c0:	50000300 	.word	0x50000300

000022c4 <gpiote_pin_cleanup>:
{
    22c4:	b510      	push	{r4, lr}
    p_reg->INTENCLR = mask;
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask)
{
    return p_reg->INTENSET & mask;
    22c6:	4b14      	ldr	r3, [pc, #80]	; (2318 <gpiote_pin_cleanup+0x54>)
    22c8:	f8d3 4304 	ldr.w	r4, [r3, #772]	; 0x304
    22cc:	b2e4      	uxtb	r4, r4
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    22ce:	2300      	movs	r3, #0
    22d0:	e000      	b.n	22d4 <gpiote_pin_cleanup+0x10>
    22d2:	3301      	adds	r3, #1
    22d4:	2b07      	cmp	r3, #7
    22d6:	d81d      	bhi.n	2314 <gpiote_pin_cleanup+0x50>
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
{
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    22d8:	f503 72a2 	add.w	r2, r3, #324	; 0x144
    22dc:	490e      	ldr	r1, [pc, #56]	; (2318 <gpiote_pin_cleanup+0x54>)
    22de:	f851 2022 	ldr.w	r2, [r1, r2, lsl #2]
    22e2:	f3c2 2205 	ubfx	r2, r2, #8, #6
		if ((nrf_gpiote_event_pin_get(NRF_GPIOTE, i) == abs_pin)
    22e6:	4290      	cmp	r0, r2
    22e8:	d1f3      	bne.n	22d2 <gpiote_pin_cleanup+0xe>
		    && (intenset & BIT(i))) {
    22ea:	fa24 f203 	lsr.w	r2, r4, r3
    22ee:	f012 0f01 	tst.w	r2, #1
    22f2:	d0ee      	beq.n	22d2 <gpiote_pin_cleanup+0xe>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
    22f4:	460a      	mov	r2, r1
    22f6:	f503 70a2 	add.w	r0, r3, #324	; 0x144
    22fa:	f851 1020 	ldr.w	r1, [r1, r0, lsl #2]
    22fe:	f021 0101 	bic.w	r1, r1, #1
    2302:	f842 1020 	str.w	r1, [r2, r0, lsl #2]
			nrf_gpiote_int_disable(NRF_GPIOTE, BIT(i));
    2306:	2101      	movs	r1, #1
    2308:	4099      	lsls	r1, r3
    p_reg->INTENCLR = mask;
    230a:	f8c2 1308 	str.w	r1, [r2, #776]	; 0x308
			nrfx_gpiote_channel_free(i);
    230e:	b2d8      	uxtb	r0, r3
    2310:	f000 fe52 	bl	2fb8 <nrfx_gpiote_channel_free>
}
    2314:	bd10      	pop	{r4, pc}
    2316:	bf00      	nop
    2318:	40006000 	.word	0x40006000

0000231c <gpiote_channel_alloc>:
{
    231c:	b570      	push	{r4, r5, r6, lr}
    231e:	b082      	sub	sp, #8
    2320:	4604      	mov	r4, r0
    2322:	460d      	mov	r5, r1
	if (nrfx_gpiote_channel_alloc(&channel) != NRFX_SUCCESS) {
    2324:	f10d 0007 	add.w	r0, sp, #7
    2328:	f000 fe62 	bl	2ff0 <nrfx_gpiote_channel_alloc>
    232c:	4b1c      	ldr	r3, [pc, #112]	; (23a0 <gpiote_channel_alloc+0x84>)
    232e:	4298      	cmp	r0, r3
    2330:	d132      	bne.n	2398 <gpiote_channel_alloc+0x7c>
	nrf_gpiote_event_t evt = offsetof(NRF_GPIOTE_Type, EVENTS_IN[channel]);
    2332:	f89d 3007 	ldrb.w	r3, [sp, #7]
    2336:	f103 0240 	add.w	r2, r3, #64	; 0x40
    233a:	0092      	lsls	r2, r2, #2
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    233c:	4e19      	ldr	r6, [pc, #100]	; (23a4 <gpiote_channel_alloc+0x88>)
    233e:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    2342:	f856 1023 	ldr.w	r1, [r6, r3, lsl #2]
    2346:	f421 314f 	bic.w	r1, r1, #211968	; 0x33c00
    234a:	f421 7140 	bic.w	r1, r1, #768	; 0x300
    234e:	f846 1023 	str.w	r1, [r6, r3, lsl #2]
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2352:	f856 1023 	ldr.w	r1, [r6, r3, lsl #2]
    2356:	0224      	lsls	r4, r4, #8
    2358:	f404 547c 	and.w	r4, r4, #16128	; 0x3f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
    235c:	042d      	lsls	r5, r5, #16
    235e:	f405 3540 	and.w	r5, r5, #196608	; 0x30000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2362:	432c      	orrs	r4, r5
    2364:	430c      	orrs	r4, r1
    2366:	f846 4023 	str.w	r4, [r6, r3, lsl #2]
    return ((uint32_t)p_reg + event);
    236a:	f102 4380 	add.w	r3, r2, #1073741824	; 0x40000000
    236e:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2372:	2000      	movs	r0, #0
    2374:	6018      	str	r0, [r3, #0]
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    2376:	681b      	ldr	r3, [r3, #0]
	nrf_gpiote_event_enable(NRF_GPIOTE, channel);
    2378:	f89d 1007 	ldrb.w	r1, [sp, #7]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    237c:	f501 73a2 	add.w	r3, r1, #324	; 0x144
    2380:	f856 2023 	ldr.w	r2, [r6, r3, lsl #2]
    2384:	f042 0201 	orr.w	r2, r2, #1
    2388:	f846 2023 	str.w	r2, [r6, r3, lsl #2]
	nrf_gpiote_int_enable(NRF_GPIOTE, BIT(channel));
    238c:	2301      	movs	r3, #1
    238e:	408b      	lsls	r3, r1
    p_reg->INTENSET = mask;
    2390:	f8c6 3304 	str.w	r3, [r6, #772]	; 0x304
}
    2394:	b002      	add	sp, #8
    2396:	bd70      	pop	{r4, r5, r6, pc}
		return -ENODEV;
    2398:	f06f 0012 	mvn.w	r0, #18
    239c:	e7fa      	b.n	2394 <gpiote_channel_alloc+0x78>
    239e:	bf00      	nop
    23a0:	0bad0000 	.word	0x0bad0000
    23a4:	40006000 	.word	0x40006000

000023a8 <gpiote_pin_int_cfg>:
{
    23a8:	b570      	push	{r4, r5, r6, lr}
    23aa:	460d      	mov	r5, r1
	return port->data;
    23ac:	6906      	ldr	r6, [r0, #16]
	return port->config;
    23ae:	6843      	ldr	r3, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    23b0:	7a1b      	ldrb	r3, [r3, #8]
    23b2:	f001 041f 	and.w	r4, r1, #31
    23b6:	ea44 1443 	orr.w	r4, r4, r3, lsl #5
	gpiote_pin_cleanup(abs_pin);
    23ba:	4620      	mov	r0, r4
    23bc:	f7ff ff82 	bl	22c4 <gpiote_pin_cleanup>
    *p_pin = pin_number & 0x1F;
    23c0:	f004 001f 	and.w	r0, r4, #31
    return pin_number >> 5;
    23c4:	0963      	lsrs	r3, r4, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    23c6:	2b01      	cmp	r3, #1
    23c8:	d020      	beq.n	240c <gpiote_pin_int_cfg+0x64>
        case 0: return NRF_P0;
    23ca:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    23ce:	f500 71e0 	add.w	r1, r0, #448	; 0x1c0
    23d2:	f852 3021 	ldr.w	r3, [r2, r1, lsl #2]
    23d6:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    23da:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
	if (data->pin_int_en & BIT(pin)) {
    23de:	68f3      	ldr	r3, [r6, #12]
    23e0:	40eb      	lsrs	r3, r5
    23e2:	f013 0f01 	tst.w	r3, #1
    23e6:	d02f      	beq.n	2448 <gpiote_pin_int_cfg+0xa0>
		if (data->trig_edge & BIT(pin)) {
    23e8:	6973      	ldr	r3, [r6, #20]
    23ea:	40eb      	lsrs	r3, r5
    23ec:	f013 0f01 	tst.w	r3, #1
    23f0:	d015      	beq.n	241e <gpiote_pin_int_cfg+0x76>
				if (data->double_edge & BIT(pin)) {
    23f2:	69b3      	ldr	r3, [r6, #24]
    23f4:	40eb      	lsrs	r3, r5
    23f6:	f013 0f01 	tst.w	r3, #1
    23fa:	d109      	bne.n	2410 <gpiote_pin_int_cfg+0x68>
				} else if ((data->int_active_level & BIT(pin)) != 0U) {
    23fc:	6931      	ldr	r1, [r6, #16]
    23fe:	fa21 f505 	lsr.w	r5, r1, r5
    2402:	f015 0f01 	tst.w	r5, #1
    2406:	d008      	beq.n	241a <gpiote_pin_int_cfg+0x72>
					pol = NRF_GPIOTE_POLARITY_LOTOHI;
    2408:	2101      	movs	r1, #1
    240a:	e002      	b.n	2412 <gpiote_pin_int_cfg+0x6a>
        case 1: return NRF_P1;
    240c:	4a0f      	ldr	r2, [pc, #60]	; (244c <gpiote_pin_int_cfg+0xa4>)
    240e:	e7de      	b.n	23ce <gpiote_pin_int_cfg+0x26>
					pol = NRF_GPIOTE_POLARITY_TOGGLE;
    2410:	2103      	movs	r1, #3
				res = gpiote_channel_alloc(abs_pin, pol);
    2412:	4620      	mov	r0, r4
    2414:	f7ff ff82 	bl	231c <gpiote_channel_alloc>
    2418:	e017      	b.n	244a <gpiote_pin_int_cfg+0xa2>
					pol = NRF_GPIOTE_POLARITY_HITOLO;
    241a:	2102      	movs	r1, #2
    241c:	e7f9      	b.n	2412 <gpiote_pin_int_cfg+0x6a>
	if ((BIT(pin) & data->int_active_level) != 0U) {
    241e:	6931      	ldr	r1, [r6, #16]
    2420:	fa21 f505 	lsr.w	r5, r1, r5
    2424:	f015 0f01 	tst.w	r5, #1
    2428:	d10c      	bne.n	2444 <gpiote_pin_int_cfg+0x9c>
	return NRF_GPIO_PIN_SENSE_LOW;
    242a:	2103      	movs	r1, #3
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    242c:	f500 70e0 	add.w	r0, r0, #448	; 0x1c0
    2430:	f852 3020 	ldr.w	r3, [r2, r0, lsl #2]
    2434:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    2438:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
    243c:	f842 3020 	str.w	r3, [r2, r0, lsl #2]
	int res = 0;
    2440:	2000      	movs	r0, #0
}
    2442:	e002      	b.n	244a <gpiote_pin_int_cfg+0xa2>
		return NRF_GPIO_PIN_SENSE_HIGH;
    2444:	2102      	movs	r1, #2
    2446:	e7f1      	b.n	242c <gpiote_pin_int_cfg+0x84>
	int res = 0;
    2448:	2000      	movs	r0, #0
}
    244a:	bd70      	pop	{r4, r5, r6, pc}
    244c:	50000300 	.word	0x50000300

00002450 <gpio_nrfx_pin_interrupt_configure>:
{
    2450:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	return port->data;
    2452:	6904      	ldr	r4, [r0, #16]
	return port->config;
    2454:	6845      	ldr	r5, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    2456:	7a2e      	ldrb	r6, [r5, #8]
    2458:	f001 051f 	and.w	r5, r1, #31
    245c:	ea45 1546 	orr.w	r5, r5, r6, lsl #5
	if (!IS_ENABLED(CONFIG_GPIO_NRF_INT_EDGE_USING_SENSE) &&
    2460:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    2464:	d025      	beq.n	24b2 <gpio_nrfx_pin_interrupt_configure+0x62>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    2466:	f5b2 5f00 	cmp.w	r2, #8192	; 0x2000
    246a:	d035      	beq.n	24d8 <gpio_nrfx_pin_interrupt_configure+0x88>
    246c:	68e5      	ldr	r5, [r4, #12]
    246e:	2601      	movs	r6, #1
    2470:	408e      	lsls	r6, r1
    2472:	4335      	orrs	r5, r6
    2474:	60e5      	str	r5, [r4, #12]
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    2476:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    247a:	d033      	beq.n	24e4 <gpio_nrfx_pin_interrupt_configure+0x94>
    247c:	6962      	ldr	r2, [r4, #20]
    247e:	2501      	movs	r5, #1
    2480:	408d      	lsls	r5, r1
    2482:	ea22 0205 	bic.w	r2, r2, r5
    2486:	6162      	str	r2, [r4, #20]
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
    2488:	f5b3 2fc0 	cmp.w	r3, #393216	; 0x60000
    248c:	d02f      	beq.n	24ee <gpio_nrfx_pin_interrupt_configure+0x9e>
    248e:	69a2      	ldr	r2, [r4, #24]
    2490:	2501      	movs	r5, #1
    2492:	408d      	lsls	r5, r1
    2494:	ea22 0205 	bic.w	r2, r2, r5
    2498:	61a2      	str	r2, [r4, #24]
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    249a:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
    249e:	d02b      	beq.n	24f8 <gpio_nrfx_pin_interrupt_configure+0xa8>
    24a0:	6923      	ldr	r3, [r4, #16]
    24a2:	2201      	movs	r2, #1
    24a4:	408a      	lsls	r2, r1
    24a6:	ea23 0302 	bic.w	r3, r3, r2
    24aa:	6123      	str	r3, [r4, #16]
	return gpiote_pin_int_cfg(port, pin);
    24ac:	f7ff ff7c 	bl	23a8 <gpiote_pin_int_cfg>
}
    24b0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    *p_pin = pin_number & 0x1F;
    24b2:	f005 061f 	and.w	r6, r5, #31
    return pin_number >> 5;
    24b6:	096d      	lsrs	r5, r5, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    24b8:	2d01      	cmp	r5, #1
    24ba:	d00b      	beq.n	24d4 <gpio_nrfx_pin_interrupt_configure+0x84>
        case 0: return NRF_P0;
    24bc:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    24c0:	f506 75e0 	add.w	r5, r6, #448	; 0x1c0
    24c4:	f857 5025 	ldr.w	r5, [r7, r5, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    24c8:	f015 0f01 	tst.w	r5, #1
    24cc:	d0cb      	beq.n	2466 <gpio_nrfx_pin_interrupt_configure+0x16>
		return -ENOTSUP;
    24ce:	f06f 0085 	mvn.w	r0, #133	; 0x85
    24d2:	e7ed      	b.n	24b0 <gpio_nrfx_pin_interrupt_configure+0x60>
        case 1: return NRF_P1;
    24d4:	4f0b      	ldr	r7, [pc, #44]	; (2504 <gpio_nrfx_pin_interrupt_configure+0xb4>)
    24d6:	e7f3      	b.n	24c0 <gpio_nrfx_pin_interrupt_configure+0x70>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    24d8:	68e5      	ldr	r5, [r4, #12]
    24da:	2601      	movs	r6, #1
    24dc:	408e      	lsls	r6, r1
    24de:	ea25 0506 	bic.w	r5, r5, r6
    24e2:	e7c7      	b.n	2474 <gpio_nrfx_pin_interrupt_configure+0x24>
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    24e4:	6962      	ldr	r2, [r4, #20]
    24e6:	2501      	movs	r5, #1
    24e8:	408d      	lsls	r5, r1
    24ea:	432a      	orrs	r2, r5
    24ec:	e7cb      	b.n	2486 <gpio_nrfx_pin_interrupt_configure+0x36>
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
    24ee:	69a2      	ldr	r2, [r4, #24]
    24f0:	2501      	movs	r5, #1
    24f2:	408d      	lsls	r5, r1
    24f4:	432a      	orrs	r2, r5
    24f6:	e7cf      	b.n	2498 <gpio_nrfx_pin_interrupt_configure+0x48>
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    24f8:	6923      	ldr	r3, [r4, #16]
    24fa:	2201      	movs	r2, #1
    24fc:	408a      	lsls	r2, r1
    24fe:	4313      	orrs	r3, r2
    2500:	e7d3      	b.n	24aa <gpio_nrfx_pin_interrupt_configure+0x5a>
    2502:	bf00      	nop
    2504:	50000300 	.word	0x50000300

00002508 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    2508:	b508      	push	{r3, lr}
	static bool gpio_initialized;

	if (!gpio_initialized) {
    250a:	4b0b      	ldr	r3, [pc, #44]	; (2538 <gpio_nrfx_init+0x30>)
    250c:	781b      	ldrb	r3, [r3, #0]
    250e:	b10b      	cbz	r3, 2514 <gpio_nrfx_init+0xc>
		irq_enable(DT_IRQN(GPIOTE_NODE));
		nrf_gpiote_int_enable(NRF_GPIOTE, NRF_GPIOTE_INT_PORT_MASK);
	}

	return 0;
}
    2510:	2000      	movs	r0, #0
    2512:	bd08      	pop	{r3, pc}
		gpio_initialized = true;
    2514:	4b08      	ldr	r3, [pc, #32]	; (2538 <gpio_nrfx_init+0x30>)
    2516:	2201      	movs	r2, #1
    2518:	701a      	strb	r2, [r3, #0]
		IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    251a:	2200      	movs	r2, #0
    251c:	2105      	movs	r1, #5
    251e:	2006      	movs	r0, #6
    2520:	f7ff fa9e 	bl	1a60 <z_arm_irq_priority_set>
		irq_enable(DT_IRQN(GPIOTE_NODE));
    2524:	2006      	movs	r0, #6
    2526:	f7ff fa7d 	bl	1a24 <arch_irq_enable>
    252a:	4b04      	ldr	r3, [pc, #16]	; (253c <gpio_nrfx_init+0x34>)
    252c:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    2530:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    2534:	e7ec      	b.n	2510 <gpio_nrfx_init+0x8>
    2536:	bf00      	nop
    2538:	2000094c 	.word	0x2000094c
    253c:	40006000 	.word	0x40006000

00002540 <gpiote_event_handler>:
{
    2540:	b570      	push	{r4, r5, r6, lr}
    2542:	b084      	sub	sp, #16
	uint32_t fired_triggers[GPIO_COUNT] = {0};
    2544:	2300      	movs	r3, #0
    2546:	9302      	str	r3, [sp, #8]
    2548:	9303      	str	r3, [sp, #12]
	uint32_t sense_levels[GPIO_COUNT] = {0};
    254a:	9300      	str	r3, [sp, #0]
    254c:	9301      	str	r3, [sp, #4]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    254e:	4b46      	ldr	r3, [pc, #280]	; (2668 <gpiote_event_handler+0x128>)
    2550:	681c      	ldr	r4, [r3, #0]
	if (port_event) {
    2552:	b90c      	cbnz	r4, 2558 <gpiote_event_handler+0x18>
{
    2554:	2100      	movs	r1, #0
    2556:	e011      	b.n	257c <gpiote_event_handler+0x3c>
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(0)),
    2558:	4d44      	ldr	r5, [pc, #272]	; (266c <gpiote_event_handler+0x12c>)
    255a:	4669      	mov	r1, sp
    255c:	4628      	mov	r0, r5
    255e:	f7ff fe5f 	bl	2220 <check_level_trigger_pins>
		fired_triggers[0] =
    2562:	9002      	str	r0, [sp, #8]
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(1)),
    2564:	a901      	add	r1, sp, #4
    2566:	f105 0018 	add.w	r0, r5, #24
    256a:	f7ff fe59 	bl	2220 <check_level_trigger_pins>
		fired_triggers[1] =
    256e:	9003      	str	r0, [sp, #12]
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2570:	4b3d      	ldr	r3, [pc, #244]	; (2668 <gpiote_event_handler+0x128>)
    2572:	2200      	movs	r2, #0
    2574:	601a      	str	r2, [r3, #0]
    2576:	681b      	ldr	r3, [r3, #0]
}
    2578:	e7ec      	b.n	2554 <gpiote_event_handler+0x14>
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    257a:	3101      	adds	r1, #1
    257c:	2907      	cmp	r1, #7
    257e:	d82d      	bhi.n	25dc <gpiote_event_handler+0x9c>
		nrf_gpiote_event_t evt =
    2580:	f101 0340 	add.w	r3, r1, #64	; 0x40
    2584:	009b      	lsls	r3, r3, #2
    2586:	b29a      	uxth	r2, r3
		if (nrf_gpiote_int_enable_check(NRF_GPIOTE, BIT(i)) &&
    2588:	2301      	movs	r3, #1
    258a:	408b      	lsls	r3, r1
    return p_reg->INTENSET & mask;
    258c:	4838      	ldr	r0, [pc, #224]	; (2670 <gpiote_event_handler+0x130>)
    258e:	f8d0 0304 	ldr.w	r0, [r0, #772]	; 0x304
    2592:	4203      	tst	r3, r0
    2594:	d0f1      	beq.n	257a <gpiote_event_handler+0x3a>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2596:	f102 4380 	add.w	r3, r2, #1073741824	; 0x40000000
    259a:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    259e:	681b      	ldr	r3, [r3, #0]
    25a0:	2b00      	cmp	r3, #0
    25a2:	d0ea      	beq.n	257a <gpiote_event_handler+0x3a>
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    25a4:	f501 73a2 	add.w	r3, r1, #324	; 0x144
    25a8:	4831      	ldr	r0, [pc, #196]	; (2670 <gpiote_event_handler+0x130>)
    25aa:	f850 0023 	ldr.w	r0, [r0, r3, lsl #2]
			fired_triggers[abs_pin / 32U] |= BIT(abs_pin % 32);
    25ae:	f3c0 3340 	ubfx	r3, r0, #13, #1
    25b2:	f3c0 2004 	ubfx	r0, r0, #8, #5
    25b6:	2501      	movs	r5, #1
    25b8:	fa05 f000 	lsl.w	r0, r5, r0
    25bc:	ad04      	add	r5, sp, #16
    25be:	eb05 0383 	add.w	r3, r5, r3, lsl #2
    25c2:	f853 5c08 	ldr.w	r5, [r3, #-8]
    25c6:	4305      	orrs	r5, r0
    25c8:	f843 5c08 	str.w	r5, [r3, #-8]
    return ((uint32_t)p_reg + event);
    25cc:	f102 4380 	add.w	r3, r2, #1073741824	; 0x40000000
    25d0:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    25d4:	2200      	movs	r2, #0
    25d6:	601a      	str	r2, [r3, #0]
    25d8:	681b      	ldr	r3, [r3, #0]
}
    25da:	e7ce      	b.n	257a <gpiote_event_handler+0x3a>
	if (fired_triggers[0]) {
    25dc:	9e02      	ldr	r6, [sp, #8]
    25de:	b92e      	cbnz	r6, 25ec <gpiote_event_handler+0xac>
	if (fired_triggers[1]) {
    25e0:	9e03      	ldr	r6, [sp, #12]
    25e2:	b9ee      	cbnz	r6, 2620 <gpiote_event_handler+0xe0>
	if (port_event) {
    25e4:	2c00      	cmp	r4, #0
    25e6:	d135      	bne.n	2654 <gpiote_event_handler+0x114>
}
    25e8:	b004      	add	sp, #16
    25ea:	bd70      	pop	{r4, r5, r6, pc}
	return list->head;
    25ec:	4b21      	ldr	r3, [pc, #132]	; (2674 <gpiote_event_handler+0x134>)
    25ee:	6859      	ldr	r1, [r3, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    25f0:	b119      	cbz	r1, 25fa <gpiote_event_handler+0xba>
    25f2:	460d      	mov	r5, r1
Z_GENLIST_PEEK_NEXT(slist, snode)
    25f4:	b149      	cbz	r1, 260a <gpiote_event_handler+0xca>
	return node->next;
    25f6:	680d      	ldr	r5, [r1, #0]
    25f8:	e007      	b.n	260a <gpiote_event_handler+0xca>
    25fa:	460d      	mov	r5, r1
    25fc:	e005      	b.n	260a <gpiote_event_handler+0xca>
    25fe:	b16d      	cbz	r5, 261c <gpiote_event_handler+0xdc>
    2600:	462b      	mov	r3, r5
Z_GENLIST_PEEK_NEXT(slist, snode)
    2602:	b105      	cbz	r5, 2606 <gpiote_event_handler+0xc6>
	return node->next;
    2604:	682b      	ldr	r3, [r5, #0]
    2606:	4629      	mov	r1, r5
    2608:	461d      	mov	r5, r3
    260a:	2900      	cmp	r1, #0
    260c:	d0e8      	beq.n	25e0 <gpiote_event_handler+0xa0>
		if (cb->pin_mask & pins) {
    260e:	688a      	ldr	r2, [r1, #8]
    2610:	4032      	ands	r2, r6
    2612:	d0f4      	beq.n	25fe <gpiote_event_handler+0xbe>
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    2614:	684b      	ldr	r3, [r1, #4]
    2616:	4815      	ldr	r0, [pc, #84]	; (266c <gpiote_event_handler+0x12c>)
    2618:	4798      	blx	r3
    261a:	e7f0      	b.n	25fe <gpiote_event_handler+0xbe>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    261c:	462b      	mov	r3, r5
    261e:	e7f2      	b.n	2606 <gpiote_event_handler+0xc6>
	return list->head;
    2620:	4b15      	ldr	r3, [pc, #84]	; (2678 <gpiote_event_handler+0x138>)
    2622:	6859      	ldr	r1, [r3, #4]
    2624:	b119      	cbz	r1, 262e <gpiote_event_handler+0xee>
    2626:	460d      	mov	r5, r1
Z_GENLIST_PEEK_NEXT(slist, snode)
    2628:	b149      	cbz	r1, 263e <gpiote_event_handler+0xfe>
	return node->next;
    262a:	680d      	ldr	r5, [r1, #0]
    262c:	e007      	b.n	263e <gpiote_event_handler+0xfe>
    262e:	460d      	mov	r5, r1
    2630:	e005      	b.n	263e <gpiote_event_handler+0xfe>
    2632:	b16d      	cbz	r5, 2650 <gpiote_event_handler+0x110>
    2634:	462b      	mov	r3, r5
Z_GENLIST_PEEK_NEXT(slist, snode)
    2636:	b105      	cbz	r5, 263a <gpiote_event_handler+0xfa>
	return node->next;
    2638:	682b      	ldr	r3, [r5, #0]
    263a:	4629      	mov	r1, r5
    263c:	461d      	mov	r5, r3
    263e:	2900      	cmp	r1, #0
    2640:	d0d0      	beq.n	25e4 <gpiote_event_handler+0xa4>
		if (cb->pin_mask & pins) {
    2642:	688a      	ldr	r2, [r1, #8]
    2644:	4032      	ands	r2, r6
    2646:	d0f4      	beq.n	2632 <gpiote_event_handler+0xf2>
			cb->handler(port, cb, cb->pin_mask & pins);
    2648:	684b      	ldr	r3, [r1, #4]
    264a:	480c      	ldr	r0, [pc, #48]	; (267c <gpiote_event_handler+0x13c>)
    264c:	4798      	blx	r3
    264e:	e7f0      	b.n	2632 <gpiote_event_handler+0xf2>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    2650:	462b      	mov	r3, r5
    2652:	e7f2      	b.n	263a <gpiote_event_handler+0xfa>
		cfg_level_pins(DEVICE_DT_GET(GPIO(0)));
    2654:	4c05      	ldr	r4, [pc, #20]	; (266c <gpiote_event_handler+0x12c>)
    2656:	4620      	mov	r0, r4
    2658:	f7ff fda8 	bl	21ac <cfg_level_pins>
		cfg_level_pins(DEVICE_DT_GET(GPIO(1)));
    265c:	f104 0018 	add.w	r0, r4, #24
    2660:	f7ff fda4 	bl	21ac <cfg_level_pins>
}
    2664:	e7c0      	b.n	25e8 <gpiote_event_handler+0xa8>
    2666:	bf00      	nop
    2668:	4000617c 	.word	0x4000617c
    266c:	0000588c 	.word	0x0000588c
    2670:	40006000 	.word	0x40006000
    2674:	20000358 	.word	0x20000358
    2678:	20000374 	.word	0x20000374
    267c:	000058a4 	.word	0x000058a4

00002680 <hfclk_on_callback>:
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)task);
}

NRF_STATIC_INLINE void nrf_temp_task_trigger(NRF_TEMP_Type * p_reg, nrf_temp_task_t task)
{
    *(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task) = 1;
    2680:	4b01      	ldr	r3, [pc, #4]	; (2688 <hfclk_on_callback+0x8>)
    2682:	2201      	movs	r2, #1
    2684:	601a      	str	r2, [r3, #0]
			      struct onoff_client *cli,
			      uint32_t state,
			      int res)
{
	nrf_temp_task_trigger(NRF_TEMP, NRF_TEMP_TASK_START);
}
    2686:	4770      	bx	lr
    2688:	4000c000 	.word	0x4000c000

0000268c <temp_nrf5_channel_get>:

static int temp_nrf5_channel_get(const struct device *dev,
				 enum sensor_channel chan,
				 struct sensor_value *val)
{
	struct temp_nrf5_data *data = dev->data;
    268c:	6903      	ldr	r3, [r0, #16]
	int32_t uval;


	if (chan != SENSOR_CHAN_DIE_TEMP) {
    268e:	290c      	cmp	r1, #12
    2690:	d110      	bne.n	26b4 <temp_nrf5_channel_get+0x28>
		return -ENOTSUP;
	}

	uval = data->sample * TEMP_NRF5_TEMP_SCALE;
    2692:	6a59      	ldr	r1, [r3, #36]	; 0x24
    2694:	4b09      	ldr	r3, [pc, #36]	; (26bc <temp_nrf5_channel_get+0x30>)
    2696:	fb03 f101 	mul.w	r1, r3, r1
	val->val1 = uval / 1000000;
    269a:	4809      	ldr	r0, [pc, #36]	; (26c0 <temp_nrf5_channel_get+0x34>)
    269c:	fb80 3001 	smull	r3, r0, r0, r1
    26a0:	17cb      	asrs	r3, r1, #31
    26a2:	ebc3 43a0 	rsb	r3, r3, r0, asr #18
    26a6:	6013      	str	r3, [r2, #0]
	val->val2 = uval % 1000000;
    26a8:	4806      	ldr	r0, [pc, #24]	; (26c4 <temp_nrf5_channel_get+0x38>)
    26aa:	fb00 1313 	mls	r3, r0, r3, r1
    26ae:	6053      	str	r3, [r2, #4]

	LOG_DBG("Temperature:%d,%d", val->val1, val->val2);

	return 0;
    26b0:	2000      	movs	r0, #0
    26b2:	4770      	bx	lr
		return -ENOTSUP;
    26b4:	f06f 0085 	mvn.w	r0, #133	; 0x85
}
    26b8:	4770      	bx	lr
    26ba:	bf00      	nop
    26bc:	0003d090 	.word	0x0003d090
    26c0:	431bde83 	.word	0x431bde83
    26c4:	000f4240 	.word	0x000f4240

000026c8 <temp_nrf5_sample_fetch>:
{
    26c8:	e92d 4370 	stmdb	sp!, {r4, r5, r6, r8, r9, lr}
    26cc:	b084      	sub	sp, #16
	struct temp_nrf5_data *data = dev->data;
    26ce:	6904      	ldr	r4, [r0, #16]
	if (data->clk_mgr == NULL) {
    26d0:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    26d2:	b373      	cbz	r3, 2732 <temp_nrf5_sample_fetch+0x6a>
	if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_DIE_TEMP) {
    26d4:	2938      	cmp	r1, #56	; 0x38
    26d6:	d001      	beq.n	26dc <temp_nrf5_sample_fetch+0x14>
    26d8:	290c      	cmp	r1, #12
    26da:	d12d      	bne.n	2738 <temp_nrf5_sample_fetch+0x70>
	k_mutex_lock(&data->mutex, K_FOREVER);
    26dc:	f104 0610 	add.w	r6, r4, #16
    26e0:	f04f 38ff 	mov.w	r8, #4294967295
    26e4:	f04f 39ff 	mov.w	r9, #4294967295
	return z_impl_k_mutex_lock(mutex, timeout);
    26e8:	4642      	mov	r2, r8
    26ea:	464b      	mov	r3, r9
    26ec:	4630      	mov	r0, r6
    26ee:	f000 fedb 	bl	34a8 <z_impl_k_mutex_lock>
					      sys_notify_generic_callback handler)
{
	__ASSERT_NO_MSG(notify != NULL);
	__ASSERT_NO_MSG(handler != NULL);

	*notify = (struct sys_notify){
    26f2:	2500      	movs	r5, #0
    26f4:	9503      	str	r5, [sp, #12]
    26f6:	4b12      	ldr	r3, [pc, #72]	; (2740 <temp_nrf5_sample_fetch+0x78>)
    26f8:	9301      	str	r3, [sp, #4]
    26fa:	2303      	movs	r3, #3
    26fc:	9302      	str	r3, [sp, #8]
	r = onoff_request(data->clk_mgr, &cli);
    26fe:	4669      	mov	r1, sp
    2700:	6aa0      	ldr	r0, [r4, #40]	; 0x28
    2702:	f002 f9e5 	bl	4ad0 <onoff_request>
	return z_impl_k_sem_take(sem, timeout);
    2706:	4642      	mov	r2, r8
    2708:	464b      	mov	r3, r9
    270a:	4620      	mov	r0, r4
    270c:	f000 ffba 	bl	3684 <z_impl_k_sem_take>
	r = onoff_release(data->clk_mgr);
    2710:	6aa0      	ldr	r0, [r4, #40]	; 0x28
    2712:	f002 fa39 	bl	4b88 <onoff_release>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
}

NRF_STATIC_INLINE int32_t nrf_temp_result_get(NRF_TEMP_Type const * p_reg)
{
    int32_t raw_measurement = p_reg->TEMP;
    2716:	4b0b      	ldr	r3, [pc, #44]	; (2744 <temp_nrf5_sample_fetch+0x7c>)
    2718:	f8d3 3508 	ldr.w	r3, [r3, #1288]	; 0x508
	data->sample = nrf_temp_result_get(NRF_TEMP);
    271c:	6263      	str	r3, [r4, #36]	; 0x24
    *(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task) = 1;
    271e:	4b0a      	ldr	r3, [pc, #40]	; (2748 <temp_nrf5_sample_fetch+0x80>)
    2720:	2201      	movs	r2, #1
    2722:	601a      	str	r2, [r3, #0]
	return z_impl_k_mutex_unlock(mutex);
    2724:	4630      	mov	r0, r6
    2726:	f000 ff49 	bl	35bc <z_impl_k_mutex_unlock>
	return 0;
    272a:	4628      	mov	r0, r5
}
    272c:	b004      	add	sp, #16
    272e:	e8bd 8370 	ldmia.w	sp!, {r4, r5, r6, r8, r9, pc}
		return -EAGAIN;
    2732:	f06f 000a 	mvn.w	r0, #10
    2736:	e7f9      	b.n	272c <temp_nrf5_sample_fetch+0x64>
		return -ENOTSUP;
    2738:	f06f 0085 	mvn.w	r0, #133	; 0x85
    273c:	e7f6      	b.n	272c <temp_nrf5_sample_fetch+0x64>
    273e:	bf00      	nop
    2740:	00002681 	.word	0x00002681
    2744:	4000c000 	.word	0x4000c000
    2748:	4000c004 	.word	0x4000c004

0000274c <temp_nrf5_init>:
	.sample_fetch = temp_nrf5_sample_fetch,
	.channel_get = temp_nrf5_channel_get,
};

static int temp_nrf5_init(const struct device *dev)
{
    274c:	b510      	push	{r4, lr}
	struct temp_nrf5_data *data = dev->data;
    274e:	6904      	ldr	r4, [r0, #16]

	LOG_DBG("");

	/* A null clk_mgr indicates sensor has not been initialized */
	data->clk_mgr =
		z_nrf_clock_control_get_onoff(CLOCK_CONTROL_NRF_SUBSYS_HF);
    2750:	2000      	movs	r0, #0
    2752:	f7fe ff05 	bl	1560 <z_nrf_clock_control_get_onoff>
	data->clk_mgr =
    2756:	62a0      	str	r0, [r4, #40]	; 0x28
	return z_impl_k_sem_init(sem, initial_count, limit);
    2758:	f04f 32ff 	mov.w	r2, #4294967295
    275c:	2100      	movs	r1, #0
    275e:	4620      	mov	r0, r4
    2760:	f002 fd8f 	bl	5282 <z_impl_k_sem_init>
	__ASSERT_NO_MSG(data->clk_mgr);

	k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
	k_mutex_init(&data->mutex);
    2764:	f104 0010 	add.w	r0, r4, #16
	return z_impl_k_mutex_init(mutex);
    2768:	f002 fd84 	bl	5274 <z_impl_k_mutex_init>

	IRQ_CONNECT(
    276c:	2200      	movs	r2, #0
    276e:	2101      	movs	r1, #1
    2770:	200c      	movs	r0, #12
    2772:	f7ff f975 	bl	1a60 <z_arm_irq_priority_set>
		DT_INST_IRQN(0),
		DT_INST_IRQ(0, priority),
		temp_nrf5_isr,
		DEVICE_DT_INST_GET(0),
		0);
	irq_enable(DT_INST_IRQN(0));
    2776:	200c      	movs	r0, #12
    2778:	f7ff f954 	bl	1a24 <arch_irq_enable>
    p_reg->INTENSET = mask;
    277c:	4b02      	ldr	r3, [pc, #8]	; (2788 <temp_nrf5_init+0x3c>)
    277e:	2201      	movs	r2, #1
    2780:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304

	nrf_temp_int_enable(NRF_TEMP, NRF_TEMP_INT_DATARDY_MASK);

	return 0;
}
    2784:	2000      	movs	r0, #0
    2786:	bd10      	pop	{r4, pc}
    2788:	4000c000 	.word	0x4000c000

0000278c <temp_nrf5_isr>:
{
    278c:	b508      	push	{r3, lr}
	struct temp_nrf5_data *data = dev->data;
    278e:	6900      	ldr	r0, [r0, #16]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2790:	4b03      	ldr	r3, [pc, #12]	; (27a0 <temp_nrf5_isr+0x14>)
    2792:	2200      	movs	r2, #0
    2794:	601a      	str	r2, [r3, #0]
    2796:	681b      	ldr	r3, [r3, #0]
		arch_syscall_invoke1(*(uintptr_t *)&sem, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    2798:	f000 ff52 	bl	3640 <z_impl_k_sem_give>
}
    279c:	bd08      	pop	{r3, pc}
    279e:	bf00      	nop
    27a0:	4000c100 	.word	0x4000c100

000027a4 <event_txdrdy_check>:
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type const * p_reg, nrf_uart_event_t event)
{
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    27a4:	4b02      	ldr	r3, [pc, #8]	; (27b0 <event_txdrdy_check+0xc>)
    27a6:	6818      	ldr	r0, [r3, #0]
	return (nrf_uart_event_check(uart0_addr, NRF_UART_EVENT_TXDRDY)
#ifdef CONFIG_UART_0_INTERRUPT_DRIVEN
		|| uart_sw_event_txdrdy
#endif
	       );
}
    27a8:	3800      	subs	r0, #0
    27aa:	bf18      	it	ne
    27ac:	2001      	movne	r0, #1
    27ae:	4770      	bx	lr
    27b0:	4000211c 	.word	0x4000211c

000027b4 <event_txdrdy_clear>:
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    27b4:	4b02      	ldr	r3, [pc, #8]	; (27c0 <event_txdrdy_clear+0xc>)
    27b6:	2200      	movs	r2, #0
    27b8:	601a      	str	r2, [r3, #0]
    27ba:	681b      	ldr	r3, [r3, #0]
{
	nrf_uart_event_clear(uart0_addr, NRF_UART_EVENT_TXDRDY);
#ifdef CONFIG_UART_0_INTERRUPT_DRIVEN
	uart_sw_event_txdrdy = 0U;
#endif
}
    27bc:	4770      	bx	lr
    27be:	bf00      	nop
    27c0:	4000211c 	.word	0x4000211c

000027c4 <baudrate_set>:

static int baudrate_set(const struct device *dev, uint32_t baudrate)
{
	nrf_uart_baudrate_t nrf_baudrate; /* calculated baudrate divisor */

	switch (baudrate) {
    27c4:	f5b1 4f16 	cmp.w	r1, #38400	; 0x9600
    27c8:	d06d      	beq.n	28a6 <baudrate_set+0xe2>
    27ca:	d83b      	bhi.n	2844 <baudrate_set+0x80>
    27cc:	f5b1 5f16 	cmp.w	r1, #9600	; 0x2580
    27d0:	d06b      	beq.n	28aa <baudrate_set+0xe6>
    27d2:	d90a      	bls.n	27ea <baudrate_set+0x26>
    27d4:	f5b1 4fe1 	cmp.w	r1, #28800	; 0x7080
    27d8:	d072      	beq.n	28c0 <baudrate_set+0xfc>
    27da:	d925      	bls.n	2828 <baudrate_set+0x64>
    27dc:	f647 2312 	movw	r3, #31250	; 0x7a12
    27e0:	4299      	cmp	r1, r3
    27e2:	d12c      	bne.n	283e <baudrate_set+0x7a>
		break;
	case 28800:
		nrf_baudrate = NRF_UART_BAUDRATE_28800;
		break;
	case 31250:
		nrf_baudrate = NRF_UART_BAUDRATE_31250;
    27e4:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    27e8:	e013      	b.n	2812 <baudrate_set+0x4e>
	switch (baudrate) {
    27ea:	f5b1 6f96 	cmp.w	r1, #1200	; 0x4b0
    27ee:	d05e      	beq.n	28ae <baudrate_set+0xea>
    27f0:	d907      	bls.n	2802 <baudrate_set+0x3e>
    27f2:	f5b1 6f16 	cmp.w	r1, #2400	; 0x960
    27f6:	d060      	beq.n	28ba <baudrate_set+0xf6>
    27f8:	f5b1 5f96 	cmp.w	r1, #4800	; 0x12c0
    27fc:	d111      	bne.n	2822 <baudrate_set+0x5e>
		nrf_baudrate = NRF_UART_BAUDRATE_4800;
    27fe:	4b3a      	ldr	r3, [pc, #232]	; (28e8 <baudrate_set+0x124>)
    2800:	e007      	b.n	2812 <baudrate_set+0x4e>
	switch (baudrate) {
    2802:	f5b1 7f96 	cmp.w	r1, #300	; 0x12c
    2806:	d055      	beq.n	28b4 <baudrate_set+0xf0>
    2808:	f5b1 7f16 	cmp.w	r1, #600	; 0x258
    280c:	d106      	bne.n	281c <baudrate_set+0x58>
		nrf_baudrate = 0x00027000;
    280e:	f44f 331c 	mov.w	r3, #159744	; 0x27000
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    2812:	4a36      	ldr	r2, [pc, #216]	; (28ec <baudrate_set+0x128>)
    2814:	f8c2 3524 	str.w	r3, [r2, #1316]	; 0x524
		return -EINVAL;
	}

	nrf_uart_baudrate_set(uart0_addr, nrf_baudrate);

	return 0;
    2818:	2000      	movs	r0, #0
    281a:	4770      	bx	lr
	switch (baudrate) {
    281c:	f06f 0015 	mvn.w	r0, #21
    2820:	4770      	bx	lr
    2822:	f06f 0015 	mvn.w	r0, #21
    2826:	4770      	bx	lr
    2828:	f5b1 5f61 	cmp.w	r1, #14400	; 0x3840
    282c:	d04a      	beq.n	28c4 <baudrate_set+0x100>
    282e:	f5b1 4f96 	cmp.w	r1, #19200	; 0x4b00
    2832:	d101      	bne.n	2838 <baudrate_set+0x74>
		nrf_baudrate = NRF_UART_BAUDRATE_19200;
    2834:	4b2e      	ldr	r3, [pc, #184]	; (28f0 <baudrate_set+0x12c>)
    2836:	e7ec      	b.n	2812 <baudrate_set+0x4e>
	switch (baudrate) {
    2838:	f06f 0015 	mvn.w	r0, #21
    283c:	4770      	bx	lr
    283e:	f06f 0015 	mvn.w	r0, #21
    2842:	4770      	bx	lr
    2844:	f5b1 3f61 	cmp.w	r1, #230400	; 0x38400
    2848:	d03f      	beq.n	28ca <baudrate_set+0x106>
    284a:	d909      	bls.n	2860 <baudrate_set+0x9c>
    284c:	f5b1 2f61 	cmp.w	r1, #921600	; 0xe1000
    2850:	d042      	beq.n	28d8 <baudrate_set+0x114>
    2852:	d91d      	bls.n	2890 <baudrate_set+0xcc>
    2854:	4b27      	ldr	r3, [pc, #156]	; (28f4 <baudrate_set+0x130>)
    2856:	4299      	cmp	r1, r3
    2858:	d143      	bne.n	28e2 <baudrate_set+0x11e>
		nrf_baudrate = NRF_UART_BAUDRATE_1000000;
    285a:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    285e:	e7d8      	b.n	2812 <baudrate_set+0x4e>
	switch (baudrate) {
    2860:	f5b1 3f96 	cmp.w	r1, #76800	; 0x12c00
    2864:	d033      	beq.n	28ce <baudrate_set+0x10a>
    2866:	d904      	bls.n	2872 <baudrate_set+0xae>
    2868:	f5b1 3fe1 	cmp.w	r1, #115200	; 0x1c200
    286c:	d10d      	bne.n	288a <baudrate_set+0xc6>
		nrf_baudrate = NRF_UART_BAUDRATE_115200;
    286e:	4b22      	ldr	r3, [pc, #136]	; (28f8 <baudrate_set+0x134>)
    2870:	e7cf      	b.n	2812 <baudrate_set+0x4e>
	switch (baudrate) {
    2872:	f64d 23c0 	movw	r3, #56000	; 0xdac0
    2876:	4299      	cmp	r1, r3
    2878:	d02b      	beq.n	28d2 <baudrate_set+0x10e>
    287a:	f5b1 4f61 	cmp.w	r1, #57600	; 0xe100
    287e:	d101      	bne.n	2884 <baudrate_set+0xc0>
		nrf_baudrate = NRF_UART_BAUDRATE_57600;
    2880:	4b1e      	ldr	r3, [pc, #120]	; (28fc <baudrate_set+0x138>)
    2882:	e7c6      	b.n	2812 <baudrate_set+0x4e>
	switch (baudrate) {
    2884:	f06f 0015 	mvn.w	r0, #21
    2888:	4770      	bx	lr
    288a:	f06f 0015 	mvn.w	r0, #21
    288e:	4770      	bx	lr
    2890:	4b1b      	ldr	r3, [pc, #108]	; (2900 <baudrate_set+0x13c>)
    2892:	4299      	cmp	r1, r3
    2894:	d022      	beq.n	28dc <baudrate_set+0x118>
    2896:	f5b1 2fe1 	cmp.w	r1, #460800	; 0x70800
    289a:	d101      	bne.n	28a0 <baudrate_set+0xdc>
		nrf_baudrate = NRF_UART_BAUDRATE_460800;
    289c:	4b19      	ldr	r3, [pc, #100]	; (2904 <baudrate_set+0x140>)
    289e:	e7b8      	b.n	2812 <baudrate_set+0x4e>
	switch (baudrate) {
    28a0:	f06f 0015 	mvn.w	r0, #21
    28a4:	4770      	bx	lr
		nrf_baudrate = NRF_UART_BAUDRATE_38400;
    28a6:	4b18      	ldr	r3, [pc, #96]	; (2908 <baudrate_set+0x144>)
    28a8:	e7b3      	b.n	2812 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_9600;
    28aa:	4b18      	ldr	r3, [pc, #96]	; (290c <baudrate_set+0x148>)
    28ac:	e7b1      	b.n	2812 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_1200;
    28ae:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    28b2:	e7ae      	b.n	2812 <baudrate_set+0x4e>
	switch (baudrate) {
    28b4:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    28b8:	e7ab      	b.n	2812 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_2400;
    28ba:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    28be:	e7a8      	b.n	2812 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_28800;
    28c0:	4b13      	ldr	r3, [pc, #76]	; (2910 <baudrate_set+0x14c>)
    28c2:	e7a6      	b.n	2812 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_14400;
    28c4:	f44f 136c 	mov.w	r3, #3866624	; 0x3b0000
    28c8:	e7a3      	b.n	2812 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_230400;
    28ca:	4b12      	ldr	r3, [pc, #72]	; (2914 <baudrate_set+0x150>)
    28cc:	e7a1      	b.n	2812 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_76800;
    28ce:	4b12      	ldr	r3, [pc, #72]	; (2918 <baudrate_set+0x154>)
    28d0:	e79f      	b.n	2812 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_56000;
    28d2:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    28d6:	e79c      	b.n	2812 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_921600;
    28d8:	4b10      	ldr	r3, [pc, #64]	; (291c <baudrate_set+0x158>)
    28da:	e79a      	b.n	2812 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_250000;
    28dc:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    28e0:	e797      	b.n	2812 <baudrate_set+0x4e>
	switch (baudrate) {
    28e2:	f06f 0015 	mvn.w	r0, #21
}
    28e6:	4770      	bx	lr
    28e8:	0013b000 	.word	0x0013b000
    28ec:	40002000 	.word	0x40002000
    28f0:	004ea000 	.word	0x004ea000
    28f4:	000f4240 	.word	0x000f4240
    28f8:	01d7e000 	.word	0x01d7e000
    28fc:	00ebf000 	.word	0x00ebf000
    2900:	0003d090 	.word	0x0003d090
    2904:	075f7000 	.word	0x075f7000
    2908:	009d5000 	.word	0x009d5000
    290c:	00275000 	.word	0x00275000
    2910:	0075f000 	.word	0x0075f000
    2914:	03afb000 	.word	0x03afb000
    2918:	013a9000 	.word	0x013a9000
    291c:	0ebed000 	.word	0x0ebed000

00002920 <uart_nrfx_poll_in>:
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2920:	4b07      	ldr	r3, [pc, #28]	; (2940 <uart_nrfx_poll_in+0x20>)
    2922:	681b      	ldr	r3, [r3, #0]
 * @return 0 if a character arrived, -1 if the input buffer if empty.
 */

static int uart_nrfx_poll_in(const struct device *dev, unsigned char *c)
{
	if (!nrf_uart_event_check(uart0_addr, NRF_UART_EVENT_RXDRDY)) {
    2924:	b143      	cbz	r3, 2938 <uart_nrfx_poll_in+0x18>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2926:	4b06      	ldr	r3, [pc, #24]	; (2940 <uart_nrfx_poll_in+0x20>)
    2928:	2000      	movs	r0, #0
    292a:	6018      	str	r0, [r3, #0]
    292c:	681b      	ldr	r3, [r3, #0]
    return p_reg->RXD;
    292e:	4b05      	ldr	r3, [pc, #20]	; (2944 <uart_nrfx_poll_in+0x24>)
    2930:	f8d3 3518 	ldr.w	r3, [r3, #1304]	; 0x518

	/* Clear the interrupt */
	nrf_uart_event_clear(uart0_addr, NRF_UART_EVENT_RXDRDY);

	/* got a character */
	*c = nrf_uart_rxd_get(uart0_addr);
    2934:	700b      	strb	r3, [r1, #0]

	return 0;
    2936:	4770      	bx	lr
		return -1;
    2938:	f04f 30ff 	mov.w	r0, #4294967295
}
    293c:	4770      	bx	lr
    293e:	bf00      	nop
    2940:	40002108 	.word	0x40002108
    2944:	40002000 	.word	0x40002000

00002948 <uart_nrfx_err_check>:
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    2948:	4b02      	ldr	r3, [pc, #8]	; (2954 <uart_nrfx_err_check+0xc>)
    294a:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    294e:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
/** Console I/O function */
static int uart_nrfx_err_check(const struct device *dev)
{
	/* register bitfields maps to the defines in uart.h */
	return nrf_uart_errorsrc_get_and_clear(uart0_addr);
}
    2952:	4770      	bx	lr
    2954:	40002000 	.word	0x40002000

00002958 <uart_nrfx_configure>:

static int uart_nrfx_configure(const struct device *dev,
			       const struct uart_config *cfg)
{
    2958:	b530      	push	{r4, r5, lr}
    295a:	b083      	sub	sp, #12
    295c:	4605      	mov	r5, r0
    295e:	460c      	mov	r4, r1
	nrf_uart_config_t uart_cfg;

#if defined(UART_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
    2960:	794b      	ldrb	r3, [r1, #5]
    2962:	2b01      	cmp	r3, #1
    2964:	d006      	beq.n	2974 <uart_nrfx_configure+0x1c>
    2966:	2b03      	cmp	r3, #3
    2968:	d011      	beq.n	298e <uart_nrfx_configure+0x36>
    296a:	f06f 0285 	mvn.w	r2, #133	; 0x85
	nrf_uart_configure(uart0_addr, &uart_cfg);

	get_dev_data(dev)->uart_config = *cfg;

	return 0;
}
    296e:	4610      	mov	r0, r2
    2970:	b003      	add	sp, #12
    2972:	bd30      	pop	{r4, r5, pc}
		uart_cfg.stop = NRF_UART_STOP_ONE;
    2974:	2300      	movs	r3, #0
    2976:	f88d 3002 	strb.w	r3, [sp, #2]
	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    297a:	79a3      	ldrb	r3, [r4, #6]
    297c:	2b03      	cmp	r3, #3
    297e:	d145      	bne.n	2a0c <uart_nrfx_configure+0xb4>
	switch (cfg->flow_ctrl) {
    2980:	79e3      	ldrb	r3, [r4, #7]
    2982:	b143      	cbz	r3, 2996 <uart_nrfx_configure+0x3e>
    2984:	2b01      	cmp	r3, #1
    2986:	d015      	beq.n	29b4 <uart_nrfx_configure+0x5c>
    2988:	f06f 0285 	mvn.w	r2, #133	; 0x85
    298c:	e7ef      	b.n	296e <uart_nrfx_configure+0x16>
		uart_cfg.stop = NRF_UART_STOP_TWO;
    298e:	2310      	movs	r3, #16
    2990:	f88d 3002 	strb.w	r3, [sp, #2]
		break;
    2994:	e7f1      	b.n	297a <uart_nrfx_configure+0x22>
		uart_cfg.hwfc = NRF_UART_HWFC_DISABLED;
    2996:	2300      	movs	r3, #0
    2998:	f88d 3000 	strb.w	r3, [sp]
	uart_cfg.paritytype = NRF_UART_PARITYTYPE_EVEN;
    299c:	2300      	movs	r3, #0
    299e:	f8ad 3004 	strh.w	r3, [sp, #4]
	switch (cfg->parity) {
    29a2:	7923      	ldrb	r3, [r4, #4]
    29a4:	2b01      	cmp	r3, #1
    29a6:	d029      	beq.n	29fc <uart_nrfx_configure+0xa4>
    29a8:	2b02      	cmp	r3, #2
    29aa:	d023      	beq.n	29f4 <uart_nrfx_configure+0x9c>
    29ac:	b133      	cbz	r3, 29bc <uart_nrfx_configure+0x64>
    29ae:	f06f 0285 	mvn.w	r2, #133	; 0x85
    29b2:	e7dc      	b.n	296e <uart_nrfx_configure+0x16>
			uart_cfg.hwfc = NRF_UART_HWFC_ENABLED;
    29b4:	2301      	movs	r3, #1
    29b6:	f88d 3000 	strb.w	r3, [sp]
		break;
    29ba:	e7ef      	b.n	299c <uart_nrfx_configure+0x44>
		uart_cfg.parity = NRF_UART_PARITY_EXCLUDED;
    29bc:	f88d 3001 	strb.w	r3, [sp, #1]
	if (baudrate_set(dev, cfg->baudrate) != 0) {
    29c0:	6821      	ldr	r1, [r4, #0]
    29c2:	4628      	mov	r0, r5
    29c4:	f7ff fefe 	bl	27c4 <baudrate_set>
    29c8:	4602      	mov	r2, r0
    29ca:	bb10      	cbnz	r0, 2a12 <uart_nrfx_configure+0xba>
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    29cc:	f89d 3001 	ldrb.w	r3, [sp, #1]
                    | (uint32_t)p_cfg->stop
    29d0:	f89d 1002 	ldrb.w	r1, [sp, #2]
    29d4:	430b      	orrs	r3, r1
                    | (uint32_t)p_cfg->paritytype
    29d6:	f8bd 1004 	ldrh.w	r1, [sp, #4]
    29da:	430b      	orrs	r3, r1
                    | (uint32_t)p_cfg->hwfc;
    29dc:	f89d 1000 	ldrb.w	r1, [sp]
    29e0:	430b      	orrs	r3, r1
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    29e2:	490d      	ldr	r1, [pc, #52]	; (2a18 <uart_nrfx_configure+0xc0>)
    29e4:	f8c1 356c 	str.w	r3, [r1, #1388]	; 0x56c
	return dev->data;
    29e8:	692b      	ldr	r3, [r5, #16]
	get_dev_data(dev)->uart_config = *cfg;
    29ea:	e894 0003 	ldmia.w	r4, {r0, r1}
    29ee:	e883 0003 	stmia.w	r3, {r0, r1}
	return 0;
    29f2:	e7bc      	b.n	296e <uart_nrfx_configure+0x16>
		uart_cfg.parity = NRF_UART_PARITY_INCLUDED;
    29f4:	230e      	movs	r3, #14
    29f6:	f88d 3001 	strb.w	r3, [sp, #1]
		break;
    29fa:	e7e1      	b.n	29c0 <uart_nrfx_configure+0x68>
		uart_cfg.parity = NRF_UART_PARITY_INCLUDED;
    29fc:	230e      	movs	r3, #14
    29fe:	f88d 3001 	strb.w	r3, [sp, #1]
		uart_cfg.paritytype = NRF_UART_PARITYTYPE_ODD;
    2a02:	f44f 7380 	mov.w	r3, #256	; 0x100
    2a06:	f8ad 3004 	strh.w	r3, [sp, #4]
		break;
    2a0a:	e7d9      	b.n	29c0 <uart_nrfx_configure+0x68>
		return -ENOTSUP;
    2a0c:	f06f 0285 	mvn.w	r2, #133	; 0x85
    2a10:	e7ad      	b.n	296e <uart_nrfx_configure+0x16>
		return -ENOTSUP;
    2a12:	f06f 0285 	mvn.w	r2, #133	; 0x85
    2a16:	e7aa      	b.n	296e <uart_nrfx_configure+0x16>
    2a18:	40002000 	.word	0x40002000

00002a1c <uart_nrfx_init>:
 * @param dev UART device struct
 *
 * @return 0 on success
 */
static int uart_nrfx_init(const struct device *dev)
{
    2a1c:	b538      	push	{r3, r4, r5, lr}
    p_reg->ENABLE = UART_ENABLE_ENABLE_Disabled;
    2a1e:	4a18      	ldr	r2, [pc, #96]	; (2a80 <uart_nrfx_init+0x64>)
    2a20:	2300      	movs	r3, #0
    2a22:	f8c2 3500 	str.w	r3, [r2, #1280]	; 0x500
    p_reg->OUTSET = set_mask;
    2a26:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    2a2a:	2140      	movs	r1, #64	; 0x40
    2a2c:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
    reg->PIN_CNF[pin_number] = cnf;
    2a30:	2403      	movs	r4, #3
    2a32:	f8c3 4718 	str.w	r4, [r3, #1816]	; 0x718
    2a36:	210c      	movs	r1, #12
    2a38:	f8c3 1720 	str.w	r1, [r3, #1824]	; 0x720
    p_reg->PSEL.RXD = pselrxd;
    2a3c:	2508      	movs	r5, #8
    2a3e:	f8c2 5514 	str.w	r5, [r2, #1300]	; 0x514
    p_reg->PSEL.TXD = pseltxd;
    2a42:	2506      	movs	r5, #6
    2a44:	f8c2 550c 	str.w	r5, [r2, #1292]	; 0x50c
    p_reg->OUTSET = set_mask;
    2a48:	2520      	movs	r5, #32
    2a4a:	f8c3 5508 	str.w	r5, [r3, #1288]	; 0x508
    reg->PIN_CNF[pin_number] = cnf;
    2a4e:	f8c3 4714 	str.w	r4, [r3, #1812]	; 0x714
    2a52:	f8c3 171c 	str.w	r1, [r3, #1820]	; 0x71c
    p_reg->PSEL.RTS = pselrts;
    2a56:	2305      	movs	r3, #5
    2a58:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
    p_reg->PSEL.CTS = pselcts;
    2a5c:	2307      	movs	r3, #7
    2a5e:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
	}

	nrf_uart_hwfc_pins_set(uart0_addr, RTS_PIN, CTS_PIN);

	/* Set initial configuration */
	err = uart_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
    2a62:	6901      	ldr	r1, [r0, #16]
    2a64:	f7ff ff78 	bl	2958 <uart_nrfx_configure>
	if (err) {
    2a68:	b948      	cbnz	r0, 2a7e <uart_nrfx_init+0x62>
    p_reg->ENABLE = UART_ENABLE_ENABLE_Enabled;
    2a6a:	4b05      	ldr	r3, [pc, #20]	; (2a80 <uart_nrfx_init+0x64>)
    2a6c:	2204      	movs	r2, #4
    2a6e:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a72:	4a04      	ldr	r2, [pc, #16]	; (2a84 <uart_nrfx_init+0x68>)
    2a74:	2100      	movs	r1, #0
    2a76:	6011      	str	r1, [r2, #0]
    2a78:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2a7a:	2201      	movs	r2, #1
    2a7c:	601a      	str	r2, [r3, #0]
#if HW_FLOW_CONTROL_AVAILABLE
	k_timer_init(&uart0_cb.tx_timeout_timer, tx_timeout, NULL);
#endif
#endif
	return 0;
}
    2a7e:	bd38      	pop	{r3, r4, r5, pc}
    2a80:	40002000 	.word	0x40002000
    2a84:	40002108 	.word	0x40002108

00002a88 <uart_nrfx_poll_out>:
{
    2a88:	b538      	push	{r3, r4, r5, lr}
    2a8a:	460c      	mov	r4, r1
	if (!k_is_in_isr()) {
    2a8c:	f002 fb90 	bl	51b0 <k_is_in_isr>
    2a90:	b9c0      	cbnz	r0, 2ac4 <uart_nrfx_poll_out+0x3c>
		uint8_t safety_cnt = 100;
    2a92:	2564      	movs	r5, #100	; 0x64
    2a94:	4b19      	ldr	r3, [pc, #100]	; (2afc <uart_nrfx_poll_out+0x74>)
    2a96:	2201      	movs	r2, #1
    2a98:	f3bf 8f5b 	dmb	ish
    2a9c:	e853 1f00 	ldrex	r1, [r3]
    2aa0:	2900      	cmp	r1, #0
    2aa2:	d103      	bne.n	2aac <uart_nrfx_poll_out+0x24>
    2aa4:	e843 2000 	strex	r0, r2, [r3]
    2aa8:	2800      	cmp	r0, #0
    2aaa:	d1f7      	bne.n	2a9c <uart_nrfx_poll_out+0x14>
    2aac:	f3bf 8f5b 	dmb	ish
		while (atomic_cas((atomic_t *) lock,
    2ab0:	d00b      	beq.n	2aca <uart_nrfx_poll_out+0x42>
	return z_impl_k_sleep(timeout);
    2ab2:	2021      	movs	r0, #33	; 0x21
    2ab4:	2100      	movs	r1, #0
    2ab6:	f001 fb03 	bl	40c0 <z_impl_k_sleep>
			if (--safety_cnt == 0) {
    2aba:	3d01      	subs	r5, #1
    2abc:	f015 05ff 	ands.w	r5, r5, #255	; 0xff
    2ac0:	d1e8      	bne.n	2a94 <uart_nrfx_poll_out+0xc>
    2ac2:	e002      	b.n	2aca <uart_nrfx_poll_out+0x42>
		*lock = 1;
    2ac4:	4b0d      	ldr	r3, [pc, #52]	; (2afc <uart_nrfx_poll_out+0x74>)
    2ac6:	2201      	movs	r2, #1
    2ac8:	601a      	str	r2, [r3, #0]
	event_txdrdy_clear();
    2aca:	f7ff fe73 	bl	27b4 <event_txdrdy_clear>
    2ace:	4b0c      	ldr	r3, [pc, #48]	; (2b00 <uart_nrfx_poll_out+0x78>)
    2ad0:	2201      	movs	r2, #1
    2ad2:	601a      	str	r2, [r3, #0]
    p_reg->TXD = txd;
    2ad4:	3b08      	subs	r3, #8
    2ad6:	f8c3 451c 	str.w	r4, [r3, #1308]	; 0x51c
	NRFX_WAIT_FOR(event_txdrdy_check(), 1000, 1, res);
    2ada:	f44f 747a 	mov.w	r4, #1000	; 0x3e8
    2ade:	f7ff fe61 	bl	27a4 <event_txdrdy_check>
    2ae2:	b920      	cbnz	r0, 2aee <uart_nrfx_poll_out+0x66>
    2ae4:	2001      	movs	r0, #1
    2ae6:	f002 fb10 	bl	510a <nrfx_busy_wait>
    2aea:	3c01      	subs	r4, #1
    2aec:	d1f7      	bne.n	2ade <uart_nrfx_poll_out+0x56>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2aee:	4b05      	ldr	r3, [pc, #20]	; (2b04 <uart_nrfx_poll_out+0x7c>)
    2af0:	2201      	movs	r2, #1
    2af2:	601a      	str	r2, [r3, #0]
	*lock = 0;
    2af4:	4b01      	ldr	r3, [pc, #4]	; (2afc <uart_nrfx_poll_out+0x74>)
    2af6:	2200      	movs	r2, #0
    2af8:	601a      	str	r2, [r3, #0]
}
    2afa:	bd38      	pop	{r3, r4, r5, pc}
    2afc:	200003c4 	.word	0x200003c4
    2b00:	40002008 	.word	0x40002008
    2b04:	4000200c 	.word	0x4000200c

00002b08 <nrf52_errata_36>:
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2b08:	4b03      	ldr	r3, [pc, #12]	; (2b18 <nrf52_errata_36+0x10>)
    2b0a:	681b      	ldr	r3, [r3, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    2b0c:	2b0d      	cmp	r3, #13
    2b0e:	d001      	beq.n	2b14 <nrf52_errata_36+0xc>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    2b10:	2000      	movs	r0, #0
    2b12:	4770      	bx	lr
                        return true;
    2b14:	2001      	movs	r0, #1
    #endif
}
    2b16:	4770      	bx	lr
    2b18:	10000130 	.word	0x10000130

00002b1c <nrf52_errata_66>:
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2b1c:	4b03      	ldr	r3, [pc, #12]	; (2b2c <nrf52_errata_66+0x10>)
    2b1e:	681b      	ldr	r3, [r3, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    2b20:	2b0d      	cmp	r3, #13
    2b22:	d001      	beq.n	2b28 <nrf52_errata_66+0xc>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    2b24:	2000      	movs	r0, #0
    2b26:	4770      	bx	lr
                        return true;
    2b28:	2001      	movs	r0, #1
    #endif
}
    2b2a:	4770      	bx	lr
    2b2c:	10000130 	.word	0x10000130

00002b30 <nrf52_errata_136>:
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2b30:	4b03      	ldr	r3, [pc, #12]	; (2b40 <nrf52_errata_136+0x10>)
    2b32:	681b      	ldr	r3, [r3, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    2b34:	2b0d      	cmp	r3, #13
    2b36:	d001      	beq.n	2b3c <nrf52_errata_136+0xc>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    2b38:	2000      	movs	r0, #0
    2b3a:	4770      	bx	lr
                        return true;
    2b3c:	2001      	movs	r0, #1
    #endif
}
    2b3e:	4770      	bx	lr
    2b40:	10000130 	.word	0x10000130

00002b44 <nrf52_errata_249>:
        #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2b44:	4b06      	ldr	r3, [pc, #24]	; (2b60 <nrf52_errata_249+0x1c>)
    2b46:	681b      	ldr	r3, [r3, #0]
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    2b48:	4a06      	ldr	r2, [pc, #24]	; (2b64 <nrf52_errata_249+0x20>)
    2b4a:	6812      	ldr	r2, [r2, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    2b4c:	2b0d      	cmp	r3, #13
    2b4e:	d001      	beq.n	2b54 <nrf52_errata_249+0x10>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    2b50:	2000      	movs	r0, #0
    2b52:	4770      	bx	lr
                switch(var2)
    2b54:	2a01      	cmp	r2, #1
    2b56:	d801      	bhi.n	2b5c <nrf52_errata_249+0x18>
    2b58:	2000      	movs	r0, #0
    2b5a:	4770      	bx	lr
                        return true;
    2b5c:	2001      	movs	r0, #1
    #endif
}
    2b5e:	4770      	bx	lr
    2b60:	10000130 	.word	0x10000130
    2b64:	10000134 	.word	0x10000134

00002b68 <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    2b68:	4b02      	ldr	r3, [pc, #8]	; (2b74 <nvmc_wait+0xc>)
    2b6a:	f8d3 3400 	ldr.w	r3, [r3, #1024]	; 0x400
    2b6e:	2b00      	cmp	r3, #0
    2b70:	d0fa      	beq.n	2b68 <nvmc_wait>
}
    2b72:	4770      	bx	lr
    2b74:	4001e000 	.word	0x4001e000

00002b78 <nvmc_config>:

/*  Configure the NVMC to "mode".
    Mode must be an enumerator of field NVMC_CONFIG_WEN */
void nvmc_config(uint32_t mode)
{
    2b78:	b508      	push	{r3, lr}
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    2b7a:	4b03      	ldr	r3, [pc, #12]	; (2b88 <nvmc_config+0x10>)
    2b7c:	f8c3 0504 	str.w	r0, [r3, #1284]	; 0x504
    nvmc_wait();
    2b80:	f7ff fff2 	bl	2b68 <nvmc_wait>
}
    2b84:	bd08      	pop	{r3, pc}
    2b86:	bf00      	nop
    2b88:	4001e000 	.word	0x4001e000

00002b8c <SystemCoreClockUpdate>:

void SystemCoreClockUpdate(void)
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    2b8c:	4b01      	ldr	r3, [pc, #4]	; (2b94 <SystemCoreClockUpdate+0x8>)
    2b8e:	4a02      	ldr	r2, [pc, #8]	; (2b98 <SystemCoreClockUpdate+0xc>)
    2b90:	601a      	str	r2, [r3, #0]
}
    2b92:	4770      	bx	lr
    2b94:	20000038 	.word	0x20000038
    2b98:	03d09000 	.word	0x03d09000

00002b9c <SystemInit>:

void SystemInit(void)
{
    2b9c:	b538      	push	{r3, r4, r5, lr}
    #endif

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
    2b9e:	f7ff ffb3 	bl	2b08 <nrf52_errata_36>
    2ba2:	b140      	cbz	r0, 2bb6 <SystemInit+0x1a>
            NRF_CLOCK->EVENTS_DONE = 0;
    2ba4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2ba8:	2200      	movs	r2, #0
    2baa:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    2bae:	f8c3 2110 	str.w	r2, [r3, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    2bb2:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    #endif

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
    2bb6:	f7ff ffb1 	bl	2b1c <nrf52_errata_66>
    2bba:	2800      	cmp	r0, #0
    2bbc:	d046      	beq.n	2c4c <SystemInit+0xb0>
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    2bbe:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
    2bc2:	f8d2 1404 	ldr.w	r1, [r2, #1028]	; 0x404
    2bc6:	4b45      	ldr	r3, [pc, #276]	; (2cdc <SystemInit+0x140>)
    2bc8:	f8c3 1520 	str.w	r1, [r3, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    2bcc:	f8d2 1408 	ldr.w	r1, [r2, #1032]	; 0x408
    2bd0:	f8c3 1524 	str.w	r1, [r3, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    2bd4:	f8d2 140c 	ldr.w	r1, [r2, #1036]	; 0x40c
    2bd8:	f8c3 1528 	str.w	r1, [r3, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    2bdc:	f8d2 1410 	ldr.w	r1, [r2, #1040]	; 0x410
    2be0:	f8c3 152c 	str.w	r1, [r3, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    2be4:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
    2be8:	f8c3 1530 	str.w	r1, [r3, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    2bec:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    2bf0:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    2bf4:	f8d2 141c 	ldr.w	r1, [r2, #1052]	; 0x41c
    2bf8:	f8c3 1540 	str.w	r1, [r3, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    2bfc:	f8d2 1420 	ldr.w	r1, [r2, #1056]	; 0x420
    2c00:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    2c04:	f8d2 1424 	ldr.w	r1, [r2, #1060]	; 0x424
    2c08:	f8c3 1548 	str.w	r1, [r3, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    2c0c:	f8d2 1428 	ldr.w	r1, [r2, #1064]	; 0x428
    2c10:	f8c3 154c 	str.w	r1, [r3, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    2c14:	f8d2 142c 	ldr.w	r1, [r2, #1068]	; 0x42c
    2c18:	f8c3 1550 	str.w	r1, [r3, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    2c1c:	f8d2 1430 	ldr.w	r1, [r2, #1072]	; 0x430
    2c20:	f8c3 1554 	str.w	r1, [r3, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    2c24:	f8d2 1434 	ldr.w	r1, [r2, #1076]	; 0x434
    2c28:	f8c3 1560 	str.w	r1, [r3, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    2c2c:	f8d2 1438 	ldr.w	r1, [r2, #1080]	; 0x438
    2c30:	f8c3 1564 	str.w	r1, [r3, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    2c34:	f8d2 143c 	ldr.w	r1, [r2, #1084]	; 0x43c
    2c38:	f8c3 1568 	str.w	r1, [r3, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    2c3c:	f8d2 1440 	ldr.w	r1, [r2, #1088]	; 0x440
    2c40:	f8c3 156c 	str.w	r1, [r3, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    2c44:	f8d2 2444 	ldr.w	r2, [r2, #1092]	; 0x444
    2c48:	f8c3 2570 	str.w	r2, [r3, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
    2c4c:	f7ff ff70 	bl	2b30 <nrf52_errata_136>
    2c50:	b160      	cbz	r0, 2c6c <SystemInit+0xd0>
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    2c52:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2c56:	f8d3 3400 	ldr.w	r3, [r3, #1024]	; 0x400
    2c5a:	f013 0f01 	tst.w	r3, #1
    2c5e:	d005      	beq.n	2c6c <SystemInit+0xd0>
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    2c60:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2c64:	f06f 0201 	mvn.w	r2, #1
    2c68:	f8c3 2400 	str.w	r2, [r3, #1024]	; 0x400
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_errata_249())
    2c6c:	f7ff ff6a 	bl	2b44 <nrf52_errata_249>
    2c70:	b138      	cbz	r0, 2c82 <SystemInit+0xe6>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    2c72:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    2c76:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    2c7a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2c7e:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    2c82:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    2c86:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
    2c8a:	2b00      	cmp	r3, #0
    2c8c:	db08      	blt.n	2ca0 <SystemInit+0x104>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    2c8e:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    2c92:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    2c96:	2b00      	cmp	r3, #0
    2c98:	db02      	blt.n	2ca0 <SystemInit+0x104>
            nvmc_config(NVMC_CONFIG_WEN_Ren);
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
    2c9a:	f7ff ff77 	bl	2b8c <SystemCoreClockUpdate>
}
    2c9e:	bd38      	pop	{r3, r4, r5, pc}
            nvmc_config(NVMC_CONFIG_WEN_Wen);
    2ca0:	2001      	movs	r0, #1
    2ca2:	f7ff ff69 	bl	2b78 <nvmc_config>
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    2ca6:	f04f 2410 	mov.w	r4, #268439552	; 0x10001000
    2caa:	2512      	movs	r5, #18
    2cac:	f8c4 5200 	str.w	r5, [r4, #512]	; 0x200
            nvmc_wait();
    2cb0:	f7ff ff5a 	bl	2b68 <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    2cb4:	f8c4 5204 	str.w	r5, [r4, #516]	; 0x204
            nvmc_wait();
    2cb8:	f7ff ff56 	bl	2b68 <nvmc_wait>
            nvmc_config(NVMC_CONFIG_WEN_Ren);
    2cbc:	2000      	movs	r0, #0
    2cbe:	f7ff ff5b 	bl	2b78 <nvmc_config>
    2cc2:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2cc6:	4906      	ldr	r1, [pc, #24]	; (2ce0 <SystemInit+0x144>)
    2cc8:	68ca      	ldr	r2, [r1, #12]
    2cca:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2cce:	4b05      	ldr	r3, [pc, #20]	; (2ce4 <SystemInit+0x148>)
    2cd0:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    2cd2:	60cb      	str	r3, [r1, #12]
    2cd4:	f3bf 8f4f 	dsb	sy
    __NOP();
    2cd8:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    2cda:	e7fd      	b.n	2cd8 <SystemInit+0x13c>
    2cdc:	4000c000 	.word	0x4000c000
    2ce0:	e000ed00 	.word	0xe000ed00
    2ce4:	05fa0004 	.word	0x05fa0004

00002ce8 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    2ce8:	4b06      	ldr	r3, [pc, #24]	; (2d04 <nrfx_clock_init+0x1c>)
    2cea:	791b      	ldrb	r3, [r3, #4]
    2cec:	b93b      	cbnz	r3, 2cfe <nrfx_clock_init+0x16>
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    }
    else
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
    2cee:	4b05      	ldr	r3, [pc, #20]	; (2d04 <nrfx_clock_init+0x1c>)
    2cf0:	2200      	movs	r2, #0
    2cf2:	715a      	strb	r2, [r3, #5]
#endif
        m_clock_cb.event_handler = event_handler;
    2cf4:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    2cf6:	2201      	movs	r2, #1
    2cf8:	711a      	strb	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    2cfa:	4803      	ldr	r0, [pc, #12]	; (2d08 <nrfx_clock_init+0x20>)
    2cfc:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    2cfe:	4803      	ldr	r0, [pc, #12]	; (2d0c <nrfx_clock_init+0x24>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    2d00:	4770      	bx	lr
    2d02:	bf00      	nop
    2d04:	200003c8 	.word	0x200003c8
    2d08:	0bad0000 	.word	0x0bad0000
    2d0c:	0bad000c 	.word	0x0bad000c

00002d10 <nrfx_clock_start>:
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    2d10:	b110      	cbz	r0, 2d18 <nrfx_clock_start+0x8>
    2d12:	2801      	cmp	r0, #1
    2d14:	d00d      	beq.n	2d32 <nrfx_clock_start+0x22>
    2d16:	4770      	bx	lr
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2d18:	4b0b      	ldr	r3, [pc, #44]	; (2d48 <nrfx_clock_start+0x38>)
    2d1a:	2200      	movs	r2, #0
    2d1c:	601a      	str	r2, [r3, #0]
    2d1e:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    2d20:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2d24:	2202      	movs	r2, #2
    2d26:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2d2a:	3308      	adds	r3, #8
    2d2c:	2201      	movs	r2, #1
    2d2e:	601a      	str	r2, [r3, #0]
}
    2d30:	4770      	bx	lr
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2d32:	4b06      	ldr	r3, [pc, #24]	; (2d4c <nrfx_clock_start+0x3c>)
    2d34:	2200      	movs	r2, #0
    2d36:	601a      	str	r2, [r3, #0]
    2d38:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    2d3a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2d3e:	2201      	movs	r2, #1
    2d40:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2d44:	601a      	str	r2, [r3, #0]
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    2d46:	4770      	bx	lr
    2d48:	40000104 	.word	0x40000104
    2d4c:	40000100 	.word	0x40000100

00002d50 <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
    2d50:	b530      	push	{r4, r5, lr}
    2d52:	b083      	sub	sp, #12
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    2d54:	4604      	mov	r4, r0
    2d56:	b118      	cbz	r0, 2d60 <nrfx_clock_stop+0x10>
    2d58:	2801      	cmp	r0, #1
    2d5a:	d013      	beq.n	2d84 <nrfx_clock_stop+0x34>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    2d5c:	b003      	add	sp, #12
    2d5e:	bd30      	pop	{r4, r5, pc}
    p_reg->INTENCLR = mask;
    2d60:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2d64:	2202      	movs	r2, #2
    2d66:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2d6a:	f503 7382 	add.w	r3, r3, #260	; 0x104
    2d6e:	2200      	movs	r2, #0
    2d70:	601a      	str	r2, [r3, #0]
    2d72:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2d74:	4b37      	ldr	r3, [pc, #220]	; (2e54 <nrfx_clock_stop+0x104>)
    2d76:	2201      	movs	r2, #1
    2d78:	601a      	str	r2, [r3, #0]
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    2d7a:	2c01      	cmp	r4, #1
    2d7c:	d00f      	beq.n	2d9e <nrfx_clock_stop+0x4e>
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    2d7e:	f242 7510 	movw	r5, #10000	; 0x2710
    2d82:	e053      	b.n	2e2c <nrfx_clock_stop+0xdc>
    p_reg->INTENCLR = mask;
    2d84:	2301      	movs	r3, #1
    2d86:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    2d8a:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2d8e:	f502 7280 	add.w	r2, r2, #256	; 0x100
    2d92:	2100      	movs	r1, #0
    2d94:	6011      	str	r1, [r2, #0]
    2d96:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2d98:	4a2f      	ldr	r2, [pc, #188]	; (2e58 <nrfx_clock_stop+0x108>)
    2d9a:	6013      	str	r3, [r2, #0]
}
    2d9c:	e7ed      	b.n	2d7a <nrfx_clock_stop+0x2a>
        nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    2d9e:	2301      	movs	r3, #1
    2da0:	f88d 3007 	strb.w	r3, [sp, #7]
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
    2da4:	f242 7510 	movw	r5, #10000	; 0x2710
    2da8:	e018      	b.n	2ddc <nrfx_clock_stop+0x8c>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    2daa:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    2dae:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    2db2:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    2db6:	f8cd 3007 	str.w	r3, [sp, #7]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2dba:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
    2dbe:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    2dc2:	d120      	bne.n	2e06 <nrfx_clock_stop+0xb6>
    return false;
    2dc4:	2300      	movs	r3, #0
    2dc6:	2b00      	cmp	r3, #0
    2dc8:	d0c8      	beq.n	2d5c <nrfx_clock_stop+0xc>
    2dca:	f89d 3007 	ldrb.w	r3, [sp, #7]
    2dce:	2b01      	cmp	r3, #1
    2dd0:	d1c4      	bne.n	2d5c <nrfx_clock_stop+0xc>
    2dd2:	2001      	movs	r0, #1
    2dd4:	f002 f999 	bl	510a <nrfx_busy_wait>
    2dd8:	3d01      	subs	r5, #1
    2dda:	d0bf      	beq.n	2d5c <nrfx_clock_stop+0xc>
    switch (domain)
    2ddc:	2c00      	cmp	r4, #0
    2dde:	d0e4      	beq.n	2daa <nrfx_clock_stop+0x5a>
    2de0:	2c01      	cmp	r4, #1
    2de2:	d001      	beq.n	2de8 <nrfx_clock_stop+0x98>
    2de4:	2300      	movs	r3, #0
    2de6:	e7ee      	b.n	2dc6 <nrfx_clock_stop+0x76>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2de8:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    2dec:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
    2df0:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    2df4:	f88d 3007 	strb.w	r3, [sp, #7]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2df8:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
    2dfc:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    2e00:	d103      	bne.n	2e0a <nrfx_clock_stop+0xba>
    return false;
    2e02:	2300      	movs	r3, #0
    2e04:	e7df      	b.n	2dc6 <nrfx_clock_stop+0x76>
                return true;
    2e06:	2301      	movs	r3, #1
    2e08:	e7dd      	b.n	2dc6 <nrfx_clock_stop+0x76>
                return true;
    2e0a:	2301      	movs	r3, #1
    2e0c:	e7db      	b.n	2dc6 <nrfx_clock_stop+0x76>
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2e0e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2e12:	f8d3 3418 	ldr.w	r3, [r3, #1048]	; 0x418
    2e16:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    2e1a:	d116      	bne.n	2e4a <nrfx_clock_stop+0xfa>
    return false;
    2e1c:	2300      	movs	r3, #0
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    2e1e:	2b00      	cmp	r3, #0
    2e20:	d09c      	beq.n	2d5c <nrfx_clock_stop+0xc>
    2e22:	2001      	movs	r0, #1
    2e24:	f002 f971 	bl	510a <nrfx_busy_wait>
    2e28:	3d01      	subs	r5, #1
    2e2a:	d097      	beq.n	2d5c <nrfx_clock_stop+0xc>
    switch (domain)
    2e2c:	2c00      	cmp	r4, #0
    2e2e:	d0ee      	beq.n	2e0e <nrfx_clock_stop+0xbe>
    2e30:	2c01      	cmp	r4, #1
    2e32:	d001      	beq.n	2e38 <nrfx_clock_stop+0xe8>
    2e34:	2300      	movs	r3, #0
    2e36:	e7f2      	b.n	2e1e <nrfx_clock_stop+0xce>
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2e38:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2e3c:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
    2e40:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    2e44:	d103      	bne.n	2e4e <nrfx_clock_stop+0xfe>
    return false;
    2e46:	2300      	movs	r3, #0
    2e48:	e7e9      	b.n	2e1e <nrfx_clock_stop+0xce>
                return true;
    2e4a:	2301      	movs	r3, #1
    2e4c:	e7e7      	b.n	2e1e <nrfx_clock_stop+0xce>
                return true;
    2e4e:	2301      	movs	r3, #1
    2e50:	e7e5      	b.n	2e1e <nrfx_clock_stop+0xce>
    2e52:	bf00      	nop
    2e54:	4000000c 	.word	0x4000000c
    2e58:	40000004 	.word	0x40000004

00002e5c <nrfx_clock_calibration_start>:
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2e5c:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    2e60:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
    2e64:	f003 0301 	and.w	r3, r3, #1
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2e68:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
    2e6c:	f412 3f80 	tst.w	r2, #65536	; 0x10000
    2e70:	d104      	bne.n	2e7c <nrfx_clock_calibration_start+0x20>
    return false;
    2e72:	2200      	movs	r2, #0
{
    nrfx_err_t err_code = NRFX_SUCCESS;

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
    nrf_clock_hfclk_t clk_src;
    if (!nrfx_clock_is_running(NRF_CLOCK_DOMAIN_HFCLK, &clk_src))
    2e74:	b302      	cbz	r2, 2eb8 <nrfx_clock_calibration_start+0x5c>
    {
        return NRFX_ERROR_INVALID_STATE;
    }

    if (clk_src != NRF_CLOCK_HFCLK_HIGH_ACCURACY)
    2e76:	b91b      	cbnz	r3, 2e80 <nrfx_clock_calibration_start+0x24>
    {
        return NRFX_ERROR_INVALID_STATE;
    2e78:	4812      	ldr	r0, [pc, #72]	; (2ec4 <nrfx_clock_calibration_start+0x68>)
    2e7a:	4770      	bx	lr
                return true;
    2e7c:	2201      	movs	r2, #1
    2e7e:	e7f9      	b.n	2e74 <nrfx_clock_calibration_start+0x18>
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2e80:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2e84:	f8d3 3418 	ldr.w	r3, [r3, #1048]	; 0x418
    2e88:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    2e8c:	d100      	bne.n	2e90 <nrfx_clock_calibration_start+0x34>
    return false;
    2e8e:	2200      	movs	r2, #0
    }

    if (!nrfx_clock_is_running(NRF_CLOCK_DOMAIN_LFCLK, NULL))
    2e90:	b1a2      	cbz	r2, 2ebc <nrfx_clock_calibration_start+0x60>
    {
        return NRFX_ERROR_INVALID_STATE;
    }

    if (m_clock_cb.cal_state == CAL_STATE_IDLE)
    2e92:	4b0d      	ldr	r3, [pc, #52]	; (2ec8 <nrfx_clock_calibration_start+0x6c>)
    2e94:	795b      	ldrb	r3, [r3, #5]
    2e96:	b99b      	cbnz	r3, 2ec0 <nrfx_clock_calibration_start+0x64>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2e98:	4b0c      	ldr	r3, [pc, #48]	; (2ecc <nrfx_clock_calibration_start+0x70>)
    2e9a:	2200      	movs	r2, #0
    2e9c:	601a      	str	r2, [r3, #0]
    2e9e:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    2ea0:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2ea4:	2208      	movs	r2, #8
    2ea6:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_DONE);
        nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_DONE_MASK);
        m_clock_cb.cal_state = CAL_STATE_CAL;
    2eaa:	2301      	movs	r3, #1
    2eac:	4a06      	ldr	r2, [pc, #24]	; (2ec8 <nrfx_clock_calibration_start+0x6c>)
    2eae:	7153      	strb	r3, [r2, #5]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2eb0:	4a07      	ldr	r2, [pc, #28]	; (2ed0 <nrfx_clock_calibration_start+0x74>)
    2eb2:	6013      	str	r3, [r2, #0]
    nrfx_err_t err_code = NRFX_SUCCESS;
    2eb4:	4807      	ldr	r0, [pc, #28]	; (2ed4 <nrfx_clock_calibration_start+0x78>)
}
    2eb6:	4770      	bx	lr
        return NRFX_ERROR_INVALID_STATE;
    2eb8:	4802      	ldr	r0, [pc, #8]	; (2ec4 <nrfx_clock_calibration_start+0x68>)
    2eba:	4770      	bx	lr
        return NRFX_ERROR_INVALID_STATE;
    2ebc:	4801      	ldr	r0, [pc, #4]	; (2ec4 <nrfx_clock_calibration_start+0x68>)
    2ebe:	4770      	bx	lr
#endif
        nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_CAL);
    }
    else
    {
        err_code = NRFX_ERROR_BUSY;
    2ec0:	4805      	ldr	r0, [pc, #20]	; (2ed8 <nrfx_clock_calibration_start+0x7c>)

    NRFX_LOG_WARNING("Function: %s, error code: %s.",
                     __func__,
                     NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    2ec2:	4770      	bx	lr
    2ec4:	0bad0005 	.word	0x0bad0005
    2ec8:	200003c8 	.word	0x200003c8
    2ecc:	4000010c 	.word	0x4000010c
    2ed0:	40000010 	.word	0x40000010
    2ed4:	0bad0000 	.word	0x0bad0000
    2ed8:	0bad000b 	.word	0x0bad000b

00002edc <nrfx_power_clock_irq_handler>:
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    2edc:	b508      	push	{r3, lr}
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2ede:	4b20      	ldr	r3, [pc, #128]	; (2f60 <nrfx_power_clock_irq_handler+0x84>)
    2ee0:	681b      	ldr	r3, [r3, #0]
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    2ee2:	b15b      	cbz	r3, 2efc <nrfx_power_clock_irq_handler+0x20>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2ee4:	4b1e      	ldr	r3, [pc, #120]	; (2f60 <nrfx_power_clock_irq_handler+0x84>)
    2ee6:	2000      	movs	r0, #0
    2ee8:	6018      	str	r0, [r3, #0]
    2eea:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    2eec:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2ef0:	2201      	movs	r2, #1
    2ef2:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    2ef6:	4b1b      	ldr	r3, [pc, #108]	; (2f64 <nrfx_power_clock_irq_handler+0x88>)
    2ef8:	681b      	ldr	r3, [r3, #0]
    2efa:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2efc:	4b1a      	ldr	r3, [pc, #104]	; (2f68 <nrfx_power_clock_irq_handler+0x8c>)
    2efe:	681b      	ldr	r3, [r3, #0]
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    2f00:	b163      	cbz	r3, 2f1c <nrfx_power_clock_irq_handler+0x40>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2f02:	4b19      	ldr	r3, [pc, #100]	; (2f68 <nrfx_power_clock_irq_handler+0x8c>)
    2f04:	2200      	movs	r2, #0
    2f06:	601a      	str	r2, [r3, #0]
    2f08:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    2f0a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2f0e:	2202      	movs	r2, #2
    2f10:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        else
#endif
        {
            // After the LF clock external source start invoke user callback.
            nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK);
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    2f14:	4b13      	ldr	r3, [pc, #76]	; (2f64 <nrfx_power_clock_irq_handler+0x88>)
    2f16:	681b      	ldr	r3, [r3, #0]
    2f18:	2001      	movs	r0, #1
    2f1a:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2f1c:	4b13      	ldr	r3, [pc, #76]	; (2f6c <nrfx_power_clock_irq_handler+0x90>)
    2f1e:	681b      	ldr	r3, [r3, #0]
        }
    }

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
#if NRF_CLOCK_HAS_CALIBRATION_TIMER
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO))
    2f20:	b163      	cbz	r3, 2f3c <nrfx_power_clock_irq_handler+0x60>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2f22:	4b12      	ldr	r3, [pc, #72]	; (2f6c <nrfx_power_clock_irq_handler+0x90>)
    2f24:	2200      	movs	r2, #0
    2f26:	601a      	str	r2, [r3, #0]
    2f28:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    2f2a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2f2e:	2210      	movs	r2, #16
    2f30:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_CTTO");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_CTTO);
    2f34:	4b0b      	ldr	r3, [pc, #44]	; (2f64 <nrfx_power_clock_irq_handler+0x88>)
    2f36:	681b      	ldr	r3, [r3, #0]
    2f38:	2002      	movs	r0, #2
    2f3a:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2f3c:	4b0c      	ldr	r3, [pc, #48]	; (2f70 <nrfx_power_clock_irq_handler+0x94>)
    2f3e:	681b      	ldr	r3, [r3, #0]
    }
#endif // NRF_CLOCK_HAS_CALIBRATION_TIMER

    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_DONE))
    2f40:	b16b      	cbz	r3, 2f5e <nrfx_power_clock_irq_handler+0x82>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2f42:	4b0b      	ldr	r3, [pc, #44]	; (2f70 <nrfx_power_clock_irq_handler+0x94>)
    2f44:	2200      	movs	r2, #0
    2f46:	601a      	str	r2, [r3, #0]
    2f48:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    2f4a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2f4e:	2108      	movs	r1, #8
    2f50:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
        *(volatile uint32_t *)0x40000C34 = 0x00000000;
#endif
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_DONE);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_DONE");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_DONE_MASK);
        m_clock_cb.cal_state = CAL_STATE_IDLE;
    2f54:	4b03      	ldr	r3, [pc, #12]	; (2f64 <nrfx_power_clock_irq_handler+0x88>)
    2f56:	715a      	strb	r2, [r3, #5]
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_CAL_DONE);
    2f58:	681b      	ldr	r3, [r3, #0]
    2f5a:	2003      	movs	r0, #3
    2f5c:	4798      	blx	r3
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    2f5e:	bd08      	pop	{r3, pc}
    2f60:	40000100 	.word	0x40000100
    2f64:	200003c8 	.word	0x200003c8
    2f68:	40000104 	.word	0x40000104
    2f6c:	40000110 	.word	0x40000110
    2f70:	4000010c 	.word	0x4000010c

00002f74 <is_allocated_channel>:
    NRFX_LOG_INFO("Uninitialized.");
}

static bool is_allocated_channel(uint8_t index)
{
    return m_cb.allocated_channels_mask & (1UL << index);
    2f74:	4b04      	ldr	r3, [pc, #16]	; (2f88 <is_allocated_channel+0x14>)
    2f76:	6d9a      	ldr	r2, [r3, #88]	; 0x58
    2f78:	2301      	movs	r3, #1
    2f7a:	4083      	lsls	r3, r0
    2f7c:	421a      	tst	r2, r3
}
    2f7e:	bf14      	ite	ne
    2f80:	2001      	movne	r0, #1
    2f82:	2000      	moveq	r0, #0
    2f84:	4770      	bx	lr
    2f86:	bf00      	nop
    2f88:	200003d0 	.word	0x200003d0

00002f8c <channel_allocated_set>:
    return NRFX_GPIOTE_APP_CHANNELS_MASK & (1UL << index);
}

static void channel_allocated_set(uint8_t index)
{
    m_cb.allocated_channels_mask |= (1UL << index);
    2f8c:	2301      	movs	r3, #1
    2f8e:	fa03 f000 	lsl.w	r0, r3, r0
    2f92:	4a02      	ldr	r2, [pc, #8]	; (2f9c <channel_allocated_set+0x10>)
    2f94:	6d93      	ldr	r3, [r2, #88]	; 0x58
    2f96:	4303      	orrs	r3, r0
    2f98:	6593      	str	r3, [r2, #88]	; 0x58
}
    2f9a:	4770      	bx	lr
    2f9c:	200003d0 	.word	0x200003d0

00002fa0 <channel_allocated_clr>:

static void channel_allocated_clr(uint8_t index)
{
    m_cb.allocated_channels_mask &= ~(1UL << index);
    2fa0:	2301      	movs	r3, #1
    2fa2:	fa03 f000 	lsl.w	r0, r3, r0
    2fa6:	4a03      	ldr	r2, [pc, #12]	; (2fb4 <channel_allocated_clr+0x14>)
    2fa8:	6d93      	ldr	r3, [r2, #88]	; 0x58
    2faa:	ea23 0300 	bic.w	r3, r3, r0
    2fae:	6593      	str	r3, [r2, #88]	; 0x58
}
    2fb0:	4770      	bx	lr
    2fb2:	bf00      	nop
    2fb4:	200003d0 	.word	0x200003d0

00002fb8 <nrfx_gpiote_channel_free>:

nrfx_err_t nrfx_gpiote_channel_free(uint8_t channel)
{
    2fb8:	b538      	push	{r3, r4, r5, lr}
    2fba:	4604      	mov	r4, r0
    nrfx_err_t err_code = NRFX_SUCCESS;

    if (!is_app_channel(channel))
    2fbc:	f002 f8b7 	bl	512e <is_app_channel>
    2fc0:	b908      	cbnz	r0, 2fc6 <nrfx_gpiote_channel_free+0xe>
    {
        err_code = NRFX_ERROR_INVALID_PARAM;
    2fc2:	4809      	ldr	r0, [pc, #36]	; (2fe8 <nrfx_gpiote_channel_free+0x30>)
        NRFX_CRITICAL_SECTION_EXIT();
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    2fc4:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    2fc6:	f04f 0320 	mov.w	r3, #32
    2fca:	f3ef 8511 	mrs	r5, BASEPRI
    2fce:	f383 8811 	msr	BASEPRI, r3
    2fd2:	f3bf 8f6f 	isb	sy
        channel_allocated_clr(channel);
    2fd6:	4620      	mov	r0, r4
    2fd8:	f7ff ffe2 	bl	2fa0 <channel_allocated_clr>
	__asm__ volatile(
    2fdc:	f385 8811 	msr	BASEPRI, r5
    2fe0:	f3bf 8f6f 	isb	sy
    nrfx_err_t err_code = NRFX_SUCCESS;
    2fe4:	4801      	ldr	r0, [pc, #4]	; (2fec <nrfx_gpiote_channel_free+0x34>)
}
    2fe6:	e7ed      	b.n	2fc4 <nrfx_gpiote_channel_free+0xc>
    2fe8:	0bad0004 	.word	0x0bad0004
    2fec:	0bad0000 	.word	0x0bad0000

00002ff0 <nrfx_gpiote_channel_alloc>:

nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel)
{
    2ff0:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    2ff4:	4680      	mov	r8, r0
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    uint32_t mask = NRFX_GPIOTE_APP_CHANNELS_MASK;

    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    2ff6:	2400      	movs	r4, #0
    uint32_t mask = NRFX_GPIOTE_APP_CHANNELS_MASK;
    2ff8:	25ff      	movs	r5, #255	; 0xff
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    2ffa:	4f17      	ldr	r7, [pc, #92]	; (3058 <nrfx_gpiote_channel_alloc+0x68>)
    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    2ffc:	e013      	b.n	3026 <nrfx_gpiote_channel_alloc+0x36>
    {
        NRFX_CRITICAL_SECTION_ENTER();
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
        {
            channel_allocated_set(ch_idx);
    2ffe:	4620      	mov	r0, r4
    3000:	f7ff ffc4 	bl	2f8c <channel_allocated_set>
            *p_channel = ch_idx;
    3004:	f888 4000 	strb.w	r4, [r8]
            err_code = NRFX_SUCCESS;
    3008:	4f14      	ldr	r7, [pc, #80]	; (305c <nrfx_gpiote_channel_alloc+0x6c>)
	__asm__ volatile(
    300a:	f386 8811 	msr	BASEPRI, r6
    300e:	f3bf 8f6f 	isb	sy
        }
        NRFX_CRITICAL_SECTION_EXIT();

        if (err_code == NRFX_SUCCESS)
    3012:	4b12      	ldr	r3, [pc, #72]	; (305c <nrfx_gpiote_channel_alloc+0x6c>)
    3014:	429f      	cmp	r7, r3
    3016:	d01b      	beq.n	3050 <nrfx_gpiote_channel_alloc+0x60>
        {
            NRFX_LOG_INFO("Allocated channel: %d.", ch_idx);
            break;
        }

        mask &= ~(1UL << ch_idx);
    3018:	2301      	movs	r3, #1
    301a:	fa03 f309 	lsl.w	r3, r3, r9
    301e:	ea25 0503 	bic.w	r5, r5, r3
    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    3022:	3401      	adds	r4, #1
    3024:	b2e4      	uxtb	r4, r4
    3026:	b19d      	cbz	r5, 3050 <nrfx_gpiote_channel_alloc+0x60>
	__asm__ volatile(
    3028:	f04f 0320 	mov.w	r3, #32
    302c:	f3ef 8611 	mrs	r6, BASEPRI
    3030:	f383 8811 	msr	BASEPRI, r3
    3034:	f3bf 8f6f 	isb	sy
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
    3038:	46a1      	mov	r9, r4
    303a:	fa25 f304 	lsr.w	r3, r5, r4
    303e:	f013 0f01 	tst.w	r3, #1
    3042:	d0e2      	beq.n	300a <nrfx_gpiote_channel_alloc+0x1a>
    3044:	4620      	mov	r0, r4
    3046:	f7ff ff95 	bl	2f74 <is_allocated_channel>
    304a:	2800      	cmp	r0, #0
    304c:	d1dd      	bne.n	300a <nrfx_gpiote_channel_alloc+0x1a>
    304e:	e7d6      	b.n	2ffe <nrfx_gpiote_channel_alloc+0xe>
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    3050:	4638      	mov	r0, r7
    3052:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    3056:	bf00      	nop
    3058:	0bad0002 	.word	0x0bad0002
    305c:	0bad0000 	.word	0x0bad0000

00003060 <_DoInit>:
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    3060:	4b14      	ldr	r3, [pc, #80]	; (30b4 <_DoInit+0x54>)
    3062:	2203      	movs	r2, #3
    3064:	611a      	str	r2, [r3, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    3066:	615a      	str	r2, [r3, #20]
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    3068:	4913      	ldr	r1, [pc, #76]	; (30b8 <_DoInit+0x58>)
    306a:	6199      	str	r1, [r3, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    306c:	4a13      	ldr	r2, [pc, #76]	; (30bc <_DoInit+0x5c>)
    306e:	61da      	str	r2, [r3, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    3070:	f44f 6280 	mov.w	r2, #1024	; 0x400
    3074:	621a      	str	r2, [r3, #32]
  p->aUp[0].RdOff         = 0u;
    3076:	2200      	movs	r2, #0
    3078:	629a      	str	r2, [r3, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    307a:	625a      	str	r2, [r3, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    307c:	62da      	str	r2, [r3, #44]	; 0x2c
  //
  // Initialize down buffer 0
  //
  p->aDown[0].sName         = "Terminal";
    307e:	6619      	str	r1, [r3, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    3080:	490f      	ldr	r1, [pc, #60]	; (30c0 <_DoInit+0x60>)
    3082:	6659      	str	r1, [r3, #100]	; 0x64
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    3084:	2110      	movs	r1, #16
    3086:	6699      	str	r1, [r3, #104]	; 0x68
  p->aDown[0].RdOff         = 0u;
    3088:	671a      	str	r2, [r3, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    308a:	66da      	str	r2, [r3, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    308c:	675a      	str	r2, [r3, #116]	; 0x74
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    308e:	4a0d      	ldr	r2, [pc, #52]	; (30c4 <_DoInit+0x64>)
    3090:	6810      	ldr	r0, [r2, #0]
    3092:	f8c3 0007 	str.w	r0, [r3, #7]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    3096:	f3bf 8f5f 	dmb	sy
  STRCPY((char*)&p->acID[0], "SEGGER");
    309a:	4a0b      	ldr	r2, [pc, #44]	; (30c8 <_DoInit+0x68>)
    309c:	e892 0003 	ldmia.w	r2, {r0, r1}
    30a0:	6018      	str	r0, [r3, #0]
    30a2:	8099      	strh	r1, [r3, #4]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    30a4:	f3bf 8f5f 	dmb	sy
  p->acID[6] = ' ';
    30a8:	2220      	movs	r2, #32
    30aa:	719a      	strb	r2, [r3, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    30ac:	f3bf 8f5f 	dmb	sy
}
    30b0:	4770      	bx	lr
    30b2:	bf00      	nop
    30b4:	2000042c 	.word	0x2000042c
    30b8:	00005bf0 	.word	0x00005bf0
    30bc:	200004e4 	.word	0x200004e4
    30c0:	200004d4 	.word	0x200004d4
    30c4:	00005bfc 	.word	0x00005bfc
    30c8:	00005c00 	.word	0x00005c00

000030cc <z_device_state_init>:
 * The state object is always zero-initialized, but this may not be
 * sufficient.
 */
void z_device_state_init(void)
{
	const struct device *dev = __device_start;
    30cc:	4b03      	ldr	r3, [pc, #12]	; (30dc <z_device_state_init+0x10>)

	while (dev < __device_end) {
    30ce:	4a04      	ldr	r2, [pc, #16]	; (30e0 <z_device_state_init+0x14>)
    30d0:	4293      	cmp	r3, r2
    30d2:	d201      	bcs.n	30d8 <z_device_state_init+0xc>
		device_pm_state_init(dev);
		z_object_init(dev);
		++dev;
    30d4:	3318      	adds	r3, #24
    30d6:	e7fa      	b.n	30ce <z_device_state_init+0x2>
	}
}
    30d8:	4770      	bx	lr
    30da:	bf00      	nop
    30dc:	00005844 	.word	0x00005844
    30e0:	000058d4 	.word	0x000058d4

000030e4 <z_sys_init_run_level>:
 * off and the next one begins.
 *
 * @param level init level to run.
 */
void z_sys_init_run_level(int32_t level)
{
    30e4:	b570      	push	{r4, r5, r6, lr}
    30e6:	4606      	mov	r6, r0
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    30e8:	4b11      	ldr	r3, [pc, #68]	; (3130 <z_sys_init_run_level+0x4c>)
    30ea:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    30ee:	e009      	b.n	3104 <z_sys_init_run_level+0x20>
			/* Mark device initialized.  If initialization
			 * failed, record the error condition.
			 */
			if (rc != 0) {
				if (rc < 0) {
					rc = -rc;
    30f0:	4240      	negs	r0, r0
    30f2:	e017      	b.n	3124 <z_sys_init_run_level+0x40>
				}
				if (rc > UINT8_MAX) {
					rc = UINT8_MAX;
				}
				dev->state->init_res = rc;
    30f4:	68eb      	ldr	r3, [r5, #12]
    30f6:	7018      	strb	r0, [r3, #0]
			}
			dev->state->initialized = true;
    30f8:	68ea      	ldr	r2, [r5, #12]
    30fa:	7853      	ldrb	r3, [r2, #1]
    30fc:	f043 0301 	orr.w	r3, r3, #1
    3100:	7053      	strb	r3, [r2, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    3102:	3408      	adds	r4, #8
    3104:	1c73      	adds	r3, r6, #1
    3106:	4a0a      	ldr	r2, [pc, #40]	; (3130 <z_sys_init_run_level+0x4c>)
    3108:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
    310c:	42a3      	cmp	r3, r4
    310e:	d90d      	bls.n	312c <z_sys_init_run_level+0x48>
		const struct device *dev = entry->dev;
    3110:	6865      	ldr	r5, [r4, #4]
		int rc = entry->init(dev);
    3112:	6823      	ldr	r3, [r4, #0]
    3114:	4628      	mov	r0, r5
    3116:	4798      	blx	r3
		if (dev != NULL) {
    3118:	2d00      	cmp	r5, #0
    311a:	d0f2      	beq.n	3102 <z_sys_init_run_level+0x1e>
			if (rc != 0) {
    311c:	2800      	cmp	r0, #0
    311e:	d0eb      	beq.n	30f8 <z_sys_init_run_level+0x14>
				if (rc < 0) {
    3120:	2800      	cmp	r0, #0
    3122:	dbe5      	blt.n	30f0 <z_sys_init_run_level+0xc>
				if (rc > UINT8_MAX) {
    3124:	28ff      	cmp	r0, #255	; 0xff
    3126:	dde5      	ble.n	30f4 <z_sys_init_run_level+0x10>
					rc = UINT8_MAX;
    3128:	20ff      	movs	r0, #255	; 0xff
    312a:	e7e3      	b.n	30f4 <z_sys_init_run_level+0x10>
		}
	}
}
    312c:	bd70      	pop	{r4, r5, r6, pc}
    312e:	bf00      	nop
    3130:	00005c08 	.word	0x00005c08

00003134 <z_impl_device_get_binding>:

const struct device *z_impl_device_get_binding(const char *name)
{
    3134:	b538      	push	{r3, r4, r5, lr}
	const struct device *dev;

	/* A null string identifies no device.  So does an empty
	 * string.
	 */
	if ((name == NULL) || (name[0] == '\0')) {
    3136:	4605      	mov	r5, r0
    3138:	b328      	cbz	r0, 3186 <z_impl_device_get_binding+0x52>
    313a:	7803      	ldrb	r3, [r0, #0]
    313c:	b32b      	cbz	r3, 318a <z_impl_device_get_binding+0x56>
	/* Split the search into two loops: in the common scenario, where
	 * device names are stored in ROM (and are referenced by the user
	 * with CONFIG_* macros), only cheap pointer comparisons will be
	 * performed. Reserve string comparisons for a fallback.
	 */
	for (dev = __device_start; dev != __device_end; dev++) {
    313e:	4c14      	ldr	r4, [pc, #80]	; (3190 <z_impl_device_get_binding+0x5c>)
    3140:	e000      	b.n	3144 <z_impl_device_get_binding+0x10>
    3142:	3418      	adds	r4, #24
    3144:	4b13      	ldr	r3, [pc, #76]	; (3194 <z_impl_device_get_binding+0x60>)
    3146:	429c      	cmp	r4, r3
    3148:	d008      	beq.n	315c <z_impl_device_get_binding+0x28>
		if (z_device_ready(dev) && (dev->name == name)) {
    314a:	4620      	mov	r0, r4
    314c:	f002 f800 	bl	5150 <z_device_ready>
    3150:	2800      	cmp	r0, #0
    3152:	d0f6      	beq.n	3142 <z_impl_device_get_binding+0xe>
    3154:	6823      	ldr	r3, [r4, #0]
    3156:	42ab      	cmp	r3, r5
    3158:	d1f3      	bne.n	3142 <z_impl_device_get_binding+0xe>
    315a:	e012      	b.n	3182 <z_impl_device_get_binding+0x4e>
			return dev;
		}
	}

	for (dev = __device_start; dev != __device_end; dev++) {
    315c:	4c0c      	ldr	r4, [pc, #48]	; (3190 <z_impl_device_get_binding+0x5c>)
    315e:	e000      	b.n	3162 <z_impl_device_get_binding+0x2e>
    3160:	3418      	adds	r4, #24
    3162:	4b0c      	ldr	r3, [pc, #48]	; (3194 <z_impl_device_get_binding+0x60>)
    3164:	429c      	cmp	r4, r3
    3166:	d00b      	beq.n	3180 <z_impl_device_get_binding+0x4c>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    3168:	4620      	mov	r0, r4
    316a:	f001 fff1 	bl	5150 <z_device_ready>
    316e:	2800      	cmp	r0, #0
    3170:	d0f6      	beq.n	3160 <z_impl_device_get_binding+0x2c>
    3172:	6821      	ldr	r1, [r4, #0]
    3174:	4628      	mov	r0, r5
    3176:	f7fd f93d 	bl	3f4 <strcmp>
    317a:	2800      	cmp	r0, #0
    317c:	d1f0      	bne.n	3160 <z_impl_device_get_binding+0x2c>
    317e:	e000      	b.n	3182 <z_impl_device_get_binding+0x4e>
			return dev;
		}
	}

	return NULL;
    3180:	2400      	movs	r4, #0
}
    3182:	4620      	mov	r0, r4
    3184:	bd38      	pop	{r3, r4, r5, pc}
		return NULL;
    3186:	4604      	mov	r4, r0
    3188:	e7fb      	b.n	3182 <z_impl_device_get_binding+0x4e>
    318a:	2400      	movs	r4, #0
    318c:	e7f9      	b.n	3182 <z_impl_device_get_binding+0x4e>
    318e:	bf00      	nop
    3190:	00005844 	.word	0x00005844
    3194:	000058d4 	.word	0x000058d4

00003198 <init_idle_thread>:
/* LCOV_EXCL_STOP */

#if defined(CONFIG_MULTITHREADING)
__boot_func
static void init_idle_thread(int i)
{
    3198:	b530      	push	{r4, r5, lr}
    319a:	b087      	sub	sp, #28
	struct k_thread *thread = &z_idle_threads[i];
    319c:	4c10      	ldr	r4, [pc, #64]	; (31e0 <init_idle_thread+0x48>)
    319e:	eb04 14c0 	add.w	r4, r4, r0, lsl #7
	k_thread_stack_t *stack = z_idle_stacks[i];
    31a2:	eb00 0580 	add.w	r5, r0, r0, lsl #2
#else
	char *tname = NULL;
#endif /* CONFIG_THREAD_NAME */

	z_setup_new_thread(thread, stack,
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    31a6:	eb00 0040 	add.w	r0, r0, r0, lsl #1
    31aa:	4b0e      	ldr	r3, [pc, #56]	; (31e4 <init_idle_thread+0x4c>)
    31ac:	eb03 00c0 	add.w	r0, r3, r0, lsl #3
	z_setup_new_thread(thread, stack,
    31b0:	2300      	movs	r3, #0
    31b2:	9305      	str	r3, [sp, #20]
    31b4:	2201      	movs	r2, #1
    31b6:	9204      	str	r2, [sp, #16]
    31b8:	220f      	movs	r2, #15
    31ba:	9203      	str	r2, [sp, #12]
    31bc:	9302      	str	r3, [sp, #8]
    31be:	9301      	str	r3, [sp, #4]
    31c0:	9000      	str	r0, [sp, #0]
    31c2:	4b09      	ldr	r3, [pc, #36]	; (31e8 <init_idle_thread+0x50>)
    31c4:	f44f 72a0 	mov.w	r2, #320	; 0x140
    31c8:	4908      	ldr	r1, [pc, #32]	; (31ec <init_idle_thread+0x54>)
    31ca:	eb01 1185 	add.w	r1, r1, r5, lsl #6
    31ce:	4620      	mov	r0, r4
    31d0:	f000 f8de 	bl	3390 <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    31d4:	7b63      	ldrb	r3, [r4, #13]
    31d6:	f023 0304 	bic.w	r3, r3, #4
    31da:	7363      	strb	r3, [r4, #13]
	z_mark_thread_as_started(thread);

#ifdef CONFIG_SMP
	thread->base.is_idle = 1U;
#endif
}
    31dc:	b007      	add	sp, #28
    31de:	bd30      	pop	{r4, r5, pc}
    31e0:	200000e0 	.word	0x200000e0
    31e4:	200008e4 	.word	0x200008e4
    31e8:	00005231 	.word	0x00005231
    31ec:	20000d58 	.word	0x20000d58

000031f0 <prepare_multithreading>:
 *
 * @return initial stack pointer for the main thread
 */
__boot_func
static char *prepare_multithreading(void)
{
    31f0:	b570      	push	{r4, r5, r6, lr}
    31f2:	b086      	sub	sp, #24
	char *stack_ptr;

	/* _kernel.ready_q is all zeroes */
	z_sched_init();
    31f4:	f000 fec2 	bl	3f7c <z_sched_init>
	 * - the main thread will be the one to run first
	 * - no other thread is initialized yet and thus their priority fields
	 *   contain garbage, which would prevent the cache loading algorithm
	 *   to work as intended
	 */
	_kernel.ready_q.cache = &z_main_thread;
    31f8:	4d1c      	ldr	r5, [pc, #112]	; (326c <prepare_multithreading+0x7c>)
    31fa:	4b1d      	ldr	r3, [pc, #116]	; (3270 <prepare_multithreading+0x80>)
    31fc:	625d      	str	r5, [r3, #36]	; 0x24
#endif
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    31fe:	4b1d      	ldr	r3, [pc, #116]	; (3274 <prepare_multithreading+0x84>)
    3200:	9305      	str	r3, [sp, #20]
    3202:	2301      	movs	r3, #1
    3204:	9304      	str	r3, [sp, #16]
    3206:	2400      	movs	r4, #0
    3208:	9403      	str	r4, [sp, #12]
    320a:	9402      	str	r4, [sp, #8]
    320c:	9401      	str	r4, [sp, #4]
    320e:	9400      	str	r4, [sp, #0]
    3210:	4b19      	ldr	r3, [pc, #100]	; (3278 <prepare_multithreading+0x88>)
    3212:	f44f 6280 	mov.w	r2, #1024	; 0x400
    3216:	4919      	ldr	r1, [pc, #100]	; (327c <prepare_multithreading+0x8c>)
    3218:	4628      	mov	r0, r5
    321a:	f000 f8b9 	bl	3390 <z_setup_new_thread>
    321e:	4606      	mov	r6, r0
    3220:	7b6b      	ldrb	r3, [r5, #13]
    3222:	f023 0304 	bic.w	r3, r3, #4
    3226:	736b      	strb	r3, [r5, #13]
				       CONFIG_MAIN_STACK_SIZE, bg_thread_main,
				       NULL, NULL, NULL,
				       CONFIG_MAIN_THREAD_PRIORITY,
				       K_ESSENTIAL, "main");
	z_mark_thread_as_started(&z_main_thread);
	z_ready_thread(&z_main_thread);
    3228:	4628      	mov	r0, r5
    322a:	f002 f8f5 	bl	5418 <z_ready_thread>

	for (int i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
    322e:	2c00      	cmp	r4, #0
    3230:	dd07      	ble.n	3242 <prepare_multithreading+0x52>
 * @return N/A
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
    3232:	4b0f      	ldr	r3, [pc, #60]	; (3270 <prepare_multithreading+0x80>)
    3234:	f103 0218 	add.w	r2, r3, #24
    3238:	619a      	str	r2, [r3, #24]
	list->tail = (sys_dnode_t *)list;
    323a:	61da      	str	r2, [r3, #28]
	}

	initialize_timeouts();

	return stack_ptr;
}
    323c:	4630      	mov	r0, r6
    323e:	b006      	add	sp, #24
    3240:	bd70      	pop	{r4, r5, r6, pc}
		init_idle_thread(i);
    3242:	4620      	mov	r0, r4
    3244:	f7ff ffa8 	bl	3198 <init_idle_thread>
		_kernel.cpus[i].idle_thread = &z_idle_threads[i];
    3248:	4a0d      	ldr	r2, [pc, #52]	; (3280 <prepare_multithreading+0x90>)
    324a:	eb02 12c4 	add.w	r2, r2, r4, lsl #7
    324e:	eb04 0144 	add.w	r1, r4, r4, lsl #1
    3252:	4b07      	ldr	r3, [pc, #28]	; (3270 <prepare_multithreading+0x80>)
    3254:	eb03 03c1 	add.w	r3, r3, r1, lsl #3
    3258:	60da      	str	r2, [r3, #12]
		_kernel.cpus[i].id = i;
    325a:	751c      	strb	r4, [r3, #20]
			(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[i]) +
    325c:	4a09      	ldr	r2, [pc, #36]	; (3284 <prepare_multithreading+0x94>)
    325e:	eb02 22c4 	add.w	r2, r2, r4, lsl #11
    3262:	f502 6200 	add.w	r2, r2, #2048	; 0x800
		_kernel.cpus[i].irq_stack =
    3266:	605a      	str	r2, [r3, #4]
	for (int i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
    3268:	3401      	adds	r4, #1
    326a:	e7e0      	b.n	322e <prepare_multithreading+0x3e>
    326c:	20000160 	.word	0x20000160
    3270:	200008e4 	.word	0x200008e4
    3274:	00005c20 	.word	0x00005c20
    3278:	000032b5 	.word	0x000032b5
    327c:	20000958 	.word	0x20000958
    3280:	200000e0 	.word	0x200000e0
    3284:	20000e98 	.word	0x20000e98

00003288 <switch_to_main_thread>:

__boot_func
static FUNC_NORETURN void switch_to_main_thread(char *stack_ptr)
{
    3288:	b508      	push	{r3, lr}
    328a:	4601      	mov	r1, r0
#ifdef CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    328c:	4a01      	ldr	r2, [pc, #4]	; (3294 <switch_to_main_thread+0xc>)
    328e:	4802      	ldr	r0, [pc, #8]	; (3298 <switch_to_main_thread+0x10>)
    3290:	f7fe fc1a 	bl	1ac8 <arch_switch_to_main_thread>
	 * current fake thread is not on a wait queue or ready queue, so it
	 * will never be rescheduled in.
	 */
	z_swap_unlocked();
#endif
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    3294:	000032b5 	.word	0x000032b5
    3298:	20000160 	.word	0x20000160

0000329c <z_bss_zero>:
{
    329c:	b508      	push	{r3, lr}
	(void)memset(__bss_start, 0, __bss_end - __bss_start);
    329e:	4803      	ldr	r0, [pc, #12]	; (32ac <z_bss_zero+0x10>)

__BEGIN_DECLS
__ssp_bos_icheck3_restrict(memcpy, void *, const void *)
__ssp_bos_icheck3(memmove, void *, const void *)
__ssp_bos_icheck3_restrict(mempcpy, void *, const void *)
__ssp_bos_icheck3(memset, void *, int)
    32a0:	4a03      	ldr	r2, [pc, #12]	; (32b0 <z_bss_zero+0x14>)
    32a2:	1a12      	subs	r2, r2, r0
    32a4:	2100      	movs	r1, #0
    32a6:	f002 fa58 	bl	575a <memset>
}
    32aa:	bd08      	pop	{r3, pc}
    32ac:	200000e0 	.word	0x200000e0
    32b0:	20000954 	.word	0x20000954

000032b4 <bg_thread_main>:
{
    32b4:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    32b6:	4b0c      	ldr	r3, [pc, #48]	; (32e8 <bg_thread_main+0x34>)
    32b8:	2201      	movs	r2, #1
    32ba:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    32bc:	2002      	movs	r0, #2
    32be:	f7ff ff11 	bl	30e4 <z_sys_init_run_level>
	boot_banner();
    32c2:	f001 f9a1 	bl	4608 <boot_banner>
	__do_global_ctors_aux();
    32c6:	f7fd ff29 	bl	111c <__do_global_ctors_aux>
	__do_init_array_aux();
    32ca:	f7fd ff19 	bl	1100 <__do_init_array_aux>
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    32ce:	2003      	movs	r0, #3
    32d0:	f7ff ff08 	bl	30e4 <z_sys_init_run_level>
	z_init_static_threads();
    32d4:	f000 f88c 	bl	33f0 <z_init_static_threads>
	main();
    32d8:	f7fd f89e 	bl	418 <main>
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    32dc:	4a03      	ldr	r2, [pc, #12]	; (32ec <bg_thread_main+0x38>)
    32de:	7b13      	ldrb	r3, [r2, #12]
    32e0:	f023 0301 	bic.w	r3, r3, #1
    32e4:	7313      	strb	r3, [r2, #12]
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    32e6:	bd08      	pop	{r3, pc}
    32e8:	2000094d 	.word	0x2000094d
    32ec:	20000160 	.word	0x20000160

000032f0 <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    32f0:	b500      	push	{lr}
    32f2:	b0a1      	sub	sp, #132	; 0x84
 *
 * @return N/A
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    32f4:	4b1a      	ldr	r3, [pc, #104]	; (3360 <z_cstart+0x70>)
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    32f6:	f383 8808 	msr	MSP, r3
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    32fa:	4c1a      	ldr	r4, [pc, #104]	; (3364 <z_cstart+0x74>)
    32fc:	6963      	ldr	r3, [r4, #20]
    32fe:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    3302:	6163      	str	r3, [r4, #20]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    3304:	23e0      	movs	r3, #224	; 0xe0
    3306:	f884 3022 	strb.w	r3, [r4, #34]	; 0x22
    330a:	2500      	movs	r5, #0
    330c:	77e5      	strb	r5, [r4, #31]
    330e:	7625      	strb	r5, [r4, #24]
    3310:	7665      	strb	r5, [r4, #25]
    3312:	76a5      	strb	r5, [r4, #26]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    3314:	6a63      	ldr	r3, [r4, #36]	; 0x24
    3316:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    331a:	6263      	str	r3, [r4, #36]	; 0x24

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    331c:	f7fe fd62 	bl	1de4 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    3320:	f7fe fbe4 	bl	1aec <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    3324:	f04f 33ff 	mov.w	r3, #4294967295
    3328:	62a3      	str	r3, [r4, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    332a:	62e3      	str	r3, [r4, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    332c:	f7fe fe14 	bl	1f58 <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    3330:	f7fe fdd8 	bl	1ee4 <z_arm_configure_static_mpu_regions>
 *
 * The memory of the dummy thread can be completely uninitialized.
 */
static inline void z_dummy_thread_init(struct k_thread *dummy_thread)
{
	dummy_thread->base.thread_state = _THREAD_DUMMY;
    3334:	2401      	movs	r4, #1
    3336:	f88d 400d 	strb.w	r4, [sp, #13]
#ifdef CONFIG_SCHED_CPU_MASK
	dummy_thread->base.cpu_mask = -1;
#endif
	dummy_thread->base.user_options = K_ESSENTIAL;
    333a:	f88d 400c 	strb.w	r4, [sp, #12]
#ifdef CONFIG_THREAD_STACK_INFO
	dummy_thread->stack_info.start = 0U;
    333e:	9519      	str	r5, [sp, #100]	; 0x64
	dummy_thread->stack_info.size = 0U;
    3340:	951a      	str	r5, [sp, #104]	; 0x68
#endif
#ifdef CONFIG_USERSPACE
	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
#endif

	_current_cpu->current = dummy_thread;
    3342:	4b09      	ldr	r3, [pc, #36]	; (3368 <z_cstart+0x78>)
    3344:	f8c3 d008 	str.w	sp, [r3, #8]
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    3348:	f7ff fec0 	bl	30cc <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    334c:	4628      	mov	r0, r5
    334e:	f7ff fec9 	bl	30e4 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    3352:	4620      	mov	r0, r4
    3354:	f7ff fec6 	bl	30e4 <z_sys_init_run_level>
	timing_init();
	timing_start();
#endif

#ifdef CONFIG_MULTITHREADING
	switch_to_main_thread(prepare_multithreading());
    3358:	f7ff ff4a 	bl	31f0 <prepare_multithreading>
    335c:	f7ff ff94 	bl	3288 <switch_to_main_thread>
    3360:	20001698 	.word	0x20001698
    3364:	e000ed00 	.word	0xe000ed00
    3368:	200008e4 	.word	0x200008e4

0000336c <schedule_new_thread>:
#endif
#endif

#ifdef CONFIG_MULTITHREADING
static void schedule_new_thread(struct k_thread *thread, k_timeout_t delay)
{
    336c:	b538      	push	{r3, r4, r5, lr}
    336e:	4614      	mov	r4, r2
    3370:	461d      	mov	r5, r3
#ifdef CONFIG_SYS_CLOCK_EXISTS
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3372:	ea54 0305 	orrs.w	r3, r4, r5
    3376:	d102      	bne.n	337e <schedule_new_thread+0x12>
	z_impl_k_thread_start(thread);
    3378:	f001 ff23 	bl	51c2 <z_impl_k_thread_start>
	}
#else
	ARG_UNUSED(delay);
	k_thread_start(thread);
#endif
}
    337c:	bd38      	pop	{r3, r4, r5, pc}

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    337e:	462b      	mov	r3, r5
    3380:	4902      	ldr	r1, [pc, #8]	; (338c <schedule_new_thread+0x20>)
    3382:	3018      	adds	r0, #24
    3384:	f000 ff7a 	bl	427c <z_add_timeout>
    3388:	e7f8      	b.n	337c <schedule_new_thread+0x10>
    338a:	bf00      	nop
    338c:	00005451 	.word	0x00005451

00003390 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    3390:	b5f0      	push	{r4, r5, r6, r7, lr}
    3392:	b085      	sub	sp, #20
    3394:	4604      	mov	r4, r0
    3396:	460e      	mov	r6, r1
    3398:	4615      	mov	r5, r2
    339a:	461f      	mov	r7, r3
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    339c:	f100 0358 	add.w	r3, r0, #88	; 0x58
	list->head = (sys_dnode_t *)list;
    33a0:	6583      	str	r3, [r0, #88]	; 0x58
	list->tail = (sys_dnode_t *)list;
    33a2:	65c3      	str	r3, [r0, #92]	; 0x5c
	k_object_access_grant(new_thread, new_thread);
#endif
	z_waitq_init(&new_thread->join_queue);

	/* Initialize various struct k_thread members */
	z_init_thread_base(&new_thread->base, prio, _THREAD_PRESTART, options);
    33a4:	9b0e      	ldr	r3, [sp, #56]	; 0x38
    33a6:	2204      	movs	r2, #4
    33a8:	990d      	ldr	r1, [sp, #52]	; 0x34
    33aa:	f001 ff0e 	bl	51ca <z_init_thread_base>
	stack_ptr = setup_thread_stack(new_thread, stack, stack_size);
    33ae:	462a      	mov	r2, r5
    33b0:	4631      	mov	r1, r6
    33b2:	4620      	mov	r0, r4
    33b4:	f001 fef3 	bl	519e <setup_thread_stack>
    33b8:	4605      	mov	r5, r0
	 */
	__ASSERT_NO_MSG(arch_mem_coherent(new_thread));
	__ASSERT_NO_MSG(!arch_mem_coherent(stack));
#endif

	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    33ba:	9b0c      	ldr	r3, [sp, #48]	; 0x30
    33bc:	9302      	str	r3, [sp, #8]
    33be:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
    33c0:	9301      	str	r3, [sp, #4]
    33c2:	9b0a      	ldr	r3, [sp, #40]	; 0x28
    33c4:	9300      	str	r3, [sp, #0]
    33c6:	463b      	mov	r3, r7
    33c8:	4602      	mov	r2, r0
    33ca:	4631      	mov	r1, r6
    33cc:	4620      	mov	r0, r4
    33ce:	f7fe fb5d 	bl	1a8c <arch_new_thread>

	/* static threads overwrite it afterwards with real value */
	new_thread->init_data = NULL;
    33d2:	2300      	movs	r3, #0
    33d4:	6563      	str	r3, [r4, #84]	; 0x54
#ifdef CONFIG_SCHED_CPU_MASK
	new_thread->base.cpu_mask = -1;
#endif
#ifdef CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN
	/* _current may be null if the dummy thread is not used */
	if (!_current) {
    33d6:	4b05      	ldr	r3, [pc, #20]	; (33ec <z_setup_new_thread+0x5c>)
    33d8:	689b      	ldr	r3, [r3, #8]
    33da:	b123      	cbz	r3, 33e6 <z_setup_new_thread+0x56>
	}
#endif
#ifdef CONFIG_SCHED_DEADLINE
	new_thread->base.prio_deadline = 0;
#endif
	new_thread->resource_pool = _current->resource_pool;
    33dc:	6f1b      	ldr	r3, [r3, #112]	; 0x70
    33de:	6723      	str	r3, [r4, #112]	; 0x70
#ifdef CONFIG_THREAD_RUNTIME_STATS
	memset(&new_thread->rt_stats, 0, sizeof(new_thread->rt_stats));
#endif

	return stack_ptr;
}
    33e0:	4628      	mov	r0, r5
    33e2:	b005      	add	sp, #20
    33e4:	bdf0      	pop	{r4, r5, r6, r7, pc}
		new_thread->resource_pool = NULL;
    33e6:	6723      	str	r3, [r4, #112]	; 0x70
		return stack_ptr;
    33e8:	e7fa      	b.n	33e0 <z_setup_new_thread+0x50>
    33ea:	bf00      	nop
    33ec:	200008e4 	.word	0x200008e4

000033f0 <z_init_static_threads>:
	}
}
#endif /* CONFIG_USERSPACE */

void z_init_static_threads(void)
{
    33f0:	e92d 4370 	stmdb	sp!, {r4, r5, r6, r8, r9, lr}
    33f4:	b086      	sub	sp, #24
	_FOREACH_STATIC_THREAD(thread_data) {
    33f6:	4c23      	ldr	r4, [pc, #140]	; (3484 <z_init_static_threads+0x94>)
    33f8:	4b23      	ldr	r3, [pc, #140]	; (3488 <z_init_static_threads+0x98>)
    33fa:	429c      	cmp	r4, r3
    33fc:	d215      	bcs.n	342a <z_init_static_threads+0x3a>
		z_setup_new_thread(
    33fe:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    3400:	9305      	str	r3, [sp, #20]
    3402:	6a23      	ldr	r3, [r4, #32]
    3404:	9304      	str	r3, [sp, #16]
    3406:	69e3      	ldr	r3, [r4, #28]
    3408:	9303      	str	r3, [sp, #12]
    340a:	69a3      	ldr	r3, [r4, #24]
    340c:	9302      	str	r3, [sp, #8]
    340e:	6963      	ldr	r3, [r4, #20]
    3410:	9301      	str	r3, [sp, #4]
    3412:	6923      	ldr	r3, [r4, #16]
    3414:	9300      	str	r3, [sp, #0]
    3416:	68e3      	ldr	r3, [r4, #12]
    3418:	68a2      	ldr	r2, [r4, #8]
    341a:	6861      	ldr	r1, [r4, #4]
    341c:	6820      	ldr	r0, [r4, #0]
    341e:	f7ff ffb7 	bl	3390 <z_setup_new_thread>
			thread_data->init_p3,
			thread_data->init_prio,
			thread_data->init_options,
			thread_data->init_name);

		thread_data->init_thread->init_data = thread_data;
    3422:	6823      	ldr	r3, [r4, #0]
    3424:	655c      	str	r4, [r3, #84]	; 0x54
	_FOREACH_STATIC_THREAD(thread_data) {
    3426:	3430      	adds	r4, #48	; 0x30
    3428:	e7e6      	b.n	33f8 <z_init_static_threads+0x8>
	 * until they are all started.
	 *
	 * Note that static threads defined using the legacy API have a
	 * delay of K_FOREVER.
	 */
	k_sched_lock();
    342a:	f000 fb39 	bl	3aa0 <k_sched_lock>
	_FOREACH_STATIC_THREAD(thread_data) {
    342e:	4c15      	ldr	r4, [pc, #84]	; (3484 <z_init_static_threads+0x94>)
    3430:	e01b      	b.n	346a <z_init_static_threads+0x7a>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
			schedule_new_thread(thread_data->init_thread,
    3432:	6826      	ldr	r6, [r4, #0]
					    K_MSEC(thread_data->init_delay));
    3434:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    3438:	ea4f 79e3 	mov.w	r9, r3, asr #31
		} else {
			return (t * to_hz + off) / from_hz;
    343c:	ea4f 31c9 	mov.w	r1, r9, lsl #15
    3440:	ea41 4153 	orr.w	r1, r1, r3, lsr #17
    3444:	03d8      	lsls	r0, r3, #15
    3446:	f240 35e7 	movw	r5, #999	; 0x3e7
    344a:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    344e:	2300      	movs	r3, #0
    3450:	1940      	adds	r0, r0, r5
    3452:	f04f 0500 	mov.w	r5, #0
    3456:	eb45 0101 	adc.w	r1, r5, r1
    345a:	f7fc fe51 	bl	100 <__aeabi_uldivmod>
    345e:	4602      	mov	r2, r0
    3460:	460b      	mov	r3, r1
			schedule_new_thread(thread_data->init_thread,
    3462:	4630      	mov	r0, r6
    3464:	f7ff ff82 	bl	336c <schedule_new_thread>
	_FOREACH_STATIC_THREAD(thread_data) {
    3468:	3430      	adds	r4, #48	; 0x30
    346a:	4b07      	ldr	r3, [pc, #28]	; (3488 <z_init_static_threads+0x98>)
    346c:	429c      	cmp	r4, r3
    346e:	d204      	bcs.n	347a <z_init_static_threads+0x8a>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    3470:	6a63      	ldr	r3, [r4, #36]	; 0x24
    3472:	f1b3 3fff 	cmp.w	r3, #4294967295
    3476:	d0f7      	beq.n	3468 <z_init_static_threads+0x78>
    3478:	e7db      	b.n	3432 <z_init_static_threads+0x42>
		}
	}
	k_sched_unlock();
    347a:	f000 fbc1 	bl	3c00 <k_sched_unlock>
}
    347e:	b006      	add	sp, #24
    3480:	e8bd 8370 	ldmia.w	sp!, {r4, r5, r6, r8, r9, pc}
    3484:	200000a8 	.word	0x200000a8
    3488:	200000a8 	.word	0x200000a8

0000348c <pm_save_idle>:
 *
 * Sets the kernel data structure idle field to either a positive value or
 * K_FOREVER.
 */
static void pm_save_idle(void)
{
    348c:	b508      	push	{r3, lr}
#ifdef CONFIG_PM
	int32_t ticks = z_get_next_timeout_expiry();
    348e:	f002 f8d1 	bl	5634 <z_get_next_timeout_expiry>
	_kernel.idle = ticks;
    3492:	4b04      	ldr	r3, [pc, #16]	; (34a4 <pm_save_idle+0x18>)
    3494:	6218      	str	r0, [r3, #32]
	 * before exiting. This is because the kernel does not do its own idle
	 * processing in those cases i.e. skips k_cpu_idle(). The kernel's
	 * idle processing re-enables interrupts which is essential for
	 * the kernel's scheduling logic.
	 */
	if (pm_system_suspend(ticks) == PM_STATE_ACTIVE) {
    3496:	f7fd fe91 	bl	11bc <pm_system_suspend>
    349a:	b100      	cbz	r0, 349e <pm_save_idle+0x12>
		k_cpu_idle();
	}
#endif
}
    349c:	bd08      	pop	{r3, pc}
	arch_cpu_idle();
    349e:	f7fe fb2b 	bl	1af8 <arch_cpu_idle>
    34a2:	e7fb      	b.n	349c <pm_save_idle+0x10>
    34a4:	200008e4 	.word	0x200008e4

000034a8 <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
    34a8:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    34ac:	b083      	sub	sp, #12
    34ae:	4604      	mov	r4, r0
    34b0:	461d      	mov	r5, r3
    34b2:	f04f 0320 	mov.w	r3, #32
    34b6:	f3ef 8711 	mrs	r7, BASEPRI
    34ba:	f383 8811 	msr	BASEPRI, r3
    34be:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, lock, mutex, timeout);

	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    34c2:	68c1      	ldr	r1, [r0, #12]
    34c4:	b999      	cbnz	r1, 34ee <z_impl_k_mutex_lock+0x46>

		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
					_current->base.prio :
    34c6:	2900      	cmp	r1, #0
    34c8:	d14f      	bne.n	356a <z_impl_k_mutex_lock+0xc2>
    34ca:	4b3a      	ldr	r3, [pc, #232]	; (35b4 <z_impl_k_mutex_lock+0x10c>)
    34cc:	689b      	ldr	r3, [r3, #8]
    34ce:	f993 300e 	ldrsb.w	r3, [r3, #14]
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
    34d2:	6123      	str	r3, [r4, #16]
					mutex->owner_orig_prio;

		mutex->lock_count++;
    34d4:	3101      	adds	r1, #1
    34d6:	60e1      	str	r1, [r4, #12]
		mutex->owner = _current;
    34d8:	4b36      	ldr	r3, [pc, #216]	; (35b4 <z_impl_k_mutex_lock+0x10c>)
    34da:	689b      	ldr	r3, [r3, #8]
    34dc:	60a3      	str	r3, [r4, #8]
	__asm__ volatile(
    34de:	f387 8811 	msr	BASEPRI, r7
    34e2:	f3bf 8f6f 	isb	sy

		k_spin_unlock(&lock, key);

		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, 0);

		return 0;
    34e6:	2000      	movs	r0, #0
	}

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EAGAIN);

	return -EAGAIN;
}
    34e8:	b003      	add	sp, #12
    34ea:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    34ee:	4616      	mov	r6, r2
	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    34f0:	6882      	ldr	r2, [r0, #8]
    34f2:	4b30      	ldr	r3, [pc, #192]	; (35b4 <z_impl_k_mutex_lock+0x10c>)
    34f4:	689b      	ldr	r3, [r3, #8]
    34f6:	429a      	cmp	r2, r3
    34f8:	d0e5      	beq.n	34c6 <z_impl_k_mutex_lock+0x1e>
	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
    34fa:	ea55 0106 	orrs.w	r1, r5, r6
    34fe:	bf0c      	ite	eq
    3500:	f04f 0801 	moveq.w	r8, #1
    3504:	f04f 0800 	movne.w	r8, #0
    3508:	d031      	beq.n	356e <z_impl_k_mutex_lock+0xc6>
					    mutex->owner->base.prio);
    350a:	f992 900e 	ldrsb.w	r9, [r2, #14]
	new_prio = new_prio_for_inheritance(_current->base.prio,
    350e:	4649      	mov	r1, r9
    3510:	f993 000e 	ldrsb.w	r0, [r3, #14]
    3514:	f001 fe98 	bl	5248 <new_prio_for_inheritance>
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
    3518:	4581      	cmp	r9, r0
    351a:	dc2f      	bgt.n	357c <z_impl_k_mutex_lock+0xd4>
	bool resched = false;
    351c:	f04f 0900 	mov.w	r9, #0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
    3520:	9600      	str	r6, [sp, #0]
    3522:	9501      	str	r5, [sp, #4]
    3524:	4622      	mov	r2, r4
    3526:	4639      	mov	r1, r7
    3528:	4823      	ldr	r0, [pc, #140]	; (35b8 <z_impl_k_mutex_lock+0x110>)
    352a:	f000 fb13 	bl	3b54 <z_pend_curr>
	if (got_mutex == 0) {
    352e:	2800      	cmp	r0, #0
    3530:	d0da      	beq.n	34e8 <z_impl_k_mutex_lock+0x40>
	__asm__ volatile(
    3532:	f04f 0320 	mov.w	r3, #32
    3536:	f3ef 8511 	mrs	r5, BASEPRI
    353a:	f383 8811 	msr	BASEPRI, r3
    353e:	f3bf 8f6f 	isb	sy
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    3542:	6823      	ldr	r3, [r4, #0]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3544:	429c      	cmp	r4, r3
    3546:	d01f      	beq.n	3588 <z_impl_k_mutex_lock+0xe0>
		new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    3548:	b1f3      	cbz	r3, 3588 <z_impl_k_mutex_lock+0xe0>
    354a:	6921      	ldr	r1, [r4, #16]
    354c:	f993 000e 	ldrsb.w	r0, [r3, #14]
    3550:	f001 fe7a 	bl	5248 <new_prio_for_inheritance>
    3554:	4601      	mov	r1, r0
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    3556:	4620      	mov	r0, r4
    3558:	f001 fe81 	bl	525e <adjust_owner_prio>
    355c:	b9b0      	cbnz	r0, 358c <z_impl_k_mutex_lock+0xe4>
    355e:	f1b9 0f00 	cmp.w	r9, #0
    3562:	d015      	beq.n	3590 <z_impl_k_mutex_lock+0xe8>
    3564:	f04f 0801 	mov.w	r8, #1
    3568:	e012      	b.n	3590 <z_impl_k_mutex_lock+0xe8>
					_current->base.prio :
    356a:	6923      	ldr	r3, [r4, #16]
    356c:	e7b1      	b.n	34d2 <z_impl_k_mutex_lock+0x2a>
	__asm__ volatile(
    356e:	f387 8811 	msr	BASEPRI, r7
    3572:	f3bf 8f6f 	isb	sy
		return -EBUSY;
    3576:	f06f 000f 	mvn.w	r0, #15
    357a:	e7b5      	b.n	34e8 <z_impl_k_mutex_lock+0x40>
		resched = adjust_owner_prio(mutex, new_prio);
    357c:	4601      	mov	r1, r0
    357e:	4620      	mov	r0, r4
    3580:	f001 fe6d 	bl	525e <adjust_owner_prio>
    3584:	4681      	mov	r9, r0
    3586:	e7cb      	b.n	3520 <z_impl_k_mutex_lock+0x78>
		new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    3588:	6921      	ldr	r1, [r4, #16]
    358a:	e7e4      	b.n	3556 <z_impl_k_mutex_lock+0xae>
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    358c:	f04f 0801 	mov.w	r8, #1
	if (resched) {
    3590:	f1b8 0f00 	cmp.w	r8, #0
    3594:	d106      	bne.n	35a4 <z_impl_k_mutex_lock+0xfc>
    3596:	f385 8811 	msr	BASEPRI, r5
    359a:	f3bf 8f6f 	isb	sy
	return -EAGAIN;
    359e:	f06f 000a 	mvn.w	r0, #10
    35a2:	e7a1      	b.n	34e8 <z_impl_k_mutex_lock+0x40>
		z_reschedule(&lock, key);
    35a4:	4629      	mov	r1, r5
    35a6:	4804      	ldr	r0, [pc, #16]	; (35b8 <z_impl_k_mutex_lock+0x110>)
    35a8:	f000 fa5e 	bl	3a68 <z_reschedule>
	return -EAGAIN;
    35ac:	f06f 000a 	mvn.w	r0, #10
    35b0:	e79a      	b.n	34e8 <z_impl_k_mutex_lock+0x40>
    35b2:	bf00      	nop
    35b4:	200008e4 	.word	0x200008e4
    35b8:	20000914 	.word	0x20000914

000035bc <z_impl_k_mutex_unlock>:

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, unlock, mutex);

	CHECKIF(mutex->owner == NULL) {
    35bc:	6882      	ldr	r2, [r0, #8]
    35be:	2a00      	cmp	r2, #0
    35c0:	d034      	beq.n	362c <z_impl_k_mutex_unlock+0x70>
{
    35c2:	b538      	push	{r3, r4, r5, lr}
    35c4:	4604      	mov	r4, r0
		return -EINVAL;
	}
	/*
	 * The current thread does not own the mutex.
	 */
	CHECKIF(mutex->owner != _current) {
    35c6:	4b1c      	ldr	r3, [pc, #112]	; (3638 <z_impl_k_mutex_unlock+0x7c>)
    35c8:	689b      	ldr	r3, [r3, #8]
    35ca:	429a      	cmp	r2, r3
    35cc:	d131      	bne.n	3632 <z_impl_k_mutex_unlock+0x76>
static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1U, "");

	--_current->base.sched_locked;
    35ce:	7bda      	ldrb	r2, [r3, #15]
    35d0:	3a01      	subs	r2, #1
    35d2:	73da      	strb	r2, [r3, #15]

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count > 1U) {
    35d4:	68c3      	ldr	r3, [r0, #12]
    35d6:	2b01      	cmp	r3, #1
    35d8:	d905      	bls.n	35e6 <z_impl_k_mutex_unlock+0x2a>
		mutex->lock_count--;
    35da:	3b01      	subs	r3, #1
    35dc:	60c3      	str	r3, [r0, #12]


k_mutex_unlock_return:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, unlock, mutex, 0);

	k_sched_unlock();
    35de:	f000 fb0f 	bl	3c00 <k_sched_unlock>

	return 0;
    35e2:	2000      	movs	r0, #0
}
    35e4:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    35e6:	f04f 0320 	mov.w	r3, #32
    35ea:	f3ef 8511 	mrs	r5, BASEPRI
    35ee:	f383 8811 	msr	BASEPRI, r3
    35f2:	f3bf 8f6f 	isb	sy
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
    35f6:	6901      	ldr	r1, [r0, #16]
    35f8:	f001 fe31 	bl	525e <adjust_owner_prio>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
    35fc:	4620      	mov	r0, r4
    35fe:	f001 ff82 	bl	5506 <z_unpend_first_thread>
	mutex->owner = new_owner;
    3602:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
    3604:	b158      	cbz	r0, 361e <z_impl_k_mutex_unlock+0x62>
		mutex->owner_orig_prio = new_owner->base.prio;
    3606:	f990 300e 	ldrsb.w	r3, [r0, #14]
    360a:	6123      	str	r3, [r4, #16]
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    360c:	2300      	movs	r3, #0
    360e:	6783      	str	r3, [r0, #120]	; 0x78
		z_ready_thread(new_owner);
    3610:	f001 ff02 	bl	5418 <z_ready_thread>
		z_reschedule(&lock, key);
    3614:	4629      	mov	r1, r5
    3616:	4809      	ldr	r0, [pc, #36]	; (363c <z_impl_k_mutex_unlock+0x80>)
    3618:	f000 fa26 	bl	3a68 <z_reschedule>
    361c:	e7df      	b.n	35de <z_impl_k_mutex_unlock+0x22>
		mutex->lock_count = 0U;
    361e:	2300      	movs	r3, #0
    3620:	60e3      	str	r3, [r4, #12]
	__asm__ volatile(
    3622:	f385 8811 	msr	BASEPRI, r5
    3626:	f3bf 8f6f 	isb	sy
    362a:	e7d8      	b.n	35de <z_impl_k_mutex_unlock+0x22>
		return -EINVAL;
    362c:	f06f 0015 	mvn.w	r0, #21
}
    3630:	4770      	bx	lr
		return -EPERM;
    3632:	f04f 30ff 	mov.w	r0, #4294967295
    3636:	e7d5      	b.n	35e4 <z_impl_k_mutex_unlock+0x28>
    3638:	200008e4 	.word	0x200008e4
    363c:	20000914 	.word	0x20000914

00003640 <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    3640:	b538      	push	{r3, r4, r5, lr}
    3642:	4604      	mov	r4, r0
	__asm__ volatile(
    3644:	f04f 0320 	mov.w	r3, #32
    3648:	f3ef 8511 	mrs	r5, BASEPRI
    364c:	f383 8811 	msr	BASEPRI, r3
    3650:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    3654:	f001 ff57 	bl	5506 <z_unpend_first_thread>

	if (thread != NULL) {
    3658:	b140      	cbz	r0, 366c <z_impl_k_sem_give+0x2c>
    365a:	2200      	movs	r2, #0
    365c:	6782      	str	r2, [r0, #120]	; 0x78
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    365e:	f001 fedb 	bl	5418 <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    3662:	4629      	mov	r1, r5
    3664:	4806      	ldr	r0, [pc, #24]	; (3680 <z_impl_k_sem_give+0x40>)
    3666:	f000 f9ff 	bl	3a68 <z_reschedule>

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    366a:	bd38      	pop	{r3, r4, r5, pc}
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    366c:	68a3      	ldr	r3, [r4, #8]
    366e:	68e2      	ldr	r2, [r4, #12]
    3670:	4293      	cmp	r3, r2
    3672:	d003      	beq.n	367c <z_impl_k_sem_give+0x3c>
    3674:	2201      	movs	r2, #1
    3676:	4413      	add	r3, r2
    3678:	60a3      	str	r3, [r4, #8]
}
    367a:	e7f2      	b.n	3662 <z_impl_k_sem_give+0x22>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    367c:	2200      	movs	r2, #0
    367e:	e7fa      	b.n	3676 <z_impl_k_sem_give+0x36>
    3680:	20000918 	.word	0x20000918

00003684 <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    3684:	b530      	push	{r4, r5, lr}
    3686:	b083      	sub	sp, #12
    3688:	461d      	mov	r5, r3
    368a:	f04f 0320 	mov.w	r3, #32
    368e:	f3ef 8111 	mrs	r1, BASEPRI
    3692:	f383 8811 	msr	BASEPRI, r3
    3696:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    369a:	6883      	ldr	r3, [r0, #8]
    369c:	b143      	cbz	r3, 36b0 <z_impl_k_sem_take+0x2c>
		sem->count--;
    369e:	3b01      	subs	r3, #1
    36a0:	6083      	str	r3, [r0, #8]
	__asm__ volatile(
    36a2:	f381 8811 	msr	BASEPRI, r1
    36a6:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    36aa:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    36ac:	b003      	add	sp, #12
    36ae:	bd30      	pop	{r4, r5, pc}
    36b0:	4614      	mov	r4, r2
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    36b2:	ea54 0305 	orrs.w	r3, r4, r5
    36b6:	d006      	beq.n	36c6 <z_impl_k_sem_take+0x42>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    36b8:	e9cd 4500 	strd	r4, r5, [sp]
    36bc:	4602      	mov	r2, r0
    36be:	4805      	ldr	r0, [pc, #20]	; (36d4 <z_impl_k_sem_take+0x50>)
    36c0:	f000 fa48 	bl	3b54 <z_pend_curr>
	return ret;
    36c4:	e7f2      	b.n	36ac <z_impl_k_sem_take+0x28>
    36c6:	f381 8811 	msr	BASEPRI, r1
    36ca:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    36ce:	f06f 000f 	mvn.w	r0, #15
    36d2:	e7eb      	b.n	36ac <z_impl_k_sem_take+0x28>
    36d4:	20000918 	.word	0x20000918

000036d8 <submit_to_queue_locked>:
 * @retval -EINVAL if no queue is provided
 * @retval -ENODEV if the queue is not started
 */
static int submit_to_queue_locked(struct k_work *work,
				  struct k_work_q **queuep)
{
    36d8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    36da:	460d      	mov	r5, r1
	return (*flagp & BIT(bit)) != 0U;
    36dc:	68c3      	ldr	r3, [r0, #12]
	int ret = 0;

	if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
    36de:	f013 0f02 	tst.w	r3, #2
    36e2:	d15b      	bne.n	379c <submit_to_queue_locked+0xc4>
    36e4:	4604      	mov	r4, r0
		/* Disallowed */
		ret = -EBUSY;
	} else if (!flag_test(&work->flags, K_WORK_QUEUED_BIT)) {
    36e6:	f013 0f04 	tst.w	r3, #4
    36ea:	d15c      	bne.n	37a6 <submit_to_queue_locked+0xce>
		/* Not currently queued */
		ret = 1;

		/* If no queue specified resubmit to last queue.
		 */
		if (*queuep == NULL) {
    36ec:	680b      	ldr	r3, [r1, #0]
    36ee:	2b00      	cmp	r3, #0
    36f0:	d037      	beq.n	3762 <submit_to_queue_locked+0x8a>
	return (*flagp & BIT(bit)) != 0U;
    36f2:	68e3      	ldr	r3, [r4, #12]

		/* If the work is currently running we have to use the
		 * queue it's running on to prevent handler
		 * re-entrancy.
		 */
		if (flag_test(&work->flags, K_WORK_RUNNING_BIT)) {
    36f4:	f013 0f01 	tst.w	r3, #1
    36f8:	d036      	beq.n	3768 <submit_to_queue_locked+0x90>
			__ASSERT_NO_MSG(work->queue != NULL);
			*queuep = work->queue;
    36fa:	68a3      	ldr	r3, [r4, #8]
    36fc:	602b      	str	r3, [r5, #0]
			ret = 2;
    36fe:	2702      	movs	r7, #2
		}

		int rc = queue_submit_locked(*queuep, work);
    3700:	682e      	ldr	r6, [r5, #0]
	if (queue == NULL) {
    3702:	2e00      	cmp	r6, #0
    3704:	d03e      	beq.n	3784 <submit_to_queue_locked+0xac>
	bool chained = (_current == &queue->thread) && !k_is_in_isr();
    3706:	4b29      	ldr	r3, [pc, #164]	; (37ac <submit_to_queue_locked+0xd4>)
    3708:	689b      	ldr	r3, [r3, #8]
    370a:	42b3      	cmp	r3, r6
    370c:	d02e      	beq.n	376c <submit_to_queue_locked+0x94>
    370e:	2300      	movs	r3, #0
    3710:	461a      	mov	r2, r3
	return (*flagp & BIT(bit)) != 0U;
    3712:	f8d6 3098 	ldr.w	r3, [r6, #152]	; 0x98
    3716:	f3c3 0180 	ubfx	r1, r3, #2, #1
    371a:	f3c3 00c0 	ubfx	r0, r3, #3, #1
	if (!flag_test(&queue->flags, K_WORK_QUEUE_STARTED_BIT)) {
    371e:	f013 0f01 	tst.w	r3, #1
    3722:	d032      	beq.n	378a <submit_to_queue_locked+0xb2>
	} else if (draining && !chained) {
    3724:	b101      	cbz	r1, 3728 <submit_to_queue_locked+0x50>
    3726:	b39a      	cbz	r2, 3790 <submit_to_queue_locked+0xb8>
	} else if (plugged && !draining) {
    3728:	b100      	cbz	r0, 372c <submit_to_queue_locked+0x54>
    372a:	b3a1      	cbz	r1, 3796 <submit_to_queue_locked+0xbe>
	parent->next = child;
    372c:	2300      	movs	r3, #0
    372e:	6023      	str	r3, [r4, #0]
	return list->tail;
    3730:	f8d6 3084 	ldr.w	r3, [r6, #132]	; 0x84
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
				    sys_snode_t *node);

Z_GENLIST_APPEND(slist, snode)
    3734:	b30b      	cbz	r3, 377a <submit_to_queue_locked+0xa2>
	parent->next = child;
    3736:	601c      	str	r4, [r3, #0]
	list->tail = node;
    3738:	f8c6 4084 	str.w	r4, [r6, #132]	; 0x84
		rv = z_sched_wake(&queue->notifyq, 0, NULL);
    373c:	2200      	movs	r2, #0
    373e:	4611      	mov	r1, r2
    3740:	f106 0088 	add.w	r0, r6, #136	; 0x88
    3744:	f001 ff0a 	bl	555c <z_sched_wake>
		ret = 1;
    3748:	2001      	movs	r0, #1

		if (rc < 0) {
    374a:	2800      	cmp	r0, #0
    374c:	db06      	blt.n	375c <submit_to_queue_locked+0x84>
	*flagp |= BIT(bit);
    374e:	68e3      	ldr	r3, [r4, #12]
    3750:	f043 0304 	orr.w	r3, r3, #4
    3754:	60e3      	str	r3, [r4, #12]
			ret = rc;
		} else {
			flag_set(&work->flags, K_WORK_QUEUED_BIT);
			work->queue = *queuep;
    3756:	682b      	ldr	r3, [r5, #0]
    3758:	60a3      	str	r3, [r4, #8]
    375a:	4638      	mov	r0, r7
		}
	} else {
		/* Already queued, do nothing. */
	}

	if (ret <= 0) {
    375c:	2800      	cmp	r0, #0
    375e:	dc21      	bgt.n	37a4 <submit_to_queue_locked+0xcc>
    3760:	e01e      	b.n	37a0 <submit_to_queue_locked+0xc8>
			*queuep = work->queue;
    3762:	6883      	ldr	r3, [r0, #8]
    3764:	600b      	str	r3, [r1, #0]
    3766:	e7c4      	b.n	36f2 <submit_to_queue_locked+0x1a>
		ret = 1;
    3768:	2701      	movs	r7, #1
    376a:	e7c9      	b.n	3700 <submit_to_queue_locked+0x28>
	bool chained = (_current == &queue->thread) && !k_is_in_isr();
    376c:	f001 fd20 	bl	51b0 <k_is_in_isr>
    3770:	b908      	cbnz	r0, 3776 <submit_to_queue_locked+0x9e>
    3772:	2301      	movs	r3, #1
    3774:	e7cc      	b.n	3710 <submit_to_queue_locked+0x38>
    3776:	2300      	movs	r3, #0
    3778:	e7ca      	b.n	3710 <submit_to_queue_locked+0x38>
    377a:	f8c6 4084 	str.w	r4, [r6, #132]	; 0x84
	list->head = node;
    377e:	f8c6 4080 	str.w	r4, [r6, #128]	; 0x80
}
    3782:	e7db      	b.n	373c <submit_to_queue_locked+0x64>
		return -EINVAL;
    3784:	f06f 0015 	mvn.w	r0, #21
    3788:	e7df      	b.n	374a <submit_to_queue_locked+0x72>
		ret = -ENODEV;
    378a:	f06f 0012 	mvn.w	r0, #18
    378e:	e7dc      	b.n	374a <submit_to_queue_locked+0x72>
		ret = -EBUSY;
    3790:	f06f 000f 	mvn.w	r0, #15
    3794:	e7d9      	b.n	374a <submit_to_queue_locked+0x72>
		ret = -EBUSY;
    3796:	f06f 000f 	mvn.w	r0, #15
    379a:	e7d6      	b.n	374a <submit_to_queue_locked+0x72>
		ret = -EBUSY;
    379c:	f06f 000f 	mvn.w	r0, #15
		*queuep = NULL;
    37a0:	2300      	movs	r3, #0
    37a2:	602b      	str	r3, [r5, #0]
	}

	return ret;
}
    37a4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	int ret = 0;
    37a6:	2000      	movs	r0, #0
    37a8:	e7fa      	b.n	37a0 <submit_to_queue_locked+0xc8>
    37aa:	bf00      	nop
    37ac:	200008e4 	.word	0x200008e4

000037b0 <finalize_cancel_locked>:
{
    37b0:	b570      	push	{r4, r5, r6, lr}
    37b2:	4605      	mov	r5, r0
	*flagp &= ~BIT(bit);
    37b4:	68c3      	ldr	r3, [r0, #12]
    37b6:	f023 0302 	bic.w	r3, r3, #2
    37ba:	60c3      	str	r3, [r0, #12]
	return list->head;
    37bc:	4b19      	ldr	r3, [pc, #100]	; (3824 <finalize_cancel_locked+0x74>)
    37be:	6818      	ldr	r0, [r3, #0]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&pending_cancels, wc, tmp, node) {
    37c0:	b1e8      	cbz	r0, 37fe <finalize_cancel_locked+0x4e>
    37c2:	4604      	mov	r4, r0
Z_GENLIST_PEEK_NEXT(slist, snode)
    37c4:	b100      	cbz	r0, 37c8 <finalize_cancel_locked+0x18>
	return node->next;
    37c6:	6804      	ldr	r4, [r0, #0]
    37c8:	2600      	movs	r6, #0
    37ca:	e01d      	b.n	3808 <finalize_cancel_locked+0x58>
 */
static inline void sys_slist_remove(sys_slist_t *list,
				    sys_snode_t *prev_node,
				    sys_snode_t *node);

Z_GENLIST_REMOVE(slist, snode)
    37cc:	b15e      	cbz	r6, 37e6 <finalize_cancel_locked+0x36>
	return node->next;
    37ce:	6803      	ldr	r3, [r0, #0]
	parent->next = child;
    37d0:	6033      	str	r3, [r6, #0]
	return list->tail;
    37d2:	4b14      	ldr	r3, [pc, #80]	; (3824 <finalize_cancel_locked+0x74>)
    37d4:	685b      	ldr	r3, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    37d6:	4298      	cmp	r0, r3
    37d8:	d00e      	beq.n	37f8 <finalize_cancel_locked+0x48>
	parent->next = child;
    37da:	2300      	movs	r3, #0
    37dc:	f840 3b08 	str.w	r3, [r0], #8
	z_impl_k_sem_give(sem);
    37e0:	f7ff ff2e 	bl	3640 <z_impl_k_sem_give>
}
    37e4:	e015      	b.n	3812 <finalize_cancel_locked+0x62>
	return node->next;
    37e6:	6802      	ldr	r2, [r0, #0]
	list->head = node;
    37e8:	4b0e      	ldr	r3, [pc, #56]	; (3824 <finalize_cancel_locked+0x74>)
    37ea:	601a      	str	r2, [r3, #0]
	return list->tail;
    37ec:	685b      	ldr	r3, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    37ee:	4298      	cmp	r0, r3
    37f0:	d1f3      	bne.n	37da <finalize_cancel_locked+0x2a>
	list->tail = node;
    37f2:	4b0c      	ldr	r3, [pc, #48]	; (3824 <finalize_cancel_locked+0x74>)
    37f4:	605a      	str	r2, [r3, #4]
}
    37f6:	e7f0      	b.n	37da <finalize_cancel_locked+0x2a>
	list->tail = node;
    37f8:	4b0a      	ldr	r3, [pc, #40]	; (3824 <finalize_cancel_locked+0x74>)
    37fa:	605e      	str	r6, [r3, #4]
}
    37fc:	e7ed      	b.n	37da <finalize_cancel_locked+0x2a>
    37fe:	4604      	mov	r4, r0
    3800:	e7e2      	b.n	37c8 <finalize_cancel_locked+0x18>
    3802:	4623      	mov	r3, r4
    3804:	4620      	mov	r0, r4
    3806:	461c      	mov	r4, r3
    3808:	b150      	cbz	r0, 3820 <finalize_cancel_locked+0x70>
		if (wc->work == work) {
    380a:	6843      	ldr	r3, [r0, #4]
    380c:	42ab      	cmp	r3, r5
    380e:	d0dd      	beq.n	37cc <finalize_cancel_locked+0x1c>
			prev = &wc->node;
    3810:	4606      	mov	r6, r0
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&pending_cancels, wc, tmp, node) {
    3812:	2c00      	cmp	r4, #0
    3814:	d0f5      	beq.n	3802 <finalize_cancel_locked+0x52>
    3816:	4623      	mov	r3, r4
Z_GENLIST_PEEK_NEXT(slist, snode)
    3818:	2c00      	cmp	r4, #0
    381a:	d0f3      	beq.n	3804 <finalize_cancel_locked+0x54>
	return node->next;
    381c:	6823      	ldr	r3, [r4, #0]
    381e:	e7f1      	b.n	3804 <finalize_cancel_locked+0x54>
}
    3820:	bd70      	pop	{r4, r5, r6, pc}
    3822:	bf00      	nop
    3824:	20000920 	.word	0x20000920

00003828 <work_queue_main>:
/* Loop executed by a work queue thread.
 *
 * @param workq_ptr pointer to the work queue structure
 */
static void work_queue_main(void *workq_ptr, void *p2, void *p3)
{
    3828:	b5f0      	push	{r4, r5, r6, r7, lr}
    382a:	b085      	sub	sp, #20
    382c:	4605      	mov	r5, r0
	struct k_work_q *queue = (struct k_work_q *)workq_ptr;
    382e:	e016      	b.n	385e <work_queue_main+0x36>
	return (*flagp & BIT(bit)) != 0U;
    3830:	f8d5 3098 	ldr.w	r3, [r5, #152]	; 0x98
	*flagp &= ~BIT(bit);
    3834:	f023 0204 	bic.w	r2, r3, #4
    3838:	f8c5 2098 	str.w	r2, [r5, #152]	; 0x98
			flag_set(&queue->flags, K_WORK_QUEUE_BUSY_BIT);
			work = CONTAINER_OF(node, struct k_work, node);
			flag_set(&work->flags, K_WORK_RUNNING_BIT);
			flag_clear(&work->flags, K_WORK_QUEUED_BIT);
			handler = work->handler;
		} else if (flag_test_and_clear(&queue->flags,
    383c:	f013 0f04 	tst.w	r3, #4
    3840:	d158      	bne.n	38f4 <work_queue_main+0xcc>
			 * the lock, and we didn't find work nor got asked to
			 * stop.  Just go to sleep: when something happens the
			 * work thread will be woken and we can check again.
			 */

			(void)z_sched_wait(&lock, key, &queue->notifyq,
    3842:	2300      	movs	r3, #0
    3844:	9302      	str	r3, [sp, #8]
    3846:	f04f 32ff 	mov.w	r2, #4294967295
    384a:	f04f 33ff 	mov.w	r3, #4294967295
    384e:	e9cd 2300 	strd	r2, r3, [sp]
    3852:	f105 0288 	add.w	r2, r5, #136	; 0x88
    3856:	4631      	mov	r1, r6
    3858:	482e      	ldr	r0, [pc, #184]	; (3914 <work_queue_main+0xec>)
    385a:	f000 fc9b 	bl	4194 <z_sched_wait>
	__asm__ volatile(
    385e:	f04f 0320 	mov.w	r3, #32
    3862:	f3ef 8611 	mrs	r6, BASEPRI
    3866:	f383 8811 	msr	BASEPRI, r3
    386a:	f3bf 8f6f 	isb	sy
	return list->head;
    386e:	f8d5 4080 	ldr.w	r4, [r5, #128]	; 0x80
Z_GENLIST_GET(slist, snode)
    3872:	2c00      	cmp	r4, #0
    3874:	d0dc      	beq.n	3830 <work_queue_main+0x8>
	return node->next;
    3876:	6823      	ldr	r3, [r4, #0]
	list->head = node;
    3878:	f8c5 3080 	str.w	r3, [r5, #128]	; 0x80
	return list->tail;
    387c:	f8d5 2084 	ldr.w	r2, [r5, #132]	; 0x84
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    3880:	4294      	cmp	r4, r2
    3882:	d034      	beq.n	38ee <work_queue_main+0xc6>
	*flagp |= BIT(bit);
    3884:	f8d5 3098 	ldr.w	r3, [r5, #152]	; 0x98
    3888:	f043 0302 	orr.w	r3, r3, #2
    388c:	f8c5 3098 	str.w	r3, [r5, #152]	; 0x98
    3890:	68e3      	ldr	r3, [r4, #12]
    3892:	f043 0301 	orr.w	r3, r3, #1
	*flagp &= ~BIT(bit);
    3896:	f023 0304 	bic.w	r3, r3, #4
    389a:	60e3      	str	r3, [r4, #12]
			handler = work->handler;
    389c:	6863      	ldr	r3, [r4, #4]
		if (work == NULL) {
    389e:	2c00      	cmp	r4, #0
    38a0:	d0cf      	beq.n	3842 <work_queue_main+0x1a>
	__asm__ volatile(
    38a2:	f386 8811 	msr	BASEPRI, r6
    38a6:	f3bf 8f6f 	isb	sy

		if (work != NULL) {
			bool yield;

			__ASSERT_NO_MSG(handler != NULL);
			handler(work);
    38aa:	4620      	mov	r0, r4
    38ac:	4798      	blx	r3
	__asm__ volatile(
    38ae:	f04f 0320 	mov.w	r3, #32
    38b2:	f3ef 8611 	mrs	r6, BASEPRI
    38b6:	f383 8811 	msr	BASEPRI, r3
    38ba:	f3bf 8f6f 	isb	sy
	*flagp &= ~BIT(bit);
    38be:	68e3      	ldr	r3, [r4, #12]
    38c0:	f023 0301 	bic.w	r3, r3, #1
    38c4:	60e3      	str	r3, [r4, #12]
			 * starving other threads.
			 */
			key = k_spin_lock(&lock);

			flag_clear(&work->flags, K_WORK_RUNNING_BIT);
			if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
    38c6:	f013 0f02 	tst.w	r3, #2
    38ca:	d11e      	bne.n	390a <work_queue_main+0xe2>
	*flagp &= ~BIT(bit);
    38cc:	f8d5 3098 	ldr.w	r3, [r5, #152]	; 0x98
    38d0:	f023 0302 	bic.w	r3, r3, #2
    38d4:	f8c5 3098 	str.w	r3, [r5, #152]	; 0x98
	return (*flagp & BIT(bit)) != 0U;
    38d8:	f3c3 2300 	ubfx	r3, r3, #8, #1
	__asm__ volatile(
    38dc:	f386 8811 	msr	BASEPRI, r6
    38e0:	f3bf 8f6f 	isb	sy
			k_spin_unlock(&lock, key);

			/* Optionally yield to prevent the work queue from
			 * starving other threads.
			 */
			if (yield) {
    38e4:	2b00      	cmp	r3, #0
    38e6:	d1ba      	bne.n	385e <work_queue_main+0x36>
	z_impl_k_yield();
    38e8:	f000 fb56 	bl	3f98 <z_impl_k_yield>
}
    38ec:	e7b7      	b.n	385e <work_queue_main+0x36>
	list->tail = node;
    38ee:	f8c5 3084 	str.w	r3, [r5, #132]	; 0x84
}
    38f2:	e7c7      	b.n	3884 <work_queue_main+0x5c>
			(void)z_sched_wake_all(&queue->drainq, 1, NULL);
    38f4:	f105 0790 	add.w	r7, r5, #144	; 0x90
static inline bool z_sched_wake_all(_wait_q_t *wait_q, int swap_retval,
				    void *swap_data)
{
	bool woken = false;

	while (z_sched_wake(wait_q, swap_retval, swap_data)) {
    38f8:	2200      	movs	r2, #0
    38fa:	2101      	movs	r1, #1
    38fc:	4638      	mov	r0, r7
    38fe:	f001 fe2d 	bl	555c <z_sched_wake>
    3902:	2800      	cmp	r0, #0
    3904:	d1f8      	bne.n	38f8 <work_queue_main+0xd0>
		k_work_handler_t handler = NULL;
    3906:	2300      	movs	r3, #0
    3908:	e7c9      	b.n	389e <work_queue_main+0x76>
				finalize_cancel_locked(work);
    390a:	4620      	mov	r0, r4
    390c:	f7ff ff50 	bl	37b0 <finalize_cancel_locked>
    3910:	e7dc      	b.n	38cc <work_queue_main+0xa4>
    3912:	bf00      	nop
    3914:	2000091c 	.word	0x2000091c

00003918 <k_work_submit>:
{
    3918:	b508      	push	{r3, lr}
    391a:	4601      	mov	r1, r0
	int ret = k_work_submit_to_queue(&k_sys_work_q, work);
    391c:	4801      	ldr	r0, [pc, #4]	; (3924 <k_work_submit+0xc>)
    391e:	f001 fcbf 	bl	52a0 <k_work_submit_to_queue>
}
    3922:	bd08      	pop	{r3, pc}
    3924:	200001e8 	.word	0x200001e8

00003928 <k_work_queue_start>:
void k_work_queue_start(struct k_work_q *queue,
			k_thread_stack_t *stack,
			size_t stack_size,
			int prio,
			const struct k_work_queue_config *cfg)
{
    3928:	b5f0      	push	{r4, r5, r6, r7, lr}
    392a:	b089      	sub	sp, #36	; 0x24
    392c:	4604      	mov	r4, r0
    392e:	9d0e      	ldr	r5, [sp, #56]	; 0x38
	list->head = NULL;
    3930:	2000      	movs	r0, #0
    3932:	f8c4 0080 	str.w	r0, [r4, #128]	; 0x80
	list->tail = NULL;
    3936:	f8c4 0084 	str.w	r0, [r4, #132]	; 0x84
    393a:	f104 0088 	add.w	r0, r4, #136	; 0x88
	list->head = (sys_dnode_t *)list;
    393e:	f8c4 0088 	str.w	r0, [r4, #136]	; 0x88
	list->tail = (sys_dnode_t *)list;
    3942:	f8c4 008c 	str.w	r0, [r4, #140]	; 0x8c
    3946:	f104 0090 	add.w	r0, r4, #144	; 0x90
	list->head = (sys_dnode_t *)list;
    394a:	f8c4 0090 	str.w	r0, [r4, #144]	; 0x90
	list->tail = (sys_dnode_t *)list;
    394e:	f8c4 0094 	str.w	r0, [r4, #148]	; 0x94

	sys_slist_init(&queue->pending);
	z_waitq_init(&queue->notifyq);
	z_waitq_init(&queue->drainq);

	if ((cfg != NULL) && cfg->no_yield) {
    3952:	b1fd      	cbz	r5, 3994 <k_work_queue_start+0x6c>
    3954:	7928      	ldrb	r0, [r5, #4]
    3956:	b9f8      	cbnz	r0, 3998 <k_work_queue_start+0x70>
	uint32_t flags = K_WORK_QUEUE_STARTED;
    3958:	2001      	movs	r0, #1
	*flagp = flags;
    395a:	f8c4 0098 	str.w	r0, [r4, #152]	; 0x98
	return z_impl_k_thread_create(new_thread, stack, stack_size, entry, p1, p2, p3, prio, options, delay);
    395e:	f04f 36ff 	mov.w	r6, #4294967295
    3962:	f04f 37ff 	mov.w	r7, #4294967295
    3966:	e9cd 6706 	strd	r6, r7, [sp, #24]
    396a:	2000      	movs	r0, #0
    396c:	9004      	str	r0, [sp, #16]
    396e:	9303      	str	r3, [sp, #12]
    3970:	9002      	str	r0, [sp, #8]
    3972:	9001      	str	r0, [sp, #4]
    3974:	9400      	str	r4, [sp, #0]
    3976:	4b0a      	ldr	r3, [pc, #40]	; (39a0 <k_work_queue_start+0x78>)
    3978:	4620      	mov	r0, r4
    397a:	f001 fc31 	bl	51e0 <z_impl_k_thread_create>

	(void)k_thread_create(&queue->thread, stack, stack_size,
			      work_queue_main, queue, NULL, NULL,
			      prio, 0, K_FOREVER);

	if ((cfg != NULL) && (cfg->name != NULL)) {
    397e:	b125      	cbz	r5, 398a <k_work_queue_start+0x62>
    3980:	6829      	ldr	r1, [r5, #0]
    3982:	b111      	cbz	r1, 398a <k_work_queue_start+0x62>
	return z_impl_k_thread_name_set(thread, str);
    3984:	4620      	mov	r0, r4
    3986:	f001 fc19 	bl	51bc <z_impl_k_thread_name_set>
	z_impl_k_thread_start(thread);
    398a:	4620      	mov	r0, r4
    398c:	f001 fc19 	bl	51c2 <z_impl_k_thread_start>
	}

	k_thread_start(&queue->thread);

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_work_queue, start, queue);
}
    3990:	b009      	add	sp, #36	; 0x24
    3992:	bdf0      	pop	{r4, r5, r6, r7, pc}
	uint32_t flags = K_WORK_QUEUE_STARTED;
    3994:	2001      	movs	r0, #1
    3996:	e7e0      	b.n	395a <k_work_queue_start+0x32>
		flags |= K_WORK_QUEUE_NO_YIELD;
    3998:	f240 1001 	movw	r0, #257	; 0x101
    399c:	e7dd      	b.n	395a <k_work_queue_start+0x32>
    399e:	bf00      	nop
    39a0:	00003829 	.word	0x00003829

000039a4 <add_thread_timeout>:
		z_priq_wait_add(&wait_q->waitq, thread);
	}
}

static void add_thread_timeout(struct k_thread *thread, k_timeout_t timeout)
{
    39a4:	b538      	push	{r3, r4, r5, lr}
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    39a6:	f1b3 3fff 	cmp.w	r3, #4294967295
    39aa:	bf08      	it	eq
    39ac:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    39b0:	d100      	bne.n	39b4 <add_thread_timeout+0x10>
		z_add_thread_timeout(thread, timeout);
	}
}
    39b2:	bd38      	pop	{r3, r4, r5, pc}
    39b4:	4902      	ldr	r1, [pc, #8]	; (39c0 <add_thread_timeout+0x1c>)
    39b6:	3018      	adds	r0, #24
    39b8:	f000 fc60 	bl	427c <z_add_timeout>
    39bc:	e7f9      	b.n	39b2 <add_thread_timeout+0xe>
    39be:	bf00      	nop
    39c0:	00005451 	.word	0x00005451

000039c4 <z_reset_time_slice>:
{
    39c4:	b508      	push	{r3, lr}
	if (slice_time != 0) {
    39c6:	4b08      	ldr	r3, [pc, #32]	; (39e8 <z_reset_time_slice+0x24>)
    39c8:	681b      	ldr	r3, [r3, #0]
    39ca:	b903      	cbnz	r3, 39ce <z_reset_time_slice+0xa>
}
    39cc:	bd08      	pop	{r3, pc}
		_current_cpu->slice_ticks = slice_time + sys_clock_elapsed();
    39ce:	f7fd ffd1 	bl	1974 <sys_clock_elapsed>
    39d2:	4603      	mov	r3, r0
    39d4:	4a04      	ldr	r2, [pc, #16]	; (39e8 <z_reset_time_slice+0x24>)
    39d6:	6810      	ldr	r0, [r2, #0]
    39d8:	4403      	add	r3, r0
    39da:	4a04      	ldr	r2, [pc, #16]	; (39ec <z_reset_time_slice+0x28>)
    39dc:	6113      	str	r3, [r2, #16]
		z_set_timeout_expiry(slice_time, false);
    39de:	2100      	movs	r1, #0
    39e0:	f001 fe3e 	bl	5660 <z_set_timeout_expiry>
}
    39e4:	e7f2      	b.n	39cc <z_reset_time_slice+0x8>
    39e6:	bf00      	nop
    39e8:	20000934 	.word	0x20000934
    39ec:	200008e4 	.word	0x200008e4

000039f0 <k_sched_time_slice_set>:
{
    39f0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    39f4:	4606      	mov	r6, r0
    39f6:	4688      	mov	r8, r1
	LOCKED(&sched_spinlock) {
    39f8:	2300      	movs	r3, #0
	__asm__ volatile(
    39fa:	f04f 0220 	mov.w	r2, #32
    39fe:	f3ef 8711 	mrs	r7, BASEPRI
    3a02:	f382 8811 	msr	BASEPRI, r2
    3a06:	f3bf 8f6f 	isb	sy
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    3a0a:	e009      	b.n	3a20 <k_sched_time_slice_set+0x30>
		slice_max_prio = prio;
    3a0c:	4b13      	ldr	r3, [pc, #76]	; (3a5c <k_sched_time_slice_set+0x6c>)
    3a0e:	f8c3 8000 	str.w	r8, [r3]
		z_reset_time_slice();
    3a12:	f7ff ffd7 	bl	39c4 <z_reset_time_slice>
	__asm__ volatile(
    3a16:	f387 8811 	msr	BASEPRI, r7
    3a1a:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    3a1e:	2301      	movs	r3, #1
    3a20:	b9cb      	cbnz	r3, 3a56 <k_sched_time_slice_set+0x66>
		_current_cpu->slice_ticks = 0;
    3a22:	2300      	movs	r3, #0
    3a24:	4a0e      	ldr	r2, [pc, #56]	; (3a60 <k_sched_time_slice_set+0x70>)
    3a26:	6113      	str	r3, [r2, #16]
			return (uint32_t)((t * to_hz + off) / from_hz);
    3a28:	0c75      	lsrs	r5, r6, #17
    3a2a:	03f4      	lsls	r4, r6, #15
    3a2c:	f240 30e7 	movw	r0, #999	; 0x3e7
    3a30:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    3a34:	2300      	movs	r3, #0
    3a36:	1820      	adds	r0, r4, r0
    3a38:	f04f 0100 	mov.w	r1, #0
    3a3c:	eb45 0101 	adc.w	r1, r5, r1
    3a40:	f7fc fb5e 	bl	100 <__aeabi_uldivmod>
		slice_time = k_ms_to_ticks_ceil32(slice);
    3a44:	4b07      	ldr	r3, [pc, #28]	; (3a64 <k_sched_time_slice_set+0x74>)
    3a46:	6018      	str	r0, [r3, #0]
		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && slice > 0) {
    3a48:	2e00      	cmp	r6, #0
    3a4a:	dddf      	ble.n	3a0c <k_sched_time_slice_set+0x1c>
			slice_time = MAX(2, slice_time);
    3a4c:	2802      	cmp	r0, #2
    3a4e:	bfb8      	it	lt
    3a50:	2002      	movlt	r0, #2
    3a52:	6018      	str	r0, [r3, #0]
    3a54:	e7da      	b.n	3a0c <k_sched_time_slice_set+0x1c>
}
    3a56:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    3a5a:	bf00      	nop
    3a5c:	20000930 	.word	0x20000930
    3a60:	200008e4 	.word	0x200008e4
    3a64:	20000934 	.word	0x20000934

00003a68 <z_reschedule>:
	return new_thread != _current;
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
    3a68:	b508      	push	{r3, lr}
	if (resched(key.key) && need_swap()) {
    3a6a:	4608      	mov	r0, r1
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    3a6c:	b921      	cbnz	r1, 3a78 <z_reschedule+0x10>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    3a6e:	f3ef 8305 	mrs	r3, IPSR
    3a72:	b913      	cbnz	r3, 3a7a <z_reschedule+0x12>
    3a74:	2101      	movs	r1, #1
    3a76:	e000      	b.n	3a7a <z_reschedule+0x12>
    3a78:	2100      	movs	r1, #0
	if (resched(key.key) && need_swap()) {
    3a7a:	f011 0f01 	tst.w	r1, #1
    3a7e:	d007      	beq.n	3a90 <z_reschedule+0x28>
	new_thread = _kernel.ready_q.cache;
    3a80:	4b06      	ldr	r3, [pc, #24]	; (3a9c <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x4>)
    3a82:	6a5a      	ldr	r2, [r3, #36]	; 0x24
	return new_thread != _current;
    3a84:	689b      	ldr	r3, [r3, #8]
	if (resched(key.key) && need_swap()) {
    3a86:	429a      	cmp	r2, r3
    3a88:	d002      	beq.n	3a90 <z_reschedule+0x28>
	ret = arch_swap(key);
    3a8a:	f7fd ff7d 	bl	1988 <arch_swap>
		z_swap(lock, key);
    3a8e:	e003      	b.n	3a98 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT>
    3a90:	f380 8811 	msr	BASEPRI, r0
    3a94:	f3bf 8f6f 	isb	sy
	} else {
		k_spin_unlock(lock, key);
	}
}
    3a98:	bd08      	pop	{r3, pc}
    3a9a:	bf00      	nop
    3a9c:	200008e4 	.word	0x200008e4

00003aa0 <k_sched_lock>:
	}
}

void k_sched_lock(void)
{
	LOCKED(&sched_spinlock) {
    3aa0:	2300      	movs	r3, #0
	__asm__ volatile(
    3aa2:	f04f 0220 	mov.w	r2, #32
    3aa6:	f3ef 8111 	mrs	r1, BASEPRI
    3aaa:	f382 8811 	msr	BASEPRI, r2
    3aae:	f3bf 8f6f 	isb	sy
    3ab2:	b953      	cbnz	r3, 3aca <k_sched_lock+0x2a>
	--_current->base.sched_locked;
    3ab4:	4b05      	ldr	r3, [pc, #20]	; (3acc <k_sched_lock+0x2c>)
    3ab6:	689a      	ldr	r2, [r3, #8]
    3ab8:	7bd3      	ldrb	r3, [r2, #15]
    3aba:	3b01      	subs	r3, #1
    3abc:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    3abe:	f381 8811 	msr	BASEPRI, r1
    3ac2:	f3bf 8f6f 	isb	sy
    3ac6:	2301      	movs	r3, #1
    3ac8:	e7f3      	b.n	3ab2 <k_sched_lock+0x12>
		SYS_PORT_TRACING_FUNC(k_thread, sched_lock);

		z_sched_lock();
	}
}
    3aca:	4770      	bx	lr
    3acc:	200008e4 	.word	0x200008e4

00003ad0 <update_cache>:
{
    3ad0:	b538      	push	{r3, r4, r5, lr}
    3ad2:	4604      	mov	r4, r0
	thread = _priq_run_best(&_kernel.ready_q.runq);
    3ad4:	480f      	ldr	r0, [pc, #60]	; (3b14 <update_cache+0x44>)
    3ad6:	f001 fc4d 	bl	5374 <z_priq_dumb_best>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    3ada:	4605      	mov	r5, r0
    3adc:	b170      	cbz	r0, 3afc <update_cache+0x2c>
	if (preempt_ok != 0) {
    3ade:	b984      	cbnz	r4, 3b02 <update_cache+0x32>
	if (z_is_thread_prevented_from_running(_current)) {
    3ae0:	4b0d      	ldr	r3, [pc, #52]	; (3b18 <update_cache+0x48>)
    3ae2:	689b      	ldr	r3, [r3, #8]
	uint8_t state = thread->base.thread_state;
    3ae4:	7b5a      	ldrb	r2, [r3, #13]
    3ae6:	f012 0f1f 	tst.w	r2, #31
    3aea:	d10a      	bne.n	3b02 <update_cache+0x32>
	return node->next != NULL;
    3aec:	69aa      	ldr	r2, [r5, #24]
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    3aee:	b942      	cbnz	r2, 3b02 <update_cache+0x32>
	return thread->base.preempt <= _PREEMPT_THRESHOLD;
    3af0:	89da      	ldrh	r2, [r3, #14]
	if (is_preempt(_current) || is_metairq(thread)) {
    3af2:	2a7f      	cmp	r2, #127	; 0x7f
    3af4:	d905      	bls.n	3b02 <update_cache+0x32>
		_kernel.ready_q.cache = _current;
    3af6:	4a08      	ldr	r2, [pc, #32]	; (3b18 <update_cache+0x48>)
    3af8:	6253      	str	r3, [r2, #36]	; 0x24
    3afa:	e00a      	b.n	3b12 <update_cache+0x42>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    3afc:	4b06      	ldr	r3, [pc, #24]	; (3b18 <update_cache+0x48>)
    3afe:	68dd      	ldr	r5, [r3, #12]
    3b00:	e7ed      	b.n	3ade <update_cache+0xe>
		if (thread != _current) {
    3b02:	4b05      	ldr	r3, [pc, #20]	; (3b18 <update_cache+0x48>)
    3b04:	689b      	ldr	r3, [r3, #8]
    3b06:	42ab      	cmp	r3, r5
    3b08:	d001      	beq.n	3b0e <update_cache+0x3e>
			z_reset_time_slice();
    3b0a:	f7ff ff5b 	bl	39c4 <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    3b0e:	4b02      	ldr	r3, [pc, #8]	; (3b18 <update_cache+0x48>)
    3b10:	625d      	str	r5, [r3, #36]	; 0x24
}
    3b12:	bd38      	pop	{r3, r4, r5, pc}
    3b14:	2000090c 	.word	0x2000090c
    3b18:	200008e4 	.word	0x200008e4

00003b1c <unready_thread>:
{
    3b1c:	b510      	push	{r4, lr}
    3b1e:	4604      	mov	r4, r0
	return (thread->base.thread_state & state) != 0U;
    3b20:	7b42      	ldrb	r2, [r0, #13]
	if (z_is_thread_queued(thread)) {
    3b22:	f990 300d 	ldrsb.w	r3, [r0, #13]
    3b26:	2b00      	cmp	r3, #0
    3b28:	db08      	blt.n	3b3c <unready_thread+0x20>
	update_cache(thread == _current);
    3b2a:	4b08      	ldr	r3, [pc, #32]	; (3b4c <unready_thread+0x30>)
    3b2c:	6898      	ldr	r0, [r3, #8]
    3b2e:	42a0      	cmp	r0, r4
    3b30:	bf14      	ite	ne
    3b32:	2000      	movne	r0, #0
    3b34:	2001      	moveq	r0, #1
    3b36:	f7ff ffcb 	bl	3ad0 <update_cache>
}
    3b3a:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3b3c:	f002 027f 	and.w	r2, r2, #127	; 0x7f
    3b40:	7342      	strb	r2, [r0, #13]
		_priq_run_remove(pq, thread);
    3b42:	4601      	mov	r1, r0
    3b44:	4802      	ldr	r0, [pc, #8]	; (3b50 <unready_thread+0x34>)
    3b46:	f001 fc0d 	bl	5364 <z_priq_dumb_remove>
}
    3b4a:	e7ee      	b.n	3b2a <unready_thread+0xe>
    3b4c:	200008e4 	.word	0x200008e4
    3b50:	2000090c 	.word	0x2000090c

00003b54 <z_pend_curr>:
{
    3b54:	b510      	push	{r4, lr}
    3b56:	460c      	mov	r4, r1
    3b58:	4611      	mov	r1, r2
	pending_current = _current;
    3b5a:	4b06      	ldr	r3, [pc, #24]	; (3b74 <z_pend_curr+0x20>)
    3b5c:	6898      	ldr	r0, [r3, #8]
    3b5e:	4b06      	ldr	r3, [pc, #24]	; (3b78 <z_pend_curr+0x24>)
    3b60:	6018      	str	r0, [r3, #0]
	pend(_current, wait_q, timeout);
    3b62:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    3b66:	f001 fc36 	bl	53d6 <pend>
    3b6a:	4620      	mov	r0, r4
    3b6c:	f7fd ff0c 	bl	1988 <arch_swap>
}
    3b70:	bd10      	pop	{r4, pc}
    3b72:	bf00      	nop
    3b74:	200008e4 	.word	0x200008e4
    3b78:	20000928 	.word	0x20000928

00003b7c <z_impl_k_thread_suspend>:
{
    3b7c:	b538      	push	{r3, r4, r5, lr}
    3b7e:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    3b80:	3018      	adds	r0, #24
    3b82:	f001 fd39 	bl	55f8 <z_abort_timeout>
	LOCKED(&sched_spinlock) {
    3b86:	2300      	movs	r3, #0
	__asm__ volatile(
    3b88:	f04f 0220 	mov.w	r2, #32
    3b8c:	f3ef 8511 	mrs	r5, BASEPRI
    3b90:	f382 8811 	msr	BASEPRI, r2
    3b94:	f3bf 8f6f 	isb	sy
    3b98:	e010      	b.n	3bbc <z_impl_k_thread_suspend+0x40>
	thread->base.thread_state |= _THREAD_SUSPENDED;
    3b9a:	7b63      	ldrb	r3, [r4, #13]
    3b9c:	f043 0310 	orr.w	r3, r3, #16
    3ba0:	7363      	strb	r3, [r4, #13]
		update_cache(thread == _current);
    3ba2:	4b15      	ldr	r3, [pc, #84]	; (3bf8 <z_impl_k_thread_suspend+0x7c>)
    3ba4:	6898      	ldr	r0, [r3, #8]
    3ba6:	42a0      	cmp	r0, r4
    3ba8:	bf14      	ite	ne
    3baa:	2000      	movne	r0, #0
    3bac:	2001      	moveq	r0, #1
    3bae:	f7ff ff8f 	bl	3ad0 <update_cache>
	__asm__ volatile(
    3bb2:	f385 8811 	msr	BASEPRI, r5
    3bb6:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    3bba:	2301      	movs	r3, #1
    3bbc:	b963      	cbnz	r3, 3bd8 <z_impl_k_thread_suspend+0x5c>
	return (thread->base.thread_state & state) != 0U;
    3bbe:	7b62      	ldrb	r2, [r4, #13]
		if (z_is_thread_queued(thread)) {
    3bc0:	f994 300d 	ldrsb.w	r3, [r4, #13]
    3bc4:	2b00      	cmp	r3, #0
    3bc6:	dae8      	bge.n	3b9a <z_impl_k_thread_suspend+0x1e>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3bc8:	f002 027f 	and.w	r2, r2, #127	; 0x7f
    3bcc:	7362      	strb	r2, [r4, #13]
		_priq_run_remove(pq, thread);
    3bce:	4621      	mov	r1, r4
    3bd0:	480a      	ldr	r0, [pc, #40]	; (3bfc <z_impl_k_thread_suspend+0x80>)
    3bd2:	f001 fbc7 	bl	5364 <z_priq_dumb_remove>
}
    3bd6:	e7e0      	b.n	3b9a <z_impl_k_thread_suspend+0x1e>
	if (thread == _current) {
    3bd8:	4b07      	ldr	r3, [pc, #28]	; (3bf8 <z_impl_k_thread_suspend+0x7c>)
    3bda:	689b      	ldr	r3, [r3, #8]
    3bdc:	42a3      	cmp	r3, r4
    3bde:	d000      	beq.n	3be2 <z_impl_k_thread_suspend+0x66>
}
    3be0:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    3be2:	f04f 0320 	mov.w	r3, #32
    3be6:	f3ef 8011 	mrs	r0, BASEPRI
    3bea:	f383 8811 	msr	BASEPRI, r3
    3bee:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    3bf2:	f001 fba2 	bl	533a <z_reschedule_irqlock>
    3bf6:	e7f3      	b.n	3be0 <z_impl_k_thread_suspend+0x64>
    3bf8:	200008e4 	.word	0x200008e4
    3bfc:	2000090c 	.word	0x2000090c

00003c00 <k_sched_unlock>:

void k_sched_unlock(void)
{
    3c00:	b510      	push	{r4, lr}
	LOCKED(&sched_spinlock) {
    3c02:	2300      	movs	r3, #0
    3c04:	f04f 0220 	mov.w	r2, #32
    3c08:	f3ef 8411 	mrs	r4, BASEPRI
    3c0c:	f382 8811 	msr	BASEPRI, r2
    3c10:	f3bf 8f6f 	isb	sy
    3c14:	b96b      	cbnz	r3, 3c32 <k_sched_unlock+0x32>
		__ASSERT(_current->base.sched_locked != 0U, "");
		__ASSERT(!arch_is_in_isr(), "");

		++_current->base.sched_locked;
    3c16:	4b0c      	ldr	r3, [pc, #48]	; (3c48 <k_sched_unlock+0x48>)
    3c18:	689a      	ldr	r2, [r3, #8]
    3c1a:	7bd3      	ldrb	r3, [r2, #15]
    3c1c:	3301      	adds	r3, #1
    3c1e:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    3c20:	2000      	movs	r0, #0
    3c22:	f7ff ff55 	bl	3ad0 <update_cache>
	__asm__ volatile(
    3c26:	f384 8811 	msr	BASEPRI, r4
    3c2a:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    3c2e:	2301      	movs	r3, #1
    3c30:	e7f0      	b.n	3c14 <k_sched_unlock+0x14>
	__asm__ volatile(
    3c32:	f04f 0320 	mov.w	r3, #32
    3c36:	f3ef 8011 	mrs	r0, BASEPRI
    3c3a:	f383 8811 	msr	BASEPRI, r3
    3c3e:	f3bf 8f6f 	isb	sy
    3c42:	f001 fb7a 	bl	533a <z_reschedule_irqlock>
		_current, _current->base.sched_locked);

	SYS_PORT_TRACING_FUNC(k_thread, sched_unlock);

	z_reschedule_unlocked();
}
    3c46:	bd10      	pop	{r4, pc}
    3c48:	200008e4 	.word	0x200008e4

00003c4c <move_thread_to_end_of_prio_q>:
{
    3c4c:	b538      	push	{r3, r4, r5, lr}
    3c4e:	4605      	mov	r5, r0
	return (thread->base.thread_state & state) != 0U;
    3c50:	7b42      	ldrb	r2, [r0, #13]
	if (z_is_thread_queued(thread)) {
    3c52:	f990 300d 	ldrsb.w	r3, [r0, #13]
    3c56:	2b00      	cmp	r3, #0
    3c58:	db28      	blt.n	3cac <move_thread_to_end_of_prio_q+0x60>
	thread->base.thread_state |= _THREAD_QUEUED;
    3c5a:	7b6b      	ldrb	r3, [r5, #13]
    3c5c:	f063 037f 	orn	r3, r3, #127	; 0x7f
    3c60:	736b      	strb	r3, [r5, #13]
	return list->head == list;
    3c62:	4b1a      	ldr	r3, [pc, #104]	; (3ccc <move_thread_to_end_of_prio_q+0x80>)
    3c64:	f853 4f28 	ldr.w	r4, [r3, #40]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3c68:	429c      	cmp	r4, r3
    3c6a:	d02d      	beq.n	3cc8 <move_thread_to_end_of_prio_q+0x7c>
{
	struct k_thread *t;

	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3c6c:	b16c      	cbz	r4, 3c8a <move_thread_to_end_of_prio_q+0x3e>
		if (z_sched_prio_cmp(thread, t) > 0) {
    3c6e:	4621      	mov	r1, r4
    3c70:	4628      	mov	r0, r5
    3c72:	f001 fb39 	bl	52e8 <z_sched_prio_cmp>
    3c76:	2800      	cmp	r0, #0
    3c78:	dc20      	bgt.n	3cbc <move_thread_to_end_of_prio_q+0x70>
 */

static inline sys_dnode_t *sys_dlist_peek_next(sys_dlist_t *list,
					       sys_dnode_t *node)
{
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3c7a:	b134      	cbz	r4, 3c8a <move_thread_to_end_of_prio_q+0x3e>
	return (node == list->tail) ? NULL : node->next;
    3c7c:	4b13      	ldr	r3, [pc, #76]	; (3ccc <move_thread_to_end_of_prio_q+0x80>)
    3c7e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    3c80:	429c      	cmp	r4, r3
    3c82:	d002      	beq.n	3c8a <move_thread_to_end_of_prio_q+0x3e>
    3c84:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3c86:	2c00      	cmp	r4, #0
    3c88:	d1f0      	bne.n	3c6c <move_thread_to_end_of_prio_q+0x20>
 * @return N/A
 */

static inline void sys_dlist_append(sys_dlist_t *list, sys_dnode_t *node)
{
	sys_dnode_t *const tail = list->tail;
    3c8a:	4b10      	ldr	r3, [pc, #64]	; (3ccc <move_thread_to_end_of_prio_q+0x80>)
    3c8c:	6ada      	ldr	r2, [r3, #44]	; 0x2c

	node->next = list;
    3c8e:	f103 0128 	add.w	r1, r3, #40	; 0x28
    3c92:	6029      	str	r1, [r5, #0]
	node->prev = tail;
    3c94:	606a      	str	r2, [r5, #4]

	tail->next = node;
    3c96:	6015      	str	r5, [r2, #0]
	list->tail = node;
    3c98:	62dd      	str	r5, [r3, #44]	; 0x2c
	update_cache(thread == _current);
    3c9a:	4b0c      	ldr	r3, [pc, #48]	; (3ccc <move_thread_to_end_of_prio_q+0x80>)
    3c9c:	6898      	ldr	r0, [r3, #8]
    3c9e:	42a8      	cmp	r0, r5
    3ca0:	bf14      	ite	ne
    3ca2:	2000      	movne	r0, #0
    3ca4:	2001      	moveq	r0, #1
    3ca6:	f7ff ff13 	bl	3ad0 <update_cache>
}
    3caa:	bd38      	pop	{r3, r4, r5, pc}
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3cac:	f002 027f 	and.w	r2, r2, #127	; 0x7f
    3cb0:	7342      	strb	r2, [r0, #13]
		_priq_run_remove(pq, thread);
    3cb2:	4601      	mov	r1, r0
    3cb4:	4806      	ldr	r0, [pc, #24]	; (3cd0 <move_thread_to_end_of_prio_q+0x84>)
    3cb6:	f001 fb55 	bl	5364 <z_priq_dumb_remove>
}
    3cba:	e7ce      	b.n	3c5a <move_thread_to_end_of_prio_q+0xe>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    3cbc:	6863      	ldr	r3, [r4, #4]

	node->prev = prev;
    3cbe:	606b      	str	r3, [r5, #4]
	node->next = successor;
    3cc0:	602c      	str	r4, [r5, #0]
	prev->next = node;
    3cc2:	601d      	str	r5, [r3, #0]
	successor->prev = node;
    3cc4:	6065      	str	r5, [r4, #4]
}
    3cc6:	e7e8      	b.n	3c9a <move_thread_to_end_of_prio_q+0x4e>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3cc8:	2400      	movs	r4, #0
    3cca:	e7cf      	b.n	3c6c <move_thread_to_end_of_prio_q+0x20>
    3ccc:	200008e4 	.word	0x200008e4
    3cd0:	2000090c 	.word	0x2000090c

00003cd4 <z_time_slice>:
{
    3cd4:	b510      	push	{r4, lr}
    3cd6:	f04f 0320 	mov.w	r3, #32
    3cda:	f3ef 8411 	mrs	r4, BASEPRI
    3cde:	f383 8811 	msr	BASEPRI, r3
    3ce2:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    3ce6:	4b1c      	ldr	r3, [pc, #112]	; (3d58 <z_time_slice+0x84>)
    3ce8:	689b      	ldr	r3, [r3, #8]
    3cea:	4a1c      	ldr	r2, [pc, #112]	; (3d5c <z_time_slice+0x88>)
    3cec:	6812      	ldr	r2, [r2, #0]
    3cee:	4293      	cmp	r3, r2
    3cf0:	d01d      	beq.n	3d2e <z_time_slice+0x5a>
	pending_current = NULL;
    3cf2:	4a1a      	ldr	r2, [pc, #104]	; (3d5c <z_time_slice+0x88>)
    3cf4:	2100      	movs	r1, #0
    3cf6:	6011      	str	r1, [r2, #0]
	if (slice_time && sliceable(_current)) {
    3cf8:	4a19      	ldr	r2, [pc, #100]	; (3d60 <z_time_slice+0x8c>)
    3cfa:	6812      	ldr	r2, [r2, #0]
    3cfc:	b322      	cbz	r2, 3d48 <z_time_slice+0x74>
	return thread->base.preempt <= _PREEMPT_THRESHOLD;
    3cfe:	89da      	ldrh	r2, [r3, #14]
		&& !z_is_idle_thread_object(thread);
    3d00:	2a7f      	cmp	r2, #127	; 0x7f
    3d02:	d821      	bhi.n	3d48 <z_time_slice+0x74>
	uint8_t state = thread->base.thread_state;
    3d04:	7b5a      	ldrb	r2, [r3, #13]
		&& !z_is_thread_prevented_from_running(thread)
    3d06:	f012 0f1f 	tst.w	r2, #31
    3d0a:	d11d      	bne.n	3d48 <z_time_slice+0x74>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    3d0c:	f993 100e 	ldrsb.w	r1, [r3, #14]
    3d10:	4a14      	ldr	r2, [pc, #80]	; (3d64 <z_time_slice+0x90>)
    3d12:	6812      	ldr	r2, [r2, #0]
    3d14:	4291      	cmp	r1, r2
    3d16:	db17      	blt.n	3d48 <z_time_slice+0x74>
		&& !z_is_idle_thread_object(thread);
    3d18:	4a13      	ldr	r2, [pc, #76]	; (3d68 <z_time_slice+0x94>)
    3d1a:	4293      	cmp	r3, r2
    3d1c:	d014      	beq.n	3d48 <z_time_slice+0x74>
		if (ticks >= _current_cpu->slice_ticks) {
    3d1e:	4a0e      	ldr	r2, [pc, #56]	; (3d58 <z_time_slice+0x84>)
    3d20:	6912      	ldr	r2, [r2, #16]
    3d22:	4282      	cmp	r2, r0
    3d24:	dd0a      	ble.n	3d3c <z_time_slice+0x68>
			_current_cpu->slice_ticks -= ticks;
    3d26:	1a10      	subs	r0, r2, r0
    3d28:	4b0b      	ldr	r3, [pc, #44]	; (3d58 <z_time_slice+0x84>)
    3d2a:	6118      	str	r0, [r3, #16]
    3d2c:	e00f      	b.n	3d4e <z_time_slice+0x7a>
		z_reset_time_slice();
    3d2e:	f7ff fe49 	bl	39c4 <z_reset_time_slice>
	__asm__ volatile(
    3d32:	f384 8811 	msr	BASEPRI, r4
    3d36:	f3bf 8f6f 	isb	sy
		return;
    3d3a:	e00c      	b.n	3d56 <z_time_slice+0x82>
			move_thread_to_end_of_prio_q(_current);
    3d3c:	4618      	mov	r0, r3
    3d3e:	f7ff ff85 	bl	3c4c <move_thread_to_end_of_prio_q>
			z_reset_time_slice();
    3d42:	f7ff fe3f 	bl	39c4 <z_reset_time_slice>
    3d46:	e002      	b.n	3d4e <z_time_slice+0x7a>
		_current_cpu->slice_ticks = 0;
    3d48:	4b03      	ldr	r3, [pc, #12]	; (3d58 <z_time_slice+0x84>)
    3d4a:	2200      	movs	r2, #0
    3d4c:	611a      	str	r2, [r3, #16]
    3d4e:	f384 8811 	msr	BASEPRI, r4
    3d52:	f3bf 8f6f 	isb	sy
}
    3d56:	bd10      	pop	{r4, pc}
    3d58:	200008e4 	.word	0x200008e4
    3d5c:	20000928 	.word	0x20000928
    3d60:	20000934 	.word	0x20000934
    3d64:	20000930 	.word	0x20000930
    3d68:	200000e0 	.word	0x200000e0

00003d6c <ready_thread>:
{
    3d6c:	b538      	push	{r3, r4, r5, lr}
	return (thread->base.thread_state & state) != 0U;
    3d6e:	7b43      	ldrb	r3, [r0, #13]
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    3d70:	f990 200d 	ldrsb.w	r2, [r0, #13]
    3d74:	2a00      	cmp	r2, #0
    3d76:	db2d      	blt.n	3dd4 <ready_thread+0x68>
    3d78:	4604      	mov	r4, r0
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    3d7a:	f013 0f1f 	tst.w	r3, #31
    3d7e:	d105      	bne.n	3d8c <ready_thread+0x20>
	return node->next != NULL;
    3d80:	6982      	ldr	r2, [r0, #24]
    3d82:	b10a      	cbz	r2, 3d88 <ready_thread+0x1c>
    3d84:	2200      	movs	r2, #0
    3d86:	e002      	b.n	3d8e <ready_thread+0x22>
    3d88:	2201      	movs	r2, #1
    3d8a:	e000      	b.n	3d8e <ready_thread+0x22>
    3d8c:	2200      	movs	r2, #0
    3d8e:	b30a      	cbz	r2, 3dd4 <ready_thread+0x68>
	thread->base.thread_state |= _THREAD_QUEUED;
    3d90:	f063 037f 	orn	r3, r3, #127	; 0x7f
    3d94:	7363      	strb	r3, [r4, #13]
	return list->head == list;
    3d96:	4b14      	ldr	r3, [pc, #80]	; (3de8 <ready_thread+0x7c>)
    3d98:	f853 5f28 	ldr.w	r5, [r3, #40]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3d9c:	429d      	cmp	r5, r3
    3d9e:	d020      	beq.n	3de2 <ready_thread+0x76>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3da0:	b16d      	cbz	r5, 3dbe <ready_thread+0x52>
		if (z_sched_prio_cmp(thread, t) > 0) {
    3da2:	4629      	mov	r1, r5
    3da4:	4620      	mov	r0, r4
    3da6:	f001 fa9f 	bl	52e8 <z_sched_prio_cmp>
    3daa:	2800      	cmp	r0, #0
    3dac:	dc13      	bgt.n	3dd6 <ready_thread+0x6a>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3dae:	b135      	cbz	r5, 3dbe <ready_thread+0x52>
	return (node == list->tail) ? NULL : node->next;
    3db0:	4b0d      	ldr	r3, [pc, #52]	; (3de8 <ready_thread+0x7c>)
    3db2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    3db4:	429d      	cmp	r5, r3
    3db6:	d002      	beq.n	3dbe <ready_thread+0x52>
    3db8:	682d      	ldr	r5, [r5, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3dba:	2d00      	cmp	r5, #0
    3dbc:	d1f0      	bne.n	3da0 <ready_thread+0x34>
	sys_dnode_t *const tail = list->tail;
    3dbe:	4b0a      	ldr	r3, [pc, #40]	; (3de8 <ready_thread+0x7c>)
    3dc0:	6ada      	ldr	r2, [r3, #44]	; 0x2c
	node->next = list;
    3dc2:	f103 0128 	add.w	r1, r3, #40	; 0x28
    3dc6:	6021      	str	r1, [r4, #0]
	node->prev = tail;
    3dc8:	6062      	str	r2, [r4, #4]
	tail->next = node;
    3dca:	6014      	str	r4, [r2, #0]
	list->tail = node;
    3dcc:	62dc      	str	r4, [r3, #44]	; 0x2c
		update_cache(0);
    3dce:	2000      	movs	r0, #0
    3dd0:	f7ff fe7e 	bl	3ad0 <update_cache>
}
    3dd4:	bd38      	pop	{r3, r4, r5, pc}
	sys_dnode_t *const prev = successor->prev;
    3dd6:	686b      	ldr	r3, [r5, #4]
	node->prev = prev;
    3dd8:	6063      	str	r3, [r4, #4]
	node->next = successor;
    3dda:	6025      	str	r5, [r4, #0]
	prev->next = node;
    3ddc:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    3dde:	606c      	str	r4, [r5, #4]
}
    3de0:	e7f5      	b.n	3dce <ready_thread+0x62>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3de2:	2500      	movs	r5, #0
    3de4:	e7dc      	b.n	3da0 <ready_thread+0x34>
    3de6:	bf00      	nop
    3de8:	200008e4 	.word	0x200008e4

00003dec <z_sched_start>:
{
    3dec:	b510      	push	{r4, lr}
	__asm__ volatile(
    3dee:	f04f 0320 	mov.w	r3, #32
    3df2:	f3ef 8411 	mrs	r4, BASEPRI
    3df6:	f383 8811 	msr	BASEPRI, r3
    3dfa:	f3bf 8f6f 	isb	sy
	return (thread->base.thread_state & _THREAD_PRESTART) == 0U;
    3dfe:	7b43      	ldrb	r3, [r0, #13]
	if (z_has_thread_started(thread)) {
    3e00:	f013 0f04 	tst.w	r3, #4
    3e04:	d104      	bne.n	3e10 <z_sched_start+0x24>
	__asm__ volatile(
    3e06:	f384 8811 	msr	BASEPRI, r4
    3e0a:	f3bf 8f6f 	isb	sy
}
    3e0e:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    3e10:	f023 0304 	bic.w	r3, r3, #4
    3e14:	7343      	strb	r3, [r0, #13]
	ready_thread(thread);
    3e16:	f7ff ffa9 	bl	3d6c <ready_thread>
	z_reschedule(&sched_spinlock, key);
    3e1a:	4621      	mov	r1, r4
    3e1c:	4801      	ldr	r0, [pc, #4]	; (3e24 <z_sched_start+0x38>)
    3e1e:	f7ff fe23 	bl	3a68 <z_reschedule>
    3e22:	e7f4      	b.n	3e0e <z_sched_start+0x22>
    3e24:	2000092c 	.word	0x2000092c

00003e28 <z_set_prio>:
{
    3e28:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    3e2c:	4604      	mov	r4, r0
    3e2e:	460f      	mov	r7, r1
	LOCKED(&sched_spinlock) {
    3e30:	2300      	movs	r3, #0
	__asm__ volatile(
    3e32:	f04f 0220 	mov.w	r2, #32
    3e36:	f3ef 8611 	mrs	r6, BASEPRI
    3e3a:	f382 8811 	msr	BASEPRI, r2
    3e3e:	f3bf 8f6f 	isb	sy
	bool need_sched = 0;
    3e42:	4698      	mov	r8, r3
    3e44:	e008      	b.n	3e58 <z_set_prio+0x30>
		if (need_sched) {
    3e46:	f012 0801 	ands.w	r8, r2, #1
    3e4a:	d111      	bne.n	3e70 <z_set_prio+0x48>
			thread->base.prio = prio;
    3e4c:	73a7      	strb	r7, [r4, #14]
	__asm__ volatile(
    3e4e:	f386 8811 	msr	BASEPRI, r6
    3e52:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    3e56:	2301      	movs	r3, #1
    3e58:	461a      	mov	r2, r3
    3e5a:	2b00      	cmp	r3, #0
    3e5c:	d13d      	bne.n	3eda <z_set_prio+0xb2>
	uint8_t state = thread->base.thread_state;
    3e5e:	7b63      	ldrb	r3, [r4, #13]
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    3e60:	f013 0f1f 	tst.w	r3, #31
    3e64:	d1ef      	bne.n	3e46 <z_set_prio+0x1e>
	return node->next != NULL;
    3e66:	69a1      	ldr	r1, [r4, #24]
    3e68:	2900      	cmp	r1, #0
    3e6a:	d1ec      	bne.n	3e46 <z_set_prio+0x1e>
    3e6c:	2201      	movs	r2, #1
    3e6e:	e7ea      	b.n	3e46 <z_set_prio+0x1e>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3e70:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3e74:	7363      	strb	r3, [r4, #13]
		_priq_run_remove(pq, thread);
    3e76:	f8df 906c 	ldr.w	r9, [pc, #108]	; 3ee4 <z_set_prio+0xbc>
    3e7a:	4621      	mov	r1, r4
    3e7c:	4648      	mov	r0, r9
    3e7e:	f001 fa71 	bl	5364 <z_priq_dumb_remove>
				thread->base.prio = prio;
    3e82:	73a7      	strb	r7, [r4, #14]
	thread->base.thread_state |= _THREAD_QUEUED;
    3e84:	7b63      	ldrb	r3, [r4, #13]
    3e86:	f063 037f 	orn	r3, r3, #127	; 0x7f
    3e8a:	7363      	strb	r3, [r4, #13]
	return list->head == list;
    3e8c:	f8d9 5000 	ldr.w	r5, [r9]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3e90:	454d      	cmp	r5, r9
    3e92:	d020      	beq.n	3ed6 <z_set_prio+0xae>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3e94:	b16d      	cbz	r5, 3eb2 <z_set_prio+0x8a>
		if (z_sched_prio_cmp(thread, t) > 0) {
    3e96:	4629      	mov	r1, r5
    3e98:	4620      	mov	r0, r4
    3e9a:	f001 fa25 	bl	52e8 <z_sched_prio_cmp>
    3e9e:	2800      	cmp	r0, #0
    3ea0:	dc13      	bgt.n	3eca <z_set_prio+0xa2>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3ea2:	b135      	cbz	r5, 3eb2 <z_set_prio+0x8a>
	return (node == list->tail) ? NULL : node->next;
    3ea4:	4b0e      	ldr	r3, [pc, #56]	; (3ee0 <z_set_prio+0xb8>)
    3ea6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    3ea8:	429d      	cmp	r5, r3
    3eaa:	d002      	beq.n	3eb2 <z_set_prio+0x8a>
    3eac:	682d      	ldr	r5, [r5, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3eae:	2d00      	cmp	r5, #0
    3eb0:	d1f0      	bne.n	3e94 <z_set_prio+0x6c>
	sys_dnode_t *const tail = list->tail;
    3eb2:	4b0b      	ldr	r3, [pc, #44]	; (3ee0 <z_set_prio+0xb8>)
    3eb4:	6ada      	ldr	r2, [r3, #44]	; 0x2c
	node->next = list;
    3eb6:	f103 0128 	add.w	r1, r3, #40	; 0x28
    3eba:	6021      	str	r1, [r4, #0]
	node->prev = tail;
    3ebc:	6062      	str	r2, [r4, #4]
	tail->next = node;
    3ebe:	6014      	str	r4, [r2, #0]
	list->tail = node;
    3ec0:	62dc      	str	r4, [r3, #44]	; 0x2c
			update_cache(1);
    3ec2:	2001      	movs	r0, #1
    3ec4:	f7ff fe04 	bl	3ad0 <update_cache>
    3ec8:	e7c1      	b.n	3e4e <z_set_prio+0x26>
	sys_dnode_t *const prev = successor->prev;
    3eca:	686b      	ldr	r3, [r5, #4]
	node->prev = prev;
    3ecc:	6063      	str	r3, [r4, #4]
	node->next = successor;
    3ece:	6025      	str	r5, [r4, #0]
	prev->next = node;
    3ed0:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    3ed2:	606c      	str	r4, [r5, #4]
}
    3ed4:	e7f5      	b.n	3ec2 <z_set_prio+0x9a>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3ed6:	2500      	movs	r5, #0
    3ed8:	e7dc      	b.n	3e94 <z_set_prio+0x6c>
}
    3eda:	4640      	mov	r0, r8
    3edc:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    3ee0:	200008e4 	.word	0x200008e4
    3ee4:	2000090c 	.word	0x2000090c

00003ee8 <end_thread>:
static void end_thread(struct k_thread *thread)
{
	/* We hold the lock, and the thread is known not to be running
	 * anywhere.
	 */
	if ((thread->base.thread_state & _THREAD_DEAD) == 0U) {
    3ee8:	7b43      	ldrb	r3, [r0, #13]
    3eea:	f013 0f08 	tst.w	r3, #8
    3eee:	d142      	bne.n	3f76 <end_thread+0x8e>
{
    3ef0:	b570      	push	{r4, r5, r6, lr}
    3ef2:	4605      	mov	r5, r0
		thread->base.thread_state |= _THREAD_DEAD;
    3ef4:	f043 0308 	orr.w	r3, r3, #8
		thread->base.thread_state &= ~_THREAD_ABORTING;
    3ef8:	f003 03df 	and.w	r3, r3, #223	; 0xdf
    3efc:	7343      	strb	r3, [r0, #13]
		if (z_is_thread_queued(thread)) {
    3efe:	f013 0f80 	tst.w	r3, #128	; 0x80
    3f02:	d113      	bne.n	3f2c <end_thread+0x44>
			dequeue_thread(&_kernel.ready_q.runq, thread);
		}
		if (thread->base.pended_on != NULL) {
    3f04:	68ab      	ldr	r3, [r5, #8]
    3f06:	b15b      	cbz	r3, 3f20 <end_thread+0x38>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    3f08:	4628      	mov	r0, r5
    3f0a:	f001 f9eb 	bl	52e4 <pended_on_thread>
    3f0e:	4629      	mov	r1, r5
    3f10:	f001 fa28 	bl	5364 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    3f14:	7b6b      	ldrb	r3, [r5, #13]
    3f16:	f023 0302 	bic.w	r3, r3, #2
    3f1a:	736b      	strb	r3, [r5, #13]
	thread->base.pended_on = NULL;
    3f1c:	2300      	movs	r3, #0
    3f1e:	60ab      	str	r3, [r5, #8]
    3f20:	f105 0018 	add.w	r0, r5, #24
    3f24:	f001 fb68 	bl	55f8 <z_abort_timeout>
			unpend_thread_no_timeout(thread);
		}
		(void)z_abort_thread_timeout(thread);
		unpend_all(&thread->join_queue);
    3f28:	3558      	adds	r5, #88	; 0x58
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    3f2a:	e01b      	b.n	3f64 <end_thread+0x7c>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3f2c:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3f30:	7343      	strb	r3, [r0, #13]
		_priq_run_remove(pq, thread);
    3f32:	4601      	mov	r1, r0
    3f34:	4810      	ldr	r0, [pc, #64]	; (3f78 <end_thread+0x90>)
    3f36:	f001 fa15 	bl	5364 <z_priq_dumb_remove>
}
    3f3a:	e7e3      	b.n	3f04 <end_thread+0x1c>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    3f3c:	4620      	mov	r0, r4
    3f3e:	f001 f9d1 	bl	52e4 <pended_on_thread>
    3f42:	4621      	mov	r1, r4
    3f44:	f001 fa0e 	bl	5364 <z_priq_dumb_remove>
    3f48:	7b63      	ldrb	r3, [r4, #13]
    3f4a:	f023 0302 	bic.w	r3, r3, #2
    3f4e:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    3f50:	2600      	movs	r6, #0
    3f52:	60a6      	str	r6, [r4, #8]
    3f54:	f104 0018 	add.w	r0, r4, #24
    3f58:	f001 fb4e 	bl	55f8 <z_abort_timeout>
    3f5c:	67a6      	str	r6, [r4, #120]	; 0x78
		ready_thread(thread);
    3f5e:	4620      	mov	r0, r4
    3f60:	f7ff ff04 	bl	3d6c <ready_thread>
	return list->head == list;
    3f64:	682c      	ldr	r4, [r5, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3f66:	42ac      	cmp	r4, r5
    3f68:	d001      	beq.n	3f6e <end_thread+0x86>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    3f6a:	2c00      	cmp	r4, #0
    3f6c:	d1e6      	bne.n	3f3c <end_thread+0x54>
		update_cache(1);
    3f6e:	2001      	movs	r0, #1
    3f70:	f7ff fdae 	bl	3ad0 <update_cache>
		z_thread_perms_all_clear(thread);
		z_object_uninit(thread->stack_obj);
		z_object_uninit(thread);
#endif
	}
}
    3f74:	bd70      	pop	{r4, r5, r6, pc}
    3f76:	4770      	bx	lr
    3f78:	2000090c 	.word	0x2000090c

00003f7c <z_sched_init>:
{
    3f7c:	b508      	push	{r3, lr}
	list->head = (sys_dnode_t *)list;
    3f7e:	4b05      	ldr	r3, [pc, #20]	; (3f94 <z_sched_init+0x18>)
    3f80:	f103 0228 	add.w	r2, r3, #40	; 0x28
    3f84:	629a      	str	r2, [r3, #40]	; 0x28
	list->tail = (sys_dnode_t *)list;
    3f86:	62da      	str	r2, [r3, #44]	; 0x2c
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    3f88:	2100      	movs	r1, #0
    3f8a:	4608      	mov	r0, r1
    3f8c:	f7ff fd30 	bl	39f0 <k_sched_time_slice_set>
}
    3f90:	bd08      	pop	{r3, pc}
    3f92:	bf00      	nop
    3f94:	200008e4 	.word	0x200008e4

00003f98 <z_impl_k_yield>:
{
    3f98:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	__asm__ volatile(
    3f9a:	f04f 0320 	mov.w	r3, #32
    3f9e:	f3ef 8611 	mrs	r6, BASEPRI
    3fa2:	f383 8811 	msr	BASEPRI, r3
    3fa6:	f3bf 8f6f 	isb	sy
		dequeue_thread(&_kernel.ready_q.runq,
    3faa:	4c1c      	ldr	r4, [pc, #112]	; (401c <z_impl_k_yield+0x84>)
    3fac:	68a1      	ldr	r1, [r4, #8]
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3fae:	7b4b      	ldrb	r3, [r1, #13]
    3fb0:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3fb4:	734b      	strb	r3, [r1, #13]
		_priq_run_remove(pq, thread);
    3fb6:	f104 0728 	add.w	r7, r4, #40	; 0x28
    3fba:	4638      	mov	r0, r7
    3fbc:	f001 f9d2 	bl	5364 <z_priq_dumb_remove>
	queue_thread(&_kernel.ready_q.runq, _current);
    3fc0:	68a5      	ldr	r5, [r4, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    3fc2:	7b6b      	ldrb	r3, [r5, #13]
    3fc4:	f063 037f 	orn	r3, r3, #127	; 0x7f
    3fc8:	736b      	strb	r3, [r5, #13]
	return list->head == list;
    3fca:	6aa4      	ldr	r4, [r4, #40]	; 0x28
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3fcc:	42bc      	cmp	r4, r7
    3fce:	d023      	beq.n	4018 <z_impl_k_yield+0x80>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3fd0:	b16c      	cbz	r4, 3fee <z_impl_k_yield+0x56>
		if (z_sched_prio_cmp(thread, t) > 0) {
    3fd2:	4621      	mov	r1, r4
    3fd4:	4628      	mov	r0, r5
    3fd6:	f001 f987 	bl	52e8 <z_sched_prio_cmp>
    3fda:	2800      	cmp	r0, #0
    3fdc:	dc16      	bgt.n	400c <z_impl_k_yield+0x74>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3fde:	b134      	cbz	r4, 3fee <z_impl_k_yield+0x56>
	return (node == list->tail) ? NULL : node->next;
    3fe0:	4b0e      	ldr	r3, [pc, #56]	; (401c <z_impl_k_yield+0x84>)
    3fe2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    3fe4:	429c      	cmp	r4, r3
    3fe6:	d002      	beq.n	3fee <z_impl_k_yield+0x56>
    3fe8:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3fea:	2c00      	cmp	r4, #0
    3fec:	d1f0      	bne.n	3fd0 <z_impl_k_yield+0x38>
	sys_dnode_t *const tail = list->tail;
    3fee:	4b0b      	ldr	r3, [pc, #44]	; (401c <z_impl_k_yield+0x84>)
    3ff0:	6ada      	ldr	r2, [r3, #44]	; 0x2c
	node->next = list;
    3ff2:	f103 0128 	add.w	r1, r3, #40	; 0x28
    3ff6:	6029      	str	r1, [r5, #0]
	node->prev = tail;
    3ff8:	606a      	str	r2, [r5, #4]
	tail->next = node;
    3ffa:	6015      	str	r5, [r2, #0]
	list->tail = node;
    3ffc:	62dd      	str	r5, [r3, #44]	; 0x2c
	update_cache(1);
    3ffe:	2001      	movs	r0, #1
    4000:	f7ff fd66 	bl	3ad0 <update_cache>
    4004:	4630      	mov	r0, r6
    4006:	f7fd fcbf 	bl	1988 <arch_swap>
}
    400a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	sys_dnode_t *const prev = successor->prev;
    400c:	6863      	ldr	r3, [r4, #4]
	node->prev = prev;
    400e:	606b      	str	r3, [r5, #4]
	node->next = successor;
    4010:	602c      	str	r4, [r5, #0]
	prev->next = node;
    4012:	601d      	str	r5, [r3, #0]
	successor->prev = node;
    4014:	6065      	str	r5, [r4, #4]
}
    4016:	e7f2      	b.n	3ffe <z_impl_k_yield+0x66>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4018:	2400      	movs	r4, #0
    401a:	e7d9      	b.n	3fd0 <z_impl_k_yield+0x38>
    401c:	200008e4 	.word	0x200008e4

00004020 <z_tick_sleep>:
{
    4020:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4024:	4604      	mov	r4, r0
    4026:	460d      	mov	r5, r1
	if (ticks == 0) {
    4028:	ea54 0105 	orrs.w	r1, r4, r5
    402c:	d037      	beq.n	409e <z_tick_sleep+0x7e>
	if (Z_TICK_ABS(ticks) <= 0) {
    402e:	f06f 0101 	mvn.w	r1, #1
    4032:	1a0a      	subs	r2, r1, r0
    4034:	f04f 31ff 	mov.w	r1, #4294967295
    4038:	eb61 0305 	sbc.w	r3, r1, r5
    403c:	2a01      	cmp	r2, #1
    403e:	f173 0300 	sbcs.w	r3, r3, #0
    4042:	db30      	blt.n	40a6 <z_tick_sleep+0x86>
		expected_wakeup_ticks = Z_TICK_ABS(ticks);
    4044:	f06f 0601 	mvn.w	r6, #1
    4048:	1a36      	subs	r6, r6, r0
    404a:	f04f 0320 	mov.w	r3, #32
    404e:	f3ef 8811 	mrs	r8, BASEPRI
    4052:	f383 8811 	msr	BASEPRI, r3
    4056:	f3bf 8f6f 	isb	sy
	pending_current = _current;
    405a:	4f16      	ldr	r7, [pc, #88]	; (40b4 <z_tick_sleep+0x94>)
    405c:	68b8      	ldr	r0, [r7, #8]
    405e:	4b16      	ldr	r3, [pc, #88]	; (40b8 <z_tick_sleep+0x98>)
    4060:	6018      	str	r0, [r3, #0]
	unready_thread(_current);
    4062:	f7ff fd5b 	bl	3b1c <unready_thread>
	z_add_thread_timeout(_current, timeout);
    4066:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    4068:	4622      	mov	r2, r4
    406a:	462b      	mov	r3, r5
    406c:	4913      	ldr	r1, [pc, #76]	; (40bc <z_tick_sleep+0x9c>)
    406e:	3018      	adds	r0, #24
    4070:	f000 f904 	bl	427c <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    4074:	68ba      	ldr	r2, [r7, #8]
	thread->base.thread_state |= _THREAD_SUSPENDED;
    4076:	7b53      	ldrb	r3, [r2, #13]
    4078:	f043 0310 	orr.w	r3, r3, #16
    407c:	7353      	strb	r3, [r2, #13]
    407e:	4640      	mov	r0, r8
    4080:	f7fd fc82 	bl	1988 <arch_swap>
	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    4084:	2500      	movs	r5, #0
    4086:	f001 fb16 	bl	56b6 <sys_clock_tick_get_32>
    408a:	1a34      	subs	r4, r6, r0
    408c:	f165 0500 	sbc.w	r5, r5, #0
	if (ticks > 0) {
    4090:	2c01      	cmp	r4, #1
    4092:	f175 0300 	sbcs.w	r3, r5, #0
    4096:	da0a      	bge.n	40ae <z_tick_sleep+0x8e>
	return 0;
    4098:	2000      	movs	r0, #0
}
    409a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	z_impl_k_yield();
    409e:	f7ff ff7b 	bl	3f98 <z_impl_k_yield>
		return 0;
    40a2:	2000      	movs	r0, #0
    40a4:	e7f9      	b.n	409a <z_tick_sleep+0x7a>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    40a6:	f001 fb06 	bl	56b6 <sys_clock_tick_get_32>
    40aa:	1906      	adds	r6, r0, r4
    40ac:	e7cd      	b.n	404a <z_tick_sleep+0x2a>
		return ticks;
    40ae:	4620      	mov	r0, r4
    40b0:	e7f3      	b.n	409a <z_tick_sleep+0x7a>
    40b2:	bf00      	nop
    40b4:	200008e4 	.word	0x200008e4
    40b8:	20000928 	.word	0x20000928
    40bc:	00005451 	.word	0x00005451

000040c0 <z_impl_k_sleep>:
{
    40c0:	b538      	push	{r3, r4, r5, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    40c2:	f1b1 3fff 	cmp.w	r1, #4294967295
    40c6:	bf08      	it	eq
    40c8:	f1b0 3fff 	cmpeq.w	r0, #4294967295
    40cc:	d01a      	beq.n	4104 <z_impl_k_sleep+0x44>
	ticks = z_tick_sleep(ticks);
    40ce:	f7ff ffa7 	bl	4020 <z_tick_sleep>
	int32_t ret = k_ticks_to_ms_floor64(ticks);
    40d2:	4604      	mov	r4, r0
    40d4:	17c5      	asrs	r5, r0, #31
			return (t * to_hz + off) / from_hz;
    40d6:	0169      	lsls	r1, r5, #5
    40d8:	0143      	lsls	r3, r0, #5
    40da:	ea41 62d0 	orr.w	r2, r1, r0, lsr #27
    40de:	1a18      	subs	r0, r3, r0
    40e0:	eb62 0305 	sbc.w	r3, r2, r5
    40e4:	009a      	lsls	r2, r3, #2
    40e6:	ea42 7290 	orr.w	r2, r2, r0, lsr #30
    40ea:	0081      	lsls	r1, r0, #2
    40ec:	4613      	mov	r3, r2
    40ee:	1908      	adds	r0, r1, r4
    40f0:	eb45 0303 	adc.w	r3, r5, r3
    40f4:	00da      	lsls	r2, r3, #3
    40f6:	ea42 7250 	orr.w	r2, r2, r0, lsr #29
    40fa:	00c1      	lsls	r1, r0, #3
    40fc:	0bc8      	lsrs	r0, r1, #15
    40fe:	ea40 4042 	orr.w	r0, r0, r2, lsl #17
}
    4102:	bd38      	pop	{r3, r4, r5, pc}
		k_thread_suspend(_current);
    4104:	4b03      	ldr	r3, [pc, #12]	; (4114 <z_impl_k_sleep+0x54>)
    4106:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    4108:	f7ff fd38 	bl	3b7c <z_impl_k_thread_suspend>
		return (int32_t) K_TICKS_FOREVER;
    410c:	f04f 30ff 	mov.w	r0, #4294967295
    4110:	e7f7      	b.n	4102 <z_impl_k_sleep+0x42>
    4112:	bf00      	nop
    4114:	200008e4 	.word	0x200008e4

00004118 <z_impl_k_current_get>:
}
    4118:	4b01      	ldr	r3, [pc, #4]	; (4120 <z_impl_k_current_get+0x8>)
    411a:	6898      	ldr	r0, [r3, #8]
    411c:	4770      	bx	lr
    411e:	bf00      	nop
    4120:	200008e4 	.word	0x200008e4

00004124 <z_impl_k_is_preempt_thread>:
    4124:	f3ef 8305 	mrs	r3, IPSR
	return !arch_is_in_isr() && is_preempt(_current);
    4128:	b933      	cbnz	r3, 4138 <z_impl_k_is_preempt_thread+0x14>
    412a:	4b05      	ldr	r3, [pc, #20]	; (4140 <z_impl_k_is_preempt_thread+0x1c>)
    412c:	689b      	ldr	r3, [r3, #8]
	return thread->base.preempt <= _PREEMPT_THRESHOLD;
    412e:	89db      	ldrh	r3, [r3, #14]
	return !arch_is_in_isr() && is_preempt(_current);
    4130:	2b7f      	cmp	r3, #127	; 0x7f
    4132:	d803      	bhi.n	413c <z_impl_k_is_preempt_thread+0x18>
    4134:	2001      	movs	r0, #1
    4136:	4770      	bx	lr
    4138:	2000      	movs	r0, #0
    413a:	4770      	bx	lr
    413c:	2000      	movs	r0, #0
}
    413e:	4770      	bx	lr
    4140:	200008e4 	.word	0x200008e4

00004144 <z_thread_abort>:

void z_thread_abort(struct k_thread *thread)
{
    4144:	b538      	push	{r3, r4, r5, lr}
    4146:	f04f 0320 	mov.w	r3, #32
    414a:	f3ef 8511 	mrs	r5, BASEPRI
    414e:	f383 8811 	msr	BASEPRI, r3
    4152:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    4156:	7b43      	ldrb	r3, [r0, #13]
    4158:	f013 0f08 	tst.w	r3, #8
    415c:	d004      	beq.n	4168 <z_thread_abort+0x24>
	__asm__ volatile(
    415e:	f385 8811 	msr	BASEPRI, r5
    4162:	f3bf 8f6f 	isb	sy
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
	}
	k_spin_unlock(&sched_spinlock, key);
}
    4166:	bd38      	pop	{r3, r4, r5, pc}
    4168:	4604      	mov	r4, r0
	end_thread(thread);
    416a:	f7ff febd 	bl	3ee8 <end_thread>
	if (thread == _current && !arch_is_in_isr()) {
    416e:	4b08      	ldr	r3, [pc, #32]	; (4190 <z_thread_abort+0x4c>)
    4170:	689b      	ldr	r3, [r3, #8]
    4172:	42a3      	cmp	r3, r4
    4174:	d004      	beq.n	4180 <z_thread_abort+0x3c>
    4176:	f385 8811 	msr	BASEPRI, r5
    417a:	f3bf 8f6f 	isb	sy
    417e:	e7f2      	b.n	4166 <z_thread_abort+0x22>
    4180:	f3ef 8305 	mrs	r3, IPSR
    4184:	2b00      	cmp	r3, #0
    4186:	d1f6      	bne.n	4176 <z_thread_abort+0x32>
    4188:	4628      	mov	r0, r5
    418a:	f7fd fbfd 	bl	1988 <arch_swap>
	return ret;
    418e:	e7f2      	b.n	4176 <z_thread_abort+0x32>
    4190:	200008e4 	.word	0x200008e4

00004194 <z_sched_wait>:
	return ret;
}

int z_sched_wait(struct k_spinlock *lock, k_spinlock_key_t key,
		 _wait_q_t *wait_q, k_timeout_t timeout, void **data)
{
    4194:	b5d0      	push	{r4, r6, r7, lr}
    4196:	b082      	sub	sp, #8
    4198:	9c08      	ldr	r4, [sp, #32]
	int ret = z_pend_curr(lock, key, wait_q, timeout);
    419a:	e9dd 6706 	ldrd	r6, r7, [sp, #24]
    419e:	e9cd 6700 	strd	r6, r7, [sp]
    41a2:	f7ff fcd7 	bl	3b54 <z_pend_curr>

	if (data != NULL) {
    41a6:	b11c      	cbz	r4, 41b0 <z_sched_wait+0x1c>
		*data = _current->base.swap_data;
    41a8:	4b02      	ldr	r3, [pc, #8]	; (41b4 <z_sched_wait+0x20>)
    41aa:	689b      	ldr	r3, [r3, #8]
    41ac:	695b      	ldr	r3, [r3, #20]
    41ae:	6023      	str	r3, [r4, #0]
	}
	return ret;
}
    41b0:	b002      	add	sp, #8
    41b2:	bdd0      	pop	{r4, r6, r7, pc}
    41b4:	200008e4 	.word	0x200008e4

000041b8 <z_data_copy>:
 * This routine copies the data section from ROM to RAM.
 *
 * @return N/A
 */
void z_data_copy(void)
{
    41b8:	b508      	push	{r3, lr}
	(void)memcpy(&__data_ram_start, &__data_rom_start,
    41ba:	4806      	ldr	r0, [pc, #24]	; (41d4 <z_data_copy+0x1c>)
__ssp_bos_icheck3_restrict(memcpy, void *, const void *)
    41bc:	4a06      	ldr	r2, [pc, #24]	; (41d8 <z_data_copy+0x20>)
    41be:	1a12      	subs	r2, r2, r0
    41c0:	4906      	ldr	r1, [pc, #24]	; (41dc <z_data_copy+0x24>)
    41c2:	f001 fabc 	bl	573e <memcpy>
    41c6:	4a06      	ldr	r2, [pc, #24]	; (41e0 <z_data_copy+0x28>)
    41c8:	4906      	ldr	r1, [pc, #24]	; (41e4 <z_data_copy+0x2c>)
    41ca:	4807      	ldr	r0, [pc, #28]	; (41e8 <z_data_copy+0x30>)
    41cc:	f001 fab7 	bl	573e <memcpy>
#else
	(void)memcpy(&_app_smem_start, &_app_smem_rom_start,
		 _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    41d0:	bd08      	pop	{r3, pc}
    41d2:	bf00      	nop
    41d4:	20000000 	.word	0x20000000
    41d8:	200000e0 	.word	0x200000e0
    41dc:	00005d6c 	.word	0x00005d6c
    41e0:	00000000 	.word	0x00000000
    41e4:	00005d6c 	.word	0x00005d6c
    41e8:	20000000 	.word	0x20000000

000041ec <first>:
	return list->head == list;
    41ec:	4b03      	ldr	r3, [pc, #12]	; (41fc <first+0x10>)
    41ee:	6818      	ldr	r0, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    41f0:	4298      	cmp	r0, r3
    41f2:	d000      	beq.n	41f6 <first+0xa>
static struct _timeout *first(void)
{
	sys_dnode_t *t = sys_dlist_peek_head(&timeout_list);

	return t == NULL ? NULL : CONTAINER_OF(t, struct _timeout, node);
}
    41f4:	4770      	bx	lr
    41f6:	2000      	movs	r0, #0
	return t == NULL ? NULL : CONTAINER_OF(t, struct _timeout, node);
    41f8:	e7fc      	b.n	41f4 <first+0x8>
    41fa:	bf00      	nop
    41fc:	2000003c 	.word	0x2000003c

00004200 <next>:
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    4200:	b130      	cbz	r0, 4210 <next+0x10>
	return (node == list->tail) ? NULL : node->next;
    4202:	4a04      	ldr	r2, [pc, #16]	; (4214 <next+0x14>)
    4204:	6852      	ldr	r2, [r2, #4]
    4206:	4290      	cmp	r0, r2
    4208:	d001      	beq.n	420e <next+0xe>
    420a:	6800      	ldr	r0, [r0, #0]
    420c:	4770      	bx	lr
    420e:	2000      	movs	r0, #0
static struct _timeout *next(struct _timeout *t)
{
	sys_dnode_t *n = sys_dlist_peek_next(&timeout_list, &t->node);

	return n == NULL ? NULL : CONTAINER_OF(n, struct _timeout, node);
}
    4210:	4770      	bx	lr
    4212:	bf00      	nop
    4214:	2000003c 	.word	0x2000003c

00004218 <elapsed>:

	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
    4218:	b508      	push	{r3, lr}
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    421a:	4b04      	ldr	r3, [pc, #16]	; (422c <elapsed+0x14>)
    421c:	681b      	ldr	r3, [r3, #0]
    421e:	b10b      	cbz	r3, 4224 <elapsed+0xc>
    4220:	2000      	movs	r0, #0
}
    4222:	bd08      	pop	{r3, pc}
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    4224:	f7fd fba6 	bl	1974 <sys_clock_elapsed>
    4228:	e7fb      	b.n	4222 <elapsed+0xa>
    422a:	bf00      	nop
    422c:	20000938 	.word	0x20000938

00004230 <next_timeout>:

static int32_t next_timeout(void)
{
    4230:	b510      	push	{r4, lr}
	struct _timeout *to = first();
    4232:	f7ff ffdb 	bl	41ec <first>
    4236:	4604      	mov	r4, r0
	int32_t ticks_elapsed = elapsed();
    4238:	f7ff ffee 	bl	4218 <elapsed>
	int32_t ret = to == NULL ? MAX_WAIT
    423c:	b18c      	cbz	r4, 4262 <next_timeout+0x32>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    423e:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    4242:	1a12      	subs	r2, r2, r0
    4244:	eb63 73e0 	sbc.w	r3, r3, r0, asr #31
	int32_t ret = to == NULL ? MAX_WAIT
    4248:	2a01      	cmp	r2, #1
    424a:	f173 0100 	sbcs.w	r1, r3, #0
    424e:	db11      	blt.n	4274 <next_timeout+0x44>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    4250:	4610      	mov	r0, r2
    4252:	f1b2 4f00 	cmp.w	r2, #2147483648	; 0x80000000
    4256:	f173 0300 	sbcs.w	r3, r3, #0
    425a:	db04      	blt.n	4266 <next_timeout+0x36>
    425c:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    4260:	e001      	b.n	4266 <next_timeout+0x36>
	int32_t ret = to == NULL ? MAX_WAIT
    4262:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    4266:	4b04      	ldr	r3, [pc, #16]	; (4278 <next_timeout+0x48>)
    4268:	691b      	ldr	r3, [r3, #16]
    426a:	b113      	cbz	r3, 4272 <next_timeout+0x42>
    426c:	4283      	cmp	r3, r0
    426e:	da00      	bge.n	4272 <next_timeout+0x42>
		ret = _current_cpu->slice_ticks;
    4270:	4618      	mov	r0, r3
	}
#endif
	return ret;
}
    4272:	bd10      	pop	{r4, pc}
	int32_t ret = to == NULL ? MAX_WAIT
    4274:	2000      	movs	r0, #0
    4276:	e7f6      	b.n	4266 <next_timeout+0x36>
    4278:	200008e4 	.word	0x200008e4

0000427c <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
    427c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4280:	b083      	sub	sp, #12
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    4282:	f1b3 3fff 	cmp.w	r3, #4294967295
    4286:	bf08      	it	eq
    4288:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    428c:	f000 8096 	beq.w	43bc <z_add_timeout+0x140>
    4290:	4682      	mov	sl, r0
    4292:	4614      	mov	r4, r2
    4294:	461d      	mov	r5, r3
#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    4296:	6081      	str	r1, [r0, #8]

	LOCKED(&timeout_lock) {
    4298:	2300      	movs	r3, #0
	__asm__ volatile(
    429a:	f04f 0220 	mov.w	r2, #32
    429e:	f3ef 8b11 	mrs	fp, BASEPRI
    42a2:	f382 8811 	msr	BASEPRI, r2
    42a6:	f3bf 8f6f 	isb	sy
    42aa:	e02e      	b.n	430a <z_add_timeout+0x8e>

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
		    Z_TICK_ABS(timeout.ticks) >= 0) {
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;

			to->dticks = MAX(1, ticks);
    42ac:	2201      	movs	r2, #1
    42ae:	2300      	movs	r3, #0
    42b0:	e04b      	b.n	434a <z_add_timeout+0xce>
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
    42b2:	f7ff ffb1 	bl	4218 <elapsed>
    42b6:	1822      	adds	r2, r4, r0
    42b8:	eb45 73e0 	adc.w	r3, r5, r0, asr #31
    42bc:	3201      	adds	r2, #1
    42be:	f143 0300 	adc.w	r3, r3, #0
    42c2:	f8ca 2010 	str.w	r2, [sl, #16]
    42c6:	f8ca 3014 	str.w	r3, [sl, #20]
    42ca:	e042      	b.n	4352 <z_add_timeout+0xd6>
		}

		for (t = first(); t != NULL; t = next(t)) {
			if (t->dticks > to->dticks) {
				t->dticks -= to->dticks;
    42cc:	9b00      	ldr	r3, [sp, #0]
    42ce:	1ac2      	subs	r2, r0, r3
    42d0:	9b01      	ldr	r3, [sp, #4]
    42d2:	eb61 0303 	sbc.w	r3, r1, r3
    42d6:	f8cc 2010 	str.w	r2, [ip, #16]
    42da:	f8cc 3014 	str.w	r3, [ip, #20]
	sys_dnode_t *const prev = successor->prev;
    42de:	f8dc 3004 	ldr.w	r3, [ip, #4]
	node->prev = prev;
    42e2:	f8ca 3004 	str.w	r3, [sl, #4]
	node->next = successor;
    42e6:	f8ca c000 	str.w	ip, [sl]
	prev->next = node;
    42ea:	f8c3 a000 	str.w	sl, [r3]
	successor->prev = node;
    42ee:	f8cc a004 	str.w	sl, [ip, #4]
				break;
			}
			to->dticks -= t->dticks;
		}

		if (t == NULL) {
    42f2:	f1bc 0f00 	cmp.w	ip, #0
    42f6:	d049      	beq.n	438c <z_add_timeout+0x110>
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    42f8:	f7ff ff78 	bl	41ec <first>
    42fc:	4582      	cmp	sl, r0
    42fe:	d050      	beq.n	43a2 <z_add_timeout+0x126>
	__asm__ volatile(
    4300:	f38b 8811 	msr	BASEPRI, fp
    4304:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    4308:	2301      	movs	r3, #1
    430a:	2b00      	cmp	r3, #0
    430c:	d156      	bne.n	43bc <z_add_timeout+0x140>
		    Z_TICK_ABS(timeout.ticks) >= 0) {
    430e:	f06f 0301 	mvn.w	r3, #1
    4312:	ebb3 0804 	subs.w	r8, r3, r4
    4316:	f04f 30ff 	mov.w	r0, #4294967295
    431a:	eb60 0905 	sbc.w	r9, r0, r5
		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    431e:	f1b8 0f00 	cmp.w	r8, #0
    4322:	f179 0300 	sbcs.w	r3, r9, #0
    4326:	dbc4      	blt.n	42b2 <z_add_timeout+0x36>
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    4328:	4a26      	ldr	r2, [pc, #152]	; (43c4 <z_add_timeout+0x148>)
    432a:	6813      	ldr	r3, [r2, #0]
    432c:	6852      	ldr	r2, [r2, #4]
    432e:	18e3      	adds	r3, r4, r3
    4330:	eb45 0202 	adc.w	r2, r5, r2
    4334:	f06f 0101 	mvn.w	r1, #1
    4338:	1ace      	subs	r6, r1, r3
    433a:	eb60 0702 	sbc.w	r7, r0, r2
			to->dticks = MAX(1, ticks);
    433e:	4632      	mov	r2, r6
    4340:	463b      	mov	r3, r7
    4342:	2e01      	cmp	r6, #1
    4344:	f177 0100 	sbcs.w	r1, r7, #0
    4348:	dbb0      	blt.n	42ac <z_add_timeout+0x30>
    434a:	f8ca 2010 	str.w	r2, [sl, #16]
    434e:	f8ca 3014 	str.w	r3, [sl, #20]
		for (t = first(); t != NULL; t = next(t)) {
    4352:	f7ff ff4b 	bl	41ec <first>
    4356:	4684      	mov	ip, r0
    4358:	f1bc 0f00 	cmp.w	ip, #0
    435c:	d0c9      	beq.n	42f2 <z_add_timeout+0x76>
			if (t->dticks > to->dticks) {
    435e:	e9dc 0104 	ldrd	r0, r1, [ip, #16]
    4362:	e9da 2304 	ldrd	r2, r3, [sl, #16]
    4366:	e9cd 2300 	strd	r2, r3, [sp]
    436a:	4282      	cmp	r2, r0
    436c:	418b      	sbcs	r3, r1
    436e:	dbad      	blt.n	42cc <z_add_timeout+0x50>
			to->dticks -= t->dticks;
    4370:	9b00      	ldr	r3, [sp, #0]
    4372:	1a1a      	subs	r2, r3, r0
    4374:	9b01      	ldr	r3, [sp, #4]
    4376:	eb63 0301 	sbc.w	r3, r3, r1
    437a:	f8ca 2010 	str.w	r2, [sl, #16]
    437e:	f8ca 3014 	str.w	r3, [sl, #20]
		for (t = first(); t != NULL; t = next(t)) {
    4382:	4660      	mov	r0, ip
    4384:	f7ff ff3c 	bl	4200 <next>
    4388:	4684      	mov	ip, r0
    438a:	e7e5      	b.n	4358 <z_add_timeout+0xdc>
	sys_dnode_t *const tail = list->tail;
    438c:	4b0e      	ldr	r3, [pc, #56]	; (43c8 <z_add_timeout+0x14c>)
    438e:	685a      	ldr	r2, [r3, #4]
	node->next = list;
    4390:	f8ca 3000 	str.w	r3, [sl]
	node->prev = tail;
    4394:	f8ca 2004 	str.w	r2, [sl, #4]
	tail->next = node;
    4398:	f8c2 a000 	str.w	sl, [r2]
	list->tail = node;
    439c:	f8c3 a004 	str.w	sl, [r3, #4]
}
    43a0:	e7aa      	b.n	42f8 <z_add_timeout+0x7c>
			 * last announcement, and slice_ticks is based
			 * on that. It means that the time remaining for
			 * the next announcement can be less than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    43a2:	f7ff ff45 	bl	4230 <next_timeout>

			if (next_time == 0 ||
    43a6:	4603      	mov	r3, r0
    43a8:	b118      	cbz	r0, 43b2 <z_add_timeout+0x136>
			    _current_cpu->slice_ticks != next_time) {
    43aa:	4a08      	ldr	r2, [pc, #32]	; (43cc <z_add_timeout+0x150>)
    43ac:	6912      	ldr	r2, [r2, #16]
			if (next_time == 0 ||
    43ae:	4282      	cmp	r2, r0
    43b0:	d0a6      	beq.n	4300 <z_add_timeout+0x84>
				sys_clock_set_timeout(next_time, false);
    43b2:	2100      	movs	r1, #0
    43b4:	4618      	mov	r0, r3
    43b6:	f7fd faad 	bl	1914 <sys_clock_set_timeout>
    43ba:	e7a1      	b.n	4300 <z_add_timeout+0x84>
#else
			sys_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    43bc:	b003      	add	sp, #12
    43be:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    43c2:	bf00      	nop
    43c4:	200001e0 	.word	0x200001e0
    43c8:	2000003c 	.word	0x2000003c
    43cc:	200008e4 	.word	0x200008e4

000043d0 <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    43d0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    43d2:	4604      	mov	r4, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    43d4:	f7ff fc7e 	bl	3cd4 <z_time_slice>
	__asm__ volatile(
    43d8:	f04f 0320 	mov.w	r3, #32
    43dc:	f3ef 8511 	mrs	r5, BASEPRI
    43e0:	f383 8811 	msr	BASEPRI, r3
    43e4:	f3bf 8f6f 	isb	sy
#endif

	k_spinlock_key_t key = k_spin_lock(&timeout_lock);

	announce_remaining = ticks;
    43e8:	4b28      	ldr	r3, [pc, #160]	; (448c <sys_clock_announce+0xbc>)
    43ea:	601c      	str	r4, [r3, #0]

	while (first() != NULL && first()->dticks <= announce_remaining) {
    43ec:	f7ff fefe 	bl	41ec <first>
    43f0:	4604      	mov	r4, r0
    43f2:	b350      	cbz	r0, 444a <sys_clock_announce+0x7a>
    43f4:	e9d0 6704 	ldrd	r6, r7, [r0, #16]
    43f8:	4b24      	ldr	r3, [pc, #144]	; (448c <sys_clock_announce+0xbc>)
    43fa:	681b      	ldr	r3, [r3, #0]
    43fc:	17d9      	asrs	r1, r3, #31
    43fe:	42b3      	cmp	r3, r6
    4400:	eb71 0207 	sbcs.w	r2, r1, r7
    4404:	db21      	blt.n	444a <sys_clock_announce+0x7a>
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    4406:	4a22      	ldr	r2, [pc, #136]	; (4490 <sys_clock_announce+0xc0>)
    4408:	e9d2 0100 	ldrd	r0, r1, [r2]
    440c:	1980      	adds	r0, r0, r6
    440e:	eb41 71e6 	adc.w	r1, r1, r6, asr #31
    4412:	e9c2 0100 	strd	r0, r1, [r2]
		announce_remaining -= dt;
    4416:	1b9b      	subs	r3, r3, r6
    4418:	4a1c      	ldr	r2, [pc, #112]	; (448c <sys_clock_announce+0xbc>)
    441a:	6013      	str	r3, [r2, #0]
		t->dticks = 0;
    441c:	2200      	movs	r2, #0
    441e:	2300      	movs	r3, #0
    4420:	e9c4 2304 	strd	r2, r3, [r4, #16]
		remove_timeout(t);
    4424:	4620      	mov	r0, r4
    4426:	f001 f8d0 	bl	55ca <remove_timeout>
	__asm__ volatile(
    442a:	f385 8811 	msr	BASEPRI, r5
    442e:	f3bf 8f6f 	isb	sy

		k_spin_unlock(&timeout_lock, key);
		t->fn(t);
    4432:	68a3      	ldr	r3, [r4, #8]
    4434:	4620      	mov	r0, r4
    4436:	4798      	blx	r3
	__asm__ volatile(
    4438:	f04f 0320 	mov.w	r3, #32
    443c:	f3ef 8511 	mrs	r5, BASEPRI
    4440:	f383 8811 	msr	BASEPRI, r3
    4444:	f3bf 8f6f 	isb	sy
    4448:	e7d0      	b.n	43ec <sys_clock_announce+0x1c>
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
    444a:	b144      	cbz	r4, 445e <sys_clock_announce+0x8e>
		first()->dticks -= announce_remaining;
    444c:	4b0f      	ldr	r3, [pc, #60]	; (448c <sys_clock_announce+0xbc>)
    444e:	6819      	ldr	r1, [r3, #0]
    4450:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    4454:	1a52      	subs	r2, r2, r1
    4456:	eb63 73e1 	sbc.w	r3, r3, r1, asr #31
    445a:	e9c4 2304 	strd	r2, r3, [r4, #16]
	}

	curr_tick += announce_remaining;
    445e:	480c      	ldr	r0, [pc, #48]	; (4490 <sys_clock_announce+0xc0>)
    4460:	490a      	ldr	r1, [pc, #40]	; (448c <sys_clock_announce+0xbc>)
    4462:	680c      	ldr	r4, [r1, #0]
    4464:	e9d0 2300 	ldrd	r2, r3, [r0]
    4468:	1912      	adds	r2, r2, r4
    446a:	eb43 73e4 	adc.w	r3, r3, r4, asr #31
    446e:	e9c0 2300 	strd	r2, r3, [r0]
	announce_remaining = 0;
    4472:	2400      	movs	r4, #0
    4474:	600c      	str	r4, [r1, #0]

	sys_clock_set_timeout(next_timeout(), false);
    4476:	f7ff fedb 	bl	4230 <next_timeout>
    447a:	4621      	mov	r1, r4
    447c:	f7fd fa4a 	bl	1914 <sys_clock_set_timeout>
	__asm__ volatile(
    4480:	f385 8811 	msr	BASEPRI, r5
    4484:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    4488:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    448a:	bf00      	nop
    448c:	20000938 	.word	0x20000938
    4490:	200001e0 	.word	0x200001e0

00004494 <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    4494:	b510      	push	{r4, lr}
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
    4496:	2100      	movs	r1, #0
	__asm__ volatile(
    4498:	f04f 0320 	mov.w	r3, #32
    449c:	f3ef 8411 	mrs	r4, BASEPRI
    44a0:	f383 8811 	msr	BASEPRI, r3
    44a4:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;
    44a8:	2200      	movs	r2, #0
    44aa:	2300      	movs	r3, #0
	LOCKED(&timeout_lock) {
    44ac:	b969      	cbnz	r1, 44ca <sys_clock_tick_get+0x36>
		t = curr_tick + sys_clock_elapsed();
    44ae:	f7fd fa61 	bl	1974 <sys_clock_elapsed>
    44b2:	4b07      	ldr	r3, [pc, #28]	; (44d0 <sys_clock_tick_get+0x3c>)
    44b4:	e9d3 2300 	ldrd	r2, r3, [r3]
    44b8:	1812      	adds	r2, r2, r0
    44ba:	f143 0300 	adc.w	r3, r3, #0
	__asm__ volatile(
    44be:	f384 8811 	msr	BASEPRI, r4
    44c2:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    44c6:	2101      	movs	r1, #1
    44c8:	e7f0      	b.n	44ac <sys_clock_tick_get+0x18>
	}
	return t;
}
    44ca:	4610      	mov	r0, r2
    44cc:	4619      	mov	r1, r3
    44ce:	bd10      	pop	{r4, pc}
    44d0:	200001e0 	.word	0x200001e0

000044d4 <z_timer_expiration_handler>:
 * @param t  Timeout used by the timer.
 *
 * @return N/A
 */
void z_timer_expiration_handler(struct _timeout *t)
{
    44d4:	b510      	push	{r4, lr}
    44d6:	4604      	mov	r4, r0

	/*
	 * if the timer is periodic, start it again; don't add _TICK_ALIGN
	 * since we're already aligned to a tick boundary
	 */
	if (!K_TIMEOUT_EQ(timer->period, K_NO_WAIT) &&
    44d8:	e9d0 230a 	ldrd	r2, r3, [r0, #40]	; 0x28
    44dc:	ea52 0103 	orrs.w	r1, r2, r3
    44e0:	d005      	beq.n	44ee <z_timer_expiration_handler+0x1a>
    44e2:	f1b3 3fff 	cmp.w	r3, #4294967295
    44e6:	bf08      	it	eq
    44e8:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    44ec:	d115      	bne.n	451a <z_timer_expiration_handler+0x46>
		z_add_timeout(&timer->timeout, z_timer_expiration_handler,
			     timer->period);
	}

	/* update timer's status */
	timer->status += 1U;
    44ee:	6b23      	ldr	r3, [r4, #48]	; 0x30
    44f0:	3301      	adds	r3, #1
    44f2:	6323      	str	r3, [r4, #48]	; 0x30

	/* invoke timer expiry function */
	if (timer->expiry_fn != NULL) {
    44f4:	6a23      	ldr	r3, [r4, #32]
    44f6:	b10b      	cbz	r3, 44fc <z_timer_expiration_handler+0x28>
		timer->expiry_fn(timer);
    44f8:	4620      	mov	r0, r4
    44fa:	4798      	blx	r3
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    44fc:	f104 0318 	add.w	r3, r4, #24
	return list->head == list;
    4500:	69a4      	ldr	r4, [r4, #24]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4502:	42a3      	cmp	r3, r4
    4504:	d008      	beq.n	4518 <z_timer_expiration_handler+0x44>
		return;
	}

	thread = z_waitq_head(&timer->wait_q);

	if (thread == NULL) {
    4506:	b13c      	cbz	r4, 4518 <z_timer_expiration_handler+0x44>
	 * place a thread can be taken off this pend queue, and b) the
	 * only place a thread can be put on the pend queue is at
	 * thread level, which of course cannot interrupt the current
	 * context.
	 */
	z_unpend_thread_no_timeout(thread);
    4508:	4620      	mov	r0, r4
    450a:	f000 fef7 	bl	52fc <z_unpend_thread_no_timeout>
    450e:	2300      	movs	r3, #0
    4510:	67a3      	str	r3, [r4, #120]	; 0x78

	arch_thread_return_value_set(thread, 0);

	z_ready_thread(thread);
    4512:	4620      	mov	r0, r4
    4514:	f000 ff80 	bl	5418 <z_ready_thread>
}
    4518:	bd10      	pop	{r4, pc}
		z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    451a:	4902      	ldr	r1, [pc, #8]	; (4524 <z_timer_expiration_handler+0x50>)
    451c:	f7ff feae 	bl	427c <z_add_timeout>
    4520:	e7e5      	b.n	44ee <z_timer_expiration_handler+0x1a>
    4522:	bf00      	nop
    4524:	000044d5 	.word	0x000044d5

00004528 <z_impl_k_timer_start>:
}


void z_impl_k_timer_start(struct k_timer *timer, k_timeout_t duration,
			  k_timeout_t period)
{
    4528:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    452c:	b087      	sub	sp, #28
    452e:	4614      	mov	r4, r2
    4530:	461d      	mov	r5, r3
    4532:	e9dd 8910 	ldrd	r8, r9, [sp, #64]	; 0x40
	SYS_PORT_TRACING_OBJ_FUNC(k_timer, start, timer);

	if (K_TIMEOUT_EQ(duration, K_FOREVER)) {
    4536:	f1b3 3fff 	cmp.w	r3, #4294967295
    453a:	bf08      	it	eq
    453c:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    4540:	d035      	beq.n	45ae <z_impl_k_timer_start+0x86>
    4542:	4606      	mov	r6, r0
    4544:	4613      	mov	r3, r2
    4546:	462a      	mov	r2, r5
	 * for backwards compatibility.  This is unfortunate
	 * (i.e. k_timer_start() doesn't treat its initial sleep
	 * argument the same way k_sleep() does), but historical.  The
	 * timer_api test relies on this behavior.
	 */
	if (!K_TIMEOUT_EQ(period, K_FOREVER) && period.ticks != 0 &&
    4548:	f1b9 3fff 	cmp.w	r9, #4294967295
    454c:	bf08      	it	eq
    454e:	f1b8 3fff 	cmpeq.w	r8, #4294967295
    4552:	d012      	beq.n	457a <z_impl_k_timer_start+0x52>
    4554:	ea58 0109 	orrs.w	r1, r8, r9
    4558:	d00f      	beq.n	457a <z_impl_k_timer_start+0x52>
	    Z_TICK_ABS(period.ticks) < 0) {
    455a:	f06f 0701 	mvn.w	r7, #1
    455e:	ebb7 0708 	subs.w	r7, r7, r8
    4562:	9702      	str	r7, [sp, #8]
    4564:	f04f 31ff 	mov.w	r1, #4294967295
    4568:	eb61 0709 	sbc.w	r7, r1, r9
    456c:	9703      	str	r7, [sp, #12]
	if (!K_TIMEOUT_EQ(period, K_FOREVER) && period.ticks != 0 &&
    456e:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
    4572:	2800      	cmp	r0, #0
    4574:	f171 0100 	sbcs.w	r1, r1, #0
    4578:	db1c      	blt.n	45b4 <z_impl_k_timer_start+0x8c>
		period.ticks = MAX(period.ticks - 1, 1);
	}
	if (Z_TICK_ABS(duration.ticks) < 0) {
    457a:	f06f 0101 	mvn.w	r1, #1
    457e:	ebb1 0a03 	subs.w	sl, r1, r3
    4582:	f04f 31ff 	mov.w	r1, #4294967295
    4586:	eb61 0b02 	sbc.w	fp, r1, r2
    458a:	f1ba 0f00 	cmp.w	sl, #0
    458e:	f17b 0100 	sbcs.w	r1, fp, #0
    4592:	db23      	blt.n	45dc <z_impl_k_timer_start+0xb4>
		duration.ticks = MAX(duration.ticks - 1, 0);
	}

	(void)z_abort_timeout(&timer->timeout);
    4594:	4630      	mov	r0, r6
    4596:	f001 f82f 	bl	55f8 <z_abort_timeout>
	timer->period = period;
    459a:	e9c6 890a 	strd	r8, r9, [r6, #40]	; 0x28
	timer->status = 0U;
    459e:	2300      	movs	r3, #0
    45a0:	6333      	str	r3, [r6, #48]	; 0x30

	z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    45a2:	4622      	mov	r2, r4
    45a4:	462b      	mov	r3, r5
    45a6:	4917      	ldr	r1, [pc, #92]	; (4604 <z_impl_k_timer_start+0xdc>)
    45a8:	4630      	mov	r0, r6
    45aa:	f7ff fe67 	bl	427c <z_add_timeout>
		     duration);
}
    45ae:	b007      	add	sp, #28
    45b0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		period.ticks = MAX(period.ticks - 1, 1);
    45b4:	f118 31ff 	adds.w	r1, r8, #4294967295
    45b8:	9104      	str	r1, [sp, #16]
    45ba:	f149 31ff 	adc.w	r1, r9, #4294967295
    45be:	9105      	str	r1, [sp, #20]
    45c0:	e9dd 7804 	ldrd	r7, r8, [sp, #16]
    45c4:	4638      	mov	r0, r7
    45c6:	4641      	mov	r1, r8
    45c8:	2f01      	cmp	r7, #1
    45ca:	f178 0700 	sbcs.w	r7, r8, #0
    45ce:	db02      	blt.n	45d6 <z_impl_k_timer_start+0xae>
    45d0:	4680      	mov	r8, r0
    45d2:	4689      	mov	r9, r1
    45d4:	e7d1      	b.n	457a <z_impl_k_timer_start+0x52>
    45d6:	2001      	movs	r0, #1
    45d8:	2100      	movs	r1, #0
    45da:	e7f9      	b.n	45d0 <z_impl_k_timer_start+0xa8>
		duration.ticks = MAX(duration.ticks - 1, 0);
    45dc:	f113 33ff 	adds.w	r3, r3, #4294967295
    45e0:	9300      	str	r3, [sp, #0]
    45e2:	f142 33ff 	adc.w	r3, r2, #4294967295
    45e6:	9301      	str	r3, [sp, #4]
    45e8:	e9dd 0100 	ldrd	r0, r1, [sp]
    45ec:	4602      	mov	r2, r0
    45ee:	460b      	mov	r3, r1
    45f0:	2800      	cmp	r0, #0
    45f2:	f171 0100 	sbcs.w	r1, r1, #0
    45f6:	db02      	blt.n	45fe <z_impl_k_timer_start+0xd6>
    45f8:	4614      	mov	r4, r2
    45fa:	461d      	mov	r5, r3
    45fc:	e7ca      	b.n	4594 <z_impl_k_timer_start+0x6c>
    45fe:	2200      	movs	r2, #0
    4600:	4613      	mov	r3, r2
    4602:	e7f9      	b.n	45f8 <z_impl_k_timer_start+0xd0>
    4604:	000044d5 	.word	0x000044d5

00004608 <boot_banner>:
#define BOOT_DELAY_BANNER ""
#endif

#if defined(CONFIG_BOOT_DELAY) || CONFIG_BOOT_DELAY > 0
void boot_banner(void)
{
    4608:	b508      	push	{r3, lr}
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
    460a:	4a03      	ldr	r2, [pc, #12]	; (4618 <boot_banner+0x10>)
    460c:	4903      	ldr	r1, [pc, #12]	; (461c <boot_banner+0x14>)
    460e:	4804      	ldr	r0, [pc, #16]	; (4620 <boot_banner+0x18>)
    4610:	f000 f959 	bl	48c6 <printk>
#else
	printk("*** Booting Zephyr OS version %s %s ***\n",
	       KERNEL_VERSION_STRING, BOOT_DELAY_BANNER);
#endif
#endif
}
    4614:	bd08      	pop	{r3, pc}
    4616:	bf00      	nop
    4618:	00005ab4 	.word	0x00005ab4
    461c:	00005c28 	.word	0x00005c28
    4620:	00005c38 	.word	0x00005c38

00004624 <k_sys_work_q_init>:
			     CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE);

struct k_work_q k_sys_work_q;

static int k_sys_work_q_init(const struct device *dev)
{
    4624:	b510      	push	{r4, lr}
    4626:	b084      	sub	sp, #16
	ARG_UNUSED(dev);
	struct k_work_queue_config cfg = {
    4628:	4b08      	ldr	r3, [pc, #32]	; (464c <k_sys_work_q_init+0x28>)
    462a:	9302      	str	r3, [sp, #8]
    462c:	2400      	movs	r4, #0
    462e:	f88d 400c 	strb.w	r4, [sp, #12]
		.name = "sysworkq",
		.no_yield = IS_ENABLED(CONFIG_SYSTEM_WORKQUEUE_NO_YIELD),
	};

	k_work_queue_start(&k_sys_work_q,
    4632:	ab02      	add	r3, sp, #8
    4634:	9300      	str	r3, [sp, #0]
    4636:	f04f 33ff 	mov.w	r3, #4294967295
    463a:	f44f 6280 	mov.w	r2, #1024	; 0x400
    463e:	4904      	ldr	r1, [pc, #16]	; (4650 <k_sys_work_q_init+0x2c>)
    4640:	4804      	ldr	r0, [pc, #16]	; (4654 <k_sys_work_q_init+0x30>)
    4642:	f7ff f971 	bl	3928 <k_work_queue_start>
			    sys_work_q_stack,
			    K_KERNEL_STACK_SIZEOF(sys_work_q_stack),
			    CONFIG_SYSTEM_WORKQUEUE_PRIORITY, &cfg);
	return 0;
}
    4646:	4620      	mov	r0, r4
    4648:	b004      	add	sp, #16
    464a:	bd10      	pop	{r4, pc}
    464c:	00005c60 	.word	0x00005c60
    4650:	20001698 	.word	0x20001698
    4654:	200001e8 	.word	0x200001e8

00004658 <_ZSt15get_new_handlerv>:
    4658:	4b02      	ldr	r3, [pc, #8]	; (4664 <_ZSt15get_new_handlerv+0xc>)
    465a:	6818      	ldr	r0, [r3, #0]
    465c:	f3bf 8f5b 	dmb	ish
    4660:	4770      	bx	lr
    4662:	bf00      	nop
    4664:	2000093c 	.word	0x2000093c

00004668 <malloc>:
    4668:	4b02      	ldr	r3, [pc, #8]	; (4674 <malloc+0xc>)
    466a:	4601      	mov	r1, r0
    466c:	6818      	ldr	r0, [r3, #0]
    466e:	f000 b859 	b.w	4724 <_malloc_r>
    4672:	bf00      	nop
    4674:	20000044 	.word	0x20000044

00004678 <free>:
    4678:	4b02      	ldr	r3, [pc, #8]	; (4684 <free+0xc>)
    467a:	4601      	mov	r1, r0
    467c:	6818      	ldr	r0, [r3, #0]
    467e:	f000 b803 	b.w	4688 <_free_r>
    4682:	bf00      	nop
    4684:	20000044 	.word	0x20000044

00004688 <_free_r>:
    4688:	b538      	push	{r3, r4, r5, lr}
    468a:	4605      	mov	r5, r0
    468c:	2900      	cmp	r1, #0
    468e:	d045      	beq.n	471c <_free_r+0x94>
    4690:	f851 3c04 	ldr.w	r3, [r1, #-4]
    4694:	1f0c      	subs	r4, r1, #4
    4696:	2b00      	cmp	r3, #0
    4698:	bfb8      	it	lt
    469a:	18e4      	addlt	r4, r4, r3
    469c:	f7fd fcbe 	bl	201c <__malloc_lock>
    46a0:	4a1f      	ldr	r2, [pc, #124]	; (4720 <_free_r+0x98>)
    46a2:	6813      	ldr	r3, [r2, #0]
    46a4:	4610      	mov	r0, r2
    46a6:	b933      	cbnz	r3, 46b6 <_free_r+0x2e>
    46a8:	6063      	str	r3, [r4, #4]
    46aa:	6014      	str	r4, [r2, #0]
    46ac:	4628      	mov	r0, r5
    46ae:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
    46b2:	f7fd bcbf 	b.w	2034 <__malloc_unlock>
    46b6:	42a3      	cmp	r3, r4
    46b8:	d90b      	bls.n	46d2 <_free_r+0x4a>
    46ba:	6821      	ldr	r1, [r4, #0]
    46bc:	1862      	adds	r2, r4, r1
    46be:	4293      	cmp	r3, r2
    46c0:	bf04      	itt	eq
    46c2:	681a      	ldreq	r2, [r3, #0]
    46c4:	685b      	ldreq	r3, [r3, #4]
    46c6:	6063      	str	r3, [r4, #4]
    46c8:	bf04      	itt	eq
    46ca:	1852      	addeq	r2, r2, r1
    46cc:	6022      	streq	r2, [r4, #0]
    46ce:	6004      	str	r4, [r0, #0]
    46d0:	e7ec      	b.n	46ac <_free_r+0x24>
    46d2:	461a      	mov	r2, r3
    46d4:	685b      	ldr	r3, [r3, #4]
    46d6:	b10b      	cbz	r3, 46dc <_free_r+0x54>
    46d8:	42a3      	cmp	r3, r4
    46da:	d9fa      	bls.n	46d2 <_free_r+0x4a>
    46dc:	6811      	ldr	r1, [r2, #0]
    46de:	1850      	adds	r0, r2, r1
    46e0:	42a0      	cmp	r0, r4
    46e2:	d10b      	bne.n	46fc <_free_r+0x74>
    46e4:	6820      	ldr	r0, [r4, #0]
    46e6:	4401      	add	r1, r0
    46e8:	1850      	adds	r0, r2, r1
    46ea:	4283      	cmp	r3, r0
    46ec:	6011      	str	r1, [r2, #0]
    46ee:	d1dd      	bne.n	46ac <_free_r+0x24>
    46f0:	6818      	ldr	r0, [r3, #0]
    46f2:	685b      	ldr	r3, [r3, #4]
    46f4:	6053      	str	r3, [r2, #4]
    46f6:	4401      	add	r1, r0
    46f8:	6011      	str	r1, [r2, #0]
    46fa:	e7d7      	b.n	46ac <_free_r+0x24>
    46fc:	d902      	bls.n	4704 <_free_r+0x7c>
    46fe:	230c      	movs	r3, #12
    4700:	602b      	str	r3, [r5, #0]
    4702:	e7d3      	b.n	46ac <_free_r+0x24>
    4704:	6820      	ldr	r0, [r4, #0]
    4706:	1821      	adds	r1, r4, r0
    4708:	428b      	cmp	r3, r1
    470a:	bf04      	itt	eq
    470c:	6819      	ldreq	r1, [r3, #0]
    470e:	685b      	ldreq	r3, [r3, #4]
    4710:	6063      	str	r3, [r4, #4]
    4712:	bf04      	itt	eq
    4714:	1809      	addeq	r1, r1, r0
    4716:	6021      	streq	r1, [r4, #0]
    4718:	6054      	str	r4, [r2, #4]
    471a:	e7c7      	b.n	46ac <_free_r+0x24>
    471c:	bd38      	pop	{r3, r4, r5, pc}
    471e:	bf00      	nop
    4720:	20000940 	.word	0x20000940

00004724 <_malloc_r>:
    4724:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4726:	1ccd      	adds	r5, r1, #3
    4728:	f025 0503 	bic.w	r5, r5, #3
    472c:	3508      	adds	r5, #8
    472e:	2d0c      	cmp	r5, #12
    4730:	bf38      	it	cc
    4732:	250c      	movcc	r5, #12
    4734:	2d00      	cmp	r5, #0
    4736:	4606      	mov	r6, r0
    4738:	db01      	blt.n	473e <_malloc_r+0x1a>
    473a:	42a9      	cmp	r1, r5
    473c:	d903      	bls.n	4746 <_malloc_r+0x22>
    473e:	230c      	movs	r3, #12
    4740:	6033      	str	r3, [r6, #0]
    4742:	2000      	movs	r0, #0
    4744:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    4746:	f7fd fc69 	bl	201c <__malloc_lock>
    474a:	4921      	ldr	r1, [pc, #132]	; (47d0 <_malloc_r+0xac>)
    474c:	680a      	ldr	r2, [r1, #0]
    474e:	4614      	mov	r4, r2
    4750:	b99c      	cbnz	r4, 477a <_malloc_r+0x56>
    4752:	4f20      	ldr	r7, [pc, #128]	; (47d4 <_malloc_r+0xb0>)
    4754:	683b      	ldr	r3, [r7, #0]
    4756:	b923      	cbnz	r3, 4762 <_malloc_r+0x3e>
    4758:	4621      	mov	r1, r4
    475a:	4630      	mov	r0, r6
    475c:	f000 f83c 	bl	47d8 <_sbrk_r>
    4760:	6038      	str	r0, [r7, #0]
    4762:	4629      	mov	r1, r5
    4764:	4630      	mov	r0, r6
    4766:	f000 f837 	bl	47d8 <_sbrk_r>
    476a:	1c43      	adds	r3, r0, #1
    476c:	d123      	bne.n	47b6 <_malloc_r+0x92>
    476e:	230c      	movs	r3, #12
    4770:	6033      	str	r3, [r6, #0]
    4772:	4630      	mov	r0, r6
    4774:	f7fd fc5e 	bl	2034 <__malloc_unlock>
    4778:	e7e3      	b.n	4742 <_malloc_r+0x1e>
    477a:	6823      	ldr	r3, [r4, #0]
    477c:	1b5b      	subs	r3, r3, r5
    477e:	d417      	bmi.n	47b0 <_malloc_r+0x8c>
    4780:	2b0b      	cmp	r3, #11
    4782:	d903      	bls.n	478c <_malloc_r+0x68>
    4784:	6023      	str	r3, [r4, #0]
    4786:	441c      	add	r4, r3
    4788:	6025      	str	r5, [r4, #0]
    478a:	e004      	b.n	4796 <_malloc_r+0x72>
    478c:	6863      	ldr	r3, [r4, #4]
    478e:	42a2      	cmp	r2, r4
    4790:	bf0c      	ite	eq
    4792:	600b      	streq	r3, [r1, #0]
    4794:	6053      	strne	r3, [r2, #4]
    4796:	4630      	mov	r0, r6
    4798:	f7fd fc4c 	bl	2034 <__malloc_unlock>
    479c:	f104 000b 	add.w	r0, r4, #11
    47a0:	1d23      	adds	r3, r4, #4
    47a2:	f020 0007 	bic.w	r0, r0, #7
    47a6:	1ac2      	subs	r2, r0, r3
    47a8:	d0cc      	beq.n	4744 <_malloc_r+0x20>
    47aa:	1a1b      	subs	r3, r3, r0
    47ac:	50a3      	str	r3, [r4, r2]
    47ae:	e7c9      	b.n	4744 <_malloc_r+0x20>
    47b0:	4622      	mov	r2, r4
    47b2:	6864      	ldr	r4, [r4, #4]
    47b4:	e7cc      	b.n	4750 <_malloc_r+0x2c>
    47b6:	1cc4      	adds	r4, r0, #3
    47b8:	f024 0403 	bic.w	r4, r4, #3
    47bc:	42a0      	cmp	r0, r4
    47be:	d0e3      	beq.n	4788 <_malloc_r+0x64>
    47c0:	1a21      	subs	r1, r4, r0
    47c2:	4630      	mov	r0, r6
    47c4:	f000 f808 	bl	47d8 <_sbrk_r>
    47c8:	3001      	adds	r0, #1
    47ca:	d1dd      	bne.n	4788 <_malloc_r+0x64>
    47cc:	e7cf      	b.n	476e <_malloc_r+0x4a>
    47ce:	bf00      	nop
    47d0:	20000940 	.word	0x20000940
    47d4:	20000944 	.word	0x20000944

000047d8 <_sbrk_r>:
    47d8:	b538      	push	{r3, r4, r5, lr}
    47da:	4d06      	ldr	r5, [pc, #24]	; (47f4 <_sbrk_r+0x1c>)
    47dc:	2300      	movs	r3, #0
    47de:	4604      	mov	r4, r0
    47e0:	4608      	mov	r0, r1
    47e2:	602b      	str	r3, [r5, #0]
    47e4:	f7fd fc04 	bl	1ff0 <_sbrk>
    47e8:	1c43      	adds	r3, r0, #1
    47ea:	d102      	bne.n	47f2 <_sbrk_r+0x1a>
    47ec:	682b      	ldr	r3, [r5, #0]
    47ee:	b103      	cbz	r3, 47f2 <_sbrk_r+0x1a>
    47f0:	6023      	str	r3, [r4, #0]
    47f2:	bd38      	pop	{r3, r4, r5, pc}
    47f4:	20000950 	.word	0x20000950

000047f8 <raise>:
    47f8:	4b02      	ldr	r3, [pc, #8]	; (4804 <raise+0xc>)
    47fa:	4601      	mov	r1, r0
    47fc:	6818      	ldr	r0, [r3, #0]
    47fe:	f000 bfb4 	b.w	576a <_raise_r>
    4802:	bf00      	nop
    4804:	20000044 	.word	0x20000044

00004808 <_kill_r>:
    4808:	b538      	push	{r3, r4, r5, lr}
    480a:	4d07      	ldr	r5, [pc, #28]	; (4828 <_kill_r+0x20>)
    480c:	2300      	movs	r3, #0
    480e:	4604      	mov	r4, r0
    4810:	4608      	mov	r0, r1
    4812:	4611      	mov	r1, r2
    4814:	602b      	str	r3, [r5, #0]
    4816:	f000 fbee 	bl	4ff6 <_kill>
    481a:	1c43      	adds	r3, r0, #1
    481c:	d102      	bne.n	4824 <_kill_r+0x1c>
    481e:	682b      	ldr	r3, [r5, #0]
    4820:	b103      	cbz	r3, 4824 <_kill_r+0x1c>
    4822:	6023      	str	r3, [r4, #0]
    4824:	bd38      	pop	{r3, r4, r5, pc}
    4826:	bf00      	nop
    4828:	20000950 	.word	0x20000950

0000482c <_ZN7MyClassC1Ei>:
#include "my_class.h"

MyClass::MyClass(int number)
    482c:	b538      	push	{r3, r4, r5, lr}
    482e:	4604      	mov	r4, r0
    4830:	460d      	mov	r5, r1
{
        m_number = number;
    4832:	6001      	str	r1, [r0, #0]
        Ptr = new int(number);
    4834:	2004      	movs	r0, #4
    4836:	f000 ff66 	bl	5706 <_Znwj>
    483a:	4603      	mov	r3, r0
    483c:	b100      	cbz	r0, 4840 <_ZN7MyClassC1Ei+0x14>
    483e:	6005      	str	r5, [r0, #0]
    4840:	6063      	str	r3, [r4, #4]
}
    4842:	4620      	mov	r0, r4
    4844:	bd38      	pop	{r3, r4, r5, pc}

00004846 <_ZN7MyClass11addToNumberEi>:


void MyClass::addToNumber(int addend)
{
    4846:	b538      	push	{r3, r4, r5, lr}
        m_number += addend;
    4848:	6803      	ldr	r3, [r0, #0]
    484a:	440b      	add	r3, r1
    484c:	6003      	str	r3, [r0, #0]
        int temp =  clock_control_on(dt, temps);
    484e:	6884      	ldr	r4, [r0, #8]
    4850:	68c5      	ldr	r5, [r0, #12]
 *
 * @return a non-positive integer as documented in device_usable_check().
 */
static inline int z_device_usable_check(const struct device *dev)
{
	return z_device_ready(dev) ? 0 : -ENODEV;
    4852:	4620      	mov	r0, r4
    4854:	f000 fc7c 	bl	5150 <z_device_ready>
    4858:	b120      	cbz	r0, 4864 <_ZN7MyClass11addToNumberEi+0x1e>

	if (ret != 0) {
		return ret;
	}

	const struct clock_control_driver_api *api =
    485a:	68a3      	ldr	r3, [r4, #8]
		(const struct clock_control_driver_api *)dev->api;

	return api->on(dev, sys);
    485c:	681b      	ldr	r3, [r3, #0]
    485e:	4629      	mov	r1, r5
    4860:	4620      	mov	r0, r4
    4862:	4798      	blx	r3
}
    4864:	bd38      	pop	{r3, r4, r5, pc}

00004866 <_ZN7MyClass9getNumberEv>:

int MyClass::getNumber()
{
        return m_number;
}
    4866:	6800      	ldr	r0, [r0, #0]
    4868:	4770      	bx	lr

0000486a <_ZN7MyClassD1Ev>:

MyClass::~MyClass()
    486a:	b510      	push	{r4, lr}
    486c:	4604      	mov	r4, r0
{
       delete Ptr;
    486e:	6840      	ldr	r0, [r0, #4]
    4870:	b108      	cbz	r0, 4876 <_ZN7MyClassD1Ev+0xc>
    4872:	f000 ff46 	bl	5702 <_ZdlPv>
}
    4876:	4620      	mov	r0, r4
    4878:	bd10      	pop	{r4, pc}

0000487a <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    487a:	4602      	mov	r2, r0
    487c:	b158      	cbz	r0, 4896 <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    487e:	6843      	ldr	r3, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    4880:	f003 0303 	and.w	r3, r3, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    4884:	2b01      	cmp	r3, #1
    4886:	d003      	beq.n	4890 <sys_notify_validate+0x16>
    4888:	2b03      	cmp	r3, #3
    488a:	d107      	bne.n	489c <sys_notify_validate+0x22>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    488c:	6803      	ldr	r3, [r0, #0]
    488e:	b143      	cbz	r3, 48a2 <sys_notify_validate+0x28>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    4890:	2000      	movs	r0, #0
    4892:	6090      	str	r0, [r2, #8]
    4894:	4770      	bx	lr
		return -EINVAL;
    4896:	f06f 0015 	mvn.w	r0, #21
    489a:	4770      	bx	lr
	switch (sys_notify_get_method(notify)) {
    489c:	f06f 0015 	mvn.w	r0, #21
    48a0:	4770      	bx	lr
			rv = -EINVAL;
    48a2:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    48a6:	4770      	bx	lr

000048a8 <sys_notify_finalize>:

sys_notify_generic_callback sys_notify_finalize(struct sys_notify *notify,
						    int res)
{
    48a8:	4603      	mov	r3, r0
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    48aa:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    48ac:	f002 0203 	and.w	r2, r2, #3
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    48b0:	6081      	str	r1, [r0, #8]
	switch (method) {
    48b2:	2a03      	cmp	r2, #3
    48b4:	d103      	bne.n	48be <sys_notify_finalize+0x16>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    48b6:	6800      	ldr	r0, [r0, #0]
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    48b8:	2200      	movs	r2, #0
    48ba:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    48bc:	4770      	bx	lr
	sys_notify_generic_callback rv = NULL;
    48be:	2000      	movs	r0, #0
    48c0:	e7fa      	b.n	48b8 <sys_notify_finalize+0x10>

000048c2 <arch_printk_char_out>:
}
    48c2:	2000      	movs	r0, #0
    48c4:	4770      	bx	lr

000048c6 <printk>:
 *
 * @return N/A
 */

void printk(const char *fmt, ...)
{
    48c6:	b40f      	push	{r0, r1, r2, r3}
    48c8:	b500      	push	{lr}
    48ca:	b083      	sub	sp, #12
    48cc:	a904      	add	r1, sp, #16
    48ce:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    48d2:	9101      	str	r1, [sp, #4]

	if (IS_ENABLED(CONFIG_LOG_PRINTK)) {
		log_printk(fmt, ap);
	} else {
		vprintk(fmt, ap);
    48d4:	f7fb fde8 	bl	4a8 <vprintk>
	}
	va_end(ap);
}
    48d8:	b003      	add	sp, #12
    48da:	f85d eb04 	ldr.w	lr, [sp], #4
    48de:	b004      	add	sp, #16
    48e0:	4770      	bx	lr

000048e2 <set_state>:
	mgr->flags = (state & ONOFF_STATE_MASK)
    48e2:	f001 0307 	and.w	r3, r1, #7
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    48e6:	8b81      	ldrh	r1, [r0, #28]
    48e8:	f021 0107 	bic.w	r1, r1, #7
    48ec:	4319      	orrs	r1, r3
	mgr->flags = (state & ONOFF_STATE_MASK)
    48ee:	8381      	strh	r1, [r0, #28]
}
    48f0:	4770      	bx	lr

000048f2 <notify_monitors>:
{
    48f2:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    48f6:	4606      	mov	r6, r0
    48f8:	460f      	mov	r7, r1
    48fa:	4690      	mov	r8, r2
	return list->head;
    48fc:	6881      	ldr	r1, [r0, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    48fe:	b119      	cbz	r1, 4908 <notify_monitors+0x16>
    4900:	460c      	mov	r4, r1
Z_GENLIST_PEEK_NEXT(slist, snode)
    4902:	b131      	cbz	r1, 4912 <notify_monitors+0x20>
	return node->next;
    4904:	680c      	ldr	r4, [r1, #0]
    4906:	e004      	b.n	4912 <notify_monitors+0x20>
    4908:	460c      	mov	r4, r1
    490a:	e002      	b.n	4912 <notify_monitors+0x20>
    490c:	4623      	mov	r3, r4
    490e:	4621      	mov	r1, r4
    4910:	461c      	mov	r4, r3
    4912:	b159      	cbz	r1, 492c <notify_monitors+0x3a>
		mon->callback(mgr, mon, state, res);
    4914:	684d      	ldr	r5, [r1, #4]
    4916:	4643      	mov	r3, r8
    4918:	463a      	mov	r2, r7
    491a:	4630      	mov	r0, r6
    491c:	47a8      	blx	r5
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    491e:	2c00      	cmp	r4, #0
    4920:	d0f4      	beq.n	490c <notify_monitors+0x1a>
    4922:	4623      	mov	r3, r4
Z_GENLIST_PEEK_NEXT(slist, snode)
    4924:	2c00      	cmp	r4, #0
    4926:	d0f2      	beq.n	490e <notify_monitors+0x1c>
	return node->next;
    4928:	6823      	ldr	r3, [r4, #0]
    492a:	e7f0      	b.n	490e <notify_monitors+0x1c>
}
    492c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00004930 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    4930:	8b83      	ldrh	r3, [r0, #28]
	if ((state == ONOFF_STATE_OFF)
    4932:	f013 0307 	ands.w	r3, r3, #7
    4936:	d103      	bne.n	4940 <process_recheck+0x10>
	return list->head;
    4938:	6802      	ldr	r2, [r0, #0]
	    && !sys_slist_is_empty(&mgr->clients)) {
    493a:	b10a      	cbz	r2, 4940 <process_recheck+0x10>
		evt = EVT_START;
    493c:	2003      	movs	r0, #3
    493e:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    4940:	2b02      	cmp	r3, #2
    4942:	d003      	beq.n	494c <process_recheck+0x1c>
	} else if ((state == ONOFF_STATE_ERROR)
    4944:	2b01      	cmp	r3, #1
    4946:	d006      	beq.n	4956 <process_recheck+0x26>
	int evt = EVT_NOP;
    4948:	2000      	movs	r0, #0
    494a:	4770      	bx	lr
		   && (mgr->refs == 0U)) {
    494c:	8bc2      	ldrh	r2, [r0, #30]
    494e:	2a00      	cmp	r2, #0
    4950:	d1f8      	bne.n	4944 <process_recheck+0x14>
		evt = EVT_STOP;
    4952:	2004      	movs	r0, #4
    4954:	4770      	bx	lr
    4956:	6803      	ldr	r3, [r0, #0]
		   && !sys_slist_is_empty(&mgr->clients)) {
    4958:	b10b      	cbz	r3, 495e <process_recheck+0x2e>
		evt = EVT_RESET;
    495a:	2005      	movs	r0, #5
}
    495c:	4770      	bx	lr
	int evt = EVT_NOP;
    495e:	2000      	movs	r0, #0
    4960:	4770      	bx	lr

00004962 <process_complete>:
{
    4962:	b538      	push	{r3, r4, r5, lr}
    4964:	4604      	mov	r4, r0
    4966:	460d      	mov	r5, r1
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    4968:	8b83      	ldrh	r3, [r0, #28]
	if (res < 0) {
    496a:	2a00      	cmp	r2, #0
    496c:	db07      	blt.n	497e <process_complete+0x1c>
    496e:	f003 0307 	and.w	r3, r3, #7
		   || (state == ONOFF_STATE_RESETTING)) {
    4972:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
    4974:	2a01      	cmp	r2, #1
    4976:	d90e      	bls.n	4996 <process_complete+0x34>
	} else if (state == ONOFF_STATE_TO_OFF) {
    4978:	2b04      	cmp	r3, #4
    497a:	d032      	beq.n	49e2 <process_complete+0x80>
}
    497c:	bd38      	pop	{r3, r4, r5, pc}
		*clients = mgr->clients;
    497e:	e9d0 0100 	ldrd	r0, r1, [r0]
    4982:	e885 0003 	stmia.w	r5, {r0, r1}
	list->head = NULL;
    4986:	2300      	movs	r3, #0
    4988:	6023      	str	r3, [r4, #0]
	list->tail = NULL;
    498a:	6063      	str	r3, [r4, #4]
		set_state(mgr, ONOFF_STATE_ERROR);
    498c:	2101      	movs	r1, #1
    498e:	4620      	mov	r0, r4
    4990:	f7ff ffa7 	bl	48e2 <set_state>
    4994:	e7f2      	b.n	497c <process_complete+0x1a>
		*clients = mgr->clients;
    4996:	e9d0 0100 	ldrd	r0, r1, [r0]
    499a:	e885 0003 	stmia.w	r5, {r0, r1}
	list->head = NULL;
    499e:	2200      	movs	r2, #0
    49a0:	6022      	str	r2, [r4, #0]
	list->tail = NULL;
    49a2:	6062      	str	r2, [r4, #4]
		if (state == ONOFF_STATE_TO_ON) {
    49a4:	2b06      	cmp	r3, #6
    49a6:	d117      	bne.n	49d8 <process_complete+0x76>
	return list->head;
    49a8:	682b      	ldr	r3, [r5, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    49aa:	b13b      	cbz	r3, 49bc <process_complete+0x5a>
				mgr->refs += 1U;
    49ac:	8be2      	ldrh	r2, [r4, #30]
    49ae:	3201      	adds	r2, #1
    49b0:	83e2      	strh	r2, [r4, #30]
Z_GENLIST_PEEK_NEXT(slist, snode)
    49b2:	2b00      	cmp	r3, #0
    49b4:	d0f9      	beq.n	49aa <process_complete+0x48>
	return node->next;
    49b6:	681b      	ldr	r3, [r3, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    49b8:	2b00      	cmp	r3, #0
    49ba:	d1f6      	bne.n	49aa <process_complete+0x48>
			set_state(mgr, ONOFF_STATE_ON);
    49bc:	2102      	movs	r1, #2
    49be:	4620      	mov	r0, r4
    49c0:	f7ff ff8f 	bl	48e2 <set_state>
		if (process_recheck(mgr) != EVT_NOP) {
    49c4:	4620      	mov	r0, r4
    49c6:	f7ff ffb3 	bl	4930 <process_recheck>
    49ca:	2800      	cmp	r0, #0
    49cc:	d0d6      	beq.n	497c <process_complete+0x1a>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    49ce:	8ba3      	ldrh	r3, [r4, #28]
    49d0:	f043 0320 	orr.w	r3, r3, #32
    49d4:	83a3      	strh	r3, [r4, #28]
    49d6:	e7d1      	b.n	497c <process_complete+0x1a>
			set_state(mgr, ONOFF_STATE_OFF);
    49d8:	2100      	movs	r1, #0
    49da:	4620      	mov	r0, r4
    49dc:	f7ff ff81 	bl	48e2 <set_state>
    49e0:	e7f0      	b.n	49c4 <process_complete+0x62>
		set_state(mgr, ONOFF_STATE_OFF);
    49e2:	2100      	movs	r1, #0
    49e4:	f7ff ff7d 	bl	48e2 <set_state>
		if (process_recheck(mgr) != EVT_NOP) {
    49e8:	4620      	mov	r0, r4
    49ea:	f7ff ffa1 	bl	4930 <process_recheck>
    49ee:	2800      	cmp	r0, #0
    49f0:	d0c4      	beq.n	497c <process_complete+0x1a>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    49f2:	8ba3      	ldrh	r3, [r4, #28]
    49f4:	f043 0320 	orr.w	r3, r3, #32
    49f8:	83a3      	strh	r3, [r4, #28]
}
    49fa:	e7bf      	b.n	497c <process_complete+0x1a>

000049fc <validate_args>:
	if ((mgr == NULL) || (cli == NULL)) {
    49fc:	b158      	cbz	r0, 4a16 <validate_args+0x1a>
{
    49fe:	b510      	push	{r4, lr}
    4a00:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    4a02:	b159      	cbz	r1, 4a1c <validate_args+0x20>
	int rv = sys_notify_validate(&cli->notify);
    4a04:	1d08      	adds	r0, r1, #4
    4a06:	f7ff ff38 	bl	487a <sys_notify_validate>
	if ((rv == 0)
    4a0a:	b918      	cbnz	r0, 4a14 <validate_args+0x18>
	    && ((cli->notify.flags
    4a0c:	68a3      	ldr	r3, [r4, #8]
    4a0e:	f033 0303 	bics.w	r3, r3, #3
    4a12:	d106      	bne.n	4a22 <validate_args+0x26>
}
    4a14:	bd10      	pop	{r4, pc}
		return -EINVAL;
    4a16:	f06f 0015 	mvn.w	r0, #21
}
    4a1a:	4770      	bx	lr
		return -EINVAL;
    4a1c:	f06f 0015 	mvn.w	r0, #21
    4a20:	e7f8      	b.n	4a14 <validate_args+0x18>
		rv = -EINVAL;
    4a22:	f06f 0015 	mvn.w	r0, #21
    4a26:	e7f5      	b.n	4a14 <validate_args+0x18>

00004a28 <notify_one>:
{
    4a28:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4a2c:	4607      	mov	r7, r0
    4a2e:	460c      	mov	r4, r1
    4a30:	4616      	mov	r6, r2
    4a32:	461d      	mov	r5, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    4a34:	4619      	mov	r1, r3
    4a36:	1d20      	adds	r0, r4, #4
    4a38:	f7ff ff36 	bl	48a8 <sys_notify_finalize>
	if (cb) {
    4a3c:	b128      	cbz	r0, 4a4a <notify_one+0x22>
    4a3e:	4680      	mov	r8, r0
		cb(mgr, cli, state, res);
    4a40:	462b      	mov	r3, r5
    4a42:	4632      	mov	r2, r6
    4a44:	4621      	mov	r1, r4
    4a46:	4638      	mov	r0, r7
    4a48:	47c0      	blx	r8
}
    4a4a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00004a4e <notify_all>:
{
    4a4e:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    4a52:	4681      	mov	r9, r0
    4a54:	460c      	mov	r4, r1
    4a56:	4690      	mov	r8, r2
    4a58:	461f      	mov	r7, r3
	while (!sys_slist_is_empty(list)) {
    4a5a:	e005      	b.n	4a68 <notify_all+0x1a>
	list->tail = node;
    4a5c:	6065      	str	r5, [r4, #4]
		notify_one(mgr, cli, state, res);
    4a5e:	463b      	mov	r3, r7
    4a60:	4642      	mov	r2, r8
    4a62:	4648      	mov	r0, r9
    4a64:	f7ff ffe0 	bl	4a28 <notify_one>
	return list->head;
    4a68:	6821      	ldr	r1, [r4, #0]
	while (!sys_slist_is_empty(list)) {
    4a6a:	b129      	cbz	r1, 4a78 <notify_all+0x2a>
	return node->next;
    4a6c:	680d      	ldr	r5, [r1, #0]
	list->head = node;
    4a6e:	6025      	str	r5, [r4, #0]
	return list->tail;
    4a70:	6866      	ldr	r6, [r4, #4]
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    4a72:	428e      	cmp	r6, r1
    4a74:	d1f3      	bne.n	4a5e <notify_all+0x10>
    4a76:	e7f1      	b.n	4a5c <notify_all+0xe>
}
    4a78:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

00004a7c <transition_complete>:
{
    4a7c:	b510      	push	{r4, lr}
	__asm__ volatile(
    4a7e:	f04f 0420 	mov.w	r4, #32
    4a82:	f3ef 8211 	mrs	r2, BASEPRI
    4a86:	f384 8811 	msr	BASEPRI, r4
    4a8a:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    4a8e:	6181      	str	r1, [r0, #24]
	process_event(mgr, EVT_COMPLETE, key);
    4a90:	2101      	movs	r1, #1
    4a92:	f7fb fd19 	bl	4c8 <process_event>
}
    4a96:	bd10      	pop	{r4, pc}

00004a98 <onoff_manager_init>:
	if ((mgr == NULL)
    4a98:	b170      	cbz	r0, 4ab8 <onoff_manager_init+0x20>
{
    4a9a:	b538      	push	{r3, r4, r5, lr}
    4a9c:	460c      	mov	r4, r1
    4a9e:	4605      	mov	r5, r0
	    || (transitions == NULL)
    4aa0:	b169      	cbz	r1, 4abe <onoff_manager_init+0x26>
	    || (transitions->start == NULL)
    4aa2:	680b      	ldr	r3, [r1, #0]
    4aa4:	b173      	cbz	r3, 4ac4 <onoff_manager_init+0x2c>
	    || (transitions->stop == NULL)) {
    4aa6:	684b      	ldr	r3, [r1, #4]
    4aa8:	b17b      	cbz	r3, 4aca <onoff_manager_init+0x32>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    4aaa:	2220      	movs	r2, #32
    4aac:	2100      	movs	r1, #0
    4aae:	f000 fe54 	bl	575a <memset>
    4ab2:	612c      	str	r4, [r5, #16]
	return 0;
    4ab4:	2000      	movs	r0, #0
}
    4ab6:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    4ab8:	f06f 0015 	mvn.w	r0, #21
}
    4abc:	4770      	bx	lr
		return -EINVAL;
    4abe:	f06f 0015 	mvn.w	r0, #21
    4ac2:	e7f8      	b.n	4ab6 <onoff_manager_init+0x1e>
    4ac4:	f06f 0015 	mvn.w	r0, #21
    4ac8:	e7f5      	b.n	4ab6 <onoff_manager_init+0x1e>
    4aca:	f06f 0015 	mvn.w	r0, #21
    4ace:	e7f2      	b.n	4ab6 <onoff_manager_init+0x1e>

00004ad0 <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    4ad0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4ad2:	4604      	mov	r4, r0
    4ad4:	460f      	mov	r7, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    4ad6:	f7ff ff91 	bl	49fc <validate_args>

	if (rv < 0) {
    4ada:	1e06      	subs	r6, r0, #0
    4adc:	db37      	blt.n	4b4e <onoff_request+0x7e>
    4ade:	f04f 0320 	mov.w	r3, #32
    4ae2:	f3ef 8211 	mrs	r2, BASEPRI
    4ae6:	f383 8811 	msr	BASEPRI, r3
    4aea:	f3bf 8f6f 	isb	sy
		return rv;
	}

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    4aee:	8ba5      	ldrh	r5, [r4, #28]
    4af0:	f005 0507 	and.w	r5, r5, #7

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    4af4:	8be3      	ldrh	r3, [r4, #30]
    4af6:	f64f 71ff 	movw	r1, #65535	; 0xffff
    4afa:	428b      	cmp	r3, r1
    4afc:	d02f      	beq.n	4b5e <onoff_request+0x8e>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
    4afe:	462e      	mov	r6, r5
	if (state == ONOFF_STATE_ON) {
    4b00:	2d02      	cmp	r5, #2
    4b02:	d00c      	beq.n	4b1e <onoff_request+0x4e>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
	} else if ((state == ONOFF_STATE_OFF)
    4b04:	b18d      	cbz	r5, 4b2a <onoff_request+0x5a>
		   || (state == ONOFF_STATE_TO_OFF)
    4b06:	2d04      	cmp	r5, #4
    4b08:	d00f      	beq.n	4b2a <onoff_request+0x5a>
		   || (state == ONOFF_STATE_TO_ON)) {
    4b0a:	2d06      	cmp	r5, #6
    4b0c:	d00d      	beq.n	4b2a <onoff_request+0x5a>
		/* Start if OFF, queue client */
		start = (state == ONOFF_STATE_OFF);
		add_client = true;
	} else if (state == ONOFF_STATE_RESETTING) {
    4b0e:	2d05      	cmp	r5, #5
    4b10:	d01f      	beq.n	4b52 <onoff_request+0x82>
		rv = -ENOTSUP;
	} else {
		__ASSERT_NO_MSG(state == ONOFF_STATE_ERROR);
		rv = -EIO;
    4b12:	f06f 0604 	mvn.w	r6, #4
	bool notify = false;            /* do client notification */
    4b16:	2100      	movs	r1, #0
	bool start = false;             /* trigger a start transition */
    4b18:	460b      	mov	r3, r1
	bool add_client = false;        /* add client to pending list */
    4b1a:	4608      	mov	r0, r1
    4b1c:	e00a      	b.n	4b34 <onoff_request+0x64>
		mgr->refs += 1U;
    4b1e:	3301      	adds	r3, #1
    4b20:	83e3      	strh	r3, [r4, #30]
		notify = true;
    4b22:	2101      	movs	r1, #1
	bool start = false;             /* trigger a start transition */
    4b24:	2300      	movs	r3, #0
	bool add_client = false;        /* add client to pending list */
    4b26:	4618      	mov	r0, r3
    4b28:	e004      	b.n	4b34 <onoff_request+0x64>
		start = (state == ONOFF_STATE_OFF);
    4b2a:	fab5 f385 	clz	r3, r5
    4b2e:	095b      	lsrs	r3, r3, #5
	bool notify = false;            /* do client notification */
    4b30:	2100      	movs	r1, #0
		add_client = true;
    4b32:	2001      	movs	r0, #1
	}

out:
	if (add_client) {
    4b34:	b128      	cbz	r0, 4b42 <onoff_request+0x72>
	parent->next = child;
    4b36:	2000      	movs	r0, #0
    4b38:	6038      	str	r0, [r7, #0]
	return list->tail;
    4b3a:	6860      	ldr	r0, [r4, #4]
Z_GENLIST_APPEND(slist, snode)
    4b3c:	b1a8      	cbz	r0, 4b6a <onoff_request+0x9a>
	parent->next = child;
    4b3e:	6007      	str	r7, [r0, #0]
	list->tail = node;
    4b40:	6067      	str	r7, [r4, #4]
		sys_slist_append(&mgr->clients, &cli->node);
	}

	if (start) {
    4b42:	b9ab      	cbnz	r3, 4b70 <onoff_request+0xa0>
	__asm__ volatile(
    4b44:	f382 8811 	msr	BASEPRI, r2
    4b48:	f3bf 8f6f 	isb	sy
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    4b4c:	b9a9      	cbnz	r1, 4b7a <onoff_request+0xaa>
			notify_one(mgr, cli, state, 0);
		}
	}

	return rv;
}
    4b4e:	4630      	mov	r0, r6
    4b50:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		rv = -ENOTSUP;
    4b52:	f06f 0685 	mvn.w	r6, #133	; 0x85
	bool notify = false;            /* do client notification */
    4b56:	2100      	movs	r1, #0
	bool start = false;             /* trigger a start transition */
    4b58:	460b      	mov	r3, r1
	bool add_client = false;        /* add client to pending list */
    4b5a:	4608      	mov	r0, r1
    4b5c:	e7ea      	b.n	4b34 <onoff_request+0x64>
		rv = -EAGAIN;
    4b5e:	f06f 060a 	mvn.w	r6, #10
	bool notify = false;            /* do client notification */
    4b62:	2100      	movs	r1, #0
	bool start = false;             /* trigger a start transition */
    4b64:	460b      	mov	r3, r1
	bool add_client = false;        /* add client to pending list */
    4b66:	4608      	mov	r0, r1
    4b68:	e7e4      	b.n	4b34 <onoff_request+0x64>
    4b6a:	6067      	str	r7, [r4, #4]
	list->head = node;
    4b6c:	6027      	str	r7, [r4, #0]
}
    4b6e:	e7e8      	b.n	4b42 <onoff_request+0x72>
		process_event(mgr, EVT_RECHECK, key);
    4b70:	2102      	movs	r1, #2
    4b72:	4620      	mov	r0, r4
    4b74:	f7fb fca8 	bl	4c8 <process_event>
    4b78:	e7e9      	b.n	4b4e <onoff_request+0x7e>
			notify_one(mgr, cli, state, 0);
    4b7a:	2300      	movs	r3, #0
    4b7c:	462a      	mov	r2, r5
    4b7e:	4639      	mov	r1, r7
    4b80:	4620      	mov	r0, r4
    4b82:	f7ff ff51 	bl	4a28 <notify_one>
    4b86:	e7e2      	b.n	4b4e <onoff_request+0x7e>

00004b88 <onoff_release>:

int onoff_release(struct onoff_manager *mgr)
{
    4b88:	b510      	push	{r4, lr}
	__asm__ volatile(
    4b8a:	f04f 0320 	mov.w	r3, #32
    4b8e:	f3ef 8211 	mrs	r2, BASEPRI
    4b92:	f383 8811 	msr	BASEPRI, r3
    4b96:	f3bf 8f6f 	isb	sy
	bool stop = false;      /* trigger a stop transition */

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    4b9a:	8b83      	ldrh	r3, [r0, #28]
    4b9c:	f003 0307 	and.w	r3, r3, #7
	int rv = state;

	if (state != ONOFF_STATE_ON) {
    4ba0:	2b02      	cmp	r3, #2
    4ba2:	d007      	beq.n	4bb4 <onoff_release+0x2c>
		if (state == ONOFF_STATE_ERROR) {
    4ba4:	2b01      	cmp	r3, #1
    4ba6:	d002      	beq.n	4bae <onoff_release+0x26>
			rv = -EIO;
		} else {
			rv = -ENOTSUP;
    4ba8:	f06f 0485 	mvn.w	r4, #133	; 0x85
	__ASSERT_NO_MSG(mgr->refs > 0);
	mgr->refs -= 1U;
	stop = (mgr->refs == 0);

out:
	if (stop) {
    4bac:	e008      	b.n	4bc0 <onoff_release+0x38>
			rv = -EIO;
    4bae:	f06f 0404 	mvn.w	r4, #4
    4bb2:	e005      	b.n	4bc0 <onoff_release+0x38>
    4bb4:	461c      	mov	r4, r3
	mgr->refs -= 1U;
    4bb6:	8bc3      	ldrh	r3, [r0, #30]
    4bb8:	3b01      	subs	r3, #1
    4bba:	b29b      	uxth	r3, r3
    4bbc:	83c3      	strh	r3, [r0, #30]
	if (stop) {
    4bbe:	b12b      	cbz	r3, 4bcc <onoff_release+0x44>
	__asm__ volatile(
    4bc0:	f382 8811 	msr	BASEPRI, r2
    4bc4:	f3bf 8f6f 	isb	sy
	} else {
		k_spin_unlock(&mgr->lock, key);
	}

	return rv;
}
    4bc8:	4620      	mov	r0, r4
    4bca:	bd10      	pop	{r4, pc}
		process_event(mgr, EVT_RECHECK, key);
    4bcc:	2102      	movs	r1, #2
    4bce:	f7fb fc7b 	bl	4c8 <process_event>
    4bd2:	e7f9      	b.n	4bc8 <onoff_release+0x40>

00004bd4 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    4bd4:	b508      	push	{r3, lr}
    4bd6:	4604      	mov	r4, r0
    4bd8:	4608      	mov	r0, r1
    4bda:	4611      	mov	r1, r2
	entry(p1, p2, p3);
    4bdc:	461a      	mov	r2, r3
    4bde:	47a0      	blx	r4
	return z_impl_k_current_get();
    4be0:	f7ff fa9a 	bl	4118 <z_impl_k_current_get>
	z_impl_k_thread_abort(thread);
    4be4:	f7fd f968 	bl	1eb8 <z_impl_k_thread_abort>

00004be8 <outs>:
{
    4be8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4bec:	4607      	mov	r7, r0
    4bee:	460e      	mov	r6, r1
    4bf0:	4614      	mov	r4, r2
    4bf2:	4698      	mov	r8, r3
	size_t count = 0;
    4bf4:	2500      	movs	r5, #0
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    4bf6:	e006      	b.n	4c06 <outs+0x1e>
		int rc = out((int)*sp++, ctx);
    4bf8:	4631      	mov	r1, r6
    4bfa:	f814 0b01 	ldrb.w	r0, [r4], #1
    4bfe:	47b8      	blx	r7
		if (rc < 0) {
    4c00:	2800      	cmp	r0, #0
    4c02:	db09      	blt.n	4c18 <outs+0x30>
		++count;
    4c04:	3501      	adds	r5, #1
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    4c06:	4544      	cmp	r4, r8
    4c08:	d3f6      	bcc.n	4bf8 <outs+0x10>
    4c0a:	f1b8 0f00 	cmp.w	r8, #0
    4c0e:	d102      	bne.n	4c16 <outs+0x2e>
    4c10:	7823      	ldrb	r3, [r4, #0]
    4c12:	2b00      	cmp	r3, #0
    4c14:	d1f0      	bne.n	4bf8 <outs+0x10>
	return (int)count;
    4c16:	4628      	mov	r0, r5
}
    4c18:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00004c1c <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_DISASSEMBLY, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_PRINT_MEMORY_USAGE, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    4c1c:	4770      	bx	lr

00004c1e <pm_policy_next_state>:
			return pm_min_residency[i];
		}
	}

	LOG_DBG("No suitable power state found!");
	return (struct pm_state_info){PM_STATE_ACTIVE, 0, 0};
    4c1e:	2200      	movs	r2, #0
    4c20:	6002      	str	r2, [r0, #0]
    4c22:	6042      	str	r2, [r0, #4]
    4c24:	6082      	str	r2, [r0, #8]
}
    4c26:	4770      	bx	lr

00004c28 <get_sub_data>:
	struct nrf_clock_control_data *data = dev->data;
    4c28:	6900      	ldr	r0, [r0, #16]
	return &data->subsys[type];
    4c2a:	eb01 0141 	add.w	r1, r1, r1, lsl #1
    4c2e:	0089      	lsls	r1, r1, #2
    4c30:	3140      	adds	r1, #64	; 0x40
}
    4c32:	4408      	add	r0, r1
    4c34:	4770      	bx	lr

00004c36 <get_sub_config>:
	const struct nrf_clock_control_config *config =
    4c36:	6840      	ldr	r0, [r0, #4]
}
    4c38:	eb00 00c1 	add.w	r0, r0, r1, lsl #3
    4c3c:	4770      	bx	lr

00004c3e <get_onoff_manager>:
	struct nrf_clock_control_data *data = dev->data;
    4c3e:	6900      	ldr	r0, [r0, #16]
}
    4c40:	eb00 1041 	add.w	r0, r0, r1, lsl #5
    4c44:	4770      	bx	lr

00004c46 <get_status>:
{
    4c46:	b508      	push	{r3, lr}
	return GET_STATUS(get_sub_data(dev, type)->flags);
    4c48:	b2c9      	uxtb	r1, r1
    4c4a:	f7ff ffed 	bl	4c28 <get_sub_data>
    4c4e:	6880      	ldr	r0, [r0, #8]
}
    4c50:	f000 0007 	and.w	r0, r0, #7
    4c54:	bd08      	pop	{r3, pc}

00004c56 <set_off_state>:
	__asm__ volatile(
    4c56:	f04f 0320 	mov.w	r3, #32
    4c5a:	f3ef 8211 	mrs	r2, BASEPRI
    4c5e:	f383 8811 	msr	BASEPRI, r3
    4c62:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    4c66:	6803      	ldr	r3, [r0, #0]
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    4c68:	f013 03c0 	ands.w	r3, r3, #192	; 0xc0
    4c6c:	d001      	beq.n	4c72 <set_off_state+0x1c>
    4c6e:	428b      	cmp	r3, r1
    4c70:	d107      	bne.n	4c82 <set_off_state+0x2c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    4c72:	2301      	movs	r3, #1
    4c74:	6003      	str	r3, [r0, #0]
	int err = 0;
    4c76:	2000      	movs	r0, #0
	__asm__ volatile(
    4c78:	f382 8811 	msr	BASEPRI, r2
    4c7c:	f3bf 8f6f 	isb	sy
}
    4c80:	4770      	bx	lr
		err = -EPERM;
    4c82:	f04f 30ff 	mov.w	r0, #4294967295
    4c86:	e7f7      	b.n	4c78 <set_off_state+0x22>

00004c88 <set_starting_state>:
{
    4c88:	b410      	push	{r4}
	__asm__ volatile(
    4c8a:	f04f 0320 	mov.w	r3, #32
    4c8e:	f3ef 8211 	mrs	r2, BASEPRI
    4c92:	f383 8811 	msr	BASEPRI, r3
    4c96:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    4c9a:	6803      	ldr	r3, [r0, #0]
    4c9c:	f003 04c0 	and.w	r4, r3, #192	; 0xc0
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    4ca0:	f003 0307 	and.w	r3, r3, #7
    4ca4:	2b01      	cmp	r3, #1
    4ca6:	d009      	beq.n	4cbc <set_starting_state+0x34>
	} else if (current_ctx != ctx) {
    4ca8:	428c      	cmp	r4, r1
    4caa:	d00a      	beq.n	4cc2 <set_starting_state+0x3a>
		err = -EPERM;
    4cac:	f04f 30ff 	mov.w	r0, #4294967295
	__asm__ volatile(
    4cb0:	f382 8811 	msr	BASEPRI, r2
    4cb4:	f3bf 8f6f 	isb	sy
}
    4cb8:	bc10      	pop	{r4}
    4cba:	4770      	bx	lr
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    4cbc:	6001      	str	r1, [r0, #0]
	int err = 0;
    4cbe:	2000      	movs	r0, #0
    4cc0:	e7f6      	b.n	4cb0 <set_starting_state+0x28>
		err = -EALREADY;
    4cc2:	f06f 0077 	mvn.w	r0, #119	; 0x77
    4cc6:	e7f3      	b.n	4cb0 <set_starting_state+0x28>

00004cc8 <set_on_state>:
	__asm__ volatile(
    4cc8:	f04f 0320 	mov.w	r3, #32
    4ccc:	f3ef 8211 	mrs	r2, BASEPRI
    4cd0:	f383 8811 	msr	BASEPRI, r3
    4cd4:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    4cd8:	6803      	ldr	r3, [r0, #0]
    4cda:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    4cde:	f043 0302 	orr.w	r3, r3, #2
    4ce2:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    4ce4:	f382 8811 	msr	BASEPRI, r2
    4ce8:	f3bf 8f6f 	isb	sy
}
    4cec:	4770      	bx	lr

00004cee <clkstarted_handle>:
{
    4cee:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4cf0:	4606      	mov	r6, r0
    4cf2:	460c      	mov	r4, r1
	struct nrf_clock_control_sub_data *sub_data = get_sub_data(dev, type);
    4cf4:	f7ff ff98 	bl	4c28 <get_sub_data>
	clock_control_cb_t callback = sub_data->cb;
    4cf8:	6805      	ldr	r5, [r0, #0]
	void *user_data = sub_data->user_data;
    4cfa:	6847      	ldr	r7, [r0, #4]
	sub_data->cb = NULL;
    4cfc:	2300      	movs	r3, #0
    4cfe:	f840 3b08 	str.w	r3, [r0], #8
	set_on_state(&sub_data->flags);
    4d02:	f7ff ffe1 	bl	4cc8 <set_on_state>
	if (callback) {
    4d06:	b11d      	cbz	r5, 4d10 <clkstarted_handle+0x22>
		callback(dev, (clock_control_subsys_t)type, user_data);
    4d08:	463a      	mov	r2, r7
    4d0a:	4621      	mov	r1, r4
    4d0c:	4630      	mov	r0, r6
    4d0e:	47a8      	blx	r5
}
    4d10:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00004d12 <stop>:
{
    4d12:	b570      	push	{r4, r5, r6, lr}
    4d14:	4606      	mov	r6, r0
    4d16:	4615      	mov	r5, r2
	enum clock_control_nrf_type type = (enum clock_control_nrf_type)subsys;
    4d18:	b2cc      	uxtb	r4, r1
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    4d1a:	4621      	mov	r1, r4
    4d1c:	f7ff ff84 	bl	4c28 <get_sub_data>
	err = set_off_state(&subdata->flags, ctx);
    4d20:	4629      	mov	r1, r5
    4d22:	3008      	adds	r0, #8
    4d24:	f7ff ff97 	bl	4c56 <set_off_state>
	if (err < 0) {
    4d28:	2800      	cmp	r0, #0
    4d2a:	db06      	blt.n	4d3a <stop+0x28>
	get_sub_config(dev, type)->stop();
    4d2c:	4621      	mov	r1, r4
    4d2e:	4630      	mov	r0, r6
    4d30:	f7ff ff81 	bl	4c36 <get_sub_config>
    4d34:	6843      	ldr	r3, [r0, #4]
    4d36:	4798      	blx	r3
	return 0;
    4d38:	2000      	movs	r0, #0
}
    4d3a:	bd70      	pop	{r4, r5, r6, pc}

00004d3c <api_stop>:
{
    4d3c:	b508      	push	{r3, lr}
	return stop(dev, subsys, CTX_API);
    4d3e:	2280      	movs	r2, #128	; 0x80
    4d40:	f7ff ffe7 	bl	4d12 <stop>
}
    4d44:	bd08      	pop	{r3, pc}

00004d46 <async_start>:
{
    4d46:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4d4a:	4606      	mov	r6, r0
    4d4c:	4690      	mov	r8, r2
    4d4e:	461f      	mov	r7, r3
	enum clock_control_nrf_type type = (enum clock_control_nrf_type)subsys;
    4d50:	b2cd      	uxtb	r5, r1
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    4d52:	4629      	mov	r1, r5
    4d54:	f7ff ff68 	bl	4c28 <get_sub_data>
    4d58:	4604      	mov	r4, r0
	err = set_starting_state(&subdata->flags, ctx);
    4d5a:	9906      	ldr	r1, [sp, #24]
    4d5c:	3008      	adds	r0, #8
    4d5e:	f7ff ff93 	bl	4c88 <set_starting_state>
	if (err < 0) {
    4d62:	2800      	cmp	r0, #0
    4d64:	db09      	blt.n	4d7a <async_start+0x34>
	subdata->cb = cb;
    4d66:	f8c4 8000 	str.w	r8, [r4]
	subdata->user_data = user_data;
    4d6a:	6067      	str	r7, [r4, #4]
	 get_sub_config(dev, type)->start();
    4d6c:	4629      	mov	r1, r5
    4d6e:	4630      	mov	r0, r6
    4d70:	f7ff ff61 	bl	4c36 <get_sub_config>
    4d74:	6803      	ldr	r3, [r0, #0]
    4d76:	4798      	blx	r3
	return 0;
    4d78:	2000      	movs	r0, #0
}
    4d7a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00004d7e <api_start>:
{
    4d7e:	b510      	push	{r4, lr}
    4d80:	b082      	sub	sp, #8
	return async_start(dev, subsys, cb, user_data, CTX_API);
    4d82:	2480      	movs	r4, #128	; 0x80
    4d84:	9400      	str	r4, [sp, #0]
    4d86:	f7ff ffde 	bl	4d46 <async_start>
}
    4d8a:	b002      	add	sp, #8
    4d8c:	bd10      	pop	{r4, pc}

00004d8e <onoff_started_callback>:
{
    4d8e:	b510      	push	{r4, lr}
    4d90:	4614      	mov	r4, r2
	struct onoff_manager *mgr = get_onoff_manager(dev, type);
    4d92:	b2c9      	uxtb	r1, r1
    4d94:	f7ff ff53 	bl	4c3e <get_onoff_manager>
	notify(mgr, 0);
    4d98:	2100      	movs	r1, #0
    4d9a:	47a0      	blx	r4
}
    4d9c:	bd10      	pop	{r4, pc}

00004d9e <hfclk_start>:
{
    4d9e:	b508      	push	{r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    4da0:	2001      	movs	r0, #1
    4da2:	f7fd ffb5 	bl	2d10 <nrfx_clock_start>
}
    4da6:	bd08      	pop	{r3, pc}

00004da8 <lfclk_start>:
{
    4da8:	b508      	push	{r3, lr}
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    4daa:	2000      	movs	r0, #0
    4dac:	f7fd ffb0 	bl	2d10 <nrfx_clock_start>
}
    4db0:	bd08      	pop	{r3, pc}

00004db2 <hfclk_stop>:
{
    4db2:	b508      	push	{r3, lr}
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    4db4:	2001      	movs	r0, #1
    4db6:	f7fd ffcb 	bl	2d50 <nrfx_clock_stop>
}
    4dba:	bd08      	pop	{r3, pc}

00004dbc <blocking_start_callback>:
{
    4dbc:	b508      	push	{r3, lr}
    4dbe:	4610      	mov	r0, r2
	z_impl_k_sem_give(sem);
    4dc0:	f7fe fc3e 	bl	3640 <z_impl_k_sem_give>
}
    4dc4:	bd08      	pop	{r3, pc}

00004dc6 <lfclk_stop>:
{
    4dc6:	b508      	push	{r3, lr}
		z_nrf_clock_calibration_lfclk_stopped();
    4dc8:	f7fc fcdc 	bl	1784 <z_nrf_clock_calibration_lfclk_stopped>
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    4dcc:	2000      	movs	r0, #0
    4dce:	f7fd ffbf 	bl	2d50 <nrfx_clock_stop>
}
    4dd2:	bd08      	pop	{r3, pc}

00004dd4 <clk_release>:
{
    4dd4:	b508      	push	{r3, lr}
	err = onoff_release(mgr);
    4dd6:	f7ff fed7 	bl	4b88 <onoff_release>
}
    4dda:	bd08      	pop	{r3, pc}

00004ddc <clk_request>:
{
    4ddc:	b538      	push	{r3, r4, r5, lr}
	*notify = (struct sys_notify){
    4dde:	2500      	movs	r5, #0
    4de0:	60cd      	str	r5, [r1, #12]
    4de2:	604a      	str	r2, [r1, #4]
    4de4:	2203      	movs	r2, #3
    4de6:	608a      	str	r2, [r1, #8]
	err = onoff_request(mgr, cli);
    4de8:	f7ff fe72 	bl	4ad0 <onoff_request>
}
    4dec:	bd38      	pop	{r3, r4, r5, pc}

00004dee <timeout_handler>:
{
    4dee:	b508      	push	{r3, lr}
	start_cal_process();
    4df0:	f7fc fc8e 	bl	1710 <start_cal_process>
}
    4df4:	bd08      	pop	{r3, pc}

00004df6 <z_nrf_clock_calibration_lfclk_started>:
{
    4df6:	b508      	push	{r3, lr}
	start_unconditional_cal_process();
    4df8:	f7fc fca0 	bl	173c <start_unconditional_cal_process>
}
    4dfc:	bd08      	pop	{r3, pc}

00004dfe <sys_clock_isr>:
/* Weak-linked noop defaults for optional driver interfaces*/

void __weak sys_clock_isr(void *arg)
{
	__ASSERT_NO_MSG(false);
}
    4dfe:	4770      	bx	lr

00004e00 <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
    4e00:	4770      	bx	lr

00004e02 <counter_sub>:
	return (a - b) & COUNTER_MAX;
    4e02:	1a40      	subs	r0, r0, r1
}
    4e04:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
    4e08:	4770      	bx	lr

00004e0a <event_clear>:
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    4e0a:	f100 0350 	add.w	r3, r0, #80	; 0x50
    4e0e:	009b      	lsls	r3, r3, #2
    4e10:	b29b      	uxth	r3, r3
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    4e12:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    4e16:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    4e1a:	2200      	movs	r2, #0
    4e1c:	601a      	str	r2, [r3, #0]
    4e1e:	681b      	ldr	r3, [r3, #0]
}
    4e20:	4770      	bx	lr

00004e22 <set_absolute_alarm>:
{
    4e22:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4e24:	4606      	mov	r6, r0
	uint32_t cc_val = abs_val & COUNTER_MAX;
    4e26:	f021 457f 	bic.w	r5, r1, #4278190080	; 0xff000000
	uint32_t prev_cc = get_comparator(chan);
    4e2a:	f7fc fcc7 	bl	17bc <get_comparator>
    4e2e:	4607      	mov	r7, r0
    4e30:	e019      	b.n	4e66 <set_absolute_alarm+0x44>
	z_impl_k_busy_wait(usec_to_wait);
    4e32:	2013      	movs	r0, #19
    4e34:	f000 fc43 	bl	56be <z_impl_k_busy_wait>
}
    4e38:	e022      	b.n	4e80 <set_absolute_alarm+0x5e>
		event_clear(chan);
    4e3a:	4630      	mov	r0, r6
    4e3c:	f7ff ffe5 	bl	4e0a <event_clear>
		event_enable(chan);
    4e40:	4630      	mov	r0, r6
    4e42:	f7fc fcc3 	bl	17cc <event_enable>
		set_comparator(chan, cc_val);
    4e46:	4629      	mov	r1, r5
    4e48:	4630      	mov	r0, r6
    4e4a:	f7fc fcad 	bl	17a8 <set_comparator>
		now2 = counter();
    4e4e:	f7fc fcd1 	bl	17f4 <counter>
		 (counter_sub(cc_val, now2 + 2) > COUNTER_HALF_SPAN));
    4e52:	4284      	cmp	r4, r0
    4e54:	d01e      	beq.n	4e94 <set_absolute_alarm+0x72>
    4e56:	1c81      	adds	r1, r0, #2
    4e58:	4628      	mov	r0, r5
    4e5a:	f7ff ffd2 	bl	4e02 <counter_sub>
	} while ((now2 != now) &&
    4e5e:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    4e62:	d917      	bls.n	4e94 <set_absolute_alarm+0x72>
		prev_cc = cc_val;
    4e64:	462f      	mov	r7, r5
		now = counter();
    4e66:	f7fc fcc5 	bl	17f4 <counter>
    4e6a:	4604      	mov	r4, r0
		set_comparator(chan, now);
    4e6c:	4601      	mov	r1, r0
    4e6e:	4630      	mov	r0, r6
    4e70:	f7fc fc9a 	bl	17a8 <set_comparator>
		if (counter_sub(prev_cc, now) == 1) {
    4e74:	4621      	mov	r1, r4
    4e76:	4638      	mov	r0, r7
    4e78:	f7ff ffc3 	bl	4e02 <counter_sub>
    4e7c:	2801      	cmp	r0, #1
    4e7e:	d0d8      	beq.n	4e32 <set_absolute_alarm+0x10>
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    4e80:	1ca7      	adds	r7, r4, #2
    4e82:	4639      	mov	r1, r7
    4e84:	4628      	mov	r0, r5
    4e86:	f7ff ffbc 	bl	4e02 <counter_sub>
    4e8a:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    4e8e:	d9d4      	bls.n	4e3a <set_absolute_alarm+0x18>
			cc_val = now + 2;
    4e90:	463d      	mov	r5, r7
    4e92:	e7d2      	b.n	4e3a <set_absolute_alarm+0x18>
}
    4e94:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00004e96 <z_irq_spurious>:
 * called.
 *
 * @return N/A
 */
void z_irq_spurious(const void *unused)
{
    4e96:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    4e98:	2100      	movs	r1, #0
    4e9a:	2001      	movs	r0, #1
    4e9c:	f000 f801 	bl	4ea2 <z_arm_fatal_error>
}
    4ea0:	bd08      	pop	{r3, pc}

00004ea2 <z_arm_fatal_error>:
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
		esf->basic.pc);
}

void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    4ea2:	b508      	push	{r3, lr}

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    4ea4:	f000 f961 	bl	516a <z_fatal_error>
}
    4ea8:	bd08      	pop	{r3, pc}

00004eaa <z_do_kernel_oops>:
 *   fault handler will executed insted of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    4eaa:	b508      	push	{r3, lr}
    4eac:	4601      	mov	r1, r0
	}

#endif /* CONFIG_USERSPACE */

#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	z_arm_fatal_error(reason, esf);
    4eae:	6800      	ldr	r0, [r0, #0]
    4eb0:	f7ff fff7 	bl	4ea2 <z_arm_fatal_error>

	memcpy(&esf_copy, esf, offsetof(z_arch_esf_t, extra_info));
	esf_copy.extra_info = (struct __extra_esf_info) { 0 };
	z_arm_fatal_error(reason, &esf_copy);
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
}
    4eb4:	bd08      	pop	{r3, pc}

00004eb6 <z_arm_nmi>:
 *
 * @return N/A
 */

void z_arm_nmi(void)
{
    4eb6:	b508      	push	{r3, lr}
	handler();
    4eb8:	f7fc fe36 	bl	1b28 <z_SysNmiOnReset>
	z_arm_int_exit();
    4ebc:	f7fc ff9a 	bl	1df4 <z_arm_exc_exit>
}
    4ec0:	bd08      	pop	{r3, pc}

00004ec2 <memory_fault_recoverable>:
}
    4ec2:	2000      	movs	r0, #0
    4ec4:	4770      	bx	lr

00004ec6 <debug_monitor>:
	*recoverable = false;
    4ec6:	2300      	movs	r3, #0
    4ec8:	700b      	strb	r3, [r1, #0]
}
    4eca:	4770      	bx	lr

00004ecc <fault_handle>:
{
    4ecc:	b508      	push	{r3, lr}
	*recoverable = false;
    4ece:	2300      	movs	r3, #0
    4ed0:	7013      	strb	r3, [r2, #0]
	switch (fault) {
    4ed2:	1ecb      	subs	r3, r1, #3
    4ed4:	2b09      	cmp	r3, #9
    4ed6:	d81a      	bhi.n	4f0e <fault_handle+0x42>
    4ed8:	e8df f003 	tbb	[pc, r3]
    4edc:	110d0905 	.word	0x110d0905
    4ee0:	19191919 	.word	0x19191919
    4ee4:	1419      	.short	0x1419
		reason = hard_fault(esf, recoverable);
    4ee6:	4611      	mov	r1, r2
    4ee8:	f7fc fefa 	bl	1ce0 <hard_fault>
		break;
    4eec:	e010      	b.n	4f10 <fault_handle+0x44>
		reason = mem_manage_fault(esf, 0, recoverable);
    4eee:	2100      	movs	r1, #0
    4ef0:	f7fc fe8e 	bl	1c10 <mem_manage_fault>
		break;
    4ef4:	e00c      	b.n	4f10 <fault_handle+0x44>
		reason = bus_fault(esf, 0, recoverable);
    4ef6:	2100      	movs	r1, #0
    4ef8:	f7fc feb6 	bl	1c68 <bus_fault>
		break;
    4efc:	e008      	b.n	4f10 <fault_handle+0x44>
		reason = usage_fault(esf);
    4efe:	f7fc fedd 	bl	1cbc <usage_fault>
		break;
    4f02:	e005      	b.n	4f10 <fault_handle+0x44>
		debug_monitor(esf, recoverable);
    4f04:	4611      	mov	r1, r2
    4f06:	f7ff ffde 	bl	4ec6 <debug_monitor>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    4f0a:	2000      	movs	r0, #0
		break;
    4f0c:	e000      	b.n	4f10 <fault_handle+0x44>
	*recoverable = false;
    4f0e:	2000      	movs	r0, #0
}
    4f10:	bd08      	pop	{r3, pc}

00004f12 <mpu_partition_is_valid>:
		((part->size & (part->size - 1U)) == 0U)
    4f12:	6843      	ldr	r3, [r0, #4]
    4f14:	1e5a      	subs	r2, r3, #1
		&&
    4f16:	4213      	tst	r3, r2
    4f18:	d106      	bne.n	4f28 <mpu_partition_is_valid+0x16>
		&&
    4f1a:	2b1f      	cmp	r3, #31
    4f1c:	d906      	bls.n	4f2c <mpu_partition_is_valid+0x1a>
		((part->start & (part->size - 1U)) == 0U);
    4f1e:	6803      	ldr	r3, [r0, #0]
		&&
    4f20:	421a      	tst	r2, r3
    4f22:	d005      	beq.n	4f30 <mpu_partition_is_valid+0x1e>
    4f24:	2000      	movs	r0, #0
    4f26:	4770      	bx	lr
    4f28:	2000      	movs	r0, #0
    4f2a:	4770      	bx	lr
    4f2c:	2000      	movs	r0, #0
    4f2e:	4770      	bx	lr
    4f30:	2001      	movs	r0, #1
}
    4f32:	4770      	bx	lr

00004f34 <region_allocate_and_init>:
	if (index > (get_num_regions() - 1U)) {
    4f34:	2807      	cmp	r0, #7
    4f36:	d805      	bhi.n	4f44 <region_allocate_and_init+0x10>
{
    4f38:	b510      	push	{r4, lr}
    4f3a:	4604      	mov	r4, r0
	region_init(index, region_conf);
    4f3c:	f7fc ffe0 	bl	1f00 <region_init>
	return index;
    4f40:	4620      	mov	r0, r4
}
    4f42:	bd10      	pop	{r4, pc}
		return -EINVAL;
    4f44:	f06f 0015 	mvn.w	r0, #21
}
    4f48:	4770      	bx	lr

00004f4a <mpu_configure_region>:
{
    4f4a:	b500      	push	{lr}
    4f4c:	b085      	sub	sp, #20
	region_conf.base = new_region->start;
    4f4e:	680b      	ldr	r3, [r1, #0]
    4f50:	9301      	str	r3, [sp, #4]
	get_region_attr_from_mpu_partition_info(&region_conf.attr,
    4f52:	684b      	ldr	r3, [r1, #4]
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    4f54:	688a      	ldr	r2, [r1, #8]
	if (size <= 32U) {
    4f56:	2b20      	cmp	r3, #32
    4f58:	d912      	bls.n	4f80 <mpu_configure_region+0x36>
	if (size > (1UL << 31)) {
    4f5a:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    4f5e:	d811      	bhi.n	4f84 <mpu_configure_region+0x3a>
	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    4f60:	3b01      	subs	r3, #1
    4f62:	fab3 f383 	clz	r3, r3
    4f66:	f1c3 031f 	rsb	r3, r3, #31
    4f6a:	005b      	lsls	r3, r3, #1
    4f6c:	f003 033e 	and.w	r3, r3, #62	; 0x3e
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    4f70:	4313      	orrs	r3, r2
    4f72:	9303      	str	r3, [sp, #12]
	return region_allocate_and_init(index,
    4f74:	a901      	add	r1, sp, #4
    4f76:	f7ff ffdd 	bl	4f34 <region_allocate_and_init>
}
    4f7a:	b005      	add	sp, #20
    4f7c:	f85d fb04 	ldr.w	pc, [sp], #4
		return REGION_32B;
    4f80:	2308      	movs	r3, #8
    4f82:	e7f5      	b.n	4f70 <mpu_configure_region+0x26>
		return REGION_4G;
    4f84:	233e      	movs	r3, #62	; 0x3e
    4f86:	e7f3      	b.n	4f70 <mpu_configure_region+0x26>

00004f88 <mpu_configure_regions>:
{
    4f88:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    4f8c:	4680      	mov	r8, r0
    4f8e:	460f      	mov	r7, r1
    4f90:	4699      	mov	r9, r3
	int reg_index = start_reg_index;
    4f92:	4616      	mov	r6, r2
	for (i = 0; i < regions_num; i++) {
    4f94:	2500      	movs	r5, #0
    4f96:	e009      	b.n	4fac <mpu_configure_regions+0x24>
		reg_index = mpu_configure_region(reg_index, &regions[i]);
    4f98:	4621      	mov	r1, r4
    4f9a:	b2f0      	uxtb	r0, r6
    4f9c:	f7ff ffd5 	bl	4f4a <mpu_configure_region>
    4fa0:	4606      	mov	r6, r0
		if (reg_index == -EINVAL) {
    4fa2:	f110 0f16 	cmn.w	r0, #22
    4fa6:	d014      	beq.n	4fd2 <mpu_configure_regions+0x4a>
		reg_index++;
    4fa8:	3601      	adds	r6, #1
	for (i = 0; i < regions_num; i++) {
    4faa:	3501      	adds	r5, #1
    4fac:	42bd      	cmp	r5, r7
    4fae:	da10      	bge.n	4fd2 <mpu_configure_regions+0x4a>
		if (regions[i].size == 0U) {
    4fb0:	eb05 0445 	add.w	r4, r5, r5, lsl #1
    4fb4:	eb08 0484 	add.w	r4, r8, r4, lsl #2
    4fb8:	6862      	ldr	r2, [r4, #4]
    4fba:	2a00      	cmp	r2, #0
    4fbc:	d0f5      	beq.n	4faa <mpu_configure_regions+0x22>
		if (do_sanity_check &&
    4fbe:	f1b9 0f00 	cmp.w	r9, #0
    4fc2:	d0e9      	beq.n	4f98 <mpu_configure_regions+0x10>
				(!mpu_partition_is_valid(&regions[i]))) {
    4fc4:	4620      	mov	r0, r4
    4fc6:	f7ff ffa4 	bl	4f12 <mpu_partition_is_valid>
		if (do_sanity_check &&
    4fca:	2800      	cmp	r0, #0
    4fcc:	d1e4      	bne.n	4f98 <mpu_configure_regions+0x10>
			return -EINVAL;
    4fce:	f06f 0615 	mvn.w	r6, #21
}
    4fd2:	4630      	mov	r0, r6
    4fd4:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

00004fd8 <arm_core_mpu_configure_static_mpu_regions>:
{
    4fd8:	b508      	push	{r3, lr}
	if (mpu_configure_static_mpu_regions(static_regions, regions_num,
    4fda:	f7fc ffa1 	bl	1f20 <mpu_configure_static_mpu_regions>
}
    4fde:	bd08      	pop	{r3, pc}

00004fe0 <malloc_prepare>:
}
    4fe0:	2000      	movs	r0, #0
    4fe2:	4770      	bx	lr

00004fe4 <_stdout_hook_default>:
}
    4fe4:	f04f 30ff 	mov.w	r0, #4294967295
    4fe8:	4770      	bx	lr

00004fea <_write>:
{
    4fea:	b508      	push	{r3, lr}
    4fec:	4608      	mov	r0, r1
	return z_impl_zephyr_write_stdout(buf, nbytes);
    4fee:	4611      	mov	r1, r2
    4ff0:	f7fc ffda 	bl	1fa8 <z_impl_zephyr_write_stdout>
}
    4ff4:	bd08      	pop	{r3, pc}

00004ff6 <_kill>:
}
    4ff6:	2000      	movs	r0, #0
    4ff8:	4770      	bx	lr

00004ffa <_getpid>:
}
    4ffa:	2000      	movs	r0, #0
    4ffc:	4770      	bx	lr

00004ffe <pm_power_state_set>:
#include <logging/log.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);

/* Invoke Low Power/System Off specific Tasks */
__weak void pm_power_state_set(struct pm_state_info info)
{
    4ffe:	b084      	sub	sp, #16
    5000:	ab04      	add	r3, sp, #16
    5002:	e903 0007 	stmdb	r3, {r0, r1, r2}
	switch (info.state) {
    5006:	f89d 3004 	ldrb.w	r3, [sp, #4]
    500a:	2b06      	cmp	r3, #6
    500c:	d001      	beq.n	5012 <pm_power_state_set+0x14>
		break;
	default:
		LOG_DBG("Unsupported power state %u", info.state);
		break;
	}
}
    500e:	b004      	add	sp, #16
    5010:	4770      	bx	lr
    p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
    5012:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    5016:	2201      	movs	r2, #1
    5018:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  __ASM volatile ("dsb 0xF":::"memory");
    501c:	f3bf 8f4f 	dsb	sy
        __WFE();
    5020:	bf20      	wfe
    while (true)
    5022:	e7fd      	b.n	5020 <pm_power_state_set+0x22>

00005024 <pm_power_state_exit_post_ops>:

/* Handle SOC specific activity after Low Power Mode Exit */
__weak void pm_power_state_exit_post_ops(struct pm_state_info info)
{
    5024:	b084      	sub	sp, #16
    5026:	ab04      	add	r3, sp, #16
    5028:	e903 0007 	stmdb	r3, {r0, r1, r2}
    502c:	2300      	movs	r3, #0
    502e:	f383 8811 	msr	BASEPRI, r3
    5032:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
    5036:	b004      	add	sp, #16
    5038:	4770      	bx	lr

0000503a <gpio_nrfx_port_get_raw>:
	return port->config;
    503a:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    503c:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    503e:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    5042:	600b      	str	r3, [r1, #0]
}
    5044:	2000      	movs	r0, #0
    5046:	4770      	bx	lr

00005048 <gpio_nrfx_port_set_masked_raw>:
	return port->config;
    5048:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    504a:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
    504c:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
    5050:	4042      	eors	r2, r0
    5052:	400a      	ands	r2, r1
    5054:	4042      	eors	r2, r0
    p_reg->OUT = value;
    5056:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
}
    505a:	2000      	movs	r0, #0
    505c:	4770      	bx	lr

0000505e <gpio_nrfx_port_set_bits_raw>:
	return port->config;
    505e:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5060:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTSET = set_mask;
    5062:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
}
    5066:	2000      	movs	r0, #0
    5068:	4770      	bx	lr

0000506a <gpio_nrfx_port_clear_bits_raw>:
	return port->config;
    506a:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    506c:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTCLR = clr_mask;
    506e:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
}
    5072:	2000      	movs	r0, #0
    5074:	4770      	bx	lr

00005076 <gpio_nrfx_port_toggle_bits>:
	return port->config;
    5076:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5078:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    507a:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value ^ mask);
    507e:	404b      	eors	r3, r1
    p_reg->OUT = value;
    5080:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
}
    5084:	2000      	movs	r0, #0
    5086:	4770      	bx	lr

00005088 <gpio_nrfx_manage_callback>:
{
    5088:	b470      	push	{r4, r5, r6}
	return port->data;
    508a:	6900      	ldr	r0, [r0, #16]
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    508c:	1d05      	adds	r5, r0, #4
	return list->head;
    508e:	6843      	ldr	r3, [r0, #4]
	if (!sys_slist_is_empty(callbacks)) {
    5090:	b1db      	cbz	r3, 50ca <gpio_nrfx_manage_callback+0x42>
		if (!sys_slist_find_and_remove(callbacks, &callback->node)) {
    5092:	460e      	mov	r6, r1
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    5094:	2400      	movs	r4, #0
    5096:	e00a      	b.n	50ae <gpio_nrfx_manage_callback+0x26>
	return node->next;
    5098:	680b      	ldr	r3, [r1, #0]
	list->head = node;
    509a:	6043      	str	r3, [r0, #4]
	return list->tail;
    509c:	686c      	ldr	r4, [r5, #4]
Z_GENLIST_REMOVE(slist, snode)
    509e:	42a1      	cmp	r1, r4
    50a0:	d10f      	bne.n	50c2 <gpio_nrfx_manage_callback+0x3a>
	list->tail = node;
    50a2:	606b      	str	r3, [r5, #4]
}
    50a4:	e00d      	b.n	50c2 <gpio_nrfx_manage_callback+0x3a>
	list->tail = node;
    50a6:	606c      	str	r4, [r5, #4]
}
    50a8:	e00b      	b.n	50c2 <gpio_nrfx_manage_callback+0x3a>
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    50aa:	461c      	mov	r4, r3
    50ac:	681b      	ldr	r3, [r3, #0]
    50ae:	b15b      	cbz	r3, 50c8 <gpio_nrfx_manage_callback+0x40>
    50b0:	429e      	cmp	r6, r3
    50b2:	d1fa      	bne.n	50aa <gpio_nrfx_manage_callback+0x22>
Z_GENLIST_REMOVE(slist, snode)
    50b4:	2c00      	cmp	r4, #0
    50b6:	d0ef      	beq.n	5098 <gpio_nrfx_manage_callback+0x10>
	return node->next;
    50b8:	680b      	ldr	r3, [r1, #0]
	parent->next = child;
    50ba:	6023      	str	r3, [r4, #0]
	return list->tail;
    50bc:	686b      	ldr	r3, [r5, #4]
Z_GENLIST_REMOVE(slist, snode)
    50be:	4299      	cmp	r1, r3
    50c0:	d0f1      	beq.n	50a6 <gpio_nrfx_manage_callback+0x1e>
	parent->next = child;
    50c2:	2300      	movs	r3, #0
    50c4:	600b      	str	r3, [r1, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    50c6:	e000      	b.n	50ca <gpio_nrfx_manage_callback+0x42>
			if (!set) {
    50c8:	b152      	cbz	r2, 50e0 <gpio_nrfx_manage_callback+0x58>
	if (set) {
    50ca:	b162      	cbz	r2, 50e6 <gpio_nrfx_manage_callback+0x5e>
	return list->head;
    50cc:	6843      	ldr	r3, [r0, #4]
	parent->next = child;
    50ce:	600b      	str	r3, [r1, #0]
	list->head = node;
    50d0:	6041      	str	r1, [r0, #4]
	return list->tail;
    50d2:	686b      	ldr	r3, [r5, #4]
Z_GENLIST_PREPEND(slist, snode)
    50d4:	b10b      	cbz	r3, 50da <gpio_nrfx_manage_callback+0x52>
	return 0;
    50d6:	2000      	movs	r0, #0
    50d8:	e006      	b.n	50e8 <gpio_nrfx_manage_callback+0x60>
	list->tail = node;
    50da:	6069      	str	r1, [r5, #4]
    50dc:	2000      	movs	r0, #0
}
    50de:	e003      	b.n	50e8 <gpio_nrfx_manage_callback+0x60>
				return -EINVAL;
    50e0:	f06f 0015 	mvn.w	r0, #21
    50e4:	e000      	b.n	50e8 <gpio_nrfx_manage_callback+0x60>
	return 0;
    50e6:	2000      	movs	r0, #0
}
    50e8:	bc70      	pop	{r4, r5, r6}
    50ea:	4770      	bx	lr

000050ec <uart_nrfx_config_get>:
{
    50ec:	460b      	mov	r3, r1
	return dev->data;
    50ee:	6902      	ldr	r2, [r0, #16]
	*cfg = get_dev_data(dev)->uart_config;
    50f0:	e892 0003 	ldmia.w	r2, {r0, r1}
    50f4:	e883 0003 	stmia.w	r3, {r0, r1}
}
    50f8:	2000      	movs	r0, #0
    50fa:	4770      	bx	lr

000050fc <k_sys_fatal_error_handler>:

extern void sys_arch_reboot(int type);

void k_sys_fatal_error_handler(unsigned int reason,
			       const z_arch_esf_t *esf)
{
    50fc:	b508      	push	{r3, lr}
	z_spm_ns_fatal_error_handler();
#endif

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
		sys_arch_reboot(0);
    50fe:	2000      	movs	r0, #0
    5100:	f7fc ffb8 	bl	2074 <sys_arch_reboot>

00005104 <nrfx_isr>:

#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
    5104:	b508      	push	{r3, lr}
	((nrfx_irq_handler_t)irq_handler)();
    5106:	4780      	blx	r0
}
    5108:	bd08      	pop	{r3, pc}

0000510a <nrfx_busy_wait>:

void nrfx_busy_wait(uint32_t usec_to_wait)
{
    510a:	b508      	push	{r3, lr}
	z_impl_k_busy_wait(usec_to_wait);
    510c:	f000 fad7 	bl	56be <z_impl_k_busy_wait>
	k_busy_wait(usec_to_wait);
}
    5110:	bd08      	pop	{r3, pc}

00005112 <nrfx_clock_enable>:
{
    5112:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    5114:	2000      	movs	r0, #0
    5116:	f7fc fc95 	bl	1a44 <arch_irq_is_enabled>
    511a:	b128      	cbz	r0, 5128 <nrfx_clock_enable+0x16>
}

NRF_STATIC_INLINE void nrf_clock_lf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_lfclk_t source)
{
    p_reg->LFCLKSRC = (uint32_t)(source);
    511c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    5120:	2200      	movs	r2, #0
    5122:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    5126:	bd08      	pop	{r3, pc}
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    5128:	f7fc fc7c 	bl	1a24 <arch_irq_enable>
    512c:	e7f6      	b.n	511c <nrfx_clock_enable+0xa>

0000512e <is_app_channel>:
    return NRFX_GPIOTE_APP_CHANNELS_MASK & (1UL << index);
    512e:	2301      	movs	r3, #1
    5130:	4083      	lsls	r3, r0
    5132:	f013 0fff 	tst.w	r3, #255	; 0xff
}
    5136:	bf14      	ite	ne
    5138:	2001      	movne	r0, #1
    513a:	2000      	moveq	r0, #0
    513c:	4770      	bx	lr

0000513e <SEGGER_RTT_Init>:
*  Function description
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
    513e:	b508      	push	{r3, lr}
  _DoInit();
    5140:	f7fd ff8e 	bl	3060 <_DoInit>
}
    5144:	bd08      	pop	{r3, pc}

00005146 <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(const struct device *unused)
{
    5146:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	SEGGER_RTT_Init();
    5148:	f7ff fff9 	bl	513e <SEGGER_RTT_Init>

	return 0;
}
    514c:	2000      	movs	r0, #0
    514e:	bd08      	pop	{r3, pc}

00005150 <z_device_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    5150:	b148      	cbz	r0, 5166 <z_device_ready+0x16>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    5152:	68c3      	ldr	r3, [r0, #12]
    5154:	8818      	ldrh	r0, [r3, #0]
    5156:	f3c0 0008 	ubfx	r0, r0, #0, #9
    515a:	f5b0 7f80 	cmp.w	r0, #256	; 0x100
    515e:	bf14      	ite	ne
    5160:	2000      	movne	r0, #0
    5162:	2001      	moveq	r0, #1
    5164:	4770      	bx	lr
		return false;
    5166:	2000      	movs	r0, #0
}
    5168:	4770      	bx	lr

0000516a <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    516a:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    516c:	4605      	mov	r5, r0
    516e:	460e      	mov	r6, r1
	__asm__ volatile(
    5170:	f04f 0320 	mov.w	r3, #32
    5174:	f3ef 8711 	mrs	r7, BASEPRI
    5178:	f383 8811 	msr	BASEPRI, r3
    517c:	f3bf 8f6f 	isb	sy
	return z_impl_k_current_get();
    5180:	f7fe ffca 	bl	4118 <z_impl_k_current_get>
    5184:	4604      	mov	r4, r0
	LOG_ERR("Current thread: %p (%s)", thread,
		log_strdup(thread_name_get(thread)));

	coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    5186:	4631      	mov	r1, r6
    5188:	4628      	mov	r0, r5
    518a:	f7ff ffb7 	bl	50fc <k_sys_fatal_error_handler>
	__asm__ volatile(
    518e:	f387 8811 	msr	BASEPRI, r7
    5192:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    5196:	4620      	mov	r0, r4
    5198:	f7fc fe8e 	bl	1eb8 <z_impl_k_thread_abort>
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    519c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

0000519e <setup_thread_stack>:
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    519e:	3207      	adds	r2, #7
    51a0:	f022 0207 	bic.w	r2, r2, #7
	new_thread->stack_info.start = (uintptr_t)stack_buf_start;
    51a4:	6641      	str	r1, [r0, #100]	; 0x64
	new_thread->stack_info.size = stack_buf_size;
    51a6:	6682      	str	r2, [r0, #104]	; 0x68
	new_thread->stack_info.delta = delta;
    51a8:	2300      	movs	r3, #0
    51aa:	66c3      	str	r3, [r0, #108]	; 0x6c
}
    51ac:	1888      	adds	r0, r1, r2
    51ae:	4770      	bx	lr

000051b0 <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    51b0:	f3ef 8005 	mrs	r0, IPSR
}
    51b4:	3800      	subs	r0, #0
    51b6:	bf18      	it	ne
    51b8:	2001      	movne	r0, #1
    51ba:	4770      	bx	lr

000051bc <z_impl_k_thread_name_set>:
}
    51bc:	f06f 0057 	mvn.w	r0, #87	; 0x57
    51c0:	4770      	bx	lr

000051c2 <z_impl_k_thread_start>:
{
    51c2:	b508      	push	{r3, lr}
	z_sched_start(thread);
    51c4:	f7fe fe12 	bl	3dec <z_sched_start>
}
    51c8:	bd08      	pop	{r3, pc}

000051ca <z_init_thread_base>:
#endif

void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
    51ca:	b410      	push	{r4}
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
    51cc:	2400      	movs	r4, #0
    51ce:	6084      	str	r4, [r0, #8]
	thread_base->user_options = (uint8_t)options;
    51d0:	7303      	strb	r3, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    51d2:	7342      	strb	r2, [r0, #13]

	thread_base->prio = priority;
    51d4:	7381      	strb	r1, [r0, #14]

	thread_base->sched_locked = 0U;
    51d6:	73c4      	strb	r4, [r0, #15]
	node->next = NULL;
    51d8:	6184      	str	r4, [r0, #24]
	node->prev = NULL;
    51da:	61c4      	str	r4, [r0, #28]
#endif

	/* swap_data does not need to be initialized */

	z_init_thread_timeout(thread_base);
}
    51dc:	bc10      	pop	{r4}
    51de:	4770      	bx	lr

000051e0 <z_impl_k_thread_create>:
{
    51e0:	b5f0      	push	{r4, r5, r6, r7, lr}
    51e2:	b087      	sub	sp, #28
    51e4:	4604      	mov	r4, r0
    51e6:	e9dd 6712 	ldrd	r6, r7, [sp, #72]	; 0x48
	z_setup_new_thread(new_thread, stack, stack_size, entry, p1, p2, p3,
    51ea:	2500      	movs	r5, #0
    51ec:	9505      	str	r5, [sp, #20]
    51ee:	9d10      	ldr	r5, [sp, #64]	; 0x40
    51f0:	9504      	str	r5, [sp, #16]
    51f2:	9d0f      	ldr	r5, [sp, #60]	; 0x3c
    51f4:	9503      	str	r5, [sp, #12]
    51f6:	9d0e      	ldr	r5, [sp, #56]	; 0x38
    51f8:	9502      	str	r5, [sp, #8]
    51fa:	9d0d      	ldr	r5, [sp, #52]	; 0x34
    51fc:	9501      	str	r5, [sp, #4]
    51fe:	9d0c      	ldr	r5, [sp, #48]	; 0x30
    5200:	9500      	str	r5, [sp, #0]
    5202:	f7fe f8c5 	bl	3390 <z_setup_new_thread>
	if (!K_TIMEOUT_EQ(delay, K_FOREVER)) {
    5206:	f1b7 3fff 	cmp.w	r7, #4294967295
    520a:	bf08      	it	eq
    520c:	f1b6 3fff 	cmpeq.w	r6, #4294967295
    5210:	d102      	bne.n	5218 <z_impl_k_thread_create+0x38>
}
    5212:	4620      	mov	r0, r4
    5214:	b007      	add	sp, #28
    5216:	bdf0      	pop	{r4, r5, r6, r7, pc}
		schedule_new_thread(new_thread, delay);
    5218:	4632      	mov	r2, r6
    521a:	463b      	mov	r3, r7
    521c:	4620      	mov	r0, r4
    521e:	f7fe f8a5 	bl	336c <schedule_new_thread>
    5222:	e7f6      	b.n	5212 <z_impl_k_thread_create+0x32>

00005224 <z_pm_save_idle_exit>:

void z_pm_save_idle_exit(int32_t ticks)
{
    5224:	b508      	push	{r3, lr}
	/* Some CPU low power states require notification at the ISR
	 * to allow any operations that needs to be done before kernel
	 * switches task or processes nested interrupts.
	 * This can be simply ignored if not required.
	 */
	pm_system_resume();
    5226:	f7fb ff89 	bl	113c <pm_system_resume>
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
    522a:	f7ff fde9 	bl	4e00 <sys_clock_idle_exit>
}
    522e:	bd08      	pop	{r3, pc}

00005230 <idle>:

void idle(void *unused1, void *unused2, void *unused3)
{
    5230:	b508      	push	{r3, lr}
	__asm__ volatile(
    5232:	f04f 0220 	mov.w	r2, #32
    5236:	f3ef 8311 	mrs	r3, BASEPRI
    523a:	f382 8811 	msr	BASEPRI, r2
    523e:	f3bf 8f6f 	isb	sy
		 * higher level construct.
		 */
		(void) arch_irq_lock();

		if (IS_ENABLED(CONFIG_PM)) {
			pm_save_idle();
    5242:	f7fe f923 	bl	348c <pm_save_idle>
    5246:	e7f4      	b.n	5232 <idle+0x2>

00005248 <new_prio_for_inheritance>:
	int new_prio = z_is_prio_higher(target, limit) ? target : limit;
    5248:	4288      	cmp	r0, r1
    524a:	da00      	bge.n	524e <new_prio_for_inheritance+0x6>
    524c:	4601      	mov	r1, r0
	return z_is_under_prio_ceiling(prio) ? prio : CONFIG_PRIORITY_CEILING;
    524e:	f111 0f7f 	cmn.w	r1, #127	; 0x7f
    5252:	db01      	blt.n	5258 <new_prio_for_inheritance+0x10>
    5254:	4608      	mov	r0, r1
    5256:	4770      	bx	lr
    5258:	f06f 007e 	mvn.w	r0, #126	; 0x7e
}
    525c:	4770      	bx	lr

0000525e <adjust_owner_prio>:
{
    525e:	b508      	push	{r3, lr}
	if (mutex->owner->base.prio != new_prio) {
    5260:	6880      	ldr	r0, [r0, #8]
    5262:	f990 300e 	ldrsb.w	r3, [r0, #14]
    5266:	428b      	cmp	r3, r1
    5268:	d101      	bne.n	526e <adjust_owner_prio+0x10>
	return false;
    526a:	2000      	movs	r0, #0
}
    526c:	bd08      	pop	{r3, pc}
		return z_set_prio(mutex->owner, new_prio);
    526e:	f7fe fddb 	bl	3e28 <z_set_prio>
    5272:	e7fb      	b.n	526c <adjust_owner_prio+0xe>

00005274 <z_impl_k_mutex_init>:
{
    5274:	4603      	mov	r3, r0
	mutex->owner = NULL;
    5276:	2000      	movs	r0, #0
    5278:	6098      	str	r0, [r3, #8]
	mutex->lock_count = 0U;
    527a:	60d8      	str	r0, [r3, #12]
	list->head = (sys_dnode_t *)list;
    527c:	601b      	str	r3, [r3, #0]
	list->tail = (sys_dnode_t *)list;
    527e:	605b      	str	r3, [r3, #4]
}
    5280:	4770      	bx	lr

00005282 <z_impl_k_sem_init>:
	CHECKIF(limit == 0U || limit > K_SEM_MAX_LIMIT || initial_count > limit) {
    5282:	b13a      	cbz	r2, 5294 <z_impl_k_sem_init+0x12>
    5284:	428a      	cmp	r2, r1
    5286:	d308      	bcc.n	529a <z_impl_k_sem_init+0x18>
	sem->count = initial_count;
    5288:	6081      	str	r1, [r0, #8]
	sem->limit = limit;
    528a:	60c2      	str	r2, [r0, #12]
	list->head = (sys_dnode_t *)list;
    528c:	6000      	str	r0, [r0, #0]
	list->tail = (sys_dnode_t *)list;
    528e:	6040      	str	r0, [r0, #4]
	return 0;
    5290:	2000      	movs	r0, #0
    5292:	4770      	bx	lr
		return -EINVAL;
    5294:	f06f 0015 	mvn.w	r0, #21
    5298:	4770      	bx	lr
    529a:	f06f 0015 	mvn.w	r0, #21
}
    529e:	4770      	bx	lr

000052a0 <k_work_submit_to_queue>:
{
    52a0:	b530      	push	{r4, r5, lr}
    52a2:	b083      	sub	sp, #12
    52a4:	9001      	str	r0, [sp, #4]
    52a6:	4608      	mov	r0, r1
    52a8:	f04f 0320 	mov.w	r3, #32
    52ac:	f3ef 8511 	mrs	r5, BASEPRI
    52b0:	f383 8811 	msr	BASEPRI, r3
    52b4:	f3bf 8f6f 	isb	sy
	int ret = submit_to_queue_locked(work, &queue);
    52b8:	a901      	add	r1, sp, #4
    52ba:	f7fe fa0d 	bl	36d8 <submit_to_queue_locked>
    52be:	4604      	mov	r4, r0
	__asm__ volatile(
    52c0:	f385 8811 	msr	BASEPRI, r5
    52c4:	f3bf 8f6f 	isb	sy
	if ((ret > 0) && (k_is_preempt_thread() != 0)) {
    52c8:	2800      	cmp	r0, #0
    52ca:	dc02      	bgt.n	52d2 <k_work_submit_to_queue+0x32>
}
    52cc:	4620      	mov	r0, r4
    52ce:	b003      	add	sp, #12
    52d0:	bd30      	pop	{r4, r5, pc}
	return z_impl_k_is_preempt_thread();
    52d2:	f7fe ff27 	bl	4124 <z_impl_k_is_preempt_thread>
	if ((ret > 0) && (k_is_preempt_thread() != 0)) {
    52d6:	2800      	cmp	r0, #0
    52d8:	d0f8      	beq.n	52cc <k_work_submit_to_queue+0x2c>
	z_impl_k_yield();
    52da:	f7fe fe5d 	bl	3f98 <z_impl_k_yield>
	return ret;
    52de:	e7f5      	b.n	52cc <k_work_submit_to_queue+0x2c>

000052e0 <thread_active_elsewhere>:
}
    52e0:	2000      	movs	r0, #0
    52e2:	4770      	bx	lr

000052e4 <pended_on_thread>:
}
    52e4:	6880      	ldr	r0, [r0, #8]
    52e6:	4770      	bx	lr

000052e8 <z_sched_prio_cmp>:
	int32_t b1 = thread_1->base.prio;
    52e8:	f990 300e 	ldrsb.w	r3, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    52ec:	f991 000e 	ldrsb.w	r0, [r1, #14]
	if (b1 != b2) {
    52f0:	4283      	cmp	r3, r0
    52f2:	d001      	beq.n	52f8 <z_sched_prio_cmp+0x10>
		return b2 - b1;
    52f4:	1ac0      	subs	r0, r0, r3
    52f6:	4770      	bx	lr
	return 0;
    52f8:	2000      	movs	r0, #0
}
    52fa:	4770      	bx	lr

000052fc <z_unpend_thread_no_timeout>:
{
    52fc:	b538      	push	{r3, r4, r5, lr}
    52fe:	4604      	mov	r4, r0
	LOCKED(&sched_spinlock) {
    5300:	2300      	movs	r3, #0
	__asm__ volatile(
    5302:	f04f 0220 	mov.w	r2, #32
    5306:	f3ef 8511 	mrs	r5, BASEPRI
    530a:	f382 8811 	msr	BASEPRI, r2
    530e:	f3bf 8f6f 	isb	sy
    5312:	b98b      	cbnz	r3, 5338 <z_unpend_thread_no_timeout+0x3c>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    5314:	4620      	mov	r0, r4
    5316:	f7ff ffe5 	bl	52e4 <pended_on_thread>
    531a:	4621      	mov	r1, r4
    531c:	f000 f822 	bl	5364 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    5320:	7b63      	ldrb	r3, [r4, #13]
    5322:	f023 0302 	bic.w	r3, r3, #2
    5326:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    5328:	2300      	movs	r3, #0
    532a:	60a3      	str	r3, [r4, #8]
	__asm__ volatile(
    532c:	f385 8811 	msr	BASEPRI, r5
    5330:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    5334:	2301      	movs	r3, #1
    5336:	e7ec      	b.n	5312 <z_unpend_thread_no_timeout+0x16>
}
    5338:	bd38      	pop	{r3, r4, r5, pc}

0000533a <z_reschedule_irqlock>:
{
    533a:	b508      	push	{r3, lr}
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    533c:	4603      	mov	r3, r0
    533e:	b920      	cbnz	r0, 534a <z_reschedule_irqlock+0x10>
    5340:	f3ef 8205 	mrs	r2, IPSR
    5344:	b942      	cbnz	r2, 5358 <z_reschedule_irqlock+0x1e>
    5346:	2201      	movs	r2, #1
    5348:	e000      	b.n	534c <z_reschedule_irqlock+0x12>
    534a:	2200      	movs	r2, #0
	if (resched(key)) {
    534c:	b932      	cbnz	r2, 535c <z_reschedule_irqlock+0x22>
    534e:	f383 8811 	msr	BASEPRI, r3
    5352:	f3bf 8f6f 	isb	sy
}
    5356:	bd08      	pop	{r3, pc}
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    5358:	2200      	movs	r2, #0
    535a:	e7f7      	b.n	534c <z_reschedule_irqlock+0x12>
	ret = arch_swap(key);
    535c:	4618      	mov	r0, r3
    535e:	f7fc fb13 	bl	1988 <arch_swap>
	return ret;
    5362:	e7f8      	b.n	5356 <z_reschedule_irqlock+0x1c>

00005364 <z_priq_dumb_remove>:
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
    5364:	684a      	ldr	r2, [r1, #4]
	sys_dnode_t *const next = node->next;
    5366:	680b      	ldr	r3, [r1, #0]

	prev->next = next;
    5368:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    536a:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    536c:	2300      	movs	r3, #0
    536e:	600b      	str	r3, [r1, #0]
	node->prev = NULL;
    5370:	604b      	str	r3, [r1, #4]
}
    5372:	4770      	bx	lr

00005374 <z_priq_dumb_best>:
{
    5374:	4603      	mov	r3, r0
	return list->head == list;
    5376:	6800      	ldr	r0, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    5378:	4283      	cmp	r3, r0
    537a:	d000      	beq.n	537e <z_priq_dumb_best+0xa>
}
    537c:	4770      	bx	lr
	struct k_thread *thread = NULL;
    537e:	2000      	movs	r0, #0
	return thread;
    5380:	e7fc      	b.n	537c <z_priq_dumb_best+0x8>

00005382 <add_to_waitq_locked>:
{
    5382:	b570      	push	{r4, r5, r6, lr}
    5384:	4605      	mov	r5, r0
    5386:	460e      	mov	r6, r1
	unready_thread(thread);
    5388:	f7fe fbc8 	bl	3b1c <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    538c:	7b6b      	ldrb	r3, [r5, #13]
    538e:	f043 0302 	orr.w	r3, r3, #2
    5392:	736b      	strb	r3, [r5, #13]
	if (wait_q != NULL) {
    5394:	b1b6      	cbz	r6, 53c4 <add_to_waitq_locked+0x42>
		thread->base.pended_on = wait_q;
    5396:	60ae      	str	r6, [r5, #8]
	return list->head == list;
    5398:	6834      	ldr	r4, [r6, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    539a:	42a6      	cmp	r6, r4
    539c:	d019      	beq.n	53d2 <add_to_waitq_locked+0x50>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    539e:	b164      	cbz	r4, 53ba <add_to_waitq_locked+0x38>
		if (z_sched_prio_cmp(thread, t) > 0) {
    53a0:	4621      	mov	r1, r4
    53a2:	4628      	mov	r0, r5
    53a4:	f7ff ffa0 	bl	52e8 <z_sched_prio_cmp>
    53a8:	2800      	cmp	r0, #0
    53aa:	dc0c      	bgt.n	53c6 <add_to_waitq_locked+0x44>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    53ac:	b12c      	cbz	r4, 53ba <add_to_waitq_locked+0x38>
	return (node == list->tail) ? NULL : node->next;
    53ae:	6873      	ldr	r3, [r6, #4]
    53b0:	429c      	cmp	r4, r3
    53b2:	d002      	beq.n	53ba <add_to_waitq_locked+0x38>
    53b4:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    53b6:	2c00      	cmp	r4, #0
    53b8:	d1f1      	bne.n	539e <add_to_waitq_locked+0x1c>
	sys_dnode_t *const tail = list->tail;
    53ba:	6873      	ldr	r3, [r6, #4]
	node->next = list;
    53bc:	602e      	str	r6, [r5, #0]
	node->prev = tail;
    53be:	606b      	str	r3, [r5, #4]
	tail->next = node;
    53c0:	601d      	str	r5, [r3, #0]
	list->tail = node;
    53c2:	6075      	str	r5, [r6, #4]
}
    53c4:	bd70      	pop	{r4, r5, r6, pc}
	sys_dnode_t *const prev = successor->prev;
    53c6:	6863      	ldr	r3, [r4, #4]
	node->prev = prev;
    53c8:	606b      	str	r3, [r5, #4]
	node->next = successor;
    53ca:	602c      	str	r4, [r5, #0]
	prev->next = node;
    53cc:	601d      	str	r5, [r3, #0]
	successor->prev = node;
    53ce:	6065      	str	r5, [r4, #4]
}
    53d0:	e7f8      	b.n	53c4 <add_to_waitq_locked+0x42>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    53d2:	2400      	movs	r4, #0
    53d4:	e7e3      	b.n	539e <add_to_waitq_locked+0x1c>

000053d6 <pend>:
{
    53d6:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    53da:	4605      	mov	r5, r0
    53dc:	460f      	mov	r7, r1
    53de:	4691      	mov	r9, r2
    53e0:	4698      	mov	r8, r3
	LOCKED(&sched_spinlock) {
    53e2:	2400      	movs	r4, #0
	__asm__ volatile(
    53e4:	f04f 0320 	mov.w	r3, #32
    53e8:	f3ef 8611 	mrs	r6, BASEPRI
    53ec:	f383 8811 	msr	BASEPRI, r3
    53f0:	f3bf 8f6f 	isb	sy
    53f4:	b94c      	cbnz	r4, 540a <pend+0x34>
		add_to_waitq_locked(thread, wait_q);
    53f6:	4639      	mov	r1, r7
    53f8:	4628      	mov	r0, r5
    53fa:	f7ff ffc2 	bl	5382 <add_to_waitq_locked>
	__asm__ volatile(
    53fe:	f386 8811 	msr	BASEPRI, r6
    5402:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    5406:	2401      	movs	r4, #1
    5408:	e7f4      	b.n	53f4 <pend+0x1e>
	add_thread_timeout(thread, timeout);
    540a:	464a      	mov	r2, r9
    540c:	4643      	mov	r3, r8
    540e:	4628      	mov	r0, r5
    5410:	f7fe fac8 	bl	39a4 <add_thread_timeout>
}
    5414:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

00005418 <z_ready_thread>:
{
    5418:	b538      	push	{r3, r4, r5, lr}
    541a:	4604      	mov	r4, r0
	LOCKED(&sched_spinlock) {
    541c:	2300      	movs	r3, #0
	__asm__ volatile(
    541e:	f04f 0220 	mov.w	r2, #32
    5422:	f3ef 8511 	mrs	r5, BASEPRI
    5426:	f382 8811 	msr	BASEPRI, r2
    542a:	f3bf 8f6f 	isb	sy
    542e:	e007      	b.n	5440 <z_ready_thread+0x28>
			ready_thread(thread);
    5430:	4620      	mov	r0, r4
    5432:	f7fe fc9b 	bl	3d6c <ready_thread>
	__asm__ volatile(
    5436:	f385 8811 	msr	BASEPRI, r5
    543a:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    543e:	2301      	movs	r3, #1
    5440:	b92b      	cbnz	r3, 544e <z_ready_thread+0x36>
		if (!thread_active_elsewhere(thread)) {
    5442:	4620      	mov	r0, r4
    5444:	f7ff ff4c 	bl	52e0 <thread_active_elsewhere>
    5448:	2800      	cmp	r0, #0
    544a:	d1f4      	bne.n	5436 <z_ready_thread+0x1e>
    544c:	e7f0      	b.n	5430 <z_ready_thread+0x18>
}
    544e:	bd38      	pop	{r3, r4, r5, pc}

00005450 <z_thread_timeout>:
{
    5450:	b570      	push	{r4, r5, r6, lr}
    5452:	4604      	mov	r4, r0
	struct k_thread *thread = CONTAINER_OF(timeout,
    5454:	f1a0 0518 	sub.w	r5, r0, #24
	LOCKED(&sched_spinlock) {
    5458:	2300      	movs	r3, #0
	__asm__ volatile(
    545a:	f04f 0220 	mov.w	r2, #32
    545e:	f3ef 8611 	mrs	r6, BASEPRI
    5462:	f382 8811 	msr	BASEPRI, r2
    5466:	f3bf 8f6f 	isb	sy
    546a:	e019      	b.n	54a0 <z_thread_timeout+0x50>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    546c:	4628      	mov	r0, r5
    546e:	f7ff ff39 	bl	52e4 <pended_on_thread>
    5472:	4629      	mov	r1, r5
    5474:	f7ff ff76 	bl	5364 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    5478:	7b6b      	ldrb	r3, [r5, #13]
    547a:	f023 0302 	bic.w	r3, r3, #2
    547e:	736b      	strb	r3, [r5, #13]
	thread->base.pended_on = NULL;
    5480:	2300      	movs	r3, #0
    5482:	60ab      	str	r3, [r5, #8]
	thread->base.thread_state &= ~_THREAD_PRESTART;
    5484:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    5488:	f003 03eb 	and.w	r3, r3, #235	; 0xeb
    548c:	f804 3c0b 	strb.w	r3, [r4, #-11]
			ready_thread(thread);
    5490:	4628      	mov	r0, r5
    5492:	f7fe fc6b 	bl	3d6c <ready_thread>
	__asm__ volatile(
    5496:	f386 8811 	msr	BASEPRI, r6
    549a:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    549e:	2301      	movs	r3, #1
    54a0:	b94b      	cbnz	r3, 54b6 <z_thread_timeout+0x66>
		bool killed = ((thread->base.thread_state & _THREAD_DEAD) ||
    54a2:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
		if (!killed) {
    54a6:	f013 0f28 	tst.w	r3, #40	; 0x28
    54aa:	d1f4      	bne.n	5496 <z_thread_timeout+0x46>
			if (thread->base.pended_on != NULL) {
    54ac:	f854 3c10 	ldr.w	r3, [r4, #-16]
    54b0:	2b00      	cmp	r3, #0
    54b2:	d1db      	bne.n	546c <z_thread_timeout+0x1c>
    54b4:	e7e6      	b.n	5484 <z_thread_timeout+0x34>
}
    54b6:	bd70      	pop	{r4, r5, r6, pc}

000054b8 <z_unpend1_no_timeout>:
{
    54b8:	b570      	push	{r4, r5, r6, lr}
    54ba:	4606      	mov	r6, r0
	LOCKED(&sched_spinlock) {
    54bc:	2300      	movs	r3, #0
	__asm__ volatile(
    54be:	f04f 0220 	mov.w	r2, #32
    54c2:	f3ef 8511 	mrs	r5, BASEPRI
    54c6:	f382 8811 	msr	BASEPRI, r2
    54ca:	f3bf 8f6f 	isb	sy
	struct k_thread *thread = NULL;
    54ce:	461c      	mov	r4, r3
    54d0:	e00f      	b.n	54f2 <z_unpend1_no_timeout+0x3a>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    54d2:	f7ff ff07 	bl	52e4 <pended_on_thread>
    54d6:	4621      	mov	r1, r4
    54d8:	f7ff ff44 	bl	5364 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    54dc:	7b63      	ldrb	r3, [r4, #13]
    54de:	f023 0302 	bic.w	r3, r3, #2
    54e2:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    54e4:	2300      	movs	r3, #0
    54e6:	60a3      	str	r3, [r4, #8]
	__asm__ volatile(
    54e8:	f385 8811 	msr	BASEPRI, r5
    54ec:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    54f0:	2301      	movs	r3, #1
    54f2:	b933      	cbnz	r3, 5502 <z_unpend1_no_timeout+0x4a>
		thread = _priq_wait_best(&wait_q->waitq);
    54f4:	4630      	mov	r0, r6
    54f6:	f7ff ff3d 	bl	5374 <z_priq_dumb_best>
		if (thread != NULL) {
    54fa:	4604      	mov	r4, r0
    54fc:	2800      	cmp	r0, #0
    54fe:	d1e8      	bne.n	54d2 <z_unpend1_no_timeout+0x1a>
    5500:	e7f2      	b.n	54e8 <z_unpend1_no_timeout+0x30>
}
    5502:	4620      	mov	r0, r4
    5504:	bd70      	pop	{r4, r5, r6, pc}

00005506 <z_unpend_first_thread>:
{
    5506:	b570      	push	{r4, r5, r6, lr}
    5508:	4606      	mov	r6, r0
	LOCKED(&sched_spinlock) {
    550a:	2300      	movs	r3, #0
	__asm__ volatile(
    550c:	f04f 0220 	mov.w	r2, #32
    5510:	f3ef 8511 	mrs	r5, BASEPRI
    5514:	f382 8811 	msr	BASEPRI, r2
    5518:	f3bf 8f6f 	isb	sy
	struct k_thread *thread = NULL;
    551c:	461c      	mov	r4, r3
    551e:	e013      	b.n	5548 <z_unpend_first_thread+0x42>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    5520:	f7ff fee0 	bl	52e4 <pended_on_thread>
    5524:	4621      	mov	r1, r4
    5526:	f7ff ff1d 	bl	5364 <z_priq_dumb_remove>
    552a:	7b63      	ldrb	r3, [r4, #13]
    552c:	f023 0302 	bic.w	r3, r3, #2
    5530:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    5532:	2300      	movs	r3, #0
    5534:	60a3      	str	r3, [r4, #8]
	return z_abort_timeout(&thread->base.timeout);
    5536:	f104 0018 	add.w	r0, r4, #24
    553a:	f000 f85d 	bl	55f8 <z_abort_timeout>
	__asm__ volatile(
    553e:	f385 8811 	msr	BASEPRI, r5
    5542:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    5546:	2301      	movs	r3, #1
    5548:	b933      	cbnz	r3, 5558 <z_unpend_first_thread+0x52>
		thread = _priq_wait_best(&wait_q->waitq);
    554a:	4630      	mov	r0, r6
    554c:	f7ff ff12 	bl	5374 <z_priq_dumb_best>
		if (thread != NULL) {
    5550:	4604      	mov	r4, r0
    5552:	2800      	cmp	r0, #0
    5554:	d1e4      	bne.n	5520 <z_unpend_first_thread+0x1a>
    5556:	e7f2      	b.n	553e <z_unpend_first_thread+0x38>
}
    5558:	4620      	mov	r0, r4
    555a:	bd70      	pop	{r4, r5, r6, pc}

0000555c <z_sched_wake>:
{
    555c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    5560:	4606      	mov	r6, r0
    5562:	4688      	mov	r8, r1
    5564:	4617      	mov	r7, r2
	LOCKED(&sched_spinlock) {
    5566:	2300      	movs	r3, #0
	__asm__ volatile(
    5568:	f04f 0220 	mov.w	r2, #32
    556c:	f3ef 8511 	mrs	r5, BASEPRI
    5570:	f382 8811 	msr	BASEPRI, r2
    5574:	f3bf 8f6f 	isb	sy
	bool ret = false;
    5578:	4699      	mov	r9, r3
    557a:	e01b      	b.n	55b4 <z_sched_wake+0x58>
    557c:	f8c0 8078 	str.w	r8, [r0, #120]	; 0x78
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    5580:	6147      	str	r7, [r0, #20]
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    5582:	f7ff feaf 	bl	52e4 <pended_on_thread>
    5586:	4621      	mov	r1, r4
    5588:	f7ff feec 	bl	5364 <z_priq_dumb_remove>
    558c:	7b63      	ldrb	r3, [r4, #13]
    558e:	f023 0302 	bic.w	r3, r3, #2
    5592:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    5594:	2300      	movs	r3, #0
    5596:	60a3      	str	r3, [r4, #8]
    5598:	f104 0018 	add.w	r0, r4, #24
    559c:	f000 f82c 	bl	55f8 <z_abort_timeout>
			ready_thread(thread);
    55a0:	4620      	mov	r0, r4
    55a2:	f7fe fbe3 	bl	3d6c <ready_thread>
			ret = true;
    55a6:	f04f 0901 	mov.w	r9, #1
	__asm__ volatile(
    55aa:	f385 8811 	msr	BASEPRI, r5
    55ae:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    55b2:	2301      	movs	r3, #1
    55b4:	b933      	cbnz	r3, 55c4 <z_sched_wake+0x68>
		thread = _priq_wait_best(&wait_q->waitq);
    55b6:	4630      	mov	r0, r6
    55b8:	f7ff fedc 	bl	5374 <z_priq_dumb_best>
		if (thread != NULL) {
    55bc:	4604      	mov	r4, r0
    55be:	2800      	cmp	r0, #0
    55c0:	d1dc      	bne.n	557c <z_sched_wake+0x20>
    55c2:	e7f2      	b.n	55aa <z_sched_wake+0x4e>
}
    55c4:	4648      	mov	r0, r9
    55c6:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

000055ca <remove_timeout>:
{
    55ca:	b538      	push	{r3, r4, r5, lr}
    55cc:	4604      	mov	r4, r0
	if (next(t) != NULL) {
    55ce:	f7fe fe17 	bl	4200 <next>
    55d2:	b148      	cbz	r0, 55e8 <remove_timeout+0x1e>
    55d4:	4602      	mov	r2, r0
		next(t)->dticks += t->dticks;
    55d6:	6920      	ldr	r0, [r4, #16]
    55d8:	6965      	ldr	r5, [r4, #20]
    55da:	6913      	ldr	r3, [r2, #16]
    55dc:	6951      	ldr	r1, [r2, #20]
    55de:	181b      	adds	r3, r3, r0
    55e0:	eb45 0101 	adc.w	r1, r5, r1
    55e4:	6113      	str	r3, [r2, #16]
    55e6:	6151      	str	r1, [r2, #20]
	sys_dnode_t *const prev = node->prev;
    55e8:	6862      	ldr	r2, [r4, #4]
	sys_dnode_t *const next = node->next;
    55ea:	6823      	ldr	r3, [r4, #0]
	prev->next = next;
    55ec:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    55ee:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    55f0:	2300      	movs	r3, #0
    55f2:	6023      	str	r3, [r4, #0]
	node->prev = NULL;
    55f4:	6063      	str	r3, [r4, #4]
}
    55f6:	bd38      	pop	{r3, r4, r5, pc}

000055f8 <z_abort_timeout>:
{
    55f8:	b570      	push	{r4, r5, r6, lr}
    55fa:	4604      	mov	r4, r0
	LOCKED(&timeout_lock) {
    55fc:	2300      	movs	r3, #0
	__asm__ volatile(
    55fe:	f04f 0220 	mov.w	r2, #32
    5602:	f3ef 8611 	mrs	r6, BASEPRI
    5606:	f382 8811 	msr	BASEPRI, r2
    560a:	f3bf 8f6f 	isb	sy
	int ret = -EINVAL;
    560e:	f06f 0015 	mvn.w	r0, #21
    5612:	e008      	b.n	5626 <z_abort_timeout+0x2e>
			remove_timeout(to);
    5614:	4620      	mov	r0, r4
    5616:	f7ff ffd8 	bl	55ca <remove_timeout>
			ret = 0;
    561a:	4628      	mov	r0, r5
	__asm__ volatile(
    561c:	f386 8811 	msr	BASEPRI, r6
    5620:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    5624:	2301      	movs	r3, #1
    5626:	461d      	mov	r5, r3
    5628:	b91b      	cbnz	r3, 5632 <z_abort_timeout+0x3a>
	return node->next != NULL;
    562a:	6823      	ldr	r3, [r4, #0]
		if (sys_dnode_is_linked(&to->node)) {
    562c:	2b00      	cmp	r3, #0
    562e:	d1f1      	bne.n	5614 <z_abort_timeout+0x1c>
    5630:	e7f4      	b.n	561c <z_abort_timeout+0x24>
}
    5632:	bd70      	pop	{r4, r5, r6, pc}

00005634 <z_get_next_timeout_expiry>:
{
    5634:	b510      	push	{r4, lr}
	LOCKED(&timeout_lock) {
    5636:	2300      	movs	r3, #0
	__asm__ volatile(
    5638:	f04f 0220 	mov.w	r2, #32
    563c:	f3ef 8411 	mrs	r4, BASEPRI
    5640:	f382 8811 	msr	BASEPRI, r2
    5644:	f3bf 8f6f 	isb	sy
	int32_t ret = (int32_t) K_TICKS_FOREVER;
    5648:	f04f 30ff 	mov.w	r0, #4294967295
	LOCKED(&timeout_lock) {
    564c:	b93b      	cbnz	r3, 565e <z_get_next_timeout_expiry+0x2a>
		ret = next_timeout();
    564e:	f7fe fdef 	bl	4230 <next_timeout>
	__asm__ volatile(
    5652:	f384 8811 	msr	BASEPRI, r4
    5656:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    565a:	2301      	movs	r3, #1
    565c:	e7f6      	b.n	564c <z_get_next_timeout_expiry+0x18>
}
    565e:	bd10      	pop	{r4, pc}

00005660 <z_set_timeout_expiry>:
{
    5660:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    5662:	4606      	mov	r6, r0
    5664:	460f      	mov	r7, r1
	LOCKED(&timeout_lock) {
    5666:	2300      	movs	r3, #0
	__asm__ volatile(
    5668:	f04f 0220 	mov.w	r2, #32
    566c:	f3ef 8511 	mrs	r5, BASEPRI
    5670:	f382 8811 	msr	BASEPRI, r2
    5674:	f3bf 8f6f 	isb	sy
    5678:	e00a      	b.n	5690 <z_set_timeout_expiry+0x30>
			      || (ticks <= next_to);
    567a:	2401      	movs	r4, #1
		bool sooner = (next_to == K_TICKS_FOREVER)
    567c:	f004 0401 	and.w	r4, r4, #1
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
    5680:	2801      	cmp	r0, #1
    5682:	dd00      	ble.n	5686 <z_set_timeout_expiry+0x26>
    5684:	b97c      	cbnz	r4, 56a6 <z_set_timeout_expiry+0x46>
	__asm__ volatile(
    5686:	f385 8811 	msr	BASEPRI, r5
    568a:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    568e:	2301      	movs	r3, #1
    5690:	461c      	mov	r4, r3
    5692:	b97b      	cbnz	r3, 56b4 <z_set_timeout_expiry+0x54>
		int next_to = next_timeout();
    5694:	f7fe fdcc 	bl	4230 <next_timeout>
			      || (ticks <= next_to);
    5698:	f1b0 3fff 	cmp.w	r0, #4294967295
    569c:	d0ed      	beq.n	567a <z_set_timeout_expiry+0x1a>
    569e:	42b0      	cmp	r0, r6
    56a0:	dbec      	blt.n	567c <z_set_timeout_expiry+0x1c>
    56a2:	2401      	movs	r4, #1
    56a4:	e7ea      	b.n	567c <z_set_timeout_expiry+0x1c>
			sys_clock_set_timeout(MIN(ticks, next_to), is_idle);
    56a6:	4639      	mov	r1, r7
    56a8:	42b0      	cmp	r0, r6
    56aa:	bfa8      	it	ge
    56ac:	4630      	movge	r0, r6
    56ae:	f7fc f931 	bl	1914 <sys_clock_set_timeout>
    56b2:	e7e8      	b.n	5686 <z_set_timeout_expiry+0x26>
}
    56b4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

000056b6 <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
    56b6:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
    56b8:	f7fe feec 	bl	4494 <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    56bc:	bd08      	pop	{r3, pc}

000056be <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    56be:	b900      	cbnz	r0, 56c2 <z_impl_k_busy_wait+0x4>
    56c0:	4770      	bx	lr
{
    56c2:	b508      	push	{r3, lr}
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    56c4:	f7fc fcec 	bl	20a0 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    56c8:	bd08      	pop	{r3, pc}

000056ca <z_impl_k_timer_stop>:
}
#include <syscalls/k_timer_start_mrsh.c>
#endif

void z_impl_k_timer_stop(struct k_timer *timer)
{
    56ca:	b510      	push	{r4, lr}
    56cc:	4604      	mov	r4, r0
	SYS_PORT_TRACING_OBJ_FUNC(k_timer, stop, timer);

	int inactive = z_abort_timeout(&timer->timeout) != 0;
    56ce:	f7ff ff93 	bl	55f8 <z_abort_timeout>

	if (inactive) {
    56d2:	b9a0      	cbnz	r0, 56fe <z_impl_k_timer_stop+0x34>
		return;
	}

	if (timer->stop_fn != NULL) {
    56d4:	6a63      	ldr	r3, [r4, #36]	; 0x24
    56d6:	b10b      	cbz	r3, 56dc <z_impl_k_timer_stop+0x12>
		timer->stop_fn(timer);
    56d8:	4620      	mov	r0, r4
    56da:	4798      	blx	r3
	}

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		struct k_thread *pending_thread = z_unpend1_no_timeout(&timer->wait_q);
    56dc:	f104 0018 	add.w	r0, r4, #24
    56e0:	f7ff feea 	bl	54b8 <z_unpend1_no_timeout>

		if (pending_thread != NULL) {
    56e4:	b158      	cbz	r0, 56fe <z_impl_k_timer_stop+0x34>
			z_ready_thread(pending_thread);
    56e6:	f7ff fe97 	bl	5418 <z_ready_thread>
	__asm__ volatile(
    56ea:	f04f 0320 	mov.w	r3, #32
    56ee:	f3ef 8011 	mrs	r0, BASEPRI
    56f2:	f383 8811 	msr	BASEPRI, r3
    56f6:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    56fa:	f7ff fe1e 	bl	533a <z_reschedule_irqlock>
			z_reschedule_unlocked();
		}
	}
}
    56fe:	bd10      	pop	{r4, pc}

00005700 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    5700:	4770      	bx	lr

00005702 <_ZdlPv>:
    5702:	f7fe bfb9 	b.w	4678 <free>

00005706 <_Znwj>:
    5706:	2801      	cmp	r0, #1
    5708:	bf38      	it	cc
    570a:	2001      	movcc	r0, #1
    570c:	b510      	push	{r4, lr}
    570e:	4604      	mov	r4, r0
    5710:	4620      	mov	r0, r4
    5712:	f7fe ffa9 	bl	4668 <malloc>
    5716:	b930      	cbnz	r0, 5726 <_Znwj+0x20>
    5718:	f7fe ff9e 	bl	4658 <_ZSt15get_new_handlerv>
    571c:	b908      	cbnz	r0, 5722 <_Znwj+0x1c>
    571e:	f000 f803 	bl	5728 <abort>
    5722:	4780      	blx	r0
    5724:	e7f4      	b.n	5710 <_Znwj+0xa>
    5726:	bd10      	pop	{r4, pc}

00005728 <abort>:
    5728:	b508      	push	{r3, lr}
    572a:	2006      	movs	r0, #6
    572c:	f7ff f864 	bl	47f8 <raise>
    5730:	2001      	movs	r0, #1
    5732:	f7fc fc53 	bl	1fdc <_exit>

00005736 <abs>:
    5736:	2800      	cmp	r0, #0
    5738:	bfb8      	it	lt
    573a:	4240      	neglt	r0, r0
    573c:	4770      	bx	lr

0000573e <memcpy>:
    573e:	440a      	add	r2, r1
    5740:	4291      	cmp	r1, r2
    5742:	f100 33ff 	add.w	r3, r0, #4294967295
    5746:	d100      	bne.n	574a <memcpy+0xc>
    5748:	4770      	bx	lr
    574a:	b510      	push	{r4, lr}
    574c:	f811 4b01 	ldrb.w	r4, [r1], #1
    5750:	f803 4f01 	strb.w	r4, [r3, #1]!
    5754:	4291      	cmp	r1, r2
    5756:	d1f9      	bne.n	574c <memcpy+0xe>
    5758:	bd10      	pop	{r4, pc}

0000575a <memset>:
    575a:	4402      	add	r2, r0
    575c:	4603      	mov	r3, r0
    575e:	4293      	cmp	r3, r2
    5760:	d100      	bne.n	5764 <memset+0xa>
    5762:	4770      	bx	lr
    5764:	f803 1b01 	strb.w	r1, [r3], #1
    5768:	e7f9      	b.n	575e <memset+0x4>

0000576a <_raise_r>:
    576a:	291f      	cmp	r1, #31
    576c:	b538      	push	{r3, r4, r5, lr}
    576e:	4604      	mov	r4, r0
    5770:	460d      	mov	r5, r1
    5772:	d904      	bls.n	577e <_raise_r+0x14>
    5774:	2316      	movs	r3, #22
    5776:	6003      	str	r3, [r0, #0]
    5778:	f04f 30ff 	mov.w	r0, #4294967295
    577c:	bd38      	pop	{r3, r4, r5, pc}
    577e:	6c42      	ldr	r2, [r0, #68]	; 0x44
    5780:	b112      	cbz	r2, 5788 <_raise_r+0x1e>
    5782:	f852 3021 	ldr.w	r3, [r2, r1, lsl #2]
    5786:	b94b      	cbnz	r3, 579c <_raise_r+0x32>
    5788:	4620      	mov	r0, r4
    578a:	f000 f816 	bl	57ba <_getpid_r>
    578e:	462a      	mov	r2, r5
    5790:	4601      	mov	r1, r0
    5792:	4620      	mov	r0, r4
    5794:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
    5798:	f7ff b836 	b.w	4808 <_kill_r>
    579c:	2b01      	cmp	r3, #1
    579e:	d00a      	beq.n	57b6 <_raise_r+0x4c>
    57a0:	1c59      	adds	r1, r3, #1
    57a2:	d103      	bne.n	57ac <_raise_r+0x42>
    57a4:	2316      	movs	r3, #22
    57a6:	6003      	str	r3, [r0, #0]
    57a8:	2001      	movs	r0, #1
    57aa:	e7e7      	b.n	577c <_raise_r+0x12>
    57ac:	2400      	movs	r4, #0
    57ae:	f842 4025 	str.w	r4, [r2, r5, lsl #2]
    57b2:	4628      	mov	r0, r5
    57b4:	4798      	blx	r3
    57b6:	2000      	movs	r0, #0
    57b8:	e7e0      	b.n	577c <_raise_r+0x12>

000057ba <_getpid_r>:
    57ba:	f7ff bc1e 	b.w	4ffa <_getpid>

000057be <strnlen>:
    57be:	b510      	push	{r4, lr}
    57c0:	4602      	mov	r2, r0
    57c2:	4401      	add	r1, r0
    57c4:	428a      	cmp	r2, r1
    57c6:	4613      	mov	r3, r2
    57c8:	d101      	bne.n	57ce <strnlen+0x10>
    57ca:	1a18      	subs	r0, r3, r0
    57cc:	bd10      	pop	{r4, pc}
    57ce:	781c      	ldrb	r4, [r3, #0]
    57d0:	3201      	adds	r2, #1
    57d2:	2c00      	cmp	r4, #0
    57d4:	d1f6      	bne.n	57c4 <strnlen+0x6>
    57d6:	e7f8      	b.n	57ca <strnlen+0xc>

000057d8 <z_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    57d8:	f7fd b9e0 	b.w	2b9c <SystemInit>
