/*
 * Generated by gen_defines.py
 *
 * DTS input file:
 *   nrf9160_cl5gmns.dts.pre.tmp
 *
 * Directories with bindings:
 *   C:/H474243/Nordic/v1.5.1/nrf/dts/bindings, $ZEPHYR_BASE\dts\bindings
 *
 * Node dependency ordering (ordinal and path):
 *   0   /
 *   1   /aliases
 *   2   /chosen
 *   3   /cpus
 *   4   /cpus/cpu@0
 *   5   /cpus/cpu@0/mpu@e000ed90
 *   6   /gpios
 *   7   /soc
 *   8   /soc/peripheral@40000000
 *   9   /soc/peripheral@40000000/gpio@842500
 *   10  /gpios/eeprom_en_0
 *   11  /gpios/factory_restore_0
 *   12  /gpios/flash_en_0
 *   13  /gpios/flash_spi_cs_0
 *   14  /gpios/force_call_1
 *   15  /gpios/gps_en_0
 *   16  /gpios/hwrev_0
 *   17  /gpios/mux_sim_sel
 *   18  /gpios/pulsein_1
 *   19  /gpios/pulsein_2
 *   20  /gpios/pulseout_0
 *   21  /gpios/pwr_temp_0
 *   22  /gpios/spi_cs_0
 *   23  /gpios/tamper_0
 *   24  /gpios/vmon_en_0
 *   25  /leds
 *   26  /leds/led_1
 *   27  /leds/led_2
 *   28  /leds/led_3
 *   29  /leds/led_4
 *   30  /reserved-memory
 *   31  /reserved-memory/image_bsd@20010000
 *   32  /reserved-memory/image_ns@20020000
 *   33  /reserved-memory/image_s@20000000
 *   34  /soc/cryptocell-sw
 *   35  /soc/interrupt-controller@e000e100
 *   36  /soc/gpiote@40031000
 *   37  /soc/memory@20000000
 *   38  /soc/timer@e000e010
 *   39  /soc/peripheral@40000000/adc@e000
 *   40  /soc/peripheral@40000000/clock@5000
 *   41  /soc/peripheral@40000000/dppic@17000
 *   42  /soc/peripheral@40000000/egu@1b000
 *   43  /soc/peripheral@40000000/egu@1c000
 *   44  /soc/peripheral@40000000/egu@1d000
 *   45  /soc/peripheral@40000000/egu@1e000
 *   46  /soc/peripheral@40000000/egu@1f000
 *   47  /soc/peripheral@40000000/egu@20000
 *   48  /soc/peripheral@40000000/i2c@8000
 *   49  /soc/peripheral@40000000/i2c@a000
 *   50  /soc/peripheral@40000000/i2c@b000
 *   51  /soc/peripheral@40000000/i2s@28000
 *   52  /soc/peripheral@40000000/kmu@39000
 *   53  /soc/peripheral@40000000/pdm@26000
 *   54  /soc/peripheral@40000000/power@5000
 *   55  /soc/peripheral@40000000/pwm@21000
 *   56  /soc/peripheral@40000000/pwm@22000
 *   57  /soc/peripheral@40000000/pwm@23000
 *   58  /soc/peripheral@40000000/pwm@24000
 *   59  /soc/peripheral@40000000/regulator@4000
 *   60  /soc/peripheral@40000000/rtc@14000
 *   61  /soc/peripheral@40000000/rtc@15000
 *   62  /soc/peripheral@40000000/spi@8000
 *   63  /soc/peripheral@40000000/spi@9000
 *   64  /soc/peripheral@40000000/spi@a000
 *   65  /soc/peripheral@40000000/timer@f000
 *   66  /soc/peripheral@40000000/timer@10000
 *   67  /soc/peripheral@40000000/timer@11000
 *   68  /soc/peripheral@40000000/uart@8000
 *   69  /soc/peripheral@40000000/uart@9000
 *   70  /soc/peripheral@40000000/uart@a000
 *   71  /soc/peripheral@40000000/uart@b000
 *   72  /soc/peripheral@40000000/vmc@3a000
 *   73  /soc/peripheral@40000000/watchdog@18000
 *   74  /soc/peripheral@40000000/flash-controller@39000
 *   75  /soc/peripheral@40000000/flash-controller@39000/flash@0
 *   76  /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions
 *   77  /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@0
 *   78  /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@10000
 *   79  /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@50000
 *   80  /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@80000
 *   81  /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@c0000
 *   82  /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@f0000
 *   83  /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@fa000
 *   84  /soc/peripheral@40000000/i2c@9000
 *   85  /soc/peripheral@40000000/i2c@9000/maxl7261@36
 *   86  /soc/peripheral@40000000/spi@b000
 *   87  /soc/peripheral@40000000/spi@b000/m95m02@0
 *
 * Definitions derived from these nodes in dependency order are next,
 * followed by /chosen nodes.
 */

/*
 * Devicetree node: /
 *
 * Node identifier: DT_N
 */

/* Node's full path: */
#define DT_N_PATH "/"
#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_leds) fn(DT_N_S_gpios) fn(DT_N_S_reserved_memory)

/* Node's dependency ordinal: */
#define DT_N_ORD 0

/* Ordinals for what this node depends on directly: */
#define DT_N_REQUIRES_ORDS /* nothing */

/* Ordinals for what depends directly on this node: */
#define DT_N_SUPPORTS_ORDS \
	1, /* /aliases */ \
	2, /* /chosen */ \
	3, /* /cpus */ \
	6, /* /gpios */ \
	7, /* /soc */ \
	25, /* /leds */ \
	30, /* /reserved-memory */

/* Existence and alternate IDs: */
#define DT_N_EXISTS 1
#define DT_N_INST_0_nordic_cl5gm DT_N

/* Special property macros: */
#define DT_N_REG_NUM 0
#define DT_N_IRQ_NUM 0
#define DT_N_COMPAT_MATCHES_nordic_cl5gm 1
#define DT_N_STATUS_okay 1

/* Generic property macros: */
#define DT_N_P_compatible {"nordic,cl5gm"}
#define DT_N_P_compatible_IDX_0 "nordic,cl5gm"
#define DT_N_P_compatible_IDX_0_EXISTS 1
#define DT_N_P_compatible_LEN 1
#define DT_N_P_compatible_EXISTS 1

/*
 * Devicetree node: /aliases
 *
 * Node identifier: DT_N_S_aliases
 */

/* Node's full path: */
#define DT_N_S_aliases_PATH "/aliases"

/* Node parent (/) identifier: */
#define DT_N_S_aliases_PARENT DT_N
#define DT_N_S_aliases_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_aliases_ORD 1

/* Ordinals for what this node depends on directly: */
#define DT_N_S_aliases_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_aliases_EXISTS 1

/* Special property macros: */
#define DT_N_S_aliases_REG_NUM 0
#define DT_N_S_aliases_IRQ_NUM 0
#define DT_N_S_aliases_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /chosen
 *
 * Node identifier: DT_N_S_chosen
 */

/* Node's full path: */
#define DT_N_S_chosen_PATH "/chosen"

/* Node parent (/) identifier: */
#define DT_N_S_chosen_PARENT DT_N
#define DT_N_S_chosen_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_chosen_ORD 2

/* Ordinals for what this node depends on directly: */
#define DT_N_S_chosen_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_chosen_EXISTS 1

/* Special property macros: */
#define DT_N_S_chosen_REG_NUM 0
#define DT_N_S_chosen_IRQ_NUM 0
#define DT_N_S_chosen_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /cpus
 *
 * Node identifier: DT_N_S_cpus
 */

/* Node's full path: */
#define DT_N_S_cpus_PATH "/cpus"

/* Node parent (/) identifier: */
#define DT_N_S_cpus_PARENT DT_N
#define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_ORD 3

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_SUPPORTS_ORDS \
	4, /* /cpus/cpu@0 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_EXISTS 1

/* Special property macros: */
#define DT_N_S_cpus_REG_NUM 0
#define DT_N_S_cpus_IRQ_NUM 0
#define DT_N_S_cpus_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/cpu@0
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0
 *
 * Binding (compatible = arm,cortex-m33f):
 *   $ZEPHYR_BASE\dts\bindings\cpu\arm,cortex-m33f.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0"

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_ORD 4

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \
	3, /* /cpus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS \
	5, /* /cpus/cpu@0/mpu@e000ed90 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_EXISTS 1
#define DT_N_INST_0_arm_cortex_m33f DT_N_S_cpus_S_cpu_0

/* Special property macros: */
#define DT_N_S_cpus_S_cpu_0_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m33f 1
#define DT_N_S_cpus_S_cpu_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_P_i_cache_line_size 0
#define DT_N_S_cpus_S_cpu_0_P_i_cache_line_size_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_d_cache_line_size 0
#define DT_N_S_cpus_S_cpu_0_P_d_cache_line_size_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m33f"}
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m33f"
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */}
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@0/mpu@e000ed90
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
 *
 * Binding (compatible = arm,armv8m-mpu):
 *   $ZEPHYR_BASE\dts\bindings\mmu_mpu\arm,armv8m-mpu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PATH "/cpus/cpu@0/mpu@e000ed90"

/* Node parent (/cpus/cpu@0) identifier: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PARENT DT_N_S_cpus_S_cpu_0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD 5

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REQUIRES_ORDS \
	4, /* /cpus/cpu@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_EXISTS 1
#define DT_N_INST_0_arm_armv8m_mpu DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
#define DT_N_NODELABEL_mpu         DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90

/* Special property macros: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS 3758157200 /* 0xe000ed90 */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE 64 /* 0x40 */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MATCHES_arm_armv8m_mpu 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg {3758157200 /* 0xe000ed90 */, 64 /* 0x40 */}
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0 3758157200
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1 64
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions 16
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible {"arm,armv8m-mpu"}
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0 "arm,armv8m-mpu"
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_EXISTS 1

/*
 * Devicetree node: /gpios
 *
 * Node identifier: DT_N_S_gpios
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_PATH "/gpios"

/* Node parent (/) identifier: */
#define DT_N_S_gpios_PARENT DT_N
#define DT_N_S_gpios_FOREACH_CHILD(fn) fn(DT_N_S_gpios_S_pulsein_1) fn(DT_N_S_gpios_S_pulsein_2) fn(DT_N_S_gpios_S_force_call_1) fn(DT_N_S_gpios_S_mux_sim_sel) fn(DT_N_S_gpios_S_pwr_temp_0) fn(DT_N_S_gpios_S_vmon_en_0) fn(DT_N_S_gpios_S_gps_en_0) fn(DT_N_S_gpios_S_tamper_0) fn(DT_N_S_gpios_S_factory_restore_0) fn(DT_N_S_gpios_S_pulseout_0) fn(DT_N_S_gpios_S_eeprom_en_0) fn(DT_N_S_gpios_S_spi_cs_0) fn(DT_N_S_gpios_S_hwrev_0) fn(DT_N_S_gpios_S_flash_en_0) fn(DT_N_S_gpios_S_flash_spi_cs_0)

/* Node's dependency ordinal: */
#define DT_N_S_gpios_ORD 6

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_SUPPORTS_ORDS \
	10, /* /gpios/eeprom_en_0 */ \
	11, /* /gpios/factory_restore_0 */ \
	12, /* /gpios/flash_en_0 */ \
	13, /* /gpios/flash_spi_cs_0 */ \
	14, /* /gpios/force_call_1 */ \
	15, /* /gpios/gps_en_0 */ \
	16, /* /gpios/hwrev_0 */ \
	17, /* /gpios/mux_sim_sel */ \
	18, /* /gpios/pulsein_1 */ \
	19, /* /gpios/pulsein_2 */ \
	20, /* /gpios/pulseout_0 */ \
	21, /* /gpios/pwr_temp_0 */ \
	22, /* /gpios/spi_cs_0 */ \
	23, /* /gpios/tamper_0 */ \
	24, /* /gpios/vmon_en_0 */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_EXISTS 1
#define DT_N_INST_0_gpio_keys DT_N_S_gpios

/* Special property macros: */
#define DT_N_S_gpios_REG_NUM 0
#define DT_N_S_gpios_IRQ_NUM 0
#define DT_N_S_gpios_COMPAT_MATCHES_gpio_keys 1
#define DT_N_S_gpios_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_P_compatible {"gpio-keys"}
#define DT_N_S_gpios_P_compatible_IDX_0 "gpio-keys"
#define DT_N_S_gpios_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_gpios_P_compatible_LEN 1
#define DT_N_S_gpios_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc
 *
 * Node identifier: DT_N_S_soc
 */

/* Node's full path: */
#define DT_N_S_soc_PATH "/soc"

/* Node parent (/) identifier: */
#define DT_N_S_soc_PARENT DT_N
#define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_40000000) fn(DT_N_S_soc_S_gpiote_40031000) fn(DT_N_S_soc_S_cryptocell_sw)

/* Node's dependency ordinal: */
#define DT_N_S_soc_ORD 7

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_SUPPORTS_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	34, /* /soc/cryptocell-sw */ \
	35, /* /soc/interrupt-controller@e000e100 */ \
	36, /* /soc/gpiote@40031000 */ \
	37, /* /soc/memory@20000000 */ \
	38, /* /soc/timer@e000e010 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_EXISTS 1
#define DT_N_INST_0_nordic_nrf9160_sica DT_N_S_soc
#define DT_N_INST_0_nordic_nrf9160      DT_N_S_soc
#define DT_N_INST_0_nordic_nrf91        DT_N_S_soc
#define DT_N_INST_0_simple_bus          DT_N_S_soc

/* Special property macros: */
#define DT_N_S_soc_REG_NUM 0
#define DT_N_S_soc_IRQ_NUM 0
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9160_sica 1
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9160 1
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf91 1
#define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_P_compatible {"nordic,nRF9160-SICA", "nordic,nRF9160", "nordic,nRF91", "simple-bus"}
#define DT_N_S_soc_P_compatible_IDX_0 "nordic,nRF9160-SICA"
#define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_1 "nordic,nRF9160"
#define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_2 "nordic,nRF91"
#define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_3 "simple-bus"
#define DT_N_S_soc_P_compatible_IDX_3_EXISTS 1
#define DT_N_S_soc_P_compatible_LEN 4
#define DT_N_S_soc_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_PATH "/soc/peripheral@40000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_ORD 8

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_REQUIRES_ORDS \
	7, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_SUPPORTS_ORDS \
	9, /* /soc/peripheral@40000000/gpio@842500 */ \
	39, /* /soc/peripheral@40000000/adc@e000 */ \
	40, /* /soc/peripheral@40000000/clock@5000 */ \
	41, /* /soc/peripheral@40000000/dppic@17000 */ \
	42, /* /soc/peripheral@40000000/egu@1b000 */ \
	43, /* /soc/peripheral@40000000/egu@1c000 */ \
	44, /* /soc/peripheral@40000000/egu@1d000 */ \
	45, /* /soc/peripheral@40000000/egu@1e000 */ \
	46, /* /soc/peripheral@40000000/egu@1f000 */ \
	47, /* /soc/peripheral@40000000/egu@20000 */ \
	48, /* /soc/peripheral@40000000/i2c@8000 */ \
	49, /* /soc/peripheral@40000000/i2c@a000 */ \
	50, /* /soc/peripheral@40000000/i2c@b000 */ \
	51, /* /soc/peripheral@40000000/i2s@28000 */ \
	52, /* /soc/peripheral@40000000/kmu@39000 */ \
	53, /* /soc/peripheral@40000000/pdm@26000 */ \
	54, /* /soc/peripheral@40000000/power@5000 */ \
	55, /* /soc/peripheral@40000000/pwm@21000 */ \
	56, /* /soc/peripheral@40000000/pwm@22000 */ \
	57, /* /soc/peripheral@40000000/pwm@23000 */ \
	58, /* /soc/peripheral@40000000/pwm@24000 */ \
	59, /* /soc/peripheral@40000000/regulator@4000 */ \
	60, /* /soc/peripheral@40000000/rtc@14000 */ \
	61, /* /soc/peripheral@40000000/rtc@15000 */ \
	62, /* /soc/peripheral@40000000/spi@8000 */ \
	63, /* /soc/peripheral@40000000/spi@9000 */ \
	64, /* /soc/peripheral@40000000/spi@a000 */ \
	65, /* /soc/peripheral@40000000/timer@f000 */ \
	66, /* /soc/peripheral@40000000/timer@10000 */ \
	67, /* /soc/peripheral@40000000/timer@11000 */ \
	68, /* /soc/peripheral@40000000/uart@8000 */ \
	69, /* /soc/peripheral@40000000/uart@9000 */ \
	70, /* /soc/peripheral@40000000/uart@a000 */ \
	71, /* /soc/peripheral@40000000/uart@b000 */ \
	72, /* /soc/peripheral@40000000/vmc@3a000 */ \
	73, /* /soc/peripheral@40000000/watchdog@18000 */ \
	74, /* /soc/peripheral@40000000/flash-controller@39000 */ \
	84, /* /soc/peripheral@40000000/i2c@9000 */ \
	86, /* /soc/peripheral@40000000/spi@b000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_EXISTS 1

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_REG_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /soc/peripheral@40000000/gpio@842500
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_PATH "/soc/peripheral@40000000/gpio@842500"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_ORD 9

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_SUPPORTS_ORDS \
	10, /* /gpios/eeprom_en_0 */ \
	11, /* /gpios/factory_restore_0 */ \
	12, /* /gpios/flash_en_0 */ \
	13, /* /gpios/flash_spi_cs_0 */ \
	14, /* /gpios/force_call_1 */ \
	15, /* /gpios/gps_en_0 */ \
	16, /* /gpios/hwrev_0 */ \
	17, /* /gpios/mux_sim_sel */ \
	18, /* /gpios/pulsein_1 */ \
	19, /* /gpios/pulsein_2 */ \
	20, /* /gpios/pulseout_0 */ \
	21, /* /gpios/pwr_temp_0 */ \
	22, /* /gpios/spi_cs_0 */ \
	23, /* /gpios/tamper_0 */ \
	24, /* /gpios/vmon_en_0 */ \
	26, /* /leds/led_1 */ \
	27, /* /leds/led_2 */ \
	28, /* /leds/led_3 */ \
	29, /* /leds/led_4 */ \
	86, /* /soc/peripheral@40000000/spi@b000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpio DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_NODELABEL_gpio0        DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_VAL_ADDRESS 1082402048 /* 0x40842500 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg {8660224 /* 0x842500 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_0 8660224
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_1 768
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_label "GPIO_0"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_port 0
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_port_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_gpio_controller 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_ngpios 32
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_EXISTS 1

/*
 * Devicetree node: /gpios/eeprom_en_0
 *
 * Node identifier: DT_N_S_gpios_S_eeprom_en_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_eeprom_en_0_PATH "/gpios/eeprom_en_0"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_eeprom_en_0_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_eeprom_en_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_eeprom_en_0_ORD 10

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_eeprom_en_0_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_eeprom_en_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_eeprom_en_0_EXISTS 1
#define DT_N_ALIAS_eepromen      DT_N_S_gpios_S_eeprom_en_0
#define DT_N_NODELABEL_eeprom_en DT_N_S_gpios_S_eeprom_en_0

/* Special property macros: */
#define DT_N_S_gpios_S_eeprom_en_0_REG_NUM 0
#define DT_N_S_gpios_S_eeprom_en_0_IRQ_NUM 0
#define DT_N_S_gpios_S_eeprom_en_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_eeprom_en_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_eeprom_en_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_eeprom_en_0_P_gpios_IDX_0_VAL_pin 19
#define DT_N_S_gpios_S_eeprom_en_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_eeprom_en_0_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_gpios_S_eeprom_en_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_eeprom_en_0_P_gpios_LEN 1
#define DT_N_S_gpios_S_eeprom_en_0_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_eeprom_en_0_P_label "eeprom en"
#define DT_N_S_gpios_S_eeprom_en_0_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/factory_restore_0
 *
 * Node identifier: DT_N_S_gpios_S_factory_restore_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_factory_restore_0_PATH "/gpios/factory_restore_0"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_factory_restore_0_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_factory_restore_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_factory_restore_0_ORD 11

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_factory_restore_0_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_factory_restore_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_factory_restore_0_EXISTS 1
#define DT_N_ALIAS_factoryrestore      DT_N_S_gpios_S_factory_restore_0
#define DT_N_NODELABEL_factory_restore DT_N_S_gpios_S_factory_restore_0

/* Special property macros: */
#define DT_N_S_gpios_S_factory_restore_0_REG_NUM 0
#define DT_N_S_gpios_S_factory_restore_0_IRQ_NUM 0
#define DT_N_S_gpios_S_factory_restore_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_factory_restore_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_factory_restore_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_factory_restore_0_P_gpios_IDX_0_VAL_pin 27
#define DT_N_S_gpios_S_factory_restore_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_factory_restore_0_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_gpios_S_factory_restore_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_factory_restore_0_P_gpios_LEN 1
#define DT_N_S_gpios_S_factory_restore_0_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_factory_restore_0_P_label "factory restore"
#define DT_N_S_gpios_S_factory_restore_0_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/flash_en_0
 *
 * Node identifier: DT_N_S_gpios_S_flash_en_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_flash_en_0_PATH "/gpios/flash_en_0"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_flash_en_0_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_flash_en_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_flash_en_0_ORD 12

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_flash_en_0_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_flash_en_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_flash_en_0_EXISTS 1
#define DT_N_ALIAS_flashen      DT_N_S_gpios_S_flash_en_0
#define DT_N_NODELABEL_flash_en DT_N_S_gpios_S_flash_en_0

/* Special property macros: */
#define DT_N_S_gpios_S_flash_en_0_REG_NUM 0
#define DT_N_S_gpios_S_flash_en_0_IRQ_NUM 0
#define DT_N_S_gpios_S_flash_en_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_flash_en_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_flash_en_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_flash_en_0_P_gpios_IDX_0_VAL_pin 20
#define DT_N_S_gpios_S_flash_en_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_flash_en_0_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_gpios_S_flash_en_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_flash_en_0_P_gpios_LEN 1
#define DT_N_S_gpios_S_flash_en_0_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_flash_en_0_P_label "flash en"
#define DT_N_S_gpios_S_flash_en_0_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/flash_spi_cs_0
 *
 * Node identifier: DT_N_S_gpios_S_flash_spi_cs_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_flash_spi_cs_0_PATH "/gpios/flash_spi_cs_0"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_flash_spi_cs_0_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_flash_spi_cs_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_flash_spi_cs_0_ORD 13

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_flash_spi_cs_0_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_flash_spi_cs_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_flash_spi_cs_0_EXISTS 1
#define DT_N_ALIAS_flashspics       DT_N_S_gpios_S_flash_spi_cs_0
#define DT_N_NODELABEL_flash_spi_cs DT_N_S_gpios_S_flash_spi_cs_0

/* Special property macros: */
#define DT_N_S_gpios_S_flash_spi_cs_0_REG_NUM 0
#define DT_N_S_gpios_S_flash_spi_cs_0_IRQ_NUM 0
#define DT_N_S_gpios_S_flash_spi_cs_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_flash_spi_cs_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_flash_spi_cs_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_flash_spi_cs_0_P_gpios_IDX_0_VAL_pin 15
#define DT_N_S_gpios_S_flash_spi_cs_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_flash_spi_cs_0_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_gpios_S_flash_spi_cs_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_flash_spi_cs_0_P_gpios_LEN 1
#define DT_N_S_gpios_S_flash_spi_cs_0_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_flash_spi_cs_0_P_label "flash spi cs"
#define DT_N_S_gpios_S_flash_spi_cs_0_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/force_call_1
 *
 * Node identifier: DT_N_S_gpios_S_force_call_1
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_force_call_1_PATH "/gpios/force_call_1"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_force_call_1_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_force_call_1_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_force_call_1_ORD 14

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_force_call_1_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_force_call_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_force_call_1_EXISTS 1
#define DT_N_ALIAS_forcecall      DT_N_S_gpios_S_force_call_1
#define DT_N_NODELABEL_force_call DT_N_S_gpios_S_force_call_1

/* Special property macros: */
#define DT_N_S_gpios_S_force_call_1_REG_NUM 0
#define DT_N_S_gpios_S_force_call_1_IRQ_NUM 0
#define DT_N_S_gpios_S_force_call_1_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_force_call_1_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_force_call_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_force_call_1_P_gpios_IDX_0_VAL_pin 17
#define DT_N_S_gpios_S_force_call_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_force_call_1_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_gpios_S_force_call_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_force_call_1_P_gpios_LEN 1
#define DT_N_S_gpios_S_force_call_1_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_force_call_1_P_label "force call"
#define DT_N_S_gpios_S_force_call_1_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/gps_en_0
 *
 * Node identifier: DT_N_S_gpios_S_gps_en_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_gps_en_0_PATH "/gpios/gps_en_0"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_gps_en_0_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_gps_en_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_gps_en_0_ORD 15

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_gps_en_0_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_gps_en_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_gps_en_0_EXISTS 1
#define DT_N_ALIAS_gpsen      DT_N_S_gpios_S_gps_en_0
#define DT_N_NODELABEL_gps_en DT_N_S_gpios_S_gps_en_0

/* Special property macros: */
#define DT_N_S_gpios_S_gps_en_0_REG_NUM 0
#define DT_N_S_gpios_S_gps_en_0_IRQ_NUM 0
#define DT_N_S_gpios_S_gps_en_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_gps_en_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_gps_en_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_gps_en_0_P_gpios_IDX_0_VAL_pin 25
#define DT_N_S_gpios_S_gps_en_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_gps_en_0_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_gpios_S_gps_en_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_gps_en_0_P_gpios_LEN 1
#define DT_N_S_gpios_S_gps_en_0_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_gps_en_0_P_label "gps en"
#define DT_N_S_gpios_S_gps_en_0_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/hwrev_0
 *
 * Node identifier: DT_N_S_gpios_S_hwrev_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_hwrev_0_PATH "/gpios/hwrev_0"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_hwrev_0_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_hwrev_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_hwrev_0_ORD 16

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_hwrev_0_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_hwrev_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_hwrev_0_EXISTS 1
#define DT_N_ALIAS_hwrev      DT_N_S_gpios_S_hwrev_0
#define DT_N_NODELABEL_hw_rev DT_N_S_gpios_S_hwrev_0

/* Special property macros: */
#define DT_N_S_gpios_S_hwrev_0_REG_NUM 0
#define DT_N_S_gpios_S_hwrev_0_IRQ_NUM 0
#define DT_N_S_gpios_S_hwrev_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_hwrev_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_hwrev_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_hwrev_0_P_gpios_IDX_0_VAL_pin 14
#define DT_N_S_gpios_S_hwrev_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_hwrev_0_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_gpios_S_hwrev_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_hwrev_0_P_gpios_LEN 1
#define DT_N_S_gpios_S_hwrev_0_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_hwrev_0_P_label "hw rev"
#define DT_N_S_gpios_S_hwrev_0_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/mux_sim_sel
 *
 * Node identifier: DT_N_S_gpios_S_mux_sim_sel
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_mux_sim_sel_PATH "/gpios/mux_sim_sel"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_mux_sim_sel_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_mux_sim_sel_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_mux_sim_sel_ORD 17

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_mux_sim_sel_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_mux_sim_sel_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_mux_sim_sel_EXISTS 1

/* Special property macros: */
#define DT_N_S_gpios_S_mux_sim_sel_REG_NUM 0
#define DT_N_S_gpios_S_mux_sim_sel_IRQ_NUM 0
#define DT_N_S_gpios_S_mux_sim_sel_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_mux_sim_sel_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_mux_sim_sel_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_mux_sim_sel_P_gpios_IDX_0_VAL_pin 18
#define DT_N_S_gpios_S_mux_sim_sel_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_mux_sim_sel_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_gpios_S_mux_sim_sel_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_mux_sim_sel_P_gpios_LEN 1
#define DT_N_S_gpios_S_mux_sim_sel_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_mux_sim_sel_P_label "Mux SIM Sel"
#define DT_N_S_gpios_S_mux_sim_sel_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/pulsein_1
 *
 * Node identifier: DT_N_S_gpios_S_pulsein_1
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_pulsein_1_PATH "/gpios/pulsein_1"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_pulsein_1_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_pulsein_1_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_pulsein_1_ORD 18

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_pulsein_1_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_pulsein_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_pulsein_1_EXISTS 1
#define DT_N_ALIAS_pulsein1       DT_N_S_gpios_S_pulsein_1
#define DT_N_NODELABEL_pulse_in_1 DT_N_S_gpios_S_pulsein_1

/* Special property macros: */
#define DT_N_S_gpios_S_pulsein_1_REG_NUM 0
#define DT_N_S_gpios_S_pulsein_1_IRQ_NUM 0
#define DT_N_S_gpios_S_pulsein_1_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_pulsein_1_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_pulsein_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_pulsein_1_P_gpios_IDX_0_VAL_pin 8
#define DT_N_S_gpios_S_pulsein_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_pulsein_1_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_gpios_S_pulsein_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_pulsein_1_P_gpios_LEN 1
#define DT_N_S_gpios_S_pulsein_1_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_pulsein_1_P_label "Pulse in 1"
#define DT_N_S_gpios_S_pulsein_1_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/pulsein_2
 *
 * Node identifier: DT_N_S_gpios_S_pulsein_2
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_pulsein_2_PATH "/gpios/pulsein_2"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_pulsein_2_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_pulsein_2_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_pulsein_2_ORD 19

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_pulsein_2_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_pulsein_2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_pulsein_2_EXISTS 1
#define DT_N_ALIAS_pulsein2       DT_N_S_gpios_S_pulsein_2
#define DT_N_NODELABEL_pulse_in_2 DT_N_S_gpios_S_pulsein_2

/* Special property macros: */
#define DT_N_S_gpios_S_pulsein_2_REG_NUM 0
#define DT_N_S_gpios_S_pulsein_2_IRQ_NUM 0
#define DT_N_S_gpios_S_pulsein_2_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_pulsein_2_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_pulsein_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_pulsein_2_P_gpios_IDX_0_VAL_pin 9
#define DT_N_S_gpios_S_pulsein_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_pulsein_2_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_gpios_S_pulsein_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_pulsein_2_P_gpios_LEN 1
#define DT_N_S_gpios_S_pulsein_2_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_pulsein_2_P_label "Pulse in 2"
#define DT_N_S_gpios_S_pulsein_2_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/pulseout_0
 *
 * Node identifier: DT_N_S_gpios_S_pulseout_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_pulseout_0_PATH "/gpios/pulseout_0"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_pulseout_0_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_pulseout_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_pulseout_0_ORD 20

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_pulseout_0_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_pulseout_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_pulseout_0_EXISTS 1
#define DT_N_ALIAS_pulseout      DT_N_S_gpios_S_pulseout_0
#define DT_N_NODELABEL_pulse_out DT_N_S_gpios_S_pulseout_0

/* Special property macros: */
#define DT_N_S_gpios_S_pulseout_0_REG_NUM 0
#define DT_N_S_gpios_S_pulseout_0_IRQ_NUM 0
#define DT_N_S_gpios_S_pulseout_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_pulseout_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_pulseout_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_pulseout_0_P_gpios_IDX_0_VAL_pin 4
#define DT_N_S_gpios_S_pulseout_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_pulseout_0_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_gpios_S_pulseout_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_pulseout_0_P_gpios_LEN 1
#define DT_N_S_gpios_S_pulseout_0_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_pulseout_0_P_label "pulse output"
#define DT_N_S_gpios_S_pulseout_0_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/pwr_temp_0
 *
 * Node identifier: DT_N_S_gpios_S_pwr_temp_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_pwr_temp_0_PATH "/gpios/pwr_temp_0"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_pwr_temp_0_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_pwr_temp_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_pwr_temp_0_ORD 21

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_pwr_temp_0_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_pwr_temp_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_pwr_temp_0_EXISTS 1
#define DT_N_ALIAS_pwrtemp      DT_N_S_gpios_S_pwr_temp_0
#define DT_N_NODELABEL_pwr_temp DT_N_S_gpios_S_pwr_temp_0

/* Special property macros: */
#define DT_N_S_gpios_S_pwr_temp_0_REG_NUM 0
#define DT_N_S_gpios_S_pwr_temp_0_IRQ_NUM 0
#define DT_N_S_gpios_S_pwr_temp_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_pwr_temp_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_pwr_temp_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_pwr_temp_0_P_gpios_IDX_0_VAL_pin 20
#define DT_N_S_gpios_S_pwr_temp_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_pwr_temp_0_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_gpios_S_pwr_temp_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_pwr_temp_0_P_gpios_LEN 1
#define DT_N_S_gpios_S_pwr_temp_0_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_pwr_temp_0_P_label "pwr temp"
#define DT_N_S_gpios_S_pwr_temp_0_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/spi_cs_0
 *
 * Node identifier: DT_N_S_gpios_S_spi_cs_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_spi_cs_0_PATH "/gpios/spi_cs_0"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_spi_cs_0_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_spi_cs_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_spi_cs_0_ORD 22

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_spi_cs_0_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_spi_cs_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_spi_cs_0_EXISTS 1
#define DT_N_ALIAS_spics      DT_N_S_gpios_S_spi_cs_0
#define DT_N_NODELABEL_spi_cs DT_N_S_gpios_S_spi_cs_0

/* Special property macros: */
#define DT_N_S_gpios_S_spi_cs_0_REG_NUM 0
#define DT_N_S_gpios_S_spi_cs_0_IRQ_NUM 0
#define DT_N_S_gpios_S_spi_cs_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_spi_cs_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_spi_cs_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_spi_cs_0_P_gpios_IDX_0_VAL_pin 29
#define DT_N_S_gpios_S_spi_cs_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_spi_cs_0_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_gpios_S_spi_cs_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_spi_cs_0_P_gpios_LEN 1
#define DT_N_S_gpios_S_spi_cs_0_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_spi_cs_0_P_label "spi cs"
#define DT_N_S_gpios_S_spi_cs_0_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/tamper_0
 *
 * Node identifier: DT_N_S_gpios_S_tamper_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_tamper_0_PATH "/gpios/tamper_0"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_tamper_0_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_tamper_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_tamper_0_ORD 23

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_tamper_0_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_tamper_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_tamper_0_EXISTS 1
#define DT_N_ALIAS_tamper     DT_N_S_gpios_S_tamper_0
#define DT_N_NODELABEL_tamper DT_N_S_gpios_S_tamper_0

/* Special property macros: */
#define DT_N_S_gpios_S_tamper_0_REG_NUM 0
#define DT_N_S_gpios_S_tamper_0_IRQ_NUM 0
#define DT_N_S_gpios_S_tamper_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_tamper_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_tamper_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_tamper_0_P_gpios_IDX_0_VAL_pin 26
#define DT_N_S_gpios_S_tamper_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_tamper_0_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_gpios_S_tamper_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_tamper_0_P_gpios_LEN 1
#define DT_N_S_gpios_S_tamper_0_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_tamper_0_P_label "tamper"
#define DT_N_S_gpios_S_tamper_0_P_label_EXISTS 1

/*
 * Devicetree node: /gpios/vmon_en_0
 *
 * Node identifier: DT_N_S_gpios_S_vmon_en_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpios_S_vmon_en_0_PATH "/gpios/vmon_en_0"

/* Node parent (/gpios) identifier: */
#define DT_N_S_gpios_S_vmon_en_0_PARENT DT_N_S_gpios
#define DT_N_S_gpios_S_vmon_en_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_gpios_S_vmon_en_0_ORD 24

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpios_S_vmon_en_0_REQUIRES_ORDS \
	6, /* /gpios */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpios_S_vmon_en_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpios_S_vmon_en_0_EXISTS 1
#define DT_N_ALIAS_vmonen      DT_N_S_gpios_S_vmon_en_0
#define DT_N_NODELABEL_vmon_en DT_N_S_gpios_S_vmon_en_0

/* Special property macros: */
#define DT_N_S_gpios_S_vmon_en_0_REG_NUM 0
#define DT_N_S_gpios_S_vmon_en_0_IRQ_NUM 0
#define DT_N_S_gpios_S_vmon_en_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_gpios_S_vmon_en_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpios_S_vmon_en_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_gpios_S_vmon_en_0_P_gpios_IDX_0_VAL_pin 23
#define DT_N_S_gpios_S_vmon_en_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpios_S_vmon_en_0_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_gpios_S_vmon_en_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpios_S_vmon_en_0_P_gpios_LEN 1
#define DT_N_S_gpios_S_vmon_en_0_P_gpios_EXISTS 1
#define DT_N_S_gpios_S_vmon_en_0_P_label "vmon en"
#define DT_N_S_gpios_S_vmon_en_0_P_label_EXISTS 1

/*
 * Devicetree node: /leds
 *
 * Node identifier: DT_N_S_leds
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_PATH "/leds"

/* Node parent (/) identifier: */
#define DT_N_S_leds_PARENT DT_N
#define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_leds_S_led_4)

/* Node's dependency ordinal: */
#define DT_N_S_leds_ORD 25

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_SUPPORTS_ORDS \
	26, /* /leds/led_1 */ \
	27, /* /leds/led_2 */ \
	28, /* /leds/led_3 */ \
	29, /* /leds/led_4 */

/* Existence and alternate IDs: */
#define DT_N_S_leds_EXISTS 1
#define DT_N_INST_0_gpio_leds DT_N_S_leds

/* Special property macros: */
#define DT_N_S_leds_REG_NUM 0
#define DT_N_S_leds_IRQ_NUM 0
#define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1
#define DT_N_S_leds_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_P_compatible {"gpio-leds"}
#define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds"
#define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_leds_P_compatible_LEN 1
#define DT_N_S_leds_P_compatible_EXISTS 1

/*
 * Devicetree node: /leds/led_1
 *
 * Node identifier: DT_N_S_leds_S_led_1
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_1_PATH "/leds/led_1"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_1_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_1_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_1_ORD 26

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_1_REQUIRES_ORDS \
	9, /* /soc/peripheral@40000000/gpio@842500 */ \
	25, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_1_EXISTS 1
#define DT_N_ALIAS_led1     DT_N_S_leds_S_led_1
#define DT_N_NODELABEL_led1 DT_N_S_leds_S_led_1

/* Special property macros: */
#define DT_N_S_leds_S_led_1_REG_NUM 0
#define DT_N_S_leds_S_led_1_IRQ_NUM 0
#define DT_N_S_leds_S_led_1_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin 0
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_LEN 1
#define DT_N_S_leds_S_led_1_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_1_P_label "Green LED 1"
#define DT_N_S_leds_S_led_1_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_2
 *
 * Node identifier: DT_N_S_leds_S_led_2
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_2_PATH "/leds/led_2"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_2_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_2_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_2_ORD 27

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_2_REQUIRES_ORDS \
	9, /* /soc/peripheral@40000000/gpio@842500 */ \
	25, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_2_EXISTS 1
#define DT_N_ALIAS_led2     DT_N_S_leds_S_led_2
#define DT_N_NODELABEL_led2 DT_N_S_leds_S_led_2

/* Special property macros: */
#define DT_N_S_leds_S_led_2_REG_NUM 0
#define DT_N_S_leds_S_led_2_IRQ_NUM 0
#define DT_N_S_leds_S_led_2_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_LEN 1
#define DT_N_S_leds_S_led_2_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_2_P_label "Green LED 2"
#define DT_N_S_leds_S_led_2_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_3
 *
 * Node identifier: DT_N_S_leds_S_led_3
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_3_PATH "/leds/led_3"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_3_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_3_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_3_ORD 28

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_3_REQUIRES_ORDS \
	9, /* /soc/peripheral@40000000/gpio@842500 */ \
	25, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_3_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_3_EXISTS 1
#define DT_N_ALIAS_led3     DT_N_S_leds_S_led_3
#define DT_N_NODELABEL_led3 DT_N_S_leds_S_led_3

/* Special property macros: */
#define DT_N_S_leds_S_led_3_REG_NUM 0
#define DT_N_S_leds_S_led_3_IRQ_NUM 0
#define DT_N_S_leds_S_led_3_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin 2
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_LEN 1
#define DT_N_S_leds_S_led_3_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_3_P_label "Green LED 3"
#define DT_N_S_leds_S_led_3_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_4
 *
 * Node identifier: DT_N_S_leds_S_led_4
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_4_PATH "/leds/led_4"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_4_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_4_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_4_ORD 29

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_4_REQUIRES_ORDS \
	9, /* /soc/peripheral@40000000/gpio@842500 */ \
	25, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_4_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_4_EXISTS 1
#define DT_N_ALIAS_led4     DT_N_S_leds_S_led_4
#define DT_N_NODELABEL_led4 DT_N_S_leds_S_led_4

/* Special property macros: */
#define DT_N_S_leds_S_led_4_REG_NUM 0
#define DT_N_S_leds_S_led_4_IRQ_NUM 0
#define DT_N_S_leds_S_led_4_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_4_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_4_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_leds_S_led_4_P_gpios_IDX_0_VAL_pin 3
#define DT_N_S_leds_S_led_4_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_4_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_4_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_4_P_gpios_LEN 1
#define DT_N_S_leds_S_led_4_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_4_P_label "Red LED 4"
#define DT_N_S_leds_S_led_4_P_label_EXISTS 1

/*
 * Devicetree node: /reserved-memory
 *
 * Node identifier: DT_N_S_reserved_memory
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_PATH "/reserved-memory"

/* Node parent (/) identifier: */
#define DT_N_S_reserved_memory_PARENT DT_N
#define DT_N_S_reserved_memory_FOREACH_CHILD(fn) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_bsd_20010000) fn(DT_N_S_reserved_memory_S_image_ns_20020000)

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_ORD 30

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_SUPPORTS_ORDS \
	31, /* /reserved-memory/image_bsd@20010000 */ \
	32, /* /reserved-memory/image_ns@20020000 */ \
	33, /* /reserved-memory/image_s@20000000 */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_EXISTS 1

/* Special property macros: */
#define DT_N_S_reserved_memory_REG_NUM 0
#define DT_N_S_reserved_memory_IRQ_NUM 0
#define DT_N_S_reserved_memory_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /reserved-memory/image_bsd@20010000
 *
 * Node identifier: DT_N_S_reserved_memory_S_image_bsd_20010000
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_S_image_bsd_20010000_PATH "/reserved-memory/image_bsd@20010000"

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_bsd_20010000_PARENT DT_N_S_reserved_memory
#define DT_N_S_reserved_memory_S_image_bsd_20010000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_S_image_bsd_20010000_ORD 31

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_S_image_bsd_20010000_REQUIRES_ORDS \
	30, /* /reserved-memory */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_S_image_bsd_20010000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_bsd_20010000_EXISTS 1
#define DT_N_NODELABEL_sram0_bsd DT_N_S_reserved_memory_S_image_bsd_20010000

/* Special property macros: */
#define DT_N_S_reserved_memory_S_image_bsd_20010000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_bsd_20010000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_bsd_20010000_REG_IDX_0_VAL_ADDRESS 536936448 /* 0x20010000 */
#define DT_N_S_reserved_memory_S_image_bsd_20010000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_reserved_memory_S_image_bsd_20010000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_bsd_20010000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_bsd_20010000_P_reg {536936448 /* 0x20010000 */, 65536 /* 0x10000 */}
#define DT_N_S_reserved_memory_S_image_bsd_20010000_P_reg_IDX_0 536936448
#define DT_N_S_reserved_memory_S_image_bsd_20010000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_bsd_20010000_P_reg_IDX_1 65536
#define DT_N_S_reserved_memory_S_image_bsd_20010000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_reserved_memory_S_image_bsd_20010000_P_reg_EXISTS 1

/*
 * Devicetree node: /reserved-memory/image_ns@20020000
 *
 * Node identifier: DT_N_S_reserved_memory_S_image_ns_20020000
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_PATH "/reserved-memory/image_ns@20020000"

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_PARENT DT_N_S_reserved_memory
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_ORD 32

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_REQUIRES_ORDS \
	30, /* /reserved-memory */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_EXISTS 1
#define DT_N_NODELABEL_sram0_ns DT_N_S_reserved_memory_S_image_ns_20020000

/* Special property macros: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_ADDRESS 537001984 /* 0x20020000 */
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_SIZE 131072 /* 0x20000 */
#define DT_N_S_reserved_memory_S_image_ns_20020000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_ns_20020000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg {537001984 /* 0x20020000 */, 131072 /* 0x20000 */}
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0 537001984
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1 131072
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_EXISTS 1

/*
 * Devicetree node: /reserved-memory/image_s@20000000
 *
 * Node identifier: DT_N_S_reserved_memory_S_image_s_20000000
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_S_image_s_20000000_PATH "/reserved-memory/image_s@20000000"

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_s_20000000_PARENT DT_N_S_reserved_memory
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_S_image_s_20000000_ORD 33

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_S_image_s_20000000_REQUIRES_ORDS \
	30, /* /reserved-memory */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_S_image_s_20000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_s_20000000_EXISTS 1
#define DT_N_NODELABEL_sram0_s DT_N_S_reserved_memory_S_image_s_20000000

/* Special property macros: */
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_s_20000000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg {536870912 /* 0x20000000 */, 65536 /* 0x10000 */}
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0 536870912
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1 65536
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/cryptocell-sw
 *
 * Node identifier: DT_N_S_soc_S_cryptocell_sw
 *
 * Binding (compatible = nordic,nrf-cc310-sw):
 *   $ZEPHYR_BASE\dts\bindings\crypto\nordic,nrf-cc310-sw.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_cryptocell_sw_PATH "/soc/cryptocell-sw"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_cryptocell_sw_PARENT DT_N_S_soc
#define DT_N_S_soc_S_cryptocell_sw_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_cryptocell_sw_ORD 34

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_cryptocell_sw_REQUIRES_ORDS \
	7, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_cryptocell_sw_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_cryptocell_sw_EXISTS 1
#define DT_N_INST_0_nordic_nrf_cc310_sw DT_N_S_soc_S_cryptocell_sw
#define DT_N_NODELABEL_cryptocell_sw    DT_N_S_soc_S_cryptocell_sw

/* Special property macros: */
#define DT_N_S_soc_S_cryptocell_sw_REG_NUM 0
#define DT_N_S_soc_S_cryptocell_sw_IRQ_NUM 0
#define DT_N_S_soc_S_cryptocell_sw_COMPAT_MATCHES_nordic_nrf_cc310_sw 1
#define DT_N_S_soc_S_cryptocell_sw_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_cryptocell_sw_P_label "CRYPTOCELL_SW"
#define DT_N_S_soc_S_cryptocell_sw_P_label_EXISTS 1
#define DT_N_S_soc_S_cryptocell_sw_P_compatible {"nordic,nrf-cc310-sw"}
#define DT_N_S_soc_S_cryptocell_sw_P_compatible_IDX_0 "nordic,nrf-cc310-sw"
#define DT_N_S_soc_S_cryptocell_sw_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_cryptocell_sw_P_compatible_LEN 1
#define DT_N_S_soc_S_cryptocell_sw_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/interrupt-controller@e000e100
 *
 * Node identifier: DT_N_S_soc_S_interrupt_controller_e000e100
 *
 * Binding (compatible = arm,v8m-nvic):
 *   $ZEPHYR_BASE\dts\bindings\interrupt-controller\arm,v8m-nvic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PATH "/soc/interrupt-controller@e000e100"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD 35

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS \
	7, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \
	36, /* /soc/gpiote@40031000 */ \
	39, /* /soc/peripheral@40000000/adc@e000 */ \
	40, /* /soc/peripheral@40000000/clock@5000 */ \
	42, /* /soc/peripheral@40000000/egu@1b000 */ \
	43, /* /soc/peripheral@40000000/egu@1c000 */ \
	44, /* /soc/peripheral@40000000/egu@1d000 */ \
	45, /* /soc/peripheral@40000000/egu@1e000 */ \
	46, /* /soc/peripheral@40000000/egu@1f000 */ \
	47, /* /soc/peripheral@40000000/egu@20000 */ \
	48, /* /soc/peripheral@40000000/i2c@8000 */ \
	49, /* /soc/peripheral@40000000/i2c@a000 */ \
	50, /* /soc/peripheral@40000000/i2c@b000 */ \
	51, /* /soc/peripheral@40000000/i2s@28000 */ \
	52, /* /soc/peripheral@40000000/kmu@39000 */ \
	53, /* /soc/peripheral@40000000/pdm@26000 */ \
	54, /* /soc/peripheral@40000000/power@5000 */ \
	55, /* /soc/peripheral@40000000/pwm@21000 */ \
	56, /* /soc/peripheral@40000000/pwm@22000 */ \
	57, /* /soc/peripheral@40000000/pwm@23000 */ \
	58, /* /soc/peripheral@40000000/pwm@24000 */ \
	60, /* /soc/peripheral@40000000/rtc@14000 */ \
	61, /* /soc/peripheral@40000000/rtc@15000 */ \
	62, /* /soc/peripheral@40000000/spi@8000 */ \
	63, /* /soc/peripheral@40000000/spi@9000 */ \
	64, /* /soc/peripheral@40000000/spi@a000 */ \
	65, /* /soc/peripheral@40000000/timer@f000 */ \
	66, /* /soc/peripheral@40000000/timer@10000 */ \
	67, /* /soc/peripheral@40000000/timer@11000 */ \
	68, /* /soc/peripheral@40000000/uart@8000 */ \
	69, /* /soc/peripheral@40000000/uart@9000 */ \
	70, /* /soc/peripheral@40000000/uart@a000 */ \
	71, /* /soc/peripheral@40000000/uart@b000 */ \
	73, /* /soc/peripheral@40000000/watchdog@18000 */ \
	84, /* /soc/peripheral@40000000/i2c@9000 */ \
	86, /* /soc/peripheral@40000000/spi@b000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1
#define DT_N_INST_0_arm_v8m_nvic DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_NODELABEL_nvic      DT_N_S_soc_S_interrupt_controller_e000e100

/* Special property macros: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 3
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v8m-nvic"}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v8m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/gpiote@40031000
 *
 * Node identifier: DT_N_S_soc_S_gpiote_40031000
 *
 * Binding (compatible = nordic,nrf-gpiote):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpiote.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_gpiote_40031000_PATH "/soc/gpiote@40031000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpiote_40031000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpiote_40031000_ORD 36

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpiote_40031000_REQUIRES_ORDS \
	7, /* /soc */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpiote_40031000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpiote_40031000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_40031000
#define DT_N_NODELABEL_gpiote         DT_N_S_soc_S_gpiote_40031000

/* Special property macros: */
#define DT_N_S_soc_S_gpiote_40031000_REG_NUM 1
#define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_VAL_ADDRESS 1073942528 /* 0x40031000 */
#define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_gpiote_40031000_IRQ_NUM 1
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_irq 49
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_priority 5
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_COMPAT_MATCHES_nordic_nrf_gpiote 1
#define DT_N_S_soc_S_gpiote_40031000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_gpiote_40031000_P_reg {1073942528 /* 0x40031000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_0 1073942528
#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts {49 /* 0x31 */, 5 /* 0x5 */}
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_0 49
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_1 5
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_P_label "GPIOTE_1"
#define DT_N_S_soc_S_gpiote_40031000_P_label_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_P_status "okay"
#define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpiote_40031000_P_status_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_P_compatible {"nordic,nrf-gpiote"}
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0 "nordic,nrf-gpiote"
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_LEN 1
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/memory@20000000
 *
 * Node identifier: DT_N_S_soc_S_memory_20000000
 *
 * Binding (compatible = mmio-sram):
 *   $ZEPHYR_BASE\dts\bindings\sram\mmio-sram.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_20000000_PATH "/soc/memory@20000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_20000000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_20000000_ORD 37

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS \
	7, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_20000000_EXISTS 1
#define DT_N_INST_0_mmio_sram DT_N_S_soc_S_memory_20000000
#define DT_N_NODELABEL_sram0  DT_N_S_soc_S_memory_20000000

/* Special property macros: */
#define DT_N_S_soc_S_memory_20000000_REG_NUM 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_memory_20000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_20000000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0 536870912
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible {"mmio-sram"}
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0 "mmio-sram"
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/timer@e000e010
 *
 * Node identifier: DT_N_S_soc_S_timer_e000e010
 */

/* Node's full path: */
#define DT_N_S_soc_S_timer_e000e010_PATH "/soc/timer@e000e010"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_e000e010_ORD 38

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \
	7, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_e000e010_EXISTS 1
#define DT_N_INST_0_arm_armv8m_systick DT_N_S_soc_S_timer_e000e010
#define DT_N_NODELABEL_systick         DT_N_S_soc_S_timer_e000e010

/* Special property macros: */
#define DT_N_S_soc_S_timer_e000e010_REG_NUM 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */
#define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick 1
#define DT_N_S_soc_S_timer_e000e010_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv8m-systick"}
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv8m-systick"
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_status "disabled"
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_e000e010_P_status_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/adc@e000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_adc_e000
 *
 * Binding (compatible = nordic,nrf-saadc):
 *   $ZEPHYR_BASE\dts\bindings\adc\nordic,nrf-saadc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_PATH "/soc/peripheral@40000000/adc@e000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_ORD 39

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_saadc DT_N_S_soc_S_peripheral_40000000_S_adc_e000
#define DT_N_NODELABEL_adc           DT_N_S_soc_S_peripheral_40000000_S_adc_e000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_VAL_ADDRESS 1073799168 /* 0x4000e000 */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_irq 14
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_COMPAT_MATCHES_nordic_nrf_saadc 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg {57344 /* 0xe000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_0 57344
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts {14 /* 0xe */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_0 14
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_label "ADC_0"
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible {"nordic,nrf-saadc"}
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0 "nordic,nrf-saadc"
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/clock@5000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_clock_5000
 *
 * Binding (compatible = nordic,nrf-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\nordic,nrf-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_PATH "/soc/peripheral@40000000/clock@5000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_ORD 40

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_clock DT_N_S_soc_S_peripheral_40000000_S_clock_5000
#define DT_N_NODELABEL_clock         DT_N_S_soc_S_peripheral_40000000_S_clock_5000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_VAL_ADDRESS 1073762304 /* 0x40005000 */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_irq 5
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_COMPAT_MATCHES_nordic_nrf_clock 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_label "CLOCK"
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_0 20480
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_0 5
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible {"nordic,nrf-clock"}
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0 "nordic,nrf-clock"
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/dppic@17000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_dppic_17000
 *
 * Binding (compatible = nordic,nrf-dppic):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-dppic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_PATH "/soc/peripheral@40000000/dppic@17000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_ORD 41

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_dppic DT_N_S_soc_S_peripheral_40000000_S_dppic_17000
#define DT_N_NODELABEL_dppic         DT_N_S_soc_S_peripheral_40000000_S_dppic_17000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_VAL_ADDRESS 1073836032 /* 0x40017000 */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_COMPAT_MATCHES_nordic_nrf_dppic 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg {94208 /* 0x17000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_0 94208
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible {"nordic,nrf-dppic"}
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0 "nordic,nrf-dppic"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_label "DPPIC"
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/egu@1b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_egu_1b000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_PATH "/soc/peripheral@40000000/egu@1b000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_ORD 42

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_egu DT_N_S_soc_S_peripheral_40000000_S_egu_1b000
#define DT_N_NODELABEL_egu0        DT_N_S_soc_S_peripheral_40000000_S_egu_1b000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_VAL_ADDRESS 1073852416 /* 0x4001b000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_irq 27
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg {110592 /* 0x1b000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_0 110592
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts {27 /* 0x1b */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_0 27
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/egu@1c000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_egu_1c000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_PATH "/soc/peripheral@40000000/egu@1c000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_ORD 43

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_egu DT_N_S_soc_S_peripheral_40000000_S_egu_1c000
#define DT_N_NODELABEL_egu1        DT_N_S_soc_S_peripheral_40000000_S_egu_1c000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_VAL_ADDRESS 1073856512 /* 0x4001c000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_irq 28
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg {114688 /* 0x1c000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_0 114688
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts {28 /* 0x1c */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_0 28
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/egu@1d000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_egu_1d000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_PATH "/soc/peripheral@40000000/egu@1d000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_ORD 44

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_egu DT_N_S_soc_S_peripheral_40000000_S_egu_1d000
#define DT_N_NODELABEL_egu2        DT_N_S_soc_S_peripheral_40000000_S_egu_1d000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_VAL_ADDRESS 1073860608 /* 0x4001d000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_irq 29
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg {118784 /* 0x1d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_0 118784
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts {29 /* 0x1d */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_0 29
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/egu@1e000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_egu_1e000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_PATH "/soc/peripheral@40000000/egu@1e000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_ORD 45

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_egu DT_N_S_soc_S_peripheral_40000000_S_egu_1e000
#define DT_N_NODELABEL_egu3        DT_N_S_soc_S_peripheral_40000000_S_egu_1e000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_VAL_ADDRESS 1073864704 /* 0x4001e000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_irq 30
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg {122880 /* 0x1e000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_0 122880
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts {30 /* 0x1e */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_0 30
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/egu@1f000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_egu_1f000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_PATH "/soc/peripheral@40000000/egu@1f000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_ORD 46

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_EXISTS 1
#define DT_N_INST_4_nordic_nrf_egu DT_N_S_soc_S_peripheral_40000000_S_egu_1f000
#define DT_N_NODELABEL_egu4        DT_N_S_soc_S_peripheral_40000000_S_egu_1f000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_VAL_ADDRESS 1073868800 /* 0x4001f000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_irq 31
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg {126976 /* 0x1f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_0 126976
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts {31 /* 0x1f */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_0 31
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/egu@20000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_egu_20000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_PATH "/soc/peripheral@40000000/egu@20000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_ORD 47

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_EXISTS 1
#define DT_N_INST_5_nordic_nrf_egu DT_N_S_soc_S_peripheral_40000000_S_egu_20000
#define DT_N_NODELABEL_egu5        DT_N_S_soc_S_peripheral_40000000_S_egu_20000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_VAL_ADDRESS 1073872896 /* 0x40020000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_irq 32
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg {131072 /* 0x20000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_0 131072
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts {32 /* 0x20 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_0 32
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/i2c@8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_i2c_8000
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_PATH "/soc/peripheral@40000000/i2c@8000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_ORD 48

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_EXISTS 1
#define DT_N_NODELABEL_i2c0 DT_N_S_soc_S_peripheral_40000000_S_i2c_8000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_VAL_ADDRESS 1073774592 /* 0x40008000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_label "I2C_0"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/i2c@a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_i2c_a000
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_PATH "/soc/peripheral@40000000/i2c@a000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_ORD 49

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_EXISTS 1
#define DT_N_NODELABEL_i2c2 DT_N_S_soc_S_peripheral_40000000_S_i2c_a000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_VAL_ADDRESS 1073782784 /* 0x4000a000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_irq 10
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_0 40960
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_0 10
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_label "I2C_2"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/i2c@b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_i2c_b000
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_PATH "/soc/peripheral@40000000/i2c@b000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_ORD 50

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_EXISTS 1
#define DT_N_NODELABEL_i2c3 DT_N_S_soc_S_peripheral_40000000_S_i2c_b000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_VAL_ADDRESS 1073786880 /* 0x4000b000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_label "I2C_3"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/i2s@28000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_i2s_28000
 *
 * Binding (compatible = nordic,nrf-i2s):
 *   $ZEPHYR_BASE\dts\bindings\i2s\nordic,nrf-i2s.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_PATH "/soc/peripheral@40000000/i2s@28000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_ORD 51

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_i2s DT_N_S_soc_S_peripheral_40000000_S_i2s_28000
#define DT_N_NODELABEL_i2s0        DT_N_S_soc_S_peripheral_40000000_S_i2s_28000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_VAL_ADDRESS 1073905664 /* 0x40028000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_irq 40
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_COMPAT_MATCHES_nordic_nrf_i2s 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg {163840 /* 0x28000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_0 163840
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts {40 /* 0x28 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_0 40
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_label "I2S_0"
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible {"nordic,nrf-i2s"}
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0 "nordic,nrf-i2s"
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/kmu@39000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_kmu_39000
 *
 * Binding (compatible = nordic,nrf-kmu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-kmu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_PATH "/soc/peripheral@40000000/kmu@39000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_ORD 52

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_kmu DT_N_S_soc_S_peripheral_40000000_S_kmu_39000
#define DT_N_NODELABEL_kmu         DT_N_S_soc_S_peripheral_40000000_S_kmu_39000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_VAL_ADDRESS 1073975296 /* 0x40039000 */
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_irq 57
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_COMPAT_MATCHES_nordic_nrf_kmu 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_0 233472
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts {57 /* 0x39 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_0 57
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible {"nordic,nrf-kmu"}
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0 "nordic,nrf-kmu"
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/pdm@26000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_pdm_26000
 *
 * Binding (compatible = nordic,nrf-pdm):
 *   $ZEPHYR_BASE\dts\bindings\audio\nordic,nrf-pdm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_PATH "/soc/peripheral@40000000/pdm@26000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_ORD 53

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pdm DT_N_S_soc_S_peripheral_40000000_S_pdm_26000
#define DT_N_NODELABEL_pdm0        DT_N_S_soc_S_peripheral_40000000_S_pdm_26000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_VAL_ADDRESS 1073897472 /* 0x40026000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_irq 38
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_COMPAT_MATCHES_nordic_nrf_pdm 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg {155648 /* 0x26000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_0 155648
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts {38 /* 0x26 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_0 38
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible {"nordic,nrf-pdm"}
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0 "nordic,nrf-pdm"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_label "PDM_0"
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/power@5000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_power_5000
 *
 * Binding (compatible = nordic,nrf-power):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-power.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_PATH "/soc/peripheral@40000000/power@5000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_ORD 54

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_power DT_N_S_soc_S_peripheral_40000000_S_power_5000
#define DT_N_NODELABEL_power         DT_N_S_soc_S_peripheral_40000000_S_power_5000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_VAL_ADDRESS 1073762304 /* 0x40005000 */
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_irq 5
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_COMPAT_MATCHES_nordic_nrf_power 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_0 20480
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_0 5
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible {"nordic,nrf-power"}
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0 "nordic,nrf-power"
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/pwm@21000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_pwm_21000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_PATH "/soc/peripheral@40000000/pwm@21000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_ORD 55

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pwm DT_N_S_soc_S_peripheral_40000000_S_pwm_21000
#define DT_N_NODELABEL_pwm0        DT_N_S_soc_S_peripheral_40000000_S_pwm_21000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_VAL_ADDRESS 1073876992 /* 0x40021000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_irq 33
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg {135168 /* 0x21000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_0 135168
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_label "PWM_0"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts {33 /* 0x21 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_0 33
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/pwm@22000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_pwm_22000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_PATH "/soc/peripheral@40000000/pwm@22000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_ORD 56

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_pwm DT_N_S_soc_S_peripheral_40000000_S_pwm_22000
#define DT_N_NODELABEL_pwm1        DT_N_S_soc_S_peripheral_40000000_S_pwm_22000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_VAL_ADDRESS 1073881088 /* 0x40022000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_irq 34
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg {139264 /* 0x22000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_0 139264
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_label "PWM_1"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts {34 /* 0x22 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_0 34
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/pwm@23000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_pwm_23000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_PATH "/soc/peripheral@40000000/pwm@23000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_ORD 57

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_pwm DT_N_S_soc_S_peripheral_40000000_S_pwm_23000
#define DT_N_NODELABEL_pwm2        DT_N_S_soc_S_peripheral_40000000_S_pwm_23000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_VAL_ADDRESS 1073885184 /* 0x40023000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_irq 35
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg {143360 /* 0x23000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_0 143360
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_label "PWM_2"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts {35 /* 0x23 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_0 35
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/pwm@24000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_pwm_24000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_PATH "/soc/peripheral@40000000/pwm@24000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_ORD 58

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_pwm DT_N_S_soc_S_peripheral_40000000_S_pwm_24000
#define DT_N_NODELABEL_pwm3        DT_N_S_soc_S_peripheral_40000000_S_pwm_24000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_VAL_ADDRESS 1073889280 /* 0x40024000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_irq 36
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg {147456 /* 0x24000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_0 147456
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_label "PWM_3"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts {36 /* 0x24 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_0 36
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/regulator@4000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_regulator_4000
 *
 * Binding (compatible = nordic,nrf-regulators):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-regulators.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_PATH "/soc/peripheral@40000000/regulator@4000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_ORD 59

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_regulators DT_N_S_soc_S_peripheral_40000000_S_regulator_4000
#define DT_N_NODELABEL_regulators         DT_N_S_soc_S_peripheral_40000000_S_regulator_4000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_VAL_ADDRESS 1073758208 /* 0x40004000 */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_COMPAT_MATCHES_nordic_nrf_regulators 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg {16384 /* 0x4000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_0 16384
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible {"nordic,nrf-regulators"}
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0 "nordic,nrf-regulators"
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/rtc@14000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_rtc_14000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_PATH "/soc/peripheral@40000000/rtc@14000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_ORD 60

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_rtc DT_N_S_soc_S_peripheral_40000000_S_rtc_14000
#define DT_N_NODELABEL_rtc0        DT_N_S_soc_S_peripheral_40000000_S_rtc_14000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_VAL_ADDRESS 1073823744 /* 0x40014000 */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_irq 20
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg {81920 /* 0x14000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_0 81920
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_cc_num 4
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_ppi_wrap 0
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_fixed_top 0
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_clock_frequency 32768
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_label "RTC_0"
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts {20 /* 0x14 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_0 20
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_prescaler 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/rtc@15000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_rtc_15000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_PATH "/soc/peripheral@40000000/rtc@15000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_ORD 61

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_rtc DT_N_S_soc_S_peripheral_40000000_S_rtc_15000
#define DT_N_NODELABEL_rtc1        DT_N_S_soc_S_peripheral_40000000_S_rtc_15000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_VAL_ADDRESS 1073827840 /* 0x40015000 */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_irq 21
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg {86016 /* 0x15000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_0 86016
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_cc_num 4
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_ppi_wrap 0
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_fixed_top 0
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_clock_frequency 32768
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_label "RTC_1"
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts {21 /* 0x15 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_0 21
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_prescaler 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_8000
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_PATH "/soc/peripheral@40000000/spi@8000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_ORD 62

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_EXISTS 1
#define DT_N_NODELABEL_spi0 DT_N_S_soc_S_peripheral_40000000_S_spi_8000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_VAL_ADDRESS 1073774592 /* 0x40008000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_label "SPI_0"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@9000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_9000
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_PATH "/soc/peripheral@40000000/spi@9000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_ORD 63

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_EXISTS 1
#define DT_N_NODELABEL_spi1 DT_N_S_soc_S_peripheral_40000000_S_spi_9000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_VAL_ADDRESS 1073778688 /* 0x40009000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_label "SPI_1"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_a000
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PATH "/soc/peripheral@40000000/spi@a000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_ORD 64

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_EXISTS 1
#define DT_N_NODELABEL_spi2 DT_N_S_soc_S_peripheral_40000000_S_spi_a000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_VAL_ADDRESS 1073782784 /* 0x4000a000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_irq 10
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_0 40960
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_0 10
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_label "SPI_2"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/timer@f000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_timer_f000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_PATH "/soc/peripheral@40000000/timer@f000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_ORD 65

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_timer DT_N_S_soc_S_peripheral_40000000_S_timer_f000
#define DT_N_NODELABEL_timer0        DT_N_S_soc_S_peripheral_40000000_S_timer_f000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_VAL_ADDRESS 1073803264 /* 0x4000f000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_irq 15
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg {61440 /* 0xf000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_0 61440
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts {15 /* 0xf */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_0 15
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_label "TIMER_0"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/timer@10000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_timer_10000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_PATH "/soc/peripheral@40000000/timer@10000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_ORD 66

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_timer DT_N_S_soc_S_peripheral_40000000_S_timer_10000
#define DT_N_NODELABEL_timer1        DT_N_S_soc_S_peripheral_40000000_S_timer_10000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_VAL_ADDRESS 1073807360 /* 0x40010000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_irq 16
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg {65536 /* 0x10000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_0 65536
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts {16 /* 0x10 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_0 16
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_label "TIMER_1"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/timer@11000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_timer_11000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_PATH "/soc/peripheral@40000000/timer@11000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_ORD 67

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_timer DT_N_S_soc_S_peripheral_40000000_S_timer_11000
#define DT_N_NODELABEL_timer2        DT_N_S_soc_S_peripheral_40000000_S_timer_11000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_VAL_ADDRESS 1073811456 /* 0x40011000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_irq 17
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg {69632 /* 0x11000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_0 69632
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts {17 /* 0x11 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_0 17
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_label "TIMER_2"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/uart@8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_uart_8000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PATH "/soc/peripheral@40000000/uart@8000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_ORD 68

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_uarte DT_N_S_soc_S_peripheral_40000000_S_uart_8000
#define DT_N_NODELABEL_uart0         DT_N_S_soc_S_peripheral_40000000_S_uart_8000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_VAL_ADDRESS 1073774592 /* 0x40008000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_tx_pin 5
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_tx_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_rx_pin 6
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_rx_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_current_speed 115200
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_label "UART_0"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/uart@9000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_uart_9000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_PATH "/soc/peripheral@40000000/uart@9000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_ORD 69

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_uarte DT_N_S_soc_S_peripheral_40000000_S_uart_9000
#define DT_N_NODELABEL_uart1         DT_N_S_soc_S_peripheral_40000000_S_uart_9000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_VAL_ADDRESS 1073778688 /* 0x40009000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_label "UART_1"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/uart@a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_uart_a000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PATH "/soc/peripheral@40000000/uart@a000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_ORD 70

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_uarte DT_N_S_soc_S_peripheral_40000000_S_uart_a000
#define DT_N_NODELABEL_uart2         DT_N_S_soc_S_peripheral_40000000_S_uart_a000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_VAL_ADDRESS 1073782784 /* 0x4000a000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_irq 10
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_0 40960
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_0 10
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_tx_pin 11
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_tx_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_rx_pin 10
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_rx_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_rts_pin 12
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_rts_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_cts_pin 7
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_cts_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_current_speed 115200
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_label "UART_2"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_hw_flow_control 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/uart@b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_uart_b000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_PATH "/soc/peripheral@40000000/uart@b000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_ORD 71

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_uarte DT_N_S_soc_S_peripheral_40000000_S_uart_b000
#define DT_N_NODELABEL_uart3         DT_N_S_soc_S_peripheral_40000000_S_uart_b000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_VAL_ADDRESS 1073786880 /* 0x4000b000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_label "UART_3"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/vmc@3a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000
 *
 * Binding (compatible = nordic,nrf-vmc):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-vmc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_PATH "/soc/peripheral@40000000/vmc@3a000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_ORD 72

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_vmc DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000
#define DT_N_NODELABEL_vmc         DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_VAL_ADDRESS 1073979392 /* 0x4003a000 */
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_COMPAT_MATCHES_nordic_nrf_vmc 1
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg {237568 /* 0x3a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_0 237568
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible {"nordic,nrf-vmc"}
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0 "nordic,nrf-vmc"
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/watchdog@18000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000
 *
 * Binding (compatible = nordic,nrf-watchdog):
 *   $ZEPHYR_BASE\dts\bindings\watchdog\nordic,nrf-watchdog.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_PATH "/soc/peripheral@40000000/watchdog@18000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_ORD 73

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_watchdog DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000
#define DT_N_NODELABEL_wdt              DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000
#define DT_N_NODELABEL_wdt0             DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_VAL_ADDRESS 1073840128 /* 0x40018000 */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq 24
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_COMPAT_MATCHES_nordic_nrf_watchdog 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg {98304 /* 0x18000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_0 98304
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_label "WDT"
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts {24 /* 0x18 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_0 24
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible {"nordic,nrf-watchdog"}
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0 "nordic,nrf-watchdog"
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/flash-controller@39000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000
 *
 * Binding (compatible = nordic,nrf91-flash-controller):
 *   $ZEPHYR_BASE\dts\bindings\flash_controller\nordic,nrf91-flash-controller.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_PATH "/soc/peripheral@40000000/flash-controller@39000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_ORD 74

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_SUPPORTS_ORDS \
	75, /* /soc/peripheral@40000000/flash-controller@39000/flash@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_EXISTS 1
#define DT_N_INST_0_nordic_nrf91_flash_controller DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000
#define DT_N_NODELABEL_flash_controller           DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_VAL_ADDRESS 1073975296 /* 0x40039000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_COMPAT_MATCHES_nordic_nrf91_flash_controller 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_label "NRF_FLASH_DRV_NAME"
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_0 233472
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible {"nordic,nrf91-flash-controller"}
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0 "nordic,nrf91-flash-controller"
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/flash-controller@39000/flash@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0
 *
 * Binding (compatible = soc-nv-flash):
 *   $ZEPHYR_BASE\dts\bindings\mtd\soc-nv-flash.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_PATH "/soc/peripheral@40000000/flash-controller@39000/flash@0"

/* Node parent (/soc/peripheral@40000000/flash-controller@39000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_PARENT DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_ORD 75

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REQUIRES_ORDS \
	74, /* /soc/peripheral@40000000/flash-controller@39000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_SUPPORTS_ORDS \
	76, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_EXISTS 1
#define DT_N_INST_0_soc_nv_flash DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0
#define DT_N_NODELABEL_flash0    DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_SIZE 1048576 /* 0x100000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_COMPAT_MATCHES_soc_nv_flash 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_label "NRF_FLASH"
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_erase_block_size 4096
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_erase_block_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_write_block_size 4
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_write_block_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible {"soc-nv-flash"}
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0 "soc-nv-flash"
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg {0 /* 0x0 */, 1048576 /* 0x100000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1 1048576
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_PATH "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions"

/* Node parent (/soc/peripheral@40000000/flash-controller@39000/flash@0) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_PARENT DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD 76

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_REQUIRES_ORDS \
	75, /* /soc/peripheral@40000000/flash-controller@39000/flash@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_SUPPORTS_ORDS \
	77, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@0 */ \
	78, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@10000 */ \
	79, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@50000 */ \
	80, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@80000 */ \
	81, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@c0000 */ \
	82, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@f0000 */ \
	83, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@fa000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_EXISTS 1
#define DT_N_INST_0_fixed_partitions DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_REG_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PATH "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@0"

/* Node parent (/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD 77

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REQUIRES_ORDS \
	76, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_EXISTS 1
#define DT_N_NODELABEL_boot_partition DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label "mcuboot"
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 65536 /* 0x10000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1 65536
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@10000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PATH "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@10000"

/* Node parent (/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARENT DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD 78

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REQUIRES_ORDS \
	76, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_EXISTS 1
#define DT_N_NODELABEL_slot0_partition DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_ADDRESS 49152 /* 0xc000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARTITION_ID 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label "image-0"
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg {49152 /* 0xc000 */, 196608 /* 0x30000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0 49152
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1 196608
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@50000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PATH "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@50000"

/* Node parent (/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARENT DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_ORD 79

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REQUIRES_ORDS \
	76, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_EXISTS 1
#define DT_N_NODELABEL_slot0_ns_partition DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_ADDRESS 253952 /* 0x3e000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARTITION_ID 2

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label "image-0-nonsecure"
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg {253952 /* 0x3e000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0 253952
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@80000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PATH "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@80000"

/* Node parent (/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARENT DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_ORD 80

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REQUIRES_ORDS \
	76, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_EXISTS 1
#define DT_N_NODELABEL_slot1_partition DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_ADDRESS 516096 /* 0x7e000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARTITION_ID 3

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label "image-1"
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg {516096 /* 0x7e000 */, 196608 /* 0x30000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0 516096
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1 196608
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@c0000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PATH "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@c0000"

/* Node parent (/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARENT DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_ORD 81

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REQUIRES_ORDS \
	76, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_EXISTS 1
#define DT_N_NODELABEL_slot1_ns_partition DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_ADDRESS 720896 /* 0xb0000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARTITION_ID 4

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label "image-1-nonsecure"
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg {720896 /* 0xb0000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0 720896
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@f0000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PATH "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@f0000"

/* Node parent (/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARENT DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_ORD 82

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REQUIRES_ORDS \
	76, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_EXISTS 1
#define DT_N_NODELABEL_scratch_partition DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_ADDRESS 983040 /* 0xf0000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_SIZE 40960 /* 0xa000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARTITION_ID 5

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label "image-scratch"
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg {983040 /* 0xf0000 */, 40960 /* 0xa000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0 983040
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1 40960
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@fa000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PATH "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@fa000"

/* Node parent (/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARENT DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_ORD 83

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REQUIRES_ORDS \
	76, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_EXISTS 1
#define DT_N_NODELABEL_storage_partition DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_ADDRESS 1024000 /* 0xfa000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_SIZE 24576 /* 0x6000 */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARTITION_ID 6

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label "storage"
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only 0
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg {1024000 /* 0xfa000 */, 24576 /* 0x6000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0 1024000
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1 24576
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/i2c@9000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_i2c_9000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PATH "/soc/peripheral@40000000/i2c@9000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_ORD 84

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_SUPPORTS_ORDS \
	85, /* /soc/peripheral@40000000/i2c@9000/maxl7261@36 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_twim DT_N_S_soc_S_peripheral_40000000_S_i2c_9000
#define DT_N_NODELABEL_i2c1         DT_N_S_soc_S_peripheral_40000000_S_i2c_9000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_VAL_ADDRESS 1073778688 /* 0x40009000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_sda_pin 22
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_sda_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_scl_pin 21
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_scl_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_clock_frequency 100000
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_label "I2C_1"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/i2c@9000/maxl7261@36
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_PATH "/soc/peripheral@40000000/i2c@9000/maxl7261@36"

/* Node parent (/soc/peripheral@40000000/i2c@9000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_PARENT DT_N_S_soc_S_peripheral_40000000_S_i2c_9000
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_ORD 85

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_REQUIRES_ORDS \
	84, /* /soc/peripheral@40000000/i2c@9000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_EXISTS 1
#define DT_N_INST_0_maxim_max17261 DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36

/* Bus info (controller: '/soc/peripheral@40000000/i2c@9000', type: 'i2c') */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_BUS_i2c 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_BUS DT_N_S_soc_S_peripheral_40000000_S_i2c_9000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_REG_IDX_0_VAL_ADDRESS 54 /* 0x36 */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_COMPAT_MATCHES_maxim_max17261 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_P_compatible {"maxim,max17261"}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_P_compatible_IDX_0 "maxim,max17261"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_P_reg {54 /* 0x36 */}
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_P_reg_IDX_0 54
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_P_label "MAX17261"
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_S_maxl7261_36_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_b000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_PATH "/soc/peripheral@40000000/spi@b000"

/* Node parent (/soc/peripheral@40000000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_PARENT DT_N_S_soc_S_peripheral_40000000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_ORD 86

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REQUIRES_ORDS \
	8, /* /soc/peripheral@40000000 */ \
	9, /* /soc/peripheral@40000000/gpio@842500 */ \
	35, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_SUPPORTS_ORDS \
	87, /* /soc/peripheral@40000000/spi@b000/m95m02@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_spim DT_N_S_soc_S_peripheral_40000000_S_spi_b000
#define DT_N_NODELABEL_spi3         DT_N_S_soc_S_peripheral_40000000_S_spi_b000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_VAL_ADDRESS 1073786880 /* 0x4000b000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_up 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_down 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_down_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_sck_pin 28
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_sck_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_mosi_pin 30
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_mosi_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pin 31
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_label "SPI_3"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_cs_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_pin 29
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_flags 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_cs_gpios_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_cs_gpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status "okay"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@40000000/spi@b000/m95m02@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_PATH "/soc/peripheral@40000000/spi@b000/m95m02@0"

/* Node parent (/soc/peripheral@40000000/spi@b000) identifier: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_PARENT DT_N_S_soc_S_peripheral_40000000_S_spi_b000
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_ORD 87

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_REQUIRES_ORDS \
	86, /* /soc/peripheral@40000000/spi@b000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_EXISTS 1
#define DT_N_INST_0_st_m95m02 DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0

/* Bus info (controller: '/soc/peripheral@40000000/spi@b000', type: 'spi') */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_BUS_spi 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_BUS DT_N_S_soc_S_peripheral_40000000_S_spi_b000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_COMPAT_MATCHES_st_m95m02 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_P_compatible {"st,m95m02"}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_P_compatible_IDX_0 "st,m95m02"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_P_label "M95M02"
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_P_reg {0 /* 0x0 */}
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_S_m95m02_0_P_reg_EXISTS 1

/*
 * Chosen nodes
 */
#define DT_CHOSEN_zephyr_flash_controller        DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000
#define DT_CHOSEN_zephyr_flash_controller_EXISTS 1
#define DT_CHOSEN_zephyr_entropy                 DT_N_S_soc_S_cryptocell_sw
#define DT_CHOSEN_zephyr_entropy_EXISTS          1
#define DT_CHOSEN_zephyr_console                 DT_N_S_soc_S_peripheral_40000000_S_uart_8000
#define DT_CHOSEN_zephyr_console_EXISTS          1
#define DT_CHOSEN_zephyr_shell_uart              DT_N_S_soc_S_peripheral_40000000_S_uart_8000
#define DT_CHOSEN_zephyr_shell_uart_EXISTS       1
#define DT_CHOSEN_zephyr_uart_mcumgr             DT_N_S_soc_S_peripheral_40000000_S_uart_8000
#define DT_CHOSEN_zephyr_uart_mcumgr_EXISTS      1
#define DT_CHOSEN_zephyr_flash                   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0
#define DT_CHOSEN_zephyr_flash_EXISTS            1
#define DT_CHOSEN_zephyr_sram                    DT_N_S_reserved_memory_S_image_ns_20020000
#define DT_CHOSEN_zephyr_sram_EXISTS             1
#define DT_CHOSEN_zephyr_code_partition          DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000
#define DT_CHOSEN_zephyr_code_partition_EXISTS   1
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_0 DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
#define DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000
#define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_1 DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000
#define DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000
#define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_storage DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000
#define DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS 1

/*
 * Macros for compatibles with status "okay" nodes
 */
#define DT_COMPAT_HAS_OKAY_nordic_cl5gm 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf9160_sica 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf9160 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf91 1
#define DT_COMPAT_HAS_OKAY_simple_bus 1
#define DT_COMPAT_HAS_OKAY_arm_v8m_nvic 1
#define DT_COMPAT_HAS_OKAY_mmio_sram 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf91_flash_controller 1
#define DT_COMPAT_HAS_OKAY_soc_nv_flash 1
#define DT_COMPAT_HAS_OKAY_fixed_partitions 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_saadc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_dppic 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_egu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_kmu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_regulators 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_vmc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uarte 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_twim 1
#define DT_COMPAT_HAS_OKAY_maxim_max17261 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_spim 1
#define DT_COMPAT_HAS_OKAY_st_m95m02 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_rtc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_clock 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_power 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_watchdog 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_timer 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_cc310_sw 1
#define DT_COMPAT_HAS_OKAY_arm_cortex_m33f 1
#define DT_COMPAT_HAS_OKAY_arm_armv8m_mpu 1
#define DT_COMPAT_HAS_OKAY_gpio_leds 1
#define DT_COMPAT_HAS_OKAY_gpio_keys 1

/*
 * Macros for status "okay" instances of each compatible
 */
#define DT_N_INST_nordic_cl5gm_NUM_OKAY 1
#define DT_N_INST_nordic_nrf9160_sica_NUM_OKAY 1
#define DT_N_INST_nordic_nrf9160_NUM_OKAY 1
#define DT_N_INST_nordic_nrf91_NUM_OKAY 1
#define DT_N_INST_simple_bus_NUM_OKAY 1
#define DT_N_INST_arm_v8m_nvic_NUM_OKAY 1
#define DT_N_INST_mmio_sram_NUM_OKAY 1
#define DT_N_INST_nordic_nrf91_flash_controller_NUM_OKAY 1
#define DT_N_INST_soc_nv_flash_NUM_OKAY 1
#define DT_N_INST_fixed_partitions_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_saadc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_dppic_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_egu_NUM_OKAY 6
#define DT_N_INST_nordic_nrf_kmu_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_regulators_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_vmc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_uarte_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_twim_NUM_OKAY 1
#define DT_N_INST_maxim_max17261_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_spim_NUM_OKAY 1
#define DT_N_INST_st_m95m02_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpio_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_rtc_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_clock_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_power_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_watchdog_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_timer_NUM_OKAY 3
#define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_cc310_sw_NUM_OKAY 1
#define DT_N_INST_arm_cortex_m33f_NUM_OKAY 1
#define DT_N_INST_arm_armv8m_mpu_NUM_OKAY 1
#define DT_N_INST_gpio_leds_NUM_OKAY 1
#define DT_N_INST_gpio_keys_NUM_OKAY 1
#define DT_FOREACH_OKAY_INST_nordic_cl5gm(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf9160_sica(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf9160(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf91(fn) fn(0)
#define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0)
#define DT_FOREACH_OKAY_INST_arm_v8m_nvic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf91_flash_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_fixed_partitions(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_saadc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_dppic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_egu(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5)
#define DT_FOREACH_OKAY_INST_nordic_nrf_kmu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_regulators(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_vmc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_uarte(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_nordic_nrf_twim(fn) fn(0)
#define DT_FOREACH_OKAY_INST_maxim_max17261(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_spim(fn) fn(0)
#define DT_FOREACH_OKAY_INST_st_m95m02(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpio(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_rtc(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_nordic_nrf_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_power(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_watchdog(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_timer(fn) fn(0) fn(1) fn(2)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_cc310_sw(fn) fn(0)
#define DT_FOREACH_OKAY_INST_arm_cortex_m33f(fn) fn(0)
#define DT_FOREACH_OKAY_INST_arm_armv8m_mpu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_gpio_keys(fn) fn(0)

/*
 * Bus information for status "okay" nodes of each compatible
 */
#define DT_COMPAT_maxim_max17261_BUS_i2c 1
#define DT_COMPAT_st_m95m02_BUS_spi 1
