/*
 * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
 * Copyright (c) 2022-2024 Cypress Semiconductor Corporation (an Infineon company)
 * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/***********  WARNING: This is an auto-generated file. Do not edit!  ***********/

/*
 * Customized region name prefix abbreviation:
 *  LR : A Load region.
 *  ER : A typical execution region.
 *  PT : An empty execution region used as position-tag/address-alignment.
 *
 * No applying customized prefixes on linker/system reserved/intentional
 * names, such as 'ARM_LIB_STACK'.
 */

#include "region_defs.h"

/* Include file with definitions for section alignments.
 * Note: it should be included after region_defs.h to let platform define
 * default values if needed. */
#include "tfm_s_linker_alignments.h"

#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) || \
    defined(__ARM_ARCH_8_1M_MAIN__)
#define STACKSEAL_SIZE  0x8
#else
#define STACKSEAL_SIZE  0x0
#endif

LR_CODE S_CODE_START S_CODE_SIZE {
    /* Position tag: Start of code + RO-data */
    PT_RO_START +0 ALIGN TFM_LINKER_PT_RO_ALIGNMENT EMPTY 0x0 {
    }

#ifdef S_CODE_VECTOR_TABLE_SIZE
    ER_VECTORS S_CODE_START S_CODE_VECTOR_TABLE_SIZE {
#else
    ER_VECTORS S_CODE_START {
#endif
        *.o (RESET +First)
    }

#ifdef S_CODE_VECTOR_TABLE_SIZE
    ER_VECTORS_FILL +0 FILL 0x0 (S_CODE_VECTOR_TABLE_SIZE - ImageLength(ER_VECTORS)) {
    }
#endif

    /* Position tag: Start of unprivileged code (shared, not PXN) */
    PT_UNPRIV_CODE_START +0 ALIGN TFM_LINKER_PT_UNPRIV_CODE_ALIGNMENT EMPTY 0x0 {
    }

#ifdef CONFIG_TFM_USE_TRUSTZONE
    /*
     * Place the CMSE Veneers (containing the SG instruction) in a separate
     * 32 bytes aligned region so that the SAU can be programmed to
     * just set this region as Non-Secure Callable.
     */
    ER_VENEER +0 ALIGN TFM_LINKER_VENEERS_ALIGNMENT {
        *(Veneer$$CMSE)
    }
    /*
     * The Limit of the VENEER_ALIGN region should be at least 32 bytes aligned
     * so that the SAU can set this region as Non-Secure Callable.
     */
    VENEER_ALIGN +0 ALIGN TFM_LINKER_VENEERS_ALIGNMENT EMPTY 0x0 {
    }
#endif

    /* Shared library code */
    ER_UNPRIV_CODE +0 {
        *armlib*(+RO-CODE)
        *libtfm_sprt*(+RO-CODE)
        *libqcbor*(+RO-CODE)
        *libtfm_t_cose_s*(+RO-CODE)
    }

    /* Position tag: End of unprivileged code (shared, not PXN) */
    PT_UNPRIV_CODE_END +0 ALIGN TFM_LINKER_PT_UNPRIV_CODE_ALIGNMENT EMPTY 0x0 {
    }

    /* Position tag: Start of Application RoT code (unprivileged, PXN) */
    PT_APP_ROT_CODE_START +0 ALIGN TFM_LINKER_PT_APP_ROT_CODE_ALIGNMENT EMPTY 0x0 {
    }

    ER_APP_ROT_CODE +0 {
        *tfm_app_rot_partition*(+RO-CODE)
        *(TFM_*_APP-ROT_ATTR_FN)
        *tfm_*partition_ps.*(+RO-CODE)
        *(TFM_SP_PS_APP-ROT_ATTR_FN)
    }

    /* Position tag: End of Application RoT code (unprivileged, PXN) */
    PT_APP_ROT_CODE_END +0 ALIGN TFM_LINKER_PT_APP_ROT_CODE_ALIGNMENT EMPTY 0x0 {
    }

    /* Position tag: Start of PSA RoT code (privileged) */
    PT_PSA_ROT_CODE_START +0 ALIGN TFM_LINKER_PT_PSA_ROT_CODE_ALIGNMENT EMPTY 0x0 {
    }

    ER_PSA_ROT_CODE +0 {
        *tfm_psa_rot_partition*(+RO-CODE)
        *(TFM_*_PSA-ROT_ATTR_FN)
        *tfm_*partition_its.*(+RO-CODE)
        *(TFM_SP_ITS_PSA-ROT_ATTR_FN)
        *tfm_*partition_crypto.*(+RO-CODE)
        *tfpsacrypto.*(+RO-CODE)
        *tfpsacrypto*acceleration.*(+RO-CODE)
        *(TFM_SP_CRYPTO_PSA-ROT_ATTR_FN)
        *tfm_*partition_platform.*(+RO-CODE)
        *(TFM_SP_PLATFORM_PSA-ROT_ATTR_FN)
    }

    /* Capture all remaining code (except RAM code) in the privileged TF-M
     * code region.
     */
    ER_TFM_CODE +0 {
        *(+RO-CODE)
    }

    /* Position tag: End of PSA RoT code (privileged) */
    PT_PSA_ROT_CODE_END +0 ALIGN TFM_LINKER_PT_PSA_ROT_CODE_ALIGNMENT EMPTY 0x0 {
    }

    /* Position tag: Start of RO-data (unprivileged, execute-never) */
    PT_RO_DATA_START +0 ALIGN TFM_LINKER_PT_RO_DATA_ALIGNMENT EMPTY 0x0 {
    }

    /* Collect all RO-data into a single unprivileged region */
    ER_RO_DATA +0 {
        *(+RO-DATA)
    }

    /**** Section for holding partition RO load data */
    /*
     * Sort the partition info by priority to guarantee the initing order.
     * The first loaded partition will be inited at last in SFN model.
     */
    TFM_SP_LOAD_LIST +0 ALIGN TFM_LINKER_PT_RO_DATA_ALIGNMENT {
        *(.part_load)
    }

    /* Position tag: End of RO-data (unprivileged, execute-never) */
    PT_RO_DATA_END +0 ALIGN TFM_LINKER_PT_RO_DATA_ALIGNMENT EMPTY 0x0 {
    }

    /* Position tag: End of code + RO-data */
    PT_RO_END +0 ALIGN TFM_LINKER_PT_RO_ALIGNMENT EMPTY 0x0 {
    }

#ifdef S_RUNTIME_ITCM_START
    /* Position tag: Start of SPM code (privileged) */
    PT_SPM_CODE_START S_RUNTIME_ITCM_START ALIGN TFM_LINKER_SPM_CODE_ALIGNMENT EMPTY 0x0 { }

    ER_SPM_CODE +0 {
        *tfm_spm*(+RO)
    }

    /* Position tag: End of SPM code (privileged) */
    PT_SPM_CODE_END +0 ALIGN TFM_LINKER_SPM_CODE_ALIGNMENT EMPTY 0x0 {
    }

    /* This empty, zero long execution region is here to mark the limit address
     * of the last execution region that is allocated in ITCM.
     */
    ITCM_WATERMARK +0 EMPTY 0x0 {
    }

    /* Make sure that the sections allocated in the ITCM does not exceed the
     * size of the ITCM available.
     */
    ScatterAssert(ImageLimit(ITCM_WATERMARK) <= S_RUNTIME_ITCM_START + S_RUNTIME_ITCM_SIZE)
#endif

#ifdef S_RAM_CODE_START
    /* Flash drivers code that gets copied from Flash */
    ER_CODE_SRAM S_RAM_CODE_START ALIGN 32 {
        *libflash_drivers*(+RO)
        *(.ramfunc)
    }

    /* This empty, zero long execution region is here to mark the limit
     * address of the last execution region that is allocated in CODE_SRAM.
     */
    ER_CODE_SRAM_WATERMARK +0 EMPTY 0x0 {
    }

    /* Make sure that the sections allocated in the CODE_SRAM does not exceed
     * the size of the SRAM available.
     */
    ScatterAssert(ImageLimit(ER_CODE_SRAM_WATERMARK) <=
                  S_RAM_CODE_START + S_RAM_CODE_SIZE)
#endif

    /**** Base address of secure data area */
    TFM_SECURE_DATA_START S_DATA_START {
    }

    /*
     * MPU on Armv6-M/v7-M core in multi-core topology may require more strict
     * alignment that MPU region base address must align with the MPU region
     * size.
     * As a result, on Armv6-M/v7-M cores, to save memory resource and MPU
     * regions, unprivileged data sections and privileged data sections can be
     * separated and gathered in unprivileged/privileged data area respectively
     * by defining S_DATA_PRIV_START. If so, the BL2 shared data area is moved
     * to the beginning of the privileged data area, otherwise it is kept at the
     * beginning of the secure data area.
     */
#ifndef S_DATA_PRIV_START
#ifdef CODE_SHARING
    /* The code sharing between bootloader and runtime requires to share the
     * global variables.
     */
    TFM_SHARED_SYMBOLS +0 ALIGN TFM_LINKER_SHARED_SYMBOLS_ALIGNMENT EMPTY SHARED_SYMBOL_AREA_SIZE {
    }
#endif

#ifdef BOOT_TFM_SHARED_DATA_SIZE
    /* Shared area between BL2 and runtime to exchange data */
    TFM_SHARED_DATA +0 ALIGN TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT EMPTY BOOT_TFM_SHARED_DATA_SIZE {
    }
#endif
#endif /* !S_DATA_PRIV_START */

    /* Position tag: Start of Application RoT data (unprivileged) */
    PT_APP_ROT_DATA_START +0 ALIGN TFM_LINKER_PT_APP_ROT_DATA_ALIGNMENT EMPTY 0x0 {
    }

#ifdef CONFIG_TFM_PARTITION_META
    TFM_SP_META_PTR +0 ALIGN TFM_LINKER_SP_META_PTR_ALIGNMENT {
        *(.bss.SP_META_PTR_SPRTL_INST)
    }
    /*
     * This empty, zero long execution region is here to mark the end address
     * of TFM partition metadata pointer region.
     */
    TFM_SP_META_PTR_END +0 ALIGN TFM_LINKER_SP_META_PTR_ALIGNMENT EMPTY 0x0 {
    }
#endif


    /* Position tag: Start of Application RoT partition's private data */
    PT_TFM_SP_PS_PRIVATE_DATA_START +0 ALIGN TFM_LINKER_PT_AROT_PART_PRIVATE_DATA_ALIGNMENT EMPTY 0x0 {
    }

    ER_TFM_SP_PS_RWZI +0 {
        *tfm_*partition_ps.*(+RW +ZI)
        *(TFM_SP_PS_APP-ROT_ATTR_RW)
        *(TFM_SP_PS_APP-ROT_ATTR_ZI)
    }

    /* Position tag: End of Application RoT partition's private data */
    PT_TFM_SP_PS_PRIVATE_DATA_END +0 ALIGN TFM_LINKER_PT_AROT_PART_PRIVATE_DATA_ALIGNMENT EMPTY 0x0 {
    }


    /* Position tag: End of Application RoT data (unprivileged) */
    PT_APP_ROT_DATA_END +0 ALIGN TFM_LINKER_PT_APP_ROT_DATA_ALIGNMENT EMPTY 0x0 {
    }

#ifdef S_DATA_PRIV_START
    /**** Privileged data area base address specified by Armv6-M/v7-M platform */
    TFM_SECURE_PRIV_DATA_BOUNDARY S_DATA_PRIV_START {
    }

    /*
     * Move BL2 shared area to the beginning of privileged data area on
     * Armv6-M/v7-M platforms.
     */
#ifdef BOOT_TFM_SHARED_DATA_SIZE
    /* Shared area between BL2 and runtime to exchange data */
    TFM_SHARED_DATA +0 ALIGN TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT EMPTY BOOT_TFM_SHARED_DATA_SIZE {
    }
#endif
#endif /* S_DATA_PRIV_START */

    /* Position tag: Start of PSA RoT data (privileged) */
    PT_PSA_ROT_DATA_START +0 ALIGN TFM_LINKER_PT_PSA_ROT_DATA_ALIGNMENT EMPTY 0x0 {
    }

    /* MSP */
    ARM_LIB_STACK +0 ALIGN TFM_LINKER_MSP_STACK_ALIGNMENT EMPTY S_MSP_STACK_SIZE - STACKSEAL_SIZE {
    }

#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) || \
    defined(__ARM_ARCH_8_1M_MAIN__)
    STACKSEAL +0 EMPTY STACKSEAL_SIZE {
    }
#endif


    /* Position tag: Start of PSA RoT partition's private data */
    PT_TFM_SP_ITS_PRIVATE_DATA_START +0 ALIGN TFM_LINKER_PT_PROT_PART_PRIVATE_DATA_ALIGNMENT EMPTY 0x0 {
    }

    ER_TFM_SP_ITS_RWZI +0 {
        *tfm_*partition_its.*(+RW +ZI)
        *(TFM_SP_ITS_PSA-ROT_ATTR_RW)
        *(TFM_SP_ITS_PSA-ROT_ATTR_ZI)
    }

    /* Position tag: End of PSA RoT partition's private data */
    PT_TFM_SP_ITS_PRIVATE_DATA_END +0 ALIGN TFM_LINKER_PT_PROT_PART_PRIVATE_DATA_ALIGNMENT EMPTY 0x0 {
    }


    /* Position tag: Start of PSA RoT partition's private data */
    PT_TFM_SP_CRYPTO_PRIVATE_DATA_START +0 ALIGN TFM_LINKER_PT_PROT_PART_PRIVATE_DATA_ALIGNMENT EMPTY 0x0 {
    }

    ER_TFM_SP_CRYPTO_RWZI +0 {
        *tfm_*partition_crypto.*(+RW +ZI)
        *tfpsacrypto.*(+RW +ZI)
        *tfpsacrypto*acceleration.*(+RW +ZI)
        *(TFM_SP_CRYPTO_PSA-ROT_ATTR_RW)
        *(TFM_SP_CRYPTO_PSA-ROT_ATTR_ZI)
    }

    /* Position tag: End of PSA RoT partition's private data */
    PT_TFM_SP_CRYPTO_PRIVATE_DATA_END +0 ALIGN TFM_LINKER_PT_PROT_PART_PRIVATE_DATA_ALIGNMENT EMPTY 0x0 {
    }


    /* Position tag: Start of PSA RoT partition's private data */
    PT_TFM_SP_PLATFORM_PRIVATE_DATA_START +0 ALIGN TFM_LINKER_PT_PROT_PART_PRIVATE_DATA_ALIGNMENT EMPTY 0x0 {
    }

    ER_TFM_SP_PLATFORM_RWZI +0 {
        *tfm_*partition_platform.*(+RW +ZI)
        *(TFM_SP_PLATFORM_PSA-ROT_ATTR_RW)
        *(TFM_SP_PLATFORM_PSA-ROT_ATTR_ZI)
    }

    /* Position tag: End of PSA RoT partition's private data */
    PT_TFM_SP_PLATFORM_PRIVATE_DATA_END +0 ALIGN TFM_LINKER_PT_PROT_PART_PRIVATE_DATA_ALIGNMENT EMPTY 0x0 {
    }


    ER_TFM_DATA +0 {
        *(+RW +ZI)
    }

    /* The runtime partition placed order is same as load partition */
    ER_PART_RT_POOL +0 ALIGN TFM_LINKER_TFM_BSS_ALIGNMENT {
        *(.bss.part_runtime)
    }

    /* The runtime service placed order is same as load partition */
    ER_SERV_RT_POOL +0 ALIGN TFM_LINKER_TFM_BSS_ALIGNMENT {
        *(.bss.serv_runtime)
    }

    /* Position tag: End of PSA RoT data (privileged) */
    PT_PSA_ROT_DATA_END +0 ALIGN TFM_LINKER_PT_PSA_ROT_DATA_ALIGNMENT EMPTY 0x0 {
    }

#ifdef RAM_VECTORS_SUPPORT
    ER_RAM_VECTORS +0 ALIGN TFM_LINKER_RAM_VECTORS_ALIGNMENT UNINIT {
        *(RESET_RAM)
    }
#endif

    /* This empty, zero long execution region is here to mark the limit address
     * of the last execution region that is allocated in SRAM.
     */
    SRAM_WATERMARK +0 EMPTY 0x0 {
    }

    /* Make sure that the sections allocated in the SRAM does not exceed the
     * size of the SRAM available.
     */
    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)




}

LR_NS_PARTITION NS_PARTITION_START {
    /* Reserved place for NS application.
     * No code will be placed here, just address of this region is used in the
     * secure code to configure certain HW components. This generates an empty
     * execution region description warning during linking.
     */
    ER_NS_PARTITION NS_PARTITION_START UNINIT NS_PARTITION_SIZE {
    }
}

#ifdef BL2
LR_SECONDARY_PARTITION SECONDARY_PARTITION_START {
    /* Reserved place for new image in case of firmware upgrade.
     * No code will be placed here, just address of this region is used in the
     * secure code to configure certain HW components. This generates an empty
     * execution region description warning during linking.
     */
    ER_SECONDARY_PARTITION SECONDARY_PARTITION_START \
        UNINIT SECONDARY_PARTITION_SIZE {
    }
}
#endif /* BL2 */
