/*
 * Generated by gen_defines.py
 *
 * DTS input file:
 *   C:/Work/nrf-samples/hello_world/app/build/mcuboot/zephyr/zephyr.dts.pre
 *
 * Directories with bindings:
 *   C:/ncs/v2.9.2/nrf/dts/bindings, $ZEPHYR_BASE\dts\bindings
 *
 * Node dependency ordering (ordinal and path):
 *   0   /
 *   1   /aliases
 *   2   /chosen
 *   3   /entropy_bt_hci
 *   4   /soc
 *   5   /soc/interrupt-controller@e000e100
 *   6   /soc/peripheral@50000000
 *   7   /soc/peripheral@50000000/timer@10000
 *   8   /sw-pwm
 *   9   /cpus
 *   10  /cpus/cpu@0
 *   11  /cpus/cpu@0/itm@e0000000
 *   12  /cpus/cpu@0/mpu@e000ed90
 *   13  /ipc
 *   14  /reserved-memory
 *   15  /reserved-memory/memory@20078000
 *   16  /soc/peripheral@50000000/mbox@2a000
 *   17  /ipc/ipc0
 *   18  /ipc/ipc0/bt_hci_ipc0
 *   19  /pin-controller
 *   20  /pin-controller/i2c0_default
 *   21  /pin-controller/i2c0_default/group1
 *   22  /pin-controller/i2c0_sleep
 *   23  /pin-controller/i2c0_sleep/group1
 *   24  /pin-controller/i2c2_default
 *   25  /pin-controller/i2c2_default/group1
 *   26  /pin-controller/i2c2_sleep
 *   27  /pin-controller/i2c2_sleep/group1
 *   28  /pin-controller/spi1_default_9160
 *   29  /pin-controller/spi1_default_9160/group1
 *   30  /pin-controller/spi1_default_dw1000
 *   31  /pin-controller/spi1_default_dw1000/group1
 *   32  /pin-controller/spi3_default
 *   33  /pin-controller/spi3_default/group1
 *   34  /pin-controller/spi3_sleep
 *   35  /pin-controller/spi3_sleep/group1
 *   36  /pin-controller/spi4_default
 *   37  /pin-controller/spi4_default/group1
 *   38  /pin-controller/spi4_sleep
 *   39  /pin-controller/spi4_sleep/group1
 *   40  /reserved-memory/image@20000000
 *   41  /reserved-memory/image_ns@20040000
 *   42  /reserved-memory/image_s@20000000
 *   43  /soc/crypto@50844000
 *   44  /soc/ficr@ff0000
 *   45  /soc/gpiote@4002f000
 *   46  /soc/memory@20000000
 *   47  /soc/spu@50003000
 *   48  /soc/timer@e000e010
 *   49  /soc/uicr@ff8000
 *   50  /soc/nordic_ram-flash-controller@0
 *   51  /soc/nordic_ram-flash-controller@0/flash_sim@0
 *   52  /soc/nordic_ram-flash-controller@0/flash_sim@0/partitions
 *   53  /soc/nordic_ram-flash-controller@0/flash_sim@0/partitions/partition@0
 *   54  /soc/peripheral@50000000/adc@e000
 *   55  /soc/peripheral@50000000/clock@5000
 *   56  /soc/peripheral@50000000/comparator@1a000
 *   57  /soc/peripheral@50000000/ctrlap@6000
 *   58  /soc/peripheral@50000000/dcnf@0
 *   59  /soc/peripheral@50000000/dppic@17000
 *   60  /soc/peripheral@50000000/egu@1b000
 *   61  /soc/peripheral@50000000/egu@1c000
 *   62  /soc/peripheral@50000000/egu@1d000
 *   63  /soc/peripheral@50000000/egu@1e000
 *   64  /soc/peripheral@50000000/egu@1f000
 *   65  /soc/peripheral@50000000/egu@20000
 *   66  /soc/gpiote@5000d000
 *   67  /soc/peripheral@50000000/gpio@842800
 *   68  /soc/peripheral@50000000/i2c@8000
 *   69  /soc/peripheral@50000000/i2c@9000
 *   70  /soc/peripheral@50000000/i2c@b000
 *   71  /soc/peripheral@50000000/i2c@c000
 *   72  /soc/peripheral@50000000/i2s@28000
 *   73  /soc/peripheral@50000000/ieee802154
 *   74  /soc/peripheral@50000000/kmu@39000
 *   75  /soc/peripheral@50000000/mutex@30000
 *   76  /soc/peripheral@50000000/nfct@2d000
 *   77  /soc/peripheral@50000000/oscillator@4000
 *   78  /soc/peripheral@50000000/pdm@26000
 *   79  /soc/peripheral@50000000/pwm@21000
 *   80  /soc/peripheral@50000000/pwm@22000
 *   81  /soc/peripheral@50000000/pwm@23000
 *   82  /soc/peripheral@50000000/pwm@24000
 *   83  /soc/peripheral@50000000/qdec@33000
 *   84  /soc/peripheral@50000000/qdec@34000
 *   85  /soc/peripheral@50000000/qspi@2b000
 *   86  /soc/peripheral@50000000/regulator@37000
 *   87  /soc/peripheral@50000000/reset-controller@5000
 *   88  /soc/peripheral@50000000/rtc@14000
 *   89  /soc/peripheral@50000000/rtc@15000
 *   90  /soc/peripheral@50000000/spi@8000
 *   91  /soc/peripheral@50000000/spi@9000
 *   92  /soc/peripheral@50000000/spi@b000
 *   93  /soc/peripheral@50000000/spi@c000
 *   94  /soc/peripheral@50000000/timer@f000
 *   95  /soc/peripheral@50000000/timer@11000
 *   96  /soc/peripheral@50000000/uart@8000
 *   97  /soc/peripheral@50000000/uart@9000
 *   98  /soc/peripheral@50000000/uart@b000
 *   99  /soc/peripheral@50000000/uart@c000
 *   100 /soc/peripheral@50000000/usbd@36000
 *   101 /soc/peripheral@50000000/vmc@81000
 *   102 /soc/peripheral@50000000/watchdog@18000
 *   103 /soc/peripheral@50000000/watchdog@19000
 *   104 /soc/peripheral@50000000/flash-controller@39000
 *   105 /soc/peripheral@50000000/flash-controller@39000/flash@0
 *   106 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *   107 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0
 *   108 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000
 *   109 /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@ed0000
 *   110 /soc/peripheral@50000000/power@5000
 *   111 /soc/peripheral@50000000/power@5000/gpregret1@51c
 *   112 /soc/peripheral@50000000/power@5000/gpregret2@520
 *   113 /soc/peripheral@50000000/regulator@4000
 *   114 /soc/peripheral@50000000/regulator@4000/regulator@4704
 *   115 /soc/peripheral@50000000/regulator@4000/regulator@4904
 *   116 /soc/peripheral@50000000/regulator@4000/regulator@4b00
 *   117 /soc/peripheral@50000000/gpio@842500
 *   118 /soc/peripheral@50000000/spi@a000
 *   119 /soc/peripheral@50000000/spi@a000/at25sl128a-node@0
 *
 * Definitions derived from these nodes in dependency order are next,
 * followed by /chosen nodes.
 */

/* Used to remove brackets from around a single argument */
#define DT_DEBRACKET_INTERNAL(...) __VA_ARGS__

/*
 * Devicetree node: /
 *
 * Node identifier: DT_N
 */

/* Node's full path: */
#define DT_N_PATH "/"

/* Node's name with unit-address: */
#define DT_N_FULL_NAME "/"

/* Helpers for dealing with node labels: */
#define DT_N_NODELABEL_NUM 0
#define DT_N_FOREACH_NODELABEL(fn) 
#define DT_N_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_CHILD_NUM 9
#define DT_N_CHILD_NUM_STATUS_OKAY 8
#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_sw_pwm) fn(DT_N_S_cpus) fn(DT_N_S_ipc) fn(DT_N_S_reserved_memory)
#define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sw_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory)
#define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_sw_pwm, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_ipc, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sw_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_ipc) fn(DT_N_S_reserved_memory)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_ipc, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_ipc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_ORD 0
#define DT_N_ORD_STR_SORTABLE 00000

/* Ordinals for what this node depends on directly: */
#define DT_N_REQUIRES_ORDS /* nothing */

/* Ordinals for what depends directly on this node: */
#define DT_N_SUPPORTS_ORDS \
	1, /* /aliases */ \
	2, /* /chosen */ \
	3, /* /entropy_bt_hci */ \
	4, /* /soc */ \
	8, /* /sw-pwm */ \
	9, /* /cpus */ \
	13, /* /ipc */ \
	14, /* /reserved-memory */ \
	19, /* /pin-controller */

/* Existence and alternate IDs: */
#define DT_N_EXISTS 1
#define DT_N_INST_0_corp_my_nrf5340_nrf5340_cpuapp DT_N

/* Macros for properties that are special in the specification: */
#define DT_N_REG_NUM 0
#define DT_N_RANGES_NUM 0
#define DT_N_FOREACH_RANGE(fn) 
#define DT_N_IRQ_NUM 0
#define DT_N_IRQ_LEVEL 0
#define DT_N_COMPAT_MATCHES_corp_my_nrf5340_nrf5340_cpuapp 1
#define DT_N_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_P_compatible {"corp,my-nrf5340-nrf5340-cpuapp"}
#define DT_N_P_compatible_IDX_0 "corp,my-nrf5340-nrf5340-cpuapp"
#define DT_N_P_compatible_IDX_0_STRING_UNQUOTED corp,my-nrf5340-nrf5340-cpuapp
#define DT_N_P_compatible_IDX_0_STRING_TOKEN corp_my_nrf5340_nrf5340_cpuapp
#define DT_N_P_compatible_IDX_0_STRING_UPPER_TOKEN CORP_MY_NRF5340_NRF5340_CPUAPP
#define DT_N_P_compatible_IDX_0_EXISTS 1
#define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_LEN 1
#define DT_N_P_compatible_EXISTS 1

/*
 * Devicetree node: /aliases
 *
 * Node identifier: DT_N_S_aliases
 */

/* Node's full path: */
#define DT_N_S_aliases_PATH "/aliases"

/* Node's name with unit-address: */
#define DT_N_S_aliases_FULL_NAME "aliases"

/* Node parent (/) identifier: */
#define DT_N_S_aliases_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_aliases_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_aliases_NODELABEL_NUM 0
#define DT_N_S_aliases_FOREACH_NODELABEL(fn) 
#define DT_N_S_aliases_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_aliases_CHILD_NUM 0
#define DT_N_S_aliases_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_aliases_FOREACH_CHILD(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_aliases_ORD 1
#define DT_N_S_aliases_ORD_STR_SORTABLE 00001

/* Ordinals for what this node depends on directly: */
#define DT_N_S_aliases_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_aliases_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_aliases_REG_NUM 0
#define DT_N_S_aliases_RANGES_NUM 0
#define DT_N_S_aliases_FOREACH_RANGE(fn) 
#define DT_N_S_aliases_IRQ_NUM 0
#define DT_N_S_aliases_IRQ_LEVEL 0
#define DT_N_S_aliases_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_aliases_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /chosen
 *
 * Node identifier: DT_N_S_chosen
 */

/* Node's full path: */
#define DT_N_S_chosen_PATH "/chosen"

/* Node's name with unit-address: */
#define DT_N_S_chosen_FULL_NAME "chosen"

/* Node parent (/) identifier: */
#define DT_N_S_chosen_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_chosen_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_chosen_NODELABEL_NUM 0
#define DT_N_S_chosen_FOREACH_NODELABEL(fn) 
#define DT_N_S_chosen_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_chosen_CHILD_NUM 0
#define DT_N_S_chosen_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_chosen_FOREACH_CHILD(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_chosen_ORD 2
#define DT_N_S_chosen_ORD_STR_SORTABLE 00002

/* Ordinals for what this node depends on directly: */
#define DT_N_S_chosen_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_chosen_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_chosen_REG_NUM 0
#define DT_N_S_chosen_RANGES_NUM 0
#define DT_N_S_chosen_FOREACH_RANGE(fn) 
#define DT_N_S_chosen_IRQ_NUM 0
#define DT_N_S_chosen_IRQ_LEVEL 0
#define DT_N_S_chosen_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_chosen_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /entropy_bt_hci
 *
 * Node identifier: DT_N_S_entropy_bt_hci
 *
 * Binding (compatible = zephyr,bt-hci-entropy):
 *   $ZEPHYR_BASE\dts\bindings\bluetooth\zephyr,bt-hci-entropy.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_entropy_bt_hci_PATH "/entropy_bt_hci"

/* Node's name with unit-address: */
#define DT_N_S_entropy_bt_hci_FULL_NAME "entropy_bt_hci"

/* Node parent (/) identifier: */
#define DT_N_S_entropy_bt_hci_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_entropy_bt_hci_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_entropy_bt_hci_NODELABEL_NUM 1
#define DT_N_S_entropy_bt_hci_FOREACH_NODELABEL(fn) fn(rng_hci)
#define DT_N_S_entropy_bt_hci_FOREACH_NODELABEL_VARGS(fn, ...) fn(rng_hci, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_entropy_bt_hci_CHILD_NUM 0
#define DT_N_S_entropy_bt_hci_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD(fn) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_entropy_bt_hci_ORD 3
#define DT_N_S_entropy_bt_hci_ORD_STR_SORTABLE 00003

/* Ordinals for what this node depends on directly: */
#define DT_N_S_entropy_bt_hci_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_entropy_bt_hci_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_entropy_bt_hci_EXISTS 1
#define DT_N_INST_0_zephyr_bt_hci_entropy DT_N_S_entropy_bt_hci
#define DT_N_NODELABEL_rng_hci            DT_N_S_entropy_bt_hci

/* Macros for properties that are special in the specification: */
#define DT_N_S_entropy_bt_hci_REG_NUM 0
#define DT_N_S_entropy_bt_hci_RANGES_NUM 0
#define DT_N_S_entropy_bt_hci_FOREACH_RANGE(fn) 
#define DT_N_S_entropy_bt_hci_IRQ_NUM 0
#define DT_N_S_entropy_bt_hci_IRQ_LEVEL 0
#define DT_N_S_entropy_bt_hci_COMPAT_MATCHES_zephyr_bt_hci_entropy 1
#define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding"
#define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0 "bt-hci-entropy"
#define DT_N_S_entropy_bt_hci_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_entropy_bt_hci_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_entropy_bt_hci_P_wakeup_source 0
#define DT_N_S_entropy_bt_hci_P_wakeup_source_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_status "okay"
#define DT_N_S_entropy_bt_hci_P_status_STRING_UNQUOTED okay
#define DT_N_S_entropy_bt_hci_P_status_STRING_TOKEN okay
#define DT_N_S_entropy_bt_hci_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_entropy_bt_hci_P_status_IDX_0 "okay"
#define DT_N_S_entropy_bt_hci_P_status_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_status_ENUM_IDX 1
#define DT_N_S_entropy_bt_hci_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_status_ENUM_TOKEN okay
#define DT_N_S_entropy_bt_hci_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, status, 0)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, status, 0)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_status_LEN 1
#define DT_N_S_entropy_bt_hci_P_status_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_compatible {"zephyr,bt-hci-entropy"}
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0 "zephyr,bt-hci-entropy"
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UNQUOTED zephyr,bt-hci-entropy
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_entropy
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_ENTROPY
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, compatible, 0)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, compatible, 0)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_compatible_LEN 1
#define DT_N_S_entropy_bt_hci_P_compatible_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_zephyr_deferred_init 0
#define DT_N_S_entropy_bt_hci_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc
 *
 * Node identifier: DT_N_S_soc
 */

/* Node's full path: */
#define DT_N_S_soc_PATH "/soc"

/* Node's name with unit-address: */
#define DT_N_S_soc_FULL_NAME "soc"

/* Node parent (/) identifier: */
#define DT_N_S_soc_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_NODELABEL_NUM 0
#define DT_N_S_soc_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_CHILD_NUM 11
#define DT_N_S_soc_CHILD_NUM_STATUS_OKAY 9
#define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_gpiote_4002f000) fn(DT_N_S_soc_S_crypto_50844000) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0)
#define DT_N_S_soc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_4002f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_nordic_ram_flash_controller_0)
#define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_4002f000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_4002f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_nordic_ram_flash_controller_0, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_crypto_50844000) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_nordic_ram_flash_controller_0)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_nordic_ram_flash_controller_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_ORD 4
#define DT_N_S_soc_ORD_STR_SORTABLE 00004

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_SUPPORTS_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */ \
	43, /* /soc/crypto@50844000 */ \
	44, /* /soc/ficr@ff0000 */ \
	45, /* /soc/gpiote@4002f000 */ \
	46, /* /soc/memory@20000000 */ \
	47, /* /soc/spu@50003000 */ \
	48, /* /soc/timer@e000e010 */ \
	49, /* /soc/uicr@ff8000 */ \
	50, /* /soc/nordic_ram-flash-controller@0 */ \
	66, /* /soc/gpiote@5000d000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_EXISTS 1
#define DT_N_INST_0_nordic_nrf5340_cpuapp_qkaa DT_N_S_soc
#define DT_N_INST_0_nordic_nrf5340_cpuapp      DT_N_S_soc
#define DT_N_INST_0_nordic_nrf53               DT_N_S_soc
#define DT_N_INST_0_simple_bus                 DT_N_S_soc

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_REG_NUM 0
#define DT_N_S_soc_RANGES_NUM 0
#define DT_N_S_soc_FOREACH_RANGE(fn) 
#define DT_N_S_soc_IRQ_NUM 0
#define DT_N_S_soc_IRQ_LEVEL 0
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf5340_cpuapp_qkaa 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_0 "nrf5340-cpuapp-qkaa"
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf5340_cpuapp 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
#define DT_N_S_soc_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_1 "nrf5340-cpuapp"
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf53 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_2_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_2 "Nordic Semiconductor"
#define DT_N_S_soc_COMPAT_MODEL_IDX_2_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_2 "nrf53"
#define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_P_compatible {"nordic,nrf5340-cpuapp-qkaa", "nordic,nrf5340-cpuapp", "nordic,nrf53", "simple-bus"}
#define DT_N_S_soc_P_compatible_IDX_0 "nordic,nrf5340-cpuapp-qkaa"
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf5340-cpuapp-qkaa
#define DT_N_S_soc_P_compatible_IDX_0_STRING_TOKEN nordic_nrf5340_cpuapp_qkaa
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF5340_CPUAPP_QKAA
#define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_1 "nordic,nrf5340-cpuapp"
#define DT_N_S_soc_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf5340-cpuapp
#define DT_N_S_soc_P_compatible_IDX_1_STRING_TOKEN nordic_nrf5340_cpuapp
#define DT_N_S_soc_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF5340_CPUAPP
#define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_2 "nordic,nrf53"
#define DT_N_S_soc_P_compatible_IDX_2_STRING_UNQUOTED nordic,nrf53
#define DT_N_S_soc_P_compatible_IDX_2_STRING_TOKEN nordic_nrf53
#define DT_N_S_soc_P_compatible_IDX_2_STRING_UPPER_TOKEN NORDIC_NRF53
#define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_3 "simple-bus"
#define DT_N_S_soc_P_compatible_IDX_3_STRING_UNQUOTED simple-bus
#define DT_N_S_soc_P_compatible_IDX_3_STRING_TOKEN simple_bus
#define DT_N_S_soc_P_compatible_IDX_3_STRING_UPPER_TOKEN SIMPLE_BUS
#define DT_N_S_soc_P_compatible_IDX_3_EXISTS 1
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0) \
	fn(DT_N_S_soc, compatible, 1) \
	fn(DT_N_S_soc, compatible, 2) \
	fn(DT_N_S_soc, compatible, 3)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 3)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 3, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 3, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_LEN 4
#define DT_N_S_soc_P_compatible_EXISTS 1
#define DT_N_S_soc_P_ranges_EXISTS 1

/*
 * Devicetree node: /soc/interrupt-controller@e000e100
 *
 * Node identifier: DT_N_S_soc_S_interrupt_controller_e000e100
 *
 * Binding (compatible = arm,v8m-nvic):
 *   $ZEPHYR_BASE\dts\bindings\interrupt-controller\arm,v8m-nvic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PATH "/soc/interrupt-controller@e000e100"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME "interrupt-controller@e000e100"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_NODELABEL_NUM 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_NODELABEL(fn) fn(nvic)
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_NODELABEL_VARGS(fn, ...) fn(nvic, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD 5
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD_STR_SORTABLE 00005

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \
	7, /* /soc/peripheral@50000000/timer@10000 */ \
	16, /* /soc/peripheral@50000000/mbox@2a000 */ \
	43, /* /soc/crypto@50844000 */ \
	45, /* /soc/gpiote@4002f000 */ \
	47, /* /soc/spu@50003000 */ \
	54, /* /soc/peripheral@50000000/adc@e000 */ \
	55, /* /soc/peripheral@50000000/clock@5000 */ \
	56, /* /soc/peripheral@50000000/comparator@1a000 */ \
	60, /* /soc/peripheral@50000000/egu@1b000 */ \
	61, /* /soc/peripheral@50000000/egu@1c000 */ \
	62, /* /soc/peripheral@50000000/egu@1d000 */ \
	63, /* /soc/peripheral@50000000/egu@1e000 */ \
	64, /* /soc/peripheral@50000000/egu@1f000 */ \
	65, /* /soc/peripheral@50000000/egu@20000 */ \
	66, /* /soc/gpiote@5000d000 */ \
	68, /* /soc/peripheral@50000000/i2c@8000 */ \
	69, /* /soc/peripheral@50000000/i2c@9000 */ \
	70, /* /soc/peripheral@50000000/i2c@b000 */ \
	71, /* /soc/peripheral@50000000/i2c@c000 */ \
	72, /* /soc/peripheral@50000000/i2s@28000 */ \
	74, /* /soc/peripheral@50000000/kmu@39000 */ \
	76, /* /soc/peripheral@50000000/nfct@2d000 */ \
	78, /* /soc/peripheral@50000000/pdm@26000 */ \
	79, /* /soc/peripheral@50000000/pwm@21000 */ \
	80, /* /soc/peripheral@50000000/pwm@22000 */ \
	81, /* /soc/peripheral@50000000/pwm@23000 */ \
	82, /* /soc/peripheral@50000000/pwm@24000 */ \
	83, /* /soc/peripheral@50000000/qdec@33000 */ \
	84, /* /soc/peripheral@50000000/qdec@34000 */ \
	85, /* /soc/peripheral@50000000/qspi@2b000 */ \
	86, /* /soc/peripheral@50000000/regulator@37000 */ \
	88, /* /soc/peripheral@50000000/rtc@14000 */ \
	89, /* /soc/peripheral@50000000/rtc@15000 */ \
	90, /* /soc/peripheral@50000000/spi@8000 */ \
	91, /* /soc/peripheral@50000000/spi@9000 */ \
	92, /* /soc/peripheral@50000000/spi@b000 */ \
	93, /* /soc/peripheral@50000000/spi@c000 */ \
	94, /* /soc/peripheral@50000000/timer@f000 */ \
	95, /* /soc/peripheral@50000000/timer@11000 */ \
	96, /* /soc/peripheral@50000000/uart@8000 */ \
	97, /* /soc/peripheral@50000000/uart@9000 */ \
	98, /* /soc/peripheral@50000000/uart@b000 */ \
	99, /* /soc/peripheral@50000000/uart@c000 */ \
	100, /* /soc/peripheral@50000000/usbd@36000 */ \
	102, /* /soc/peripheral@50000000/watchdog@18000 */ \
	103, /* /soc/peripheral@50000000/watchdog@19000 */ \
	110, /* /soc/peripheral@50000000/power@5000 */ \
	118, /* /soc/peripheral@50000000/spi@a000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1
#define DT_N_INST_0_arm_v8m_nvic DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_NODELABEL_nvic      DT_N_S_soc_S_interrupt_controller_e000e100

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_LEVEL 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0 "v8m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v8m-nvic"}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v8m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UNQUOTED arm,v8m-nvic
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_TOKEN arm_v8m_nvic
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_V8M_NVIC
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 3
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_PATH "/soc/peripheral@50000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_FULL_NAME "peripheral@50000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_NODELABEL_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_CHILD_NUM 56
#define DT_N_S_soc_S_peripheral_50000000_CHILD_NUM_STATUS_OKAY 28
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_ORD 6
#define DT_N_S_soc_S_peripheral_50000000_ORD_STR_SORTABLE 00006

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_SUPPORTS_ORDS \
	7, /* /soc/peripheral@50000000/timer@10000 */ \
	16, /* /soc/peripheral@50000000/mbox@2a000 */ \
	54, /* /soc/peripheral@50000000/adc@e000 */ \
	55, /* /soc/peripheral@50000000/clock@5000 */ \
	56, /* /soc/peripheral@50000000/comparator@1a000 */ \
	57, /* /soc/peripheral@50000000/ctrlap@6000 */ \
	58, /* /soc/peripheral@50000000/dcnf@0 */ \
	59, /* /soc/peripheral@50000000/dppic@17000 */ \
	60, /* /soc/peripheral@50000000/egu@1b000 */ \
	61, /* /soc/peripheral@50000000/egu@1c000 */ \
	62, /* /soc/peripheral@50000000/egu@1d000 */ \
	63, /* /soc/peripheral@50000000/egu@1e000 */ \
	64, /* /soc/peripheral@50000000/egu@1f000 */ \
	65, /* /soc/peripheral@50000000/egu@20000 */ \
	67, /* /soc/peripheral@50000000/gpio@842800 */ \
	68, /* /soc/peripheral@50000000/i2c@8000 */ \
	69, /* /soc/peripheral@50000000/i2c@9000 */ \
	70, /* /soc/peripheral@50000000/i2c@b000 */ \
	71, /* /soc/peripheral@50000000/i2c@c000 */ \
	72, /* /soc/peripheral@50000000/i2s@28000 */ \
	73, /* /soc/peripheral@50000000/ieee802154 */ \
	74, /* /soc/peripheral@50000000/kmu@39000 */ \
	75, /* /soc/peripheral@50000000/mutex@30000 */ \
	76, /* /soc/peripheral@50000000/nfct@2d000 */ \
	77, /* /soc/peripheral@50000000/oscillator@4000 */ \
	78, /* /soc/peripheral@50000000/pdm@26000 */ \
	79, /* /soc/peripheral@50000000/pwm@21000 */ \
	80, /* /soc/peripheral@50000000/pwm@22000 */ \
	81, /* /soc/peripheral@50000000/pwm@23000 */ \
	82, /* /soc/peripheral@50000000/pwm@24000 */ \
	83, /* /soc/peripheral@50000000/qdec@33000 */ \
	84, /* /soc/peripheral@50000000/qdec@34000 */ \
	85, /* /soc/peripheral@50000000/qspi@2b000 */ \
	86, /* /soc/peripheral@50000000/regulator@37000 */ \
	87, /* /soc/peripheral@50000000/reset-controller@5000 */ \
	88, /* /soc/peripheral@50000000/rtc@14000 */ \
	89, /* /soc/peripheral@50000000/rtc@15000 */ \
	90, /* /soc/peripheral@50000000/spi@8000 */ \
	91, /* /soc/peripheral@50000000/spi@9000 */ \
	92, /* /soc/peripheral@50000000/spi@b000 */ \
	93, /* /soc/peripheral@50000000/spi@c000 */ \
	94, /* /soc/peripheral@50000000/timer@f000 */ \
	95, /* /soc/peripheral@50000000/timer@11000 */ \
	96, /* /soc/peripheral@50000000/uart@8000 */ \
	97, /* /soc/peripheral@50000000/uart@9000 */ \
	98, /* /soc/peripheral@50000000/uart@b000 */ \
	99, /* /soc/peripheral@50000000/uart@c000 */ \
	100, /* /soc/peripheral@50000000/usbd@36000 */ \
	101, /* /soc/peripheral@50000000/vmc@81000 */ \
	102, /* /soc/peripheral@50000000/watchdog@18000 */ \
	103, /* /soc/peripheral@50000000/watchdog@19000 */ \
	104, /* /soc/peripheral@50000000/flash-controller@39000 */ \
	110, /* /soc/peripheral@50000000/power@5000 */ \
	113, /* /soc/peripheral@50000000/regulator@4000 */ \
	117, /* /soc/peripheral@50000000/gpio@842500 */ \
	118, /* /soc/peripheral@50000000/spi@a000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_REG_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_RANGES_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 1342177280 /* 0x50000000 */
#define DT_N_S_soc_S_peripheral_50000000_RANGES_IDX_0_VAL_LENGTH 268435456 /* 0x10000000 */
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_peripheral_50000000, 0)
#define DT_N_S_soc_S_peripheral_50000000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_P_ranges_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/timer@10000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_10000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PATH "/soc/peripheral@50000000/timer@10000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FULL_NAME "timer@10000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_CHILD_IDX 22

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_NODELABEL(fn) fn(timer1)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_ORD 7
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_ORD_STR_SORTABLE 00007

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_SUPPORTS_ORDS \
	8, /* /sw-pwm */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_10000
#define DT_N_NODELABEL_timer1        DT_N_S_soc_S_peripheral_50000000_S_timer_10000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_ADDRESS 1342242816 /* 0x50010000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq 16
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg {65536 /* 0x10000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_0 65536
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts {16 /* 0x10 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_0 16
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_bit_width 32
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_frequency 16000000
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zli 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_zli_EXISTS 1

/*
 * Devicetree node: /sw-pwm
 *
 * Node identifier: DT_N_S_sw_pwm
 *
 * Binding (compatible = nordic,nrf-sw-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-sw-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_sw_pwm_PATH "/sw-pwm"

/* Node's name with unit-address: */
#define DT_N_S_sw_pwm_FULL_NAME "sw-pwm"

/* Node parent (/) identifier: */
#define DT_N_S_sw_pwm_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_sw_pwm_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_sw_pwm_NODELABEL_NUM 1
#define DT_N_S_sw_pwm_FOREACH_NODELABEL(fn) fn(sw_pwm)
#define DT_N_S_sw_pwm_FOREACH_NODELABEL_VARGS(fn, ...) fn(sw_pwm, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_sw_pwm_CHILD_NUM 0
#define DT_N_S_sw_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_sw_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_sw_pwm_ORD 8
#define DT_N_S_sw_pwm_ORD_STR_SORTABLE 00008

/* Ordinals for what this node depends on directly: */
#define DT_N_S_sw_pwm_REQUIRES_ORDS \
	0, /* / */ \
	7, /* /soc/peripheral@50000000/timer@10000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_sw_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_sw_pwm_EXISTS 1
#define DT_N_INST_0_nordic_nrf_sw_pwm DT_N_S_sw_pwm
#define DT_N_NODELABEL_sw_pwm         DT_N_S_sw_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_sw_pwm_REG_NUM 0
#define DT_N_S_sw_pwm_RANGES_NUM 0
#define DT_N_S_sw_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_sw_pwm_IRQ_NUM 0
#define DT_N_S_sw_pwm_IRQ_LEVEL 0
#define DT_N_S_sw_pwm_COMPAT_MATCHES_nordic_nrf_sw_pwm 1
#define DT_N_S_sw_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_sw_pwm_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_sw_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_sw_pwm_COMPAT_MODEL_IDX_0 "nrf-sw-pwm"
#define DT_N_S_sw_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_sw_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_sw_pwm_P_wakeup_source 0
#define DT_N_S_sw_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_sw_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_sw_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_sw_pwm_P_status "disabled"
#define DT_N_S_sw_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_sw_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_sw_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_sw_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_sw_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_sw_pwm_P_status_ENUM_IDX 2
#define DT_N_S_sw_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_sw_pwm_P_status_ENUM_TOKEN disabled
#define DT_N_S_sw_pwm_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, status, 0)
#define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, status, 0)
#define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_status_LEN 1
#define DT_N_S_sw_pwm_P_status_EXISTS 1
#define DT_N_S_sw_pwm_P_compatible {"nordic,nrf-sw-pwm"}
#define DT_N_S_sw_pwm_P_compatible_IDX_0 "nordic,nrf-sw-pwm"
#define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-sw-pwm
#define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_sw_pwm
#define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SW_PWM
#define DT_N_S_sw_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, compatible, 0)
#define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, compatible, 0)
#define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_compatible_LEN 1
#define DT_N_S_sw_pwm_P_compatible_EXISTS 1
#define DT_N_S_sw_pwm_P_zephyr_deferred_init 0
#define DT_N_S_sw_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_sw_pwm_P_generator DT_N_S_soc_S_peripheral_50000000_S_timer_10000
#define DT_N_S_sw_pwm_P_generator_IDX_0 DT_N_S_soc_S_peripheral_50000000_S_timer_10000
#define DT_N_S_sw_pwm_P_generator_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_timer_10000
#define DT_N_S_sw_pwm_P_generator_IDX_0_EXISTS 1
#define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, generator, 0)
#define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, generator, 0)
#define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, generator, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, generator, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_generator_LEN 1
#define DT_N_S_sw_pwm_P_generator_EXISTS 1
#define DT_N_S_sw_pwm_P_clock_prescaler 0
#define DT_N_S_sw_pwm_P_clock_prescaler_EXISTS 1

/*
 * Devicetree node: /cpus
 *
 * Node identifier: DT_N_S_cpus
 */

/* Node's full path: */
#define DT_N_S_cpus_PATH "/cpus"

/* Node's name with unit-address: */
#define DT_N_S_cpus_FULL_NAME "cpus"

/* Node parent (/) identifier: */
#define DT_N_S_cpus_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_NODELABEL_NUM 0
#define DT_N_S_cpus_FOREACH_NODELABEL(fn) 
#define DT_N_S_cpus_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_CHILD_NUM 1
#define DT_N_S_cpus_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_ORD 9
#define DT_N_S_cpus_ORD_STR_SORTABLE 00009

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_SUPPORTS_ORDS \
	10, /* /cpus/cpu@0 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_REG_NUM 0
#define DT_N_S_cpus_RANGES_NUM 0
#define DT_N_S_cpus_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_IRQ_NUM 0
#define DT_N_S_cpus_IRQ_LEVEL 0
#define DT_N_S_cpus_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/cpu@0
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0
 *
 * Binding (compatible = arm,cortex-m33f):
 *   $ZEPHYR_BASE\dts\bindings\cpu\arm,cortex-m33f.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0"

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_cpu_0_NODELABEL_NUM 1
#define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL(fn) fn(cpu0)
#define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpu0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM 2
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_ORD 10
#define DT_N_S_cpus_S_cpu_0_ORD_STR_SORTABLE 00010

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \
	9, /* /cpus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS \
	11, /* /cpus/cpu@0/itm@e0000000 */ \
	12, /* /cpus/cpu@0/mpu@e000ed90 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_EXISTS 1
#define DT_N_INST_0_arm_cortex_m33f DT_N_S_cpus_S_cpu_0
#define DT_N_NODELABEL_cpu0         DT_N_S_cpus_S_cpu_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_IRQ_LEVEL 0
#define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m33f 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0 "cortex-m33f"
#define DT_N_S_cpus_S_cpu_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m33f"}
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m33f"
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UNQUOTED arm,cortex-m33f
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_TOKEN arm_cortex_m33f
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CORTEX_M33F
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */}
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@0/itm@e0000000
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0_S_itm_e0000000
 *
 * Binding (compatible = arm,armv8m-itm):
 *   $ZEPHYR_BASE\dts\bindings\debug\arm,armv8m-itm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PATH "/cpus/cpu@0/itm@e0000000"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FULL_NAME "itm@e0000000"

/* Node parent (/cpus/cpu@0) identifier: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PARENT DT_N_S_cpus_S_cpu_0

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_NODELABEL_NUM 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_NODELABEL(fn) fn(itm)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(itm, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_ORD 11
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_ORD_STR_SORTABLE 00011

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REQUIRES_ORDS \
	10, /* /cpus/cpu@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_EXISTS 1
#define DT_N_INST_0_arm_armv8m_itm DT_N_S_cpus_S_cpu_0_S_itm_e0000000
#define DT_N_NODELABEL_itm         DT_N_S_cpus_S_cpu_0_S_itm_e0000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_VAL_ADDRESS 3758096384 /* 0xe0000000 */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_IRQ_LEVEL 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MATCHES_arm_armv8m_itm 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MODEL_IDX_0 "armv8m-itm"
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_wakeup_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible {"arm,armv8m-itm"}
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0 "arm,armv8m-itm"
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-itm
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_itm
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_ITM
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg {3758096384 /* 0xe0000000 */, 4096 /* 0x1000 */}
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_0 3758096384
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_1 4096
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_deferred_init 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_swo_ref_frequency 64000000
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_swo_ref_frequency_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@0/mpu@e000ed90
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
 *
 * Binding (compatible = arm,armv8m-mpu):
 *   $ZEPHYR_BASE\dts\bindings\mmu_mpu\arm,armv8m-mpu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PATH "/cpus/cpu@0/mpu@e000ed90"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME "mpu@e000ed90"

/* Node parent (/cpus/cpu@0) identifier: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PARENT DT_N_S_cpus_S_cpu_0

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_NODELABEL_NUM 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_NODELABEL(fn) fn(mpu)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_NODELABEL_VARGS(fn, ...) fn(mpu, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD 12
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD_STR_SORTABLE 00012

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REQUIRES_ORDS \
	10, /* /cpus/cpu@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_EXISTS 1
#define DT_N_INST_0_arm_armv8m_mpu DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
#define DT_N_NODELABEL_mpu         DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS 3758157200 /* 0xe000ed90 */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE 64 /* 0x40 */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_LEVEL 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MATCHES_arm_armv8m_mpu 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MODEL_IDX_0 "armv8m-mpu"
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible {"arm,armv8m-mpu"}
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0 "arm,armv8m-mpu"
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-mpu
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_mpu
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_MPU
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg {3758157200 /* 0xe000ed90 */, 64 /* 0x40 */}
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0 3758157200
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1 64
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_deferred_init 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /ipc
 *
 * Node identifier: DT_N_S_ipc
 */

/* Node's full path: */
#define DT_N_S_ipc_PATH "/ipc"

/* Node's name with unit-address: */
#define DT_N_S_ipc_FULL_NAME "ipc"

/* Node parent (/) identifier: */
#define DT_N_S_ipc_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_ipc_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_ipc_NODELABEL_NUM 0
#define DT_N_S_ipc_FOREACH_NODELABEL(fn) 
#define DT_N_S_ipc_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_ipc_CHILD_NUM 1
#define DT_N_S_ipc_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_ipc_FOREACH_CHILD(fn) fn(DT_N_S_ipc_S_ipc0)
#define DT_N_S_ipc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0)
#define DT_N_S_ipc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__)
#define DT_N_S_ipc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__)
#define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_ipc_S_ipc0)
#define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0)
#define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__)
#define DT_N_S_ipc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_ipc_ORD 13
#define DT_N_S_ipc_ORD_STR_SORTABLE 00013

/* Ordinals for what this node depends on directly: */
#define DT_N_S_ipc_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_ipc_SUPPORTS_ORDS \
	17, /* /ipc/ipc0 */

/* Existence and alternate IDs: */
#define DT_N_S_ipc_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_ipc_REG_NUM 0
#define DT_N_S_ipc_RANGES_NUM 0
#define DT_N_S_ipc_FOREACH_RANGE(fn) 
#define DT_N_S_ipc_IRQ_NUM 0
#define DT_N_S_ipc_IRQ_LEVEL 0
#define DT_N_S_ipc_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_ipc_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /reserved-memory
 *
 * Node identifier: DT_N_S_reserved_memory
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_PATH "/reserved-memory"

/* Node's name with unit-address: */
#define DT_N_S_reserved_memory_FULL_NAME "reserved-memory"

/* Node parent (/) identifier: */
#define DT_N_S_reserved_memory_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_reserved_memory_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_reserved_memory_NODELABEL_NUM 0
#define DT_N_S_reserved_memory_FOREACH_NODELABEL(fn) 
#define DT_N_S_reserved_memory_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_reserved_memory_CHILD_NUM 4
#define DT_N_S_reserved_memory_CHILD_NUM_STATUS_OKAY 4
#define DT_N_S_reserved_memory_FOREACH_CHILD(fn) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_memory_20078000)
#define DT_N_S_reserved_memory_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20078000)
#define DT_N_S_reserved_memory_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__)
#define DT_N_S_reserved_memory_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__)
#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_memory_20078000)
#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_reserved_memory_S_image_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20078000)
#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__)
#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_ORD 14
#define DT_N_S_reserved_memory_ORD_STR_SORTABLE 00014

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_SUPPORTS_ORDS \
	15, /* /reserved-memory/memory@20078000 */ \
	40, /* /reserved-memory/image@20000000 */ \
	41, /* /reserved-memory/image_ns@20040000 */ \
	42, /* /reserved-memory/image_s@20000000 */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_reserved_memory_REG_NUM 0
#define DT_N_S_reserved_memory_RANGES_NUM 0
#define DT_N_S_reserved_memory_FOREACH_RANGE(fn) 
#define DT_N_S_reserved_memory_IRQ_NUM 0
#define DT_N_S_reserved_memory_IRQ_LEVEL 0
#define DT_N_S_reserved_memory_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_reserved_memory_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_reserved_memory_P_ranges_EXISTS 1

/*
 * Devicetree node: /reserved-memory/memory@20078000
 *
 * Node identifier: DT_N_S_reserved_memory_S_memory_20078000
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_S_memory_20078000_PATH "/reserved-memory/memory@20078000"

/* Node's name with unit-address: */
#define DT_N_S_reserved_memory_S_memory_20078000_FULL_NAME "memory@20078000"

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_memory_20078000_PARENT DT_N_S_reserved_memory

/* Node's index in its parent's list of children: */
#define DT_N_S_reserved_memory_S_memory_20078000_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_reserved_memory_S_memory_20078000_NODELABEL_NUM 1
#define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_NODELABEL(fn) fn(sram0_shared)
#define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0_shared, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_reserved_memory_S_memory_20078000_CHILD_NUM 0
#define DT_N_S_reserved_memory_S_memory_20078000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD(fn) 
#define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_S_memory_20078000_ORD 15
#define DT_N_S_reserved_memory_S_memory_20078000_ORD_STR_SORTABLE 00015

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_S_memory_20078000_REQUIRES_ORDS \
	14, /* /reserved-memory */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_S_memory_20078000_SUPPORTS_ORDS \
	17, /* /ipc/ipc0 */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_memory_20078000_EXISTS 1
#define DT_N_NODELABEL_sram0_shared DT_N_S_reserved_memory_S_memory_20078000

/* Macros for properties that are special in the specification: */
#define DT_N_S_reserved_memory_S_memory_20078000_REG_NUM 1
#define DT_N_S_reserved_memory_S_memory_20078000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_memory_20078000_REG_IDX_0_VAL_ADDRESS 537362432 /* 0x20078000 */
#define DT_N_S_reserved_memory_S_memory_20078000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */
#define DT_N_S_reserved_memory_S_memory_20078000_RANGES_NUM 0
#define DT_N_S_reserved_memory_S_memory_20078000_FOREACH_RANGE(fn) 
#define DT_N_S_reserved_memory_S_memory_20078000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_memory_20078000_IRQ_LEVEL 0
#define DT_N_S_reserved_memory_S_memory_20078000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_reserved_memory_S_memory_20078000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_memory_20078000_P_reg {537362432 /* 0x20078000 */, 32768 /* 0x8000 */}
#define DT_N_S_reserved_memory_S_memory_20078000_P_reg_IDX_0 537362432
#define DT_N_S_reserved_memory_S_memory_20078000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_memory_20078000_P_reg_IDX_1 32768
#define DT_N_S_reserved_memory_S_memory_20078000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_reserved_memory_S_memory_20078000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/mbox@2a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
 *
 * Binding (compatible = nordic,mbox-nrf-ipc):
 *   $ZEPHYR_BASE\dts\bindings\mbox\nordic,mbox-nrf-ipc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_PATH "/soc/peripheral@50000000/mbox@2a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FULL_NAME "mbox@2a000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_CHILD_IDX 42

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_NODELABEL_NUM 2
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_NODELABEL(fn) fn(mbox) fn(ipc)
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(mbox, __VA_ARGS__) fn(ipc, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_ORD 16
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_ORD_STR_SORTABLE 00016

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_SUPPORTS_ORDS \
	17, /* /ipc/ipc0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_EXISTS 1
#define DT_N_INST_0_nordic_mbox_nrf_ipc DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
#define DT_N_INST_0_nordic_nrf_ipc      DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
#define DT_N_NODELABEL_mbox             DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
#define DT_N_NODELABEL_ipc              DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_IDX_0_VAL_ADDRESS 1342349312 /* 0x5002a000 */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_irq 42
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MATCHES_nordic_mbox_nrf_ipc 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_0 "mbox-nrf-ipc"
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MATCHES_nordic_nrf_ipc 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_COMPAT_MODEL_IDX_1 "nrf-ipc"
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible {"nordic,mbox-nrf-ipc", "nordic,nrf-ipc"}
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0 "nordic,mbox-nrf-ipc"
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,mbox-nrf-ipc
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_STRING_TOKEN nordic_mbox_nrf_ipc
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_MBOX_NRF_IPC
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1 "nordic,nrf-ipc"
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf-ipc
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_STRING_TOKEN nordic_nrf_ipc
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF_IPC
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_LEN 2
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg {172032 /* 0x2a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_0 172032
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts {42 /* 0x2a */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_0 42
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_tx_mask 65535
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_tx_mask_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_rx_mask 65535
#define DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000_P_rx_mask_EXISTS 1

/*
 * Devicetree node: /ipc/ipc0
 *
 * Node identifier: DT_N_S_ipc_S_ipc0
 *
 * Binding (compatible = zephyr,ipc-openamp-static-vrings):
 *   $ZEPHYR_BASE\dts\bindings\ipc\zephyr,ipc-openamp-static-vrings.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_ipc_S_ipc0_PATH "/ipc/ipc0"

/* Node's name with unit-address: */
#define DT_N_S_ipc_S_ipc0_FULL_NAME "ipc0"

/* Node parent (/ipc) identifier: */
#define DT_N_S_ipc_S_ipc0_PARENT DT_N_S_ipc

/* Node's index in its parent's list of children: */
#define DT_N_S_ipc_S_ipc0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_ipc_S_ipc0_NODELABEL_NUM 1
#define DT_N_S_ipc_S_ipc0_FOREACH_NODELABEL(fn) fn(ipc0)
#define DT_N_S_ipc_S_ipc0_FOREACH_NODELABEL_VARGS(fn, ...) fn(ipc0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_ipc_S_ipc0_CHILD_NUM 1
#define DT_N_S_ipc_S_ipc0_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_ipc_S_ipc0_FOREACH_CHILD(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0)
#define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0)
#define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0)
#define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0)
#define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_ipc_S_ipc0_ORD 17
#define DT_N_S_ipc_S_ipc0_ORD_STR_SORTABLE 00017

/* Ordinals for what this node depends on directly: */
#define DT_N_S_ipc_S_ipc0_REQUIRES_ORDS \
	13, /* /ipc */ \
	15, /* /reserved-memory/memory@20078000 */ \
	16, /* /soc/peripheral@50000000/mbox@2a000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_ipc_S_ipc0_SUPPORTS_ORDS \
	18, /* /ipc/ipc0/bt_hci_ipc0 */

/* Existence and alternate IDs: */
#define DT_N_S_ipc_S_ipc0_EXISTS 1
#define DT_N_INST_0_zephyr_ipc_openamp_static_vrings DT_N_S_ipc_S_ipc0
#define DT_N_NODELABEL_ipc0                          DT_N_S_ipc_S_ipc0

/* Macros for properties that are special in the specification: */
#define DT_N_S_ipc_S_ipc0_REG_NUM 0
#define DT_N_S_ipc_S_ipc0_RANGES_NUM 0
#define DT_N_S_ipc_S_ipc0_FOREACH_RANGE(fn) 
#define DT_N_S_ipc_S_ipc0_IRQ_NUM 0
#define DT_N_S_ipc_S_ipc0_IRQ_LEVEL 0
#define DT_N_S_ipc_S_ipc0_COMPAT_MATCHES_zephyr_ipc_openamp_static_vrings 1
#define DT_N_S_ipc_S_ipc0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding"
#define DT_N_S_ipc_S_ipc0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_COMPAT_MODEL_IDX_0 "ipc-openamp-static-vrings"
#define DT_N_S_ipc_S_ipc0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_ipc_S_ipc0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_ipc_S_ipc0_P_wakeup_source 0
#define DT_N_S_ipc_S_ipc0_P_wakeup_source_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_ipc_S_ipc0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_status "okay"
#define DT_N_S_ipc_S_ipc0_P_status_STRING_UNQUOTED okay
#define DT_N_S_ipc_S_ipc0_P_status_STRING_TOKEN okay
#define DT_N_S_ipc_S_ipc0_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_ipc_S_ipc0_P_status_IDX_0 "okay"
#define DT_N_S_ipc_S_ipc0_P_status_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_status_ENUM_IDX 1
#define DT_N_S_ipc_S_ipc0_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_status_ENUM_TOKEN okay
#define DT_N_S_ipc_S_ipc0_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, status, 0)
#define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, status, 0)
#define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, status, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, status, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_status_LEN 1
#define DT_N_S_ipc_S_ipc0_P_status_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_compatible {"zephyr,ipc-openamp-static-vrings"}
#define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0 "zephyr,ipc-openamp-static-vrings"
#define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_STRING_UNQUOTED zephyr,ipc-openamp-static-vrings
#define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_STRING_TOKEN zephyr_ipc_openamp_static_vrings
#define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_IPC_OPENAMP_STATIC_VRINGS
#define DT_N_S_ipc_S_ipc0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, compatible, 0)
#define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, compatible, 0)
#define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, compatible, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, compatible, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_compatible_LEN 1
#define DT_N_S_ipc_S_ipc0_P_compatible_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
#define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_VAL_channel 0
#define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_NAME "tx"
#define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
#define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_VAL_channel DT_N_S_ipc_S_ipc0_P_mboxes_IDX_0_VAL_channel
#define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_tx_VAL_channel_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
#define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_VAL_channel 1
#define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_VAL_channel_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_NAME "rx"
#define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_PH DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000
#define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_VAL_channel DT_N_S_ipc_S_ipc0_P_mboxes_IDX_1_VAL_channel
#define DT_N_S_ipc_S_ipc0_P_mboxes_NAME_rx_VAL_channel_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, mboxes, 0) \
	fn(DT_N_S_ipc_S_ipc0, mboxes, 1)
#define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, mboxes, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_ipc_S_ipc0, mboxes, 1)
#define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, mboxes, 0, __VA_ARGS__) \
	fn(DT_N_S_ipc_S_ipc0, mboxes, 1, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_mboxes_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, mboxes, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_ipc_S_ipc0, mboxes, 1, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_mboxes_LEN 2
#define DT_N_S_ipc_S_ipc0_P_mboxes_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mbox_names {"tx", "rx"}
#define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0 "tx"
#define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_STRING_UNQUOTED tx
#define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_STRING_TOKEN tx
#define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_STRING_UPPER_TOKEN TX
#define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1 "rx"
#define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_STRING_UNQUOTED rx
#define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_STRING_TOKEN rx
#define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_STRING_UPPER_TOKEN RX
#define DT_N_S_ipc_S_ipc0_P_mbox_names_IDX_1_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0) \
	fn(DT_N_S_ipc_S_ipc0, mbox_names, 1)
#define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_ipc_S_ipc0, mbox_names, 1)
#define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0, __VA_ARGS__) \
	fn(DT_N_S_ipc_S_ipc0, mbox_names, 1, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_mbox_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, mbox_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_ipc_S_ipc0, mbox_names, 1, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_mbox_names_LEN 2
#define DT_N_S_ipc_S_ipc0_P_mbox_names_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_zephyr_deferred_init 0
#define DT_N_S_ipc_S_ipc0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_role "host"
#define DT_N_S_ipc_S_ipc0_P_role_STRING_UNQUOTED host
#define DT_N_S_ipc_S_ipc0_P_role_STRING_TOKEN host
#define DT_N_S_ipc_S_ipc0_P_role_STRING_UPPER_TOKEN HOST
#define DT_N_S_ipc_S_ipc0_P_role_IDX_0 "host"
#define DT_N_S_ipc_S_ipc0_P_role_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_role_ENUM_IDX 0
#define DT_N_S_ipc_S_ipc0_P_role_ENUM_VAL_host_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_role_ENUM_TOKEN host
#define DT_N_S_ipc_S_ipc0_P_role_ENUM_UPPER_TOKEN HOST
#define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, role, 0)
#define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, role, 0)
#define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, role, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_role_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, role, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_role_LEN 1
#define DT_N_S_ipc_S_ipc0_P_role_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_memory_region DT_N_S_reserved_memory_S_memory_20078000
#define DT_N_S_ipc_S_ipc0_P_memory_region_IDX_0 DT_N_S_reserved_memory_S_memory_20078000
#define DT_N_S_ipc_S_ipc0_P_memory_region_IDX_0_PH DT_N_S_reserved_memory_S_memory_20078000
#define DT_N_S_ipc_S_ipc0_P_memory_region_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_P_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0, memory_region, 0)
#define DT_N_S_ipc_S_ipc0_P_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0, memory_region, 0)
#define DT_N_S_ipc_S_ipc0_P_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0, memory_region, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0, memory_region, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_P_memory_region_LEN 1
#define DT_N_S_ipc_S_ipc0_P_memory_region_EXISTS 1

/*
 * Devicetree node: /ipc/ipc0/bt_hci_ipc0
 *
 * Node identifier: DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0
 *
 * Binding (compatible = zephyr,bt-hci-ipc):
 *   $ZEPHYR_BASE\dts\bindings\bluetooth\zephyr,bt-hci-ipc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_PATH "/ipc/ipc0/bt_hci_ipc0"

/* Node's name with unit-address: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FULL_NAME "bt_hci_ipc0"

/* Node parent (/ipc/ipc0) identifier: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_PARENT DT_N_S_ipc_S_ipc0

/* Node's index in its parent's list of children: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_NODELABEL_NUM 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_NODELABEL(fn) fn(bt_hci_ipc0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_NODELABEL_VARGS(fn, ...) fn(bt_hci_ipc0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_CHILD_NUM 0
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD(fn) 
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_ORD 18
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_ORD_STR_SORTABLE 00018

/* Ordinals for what this node depends on directly: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_REQUIRES_ORDS \
	17, /* /ipc/ipc0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_EXISTS 1
#define DT_N_INST_0_zephyr_bt_hci_ipc DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0
#define DT_N_NODELABEL_bt_hci_ipc0    DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0

/* Macros for properties that are special in the specification: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_REG_NUM 0
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_RANGES_NUM 0
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_FOREACH_RANGE(fn) 
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_IRQ_NUM 0
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_IRQ_LEVEL 0
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_COMPAT_MATCHES_zephyr_bt_hci_ipc 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_COMPAT_MODEL_IDX_0 "bt-hci-ipc"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_wakeup_source 0
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_wakeup_source_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status "okay"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_STRING_UNQUOTED okay
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_STRING_TOKEN okay
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_IDX_0 "okay"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_ENUM_IDX 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_ENUM_TOKEN okay
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, status, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, status, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, status, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, status, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_LEN 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_status_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible {"zephyr,bt-hci-ipc"}
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_IDX_0 "zephyr,bt-hci-ipc"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_IDX_0_STRING_UNQUOTED zephyr,bt-hci-ipc
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_ipc
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_IPC
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, compatible, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, compatible, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, compatible, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, compatible, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_LEN 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_compatible_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_zephyr_deferred_init 0
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name "IPC"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_STRING_UNQUOTED IPC
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_STRING_TOKEN IPC
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_STRING_UPPER_TOKEN IPC
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_IDX_0 "IPC"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_name, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_name, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_name, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_name, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_LEN 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_name_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus "BT_HCI_BUS_IPM"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_STRING_UNQUOTED BT_HCI_BUS_IPM
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_STRING_TOKEN BT_HCI_BUS_IPM
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_STRING_UPPER_TOKEN BT_HCI_BUS_IPM
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_IDX_0 "BT_HCI_BUS_IPM"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_ENUM_IDX 9
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_ENUM_VAL_BT_HCI_BUS_IPM_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_ENUM_TOKEN BT_HCI_BUS_IPM
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_ENUM_UPPER_TOKEN BT_HCI_BUS_IPM
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_bus, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_bus, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_bus, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_bus, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_LEN 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_bus_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks {"BT_HCI_QUIRK_NO_AUTO_DLE"}
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0 "BT_HCI_QUIRK_NO_AUTO_DLE"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0_STRING_UNQUOTED BT_HCI_QUIRK_NO_AUTO_DLE
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0_STRING_TOKEN BT_HCI_QUIRK_NO_AUTO_DLE
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0_STRING_UPPER_TOKEN BT_HCI_QUIRK_NO_AUTO_DLE
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_quirks, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_quirks, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_quirks, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_quirks, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_LEN 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_quirks_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_vs_ext 0
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_vs_ext_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name "nrf_bt_hci"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_STRING_UNQUOTED nrf_bt_hci
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_STRING_TOKEN nrf_bt_hci
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_STRING_UPPER_TOKEN NRF_BT_HCI
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_IDX_0 "nrf_bt_hci"
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_IDX_0_EXISTS 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_ipc_name, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_ipc_name, 0)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_ipc_name, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, bt_hci_ipc_name, 0, __VA_ARGS__)
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_LEN 1
#define DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0_P_bt_hci_ipc_name_EXISTS 1

/*
 * Devicetree node: /pin-controller
 *
 * Node identifier: DT_N_S_pin_controller
 *
 * Binding (compatible = nordic,nrf-pinctrl):
 *   $ZEPHYR_BASE\dts\bindings\pinctrl\nordic,nrf-pinctrl.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_PATH "/pin-controller"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_FULL_NAME "pin-controller"

/* Node parent (/) identifier: */
#define DT_N_S_pin_controller_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_NODELABEL_NUM 1
#define DT_N_S_pin_controller_FOREACH_NODELABEL(fn) fn(pinctrl)
#define DT_N_S_pin_controller_FOREACH_NODELABEL_VARGS(fn, ...) fn(pinctrl, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_CHILD_NUM 10
#define DT_N_S_pin_controller_CHILD_NUM_STATUS_OKAY 10
#define DT_N_S_pin_controller_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi1_default_9160) fn(DT_N_S_pin_controller_S_spi1_default_dw1000) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_sleep) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c0_sleep) fn(DT_N_S_pin_controller_S_i2c2_default) fn(DT_N_S_pin_controller_S_i2c2_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_default_9160) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_default_dw1000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_default_9160, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_dw1000, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_default_9160, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_default_dw1000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi1_default_9160) fn(DT_N_S_pin_controller_S_spi1_default_dw1000) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_sleep) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c0_sleep) fn(DT_N_S_pin_controller_S_i2c2_default) fn(DT_N_S_pin_controller_S_i2c2_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_default_9160) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_default_dw1000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_default_9160, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_dw1000, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_default_9160, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_default_dw1000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_ORD 19
#define DT_N_S_pin_controller_ORD_STR_SORTABLE 00019

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_SUPPORTS_ORDS \
	20, /* /pin-controller/i2c0_default */ \
	22, /* /pin-controller/i2c0_sleep */ \
	24, /* /pin-controller/i2c2_default */ \
	26, /* /pin-controller/i2c2_sleep */ \
	28, /* /pin-controller/spi1_default_9160 */ \
	30, /* /pin-controller/spi1_default_dw1000 */ \
	32, /* /pin-controller/spi3_default */ \
	34, /* /pin-controller/spi3_sleep */ \
	36, /* /pin-controller/spi4_default */ \
	38, /* /pin-controller/spi4_sleep */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pinctrl DT_N_S_pin_controller
#define DT_N_NODELABEL_pinctrl         DT_N_S_pin_controller

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_REG_NUM 0
#define DT_N_S_pin_controller_RANGES_NUM 0
#define DT_N_S_pin_controller_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_IRQ_NUM 0
#define DT_N_S_pin_controller_IRQ_LEVEL 0
#define DT_N_S_pin_controller_COMPAT_MATCHES_nordic_nrf_pinctrl 1
#define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0 "nrf-pinctrl"
#define DT_N_S_pin_controller_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_P_wakeup_source 0
#define DT_N_S_pin_controller_P_wakeup_source_EXISTS 1
#define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_pin_controller_P_compatible {"nordic,nrf-pinctrl"}
#define DT_N_S_pin_controller_P_compatible_IDX_0 "nordic,nrf-pinctrl"
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pinctrl
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pinctrl
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PINCTRL
#define DT_N_S_pin_controller_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller, compatible, 0)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller, compatible, 0)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_compatible_LEN 1
#define DT_N_S_pin_controller_P_compatible_EXISTS 1
#define DT_N_S_pin_controller_P_zephyr_deferred_init 0
#define DT_N_S_pin_controller_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /pin-controller/i2c0_default
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c0_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c0_default_PATH "/pin-controller/i2c0_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c0_default_FULL_NAME "i2c0_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_i2c0_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c0_default_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c0_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_NODELABEL(fn) fn(i2c0_default)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c0_default, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c0_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_i2c0_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c0_default_ORD 20
#define DT_N_S_pin_controller_S_i2c0_default_ORD_STR_SORTABLE 00020

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c0_default_REQUIRES_ORDS \
	19, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c0_default_SUPPORTS_ORDS \
	21, /* /pin-controller/i2c0_default/group1 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c0_default_EXISTS 1
#define DT_N_NODELABEL_i2c0_default DT_N_S_pin_controller_S_i2c0_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c0_default_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c0_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c0_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/i2c0_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c0_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_PATH "/pin-controller/i2c0_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/i2c0_default) identifier: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_PARENT DT_N_S_pin_controller_S_i2c0_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_ORD 21
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_ORD_STR_SORTABLE 00021

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_REQUIRES_ORDS \
	20, /* /pin-controller/i2c0_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels {184549410 /* 0xb000022 */, 201326627 /* 0xc000023 */}
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_IDX_0 184549410
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_IDX_1 201326627
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/i2c0_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c0_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c0_sleep_PATH "/pin-controller/i2c0_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c0_sleep_FULL_NAME "i2c0_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_i2c0_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c0_sleep_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c0_sleep_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_NODELABEL(fn) fn(i2c0_sleep)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c0_sleep, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c0_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_i2c0_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c0_sleep_ORD 22
#define DT_N_S_pin_controller_S_i2c0_sleep_ORD_STR_SORTABLE 00022

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c0_sleep_REQUIRES_ORDS \
	19, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c0_sleep_SUPPORTS_ORDS \
	23, /* /pin-controller/i2c0_sleep/group1 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c0_sleep_EXISTS 1
#define DT_N_NODELABEL_i2c0_sleep DT_N_S_pin_controller_S_i2c0_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c0_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c0_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c0_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c0_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/i2c0_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c0_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_PATH "/pin-controller/i2c0_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/i2c0_sleep) identifier: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_i2c0_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_ORD 23
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_ORD_STR_SORTABLE 00023

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_REQUIRES_ORDS \
	22, /* /pin-controller/i2c0_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels {184549410 /* 0xb000022 */, 201326627 /* 0xc000023 */}
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_IDX_0 184549410
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_IDX_1 201326627
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/i2c2_default
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c2_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c2_default_PATH "/pin-controller/i2c2_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c2_default_FULL_NAME "i2c2_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_i2c2_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c2_default_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c2_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_i2c2_default_FOREACH_NODELABEL(fn) fn(i2c2_default)
#define DT_N_S_pin_controller_S_i2c2_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c2_default, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c2_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_i2c2_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1)
#define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1)
#define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1)
#define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1)
#define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c2_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c2_default_ORD 24
#define DT_N_S_pin_controller_S_i2c2_default_ORD_STR_SORTABLE 00024

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c2_default_REQUIRES_ORDS \
	19, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c2_default_SUPPORTS_ORDS \
	25, /* /pin-controller/i2c2_default/group1 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c2_default_EXISTS 1
#define DT_N_NODELABEL_i2c2_default DT_N_S_pin_controller_S_i2c2_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c2_default_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c2_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c2_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c2_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c2_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c2_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c2_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/i2c2_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c2_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_PATH "/pin-controller/i2c2_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/i2c2_default) identifier: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_PARENT DT_N_S_pin_controller_S_i2c2_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_ORD 25
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_ORD_STR_SORTABLE 00025

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_REQUIRES_ORDS \
	24, /* /pin-controller/i2c2_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_pull_up 1
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels {184549417 /* 0xb000029 */, 201326631 /* 0xc000027 */}
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_IDX_0 184549417
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_IDX_1 201326631
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_i2c2_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/i2c2_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c2_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c2_sleep_PATH "/pin-controller/i2c2_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c2_sleep_FULL_NAME "i2c2_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_i2c2_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c2_sleep_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c2_sleep_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_NODELABEL(fn) fn(i2c2_sleep)
#define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c2_sleep, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c2_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_i2c2_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c2_sleep_ORD 26
#define DT_N_S_pin_controller_S_i2c2_sleep_ORD_STR_SORTABLE 00026

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c2_sleep_REQUIRES_ORDS \
	19, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c2_sleep_SUPPORTS_ORDS \
	27, /* /pin-controller/i2c2_sleep/group1 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c2_sleep_EXISTS 1
#define DT_N_NODELABEL_i2c2_sleep DT_N_S_pin_controller_S_i2c2_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c2_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c2_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c2_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c2_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c2_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c2_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c2_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/i2c2_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c2_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_PATH "/pin-controller/i2c2_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/i2c2_sleep) identifier: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_PARENT DT_N_S_pin_controller_S_i2c2_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_ORD 27
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_ORD_STR_SORTABLE 00027

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_REQUIRES_ORDS \
	26, /* /pin-controller/i2c2_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_pull_up 1
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels {184549417 /* 0xb000029 */, 201326631 /* 0xc000027 */}
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_IDX_0 184549417
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_IDX_1 201326631
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_i2c2_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi1_default_9160
 *
 * Node identifier: DT_N_S_pin_controller_S_spi1_default_9160
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi1_default_9160_PATH "/pin-controller/spi1_default_9160"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi1_default_9160_FULL_NAME "spi1_default_9160"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi1_default_9160_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi1_default_9160_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi1_default_9160_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_spi1_default_9160_FOREACH_NODELABEL(fn) fn(spi1_default_9160)
#define DT_N_S_pin_controller_S_spi1_default_9160_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1_default_9160, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi1_default_9160_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi1_default_9160_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi1_default_9160_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_9160_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_9160_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_9160_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_9160_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_9160_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_9160_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_9160_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi1_default_9160_ORD 28
#define DT_N_S_pin_controller_S_spi1_default_9160_ORD_STR_SORTABLE 00028

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi1_default_9160_REQUIRES_ORDS \
	19, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi1_default_9160_SUPPORTS_ORDS \
	29, /* /pin-controller/spi1_default_9160/group1 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi1_default_9160_EXISTS 1
#define DT_N_NODELABEL_spi1_default_9160 DT_N_S_pin_controller_S_spi1_default_9160

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi1_default_9160_REG_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_9160_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_9160_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi1_default_9160_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_9160_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi1_default_9160_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi1_default_9160_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi1_default_9160/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi1_default_9160_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_PATH "/pin-controller/spi1_default_9160/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi1_default_9160) identifier: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_PARENT DT_N_S_pin_controller_S_spi1_default_9160

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_ORD 29
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_ORD_STR_SORTABLE 00029

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_REQUIRES_ORDS \
	28, /* /pin-controller/spi1_default_9160 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels {67108894 /* 0x400001e */, 83886111 /* 0x500001f */, 100663339 /* 0x600002b */}
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_IDX_0 67108894
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_IDX_1 83886111
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_IDX_2 100663339
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi1_default_9160_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi1_default_dw1000
 *
 * Node identifier: DT_N_S_pin_controller_S_spi1_default_dw1000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_PATH "/pin-controller/spi1_default_dw1000"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FULL_NAME "spi1_default_dw1000"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FOREACH_NODELABEL(fn) fn(spi1_default_dw1000)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1_default_dw1000, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_ORD 30
#define DT_N_S_pin_controller_S_spi1_default_dw1000_ORD_STR_SORTABLE 00030

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_REQUIRES_ORDS \
	19, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_SUPPORTS_ORDS \
	31, /* /pin-controller/spi1_default_dw1000/group1 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_EXISTS 1
#define DT_N_NODELABEL_spi1_default_dw1000 DT_N_S_pin_controller_S_spi1_default_dw1000

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_REG_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi1_default_dw1000_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi1_default_dw1000/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_PATH "/pin-controller/spi1_default_dw1000/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi1_default_dw1000) identifier: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_PARENT DT_N_S_pin_controller_S_spi1_default_dw1000

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_ORD 31
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_ORD_STR_SORTABLE 00031

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_REQUIRES_ORDS \
	30, /* /pin-controller/spi1_default_dw1000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels {67108871 /* 0x4000007 */, 83886086 /* 0x5000006 */, 100663301 /* 0x6000005 */}
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_IDX_0 67108871
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_IDX_1 83886086
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_IDX_2 100663301
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi3_default
 *
 * Node identifier: DT_N_S_pin_controller_S_spi3_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi3_default_PATH "/pin-controller/spi3_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi3_default_FULL_NAME "spi3_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi3_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi3_default_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi3_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_NODELABEL(fn) fn(spi3_default)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3_default, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi3_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi3_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi3_default_S_group1)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_default_S_group1)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi3_default_S_group1)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_default_S_group1)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi3_default_ORD 32
#define DT_N_S_pin_controller_S_spi3_default_ORD_STR_SORTABLE 00032

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi3_default_REQUIRES_ORDS \
	19, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi3_default_SUPPORTS_ORDS \
	33, /* /pin-controller/spi3_default/group1 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi3_default_EXISTS 1
#define DT_N_NODELABEL_spi3_default DT_N_S_pin_controller_S_spi3_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi3_default_REG_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi3_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi3_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi3_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi3_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi3_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_PATH "/pin-controller/spi3_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi3_default) identifier: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_PARENT DT_N_S_pin_controller_S_spi3_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_ORD 33
#define DT_N_S_pin_controller_S_spi3_default_S_group1_ORD_STR_SORTABLE 00033

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_REQUIRES_ORDS \
	32, /* /pin-controller/spi3_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels {117440559 /* 0x700002f */, 134217774 /* 0x800002e */, 150994976 /* 0x9000020 */, 167772179 /* 0xa000013 */}
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_0 117440559
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_1 134217774
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_2 150994976
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_3 167772179
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_3_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2) \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 3)
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 3)
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 3, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 3, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_LEN 4
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi3_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_spi3_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi3_sleep_PATH "/pin-controller/spi3_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi3_sleep_FULL_NAME "spi3_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi3_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi3_sleep_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi3_sleep_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_NODELABEL(fn) fn(spi3_sleep)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3_sleep, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi3_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi3_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi3_sleep_ORD 34
#define DT_N_S_pin_controller_S_spi3_sleep_ORD_STR_SORTABLE 00034

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi3_sleep_REQUIRES_ORDS \
	19, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi3_sleep_SUPPORTS_ORDS \
	35, /* /pin-controller/spi3_sleep/group1 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi3_sleep_EXISTS 1
#define DT_N_NODELABEL_spi3_sleep DT_N_S_pin_controller_S_spi3_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi3_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi3_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi3_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi3_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi3_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi3_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_PATH "/pin-controller/spi3_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi3_sleep) identifier: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi3_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_ORD 35
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_ORD_STR_SORTABLE 00035

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_REQUIRES_ORDS \
	34, /* /pin-controller/spi3_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels {117440559 /* 0x700002f */, 134217774 /* 0x800002e */, 150994976 /* 0x9000020 */, 167772179 /* 0xa000013 */}
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_0 117440559
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_1 134217774
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_2 150994976
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_3 167772179
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_3_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2) \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 3)
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 3)
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 3, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 3, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_LEN 4
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi4_default
 *
 * Node identifier: DT_N_S_pin_controller_S_spi4_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi4_default_PATH "/pin-controller/spi4_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi4_default_FULL_NAME "spi4_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi4_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi4_default_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi4_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_spi4_default_FOREACH_NODELABEL(fn) fn(spi4_default)
#define DT_N_S_pin_controller_S_spi4_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi4_default, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi4_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi4_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi4_default_S_group1)
#define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_default_S_group1)
#define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi4_default_S_group1)
#define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_default_S_group1)
#define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi4_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi4_default_ORD 36
#define DT_N_S_pin_controller_S_spi4_default_ORD_STR_SORTABLE 00036

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi4_default_REQUIRES_ORDS \
	19, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi4_default_SUPPORTS_ORDS \
	37, /* /pin-controller/spi4_default/group1 */ \
	118, /* /soc/peripheral@50000000/spi@a000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi4_default_EXISTS 1
#define DT_N_NODELABEL_spi4_default DT_N_S_pin_controller_S_spi4_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi4_default_REG_NUM 0
#define DT_N_S_pin_controller_S_spi4_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi4_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi4_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi4_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi4_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi4_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi4_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi4_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_PATH "/pin-controller/spi4_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi4_default) identifier: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_PARENT DT_N_S_pin_controller_S_spi4_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_ORD 37
#define DT_N_S_pin_controller_S_spi4_default_S_group1_ORD_STR_SORTABLE 00037

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_REQUIRES_ORDS \
	36, /* /pin-controller/spi4_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi4_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels {67108872 /* 0x4000008 */, 83886089 /* 0x5000009 */, 100663306 /* 0x600000a */}
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_0 67108872
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_1 83886089
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_2 100663306
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi4_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi4_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi4_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_spi4_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi4_sleep_PATH "/pin-controller/spi4_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi4_sleep_FULL_NAME "spi4_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi4_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi4_sleep_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi4_sleep_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_NODELABEL(fn) fn(spi4_sleep)
#define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi4_sleep, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi4_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi4_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi4_sleep_ORD 38
#define DT_N_S_pin_controller_S_spi4_sleep_ORD_STR_SORTABLE 00038

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi4_sleep_REQUIRES_ORDS \
	19, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi4_sleep_SUPPORTS_ORDS \
	39, /* /pin-controller/spi4_sleep/group1 */ \
	118, /* /soc/peripheral@50000000/spi@a000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi4_sleep_EXISTS 1
#define DT_N_NODELABEL_spi4_sleep DT_N_S_pin_controller_S_spi4_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi4_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_spi4_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi4_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi4_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi4_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi4_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi4_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi4_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi4_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_PATH "/pin-controller/spi4_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi4_sleep) identifier: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi4_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_ORD 39
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_ORD_STR_SORTABLE 00039

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_REQUIRES_ORDS \
	38, /* /pin-controller/spi4_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels {67108872 /* 0x4000008 */, 83886089 /* 0x5000009 */, 100663306 /* 0x600000a */}
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_0 67108872
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_1 83886089
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_2 100663306
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi4_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /reserved-memory/image@20000000
 *
 * Node identifier: DT_N_S_reserved_memory_S_image_20000000
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_S_image_20000000_PATH "/reserved-memory/image@20000000"

/* Node's name with unit-address: */
#define DT_N_S_reserved_memory_S_image_20000000_FULL_NAME "image@20000000"

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_20000000_PARENT DT_N_S_reserved_memory

/* Node's index in its parent's list of children: */
#define DT_N_S_reserved_memory_S_image_20000000_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_reserved_memory_S_image_20000000_NODELABEL_NUM 1
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_NODELABEL(fn) fn(sram0_image)
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0_image, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_reserved_memory_S_image_20000000_CHILD_NUM 0
#define DT_N_S_reserved_memory_S_image_20000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD(fn) 
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_S_image_20000000_ORD 40
#define DT_N_S_reserved_memory_S_image_20000000_ORD_STR_SORTABLE 00040

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_S_image_20000000_REQUIRES_ORDS \
	14, /* /reserved-memory */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_S_image_20000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_20000000_EXISTS 1
#define DT_N_NODELABEL_sram0_image DT_N_S_reserved_memory_S_image_20000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_reserved_memory_S_image_20000000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_VAL_SIZE 458752 /* 0x70000 */
#define DT_N_S_reserved_memory_S_image_20000000_RANGES_NUM 0
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_RANGE(fn) 
#define DT_N_S_reserved_memory_S_image_20000000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_20000000_IRQ_LEVEL 0
#define DT_N_S_reserved_memory_S_image_20000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_reserved_memory_S_image_20000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_20000000_P_reg {536870912 /* 0x20000000 */, 458752 /* 0x70000 */}
#define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_0 536870912
#define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_1 458752
#define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_reserved_memory_S_image_20000000_P_reg_EXISTS 1

/*
 * Devicetree node: /reserved-memory/image_ns@20040000
 *
 * Node identifier: DT_N_S_reserved_memory_S_image_ns_20040000
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_PATH "/reserved-memory/image_ns@20040000"

/* Node's name with unit-address: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_FULL_NAME "image_ns@20040000"

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_PARENT DT_N_S_reserved_memory

/* Node's index in its parent's list of children: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_NODELABEL_NUM 1
#define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_NODELABEL(fn) fn(sram0_ns)
#define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0_ns, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_reserved_memory_S_image_ns_20040000_CHILD_NUM 0
#define DT_N_S_reserved_memory_S_image_ns_20040000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD(fn) 
#define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_ORD 41
#define DT_N_S_reserved_memory_S_image_ns_20040000_ORD_STR_SORTABLE 00041

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_REQUIRES_ORDS \
	14, /* /reserved-memory */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_EXISTS 1
#define DT_N_NODELABEL_sram0_ns DT_N_S_reserved_memory_S_image_ns_20040000

/* Macros for properties that are special in the specification: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_ns_20040000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_ns_20040000_REG_IDX_0_VAL_ADDRESS 537133056 /* 0x20040000 */
#define DT_N_S_reserved_memory_S_image_ns_20040000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
#define DT_N_S_reserved_memory_S_image_ns_20040000_RANGES_NUM 0
#define DT_N_S_reserved_memory_S_image_ns_20040000_FOREACH_RANGE(fn) 
#define DT_N_S_reserved_memory_S_image_ns_20040000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_ns_20040000_IRQ_LEVEL 0
#define DT_N_S_reserved_memory_S_image_ns_20040000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg {537133056 /* 0x20040000 */, 196608 /* 0x30000 */}
#define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_0 537133056
#define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_1 196608
#define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_reserved_memory_S_image_ns_20040000_P_reg_EXISTS 1

/*
 * Devicetree node: /reserved-memory/image_s@20000000
 *
 * Node identifier: DT_N_S_reserved_memory_S_image_s_20000000
 */

/* Node's full path: */
#define DT_N_S_reserved_memory_S_image_s_20000000_PATH "/reserved-memory/image_s@20000000"

/* Node's name with unit-address: */
#define DT_N_S_reserved_memory_S_image_s_20000000_FULL_NAME "image_s@20000000"

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_s_20000000_PARENT DT_N_S_reserved_memory

/* Node's index in its parent's list of children: */
#define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_reserved_memory_S_image_s_20000000_NODELABEL_NUM 1
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_NODELABEL(fn) fn(sram0_s)
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0_s, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_NUM 0
#define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD(fn) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_S_image_s_20000000_ORD 42
#define DT_N_S_reserved_memory_S_image_s_20000000_ORD_STR_SORTABLE 00042

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_S_image_s_20000000_REQUIRES_ORDS \
	14, /* /reserved-memory */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_S_image_s_20000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_s_20000000_EXISTS 1
#define DT_N_NODELABEL_sram0_s DT_N_S_reserved_memory_S_image_s_20000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_reserved_memory_S_image_s_20000000_RANGES_NUM 0
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_RANGE(fn) 
#define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_LEVEL 0
#define DT_N_S_reserved_memory_S_image_s_20000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_reserved_memory_S_image_s_20000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg {536870912 /* 0x20000000 */, 262144 /* 0x40000 */}
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0 536870912
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1 262144
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/crypto@50844000
 *
 * Node identifier: DT_N_S_soc_S_crypto_50844000
 *
 * Binding (compatible = arm,cryptocell-312):
 *   $ZEPHYR_BASE\dts\bindings\crypto\arm,cryptocell-312.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_crypto_50844000_PATH "/soc/crypto@50844000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_crypto_50844000_FULL_NAME "crypto@50844000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_crypto_50844000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_crypto_50844000_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_crypto_50844000_NODELABEL_NUM 1
#define DT_N_S_soc_S_crypto_50844000_FOREACH_NODELABEL(fn) fn(cryptocell)
#define DT_N_S_soc_S_crypto_50844000_FOREACH_NODELABEL_VARGS(fn, ...) fn(cryptocell, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_crypto_50844000_CHILD_NUM 0
#define DT_N_S_soc_S_crypto_50844000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_crypto_50844000_ORD 43
#define DT_N_S_soc_S_crypto_50844000_ORD_STR_SORTABLE 00043

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_crypto_50844000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_crypto_50844000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_crypto_50844000_EXISTS 1
#define DT_N_INST_0_nordic_cryptocell  DT_N_S_soc_S_crypto_50844000
#define DT_N_INST_0_arm_cryptocell_312 DT_N_S_soc_S_crypto_50844000
#define DT_N_NODELABEL_cryptocell      DT_N_S_soc_S_crypto_50844000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_crypto_50844000_REG_NUM 2
#define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_ADDRESS 1350844416 /* 0x50844000 */
#define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_crypto_50844000_REG_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_REG_IDX_1_VAL_ADDRESS 1350848512 /* 0x50845000 */
#define DT_N_S_soc_S_crypto_50844000_REG_IDX_1_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_crypto_50844000_REG_NAME_wrapper_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_REG_NAME_wrapper_VAL_ADDRESS DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_ADDRESS
#define DT_N_S_soc_S_crypto_50844000_REG_NAME_wrapper_VAL_SIZE DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_SIZE
#define DT_N_S_soc_S_crypto_50844000_REG_NAME_core_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_REG_NAME_core_VAL_ADDRESS DT_N_S_soc_S_crypto_50844000_REG_IDX_1_VAL_ADDRESS
#define DT_N_S_soc_S_crypto_50844000_REG_NAME_core_VAL_SIZE DT_N_S_soc_S_crypto_50844000_REG_IDX_1_VAL_SIZE
#define DT_N_S_soc_S_crypto_50844000_RANGES_NUM 0
#define DT_N_S_soc_S_crypto_50844000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_crypto_50844000_IRQ_NUM 1
#define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_VAL_irq 68
#define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_crypto_50844000_IRQ_LEVEL 1
#define DT_N_S_soc_S_crypto_50844000_COMPAT_MATCHES_nordic_cryptocell 1
#define DT_N_S_soc_S_crypto_50844000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_crypto_50844000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_COMPAT_MODEL_IDX_0 "cryptocell"
#define DT_N_S_soc_S_crypto_50844000_COMPAT_MATCHES_arm_cryptocell_312 1
#define DT_N_S_soc_S_crypto_50844000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_COMPAT_VENDOR_IDX_1 "ARM Ltd."
#define DT_N_S_soc_S_crypto_50844000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_COMPAT_MODEL_IDX_1 "cryptocell-312"
#define DT_N_S_soc_S_crypto_50844000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_crypto_50844000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_crypto_50844000_P_wakeup_source 0
#define DT_N_S_soc_S_crypto_50844000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_crypto_50844000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_status "okay"
#define DT_N_S_soc_S_crypto_50844000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_crypto_50844000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_crypto_50844000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_crypto_50844000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_crypto_50844000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_crypto_50844000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_crypto_50844000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000, status, 0)
#define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000, status, 0)
#define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50844000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50844000_P_status_LEN 1
#define DT_N_S_soc_S_crypto_50844000_P_status_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_compatible {"nordic,cryptocell", "arm,cryptocell-312"}
#define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0 "nordic,cryptocell"
#define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_STRING_UNQUOTED nordic,cryptocell
#define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_STRING_TOKEN nordic_cryptocell
#define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_CRYPTOCELL
#define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_1 "arm,cryptocell-312"
#define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_1_STRING_UNQUOTED arm,cryptocell-312
#define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_1_STRING_TOKEN arm_cryptocell_312
#define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_1_STRING_UPPER_TOKEN ARM_CRYPTOCELL_312
#define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0) \
	fn(DT_N_S_soc_S_crypto_50844000, compatible, 1)
#define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50844000, compatible, 1)
#define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_crypto_50844000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50844000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50844000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50844000_P_compatible_LEN 2
#define DT_N_S_soc_S_crypto_50844000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_reg {1350844416 /* 0x50844000 */, 4096 /* 0x1000 */, 1350848512 /* 0x50845000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_0 1350844416
#define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_2 1350848512
#define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_2_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_3 4096
#define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_3_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_reg_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_reg_names {"wrapper", "core"}
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_0 "wrapper"
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_0_STRING_UNQUOTED wrapper
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_0_STRING_TOKEN wrapper
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_0_STRING_UPPER_TOKEN WRAPPER
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_1 "core"
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_1_STRING_UNQUOTED core
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_1_STRING_TOKEN core
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_1_STRING_UPPER_TOKEN CORE
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_50844000, reg_names, 0) \
	fn(DT_N_S_soc_S_crypto_50844000, reg_names, 1)
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_50844000, reg_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50844000, reg_names, 1)
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, reg_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_crypto_50844000, reg_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_50844000, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_50844000, reg_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_LEN 2
#define DT_N_S_soc_S_crypto_50844000_P_reg_names_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_interrupts {68 /* 0x44 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_crypto_50844000_P_interrupts_IDX_0 68
#define DT_N_S_soc_S_crypto_50844000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_crypto_50844000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_crypto_50844000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/ficr@ff0000
 *
 * Node identifier: DT_N_S_soc_S_ficr_ff0000
 *
 * Binding (compatible = nordic,nrf-ficr):
 *   $ZEPHYR_BASE\dts\bindings\misc\nordic,nrf-ficr.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ficr_ff0000_PATH "/soc/ficr@ff0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ficr_ff0000_FULL_NAME "ficr@ff0000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ficr_ff0000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ficr_ff0000_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_ficr_ff0000_NODELABEL_NUM 1
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_NODELABEL(fn) fn(ficr)
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(ficr, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ficr_ff0000_CHILD_NUM 0
#define DT_N_S_soc_S_ficr_ff0000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ficr_ff0000_ORD 44
#define DT_N_S_soc_S_ficr_ff0000_ORD_STR_SORTABLE 00044

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ficr_ff0000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ficr_ff0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ficr_ff0000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ficr DT_N_S_soc_S_ficr_ff0000
#define DT_N_NODELABEL_ficr         DT_N_S_soc_S_ficr_ff0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ficr_ff0000_REG_NUM 1
#define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_ADDRESS 16711680 /* 0xff0000 */
#define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ficr_ff0000_RANGES_NUM 0
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ficr_ff0000_IRQ_NUM 0
#define DT_N_S_soc_S_ficr_ff0000_IRQ_LEVEL 0
#define DT_N_S_soc_S_ficr_ff0000_COMPAT_MATCHES_nordic_nrf_ficr 1
#define DT_N_S_soc_S_ficr_ff0000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_ficr_ff0000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_COMPAT_MODEL_IDX_0 "nrf-ficr"
#define DT_N_S_soc_S_ficr_ff0000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ficr_ff0000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ficr_ff0000_P_wakeup_source 0
#define DT_N_S_soc_S_ficr_ff0000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ficr_ff0000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_status "okay"
#define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_ficr_ff0000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ficr_ff0000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_ficr_ff0000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, status, 0)
#define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, status, 0)
#define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ff0000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ff0000_P_status_LEN 1
#define DT_N_S_soc_S_ficr_ff0000_P_status_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_compatible {"nordic,nrf-ficr"}
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0 "nordic,nrf-ficr"
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ficr
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ficr
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_FICR
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0)
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0)
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_ff0000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_LEN 1
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_reg {16711680 /* 0xff0000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_0 16711680
#define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ficr_ff0000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/gpiote@4002f000
 *
 * Node identifier: DT_N_S_soc_S_gpiote_4002f000
 *
 * Binding (compatible = nordic,nrf-gpiote):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpiote.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_gpiote_4002f000_PATH "/soc/gpiote@4002f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_gpiote_4002f000_FULL_NAME "gpiote@4002f000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpiote_4002f000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_gpiote_4002f000_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_gpiote_4002f000_NODELABEL_NUM 1
#define DT_N_S_soc_S_gpiote_4002f000_FOREACH_NODELABEL(fn) fn(gpiote1)
#define DT_N_S_soc_S_gpiote_4002f000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiote1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_gpiote_4002f000_CHILD_NUM 0
#define DT_N_S_soc_S_gpiote_4002f000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpiote_4002f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpiote_4002f000_ORD 45
#define DT_N_S_soc_S_gpiote_4002f000_ORD_STR_SORTABLE 00045

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpiote_4002f000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpiote_4002f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpiote_4002f000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_4002f000
#define DT_N_NODELABEL_gpiote1        DT_N_S_soc_S_gpiote_4002f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_gpiote_4002f000_REG_NUM 1
#define DT_N_S_soc_S_gpiote_4002f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_REG_IDX_0_VAL_ADDRESS 1073934336 /* 0x4002f000 */
#define DT_N_S_soc_S_gpiote_4002f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_gpiote_4002f000_RANGES_NUM 0
#define DT_N_S_soc_S_gpiote_4002f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_gpiote_4002f000_IRQ_NUM 1
#define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_irq 47
#define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_priority 5
#define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_gpiote_4002f000_IRQ_LEVEL 1
#define DT_N_S_soc_S_gpiote_4002f000_COMPAT_MATCHES_nordic_nrf_gpiote 1
#define DT_N_S_soc_S_gpiote_4002f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_gpiote_4002f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_COMPAT_MODEL_IDX_0 "nrf-gpiote"
#define DT_N_S_soc_S_gpiote_4002f000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_gpiote_4002f000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_gpiote_4002f000_P_wakeup_source 0
#define DT_N_S_soc_S_gpiote_4002f000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_gpiote_4002f000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_status "disabled"
#define DT_N_S_soc_S_gpiote_4002f000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_gpiote_4002f000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_gpiote_4002f000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_gpiote_4002f000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_gpiote_4002f000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_gpiote_4002f000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_gpiote_4002f000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0)
#define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0)
#define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_4002f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_4002f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_4002f000_P_status_LEN 1
#define DT_N_S_soc_S_gpiote_4002f000_P_status_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible {"nordic,nrf-gpiote"}
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0 "nordic,nrf-gpiote"
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpiote
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0)
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0)
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_4002f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible_LEN 1
#define DT_N_S_soc_S_gpiote_4002f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_reg {1073934336 /* 0x4002f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_0 1073934336
#define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_gpiote_4002f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_interrupts {47 /* 0x2f */, 5 /* 0x5 */}
#define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_0 47
#define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_1 5
#define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_gpiote_4002f000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_gpiote_4002f000_P_instance 1
#define DT_N_S_soc_S_gpiote_4002f000_P_instance_EXISTS 1

/*
 * Devicetree node: /soc/memory@20000000
 *
 * Node identifier: DT_N_S_soc_S_memory_20000000
 *
 * Binding (compatible = mmio-sram):
 *   $ZEPHYR_BASE\dts\bindings\sram\mmio-sram.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_20000000_PATH "/soc/memory@20000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_20000000_FULL_NAME "memory@20000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_20000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_20000000_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_20000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_20000000_FOREACH_NODELABEL(fn) fn(sram0)
#define DT_N_S_soc_S_memory_20000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_20000000_CHILD_NUM 0
#define DT_N_S_soc_S_memory_20000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_20000000_ORD 46
#define DT_N_S_soc_S_memory_20000000_ORD_STR_SORTABLE 00046

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_20000000_EXISTS 1
#define DT_N_INST_0_mmio_sram DT_N_S_soc_S_memory_20000000
#define DT_N_NODELABEL_sram0  DT_N_S_soc_S_memory_20000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_20000000_REG_NUM 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE 524288 /* 0x80000 */
#define DT_N_S_soc_S_memory_20000000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_20000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_20000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_20000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_20000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_20000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_20000000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_20000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible {"mmio-sram"}
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0 "mmio-sram"
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UNQUOTED mmio-sram
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_TOKEN mmio_sram
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_20000000, compatible, 0)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_20000000, compatible, 0)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 524288 /* 0x80000 */}
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0 536870912
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1 524288
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_20000000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/spu@50003000
 *
 * Node identifier: DT_N_S_soc_S_spu_50003000
 *
 * Binding (compatible = nordic,nrf-spu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-spu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spu_50003000_PATH "/soc/spu@50003000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spu_50003000_FULL_NAME "spu@50003000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spu_50003000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spu_50003000_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spu_50003000_NODELABEL_NUM 1
#define DT_N_S_soc_S_spu_50003000_FOREACH_NODELABEL(fn) fn(spu)
#define DT_N_S_soc_S_spu_50003000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spu, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spu_50003000_CHILD_NUM 0
#define DT_N_S_soc_S_spu_50003000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spu_50003000_ORD 47
#define DT_N_S_soc_S_spu_50003000_ORD_STR_SORTABLE 00047

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spu_50003000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spu_50003000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spu_50003000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_spu DT_N_S_soc_S_spu_50003000
#define DT_N_NODELABEL_spu         DT_N_S_soc_S_spu_50003000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spu_50003000_REG_NUM 1
#define DT_N_S_soc_S_spu_50003000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_ADDRESS 1342189568 /* 0x50003000 */
#define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_spu_50003000_RANGES_NUM 0
#define DT_N_S_soc_S_spu_50003000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spu_50003000_IRQ_NUM 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq 3
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spu_50003000_IRQ_LEVEL 1
#define DT_N_S_soc_S_spu_50003000_COMPAT_MATCHES_nordic_nrf_spu 1
#define DT_N_S_soc_S_spu_50003000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_spu_50003000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_COMPAT_MODEL_IDX_0 "nrf-spu"
#define DT_N_S_soc_S_spu_50003000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spu_50003000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_spu_50003000_P_wakeup_source 0
#define DT_N_S_soc_S_spu_50003000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spu_50003000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_status "okay"
#define DT_N_S_soc_S_spu_50003000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_spu_50003000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_spu_50003000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spu_50003000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_spu_50003000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_spu_50003000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_spu_50003000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, status, 0)
#define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, status, 0)
#define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_status_LEN 1
#define DT_N_S_soc_S_spu_50003000_P_status_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_compatible {"nordic,nrf-spu"}
#define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0 "nordic,nrf-spu"
#define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spu
#define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spu
#define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPU
#define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spu_50003000, compatible, 0)
#define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spu_50003000, compatible, 0)
#define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spu_50003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spu_50003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spu_50003000_P_compatible_LEN 1
#define DT_N_S_soc_S_spu_50003000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_reg {1342189568 /* 0x50003000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_spu_50003000_P_reg_IDX_0 1342189568
#define DT_N_S_soc_S_spu_50003000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_spu_50003000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_interrupts {3 /* 0x3 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_0 3
#define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spu_50003000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/timer@e000e010
 *
 * Node identifier: DT_N_S_soc_S_timer_e000e010
 *
 * Binding (compatible = arm,armv8m-systick):
 *   $ZEPHYR_BASE\dts\bindings\timer\arm,armv8m-systick.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timer_e000e010_PATH "/soc/timer@e000e010"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME "timer@e000e010"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timer_e000e010_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timer_e000e010_NODELABEL_NUM 1
#define DT_N_S_soc_S_timer_e000e010_FOREACH_NODELABEL(fn) fn(systick)
#define DT_N_S_soc_S_timer_e000e010_FOREACH_NODELABEL_VARGS(fn, ...) fn(systick, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timer_e000e010_CHILD_NUM 0
#define DT_N_S_soc_S_timer_e000e010_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_e000e010_ORD 48
#define DT_N_S_soc_S_timer_e000e010_ORD_STR_SORTABLE 00048

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_e000e010_EXISTS 1
#define DT_N_INST_0_arm_armv8m_systick DT_N_S_soc_S_timer_e000e010
#define DT_N_NODELABEL_systick         DT_N_S_soc_S_timer_e000e010

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timer_e000e010_REG_NUM 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */
#define DT_N_S_soc_S_timer_e000e010_RANGES_NUM 0
#define DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0
#define DT_N_S_soc_S_timer_e000e010_IRQ_LEVEL 0
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0 "armv8m-systick"
#define DT_N_S_soc_S_timer_e000e010_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source 0
#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_status "disabled"
#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_e000e010_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timer_e000e010_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, status, 0)
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, status, 0)
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_status_LEN 1
#define DT_N_S_soc_S_timer_e000e010_P_status_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv8m-systick"}
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv8m-systick"
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UNQUOTED arm,armv8m-systick
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_TOKEN arm_armv8m_systick
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV8M_SYSTICK
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/uicr@ff8000
 *
 * Node identifier: DT_N_S_soc_S_uicr_ff8000
 *
 * Binding (compatible = nordic,nrf-uicr):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-uicr.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_uicr_ff8000_PATH "/soc/uicr@ff8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_uicr_ff8000_FULL_NAME "uicr@ff8000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uicr_ff8000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_uicr_ff8000_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_uicr_ff8000_NODELABEL_NUM 1
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_NODELABEL(fn) fn(uicr)
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uicr, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_uicr_ff8000_CHILD_NUM 0
#define DT_N_S_soc_S_uicr_ff8000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_uicr_ff8000_ORD 49
#define DT_N_S_soc_S_uicr_ff8000_ORD_STR_SORTABLE 00049

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_uicr_ff8000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_uicr_ff8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uicr_ff8000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_uicr DT_N_S_soc_S_uicr_ff8000
#define DT_N_NODELABEL_uicr         DT_N_S_soc_S_uicr_ff8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_uicr_ff8000_REG_NUM 1
#define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_ADDRESS 16744448 /* 0xff8000 */
#define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uicr_ff8000_RANGES_NUM 0
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_uicr_ff8000_IRQ_NUM 0
#define DT_N_S_soc_S_uicr_ff8000_IRQ_LEVEL 0
#define DT_N_S_soc_S_uicr_ff8000_COMPAT_MATCHES_nordic_nrf_uicr 1
#define DT_N_S_soc_S_uicr_ff8000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_uicr_ff8000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_COMPAT_MODEL_IDX_0 "nrf-uicr"
#define DT_N_S_soc_S_uicr_ff8000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_uicr_ff8000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_uicr_ff8000_P_wakeup_source 0
#define DT_N_S_soc_S_uicr_ff8000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_uicr_ff8000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_status "okay"
#define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_uicr_ff8000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_uicr_ff8000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_uicr_ff8000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, status, 0)
#define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, status, 0)
#define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_ff8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_ff8000_P_status_LEN 1
#define DT_N_S_soc_S_uicr_ff8000_P_status_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_compatible {"nordic,nrf-uicr"}
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0 "nordic,nrf-uicr"
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uicr
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uicr
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UICR
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0)
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0)
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_ff8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_LEN 1
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_reg {16744448 /* 0xff8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_0 16744448
#define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_uicr_ff8000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_nfct_pins_as_gpios 1
#define DT_N_S_soc_S_uicr_ff8000_P_nfct_pins_as_gpios_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_gpio_as_nreset 0
#define DT_N_S_soc_S_uicr_ff8000_P_gpio_as_nreset_EXISTS 1

/*
 * Devicetree node: /soc/nordic_ram-flash-controller@0
 *
 * Node identifier: DT_N_S_soc_S_nordic_ram_flash_controller_0
 *
 * Binding (compatible = zephyr,sim-flash):
 *   $ZEPHYR_BASE\dts\bindings\flash_controller\zephyr,sim-flash.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_PATH "/soc/nordic_ram-flash-controller@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FULL_NAME "nordic_ram-flash-controller@0"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FOREACH_NODELABEL(fn) fn(nordic_ram_flash_controller)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(nordic_ram_flash_controller, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_CHILD_NUM 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_ORD 50
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_ORD_STR_SORTABLE 00050

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_SUPPORTS_ORDS \
	51, /* /soc/nordic_ram-flash-controller@0/flash_sim@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_EXISTS 1
#define DT_N_INST_0_zephyr_sim_flash               DT_N_S_soc_S_nordic_ram_flash_controller_0
#define DT_N_NODELABEL_nordic_ram_flash_controller DT_N_S_soc_S_nordic_ram_flash_controller_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_REG_NUM 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_REG_IDX_0_VAL_SIZE 40960 /* 0xa000 */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_RANGES_NUM 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_IRQ_NUM 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_COMPAT_MATCHES_zephyr_sim_flash 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding"
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_COMPAT_MODEL_IDX_0 "sim-flash"
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_wakeup_source 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible {"zephyr,sim-flash"}
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible_IDX_0 "zephyr,sim-flash"
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible_IDX_0_STRING_UNQUOTED zephyr,sim-flash
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible_IDX_0_STRING_TOKEN zephyr_sim_flash
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_SIM_FLASH
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0, compatible, 0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0, compatible, 0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible_LEN 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_reg {0 /* 0x0 */, 40960 /* 0xa000 */}
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_reg_IDX_1 40960
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_erase_value 255
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_erase_value_ENUM_IDX 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_erase_value_ENUM_VAL_255_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_P_erase_value_EXISTS 1

/*
 * Devicetree node: /soc/nordic_ram-flash-controller@0/flash_sim@0
 *
 * Node identifier: DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0
 *
 * Binding (compatible = soc-nv-flash):
 *   $ZEPHYR_BASE\dts\bindings\mtd\soc-nv-flash.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_PATH "/soc/nordic_ram-flash-controller@0/flash_sim@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FULL_NAME "flash_sim@0"

/* Node parent (/soc/nordic_ram-flash-controller@0) identifier: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_PARENT DT_N_S_soc_S_nordic_ram_flash_controller_0

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FOREACH_NODELABEL(fn) fn(flash_sim0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(flash_sim0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_CHILD_NUM 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_ORD 51
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_ORD_STR_SORTABLE 00051

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_REQUIRES_ORDS \
	50, /* /soc/nordic_ram-flash-controller@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_SUPPORTS_ORDS \
	52, /* /soc/nordic_ram-flash-controller@0/flash_sim@0/partitions */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_EXISTS 1
#define DT_N_INST_1_soc_nv_flash  DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0
#define DT_N_NODELABEL_flash_sim0 DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_REG_NUM 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_RANGES_NUM 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_IRQ_NUM 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_COMPAT_MATCHES_soc_nv_flash 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_wakeup_source 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status "okay"
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, status, 0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, status, 0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_LEN 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_status_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible {"soc-nv-flash"}
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible_IDX_0 "soc-nv-flash"
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible_IDX_0_STRING_UNQUOTED soc-nv-flash
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible_IDX_0_STRING_TOKEN soc_nv_flash
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SOC_NV_FLASH
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, compatible, 0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, compatible, 0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible_LEN 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_reg {0 /* 0x0 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_reg_IDX_1 262144
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_erase_block_size 4096
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_erase_block_size_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_write_block_size 4
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_P_write_block_size_EXISTS 1

/*
 * Devicetree node: /soc/nordic_ram-flash-controller@0/flash_sim@0/partitions
 *
 * Node identifier: DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\fixed-partitions.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_PATH "/soc/nordic_ram-flash-controller@0/flash_sim@0/partitions"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FULL_NAME "partitions"

/* Node parent (/soc/nordic_ram-flash-controller@0/flash_sim@0) identifier: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_PARENT DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_NODELABEL_NUM 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_CHILD_NUM 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_ORD 52
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_ORD_STR_SORTABLE 00052

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_REQUIRES_ORDS \
	51, /* /soc/nordic_ram-flash-controller@0/flash_sim@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_SUPPORTS_ORDS \
	53, /* /soc/nordic_ram-flash-controller@0/flash_sim@0/partitions/partition@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_EXISTS 1
#define DT_N_INST_1_fixed_partitions DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_REG_NUM 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_RANGES_NUM 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_IRQ_NUM 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_IRQ_LEVEL 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /soc/nordic_ram-flash-controller@0/flash_sim@0/partitions/partition@0
 *
 * Node identifier: DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_PATH "/soc/nordic_ram-flash-controller@0/flash_sim@0/partitions/partition@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FULL_NAME "partition@0"

/* Node parent (/soc/nordic_ram-flash-controller@0/flash_sim@0/partitions) identifier: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FOREACH_NODELABEL(fn) fn(slot2_partition)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot2_partition, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_CHILD_NUM 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_ORD 53
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_ORD_STR_SORTABLE 00053

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_REQUIRES_ORDS \
	52, /* /soc/nordic_ram-flash-controller@0/flash_sim@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_EXISTS 1
#define DT_N_NODELABEL_slot2_partition DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 40960 /* 0xa000 */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_RANGES_NUM 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_PARTITION_ID 0

/* Generic property macros: */
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label "image-2"
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label_STRING_UNQUOTED image-2
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label_STRING_TOKEN image_2
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN IMAGE_2
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label_IDX_0 "image-2"
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label_LEN 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_read_only 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 40960 /* 0xa000 */}
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_reg_IDX_1 40960
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/adc@e000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_adc_e000
 *
 * Binding (compatible = nordic,nrf-saadc):
 *   $ZEPHYR_BASE\dts\bindings\adc\nordic,nrf-saadc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PATH "/soc/peripheral@50000000/adc@e000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FULL_NAME "adc@e000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_CHILD_IDX 20

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_NODELABEL(fn) fn(adc)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_ORD 54
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_ORD_STR_SORTABLE 00054

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_saadc DT_N_S_soc_S_peripheral_50000000_S_adc_e000
#define DT_N_NODELABEL_adc           DT_N_S_soc_S_peripheral_50000000_S_adc_e000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_ADDRESS 1342234624 /* 0x5000e000 */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq 14
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MATCHES_nordic_nrf_saadc 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MODEL_IDX_0 "nrf-saadc"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible {"nordic,nrf-saadc"}
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0 "nordic,nrf-saadc"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-saadc
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_saadc
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SAADC
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg {57344 /* 0xe000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_0 57344
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts {14 /* 0xe */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_0 14
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/clock@5000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_clock_5000
 *
 * Binding (compatible = nordic,nrf-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\nordic,nrf-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PATH "/soc/peripheral@50000000/clock@5000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FULL_NAME "clock@5000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_NODELABEL(fn) fn(clock)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_NODELABEL_VARGS(fn, ...) fn(clock, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_ORD 55
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_ORD_STR_SORTABLE 00055

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_clock DT_N_S_soc_S_peripheral_50000000_S_clock_5000
#define DT_N_NODELABEL_clock         DT_N_S_soc_S_peripheral_50000000_S_clock_5000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq 5
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MATCHES_nordic_nrf_clock 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MODEL_IDX_0 "nrf-clock"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible {"nordic,nrf-clock"}
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0 "nordic,nrf-clock"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-clock
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_clock
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CLOCK
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_0 20480
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_0 5
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/comparator@1a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000
 *
 * Binding (compatible = nordic,nrf-comp):
 *   $ZEPHYR_BASE\dts\bindings\comparator\nordic,nrf-comp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_PATH "/soc/peripheral@50000000/comparator@1a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FULL_NAME "comparator@1a000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_CHILD_IDX 29

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_NODELABEL(fn) fn(comp)
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(comp, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_ORD 56
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_ORD_STR_SORTABLE 00056

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_comp DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000
#define DT_N_NODELABEL_comp         DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_IDX_0_VAL_ADDRESS 1342283776 /* 0x5001a000 */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_irq 26
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_MATCHES_nordic_nrf_comp 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_COMPAT_MODEL_IDX_0 "nrf-comp"
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible {"nordic,nrf-comp"}
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0 "nordic,nrf-comp"
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-comp
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_comp
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_COMP
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg {106496 /* 0x1a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_0 106496
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts {26 /* 0x1a */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_0 26
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_enable_hyst 0
#define DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000_P_enable_hyst_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/ctrlap@6000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000
 *
 * Binding (compatible = nordic,nrf-ctrlapperi):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-ctrlapperi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_PATH "/soc/peripheral@50000000/ctrlap@6000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FULL_NAME "ctrlap@6000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_NODELABEL(fn) fn(ctrlap)
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_NODELABEL_VARGS(fn, ...) fn(ctrlap, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_ORD 57
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_ORD_STR_SORTABLE 00057

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ctrlapperi DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000
#define DT_N_NODELABEL_ctrlap             DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_IDX_0_VAL_ADDRESS 1342201856 /* 0x50006000 */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_MATCHES_nordic_nrf_ctrlapperi 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_COMPAT_MODEL_IDX_0 "nrf-ctrlapperi"
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible {"nordic,nrf-ctrlapperi"}
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0 "nordic,nrf-ctrlapperi"
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ctrlapperi
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ctrlapperi
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CTRLAPPERI
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg {24576 /* 0x6000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_0 24576
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/dcnf@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_dcnf_0
 *
 * Binding (compatible = nordic,nrf-dcnf):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-dcnf.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_PATH "/soc/peripheral@50000000/dcnf@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FULL_NAME "dcnf@0"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_NODELABEL(fn) fn(dcnf)
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcnf, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_ORD 58
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_ORD_STR_SORTABLE 00058

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_EXISTS 1
#define DT_N_INST_0_nordic_nrf_dcnf DT_N_S_soc_S_peripheral_50000000_S_dcnf_0
#define DT_N_NODELABEL_dcnf         DT_N_S_soc_S_peripheral_50000000_S_dcnf_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_IDX_0_VAL_ADDRESS 1342177280 /* 0x50000000 */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_MATCHES_nordic_nrf_dcnf 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_COMPAT_MODEL_IDX_0 "nrf-dcnf"
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible {"nordic,nrf-dcnf"}
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0 "nordic,nrf-dcnf"
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-dcnf
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dcnf
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DCNF
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg {0 /* 0x0 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_dcnf_0_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/dppic@17000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_dppic_17000
 *
 * Binding (compatible = nordic,nrf-dppic):
 *   $ZEPHYR_BASE\dts\bindings\misc\nordic,nrf-dppic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PATH "/soc/peripheral@50000000/dppic@17000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FULL_NAME "dppic@17000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_CHILD_IDX 26

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_NODELABEL_NUM 2
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_NODELABEL(fn) fn(dppic0) fn(dppic)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dppic0, __VA_ARGS__) fn(dppic, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_ORD 59
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_ORD_STR_SORTABLE 00059

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_dppic DT_N_S_soc_S_peripheral_50000000_S_dppic_17000
#define DT_N_NODELABEL_dppic0        DT_N_S_soc_S_peripheral_50000000_S_dppic_17000
#define DT_N_NODELABEL_dppic         DT_N_S_soc_S_peripheral_50000000_S_dppic_17000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_ADDRESS 1342271488 /* 0x50017000 */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MATCHES_nordic_nrf_dppic 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MODEL_IDX_0 "nrf-dppic"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible {"nordic,nrf-dppic"}
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0 "nordic,nrf-dppic"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-dppic
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_dppic
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_DPPIC
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg {94208 /* 0x17000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_0 94208
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1b000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PATH "/soc/peripheral@50000000/egu@1b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FULL_NAME "egu@1b000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_CHILD_IDX 30

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_NODELABEL(fn) fn(egu0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_ORD 60
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_ORD_STR_SORTABLE 00060

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1b000
#define DT_N_NODELABEL_egu0        DT_N_S_soc_S_peripheral_50000000_S_egu_1b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_ADDRESS 1342287872 /* 0x5001b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq 27
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg {110592 /* 0x1b000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_0 110592
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts {27 /* 0x1b */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_0 27
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1c000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1c000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PATH "/soc/peripheral@50000000/egu@1c000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FULL_NAME "egu@1c000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_CHILD_IDX 31

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_NODELABEL(fn) fn(egu1)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_ORD 61
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_ORD_STR_SORTABLE 00061

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1c000
#define DT_N_NODELABEL_egu1        DT_N_S_soc_S_peripheral_50000000_S_egu_1c000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_ADDRESS 1342291968 /* 0x5001c000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq 28
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg {114688 /* 0x1c000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_0 114688
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts {28 /* 0x1c */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_0 28
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1d000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1d000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PATH "/soc/peripheral@50000000/egu@1d000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FULL_NAME "egu@1d000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_CHILD_IDX 32

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_NODELABEL(fn) fn(egu2)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu2, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_ORD 62
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_ORD_STR_SORTABLE 00062

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1d000
#define DT_N_NODELABEL_egu2        DT_N_S_soc_S_peripheral_50000000_S_egu_1d000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_ADDRESS 1342296064 /* 0x5001d000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq 29
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg {118784 /* 0x1d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_0 118784
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts {29 /* 0x1d */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_0 29
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1e000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1e000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PATH "/soc/peripheral@50000000/egu@1e000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FULL_NAME "egu@1e000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_CHILD_IDX 33

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_NODELABEL(fn) fn(egu3)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu3, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_ORD 63
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_ORD_STR_SORTABLE 00063

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1e000
#define DT_N_NODELABEL_egu3        DT_N_S_soc_S_peripheral_50000000_S_egu_1e000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_ADDRESS 1342300160 /* 0x5001e000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq 30
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg {122880 /* 0x1e000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_0 122880
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts {30 /* 0x1e */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_0 30
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1f000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1f000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PATH "/soc/peripheral@50000000/egu@1f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FULL_NAME "egu@1f000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_CHILD_IDX 34

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_NODELABEL(fn) fn(egu4)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu4, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_ORD 64
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_ORD_STR_SORTABLE 00064

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_EXISTS 1
#define DT_N_INST_4_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1f000
#define DT_N_NODELABEL_egu4        DT_N_S_soc_S_peripheral_50000000_S_egu_1f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_ADDRESS 1342304256 /* 0x5001f000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq 31
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg {126976 /* 0x1f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_0 126976
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts {31 /* 0x1f */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_0 31
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@20000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_20000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PATH "/soc/peripheral@50000000/egu@20000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FULL_NAME "egu@20000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_CHILD_IDX 35

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_NODELABEL(fn) fn(egu5)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_NODELABEL_VARGS(fn, ...) fn(egu5, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_ORD 65
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_ORD_STR_SORTABLE 00065

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_EXISTS 1
#define DT_N_INST_5_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_20000
#define DT_N_NODELABEL_egu5        DT_N_S_soc_S_peripheral_50000000_S_egu_20000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_ADDRESS 1342308352 /* 0x50020000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq 32
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg {131072 /* 0x20000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_0 131072
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts {32 /* 0x20 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_0 32
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/gpiote@5000d000
 *
 * Node identifier: DT_N_S_soc_S_gpiote_5000d000
 *
 * Binding (compatible = nordic,nrf-gpiote):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpiote.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_gpiote_5000d000_PATH "/soc/gpiote@5000d000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_gpiote_5000d000_FULL_NAME "gpiote@5000d000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpiote_5000d000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_gpiote_5000d000_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_gpiote_5000d000_NODELABEL_NUM 2
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_NODELABEL(fn) fn(gpiote) fn(gpiote0)
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiote, __VA_ARGS__) fn(gpiote0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_gpiote_5000d000_CHILD_NUM 0
#define DT_N_S_soc_S_gpiote_5000d000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpiote_5000d000_ORD 66
#define DT_N_S_soc_S_gpiote_5000d000_ORD_STR_SORTABLE 00066

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpiote_5000d000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpiote_5000d000_SUPPORTS_ORDS \
	67, /* /soc/peripheral@50000000/gpio@842800 */ \
	117, /* /soc/peripheral@50000000/gpio@842500 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpiote_5000d000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_5000d000
#define DT_N_NODELABEL_gpiote         DT_N_S_soc_S_gpiote_5000d000
#define DT_N_NODELABEL_gpiote0        DT_N_S_soc_S_gpiote_5000d000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_gpiote_5000d000_REG_NUM 1
#define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_ADDRESS 1342230528 /* 0x5000d000 */
#define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_gpiote_5000d000_RANGES_NUM 0
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_NUM 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq 13
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority 5
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_LEVEL 1
#define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MATCHES_nordic_nrf_gpiote 1
#define DT_N_S_soc_S_gpiote_5000d000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MODEL_IDX_0 "nrf-gpiote"
#define DT_N_S_soc_S_gpiote_5000d000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_gpiote_5000d000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_gpiote_5000d000_P_wakeup_source 0
#define DT_N_S_soc_S_gpiote_5000d000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_status "okay"
#define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_gpiote_5000d000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpiote_5000d000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_gpiote_5000d000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0)
#define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0)
#define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_status_LEN 1
#define DT_N_S_soc_S_gpiote_5000d000_P_status_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible {"nordic,nrf-gpiote"}
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0 "nordic,nrf-gpiote"
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpiote
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0)
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0)
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_5000d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_LEN 1
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_reg {1342230528 /* 0x5000d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_0 1342230528
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts {13 /* 0xd */, 5 /* 0x5 */}
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_0 13
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_1 5
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_gpiote_5000d000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_instance 0
#define DT_N_S_soc_S_gpiote_5000d000_P_instance_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/gpio@842800
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_PATH "/soc/peripheral@50000000/gpio@842800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FULL_NAME "gpio@842800"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_CHILD_IDX 54

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_NODELABEL(fn) fn(gpio1)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpio1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_ORD 67
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_ORD_STR_SORTABLE 00067

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */ \
	66, /* /soc/gpiote@5000d000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_EXISTS 1
#define DT_N_INST_1_nordic_nrf_gpio DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
#define DT_N_NODELABEL_gpio1        DT_N_S_soc_S_peripheral_50000000_S_gpio_842800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_VAL_ADDRESS 1350838272 /* 0x50842800 */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_MODEL_IDX_0 "nrf-gpio"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpio_controller 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_ngpios 16
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg {8660992 /* 0x842800 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_0 8660992
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_1 768
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance DT_N_S_soc_S_gpiote_5000d000
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_IDX_0 DT_N_S_soc_S_gpiote_5000d000
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_IDX_0_PH DT_N_S_soc_S_gpiote_5000d000
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, gpiote_instance, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, gpiote_instance, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpiote_instance_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_port 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_port_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_8000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PATH "/soc/peripheral@50000000/i2c@8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FULL_NAME "i2c@8000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_NODELABEL(fn) fn(i2c0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_ORD 68
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_ORD_STR_SORTABLE 00068

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_8000
#define DT_N_NODELABEL_i2c0         DT_N_S_soc_S_peripheral_50000000_S_i2c_8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_pm_device_runtime_auto 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_sq_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_cq_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_zephyr_flash_buf_max_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@9000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PATH "/soc/peripheral@50000000/i2c@9000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FULL_NAME "i2c@9000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_NODELABEL(fn) fn(i2c1)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_ORD 69
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_ORD_STR_SORTABLE 00069

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
#define DT_N_NODELABEL_i2c1         DT_N_S_soc_S_peripheral_50000000_S_i2c_9000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_pm_device_runtime_auto 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_sq_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_cq_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_zephyr_flash_buf_max_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_b000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PATH "/soc/peripheral@50000000/i2c@b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FULL_NAME "i2c@b000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_CHILD_IDX 14

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_NODELABEL(fn) fn(i2c2)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c2, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_ORD 70
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_ORD_STR_SORTABLE 00070

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_b000
#define DT_N_NODELABEL_i2c2         DT_N_S_soc_S_peripheral_50000000_S_i2c_b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_pm_device_runtime_auto 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_sq_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_cq_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_zephyr_flash_buf_max_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@c000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_c000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_PATH "/soc/peripheral@50000000/i2c@c000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FULL_NAME "i2c@c000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_CHILD_IDX 17

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_NODELABEL(fn) fn(i2c3)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c3, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_ORD 71
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_ORD_STR_SORTABLE 00071

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_c000
#define DT_N_NODELABEL_i2c3         DT_N_S_soc_S_peripheral_50000000_S_i2c_c000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_irq 12
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_COMPAT_MODEL_IDX_0 "nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_pm_device_runtime_auto 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twim
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWIM
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_0 49152
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_0 12
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_sq_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_cq_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_concat_buf_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_concat_buf_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_flash_buf_max_size 16
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_zephyr_flash_buf_max_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2s@28000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_i2s_28000
 *
 * Binding (compatible = nordic,nrf-i2s):
 *   $ZEPHYR_BASE\dts\bindings\i2s\nordic,nrf-i2s.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PATH "/soc/peripheral@50000000/i2s@28000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FULL_NAME "i2s@28000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_CHILD_IDX 41

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_NODELABEL(fn) fn(i2s0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2s0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_ORD 72
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_ORD_STR_SORTABLE 00072

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_i2s DT_N_S_soc_S_peripheral_50000000_S_i2s_28000
#define DT_N_NODELABEL_i2s0        DT_N_S_soc_S_peripheral_50000000_S_i2s_28000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_ADDRESS 1342341120 /* 0x50028000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq 40
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MATCHES_nordic_nrf_i2s 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MODEL_IDX_0 "nrf-i2s"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible {"nordic,nrf-i2s"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0 "nordic,nrf-i2s"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-i2s
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_i2s
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_I2S
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg {163840 /* 0x28000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_0 163840
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts {40 /* 0x28 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_0 40
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_IDX_0 "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_VAL_PCLK32M_HFXO_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_clock_source_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/ieee802154
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_ieee802154
 *
 * Binding (compatible = nordic,nrf-ieee802154):
 *   $ZEPHYR_BASE\dts\bindings\ieee802154\nordic,nrf-ieee802154.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_PATH "/soc/peripheral@50000000/ieee802154"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FULL_NAME "ieee802154"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_CHILD_IDX 55

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_NODELABEL(fn) fn(ieee802154)
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_NODELABEL_VARGS(fn, ...) fn(ieee802154, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_ORD 73
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_ORD_STR_SORTABLE 00073

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ieee802154 DT_N_S_soc_S_peripheral_50000000_S_ieee802154
#define DT_N_NODELABEL_ieee802154         DT_N_S_soc_S_peripheral_50000000_S_ieee802154

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_REG_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_MATCHES_nordic_nrf_ieee802154 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_COMPAT_MODEL_IDX_0 "nrf-ieee802154"
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible {"nordic,nrf-ieee802154"}
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0 "nordic,nrf-ieee802154"
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ieee802154
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ieee802154
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_IEEE802154
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_ieee802154_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/kmu@39000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_kmu_39000
 *
 * Binding (compatible = nordic,nrf-kmu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-kmu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PATH "/soc/peripheral@50000000/kmu@39000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FULL_NAME "kmu@39000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_CHILD_IDX 51

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_NODELABEL(fn) fn(kmu)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_NODELABEL_VARGS(fn, ...) fn(kmu, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_ORD 74
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_ORD_STR_SORTABLE 00074

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_kmu DT_N_S_soc_S_peripheral_50000000_S_kmu_39000
#define DT_N_NODELABEL_kmu         DT_N_S_soc_S_peripheral_50000000_S_kmu_39000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq 57
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MATCHES_nordic_nrf_kmu 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MODEL_IDX_0 "nrf-kmu"
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible {"nordic,nrf-kmu"}
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0 "nordic,nrf-kmu"
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-kmu
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_kmu
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_KMU
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_0 233472
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts {57 /* 0x39 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_0 57
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/mutex@30000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_mutex_30000
 *
 * Binding (compatible = nordic,nrf-mutex):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-mutex.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_PATH "/soc/peripheral@50000000/mutex@30000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FULL_NAME "mutex@30000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_CHILD_IDX 45

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_NODELABEL(fn) fn(mutex)
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_NODELABEL_VARGS(fn, ...) fn(mutex, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_ORD 75
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_ORD_STR_SORTABLE 00075

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_mutex DT_N_S_soc_S_peripheral_50000000_S_mutex_30000
#define DT_N_NODELABEL_mutex         DT_N_S_soc_S_peripheral_50000000_S_mutex_30000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_IDX_0_VAL_ADDRESS 1342373888 /* 0x50030000 */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_MATCHES_nordic_nrf_mutex 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_COMPAT_MODEL_IDX_0 "nrf-mutex"
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible {"nordic,nrf-mutex"}
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0 "nordic,nrf-mutex"
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-mutex
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_mutex
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_MUTEX
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg {196608 /* 0x30000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_0 196608
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_mutex_30000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/nfct@2d000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000
 *
 * Binding (compatible = nordic,nrf-nfct):
 *   $ZEPHYR_BASE\dts\bindings\net\wireless\nordic,nrf-nfct.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_PATH "/soc/peripheral@50000000/nfct@2d000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FULL_NAME "nfct@2d000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_CHILD_IDX 44

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_NODELABEL(fn) fn(nfct)
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_NODELABEL_VARGS(fn, ...) fn(nfct, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_ORD 76
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_ORD_STR_SORTABLE 00076

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_nfct DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000
#define DT_N_NODELABEL_nfct         DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_IDX_0_VAL_ADDRESS 1342361600 /* 0x5002d000 */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_irq 45
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_MATCHES_nordic_nrf_nfct 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_COMPAT_MODEL_IDX_0 "nrf-nfct"
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible {"nordic,nrf-nfct"}
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0 "nordic,nrf-nfct"
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-nfct
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_nfct
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_NFCT
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg {184320 /* 0x2d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_0 184320
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts {45 /* 0x2d */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_0 45
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/oscillator@4000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000
 *
 * Binding (compatible = nordic,nrf-oscillators):
 *   $ZEPHYR_BASE\dts\bindings\clock\nordic,nrf-oscillators.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_PATH "/soc/peripheral@50000000/oscillator@4000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FULL_NAME "oscillator@4000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_NODELABEL(fn) fn(oscillators)
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_NODELABEL_VARGS(fn, ...) fn(oscillators, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_ORD 77
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_ORD_STR_SORTABLE 00077

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_oscillators DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000
#define DT_N_NODELABEL_oscillators         DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_REG_IDX_0_VAL_ADDRESS 1342193664 /* 0x50004000 */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_COMPAT_MATCHES_nordic_nrf_oscillators 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_COMPAT_MODEL_IDX_0 "nrf-oscillators"
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible {"nordic,nrf-oscillators"}
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_IDX_0 "nordic,nrf-oscillators"
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-oscillators
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_oscillators
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_OSCILLATORS
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg {16384 /* 0x4000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_IDX_0 16384
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pdm@26000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pdm_26000
 *
 * Binding (compatible = nordic,nrf-pdm):
 *   $ZEPHYR_BASE\dts\bindings\audio\nordic,nrf-pdm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PATH "/soc/peripheral@50000000/pdm@26000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FULL_NAME "pdm@26000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_CHILD_IDX 40

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_NODELABEL(fn) fn(pdm0)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pdm0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_ORD 78
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_ORD_STR_SORTABLE 00078

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pdm DT_N_S_soc_S_peripheral_50000000_S_pdm_26000
#define DT_N_NODELABEL_pdm0        DT_N_S_soc_S_peripheral_50000000_S_pdm_26000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_ADDRESS 1342332928 /* 0x50026000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq 38
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MATCHES_nordic_nrf_pdm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MODEL_IDX_0 "nrf-pdm"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible {"nordic,nrf-pdm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0 "nordic,nrf-pdm"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pdm
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pdm
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PDM
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg {155648 /* 0x26000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_0 155648
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts {38 /* 0x26 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_0 38
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_IDX_0 "PCLK32M_HFXO"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_VAL_PCLK32M_HFXO_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_clock_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_queue_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_queue_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@21000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_21000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PATH "/soc/peripheral@50000000/pwm@21000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FULL_NAME "pwm@21000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_CHILD_IDX 36

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_NODELABEL(fn) fn(pwm0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_ORD 79
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_ORD_STR_SORTABLE 00079

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_21000
#define DT_N_NODELABEL_pwm0        DT_N_S_soc_S_peripheral_50000000_S_pwm_21000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_ADDRESS 1342312448 /* 0x50021000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq 33
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg {135168 /* 0x21000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_0 135168
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts {33 /* 0x21 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_0 33
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@22000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_22000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PATH "/soc/peripheral@50000000/pwm@22000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FULL_NAME "pwm@22000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_CHILD_IDX 37

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_NODELABEL(fn) fn(pwm1)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_ORD 80
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_ORD_STR_SORTABLE 00080

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_22000
#define DT_N_NODELABEL_pwm1        DT_N_S_soc_S_peripheral_50000000_S_pwm_22000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_ADDRESS 1342316544 /* 0x50022000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq 34
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg {139264 /* 0x22000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_0 139264
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts {34 /* 0x22 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_0 34
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@23000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_23000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PATH "/soc/peripheral@50000000/pwm@23000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FULL_NAME "pwm@23000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_CHILD_IDX 38

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_NODELABEL(fn) fn(pwm2)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm2, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_ORD 81
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_ORD_STR_SORTABLE 00081

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_23000
#define DT_N_NODELABEL_pwm2        DT_N_S_soc_S_peripheral_50000000_S_pwm_23000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_ADDRESS 1342320640 /* 0x50023000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq 35
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg {143360 /* 0x23000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_0 143360
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts {35 /* 0x23 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_0 35
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@24000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_24000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PATH "/soc/peripheral@50000000/pwm@24000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FULL_NAME "pwm@24000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_CHILD_IDX 39

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_NODELABEL(fn) fn(pwm3)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm3, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_ORD 82
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_ORD_STR_SORTABLE 00082

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_24000
#define DT_N_NODELABEL_pwm3        DT_N_S_soc_S_peripheral_50000000_S_pwm_24000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_ADDRESS 1342324736 /* 0x50024000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq 36
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg {147456 /* 0x24000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_0 147456
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts {36 /* 0x24 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_0 36
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/qdec@33000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qdec_33000
 *
 * Binding (compatible = nordic,nrf-qdec):
 *   $ZEPHYR_BASE\dts\bindings\sensor\nordic,nrf-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_PATH "/soc/peripheral@50000000/qdec@33000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FULL_NAME "qdec@33000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_CHILD_IDX 46

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_NODELABEL(fn) fn(qdec0)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_NODELABEL_VARGS(fn, ...) fn(qdec0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_ORD 83
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_ORD_STR_SORTABLE 00083

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_qdec DT_N_S_soc_S_peripheral_50000000_S_qdec_33000
#define DT_N_NODELABEL_qdec0        DT_N_S_soc_S_peripheral_50000000_S_qdec_33000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_IDX_0_VAL_ADDRESS 1342386176 /* 0x50033000 */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_irq 51
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_MATCHES_nordic_nrf_qdec 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_COMPAT_MODEL_IDX_0 "nrf-qdec"
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible {"nordic,nrf-qdec"}
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0 "nordic,nrf-qdec"
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qdec
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qdec
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QDEC
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg {208896 /* 0x33000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_0 208896
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts {51 /* 0x33 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_0 51
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_33000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/qdec@34000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qdec_34000
 *
 * Binding (compatible = nordic,nrf-qdec):
 *   $ZEPHYR_BASE\dts\bindings\sensor\nordic,nrf-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_PATH "/soc/peripheral@50000000/qdec@34000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FULL_NAME "qdec@34000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_CHILD_IDX 47

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_NODELABEL(fn) fn(qdec1)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_NODELABEL_VARGS(fn, ...) fn(qdec1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_ORD 84
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_ORD_STR_SORTABLE 00084

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_qdec DT_N_S_soc_S_peripheral_50000000_S_qdec_34000
#define DT_N_NODELABEL_qdec1        DT_N_S_soc_S_peripheral_50000000_S_qdec_34000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_IDX_0_VAL_ADDRESS 1342390272 /* 0x50034000 */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_irq 52
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_MATCHES_nordic_nrf_qdec 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_COMPAT_MODEL_IDX_0 "nrf-qdec"
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible {"nordic,nrf-qdec"}
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0 "nordic,nrf-qdec"
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qdec
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qdec
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QDEC
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg {212992 /* 0x34000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_0 212992
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts {52 /* 0x34 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_0 52
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_qdec_34000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/qspi@2b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000
 *
 * Binding (compatible = nordic,nrf-qspi):
 *   $ZEPHYR_BASE\dts\bindings\flash_controller\nordic,nrf-qspi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PATH "/soc/peripheral@50000000/qspi@2b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FULL_NAME "qspi@2b000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_CHILD_IDX 43

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_NODELABEL(fn) fn(qspi)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(qspi, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_ORD 85
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_ORD_STR_SORTABLE 00085

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_qspi DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000
#define DT_N_NODELABEL_qspi         DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NUM 2
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_ADDRESS 1342353408 /* 0x5002b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_ADDRESS 268435456 /* 0x10000000 */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_SIZE 268435456 /* 0x10000000 */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_VAL_ADDRESS DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_ADDRESS
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_VAL_SIZE DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_0_VAL_SIZE
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_mm_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_mm_VAL_ADDRESS DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_ADDRESS
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_NAME_qspi_mm_VAL_SIZE DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_REG_IDX_1_VAL_SIZE
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_irq 43
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_MATCHES_nordic_nrf_qspi 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_COMPAT_MODEL_IDX_0 "nrf-qspi"
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible {"nordic,nrf-qspi"}
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0 "nordic,nrf-qspi"
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qspi
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qspi
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QSPI
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg {176128 /* 0x2b000 */, 4096 /* 0x1000 */, 268435456 /* 0x10000000 */, 268435456 /* 0x10000000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_0 176128
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_2 268435456
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_2_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_3 268435456
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_IDX_3_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names {"qspi", "qspi_mm"}
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0 "qspi"
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_STRING_UNQUOTED qspi
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_STRING_TOKEN qspi
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_STRING_UPPER_TOKEN QSPI
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1 "qspi_mm"
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_STRING_UNQUOTED qspi_mm
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_STRING_TOKEN qspi_mm
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_STRING_UPPER_TOKEN QSPI_MM
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, reg_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_LEN 2
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_reg_names_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts {43 /* 0x2b */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_0 43
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/regulator@37000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_37000
 *
 * Binding (compatible = nordic,nrf-usbreg):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-usbreg.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_PATH "/soc/peripheral@50000000/regulator@37000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FULL_NAME "regulator@37000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_CHILD_IDX 49

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_NODELABEL(fn) fn(usbreg)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_NODELABEL_VARGS(fn, ...) fn(usbreg, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_ORD 86
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_ORD_STR_SORTABLE 00086

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_usbreg DT_N_S_soc_S_peripheral_50000000_S_regulator_37000
#define DT_N_NODELABEL_usbreg         DT_N_S_soc_S_peripheral_50000000_S_regulator_37000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_IDX_0_VAL_ADDRESS 1342402560 /* 0x50037000 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_irq 55
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_MATCHES_nordic_nrf_usbreg 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_COMPAT_MODEL_IDX_0 "nrf-usbreg"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible {"nordic,nrf-usbreg"}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0 "nordic,nrf-usbreg"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-usbreg
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_usbreg
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_USBREG
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg {225280 /* 0x37000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_0 225280
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts {55 /* 0x37 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_0 55
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_37000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/reset-controller@5000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000
 *
 * Binding (compatible = nordic,nrf-reset):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-reset.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_PATH "/soc/peripheral@50000000/reset-controller@5000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FULL_NAME "reset-controller@5000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_NODELABEL(fn) fn(reset)
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_NODELABEL_VARGS(fn, ...) fn(reset, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_ORD 87
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_ORD_STR_SORTABLE 00087

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_reset DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000
#define DT_N_NODELABEL_reset         DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_MATCHES_nordic_nrf_reset 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_COMPAT_MODEL_IDX_0 "nrf-reset"
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible {"nordic,nrf-reset"}
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0 "nordic,nrf-reset"
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-reset
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_reset
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RESET
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_0 20480
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/rtc@14000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_14000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PATH "/soc/peripheral@50000000/rtc@14000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FULL_NAME "rtc@14000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_CHILD_IDX 24

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_NODELABEL(fn) fn(rtc0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_NODELABEL_VARGS(fn, ...) fn(rtc0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_ORD 88
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_ORD_STR_SORTABLE 00088

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_14000
#define DT_N_NODELABEL_rtc0        DT_N_S_soc_S_peripheral_50000000_S_rtc_14000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_ADDRESS 1342259200 /* 0x50014000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq 20
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MODEL_IDX_0 "nrf-rtc"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rtc
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg {81920 /* 0x14000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_0 81920
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts {20 /* 0x14 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_0 20
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency 32768
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_cc_num 4
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zli 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/rtc@15000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_15000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PATH "/soc/peripheral@50000000/rtc@15000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FULL_NAME "rtc@15000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_CHILD_IDX 25

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_NODELABEL(fn) fn(rtc1)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_NODELABEL_VARGS(fn, ...) fn(rtc1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_ORD 89
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_ORD_STR_SORTABLE 00089

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_15000
#define DT_N_NODELABEL_rtc1        DT_N_S_soc_S_peripheral_50000000_S_rtc_15000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_ADDRESS 1342263296 /* 0x50015000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq 21
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MODEL_IDX_0 "nrf-rtc"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rtc
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg {86016 /* 0x15000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_0 86016
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts {21 /* 0x15 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_0 21
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency 32768
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_cc_num 4
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zli 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_8000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PATH "/soc/peripheral@50000000/spi@8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FULL_NAME "spi@8000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_NODELABEL(fn) fn(spi0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_ORD 90
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_ORD_STR_SORTABLE 00090

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_8000
#define DT_N_NODELABEL_spi0         DT_N_S_soc_S_peripheral_50000000_S_spi_8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_rx_delay_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_rx_delay_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@9000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_9000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PATH "/soc/peripheral@50000000/spi@9000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FULL_NAME "spi@9000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_CHILD_IDX 11

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_NODELABEL(fn) fn(spi1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_ORD 91
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_ORD_STR_SORTABLE 00091

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_9000
#define DT_N_NODELABEL_spi1         DT_N_S_soc_S_peripheral_50000000_S_spi_9000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_rx_delay_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_rx_delay_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_b000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PATH "/soc/peripheral@50000000/spi@b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FULL_NAME "spi@b000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_CHILD_IDX 15

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_NODELABEL(fn) fn(spi2)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi2, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_ORD 92
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_ORD_STR_SORTABLE 00092

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_b000
#define DT_N_NODELABEL_spi2         DT_N_S_soc_S_peripheral_50000000_S_spi_b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_rx_delay_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_rx_delay_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@c000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_c000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PATH "/soc/peripheral@50000000/spi@c000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FULL_NAME "spi@c000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_CHILD_IDX 18

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_NODELABEL(fn) fn(spi3)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_ORD 93
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_ORD_STR_SORTABLE 00093

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_EXISTS 1
#define DT_N_INST_4_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_c000
#define DT_N_NODELABEL_spi3         DT_N_S_soc_S_peripheral_50000000_S_spi_c000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_irq 12
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_0 49152
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_0 12
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_max_frequency 8000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_rx_delay_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_rx_delay_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/timer@f000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_f000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PATH "/soc/peripheral@50000000/timer@f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FULL_NAME "timer@f000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_CHILD_IDX 21

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_NODELABEL(fn) fn(timer0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_ORD 94
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_ORD_STR_SORTABLE 00094

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_f000
#define DT_N_NODELABEL_timer0        DT_N_S_soc_S_peripheral_50000000_S_timer_f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_ADDRESS 1342238720 /* 0x5000f000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq 15
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg {61440 /* 0xf000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_0 61440
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts {15 /* 0xf */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_0 15
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_bit_width 32
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_frequency 16000000
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zli 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/timer@11000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_11000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PATH "/soc/peripheral@50000000/timer@11000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FULL_NAME "timer@11000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_CHILD_IDX 23

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_NODELABEL(fn) fn(timer2)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer2, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_ORD 95
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_ORD_STR_SORTABLE 00095

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_11000
#define DT_N_NODELABEL_timer2        DT_N_S_soc_S_peripheral_50000000_S_timer_11000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_ADDRESS 1342246912 /* 0x50011000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq 17
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg {69632 /* 0x11000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_0 69632
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts {17 /* 0x11 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_0 17
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_cc_num 6
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_bit_width 32
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_frequency 16000000
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zli 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@8000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_8000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PATH "/soc/peripheral@50000000/uart@8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FULL_NAME "uart@8000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_NODELABEL(fn) fn(uart0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_ORD 96
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_ORD_STR_SORTABLE 00096

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_N_NODELABEL_uart0         DT_N_S_soc_S_peripheral_50000000_S_uart_8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_endtx_stoptx_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_endtx_stoptx_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_frame_timeout_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_frame_timeout_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@9000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_9000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PATH "/soc/peripheral@50000000/uart@9000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FULL_NAME "uart@9000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_CHILD_IDX 12

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_NODELABEL(fn) fn(uart1)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_ORD 97
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_ORD_STR_SORTABLE 00097

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_9000
#define DT_N_NODELABEL_uart1         DT_N_S_soc_S_peripheral_50000000_S_uart_9000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_endtx_stoptx_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_endtx_stoptx_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_frame_timeout_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_frame_timeout_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@b000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_b000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PATH "/soc/peripheral@50000000/uart@b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FULL_NAME "uart@b000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_CHILD_IDX 16

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_NODELABEL(fn) fn(uart2)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart2, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_ORD 98
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_ORD_STR_SORTABLE 00098

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_b000
#define DT_N_NODELABEL_uart2         DT_N_S_soc_S_peripheral_50000000_S_uart_b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_endtx_stoptx_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_endtx_stoptx_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_frame_timeout_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_frame_timeout_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@c000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_c000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_PATH "/soc/peripheral@50000000/uart@c000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FULL_NAME "uart@c000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_CHILD_IDX 19

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_NODELABEL(fn) fn(uart3)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart3, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_ORD 99
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_ORD_STR_SORTABLE 00099

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_c000
#define DT_N_NODELABEL_uart3         DT_N_S_soc_S_peripheral_50000000_S_uart_c000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_irq 12
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_0 49152
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_0 12
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_disable_rx 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_disable_rx_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_endtx_stoptx_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_endtx_stoptx_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_frame_timeout_supported 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_frame_timeout_supported_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/usbd@36000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_usbd_36000
 *
 * Binding (compatible = nordic,nrf-usbd):
 *   $ZEPHYR_BASE\dts\bindings\usb\nordic,nrf-usbd.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_PATH "/soc/peripheral@50000000/usbd@36000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FULL_NAME "usbd@36000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_CHILD_IDX 48

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_NODELABEL(fn) fn(usbd)
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_NODELABEL_VARGS(fn, ...) fn(usbd, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_ORD 100
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_ORD_STR_SORTABLE 00100

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_usbd DT_N_S_soc_S_peripheral_50000000_S_usbd_36000
#define DT_N_NODELABEL_usbd         DT_N_S_soc_S_peripheral_50000000_S_usbd_36000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_IDX_0_VAL_ADDRESS 1342398464 /* 0x50036000 */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_irq 54
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_MATCHES_nordic_nrf_usbd 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_COMPAT_MODEL_IDX_0 "nrf-usbd"
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible {"nordic,nrf-usbd"}
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0 "nordic,nrf-usbd"
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-usbd
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_usbd
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_USBD
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg {221184 /* 0x36000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_0 221184
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts {54 /* 0x36 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_0 54
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_bidir_endpoints 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_bidir_endpoints_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_in_endpoints 7
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_in_endpoints_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_out_endpoints 7
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_out_endpoints_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoin_endpoints 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoin_endpoints_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoout_endpoints 1
#define DT_N_S_soc_S_peripheral_50000000_S_usbd_36000_P_num_isoout_endpoints_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/vmc@81000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_vmc_81000
 *
 * Binding (compatible = nordic,nrf-vmc):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-vmc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_PATH "/soc/peripheral@50000000/vmc@81000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FULL_NAME "vmc@81000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_CHILD_IDX 52

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_NODELABEL(fn) fn(vmc)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_NODELABEL_VARGS(fn, ...) fn(vmc, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_ORD 101
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_ORD_STR_SORTABLE 00101

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_vmc DT_N_S_soc_S_peripheral_50000000_S_vmc_81000
#define DT_N_NODELABEL_vmc         DT_N_S_soc_S_peripheral_50000000_S_vmc_81000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_VAL_ADDRESS 1342705664 /* 0x50081000 */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_MATCHES_nordic_nrf_vmc 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_MODEL_IDX_0 "nrf-vmc"
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible {"nordic,nrf-vmc"}
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0 "nordic,nrf-vmc"
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-vmc
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_vmc
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_VMC
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg {528384 /* 0x81000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_0 528384
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/watchdog@18000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
 *
 * Binding (compatible = nordic,nrf-wdt):
 *   $ZEPHYR_BASE\dts\bindings\watchdog\nordic,nrf-wdt.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PATH "/soc/peripheral@50000000/watchdog@18000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FULL_NAME "watchdog@18000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_CHILD_IDX 27

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_NODELABEL_NUM 2
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_NODELABEL(fn) fn(wdt) fn(wdt0)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_NODELABEL_VARGS(fn, ...) fn(wdt, __VA_ARGS__) fn(wdt0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_ORD 102
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_ORD_STR_SORTABLE 00102

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_wdt DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
#define DT_N_NODELABEL_wdt         DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
#define DT_N_NODELABEL_wdt0        DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_ADDRESS 1342275584 /* 0x50018000 */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq 24
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MATCHES_nordic_nrf_wdt 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MODEL_IDX_0 "nrf-wdt"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible {"nordic,nrf-wdt"}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0 "nordic,nrf-wdt"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-wdt
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_wdt
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_WDT
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg {98304 /* 0x18000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_0 98304
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts {24 /* 0x18 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_0 24
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/watchdog@19000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000
 *
 * Binding (compatible = nordic,nrf-wdt):
 *   $ZEPHYR_BASE\dts\bindings\watchdog\nordic,nrf-wdt.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_PATH "/soc/peripheral@50000000/watchdog@19000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FULL_NAME "watchdog@19000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_CHILD_IDX 28

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_NODELABEL(fn) fn(wdt1)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_NODELABEL_VARGS(fn, ...) fn(wdt1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_ORD 103
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_ORD_STR_SORTABLE 00103

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_wdt DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000
#define DT_N_NODELABEL_wdt1        DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_VAL_ADDRESS 1342279680 /* 0x50019000 */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_irq 25
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_MATCHES_nordic_nrf_wdt 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_MODEL_IDX_0 "nrf-wdt"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible {"nordic,nrf-wdt"}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0 "nordic,nrf-wdt"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-wdt
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_wdt
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_WDT
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg {102400 /* 0x19000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_0 102400
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts {25 /* 0x19 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_0 25
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
 *
 * Binding (compatible = nordic,nrf53-flash-controller):
 *   $ZEPHYR_BASE\dts\bindings\flash_controller\nordic,nrf53-flash-controller.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PATH "/soc/peripheral@50000000/flash-controller@39000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FULL_NAME "flash-controller@39000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_CHILD_IDX 50

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_NODELABEL(fn) fn(flash_controller)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_NODELABEL_VARGS(fn, ...) fn(flash_controller, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_CHILD_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_ORD 104
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_ORD_STR_SORTABLE 00104

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_SUPPORTS_ORDS \
	105, /* /soc/peripheral@50000000/flash-controller@39000/flash@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_EXISTS 1
#define DT_N_INST_0_nordic_nrf53_flash_controller DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
#define DT_N_NODELABEL_flash_controller           DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MATCHES_nordic_nrf53_flash_controller 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MODEL_IDX_0 "nrf53-flash-controller"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible {"nordic,nrf53-flash-controller"}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0 "nordic,nrf53-flash-controller"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf53-flash-controller
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf53_flash_controller
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF53_FLASH_CONTROLLER
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_0 233472
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_partial_erase 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_partial_erase_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
 *
 * Binding (compatible = soc-nv-flash):
 *   $ZEPHYR_BASE\dts\bindings\mtd\soc-nv-flash.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FULL_NAME "flash@0"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_NODELABEL(fn) fn(flash0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(flash0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_CHILD_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_ORD 105
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_ORD_STR_SORTABLE 00105

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REQUIRES_ORDS \
	104, /* /soc/peripheral@50000000/flash-controller@39000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_SUPPORTS_ORDS \
	106, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_EXISTS 1
#define DT_N_INST_0_soc_nv_flash DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
#define DT_N_NODELABEL_flash0    DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_SIZE 1048576 /* 0x100000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_COMPAT_MATCHES_soc_nv_flash 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible {"soc-nv-flash"}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0 "soc-nv-flash"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_UNQUOTED soc-nv-flash
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_TOKEN soc_nv_flash
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SOC_NV_FLASH
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg {0 /* 0x0 */, 1048576 /* 0x100000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1 1048576
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size 4096
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\fixed-partitions.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FULL_NAME "partitions"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_NODELABEL_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_NODELABEL_VARGS(fn, ...) 

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_NUM 3
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_NUM_STATUS_OKAY 3
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD 106
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD_STR_SORTABLE 00106

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_REQUIRES_ORDS \
	105, /* /soc/peripheral@50000000/flash-controller@39000/flash@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_SUPPORTS_ORDS \
	107, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0 */ \
	108, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000 */ \
	109, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@ed0000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_EXISTS 1
#define DT_N_INST_0_fixed_partitions DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_REG_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FULL_NAME "partition@0"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_NODELABEL(fn) fn(boot_partition)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(boot_partition, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD 107
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD_STR_SORTABLE 00107

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REQUIRES_ORDS \
	106, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_EXISTS 1
#define DT_N_NODELABEL_boot_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label "mcuboot"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UNQUOTED mcuboot
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_TOKEN mcuboot
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN MCUBOOT
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_IDX_0 "mcuboot"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 65536 /* 0x10000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1 65536
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME "partition@10000"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_NODELABEL(fn) fn(slot0_partition)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot0_partition, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD 108
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD_STR_SORTABLE 00108

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REQUIRES_ORDS \
	106, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_EXISTS 1
#define DT_N_NODELABEL_slot0_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_ADDRESS 65536 /* 0x10000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_SIZE 983040 /* 0xf0000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARTITION_ID 2

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label "mcuboot_primary"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UNQUOTED mcuboot_primary
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_TOKEN mcuboot_primary
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UPPER_TOKEN MCUBOOT_PRIMARY
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_IDX_0 "mcuboot_primary"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg {65536 /* 0x10000 */, 983040 /* 0xf0000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0 65536
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1 983040
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@ed0000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_PATH "/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@ed0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FULL_NAME "partition@ed0000"

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FOREACH_NODELABEL(fn) fn(slot1_partition)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot1_partition, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_ORD 109
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_ORD_STR_SORTABLE 00109

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_REQUIRES_ORDS \
	106, /* /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_EXISTS 1
#define DT_N_NODELABEL_slot1_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_REG_IDX_0_VAL_ADDRESS 15532032 /* 0xed0000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_REG_IDX_0_VAL_SIZE 983040 /* 0xf0000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_PARTITION_ID 3

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label "mcuboot_secondary"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label_STRING_UNQUOTED mcuboot_secondary
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label_STRING_TOKEN mcuboot_secondary
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label_STRING_UPPER_TOKEN MCUBOOT_SECONDARY
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label_IDX_0 "mcuboot_secondary"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000, label, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000, label, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_reg {15532032 /* 0xed0000 */, 983040 /* 0xf0000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_reg_IDX_0 15532032
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_reg_IDX_1 983040
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/power@5000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000
 *
 * Binding (compatible = nordic,nrf-power):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-power.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PATH "/soc/peripheral@50000000/power@5000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FULL_NAME "power@5000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_NODELABEL(fn) fn(power)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_NODELABEL_VARGS(fn, ...) fn(power, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_CHILD_NUM 2
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_ORD 110
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_ORD_STR_SORTABLE 00110

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_SUPPORTS_ORDS \
	111, /* /soc/peripheral@50000000/power@5000/gpregret1@51c */ \
	112, /* /soc/peripheral@50000000/power@5000/gpregret2@520 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_power DT_N_S_soc_S_peripheral_50000000_S_power_5000
#define DT_N_NODELABEL_power         DT_N_S_soc_S_peripheral_50000000_S_power_5000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 20480 /* 0x5000 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_RANGES_IDX_0_VAL_LENGTH 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq 5
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MATCHES_nordic_nrf_power 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MODEL_IDX_0 "nrf-power"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible {"nordic,nrf-power"}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0 "nordic,nrf-power"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-power
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_power
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_POWER
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_0 20480
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_0 5
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/power@5000/gpregret1@51c
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c
 *
 * Binding (compatible = nordic,nrf-gpregret):
 *   $ZEPHYR_BASE\dts\bindings\retained_mem\nordic,nrf-gpreget.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_PATH "/soc/peripheral@50000000/power@5000/gpregret1@51c"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FULL_NAME "gpregret1@51c"

/* Node parent (/soc/peripheral@50000000/power@5000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_PARENT DT_N_S_soc_S_peripheral_50000000_S_power_5000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_NODELABEL(fn) fn(gpregret1)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpregret1, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_ORD 111
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_ORD_STR_SORTABLE 00111

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REQUIRES_ORDS \
	110, /* /soc/peripheral@50000000/power@5000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpregret DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c
#define DT_N_NODELABEL_gpregret1        DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_IDX_0_VAL_ADDRESS 1342199068 /* 0x5000551c */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_REG_IDX_0_VAL_SIZE 1 /* 0x1 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_MATCHES_nordic_nrf_gpregret 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_COMPAT_MODEL_IDX_0 "nrf-gpregret"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible {"nordic,nrf-gpregret"}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0 "nordic,nrf-gpregret"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg {1308 /* 0x51c */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_0 1308
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/power@5000/gpregret2@520
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520
 *
 * Binding (compatible = nordic,nrf-gpregret):
 *   $ZEPHYR_BASE\dts\bindings\retained_mem\nordic,nrf-gpreget.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_PATH "/soc/peripheral@50000000/power@5000/gpregret2@520"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FULL_NAME "gpregret2@520"

/* Node parent (/soc/peripheral@50000000/power@5000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_PARENT DT_N_S_soc_S_peripheral_50000000_S_power_5000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_NODELABEL(fn) fn(gpregret2)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpregret2, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_ORD 112
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_ORD_STR_SORTABLE 00112

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REQUIRES_ORDS \
	110, /* /soc/peripheral@50000000/power@5000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_EXISTS 1
#define DT_N_INST_1_nordic_nrf_gpregret DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520
#define DT_N_NODELABEL_gpregret2        DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_IDX_0_VAL_ADDRESS 1342199072 /* 0x50005520 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_REG_IDX_0_VAL_SIZE 1 /* 0x1 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_MATCHES_nordic_nrf_gpregret 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_COMPAT_MODEL_IDX_0 "nrf-gpregret"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible {"nordic,nrf-gpregret"}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0 "nordic,nrf-gpregret"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg {1312 /* 0x520 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_0 1312
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/regulator@4000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000
 *
 * Binding (compatible = nordic,nrf53x-regulators):
 *   $ZEPHYR_BASE\dts\bindings\regulator\nordic,nrf53x-regulators.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PATH "/soc/peripheral@50000000/regulator@4000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FULL_NAME "regulator@4000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_NODELABEL(fn) fn(regulators)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_NODELABEL_VARGS(fn, ...) fn(regulators, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_CHILD_NUM 3
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_ORD 113
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_ORD_STR_SORTABLE 00113

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_SUPPORTS_ORDS \
	114, /* /soc/peripheral@50000000/regulator@4000/regulator@4704 */ \
	115, /* /soc/peripheral@50000000/regulator@4000/regulator@4904 */ \
	116, /* /soc/peripheral@50000000/regulator@4000/regulator@4b00 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_EXISTS 1
#define DT_N_INST_0_nordic_nrf53x_regulators DT_N_S_soc_S_peripheral_50000000_S_regulator_4000
#define DT_N_NODELABEL_regulators            DT_N_S_soc_S_peripheral_50000000_S_regulator_4000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_ADDRESS 1342193664 /* 0x50004000 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MATCHES_nordic_nrf53x_regulators 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MODEL_IDX_0 "nrf53x-regulators"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible {"nordic,nrf53x-regulators"}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0 "nordic,nrf53x-regulators"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf53x-regulators
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf53x_regulators
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF53X_REGULATORS
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg {16384 /* 0x4000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_0 16384
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/regulator@4000/regulator@4704
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704
 *
 * Binding (compatible = nordic,nrf5x-regulator):
 *   $ZEPHYR_BASE\dts\bindings\regulator\nordic,nrf5x-regulator.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_PATH "/soc/peripheral@50000000/regulator@4000/regulator@4704"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FULL_NAME "regulator@4704"

/* Node parent (/soc/peripheral@50000000/regulator@4000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_PARENT DT_N_S_soc_S_peripheral_50000000_S_regulator_4000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_NODELABEL(fn) fn(vregmain)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_NODELABEL_VARGS(fn, ...) fn(vregmain, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_ORD 114
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_ORD_STR_SORTABLE 00114

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_REQUIRES_ORDS \
	113, /* /soc/peripheral@50000000/regulator@4000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_EXISTS 1
#define DT_N_INST_0_nordic_nrf5x_regulator DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704
#define DT_N_NODELABEL_vregmain            DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_REG_IDX_0_VAL_ADDRESS 18180 /* 0x4704 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_REG_IDX_0_VAL_SIZE 1 /* 0x1 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_COMPAT_MATCHES_nordic_nrf5x_regulator 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_COMPAT_MODEL_IDX_0 "nrf5x-regulator"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible {"nordic,nrf5x-regulator"}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_IDX_0 "nordic,nrf5x-regulator"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf5x-regulator
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_IDX_0_STRING_TOKEN nordic_nrf5x_regulator
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF5X_REGULATOR
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg {18180 /* 0x4704 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg_IDX_0 18180
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name "VREGMAIN"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_STRING_UNQUOTED VREGMAIN
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_STRING_TOKEN VREGMAIN
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_STRING_UPPER_TOKEN VREGMAIN
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_IDX_0 "VREGMAIN"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, regulator_name, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, regulator_name, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, regulator_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, regulator_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_name_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_initial_mode 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704_P_regulator_initial_mode_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/regulator@4000/regulator@4904
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904
 *
 * Binding (compatible = nordic,nrf5x-regulator):
 *   $ZEPHYR_BASE\dts\bindings\regulator\nordic,nrf5x-regulator.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_PATH "/soc/peripheral@50000000/regulator@4000/regulator@4904"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FULL_NAME "regulator@4904"

/* Node parent (/soc/peripheral@50000000/regulator@4000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_PARENT DT_N_S_soc_S_peripheral_50000000_S_regulator_4000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_NODELABEL(fn) fn(vregradio)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_NODELABEL_VARGS(fn, ...) fn(vregradio, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_ORD 115
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_ORD_STR_SORTABLE 00115

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_REQUIRES_ORDS \
	113, /* /soc/peripheral@50000000/regulator@4000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_EXISTS 1
#define DT_N_INST_1_nordic_nrf5x_regulator DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904
#define DT_N_NODELABEL_vregradio           DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_REG_IDX_0_VAL_ADDRESS 18692 /* 0x4904 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_REG_IDX_0_VAL_SIZE 1 /* 0x1 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_COMPAT_MATCHES_nordic_nrf5x_regulator 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_COMPAT_MODEL_IDX_0 "nrf5x-regulator"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible {"nordic,nrf5x-regulator"}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_IDX_0 "nordic,nrf5x-regulator"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf5x-regulator
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_IDX_0_STRING_TOKEN nordic_nrf5x_regulator
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF5X_REGULATOR
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg {18692 /* 0x4904 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg_IDX_0 18692
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name "VREGRADIO"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_STRING_UNQUOTED VREGRADIO
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_STRING_TOKEN VREGRADIO
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_STRING_UPPER_TOKEN VREGRADIO
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_IDX_0 "VREGRADIO"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, regulator_name, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, regulator_name, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, regulator_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, regulator_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_name_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_initial_mode 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904_P_regulator_initial_mode_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/regulator@4000/regulator@4b00
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00
 *
 * Binding (compatible = nordic,nrf53x-regulator-hv):
 *   $ZEPHYR_BASE\dts\bindings\regulator\nordic,nrf53x-regulator-hv.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_PATH "/soc/peripheral@50000000/regulator@4000/regulator@4b00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FULL_NAME "regulator@4b00"

/* Node parent (/soc/peripheral@50000000/regulator@4000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_PARENT DT_N_S_soc_S_peripheral_50000000_S_regulator_4000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_NODELABEL(fn) fn(vregh)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_NODELABEL_VARGS(fn, ...) fn(vregh, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_ORD 116
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_ORD_STR_SORTABLE 00116

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_REQUIRES_ORDS \
	113, /* /soc/peripheral@50000000/regulator@4000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_EXISTS 1
#define DT_N_INST_0_nordic_nrf53x_regulator_hv DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00
#define DT_N_NODELABEL_vregh                   DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_REG_IDX_0_VAL_ADDRESS 19200 /* 0x4b00 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_REG_IDX_0_VAL_SIZE 68 /* 0x44 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_COMPAT_MATCHES_nordic_nrf53x_regulator_hv 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_COMPAT_MODEL_IDX_0 "nrf53x-regulator-hv"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible {"nordic,nrf53x-regulator-hv"}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_IDX_0 "nordic,nrf53x-regulator-hv"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf53x-regulator-hv
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_IDX_0_STRING_TOKEN nordic_nrf53x_regulator_hv
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF53X_REGULATOR_HV
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg {19200 /* 0x4b00 */, 68 /* 0x44 */}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg_IDX_0 19200
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg_IDX_1 68
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name "VREGH"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_STRING_UNQUOTED VREGH
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_STRING_TOKEN VREGH
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_STRING_UPPER_TOKEN VREGH
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_IDX_0 "VREGH"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, regulator_name, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, regulator_name, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, regulator_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, regulator_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00_P_regulator_name_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/gpio@842500
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PATH "/soc/peripheral@50000000/gpio@842500"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FULL_NAME "gpio@842500"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_CHILD_IDX 53

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_NODELABEL(fn) fn(gpio0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpio0, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_ORD 117
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_ORD_STR_SORTABLE 00117

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REQUIRES_ORDS \
	6, /* /soc/peripheral@50000000 */ \
	66, /* /soc/gpiote@5000d000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_SUPPORTS_ORDS \
	118, /* /soc/peripheral@50000000/spi@a000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpio DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_NODELABEL_gpio0        DT_N_S_soc_S_peripheral_50000000_S_gpio_842500

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_ADDRESS 1350837504 /* 0x50842500 */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MODEL_IDX_0 "nrf-gpio"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios 32
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg {8660224 /* 0x842500 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_0 8660224
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_1 768
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance DT_N_S_soc_S_gpiote_5000d000
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_IDX_0 DT_N_S_soc_S_gpiote_5000d000
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_IDX_0_PH DT_N_S_soc_S_gpiote_5000d000
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpiote_instance_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_port 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_port_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@a000
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_a000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PATH "/soc/peripheral@50000000/spi@a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FULL_NAME "spi@a000"

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PARENT DT_N_S_soc_S_peripheral_50000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_CHILD_IDX 13

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_NODELABEL(fn) fn(spi4)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi4, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_CHILD_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_ORD 118
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_ORD_STR_SORTABLE 00118

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REQUIRES_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	6, /* /soc/peripheral@50000000 */ \
	36, /* /pin-controller/spi4_default */ \
	38, /* /pin-controller/spi4_sleep */ \
	117, /* /soc/peripheral@50000000/gpio@842500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_SUPPORTS_ORDS \
	119, /* /soc/peripheral@50000000/spi@a000/at25sl128a-node@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_a000
#define DT_N_NODELABEL_spi4         DT_N_S_soc_S_peripheral_50000000_S_spi_a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_ADDRESS 1342218240 /* 0x5000a000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq 10
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_LEVEL 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NUM 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi4_default
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi4_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_0 40960
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_0 10
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin 11
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_cs_gpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_overrun_character 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi4_default
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi4_default
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi4_sleep
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi4_sleep
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_max_frequency 32000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_supported 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_supported_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_ENUM_VAL_2_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_rx_delay_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@a000/at25sl128a-node@0
 *
 * Node identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0
 *
 * Binding (compatible = jedec,spi-nor):
 *   $ZEPHYR_BASE\dts\bindings\mtd\jedec,spi-nor.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_PATH "/soc/peripheral@50000000/spi@a000/at25sl128a-node@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FULL_NAME "at25sl128a-node@0"

/* Node parent (/soc/peripheral@50000000/spi@a000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_spi_a000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FOREACH_NODELABEL(fn) fn(at25sl128a)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(at25sl128a, __VA_ARGS__)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_CHILD_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_ORD 119
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_ORD_STR_SORTABLE 00119

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_REQUIRES_ORDS \
	118, /* /soc/peripheral@50000000/spi@a000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_EXISTS 1
#define DT_N_INST_0_jedec_spi_nor DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0
#define DT_N_NODELABEL_at25sl128a DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0

/* Bus info (controller: '/soc/peripheral@50000000/spi@a000', type: '['spi']') */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_BUS_spi 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_BUS DT_N_S_soc_S_peripheral_50000000_S_spi_a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_RANGES_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_COMPAT_MATCHES_jedec_spi_nor 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_COMPAT_VENDOR_IDX_0 "JEDEC Solid State Technology Association"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_COMPAT_MODEL_IDX_0 "spi-nor"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_wakeup_source 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible {"jedec,spi-nor"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible_IDX_0 "jedec,spi-nor"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible_IDX_0_STRING_UNQUOTED jedec,spi-nor
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible_IDX_0_STRING_TOKEN jedec_spi_nor
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible_IDX_0_STRING_UPPER_TOKEN JEDEC_SPI_NOR
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, compatible, 0)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_reg {0 /* 0x0 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_spi_max_frequency 16000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_spi_max_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_duplex 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_duplex_ENUM_IDX 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_duplex_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_duplex_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_frame_format 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_frame_format_ENUM_IDX 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_frame_format_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_frame_format_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_spi_cpol 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_spi_cpol_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_spi_cpha 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_spi_cpha_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_spi_hold_cs 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_spi_hold_cs_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id {31 /* 0x1f */, 66 /* 0x42 */, 24 /* 0x18 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_IDX_0 31
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_IDX_1 66
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_IDX_2 24
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_IDX_2_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 2)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 2)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 2, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, jedec_id, 2, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_LEN 3
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_jedec_id_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_size 134217728
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp {229 /* 0xe5 */, 32 /* 0x20 */, 241 /* 0xf1 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 7 /* 0x7 */, 68 /* 0x44 */, 235 /* 0xeb */, 8 /* 0x8 */, 107 /* 0x6b */, 8 /* 0x8 */, 59 /* 0x3b */, 128 /* 0x80 */, 187 /* 0xbb */, 254 /* 0xfe */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 66 /* 0x42 */, 235 /* 0xeb */, 12 /* 0xc */, 32 /* 0x20 */, 15 /* 0xf */, 82 /* 0x52 */, 16 /* 0x10 */, 216 /* 0xd8 */, 0 /* 0x0 */, 255 /* 0xff */, 51 /* 0x33 */, 98 /* 0x62 */, 213 /* 0xd5 */, 0 /* 0x0 */, 132 /* 0x84 */, 41 /* 0x29 */, 1 /* 0x1 */, 206 /* 0xce */, 236 /* 0xec */, 161 /* 0xa1 */, 7 /* 0x7 */, 61 /* 0x3d */, 122 /* 0x7a */, 117 /* 0x75 */, 122 /* 0x7a */, 117 /* 0x75 */, 247 /* 0xf7 */, 162 /* 0xa2 */, 213 /* 0xd5 */, 92 /* 0x5c */, 25 /* 0x19 */, 246 /* 0xf6 */, 28 /* 0x1c */, 255 /* 0xff */, 232 /* 0xe8 */, 16 /* 0x10 */, 192 /* 0xc0 */, 128 /* 0x80 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_0 229
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_1 32
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_1_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_2 241
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_2_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_3 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_3_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_4 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_4_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_5 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_5_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_6 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_6_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_7 7
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_7_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_8 68
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_8_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_9 235
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_9_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_10 8
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_10_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_11 107
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_11_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_12 8
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_12_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_13 59
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_13_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_14 128
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_14_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_15 187
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_15_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_16 254
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_16_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_17 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_17_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_18 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_18_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_19 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_19_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_20 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_20_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_21 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_21_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_22 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_22_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_23 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_23_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_24 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_24_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_25 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_25_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_26 66
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_26_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_27 235
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_27_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_28 12
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_28_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_29 32
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_29_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_30 15
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_30_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_31 82
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_31_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_32 16
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_32_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_33 216
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_33_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_34 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_34_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_35 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_35_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_36 51
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_36_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_37 98
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_37_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_38 213
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_38_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_39 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_39_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_40 132
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_40_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_41 41
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_41_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_42 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_42_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_43 206
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_43_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_44 236
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_44_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_45 161
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_45_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_46 7
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_46_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_47 61
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_47_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_48 122
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_48_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_49 117
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_49_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_50 122
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_50_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_51 117
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_51_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_52 247
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_52_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_53 162
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_53_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_54 213
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_54_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_55 92
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_55_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_56 25
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_56_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_57 246
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_57_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_58 28
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_58_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_59 255
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_59_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_60 232
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_60_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_61 16
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_61_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_62 192
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_62_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_63 128
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_IDX_63_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 0) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 1) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 2) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 3) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 4) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 5) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 6) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 7) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 8) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 9) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 10) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 11) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 12) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 13) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 14) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 15) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 16) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 17) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 18) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 19) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 20) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 21) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 22) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 23) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 24) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 25) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 26) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 27) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 28) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 29) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 30) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 31) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 32) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 33) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 34) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 35) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 36) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 37) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 38) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 39) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 40) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 41) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 42) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 43) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 44) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 45) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 46) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 47) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 48) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 49) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 50) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 51) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 52) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 53) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 54) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 55) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 56) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 57) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 58) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 59) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 60) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 61) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 62) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 63)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 13) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 14) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 15) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 16) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 17) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 18) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 19) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 20) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 21) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 22) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 23) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 24) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 25) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 26) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 27) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 28) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 29) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 30) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 31) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 32) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 33) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 34) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 35) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 36) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 37) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 38) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 39) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 40) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 41) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 42) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 43) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 44) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 45) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 46) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 47) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 48) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 49) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 50) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 51) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 52) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 53) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 54) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 55) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 56) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 57) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 58) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 59) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 60) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 61) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 62) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 63)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 11, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 12, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 13, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 14, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 15, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 16, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 17, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 18, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 19, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 20, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 21, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 22, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 23, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 24, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 25, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 26, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 27, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 28, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 29, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 30, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 31, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 32, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 33, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 34, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 35, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 36, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 37, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 38, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 39, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 40, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 41, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 42, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 43, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 44, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 45, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 46, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 47, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 48, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 49, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 50, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 51, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 52, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 53, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 54, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 55, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 56, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 57, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 58, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 59, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 60, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 61, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 62, __VA_ARGS__) \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 63, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 21, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 22, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 23, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 24, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 25, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 26, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 27, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 28, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 29, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 30, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 31, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 32, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 33, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 34, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 35, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 36, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 37, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 38, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 39, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 40, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 41, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 42, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 43, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 44, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 45, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 46, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 47, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 48, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 49, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 50, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 51, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 52, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 53, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 54, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 55, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 56, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 57, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 58, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 59, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 60, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 61, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 62, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, sfdp_bfp, 63, __VA_ARGS__)
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_LEN 64
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_sfdp_bfp_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_requires_ulbpr 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_requires_ulbpr_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_has_dpd 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_has_dpd_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_t_enter_dpd 3000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_t_enter_dpd_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_t_exit_dpd 3000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0_P_t_exit_dpd_EXISTS 1

/*
 * Chosen nodes
 */
#define DT_CHOSEN_zephyr_entropy                          DT_N_S_soc_S_crypto_50844000
#define DT_CHOSEN_zephyr_entropy_EXISTS                   1
#define DT_CHOSEN_zephyr_flash_controller                 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
#define DT_CHOSEN_zephyr_flash_controller_EXISTS          1
#define DT_CHOSEN_zephyr_bt_hci                           DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0
#define DT_CHOSEN_zephyr_bt_hci_EXISTS                    1
#define DT_CHOSEN_zephyr_ipc_shm                          DT_N_S_reserved_memory_S_memory_20078000
#define DT_CHOSEN_zephyr_ipc_shm_EXISTS                   1
#define DT_CHOSEN_zephyr_sram                             DT_N_S_reserved_memory_S_image_20000000
#define DT_CHOSEN_zephyr_sram_EXISTS                      1
#define DT_CHOSEN_zephyr_flash                            DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
#define DT_CHOSEN_zephyr_flash_EXISTS                     1
#define DT_CHOSEN_zephyr_code_partition                   DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
#define DT_CHOSEN_zephyr_code_partition_EXISTS            1
#define DT_CHOSEN_zephyr_sram_secure_partition            DT_N_S_reserved_memory_S_image_s_20000000
#define DT_CHOSEN_zephyr_sram_secure_partition_EXISTS     1
#define DT_CHOSEN_zephyr_sram_non_secure_partition        DT_N_S_reserved_memory_S_image_ns_20040000
#define DT_CHOSEN_zephyr_sram_non_secure_partition_EXISTS 1
#define DT_CHOSEN_nordic_pm_ext_flash                     DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0
#define DT_CHOSEN_nordic_pm_ext_flash_EXISTS              1

/* Macros for iterating over all nodes and enabled nodes */
#define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_gpiote_4002f000) fn(DT_N_S_soc_S_crypto_50844000) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_spi1_default_9160) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1) fn(DT_N_S_pin_controller_S_spi1_default_dw1000) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_default_S_group1) fn(DT_N_S_pin_controller_S_spi3_sleep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_default_S_group1) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1) fn(DT_N_S_pin_controller_S_i2c0_sleep) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1) fn(DT_N_S_pin_controller_S_i2c2_default) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1) fn(DT_N_S_pin_controller_S_i2c2_sleep) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_sw_pwm) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_ipc) fn(DT_N_S_ipc_S_ipc0) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0) fn(DT_N_S_reserved_memory) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_memory_20078000)
#define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_crypto_50844000) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_spi1_default_9160) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1) fn(DT_N_S_pin_controller_S_spi1_default_dw1000) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_default_S_group1) fn(DT_N_S_pin_controller_S_spi3_sleep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi4_default) fn(DT_N_S_pin_controller_S_spi4_default_S_group1) fn(DT_N_S_pin_controller_S_spi4_sleep) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1) fn(DT_N_S_pin_controller_S_i2c0_sleep) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1) fn(DT_N_S_pin_controller_S_i2c2_default) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1) fn(DT_N_S_pin_controller_S_i2c2_sleep) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_ipc) fn(DT_N_S_ipc_S_ipc0) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0) fn(DT_N_S_reserved_memory) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20040000) fn(DT_N_S_reserved_memory_S_memory_20078000)
#define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4b00, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_comparator_1a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qspi_2b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_nfct_2d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_33000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_qdec_34000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_usbd_36000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ieee802154, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_4002f000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_9160, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_dw1000, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_sw_pwm, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_ipc, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__)
#define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_9160, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_9160_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_dw1000, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_dw1000_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi4_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c2_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_ipc, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20040000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_memory_20078000, __VA_ARGS__)
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_primary DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_primary_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_secondary DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_ed0000
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_secondary_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_2 DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions_S_partition_0
#define DT_COMPAT_fixed_partitions_LABEL_image_2_EXISTS 1

/*
 * Macros for compatibles with status "okay" nodes
 */
#define DT_COMPAT_HAS_OKAY_corp_my_nrf5340_nrf5340_cpuapp 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpuapp_qkaa 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpuapp 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf53 1
#define DT_COMPAT_HAS_OKAY_simple_bus 1
#define DT_COMPAT_HAS_OKAY_arm_v8m_nvic 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ficr 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uicr 1
#define DT_COMPAT_HAS_OKAY_mmio_sram 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_dcnf 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_oscillators 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf53x_regulators 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf5x_regulator 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_clock 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_power 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpregret 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_reset 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ctrlapperi 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_spim 1
#define DT_COMPAT_HAS_OKAY_jedec_spi_nor 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_saadc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_timer 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_dppic 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_wdt 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_egu 1
#define DT_COMPAT_HAS_OKAY_nordic_mbox_nrf_ipc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ipc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_mutex 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_usbreg 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf53_flash_controller 1
#define DT_COMPAT_HAS_OKAY_soc_nv_flash 1
#define DT_COMPAT_HAS_OKAY_fixed_partitions 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_kmu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_vmc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_spu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote 1
#define DT_COMPAT_HAS_OKAY_nordic_cryptocell 1
#define DT_COMPAT_HAS_OKAY_arm_cryptocell_312 1
#define DT_COMPAT_HAS_OKAY_zephyr_sim_flash 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_pinctrl 1
#define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_entropy 1
#define DT_COMPAT_HAS_OKAY_arm_cortex_m33f 1
#define DT_COMPAT_HAS_OKAY_arm_armv8m_itm 1
#define DT_COMPAT_HAS_OKAY_arm_armv8m_mpu 1
#define DT_COMPAT_HAS_OKAY_zephyr_ipc_openamp_static_vrings 1
#define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_ipc 1

/*
 * Macros for status "okay" instances of each compatible
 */
#define DT_N_INST_corp_my_nrf5340_nrf5340_cpuapp_NUM_OKAY 1
#define DT_N_INST_nordic_nrf5340_cpuapp_qkaa_NUM_OKAY 1
#define DT_N_INST_nordic_nrf5340_cpuapp_NUM_OKAY 1
#define DT_N_INST_nordic_nrf53_NUM_OKAY 1
#define DT_N_INST_simple_bus_NUM_OKAY 1
#define DT_N_INST_arm_v8m_nvic_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ficr_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_uicr_NUM_OKAY 1
#define DT_N_INST_mmio_sram_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_dcnf_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_oscillators_NUM_OKAY 1
#define DT_N_INST_nordic_nrf53x_regulators_NUM_OKAY 1
#define DT_N_INST_nordic_nrf5x_regulator_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_clock_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_power_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpregret_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_reset_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ctrlapperi_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_spim_NUM_OKAY 1
#define DT_N_INST_jedec_spi_nor_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_saadc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_timer_NUM_OKAY 3
#define DT_N_INST_nordic_nrf_dppic_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_wdt_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_egu_NUM_OKAY 6
#define DT_N_INST_nordic_mbox_nrf_ipc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ipc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_mutex_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_usbreg_NUM_OKAY 1
#define DT_N_INST_nordic_nrf53_flash_controller_NUM_OKAY 1
#define DT_N_INST_soc_nv_flash_NUM_OKAY 2
#define DT_N_INST_fixed_partitions_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_kmu_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_vmc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpio_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_spu_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY 1
#define DT_N_INST_nordic_cryptocell_NUM_OKAY 1
#define DT_N_INST_arm_cryptocell_312_NUM_OKAY 1
#define DT_N_INST_zephyr_sim_flash_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_pinctrl_NUM_OKAY 1
#define DT_N_INST_zephyr_bt_hci_entropy_NUM_OKAY 1
#define DT_N_INST_arm_cortex_m33f_NUM_OKAY 1
#define DT_N_INST_arm_armv8m_itm_NUM_OKAY 1
#define DT_N_INST_arm_armv8m_mpu_NUM_OKAY 1
#define DT_N_INST_zephyr_ipc_openamp_static_vrings_NUM_OKAY 1
#define DT_N_INST_zephyr_bt_hci_ipc_NUM_OKAY 1
#define DT_FOREACH_OKAY_corp_my_nrf5340_nrf5340_cpuapp(fn) fn(DT_N)
#define DT_FOREACH_OKAY_VARGS_corp_my_nrf5340_nrf5340_cpuapp(fn, ...) fn(DT_N, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_corp_my_nrf5340_nrf5340_cpuapp(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_corp_my_nrf5340_nrf5340_cpuapp(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf5340_cpuapp_qkaa(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf5340_cpuapp_qkaa(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpuapp_qkaa(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf5340_cpuapp_qkaa(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf5340_cpuapp(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf5340_cpuapp(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpuapp(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf5340_cpuapp(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf53(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf53(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf53(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf53(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_simple_bus(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_v8m_nvic(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100)
#define DT_FOREACH_OKAY_VARGS_arm_v8m_nvic(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_v8m_nvic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_v8m_nvic(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ficr(fn) fn(DT_N_S_soc_S_ficr_ff0000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ficr(fn, ...) fn(DT_N_S_soc_S_ficr_ff0000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ficr(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ficr(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_uicr(fn) fn(DT_N_S_soc_S_uicr_ff8000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_uicr(fn, ...) fn(DT_N_S_soc_S_uicr_ff8000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_uicr(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uicr(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_mmio_sram(fn) fn(DT_N_S_soc_S_memory_20000000)
#define DT_FOREACH_OKAY_VARGS_mmio_sram(fn, ...) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_mmio_sram(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_dcnf(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_dcnf(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dcnf_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_dcnf(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_dcnf(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_oscillators(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_oscillators(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_oscillator_4000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_oscillators(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_oscillators(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf53x_regulators(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf53x_regulators(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf53x_regulators(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf53x_regulators(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf5x_regulator(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf5x_regulator(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4704, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_S_regulator_4904, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf5x_regulator(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf5x_regulator(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_clock(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_clock(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_clock(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_power(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_power(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_power(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_power(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_gpregret(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpregret(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret1_51c, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000_S_gpregret2_520, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpregret(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpregret(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_reset(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_reset(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_reset_controller_5000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_reset(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_reset(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ctrlapperi(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ctrlapperi(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_ctrlap_6000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ctrlapperi(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ctrlapperi(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_spim(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_spim(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_spim(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spim(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_jedec_spi_nor(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0)
#define DT_FOREACH_OKAY_VARGS_jedec_spi_nor(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000_S_at25sl128a_node_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_jedec_spi_nor(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_jedec_spi_nor(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_saadc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_saadc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_saadc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_saadc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_timer(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_timer(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_timer(fn) fn(0) fn(1) fn(2)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_timer(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_dppic(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_dppic(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_dppic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_dppic(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_wdt(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_wdt(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_wdt(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_wdt(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_egu(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_egu(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_egu(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_egu(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_mbox_nrf_ipc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000)
#define DT_FOREACH_OKAY_VARGS_nordic_mbox_nrf_ipc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_mbox_nrf_ipc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_mbox_nrf_ipc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ipc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ipc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mbox_2a000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ipc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ipc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_mutex(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_mutex(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_mutex_30000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_mutex(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_mutex(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_usbreg(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_usbreg(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_37000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_usbreg(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_usbreg(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf53_flash_controller(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf53_flash_controller(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf53_flash_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf53_flash_controller(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_soc_nv_flash(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0)
#define DT_FOREACH_OKAY_VARGS_soc_nv_flash(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_fixed_partitions(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions)
#define DT_FOREACH_OKAY_VARGS_fixed_partitions(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0_S_flash_sim_0_S_partitions, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_fixed_partitions(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_fixed_partitions(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_kmu(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_kmu(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_kmu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_kmu(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_vmc(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_vmc(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_vmc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_vmc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_gpio(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpio(fn, ...) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpio(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpio(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_spu(fn) fn(DT_N_S_soc_S_spu_50003000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_spu(fn, ...) fn(DT_N_S_soc_S_spu_50003000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_spu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spu(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_gpiote(fn) fn(DT_N_S_soc_S_gpiote_5000d000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpiote(fn, ...) fn(DT_N_S_soc_S_gpiote_5000d000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpiote(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_cryptocell(fn) fn(DT_N_S_soc_S_crypto_50844000)
#define DT_FOREACH_OKAY_VARGS_nordic_cryptocell(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_cryptocell(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_cryptocell(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_cryptocell_312(fn) fn(DT_N_S_soc_S_crypto_50844000)
#define DT_FOREACH_OKAY_VARGS_arm_cryptocell_312(fn, ...) fn(DT_N_S_soc_S_crypto_50844000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_cryptocell_312(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_cryptocell_312(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_sim_flash(fn) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0)
#define DT_FOREACH_OKAY_VARGS_zephyr_sim_flash(fn, ...) fn(DT_N_S_soc_S_nordic_ram_flash_controller_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_sim_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_sim_flash(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_pinctrl(fn) fn(DT_N_S_pin_controller)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_pinctrl(fn, ...) fn(DT_N_S_pin_controller, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_pinctrl(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pinctrl(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_bt_hci_entropy(fn) fn(DT_N_S_entropy_bt_hci)
#define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_bt_hci_entropy(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_cortex_m33f(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_FOREACH_OKAY_VARGS_arm_cortex_m33f(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_cortex_m33f(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m33f(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_armv8m_itm(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
#define DT_FOREACH_OKAY_VARGS_arm_armv8m_itm(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_armv8m_itm(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_itm(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_armv8m_mpu(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
#define DT_FOREACH_OKAY_VARGS_arm_armv8m_mpu(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_armv8m_mpu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_mpu(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_ipc_openamp_static_vrings(fn) fn(DT_N_S_ipc_S_ipc0)
#define DT_FOREACH_OKAY_VARGS_zephyr_ipc_openamp_static_vrings(fn, ...) fn(DT_N_S_ipc_S_ipc0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_ipc_openamp_static_vrings(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_ipc_openamp_static_vrings(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_bt_hci_ipc(fn) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0)
#define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_ipc(fn, ...) fn(DT_N_S_ipc_S_ipc0_S_bt_hci_ipc0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_bt_hci_ipc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_ipc(fn, ...) fn(0, __VA_ARGS__)

/*
 * Bus information for status "okay" nodes of each compatible
 */
#define DT_COMPAT_jedec_spi_nor_BUS_spi 1
